VirtualBox

source: vbox/trunk/src/VBox/VMM/include/HMInternal.h@ 45478

Last change on this file since 45478 was 45410, checked in by vboxsync, 12 years ago

VMM/VMMR0: HM bits. missed commit.
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1/* $Id: HMInternal.h 45410 2013-04-08 15:01:48Z vboxsync $ */
2/** @file
3 * HM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef ___HMInternal_h
19#define ___HMInternal_h
20
21#include <VBox/cdefs.h>
22#include <VBox/types.h>
23#include <VBox/vmm/em.h>
24#include <VBox/vmm/stam.h>
25#include <VBox/dis.h>
26#include <VBox/vmm/hm.h>
27#include <VBox/vmm/hm_vmx.h>
28#include <VBox/vmm/pgm.h>
29#include <VBox/vmm/cpum.h>
30#include <iprt/memobj.h>
31#include <iprt/cpuset.h>
32#include <iprt/mp.h>
33#include <iprt/avl.h>
34
35#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL) || defined (VBOX_WITH_64_BITS_GUESTS)
36/* Enable 64 bits guest support. */
37# define VBOX_ENABLE_64_BITS_GUESTS
38#endif
39
40#ifdef VBOX_WITH_OLD_VTX_CODE
41# define VMX_USE_CACHED_VMCS_ACCESSES
42#elif HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
43# define VMX_USE_CACHED_VMCS_ACCESSES
44#endif
45
46#define HM_VMX_EMULATE_REALMODE
47
48/* The MSR auto load/store does not work for KERNEL_GS_BASE MSR, thus we
49 * handle this MSR manually. See @bugref{6208}. This is clearly visible while
50 * booting Solaris 11 (11.1 b19) VMs with 2 Cpus.
51 *
52 * Note: don't forget to update the assembly files while modifying this!
53 */
54# define VBOX_WITH_AUTO_MSR_LOAD_RESTORE
55
56RT_C_DECLS_BEGIN
57
58
59/** @defgroup grp_hm_int Internal
60 * @ingroup grp_hm
61 * @internal
62 * @{
63 */
64
65
66/** Maximum number of exit reason statistics counters. */
67#define MAX_EXITREASON_STAT 0x100
68#define MASK_EXITREASON_STAT 0xff
69#define MASK_INJECT_IRQ_STAT 0xff
70
71/** @name Changed flags
72 * These flags are used to keep track of which important registers that
73 * have been changed since last they were reset.
74 * @{
75 */
76#ifdef VBOX_WITH_OLD_VTX_CODE
77# define HM_CHANGED_GUEST_FPU RT_BIT(0)
78# define HM_CHANGED_GUEST_CR0 RT_BIT(1)
79# define HM_CHANGED_GUEST_CR3 RT_BIT(2)
80# define HM_CHANGED_GUEST_CR4 RT_BIT(3)
81# define HM_CHANGED_GUEST_GDTR RT_BIT(4)
82# define HM_CHANGED_GUEST_IDTR RT_BIT(5)
83# define HM_CHANGED_GUEST_LDTR RT_BIT(6)
84# define HM_CHANGED_GUEST_TR RT_BIT(7)
85# define HM_CHANGED_GUEST_MSR RT_BIT(8)
86# define HM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(9)
87# define HM_CHANGED_GUEST_DEBUG RT_BIT(10)
88# define HM_CHANGED_HOST_CONTEXT RT_BIT(11)
89# define HM_CHANGED_ALL_GUEST ( HM_CHANGED_GUEST_SEGMENT_REGS \
90 | HM_CHANGED_GUEST_CR0 \
91 | HM_CHANGED_GUEST_CR3 \
92 | HM_CHANGED_GUEST_CR4 \
93 | HM_CHANGED_GUEST_GDTR \
94 | HM_CHANGED_GUEST_IDTR \
95 | HM_CHANGED_GUEST_LDTR \
96 | HM_CHANGED_GUEST_TR \
97 | HM_CHANGED_GUEST_MSR \
98 | HM_CHANGED_GUEST_DEBUG \
99 | HM_CHANGED_GUEST_FPU)
100#else
101# define HM_CHANGED_GUEST_RIP RT_BIT(0)
102# define HM_CHANGED_GUEST_RSP RT_BIT(1)
103# define HM_CHANGED_GUEST_RFLAGS RT_BIT(2)
104# define HM_CHANGED_GUEST_CR0 RT_BIT(3)
105# define HM_CHANGED_GUEST_CR3 RT_BIT(4)
106# define HM_CHANGED_GUEST_CR4 RT_BIT(5)
107# define HM_CHANGED_GUEST_GDTR RT_BIT(6)
108# define HM_CHANGED_GUEST_IDTR RT_BIT(7)
109# define HM_CHANGED_GUEST_LDTR RT_BIT(8)
110# define HM_CHANGED_GUEST_TR RT_BIT(9)
111# define HM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(10)
112# define HM_CHANGED_GUEST_DEBUG RT_BIT(11)
113# define HM_CHANGED_GUEST_FS_BASE_MSR RT_BIT(12)
114# define HM_CHANGED_GUEST_GS_BASE_MSR RT_BIT(13)
115# define HM_CHANGED_GUEST_SYSENTER_CS_MSR RT_BIT(14)
116# define HM_CHANGED_GUEST_SYSENTER_EIP_MSR RT_BIT(15)
117# define HM_CHANGED_GUEST_SYSENTER_ESP_MSR RT_BIT(16)
118# define HM_CHANGED_VMX_GUEST_AUTO_MSRS RT_BIT(17)
119# define HM_CHANGED_VMX_GUEST_ACTIVITY_STATE RT_BIT(18)
120# define HM_CHANGED_VMX_GUEST_APIC_STATE RT_BIT(19)
121# define HM_CHANGED_VMX_ENTRY_CTLS RT_BIT(20)
122# define HM_CHANGED_VMX_EXIT_CTLS RT_BIT(21)
123
124# define HM_CHANGED_HOST_CONTEXT RT_BIT(22)
125
126# define HM_CHANGED_ALL_GUEST ( HM_CHANGED_GUEST_RIP \
127 | HM_CHANGED_GUEST_RSP \
128 | HM_CHANGED_GUEST_RFLAGS \
129 | HM_CHANGED_GUEST_CR0 \
130 | HM_CHANGED_GUEST_CR3 \
131 | HM_CHANGED_GUEST_CR4 \
132 | HM_CHANGED_GUEST_GDTR \
133 | HM_CHANGED_GUEST_IDTR \
134 | HM_CHANGED_GUEST_LDTR \
135 | HM_CHANGED_GUEST_TR \
136 | HM_CHANGED_GUEST_SEGMENT_REGS \
137 | HM_CHANGED_GUEST_DEBUG \
138 | HM_CHANGED_GUEST_FS_BASE_MSR \
139 | HM_CHANGED_GUEST_GS_BASE_MSR \
140 | HM_CHANGED_GUEST_SYSENTER_CS_MSR \
141 | HM_CHANGED_GUEST_SYSENTER_EIP_MSR \
142 | HM_CHANGED_GUEST_SYSENTER_ESP_MSR \
143 | HM_CHANGED_VMX_GUEST_AUTO_MSRS \
144 | HM_CHANGED_VMX_GUEST_ACTIVITY_STATE \
145 | HM_CHANGED_VMX_GUEST_APIC_STATE \
146 | HM_CHANGED_VMX_ENTRY_CTLS \
147 | HM_CHANGED_VMX_EXIT_CTLS)
148#endif
149
150#define HM_CHANGED_ALL (HM_CHANGED_ALL_GUEST | HM_CHANGED_HOST_CONTEXT)
151/** @} */
152
153/** Maximum number of page flushes we are willing to remember before considering a full TLB flush. */
154#define HM_MAX_TLB_SHOOTDOWN_PAGES 8
155
156/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
157#define HM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
158/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
159#define HM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2 * PAGE_SIZE + 1)
160/** Total guest mapped memory needed. */
161#define HM_VTX_TOTAL_DEVHEAP_MEM (HM_EPT_IDENTITY_PG_TABLE_SIZE + HM_VTX_TSS_SIZE)
162
163/** Enable for TPR guest patching. */
164#define VBOX_HM_WITH_GUEST_PATCHING
165
166/** HM SSM version
167 */
168#ifdef VBOX_HM_WITH_GUEST_PATCHING
169# define HM_SSM_VERSION 5
170# define HM_SSM_VERSION_NO_PATCHING 4
171#else
172# define HM_SSM_VERSION 4
173# define HM_SSM_VERSION_NO_PATCHING 4
174#endif
175#define HM_SSM_VERSION_2_0_X 3
176
177/**
178 * Global per-cpu information. (host)
179 */
180typedef struct HMGLOBLCPUINFO
181{
182 /** The CPU ID. */
183 RTCPUID idCpu;
184 /** The memory object */
185 RTR0MEMOBJ hMemObj;
186 /** Current ASID (AMD-V) / VPID (Intel). */
187 uint32_t uCurrentAsid;
188 /** TLB flush count. */
189 uint32_t cTlbFlushes;
190 /** Whether to flush each new ASID/VPID before use. */
191 bool fFlushAsidBeforeUse;
192 /** Configured for VT-x or AMD-V. */
193 bool fConfigured;
194 /** Set if the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active. */
195 bool fIgnoreAMDVInUseError;
196 /** In use by our code. (for power suspend) */
197 volatile bool fInUse;
198} HMGLOBLCPUINFO;
199/** Pointer to the per-cpu global information. */
200typedef HMGLOBLCPUINFO *PHMGLOBLCPUINFO;
201
202typedef enum
203{
204 HMPENDINGIO_INVALID = 0,
205 HMPENDINGIO_PORT_READ,
206 HMPENDINGIO_PORT_WRITE,
207 HMPENDINGIO_STRING_READ,
208 HMPENDINGIO_STRING_WRITE,
209 /** The usual 32-bit paranoia. */
210 HMPENDINGIO_32BIT_HACK = 0x7fffffff
211} HMPENDINGIO;
212
213
214typedef enum
215{
216 HMTPRINSTR_INVALID,
217 HMTPRINSTR_READ,
218 HMTPRINSTR_READ_SHR4,
219 HMTPRINSTR_WRITE_REG,
220 HMTPRINSTR_WRITE_IMM,
221 HMTPRINSTR_JUMP_REPLACEMENT,
222 /** The usual 32-bit paranoia. */
223 HMTPRINSTR_32BIT_HACK = 0x7fffffff
224} HMTPRINSTR;
225
226typedef struct
227{
228 /** The key is the address of patched instruction. (32 bits GC ptr) */
229 AVLOU32NODECORE Core;
230 /** Original opcode. */
231 uint8_t aOpcode[16];
232 /** Instruction size. */
233 uint32_t cbOp;
234 /** Replacement opcode. */
235 uint8_t aNewOpcode[16];
236 /** Replacement instruction size. */
237 uint32_t cbNewOp;
238 /** Instruction type. */
239 HMTPRINSTR enmType;
240 /** Source operand. */
241 uint32_t uSrcOperand;
242 /** Destination operand. */
243 uint32_t uDstOperand;
244 /** Number of times the instruction caused a fault. */
245 uint32_t cFaults;
246 /** Patch address of the jump replacement. */
247 RTGCPTR32 pJumpTarget;
248} HMTPRPATCH;
249/** Pointer to HMTPRPATCH. */
250typedef HMTPRPATCH *PHMTPRPATCH;
251
252/**
253 * Switcher function, HC to RC.
254 *
255 * @param pVM Pointer to the VM.
256 * @param uOffsetVMCPU VMCPU offset from pVM
257 * @returns Return code indicating the action to take.
258 */
259typedef DECLCALLBACK (int) FNHMSWITCHERHC(PVM pVM, uint32_t uOffsetVMCPU);
260/** Pointer to switcher function. */
261typedef FNHMSWITCHERHC *PFNHMSWITCHERHC;
262
263/**
264 * HM VM Instance data.
265 * Changes to this must checked against the padding of the hm union in VM!
266 */
267typedef struct HM
268{
269 /** Set when we've initialized VMX or SVM. */
270 bool fInitialized;
271
272 /** Set when hardware acceleration is allowed. */
273 bool fAllowed;
274
275 /** Set if nested paging is enabled. */
276 bool fNestedPaging;
277
278 /** Set if nested paging is allowed. */
279 bool fAllowNestedPaging;
280
281 /** Set if large pages are enabled (requires nested paging). */
282 bool fLargePages;
283
284 /** Set if we can support 64-bit guests or not. */
285 bool fAllow64BitGuests;
286
287 /** Set if an IO-APIC is configured for this VM. */
288 bool fHasIoApic;
289
290 /** Set when TPR patching is allowed. */
291 bool fTRPPatchingAllowed;
292
293 /** Set when we initialize VT-x or AMD-V once for all CPUs. */
294 bool fGlobalInit;
295
296 /** Set when TPR patching is active. */
297 bool fTPRPatchingActive;
298 bool u8Alignment[6];
299
300 /** And mask for copying register contents. */
301 uint64_t u64RegisterMask;
302
303 /** Maximum ASID allowed. */
304 uint32_t uMaxAsid;
305
306 /** The maximum number of resumes loops allowed in ring-0 (safety precaution).
307 * This number is set much higher when RTThreadPreemptIsPending is reliable. */
308 uint32_t cMaxResumeLoops;
309
310 /** Guest allocated memory for patching purposes. */
311 RTGCPTR pGuestPatchMem;
312 /** Current free pointer inside the patch block. */
313 RTGCPTR pFreeGuestPatchMem;
314 /** Size of the guest patch memory block. */
315 uint32_t cbGuestPatchMem;
316 uint32_t uPadding1;
317
318#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
319 /** 32 to 64 bits switcher entrypoint. */
320 R0PTRTYPE(PFNHMSWITCHERHC) pfnHost32ToGuest64R0;
321
322 /* AMD-V 64 bits vmrun handler */
323 RTRCPTR pfnSVMGCVMRun64;
324
325 /* VT-x 64 bits vmlaunch handler */
326 RTRCPTR pfnVMXGCStartVM64;
327
328 /* RC handler to setup the 64 bits FPU state. */
329 RTRCPTR pfnSaveGuestFPU64;
330
331 /* RC handler to setup the 64 bits debug state. */
332 RTRCPTR pfnSaveGuestDebug64;
333
334 /* Test handler */
335 RTRCPTR pfnTest64;
336
337 RTRCPTR uAlignment[2];
338/*#elif defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
339 uint32_t u32Alignment[1]; */
340#endif
341
342 struct
343 {
344 /** Set by the ring-0 side of HM to indicate VMX is supported by the
345 * CPU. */
346 bool fSupported;
347
348 /** Set when we've enabled VMX. */
349 bool fEnabled;
350
351 /** Set if VPID is supported. */
352 bool fVpid;
353
354 /** Set if VT-x VPID is allowed. */
355 bool fAllowVpid;
356
357 /** Set if unrestricted guest execution is allowed (real and protected mode without paging). */
358 bool fUnrestrictedGuest;
359
360 /** Whether we're using the preemption timer or not. */
361 bool fUsePreemptTimer;
362 /** The shift mask employed by the VMX-Preemption timer. */
363 uint8_t cPreemptTimerShift;
364
365 bool uAlignment[1];
366
367 /** Virtual address of the TSS page used for real mode emulation. */
368 R3PTRTYPE(PVBOXTSS) pRealModeTSS;
369
370 /** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
371 R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
372
373 /** R0 memory object for the APIC-access page. */
374 RTR0MEMOBJ hMemObjApicAccess;
375 /** Physical address of the APIC-access page. */
376 RTHCPHYS HCPhysApicAccess;
377 /** Virtual address of the APIC-access page. */
378 R0PTRTYPE(uint8_t *) pbApicAccess;
379
380#ifdef VBOX_WITH_CRASHDUMP_MAGIC
381 RTR0MEMOBJ hMemObjScratch;
382 RTHCPHYS HCPhysScratch;
383 R0PTRTYPE(uint8_t *) pbScratch;
384#endif
385 /** Ring 0 handlers for VT-x. */
386 DECLR0CALLBACKMEMBER(void, pfnFlushTaggedTlb, (PVM pVM, PVMCPU pVCpu));
387
388#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
389 uint32_t u32Alignment;
390#endif
391 /** Host CR4 value (set by ring-0 VMX init) */
392 uint64_t hostCR4;
393
394 /** Host EFER value (set by ring-0 VMX init) */
395 uint64_t hostEFER;
396
397 /** VMX MSR values */
398 struct
399 {
400 uint64_t feature_ctrl;
401 uint64_t vmx_basic_info;
402 VMX_CAPABILITY vmx_pin_ctls;
403 VMX_CAPABILITY vmx_proc_ctls;
404 VMX_CAPABILITY vmx_proc_ctls2;
405 VMX_CAPABILITY vmx_exit;
406 VMX_CAPABILITY vmx_entry;
407 uint64_t vmx_misc;
408 uint64_t vmx_cr0_fixed0;
409 uint64_t vmx_cr0_fixed1;
410 uint64_t vmx_cr4_fixed0;
411 uint64_t vmx_cr4_fixed1;
412 uint64_t vmx_vmcs_enum;
413 uint64_t vmx_ept_vpid_caps;
414 } msr;
415
416 /** Flush types for invept & invvpid; they depend on capabilities. */
417 VMX_FLUSH_EPT enmFlushEpt;
418 VMX_FLUSH_VPID enmFlushVpid;
419 } vmx;
420
421 struct
422 {
423 /** Set by the ring-0 side of HM to indicate SVM is supported by the
424 * CPU. */
425 bool fSupported;
426 /** Set when we've enabled SVM. */
427 bool fEnabled;
428 /** Set if erratum 170 affects the AMD cpu. */
429 bool fAlwaysFlushTLB;
430 /** Set when the hack to ignore VERR_SVM_IN_USE is active. */
431 bool fIgnoreInUseError;
432
433 /** R0 memory object for the IO bitmap (12kb). */
434 RTR0MEMOBJ hMemObjIOBitmap;
435 /** Physical address of the IO bitmap (12kb). */
436 RTHCPHYS HCPhysIOBitmap;
437 /** Virtual address of the IO bitmap. */
438 R0PTRTYPE(void *) pvIOBitmap;
439
440 /* HWCR MSR (for diagnostics) */
441 uint64_t msrHwcr;
442
443 /** SVM revision. */
444 uint32_t u32Rev;
445
446 /** SVM feature bits from cpuid 0x8000000a */
447 uint32_t u32Features;
448 } svm;
449
450 /**
451 * AVL tree with all patches (active or disabled) sorted by guest instruction address
452 */
453 AVLOU32TREE PatchTree;
454 uint32_t cPatches;
455 HMTPRPATCH aPatches[64];
456
457 struct
458 {
459 uint32_t u32AMDFeatureECX;
460 uint32_t u32AMDFeatureEDX;
461 } cpuid;
462
463 /** Saved error from detection */
464 int32_t lLastError;
465
466 /** HMR0Init was run */
467 bool fHMR0Init;
468 bool u8Alignment1[7];
469
470 STAMCOUNTER StatTprPatchSuccess;
471 STAMCOUNTER StatTprPatchFailure;
472 STAMCOUNTER StatTprReplaceSuccess;
473 STAMCOUNTER StatTprReplaceFailure;
474} HM;
475/** Pointer to HM VM instance data. */
476typedef HM *PHM;
477
478/* Maximum number of cached entries. */
479#define VMCSCACHE_MAX_ENTRY 128
480
481/* Structure for storing read and write VMCS actions. */
482typedef struct VMCSCACHE
483{
484#ifdef VBOX_WITH_CRASHDUMP_MAGIC
485 /* Magic marker for searching in crash dumps. */
486 uint8_t aMagic[16];
487 uint64_t uMagic;
488 uint64_t u64TimeEntry;
489 uint64_t u64TimeSwitch;
490 uint64_t cResume;
491 uint64_t interPD;
492 uint64_t pSwitcher;
493 uint32_t uPos;
494 uint32_t idCpu;
495#endif
496 /* CR2 is saved here for EPT syncing. */
497 uint64_t cr2;
498 struct
499 {
500 uint32_t cValidEntries;
501 uint32_t uAlignment;
502 uint32_t aField[VMCSCACHE_MAX_ENTRY];
503 uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
504 } Write;
505 struct
506 {
507 uint32_t cValidEntries;
508 uint32_t uAlignment;
509 uint32_t aField[VMCSCACHE_MAX_ENTRY];
510 uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
511 } Read;
512#ifdef DEBUG
513 struct
514 {
515 RTHCPHYS HCPhysCpuPage;
516 RTHCPHYS HCPhysVmcs;
517 RTGCPTR pCache;
518 RTGCPTR pCtx;
519 } TestIn;
520 struct
521 {
522 RTHCPHYS HCPhysVmcs;
523 RTGCPTR pCache;
524 RTGCPTR pCtx;
525 uint64_t eflags;
526 uint64_t cr8;
527 } TestOut;
528 struct
529 {
530 uint64_t param1;
531 uint64_t param2;
532 uint64_t param3;
533 uint64_t param4;
534 } ScratchPad;
535#endif
536} VMCSCACHE;
537/** Pointer to VMCSCACHE. */
538typedef VMCSCACHE *PVMCSCACHE;
539
540/** VMX StartVM function. */
541typedef DECLCALLBACK(int) FNHMVMXSTARTVM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);
542/** Pointer to a VMX StartVM function. */
543typedef R0PTRTYPE(FNHMVMXSTARTVM *) PFNHMVMXSTARTVM;
544
545/** SVM VMRun function. */
546typedef DECLCALLBACK(int) FNHMSVMVMRUN(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu);
547/** Pointer to a SVM VMRun function. */
548typedef R0PTRTYPE(FNHMSVMVMRUN *) PFNHMSVMVMRUN;
549
550/**
551 * HM VMCPU Instance data.
552 */
553typedef struct HMCPU
554{
555 /** Old style FPU reporting trap mask override performed (optimization) */
556 bool fFPUOldStyleOverride;
557 /** Set if we don't have to flush the TLB on VM entry. */
558 bool fResumeVM;
559 /** Set if we need to flush the TLB during the world switch. */
560 bool fForceTLBFlush;
561 /** Set when we're using VT-x or AMD-V at that moment. */
562 bool fActive;
563 /** Set when the TLB has been checked until we return from the world switch. */
564 volatile bool fCheckedTLBFlush;
565 uint8_t u8Alignment[3];
566
567 /** World switch exit counter. */
568 volatile uint32_t cWorldSwitchExits;
569 /** HM_CHANGED_* flags. */
570 uint32_t fContextUseFlags;
571 /** Id of the last cpu we were executing code on (NIL_RTCPUID for the first time) */
572 RTCPUID idLastCpu;
573 /** TLB flush count */
574 uint32_t cTlbFlushes;
575 /** Current ASID in use by the VM */
576 uint32_t uCurrentAsid;
577 uint32_t u32Alignment;
578
579 /* Host's TSC_AUX MSR (used when RDTSCP doesn't cause VM-exits). */
580 uint64_t u64HostTscAux;
581
582 struct
583 {
584 /** Physical address of the VM control structure (VMCS). */
585 RTHCPHYS HCPhysVmcs;
586 /** R0 memory object for the VM control structure (VMCS). */
587 RTR0MEMOBJ hMemObjVmcs;
588 /** Virtual address of the VM control structure (VMCS). */
589 R0PTRTYPE(void *) pvVmcs;
590 /** Ring 0 handlers for VT-x. */
591 PFNHMVMXSTARTVM pfnStartVM;
592#if HC_ARCH_BITS == 32
593 uint32_t u32Alignment1;
594#endif
595
596 /** Current VMX_VMCS32_CTRL_PIN_EXEC_CONTROLS. */
597 uint32_t u32PinCtls;
598 /** Current VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS. */
599 uint32_t u32ProcCtls;
600 /** Current VMX_VMCS32_CTRL_PROC_EXEC2_CONTROLS. */
601 uint32_t u32ProcCtls2;
602 /** Current VMX_VMCS32_CTRL_EXIT_CONTROLS. */
603 uint32_t u32ExitCtls;
604 /** Current VMX_VMCS32_CTRL_ENTRY_CONTROLS. */
605 uint32_t u32EntryCtls;
606 /** Physical address of the virtual APIC page for TPR caching. */
607 RTHCPHYS HCPhysVirtApic;
608 /** R0 memory object for the virtual APIC page for TPR caching. */
609 RTR0MEMOBJ hMemObjVirtApic;
610 /** Virtual address of the virtual APIC page for TPR caching. */
611 R0PTRTYPE(uint8_t *) pbVirtApic;
612#if HC_ARCH_BITS == 32
613 uint32_t u32Alignment2;
614#endif
615
616 /** Current CR0 mask. */
617 uint64_t cr0_mask;
618 /** Current CR4 mask. */
619 uint64_t cr4_mask;
620 /** Current exception bitmap. */
621 uint32_t u32XcptBitmap;
622 /** The updated-guest-state mask. */
623 uint32_t fUpdatedGuestState;
624 /** Current EPTP. */
625 RTHCPHYS GCPhysEPTP;
626
627 /** Physical address of the MSR bitmap. */
628 RTHCPHYS HCPhysMsrBitmap;
629 /** R0 memory object for the MSR bitmap. */
630 RTR0MEMOBJ hMemObjMsrBitmap;
631 /** Virtual address of the MSR bitmap. */
632 R0PTRTYPE(void *) pvMsrBitmap;
633
634#ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
635 /** Physical address of the VM-entry MSR-load and VM-exit MSR-store area (used
636 * for guest MSRs). */
637 RTHCPHYS HCPhysGuestMsr;
638 /** R0 memory object of the VM-entry MSR-load and VM-exit MSR-store area
639 * (used for guest MSRs). */
640 RTR0MEMOBJ hMemObjGuestMsr;
641 /** Virtual address of the VM-entry MSR-load and VM-exit MSR-store area (used
642 * for guest MSRs). */
643 R0PTRTYPE(void *) pvGuestMsr;
644
645 /** Physical address of the VM-exit MSR-load area (used for host MSRs). */
646 RTHCPHYS HCPhysHostMsr;
647 /** R0 memory object for the VM-exit MSR-load area (used for host MSRs). */
648 RTR0MEMOBJ hMemObjHostMsr;
649 /** Virtual address of the VM-exit MSR-load area (used for host MSRs). */
650 R0PTRTYPE(void *) pvHostMsr;
651
652 /* Number of automatically loaded/restored guest MSRs during the world switch. */
653 uint32_t cGuestMsrs;
654 uint32_t uAlignment;
655#endif /* VBOX_WITH_AUTO_MSR_LOAD_RESTORE */
656
657 /* The cached APIC-base MSR used for identifying when to map the HC physical APIC-access page. */
658 uint64_t u64MsrApicBase;
659 /* Last use TSC offset value. (cached) */
660 uint64_t u64TSCOffset;
661 /** VMCS cache. */
662 VMCSCACHE VMCSCache;
663
664 /** Real-mode emulation state. */
665 struct
666 {
667 X86DESCATTR uAttrCS;
668 X86DESCATTR uAttrDS;
669 X86DESCATTR uAttrES;
670 X86DESCATTR uAttrFS;
671 X86DESCATTR uAttrGS;
672 X86DESCATTR uAttrSS;
673 X86EFLAGS eflags;
674 uint32_t fRealOnV86Active;
675 } RealMode;
676
677 struct
678 {
679 uint64_t u64VMCSPhys;
680 uint32_t u32VMCSRevision;
681 uint32_t u32InstrError;
682 uint32_t u32ExitReason;
683 RTCPUID idEnteredCpu;
684 RTCPUID idCurrentCpu;
685 uint32_t padding;
686 } lasterror;
687
688 /** The last seen guest paging mode (by VT-x). */
689 PGMMODE enmLastSeenGuestMode;
690 /** Current guest paging mode (as seen by HMR3PagingModeChanged). */
691 PGMMODE enmCurrGuestMode;
692 /** Previous guest paging mode (as seen by HMR3PagingModeChanged). */
693 PGMMODE enmPrevGuestMode;
694 } vmx;
695
696 struct
697 {
698 /** R0 memory object for the host VM control block (VMCB). */
699 RTR0MEMOBJ hMemObjVMCBHost;
700 /** Physical address of the host VM control block (VMCB). */
701 RTHCPHYS HCPhysVMCBHost;
702 /** Virtual address of the host VM control block (VMCB). */
703 R0PTRTYPE(void *) pvVMCBHost;
704
705 /** R0 memory object for the VM control block (VMCB). */
706 RTR0MEMOBJ hMemObjVMCB;
707 /** Physical address of the VM control block (VMCB). */
708 RTHCPHYS HCPhysVMCB;
709 /** Virtual address of the VM control block (VMCB). */
710 R0PTRTYPE(void *) pvVMCB;
711
712 /** Ring 0 handlers for VT-x. */
713 PFNHMSVMVMRUN pfnVMRun;
714
715 /** R0 memory object for the MSR bitmap (8kb). */
716 RTR0MEMOBJ hMemObjMsrBitmap;
717 /** Physical address of the MSR bitmap (8kb). */
718 RTHCPHYS HCPhysMsrBitmap;
719 /** Virtual address of the MSR bitmap. */
720 R0PTRTYPE(void *) pvMsrBitmap;
721 } svm;
722
723 /** Event injection state. */
724 struct
725 {
726 uint32_t fPending;
727 uint32_t u32ErrCode;
728 uint64_t u64IntrInfo;
729 } Event;
730
731 /** IO Block emulation state. */
732 struct
733 {
734 bool fEnabled;
735 uint8_t u8Align[7];
736
737 /** RIP at the start of the io code we wish to emulate in the recompiler. */
738 RTGCPTR GCPtrFunctionEip;
739
740 uint64_t cr0;
741 } EmulateIoBlock;
742
743 struct
744 {
745 /* Pending IO operation type. */
746 HMPENDINGIO enmType;
747 uint32_t uPadding;
748 RTGCPTR GCPtrRip;
749 RTGCPTR GCPtrRipNext;
750 union
751 {
752 struct
753 {
754 unsigned uPort;
755 unsigned uAndVal;
756 unsigned cbSize;
757 } Port;
758 uint64_t aRaw[2];
759 } s;
760 } PendingIO;
761
762 /** The PAE PDPEs used with Nested Paging (only valid when
763 * VMCPU_FF_HM_UPDATE_PAE_PDPES is set). */
764 X86PDPE aPdpes[4];
765
766 /** Current shadow paging mode. */
767 PGMMODE enmShadowMode;
768
769 /** The CPU ID of the CPU currently owning the VMCS. Set in
770 * HMR0Enter and cleared in HMR0Leave. */
771 RTCPUID idEnteredCpu;
772
773 /** To keep track of pending TLB shootdown pages. (SMP guest only) */
774 struct
775 {
776 RTGCPTR aPages[HM_MAX_TLB_SHOOTDOWN_PAGES];
777 unsigned cPages;
778 } TlbShootdown;
779
780 /** For saving stack space, the disassembler state is allocated here instead of
781 * on the stack. */
782 DISCPUSTATE DisState;
783
784 uint32_t padding2[1];
785
786 STAMPROFILEADV StatEntry;
787 STAMPROFILEADV StatExit1;
788 STAMPROFILEADV StatExit2;
789#ifdef VBOX_WITH_OLD_VTX_CODE /* temporary for tracking down darwin issues. */
790 STAMPROFILEADV StatExit2Sub1;
791 STAMPROFILEADV StatExit2Sub2;
792 STAMPROFILEADV StatExit2Sub3;
793#endif
794 STAMPROFILEADV StatLoadGuestState;
795 STAMPROFILEADV StatInGC;
796
797#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
798 STAMPROFILEADV StatWorldSwitch3264;
799#endif
800 STAMPROFILEADV StatPoke;
801 STAMPROFILEADV StatSpinPoke;
802 STAMPROFILEADV StatSpinPokeFailed;
803
804 STAMCOUNTER StatIntInject;
805
806 STAMCOUNTER StatExitShadowNM;
807 STAMCOUNTER StatExitGuestNM;
808 STAMCOUNTER StatExitShadowPF; /* Misleading, currently used for MMIO #PFs as well. */
809 STAMCOUNTER StatExitShadowPFEM;
810 STAMCOUNTER StatExitGuestPF;
811 STAMCOUNTER StatExitGuestUD;
812 STAMCOUNTER StatExitGuestSS;
813 STAMCOUNTER StatExitGuestNP;
814 STAMCOUNTER StatExitGuestGP;
815 STAMCOUNTER StatExitGuestDE;
816 STAMCOUNTER StatExitGuestDB;
817 STAMCOUNTER StatExitGuestMF;
818 STAMCOUNTER StatExitGuestBP;
819 STAMCOUNTER StatExitGuestXF;
820 STAMCOUNTER StatExitGuestXcpUnk;
821 STAMCOUNTER StatExitInvlpg;
822 STAMCOUNTER StatExitInvd;
823 STAMCOUNTER StatExitWbinvd;
824 STAMCOUNTER StatExitPause;
825 STAMCOUNTER StatExitCpuid;
826 STAMCOUNTER StatExitRdtsc;
827 STAMCOUNTER StatExitRdtscp;
828 STAMCOUNTER StatExitRdpmc;
829 STAMCOUNTER StatExitRdrand;
830 STAMCOUNTER StatExitCli;
831 STAMCOUNTER StatExitSti;
832 STAMCOUNTER StatExitPushf;
833 STAMCOUNTER StatExitPopf;
834 STAMCOUNTER StatExitIret;
835 STAMCOUNTER StatExitInt;
836 STAMCOUNTER StatExitCRxWrite[16];
837 STAMCOUNTER StatExitCRxRead[16];
838 STAMCOUNTER StatExitDRxWrite;
839 STAMCOUNTER StatExitDRxRead;
840 STAMCOUNTER StatExitRdmsr;
841 STAMCOUNTER StatExitWrmsr;
842 STAMCOUNTER StatExitClts;
843 STAMCOUNTER StatExitXdtrAccess;
844 STAMCOUNTER StatExitHlt;
845 STAMCOUNTER StatExitMwait;
846 STAMCOUNTER StatExitMonitor;
847 STAMCOUNTER StatExitLmsw;
848 STAMCOUNTER StatExitIOWrite;
849 STAMCOUNTER StatExitIORead;
850 STAMCOUNTER StatExitIOStringWrite;
851 STAMCOUNTER StatExitIOStringRead;
852 STAMCOUNTER StatExitIntWindow;
853 STAMCOUNTER StatExitMaxResume;
854 STAMCOUNTER StatExitExtInt;
855 STAMCOUNTER StatExitPreemptTimer;
856 STAMCOUNTER StatExitTprBelowThreshold;
857 STAMCOUNTER StatExitTaskSwitch;
858 STAMCOUNTER StatExitMtf;
859 STAMCOUNTER StatExitApicAccess;
860 STAMCOUNTER StatIntReinject;
861 STAMCOUNTER StatPendingHostIrq;
862
863 STAMCOUNTER StatFlushPage;
864 STAMCOUNTER StatFlushPageManual;
865 STAMCOUNTER StatFlushPhysPageManual;
866 STAMCOUNTER StatFlushTlb;
867 STAMCOUNTER StatFlushTlbManual;
868 STAMCOUNTER StatFlushTlbWorldSwitch;
869 STAMCOUNTER StatNoFlushTlbWorldSwitch;
870 STAMCOUNTER StatFlushAsid;
871 STAMCOUNTER StatFlushNestedPaging;
872 STAMCOUNTER StatFlushTlbInvlpgVirt;
873 STAMCOUNTER StatFlushTlbInvlpgPhys;
874 STAMCOUNTER StatTlbShootdown;
875 STAMCOUNTER StatTlbShootdownFlush;
876
877 STAMCOUNTER StatSwitchGuestIrq;
878 STAMCOUNTER StatSwitchHmToR3FF;
879 STAMCOUNTER StatSwitchExitToR3;
880 STAMCOUNTER StatSwitchLongJmpToR3;
881
882 STAMCOUNTER StatTscOffset;
883 STAMCOUNTER StatTscIntercept;
884 STAMCOUNTER StatTscInterceptOverFlow;
885
886 STAMCOUNTER StatExitReasonNpf;
887 STAMCOUNTER StatDRxArmed;
888 STAMCOUNTER StatDRxContextSwitch;
889 STAMCOUNTER StatDRxIoCheck;
890
891 STAMCOUNTER StatLoadMinimal;
892 STAMCOUNTER StatLoadFull;
893
894#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
895 STAMCOUNTER StatFpu64SwitchBack;
896 STAMCOUNTER StatDebug64SwitchBack;
897#endif
898
899#ifdef VBOX_WITH_STATISTICS
900 R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
901 R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
902 R3PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqs;
903 R0PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqsR0;
904#endif
905} HMCPU;
906/** Pointer to HM VM instance data. */
907typedef HMCPU *PHMCPU;
908
909
910#ifdef IN_RING0
911
912VMMR0DECL(PHMGLOBLCPUINFO) HMR0GetCurrentCpu(void);
913VMMR0DECL(PHMGLOBLCPUINFO) HMR0GetCurrentCpuEx(RTCPUID idCpu);
914
915
916#ifdef VBOX_STRICT
917VMMR0DECL(void) HMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
918VMMR0DECL(void) HMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg);
919#else
920# define HMDumpRegs(a, b ,c) do { } while (0)
921# define HMR0DumpDescriptor(a, b, c) do { } while (0)
922#endif
923
924# ifdef VBOX_WITH_KERNEL_USING_XMM
925DECLASM(int) hmR0VMXStartVMWrapXMM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu, PFNHMVMXSTARTVM pfnStartVM);
926DECLASM(int) hmR0SVMRunWrapXMM(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu, PFNHMSVMVMRUN pfnVMRun);
927# endif
928
929# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
930/**
931 * Gets 64-bit GDTR and IDTR on darwin.
932 * @param pGdtr Where to store the 64-bit GDTR.
933 * @param pIdtr Where to store the 64-bit IDTR.
934 */
935DECLASM(void) hmR0Get64bitGdtrAndIdtr(PX86XDTR64 pGdtr, PX86XDTR64 pIdtr);
936
937/**
938 * Gets 64-bit CR3 on darwin.
939 * @returns CR3
940 */
941DECLASM(uint64_t) hmR0Get64bitCR3(void);
942# endif
943
944#endif /* IN_RING0 */
945
946/** @} */
947
948RT_C_DECLS_END
949
950#endif
951
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