VirtualBox

source: vbox/trunk/src/VBox/VMM/include/HMInternal.h@ 45502

Last change on this file since 45502 was 45502, checked in by vboxsync, 12 years ago

VMMR0/HMVMXR0: Redo the event injection logic to be done only on the entry side. This is cleaner and any returns the recompiler should not lose any events.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 35.1 KB
Line 
1/* $Id: HMInternal.h 45502 2013-04-12 00:22:50Z vboxsync $ */
2/** @file
3 * HM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef ___HMInternal_h
19#define ___HMInternal_h
20
21#include <VBox/cdefs.h>
22#include <VBox/types.h>
23#include <VBox/vmm/em.h>
24#include <VBox/vmm/stam.h>
25#include <VBox/dis.h>
26#include <VBox/vmm/hm.h>
27#include <VBox/vmm/hm_vmx.h>
28#include <VBox/vmm/pgm.h>
29#include <VBox/vmm/cpum.h>
30#include <iprt/memobj.h>
31#include <iprt/cpuset.h>
32#include <iprt/mp.h>
33#include <iprt/avl.h>
34
35#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL) || defined (VBOX_WITH_64_BITS_GUESTS)
36/* Enable 64 bits guest support. */
37# define VBOX_ENABLE_64_BITS_GUESTS
38#endif
39
40#ifdef VBOX_WITH_OLD_VTX_CODE
41# define VMX_USE_CACHED_VMCS_ACCESSES
42#elif HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
43# define VMX_USE_CACHED_VMCS_ACCESSES
44#endif
45
46#define HM_VMX_EMULATE_REALMODE
47
48/* The MSR auto load/store does not work for KERNEL_GS_BASE MSR, thus we
49 * handle this MSR manually. See @bugref{6208}. This is clearly visible while
50 * booting Solaris 11 (11.1 b19) VMs with 2 Cpus.
51 *
52 * Note: don't forget to update the assembly files while modifying this!
53 */
54# define VBOX_WITH_AUTO_MSR_LOAD_RESTORE
55
56RT_C_DECLS_BEGIN
57
58
59/** @defgroup grp_hm_int Internal
60 * @ingroup grp_hm
61 * @internal
62 * @{
63 */
64
65
66/** Maximum number of exit reason statistics counters. */
67#define MAX_EXITREASON_STAT 0x100
68#define MASK_EXITREASON_STAT 0xff
69#define MASK_INJECT_IRQ_STAT 0xff
70
71/** @name Changed flags
72 * These flags are used to keep track of which important registers that
73 * have been changed since last they were reset.
74 * @{
75 */
76#ifdef VBOX_WITH_OLD_VTX_CODE
77# define HM_CHANGED_GUEST_FPU RT_BIT(0)
78# define HM_CHANGED_GUEST_CR0 RT_BIT(1)
79# define HM_CHANGED_GUEST_CR3 RT_BIT(2)
80# define HM_CHANGED_GUEST_CR4 RT_BIT(3)
81# define HM_CHANGED_GUEST_GDTR RT_BIT(4)
82# define HM_CHANGED_GUEST_IDTR RT_BIT(5)
83# define HM_CHANGED_GUEST_LDTR RT_BIT(6)
84# define HM_CHANGED_GUEST_TR RT_BIT(7)
85# define HM_CHANGED_GUEST_MSR RT_BIT(8)
86# define HM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(9)
87# define HM_CHANGED_GUEST_DEBUG RT_BIT(10)
88# define HM_CHANGED_HOST_CONTEXT RT_BIT(11)
89# define HM_CHANGED_ALL_GUEST ( HM_CHANGED_GUEST_SEGMENT_REGS \
90 | HM_CHANGED_GUEST_CR0 \
91 | HM_CHANGED_GUEST_CR3 \
92 | HM_CHANGED_GUEST_CR4 \
93 | HM_CHANGED_GUEST_GDTR \
94 | HM_CHANGED_GUEST_IDTR \
95 | HM_CHANGED_GUEST_LDTR \
96 | HM_CHANGED_GUEST_TR \
97 | HM_CHANGED_GUEST_MSR \
98 | HM_CHANGED_GUEST_DEBUG \
99 | HM_CHANGED_GUEST_FPU)
100#else
101# define HM_CHANGED_GUEST_RIP RT_BIT(0)
102# define HM_CHANGED_GUEST_RSP RT_BIT(1)
103# define HM_CHANGED_GUEST_RFLAGS RT_BIT(2)
104# define HM_CHANGED_GUEST_CR0 RT_BIT(3)
105# define HM_CHANGED_GUEST_CR3 RT_BIT(4)
106# define HM_CHANGED_GUEST_CR4 RT_BIT(5)
107# define HM_CHANGED_GUEST_GDTR RT_BIT(6)
108# define HM_CHANGED_GUEST_IDTR RT_BIT(7)
109# define HM_CHANGED_GUEST_LDTR RT_BIT(8)
110# define HM_CHANGED_GUEST_TR RT_BIT(9)
111# define HM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(10)
112# define HM_CHANGED_GUEST_DEBUG RT_BIT(11)
113# define HM_CHANGED_GUEST_FS_BASE_MSR RT_BIT(12)
114# define HM_CHANGED_GUEST_GS_BASE_MSR RT_BIT(13)
115# define HM_CHANGED_GUEST_SYSENTER_CS_MSR RT_BIT(14)
116# define HM_CHANGED_GUEST_SYSENTER_EIP_MSR RT_BIT(15)
117# define HM_CHANGED_GUEST_SYSENTER_ESP_MSR RT_BIT(16)
118# define HM_CHANGED_VMX_GUEST_AUTO_MSRS RT_BIT(17)
119# define HM_CHANGED_VMX_GUEST_ACTIVITY_STATE RT_BIT(18)
120# define HM_CHANGED_VMX_GUEST_APIC_STATE RT_BIT(19)
121# define HM_CHANGED_VMX_ENTRY_CTLS RT_BIT(20)
122# define HM_CHANGED_VMX_EXIT_CTLS RT_BIT(21)
123
124# define HM_CHANGED_HOST_CONTEXT RT_BIT(22)
125
126# define HM_CHANGED_ALL_GUEST ( HM_CHANGED_GUEST_RIP \
127 | HM_CHANGED_GUEST_RSP \
128 | HM_CHANGED_GUEST_RFLAGS \
129 | HM_CHANGED_GUEST_CR0 \
130 | HM_CHANGED_GUEST_CR3 \
131 | HM_CHANGED_GUEST_CR4 \
132 | HM_CHANGED_GUEST_GDTR \
133 | HM_CHANGED_GUEST_IDTR \
134 | HM_CHANGED_GUEST_LDTR \
135 | HM_CHANGED_GUEST_TR \
136 | HM_CHANGED_GUEST_SEGMENT_REGS \
137 | HM_CHANGED_GUEST_DEBUG \
138 | HM_CHANGED_GUEST_FS_BASE_MSR \
139 | HM_CHANGED_GUEST_GS_BASE_MSR \
140 | HM_CHANGED_GUEST_SYSENTER_CS_MSR \
141 | HM_CHANGED_GUEST_SYSENTER_EIP_MSR \
142 | HM_CHANGED_GUEST_SYSENTER_ESP_MSR \
143 | HM_CHANGED_VMX_GUEST_AUTO_MSRS \
144 | HM_CHANGED_VMX_GUEST_ACTIVITY_STATE \
145 | HM_CHANGED_VMX_GUEST_APIC_STATE \
146 | HM_CHANGED_VMX_ENTRY_CTLS \
147 | HM_CHANGED_VMX_EXIT_CTLS)
148#endif
149
150#define HM_CHANGED_ALL (HM_CHANGED_ALL_GUEST | HM_CHANGED_HOST_CONTEXT)
151/** @} */
152
153/** Maximum number of page flushes we are willing to remember before considering a full TLB flush. */
154#define HM_MAX_TLB_SHOOTDOWN_PAGES 8
155
156/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
157#define HM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
158/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
159#define HM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2 * PAGE_SIZE + 1)
160/** Total guest mapped memory needed. */
161#define HM_VTX_TOTAL_DEVHEAP_MEM (HM_EPT_IDENTITY_PG_TABLE_SIZE + HM_VTX_TSS_SIZE)
162
163/** Enable for TPR guest patching. */
164#define VBOX_HM_WITH_GUEST_PATCHING
165
166/** HM SSM version
167 */
168#ifdef VBOX_HM_WITH_GUEST_PATCHING
169# define HM_SSM_VERSION 5
170# define HM_SSM_VERSION_NO_PATCHING 4
171#else
172# define HM_SSM_VERSION 4
173# define HM_SSM_VERSION_NO_PATCHING 4
174#endif
175#define HM_SSM_VERSION_2_0_X 3
176
177/**
178 * Global per-cpu information. (host)
179 */
180typedef struct HMGLOBLCPUINFO
181{
182 /** The CPU ID. */
183 RTCPUID idCpu;
184 /** The memory object */
185 RTR0MEMOBJ hMemObj;
186 /** Current ASID (AMD-V) / VPID (Intel). */
187 uint32_t uCurrentAsid;
188 /** TLB flush count. */
189 uint32_t cTlbFlushes;
190 /** Whether to flush each new ASID/VPID before use. */
191 bool fFlushAsidBeforeUse;
192 /** Configured for VT-x or AMD-V. */
193 bool fConfigured;
194 /** Set if the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active. */
195 bool fIgnoreAMDVInUseError;
196 /** In use by our code. (for power suspend) */
197 volatile bool fInUse;
198} HMGLOBLCPUINFO;
199/** Pointer to the per-cpu global information. */
200typedef HMGLOBLCPUINFO *PHMGLOBLCPUINFO;
201
202typedef enum
203{
204 HMPENDINGIO_INVALID = 0,
205 HMPENDINGIO_PORT_READ,
206 HMPENDINGIO_PORT_WRITE,
207 HMPENDINGIO_STRING_READ,
208 HMPENDINGIO_STRING_WRITE,
209 /** The usual 32-bit paranoia. */
210 HMPENDINGIO_32BIT_HACK = 0x7fffffff
211} HMPENDINGIO;
212
213
214typedef enum
215{
216 HMTPRINSTR_INVALID,
217 HMTPRINSTR_READ,
218 HMTPRINSTR_READ_SHR4,
219 HMTPRINSTR_WRITE_REG,
220 HMTPRINSTR_WRITE_IMM,
221 HMTPRINSTR_JUMP_REPLACEMENT,
222 /** The usual 32-bit paranoia. */
223 HMTPRINSTR_32BIT_HACK = 0x7fffffff
224} HMTPRINSTR;
225
226typedef struct
227{
228 /** The key is the address of patched instruction. (32 bits GC ptr) */
229 AVLOU32NODECORE Core;
230 /** Original opcode. */
231 uint8_t aOpcode[16];
232 /** Instruction size. */
233 uint32_t cbOp;
234 /** Replacement opcode. */
235 uint8_t aNewOpcode[16];
236 /** Replacement instruction size. */
237 uint32_t cbNewOp;
238 /** Instruction type. */
239 HMTPRINSTR enmType;
240 /** Source operand. */
241 uint32_t uSrcOperand;
242 /** Destination operand. */
243 uint32_t uDstOperand;
244 /** Number of times the instruction caused a fault. */
245 uint32_t cFaults;
246 /** Patch address of the jump replacement. */
247 RTGCPTR32 pJumpTarget;
248} HMTPRPATCH;
249/** Pointer to HMTPRPATCH. */
250typedef HMTPRPATCH *PHMTPRPATCH;
251
252/**
253 * Switcher function, HC to RC.
254 *
255 * @param pVM Pointer to the VM.
256 * @param uOffsetVMCPU VMCPU offset from pVM
257 * @returns Return code indicating the action to take.
258 */
259typedef DECLCALLBACK (int) FNHMSWITCHERHC(PVM pVM, uint32_t uOffsetVMCPU);
260/** Pointer to switcher function. */
261typedef FNHMSWITCHERHC *PFNHMSWITCHERHC;
262
263/**
264 * HM VM Instance data.
265 * Changes to this must checked against the padding of the hm union in VM!
266 */
267typedef struct HM
268{
269 /** Set when we've initialized VMX or SVM. */
270 bool fInitialized;
271
272 /** Set when hardware acceleration is allowed. */
273 bool fAllowed;
274
275 /** Set if nested paging is enabled. */
276 bool fNestedPaging;
277
278 /** Set if nested paging is allowed. */
279 bool fAllowNestedPaging;
280
281 /** Set if large pages are enabled (requires nested paging). */
282 bool fLargePages;
283
284 /** Set if we can support 64-bit guests or not. */
285 bool fAllow64BitGuests;
286
287 /** Set if an IO-APIC is configured for this VM. */
288 bool fHasIoApic;
289
290 /** Set when TPR patching is allowed. */
291 bool fTRPPatchingAllowed;
292
293 /** Set when we initialize VT-x or AMD-V once for all CPUs. */
294 bool fGlobalInit;
295
296 /** Set when TPR patching is active. */
297 bool fTPRPatchingActive;
298 bool u8Alignment[6];
299
300 /** And mask for copying register contents. */
301 uint64_t u64RegisterMask;
302
303 /** Maximum ASID allowed. */
304 uint32_t uMaxAsid;
305
306 /** The maximum number of resumes loops allowed in ring-0 (safety precaution).
307 * This number is set much higher when RTThreadPreemptIsPending is reliable. */
308 uint32_t cMaxResumeLoops;
309
310 /** Guest allocated memory for patching purposes. */
311 RTGCPTR pGuestPatchMem;
312 /** Current free pointer inside the patch block. */
313 RTGCPTR pFreeGuestPatchMem;
314 /** Size of the guest patch memory block. */
315 uint32_t cbGuestPatchMem;
316 uint32_t uPadding1;
317
318#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
319 /** 32 to 64 bits switcher entrypoint. */
320 R0PTRTYPE(PFNHMSWITCHERHC) pfnHost32ToGuest64R0;
321
322 /* AMD-V 64 bits vmrun handler */
323 RTRCPTR pfnSVMGCVMRun64;
324
325 /* VT-x 64 bits vmlaunch handler */
326 RTRCPTR pfnVMXGCStartVM64;
327
328 /* RC handler to setup the 64 bits FPU state. */
329 RTRCPTR pfnSaveGuestFPU64;
330
331 /* RC handler to setup the 64 bits debug state. */
332 RTRCPTR pfnSaveGuestDebug64;
333
334 /* Test handler */
335 RTRCPTR pfnTest64;
336
337 RTRCPTR uAlignment[2];
338/*#elif defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
339 uint32_t u32Alignment[1]; */
340#endif
341
342 struct
343 {
344 /** Set by the ring-0 side of HM to indicate VMX is supported by the
345 * CPU. */
346 bool fSupported;
347
348 /** Set when we've enabled VMX. */
349 bool fEnabled;
350
351 /** Set if VPID is supported. */
352 bool fVpid;
353
354 /** Set if VT-x VPID is allowed. */
355 bool fAllowVpid;
356
357 /** Set if unrestricted guest execution is allowed (real and protected mode without paging). */
358 bool fUnrestrictedGuest;
359
360 /** Whether we're using the preemption timer or not. */
361 bool fUsePreemptTimer;
362 /** The shift mask employed by the VMX-Preemption timer. */
363 uint8_t cPreemptTimerShift;
364
365 bool uAlignment[1];
366
367 /** Virtual address of the TSS page used for real mode emulation. */
368 R3PTRTYPE(PVBOXTSS) pRealModeTSS;
369
370 /** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
371 R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
372
373 /** R0 memory object for the APIC-access page. */
374 RTR0MEMOBJ hMemObjApicAccess;
375 /** Physical address of the APIC-access page. */
376 RTHCPHYS HCPhysApicAccess;
377 /** Virtual address of the APIC-access page. */
378 R0PTRTYPE(uint8_t *) pbApicAccess;
379
380#ifdef VBOX_WITH_CRASHDUMP_MAGIC
381 RTR0MEMOBJ hMemObjScratch;
382 RTHCPHYS HCPhysScratch;
383 R0PTRTYPE(uint8_t *) pbScratch;
384#endif
385
386#ifndef VBOX_WITH_OLD_VTX_CODE
387 unsigned uFlushTaggedTlb;
388#else
389 /** Ring 0 handlers for VT-x. */
390 DECLR0CALLBACKMEMBER(void, pfnFlushTaggedTlb, (PVM pVM, PVMCPU pVCpu));
391#endif
392
393#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
394 uint32_t u32Alignment;
395#endif
396 /** Host CR4 value (set by ring-0 VMX init) */
397 uint64_t hostCR4;
398
399 /** Host EFER value (set by ring-0 VMX init) */
400 uint64_t hostEFER;
401
402 /** VMX MSR values */
403 struct
404 {
405 uint64_t feature_ctrl;
406 uint64_t vmx_basic_info;
407 VMX_CAPABILITY vmx_pin_ctls;
408 VMX_CAPABILITY vmx_proc_ctls;
409 VMX_CAPABILITY vmx_proc_ctls2;
410 VMX_CAPABILITY vmx_exit;
411 VMX_CAPABILITY vmx_entry;
412 uint64_t vmx_misc;
413 uint64_t vmx_cr0_fixed0;
414 uint64_t vmx_cr0_fixed1;
415 uint64_t vmx_cr4_fixed0;
416 uint64_t vmx_cr4_fixed1;
417 uint64_t vmx_vmcs_enum;
418 uint64_t vmx_ept_vpid_caps;
419 } msr;
420
421 /** Flush types for invept & invvpid; they depend on capabilities. */
422 VMX_FLUSH_EPT enmFlushEpt;
423 VMX_FLUSH_VPID enmFlushVpid;
424 } vmx;
425
426 struct
427 {
428 /** Set by the ring-0 side of HM to indicate SVM is supported by the
429 * CPU. */
430 bool fSupported;
431 /** Set when we've enabled SVM. */
432 bool fEnabled;
433 /** Set if erratum 170 affects the AMD cpu. */
434 bool fAlwaysFlushTLB;
435 /** Set when the hack to ignore VERR_SVM_IN_USE is active. */
436 bool fIgnoreInUseError;
437
438 /** R0 memory object for the IO bitmap (12kb). */
439 RTR0MEMOBJ hMemObjIOBitmap;
440 /** Physical address of the IO bitmap (12kb). */
441 RTHCPHYS HCPhysIOBitmap;
442 /** Virtual address of the IO bitmap. */
443 R0PTRTYPE(void *) pvIOBitmap;
444
445 /* HWCR MSR (for diagnostics) */
446 uint64_t msrHwcr;
447
448 /** SVM revision. */
449 uint32_t u32Rev;
450
451 /** SVM feature bits from cpuid 0x8000000a */
452 uint32_t u32Features;
453 } svm;
454
455 /**
456 * AVL tree with all patches (active or disabled) sorted by guest instruction address
457 */
458 AVLOU32TREE PatchTree;
459 uint32_t cPatches;
460 HMTPRPATCH aPatches[64];
461
462 struct
463 {
464 uint32_t u32AMDFeatureECX;
465 uint32_t u32AMDFeatureEDX;
466 } cpuid;
467
468 /** Saved error from detection */
469 int32_t lLastError;
470
471 /** HMR0Init was run */
472 bool fHMR0Init;
473 bool u8Alignment1[7];
474
475 STAMCOUNTER StatTprPatchSuccess;
476 STAMCOUNTER StatTprPatchFailure;
477 STAMCOUNTER StatTprReplaceSuccess;
478 STAMCOUNTER StatTprReplaceFailure;
479} HM;
480/** Pointer to HM VM instance data. */
481typedef HM *PHM;
482
483/* Maximum number of cached entries. */
484#define VMCSCACHE_MAX_ENTRY 128
485
486/* Structure for storing read and write VMCS actions. */
487typedef struct VMCSCACHE
488{
489#ifdef VBOX_WITH_CRASHDUMP_MAGIC
490 /* Magic marker for searching in crash dumps. */
491 uint8_t aMagic[16];
492 uint64_t uMagic;
493 uint64_t u64TimeEntry;
494 uint64_t u64TimeSwitch;
495 uint64_t cResume;
496 uint64_t interPD;
497 uint64_t pSwitcher;
498 uint32_t uPos;
499 uint32_t idCpu;
500#endif
501 /* CR2 is saved here for EPT syncing. */
502 uint64_t cr2;
503 struct
504 {
505 uint32_t cValidEntries;
506 uint32_t uAlignment;
507 uint32_t aField[VMCSCACHE_MAX_ENTRY];
508 uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
509 } Write;
510 struct
511 {
512 uint32_t cValidEntries;
513 uint32_t uAlignment;
514 uint32_t aField[VMCSCACHE_MAX_ENTRY];
515 uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
516 } Read;
517#ifdef DEBUG
518 struct
519 {
520 RTHCPHYS HCPhysCpuPage;
521 RTHCPHYS HCPhysVmcs;
522 RTGCPTR pCache;
523 RTGCPTR pCtx;
524 } TestIn;
525 struct
526 {
527 RTHCPHYS HCPhysVmcs;
528 RTGCPTR pCache;
529 RTGCPTR pCtx;
530 uint64_t eflags;
531 uint64_t cr8;
532 } TestOut;
533 struct
534 {
535 uint64_t param1;
536 uint64_t param2;
537 uint64_t param3;
538 uint64_t param4;
539 } ScratchPad;
540#endif
541} VMCSCACHE;
542/** Pointer to VMCSCACHE. */
543typedef VMCSCACHE *PVMCSCACHE;
544
545/** VMX StartVM function. */
546typedef DECLCALLBACK(int) FNHMVMXSTARTVM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);
547/** Pointer to a VMX StartVM function. */
548typedef R0PTRTYPE(FNHMVMXSTARTVM *) PFNHMVMXSTARTVM;
549
550/** SVM VMRun function. */
551typedef DECLCALLBACK(int) FNHMSVMVMRUN(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu);
552/** Pointer to a SVM VMRun function. */
553typedef R0PTRTYPE(FNHMSVMVMRUN *) PFNHMSVMVMRUN;
554
555/**
556 * HM VMCPU Instance data.
557 */
558typedef struct HMCPU
559{
560 /** Old style FPU reporting trap mask override performed (optimization) */
561 bool fFPUOldStyleOverride;
562 /** Set if we don't have to flush the TLB on VM entry. */
563 bool fResumeVM;
564 /** Set if we need to flush the TLB during the world switch. */
565 bool fForceTLBFlush;
566 /** Set when we're using VT-x or AMD-V at that moment. */
567 bool fActive;
568 /** Set when the TLB has been checked until we return from the world switch. */
569 volatile bool fCheckedTLBFlush;
570 uint8_t u8Alignment[3];
571
572 /** World switch exit counter. */
573 volatile uint32_t cWorldSwitchExits;
574 /** HM_CHANGED_* flags. */
575 uint32_t fContextUseFlags;
576 /** Id of the last cpu we were executing code on (NIL_RTCPUID for the first time) */
577 RTCPUID idLastCpu;
578 /** TLB flush count */
579 uint32_t cTlbFlushes;
580 /** Current ASID in use by the VM */
581 uint32_t uCurrentAsid;
582 uint32_t u32Alignment;
583
584 /* Host's TSC_AUX MSR (used when RDTSCP doesn't cause VM-exits). */
585 uint64_t u64HostTscAux;
586
587 struct
588 {
589 /** Physical address of the VM control structure (VMCS). */
590 RTHCPHYS HCPhysVmcs;
591 /** R0 memory object for the VM control structure (VMCS). */
592 RTR0MEMOBJ hMemObjVmcs;
593 /** Virtual address of the VM control structure (VMCS). */
594 R0PTRTYPE(void *) pvVmcs;
595 /** Ring 0 handlers for VT-x. */
596 PFNHMVMXSTARTVM pfnStartVM;
597#if HC_ARCH_BITS == 32
598 uint32_t u32Alignment1;
599#endif
600
601 /** Current VMX_VMCS32_CTRL_PIN_EXEC_CONTROLS. */
602 uint32_t u32PinCtls;
603 /** Current VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS. */
604 uint32_t u32ProcCtls;
605 /** Current VMX_VMCS32_CTRL_PROC_EXEC2_CONTROLS. */
606 uint32_t u32ProcCtls2;
607 /** Current VMX_VMCS32_CTRL_EXIT_CONTROLS. */
608 uint32_t u32ExitCtls;
609 /** Current VMX_VMCS32_CTRL_ENTRY_CONTROLS. */
610 uint32_t u32EntryCtls;
611 /** Physical address of the virtual APIC page for TPR caching. */
612 RTHCPHYS HCPhysVirtApic;
613 /** R0 memory object for the virtual APIC page for TPR caching. */
614 RTR0MEMOBJ hMemObjVirtApic;
615 /** Virtual address of the virtual APIC page for TPR caching. */
616 R0PTRTYPE(uint8_t *) pbVirtApic;
617#if HC_ARCH_BITS == 32
618 uint32_t u32Alignment2;
619#endif
620
621 /** Current CR0 mask. */
622 uint64_t cr0_mask;
623 /** Current CR4 mask. */
624 uint64_t cr4_mask;
625 /** Current exception bitmap. */
626 uint32_t u32XcptBitmap;
627 /** The updated-guest-state mask. */
628 uint32_t fUpdatedGuestState;
629 /** Current EPTP. */
630 RTHCPHYS GCPhysEPTP;
631
632 /** Physical address of the MSR bitmap. */
633 RTHCPHYS HCPhysMsrBitmap;
634 /** R0 memory object for the MSR bitmap. */
635 RTR0MEMOBJ hMemObjMsrBitmap;
636 /** Virtual address of the MSR bitmap. */
637 R0PTRTYPE(void *) pvMsrBitmap;
638
639#ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
640 /** Physical address of the VM-entry MSR-load and VM-exit MSR-store area (used
641 * for guest MSRs). */
642 RTHCPHYS HCPhysGuestMsr;
643 /** R0 memory object of the VM-entry MSR-load and VM-exit MSR-store area
644 * (used for guest MSRs). */
645 RTR0MEMOBJ hMemObjGuestMsr;
646 /** Virtual address of the VM-entry MSR-load and VM-exit MSR-store area (used
647 * for guest MSRs). */
648 R0PTRTYPE(void *) pvGuestMsr;
649
650 /** Physical address of the VM-exit MSR-load area (used for host MSRs). */
651 RTHCPHYS HCPhysHostMsr;
652 /** R0 memory object for the VM-exit MSR-load area (used for host MSRs). */
653 RTR0MEMOBJ hMemObjHostMsr;
654 /** Virtual address of the VM-exit MSR-load area (used for host MSRs). */
655 R0PTRTYPE(void *) pvHostMsr;
656
657 /* Number of automatically loaded/restored guest MSRs during the world switch. */
658 uint32_t cGuestMsrs;
659 uint32_t uAlignment;
660#endif /* VBOX_WITH_AUTO_MSR_LOAD_RESTORE */
661
662 /* The cached APIC-base MSR used for identifying when to map the HC physical APIC-access page. */
663 uint64_t u64MsrApicBase;
664 /* Last use TSC offset value. (cached) */
665 uint64_t u64TSCOffset;
666 /** VMCS cache. */
667 VMCSCACHE VMCSCache;
668
669 /** Real-mode emulation state. */
670 struct
671 {
672 X86DESCATTR uAttrCS;
673 X86DESCATTR uAttrDS;
674 X86DESCATTR uAttrES;
675 X86DESCATTR uAttrFS;
676 X86DESCATTR uAttrGS;
677 X86DESCATTR uAttrSS;
678 X86EFLAGS eflags;
679 uint32_t fRealOnV86Active;
680 } RealMode;
681
682 struct
683 {
684 uint64_t u64VMCSPhys;
685 uint32_t u32VMCSRevision;
686 uint32_t u32InstrError;
687 uint32_t u32ExitReason;
688 RTCPUID idEnteredCpu;
689 RTCPUID idCurrentCpu;
690 uint32_t padding;
691 } lasterror;
692
693 /** The last seen guest paging mode (by VT-x). */
694 PGMMODE enmLastSeenGuestMode;
695 /** Current guest paging mode (as seen by HMR3PagingModeChanged). */
696 PGMMODE enmCurrGuestMode;
697 /** Previous guest paging mode (as seen by HMR3PagingModeChanged). */
698 PGMMODE enmPrevGuestMode;
699 } vmx;
700
701 struct
702 {
703 /** R0 memory object for the host VM control block (VMCB). */
704 RTR0MEMOBJ hMemObjVMCBHost;
705 /** Physical address of the host VM control block (VMCB). */
706 RTHCPHYS HCPhysVMCBHost;
707 /** Virtual address of the host VM control block (VMCB). */
708 R0PTRTYPE(void *) pvVMCBHost;
709
710 /** R0 memory object for the VM control block (VMCB). */
711 RTR0MEMOBJ hMemObjVMCB;
712 /** Physical address of the VM control block (VMCB). */
713 RTHCPHYS HCPhysVMCB;
714 /** Virtual address of the VM control block (VMCB). */
715 R0PTRTYPE(void *) pvVMCB;
716
717 /** Ring 0 handlers for VT-x. */
718 PFNHMSVMVMRUN pfnVMRun;
719
720 /** R0 memory object for the MSR bitmap (8kb). */
721 RTR0MEMOBJ hMemObjMsrBitmap;
722 /** Physical address of the MSR bitmap (8kb). */
723 RTHCPHYS HCPhysMsrBitmap;
724 /** Virtual address of the MSR bitmap. */
725 R0PTRTYPE(void *) pvMsrBitmap;
726 } svm;
727
728 /** Event injection state. */
729 struct
730 {
731 uint32_t fPending;
732 uint32_t u32ErrCode;
733 uint32_t u32InstrLen;
734 uint64_t u64IntrInfo;
735 } Event;
736
737 /** IO Block emulation state. */
738 struct
739 {
740 bool fEnabled;
741 uint8_t u8Align[7];
742
743 /** RIP at the start of the io code we wish to emulate in the recompiler. */
744 RTGCPTR GCPtrFunctionEip;
745
746 uint64_t cr0;
747 } EmulateIoBlock;
748
749 struct
750 {
751 /* Pending IO operation type. */
752 HMPENDINGIO enmType;
753 uint32_t uPadding;
754 RTGCPTR GCPtrRip;
755 RTGCPTR GCPtrRipNext;
756 union
757 {
758 struct
759 {
760 unsigned uPort;
761 unsigned uAndVal;
762 unsigned cbSize;
763 } Port;
764 uint64_t aRaw[2];
765 } s;
766 } PendingIO;
767
768 /** The PAE PDPEs used with Nested Paging (only valid when
769 * VMCPU_FF_HM_UPDATE_PAE_PDPES is set). */
770 X86PDPE aPdpes[4];
771
772 /** Current shadow paging mode. */
773 PGMMODE enmShadowMode;
774
775 /** The CPU ID of the CPU currently owning the VMCS. Set in
776 * HMR0Enter and cleared in HMR0Leave. */
777 RTCPUID idEnteredCpu;
778
779 /** To keep track of pending TLB shootdown pages. (SMP guest only) */
780 struct
781 {
782 RTGCPTR aPages[HM_MAX_TLB_SHOOTDOWN_PAGES];
783 unsigned cPages;
784 } TlbShootdown;
785
786 /** For saving stack space, the disassembler state is allocated here instead of
787 * on the stack. */
788 DISCPUSTATE DisState;
789
790 uint32_t padding2[1];
791
792 STAMPROFILEADV StatEntry;
793 STAMPROFILEADV StatExit1;
794 STAMPROFILEADV StatExit2;
795#ifdef VBOX_WITH_OLD_VTX_CODE /* temporary for tracking down darwin issues. */
796 STAMPROFILEADV StatExit2Sub1;
797 STAMPROFILEADV StatExit2Sub2;
798 STAMPROFILEADV StatExit2Sub3;
799#endif
800 STAMPROFILEADV StatLoadGuestState;
801 STAMPROFILEADV StatInGC;
802
803#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
804 STAMPROFILEADV StatWorldSwitch3264;
805#endif
806 STAMPROFILEADV StatPoke;
807 STAMPROFILEADV StatSpinPoke;
808 STAMPROFILEADV StatSpinPokeFailed;
809
810 STAMCOUNTER StatIntInject;
811
812 STAMCOUNTER StatExitShadowNM;
813 STAMCOUNTER StatExitGuestNM;
814 STAMCOUNTER StatExitShadowPF; /* Misleading, currently used for MMIO #PFs as well. */
815 STAMCOUNTER StatExitShadowPFEM;
816 STAMCOUNTER StatExitGuestPF;
817 STAMCOUNTER StatExitGuestUD;
818 STAMCOUNTER StatExitGuestSS;
819 STAMCOUNTER StatExitGuestNP;
820 STAMCOUNTER StatExitGuestGP;
821 STAMCOUNTER StatExitGuestDE;
822 STAMCOUNTER StatExitGuestDB;
823 STAMCOUNTER StatExitGuestMF;
824 STAMCOUNTER StatExitGuestBP;
825 STAMCOUNTER StatExitGuestXF;
826 STAMCOUNTER StatExitGuestXcpUnk;
827 STAMCOUNTER StatExitInvlpg;
828 STAMCOUNTER StatExitInvd;
829 STAMCOUNTER StatExitWbinvd;
830 STAMCOUNTER StatExitPause;
831 STAMCOUNTER StatExitCpuid;
832 STAMCOUNTER StatExitRdtsc;
833 STAMCOUNTER StatExitRdtscp;
834 STAMCOUNTER StatExitRdpmc;
835 STAMCOUNTER StatExitRdrand;
836 STAMCOUNTER StatExitCli;
837 STAMCOUNTER StatExitSti;
838 STAMCOUNTER StatExitPushf;
839 STAMCOUNTER StatExitPopf;
840 STAMCOUNTER StatExitIret;
841 STAMCOUNTER StatExitInt;
842 STAMCOUNTER StatExitCRxWrite[16];
843 STAMCOUNTER StatExitCRxRead[16];
844 STAMCOUNTER StatExitDRxWrite;
845 STAMCOUNTER StatExitDRxRead;
846 STAMCOUNTER StatExitRdmsr;
847 STAMCOUNTER StatExitWrmsr;
848 STAMCOUNTER StatExitClts;
849 STAMCOUNTER StatExitXdtrAccess;
850 STAMCOUNTER StatExitHlt;
851 STAMCOUNTER StatExitMwait;
852 STAMCOUNTER StatExitMonitor;
853 STAMCOUNTER StatExitLmsw;
854 STAMCOUNTER StatExitIOWrite;
855 STAMCOUNTER StatExitIORead;
856 STAMCOUNTER StatExitIOStringWrite;
857 STAMCOUNTER StatExitIOStringRead;
858 STAMCOUNTER StatExitIntWindow;
859 STAMCOUNTER StatExitMaxResume;
860 STAMCOUNTER StatExitExtInt;
861 STAMCOUNTER StatExitPreemptTimer;
862 STAMCOUNTER StatExitTprBelowThreshold;
863 STAMCOUNTER StatExitTaskSwitch;
864 STAMCOUNTER StatExitMtf;
865 STAMCOUNTER StatExitApicAccess;
866 STAMCOUNTER StatIntReinject;
867 STAMCOUNTER StatPendingHostIrq;
868
869 STAMCOUNTER StatFlushPage;
870 STAMCOUNTER StatFlushPageManual;
871 STAMCOUNTER StatFlushPhysPageManual;
872 STAMCOUNTER StatFlushTlb;
873 STAMCOUNTER StatFlushTlbManual;
874 STAMCOUNTER StatFlushTlbWorldSwitch;
875 STAMCOUNTER StatNoFlushTlbWorldSwitch;
876 STAMCOUNTER StatFlushAsid;
877 STAMCOUNTER StatFlushNestedPaging;
878 STAMCOUNTER StatFlushTlbInvlpgVirt;
879 STAMCOUNTER StatFlushTlbInvlpgPhys;
880 STAMCOUNTER StatTlbShootdown;
881 STAMCOUNTER StatTlbShootdownFlush;
882
883 STAMCOUNTER StatSwitchGuestIrq;
884 STAMCOUNTER StatSwitchHmToR3FF;
885 STAMCOUNTER StatSwitchExitToR3;
886 STAMCOUNTER StatSwitchLongJmpToR3;
887
888 STAMCOUNTER StatTscOffset;
889 STAMCOUNTER StatTscIntercept;
890 STAMCOUNTER StatTscInterceptOverFlow;
891
892 STAMCOUNTER StatExitReasonNpf;
893 STAMCOUNTER StatDRxArmed;
894 STAMCOUNTER StatDRxContextSwitch;
895 STAMCOUNTER StatDRxIoCheck;
896
897 STAMCOUNTER StatLoadMinimal;
898 STAMCOUNTER StatLoadFull;
899
900#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
901 STAMCOUNTER StatFpu64SwitchBack;
902 STAMCOUNTER StatDebug64SwitchBack;
903#endif
904
905#ifdef VBOX_WITH_STATISTICS
906 R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
907 R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
908 R3PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqs;
909 R0PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqsR0;
910#endif
911} HMCPU;
912/** Pointer to HM VM instance data. */
913typedef HMCPU *PHMCPU;
914
915
916#ifdef IN_RING0
917
918VMMR0DECL(PHMGLOBLCPUINFO) HMR0GetCurrentCpu(void);
919VMMR0DECL(PHMGLOBLCPUINFO) HMR0GetCurrentCpuEx(RTCPUID idCpu);
920
921
922#ifdef VBOX_STRICT
923VMMR0DECL(void) HMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
924VMMR0DECL(void) HMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg);
925#else
926# define HMDumpRegs(a, b ,c) do { } while (0)
927# define HMR0DumpDescriptor(a, b, c) do { } while (0)
928#endif
929
930# ifdef VBOX_WITH_KERNEL_USING_XMM
931DECLASM(int) hmR0VMXStartVMWrapXMM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu, PFNHMVMXSTARTVM pfnStartVM);
932DECLASM(int) hmR0SVMRunWrapXMM(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu, PFNHMSVMVMRUN pfnVMRun);
933# endif
934
935# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
936/**
937 * Gets 64-bit GDTR and IDTR on darwin.
938 * @param pGdtr Where to store the 64-bit GDTR.
939 * @param pIdtr Where to store the 64-bit IDTR.
940 */
941DECLASM(void) hmR0Get64bitGdtrAndIdtr(PX86XDTR64 pGdtr, PX86XDTR64 pIdtr);
942
943/**
944 * Gets 64-bit CR3 on darwin.
945 * @returns CR3
946 */
947DECLASM(uint64_t) hmR0Get64bitCR3(void);
948# endif
949
950#endif /* IN_RING0 */
951
952/** @} */
953
954RT_C_DECLS_END
955
956#endif
957
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette