VirtualBox

source: vbox/trunk/src/VBox/VMM/include/HMInternal.h@ 45693

Last change on this file since 45693 was 45684, checked in by vboxsync, 12 years ago

VMM/HMVMXR0: 32-bit fixes, round 2.
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1/* $Id: HMInternal.h 45684 2013-04-23 15:44:47Z vboxsync $ */
2/** @file
3 * HM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef ___HMInternal_h
19#define ___HMInternal_h
20
21#include <VBox/cdefs.h>
22#include <VBox/types.h>
23#include <VBox/vmm/em.h>
24#include <VBox/vmm/stam.h>
25#include <VBox/dis.h>
26#include <VBox/vmm/hm.h>
27#include <VBox/vmm/hm_vmx.h>
28#include <VBox/vmm/pgm.h>
29#include <VBox/vmm/cpum.h>
30#include <iprt/memobj.h>
31#include <iprt/cpuset.h>
32#include <iprt/mp.h>
33#include <iprt/avl.h>
34
35#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL) || defined (VBOX_WITH_64_BITS_GUESTS)
36/* Enable 64 bits guest support. */
37# define VBOX_ENABLE_64_BITS_GUESTS
38#endif
39
40#ifdef VBOX_WITH_OLD_VTX_CODE
41# define VMX_USE_CACHED_VMCS_ACCESSES
42#elif HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
43# define VMX_USE_CACHED_VMCS_ACCESSES
44#endif
45
46/** @def HM_PROFILE_EXIT_DISPATCH
47 * Enables profiling of the VM exit handler dispatching. */
48#if 0
49# define HM_PROFILE_EXIT_DISPATCH
50#endif
51
52/* The MSR auto load/store does not work for KERNEL_GS_BASE MSR, thus we
53 * handle this MSR manually. See @bugref{6208}. This is clearly visible while
54 * booting Solaris 11 (11.1 b19) VMs with 2 Cpus.
55 *
56 * Note: don't forget to update the assembly files while modifying this!
57 */
58# define VBOX_WITH_AUTO_MSR_LOAD_RESTORE
59
60RT_C_DECLS_BEGIN
61
62
63/** @defgroup grp_hm_int Internal
64 * @ingroup grp_hm
65 * @internal
66 * @{
67 */
68
69
70/** Maximum number of exit reason statistics counters. */
71#define MAX_EXITREASON_STAT 0x100
72#define MASK_EXITREASON_STAT 0xff
73#define MASK_INJECT_IRQ_STAT 0xff
74
75/** @name Changed flags
76 * These flags are used to keep track of which important registers that
77 * have been changed since last they were reset.
78 * @{
79 */
80#ifdef VBOX_WITH_OLD_VTX_CODE
81# define HM_CHANGED_GUEST_FPU RT_BIT(0)
82# define HM_CHANGED_GUEST_CR0 RT_BIT(1)
83# define HM_CHANGED_GUEST_CR3 RT_BIT(2)
84# define HM_CHANGED_GUEST_CR4 RT_BIT(3)
85# define HM_CHANGED_GUEST_GDTR RT_BIT(4)
86# define HM_CHANGED_GUEST_IDTR RT_BIT(5)
87# define HM_CHANGED_GUEST_LDTR RT_BIT(6)
88# define HM_CHANGED_GUEST_TR RT_BIT(7)
89# define HM_CHANGED_GUEST_MSR RT_BIT(8)
90# define HM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(9)
91# define HM_CHANGED_GUEST_DEBUG RT_BIT(10)
92# define HM_CHANGED_HOST_CONTEXT RT_BIT(11)
93# define HM_CHANGED_ALL_GUEST ( HM_CHANGED_GUEST_SEGMENT_REGS \
94 | HM_CHANGED_GUEST_CR0 \
95 | HM_CHANGED_GUEST_CR3 \
96 | HM_CHANGED_GUEST_CR4 \
97 | HM_CHANGED_GUEST_GDTR \
98 | HM_CHANGED_GUEST_IDTR \
99 | HM_CHANGED_GUEST_LDTR \
100 | HM_CHANGED_GUEST_TR \
101 | HM_CHANGED_GUEST_MSR \
102 | HM_CHANGED_GUEST_DEBUG \
103 | HM_CHANGED_GUEST_FPU)
104#else
105# define HM_CHANGED_GUEST_RIP RT_BIT(0)
106# define HM_CHANGED_GUEST_RSP RT_BIT(1)
107# define HM_CHANGED_GUEST_RFLAGS RT_BIT(2)
108# define HM_CHANGED_GUEST_CR0 RT_BIT(3)
109# define HM_CHANGED_GUEST_CR3 RT_BIT(4)
110# define HM_CHANGED_GUEST_CR4 RT_BIT(5)
111# define HM_CHANGED_GUEST_GDTR RT_BIT(6)
112# define HM_CHANGED_GUEST_IDTR RT_BIT(7)
113# define HM_CHANGED_GUEST_LDTR RT_BIT(8)
114# define HM_CHANGED_GUEST_TR RT_BIT(9)
115# define HM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(10)
116# define HM_CHANGED_GUEST_DEBUG RT_BIT(11)
117# define HM_CHANGED_GUEST_SYSENTER_CS_MSR RT_BIT(12)
118# define HM_CHANGED_GUEST_SYSENTER_EIP_MSR RT_BIT(13)
119# define HM_CHANGED_GUEST_SYSENTER_ESP_MSR RT_BIT(14)
120# define HM_CHANGED_VMX_GUEST_AUTO_MSRS RT_BIT(15)
121# define HM_CHANGED_VMX_GUEST_ACTIVITY_STATE RT_BIT(16)
122# define HM_CHANGED_VMX_GUEST_APIC_STATE RT_BIT(17)
123# define HM_CHANGED_VMX_ENTRY_CTLS RT_BIT(18)
124# define HM_CHANGED_VMX_EXIT_CTLS RT_BIT(19)
125
126# define HM_CHANGED_HOST_CONTEXT RT_BIT(20)
127
128# define HM_CHANGED_ALL_GUEST ( HM_CHANGED_GUEST_RIP \
129 | HM_CHANGED_GUEST_RSP \
130 | HM_CHANGED_GUEST_RFLAGS \
131 | HM_CHANGED_GUEST_CR0 \
132 | HM_CHANGED_GUEST_CR3 \
133 | HM_CHANGED_GUEST_CR4 \
134 | HM_CHANGED_GUEST_GDTR \
135 | HM_CHANGED_GUEST_IDTR \
136 | HM_CHANGED_GUEST_LDTR \
137 | HM_CHANGED_GUEST_TR \
138 | HM_CHANGED_GUEST_SEGMENT_REGS \
139 | HM_CHANGED_GUEST_DEBUG \
140 | HM_CHANGED_GUEST_SYSENTER_CS_MSR \
141 | HM_CHANGED_GUEST_SYSENTER_EIP_MSR \
142 | HM_CHANGED_GUEST_SYSENTER_ESP_MSR \
143 | HM_CHANGED_VMX_GUEST_AUTO_MSRS \
144 | HM_CHANGED_VMX_GUEST_ACTIVITY_STATE \
145 | HM_CHANGED_VMX_GUEST_APIC_STATE \
146 | HM_CHANGED_VMX_ENTRY_CTLS \
147 | HM_CHANGED_VMX_EXIT_CTLS)
148#endif
149
150#define HM_CHANGED_ALL (HM_CHANGED_ALL_GUEST | HM_CHANGED_HOST_CONTEXT)
151/** @} */
152
153/** Maximum number of page flushes we are willing to remember before considering a full TLB flush. */
154#define HM_MAX_TLB_SHOOTDOWN_PAGES 8
155
156/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
157#define HM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
158/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
159#define HM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2 * PAGE_SIZE + 1)
160/** Total guest mapped memory needed. */
161#define HM_VTX_TOTAL_DEVHEAP_MEM (HM_EPT_IDENTITY_PG_TABLE_SIZE + HM_VTX_TSS_SIZE)
162
163/** Enable for TPR guest patching. */
164#define VBOX_HM_WITH_GUEST_PATCHING
165
166/** HM SSM version
167 */
168#ifdef VBOX_HM_WITH_GUEST_PATCHING
169# define HM_SSM_VERSION 5
170# define HM_SSM_VERSION_NO_PATCHING 4
171#else
172# define HM_SSM_VERSION 4
173# define HM_SSM_VERSION_NO_PATCHING 4
174#endif
175#define HM_SSM_VERSION_2_0_X 3
176
177/**
178 * Global per-cpu information. (host)
179 */
180typedef struct HMGLOBLCPUINFO
181{
182 /** The CPU ID. */
183 RTCPUID idCpu;
184 /** The memory object */
185 RTR0MEMOBJ hMemObj;
186 /** Current ASID (AMD-V) / VPID (Intel). */
187 uint32_t uCurrentAsid;
188 /** TLB flush count. */
189 uint32_t cTlbFlushes;
190 /** Whether to flush each new ASID/VPID before use. */
191 bool fFlushAsidBeforeUse;
192 /** Configured for VT-x or AMD-V. */
193 bool fConfigured;
194 /** Set if the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active. */
195 bool fIgnoreAMDVInUseError;
196 /** In use by our code. (for power suspend) */
197 volatile bool fInUse;
198} HMGLOBLCPUINFO;
199/** Pointer to the per-cpu global information. */
200typedef HMGLOBLCPUINFO *PHMGLOBLCPUINFO;
201
202typedef enum
203{
204 HMPENDINGIO_INVALID = 0,
205 HMPENDINGIO_PORT_READ,
206 HMPENDINGIO_PORT_WRITE,
207 HMPENDINGIO_STRING_READ,
208 HMPENDINGIO_STRING_WRITE,
209 /** The usual 32-bit paranoia. */
210 HMPENDINGIO_32BIT_HACK = 0x7fffffff
211} HMPENDINGIO;
212
213
214typedef enum
215{
216 HMTPRINSTR_INVALID,
217 HMTPRINSTR_READ,
218 HMTPRINSTR_READ_SHR4,
219 HMTPRINSTR_WRITE_REG,
220 HMTPRINSTR_WRITE_IMM,
221 HMTPRINSTR_JUMP_REPLACEMENT,
222 /** The usual 32-bit paranoia. */
223 HMTPRINSTR_32BIT_HACK = 0x7fffffff
224} HMTPRINSTR;
225
226typedef struct
227{
228 /** The key is the address of patched instruction. (32 bits GC ptr) */
229 AVLOU32NODECORE Core;
230 /** Original opcode. */
231 uint8_t aOpcode[16];
232 /** Instruction size. */
233 uint32_t cbOp;
234 /** Replacement opcode. */
235 uint8_t aNewOpcode[16];
236 /** Replacement instruction size. */
237 uint32_t cbNewOp;
238 /** Instruction type. */
239 HMTPRINSTR enmType;
240 /** Source operand. */
241 uint32_t uSrcOperand;
242 /** Destination operand. */
243 uint32_t uDstOperand;
244 /** Number of times the instruction caused a fault. */
245 uint32_t cFaults;
246 /** Patch address of the jump replacement. */
247 RTGCPTR32 pJumpTarget;
248} HMTPRPATCH;
249/** Pointer to HMTPRPATCH. */
250typedef HMTPRPATCH *PHMTPRPATCH;
251
252/**
253 * Switcher function, HC to RC.
254 *
255 * @param pVM Pointer to the VM.
256 * @param uOffsetVMCPU VMCPU offset from pVM
257 * @returns Return code indicating the action to take.
258 */
259typedef DECLCALLBACK (int) FNHMSWITCHERHC(PVM pVM, uint32_t uOffsetVMCPU);
260/** Pointer to switcher function. */
261typedef FNHMSWITCHERHC *PFNHMSWITCHERHC;
262
263/**
264 * HM VM Instance data.
265 * Changes to this must checked against the padding of the hm union in VM!
266 */
267typedef struct HM
268{
269 /** Set when we've initialized VMX or SVM. */
270 bool fInitialized;
271
272 /** Set if nested paging is enabled. */
273 bool fNestedPaging;
274
275 /** Set if nested paging is allowed. */
276 bool fAllowNestedPaging;
277
278 /** Set if large pages are enabled (requires nested paging). */
279 bool fLargePages;
280
281 /** Set if we can support 64-bit guests or not. */
282 bool fAllow64BitGuests;
283
284 /** Set if an IO-APIC is configured for this VM. */
285 bool fHasIoApic;
286
287 /** Set when TPR patching is allowed. */
288 bool fTRPPatchingAllowed;
289
290 /** Set when we initialize VT-x or AMD-V once for all CPUs. */
291 bool fGlobalInit;
292
293 /** Set when TPR patching is active. */
294 bool fTPRPatchingActive;
295 bool u8Alignment[7];
296
297 /** And mask for copying register contents. */
298 uint64_t u64RegisterMask;
299
300 /** Maximum ASID allowed. */
301 uint32_t uMaxAsid;
302
303 /** The maximum number of resumes loops allowed in ring-0 (safety precaution).
304 * This number is set much higher when RTThreadPreemptIsPending is reliable. */
305 uint32_t cMaxResumeLoops;
306
307 /** Guest allocated memory for patching purposes. */
308 RTGCPTR pGuestPatchMem;
309 /** Current free pointer inside the patch block. */
310 RTGCPTR pFreeGuestPatchMem;
311 /** Size of the guest patch memory block. */
312 uint32_t cbGuestPatchMem;
313 uint32_t uPadding1;
314
315#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
316 /** 32 to 64 bits switcher entrypoint. */
317 R0PTRTYPE(PFNHMSWITCHERHC) pfnHost32ToGuest64R0;
318
319 /* AMD-V 64 bits vmrun handler */
320 RTRCPTR pfnSVMGCVMRun64;
321
322 /* VT-x 64 bits vmlaunch handler */
323 RTRCPTR pfnVMXGCStartVM64;
324
325 /* RC handler to setup the 64 bits FPU state. */
326 RTRCPTR pfnSaveGuestFPU64;
327
328 /* RC handler to setup the 64 bits debug state. */
329 RTRCPTR pfnSaveGuestDebug64;
330
331 /* Test handler */
332 RTRCPTR pfnTest64;
333
334 RTRCPTR uAlignment[2];
335/*#elif defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
336 uint32_t u32Alignment[1]; */
337#endif
338
339 struct
340 {
341 /** Set by the ring-0 side of HM to indicate VMX is supported by the
342 * CPU. */
343 bool fSupported;
344
345 /** Set when we've enabled VMX. */
346 bool fEnabled;
347
348 /** Set if VPID is supported. */
349 bool fVpid;
350
351 /** Set if VT-x VPID is allowed. */
352 bool fAllowVpid;
353
354 /** Set if unrestricted guest execution is allowed (real and protected mode without paging). */
355 bool fUnrestrictedGuest;
356
357 /** Whether we're using the preemption timer or not. */
358 bool fUsePreemptTimer;
359 /** The shift mask employed by the VMX-Preemption timer. */
360 uint8_t cPreemptTimerShift;
361
362 bool uAlignment[1];
363
364 /** Virtual address of the TSS page used for real mode emulation. */
365 R3PTRTYPE(PVBOXTSS) pRealModeTSS;
366
367 /** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
368 R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
369
370 /** R0 memory object for the APIC-access page. */
371 RTR0MEMOBJ hMemObjApicAccess;
372 /** Physical address of the APIC-access page. */
373 RTHCPHYS HCPhysApicAccess;
374 /** Virtual address of the APIC-access page. */
375 R0PTRTYPE(uint8_t *) pbApicAccess;
376
377#ifdef VBOX_WITH_CRASHDUMP_MAGIC
378 RTR0MEMOBJ hMemObjScratch;
379 RTHCPHYS HCPhysScratch;
380 R0PTRTYPE(uint8_t *) pbScratch;
381#endif
382
383#ifndef VBOX_WITH_OLD_VTX_CODE
384 unsigned uFlushTaggedTlb;
385#else
386 /** Ring 0 handlers for VT-x. */
387 DECLR0CALLBACKMEMBER(void, pfnFlushTaggedTlb, (PVM pVM, PVMCPU pVCpu));
388#endif
389
390#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
391 uint32_t u32Alignment;
392#endif
393 /** Host CR4 value (set by ring-0 VMX init) */
394 uint64_t hostCR4;
395
396 /** Host EFER value (set by ring-0 VMX init) */
397 uint64_t hostEFER;
398
399 /** VMX MSR values */
400 struct
401 {
402 uint64_t feature_ctrl;
403 uint64_t vmx_basic_info;
404 VMX_CAPABILITY vmx_pin_ctls;
405 VMX_CAPABILITY vmx_proc_ctls;
406 VMX_CAPABILITY vmx_proc_ctls2;
407 VMX_CAPABILITY vmx_exit;
408 VMX_CAPABILITY vmx_entry;
409 uint64_t vmx_misc;
410 uint64_t vmx_cr0_fixed0;
411 uint64_t vmx_cr0_fixed1;
412 uint64_t vmx_cr4_fixed0;
413 uint64_t vmx_cr4_fixed1;
414 uint64_t vmx_vmcs_enum;
415 uint64_t vmx_ept_vpid_caps;
416 } msr;
417
418 /** Flush types for invept & invvpid; they depend on capabilities. */
419 VMX_FLUSH_EPT enmFlushEpt;
420 VMX_FLUSH_VPID enmFlushVpid;
421 } vmx;
422
423 struct
424 {
425 /** Set by the ring-0 side of HM to indicate SVM is supported by the
426 * CPU. */
427 bool fSupported;
428 /** Set when we've enabled SVM. */
429 bool fEnabled;
430 /** Set if erratum 170 affects the AMD cpu. */
431 bool fAlwaysFlushTLB;
432 /** Set when the hack to ignore VERR_SVM_IN_USE is active. */
433 bool fIgnoreInUseError;
434
435 /** R0 memory object for the IO bitmap (12kb). */
436 RTR0MEMOBJ hMemObjIOBitmap;
437 /** Physical address of the IO bitmap (12kb). */
438 RTHCPHYS HCPhysIOBitmap;
439 /** Virtual address of the IO bitmap. */
440 R0PTRTYPE(void *) pvIOBitmap;
441
442 /* HWCR MSR (for diagnostics) */
443 uint64_t msrHwcr;
444
445 /** SVM revision. */
446 uint32_t u32Rev;
447
448 /** SVM feature bits from cpuid 0x8000000a */
449 uint32_t u32Features;
450 } svm;
451
452 /**
453 * AVL tree with all patches (active or disabled) sorted by guest instruction address
454 */
455 AVLOU32TREE PatchTree;
456 uint32_t cPatches;
457 HMTPRPATCH aPatches[64];
458
459 struct
460 {
461 uint32_t u32AMDFeatureECX;
462 uint32_t u32AMDFeatureEDX;
463 } cpuid;
464
465 /** Saved error from detection */
466 int32_t lLastError;
467
468 /** HMR0Init was run */
469 bool fHMR0Init;
470 bool u8Alignment1[7];
471
472 STAMCOUNTER StatTprPatchSuccess;
473 STAMCOUNTER StatTprPatchFailure;
474 STAMCOUNTER StatTprReplaceSuccess;
475 STAMCOUNTER StatTprReplaceFailure;
476} HM;
477/** Pointer to HM VM instance data. */
478typedef HM *PHM;
479
480/* Maximum number of cached entries. */
481#define VMCSCACHE_MAX_ENTRY 128
482
483/* Structure for storing read and write VMCS actions. */
484typedef struct VMCSCACHE
485{
486#ifdef VBOX_WITH_CRASHDUMP_MAGIC
487 /* Magic marker for searching in crash dumps. */
488 uint8_t aMagic[16];
489 uint64_t uMagic;
490 uint64_t u64TimeEntry;
491 uint64_t u64TimeSwitch;
492 uint64_t cResume;
493 uint64_t interPD;
494 uint64_t pSwitcher;
495 uint32_t uPos;
496 uint32_t idCpu;
497#endif
498 /* CR2 is saved here for EPT syncing. */
499 uint64_t cr2;
500 struct
501 {
502 uint32_t cValidEntries;
503 uint32_t uAlignment;
504 uint32_t aField[VMCSCACHE_MAX_ENTRY];
505 uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
506 } Write;
507 struct
508 {
509 uint32_t cValidEntries;
510 uint32_t uAlignment;
511 uint32_t aField[VMCSCACHE_MAX_ENTRY];
512 uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
513 } Read;
514#ifdef DEBUG
515 struct
516 {
517 RTHCPHYS HCPhysCpuPage;
518 RTHCPHYS HCPhysVmcs;
519 RTGCPTR pCache;
520 RTGCPTR pCtx;
521 } TestIn;
522 struct
523 {
524 RTHCPHYS HCPhysVmcs;
525 RTGCPTR pCache;
526 RTGCPTR pCtx;
527 uint64_t eflags;
528 uint64_t cr8;
529 } TestOut;
530 struct
531 {
532 uint64_t param1;
533 uint64_t param2;
534 uint64_t param3;
535 uint64_t param4;
536 } ScratchPad;
537#endif
538} VMCSCACHE;
539/** Pointer to VMCSCACHE. */
540typedef VMCSCACHE *PVMCSCACHE;
541
542/** VMX StartVM function. */
543typedef DECLCALLBACK(int) FNHMVMXSTARTVM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);
544/** Pointer to a VMX StartVM function. */
545typedef R0PTRTYPE(FNHMVMXSTARTVM *) PFNHMVMXSTARTVM;
546
547/** SVM VMRun function. */
548typedef DECLCALLBACK(int) FNHMSVMVMRUN(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu);
549/** Pointer to a SVM VMRun function. */
550typedef R0PTRTYPE(FNHMSVMVMRUN *) PFNHMSVMVMRUN;
551
552/**
553 * HM VMCPU Instance data.
554 */
555typedef struct HMCPU
556{
557 /** Old style FPU reporting trap mask override performed (optimization) */
558 bool fFPUOldStyleOverride;
559 /** Set if we don't have to flush the TLB on VM entry. */
560 bool fResumeVM;
561 /** Set if we need to flush the TLB during the world switch. */
562 bool fForceTLBFlush;
563 /** Set when we're using VT-x or AMD-V at that moment. */
564 bool fActive;
565 /** Set when the TLB has been checked until we return from the world switch. */
566 volatile bool fCheckedTLBFlush;
567 uint8_t u8Alignment[3];
568
569 /** World switch exit counter. */
570 volatile uint32_t cWorldSwitchExits;
571 /** HM_CHANGED_* flags. */
572 uint32_t fContextUseFlags;
573 /** Id of the last cpu we were executing code on (NIL_RTCPUID for the first time) */
574 RTCPUID idLastCpu;
575 /** TLB flush count */
576 uint32_t cTlbFlushes;
577 /** Current ASID in use by the VM */
578 uint32_t uCurrentAsid;
579 uint32_t u32Alignment;
580
581 /** Host's TSC_AUX MSR (used when RDTSCP doesn't cause VM-exits). */
582 uint64_t u64HostTscAux;
583
584 struct
585 {
586 /** Physical address of the VM control structure (VMCS). */
587 RTHCPHYS HCPhysVmcs;
588 /** R0 memory object for the VM control structure (VMCS). */
589 RTR0MEMOBJ hMemObjVmcs;
590 /** Virtual address of the VM control structure (VMCS). */
591 R0PTRTYPE(void *) pvVmcs;
592 /** Ring 0 handlers for VT-x. */
593 PFNHMVMXSTARTVM pfnStartVM;
594#if HC_ARCH_BITS == 32
595 uint32_t u32Alignment1;
596#endif
597
598 /** Current VMX_VMCS32_CTRL_PIN_EXEC_CONTROLS. */
599 uint32_t u32PinCtls;
600 /** Current VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS. */
601 uint32_t u32ProcCtls;
602 /** Current VMX_VMCS32_CTRL_PROC_EXEC2_CONTROLS. */
603 uint32_t u32ProcCtls2;
604 /** Current VMX_VMCS32_CTRL_EXIT_CONTROLS. */
605 uint32_t u32ExitCtls;
606 /** Current VMX_VMCS32_CTRL_ENTRY_CONTROLS. */
607 uint32_t u32EntryCtls;
608 /** Physical address of the virtual APIC page for TPR caching. */
609 RTHCPHYS HCPhysVirtApic;
610 /** R0 memory object for the virtual APIC page for TPR caching. */
611 RTR0MEMOBJ hMemObjVirtApic;
612 /** Virtual address of the virtual APIC page for TPR caching. */
613 R0PTRTYPE(uint8_t *) pbVirtApic;
614#if HC_ARCH_BITS == 32
615 uint32_t u32Alignment2;
616#endif
617
618 /** Current CR0 mask. */
619 uint64_t cr0_mask;
620 /** Current CR4 mask. */
621 uint64_t cr4_mask;
622 /** Current exception bitmap. */
623 uint32_t u32XcptBitmap;
624 /** The updated-guest-state mask. */
625 uint32_t fUpdatedGuestState;
626 /** Current EPTP. */
627 RTHCPHYS HCPhysEPTP;
628
629 /** Physical address of the MSR bitmap. */
630 RTHCPHYS HCPhysMsrBitmap;
631 /** R0 memory object for the MSR bitmap. */
632 RTR0MEMOBJ hMemObjMsrBitmap;
633 /** Virtual address of the MSR bitmap. */
634 R0PTRTYPE(void *) pvMsrBitmap;
635
636#ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
637 /** Physical address of the VM-entry MSR-load and VM-exit MSR-store area (used
638 * for guest MSRs). */
639 RTHCPHYS HCPhysGuestMsr;
640 /** R0 memory object of the VM-entry MSR-load and VM-exit MSR-store area
641 * (used for guest MSRs). */
642 RTR0MEMOBJ hMemObjGuestMsr;
643 /** Virtual address of the VM-entry MSR-load and VM-exit MSR-store area (used
644 * for guest MSRs). */
645 R0PTRTYPE(void *) pvGuestMsr;
646
647 /** Physical address of the VM-exit MSR-load area (used for host MSRs). */
648 RTHCPHYS HCPhysHostMsr;
649 /** R0 memory object for the VM-exit MSR-load area (used for host MSRs). */
650 RTR0MEMOBJ hMemObjHostMsr;
651 /** Virtual address of the VM-exit MSR-load area (used for host MSRs). */
652 R0PTRTYPE(void *) pvHostMsr;
653
654 /** Number of automatically loaded/restored guest MSRs during the world switch. */
655 uint32_t cGuestMsrs;
656 uint32_t uAlignment;
657#endif /* VBOX_WITH_AUTO_MSR_LOAD_RESTORE */
658
659 /** The cached APIC-base MSR used for identifying when to map the HC physical APIC-access page. */
660 uint64_t u64MsrApicBase;
661 /** Last use TSC offset value. (cached) */
662 uint64_t u64TSCOffset;
663 /** VMCS cache. */
664 VMCSCACHE VMCSCache;
665
666 /** Real-mode emulation state. */
667 struct
668 {
669 X86DESCATTR uAttrCS;
670 X86DESCATTR uAttrDS;
671 X86DESCATTR uAttrES;
672 X86DESCATTR uAttrFS;
673 X86DESCATTR uAttrGS;
674 X86DESCATTR uAttrSS;
675 X86EFLAGS eflags;
676 uint32_t fRealOnV86Active;
677 } RealMode;
678
679 struct
680 {
681 uint64_t u64VMCSPhys;
682 uint32_t u32VMCSRevision;
683 uint32_t u32InstrError;
684 uint32_t u32ExitReason;
685 RTCPUID idEnteredCpu;
686 RTCPUID idCurrentCpu;
687 uint32_t padding;
688 } lasterror;
689
690 /** The last seen guest paging mode (by VT-x). */
691 PGMMODE enmLastSeenGuestMode;
692 /** Current guest paging mode (as seen by HMR3PagingModeChanged). */
693 PGMMODE enmCurrGuestMode;
694 /** Previous guest paging mode (as seen by HMR3PagingModeChanged). */
695 PGMMODE enmPrevGuestMode;
696 } vmx;
697
698 struct
699 {
700 /** R0 memory object for the host VM control block (VMCB). */
701 RTR0MEMOBJ hMemObjVMCBHost;
702 /** Physical address of the host VM control block (VMCB). */
703 RTHCPHYS HCPhysVMCBHost;
704 /** Virtual address of the host VM control block (VMCB). */
705 R0PTRTYPE(void *) pvVMCBHost;
706
707 /** R0 memory object for the VM control block (VMCB). */
708 RTR0MEMOBJ hMemObjVMCB;
709 /** Physical address of the VM control block (VMCB). */
710 RTHCPHYS HCPhysVMCB;
711 /** Virtual address of the VM control block (VMCB). */
712 R0PTRTYPE(void *) pvVMCB;
713
714 /** Ring 0 handlers for VT-x. */
715 PFNHMSVMVMRUN pfnVMRun;
716
717 /** R0 memory object for the MSR bitmap (8kb). */
718 RTR0MEMOBJ hMemObjMsrBitmap;
719 /** Physical address of the MSR bitmap (8kb). */
720 RTHCPHYS HCPhysMsrBitmap;
721 /** Virtual address of the MSR bitmap. */
722 R0PTRTYPE(void *) pvMsrBitmap;
723 } svm;
724
725 /** Event injection state. */
726 struct
727 {
728 uint32_t fPending;
729 uint32_t u32ErrCode;
730 uint32_t cbInstr;
731 uint32_t u32Padding; /**< Explicit alignment padding. */
732 uint64_t u64IntrInfo;
733 RTGCUINTPTR GCPtrFaultAddress;
734 } Event;
735
736 /** IO Block emulation state. */
737 struct
738 {
739 bool fEnabled;
740 uint8_t u8Align[7];
741
742 /** RIP at the start of the io code we wish to emulate in the recompiler. */
743 RTGCPTR GCPtrFunctionEip;
744
745 uint64_t cr0;
746 } EmulateIoBlock;
747
748 struct
749 {
750 /** Pending IO operation type. */
751 HMPENDINGIO enmType;
752 uint32_t uPadding;
753 RTGCPTR GCPtrRip;
754 RTGCPTR GCPtrRipNext;
755 union
756 {
757 struct
758 {
759 uint32_t uPort;
760 uint32_t uAndVal;
761 uint32_t cbSize;
762 } Port;
763 uint64_t aRaw[2];
764 } s;
765 } PendingIO;
766
767 /** The PAE PDPEs used with Nested Paging (only valid when
768 * VMCPU_FF_HM_UPDATE_PAE_PDPES is set). */
769 X86PDPE aPdpes[4];
770
771 /** Current shadow paging mode. */
772 PGMMODE enmShadowMode;
773
774 /** The CPU ID of the CPU currently owning the VMCS. Set in
775 * HMR0Enter and cleared in HMR0Leave. */
776 RTCPUID idEnteredCpu;
777
778 /** To keep track of pending TLB shootdown pages. (SMP guest only) */
779 struct
780 {
781 RTGCPTR aPages[HM_MAX_TLB_SHOOTDOWN_PAGES];
782 uint32_t cPages;
783 uint32_t u32Padding; /**< Explicit alignment padding. */
784 } TlbShootdown;
785
786 /** For saving stack space, the disassembler state is allocated here instead of
787 * on the stack. */
788 DISCPUSTATE DisState;
789
790 STAMPROFILEADV StatEntry;
791 STAMPROFILEADV StatExit1;
792 STAMPROFILEADV StatExit2;
793 STAMPROFILEADV StatExitIO;
794 STAMPROFILEADV StatExitMovCRx;
795 STAMPROFILEADV StatExitXcptNmi;
796 STAMPROFILEADV StatLoadGuestState;
797 STAMPROFILEADV StatInGC;
798
799#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
800 STAMPROFILEADV StatWorldSwitch3264;
801#endif
802 STAMPROFILEADV StatPoke;
803 STAMPROFILEADV StatSpinPoke;
804 STAMPROFILEADV StatSpinPokeFailed;
805
806 STAMCOUNTER StatIntInject;
807
808 STAMCOUNTER StatExitShadowNM;
809 STAMCOUNTER StatExitGuestNM;
810 STAMCOUNTER StatExitShadowPF; /* Misleading, currently used for MMIO #PFs as well. */
811 STAMCOUNTER StatExitShadowPFEM;
812 STAMCOUNTER StatExitGuestPF;
813 STAMCOUNTER StatExitGuestUD;
814 STAMCOUNTER StatExitGuestSS;
815 STAMCOUNTER StatExitGuestNP;
816 STAMCOUNTER StatExitGuestGP;
817 STAMCOUNTER StatExitGuestDE;
818 STAMCOUNTER StatExitGuestDB;
819 STAMCOUNTER StatExitGuestMF;
820 STAMCOUNTER StatExitGuestBP;
821 STAMCOUNTER StatExitGuestXF;
822 STAMCOUNTER StatExitGuestXcpUnk;
823 STAMCOUNTER StatExitInvlpg;
824 STAMCOUNTER StatExitInvd;
825 STAMCOUNTER StatExitWbinvd;
826 STAMCOUNTER StatExitPause;
827 STAMCOUNTER StatExitCpuid;
828 STAMCOUNTER StatExitRdtsc;
829 STAMCOUNTER StatExitRdtscp;
830 STAMCOUNTER StatExitRdpmc;
831 STAMCOUNTER StatExitRdrand;
832 STAMCOUNTER StatExitCli;
833 STAMCOUNTER StatExitSti;
834 STAMCOUNTER StatExitPushf;
835 STAMCOUNTER StatExitPopf;
836 STAMCOUNTER StatExitIret;
837 STAMCOUNTER StatExitInt;
838 STAMCOUNTER StatExitCRxWrite[16];
839 STAMCOUNTER StatExitCRxRead[16];
840 STAMCOUNTER StatExitDRxWrite;
841 STAMCOUNTER StatExitDRxRead;
842 STAMCOUNTER StatExitRdmsr;
843 STAMCOUNTER StatExitWrmsr;
844 STAMCOUNTER StatExitClts;
845 STAMCOUNTER StatExitXdtrAccess;
846 STAMCOUNTER StatExitHlt;
847 STAMCOUNTER StatExitMwait;
848 STAMCOUNTER StatExitMonitor;
849 STAMCOUNTER StatExitLmsw;
850 STAMCOUNTER StatExitIOWrite;
851 STAMCOUNTER StatExitIORead;
852 STAMCOUNTER StatExitIOStringWrite;
853 STAMCOUNTER StatExitIOStringRead;
854 STAMCOUNTER StatExitIntWindow;
855 STAMCOUNTER StatExitMaxResume;
856 STAMCOUNTER StatExitExtInt;
857 STAMCOUNTER StatExitPreemptTimer;
858 STAMCOUNTER StatExitTprBelowThreshold;
859 STAMCOUNTER StatExitTaskSwitch;
860 STAMCOUNTER StatExitMtf;
861 STAMCOUNTER StatExitApicAccess;
862 STAMCOUNTER StatIntReinject;
863 STAMCOUNTER StatPendingHostIrq;
864
865 STAMCOUNTER StatFlushPage;
866 STAMCOUNTER StatFlushPageManual;
867 STAMCOUNTER StatFlushPhysPageManual;
868 STAMCOUNTER StatFlushTlb;
869 STAMCOUNTER StatFlushTlbManual;
870 STAMCOUNTER StatFlushTlbWorldSwitch;
871 STAMCOUNTER StatNoFlushTlbWorldSwitch;
872 STAMCOUNTER StatFlushAsid;
873 STAMCOUNTER StatFlushNestedPaging;
874 STAMCOUNTER StatFlushTlbInvlpgVirt;
875 STAMCOUNTER StatFlushTlbInvlpgPhys;
876 STAMCOUNTER StatTlbShootdown;
877 STAMCOUNTER StatTlbShootdownFlush;
878
879 STAMCOUNTER StatSwitchGuestIrq;
880 STAMCOUNTER StatSwitchHmToR3FF;
881 STAMCOUNTER StatSwitchExitToR3;
882 STAMCOUNTER StatSwitchLongJmpToR3;
883
884 STAMCOUNTER StatTscOffset;
885 STAMCOUNTER StatTscIntercept;
886 STAMCOUNTER StatTscInterceptOverFlow;
887
888 STAMCOUNTER StatExitReasonNpf;
889 STAMCOUNTER StatDRxArmed;
890 STAMCOUNTER StatDRxContextSwitch;
891 STAMCOUNTER StatDRxIoCheck;
892
893 STAMCOUNTER StatLoadMinimal;
894 STAMCOUNTER StatLoadFull;
895
896#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
897 STAMCOUNTER StatFpu64SwitchBack;
898 STAMCOUNTER StatDebug64SwitchBack;
899#endif
900
901#ifdef VBOX_WITH_STATISTICS
902 R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
903 R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
904 R3PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqs;
905 R0PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqsR0;
906#endif
907#ifdef HM_PROFILE_EXIT_DISPATCH
908 STAMPROFILEADV StatExitDispatch;
909#endif
910} HMCPU;
911/** Pointer to HM VM instance data. */
912typedef HMCPU *PHMCPU;
913
914
915#ifdef IN_RING0
916
917VMMR0DECL(PHMGLOBLCPUINFO) HMR0GetCurrentCpu(void);
918VMMR0DECL(PHMGLOBLCPUINFO) HMR0GetCurrentCpuEx(RTCPUID idCpu);
919
920
921#ifdef VBOX_STRICT
922VMMR0DECL(void) HMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
923VMMR0DECL(void) HMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg);
924#else
925# define HMDumpRegs(a, b ,c) do { } while (0)
926# define HMR0DumpDescriptor(a, b, c) do { } while (0)
927#endif
928
929# ifdef VBOX_WITH_KERNEL_USING_XMM
930DECLASM(int) hmR0VMXStartVMWrapXMM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu, PFNHMVMXSTARTVM pfnStartVM);
931DECLASM(int) hmR0SVMRunWrapXMM(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu, PFNHMSVMVMRUN pfnVMRun);
932# endif
933
934# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
935/**
936 * Gets 64-bit GDTR and IDTR on darwin.
937 * @param pGdtr Where to store the 64-bit GDTR.
938 * @param pIdtr Where to store the 64-bit IDTR.
939 */
940DECLASM(void) hmR0Get64bitGdtrAndIdtr(PX86XDTR64 pGdtr, PX86XDTR64 pIdtr);
941
942/**
943 * Gets 64-bit CR3 on darwin.
944 * @returns CR3
945 */
946DECLASM(uint64_t) hmR0Get64bitCR3(void);
947# endif
948
949#endif /* IN_RING0 */
950
951/** @} */
952
953RT_C_DECLS_END
954
955#endif
956
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