1 | /* $Id: HMInternal.h 49755 2013-12-03 14:09:51Z vboxsync $ */
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2 | /** @file
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3 | * HM - Internal header file.
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4 | */
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5 |
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6 | /*
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7 | * Copyright (C) 2006-2013 Oracle Corporation
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8 | *
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9 | * This file is part of VirtualBox Open Source Edition (OSE), as
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10 | * available from http://www.virtualbox.org. This file is free software;
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11 | * you can redistribute it and/or modify it under the terms of the GNU
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12 | * General Public License (GPL) as published by the Free Software
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13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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16 | */
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17 |
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18 | #ifndef ___HMInternal_h
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19 | #define ___HMInternal_h
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20 |
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21 | #include <VBox/cdefs.h>
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22 | #include <VBox/types.h>
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23 | #include <VBox/vmm/em.h>
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24 | #include <VBox/vmm/stam.h>
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25 | #include <VBox/dis.h>
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26 | #include <VBox/vmm/hm.h>
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27 | #include <VBox/vmm/hm_vmx.h>
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28 | #include <VBox/vmm/pgm.h>
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29 | #include <VBox/vmm/cpum.h>
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30 | #include <iprt/memobj.h>
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31 | #include <iprt/cpuset.h>
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32 | #include <iprt/mp.h>
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33 | #include <iprt/avl.h>
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34 |
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35 | #if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL) || defined (VBOX_WITH_64_BITS_GUESTS)
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36 | /* Enable 64 bits guest support. */
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37 | # define VBOX_ENABLE_64_BITS_GUESTS
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38 | #endif
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39 |
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40 | #if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
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41 | # define VMX_USE_CACHED_VMCS_ACCESSES
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42 | #endif
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43 |
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44 | /** @def HM_PROFILE_EXIT_DISPATCH
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45 | * Enables profiling of the VM exit handler dispatching. */
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46 | #if 0
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47 | # define HM_PROFILE_EXIT_DISPATCH
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48 | #endif
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49 |
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50 | RT_C_DECLS_BEGIN
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51 |
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52 |
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53 | /** @defgroup grp_hm_int Internal
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54 | * @ingroup grp_hm
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55 | * @internal
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56 | * @{
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57 | */
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58 |
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59 | /** @def HMCPU_CF_CLEAR
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60 | * Clears a HM-context flag.
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61 | *
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62 | * @param pVCpu Pointer to the VMCPU.
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63 | * @param fFlag The flag to clear.
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64 | */
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65 | #define HMCPU_CF_CLEAR(pVCpu, fFlag) (ASMAtomicUoAndU32(&(pVCpu)->hm.s.fContextUseFlags, ~(fFlag)))
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66 |
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67 | /** @def HMCPU_CF_SET
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68 | * Sets a HM-context flag.
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69 | *
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70 | * @param pVCpu Pointer to the VMCPU.
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71 | * @param fFlag The flag to set.
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72 | */
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73 | #define HMCPU_CF_SET(pVCpu, fFlag) (ASMAtomicUoOrU32(&(pVCpu)->hm.s.fContextUseFlags, (fFlag)))
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74 |
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75 | /** @def HMCPU_CF_IS_SET
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76 | * Checks if all the flags in the specified HM-context set is pending.
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77 | *
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78 | * @param pVCpu Pointer to the VMCPU.
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79 | * @param fFlag The flag to check.
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80 | */
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81 | #define HMCPU_CF_IS_SET(pVCpu, fFlag) ((ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags) & (fFlag)) == (fFlag))
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82 |
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83 | /** @def HMCPU_CF_IS_PENDING
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84 | * Checks if one or more of the flags in the specified HM-context set is
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85 | * pending.
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86 | *
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87 | * @param pVCpu Pointer to the VMCPU.
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88 | * @param fFlags The flags to check for.
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89 | */
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90 | #define HMCPU_CF_IS_PENDING(pVCpu, fFlags) RT_BOOL(ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags) & (fFlags))
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91 |
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92 | /** @def HMCPU_CF_IS_PENDING_ONLY
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93 | * Checks if -only- one or more of the specified HM-context flags is pending.
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94 | *
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95 | * @param pVCpu Pointer to the VMCPU.
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96 | * @param fFlags The flags to check for.
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97 | */
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98 | #define HMCPU_CF_IS_PENDING_ONLY(pVCpu, fFlags) !RT_BOOL(ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags) & ~(fFlags))
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99 |
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100 | /** @def HMCPU_CF_IS_SET_ONLY
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101 | * Checks if -only- all the flags in the specified HM-context set is pending.
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102 | *
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103 | * @param pVCpu Pointer to the VMCPU.
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104 | * @param fFlags The flags to check for.
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105 | */
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106 | #define HMCPU_CF_IS_SET_ONLY(pVCpu, fFlags) (ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags) == (fFlags))
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107 |
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108 | /** @def HMCPU_CF_RESET_TO
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109 | * Resets the HM-context flags to the specified value.
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110 | *
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111 | * @param pVCpu Pointer to the VMCPU.
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112 | * @param fFlags The new value.
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113 | */
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114 | #define HMCPU_CF_RESET_TO(pVCpu, fFlags) (ASMAtomicUoWriteU32(&(pVCpu)->hm.s.fContextUseFlags, (fFlags)))
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115 |
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116 | /** @def HMCPU_CF_VALUE
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117 | * Returns the current HM-context flags value.
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118 | *
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119 | * @param pVCpu Pointer to the VMCPU.
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120 | */
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121 | #define HMCPU_CF_VALUE(pVCpu) (ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags))
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122 |
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123 |
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124 | /** Maximum number of exit reason statistics counters. */
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125 | #define MAX_EXITREASON_STAT 0x100
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126 | #define MASK_EXITREASON_STAT 0xff
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127 | #define MASK_INJECT_IRQ_STAT 0xff
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128 |
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129 | /** @name HM changed flags.
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130 | * These flags are used to keep track of which important registers that
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131 | * have been changed since last they were reset.
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132 | * @{
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133 | */
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134 | #define HM_CHANGED_GUEST_CR0 RT_BIT(0) /* Shared */
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135 | #define HM_CHANGED_GUEST_CR3 RT_BIT(1)
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136 | #define HM_CHANGED_GUEST_CR4 RT_BIT(2)
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137 | #define HM_CHANGED_GUEST_GDTR RT_BIT(3)
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138 | #define HM_CHANGED_GUEST_IDTR RT_BIT(4)
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139 | #define HM_CHANGED_GUEST_LDTR RT_BIT(5)
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140 | #define HM_CHANGED_GUEST_TR RT_BIT(6)
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141 | #define HM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(7)
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142 | #define HM_CHANGED_GUEST_DEBUG RT_BIT(8) /* Shared */
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143 | #define HM_CHANGED_GUEST_RIP RT_BIT(9)
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144 | #define HM_CHANGED_GUEST_RSP RT_BIT(10)
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145 | #define HM_CHANGED_GUEST_RFLAGS RT_BIT(11)
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146 | #define HM_CHANGED_GUEST_CR2 RT_BIT(12)
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147 | #define HM_CHANGED_GUEST_SYSENTER_CS_MSR RT_BIT(13)
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148 | #define HM_CHANGED_GUEST_SYSENTER_EIP_MSR RT_BIT(14)
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149 | #define HM_CHANGED_GUEST_SYSENTER_ESP_MSR RT_BIT(15)
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150 | #define HM_CHANGED_GUEST_LAZY_MSRS RT_BIT(16) /* Shared */
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151 | /* VT-x specific state. */
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152 | #define HM_CHANGED_VMX_GUEST_AUTO_MSRS RT_BIT(17)
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153 | #define HM_CHANGED_VMX_GUEST_ACTIVITY_STATE RT_BIT(18)
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154 | #define HM_CHANGED_VMX_GUEST_APIC_STATE RT_BIT(19)
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155 | #define HM_CHANGED_VMX_ENTRY_CTLS RT_BIT(20)
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156 | #define HM_CHANGED_VMX_EXIT_CTLS RT_BIT(21)
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157 | /* AMD-V specific state. */
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158 | #define HM_CHANGED_SVM_GUEST_EFER_MSR RT_BIT(17)
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159 | #define HM_CHANGED_SVM_GUEST_APIC_STATE RT_BIT(18)
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160 | #define HM_CHANGED_SVM_RESERVED1 RT_BIT(19)
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161 | #define HM_CHANGED_SVM_RESERVED2 RT_BIT(20)
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162 | #define HM_CHANGED_SVM_RESERVED3 RT_BIT(21)
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163 |
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164 | #define HM_CHANGED_ALL_GUEST ( HM_CHANGED_GUEST_CR0 \
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165 | | HM_CHANGED_GUEST_CR3 \
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166 | | HM_CHANGED_GUEST_CR4 \
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167 | | HM_CHANGED_GUEST_GDTR \
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168 | | HM_CHANGED_GUEST_IDTR \
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169 | | HM_CHANGED_GUEST_LDTR \
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170 | | HM_CHANGED_GUEST_TR \
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171 | | HM_CHANGED_GUEST_SEGMENT_REGS \
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172 | | HM_CHANGED_GUEST_DEBUG \
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173 | | HM_CHANGED_GUEST_RIP \
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174 | | HM_CHANGED_GUEST_RSP \
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175 | | HM_CHANGED_GUEST_RFLAGS \
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176 | | HM_CHANGED_GUEST_CR2 \
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177 | | HM_CHANGED_GUEST_SYSENTER_CS_MSR \
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178 | | HM_CHANGED_GUEST_SYSENTER_EIP_MSR \
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179 | | HM_CHANGED_GUEST_SYSENTER_ESP_MSR \
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180 | | HM_CHANGED_GUEST_LAZY_MSRS \
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181 | | HM_CHANGED_VMX_GUEST_AUTO_MSRS \
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182 | | HM_CHANGED_VMX_GUEST_ACTIVITY_STATE \
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183 | | HM_CHANGED_VMX_GUEST_APIC_STATE \
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184 | | HM_CHANGED_VMX_ENTRY_CTLS \
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185 | | HM_CHANGED_VMX_EXIT_CTLS)
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186 |
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187 | #define HM_CHANGED_HOST_CONTEXT RT_BIT(22)
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188 |
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189 | /* Bits shared between host and guest. */
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190 | #define HM_CHANGED_HOST_GUEST_SHARED_STATE ( HM_CHANGED_GUEST_CR0 \
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191 | | HM_CHANGED_GUEST_DEBUG \
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192 | | HM_CHANGED_GUEST_LAZY_MSRS)
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193 | /** @} */
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194 |
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195 | /** Maximum number of page flushes we are willing to remember before considering a full TLB flush. */
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196 | #define HM_MAX_TLB_SHOOTDOWN_PAGES 8
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197 |
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198 | /** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
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199 | #define HM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
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200 | /** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
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201 | #define HM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2 * PAGE_SIZE + 1)
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202 | /** Total guest mapped memory needed. */
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203 | #define HM_VTX_TOTAL_DEVHEAP_MEM (HM_EPT_IDENTITY_PG_TABLE_SIZE + HM_VTX_TSS_SIZE)
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204 |
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205 | /** Enable for TPR guest patching. */
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206 | #define VBOX_HM_WITH_GUEST_PATCHING
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207 |
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208 | /** HM SSM version
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209 | */
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210 | #ifdef VBOX_HM_WITH_GUEST_PATCHING
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211 | # define HM_SSM_VERSION 5
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212 | # define HM_SSM_VERSION_NO_PATCHING 4
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213 | #else
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214 | # define HM_SSM_VERSION 4
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215 | # define HM_SSM_VERSION_NO_PATCHING 4
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216 | #endif
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217 | #define HM_SSM_VERSION_2_0_X 3
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218 |
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219 | /**
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220 | * Global per-cpu information. (host)
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221 | */
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222 | typedef struct HMGLOBALCPUINFO
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223 | {
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224 | /** The CPU ID. */
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225 | RTCPUID idCpu;
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226 | /** The memory object */
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227 | RTR0MEMOBJ hMemObj;
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228 | /** Current ASID (AMD-V) / VPID (Intel). */
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229 | uint32_t uCurrentAsid;
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230 | /** TLB flush count. */
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231 | uint32_t cTlbFlushes;
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232 | /** Whether to flush each new ASID/VPID before use. */
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233 | bool fFlushAsidBeforeUse;
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234 | /** Configured for VT-x or AMD-V. */
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235 | bool fConfigured;
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236 | /** Set if the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active. */
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237 | bool fIgnoreAMDVInUseError;
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238 | /** In use by our code. (for power suspend) */
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239 | volatile bool fInUse;
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240 | } HMGLOBALCPUINFO;
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241 | /** Pointer to the per-cpu global information. */
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242 | typedef HMGLOBALCPUINFO *PHMGLOBALCPUINFO;
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243 |
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244 | typedef enum
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245 | {
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246 | HMPENDINGIO_INVALID = 0,
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247 | HMPENDINGIO_PORT_READ,
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248 | HMPENDINGIO_PORT_WRITE,
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249 | HMPENDINGIO_STRING_READ,
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250 | HMPENDINGIO_STRING_WRITE,
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251 | /** The usual 32-bit paranoia. */
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252 | HMPENDINGIO_32BIT_HACK = 0x7fffffff
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253 | } HMPENDINGIO;
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254 |
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255 |
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256 | typedef enum
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257 | {
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258 | HMTPRINSTR_INVALID,
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259 | HMTPRINSTR_READ,
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260 | HMTPRINSTR_READ_SHR4,
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261 | HMTPRINSTR_WRITE_REG,
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262 | HMTPRINSTR_WRITE_IMM,
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263 | HMTPRINSTR_JUMP_REPLACEMENT,
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264 | /** The usual 32-bit paranoia. */
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265 | HMTPRINSTR_32BIT_HACK = 0x7fffffff
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266 | } HMTPRINSTR;
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267 |
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268 | typedef struct
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269 | {
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270 | /** The key is the address of patched instruction. (32 bits GC ptr) */
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271 | AVLOU32NODECORE Core;
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272 | /** Original opcode. */
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273 | uint8_t aOpcode[16];
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274 | /** Instruction size. */
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275 | uint32_t cbOp;
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276 | /** Replacement opcode. */
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277 | uint8_t aNewOpcode[16];
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278 | /** Replacement instruction size. */
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279 | uint32_t cbNewOp;
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280 | /** Instruction type. */
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281 | HMTPRINSTR enmType;
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282 | /** Source operand. */
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283 | uint32_t uSrcOperand;
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284 | /** Destination operand. */
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285 | uint32_t uDstOperand;
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286 | /** Number of times the instruction caused a fault. */
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287 | uint32_t cFaults;
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288 | /** Patch address of the jump replacement. */
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289 | RTGCPTR32 pJumpTarget;
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290 | } HMTPRPATCH;
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291 | /** Pointer to HMTPRPATCH. */
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292 | typedef HMTPRPATCH *PHMTPRPATCH;
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293 |
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294 | /**
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295 | * Switcher function, HC to the special 64-bit RC.
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296 | *
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297 | * @param pVM Pointer to the VM.
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298 | * @param offCpumVCpu Offset from pVM->cpum to pVM->aCpus[idCpu].cpum.
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299 | * @returns Return code indicating the action to take.
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300 | */
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301 | typedef DECLCALLBACK(int) FNHMSWITCHERHC(PVM pVM, uint32_t offCpumVCpu);
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302 | /** Pointer to switcher function. */
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303 | typedef FNHMSWITCHERHC *PFNHMSWITCHERHC;
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304 |
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305 | /**
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306 | * HM VM Instance data.
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307 | * Changes to this must checked against the padding of the hm union in VM!
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308 | */
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309 | typedef struct HM
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310 | {
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311 | /** Set when we've initialized VMX or SVM. */
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312 | bool fInitialized;
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313 |
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314 | /** Set if nested paging is enabled. */
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315 | bool fNestedPaging;
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316 |
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317 | /** Set if nested paging is allowed. */
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318 | bool fAllowNestedPaging;
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319 |
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320 | /** Set if large pages are enabled (requires nested paging). */
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321 | bool fLargePages;
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322 |
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323 | /** Set if we can support 64-bit guests or not. */
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324 | bool fAllow64BitGuests;
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325 |
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326 | /** Set if an IO-APIC is configured for this VM. */
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327 | bool fHasIoApic;
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328 |
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329 | /** Set when TPR patching is allowed. */
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330 | bool fTRPPatchingAllowed;
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331 |
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332 | /** Set when we initialize VT-x or AMD-V once for all CPUs. */
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333 | bool fGlobalInit;
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334 |
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335 | /** Set when TPR patching is active. */
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336 | bool fTPRPatchingActive;
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337 | bool u8Alignment[7];
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338 |
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339 | /** Maximum ASID allowed. */
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340 | uint32_t uMaxAsid;
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341 |
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342 | /** The maximum number of resumes loops allowed in ring-0 (safety precaution).
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343 | * This number is set much higher when RTThreadPreemptIsPending is reliable. */
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344 | uint32_t cMaxResumeLoops;
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345 |
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346 | /** Guest allocated memory for patching purposes. */
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347 | RTGCPTR pGuestPatchMem;
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348 | /** Current free pointer inside the patch block. */
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349 | RTGCPTR pFreeGuestPatchMem;
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350 | /** Size of the guest patch memory block. */
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351 | uint32_t cbGuestPatchMem;
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352 | uint32_t uPadding1;
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353 |
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354 | #if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
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355 | /** 32 to 64 bits switcher entrypoint. */
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356 | R0PTRTYPE(PFNHMSWITCHERHC) pfnHost32ToGuest64R0;
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357 | RTR0PTR uPadding2;
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358 | #endif
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359 |
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360 | struct
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361 | {
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362 | /** Set by the ring-0 side of HM to indicate VMX is supported by the
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363 | * CPU. */
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364 | bool fSupported;
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365 |
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366 | /** Set when we've enabled VMX. */
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367 | bool fEnabled;
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368 |
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369 | /** Set if VPID is supported. */
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370 | bool fVpid;
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371 |
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372 | /** Set if VT-x VPID is allowed. */
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373 | bool fAllowVpid;
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374 |
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375 | /** Set if unrestricted guest execution is in use (real and protected mode without paging). */
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376 | bool fUnrestrictedGuest;
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377 |
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378 | /** Set if unrestricted guest execution is allowed to be used. */
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379 | bool fAllowUnrestricted;
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380 |
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381 | /** Whether we're using the preemption timer or not. */
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382 | bool fUsePreemptTimer;
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383 | /** The shift mask employed by the VMX-Preemption timer. */
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384 | uint8_t cPreemptTimerShift;
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385 |
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386 | /** Virtual address of the TSS page used for real mode emulation. */
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387 | R3PTRTYPE(PVBOXTSS) pRealModeTSS;
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388 |
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389 | /** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
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390 | R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
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391 |
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392 | /** R0 memory object for the APIC-access page. */
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393 | RTR0MEMOBJ hMemObjApicAccess;
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394 | /** Physical address of the APIC-access page. */
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395 | RTHCPHYS HCPhysApicAccess;
|
---|
396 | /** Virtual address of the APIC-access page. */
|
---|
397 | R0PTRTYPE(uint8_t *) pbApicAccess;
|
---|
398 |
|
---|
399 | #ifdef VBOX_WITH_CRASHDUMP_MAGIC
|
---|
400 | RTR0MEMOBJ hMemObjScratch;
|
---|
401 | RTHCPHYS HCPhysScratch;
|
---|
402 | R0PTRTYPE(uint8_t *) pbScratch;
|
---|
403 | #endif
|
---|
404 |
|
---|
405 | /** Internal Id of which flush-handler to use for tagged-TLB entries. */
|
---|
406 | unsigned uFlushTaggedTlb;
|
---|
407 |
|
---|
408 | #if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
|
---|
409 | uint32_t u32Alignment;
|
---|
410 | #endif
|
---|
411 | /** Host CR4 value (set by ring-0 VMX init) */
|
---|
412 | uint64_t u64HostCr4;
|
---|
413 |
|
---|
414 | /** Host EFER value (set by ring-0 VMX init) */
|
---|
415 | uint64_t u64HostEfer;
|
---|
416 |
|
---|
417 | /** VMX MSR values */
|
---|
418 | VMXMSRS Msrs;
|
---|
419 |
|
---|
420 | /** Flush types for invept & invvpid; they depend on capabilities. */
|
---|
421 | VMX_FLUSH_EPT enmFlushEpt;
|
---|
422 | VMX_FLUSH_VPID enmFlushVpid;
|
---|
423 | } vmx;
|
---|
424 |
|
---|
425 | struct
|
---|
426 | {
|
---|
427 | /** Set by the ring-0 side of HM to indicate SVM is supported by the
|
---|
428 | * CPU. */
|
---|
429 | bool fSupported;
|
---|
430 | /** Set when we've enabled SVM. */
|
---|
431 | bool fEnabled;
|
---|
432 | /** Set if erratum 170 affects the AMD cpu. */
|
---|
433 | bool fAlwaysFlushTLB;
|
---|
434 | /** Set when the hack to ignore VERR_SVM_IN_USE is active. */
|
---|
435 | bool fIgnoreInUseError;
|
---|
436 |
|
---|
437 | /** R0 memory object for the IO bitmap (12kb). */
|
---|
438 | RTR0MEMOBJ hMemObjIOBitmap;
|
---|
439 | /** Physical address of the IO bitmap (12kb). */
|
---|
440 | RTHCPHYS HCPhysIOBitmap;
|
---|
441 | /** Virtual address of the IO bitmap. */
|
---|
442 | R0PTRTYPE(void *) pvIOBitmap;
|
---|
443 |
|
---|
444 | /* HWCR MSR (for diagnostics) */
|
---|
445 | uint64_t u64MsrHwcr;
|
---|
446 |
|
---|
447 | /** SVM revision. */
|
---|
448 | uint32_t u32Rev;
|
---|
449 |
|
---|
450 | /** SVM feature bits from cpuid 0x8000000a */
|
---|
451 | uint32_t u32Features;
|
---|
452 | } svm;
|
---|
453 |
|
---|
454 | /**
|
---|
455 | * AVL tree with all patches (active or disabled) sorted by guest instruction address
|
---|
456 | */
|
---|
457 | AVLOU32TREE PatchTree;
|
---|
458 | uint32_t cPatches;
|
---|
459 | HMTPRPATCH aPatches[64];
|
---|
460 |
|
---|
461 | struct
|
---|
462 | {
|
---|
463 | uint32_t u32AMDFeatureECX;
|
---|
464 | uint32_t u32AMDFeatureEDX;
|
---|
465 | } cpuid;
|
---|
466 |
|
---|
467 | /** Saved error from detection */
|
---|
468 | int32_t lLastError;
|
---|
469 |
|
---|
470 | /** HMR0Init was run */
|
---|
471 | bool fHMR0Init;
|
---|
472 | bool u8Alignment1[7];
|
---|
473 |
|
---|
474 | STAMCOUNTER StatTprPatchSuccess;
|
---|
475 | STAMCOUNTER StatTprPatchFailure;
|
---|
476 | STAMCOUNTER StatTprReplaceSuccess;
|
---|
477 | STAMCOUNTER StatTprReplaceFailure;
|
---|
478 | } HM;
|
---|
479 | /** Pointer to HM VM instance data. */
|
---|
480 | typedef HM *PHM;
|
---|
481 |
|
---|
482 | /* Maximum number of cached entries. */
|
---|
483 | #define VMCSCACHE_MAX_ENTRY 128
|
---|
484 |
|
---|
485 | /* Structure for storing read and write VMCS actions. */
|
---|
486 | typedef struct VMCSCACHE
|
---|
487 | {
|
---|
488 | #ifdef VBOX_WITH_CRASHDUMP_MAGIC
|
---|
489 | /* Magic marker for searching in crash dumps. */
|
---|
490 | uint8_t aMagic[16];
|
---|
491 | uint64_t uMagic;
|
---|
492 | uint64_t u64TimeEntry;
|
---|
493 | uint64_t u64TimeSwitch;
|
---|
494 | uint64_t cResume;
|
---|
495 | uint64_t interPD;
|
---|
496 | uint64_t pSwitcher;
|
---|
497 | uint32_t uPos;
|
---|
498 | uint32_t idCpu;
|
---|
499 | #endif
|
---|
500 | /* CR2 is saved here for EPT syncing. */
|
---|
501 | uint64_t cr2;
|
---|
502 | struct
|
---|
503 | {
|
---|
504 | uint32_t cValidEntries;
|
---|
505 | uint32_t uAlignment;
|
---|
506 | uint32_t aField[VMCSCACHE_MAX_ENTRY];
|
---|
507 | uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
|
---|
508 | } Write;
|
---|
509 | struct
|
---|
510 | {
|
---|
511 | uint32_t cValidEntries;
|
---|
512 | uint32_t uAlignment;
|
---|
513 | uint32_t aField[VMCSCACHE_MAX_ENTRY];
|
---|
514 | uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
|
---|
515 | } Read;
|
---|
516 | #ifdef VBOX_STRICT
|
---|
517 | struct
|
---|
518 | {
|
---|
519 | RTHCPHYS HCPhysCpuPage;
|
---|
520 | RTHCPHYS HCPhysVmcs;
|
---|
521 | RTGCPTR pCache;
|
---|
522 | RTGCPTR pCtx;
|
---|
523 | } TestIn;
|
---|
524 | struct
|
---|
525 | {
|
---|
526 | RTHCPHYS HCPhysVmcs;
|
---|
527 | RTGCPTR pCache;
|
---|
528 | RTGCPTR pCtx;
|
---|
529 | uint64_t eflags;
|
---|
530 | uint64_t cr8;
|
---|
531 | } TestOut;
|
---|
532 | struct
|
---|
533 | {
|
---|
534 | uint64_t param1;
|
---|
535 | uint64_t param2;
|
---|
536 | uint64_t param3;
|
---|
537 | uint64_t param4;
|
---|
538 | } ScratchPad;
|
---|
539 | #endif
|
---|
540 | } VMCSCACHE;
|
---|
541 | /** Pointer to VMCSCACHE. */
|
---|
542 | typedef VMCSCACHE *PVMCSCACHE;
|
---|
543 |
|
---|
544 | /** VMX StartVM function. */
|
---|
545 | typedef DECLCALLBACK(int) FNHMVMXSTARTVM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);
|
---|
546 | /** Pointer to a VMX StartVM function. */
|
---|
547 | typedef R0PTRTYPE(FNHMVMXSTARTVM *) PFNHMVMXSTARTVM;
|
---|
548 |
|
---|
549 | /** SVM VMRun function. */
|
---|
550 | typedef DECLCALLBACK(int) FNHMSVMVMRUN(RTHCPHYS pVmcbHostPhys, RTHCPHYS pVmcbPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu);
|
---|
551 | /** Pointer to a SVM VMRun function. */
|
---|
552 | typedef R0PTRTYPE(FNHMSVMVMRUN *) PFNHMSVMVMRUN;
|
---|
553 |
|
---|
554 | /**
|
---|
555 | * HM VMCPU Instance data.
|
---|
556 | */
|
---|
557 | typedef struct HMCPU
|
---|
558 | {
|
---|
559 | /** Set if we need to flush the TLB during the world switch. */
|
---|
560 | bool fForceTLBFlush;
|
---|
561 | /** Set when we're using VT-x or AMD-V at that moment. */
|
---|
562 | bool fActive;
|
---|
563 | /** Set when the TLB has been checked until we return from the world switch. */
|
---|
564 | volatile bool fCheckedTLBFlush;
|
---|
565 | /** Whether we're executing a single instruction. */
|
---|
566 | bool fSingleInstruction;
|
---|
567 | /** Set if we need to clear the trap flag because of single stepping. */
|
---|
568 | bool fClearTrapFlag;
|
---|
569 | /** Whether we've completed the inner HM leave function. */
|
---|
570 | bool fLeaveDone;
|
---|
571 | /** Whether we're using the hyper DR7 or guest DR7. */
|
---|
572 | bool fUsingHyperDR7;
|
---|
573 | /** Whether to preload the guest-FPU state to avoid #NM VM-exit overhead. */
|
---|
574 | bool fUseGuestFpu;
|
---|
575 |
|
---|
576 | /** World switch exit counter. */
|
---|
577 | volatile uint32_t cWorldSwitchExits;
|
---|
578 | /** HM_CHANGED_* flags. */
|
---|
579 | volatile uint32_t fContextUseFlags;
|
---|
580 | /** Id of the last cpu we were executing code on (NIL_RTCPUID for the first
|
---|
581 | * time). */
|
---|
582 | RTCPUID idLastCpu;
|
---|
583 | /** TLB flush count. */
|
---|
584 | uint32_t cTlbFlushes;
|
---|
585 | /** Current ASID in use by the VM. */
|
---|
586 | uint32_t uCurrentAsid;
|
---|
587 | /** An additional error code used for some gurus. */
|
---|
588 | uint32_t u32HMError;
|
---|
589 | /** Host's TSC_AUX MSR (used when RDTSCP doesn't cause VM-exits). */
|
---|
590 | uint64_t u64HostTscAux;
|
---|
591 |
|
---|
592 | struct
|
---|
593 | {
|
---|
594 | /** Physical address of the VM control structure (VMCS). */
|
---|
595 | RTHCPHYS HCPhysVmcs;
|
---|
596 | /** R0 memory object for the VM control structure (VMCS). */
|
---|
597 | RTR0MEMOBJ hMemObjVmcs;
|
---|
598 | /** Virtual address of the VM control structure (VMCS). */
|
---|
599 | R0PTRTYPE(void *) pvVmcs;
|
---|
600 | /** Ring 0 handlers for VT-x. */
|
---|
601 | PFNHMVMXSTARTVM pfnStartVM;
|
---|
602 | #if HC_ARCH_BITS == 32
|
---|
603 | uint32_t u32Alignment1;
|
---|
604 | #endif
|
---|
605 |
|
---|
606 | /** Current VMX_VMCS32_CTRL_PIN_EXEC. */
|
---|
607 | uint32_t u32PinCtls;
|
---|
608 | /** Current VMX_VMCS32_CTRL_PROC_EXEC. */
|
---|
609 | uint32_t u32ProcCtls;
|
---|
610 | /** Current VMX_VMCS32_CTRL_PROC_EXEC2. */
|
---|
611 | uint32_t u32ProcCtls2;
|
---|
612 | /** Current VMX_VMCS32_CTRL_EXIT. */
|
---|
613 | uint32_t u32ExitCtls;
|
---|
614 | /** Current VMX_VMCS32_CTRL_ENTRY. */
|
---|
615 | uint32_t u32EntryCtls;
|
---|
616 |
|
---|
617 | /** Physical address of the virtual APIC page for TPR caching. */
|
---|
618 | RTHCPHYS HCPhysVirtApic;
|
---|
619 | /** R0 memory object for the virtual APIC page for TPR caching. */
|
---|
620 | RTR0MEMOBJ hMemObjVirtApic;
|
---|
621 | /** Virtual address of the virtual APIC page for TPR caching. */
|
---|
622 | R0PTRTYPE(uint8_t *) pbVirtApic;
|
---|
623 | #if HC_ARCH_BITS == 32
|
---|
624 | uint32_t u32Alignment2;
|
---|
625 | #endif
|
---|
626 |
|
---|
627 | /** Current CR0 mask. */
|
---|
628 | uint32_t u32CR0Mask;
|
---|
629 | /** Current CR4 mask. */
|
---|
630 | uint32_t u32CR4Mask;
|
---|
631 | /** Current exception bitmap. */
|
---|
632 | uint32_t u32XcptBitmap;
|
---|
633 | /** The updated-guest-state mask. */
|
---|
634 | volatile uint32_t fUpdatedGuestState;
|
---|
635 | /** Current EPTP. */
|
---|
636 | RTHCPHYS HCPhysEPTP;
|
---|
637 |
|
---|
638 | /** Physical address of the MSR bitmap. */
|
---|
639 | RTHCPHYS HCPhysMsrBitmap;
|
---|
640 | /** R0 memory object for the MSR bitmap. */
|
---|
641 | RTR0MEMOBJ hMemObjMsrBitmap;
|
---|
642 | /** Virtual address of the MSR bitmap. */
|
---|
643 | R0PTRTYPE(void *) pvMsrBitmap;
|
---|
644 |
|
---|
645 | /** Physical address of the VM-entry MSR-load and VM-exit MSR-store area (used
|
---|
646 | * for guest MSRs). */
|
---|
647 | RTHCPHYS HCPhysGuestMsr;
|
---|
648 | /** R0 memory object of the VM-entry MSR-load and VM-exit MSR-store area
|
---|
649 | * (used for guest MSRs). */
|
---|
650 | RTR0MEMOBJ hMemObjGuestMsr;
|
---|
651 | /** Virtual address of the VM-entry MSR-load and VM-exit MSR-store area (used
|
---|
652 | * for guest MSRs). */
|
---|
653 | R0PTRTYPE(void *) pvGuestMsr;
|
---|
654 |
|
---|
655 | /** Physical address of the VM-exit MSR-load area (used for host MSRs). */
|
---|
656 | RTHCPHYS HCPhysHostMsr;
|
---|
657 | /** R0 memory object for the VM-exit MSR-load area (used for host MSRs). */
|
---|
658 | RTR0MEMOBJ hMemObjHostMsr;
|
---|
659 | /** Virtual address of the VM-exit MSR-load area (used for host MSRs). */
|
---|
660 | R0PTRTYPE(void *) pvHostMsr;
|
---|
661 |
|
---|
662 | /** Number of guest/host MSR pairs in the auto-load/store area. */
|
---|
663 | uint32_t cMsrs;
|
---|
664 | /** Whether the host MSR values are up-to-date in the auto-load/store area. */
|
---|
665 | bool fUpdatedHostMsrs;
|
---|
666 | uint8_t u8Align[7];
|
---|
667 |
|
---|
668 | /** Host LSTAR MSR value to restore lazily while leaving VT-x. */
|
---|
669 | uint64_t u64HostLStarMsr;
|
---|
670 | /** Host STAR MSR value to restore lazily while leaving VT-x. */
|
---|
671 | uint64_t u64HostStarMsr;
|
---|
672 | /** Host SF_MASK MSR value to restore lazily while leaving VT-x. */
|
---|
673 | uint64_t u64HostSFMaskMsr;
|
---|
674 | /** Host KernelGS-Base MSR value to restore lazily while leaving VT-x. */
|
---|
675 | uint64_t u64HostKernelGSBaseMsr;
|
---|
676 | /** A mask of which MSRs have been swapped and need restoration. */
|
---|
677 | uint32_t fRestoreHostMsrs;
|
---|
678 | uint32_t u32Alignment3;
|
---|
679 |
|
---|
680 | /** The cached APIC-base MSR used for identifying when to map the HC physical APIC-access page. */
|
---|
681 | uint64_t u64MsrApicBase;
|
---|
682 | /** Last use TSC offset value. (cached) */
|
---|
683 | uint64_t u64TSCOffset;
|
---|
684 |
|
---|
685 | /** VMCS cache. */
|
---|
686 | VMCSCACHE VMCSCache;
|
---|
687 |
|
---|
688 | /** Real-mode emulation state. */
|
---|
689 | struct
|
---|
690 | {
|
---|
691 | X86DESCATTR AttrCS;
|
---|
692 | X86DESCATTR AttrDS;
|
---|
693 | X86DESCATTR AttrES;
|
---|
694 | X86DESCATTR AttrFS;
|
---|
695 | X86DESCATTR AttrGS;
|
---|
696 | X86DESCATTR AttrSS;
|
---|
697 | X86EFLAGS Eflags;
|
---|
698 | uint32_t fRealOnV86Active;
|
---|
699 | } RealMode;
|
---|
700 |
|
---|
701 | struct
|
---|
702 | {
|
---|
703 | uint64_t u64VMCSPhys;
|
---|
704 | uint32_t u32VMCSRevision;
|
---|
705 | uint32_t u32InstrError;
|
---|
706 | uint32_t u32ExitReason;
|
---|
707 | RTCPUID idEnteredCpu;
|
---|
708 | RTCPUID idCurrentCpu;
|
---|
709 | uint32_t u32Padding;
|
---|
710 | } LastError;
|
---|
711 |
|
---|
712 | /** State of the VMCS. */
|
---|
713 | uint32_t uVmcsState;
|
---|
714 | /** Which host-state bits to restore before being preempted. */
|
---|
715 | uint32_t fRestoreHostFlags;
|
---|
716 | /** The host-state restoration structure. */
|
---|
717 | VMXRESTOREHOST RestoreHost;
|
---|
718 | /** Set if guest was executing in real mode (extra checks). */
|
---|
719 | bool fWasInRealMode;
|
---|
720 | uint8_t u8Align2[7];
|
---|
721 |
|
---|
722 | /** Alignment padding. */
|
---|
723 | uint32_t u32Padding;
|
---|
724 | } vmx;
|
---|
725 |
|
---|
726 | struct
|
---|
727 | {
|
---|
728 | /** R0 memory object for the host VMCB which holds additional host-state. */
|
---|
729 | RTR0MEMOBJ hMemObjVmcbHost;
|
---|
730 | /** Physical address of the host VMCB which holds additional host-state. */
|
---|
731 | RTHCPHYS HCPhysVmcbHost;
|
---|
732 | /** Virtual address of the host VMCB which holds additional host-state. */
|
---|
733 | R0PTRTYPE(void *) pvVmcbHost;
|
---|
734 |
|
---|
735 | /** R0 memory object for the guest VMCB. */
|
---|
736 | RTR0MEMOBJ hMemObjVmcb;
|
---|
737 | /** Physical address of the guest VMCB. */
|
---|
738 | RTHCPHYS HCPhysVmcb;
|
---|
739 | /** Virtual address of the guest VMCB. */
|
---|
740 | R0PTRTYPE(void *) pvVmcb;
|
---|
741 |
|
---|
742 | /** Ring 0 handlers for VT-x. */
|
---|
743 | PFNHMSVMVMRUN pfnVMRun;
|
---|
744 |
|
---|
745 | /** R0 memory object for the MSR bitmap (8 KB). */
|
---|
746 | RTR0MEMOBJ hMemObjMsrBitmap;
|
---|
747 | /** Physical address of the MSR bitmap (8 KB). */
|
---|
748 | RTHCPHYS HCPhysMsrBitmap;
|
---|
749 | /** Virtual address of the MSR bitmap. */
|
---|
750 | R0PTRTYPE(void *) pvMsrBitmap;
|
---|
751 |
|
---|
752 | /** Whether VTPR with V_INTR_MASKING set is in effect, indicating
|
---|
753 | * we should check if the VTPR changed on every VM-exit. */
|
---|
754 | bool fSyncVTpr;
|
---|
755 | uint8_t u8Align[7];
|
---|
756 |
|
---|
757 | /** Alignment padding. */
|
---|
758 | uint32_t u32Padding;
|
---|
759 | } svm;
|
---|
760 |
|
---|
761 | /** Event injection state. */
|
---|
762 | struct
|
---|
763 | {
|
---|
764 | uint32_t fPending;
|
---|
765 | uint32_t u32ErrCode;
|
---|
766 | uint32_t cbInstr;
|
---|
767 | uint32_t u32Padding; /**< Explicit alignment padding. */
|
---|
768 | uint64_t u64IntInfo;
|
---|
769 | RTGCUINTPTR GCPtrFaultAddress;
|
---|
770 | } Event;
|
---|
771 |
|
---|
772 | /** IO Block emulation state. */
|
---|
773 | struct
|
---|
774 | {
|
---|
775 | bool fEnabled;
|
---|
776 | uint8_t u8Align[7];
|
---|
777 |
|
---|
778 | /** RIP at the start of the io code we wish to emulate in the recompiler. */
|
---|
779 | RTGCPTR GCPtrFunctionEip;
|
---|
780 |
|
---|
781 | uint64_t cr0;
|
---|
782 | } EmulateIoBlock;
|
---|
783 |
|
---|
784 | struct
|
---|
785 | {
|
---|
786 | /** Pending IO operation type. */
|
---|
787 | HMPENDINGIO enmType;
|
---|
788 | uint32_t uPadding;
|
---|
789 | RTGCPTR GCPtrRip;
|
---|
790 | RTGCPTR GCPtrRipNext;
|
---|
791 | union
|
---|
792 | {
|
---|
793 | struct
|
---|
794 | {
|
---|
795 | uint32_t uPort;
|
---|
796 | uint32_t uAndVal;
|
---|
797 | uint32_t cbSize;
|
---|
798 | } Port;
|
---|
799 | uint64_t aRaw[2];
|
---|
800 | } s;
|
---|
801 | } PendingIO;
|
---|
802 |
|
---|
803 | /** The PAE PDPEs used with Nested Paging (only valid when
|
---|
804 | * VMCPU_FF_HM_UPDATE_PAE_PDPES is set). */
|
---|
805 | X86PDPE aPdpes[4];
|
---|
806 |
|
---|
807 | /** Current shadow paging mode. */
|
---|
808 | PGMMODE enmShadowMode;
|
---|
809 |
|
---|
810 | /** The CPU ID of the CPU currently owning the VMCS. Set in
|
---|
811 | * HMR0Enter and cleared in HMR0Leave. */
|
---|
812 | RTCPUID idEnteredCpu;
|
---|
813 |
|
---|
814 | /** To keep track of pending TLB shootdown pages. (SMP guest only) */
|
---|
815 | struct
|
---|
816 | {
|
---|
817 | RTGCPTR aPages[HM_MAX_TLB_SHOOTDOWN_PAGES];
|
---|
818 | uint32_t cPages;
|
---|
819 | uint32_t u32Padding; /**< Explicit alignment padding. */
|
---|
820 | } TlbShootdown;
|
---|
821 |
|
---|
822 | /** For saving stack space, the disassembler state is allocated here instead of
|
---|
823 | * on the stack. */
|
---|
824 | DISCPUSTATE DisState;
|
---|
825 |
|
---|
826 | STAMPROFILEADV StatEntry;
|
---|
827 | STAMPROFILEADV StatExit1;
|
---|
828 | STAMPROFILEADV StatExit2;
|
---|
829 | STAMPROFILEADV StatExitIO;
|
---|
830 | STAMPROFILEADV StatExitMovCRx;
|
---|
831 | STAMPROFILEADV StatExitXcptNmi;
|
---|
832 | STAMPROFILEADV StatLoadGuestState;
|
---|
833 | STAMPROFILEADV StatInGC;
|
---|
834 |
|
---|
835 | #if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
|
---|
836 | STAMPROFILEADV StatWorldSwitch3264;
|
---|
837 | #endif
|
---|
838 | STAMPROFILEADV StatPoke;
|
---|
839 | STAMPROFILEADV StatSpinPoke;
|
---|
840 | STAMPROFILEADV StatSpinPokeFailed;
|
---|
841 |
|
---|
842 | STAMCOUNTER StatInjectInterrupt;
|
---|
843 | STAMCOUNTER StatInjectXcpt;
|
---|
844 | STAMCOUNTER StatInjectPendingReflect;
|
---|
845 |
|
---|
846 | STAMCOUNTER StatExitAll;
|
---|
847 | STAMCOUNTER StatExitShadowNM;
|
---|
848 | STAMCOUNTER StatExitGuestNM;
|
---|
849 | STAMCOUNTER StatExitShadowPF; /* Misleading, currently used for MMIO #PFs as well. */
|
---|
850 | STAMCOUNTER StatExitShadowPFEM;
|
---|
851 | STAMCOUNTER StatExitGuestPF;
|
---|
852 | STAMCOUNTER StatExitGuestUD;
|
---|
853 | STAMCOUNTER StatExitGuestSS;
|
---|
854 | STAMCOUNTER StatExitGuestNP;
|
---|
855 | STAMCOUNTER StatExitGuestGP;
|
---|
856 | STAMCOUNTER StatExitGuestDE;
|
---|
857 | STAMCOUNTER StatExitGuestDB;
|
---|
858 | STAMCOUNTER StatExitGuestMF;
|
---|
859 | STAMCOUNTER StatExitGuestBP;
|
---|
860 | STAMCOUNTER StatExitGuestXF;
|
---|
861 | STAMCOUNTER StatExitGuestXcpUnk;
|
---|
862 | STAMCOUNTER StatExitInvlpg;
|
---|
863 | STAMCOUNTER StatExitInvd;
|
---|
864 | STAMCOUNTER StatExitWbinvd;
|
---|
865 | STAMCOUNTER StatExitPause;
|
---|
866 | STAMCOUNTER StatExitCpuid;
|
---|
867 | STAMCOUNTER StatExitRdtsc;
|
---|
868 | STAMCOUNTER StatExitRdtscp;
|
---|
869 | STAMCOUNTER StatExitRdpmc;
|
---|
870 | STAMCOUNTER StatExitRdrand;
|
---|
871 | STAMCOUNTER StatExitCli;
|
---|
872 | STAMCOUNTER StatExitSti;
|
---|
873 | STAMCOUNTER StatExitPushf;
|
---|
874 | STAMCOUNTER StatExitPopf;
|
---|
875 | STAMCOUNTER StatExitIret;
|
---|
876 | STAMCOUNTER StatExitInt;
|
---|
877 | STAMCOUNTER StatExitCRxWrite[16];
|
---|
878 | STAMCOUNTER StatExitCRxRead[16];
|
---|
879 | STAMCOUNTER StatExitDRxWrite;
|
---|
880 | STAMCOUNTER StatExitDRxRead;
|
---|
881 | STAMCOUNTER StatExitRdmsr;
|
---|
882 | STAMCOUNTER StatExitWrmsr;
|
---|
883 | STAMCOUNTER StatExitClts;
|
---|
884 | STAMCOUNTER StatExitXdtrAccess;
|
---|
885 | STAMCOUNTER StatExitHlt;
|
---|
886 | STAMCOUNTER StatExitMwait;
|
---|
887 | STAMCOUNTER StatExitMonitor;
|
---|
888 | STAMCOUNTER StatExitLmsw;
|
---|
889 | STAMCOUNTER StatExitIOWrite;
|
---|
890 | STAMCOUNTER StatExitIORead;
|
---|
891 | STAMCOUNTER StatExitIOStringWrite;
|
---|
892 | STAMCOUNTER StatExitIOStringRead;
|
---|
893 | STAMCOUNTER StatExitIntWindow;
|
---|
894 | STAMCOUNTER StatExitMaxResume;
|
---|
895 | STAMCOUNTER StatExitExtInt;
|
---|
896 | STAMCOUNTER StatExitHostNmiInGC;
|
---|
897 | STAMCOUNTER StatExitPreemptTimer;
|
---|
898 | STAMCOUNTER StatExitTprBelowThreshold;
|
---|
899 | STAMCOUNTER StatExitTaskSwitch;
|
---|
900 | STAMCOUNTER StatExitMtf;
|
---|
901 | STAMCOUNTER StatExitApicAccess;
|
---|
902 | STAMCOUNTER StatPendingHostIrq;
|
---|
903 |
|
---|
904 | STAMCOUNTER StatPreemptPreempting;
|
---|
905 | STAMCOUNTER StatPreemptSaveHostState;
|
---|
906 |
|
---|
907 | STAMCOUNTER StatFlushPage;
|
---|
908 | STAMCOUNTER StatFlushPageManual;
|
---|
909 | STAMCOUNTER StatFlushPhysPageManual;
|
---|
910 | STAMCOUNTER StatFlushTlb;
|
---|
911 | STAMCOUNTER StatFlushTlbManual;
|
---|
912 | STAMCOUNTER StatFlushTlbWorldSwitch;
|
---|
913 | STAMCOUNTER StatNoFlushTlbWorldSwitch;
|
---|
914 | STAMCOUNTER StatFlushEntire;
|
---|
915 | STAMCOUNTER StatFlushAsid;
|
---|
916 | STAMCOUNTER StatFlushNestedPaging;
|
---|
917 | STAMCOUNTER StatFlushTlbInvlpgVirt;
|
---|
918 | STAMCOUNTER StatFlushTlbInvlpgPhys;
|
---|
919 | STAMCOUNTER StatTlbShootdown;
|
---|
920 | STAMCOUNTER StatTlbShootdownFlush;
|
---|
921 |
|
---|
922 | STAMCOUNTER StatSwitchGuestIrq;
|
---|
923 | STAMCOUNTER StatSwitchHmToR3FF;
|
---|
924 | STAMCOUNTER StatSwitchExitToR3;
|
---|
925 | STAMCOUNTER StatSwitchLongJmpToR3;
|
---|
926 |
|
---|
927 | STAMCOUNTER StatTscOffset;
|
---|
928 | STAMCOUNTER StatTscIntercept;
|
---|
929 | STAMCOUNTER StatTscInterceptOverFlow;
|
---|
930 |
|
---|
931 | STAMCOUNTER StatExitReasonNpf;
|
---|
932 | STAMCOUNTER StatDRxArmed;
|
---|
933 | STAMCOUNTER StatDRxContextSwitch;
|
---|
934 | STAMCOUNTER StatDRxIoCheck;
|
---|
935 |
|
---|
936 | STAMCOUNTER StatLoadMinimal;
|
---|
937 | STAMCOUNTER StatLoadFull;
|
---|
938 |
|
---|
939 | STAMCOUNTER StatVmxCheckBadRmSelBase;
|
---|
940 | STAMCOUNTER StatVmxCheckBadRmSelLimit;
|
---|
941 | STAMCOUNTER StatVmxCheckRmOk;
|
---|
942 |
|
---|
943 | STAMCOUNTER StatVmxCheckBadSel;
|
---|
944 | STAMCOUNTER StatVmxCheckBadRpl;
|
---|
945 | STAMCOUNTER StatVmxCheckBadLdt;
|
---|
946 | STAMCOUNTER StatVmxCheckBadTr;
|
---|
947 | STAMCOUNTER StatVmxCheckPmOk;
|
---|
948 |
|
---|
949 | #if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
|
---|
950 | STAMCOUNTER StatFpu64SwitchBack;
|
---|
951 | STAMCOUNTER StatDebug64SwitchBack;
|
---|
952 | #endif
|
---|
953 |
|
---|
954 | #ifdef VBOX_WITH_STATISTICS
|
---|
955 | R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
|
---|
956 | R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
|
---|
957 | R3PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqs;
|
---|
958 | R0PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqsR0;
|
---|
959 | #endif
|
---|
960 | #ifdef HM_PROFILE_EXIT_DISPATCH
|
---|
961 | STAMPROFILEADV StatExitDispatch;
|
---|
962 | #endif
|
---|
963 | } HMCPU;
|
---|
964 | /** Pointer to HM VM instance data. */
|
---|
965 | typedef HMCPU *PHMCPU;
|
---|
966 |
|
---|
967 |
|
---|
968 | #ifdef IN_RING0
|
---|
969 |
|
---|
970 | VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpu(void);
|
---|
971 | VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpuEx(RTCPUID idCpu);
|
---|
972 |
|
---|
973 |
|
---|
974 | #ifdef VBOX_STRICT
|
---|
975 | VMMR0DECL(void) HMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
|
---|
976 | VMMR0DECL(void) HMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg);
|
---|
977 | #else
|
---|
978 | # define HMDumpRegs(a, b ,c) do { } while (0)
|
---|
979 | # define HMR0DumpDescriptor(a, b, c) do { } while (0)
|
---|
980 | #endif
|
---|
981 |
|
---|
982 | # ifdef VBOX_WITH_KERNEL_USING_XMM
|
---|
983 | DECLASM(int) HMR0VMXStartVMWrapXMM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu, PFNHMVMXSTARTVM pfnStartVM);
|
---|
984 | DECLASM(int) HMR0SVMRunWrapXMM(RTHCPHYS pVmcbHostPhys, RTHCPHYS pVmcbPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu, PFNHMSVMVMRUN pfnVMRun);
|
---|
985 | # endif
|
---|
986 |
|
---|
987 | # ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
|
---|
988 | /**
|
---|
989 | * Gets 64-bit GDTR and IDTR on darwin.
|
---|
990 | * @param pGdtr Where to store the 64-bit GDTR.
|
---|
991 | * @param pIdtr Where to store the 64-bit IDTR.
|
---|
992 | */
|
---|
993 | DECLASM(void) HMR0Get64bitGdtrAndIdtr(PX86XDTR64 pGdtr, PX86XDTR64 pIdtr);
|
---|
994 |
|
---|
995 | /**
|
---|
996 | * Gets 64-bit CR3 on darwin.
|
---|
997 | * @returns CR3
|
---|
998 | */
|
---|
999 | DECLASM(uint64_t) HMR0Get64bitCR3(void);
|
---|
1000 | # endif
|
---|
1001 |
|
---|
1002 | #endif /* IN_RING0 */
|
---|
1003 |
|
---|
1004 | /** @} */
|
---|
1005 |
|
---|
1006 | RT_C_DECLS_END
|
---|
1007 |
|
---|
1008 | #endif
|
---|
1009 |
|
---|