VirtualBox

source: vbox/trunk/src/VBox/VMM/include/HMInternal.h@ 60850

Last change on this file since 60850 was 60850, checked in by vboxsync, 9 years ago

HM: Dropped HMR0SavePendingIOPortWrite and associated code (leaving HMR0SavePendingIOPortRead), since IOMIOPortWrite won't be returning VINF_IOM_R3_IOPORT_WRITE any more but rather VINF_IOM_R3_IOPORT_COMMIT_WRITE.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 42.8 KB
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1/* $Id: HMInternal.h 60850 2016-05-05 15:43:19Z vboxsync $ */
2/** @file
3 * HM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2015 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef ___HMInternal_h
19#define ___HMInternal_h
20
21#include <VBox/cdefs.h>
22#include <VBox/types.h>
23#include <VBox/vmm/em.h>
24#include <VBox/vmm/stam.h>
25#include <VBox/dis.h>
26#include <VBox/vmm/hm.h>
27#include <VBox/vmm/hm_vmx.h>
28#include <VBox/vmm/pgm.h>
29#include <VBox/vmm/cpum.h>
30#include <iprt/memobj.h>
31#include <iprt/cpuset.h>
32#include <iprt/mp.h>
33#include <iprt/avl.h>
34#include <iprt/string.h>
35
36#if defined(RT_OS_DARWIN) && HC_ARCH_BITS == 32
37# error "32-bit darwin is no longer supported. Go back to 4.3 or earlier!"
38#endif
39
40#if HC_ARCH_BITS == 64 || defined (VBOX_WITH_64_BITS_GUESTS)
41/* Enable 64 bits guest support. */
42# define VBOX_ENABLE_64_BITS_GUESTS
43#endif
44
45#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
46# define VMX_USE_CACHED_VMCS_ACCESSES
47#endif
48
49/** @def HM_PROFILE_EXIT_DISPATCH
50 * Enables profiling of the VM exit handler dispatching. */
51#if 0 || defined(DOXYGEN_RUNNING)
52# define HM_PROFILE_EXIT_DISPATCH
53#endif
54
55RT_C_DECLS_BEGIN
56
57
58/** @defgroup grp_hm_int Internal
59 * @ingroup grp_hm
60 * @internal
61 * @{
62 */
63
64/** @def HMCPU_CF_CLEAR
65 * Clears a HM-context flag.
66 *
67 * @param pVCpu The cross context virtual CPU structure.
68 * @param fFlag The flag to clear.
69 */
70#define HMCPU_CF_CLEAR(pVCpu, fFlag) (ASMAtomicUoAndU32(&(pVCpu)->hm.s.fContextUseFlags, ~(fFlag)))
71
72/** @def HMCPU_CF_SET
73 * Sets a HM-context flag.
74 *
75 * @param pVCpu The cross context virtual CPU structure.
76 * @param fFlag The flag to set.
77 */
78#define HMCPU_CF_SET(pVCpu, fFlag) (ASMAtomicUoOrU32(&(pVCpu)->hm.s.fContextUseFlags, (fFlag)))
79
80/** @def HMCPU_CF_IS_SET
81 * Checks if all the flags in the specified HM-context set is pending.
82 *
83 * @param pVCpu The cross context virtual CPU structure.
84 * @param fFlag The flag to check.
85 */
86#define HMCPU_CF_IS_SET(pVCpu, fFlag) ((ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags) & (fFlag)) == (fFlag))
87
88/** @def HMCPU_CF_IS_PENDING
89 * Checks if one or more of the flags in the specified HM-context set is
90 * pending.
91 *
92 * @param pVCpu The cross context virtual CPU structure.
93 * @param fFlags The flags to check for.
94 */
95#define HMCPU_CF_IS_PENDING(pVCpu, fFlags) RT_BOOL(ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags) & (fFlags))
96
97/** @def HMCPU_CF_IS_PENDING_ONLY
98 * Checks if -only- one or more of the specified HM-context flags is pending.
99 *
100 * @param pVCpu The cross context virtual CPU structure.
101 * @param fFlags The flags to check for.
102 */
103#define HMCPU_CF_IS_PENDING_ONLY(pVCpu, fFlags) !RT_BOOL(ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags) & ~(fFlags))
104
105/** @def HMCPU_CF_IS_SET_ONLY
106 * Checks if -only- all the flags in the specified HM-context set is pending.
107 *
108 * @param pVCpu The cross context virtual CPU structure.
109 * @param fFlags The flags to check for.
110 */
111#define HMCPU_CF_IS_SET_ONLY(pVCpu, fFlags) (ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags) == (fFlags))
112
113/** @def HMCPU_CF_RESET_TO
114 * Resets the HM-context flags to the specified value.
115 *
116 * @param pVCpu The cross context virtual CPU structure.
117 * @param fFlags The new value.
118 */
119#define HMCPU_CF_RESET_TO(pVCpu, fFlags) (ASMAtomicUoWriteU32(&(pVCpu)->hm.s.fContextUseFlags, (fFlags)))
120
121/** @def HMCPU_CF_VALUE
122 * Returns the current HM-context flags value.
123 *
124 * @param pVCpu The cross context virtual CPU structure.
125 */
126#define HMCPU_CF_VALUE(pVCpu) (ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags))
127
128
129/** Resets/initializes the VM-exit/\#VMEXIT history array. */
130#define HMCPU_EXIT_HISTORY_RESET(pVCpu) (memset(&(pVCpu)->hm.s.auExitHistory, 0xff, sizeof((pVCpu)->hm.s.auExitHistory)))
131
132/** Updates the VM-exit/\#VMEXIT history array. */
133#define HMCPU_EXIT_HISTORY_ADD(pVCpu, a_ExitReason) \
134 do { \
135 AssertMsg((pVCpu)->hm.s.idxExitHistoryFree < RT_ELEMENTS((pVCpu)->hm.s.auExitHistory), ("%u\n", (pVCpu)->hm.s.idxExitHistoryFree)); \
136 (pVCpu)->hm.s.auExitHistory[(pVCpu)->hm.s.idxExitHistoryFree++] = (uint16_t)(a_ExitReason); \
137 if ((pVCpu)->hm.s.idxExitHistoryFree == RT_ELEMENTS((pVCpu)->hm.s.auExitHistory)) \
138 (pVCpu)->hm.s.idxExitHistoryFree = 0; \
139 (pVCpu)->hm.s.auExitHistory[(pVCpu)->hm.s.idxExitHistoryFree] = UINT16_MAX; \
140 } while (0)
141
142/** Maximum number of exit reason statistics counters. */
143#define MAX_EXITREASON_STAT 0x100
144#define MASK_EXITREASON_STAT 0xff
145#define MASK_INJECT_IRQ_STAT 0xff
146
147/** @name HM changed flags.
148 * These flags are used to keep track of which important registers that
149 * have been changed since last they were reset.
150 * @{
151 */
152#define HM_CHANGED_GUEST_CR0 RT_BIT(0) /* Shared */
153#define HM_CHANGED_GUEST_CR3 RT_BIT(1)
154#define HM_CHANGED_GUEST_CR4 RT_BIT(2)
155#define HM_CHANGED_GUEST_GDTR RT_BIT(3)
156#define HM_CHANGED_GUEST_IDTR RT_BIT(4)
157#define HM_CHANGED_GUEST_LDTR RT_BIT(5)
158#define HM_CHANGED_GUEST_TR RT_BIT(6)
159#define HM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(7)
160#define HM_CHANGED_GUEST_DEBUG RT_BIT(8) /* Shared */
161#define HM_CHANGED_GUEST_RIP RT_BIT(9)
162#define HM_CHANGED_GUEST_RSP RT_BIT(10)
163#define HM_CHANGED_GUEST_RFLAGS RT_BIT(11)
164#define HM_CHANGED_GUEST_CR2 RT_BIT(12)
165#define HM_CHANGED_GUEST_SYSENTER_CS_MSR RT_BIT(13)
166#define HM_CHANGED_GUEST_SYSENTER_EIP_MSR RT_BIT(14)
167#define HM_CHANGED_GUEST_SYSENTER_ESP_MSR RT_BIT(15)
168#define HM_CHANGED_GUEST_EFER_MSR RT_BIT(16)
169#define HM_CHANGED_GUEST_LAZY_MSRS RT_BIT(17) /* Shared */
170#define HM_CHANGED_GUEST_XCPT_INTERCEPTS RT_BIT(18)
171/* VT-x specific state. */
172#define HM_CHANGED_VMX_GUEST_AUTO_MSRS RT_BIT(19)
173#define HM_CHANGED_VMX_GUEST_ACTIVITY_STATE RT_BIT(20)
174#define HM_CHANGED_VMX_GUEST_APIC_STATE RT_BIT(21)
175#define HM_CHANGED_VMX_ENTRY_CTLS RT_BIT(22)
176#define HM_CHANGED_VMX_EXIT_CTLS RT_BIT(23)
177/* AMD-V specific state. */
178#define HM_CHANGED_SVM_GUEST_APIC_STATE RT_BIT(19)
179#define HM_CHANGED_SVM_RESERVED1 RT_BIT(20)
180#define HM_CHANGED_SVM_RESERVED2 RT_BIT(21)
181#define HM_CHANGED_SVM_RESERVED3 RT_BIT(22)
182#define HM_CHANGED_SVM_RESERVED4 RT_BIT(23)
183
184#define HM_CHANGED_ALL_GUEST ( HM_CHANGED_GUEST_CR0 \
185 | HM_CHANGED_GUEST_CR3 \
186 | HM_CHANGED_GUEST_CR4 \
187 | HM_CHANGED_GUEST_GDTR \
188 | HM_CHANGED_GUEST_IDTR \
189 | HM_CHANGED_GUEST_LDTR \
190 | HM_CHANGED_GUEST_TR \
191 | HM_CHANGED_GUEST_SEGMENT_REGS \
192 | HM_CHANGED_GUEST_DEBUG \
193 | HM_CHANGED_GUEST_RIP \
194 | HM_CHANGED_GUEST_RSP \
195 | HM_CHANGED_GUEST_RFLAGS \
196 | HM_CHANGED_GUEST_CR2 \
197 | HM_CHANGED_GUEST_SYSENTER_CS_MSR \
198 | HM_CHANGED_GUEST_SYSENTER_EIP_MSR \
199 | HM_CHANGED_GUEST_SYSENTER_ESP_MSR \
200 | HM_CHANGED_GUEST_EFER_MSR \
201 | HM_CHANGED_GUEST_LAZY_MSRS \
202 | HM_CHANGED_GUEST_XCPT_INTERCEPTS \
203 | HM_CHANGED_VMX_GUEST_AUTO_MSRS \
204 | HM_CHANGED_VMX_GUEST_ACTIVITY_STATE \
205 | HM_CHANGED_VMX_GUEST_APIC_STATE \
206 | HM_CHANGED_VMX_ENTRY_CTLS \
207 | HM_CHANGED_VMX_EXIT_CTLS)
208
209#define HM_CHANGED_HOST_CONTEXT RT_BIT(24)
210
211/* Bits shared between host and guest. */
212#define HM_CHANGED_HOST_GUEST_SHARED_STATE ( HM_CHANGED_GUEST_CR0 \
213 | HM_CHANGED_GUEST_DEBUG \
214 | HM_CHANGED_GUEST_LAZY_MSRS)
215/** @} */
216
217/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
218#define HM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
219/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
220#define HM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2 * PAGE_SIZE + 1)
221/** Total guest mapped memory needed. */
222#define HM_VTX_TOTAL_DEVHEAP_MEM (HM_EPT_IDENTITY_PG_TABLE_SIZE + HM_VTX_TSS_SIZE)
223
224
225/** @name Macros for enabling and disabling preemption.
226 * These are really just for hiding the RTTHREADPREEMPTSTATE and asserting that
227 * preemption has already been disabled when there is no context hook.
228 * @{ */
229#ifdef VBOX_STRICT
230# define HM_DISABLE_PREEMPT() \
231 RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
232 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD) || VMMR0ThreadCtxHookIsEnabled(pVCpu)); \
233 RTThreadPreemptDisable(&PreemptStateInternal)
234#else
235# define HM_DISABLE_PREEMPT() \
236 RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
237 RTThreadPreemptDisable(&PreemptStateInternal)
238#endif /* VBOX_STRICT */
239#define HM_RESTORE_PREEMPT() do { RTThreadPreemptRestore(&PreemptStateInternal); } while(0)
240/** @} */
241
242
243/** Enable for TPR guest patching. */
244#define VBOX_HM_WITH_GUEST_PATCHING
245
246/** @name HM saved state versions
247 * @{
248 */
249#ifdef VBOX_HM_WITH_GUEST_PATCHING
250# define HM_SAVED_STATE_VERSION 5
251# define HM_SAVED_STATE_VERSION_NO_PATCHING 4
252#else
253# define HM_SAVED_STATE_VERSION 4
254# define HM_SAVED_STATE_VERSION_NO_PATCHING 4
255#endif
256#define HM_SAVED_STATE_VERSION_2_0_X 3
257/** @} */
258
259/**
260 * Global per-cpu information. (host)
261 */
262typedef struct HMGLOBALCPUINFO
263{
264 /** The CPU ID. */
265 RTCPUID idCpu;
266 /** The VM_HSAVE_AREA (AMD-V) / VMXON region (Intel) memory backing. */
267 RTR0MEMOBJ hMemObj;
268 /** The physical address of the first page in hMemObj (it's a
269 * physcially contigous allocation if it spans multiple pages). */
270 RTHCPHYS HCPhysMemObj;
271 /** The address of the memory (for pfnEnable). */
272 void *pvMemObj;
273 /** Current ASID (AMD-V) / VPID (Intel). */
274 uint32_t uCurrentAsid;
275 /** TLB flush count. */
276 uint32_t cTlbFlushes;
277 /** Whether to flush each new ASID/VPID before use. */
278 bool fFlushAsidBeforeUse;
279 /** Configured for VT-x or AMD-V. */
280 bool fConfigured;
281 /** Set if the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active. */
282 bool fIgnoreAMDVInUseError;
283 /** In use by our code. (for power suspend) */
284 volatile bool fInUse;
285} HMGLOBALCPUINFO;
286/** Pointer to the per-cpu global information. */
287typedef HMGLOBALCPUINFO *PHMGLOBALCPUINFO;
288
289typedef enum
290{
291 HMPENDINGIO_INVALID = 0,
292 HMPENDINGIO_PORT_READ,
293 /* not implemented: HMPENDINGIO_STRING_READ, */
294 /* not implemented: HMPENDINGIO_STRING_WRITE, */
295 /** The usual 32-bit paranoia. */
296 HMPENDINGIO_32BIT_HACK = 0x7fffffff
297} HMPENDINGIO;
298
299
300typedef enum
301{
302 HMTPRINSTR_INVALID,
303 HMTPRINSTR_READ,
304 HMTPRINSTR_READ_SHR4,
305 HMTPRINSTR_WRITE_REG,
306 HMTPRINSTR_WRITE_IMM,
307 HMTPRINSTR_JUMP_REPLACEMENT,
308 /** The usual 32-bit paranoia. */
309 HMTPRINSTR_32BIT_HACK = 0x7fffffff
310} HMTPRINSTR;
311
312typedef struct
313{
314 /** The key is the address of patched instruction. (32 bits GC ptr) */
315 AVLOU32NODECORE Core;
316 /** Original opcode. */
317 uint8_t aOpcode[16];
318 /** Instruction size. */
319 uint32_t cbOp;
320 /** Replacement opcode. */
321 uint8_t aNewOpcode[16];
322 /** Replacement instruction size. */
323 uint32_t cbNewOp;
324 /** Instruction type. */
325 HMTPRINSTR enmType;
326 /** Source operand. */
327 uint32_t uSrcOperand;
328 /** Destination operand. */
329 uint32_t uDstOperand;
330 /** Number of times the instruction caused a fault. */
331 uint32_t cFaults;
332 /** Patch address of the jump replacement. */
333 RTGCPTR32 pJumpTarget;
334} HMTPRPATCH;
335/** Pointer to HMTPRPATCH. */
336typedef HMTPRPATCH *PHMTPRPATCH;
337
338/**
339 * Switcher function, HC to the special 64-bit RC.
340 *
341 * @param pVM The cross context VM structure.
342 * @param offCpumVCpu Offset from pVM->cpum to pVM->aCpus[idCpu].cpum.
343 * @returns Return code indicating the action to take.
344 */
345typedef DECLCALLBACK(int) FNHMSWITCHERHC(PVM pVM, uint32_t offCpumVCpu);
346/** Pointer to switcher function. */
347typedef FNHMSWITCHERHC *PFNHMSWITCHERHC;
348
349/**
350 * HM VM Instance data.
351 * Changes to this must checked against the padding of the hm union in VM!
352 */
353typedef struct HM
354{
355 /** Set when we've initialized VMX or SVM. */
356 bool fInitialized;
357 /** Set if nested paging is enabled. */
358 bool fNestedPaging;
359 /** Set if nested paging is allowed. */
360 bool fAllowNestedPaging;
361 /** Set if large pages are enabled (requires nested paging). */
362 bool fLargePages;
363 /** Set if we can support 64-bit guests or not. */
364 bool fAllow64BitGuests;
365 /** Set if an IO-APIC is configured for this VM. */
366 bool fHasIoApic;
367 /** Set when TPR patching is allowed. */
368 bool fTprPatchingAllowed;
369 /** Set when we initialize VT-x or AMD-V once for all CPUs. */
370 bool fGlobalInit;
371 /** Set when TPR patching is active. */
372 bool fTPRPatchingActive;
373 /** Set when the debug facility has breakpoints/events enabled that requires
374 * us to use the debug execution loop in ring-0. */
375 bool fUseDebugLoop;
376 /** Set if hardware APIC virtualization is enabled. */
377 bool fVirtApicRegs;
378 /** Set if posted interrupt processing is enabled. */
379 bool fPostedIntrs;
380
381 /** Host kernel flags that HM might need to know (SUPKERNELFEATURES_XXX). */
382 uint32_t fHostKernelFeatures;
383
384 /** Maximum ASID allowed. */
385 uint32_t uMaxAsid;
386 /** The maximum number of resumes loops allowed in ring-0 (safety precaution).
387 * This number is set much higher when RTThreadPreemptIsPending is reliable. */
388 uint32_t cMaxResumeLoops;
389
390 /** Guest allocated memory for patching purposes. */
391 RTGCPTR pGuestPatchMem;
392 /** Current free pointer inside the patch block. */
393 RTGCPTR pFreeGuestPatchMem;
394 /** Size of the guest patch memory block. */
395 uint32_t cbGuestPatchMem;
396 uint32_t u32Alignment0;
397
398#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
399 /** 32 to 64 bits switcher entrypoint. */
400 R0PTRTYPE(PFNHMSWITCHERHC) pfnHost32ToGuest64R0;
401 RTR0PTR pvR0Alignment0;
402#endif
403
404 struct
405 {
406 /** Set by the ring-0 side of HM to indicate VMX is supported by the
407 * CPU. */
408 bool fSupported;
409 /** Set when we've enabled VMX. */
410 bool fEnabled;
411 /** Set if VPID is supported. */
412 bool fVpid;
413 /** Set if VT-x VPID is allowed. */
414 bool fAllowVpid;
415 /** Set if unrestricted guest execution is in use (real and protected mode without paging). */
416 bool fUnrestrictedGuest;
417 /** Set if unrestricted guest execution is allowed to be used. */
418 bool fAllowUnrestricted;
419 /** Whether we're using the preemption timer or not. */
420 bool fUsePreemptTimer;
421 /** The shift mask employed by the VMX-Preemption timer. */
422 uint8_t cPreemptTimerShift;
423
424 /** Virtual address of the TSS page used for real mode emulation. */
425 R3PTRTYPE(PVBOXTSS) pRealModeTSS;
426 /** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
427 R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
428
429 /** Physical address of the APIC-access page. */
430 RTHCPHYS HCPhysApicAccess;
431 /** R0 memory object for the APIC-access page. */
432 RTR0MEMOBJ hMemObjApicAccess;
433 /** Virtual address of the APIC-access page. */
434 R0PTRTYPE(uint8_t *) pbApicAccess;
435
436#ifdef VBOX_WITH_CRASHDUMP_MAGIC
437 RTHCPHYS HCPhysScratch;
438 RTR0MEMOBJ hMemObjScratch;
439 R0PTRTYPE(uint8_t *) pbScratch;
440#endif
441
442 /** Internal Id of which flush-handler to use for tagged-TLB entries. */
443 uint32_t uFlushTaggedTlb;
444
445 /** Pause-loop exiting (PLE) gap in ticks. */
446 uint32_t cPleGapTicks;
447 /** Pause-loop exiting (PLE) window in ticks. */
448 uint32_t cPleWindowTicks;
449 uint32_t u32Alignment0;
450
451 /** Host CR4 value (set by ring-0 VMX init) */
452 uint64_t u64HostCr4;
453 /** Host SMM monitor control (set by ring-0 VMX init) */
454 uint64_t u64HostSmmMonitorCtl;
455 /** Host EFER value (set by ring-0 VMX init) */
456 uint64_t u64HostEfer;
457 /** Whether the CPU supports VMCS fields for swapping EFER. */
458 bool fSupportsVmcsEfer;
459 uint8_t u8Alignment2[7];
460
461 /** VMX MSR values. */
462 VMXMSRS Msrs;
463
464 /** Flush types for invept & invvpid; they depend on capabilities. */
465 VMXFLUSHEPT enmFlushEpt;
466 VMXFLUSHVPID enmFlushVpid;
467
468 /** Host-physical address for a failing VMXON instruction. */
469 RTHCPHYS HCPhysVmxEnableError;
470 } vmx;
471
472 struct
473 {
474 /** Set by the ring-0 side of HM to indicate SVM is supported by the
475 * CPU. */
476 bool fSupported;
477 /** Set when we've enabled SVM. */
478 bool fEnabled;
479 /** Set if erratum 170 affects the AMD cpu. */
480 bool fAlwaysFlushTLB;
481 /** Set when the hack to ignore VERR_SVM_IN_USE is active. */
482 bool fIgnoreInUseError;
483 uint8_t u8Alignment0[4];
484
485 /** Physical address of the IO bitmap (12kb). */
486 RTHCPHYS HCPhysIOBitmap;
487 /** R0 memory object for the IO bitmap (12kb). */
488 RTR0MEMOBJ hMemObjIOBitmap;
489 /** Virtual address of the IO bitmap. */
490 R0PTRTYPE(void *) pvIOBitmap;
491
492 /* HWCR MSR (for diagnostics) */
493 uint64_t u64MsrHwcr;
494
495 /** SVM revision. */
496 uint32_t u32Rev;
497 /** SVM feature bits from cpuid 0x8000000a */
498 uint32_t u32Features;
499
500 /** Pause filter counter. */
501 uint16_t cPauseFilter;
502 /** Pause filter treshold in ticks. */
503 uint16_t cPauseFilterThresholdTicks;
504 uint32_t u32Alignment0;
505 } svm;
506
507 /**
508 * AVL tree with all patches (active or disabled) sorted by guest instruction
509 * address.
510 */
511 AVLOU32TREE PatchTree;
512 uint32_t cPatches;
513 HMTPRPATCH aPatches[64];
514
515 struct
516 {
517 uint32_t u32AMDFeatureECX;
518 uint32_t u32AMDFeatureEDX;
519 } cpuid;
520
521 /** Saved error from detection */
522 int32_t lLastError;
523
524 /** HMR0Init was run */
525 bool fHMR0Init;
526 bool u8Alignment1[3];
527
528 STAMCOUNTER StatTprPatchSuccess;
529 STAMCOUNTER StatTprPatchFailure;
530 STAMCOUNTER StatTprReplaceSuccessCr8;
531 STAMCOUNTER StatTprReplaceSuccessVmc;
532 STAMCOUNTER StatTprReplaceFailure;
533} HM;
534/** Pointer to HM VM instance data. */
535typedef HM *PHM;
536
537AssertCompileMemberAlignment(HM, StatTprPatchSuccess, 8);
538
539/* Maximum number of cached entries. */
540#define VMCSCACHE_MAX_ENTRY 128
541
542/**
543 * Structure for storing read and write VMCS actions.
544 */
545typedef struct VMCSCACHE
546{
547#ifdef VBOX_WITH_CRASHDUMP_MAGIC
548 /* Magic marker for searching in crash dumps. */
549 uint8_t aMagic[16];
550 uint64_t uMagic;
551 uint64_t u64TimeEntry;
552 uint64_t u64TimeSwitch;
553 uint64_t cResume;
554 uint64_t interPD;
555 uint64_t pSwitcher;
556 uint32_t uPos;
557 uint32_t idCpu;
558#endif
559 /* CR2 is saved here for EPT syncing. */
560 uint64_t cr2;
561 struct
562 {
563 uint32_t cValidEntries;
564 uint32_t uAlignment;
565 uint32_t aField[VMCSCACHE_MAX_ENTRY];
566 uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
567 } Write;
568 struct
569 {
570 uint32_t cValidEntries;
571 uint32_t uAlignment;
572 uint32_t aField[VMCSCACHE_MAX_ENTRY];
573 uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
574 } Read;
575#ifdef VBOX_STRICT
576 struct
577 {
578 RTHCPHYS HCPhysCpuPage;
579 RTHCPHYS HCPhysVmcs;
580 RTGCPTR pCache;
581 RTGCPTR pCtx;
582 } TestIn;
583 struct
584 {
585 RTHCPHYS HCPhysVmcs;
586 RTGCPTR pCache;
587 RTGCPTR pCtx;
588 uint64_t eflags;
589 uint64_t cr8;
590 } TestOut;
591 struct
592 {
593 uint64_t param1;
594 uint64_t param2;
595 uint64_t param3;
596 uint64_t param4;
597 } ScratchPad;
598#endif
599} VMCSCACHE;
600/** Pointer to VMCSCACHE. */
601typedef VMCSCACHE *PVMCSCACHE;
602AssertCompileSizeAlignment(VMCSCACHE, 8);
603
604/**
605 * VMX StartVM function.
606 *
607 * @returns VBox status code (no informational stuff).
608 * @param fResume Whether to use VMRESUME (true) or VMLAUNCH (false).
609 * @param pCtx The CPU register context.
610 * @param pCache The VMCS cache.
611 * @param pVM Pointer to the cross context VM structure.
612 * @param pVCpu Pointer to the cross context per-CPU structure.
613 */
614typedef DECLCALLBACK(int) FNHMVMXSTARTVM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);
615/** Pointer to a VMX StartVM function. */
616typedef R0PTRTYPE(FNHMVMXSTARTVM *) PFNHMVMXSTARTVM;
617
618/** SVM VMRun function. */
619typedef DECLCALLBACK(int) FNHMSVMVMRUN(RTHCPHYS pVmcbHostPhys, RTHCPHYS pVmcbPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu);
620/** Pointer to a SVM VMRun function. */
621typedef R0PTRTYPE(FNHMSVMVMRUN *) PFNHMSVMVMRUN;
622
623/**
624 * HM VMCPU Instance data.
625 *
626 * Note! If you change members of this struct, make sure to check if the
627 * assembly counterpart in HMInternal.mac needs to be updated as well.
628 */
629typedef struct HMCPU
630{
631 /** Set if we need to flush the TLB during the world switch. */
632 bool fForceTLBFlush;
633 /** Set when we're using VT-x or AMD-V at that moment. */
634 bool fActive;
635 /** Set when the TLB has been checked until we return from the world switch. */
636 volatile bool fCheckedTLBFlush;
637 /** Whether we've completed the inner HM leave function. */
638 bool fLeaveDone;
639 /** Whether we're using the hyper DR7 or guest DR7. */
640 bool fUsingHyperDR7;
641 /** Whether to preload the guest-FPU state to avoid \#NM VM-exit overhead. */
642 bool fPreloadGuestFpu;
643 /** Set if XCR0 needs to be loaded and saved when entering and exiting guest
644 * code execution. */
645 bool fLoadSaveGuestXcr0;
646
647 /** Whether we should use the debug loop because of single stepping or special
648 * debug breakpoints / events are armed. */
649 bool fUseDebugLoop;
650 /** Whether we are currently executing in the debug loop.
651 * Mainly for assertions. */
652 bool fUsingDebugLoop;
653 /** Set if we using the debug loop and wish to intercept RDTSC. */
654 bool fDebugWantRdTscExit;
655 /** Whether we're executing a single instruction. */
656 bool fSingleInstruction;
657 /** Set if we need to clear the trap flag because of single stepping. */
658 bool fClearTrapFlag;
659
660 /** Whether \#UD needs to be intercepted (required by certain GIM providers). */
661 bool fGIMTrapXcptUD;
662 /** Whether paravirt. hypercalls are enabled. */
663 bool fHypercallsEnabled;
664 uint8_t u8Alignment0[2];
665
666 /** World switch exit counter. */
667 volatile uint32_t cWorldSwitchExits;
668 /** HM_CHANGED_* flags. */
669 volatile uint32_t fContextUseFlags;
670 /** Id of the last cpu we were executing code on (NIL_RTCPUID for the first
671 * time). */
672 RTCPUID idLastCpu;
673 /** TLB flush count. */
674 uint32_t cTlbFlushes;
675 /** Current ASID in use by the VM. */
676 uint32_t uCurrentAsid;
677 /** An additional error code used for some gurus. */
678 uint32_t u32HMError;
679 /** Host's TSC_AUX MSR (used when RDTSCP doesn't cause VM-exits). */
680 uint64_t u64HostTscAux;
681
682 struct
683 {
684 /** Ring 0 handlers for VT-x. */
685 PFNHMVMXSTARTVM pfnStartVM;
686#if HC_ARCH_BITS == 32
687 uint32_t u32Alignment0;
688#endif
689 /** Current VMX_VMCS32_CTRL_PIN_EXEC. */
690 uint32_t u32PinCtls;
691 /** Current VMX_VMCS32_CTRL_PROC_EXEC. */
692 uint32_t u32ProcCtls;
693 /** Current VMX_VMCS32_CTRL_PROC_EXEC2. */
694 uint32_t u32ProcCtls2;
695 /** Current VMX_VMCS32_CTRL_EXIT. */
696 uint32_t u32ExitCtls;
697 /** Current VMX_VMCS32_CTRL_ENTRY. */
698 uint32_t u32EntryCtls;
699
700 /** Current CR0 mask. */
701 uint32_t u32CR0Mask;
702 /** Current CR4 mask. */
703 uint32_t u32CR4Mask;
704 /** Current exception bitmap. */
705 uint32_t u32XcptBitmap;
706 /** The updated-guest-state mask. */
707 volatile uint32_t fUpdatedGuestState;
708 uint32_t u32Alignment1;
709
710 /** Physical address of the VM control structure (VMCS). */
711 RTHCPHYS HCPhysVmcs;
712 /** R0 memory object for the VM control structure (VMCS). */
713 RTR0MEMOBJ hMemObjVmcs;
714 /** Virtual address of the VM control structure (VMCS). */
715 R0PTRTYPE(void *) pvVmcs;
716
717 /** Physical address of the virtual APIC page for TPR caching. */
718 RTHCPHYS HCPhysVirtApic;
719 /** R0 memory object for the virtual APIC page for TPR caching. */
720 RTR0MEMOBJ hMemObjVirtApic;
721 /** Virtual address of the virtual APIC page for TPR caching. */
722 R0PTRTYPE(uint8_t *) pbVirtApic;
723
724 /** Physical address of the MSR bitmap. */
725 RTHCPHYS HCPhysMsrBitmap;
726 /** R0 memory object for the MSR bitmap. */
727 RTR0MEMOBJ hMemObjMsrBitmap;
728 /** Virtual address of the MSR bitmap. */
729 R0PTRTYPE(void *) pvMsrBitmap;
730
731 /** Physical address of the VM-entry MSR-load and VM-exit MSR-store area (used
732 * for guest MSRs). */
733 RTHCPHYS HCPhysGuestMsr;
734 /** R0 memory object of the VM-entry MSR-load and VM-exit MSR-store area
735 * (used for guest MSRs). */
736 RTR0MEMOBJ hMemObjGuestMsr;
737 /** Virtual address of the VM-entry MSR-load and VM-exit MSR-store area (used
738 * for guest MSRs). */
739 R0PTRTYPE(void *) pvGuestMsr;
740
741 /** Physical address of the VM-exit MSR-load area (used for host MSRs). */
742 RTHCPHYS HCPhysHostMsr;
743 /** R0 memory object for the VM-exit MSR-load area (used for host MSRs). */
744 RTR0MEMOBJ hMemObjHostMsr;
745 /** Virtual address of the VM-exit MSR-load area (used for host MSRs). */
746 R0PTRTYPE(void *) pvHostMsr;
747
748 /** Current EPTP. */
749 RTHCPHYS HCPhysEPTP;
750
751 /** Number of guest/host MSR pairs in the auto-load/store area. */
752 uint32_t cMsrs;
753 /** Whether the host MSR values are up-to-date in the auto-load/store area. */
754 bool fUpdatedHostMsrs;
755 uint8_t u8Alignment0[3];
756
757 /** Host LSTAR MSR value to restore lazily while leaving VT-x. */
758 uint64_t u64HostLStarMsr;
759 /** Host STAR MSR value to restore lazily while leaving VT-x. */
760 uint64_t u64HostStarMsr;
761 /** Host SF_MASK MSR value to restore lazily while leaving VT-x. */
762 uint64_t u64HostSFMaskMsr;
763 /** Host KernelGS-Base MSR value to restore lazily while leaving VT-x. */
764 uint64_t u64HostKernelGSBaseMsr;
765 /** A mask of which MSRs have been swapped and need restoration. */
766 uint32_t fLazyMsrs;
767 uint32_t u32Alignment2;
768
769 /** The cached APIC-base MSR used for identifying when to map the HC physical APIC-access page. */
770 uint64_t u64MsrApicBase;
771 /** Last use TSC offset value. (cached) */
772 uint64_t u64TSCOffset;
773
774 /** VMCS cache. */
775 VMCSCACHE VMCSCache;
776
777 /** Real-mode emulation state. */
778 struct
779 {
780 X86DESCATTR AttrCS;
781 X86DESCATTR AttrDS;
782 X86DESCATTR AttrES;
783 X86DESCATTR AttrFS;
784 X86DESCATTR AttrGS;
785 X86DESCATTR AttrSS;
786 X86EFLAGS Eflags;
787 uint32_t fRealOnV86Active;
788 } RealMode;
789
790 /** VT-x error-reporting (mainly for ring-3 propagation). */
791 struct
792 {
793 uint64_t u64VMCSPhys;
794 uint32_t u32VMCSRevision;
795 uint32_t u32InstrError;
796 uint32_t u32ExitReason;
797 RTCPUID idEnteredCpu;
798 RTCPUID idCurrentCpu;
799 uint32_t u32Alignment0;
800 } LastError;
801
802 /** Current state of the VMCS. */
803 uint32_t uVmcsState;
804 /** Which host-state bits to restore before being preempted. */
805 uint32_t fRestoreHostFlags;
806 /** The host-state restoration structure. */
807 VMXRESTOREHOST RestoreHost;
808
809 /** Set if guest was executing in real mode (extra checks). */
810 bool fWasInRealMode;
811 uint8_t u8Alignment1[7];
812 } vmx;
813
814 struct
815 {
816 /** Ring 0 handlers for VT-x. */
817 PFNHMSVMVMRUN pfnVMRun;
818#if HC_ARCH_BITS == 32
819 uint32_t u32Alignment0;
820#endif
821
822 /** Physical address of the host VMCB which holds additional host-state. */
823 RTHCPHYS HCPhysVmcbHost;
824 /** R0 memory object for the host VMCB which holds additional host-state. */
825 RTR0MEMOBJ hMemObjVmcbHost;
826 /** Virtual address of the host VMCB which holds additional host-state. */
827 R0PTRTYPE(void *) pvVmcbHost;
828
829 /** Physical address of the guest VMCB. */
830 RTHCPHYS HCPhysVmcb;
831 /** R0 memory object for the guest VMCB. */
832 RTR0MEMOBJ hMemObjVmcb;
833 /** Virtual address of the guest VMCB. */
834 R0PTRTYPE(void *) pvVmcb;
835
836 /** Physical address of the MSR bitmap (8 KB). */
837 RTHCPHYS HCPhysMsrBitmap;
838 /** R0 memory object for the MSR bitmap (8 KB). */
839 RTR0MEMOBJ hMemObjMsrBitmap;
840 /** Virtual address of the MSR bitmap. */
841 R0PTRTYPE(void *) pvMsrBitmap;
842
843 /** Whether VTPR with V_INTR_MASKING set is in effect, indicating
844 * we should check if the VTPR changed on every VM-exit. */
845 bool fSyncVTpr;
846 uint8_t u8Alignment0[7];
847 } svm;
848
849 /** Event injection state. */
850 struct
851 {
852 uint32_t fPending;
853 uint32_t u32ErrCode;
854 uint32_t cbInstr;
855 uint32_t u32Padding; /**< Explicit alignment padding. */
856 uint64_t u64IntInfo;
857 RTGCUINTPTR GCPtrFaultAddress;
858 } Event;
859
860 /** IO Block emulation state. */
861 struct
862 {
863 bool fEnabled;
864 uint8_t u8Align[7];
865
866 /** RIP at the start of the io code we wish to emulate in the recompiler. */
867 RTGCPTR GCPtrFunctionEip;
868
869 uint64_t cr0;
870 } EmulateIoBlock;
871
872 /* */
873 struct
874 {
875 /** Pending IO operation type. */
876 HMPENDINGIO enmType;
877 uint32_t u32Alignment0;
878 RTGCPTR GCPtrRip;
879 RTGCPTR GCPtrRipNext;
880 union
881 {
882 struct
883 {
884 uint32_t uPort;
885 uint32_t uAndVal;
886 uint32_t cbSize;
887 } Port;
888 uint64_t aRaw[2];
889 } s;
890 } PendingIO;
891
892 /** The PAE PDPEs used with Nested Paging (only valid when
893 * VMCPU_FF_HM_UPDATE_PAE_PDPES is set). */
894 X86PDPE aPdpes[4];
895
896 /** Current shadow paging mode. */
897 PGMMODE enmShadowMode;
898
899 /** The CPU ID of the CPU currently owning the VMCS. Set in
900 * HMR0Enter and cleared in HMR0Leave. */
901 RTCPUID idEnteredCpu;
902
903 /** VT-x/AMD-V VM-exit/\#VMXEXIT history, circular array. */
904 uint16_t auExitHistory[31];
905 /** The index of the next free slot in the history array. */
906 uint16_t idxExitHistoryFree;
907
908 /** For saving stack space, the disassembler state is allocated here instead of
909 * on the stack. */
910 DISCPUSTATE DisState;
911
912 STAMPROFILEADV StatEntry;
913 STAMPROFILEADV StatExit1;
914 STAMPROFILEADV StatExit2;
915 STAMPROFILEADV StatExitIO;
916 STAMPROFILEADV StatExitMovCRx;
917 STAMPROFILEADV StatExitXcptNmi;
918 STAMPROFILEADV StatLoadGuestState;
919 STAMPROFILEADV StatInGC;
920
921#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
922 STAMPROFILEADV StatWorldSwitch3264;
923#endif
924 STAMPROFILEADV StatPoke;
925 STAMPROFILEADV StatSpinPoke;
926 STAMPROFILEADV StatSpinPokeFailed;
927
928 STAMCOUNTER StatInjectInterrupt;
929 STAMCOUNTER StatInjectXcpt;
930 STAMCOUNTER StatInjectPendingReflect;
931
932 STAMCOUNTER StatExitAll;
933 STAMCOUNTER StatExitShadowNM;
934 STAMCOUNTER StatExitGuestNM;
935 STAMCOUNTER StatExitShadowPF; /**< Misleading, currently used for MMIO \#PFs as well. */
936 STAMCOUNTER StatExitShadowPFEM;
937 STAMCOUNTER StatExitGuestPF;
938 STAMCOUNTER StatExitGuestUD;
939 STAMCOUNTER StatExitGuestSS;
940 STAMCOUNTER StatExitGuestNP;
941 STAMCOUNTER StatExitGuestTS;
942 STAMCOUNTER StatExitGuestGP;
943 STAMCOUNTER StatExitGuestDE;
944 STAMCOUNTER StatExitGuestDB;
945 STAMCOUNTER StatExitGuestMF;
946 STAMCOUNTER StatExitGuestBP;
947 STAMCOUNTER StatExitGuestXF;
948 STAMCOUNTER StatExitGuestXcpUnk;
949 STAMCOUNTER StatExitInvlpg;
950 STAMCOUNTER StatExitInvd;
951 STAMCOUNTER StatExitWbinvd;
952 STAMCOUNTER StatExitPause;
953 STAMCOUNTER StatExitCpuid;
954 STAMCOUNTER StatExitRdtsc;
955 STAMCOUNTER StatExitRdtscp;
956 STAMCOUNTER StatExitRdpmc;
957 STAMCOUNTER StatExitVmcall;
958 STAMCOUNTER StatExitRdrand;
959 STAMCOUNTER StatExitCli;
960 STAMCOUNTER StatExitSti;
961 STAMCOUNTER StatExitPushf;
962 STAMCOUNTER StatExitPopf;
963 STAMCOUNTER StatExitIret;
964 STAMCOUNTER StatExitInt;
965 STAMCOUNTER StatExitCRxWrite[16];
966 STAMCOUNTER StatExitCRxRead[16];
967 STAMCOUNTER StatExitDRxWrite;
968 STAMCOUNTER StatExitDRxRead;
969 STAMCOUNTER StatExitRdmsr;
970 STAMCOUNTER StatExitWrmsr;
971 STAMCOUNTER StatExitClts;
972 STAMCOUNTER StatExitXdtrAccess;
973 STAMCOUNTER StatExitHlt;
974 STAMCOUNTER StatExitMwait;
975 STAMCOUNTER StatExitMonitor;
976 STAMCOUNTER StatExitLmsw;
977 STAMCOUNTER StatExitIOWrite;
978 STAMCOUNTER StatExitIORead;
979 STAMCOUNTER StatExitIOStringWrite;
980 STAMCOUNTER StatExitIOStringRead;
981 STAMCOUNTER StatExitIntWindow;
982 STAMCOUNTER StatExitExtInt;
983 STAMCOUNTER StatExitHostNmiInGC;
984 STAMCOUNTER StatExitPreemptTimer;
985 STAMCOUNTER StatExitTprBelowThreshold;
986 STAMCOUNTER StatExitTaskSwitch;
987 STAMCOUNTER StatExitMtf;
988 STAMCOUNTER StatExitApicAccess;
989 STAMCOUNTER StatPendingHostIrq;
990
991 STAMCOUNTER StatFlushPage;
992 STAMCOUNTER StatFlushPageManual;
993 STAMCOUNTER StatFlushPhysPageManual;
994 STAMCOUNTER StatFlushTlb;
995 STAMCOUNTER StatFlushTlbManual;
996 STAMCOUNTER StatFlushTlbWorldSwitch;
997 STAMCOUNTER StatNoFlushTlbWorldSwitch;
998 STAMCOUNTER StatFlushEntire;
999 STAMCOUNTER StatFlushAsid;
1000 STAMCOUNTER StatFlushNestedPaging;
1001 STAMCOUNTER StatFlushTlbInvlpgVirt;
1002 STAMCOUNTER StatFlushTlbInvlpgPhys;
1003 STAMCOUNTER StatTlbShootdown;
1004 STAMCOUNTER StatTlbShootdownFlush;
1005
1006 STAMCOUNTER StatSwitchTprMaskedIrq;
1007 STAMCOUNTER StatSwitchGuestIrq;
1008 STAMCOUNTER StatSwitchHmToR3FF;
1009 STAMCOUNTER StatSwitchExitToR3;
1010 STAMCOUNTER StatSwitchLongJmpToR3;
1011 STAMCOUNTER StatSwitchMaxResumeLoops;
1012 STAMCOUNTER StatSwitchHltToR3;
1013 STAMCOUNTER StatSwitchApicAccessToR3;
1014 STAMCOUNTER StatSwitchPreempt;
1015 STAMCOUNTER StatSwitchPreemptSaveHostState;
1016
1017 STAMCOUNTER StatTscParavirt;
1018 STAMCOUNTER StatTscOffset;
1019 STAMCOUNTER StatTscIntercept;
1020
1021 STAMCOUNTER StatExitReasonNpf;
1022 STAMCOUNTER StatDRxArmed;
1023 STAMCOUNTER StatDRxContextSwitch;
1024 STAMCOUNTER StatDRxIoCheck;
1025
1026 STAMCOUNTER StatLoadMinimal;
1027 STAMCOUNTER StatLoadFull;
1028
1029 STAMCOUNTER StatVmxCheckBadRmSelBase;
1030 STAMCOUNTER StatVmxCheckBadRmSelLimit;
1031 STAMCOUNTER StatVmxCheckRmOk;
1032
1033 STAMCOUNTER StatVmxCheckBadSel;
1034 STAMCOUNTER StatVmxCheckBadRpl;
1035 STAMCOUNTER StatVmxCheckBadLdt;
1036 STAMCOUNTER StatVmxCheckBadTr;
1037 STAMCOUNTER StatVmxCheckPmOk;
1038
1039#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1040 STAMCOUNTER StatFpu64SwitchBack;
1041 STAMCOUNTER StatDebug64SwitchBack;
1042#endif
1043
1044#ifdef VBOX_WITH_STATISTICS
1045 R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
1046 R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
1047 R3PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqs;
1048 R0PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqsR0;
1049#endif
1050#ifdef HM_PROFILE_EXIT_DISPATCH
1051 STAMPROFILEADV StatExitDispatch;
1052#endif
1053} HMCPU;
1054/** Pointer to HM VMCPU instance data. */
1055typedef HMCPU *PHMCPU;
1056AssertCompileMemberAlignment(HMCPU, vmx, 8);
1057AssertCompileMemberAlignment(HMCPU, svm, 8);
1058AssertCompileMemberAlignment(HMCPU, Event, 8);
1059
1060
1061#ifdef IN_RING0
1062/** @todo r=bird: s/[[:space:]]HM/ hm/ - internal functions starts with a
1063 * lower cased prefix. HMInternal.h is an internal header, so
1064 * everything here must be internal. */
1065VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpu(void);
1066VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpuEx(RTCPUID idCpu);
1067
1068
1069# ifdef VBOX_STRICT
1070VMMR0DECL(void) HMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
1071VMMR0DECL(void) HMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg);
1072# else
1073# define HMDumpRegs(a, b ,c) do { } while (0)
1074# define HMR0DumpDescriptor(a, b, c) do { } while (0)
1075# endif /* VBOX_STRICT */
1076
1077# ifdef VBOX_WITH_KERNEL_USING_XMM
1078DECLASM(int) HMR0VMXStartVMWrapXMM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu, PFNHMVMXSTARTVM pfnStartVM);
1079DECLASM(int) HMR0SVMRunWrapXMM(RTHCPHYS pVmcbHostPhys, RTHCPHYS pVmcbPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu, PFNHMSVMVMRUN pfnVMRun);
1080# endif
1081
1082#endif /* IN_RING0 */
1083
1084/** @} */
1085
1086RT_C_DECLS_END
1087
1088#endif
1089
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