HMInternal.h@ 65909

Last change on this file since 65909 was 65448, checked in by vboxsync, 8 years ago
HMInternal.h: todo, comment.
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1	/* $Id: HMInternal.h 65448 2017-01-26 09:39:54Z vboxsync $ */
2	/** @file
3	* HM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef ___HMInternal_h
19	#define ___HMInternal_h
20
21	#include <VBox/cdefs.h>
22	#include <VBox/types.h>
23	#include <VBox/vmm/em.h>
24	#include <VBox/vmm/stam.h>
25	#include <VBox/dis.h>
26	#include <VBox/vmm/hm.h>
27	#include <VBox/vmm/hm_vmx.h>
28	#include <VBox/vmm/pgm.h>
29	#include <VBox/vmm/cpum.h>
30	#include <iprt/memobj.h>
31	#include <iprt/cpuset.h>
32	#include <iprt/mp.h>
33	#include <iprt/avl.h>
34	#include <iprt/string.h>
35
36	#if defined(RT_OS_DARWIN) && HC_ARCH_BITS == 32
37	# error "32-bit darwin is no longer supported. Go back to 4.3 or earlier!"
38	#endif
39
40	#if HC_ARCH_BITS == 64 \|\| defined (VBOX_WITH_64_BITS_GUESTS)
41	/* Enable 64 bits guest support. */
42	# define VBOX_ENABLE_64_BITS_GUESTS
43	#endif
44
45	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
46	# define VMX_USE_CACHED_VMCS_ACCESSES
47	#endif
48
49	/** @def HM_PROFILE_EXIT_DISPATCH
50	* Enables profiling of the VM exit handler dispatching. */
51	#if 0 \|\| defined(DOXYGEN_RUNNING)
52	# define HM_PROFILE_EXIT_DISPATCH
53	#endif
54
55	RT_C_DECLS_BEGIN
56
57
58	/** @defgroup grp_hm_int Internal
59	* @ingroup grp_hm
60	* @internal
61	* @{
62	*/
63
64	/** @def HMCPU_CF_CLEAR
65	* Clears a HM-context flag.
66	*
67	* @param pVCpu The cross context virtual CPU structure.
68	* @param fFlag The flag to clear.
69	*/
70	#define HMCPU_CF_CLEAR(pVCpu, fFlag) (ASMAtomicUoAndU32(&(pVCpu)->hm.s.fContextUseFlags, ~(fFlag)))
71
72	/** @def HMCPU_CF_SET
73	* Sets a HM-context flag.
74	*
75	* @param pVCpu The cross context virtual CPU structure.
76	* @param fFlag The flag to set.
77	*/
78	#define HMCPU_CF_SET(pVCpu, fFlag) (ASMAtomicUoOrU32(&(pVCpu)->hm.s.fContextUseFlags, (fFlag)))
79
80	/** @def HMCPU_CF_IS_SET
81	* Checks if all the flags in the specified HM-context set is pending.
82	*
83	* @param pVCpu The cross context virtual CPU structure.
84	* @param fFlag The flag to check.
85	*/
86	#define HMCPU_CF_IS_SET(pVCpu, fFlag) ((ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags) & (fFlag)) == (fFlag))
87
88	/** @def HMCPU_CF_IS_PENDING
89	* Checks if one or more of the flags in the specified HM-context set is
90	* pending.
91	*
92	* @param pVCpu The cross context virtual CPU structure.
93	* @param fFlags The flags to check for.
94	*/
95	#define HMCPU_CF_IS_PENDING(pVCpu, fFlags) RT_BOOL(ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags) & (fFlags))
96
97	/** @def HMCPU_CF_IS_PENDING_ONLY
98	* Checks if -only- one or more of the specified HM-context flags is pending.
99	*
100	* @param pVCpu The cross context virtual CPU structure.
101	* @param fFlags The flags to check for.
102	*/
103	#define HMCPU_CF_IS_PENDING_ONLY(pVCpu, fFlags) !RT_BOOL(ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags) & ~(fFlags))
104
105	/** @def HMCPU_CF_IS_SET_ONLY
106	* Checks if -only- all the flags in the specified HM-context set is pending.
107	*
108	* @param pVCpu The cross context virtual CPU structure.
109	* @param fFlags The flags to check for.
110	*/
111	#define HMCPU_CF_IS_SET_ONLY(pVCpu, fFlags) (ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags) == (fFlags))
112
113	/** @def HMCPU_CF_RESET_TO
114	* Resets the HM-context flags to the specified value.
115	*
116	* @param pVCpu The cross context virtual CPU structure.
117	* @param fFlags The new value.
118	*/
119	#define HMCPU_CF_RESET_TO(pVCpu, fFlags) (ASMAtomicUoWriteU32(&(pVCpu)->hm.s.fContextUseFlags, (fFlags)))
120
121	/** @def HMCPU_CF_VALUE
122	* Returns the current HM-context flags value.
123	*
124	* @param pVCpu The cross context virtual CPU structure.
125	*/
126	#define HMCPU_CF_VALUE(pVCpu) (ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags))
127
128
129	/** Resets/initializes the VM-exit/\#VMEXIT history array. */
130	#define HMCPU_EXIT_HISTORY_RESET(pVCpu) (memset(&(pVCpu)->hm.s.auExitHistory, 0xff, sizeof((pVCpu)->hm.s.auExitHistory)))
131
132	/** Updates the VM-exit/\#VMEXIT history array. */
133	#define HMCPU_EXIT_HISTORY_ADD(pVCpu, a_ExitReason) \
134	do { \
135	AssertMsg((pVCpu)->hm.s.idxExitHistoryFree < RT_ELEMENTS((pVCpu)->hm.s.auExitHistory), ("%u\n", (pVCpu)->hm.s.idxExitHistoryFree)); \
136	(pVCpu)->hm.s.auExitHistory[(pVCpu)->hm.s.idxExitHistoryFree++] = (uint16_t)(a_ExitReason); \
137	if ((pVCpu)->hm.s.idxExitHistoryFree == RT_ELEMENTS((pVCpu)->hm.s.auExitHistory)) \
138	(pVCpu)->hm.s.idxExitHistoryFree = 0; \
139	(pVCpu)->hm.s.auExitHistory[(pVCpu)->hm.s.idxExitHistoryFree] = UINT16_MAX; \
140	} while (0)
141
142	/** Maximum number of exit reason statistics counters. */
143	#define MAX_EXITREASON_STAT 0x100
144	#define MASK_EXITREASON_STAT 0xff
145	#define MASK_INJECT_IRQ_STAT 0xff
146
147	/** @name HM changed flags.
148	* These flags are used to keep track of which important registers that have
149	* been changed since last they were reset.
150	*
151	* Flags marked "shared" are used for registers that are common to both the host
152	* and guest (i.e. without dedicated VMCS/VMCB fields for guest bits).
153	*
154	* @{
155	*/
156	#define HM_CHANGED_GUEST_CR0 RT_BIT(0) /* Shared */
157	#define HM_CHANGED_GUEST_CR3 RT_BIT(1)
158	#define HM_CHANGED_GUEST_CR4 RT_BIT(2)
159	#define HM_CHANGED_GUEST_GDTR RT_BIT(3)
160	#define HM_CHANGED_GUEST_IDTR RT_BIT(4)
161	#define HM_CHANGED_GUEST_LDTR RT_BIT(5)
162	#define HM_CHANGED_GUEST_TR RT_BIT(6)
163	#define HM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(7)
164	#define HM_CHANGED_GUEST_DEBUG RT_BIT(8) /* Shared */
165	#define HM_CHANGED_GUEST_RIP RT_BIT(9)
166	#define HM_CHANGED_GUEST_RSP RT_BIT(10)
167	#define HM_CHANGED_GUEST_RFLAGS RT_BIT(11)
168	#define HM_CHANGED_GUEST_CR2 RT_BIT(12)
169	#define HM_CHANGED_GUEST_SYSENTER_CS_MSR RT_BIT(13)
170	#define HM_CHANGED_GUEST_SYSENTER_EIP_MSR RT_BIT(14)
171	#define HM_CHANGED_GUEST_SYSENTER_ESP_MSR RT_BIT(15)
172	#define HM_CHANGED_GUEST_EFER_MSR RT_BIT(16)
173	#define HM_CHANGED_GUEST_LAZY_MSRS RT_BIT(17) /* Shared / /* @todo Move this to VT-x specific? */
174	#define HM_CHANGED_GUEST_XCPT_INTERCEPTS RT_BIT(18)
175	/* VT-x specific state. */
176	#define HM_CHANGED_VMX_GUEST_AUTO_MSRS RT_BIT(19)
177	#define HM_CHANGED_VMX_GUEST_ACTIVITY_STATE RT_BIT(20)
178	#define HM_CHANGED_VMX_GUEST_APIC_STATE RT_BIT(21)
179	#define HM_CHANGED_VMX_ENTRY_CTLS RT_BIT(22)
180	#define HM_CHANGED_VMX_EXIT_CTLS RT_BIT(23)
181	/* AMD-V specific state. */
182	#define HM_CHANGED_SVM_GUEST_APIC_STATE RT_BIT(19)
183	#define HM_CHANGED_SVM_RESERVED1 RT_BIT(20)
184	#define HM_CHANGED_SVM_RESERVED2 RT_BIT(21)
185	#define HM_CHANGED_SVM_RESERVED3 RT_BIT(22)
186	#define HM_CHANGED_SVM_RESERVED4 RT_BIT(23)
187
188	#define HM_CHANGED_ALL_GUEST ( HM_CHANGED_GUEST_CR0 \
189	\| HM_CHANGED_GUEST_CR3 \
190	\| HM_CHANGED_GUEST_CR4 \
191	\| HM_CHANGED_GUEST_GDTR \
192	\| HM_CHANGED_GUEST_IDTR \
193	\| HM_CHANGED_GUEST_LDTR \
194	\| HM_CHANGED_GUEST_TR \
195	\| HM_CHANGED_GUEST_SEGMENT_REGS \
196	\| HM_CHANGED_GUEST_DEBUG \
197	\| HM_CHANGED_GUEST_RIP \
198	\| HM_CHANGED_GUEST_RSP \
199	\| HM_CHANGED_GUEST_RFLAGS \
200	\| HM_CHANGED_GUEST_CR2 \
201	\| HM_CHANGED_GUEST_SYSENTER_CS_MSR \
202	\| HM_CHANGED_GUEST_SYSENTER_EIP_MSR \
203	\| HM_CHANGED_GUEST_SYSENTER_ESP_MSR \
204	\| HM_CHANGED_GUEST_EFER_MSR \
205	\| HM_CHANGED_GUEST_LAZY_MSRS \
206	\| HM_CHANGED_GUEST_XCPT_INTERCEPTS \
207	\| HM_CHANGED_VMX_GUEST_AUTO_MSRS \
208	\| HM_CHANGED_VMX_GUEST_ACTIVITY_STATE \
209	\| HM_CHANGED_VMX_GUEST_APIC_STATE \
210	\| HM_CHANGED_VMX_ENTRY_CTLS \
211	\| HM_CHANGED_VMX_EXIT_CTLS)
212
213	#define HM_CHANGED_HOST_CONTEXT RT_BIT(24)
214
215	/* Bits shared between host and guest. */
216	#define HM_CHANGED_HOST_GUEST_SHARED_STATE ( HM_CHANGED_GUEST_CR0 \
217	\| HM_CHANGED_GUEST_DEBUG \
218	\| HM_CHANGED_GUEST_LAZY_MSRS)
219	/** @} */
220
221	/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
222	#define HM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
223	/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
224	#define HM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2 * PAGE_SIZE + 1)
225	/** Total guest mapped memory needed. */
226	#define HM_VTX_TOTAL_DEVHEAP_MEM (HM_EPT_IDENTITY_PG_TABLE_SIZE + HM_VTX_TSS_SIZE)
227
228
229	/** @name Macros for enabling and disabling preemption.
230	* These are really just for hiding the RTTHREADPREEMPTSTATE and asserting that
231	* preemption has already been disabled when there is no context hook.
232	* @{ */
233	#ifdef VBOX_STRICT
234	# define HM_DISABLE_PREEMPT() \
235	RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
236	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD) \|\| VMMR0ThreadCtxHookIsEnabled(pVCpu)); \
237	RTThreadPreemptDisable(&PreemptStateInternal)
238	#else
239	# define HM_DISABLE_PREEMPT() \
240	RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
241	RTThreadPreemptDisable(&PreemptStateInternal)
242	#endif /* VBOX_STRICT */
243	#define HM_RESTORE_PREEMPT() do { RTThreadPreemptRestore(&PreemptStateInternal); } while(0)
244	/** @} */
245
246
247	/** Enable for TPR guest patching. */
248	#define VBOX_HM_WITH_GUEST_PATCHING
249
250	/** @name HM saved state versions
251	* @{
252	*/
253	#ifdef VBOX_HM_WITH_GUEST_PATCHING
254	# define HM_SAVED_STATE_VERSION 5
255	# define HM_SAVED_STATE_VERSION_NO_PATCHING 4
256	#else
257	# define HM_SAVED_STATE_VERSION 4
258	# define HM_SAVED_STATE_VERSION_NO_PATCHING 4
259	#endif
260	#define HM_SAVED_STATE_VERSION_2_0_X 3
261	/** @} */
262
263	/**
264	* Global per-cpu information. (host)
265	*/
266	typedef struct HMGLOBALCPUINFO
267	{
268	/** The CPU ID. */
269	RTCPUID idCpu;
270	/** The VM_HSAVE_AREA (AMD-V) / VMXON region (Intel) memory backing. */
271	RTR0MEMOBJ hMemObj;
272	/** The physical address of the first page in hMemObj (it's a
273	* physcially contigous allocation if it spans multiple pages). */
274	RTHCPHYS HCPhysMemObj;
275	/** The address of the memory (for pfnEnable). */
276	void *pvMemObj;
277	/** Current ASID (AMD-V) / VPID (Intel). */
278	uint32_t uCurrentAsid;
279	/** TLB flush count. */
280	uint32_t cTlbFlushes;
281	/** Whether to flush each new ASID/VPID before use. */
282	bool fFlushAsidBeforeUse;
283	/** Configured for VT-x or AMD-V. */
284	bool fConfigured;
285	/** Set if the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active. */
286	bool fIgnoreAMDVInUseError;
287	/** In use by our code. (for power suspend) */
288	volatile bool fInUse;
289	} HMGLOBALCPUINFO;
290	/** Pointer to the per-cpu global information. */
291	typedef HMGLOBALCPUINFO *PHMGLOBALCPUINFO;
292
293	typedef enum
294	{
295	HMPENDINGIO_INVALID = 0,
296	HMPENDINGIO_PORT_READ,
297	/* not implemented: HMPENDINGIO_STRING_READ, */
298	/* not implemented: HMPENDINGIO_STRING_WRITE, */
299	/** The usual 32-bit paranoia. */
300	HMPENDINGIO_32BIT_HACK = 0x7fffffff
301	} HMPENDINGIO;
302
303
304	typedef enum
305	{
306	HMTPRINSTR_INVALID,
307	HMTPRINSTR_READ,
308	HMTPRINSTR_READ_SHR4,
309	HMTPRINSTR_WRITE_REG,
310	HMTPRINSTR_WRITE_IMM,
311	HMTPRINSTR_JUMP_REPLACEMENT,
312	/** The usual 32-bit paranoia. */
313	HMTPRINSTR_32BIT_HACK = 0x7fffffff
314	} HMTPRINSTR;
315
316	typedef struct
317	{
318	/** The key is the address of patched instruction. (32 bits GC ptr) */
319	AVLOU32NODECORE Core;
320	/** Original opcode. */
321	uint8_t aOpcode[16];
322	/** Instruction size. */
323	uint32_t cbOp;
324	/** Replacement opcode. */
325	uint8_t aNewOpcode[16];
326	/** Replacement instruction size. */
327	uint32_t cbNewOp;
328	/** Instruction type. */
329	HMTPRINSTR enmType;
330	/** Source operand. */
331	uint32_t uSrcOperand;
332	/** Destination operand. */
333	uint32_t uDstOperand;
334	/** Number of times the instruction caused a fault. */
335	uint32_t cFaults;
336	/** Patch address of the jump replacement. */
337	RTGCPTR32 pJumpTarget;
338	} HMTPRPATCH;
339	/** Pointer to HMTPRPATCH. */
340	typedef HMTPRPATCH *PHMTPRPATCH;
341
342
343	/**
344	* Makes a HMEXITSTAT::uKey value from a program counter and an exit code.
345	*
346	* @returns 64-bit key
347	* @param a_uPC The RIP + CS.BASE value of the exit.
348	* @param a_uExit The exit code.
349	* @todo Add CPL?
350	*/
351	#define HMEXITSTAT_MAKE_KEY(a_uPC, a_uExit) (((a_uPC) & UINT64_C(0x0000ffffffffffff)) \| (uint64_t)(a_uExit) << 48)
352
353	typedef struct HMEXITINFO
354	{
355	/** See HMEXITSTAT_MAKE_KEY(). */
356	uint64_t uKey;
357	/** Number of recent hits (depreciates with time). */
358	uint32_t volatile cHits;
359	/** The age + lock. */
360	uint16_t volatile uAge;
361	/** Action or action table index. */
362	uint16_t iAction;
363	} HMEXITINFO;
364	AssertCompileSize(HMEXITINFO, 16); /* Lots of these guys, so don't add any unnecessary stuff! */
365
366	typedef struct HMEXITHISTORY
367	{
368	/** The exit timestamp. */
369	uint64_t uTscExit;
370	/** The index of the corresponding HMEXITINFO entry.
371	* UINT32_MAX if none (too many collisions, race, whatever). */
372	uint32_t iExitInfo;
373	/** Figure out later, needed for padding now. */
374	uint32_t uSomeClueOrSomething;
375	} HMEXITHISTORY;
376
377	/**
378	* Switcher function, HC to the special 64-bit RC.
379	*
380	* @param pVM The cross context VM structure.
381	* @param offCpumVCpu Offset from pVM->cpum to pVM->aCpus[idCpu].cpum.
382	* @returns Return code indicating the action to take.
383	*/
384	typedef DECLCALLBACK(int) FNHMSWITCHERHC(PVM pVM, uint32_t offCpumVCpu);
385	/** Pointer to switcher function. */
386	typedef FNHMSWITCHERHC *PFNHMSWITCHERHC;
387
388	/**
389	* HM VM Instance data.
390	* Changes to this must checked against the padding of the hm union in VM!
391	*/
392	typedef struct HM
393	{
394	/** Set when we've initialized VMX or SVM. */
395	bool fInitialized;
396	/** Set if nested paging is enabled. */
397	bool fNestedPaging;
398	/** Set if nested paging is allowed. */
399	bool fAllowNestedPaging;
400	/** Set if large pages are enabled (requires nested paging). */
401	bool fLargePages;
402	/** Set if we can support 64-bit guests or not. */
403	bool fAllow64BitGuests;
404	/** Set when TPR patching is allowed. */
405	bool fTprPatchingAllowed;
406	/** Set when we initialize VT-x or AMD-V once for all CPUs. */
407	bool fGlobalInit;
408	/** Set when TPR patching is active. */
409	bool fTPRPatchingActive;
410	/** Set when the debug facility has breakpoints/events enabled that requires
411	* us to use the debug execution loop in ring-0. */
412	bool fUseDebugLoop;
413	/** Set if hardware APIC virtualization is enabled. */
414	bool fVirtApicRegs;
415	/** Set if posted interrupt processing is enabled. */
416	bool fPostedIntrs;
417	/** Alignment. */
418	bool fAlignment0;
419
420	/** Host kernel flags that HM might need to know (SUPKERNELFEATURES_XXX). */
421	uint32_t fHostKernelFeatures;
422
423	/** Maximum ASID allowed. */
424	uint32_t uMaxAsid;
425	/** The maximum number of resumes loops allowed in ring-0 (safety precaution).
426	* This number is set much higher when RTThreadPreemptIsPending is reliable. */
427	uint32_t cMaxResumeLoops;
428
429	/** Guest allocated memory for patching purposes. */
430	RTGCPTR pGuestPatchMem;
431	/** Current free pointer inside the patch block. */
432	RTGCPTR pFreeGuestPatchMem;
433	/** Size of the guest patch memory block. */
434	uint32_t cbGuestPatchMem;
435	uint32_t u32Alignment0;
436
437	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
438	/** 32 to 64 bits switcher entrypoint. */
439	R0PTRTYPE(PFNHMSWITCHERHC) pfnHost32ToGuest64R0;
440	RTR0PTR pvR0Alignment0;
441	#endif
442
443	struct
444	{
445	/** Set by the ring-0 side of HM to indicate VMX is supported by the
446	* CPU. */
447	bool fSupported;
448	/** Set when we've enabled VMX. */
449	bool fEnabled;
450	/** Set if VPID is supported. */
451	bool fVpid;
452	/** Set if VT-x VPID is allowed. */
453	bool fAllowVpid;
454	/** Set if unrestricted guest execution is in use (real and protected mode without paging). */
455	bool fUnrestrictedGuest;
456	/** Set if unrestricted guest execution is allowed to be used. */
457	bool fAllowUnrestricted;
458	/** Whether we're using the preemption timer or not. */
459	bool fUsePreemptTimer;
460	/** The shift mask employed by the VMX-Preemption timer. */
461	uint8_t cPreemptTimerShift;
462
463	/** Virtual address of the TSS page used for real mode emulation. */
464	R3PTRTYPE(PVBOXTSS) pRealModeTSS;
465	/** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
466	R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
467
468	/** Physical address of the APIC-access page. */
469	RTHCPHYS HCPhysApicAccess;
470	/** R0 memory object for the APIC-access page. */
471	RTR0MEMOBJ hMemObjApicAccess;
472	/** Virtual address of the APIC-access page. */
473	R0PTRTYPE(uint8_t *) pbApicAccess;
474
475	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
476	RTHCPHYS HCPhysScratch;
477	RTR0MEMOBJ hMemObjScratch;
478	R0PTRTYPE(uint8_t *) pbScratch;
479	#endif
480
481	/** Internal Id of which flush-handler to use for tagged-TLB entries. */
482	uint32_t uFlushTaggedTlb;
483
484	/** Pause-loop exiting (PLE) gap in ticks. */
485	uint32_t cPleGapTicks;
486	/** Pause-loop exiting (PLE) window in ticks. */
487	uint32_t cPleWindowTicks;
488	uint32_t u32Alignment0;
489
490	/** Host CR4 value (set by ring-0 VMX init) */
491	uint64_t u64HostCr4;
492	/** Host SMM monitor control (set by ring-0 VMX init) */
493	uint64_t u64HostSmmMonitorCtl;
494	/** Host EFER value (set by ring-0 VMX init) */
495	uint64_t u64HostEfer;
496	/** Whether the CPU supports VMCS fields for swapping EFER. */
497	bool fSupportsVmcsEfer;
498	uint8_t u8Alignment2[7];
499
500	/** VMX MSR values. */
501	VMXMSRS Msrs;
502
503	/** Flush types for invept & invvpid; they depend on capabilities. */
504	VMXFLUSHEPT enmFlushEpt;
505	VMXFLUSHVPID enmFlushVpid;
506
507	/** Host-physical address for a failing VMXON instruction. */
508	RTHCPHYS HCPhysVmxEnableError;
509	} vmx;
510
511	struct
512	{
513	/** Set by the ring-0 side of HM to indicate SVM is supported by the
514	* CPU. */
515	bool fSupported;
516	/** Set when we've enabled SVM. */
517	bool fEnabled;
518	/** Set if erratum 170 affects the AMD cpu. */
519	bool fAlwaysFlushTLB;
520	/** Set when the hack to ignore VERR_SVM_IN_USE is active. */
521	bool fIgnoreInUseError;
522	uint8_t u8Alignment0[4];
523
524	/** Physical address of the IO bitmap (12kb). */
525	RTHCPHYS HCPhysIOBitmap;
526	/** R0 memory object for the IO bitmap (12kb). */
527	RTR0MEMOBJ hMemObjIOBitmap;
528	/** Virtual address of the IO bitmap. */
529	R0PTRTYPE(void *) pvIOBitmap;
530
531	/* HWCR MSR (for diagnostics) */
532	uint64_t u64MsrHwcr;
533
534	/** SVM revision. */
535	uint32_t u32Rev;
536	/** SVM feature bits from cpuid 0x8000000a */
537	uint32_t u32Features;
538
539	/** Pause filter counter. */
540	uint16_t cPauseFilter;
541	/** Pause filter treshold in ticks. */
542	uint16_t cPauseFilterThresholdTicks;
543	uint32_t u32Alignment0;
544	} svm;
545
546	/**
547	* AVL tree with all patches (active or disabled) sorted by guest instruction
548	* address.
549	*/
550	AVLOU32TREE PatchTree;
551	uint32_t cPatches;
552	HMTPRPATCH aPatches[64];
553
554	struct
555	{
556	uint32_t u32AMDFeatureECX;
557	uint32_t u32AMDFeatureEDX;
558	} cpuid;
559
560	/** Saved error from detection */
561	int32_t lLastError;
562
563	/** HMR0Init was run */
564	bool fHMR0Init;
565	bool u8Alignment1[3];
566
567	STAMCOUNTER StatTprPatchSuccess;
568	STAMCOUNTER StatTprPatchFailure;
569	STAMCOUNTER StatTprReplaceSuccessCr8;
570	STAMCOUNTER StatTprReplaceSuccessVmc;
571	STAMCOUNTER StatTprReplaceFailure;
572	} HM;
573	/** Pointer to HM VM instance data. */
574	typedef HM *PHM;
575
576	AssertCompileMemberAlignment(HM, StatTprPatchSuccess, 8);
577
578	/* Maximum number of cached entries. */
579	#define VMCSCACHE_MAX_ENTRY 128
580
581	/**
582	* Structure for storing read and write VMCS actions.
583	*/
584	typedef struct VMCSCACHE
585	{
586	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
587	/* Magic marker for searching in crash dumps. */
588	uint8_t aMagic[16];
589	uint64_t uMagic;
590	uint64_t u64TimeEntry;
591	uint64_t u64TimeSwitch;
592	uint64_t cResume;
593	uint64_t interPD;
594	uint64_t pSwitcher;
595	uint32_t uPos;
596	uint32_t idCpu;
597	#endif
598	/* CR2 is saved here for EPT syncing. */
599	uint64_t cr2;
600	struct
601	{
602	uint32_t cValidEntries;
603	uint32_t uAlignment;
604	uint32_t aField[VMCSCACHE_MAX_ENTRY];
605	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
606	} Write;
607	struct
608	{
609	uint32_t cValidEntries;
610	uint32_t uAlignment;
611	uint32_t aField[VMCSCACHE_MAX_ENTRY];
612	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
613	} Read;
614	#ifdef VBOX_STRICT
615	struct
616	{
617	RTHCPHYS HCPhysCpuPage;
618	RTHCPHYS HCPhysVmcs;
619	RTGCPTR pCache;
620	RTGCPTR pCtx;
621	} TestIn;
622	struct
623	{
624	RTHCPHYS HCPhysVmcs;
625	RTGCPTR pCache;
626	RTGCPTR pCtx;
627	uint64_t eflags;
628	uint64_t cr8;
629	} TestOut;
630	struct
631	{
632	uint64_t param1;
633	uint64_t param2;
634	uint64_t param3;
635	uint64_t param4;
636	} ScratchPad;
637	#endif
638	} VMCSCACHE;
639	/** Pointer to VMCSCACHE. */
640	typedef VMCSCACHE *PVMCSCACHE;
641	AssertCompileSizeAlignment(VMCSCACHE, 8);
642
643	/**
644	* VMX StartVM function.
645	*
646	* @returns VBox status code (no informational stuff).
647	* @param fResume Whether to use VMRESUME (true) or VMLAUNCH (false).
648	* @param pCtx The CPU register context.
649	* @param pCache The VMCS cache.
650	* @param pVM Pointer to the cross context VM structure.
651	* @param pVCpu Pointer to the cross context per-CPU structure.
652	*/
653	typedef DECLCALLBACK(int) FNHMVMXSTARTVM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);
654	/** Pointer to a VMX StartVM function. */
655	typedef R0PTRTYPE(FNHMVMXSTARTVM *) PFNHMVMXSTARTVM;
656
657	/** SVM VMRun function. */
658	typedef DECLCALLBACK(int) FNHMSVMVMRUN(RTHCPHYS pVmcbHostPhys, RTHCPHYS pVmcbPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu);
659	/** Pointer to a SVM VMRun function. */
660	typedef R0PTRTYPE(FNHMSVMVMRUN *) PFNHMSVMVMRUN;
661
662	/**
663	* HM VMCPU Instance data.
664	*
665	* Note! If you change members of this struct, make sure to check if the
666	* assembly counterpart in HMInternal.mac needs to be updated as well.
667	*/
668	typedef struct HMCPU
669	{
670	/** Set if we need to flush the TLB during the world switch. */
671	bool fForceTLBFlush;
672	/** Set when we're using VT-x or AMD-V at that moment. */
673	bool fActive;
674	/** Set when the TLB has been checked until we return from the world switch. */
675	volatile bool fCheckedTLBFlush;
676	/** Whether we've completed the inner HM leave function. */
677	bool fLeaveDone;
678	/** Whether we're using the hyper DR7 or guest DR7. */
679	bool fUsingHyperDR7;
680	/** Whether to preload the guest-FPU state to avoid \#NM VM-exit overhead. */
681	bool fPreloadGuestFpu;
682	/** Set if XCR0 needs to be loaded and saved when entering and exiting guest
683	* code execution. */
684	bool fLoadSaveGuestXcr0;
685
686	/** Whether we should use the debug loop because of single stepping or special
687	* debug breakpoints / events are armed. */
688	bool fUseDebugLoop;
689	/** Whether we are currently executing in the debug loop.
690	* Mainly for assertions. */
691	bool fUsingDebugLoop;
692	/** Set if we using the debug loop and wish to intercept RDTSC. */
693	bool fDebugWantRdTscExit;
694	/** Whether we're executing a single instruction. */
695	bool fSingleInstruction;
696	/** Set if we need to clear the trap flag because of single stepping. */
697	bool fClearTrapFlag;
698
699	/** Whether \#UD needs to be intercepted (required by certain GIM providers). */
700	bool fGIMTrapXcptUD;
701	/** Whether paravirt. hypercalls are enabled. */
702	bool fHypercallsEnabled;
703	uint8_t u8Alignment0[2];
704
705	/** World switch exit counter. */
706	volatile uint32_t cWorldSwitchExits;
707	/** HM_CHANGED_* flags. */
708	volatile uint32_t fContextUseFlags;
709	/** Id of the last cpu we were executing code on (NIL_RTCPUID for the first
710	* time). */
711	RTCPUID idLastCpu;
712	/** TLB flush count. */
713	uint32_t cTlbFlushes;
714	/** Current ASID in use by the VM. */
715	uint32_t uCurrentAsid;
716	/** An additional error code used for some gurus. */
717	uint32_t u32HMError;
718	/** Host's TSC_AUX MSR (used when RDTSCP doesn't cause VM-exits). */
719	uint64_t u64HostTscAux;
720
721	struct
722	{
723	/** Ring 0 handlers for VT-x. */
724	PFNHMVMXSTARTVM pfnStartVM;
725	#if HC_ARCH_BITS == 32
726	uint32_t u32Alignment0;
727	#endif
728	/** Current VMX_VMCS32_CTRL_PIN_EXEC. */
729	uint32_t u32PinCtls;
730	/** Current VMX_VMCS32_CTRL_PROC_EXEC. */
731	uint32_t u32ProcCtls;
732	/** Current VMX_VMCS32_CTRL_PROC_EXEC2. */
733	uint32_t u32ProcCtls2;
734	/** Current VMX_VMCS32_CTRL_EXIT. */
735	uint32_t u32ExitCtls;
736	/** Current VMX_VMCS32_CTRL_ENTRY. */
737	uint32_t u32EntryCtls;
738
739	/** Current CR0 mask. */
740	uint32_t u32CR0Mask;
741	/** Current CR4 mask. */
742	uint32_t u32CR4Mask;
743	/** Current exception bitmap. */
744	uint32_t u32XcptBitmap;
745	/** The updated-guest-state mask. */
746	volatile uint32_t fUpdatedGuestState;
747	uint32_t u32Alignment1;
748
749	/** Physical address of the VM control structure (VMCS). */
750	RTHCPHYS HCPhysVmcs;
751	/** R0 memory object for the VM control structure (VMCS). */
752	RTR0MEMOBJ hMemObjVmcs;
753	/** Virtual address of the VM control structure (VMCS). */
754	R0PTRTYPE(void *) pvVmcs;
755
756	/** Physical address of the virtual APIC page for TPR caching. */
757	RTHCPHYS HCPhysVirtApic;
758	/** Padding. */
759	R0PTRTYPE(void *) pvAlignment0;
760	/** Virtual address of the virtual APIC page for TPR caching. */
761	R0PTRTYPE(uint8_t *) pbVirtApic;
762
763	/** Physical address of the MSR bitmap. */
764	RTHCPHYS HCPhysMsrBitmap;
765	/** R0 memory object for the MSR bitmap. */
766	RTR0MEMOBJ hMemObjMsrBitmap;
767	/** Virtual address of the MSR bitmap. */
768	R0PTRTYPE(void *) pvMsrBitmap;
769
770	/** Physical address of the VM-entry MSR-load and VM-exit MSR-store area (used
771	* for guest MSRs). */
772	RTHCPHYS HCPhysGuestMsr;
773	/** R0 memory object of the VM-entry MSR-load and VM-exit MSR-store area
774	* (used for guest MSRs). */
775	RTR0MEMOBJ hMemObjGuestMsr;
776	/** Virtual address of the VM-entry MSR-load and VM-exit MSR-store area (used
777	* for guest MSRs). */
778	R0PTRTYPE(void *) pvGuestMsr;
779
780	/** Physical address of the VM-exit MSR-load area (used for host MSRs). */
781	RTHCPHYS HCPhysHostMsr;
782	/** R0 memory object for the VM-exit MSR-load area (used for host MSRs). */
783	RTR0MEMOBJ hMemObjHostMsr;
784	/** Virtual address of the VM-exit MSR-load area (used for host MSRs). */
785	R0PTRTYPE(void *) pvHostMsr;
786
787	/** Current EPTP. */
788	RTHCPHYS HCPhysEPTP;
789
790	/** Number of guest/host MSR pairs in the auto-load/store area. */
791	uint32_t cMsrs;
792	/** Whether the host MSR values are up-to-date in the auto-load/store area. */
793	bool fUpdatedHostMsrs;
794	uint8_t u8Alignment0[3];
795
796	/** Host LSTAR MSR value to restore lazily while leaving VT-x. */
797	uint64_t u64HostLStarMsr;
798	/** Host STAR MSR value to restore lazily while leaving VT-x. */
799	uint64_t u64HostStarMsr;
800	/** Host SF_MASK MSR value to restore lazily while leaving VT-x. */
801	uint64_t u64HostSFMaskMsr;
802	/** Host KernelGS-Base MSR value to restore lazily while leaving VT-x. */
803	uint64_t u64HostKernelGSBaseMsr;
804	/** A mask of which MSRs have been swapped and need restoration. */
805	uint32_t fLazyMsrs;
806	uint32_t u32Alignment2;
807
808	/** The cached APIC-base MSR used for identifying when to map the HC physical APIC-access page. */
809	uint64_t u64MsrApicBase;
810	/** Last use TSC offset value. (cached) */
811	uint64_t u64TSCOffset;
812
813	/** VMCS cache. */
814	VMCSCACHE VMCSCache;
815
816	/** Real-mode emulation state. */
817	struct
818	{
819	X86DESCATTR AttrCS;
820	X86DESCATTR AttrDS;
821	X86DESCATTR AttrES;
822	X86DESCATTR AttrFS;
823	X86DESCATTR AttrGS;
824	X86DESCATTR AttrSS;
825	X86EFLAGS Eflags;
826	uint32_t fRealOnV86Active;
827	} RealMode;
828
829	/** VT-x error-reporting (mainly for ring-3 propagation). */
830	struct
831	{
832	uint64_t u64VMCSPhys;
833	uint32_t u32VMCSRevision;
834	uint32_t u32InstrError;
835	uint32_t u32ExitReason;
836	RTCPUID idEnteredCpu;
837	RTCPUID idCurrentCpu;
838	uint32_t u32Alignment0;
839	} LastError;
840
841	/** Current state of the VMCS. */
842	uint32_t uVmcsState;
843	/** Which host-state bits to restore before being preempted. */
844	uint32_t fRestoreHostFlags;
845	/** The host-state restoration structure. */
846	VMXRESTOREHOST RestoreHost;
847
848	/** Set if guest was executing in real mode (extra checks). */
849	bool fWasInRealMode;
850	/** Set if guest switched to 64-bit mode on a 32-bit host. */
851	bool fSwitchedTo64on32;
852
853	uint8_t u8Alignment1[6];
854	} vmx;
855
856	struct
857	{
858	/** Ring 0 handlers for VT-x. */
859	PFNHMSVMVMRUN pfnVMRun;
860	#if HC_ARCH_BITS == 32
861	uint32_t u32Alignment0;
862	#endif
863
864	/** Physical address of the host VMCB which holds additional host-state. */
865	RTHCPHYS HCPhysVmcbHost;
866	/** R0 memory object for the host VMCB which holds additional host-state. */
867	RTR0MEMOBJ hMemObjVmcbHost;
868	/** Virtual address of the host VMCB which holds additional host-state. */
869	R0PTRTYPE(void *) pvVmcbHost;
870
871	/** Physical address of the guest VMCB. */
872	RTHCPHYS HCPhysVmcb;
873	/** R0 memory object for the guest VMCB. */
874	RTR0MEMOBJ hMemObjVmcb;
875	/** Virtual address of the guest VMCB. */
876	R0PTRTYPE(void *) pvVmcb;
877
878	/** Physical address of the MSR bitmap (8 KB). */
879	RTHCPHYS HCPhysMsrBitmap;
880	/** R0 memory object for the MSR bitmap (8 KB). */
881	RTR0MEMOBJ hMemObjMsrBitmap;
882	/** Virtual address of the MSR bitmap. */
883	R0PTRTYPE(void *) pvMsrBitmap;
884
885	/** Whether VTPR with V_INTR_MASKING set is in effect, indicating
886	* we should check if the VTPR changed on every VM-exit. */
887	bool fSyncVTpr;
888	uint8_t u8Alignment0[7];
889	} svm;
890
891	/** Event injection state. */
892	struct
893	{
894	uint32_t fPending;
895	uint32_t u32ErrCode;
896	uint32_t cbInstr;
897	uint32_t u32Padding; /*< Explicit alignment padding. /
898	uint64_t u64IntInfo;
899	RTGCUINTPTR GCPtrFaultAddress;
900	} Event;
901
902	/** IO Block emulation state. */
903	struct
904	{
905	bool fEnabled;
906	uint8_t u8Align[7];
907
908	/** RIP at the start of the io code we wish to emulate in the recompiler. */
909	RTGCPTR GCPtrFunctionEip;
910
911	uint64_t cr0;
912	} EmulateIoBlock;
913
914	/* */
915	struct
916	{
917	/** Pending IO operation type. */
918	HMPENDINGIO enmType;
919	uint32_t u32Alignment0;
920	RTGCPTR GCPtrRip;
921	RTGCPTR GCPtrRipNext;
922	union
923	{
924	struct
925	{
926	uint32_t uPort;
927	uint32_t uAndVal;
928	uint32_t cbSize;
929	} Port;
930	uint64_t aRaw[2];
931	} s;
932	} PendingIO;
933
934	/** The PAE PDPEs used with Nested Paging (only valid when
935	* VMCPU_FF_HM_UPDATE_PAE_PDPES is set). */
936	X86PDPE aPdpes[4];
937
938	/** Current shadow paging mode. */
939	PGMMODE enmShadowMode;
940
941	/** The CPU ID of the CPU currently owning the VMCS. Set in
942	* HMR0Enter and cleared in HMR0Leave. */
943	RTCPUID idEnteredCpu;
944
945	/** VT-x/AMD-V VM-exit/\#VMXEXIT history, circular array. */
946	uint16_t auExitHistory[31];
947	/** The index of the next free slot in the history array. */
948	uint16_t idxExitHistoryFree;
949
950	/** For saving stack space, the disassembler state is allocated here instead of
951	* on the stack. */
952	DISCPUSTATE DisState;
953
954	STAMPROFILEADV StatEntry;
955	STAMPROFILEADV StatExit1;
956	STAMPROFILEADV StatExit2;
957	STAMPROFILEADV StatExitIO;
958	STAMPROFILEADV StatExitMovCRx;
959	STAMPROFILEADV StatExitXcptNmi;
960	STAMPROFILEADV StatLoadGuestState;
961	STAMPROFILEADV StatInGC;
962
963	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
964	STAMPROFILEADV StatWorldSwitch3264;
965	#endif
966	STAMPROFILEADV StatPoke;
967	STAMPROFILEADV StatSpinPoke;
968	STAMPROFILEADV StatSpinPokeFailed;
969
970	STAMCOUNTER StatInjectInterrupt;
971	STAMCOUNTER StatInjectXcpt;
972	STAMCOUNTER StatInjectPendingReflect;
973	STAMCOUNTER StatInjectPendingInterpret;
974
975	STAMCOUNTER StatExitAll;
976	STAMCOUNTER StatExitShadowNM;
977	STAMCOUNTER StatExitGuestNM;
978	STAMCOUNTER StatExitShadowPF; /*< Misleading, currently used for MMIO \#PFs as well. /
979	STAMCOUNTER StatExitShadowPFEM;
980	STAMCOUNTER StatExitGuestPF;
981	STAMCOUNTER StatExitGuestUD;
982	STAMCOUNTER StatExitGuestSS;
983	STAMCOUNTER StatExitGuestNP;
984	STAMCOUNTER StatExitGuestTS;
985	STAMCOUNTER StatExitGuestGP;
986	STAMCOUNTER StatExitGuestDE;
987	STAMCOUNTER StatExitGuestDB;
988	STAMCOUNTER StatExitGuestMF;
989	STAMCOUNTER StatExitGuestBP;
990	STAMCOUNTER StatExitGuestXF;
991	STAMCOUNTER StatExitGuestXcpUnk;
992	STAMCOUNTER StatExitInvlpg;
993	STAMCOUNTER StatExitInvd;
994	STAMCOUNTER StatExitWbinvd;
995	STAMCOUNTER StatExitPause;
996	STAMCOUNTER StatExitCpuid;
997	STAMCOUNTER StatExitRdtsc;
998	STAMCOUNTER StatExitRdtscp;
999	STAMCOUNTER StatExitRdpmc;
1000	STAMCOUNTER StatExitVmcall;
1001	STAMCOUNTER StatExitRdrand;
1002	STAMCOUNTER StatExitCli;
1003	STAMCOUNTER StatExitSti;
1004	STAMCOUNTER StatExitPushf;
1005	STAMCOUNTER StatExitPopf;
1006	STAMCOUNTER StatExitIret;
1007	STAMCOUNTER StatExitInt;
1008	STAMCOUNTER StatExitCRxWrite[16];
1009	STAMCOUNTER StatExitCRxRead[16];
1010	STAMCOUNTER StatExitDRxWrite;
1011	STAMCOUNTER StatExitDRxRead;
1012	STAMCOUNTER StatExitRdmsr;
1013	STAMCOUNTER StatExitWrmsr;
1014	STAMCOUNTER StatExitClts;
1015	STAMCOUNTER StatExitXdtrAccess;
1016	STAMCOUNTER StatExitHlt;
1017	STAMCOUNTER StatExitMwait;
1018	STAMCOUNTER StatExitMonitor;
1019	STAMCOUNTER StatExitLmsw;
1020	STAMCOUNTER StatExitIOWrite;
1021	STAMCOUNTER StatExitIORead;
1022	STAMCOUNTER StatExitIOStringWrite;
1023	STAMCOUNTER StatExitIOStringRead;
1024	STAMCOUNTER StatExitIntWindow;
1025	STAMCOUNTER StatExitExtInt;
1026	STAMCOUNTER StatExitHostNmiInGC;
1027	STAMCOUNTER StatExitPreemptTimer;
1028	STAMCOUNTER StatExitTprBelowThreshold;
1029	STAMCOUNTER StatExitTaskSwitch;
1030	STAMCOUNTER StatExitMtf;
1031	STAMCOUNTER StatExitApicAccess;
1032	STAMCOUNTER StatPendingHostIrq;
1033
1034	STAMCOUNTER StatFlushPage;
1035	STAMCOUNTER StatFlushPageManual;
1036	STAMCOUNTER StatFlushPhysPageManual;
1037	STAMCOUNTER StatFlushTlb;
1038	STAMCOUNTER StatFlushTlbManual;
1039	STAMCOUNTER StatFlushTlbWorldSwitch;
1040	STAMCOUNTER StatNoFlushTlbWorldSwitch;
1041	STAMCOUNTER StatFlushEntire;
1042	STAMCOUNTER StatFlushAsid;
1043	STAMCOUNTER StatFlushNestedPaging;
1044	STAMCOUNTER StatFlushTlbInvlpgVirt;
1045	STAMCOUNTER StatFlushTlbInvlpgPhys;
1046	STAMCOUNTER StatTlbShootdown;
1047	STAMCOUNTER StatTlbShootdownFlush;
1048
1049	STAMCOUNTER StatSwitchTprMaskedIrq;
1050	STAMCOUNTER StatSwitchGuestIrq;
1051	STAMCOUNTER StatSwitchHmToR3FF;
1052	STAMCOUNTER StatSwitchExitToR3;
1053	STAMCOUNTER StatSwitchLongJmpToR3;
1054	STAMCOUNTER StatSwitchMaxResumeLoops;
1055	STAMCOUNTER StatSwitchHltToR3;
1056	STAMCOUNTER StatSwitchApicAccessToR3;
1057	STAMCOUNTER StatSwitchPreempt;
1058	STAMCOUNTER StatSwitchPreemptSaveHostState;
1059
1060	STAMCOUNTER StatTscParavirt;
1061	STAMCOUNTER StatTscOffset;
1062	STAMCOUNTER StatTscIntercept;
1063
1064	STAMCOUNTER StatExitReasonNpf;
1065	STAMCOUNTER StatDRxArmed;
1066	STAMCOUNTER StatDRxContextSwitch;
1067	STAMCOUNTER StatDRxIoCheck;
1068
1069	STAMCOUNTER StatLoadMinimal;
1070	STAMCOUNTER StatLoadFull;
1071
1072	STAMCOUNTER StatVmxCheckBadRmSelBase;
1073	STAMCOUNTER StatVmxCheckBadRmSelLimit;
1074	STAMCOUNTER StatVmxCheckRmOk;
1075
1076	STAMCOUNTER StatVmxCheckBadSel;
1077	STAMCOUNTER StatVmxCheckBadRpl;
1078	STAMCOUNTER StatVmxCheckBadLdt;
1079	STAMCOUNTER StatVmxCheckBadTr;
1080	STAMCOUNTER StatVmxCheckPmOk;
1081
1082	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1083	STAMCOUNTER StatFpu64SwitchBack;
1084	STAMCOUNTER StatDebug64SwitchBack;
1085	#endif
1086
1087	#ifdef VBOX_WITH_STATISTICS
1088	R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
1089	R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
1090	R3PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqs;
1091	R0PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqsR0;
1092	#endif
1093	#ifdef HM_PROFILE_EXIT_DISPATCH
1094	STAMPROFILEADV StatExitDispatch;
1095	#endif
1096	} HMCPU;
1097	/** Pointer to HM VMCPU instance data. */
1098	typedef HMCPU *PHMCPU;
1099	AssertCompileMemberAlignment(HMCPU, vmx, 8);
1100	AssertCompileMemberAlignment(HMCPU, svm, 8);
1101	AssertCompileMemberAlignment(HMCPU, Event, 8);
1102
1103
1104	#ifdef IN_RING0
1105	VMMR0DECL(PHMGLOBALCPUINFO) hmR0GetCurrentCpu(void);
1106
1107	# ifdef VBOX_STRICT
1108	VMMR0DECL(void) hmDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
1109	VMMR0DECL(void) hmR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg);
1110	# else
1111	# define hmDumpRegs(a, b ,c) do { } while (0)
1112	# define hmR0DumpDescriptor(a, b, c) do { } while (0)
1113	# endif /* VBOX_STRICT */
1114
1115	# ifdef VBOX_WITH_KERNEL_USING_XMM
1116	DECLASM(int) hmR0VMXStartVMWrapXMM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu, PFNHMVMXSTARTVM pfnStartVM);
1117	DECLASM(int) hmR0SVMRunWrapXMM(RTHCPHYS pVmcbHostPhys, RTHCPHYS pVmcbPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu, PFNHMSVMVMRUN pfnVMRun);
1118	# endif
1119
1120	#endif /* IN_RING0 */
1121
1122	/** @} */
1123
1124	RT_C_DECLS_END
1125
1126	#endif
1127

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source: vbox/trunk/src/VBox/VMM/include/HMInternal.h@ 65909

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