HMInternal.h@ 71688

Last change on this file since 71688 was 71529, checked in by vboxsync, 7 years ago
VMM/HM: Fixes to MSRPM bit accesses. Implemented merging of guest and nested-guest MSRPMs. Other nits and cleanups.
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 45.6 KB

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1	/* $Id: HMInternal.h 71529 2018-03-28 06:32:43Z vboxsync $ */
2	/** @file
3	* HM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef ___HMInternal_h
19	#define ___HMInternal_h
20
21	#include <VBox/cdefs.h>
22	#include <VBox/types.h>
23	#include <VBox/vmm/em.h>
24	#include <VBox/vmm/stam.h>
25	#include <VBox/dis.h>
26	#include <VBox/vmm/hm.h>
27	#include <VBox/vmm/hm_vmx.h>
28	#include <VBox/vmm/hm_svm.h>
29	#include <VBox/vmm/pgm.h>
30	#include <VBox/vmm/cpum.h>
31	#include <VBox/vmm/trpm.h>
32	#include <iprt/memobj.h>
33	#include <iprt/cpuset.h>
34	#include <iprt/mp.h>
35	#include <iprt/avl.h>
36	#include <iprt/string.h>
37
38	#if defined(RT_OS_DARWIN) && HC_ARCH_BITS == 32
39	# error "32-bit darwin is no longer supported. Go back to 4.3 or earlier!"
40	#endif
41
42	#if HC_ARCH_BITS == 64 \|\| defined (VBOX_WITH_64_BITS_GUESTS)
43	/* Enable 64 bits guest support. */
44	# define VBOX_ENABLE_64_BITS_GUESTS
45	#endif
46
47	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
48	# define VMX_USE_CACHED_VMCS_ACCESSES
49	#endif
50
51	/** @def HM_PROFILE_EXIT_DISPATCH
52	* Enables profiling of the VM exit handler dispatching. */
53	#if 0 \|\| defined(DOXYGEN_RUNNING)
54	# define HM_PROFILE_EXIT_DISPATCH
55	#endif
56
57	RT_C_DECLS_BEGIN
58
59
60	/** @defgroup grp_hm_int Internal
61	* @ingroup grp_hm
62	* @internal
63	* @{
64	*/
65
66	/** @def HMCPU_CF_CLEAR
67	* Clears a HM-context flag.
68	*
69	* @param pVCpu The cross context virtual CPU structure.
70	* @param fFlag The flag to clear.
71	*/
72	#define HMCPU_CF_CLEAR(pVCpu, fFlag) (ASMAtomicUoAndU32(&(pVCpu)->hm.s.fContextUseFlags, ~(fFlag)))
73
74	/** @def HMCPU_CF_SET
75	* Sets a HM-context flag.
76	*
77	* @param pVCpu The cross context virtual CPU structure.
78	* @param fFlag The flag to set.
79	*/
80	#define HMCPU_CF_SET(pVCpu, fFlag) (ASMAtomicUoOrU32(&(pVCpu)->hm.s.fContextUseFlags, (fFlag)))
81
82	/** @def HMCPU_CF_IS_SET
83	* Checks if all the flags in the specified HM-context set is pending.
84	*
85	* @param pVCpu The cross context virtual CPU structure.
86	* @param fFlag The flag to check.
87	*/
88	#define HMCPU_CF_IS_SET(pVCpu, fFlag) ((ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags) & (fFlag)) == (fFlag))
89
90	/** @def HMCPU_CF_IS_PENDING
91	* Checks if one or more of the flags in the specified HM-context set is
92	* pending.
93	*
94	* @param pVCpu The cross context virtual CPU structure.
95	* @param fFlags The flags to check for.
96	*/
97	#define HMCPU_CF_IS_PENDING(pVCpu, fFlags) RT_BOOL(ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags) & (fFlags))
98
99	/** @def HMCPU_CF_IS_PENDING_ONLY
100	* Checks if -only- one or more of the specified HM-context flags is pending.
101	*
102	* @param pVCpu The cross context virtual CPU structure.
103	* @param fFlags The flags to check for.
104	*/
105	#define HMCPU_CF_IS_PENDING_ONLY(pVCpu, fFlags) !RT_BOOL(ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags) & ~(fFlags))
106
107	/** @def HMCPU_CF_IS_SET_ONLY
108	* Checks if -only- all the flags in the specified HM-context set is pending.
109	*
110	* @param pVCpu The cross context virtual CPU structure.
111	* @param fFlags The flags to check for.
112	*/
113	#define HMCPU_CF_IS_SET_ONLY(pVCpu, fFlags) (ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags) == (fFlags))
114
115	/** @def HMCPU_CF_RESET_TO
116	* Resets the HM-context flags to the specified value.
117	*
118	* @param pVCpu The cross context virtual CPU structure.
119	* @param fFlags The new value.
120	*/
121	#define HMCPU_CF_RESET_TO(pVCpu, fFlags) (ASMAtomicUoWriteU32(&(pVCpu)->hm.s.fContextUseFlags, (fFlags)))
122
123	/** @def HMCPU_CF_VALUE
124	* Returns the current HM-context flags value.
125	*
126	* @param pVCpu The cross context virtual CPU structure.
127	*/
128	#define HMCPU_CF_VALUE(pVCpu) (ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags))
129
130
131	/** Resets/initializes the VM-exit/\#VMEXIT history array. */
132	#define HMCPU_EXIT_HISTORY_RESET(pVCpu) (memset(&(pVCpu)->hm.s.auExitHistory, 0xff, sizeof((pVCpu)->hm.s.auExitHistory)))
133
134	/** Updates the VM-exit/\#VMEXIT history array. */
135	#define HMCPU_EXIT_HISTORY_ADD(pVCpu, a_ExitReason) \
136	do { \
137	AssertMsg((pVCpu)->hm.s.idxExitHistoryFree < RT_ELEMENTS((pVCpu)->hm.s.auExitHistory), ("%u\n", (pVCpu)->hm.s.idxExitHistoryFree)); \
138	(pVCpu)->hm.s.auExitHistory[(pVCpu)->hm.s.idxExitHistoryFree++] = (uint16_t)(a_ExitReason); \
139	if ((pVCpu)->hm.s.idxExitHistoryFree == RT_ELEMENTS((pVCpu)->hm.s.auExitHistory)) \
140	(pVCpu)->hm.s.idxExitHistoryFree = 0; \
141	(pVCpu)->hm.s.auExitHistory[(pVCpu)->hm.s.idxExitHistoryFree] = UINT16_MAX; \
142	} while (0)
143
144	/** Maximum number of exit reason statistics counters. */
145	#define MAX_EXITREASON_STAT 0x100
146	#define MASK_EXITREASON_STAT 0xff
147	#define MASK_INJECT_IRQ_STAT 0xff
148
149	/** @name HM changed flags.
150	* These flags are used to keep track of which important registers that have
151	* been changed since last they were reset.
152	*
153	* Flags marked "shared" are used for registers that are common to both the host
154	* and guest (i.e. without dedicated VMCS/VMCB fields for guest bits).
155	*
156	* @{
157	*/
158	#define HM_CHANGED_GUEST_CR0 RT_BIT(0) /* Shared */
159	#define HM_CHANGED_GUEST_CR3 RT_BIT(1)
160	#define HM_CHANGED_GUEST_CR4 RT_BIT(2)
161	#define HM_CHANGED_GUEST_GDTR RT_BIT(3)
162	#define HM_CHANGED_GUEST_IDTR RT_BIT(4)
163	#define HM_CHANGED_GUEST_LDTR RT_BIT(5)
164	#define HM_CHANGED_GUEST_TR RT_BIT(6)
165	#define HM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(7)
166	#define HM_CHANGED_GUEST_DEBUG RT_BIT(8) /* Shared */
167	#define HM_CHANGED_GUEST_RIP RT_BIT(9)
168	#define HM_CHANGED_GUEST_RSP RT_BIT(10)
169	#define HM_CHANGED_GUEST_RFLAGS RT_BIT(11)
170	#define HM_CHANGED_GUEST_CR2 RT_BIT(12)
171	#define HM_CHANGED_GUEST_SYSENTER_CS_MSR RT_BIT(13)
172	#define HM_CHANGED_GUEST_SYSENTER_EIP_MSR RT_BIT(14)
173	#define HM_CHANGED_GUEST_SYSENTER_ESP_MSR RT_BIT(15)
174	#define HM_CHANGED_GUEST_EFER_MSR RT_BIT(16)
175	#define HM_CHANGED_GUEST_LAZY_MSRS RT_BIT(17) /* Shared / /* @todo Move this to VT-x specific? */
176	#define HM_CHANGED_GUEST_XCPT_INTERCEPTS RT_BIT(18)
177	/* VT-x specific state. */
178	#define HM_CHANGED_VMX_GUEST_AUTO_MSRS RT_BIT(19)
179	#define HM_CHANGED_VMX_GUEST_ACTIVITY_STATE RT_BIT(20)
180	#define HM_CHANGED_VMX_GUEST_APIC_STATE RT_BIT(21)
181	#define HM_CHANGED_VMX_ENTRY_CTLS RT_BIT(22)
182	#define HM_CHANGED_VMX_EXIT_CTLS RT_BIT(23)
183	/* AMD-V specific state. */
184	#define HM_CHANGED_SVM_GUEST_APIC_STATE RT_BIT(19)
185	#define HM_CHANGED_SVM_RESERVED1 RT_BIT(20)
186	#define HM_CHANGED_SVM_RESERVED2 RT_BIT(21)
187	#define HM_CHANGED_SVM_RESERVED3 RT_BIT(22)
188	#define HM_CHANGED_SVM_RESERVED4 RT_BIT(23)
189
190	#define HM_CHANGED_ALL_GUEST ( HM_CHANGED_GUEST_CR0 \
191	\| HM_CHANGED_GUEST_CR3 \
192	\| HM_CHANGED_GUEST_CR4 \
193	\| HM_CHANGED_GUEST_GDTR \
194	\| HM_CHANGED_GUEST_IDTR \
195	\| HM_CHANGED_GUEST_LDTR \
196	\| HM_CHANGED_GUEST_TR \
197	\| HM_CHANGED_GUEST_SEGMENT_REGS \
198	\| HM_CHANGED_GUEST_DEBUG \
199	\| HM_CHANGED_GUEST_RIP \
200	\| HM_CHANGED_GUEST_RSP \
201	\| HM_CHANGED_GUEST_RFLAGS \
202	\| HM_CHANGED_GUEST_CR2 \
203	\| HM_CHANGED_GUEST_SYSENTER_CS_MSR \
204	\| HM_CHANGED_GUEST_SYSENTER_EIP_MSR \
205	\| HM_CHANGED_GUEST_SYSENTER_ESP_MSR \
206	\| HM_CHANGED_GUEST_EFER_MSR \
207	\| HM_CHANGED_GUEST_LAZY_MSRS \
208	\| HM_CHANGED_GUEST_XCPT_INTERCEPTS \
209	\| HM_CHANGED_VMX_GUEST_AUTO_MSRS \
210	\| HM_CHANGED_VMX_GUEST_ACTIVITY_STATE \
211	\| HM_CHANGED_VMX_GUEST_APIC_STATE \
212	\| HM_CHANGED_VMX_ENTRY_CTLS \
213	\| HM_CHANGED_VMX_EXIT_CTLS)
214
215	#define HM_CHANGED_HOST_CONTEXT RT_BIT(24)
216
217	/* Bits shared between host and guest. */
218	#define HM_CHANGED_HOST_GUEST_SHARED_STATE ( HM_CHANGED_GUEST_CR0 \
219	\| HM_CHANGED_GUEST_DEBUG \
220	\| HM_CHANGED_GUEST_LAZY_MSRS)
221	/** @} */
222
223	/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
224	#define HM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
225	/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
226	#define HM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2 * PAGE_SIZE + 1)
227	/** Total guest mapped memory needed. */
228	#define HM_VTX_TOTAL_DEVHEAP_MEM (HM_EPT_IDENTITY_PG_TABLE_SIZE + HM_VTX_TSS_SIZE)
229
230
231	/** @name Macros for enabling and disabling preemption.
232	* These are really just for hiding the RTTHREADPREEMPTSTATE and asserting that
233	* preemption has already been disabled when there is no context hook.
234	* @{ */
235	#ifdef VBOX_STRICT
236	# define HM_DISABLE_PREEMPT() \
237	RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
238	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD) \|\| VMMR0ThreadCtxHookIsEnabled(pVCpu)); \
239	RTThreadPreemptDisable(&PreemptStateInternal)
240	#else
241	# define HM_DISABLE_PREEMPT() \
242	RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
243	RTThreadPreemptDisable(&PreemptStateInternal)
244	#endif /* VBOX_STRICT */
245	#define HM_RESTORE_PREEMPT() do { RTThreadPreemptRestore(&PreemptStateInternal); } while(0)
246	/** @} */
247
248
249	/** Enable for TPR guest patching. */
250	#define VBOX_HM_WITH_GUEST_PATCHING
251
252	/** @name HM saved state versions
253	* @{
254	*/
255	#ifdef VBOX_HM_WITH_GUEST_PATCHING
256	# define HM_SAVED_STATE_VERSION 5
257	# define HM_SAVED_STATE_VERSION_NO_PATCHING 4
258	#else
259	# define HM_SAVED_STATE_VERSION 4
260	# define HM_SAVED_STATE_VERSION_NO_PATCHING 4
261	#endif
262	#define HM_SAVED_STATE_VERSION_2_0_X 3
263	/** @} */
264
265	/**
266	* Global per-cpu information. (host)
267	*/
268	typedef struct HMGLOBALCPUINFO
269	{
270	/** The CPU ID. */
271	RTCPUID idCpu;
272	/** The VM_HSAVE_AREA (AMD-V) / VMXON region (Intel) memory backing. */
273	RTR0MEMOBJ hMemObj;
274	/** The physical address of the first page in hMemObj (it's a
275	* physcially contigous allocation if it spans multiple pages). */
276	RTHCPHYS HCPhysMemObj;
277	/** The address of the memory (for pfnEnable). */
278	void *pvMemObj;
279	/** Current ASID (AMD-V) / VPID (Intel). */
280	uint32_t uCurrentAsid;
281	/** TLB flush count. */
282	uint32_t cTlbFlushes;
283	/** Whether to flush each new ASID/VPID before use. */
284	bool fFlushAsidBeforeUse;
285	/** Configured for VT-x or AMD-V. */
286	bool fConfigured;
287	/** Set if the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active. */
288	bool fIgnoreAMDVInUseError;
289	/** In use by our code. (for power suspend) */
290	volatile bool fInUse;
291	#ifdef VBOX_WITH_NESTED_HWVIRT
292	/** Nested-guest union (put data common to SVM/VMX outside the union). */
293	union
294	{
295	/** Nested-guest SVM data. */
296	struct
297	{
298	/** The active nested-guest MSR permission bitmap memory backing. */
299	RTR0MEMOBJ hNstGstMsrpm;
300	/** The physical address of the first page in hNstGstMsrpm (physcially
301	* contigous allocation). */
302	RTHCPHYS HCPhysNstGstMsrpm;
303	/** The address of the active nested-guest MSRPM. */
304	void *pvNstGstMsrpm;
305	} svm;
306	/** @todo Nested-VMX. */
307	} n;
308	#endif
309	} HMGLOBALCPUINFO;
310	/** Pointer to the per-cpu global information. */
311	typedef HMGLOBALCPUINFO *PHMGLOBALCPUINFO;
312
313	typedef enum
314	{
315	HMPENDINGIO_INVALID = 0,
316	HMPENDINGIO_PORT_READ,
317	/* not implemented: HMPENDINGIO_STRING_READ, */
318	/* not implemented: HMPENDINGIO_STRING_WRITE, */
319	/** The usual 32-bit paranoia. */
320	HMPENDINGIO_32BIT_HACK = 0x7fffffff
321	} HMPENDINGIO;
322
323
324	typedef enum
325	{
326	HMTPRINSTR_INVALID,
327	HMTPRINSTR_READ,
328	HMTPRINSTR_READ_SHR4,
329	HMTPRINSTR_WRITE_REG,
330	HMTPRINSTR_WRITE_IMM,
331	HMTPRINSTR_JUMP_REPLACEMENT,
332	/** The usual 32-bit paranoia. */
333	HMTPRINSTR_32BIT_HACK = 0x7fffffff
334	} HMTPRINSTR;
335
336	typedef struct
337	{
338	/** The key is the address of patched instruction. (32 bits GC ptr) */
339	AVLOU32NODECORE Core;
340	/** Original opcode. */
341	uint8_t aOpcode[16];
342	/** Instruction size. */
343	uint32_t cbOp;
344	/** Replacement opcode. */
345	uint8_t aNewOpcode[16];
346	/** Replacement instruction size. */
347	uint32_t cbNewOp;
348	/** Instruction type. */
349	HMTPRINSTR enmType;
350	/** Source operand. */
351	uint32_t uSrcOperand;
352	/** Destination operand. */
353	uint32_t uDstOperand;
354	/** Number of times the instruction caused a fault. */
355	uint32_t cFaults;
356	/** Patch address of the jump replacement. */
357	RTGCPTR32 pJumpTarget;
358	} HMTPRPATCH;
359	/** Pointer to HMTPRPATCH. */
360	typedef HMTPRPATCH *PHMTPRPATCH;
361
362
363	/**
364	* Makes a HMEXITSTAT::uKey value from a program counter and an exit code.
365	*
366	* @returns 64-bit key
367	* @param a_uPC The RIP + CS.BASE value of the exit.
368	* @param a_uExit The exit code.
369	* @todo Add CPL?
370	*/
371	#define HMEXITSTAT_MAKE_KEY(a_uPC, a_uExit) (((a_uPC) & UINT64_C(0x0000ffffffffffff)) \| (uint64_t)(a_uExit) << 48)
372
373	typedef struct HMEXITINFO
374	{
375	/** See HMEXITSTAT_MAKE_KEY(). */
376	uint64_t uKey;
377	/** Number of recent hits (depreciates with time). */
378	uint32_t volatile cHits;
379	/** The age + lock. */
380	uint16_t volatile uAge;
381	/** Action or action table index. */
382	uint16_t iAction;
383	} HMEXITINFO;
384	AssertCompileSize(HMEXITINFO, 16); /* Lots of these guys, so don't add any unnecessary stuff! */
385
386	typedef struct HMEXITHISTORY
387	{
388	/** The exit timestamp. */
389	uint64_t uTscExit;
390	/** The index of the corresponding HMEXITINFO entry.
391	* UINT32_MAX if none (too many collisions, race, whatever). */
392	uint32_t iExitInfo;
393	/** Figure out later, needed for padding now. */
394	uint32_t uSomeClueOrSomething;
395	} HMEXITHISTORY;
396
397	/**
398	* Switcher function, HC to the special 64-bit RC.
399	*
400	* @param pVM The cross context VM structure.
401	* @param offCpumVCpu Offset from pVM->cpum to pVM->aCpus[idCpu].cpum.
402	* @returns Return code indicating the action to take.
403	*/
404	typedef DECLCALLBACK(int) FNHMSWITCHERHC(PVM pVM, uint32_t offCpumVCpu);
405	/** Pointer to switcher function. */
406	typedef FNHMSWITCHERHC *PFNHMSWITCHERHC;
407
408	/**
409	* HM VM Instance data.
410	* Changes to this must checked against the padding of the hm union in VM!
411	*/
412	typedef struct HM
413	{
414	/** Set when we've initialized VMX or SVM. */
415	bool fInitialized;
416	/** Set if nested paging is enabled. */
417	bool fNestedPaging;
418	/** Set if nested paging is allowed. */
419	bool fAllowNestedPaging;
420	/** Set if large pages are enabled (requires nested paging). */
421	bool fLargePages;
422	/** Set if we can support 64-bit guests or not. */
423	bool fAllow64BitGuests;
424	/** Set when TPR patching is allowed. */
425	bool fTprPatchingAllowed;
426	/** Set when we initialize VT-x or AMD-V once for all CPUs. */
427	bool fGlobalInit;
428	/** Set when TPR patching is active. */
429	bool fTPRPatchingActive;
430	/** Set when the debug facility has breakpoints/events enabled that requires
431	* us to use the debug execution loop in ring-0. */
432	bool fUseDebugLoop;
433	/** Set if hardware APIC virtualization is enabled. */
434	bool fVirtApicRegs;
435	/** Set if posted interrupt processing is enabled. */
436	bool fPostedIntrs;
437	/** Set if indirect branch prediction barrier on VM exit. */
438	bool fIbpbOnVmExit;
439	/** Set if indirect branch prediction barrier on VM entry. */
440	bool fIbpbOnVmEntry;
441	/** Set if host manages speculation control settings. */
442	bool fSpecCtrlByHost;
443	/** Explicit padding. */
444	bool afPadding[2];
445
446	/** Maximum ASID allowed. */
447	uint32_t uMaxAsid;
448	/** The maximum number of resumes loops allowed in ring-0 (safety precaution).
449	* This number is set much higher when RTThreadPreemptIsPending is reliable. */
450	uint32_t cMaxResumeLoops;
451
452	/** Host kernel flags that HM might need to know (SUPKERNELFEATURES_XXX). */
453	uint32_t fHostKernelFeatures;
454
455	/** Size of the guest patch memory block. */
456	uint32_t cbGuestPatchMem;
457	/** Guest allocated memory for patching purposes. */
458	RTGCPTR pGuestPatchMem;
459	/** Current free pointer inside the patch block. */
460	RTGCPTR pFreeGuestPatchMem;
461
462	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
463	/** 32 to 64 bits switcher entrypoint. */
464	R0PTRTYPE(PFNHMSWITCHERHC) pfnHost32ToGuest64R0;
465	RTR0PTR pvR0Alignment0;
466	#endif
467
468	struct
469	{
470	/** Set by the ring-0 side of HM to indicate VMX is supported by the
471	* CPU. */
472	bool fSupported;
473	/** Set when we've enabled VMX. */
474	bool fEnabled;
475	/** Set if VPID is supported. */
476	bool fVpid;
477	/** Set if VT-x VPID is allowed. */
478	bool fAllowVpid;
479	/** Set if unrestricted guest execution is in use (real and protected mode without paging). */
480	bool fUnrestrictedGuest;
481	/** Set if unrestricted guest execution is allowed to be used. */
482	bool fAllowUnrestricted;
483	/** Whether we're using the preemption timer or not. */
484	bool fUsePreemptTimer;
485	/** The shift mask employed by the VMX-Preemption timer. */
486	uint8_t cPreemptTimerShift;
487
488	/** Virtual address of the TSS page used for real mode emulation. */
489	R3PTRTYPE(PVBOXTSS) pRealModeTSS;
490	/** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
491	R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
492
493	/** Physical address of the APIC-access page. */
494	RTHCPHYS HCPhysApicAccess;
495	/** R0 memory object for the APIC-access page. */
496	RTR0MEMOBJ hMemObjApicAccess;
497	/** Virtual address of the APIC-access page. */
498	R0PTRTYPE(uint8_t *) pbApicAccess;
499
500	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
501	RTHCPHYS HCPhysScratch;
502	RTR0MEMOBJ hMemObjScratch;
503	R0PTRTYPE(uint8_t *) pbScratch;
504	#endif
505
506	/** Internal Id of which flush-handler to use for tagged-TLB entries. */
507	uint32_t uFlushTaggedTlb;
508
509	/** Pause-loop exiting (PLE) gap in ticks. */
510	uint32_t cPleGapTicks;
511	/** Pause-loop exiting (PLE) window in ticks. */
512	uint32_t cPleWindowTicks;
513	uint32_t u32Alignment0;
514
515	/** Host CR4 value (set by ring-0 VMX init) */
516	uint64_t u64HostCr4;
517	/** Host SMM monitor control (set by ring-0 VMX init) */
518	uint64_t u64HostSmmMonitorCtl;
519	/** Host EFER value (set by ring-0 VMX init) */
520	uint64_t u64HostEfer;
521	/** Whether the CPU supports VMCS fields for swapping EFER. */
522	bool fSupportsVmcsEfer;
523	uint8_t u8Alignment2[7];
524
525	/** VMX MSR values. */
526	VMXMSRS Msrs;
527
528	/** Flush types for invept & invvpid; they depend on capabilities. */
529	VMXFLUSHEPT enmFlushEpt;
530	VMXFLUSHVPID enmFlushVpid;
531
532	/** Host-physical address for a failing VMXON instruction. */
533	RTHCPHYS HCPhysVmxEnableError;
534	} vmx;
535
536	struct
537	{
538	/** Set by the ring-0 side of HM to indicate SVM is supported by the
539	* CPU. */
540	bool fSupported;
541	/** Set when we've enabled SVM. */
542	bool fEnabled;
543	/** Set if erratum 170 affects the AMD cpu. */
544	bool fAlwaysFlushTLB;
545	/** Set when the hack to ignore VERR_SVM_IN_USE is active. */
546	bool fIgnoreInUseError;
547	/** Whether to use virtualized VMSAVE/VMLOAD feature. */
548	bool fVirtVmsaveVmload;
549	/** Whether to use virtual GIF feature. */
550	bool fVGif;
551	uint8_t u8Alignment0[2];
552
553	/** Physical address of the IO bitmap (12kb). */
554	RTHCPHYS HCPhysIOBitmap;
555	/** R0 memory object for the IO bitmap (12kb). */
556	RTR0MEMOBJ hMemObjIOBitmap;
557	/** Virtual address of the IO bitmap. */
558	R0PTRTYPE(void *) pvIOBitmap;
559
560	/* HWCR MSR (for diagnostics) */
561	uint64_t u64MsrHwcr;
562
563	/** SVM revision. */
564	uint32_t u32Rev;
565	/** SVM feature bits from cpuid 0x8000000a */
566	uint32_t u32Features;
567
568	/** Pause filter counter. */
569	uint16_t cPauseFilter;
570	/** Pause filter treshold in ticks. */
571	uint16_t cPauseFilterThresholdTicks;
572	uint32_t u32Alignment0;
573	} svm;
574
575	/**
576	* AVL tree with all patches (active or disabled) sorted by guest instruction
577	* address.
578	*/
579	AVLOU32TREE PatchTree;
580	uint32_t cPatches;
581	HMTPRPATCH aPatches[64];
582
583	struct
584	{
585	uint32_t u32AMDFeatureECX;
586	uint32_t u32AMDFeatureEDX;
587	} cpuid;
588
589	/** Saved error from detection */
590	int32_t lLastError;
591
592	/** HMR0Init was run */
593	bool fHMR0Init;
594	bool u8Alignment1[3];
595
596	STAMCOUNTER StatTprPatchSuccess;
597	STAMCOUNTER StatTprPatchFailure;
598	STAMCOUNTER StatTprReplaceSuccessCr8;
599	STAMCOUNTER StatTprReplaceSuccessVmc;
600	STAMCOUNTER StatTprReplaceFailure;
601	} HM;
602	/** Pointer to HM VM instance data. */
603	typedef HM *PHM;
604
605	AssertCompileMemberAlignment(HM, StatTprPatchSuccess, 8);
606
607	/* Maximum number of cached entries. */
608	#define VMCSCACHE_MAX_ENTRY 128
609
610	/**
611	* Structure for storing read and write VMCS actions.
612	*/
613	typedef struct VMCSCACHE
614	{
615	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
616	/* Magic marker for searching in crash dumps. */
617	uint8_t aMagic[16];
618	uint64_t uMagic;
619	uint64_t u64TimeEntry;
620	uint64_t u64TimeSwitch;
621	uint64_t cResume;
622	uint64_t interPD;
623	uint64_t pSwitcher;
624	uint32_t uPos;
625	uint32_t idCpu;
626	#endif
627	/* CR2 is saved here for EPT syncing. */
628	uint64_t cr2;
629	struct
630	{
631	uint32_t cValidEntries;
632	uint32_t uAlignment;
633	uint32_t aField[VMCSCACHE_MAX_ENTRY];
634	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
635	} Write;
636	struct
637	{
638	uint32_t cValidEntries;
639	uint32_t uAlignment;
640	uint32_t aField[VMCSCACHE_MAX_ENTRY];
641	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
642	} Read;
643	#ifdef VBOX_STRICT
644	struct
645	{
646	RTHCPHYS HCPhysCpuPage;
647	RTHCPHYS HCPhysVmcs;
648	RTGCPTR pCache;
649	RTGCPTR pCtx;
650	} TestIn;
651	struct
652	{
653	RTHCPHYS HCPhysVmcs;
654	RTGCPTR pCache;
655	RTGCPTR pCtx;
656	uint64_t eflags;
657	uint64_t cr8;
658	} TestOut;
659	struct
660	{
661	uint64_t param1;
662	uint64_t param2;
663	uint64_t param3;
664	uint64_t param4;
665	} ScratchPad;
666	#endif
667	} VMCSCACHE;
668	/** Pointer to VMCSCACHE. */
669	typedef VMCSCACHE *PVMCSCACHE;
670	AssertCompileSizeAlignment(VMCSCACHE, 8);
671
672	/**
673	* VMX StartVM function.
674	*
675	* @returns VBox status code (no informational stuff).
676	* @param fResume Whether to use VMRESUME (true) or VMLAUNCH (false).
677	* @param pCtx The CPU register context.
678	* @param pCache The VMCS cache.
679	* @param pVM Pointer to the cross context VM structure.
680	* @param pVCpu Pointer to the cross context per-CPU structure.
681	*/
682	typedef DECLCALLBACK(int) FNHMVMXSTARTVM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);
683	/** Pointer to a VMX StartVM function. */
684	typedef R0PTRTYPE(FNHMVMXSTARTVM *) PFNHMVMXSTARTVM;
685
686	/** SVM VMRun function. */
687	typedef DECLCALLBACK(int) FNHMSVMVMRUN(RTHCPHYS pVmcbHostPhys, RTHCPHYS pVmcbPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu);
688	/** Pointer to a SVM VMRun function. */
689	typedef R0PTRTYPE(FNHMSVMVMRUN *) PFNHMSVMVMRUN;
690
691	/**
692	* HM VMCPU Instance data.
693	*
694	* Note! If you change members of this struct, make sure to check if the
695	* assembly counterpart in HMInternal.mac needs to be updated as well.
696	*/
697	typedef struct HMCPU
698	{
699	/** Set if we need to flush the TLB during the world switch. */
700	bool fForceTLBFlush;
701	/** Set when we're using VT-x or AMD-V at that moment. */
702	bool fActive;
703	/** Set when the TLB has been checked until we return from the world switch. */
704	volatile bool fCheckedTLBFlush;
705	/** Whether we've completed the inner HM leave function. */
706	bool fLeaveDone;
707	/** Whether we're using the hyper DR7 or guest DR7. */
708	bool fUsingHyperDR7;
709	/** Whether to preload the guest-FPU state to avoid \#NM VM-exit overhead. */
710	bool fPreloadGuestFpu;
711	/** Set if XCR0 needs to be loaded and saved when entering and exiting guest
712	* code execution. */
713	bool fLoadSaveGuestXcr0;
714
715	/** Whether we should use the debug loop because of single stepping or special
716	* debug breakpoints / events are armed. */
717	bool fUseDebugLoop;
718	/** Whether we are currently executing in the debug loop.
719	* Mainly for assertions. */
720	bool fUsingDebugLoop;
721	/** Set if we using the debug loop and wish to intercept RDTSC. */
722	bool fDebugWantRdTscExit;
723	/** Whether we're executing a single instruction. */
724	bool fSingleInstruction;
725	/** Set if we need to clear the trap flag because of single stepping. */
726	bool fClearTrapFlag;
727
728	/** Whether \#UD needs to be intercepted (required by certain GIM providers). */
729	bool fGIMTrapXcptUD;
730	/** Whether paravirt. hypercalls are enabled. */
731	bool fHypercallsEnabled;
732	uint8_t u8Alignment0[2];
733
734	/** World switch exit counter. */
735	volatile uint32_t cWorldSwitchExits;
736	/** HM_CHANGED_* flags. */
737	volatile uint32_t fContextUseFlags;
738	/** Id of the last cpu we were executing code on (NIL_RTCPUID for the first
739	* time). */
740	RTCPUID idLastCpu;
741	/** TLB flush count. */
742	uint32_t cTlbFlushes;
743	/** Current ASID in use by the VM. */
744	uint32_t uCurrentAsid;
745	/** An additional error code used for some gurus. */
746	uint32_t u32HMError;
747	/** Host's TSC_AUX MSR (used when RDTSCP doesn't cause VM-exits). */
748	uint64_t u64HostTscAux;
749
750	struct
751	{
752	/** Ring 0 handlers for VT-x. */
753	PFNHMVMXSTARTVM pfnStartVM;
754	#if HC_ARCH_BITS == 32
755	uint32_t u32Alignment0;
756	#endif
757	/** Current VMX_VMCS32_CTRL_PIN_EXEC. */
758	uint32_t u32PinCtls;
759	/** Current VMX_VMCS32_CTRL_PROC_EXEC. */
760	uint32_t u32ProcCtls;
761	/** Current VMX_VMCS32_CTRL_PROC_EXEC2. */
762	uint32_t u32ProcCtls2;
763	/** Current VMX_VMCS32_CTRL_EXIT. */
764	uint32_t u32ExitCtls;
765	/** Current VMX_VMCS32_CTRL_ENTRY. */
766	uint32_t u32EntryCtls;
767
768	/** Current CR0 mask. */
769	uint32_t u32CR0Mask;
770	/** Current CR4 mask. */
771	uint32_t u32CR4Mask;
772	/** Current exception bitmap. */
773	uint32_t u32XcptBitmap;
774	/** The updated-guest-state mask. */
775	volatile uint32_t fUpdatedGuestState;
776	uint32_t u32Alignment1;
777
778	/** Physical address of the VM control structure (VMCS). */
779	RTHCPHYS HCPhysVmcs;
780	/** R0 memory object for the VM control structure (VMCS). */
781	RTR0MEMOBJ hMemObjVmcs;
782	/** Virtual address of the VM control structure (VMCS). */
783	R0PTRTYPE(void *) pvVmcs;
784
785	/** Physical address of the virtual APIC page for TPR caching. */
786	RTHCPHYS HCPhysVirtApic;
787	/** Padding. */
788	R0PTRTYPE(void *) pvAlignment0;
789	/** Virtual address of the virtual APIC page for TPR caching. */
790	R0PTRTYPE(uint8_t *) pbVirtApic;
791
792	/** Physical address of the MSR bitmap. */
793	RTHCPHYS HCPhysMsrBitmap;
794	/** R0 memory object for the MSR bitmap. */
795	RTR0MEMOBJ hMemObjMsrBitmap;
796	/** Virtual address of the MSR bitmap. */
797	R0PTRTYPE(void *) pvMsrBitmap;
798
799	/** Physical address of the VM-entry MSR-load and VM-exit MSR-store area (used
800	* for guest MSRs). */
801	RTHCPHYS HCPhysGuestMsr;
802	/** R0 memory object of the VM-entry MSR-load and VM-exit MSR-store area
803	* (used for guest MSRs). */
804	RTR0MEMOBJ hMemObjGuestMsr;
805	/** Virtual address of the VM-entry MSR-load and VM-exit MSR-store area (used
806	* for guest MSRs). */
807	R0PTRTYPE(void *) pvGuestMsr;
808
809	/** Physical address of the VM-exit MSR-load area (used for host MSRs). */
810	RTHCPHYS HCPhysHostMsr;
811	/** R0 memory object for the VM-exit MSR-load area (used for host MSRs). */
812	RTR0MEMOBJ hMemObjHostMsr;
813	/** Virtual address of the VM-exit MSR-load area (used for host MSRs). */
814	R0PTRTYPE(void *) pvHostMsr;
815
816	/** Current EPTP. */
817	RTHCPHYS HCPhysEPTP;
818
819	/** Number of guest/host MSR pairs in the auto-load/store area. */
820	uint32_t cMsrs;
821	/** Whether the host MSR values are up-to-date in the auto-load/store area. */
822	bool fUpdatedHostMsrs;
823	uint8_t u8Alignment0[3];
824
825	/** Host LSTAR MSR value to restore lazily while leaving VT-x. */
826	uint64_t u64HostLStarMsr;
827	/** Host STAR MSR value to restore lazily while leaving VT-x. */
828	uint64_t u64HostStarMsr;
829	/** Host SF_MASK MSR value to restore lazily while leaving VT-x. */
830	uint64_t u64HostSFMaskMsr;
831	/** Host KernelGS-Base MSR value to restore lazily while leaving VT-x. */
832	uint64_t u64HostKernelGSBaseMsr;
833	/** A mask of which MSRs have been swapped and need restoration. */
834	uint32_t fLazyMsrs;
835	uint32_t u32Alignment2;
836
837	/** The cached APIC-base MSR used for identifying when to map the HC physical APIC-access page. */
838	uint64_t u64MsrApicBase;
839	/** Last use TSC offset value. (cached) */
840	uint64_t u64TSCOffset;
841
842	/** VMCS cache. */
843	VMCSCACHE VMCSCache;
844
845	/** Real-mode emulation state. */
846	struct
847	{
848	X86DESCATTR AttrCS;
849	X86DESCATTR AttrDS;
850	X86DESCATTR AttrES;
851	X86DESCATTR AttrFS;
852	X86DESCATTR AttrGS;
853	X86DESCATTR AttrSS;
854	X86EFLAGS Eflags;
855	uint32_t fRealOnV86Active;
856	} RealMode;
857
858	/** VT-x error-reporting (mainly for ring-3 propagation). */
859	struct
860	{
861	uint64_t u64VMCSPhys;
862	uint32_t u32VMCSRevision;
863	uint32_t u32InstrError;
864	uint32_t u32ExitReason;
865	RTCPUID idEnteredCpu;
866	RTCPUID idCurrentCpu;
867	uint32_t u32Alignment0;
868	} LastError;
869
870	/** Current state of the VMCS. */
871	uint32_t uVmcsState;
872	/** Which host-state bits to restore before being preempted. */
873	uint32_t fRestoreHostFlags;
874	/** The host-state restoration structure. */
875	VMXRESTOREHOST RestoreHost;
876
877	/** Set if guest was executing in real mode (extra checks). */
878	bool fWasInRealMode;
879	/** Set if guest switched to 64-bit mode on a 32-bit host. */
880	bool fSwitchedTo64on32;
881
882	uint8_t u8Alignment1[6];
883	} vmx;
884
885	struct
886	{
887	/** Ring 0 handlers for VT-x. */
888	PFNHMSVMVMRUN pfnVMRun;
889	#if HC_ARCH_BITS == 32
890	uint32_t u32Alignment0;
891	#endif
892
893	/** Physical address of the host VMCB which holds additional host-state. */
894	RTHCPHYS HCPhysVmcbHost;
895	/** R0 memory object for the host VMCB which holds additional host-state. */
896	RTR0MEMOBJ hMemObjVmcbHost;
897	/** Padding. */
898	R0PTRTYPE(void *) pvPadding;
899
900	/** Physical address of the guest VMCB. */
901	RTHCPHYS HCPhysVmcb;
902	/** R0 memory object for the guest VMCB. */
903	RTR0MEMOBJ hMemObjVmcb;
904	/** Pointer to the guest VMCB. */
905	R0PTRTYPE(PSVMVMCB) pVmcb;
906
907	/** Physical address of the MSR bitmap (8 KB). */
908	RTHCPHYS HCPhysMsrBitmap;
909	/** R0 memory object for the MSR bitmap (8 KB). */
910	RTR0MEMOBJ hMemObjMsrBitmap;
911	/** Pointer to the MSR bitmap. */
912	R0PTRTYPE(void *) pvMsrBitmap;
913
914	/** Whether VTPR with V_INTR_MASKING set is in effect, indicating
915	* we should check if the VTPR changed on every VM-exit. */
916	bool fSyncVTpr;
917	uint8_t u8Alignment0[7];
918
919	/** Cache of the nested-guest's VMCB fields that we modify in order to run the
920	* nested-guest using AMD-V. This will be restored on \#VMEXIT. */
921	SVMNESTEDVMCBCACHE NstGstVmcbCache;
922	} svm;
923
924	/** Event injection state. */
925	struct
926	{
927	uint32_t fPending;
928	uint32_t u32ErrCode;
929	uint32_t cbInstr;
930	uint32_t u32Padding; /*< Explicit alignment padding. /
931	uint64_t u64IntInfo;
932	RTGCUINTPTR GCPtrFaultAddress;
933	} Event;
934
935	/** IO Block emulation state. */
936	struct
937	{
938	bool fEnabled;
939	uint8_t u8Align[7];
940
941	/** RIP at the start of the io code we wish to emulate in the recompiler. */
942	RTGCPTR GCPtrFunctionEip;
943
944	uint64_t cr0;
945	} EmulateIoBlock;
946
947	/* */
948	struct
949	{
950	/** Pending IO operation type. */
951	HMPENDINGIO enmType;
952	uint32_t u32Alignment0;
953	RTGCPTR GCPtrRip;
954	RTGCPTR GCPtrRipNext;
955	union
956	{
957	struct
958	{
959	uint32_t uPort;
960	uint32_t uAndVal;
961	uint32_t cbSize;
962	} Port;
963	uint64_t aRaw[2];
964	} s;
965	} PendingIO;
966
967	/** The PAE PDPEs used with Nested Paging (only valid when
968	* VMCPU_FF_HM_UPDATE_PAE_PDPES is set). */
969	X86PDPE aPdpes[4];
970
971	/** Current shadow paging mode. */
972	PGMMODE enmShadowMode;
973
974	/** The CPU ID of the CPU currently owning the VMCS. Set in
975	* HMR0Enter and cleared in HMR0Leave. */
976	RTCPUID idEnteredCpu;
977
978	/** VT-x/AMD-V VM-exit/\#VMXEXIT history, circular array. */
979	uint16_t auExitHistory[31];
980	/** The index of the next free slot in the history array. */
981	uint16_t idxExitHistoryFree;
982
983	/** For saving stack space, the disassembler state is allocated here instead of
984	* on the stack. */
985	DISCPUSTATE DisState;
986
987	STAMPROFILEADV StatEntry;
988	STAMPROFILEADV StatExit1;
989	STAMPROFILEADV StatExit2;
990	STAMPROFILEADV StatExitIO;
991	STAMPROFILEADV StatExitMovCRx;
992	STAMPROFILEADV StatExitXcptNmi;
993	STAMPROFILEADV StatLoadGuestState;
994	STAMPROFILEADV StatLoadGuestFpuState;
995	STAMPROFILEADV StatInGC;
996
997	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
998	STAMPROFILEADV StatWorldSwitch3264;
999	#endif
1000	STAMPROFILEADV StatPoke;
1001	STAMPROFILEADV StatSpinPoke;
1002	STAMPROFILEADV StatSpinPokeFailed;
1003
1004	STAMCOUNTER StatInjectInterrupt;
1005	STAMCOUNTER StatInjectXcpt;
1006	STAMCOUNTER StatInjectPendingReflect;
1007	STAMCOUNTER StatInjectPendingInterpret;
1008
1009	STAMCOUNTER StatExitAll;
1010	STAMCOUNTER StatExitShadowNM;
1011	STAMCOUNTER StatExitGuestNM;
1012	STAMCOUNTER StatExitShadowPF; /*< Misleading, currently used for MMIO \#PFs as well. /
1013	STAMCOUNTER StatExitShadowPFEM;
1014	STAMCOUNTER StatExitGuestPF;
1015	STAMCOUNTER StatExitGuestUD;
1016	STAMCOUNTER StatExitGuestSS;
1017	STAMCOUNTER StatExitGuestNP;
1018	STAMCOUNTER StatExitGuestTS;
1019	STAMCOUNTER StatExitGuestGP;
1020	STAMCOUNTER StatExitGuestDE;
1021	STAMCOUNTER StatExitGuestDB;
1022	STAMCOUNTER StatExitGuestMF;
1023	STAMCOUNTER StatExitGuestBP;
1024	STAMCOUNTER StatExitGuestXF;
1025	STAMCOUNTER StatExitGuestXcpUnk;
1026	STAMCOUNTER StatExitInvlpg;
1027	STAMCOUNTER StatExitInvd;
1028	STAMCOUNTER StatExitWbinvd;
1029	STAMCOUNTER StatExitPause;
1030	STAMCOUNTER StatExitCpuid;
1031	STAMCOUNTER StatExitRdtsc;
1032	STAMCOUNTER StatExitRdtscp;
1033	STAMCOUNTER StatExitRdpmc;
1034	STAMCOUNTER StatExitVmcall;
1035	STAMCOUNTER StatExitRdrand;
1036	STAMCOUNTER StatExitCli;
1037	STAMCOUNTER StatExitSti;
1038	STAMCOUNTER StatExitPushf;
1039	STAMCOUNTER StatExitPopf;
1040	STAMCOUNTER StatExitIret;
1041	STAMCOUNTER StatExitInt;
1042	STAMCOUNTER StatExitCRxWrite[16];
1043	STAMCOUNTER StatExitCRxRead[16];
1044	STAMCOUNTER StatExitDRxWrite;
1045	STAMCOUNTER StatExitDRxRead;
1046	STAMCOUNTER StatExitRdmsr;
1047	STAMCOUNTER StatExitWrmsr;
1048	STAMCOUNTER StatExitClts;
1049	STAMCOUNTER StatExitXdtrAccess;
1050	STAMCOUNTER StatExitHlt;
1051	STAMCOUNTER StatExitMwait;
1052	STAMCOUNTER StatExitMonitor;
1053	STAMCOUNTER StatExitLmsw;
1054	STAMCOUNTER StatExitIOWrite;
1055	STAMCOUNTER StatExitIORead;
1056	STAMCOUNTER StatExitIOStringWrite;
1057	STAMCOUNTER StatExitIOStringRead;
1058	STAMCOUNTER StatExitIntWindow;
1059	STAMCOUNTER StatExitExtInt;
1060	STAMCOUNTER StatExitHostNmiInGC;
1061	STAMCOUNTER StatExitPreemptTimer;
1062	STAMCOUNTER StatExitTprBelowThreshold;
1063	STAMCOUNTER StatExitTaskSwitch;
1064	STAMCOUNTER StatExitMtf;
1065	STAMCOUNTER StatExitApicAccess;
1066	STAMCOUNTER StatPendingHostIrq;
1067
1068	STAMCOUNTER StatFlushPage;
1069	STAMCOUNTER StatFlushPageManual;
1070	STAMCOUNTER StatFlushPhysPageManual;
1071	STAMCOUNTER StatFlushTlb;
1072	STAMCOUNTER StatFlushTlbManual;
1073	STAMCOUNTER StatFlushTlbWorldSwitch;
1074	STAMCOUNTER StatNoFlushTlbWorldSwitch;
1075	STAMCOUNTER StatFlushEntire;
1076	STAMCOUNTER StatFlushAsid;
1077	STAMCOUNTER StatFlushNestedPaging;
1078	STAMCOUNTER StatFlushTlbInvlpgVirt;
1079	STAMCOUNTER StatFlushTlbInvlpgPhys;
1080	STAMCOUNTER StatTlbShootdown;
1081	STAMCOUNTER StatTlbShootdownFlush;
1082
1083	STAMCOUNTER StatSwitchTprMaskedIrq;
1084	STAMCOUNTER StatSwitchGuestIrq;
1085	STAMCOUNTER StatSwitchHmToR3FF;
1086	STAMCOUNTER StatSwitchExitToR3;
1087	STAMCOUNTER StatSwitchLongJmpToR3;
1088	STAMCOUNTER StatSwitchMaxResumeLoops;
1089	STAMCOUNTER StatSwitchHltToR3;
1090	STAMCOUNTER StatSwitchApicAccessToR3;
1091	STAMCOUNTER StatSwitchPreempt;
1092	STAMCOUNTER StatSwitchPreemptSaveHostState;
1093
1094	STAMCOUNTER StatTscParavirt;
1095	STAMCOUNTER StatTscOffset;
1096	STAMCOUNTER StatTscIntercept;
1097
1098	STAMCOUNTER StatExitReasonNpf;
1099	STAMCOUNTER StatDRxArmed;
1100	STAMCOUNTER StatDRxContextSwitch;
1101	STAMCOUNTER StatDRxIoCheck;
1102
1103	STAMCOUNTER StatLoadMinimal;
1104	STAMCOUNTER StatLoadFull;
1105	STAMCOUNTER StatLoadGuestFpu;
1106
1107	STAMCOUNTER StatVmxCheckBadRmSelBase;
1108	STAMCOUNTER StatVmxCheckBadRmSelLimit;
1109	STAMCOUNTER StatVmxCheckRmOk;
1110
1111	STAMCOUNTER StatVmxCheckBadSel;
1112	STAMCOUNTER StatVmxCheckBadRpl;
1113	STAMCOUNTER StatVmxCheckBadLdt;
1114	STAMCOUNTER StatVmxCheckBadTr;
1115	STAMCOUNTER StatVmxCheckPmOk;
1116
1117	STAMCOUNTER StatNestedExitReasonNpf;
1118
1119	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1120	STAMCOUNTER StatFpu64SwitchBack;
1121	STAMCOUNTER StatDebug64SwitchBack;
1122	#endif
1123
1124	#ifdef VBOX_WITH_STATISTICS
1125	R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
1126	R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
1127	R3PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqs;
1128	R0PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqsR0;
1129	R3PTRTYPE(PSTAMCOUNTER) paStatNestedExitReason;
1130	R0PTRTYPE(PSTAMCOUNTER) paStatNestedExitReasonR0;
1131	#endif
1132	#ifdef HM_PROFILE_EXIT_DISPATCH
1133	STAMPROFILEADV StatExitDispatch;
1134	#endif
1135	} HMCPU;
1136	/** Pointer to HM VMCPU instance data. */
1137	typedef HMCPU *PHMCPU;
1138	AssertCompileMemberAlignment(HMCPU, vmx, 8);
1139	AssertCompileMemberAlignment(HMCPU, svm, 8);
1140	AssertCompileMemberAlignment(HMCPU, Event, 8);
1141
1142	#ifdef IN_RING0
1143	VMMR0_INT_DECL(PHMGLOBALCPUINFO) hmR0GetCurrentCpu(void);
1144
1145	# ifdef VBOX_STRICT
1146	VMMR0_INT_DECL(void) hmR0DumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
1147	VMMR0_INT_DECL(void) hmR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg);
1148	# else
1149	# define hmR0DumpRegs(a, b ,c) do { } while (0)
1150	# define hmR0DumpDescriptor(a, b, c) do { } while (0)
1151	# endif /* VBOX_STRICT */
1152
1153	# ifdef VBOX_WITH_KERNEL_USING_XMM
1154	DECLASM(int) hmR0VMXStartVMWrapXMM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu, PFNHMVMXSTARTVM pfnStartVM);
1155	DECLASM(int) hmR0SVMRunWrapXMM(RTHCPHYS pVmcbHostPhys, RTHCPHYS pVmcbPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu, PFNHMSVMVMRUN pfnVMRun);
1156	# endif
1157
1158	#endif /* IN_RING0 */
1159
1160	/** @} */
1161
1162	RT_C_DECLS_END
1163
1164	#endif
1165

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source: vbox/trunk/src/VBox/VMM/include/HMInternal.h@ 71688

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