HMInternal.h@ 72079

Last change on this file since 72079 was 71910, checked in by vboxsync, 7 years ago
VMM/HM: Clean up and also fix HMR0EnsureCompleteBasicContext for AMD-V which also selectively re-loads guest state back into the VMCB.
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 45.7 KB

Line
1	/* $Id: HMInternal.h 71910 2018-04-19 08:54:23Z vboxsync $ */
2	/** @file
3	* HM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef ___HMInternal_h
19	#define ___HMInternal_h
20
21	#include <VBox/cdefs.h>
22	#include <VBox/types.h>
23	#include <VBox/vmm/em.h>
24	#include <VBox/vmm/stam.h>
25	#include <VBox/dis.h>
26	#include <VBox/vmm/hm.h>
27	#include <VBox/vmm/hm_vmx.h>
28	#include <VBox/vmm/hm_svm.h>
29	#include <VBox/vmm/pgm.h>
30	#include <VBox/vmm/cpum.h>
31	#include <VBox/vmm/trpm.h>
32	#include <iprt/memobj.h>
33	#include <iprt/cpuset.h>
34	#include <iprt/mp.h>
35	#include <iprt/avl.h>
36	#include <iprt/string.h>
37
38	#if defined(RT_OS_DARWIN) && HC_ARCH_BITS == 32
39	# error "32-bit darwin is no longer supported. Go back to 4.3 or earlier!"
40	#endif
41
42	#if HC_ARCH_BITS == 64 \|\| defined (VBOX_WITH_64_BITS_GUESTS)
43	/* Enable 64 bits guest support. */
44	# define VBOX_ENABLE_64_BITS_GUESTS
45	#endif
46
47	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
48	# define VMX_USE_CACHED_VMCS_ACCESSES
49	#endif
50
51	/** @def HM_PROFILE_EXIT_DISPATCH
52	* Enables profiling of the VM exit handler dispatching. */
53	#if 0 \|\| defined(DOXYGEN_RUNNING)
54	# define HM_PROFILE_EXIT_DISPATCH
55	#endif
56
57	RT_C_DECLS_BEGIN
58
59
60	/** @defgroup grp_hm_int Internal
61	* @ingroup grp_hm
62	* @internal
63	* @{
64	*/
65
66	/** @def HMCPU_CF_CLEAR
67	* Clears a HM-context flag.
68	*
69	* @param pVCpu The cross context virtual CPU structure.
70	* @param fFlag The flag to clear.
71	*/
72	#define HMCPU_CF_CLEAR(pVCpu, fFlag) (ASMAtomicUoAndU32(&(pVCpu)->hm.s.fContextUseFlags, ~(fFlag)))
73
74	/** @def HMCPU_CF_SET
75	* Sets a HM-context flag.
76	*
77	* @param pVCpu The cross context virtual CPU structure.
78	* @param fFlag The flag to set.
79	*/
80	#define HMCPU_CF_SET(pVCpu, fFlag) (ASMAtomicUoOrU32(&(pVCpu)->hm.s.fContextUseFlags, (fFlag)))
81
82	/** @def HMCPU_CF_IS_SET
83	* Checks if all the flags in the specified HM-context set is pending.
84	*
85	* @param pVCpu The cross context virtual CPU structure.
86	* @param fFlag The flag to check.
87	*/
88	#define HMCPU_CF_IS_SET(pVCpu, fFlag) ((ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags) & (fFlag)) == (fFlag))
89
90	/** @def HMCPU_CF_IS_PENDING
91	* Checks if one or more of the flags in the specified HM-context set is
92	* pending.
93	*
94	* @param pVCpu The cross context virtual CPU structure.
95	* @param fFlags The flags to check for.
96	*/
97	#define HMCPU_CF_IS_PENDING(pVCpu, fFlags) RT_BOOL(ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags) & (fFlags))
98
99	/** @def HMCPU_CF_IS_PENDING_ONLY
100	* Checks if -only- one or more of the specified HM-context flags is pending.
101	*
102	* @param pVCpu The cross context virtual CPU structure.
103	* @param fFlags The flags to check for.
104	*/
105	#define HMCPU_CF_IS_PENDING_ONLY(pVCpu, fFlags) !RT_BOOL(ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags) & ~(fFlags))
106
107	/** @def HMCPU_CF_IS_SET_ONLY
108	* Checks if -only- all the flags in the specified HM-context set is pending.
109	*
110	* @param pVCpu The cross context virtual CPU structure.
111	* @param fFlags The flags to check for.
112	*/
113	#define HMCPU_CF_IS_SET_ONLY(pVCpu, fFlags) (ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags) == (fFlags))
114
115	/** @def HMCPU_CF_RESET_TO
116	* Resets the HM-context flags to the specified value.
117	*
118	* @param pVCpu The cross context virtual CPU structure.
119	* @param fFlags The new value.
120	*/
121	#define HMCPU_CF_RESET_TO(pVCpu, fFlags) (ASMAtomicUoWriteU32(&(pVCpu)->hm.s.fContextUseFlags, (fFlags)))
122
123	/** @def HMCPU_CF_VALUE
124	* Returns the current HM-context flags value.
125	*
126	* @param pVCpu The cross context virtual CPU structure.
127	*/
128	#define HMCPU_CF_VALUE(pVCpu) (ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags))
129
130
131	/** Resets/initializes the VM-exit/\#VMEXIT history array. */
132	#define HMCPU_EXIT_HISTORY_RESET(pVCpu) (memset(&(pVCpu)->hm.s.auExitHistory, 0xff, sizeof((pVCpu)->hm.s.auExitHistory)))
133
134	/** Updates the VM-exit/\#VMEXIT history array. */
135	#define HMCPU_EXIT_HISTORY_ADD(pVCpu, a_ExitReason) \
136	do { \
137	AssertMsg((pVCpu)->hm.s.idxExitHistoryFree < RT_ELEMENTS((pVCpu)->hm.s.auExitHistory), ("%u\n", (pVCpu)->hm.s.idxExitHistoryFree)); \
138	(pVCpu)->hm.s.auExitHistory[(pVCpu)->hm.s.idxExitHistoryFree++] = (uint16_t)(a_ExitReason); \
139	if ((pVCpu)->hm.s.idxExitHistoryFree == RT_ELEMENTS((pVCpu)->hm.s.auExitHistory)) \
140	(pVCpu)->hm.s.idxExitHistoryFree = 0; \
141	(pVCpu)->hm.s.auExitHistory[(pVCpu)->hm.s.idxExitHistoryFree] = UINT16_MAX; \
142	} while (0)
143
144	/** Maximum number of exit reason statistics counters. */
145	#define MAX_EXITREASON_STAT 0x100
146	#define MASK_EXITREASON_STAT 0xff
147	#define MASK_INJECT_IRQ_STAT 0xff
148
149	/** @name HM changed flags.
150	* These flags are used to keep track of which important registers that have
151	* been changed since last they were reset.
152	*
153	* Flags marked "shared" are used for registers that are common to both the host
154	* and guest (i.e. without dedicated VMCS/VMCB fields for guest bits).
155	*
156	* @{
157	*/
158	#define HM_CHANGED_GUEST_CR0 RT_BIT(0) /* Shared */
159	#define HM_CHANGED_GUEST_CR3 RT_BIT(1)
160	#define HM_CHANGED_GUEST_CR4 RT_BIT(2)
161	#define HM_CHANGED_GUEST_GDTR RT_BIT(3)
162	#define HM_CHANGED_GUEST_IDTR RT_BIT(4)
163	#define HM_CHANGED_GUEST_LDTR RT_BIT(5)
164	#define HM_CHANGED_GUEST_TR RT_BIT(6)
165	#define HM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(7)
166	#define HM_CHANGED_GUEST_DEBUG RT_BIT(8) /* Shared */
167	#define HM_CHANGED_GUEST_RIP RT_BIT(9)
168	#define HM_CHANGED_GUEST_RSP RT_BIT(10)
169	#define HM_CHANGED_GUEST_RFLAGS RT_BIT(11)
170	#define HM_CHANGED_GUEST_CR2 RT_BIT(12)
171	#define HM_CHANGED_GUEST_SYSENTER_CS_MSR RT_BIT(13)
172	#define HM_CHANGED_GUEST_SYSENTER_EIP_MSR RT_BIT(14)
173	#define HM_CHANGED_GUEST_SYSENTER_ESP_MSR RT_BIT(15)
174	#define HM_CHANGED_GUEST_EFER_MSR RT_BIT(16)
175	#define HM_CHANGED_GUEST_APIC_STATE RT_BIT(17)
176	#define HM_CHANGED_GUEST_HWVIRT RT_BIT(18)
177	/* Logically common VMM state. */
178	#define HM_CHANGED_VMM_GUEST_XCPT_INTERCEPTS RT_BIT(19)
179	#define HM_CHANGED_VMM_GUEST_LAZY_MSRS RT_BIT(20)
180	/* VT-x specific state. */
181	#define HM_CHANGED_VMX_GUEST_AUTO_MSRS RT_BIT(21)
182	#define HM_CHANGED_VMX_GUEST_ACTIVITY_STATE RT_BIT(22)
183	#define HM_CHANGED_VMX_ENTRY_CTLS RT_BIT(23)
184	#define HM_CHANGED_VMX_EXIT_CTLS RT_BIT(24)
185	/* AMD-V specific state. */
186	#define HM_CHANGED_SVM_RESERVED1 RT_BIT(21)
187	#define HM_CHANGED_SVM_RESERVED2 RT_BIT(22)
188	#define HM_CHANGED_SVM_RESERVED3 RT_BIT(23)
189	#define HM_CHANGED_SVM_RESERVED4 RT_BIT(24)
190
191	#define HM_CHANGED_ALL_GUEST ( HM_CHANGED_GUEST_CR0 \
192	\| HM_CHANGED_GUEST_CR3 \
193	\| HM_CHANGED_GUEST_CR4 \
194	\| HM_CHANGED_GUEST_GDTR \
195	\| HM_CHANGED_GUEST_IDTR \
196	\| HM_CHANGED_GUEST_LDTR \
197	\| HM_CHANGED_GUEST_TR \
198	\| HM_CHANGED_GUEST_SEGMENT_REGS \
199	\| HM_CHANGED_GUEST_DEBUG \
200	\| HM_CHANGED_GUEST_RIP \
201	\| HM_CHANGED_GUEST_RSP \
202	\| HM_CHANGED_GUEST_RFLAGS \
203	\| HM_CHANGED_GUEST_CR2 \
204	\| HM_CHANGED_GUEST_SYSENTER_CS_MSR \
205	\| HM_CHANGED_GUEST_SYSENTER_EIP_MSR \
206	\| HM_CHANGED_GUEST_SYSENTER_ESP_MSR \
207	\| HM_CHANGED_GUEST_EFER_MSR \
208	\| HM_CHANGED_GUEST_APIC_STATE \
209	\| HM_CHANGED_GUEST_HWVIRT \
210	\| HM_CHANGED_VMM_GUEST_XCPT_INTERCEPTS \
211	\| HM_CHANGED_VMM_GUEST_LAZY_MSRS \
212	\| HM_CHANGED_VMX_GUEST_AUTO_MSRS \
213	\| HM_CHANGED_VMX_GUEST_ACTIVITY_STATE \
214	\| HM_CHANGED_VMX_ENTRY_CTLS \
215	\| HM_CHANGED_VMX_EXIT_CTLS)
216
217	#define HM_CHANGED_HOST_CONTEXT RT_BIT(25)
218
219	/* Bits shared between host and guest. */
220	#define HM_CHANGED_HOST_GUEST_SHARED_STATE ( HM_CHANGED_GUEST_CR0 \
221	\| HM_CHANGED_GUEST_DEBUG \
222	\| HM_CHANGED_VMM_GUEST_LAZY_MSRS)
223	/** @} */
224
225	/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
226	#define HM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
227	/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
228	#define HM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2 * PAGE_SIZE + 1)
229	/** Total guest mapped memory needed. */
230	#define HM_VTX_TOTAL_DEVHEAP_MEM (HM_EPT_IDENTITY_PG_TABLE_SIZE + HM_VTX_TSS_SIZE)
231
232
233	/** @name Macros for enabling and disabling preemption.
234	* These are really just for hiding the RTTHREADPREEMPTSTATE and asserting that
235	* preemption has already been disabled when there is no context hook.
236	* @{ */
237	#ifdef VBOX_STRICT
238	# define HM_DISABLE_PREEMPT() \
239	RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
240	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD) \|\| VMMR0ThreadCtxHookIsEnabled(pVCpu)); \
241	RTThreadPreemptDisable(&PreemptStateInternal)
242	#else
243	# define HM_DISABLE_PREEMPT() \
244	RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
245	RTThreadPreemptDisable(&PreemptStateInternal)
246	#endif /* VBOX_STRICT */
247	#define HM_RESTORE_PREEMPT() do { RTThreadPreemptRestore(&PreemptStateInternal); } while(0)
248	/** @} */
249
250
251	/** Enable for TPR guest patching. */
252	#define VBOX_HM_WITH_GUEST_PATCHING
253
254	/** @name HM saved state versions
255	* @{
256	*/
257	#ifdef VBOX_HM_WITH_GUEST_PATCHING
258	# define HM_SAVED_STATE_VERSION 5
259	# define HM_SAVED_STATE_VERSION_NO_PATCHING 4
260	#else
261	# define HM_SAVED_STATE_VERSION 4
262	# define HM_SAVED_STATE_VERSION_NO_PATCHING 4
263	#endif
264	#define HM_SAVED_STATE_VERSION_2_0_X 3
265	/** @} */
266
267	/**
268	* Global per-cpu information. (host)
269	*/
270	typedef struct HMGLOBALCPUINFO
271	{
272	/** The CPU ID. */
273	RTCPUID idCpu;
274	/** The VM_HSAVE_AREA (AMD-V) / VMXON region (Intel) memory backing. */
275	RTR0MEMOBJ hMemObj;
276	/** The physical address of the first page in hMemObj (it's a
277	* physcially contigous allocation if it spans multiple pages). */
278	RTHCPHYS HCPhysMemObj;
279	/** The address of the memory (for pfnEnable). */
280	void *pvMemObj;
281	/** Current ASID (AMD-V) / VPID (Intel). */
282	uint32_t uCurrentAsid;
283	/** TLB flush count. */
284	uint32_t cTlbFlushes;
285	/** Whether to flush each new ASID/VPID before use. */
286	bool fFlushAsidBeforeUse;
287	/** Configured for VT-x or AMD-V. */
288	bool fConfigured;
289	/** Set if the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active. */
290	bool fIgnoreAMDVInUseError;
291	/** In use by our code. (for power suspend) */
292	volatile bool fInUse;
293	#ifdef VBOX_WITH_NESTED_HWVIRT
294	/** Nested-guest union (put data common to SVM/VMX outside the union). */
295	union
296	{
297	/** Nested-guest SVM data. */
298	struct
299	{
300	/** The active nested-guest MSR permission bitmap memory backing. */
301	RTR0MEMOBJ hNstGstMsrpm;
302	/** The physical address of the first page in hNstGstMsrpm (physcially
303	* contigous allocation). */
304	RTHCPHYS HCPhysNstGstMsrpm;
305	/** The address of the active nested-guest MSRPM. */
306	void *pvNstGstMsrpm;
307	} svm;
308	/** @todo Nested-VMX. */
309	} n;
310	#endif
311	} HMGLOBALCPUINFO;
312	/** Pointer to the per-cpu global information. */
313	typedef HMGLOBALCPUINFO *PHMGLOBALCPUINFO;
314
315	typedef enum
316	{
317	HMPENDINGIO_INVALID = 0,
318	HMPENDINGIO_PORT_READ,
319	/* not implemented: HMPENDINGIO_STRING_READ, */
320	/* not implemented: HMPENDINGIO_STRING_WRITE, */
321	/** The usual 32-bit paranoia. */
322	HMPENDINGIO_32BIT_HACK = 0x7fffffff
323	} HMPENDINGIO;
324
325
326	typedef enum
327	{
328	HMTPRINSTR_INVALID,
329	HMTPRINSTR_READ,
330	HMTPRINSTR_READ_SHR4,
331	HMTPRINSTR_WRITE_REG,
332	HMTPRINSTR_WRITE_IMM,
333	HMTPRINSTR_JUMP_REPLACEMENT,
334	/** The usual 32-bit paranoia. */
335	HMTPRINSTR_32BIT_HACK = 0x7fffffff
336	} HMTPRINSTR;
337
338	typedef struct
339	{
340	/** The key is the address of patched instruction. (32 bits GC ptr) */
341	AVLOU32NODECORE Core;
342	/** Original opcode. */
343	uint8_t aOpcode[16];
344	/** Instruction size. */
345	uint32_t cbOp;
346	/** Replacement opcode. */
347	uint8_t aNewOpcode[16];
348	/** Replacement instruction size. */
349	uint32_t cbNewOp;
350	/** Instruction type. */
351	HMTPRINSTR enmType;
352	/** Source operand. */
353	uint32_t uSrcOperand;
354	/** Destination operand. */
355	uint32_t uDstOperand;
356	/** Number of times the instruction caused a fault. */
357	uint32_t cFaults;
358	/** Patch address of the jump replacement. */
359	RTGCPTR32 pJumpTarget;
360	} HMTPRPATCH;
361	/** Pointer to HMTPRPATCH. */
362	typedef HMTPRPATCH *PHMTPRPATCH;
363
364
365	/**
366	* Makes a HMEXITSTAT::uKey value from a program counter and an exit code.
367	*
368	* @returns 64-bit key
369	* @param a_uPC The RIP + CS.BASE value of the exit.
370	* @param a_uExit The exit code.
371	* @todo Add CPL?
372	*/
373	#define HMEXITSTAT_MAKE_KEY(a_uPC, a_uExit) (((a_uPC) & UINT64_C(0x0000ffffffffffff)) \| (uint64_t)(a_uExit) << 48)
374
375	typedef struct HMEXITINFO
376	{
377	/** See HMEXITSTAT_MAKE_KEY(). */
378	uint64_t uKey;
379	/** Number of recent hits (depreciates with time). */
380	uint32_t volatile cHits;
381	/** The age + lock. */
382	uint16_t volatile uAge;
383	/** Action or action table index. */
384	uint16_t iAction;
385	} HMEXITINFO;
386	AssertCompileSize(HMEXITINFO, 16); /* Lots of these guys, so don't add any unnecessary stuff! */
387
388	typedef struct HMEXITHISTORY
389	{
390	/** The exit timestamp. */
391	uint64_t uTscExit;
392	/** The index of the corresponding HMEXITINFO entry.
393	* UINT32_MAX if none (too many collisions, race, whatever). */
394	uint32_t iExitInfo;
395	/** Figure out later, needed for padding now. */
396	uint32_t uSomeClueOrSomething;
397	} HMEXITHISTORY;
398
399	/**
400	* Switcher function, HC to the special 64-bit RC.
401	*
402	* @param pVM The cross context VM structure.
403	* @param offCpumVCpu Offset from pVM->cpum to pVM->aCpus[idCpu].cpum.
404	* @returns Return code indicating the action to take.
405	*/
406	typedef DECLCALLBACK(int) FNHMSWITCHERHC(PVM pVM, uint32_t offCpumVCpu);
407	/** Pointer to switcher function. */
408	typedef FNHMSWITCHERHC *PFNHMSWITCHERHC;
409
410	/**
411	* HM VM Instance data.
412	* Changes to this must checked against the padding of the hm union in VM!
413	*/
414	typedef struct HM
415	{
416	/** Set when we've initialized VMX or SVM. */
417	bool fInitialized;
418	/** Set if nested paging is enabled. */
419	bool fNestedPaging;
420	/** Set if nested paging is allowed. */
421	bool fAllowNestedPaging;
422	/** Set if large pages are enabled (requires nested paging). */
423	bool fLargePages;
424	/** Set if we can support 64-bit guests or not. */
425	bool fAllow64BitGuests;
426	/** Set when TPR patching is allowed. */
427	bool fTprPatchingAllowed;
428	/** Set when we initialize VT-x or AMD-V once for all CPUs. */
429	bool fGlobalInit;
430	/** Set when TPR patching is active. */
431	bool fTPRPatchingActive;
432	/** Set when the debug facility has breakpoints/events enabled that requires
433	* us to use the debug execution loop in ring-0. */
434	bool fUseDebugLoop;
435	/** Set if hardware APIC virtualization is enabled. */
436	bool fVirtApicRegs;
437	/** Set if posted interrupt processing is enabled. */
438	bool fPostedIntrs;
439	/** Set if indirect branch prediction barrier on VM exit. */
440	bool fIbpbOnVmExit;
441	/** Set if indirect branch prediction barrier on VM entry. */
442	bool fIbpbOnVmEntry;
443	/** Set if host manages speculation control settings. */
444	bool fSpecCtrlByHost;
445	/** Explicit padding. */
446	bool afPadding[2];
447
448	/** Maximum ASID allowed. */
449	uint32_t uMaxAsid;
450	/** The maximum number of resumes loops allowed in ring-0 (safety precaution).
451	* This number is set much higher when RTThreadPreemptIsPending is reliable. */
452	uint32_t cMaxResumeLoops;
453
454	/** Host kernel flags that HM might need to know (SUPKERNELFEATURES_XXX). */
455	uint32_t fHostKernelFeatures;
456
457	/** Size of the guest patch memory block. */
458	uint32_t cbGuestPatchMem;
459	/** Guest allocated memory for patching purposes. */
460	RTGCPTR pGuestPatchMem;
461	/** Current free pointer inside the patch block. */
462	RTGCPTR pFreeGuestPatchMem;
463
464	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
465	/** 32 to 64 bits switcher entrypoint. */
466	R0PTRTYPE(PFNHMSWITCHERHC) pfnHost32ToGuest64R0;
467	RTR0PTR pvR0Alignment0;
468	#endif
469
470	struct
471	{
472	/** Set by the ring-0 side of HM to indicate VMX is supported by the
473	* CPU. */
474	bool fSupported;
475	/** Set when we've enabled VMX. */
476	bool fEnabled;
477	/** Set if VPID is supported. */
478	bool fVpid;
479	/** Set if VT-x VPID is allowed. */
480	bool fAllowVpid;
481	/** Set if unrestricted guest execution is in use (real and protected mode without paging). */
482	bool fUnrestrictedGuest;
483	/** Set if unrestricted guest execution is allowed to be used. */
484	bool fAllowUnrestricted;
485	/** Whether we're using the preemption timer or not. */
486	bool fUsePreemptTimer;
487	/** The shift mask employed by the VMX-Preemption timer. */
488	uint8_t cPreemptTimerShift;
489
490	/** Virtual address of the TSS page used for real mode emulation. */
491	R3PTRTYPE(PVBOXTSS) pRealModeTSS;
492	/** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
493	R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
494
495	/** Physical address of the APIC-access page. */
496	RTHCPHYS HCPhysApicAccess;
497	/** R0 memory object for the APIC-access page. */
498	RTR0MEMOBJ hMemObjApicAccess;
499	/** Virtual address of the APIC-access page. */
500	R0PTRTYPE(uint8_t *) pbApicAccess;
501
502	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
503	RTHCPHYS HCPhysScratch;
504	RTR0MEMOBJ hMemObjScratch;
505	R0PTRTYPE(uint8_t *) pbScratch;
506	#endif
507
508	/** Internal Id of which flush-handler to use for tagged-TLB entries. */
509	uint32_t uFlushTaggedTlb;
510
511	/** Pause-loop exiting (PLE) gap in ticks. */
512	uint32_t cPleGapTicks;
513	/** Pause-loop exiting (PLE) window in ticks. */
514	uint32_t cPleWindowTicks;
515	uint32_t u32Alignment0;
516
517	/** Host CR4 value (set by ring-0 VMX init) */
518	uint64_t u64HostCr4;
519	/** Host SMM monitor control (set by ring-0 VMX init) */
520	uint64_t u64HostSmmMonitorCtl;
521	/** Host EFER value (set by ring-0 VMX init) */
522	uint64_t u64HostEfer;
523	/** Whether the CPU supports VMCS fields for swapping EFER. */
524	bool fSupportsVmcsEfer;
525	uint8_t u8Alignment2[7];
526
527	/** VMX MSR values. */
528	VMXMSRS Msrs;
529
530	/** Flush types for invept & invvpid; they depend on capabilities. */
531	VMXFLUSHEPT enmFlushEpt;
532	VMXFLUSHVPID enmFlushVpid;
533
534	/** Host-physical address for a failing VMXON instruction. */
535	RTHCPHYS HCPhysVmxEnableError;
536	} vmx;
537
538	struct
539	{
540	/** Set by the ring-0 side of HM to indicate SVM is supported by the
541	* CPU. */
542	bool fSupported;
543	/** Set when we've enabled SVM. */
544	bool fEnabled;
545	/** Set if erratum 170 affects the AMD cpu. */
546	bool fAlwaysFlushTLB;
547	/** Set when the hack to ignore VERR_SVM_IN_USE is active. */
548	bool fIgnoreInUseError;
549	/** Whether to use virtualized VMSAVE/VMLOAD feature. */
550	bool fVirtVmsaveVmload;
551	/** Whether to use virtual GIF feature. */
552	bool fVGif;
553	uint8_t u8Alignment0[2];
554
555	/** Physical address of the IO bitmap (12kb). */
556	RTHCPHYS HCPhysIOBitmap;
557	/** R0 memory object for the IO bitmap (12kb). */
558	RTR0MEMOBJ hMemObjIOBitmap;
559	/** Virtual address of the IO bitmap. */
560	R0PTRTYPE(void *) pvIOBitmap;
561
562	/* HWCR MSR (for diagnostics) */
563	uint64_t u64MsrHwcr;
564
565	/** SVM revision. */
566	uint32_t u32Rev;
567	/** SVM feature bits from cpuid 0x8000000a */
568	uint32_t u32Features;
569
570	/** Pause filter counter. */
571	uint16_t cPauseFilter;
572	/** Pause filter treshold in ticks. */
573	uint16_t cPauseFilterThresholdTicks;
574	uint32_t u32Alignment0;
575	} svm;
576
577	/**
578	* AVL tree with all patches (active or disabled) sorted by guest instruction
579	* address.
580	*/
581	AVLOU32TREE PatchTree;
582	uint32_t cPatches;
583	HMTPRPATCH aPatches[64];
584
585	struct
586	{
587	uint32_t u32AMDFeatureECX;
588	uint32_t u32AMDFeatureEDX;
589	} cpuid;
590
591	/** Saved error from detection */
592	int32_t lLastError;
593
594	/** HMR0Init was run */
595	bool fHMR0Init;
596	bool u8Alignment1[3];
597
598	STAMCOUNTER StatTprPatchSuccess;
599	STAMCOUNTER StatTprPatchFailure;
600	STAMCOUNTER StatTprReplaceSuccessCr8;
601	STAMCOUNTER StatTprReplaceSuccessVmc;
602	STAMCOUNTER StatTprReplaceFailure;
603	} HM;
604	/** Pointer to HM VM instance data. */
605	typedef HM *PHM;
606
607	AssertCompileMemberAlignment(HM, StatTprPatchSuccess, 8);
608
609	/* Maximum number of cached entries. */
610	#define VMCSCACHE_MAX_ENTRY 128
611
612	/**
613	* Structure for storing read and write VMCS actions.
614	*/
615	typedef struct VMCSCACHE
616	{
617	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
618	/* Magic marker for searching in crash dumps. */
619	uint8_t aMagic[16];
620	uint64_t uMagic;
621	uint64_t u64TimeEntry;
622	uint64_t u64TimeSwitch;
623	uint64_t cResume;
624	uint64_t interPD;
625	uint64_t pSwitcher;
626	uint32_t uPos;
627	uint32_t idCpu;
628	#endif
629	/* CR2 is saved here for EPT syncing. */
630	uint64_t cr2;
631	struct
632	{
633	uint32_t cValidEntries;
634	uint32_t uAlignment;
635	uint32_t aField[VMCSCACHE_MAX_ENTRY];
636	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
637	} Write;
638	struct
639	{
640	uint32_t cValidEntries;
641	uint32_t uAlignment;
642	uint32_t aField[VMCSCACHE_MAX_ENTRY];
643	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
644	} Read;
645	#ifdef VBOX_STRICT
646	struct
647	{
648	RTHCPHYS HCPhysCpuPage;
649	RTHCPHYS HCPhysVmcs;
650	RTGCPTR pCache;
651	RTGCPTR pCtx;
652	} TestIn;
653	struct
654	{
655	RTHCPHYS HCPhysVmcs;
656	RTGCPTR pCache;
657	RTGCPTR pCtx;
658	uint64_t eflags;
659	uint64_t cr8;
660	} TestOut;
661	struct
662	{
663	uint64_t param1;
664	uint64_t param2;
665	uint64_t param3;
666	uint64_t param4;
667	} ScratchPad;
668	#endif
669	} VMCSCACHE;
670	/** Pointer to VMCSCACHE. */
671	typedef VMCSCACHE *PVMCSCACHE;
672	AssertCompileSizeAlignment(VMCSCACHE, 8);
673
674	/**
675	* VMX StartVM function.
676	*
677	* @returns VBox status code (no informational stuff).
678	* @param fResume Whether to use VMRESUME (true) or VMLAUNCH (false).
679	* @param pCtx The CPU register context.
680	* @param pCache The VMCS cache.
681	* @param pVM Pointer to the cross context VM structure.
682	* @param pVCpu Pointer to the cross context per-CPU structure.
683	*/
684	typedef DECLCALLBACK(int) FNHMVMXSTARTVM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);
685	/** Pointer to a VMX StartVM function. */
686	typedef R0PTRTYPE(FNHMVMXSTARTVM *) PFNHMVMXSTARTVM;
687
688	/** SVM VMRun function. */
689	typedef DECLCALLBACK(int) FNHMSVMVMRUN(RTHCPHYS pVmcbHostPhys, RTHCPHYS pVmcbPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu);
690	/** Pointer to a SVM VMRun function. */
691	typedef R0PTRTYPE(FNHMSVMVMRUN *) PFNHMSVMVMRUN;
692
693	/**
694	* HM VMCPU Instance data.
695	*
696	* Note! If you change members of this struct, make sure to check if the
697	* assembly counterpart in HMInternal.mac needs to be updated as well.
698	*/
699	typedef struct HMCPU
700	{
701	/** Set if we need to flush the TLB during the world switch. */
702	bool fForceTLBFlush;
703	/** Set when we're using VT-x or AMD-V at that moment. */
704	bool fActive;
705	/** Set when the TLB has been checked until we return from the world switch. */
706	volatile bool fCheckedTLBFlush;
707	/** Whether we've completed the inner HM leave function. */
708	bool fLeaveDone;
709	/** Whether we're using the hyper DR7 or guest DR7. */
710	bool fUsingHyperDR7;
711	/** Whether to preload the guest-FPU state to avoid \#NM VM-exit overhead. */
712	bool fPreloadGuestFpu;
713	/** Set if XCR0 needs to be loaded and saved when entering and exiting guest
714	* code execution. */
715	bool fLoadSaveGuestXcr0;
716
717	/** Whether we should use the debug loop because of single stepping or special
718	* debug breakpoints / events are armed. */
719	bool fUseDebugLoop;
720	/** Whether we are currently executing in the debug loop.
721	* Mainly for assertions. */
722	bool fUsingDebugLoop;
723	/** Set if we using the debug loop and wish to intercept RDTSC. */
724	bool fDebugWantRdTscExit;
725	/** Whether we're executing a single instruction. */
726	bool fSingleInstruction;
727	/** Set if we need to clear the trap flag because of single stepping. */
728	bool fClearTrapFlag;
729
730	/** Whether \#UD needs to be intercepted (required by certain GIM providers). */
731	bool fGIMTrapXcptUD;
732	/** Whether paravirt. hypercalls are enabled. */
733	bool fHypercallsEnabled;
734	uint8_t u8Alignment0[2];
735
736	/** World switch exit counter. */
737	volatile uint32_t cWorldSwitchExits;
738	/** HM_CHANGED_* flags. */
739	volatile uint32_t fContextUseFlags;
740	/** Id of the last cpu we were executing code on (NIL_RTCPUID for the first
741	* time). */
742	RTCPUID idLastCpu;
743	/** TLB flush count. */
744	uint32_t cTlbFlushes;
745	/** Current ASID in use by the VM. */
746	uint32_t uCurrentAsid;
747	/** An additional error code used for some gurus. */
748	uint32_t u32HMError;
749	/** Host's TSC_AUX MSR (used when RDTSCP doesn't cause VM-exits). */
750	uint64_t u64HostTscAux;
751
752	struct
753	{
754	/** Ring 0 handlers for VT-x. */
755	PFNHMVMXSTARTVM pfnStartVM;
756	#if HC_ARCH_BITS == 32
757	uint32_t u32Alignment0;
758	#endif
759	/** Current VMX_VMCS32_CTRL_PIN_EXEC. */
760	uint32_t u32PinCtls;
761	/** Current VMX_VMCS32_CTRL_PROC_EXEC. */
762	uint32_t u32ProcCtls;
763	/** Current VMX_VMCS32_CTRL_PROC_EXEC2. */
764	uint32_t u32ProcCtls2;
765	/** Current VMX_VMCS32_CTRL_EXIT. */
766	uint32_t u32ExitCtls;
767	/** Current VMX_VMCS32_CTRL_ENTRY. */
768	uint32_t u32EntryCtls;
769
770	/** Current CR0 mask. */
771	uint32_t u32CR0Mask;
772	/** Current CR4 mask. */
773	uint32_t u32CR4Mask;
774	/** Current exception bitmap. */
775	uint32_t u32XcptBitmap;
776	/** The updated-guest-state mask. */
777	volatile uint32_t fUpdatedGuestState;
778	uint32_t u32Alignment1;
779
780	/** Physical address of the VM control structure (VMCS). */
781	RTHCPHYS HCPhysVmcs;
782	/** R0 memory object for the VM control structure (VMCS). */
783	RTR0MEMOBJ hMemObjVmcs;
784	/** Virtual address of the VM control structure (VMCS). */
785	R0PTRTYPE(void *) pvVmcs;
786
787	/** Physical address of the virtual APIC page for TPR caching. */
788	RTHCPHYS HCPhysVirtApic;
789	/** Padding. */
790	R0PTRTYPE(void *) pvAlignment0;
791	/** Virtual address of the virtual APIC page for TPR caching. */
792	R0PTRTYPE(uint8_t *) pbVirtApic;
793
794	/** Physical address of the MSR bitmap. */
795	RTHCPHYS HCPhysMsrBitmap;
796	/** R0 memory object for the MSR bitmap. */
797	RTR0MEMOBJ hMemObjMsrBitmap;
798	/** Virtual address of the MSR bitmap. */
799	R0PTRTYPE(void *) pvMsrBitmap;
800
801	/** Physical address of the VM-entry MSR-load and VM-exit MSR-store area (used
802	* for guest MSRs). */
803	RTHCPHYS HCPhysGuestMsr;
804	/** R0 memory object of the VM-entry MSR-load and VM-exit MSR-store area
805	* (used for guest MSRs). */
806	RTR0MEMOBJ hMemObjGuestMsr;
807	/** Virtual address of the VM-entry MSR-load and VM-exit MSR-store area (used
808	* for guest MSRs). */
809	R0PTRTYPE(void *) pvGuestMsr;
810
811	/** Physical address of the VM-exit MSR-load area (used for host MSRs). */
812	RTHCPHYS HCPhysHostMsr;
813	/** R0 memory object for the VM-exit MSR-load area (used for host MSRs). */
814	RTR0MEMOBJ hMemObjHostMsr;
815	/** Virtual address of the VM-exit MSR-load area (used for host MSRs). */
816	R0PTRTYPE(void *) pvHostMsr;
817
818	/** Current EPTP. */
819	RTHCPHYS HCPhysEPTP;
820
821	/** Number of guest/host MSR pairs in the auto-load/store area. */
822	uint32_t cMsrs;
823	/** Whether the host MSR values are up-to-date in the auto-load/store area. */
824	bool fUpdatedHostMsrs;
825	uint8_t u8Alignment0[3];
826
827	/** Host LSTAR MSR value to restore lazily while leaving VT-x. */
828	uint64_t u64HostLStarMsr;
829	/** Host STAR MSR value to restore lazily while leaving VT-x. */
830	uint64_t u64HostStarMsr;
831	/** Host SF_MASK MSR value to restore lazily while leaving VT-x. */
832	uint64_t u64HostSFMaskMsr;
833	/** Host KernelGS-Base MSR value to restore lazily while leaving VT-x. */
834	uint64_t u64HostKernelGSBaseMsr;
835	/** A mask of which MSRs have been swapped and need restoration. */
836	uint32_t fLazyMsrs;
837	uint32_t u32Alignment2;
838
839	/** The cached APIC-base MSR used for identifying when to map the HC physical APIC-access page. */
840	uint64_t u64MsrApicBase;
841	/** Last use TSC offset value. (cached) */
842	uint64_t u64TSCOffset;
843
844	/** VMCS cache. */
845	VMCSCACHE VMCSCache;
846
847	/** Real-mode emulation state. */
848	struct
849	{
850	X86DESCATTR AttrCS;
851	X86DESCATTR AttrDS;
852	X86DESCATTR AttrES;
853	X86DESCATTR AttrFS;
854	X86DESCATTR AttrGS;
855	X86DESCATTR AttrSS;
856	X86EFLAGS Eflags;
857	uint32_t fRealOnV86Active;
858	} RealMode;
859
860	/** VT-x error-reporting (mainly for ring-3 propagation). */
861	struct
862	{
863	uint64_t u64VMCSPhys;
864	uint32_t u32VMCSRevision;
865	uint32_t u32InstrError;
866	uint32_t u32ExitReason;
867	RTCPUID idEnteredCpu;
868	RTCPUID idCurrentCpu;
869	uint32_t u32Alignment0;
870	} LastError;
871
872	/** Current state of the VMCS. */
873	uint32_t uVmcsState;
874	/** Which host-state bits to restore before being preempted. */
875	uint32_t fRestoreHostFlags;
876	/** The host-state restoration structure. */
877	VMXRESTOREHOST RestoreHost;
878
879	/** Set if guest was executing in real mode (extra checks). */
880	bool fWasInRealMode;
881	/** Set if guest switched to 64-bit mode on a 32-bit host. */
882	bool fSwitchedTo64on32;
883
884	uint8_t u8Alignment1[6];
885	} vmx;
886
887	struct
888	{
889	/** Ring 0 handlers for VT-x. */
890	PFNHMSVMVMRUN pfnVMRun;
891	#if HC_ARCH_BITS == 32
892	uint32_t u32Alignment0;
893	#endif
894
895	/** Physical address of the host VMCB which holds additional host-state. */
896	RTHCPHYS HCPhysVmcbHost;
897	/** R0 memory object for the host VMCB which holds additional host-state. */
898	RTR0MEMOBJ hMemObjVmcbHost;
899	/** Padding. */
900	R0PTRTYPE(void *) pvPadding;
901
902	/** Physical address of the guest VMCB. */
903	RTHCPHYS HCPhysVmcb;
904	/** R0 memory object for the guest VMCB. */
905	RTR0MEMOBJ hMemObjVmcb;
906	/** Pointer to the guest VMCB. */
907	R0PTRTYPE(PSVMVMCB) pVmcb;
908
909	/** Physical address of the MSR bitmap (8 KB). */
910	RTHCPHYS HCPhysMsrBitmap;
911	/** R0 memory object for the MSR bitmap (8 KB). */
912	RTR0MEMOBJ hMemObjMsrBitmap;
913	/** Pointer to the MSR bitmap. */
914	R0PTRTYPE(void *) pvMsrBitmap;
915
916	/** Whether VTPR with V_INTR_MASKING set is in effect, indicating
917	* we should check if the VTPR changed on every VM-exit. */
918	bool fSyncVTpr;
919	uint8_t u8Alignment0[7];
920
921	/** Cache of the nested-guest's VMCB fields that we modify in order to run the
922	* nested-guest using AMD-V. This will be restored on \#VMEXIT. */
923	SVMNESTEDVMCBCACHE NstGstVmcbCache;
924	} svm;
925
926	/** Event injection state. */
927	struct
928	{
929	uint32_t fPending;
930	uint32_t u32ErrCode;
931	uint32_t cbInstr;
932	uint32_t u32Padding; /*< Explicit alignment padding. /
933	uint64_t u64IntInfo;
934	RTGCUINTPTR GCPtrFaultAddress;
935	} Event;
936
937	/** IO Block emulation state. */
938	struct
939	{
940	bool fEnabled;
941	uint8_t u8Align[7];
942
943	/** RIP at the start of the io code we wish to emulate in the recompiler. */
944	RTGCPTR GCPtrFunctionEip;
945
946	uint64_t cr0;
947	} EmulateIoBlock;
948
949	/* */
950	struct
951	{
952	/** Pending IO operation type. */
953	HMPENDINGIO enmType;
954	uint32_t u32Alignment0;
955	RTGCPTR GCPtrRip;
956	RTGCPTR GCPtrRipNext;
957	union
958	{
959	struct
960	{
961	uint32_t uPort;
962	uint32_t uAndVal;
963	uint32_t cbSize;
964	} Port;
965	uint64_t aRaw[2];
966	} s;
967	} PendingIO;
968
969	/** The PAE PDPEs used with Nested Paging (only valid when
970	* VMCPU_FF_HM_UPDATE_PAE_PDPES is set). */
971	X86PDPE aPdpes[4];
972
973	/** Current shadow paging mode. */
974	PGMMODE enmShadowMode;
975
976	/** The CPU ID of the CPU currently owning the VMCS. Set in
977	* HMR0Enter and cleared in HMR0Leave. */
978	RTCPUID idEnteredCpu;
979
980	/** VT-x/AMD-V VM-exit/\#VMXEXIT history, circular array. */
981	uint16_t auExitHistory[31];
982	/** The index of the next free slot in the history array. */
983	uint16_t idxExitHistoryFree;
984
985	/** For saving stack space, the disassembler state is allocated here instead of
986	* on the stack. */
987	DISCPUSTATE DisState;
988
989	STAMPROFILEADV StatEntry;
990	STAMPROFILEADV StatExit1;
991	STAMPROFILEADV StatExit2;
992	STAMPROFILEADV StatExitIO;
993	STAMPROFILEADV StatExitMovCRx;
994	STAMPROFILEADV StatExitXcptNmi;
995	STAMPROFILEADV StatLoadGuestState;
996	STAMPROFILEADV StatLoadGuestFpuState;
997	STAMPROFILEADV StatInGC;
998
999	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1000	STAMPROFILEADV StatWorldSwitch3264;
1001	#endif
1002	STAMPROFILEADV StatPoke;
1003	STAMPROFILEADV StatSpinPoke;
1004	STAMPROFILEADV StatSpinPokeFailed;
1005
1006	STAMCOUNTER StatInjectInterrupt;
1007	STAMCOUNTER StatInjectXcpt;
1008	STAMCOUNTER StatInjectPendingReflect;
1009	STAMCOUNTER StatInjectPendingInterpret;
1010
1011	STAMCOUNTER StatExitAll;
1012	STAMCOUNTER StatExitShadowNM;
1013	STAMCOUNTER StatExitGuestNM;
1014	STAMCOUNTER StatExitShadowPF; /*< Misleading, currently used for MMIO \#PFs as well. /
1015	STAMCOUNTER StatExitShadowPFEM;
1016	STAMCOUNTER StatExitGuestPF;
1017	STAMCOUNTER StatExitGuestUD;
1018	STAMCOUNTER StatExitGuestSS;
1019	STAMCOUNTER StatExitGuestNP;
1020	STAMCOUNTER StatExitGuestTS;
1021	STAMCOUNTER StatExitGuestGP;
1022	STAMCOUNTER StatExitGuestDE;
1023	STAMCOUNTER StatExitGuestDB;
1024	STAMCOUNTER StatExitGuestMF;
1025	STAMCOUNTER StatExitGuestBP;
1026	STAMCOUNTER StatExitGuestXF;
1027	STAMCOUNTER StatExitGuestXcpUnk;
1028	STAMCOUNTER StatExitInvlpg;
1029	STAMCOUNTER StatExitInvd;
1030	STAMCOUNTER StatExitWbinvd;
1031	STAMCOUNTER StatExitPause;
1032	STAMCOUNTER StatExitCpuid;
1033	STAMCOUNTER StatExitRdtsc;
1034	STAMCOUNTER StatExitRdtscp;
1035	STAMCOUNTER StatExitRdpmc;
1036	STAMCOUNTER StatExitVmcall;
1037	STAMCOUNTER StatExitRdrand;
1038	STAMCOUNTER StatExitCli;
1039	STAMCOUNTER StatExitSti;
1040	STAMCOUNTER StatExitPushf;
1041	STAMCOUNTER StatExitPopf;
1042	STAMCOUNTER StatExitIret;
1043	STAMCOUNTER StatExitInt;
1044	STAMCOUNTER StatExitCRxWrite[16];
1045	STAMCOUNTER StatExitCRxRead[16];
1046	STAMCOUNTER StatExitDRxWrite;
1047	STAMCOUNTER StatExitDRxRead;
1048	STAMCOUNTER StatExitRdmsr;
1049	STAMCOUNTER StatExitWrmsr;
1050	STAMCOUNTER StatExitClts;
1051	STAMCOUNTER StatExitXdtrAccess;
1052	STAMCOUNTER StatExitHlt;
1053	STAMCOUNTER StatExitMwait;
1054	STAMCOUNTER StatExitMonitor;
1055	STAMCOUNTER StatExitLmsw;
1056	STAMCOUNTER StatExitIOWrite;
1057	STAMCOUNTER StatExitIORead;
1058	STAMCOUNTER StatExitIOStringWrite;
1059	STAMCOUNTER StatExitIOStringRead;
1060	STAMCOUNTER StatExitIntWindow;
1061	STAMCOUNTER StatExitExtInt;
1062	STAMCOUNTER StatExitHostNmiInGC;
1063	STAMCOUNTER StatExitPreemptTimer;
1064	STAMCOUNTER StatExitTprBelowThreshold;
1065	STAMCOUNTER StatExitTaskSwitch;
1066	STAMCOUNTER StatExitMtf;
1067	STAMCOUNTER StatExitApicAccess;
1068	STAMCOUNTER StatPendingHostIrq;
1069
1070	STAMCOUNTER StatFlushPage;
1071	STAMCOUNTER StatFlushPageManual;
1072	STAMCOUNTER StatFlushPhysPageManual;
1073	STAMCOUNTER StatFlushTlb;
1074	STAMCOUNTER StatFlushTlbManual;
1075	STAMCOUNTER StatFlushTlbWorldSwitch;
1076	STAMCOUNTER StatNoFlushTlbWorldSwitch;
1077	STAMCOUNTER StatFlushEntire;
1078	STAMCOUNTER StatFlushAsid;
1079	STAMCOUNTER StatFlushNestedPaging;
1080	STAMCOUNTER StatFlushTlbInvlpgVirt;
1081	STAMCOUNTER StatFlushTlbInvlpgPhys;
1082	STAMCOUNTER StatTlbShootdown;
1083	STAMCOUNTER StatTlbShootdownFlush;
1084
1085	STAMCOUNTER StatSwitchTprMaskedIrq;
1086	STAMCOUNTER StatSwitchGuestIrq;
1087	STAMCOUNTER StatSwitchHmToR3FF;
1088	STAMCOUNTER StatSwitchExitToR3;
1089	STAMCOUNTER StatSwitchLongJmpToR3;
1090	STAMCOUNTER StatSwitchMaxResumeLoops;
1091	STAMCOUNTER StatSwitchHltToR3;
1092	STAMCOUNTER StatSwitchApicAccessToR3;
1093	STAMCOUNTER StatSwitchPreempt;
1094	STAMCOUNTER StatSwitchPreemptSaveHostState;
1095
1096	STAMCOUNTER StatTscParavirt;
1097	STAMCOUNTER StatTscOffset;
1098	STAMCOUNTER StatTscIntercept;
1099
1100	STAMCOUNTER StatExitReasonNpf;
1101	STAMCOUNTER StatDRxArmed;
1102	STAMCOUNTER StatDRxContextSwitch;
1103	STAMCOUNTER StatDRxIoCheck;
1104
1105	STAMCOUNTER StatLoadMinimal;
1106	STAMCOUNTER StatLoadFull;
1107	STAMCOUNTER StatLoadGuestFpu;
1108
1109	STAMCOUNTER StatVmxCheckBadRmSelBase;
1110	STAMCOUNTER StatVmxCheckBadRmSelLimit;
1111	STAMCOUNTER StatVmxCheckRmOk;
1112
1113	STAMCOUNTER StatVmxCheckBadSel;
1114	STAMCOUNTER StatVmxCheckBadRpl;
1115	STAMCOUNTER StatVmxCheckBadLdt;
1116	STAMCOUNTER StatVmxCheckBadTr;
1117	STAMCOUNTER StatVmxCheckPmOk;
1118
1119	STAMCOUNTER StatNestedExitReasonNpf;
1120
1121	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1122	STAMCOUNTER StatFpu64SwitchBack;
1123	STAMCOUNTER StatDebug64SwitchBack;
1124	#endif
1125
1126	#ifdef VBOX_WITH_STATISTICS
1127	R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
1128	R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
1129	R3PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqs;
1130	R0PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqsR0;
1131	R3PTRTYPE(PSTAMCOUNTER) paStatNestedExitReason;
1132	R0PTRTYPE(PSTAMCOUNTER) paStatNestedExitReasonR0;
1133	#endif
1134	#ifdef HM_PROFILE_EXIT_DISPATCH
1135	STAMPROFILEADV StatExitDispatch;
1136	#endif
1137	} HMCPU;
1138	/** Pointer to HM VMCPU instance data. */
1139	typedef HMCPU *PHMCPU;
1140	AssertCompileMemberAlignment(HMCPU, vmx, 8);
1141	AssertCompileMemberAlignment(HMCPU, svm, 8);
1142	AssertCompileMemberAlignment(HMCPU, Event, 8);
1143
1144	#ifdef IN_RING0
1145	VMMR0_INT_DECL(PHMGLOBALCPUINFO) hmR0GetCurrentCpu(void);
1146
1147	# ifdef VBOX_STRICT
1148	VMMR0_INT_DECL(void) hmR0DumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
1149	VMMR0_INT_DECL(void) hmR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg);
1150	# else
1151	# define hmR0DumpRegs(a, b ,c) do { } while (0)
1152	# define hmR0DumpDescriptor(a, b, c) do { } while (0)
1153	# endif /* VBOX_STRICT */
1154
1155	# ifdef VBOX_WITH_KERNEL_USING_XMM
1156	DECLASM(int) hmR0VMXStartVMWrapXMM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu, PFNHMVMXSTARTVM pfnStartVM);
1157	DECLASM(int) hmR0SVMRunWrapXMM(RTHCPHYS pVmcbHostPhys, RTHCPHYS pVmcbPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu, PFNHMSVMVMRUN pfnVMRun);
1158	# endif
1159
1160	#endif /* IN_RING0 */
1161
1162	/** @} */
1163
1164	RT_C_DECLS_END
1165
1166	#endif
1167

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source: vbox/trunk/src/VBox/VMM/include/HMInternal.h@ 72079

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