HMInternal.h@ 72532

Last change on this file since 72532 was 72532, checked in by vboxsync, 6 years ago
VMM/HM: Remove unused variable.
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1	/* $Id: HMInternal.h 72532 2018-06-13 04:17:47Z vboxsync $ */
2	/** @file
3	* HM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef ___HMInternal_h
19	#define ___HMInternal_h
20
21	#include <VBox/cdefs.h>
22	#include <VBox/types.h>
23	#include <VBox/vmm/em.h>
24	#include <VBox/vmm/stam.h>
25	#include <VBox/dis.h>
26	#include <VBox/vmm/hm.h>
27	#include <VBox/vmm/hm_vmx.h>
28	#include <VBox/vmm/hm_svm.h>
29	#include <VBox/vmm/pgm.h>
30	#include <VBox/vmm/cpum.h>
31	#include <VBox/vmm/trpm.h>
32	#include <iprt/memobj.h>
33	#include <iprt/cpuset.h>
34	#include <iprt/mp.h>
35	#include <iprt/avl.h>
36	#include <iprt/string.h>
37
38	#if defined(RT_OS_DARWIN) && HC_ARCH_BITS == 32
39	# error "32-bit darwin is no longer supported. Go back to 4.3 or earlier!"
40	#endif
41
42	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_64_BITS_GUESTS)
43	/* Enable 64 bits guest support. */
44	# define VBOX_ENABLE_64_BITS_GUESTS
45	#endif
46
47	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
48	# define VMX_USE_CACHED_VMCS_ACCESSES
49	#endif
50
51	/** @def HM_PROFILE_EXIT_DISPATCH
52	* Enables profiling of the VM exit handler dispatching. */
53	#if 0 \|\| defined(DOXYGEN_RUNNING)
54	# define HM_PROFILE_EXIT_DISPATCH
55	#endif
56
57	RT_C_DECLS_BEGIN
58
59
60	/** @defgroup grp_hm_int Internal
61	* @ingroup grp_hm
62	* @internal
63	* @{
64	*/
65
66	/** @def HMCPU_CF_CLEAR
67	* Clears a HM-context flag.
68	*
69	* @param pVCpu The cross context virtual CPU structure.
70	* @param fFlag The flag to clear.
71	*/
72	#define HMCPU_CF_CLEAR(pVCpu, fFlag) (ASMAtomicUoAndU32(&(pVCpu)->hm.s.fContextUseFlags, ~(fFlag)))
73
74	/** @def HMCPU_CF_SET
75	* Sets a HM-context flag.
76	*
77	* @param pVCpu The cross context virtual CPU structure.
78	* @param fFlag The flag to set.
79	*/
80	#define HMCPU_CF_SET(pVCpu, fFlag) (ASMAtomicUoOrU32(&(pVCpu)->hm.s.fContextUseFlags, (fFlag)))
81
82	/** @def HMCPU_CF_IS_SET
83	* Checks if all the flags in the specified HM-context set is pending.
84	*
85	* @param pVCpu The cross context virtual CPU structure.
86	* @param fFlag The flag to check.
87	*/
88	#define HMCPU_CF_IS_SET(pVCpu, fFlag) ((ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags) & (fFlag)) == (fFlag))
89
90	/** @def HMCPU_CF_IS_PENDING
91	* Checks if one or more of the flags in the specified HM-context set is
92	* pending.
93	*
94	* @param pVCpu The cross context virtual CPU structure.
95	* @param fFlags The flags to check for.
96	*/
97	#define HMCPU_CF_IS_PENDING(pVCpu, fFlags) RT_BOOL(ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags) & (fFlags))
98
99	/** @def HMCPU_CF_IS_PENDING_ONLY
100	* Checks if -only- one or more of the specified HM-context flags is pending.
101	*
102	* @param pVCpu The cross context virtual CPU structure.
103	* @param fFlags The flags to check for.
104	*/
105	#define HMCPU_CF_IS_PENDING_ONLY(pVCpu, fFlags) !RT_BOOL(ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags) & ~(fFlags))
106
107	/** @def HMCPU_CF_IS_SET_ONLY
108	* Checks if -only- all the flags in the specified HM-context set is pending.
109	*
110	* @param pVCpu The cross context virtual CPU structure.
111	* @param fFlags The flags to check for.
112	*/
113	#define HMCPU_CF_IS_SET_ONLY(pVCpu, fFlags) (ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags) == (fFlags))
114
115	/** @def HMCPU_CF_RESET_TO
116	* Resets the HM-context flags to the specified value.
117	*
118	* @param pVCpu The cross context virtual CPU structure.
119	* @param fFlags The new value.
120	*/
121	#define HMCPU_CF_RESET_TO(pVCpu, fFlags) (ASMAtomicUoWriteU32(&(pVCpu)->hm.s.fContextUseFlags, (fFlags)))
122
123	/** @def HMCPU_CF_VALUE
124	* Returns the current HM-context flags value.
125	*
126	* @param pVCpu The cross context virtual CPU structure.
127	*/
128	#define HMCPU_CF_VALUE(pVCpu) (ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags))
129
130
131	/** Resets/initializes the VM-exit/\#VMEXIT history array. */
132	#define HMCPU_EXIT_HISTORY_RESET(pVCpu) (memset(&(pVCpu)->hm.s.auExitHistory, 0xff, sizeof((pVCpu)->hm.s.auExitHistory)))
133
134	/** Updates the VM-exit/\#VMEXIT history array. */
135	#define HMCPU_EXIT_HISTORY_ADD(pVCpu, a_ExitReason) \
136	do { \
137	AssertMsg((pVCpu)->hm.s.idxExitHistoryFree < RT_ELEMENTS((pVCpu)->hm.s.auExitHistory), ("%u\n", (pVCpu)->hm.s.idxExitHistoryFree)); \
138	(pVCpu)->hm.s.auExitHistory[(pVCpu)->hm.s.idxExitHistoryFree++] = (uint16_t)(a_ExitReason); \
139	if ((pVCpu)->hm.s.idxExitHistoryFree == RT_ELEMENTS((pVCpu)->hm.s.auExitHistory)) \
140	(pVCpu)->hm.s.idxExitHistoryFree = 0; \
141	(pVCpu)->hm.s.auExitHistory[(pVCpu)->hm.s.idxExitHistoryFree] = UINT16_MAX; \
142	} while (0)
143
144	/** Maximum number of exit reason statistics counters. */
145	#define MAX_EXITREASON_STAT 0x100
146	#define MASK_EXITREASON_STAT 0xff
147	#define MASK_INJECT_IRQ_STAT 0xff
148
149	/** @name HM changed flags.
150	* These flags are used to keep track of which important registers that have
151	* been changed since last they were reset.
152	*
153	* Flags marked "shared" are used for registers that are common to both the host
154	* and guest (i.e. without dedicated VMCS/VMCB fields for guest bits).
155	*
156	* @{
157	*/
158	#define HM_CHANGED_GUEST_CR0 RT_BIT(0) /* Shared */
159	#define HM_CHANGED_GUEST_CR3 RT_BIT(1)
160	#define HM_CHANGED_GUEST_CR4 RT_BIT(2)
161	#define HM_CHANGED_GUEST_GDTR RT_BIT(3)
162	#define HM_CHANGED_GUEST_IDTR RT_BIT(4)
163	#define HM_CHANGED_GUEST_LDTR RT_BIT(5)
164	#define HM_CHANGED_GUEST_TR RT_BIT(6)
165	#define HM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(7)
166	#define HM_CHANGED_GUEST_DEBUG RT_BIT(8) /* Shared */
167	#define HM_CHANGED_GUEST_RIP RT_BIT(9)
168	#define HM_CHANGED_GUEST_RSP RT_BIT(10)
169	#define HM_CHANGED_GUEST_RFLAGS RT_BIT(11)
170	#define HM_CHANGED_GUEST_CR2 RT_BIT(12)
171	#define HM_CHANGED_GUEST_SYSENTER_CS_MSR RT_BIT(13)
172	#define HM_CHANGED_GUEST_SYSENTER_EIP_MSR RT_BIT(14)
173	#define HM_CHANGED_GUEST_SYSENTER_ESP_MSR RT_BIT(15)
174	#define HM_CHANGED_GUEST_EFER_MSR RT_BIT(16)
175	#define HM_CHANGED_GUEST_APIC_STATE RT_BIT(17)
176	#define HM_CHANGED_GUEST_HWVIRT RT_BIT(18)
177	/* Logically common VMM state. */
178	#define HM_CHANGED_VMM_GUEST_XCPT_INTERCEPTS RT_BIT(19)
179	#define HM_CHANGED_VMM_GUEST_LAZY_MSRS RT_BIT(20)
180	/* VT-x specific state. */
181	#define HM_CHANGED_VMX_GUEST_AUTO_MSRS RT_BIT(21)
182	#define HM_CHANGED_VMX_GUEST_ACTIVITY_STATE RT_BIT(22)
183	#define HM_CHANGED_VMX_ENTRY_CTLS RT_BIT(23)
184	#define HM_CHANGED_VMX_EXIT_CTLS RT_BIT(24)
185	/* AMD-V specific state. */
186	#define HM_CHANGED_SVM_RESERVED1 RT_BIT(21)
187	#define HM_CHANGED_SVM_RESERVED2 RT_BIT(22)
188	#define HM_CHANGED_SVM_RESERVED3 RT_BIT(23)
189	#define HM_CHANGED_SVM_RESERVED4 RT_BIT(24)
190
191	#define HM_CHANGED_ALL_GUEST ( HM_CHANGED_GUEST_CR0 \
192	\| HM_CHANGED_GUEST_CR3 \
193	\| HM_CHANGED_GUEST_CR4 \
194	\| HM_CHANGED_GUEST_GDTR \
195	\| HM_CHANGED_GUEST_IDTR \
196	\| HM_CHANGED_GUEST_LDTR \
197	\| HM_CHANGED_GUEST_TR \
198	\| HM_CHANGED_GUEST_SEGMENT_REGS \
199	\| HM_CHANGED_GUEST_DEBUG \
200	\| HM_CHANGED_GUEST_RIP \
201	\| HM_CHANGED_GUEST_RSP \
202	\| HM_CHANGED_GUEST_RFLAGS \
203	\| HM_CHANGED_GUEST_CR2 \
204	\| HM_CHANGED_GUEST_SYSENTER_CS_MSR \
205	\| HM_CHANGED_GUEST_SYSENTER_EIP_MSR \
206	\| HM_CHANGED_GUEST_SYSENTER_ESP_MSR \
207	\| HM_CHANGED_GUEST_EFER_MSR \
208	\| HM_CHANGED_GUEST_APIC_STATE \
209	\| HM_CHANGED_GUEST_HWVIRT \
210	\| HM_CHANGED_VMM_GUEST_XCPT_INTERCEPTS \
211	\| HM_CHANGED_VMM_GUEST_LAZY_MSRS \
212	\| HM_CHANGED_VMX_GUEST_AUTO_MSRS \
213	\| HM_CHANGED_VMX_GUEST_ACTIVITY_STATE \
214	\| HM_CHANGED_VMX_ENTRY_CTLS \
215	\| HM_CHANGED_VMX_EXIT_CTLS)
216
217	#define HM_CHANGED_HOST_CONTEXT RT_BIT(25)
218
219	/* Bits shared between host and guest. */
220	#define HM_CHANGED_HOST_GUEST_SHARED_STATE ( HM_CHANGED_GUEST_CR0 \
221	\| HM_CHANGED_GUEST_DEBUG \
222	\| HM_CHANGED_VMM_GUEST_LAZY_MSRS)
223	/** @} */
224
225	/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
226	#define HM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
227	/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
228	#define HM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2 * PAGE_SIZE + 1)
229	/** Total guest mapped memory needed. */
230	#define HM_VTX_TOTAL_DEVHEAP_MEM (HM_EPT_IDENTITY_PG_TABLE_SIZE + HM_VTX_TSS_SIZE)
231
232
233	/** @name Macros for enabling and disabling preemption.
234	* These are really just for hiding the RTTHREADPREEMPTSTATE and asserting that
235	* preemption has already been disabled when there is no context hook.
236	* @{ */
237	#ifdef VBOX_STRICT
238	# define HM_DISABLE_PREEMPT() \
239	RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
240	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD) \|\| VMMR0ThreadCtxHookIsEnabled(pVCpu)); \
241	RTThreadPreemptDisable(&PreemptStateInternal)
242	#else
243	# define HM_DISABLE_PREEMPT() \
244	RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
245	RTThreadPreemptDisable(&PreemptStateInternal)
246	#endif /* VBOX_STRICT */
247	#define HM_RESTORE_PREEMPT() do { RTThreadPreemptRestore(&PreemptStateInternal); } while(0)
248	/** @} */
249
250
251	/** @name HM saved state versions.
252	* @{
253	*/
254	#define HM_SAVED_STATE_VERSION HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT
255	#define HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT 6
256	#define HM_SAVED_STATE_VERSION_TPR_PATCHING 5
257	#define HM_SAVED_STATE_VERSION_NO_TPR_PATCHING 4
258	#define HM_SAVED_STATE_VERSION_2_0_X 3
259	/** @} */
260
261
262	/**
263	* Global per-cpu information. (host)
264	*/
265	typedef struct HMGLOBALCPUINFO
266	{
267	/** The CPU ID. */
268	RTCPUID idCpu;
269	/** The VM_HSAVE_AREA (AMD-V) / VMXON region (Intel) memory backing. */
270	RTR0MEMOBJ hMemObj;
271	/** The physical address of the first page in hMemObj (it's a
272	* physcially contigous allocation if it spans multiple pages). */
273	RTHCPHYS HCPhysMemObj;
274	/** The address of the memory (for pfnEnable). */
275	void *pvMemObj;
276	/** Current ASID (AMD-V) / VPID (Intel). */
277	uint32_t uCurrentAsid;
278	/** TLB flush count. */
279	uint32_t cTlbFlushes;
280	/** Whether to flush each new ASID/VPID before use. */
281	bool fFlushAsidBeforeUse;
282	/** Configured for VT-x or AMD-V. */
283	bool fConfigured;
284	/** Set if the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active. */
285	bool fIgnoreAMDVInUseError;
286	/** In use by our code. (for power suspend) */
287	volatile bool fInUse;
288	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
289	/** Nested-guest union (put data common to SVM/VMX outside the union). */
290	union
291	{
292	/** Nested-guest SVM data. */
293	struct
294	{
295	/** The active nested-guest MSR permission bitmap memory backing. */
296	RTR0MEMOBJ hNstGstMsrpm;
297	/** The physical address of the first page in hNstGstMsrpm (physcially
298	* contigous allocation). */
299	RTHCPHYS HCPhysNstGstMsrpm;
300	/** The address of the active nested-guest MSRPM. */
301	void *pvNstGstMsrpm;
302	} svm;
303	/** @todo Nested-VMX. */
304	} n;
305	#endif
306	} HMGLOBALCPUINFO;
307	/** Pointer to the per-cpu global information. */
308	typedef HMGLOBALCPUINFO *PHMGLOBALCPUINFO;
309
310	typedef enum
311	{
312	HMPENDINGIO_INVALID = 0,
313	HMPENDINGIO_PORT_READ,
314	/* not implemented: HMPENDINGIO_STRING_READ, */
315	/* not implemented: HMPENDINGIO_STRING_WRITE, */
316	/** The usual 32-bit paranoia. */
317	HMPENDINGIO_32BIT_HACK = 0x7fffffff
318	} HMPENDINGIO;
319
320
321	typedef enum
322	{
323	HMTPRINSTR_INVALID,
324	HMTPRINSTR_READ,
325	HMTPRINSTR_READ_SHR4,
326	HMTPRINSTR_WRITE_REG,
327	HMTPRINSTR_WRITE_IMM,
328	HMTPRINSTR_JUMP_REPLACEMENT,
329	/** The usual 32-bit paranoia. */
330	HMTPRINSTR_32BIT_HACK = 0x7fffffff
331	} HMTPRINSTR;
332
333	typedef struct
334	{
335	/** The key is the address of patched instruction. (32 bits GC ptr) */
336	AVLOU32NODECORE Core;
337	/** Original opcode. */
338	uint8_t aOpcode[16];
339	/** Instruction size. */
340	uint32_t cbOp;
341	/** Replacement opcode. */
342	uint8_t aNewOpcode[16];
343	/** Replacement instruction size. */
344	uint32_t cbNewOp;
345	/** Instruction type. */
346	HMTPRINSTR enmType;
347	/** Source operand. */
348	uint32_t uSrcOperand;
349	/** Destination operand. */
350	uint32_t uDstOperand;
351	/** Number of times the instruction caused a fault. */
352	uint32_t cFaults;
353	/** Patch address of the jump replacement. */
354	RTGCPTR32 pJumpTarget;
355	} HMTPRPATCH;
356	/** Pointer to HMTPRPATCH. */
357	typedef HMTPRPATCH *PHMTPRPATCH;
358	/** Pointer to a const HMTPRPATCH. */
359	typedef const HMTPRPATCH *PCHMTPRPATCH;
360
361
362	/**
363	* Makes a HMEXITSTAT::uKey value from a program counter and an exit code.
364	*
365	* @returns 64-bit key
366	* @param a_uPC The RIP + CS.BASE value of the exit.
367	* @param a_uExit The exit code.
368	* @todo Add CPL?
369	*/
370	#define HMEXITSTAT_MAKE_KEY(a_uPC, a_uExit) (((a_uPC) & UINT64_C(0x0000ffffffffffff)) \| (uint64_t)(a_uExit) << 48)
371
372	typedef struct HMEXITINFO
373	{
374	/** See HMEXITSTAT_MAKE_KEY(). */
375	uint64_t uKey;
376	/** Number of recent hits (depreciates with time). */
377	uint32_t volatile cHits;
378	/** The age + lock. */
379	uint16_t volatile uAge;
380	/** Action or action table index. */
381	uint16_t iAction;
382	} HMEXITINFO;
383	AssertCompileSize(HMEXITINFO, 16); /* Lots of these guys, so don't add any unnecessary stuff! */
384
385	typedef struct HMEXITHISTORY
386	{
387	/** The exit timestamp. */
388	uint64_t uTscExit;
389	/** The index of the corresponding HMEXITINFO entry.
390	* UINT32_MAX if none (too many collisions, race, whatever). */
391	uint32_t iExitInfo;
392	/** Figure out later, needed for padding now. */
393	uint32_t uSomeClueOrSomething;
394	} HMEXITHISTORY;
395
396	/**
397	* Switcher function, HC to the special 64-bit RC.
398	*
399	* @param pVM The cross context VM structure.
400	* @param offCpumVCpu Offset from pVM->cpum to pVM->aCpus[idCpu].cpum.
401	* @returns Return code indicating the action to take.
402	*/
403	typedef DECLCALLBACK(int) FNHMSWITCHERHC(PVM pVM, uint32_t offCpumVCpu);
404	/** Pointer to switcher function. */
405	typedef FNHMSWITCHERHC *PFNHMSWITCHERHC;
406
407	/**
408	* HM VM Instance data.
409	* Changes to this must checked against the padding of the hm union in VM!
410	*/
411	typedef struct HM
412	{
413	/** Set when we've initialized VMX or SVM. */
414	bool fInitialized;
415	/** Set if nested paging is enabled. */
416	bool fNestedPaging;
417	/** Set if nested paging is allowed. */
418	bool fAllowNestedPaging;
419	/** Set if large pages are enabled (requires nested paging). */
420	bool fLargePages;
421	/** Set if we can support 64-bit guests or not. */
422	bool fAllow64BitGuests;
423	/** Set when TPR patching is allowed. */
424	bool fTprPatchingAllowed;
425	/** Set when we initialize VT-x or AMD-V once for all CPUs. */
426	bool fGlobalInit;
427	/** Set when TPR patching is active. */
428	bool fTPRPatchingActive;
429	/** Set when the debug facility has breakpoints/events enabled that requires
430	* us to use the debug execution loop in ring-0. */
431	bool fUseDebugLoop;
432	/** Set if hardware APIC virtualization is enabled. */
433	bool fVirtApicRegs;
434	/** Set if posted interrupt processing is enabled. */
435	bool fPostedIntrs;
436	/** Set if indirect branch prediction barrier on VM exit. */
437	bool fIbpbOnVmExit;
438	/** Set if indirect branch prediction barrier on VM entry. */
439	bool fIbpbOnVmEntry;
440	/** Set if host manages speculation control settings. */
441	bool fSpecCtrlByHost;
442	/** Explicit padding. */
443	bool afPadding[2];
444
445	/** Maximum ASID allowed. */
446	uint32_t uMaxAsid;
447	/** The maximum number of resumes loops allowed in ring-0 (safety precaution).
448	* This number is set much higher when RTThreadPreemptIsPending is reliable. */
449	uint32_t cMaxResumeLoops;
450
451	/** Host kernel flags that HM might need to know (SUPKERNELFEATURES_XXX). */
452	uint32_t fHostKernelFeatures;
453
454	/** Size of the guest patch memory block. */
455	uint32_t cbGuestPatchMem;
456	/** Guest allocated memory for patching purposes. */
457	RTGCPTR pGuestPatchMem;
458	/** Current free pointer inside the patch block. */
459	RTGCPTR pFreeGuestPatchMem;
460
461	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
462	/** 32 to 64 bits switcher entrypoint. */
463	R0PTRTYPE(PFNHMSWITCHERHC) pfnHost32ToGuest64R0;
464	RTR0PTR pvR0Alignment0;
465	#endif
466
467	struct
468	{
469	/** Set by the ring-0 side of HM to indicate VMX is supported by the
470	* CPU. */
471	bool fSupported;
472	/** Set when we've enabled VMX. */
473	bool fEnabled;
474	/** Set if VPID is supported. */
475	bool fVpid;
476	/** Set if VT-x VPID is allowed. */
477	bool fAllowVpid;
478	/** Set if unrestricted guest execution is in use (real and protected mode without paging). */
479	bool fUnrestrictedGuest;
480	/** Set if unrestricted guest execution is allowed to be used. */
481	bool fAllowUnrestricted;
482	/** Whether we're using the preemption timer or not. */
483	bool fUsePreemptTimer;
484	/** The shift mask employed by the VMX-Preemption timer. */
485	uint8_t cPreemptTimerShift;
486
487	/** Virtual address of the TSS page used for real mode emulation. */
488	R3PTRTYPE(PVBOXTSS) pRealModeTSS;
489	/** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
490	R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
491
492	/** Physical address of the APIC-access page. */
493	RTHCPHYS HCPhysApicAccess;
494	/** R0 memory object for the APIC-access page. */
495	RTR0MEMOBJ hMemObjApicAccess;
496	/** Virtual address of the APIC-access page. */
497	R0PTRTYPE(uint8_t *) pbApicAccess;
498
499	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
500	RTHCPHYS HCPhysScratch;
501	RTR0MEMOBJ hMemObjScratch;
502	R0PTRTYPE(uint8_t *) pbScratch;
503	#endif
504
505	/** Internal Id of which flush-handler to use for tagged-TLB entries. */
506	uint32_t uFlushTaggedTlb;
507
508	/** Pause-loop exiting (PLE) gap in ticks. */
509	uint32_t cPleGapTicks;
510	/** Pause-loop exiting (PLE) window in ticks. */
511	uint32_t cPleWindowTicks;
512	uint32_t u32Alignment0;
513
514	/** Host CR4 value (set by ring-0 VMX init) */
515	uint64_t u64HostCr4;
516	/** Host SMM monitor control (set by ring-0 VMX init) */
517	uint64_t u64HostSmmMonitorCtl;
518	/** Host EFER value (set by ring-0 VMX init) */
519	uint64_t u64HostEfer;
520	/** Whether the CPU supports VMCS fields for swapping EFER. */
521	bool fSupportsVmcsEfer;
522	uint8_t u8Alignment2[7];
523
524	/** VMX MSR values. */
525	VMXMSRS Msrs;
526
527	/** Flush types for invept & invvpid; they depend on capabilities. */
528	VMXFLUSHEPT enmFlushEpt;
529	VMXFLUSHVPID enmFlushVpid;
530
531	/** Host-physical address for a failing VMXON instruction. */
532	RTHCPHYS HCPhysVmxEnableError;
533	} vmx;
534
535	struct
536	{
537	/** Set by the ring-0 side of HM to indicate SVM is supported by the
538	* CPU. */
539	bool fSupported;
540	/** Set when we've enabled SVM. */
541	bool fEnabled;
542	/** Set if erratum 170 affects the AMD cpu. */
543	bool fAlwaysFlushTLB;
544	/** Set when the hack to ignore VERR_SVM_IN_USE is active. */
545	bool fIgnoreInUseError;
546	/** Whether to use virtualized VMSAVE/VMLOAD feature. */
547	bool fVirtVmsaveVmload;
548	/** Whether to use virtual GIF feature. */
549	bool fVGif;
550	uint8_t u8Alignment0[2];
551
552	/** Physical address of the IO bitmap (12kb). */
553	RTHCPHYS HCPhysIOBitmap;
554	/** R0 memory object for the IO bitmap (12kb). */
555	RTR0MEMOBJ hMemObjIOBitmap;
556	/** Virtual address of the IO bitmap. */
557	R0PTRTYPE(void *) pvIOBitmap;
558
559	/* HWCR MSR (for diagnostics) */
560	uint64_t u64MsrHwcr;
561
562	/** SVM revision. */
563	uint32_t u32Rev;
564	/** SVM feature bits from cpuid 0x8000000a */
565	uint32_t u32Features;
566
567	/** Pause filter counter. */
568	uint16_t cPauseFilter;
569	/** Pause filter treshold in ticks. */
570	uint16_t cPauseFilterThresholdTicks;
571	uint32_t u32Alignment0;
572	} svm;
573
574	/**
575	* AVL tree with all patches (active or disabled) sorted by guest instruction
576	* address.
577	*/
578	AVLOU32TREE PatchTree;
579	uint32_t cPatches;
580	HMTPRPATCH aPatches[64];
581
582	struct
583	{
584	uint32_t u32AMDFeatureECX;
585	uint32_t u32AMDFeatureEDX;
586	} cpuid;
587
588	/** Saved error from detection */
589	int32_t lLastError;
590
591	/** HMR0Init was run */
592	bool fHMR0Init;
593	bool u8Alignment1[3];
594
595	STAMCOUNTER StatTprPatchSuccess;
596	STAMCOUNTER StatTprPatchFailure;
597	STAMCOUNTER StatTprReplaceSuccessCr8;
598	STAMCOUNTER StatTprReplaceSuccessVmc;
599	STAMCOUNTER StatTprReplaceFailure;
600	} HM;
601	/** Pointer to HM VM instance data. */
602	typedef HM *PHM;
603
604	AssertCompileMemberAlignment(HM, StatTprPatchSuccess, 8);
605
606	/* Maximum number of cached entries. */
607	#define VMCSCACHE_MAX_ENTRY 128
608
609	/**
610	* Structure for storing read and write VMCS actions.
611	*/
612	typedef struct VMCSCACHE
613	{
614	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
615	/* Magic marker for searching in crash dumps. */
616	uint8_t aMagic[16];
617	uint64_t uMagic;
618	uint64_t u64TimeEntry;
619	uint64_t u64TimeSwitch;
620	uint64_t cResume;
621	uint64_t interPD;
622	uint64_t pSwitcher;
623	uint32_t uPos;
624	uint32_t idCpu;
625	#endif
626	/* CR2 is saved here for EPT syncing. */
627	uint64_t cr2;
628	struct
629	{
630	uint32_t cValidEntries;
631	uint32_t uAlignment;
632	uint32_t aField[VMCSCACHE_MAX_ENTRY];
633	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
634	} Write;
635	struct
636	{
637	uint32_t cValidEntries;
638	uint32_t uAlignment;
639	uint32_t aField[VMCSCACHE_MAX_ENTRY];
640	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
641	} Read;
642	#ifdef VBOX_STRICT
643	struct
644	{
645	RTHCPHYS HCPhysCpuPage;
646	RTHCPHYS HCPhysVmcs;
647	RTGCPTR pCache;
648	RTGCPTR pCtx;
649	} TestIn;
650	struct
651	{
652	RTHCPHYS HCPhysVmcs;
653	RTGCPTR pCache;
654	RTGCPTR pCtx;
655	uint64_t eflags;
656	uint64_t cr8;
657	} TestOut;
658	struct
659	{
660	uint64_t param1;
661	uint64_t param2;
662	uint64_t param3;
663	uint64_t param4;
664	} ScratchPad;
665	#endif
666	} VMCSCACHE;
667	/** Pointer to VMCSCACHE. */
668	typedef VMCSCACHE *PVMCSCACHE;
669	AssertCompileSizeAlignment(VMCSCACHE, 8);
670
671	/**
672	* VMX StartVM function.
673	*
674	* @returns VBox status code (no informational stuff).
675	* @param fResume Whether to use VMRESUME (true) or VMLAUNCH (false).
676	* @param pCtx The CPU register context.
677	* @param pCache The VMCS cache.
678	* @param pVM Pointer to the cross context VM structure.
679	* @param pVCpu Pointer to the cross context per-CPU structure.
680	*/
681	typedef DECLCALLBACK(int) FNHMVMXSTARTVM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);
682	/** Pointer to a VMX StartVM function. */
683	typedef R0PTRTYPE(FNHMVMXSTARTVM *) PFNHMVMXSTARTVM;
684
685	/** SVM VMRun function. */
686	typedef DECLCALLBACK(int) FNHMSVMVMRUN(RTHCPHYS pVmcbHostPhys, RTHCPHYS pVmcbPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu);
687	/** Pointer to a SVM VMRun function. */
688	typedef R0PTRTYPE(FNHMSVMVMRUN *) PFNHMSVMVMRUN;
689
690	/**
691	* HM VMCPU Instance data.
692	*
693	* Note! If you change members of this struct, make sure to check if the
694	* assembly counterpart in HMInternal.mac needs to be updated as well.
695	*/
696	typedef struct HMCPU
697	{
698	/** Set if we need to flush the TLB during the world switch. */
699	bool fForceTLBFlush;
700	/** Set when we're using VT-x or AMD-V at that moment. */
701	bool fActive;
702	/** Set when the TLB has been checked until we return from the world switch. */
703	volatile bool fCheckedTLBFlush;
704	/** Whether we've completed the inner HM leave function. */
705	bool fLeaveDone;
706	/** Whether we're using the hyper DR7 or guest DR7. */
707	bool fUsingHyperDR7;
708	/** Set if XCR0 needs to be loaded and saved when entering and exiting guest
709	* code execution. */
710	bool fLoadSaveGuestXcr0;
711
712	/** Whether we should use the debug loop because of single stepping or special
713	* debug breakpoints / events are armed. */
714	bool fUseDebugLoop;
715	/** Whether we are currently executing in the debug loop.
716	* Mainly for assertions. */
717	bool fUsingDebugLoop;
718	/** Set if we using the debug loop and wish to intercept RDTSC. */
719	bool fDebugWantRdTscExit;
720	/** Whether we're executing a single instruction. */
721	bool fSingleInstruction;
722	/** Set if we need to clear the trap flag because of single stepping. */
723	bool fClearTrapFlag;
724
725	/** Whether \#UD needs to be intercepted (required by certain GIM providers). */
726	bool fGIMTrapXcptUD;
727	uint8_t u8Alignment0[4];
728
729	/** World switch exit counter. */
730	volatile uint32_t cWorldSwitchExits;
731	/** HM_CHANGED_* flags. */
732	volatile uint32_t fContextUseFlags;
733	/** Id of the last cpu we were executing code on (NIL_RTCPUID for the first
734	* time). */
735	RTCPUID idLastCpu;
736	/** TLB flush count. */
737	uint32_t cTlbFlushes;
738	/** Current ASID in use by the VM. */
739	uint32_t uCurrentAsid;
740	/** An additional error code used for some gurus. */
741	uint32_t u32HMError;
742	/** Host's TSC_AUX MSR (used when RDTSCP doesn't cause VM-exits). */
743	uint64_t u64HostTscAux;
744
745	struct
746	{
747	/** Ring 0 handlers for VT-x. */
748	PFNHMVMXSTARTVM pfnStartVM;
749	#if HC_ARCH_BITS == 32
750	uint32_t u32Alignment0;
751	#endif
752	/** Current VMX_VMCS32_CTRL_PIN_EXEC. */
753	uint32_t u32PinCtls;
754	/** Current VMX_VMCS32_CTRL_PROC_EXEC. */
755	uint32_t u32ProcCtls;
756	/** Current VMX_VMCS32_CTRL_PROC_EXEC2. */
757	uint32_t u32ProcCtls2;
758	/** Current VMX_VMCS32_CTRL_EXIT. */
759	uint32_t u32ExitCtls;
760	/** Current VMX_VMCS32_CTRL_ENTRY. */
761	uint32_t u32EntryCtls;
762
763	/** Current CR0 mask. */
764	uint32_t u32CR0Mask;
765	/** Current CR4 mask. */
766	uint32_t u32CR4Mask;
767	/** Current exception bitmap. */
768	uint32_t u32XcptBitmap;
769	/** The updated-guest-state mask. */
770	volatile uint32_t fUpdatedGuestState;
771	uint32_t u32Alignment1;
772
773	/** Physical address of the VM control structure (VMCS). */
774	RTHCPHYS HCPhysVmcs;
775	/** R0 memory object for the VM control structure (VMCS). */
776	RTR0MEMOBJ hMemObjVmcs;
777	/** Virtual address of the VM control structure (VMCS). */
778	R0PTRTYPE(void *) pvVmcs;
779
780	/** Physical address of the virtual APIC page for TPR caching. */
781	RTHCPHYS HCPhysVirtApic;
782	/** Padding. */
783	R0PTRTYPE(void *) pvAlignment0;
784	/** Virtual address of the virtual APIC page for TPR caching. */
785	R0PTRTYPE(uint8_t *) pbVirtApic;
786
787	/** Physical address of the MSR bitmap. */
788	RTHCPHYS HCPhysMsrBitmap;
789	/** R0 memory object for the MSR bitmap. */
790	RTR0MEMOBJ hMemObjMsrBitmap;
791	/** Virtual address of the MSR bitmap. */
792	R0PTRTYPE(void *) pvMsrBitmap;
793
794	/** Physical address of the VM-entry MSR-load and VM-exit MSR-store area (used
795	* for guest MSRs). */
796	RTHCPHYS HCPhysGuestMsr;
797	/** R0 memory object of the VM-entry MSR-load and VM-exit MSR-store area
798	* (used for guest MSRs). */
799	RTR0MEMOBJ hMemObjGuestMsr;
800	/** Virtual address of the VM-entry MSR-load and VM-exit MSR-store area (used
801	* for guest MSRs). */
802	R0PTRTYPE(void *) pvGuestMsr;
803
804	/** Physical address of the VM-exit MSR-load area (used for host MSRs). */
805	RTHCPHYS HCPhysHostMsr;
806	/** R0 memory object for the VM-exit MSR-load area (used for host MSRs). */
807	RTR0MEMOBJ hMemObjHostMsr;
808	/** Virtual address of the VM-exit MSR-load area (used for host MSRs). */
809	R0PTRTYPE(void *) pvHostMsr;
810
811	/** Current EPTP. */
812	RTHCPHYS HCPhysEPTP;
813
814	/** Number of guest/host MSR pairs in the auto-load/store area. */
815	uint32_t cMsrs;
816	/** Whether the host MSR values are up-to-date in the auto-load/store area. */
817	bool fUpdatedHostMsrs;
818	uint8_t u8Alignment0[3];
819
820	/** Host LSTAR MSR value to restore lazily while leaving VT-x. */
821	uint64_t u64HostLStarMsr;
822	/** Host STAR MSR value to restore lazily while leaving VT-x. */
823	uint64_t u64HostStarMsr;
824	/** Host SF_MASK MSR value to restore lazily while leaving VT-x. */
825	uint64_t u64HostSFMaskMsr;
826	/** Host KernelGS-Base MSR value to restore lazily while leaving VT-x. */
827	uint64_t u64HostKernelGSBaseMsr;
828	/** A mask of which MSRs have been swapped and need restoration. */
829	uint32_t fLazyMsrs;
830	uint32_t u32Alignment2;
831
832	/** The cached APIC-base MSR used for identifying when to map the HC physical APIC-access page. */
833	uint64_t u64MsrApicBase;
834	/** Last use TSC offset value. (cached) */
835	uint64_t u64TSCOffset;
836
837	/** VMCS cache. */
838	VMCSCACHE VMCSCache;
839
840	/** Real-mode emulation state. */
841	struct
842	{
843	X86DESCATTR AttrCS;
844	X86DESCATTR AttrDS;
845	X86DESCATTR AttrES;
846	X86DESCATTR AttrFS;
847	X86DESCATTR AttrGS;
848	X86DESCATTR AttrSS;
849	X86EFLAGS Eflags;
850	uint32_t fRealOnV86Active;
851	} RealMode;
852
853	/** VT-x error-reporting (mainly for ring-3 propagation). */
854	struct
855	{
856	uint64_t u64VMCSPhys;
857	uint32_t u32VMCSRevision;
858	uint32_t u32InstrError;
859	uint32_t u32ExitReason;
860	RTCPUID idEnteredCpu;
861	RTCPUID idCurrentCpu;
862	uint32_t u32Alignment0;
863	} LastError;
864
865	/** Current state of the VMCS. */
866	uint32_t uVmcsState;
867	/** Which host-state bits to restore before being preempted. */
868	uint32_t fRestoreHostFlags;
869	/** The host-state restoration structure. */
870	VMXRESTOREHOST RestoreHost;
871
872	/** Set if guest was executing in real mode (extra checks). */
873	bool fWasInRealMode;
874	/** Set if guest switched to 64-bit mode on a 32-bit host. */
875	bool fSwitchedTo64on32;
876
877	uint8_t u8Alignment1[6];
878	} vmx;
879
880	struct
881	{
882	/** Ring 0 handlers for VT-x. */
883	PFNHMSVMVMRUN pfnVMRun;
884	#if HC_ARCH_BITS == 32
885	uint32_t u32Alignment0;
886	#endif
887
888	/** Physical address of the host VMCB which holds additional host-state. */
889	RTHCPHYS HCPhysVmcbHost;
890	/** R0 memory object for the host VMCB which holds additional host-state. */
891	RTR0MEMOBJ hMemObjVmcbHost;
892	/** Padding. */
893	R0PTRTYPE(void *) pvPadding;
894
895	/** Physical address of the guest VMCB. */
896	RTHCPHYS HCPhysVmcb;
897	/** R0 memory object for the guest VMCB. */
898	RTR0MEMOBJ hMemObjVmcb;
899	/** Pointer to the guest VMCB. */
900	R0PTRTYPE(PSVMVMCB) pVmcb;
901
902	/** Physical address of the MSR bitmap (8 KB). */
903	RTHCPHYS HCPhysMsrBitmap;
904	/** R0 memory object for the MSR bitmap (8 KB). */
905	RTR0MEMOBJ hMemObjMsrBitmap;
906	/** Pointer to the MSR bitmap. */
907	R0PTRTYPE(void *) pvMsrBitmap;
908
909	/** Whether VTPR with V_INTR_MASKING set is in effect, indicating
910	* we should check if the VTPR changed on every VM-exit. */
911	bool fSyncVTpr;
912	uint8_t u8Alignment0[7];
913
914	/** Cache of the nested-guest's VMCB fields that we modify in order to run the
915	* nested-guest using AMD-V. This will be restored on \#VMEXIT. */
916	SVMNESTEDVMCBCACHE NstGstVmcbCache;
917	} svm;
918
919	/** Event injection state. */
920	struct
921	{
922	uint32_t fPending;
923	uint32_t u32ErrCode;
924	uint32_t cbInstr;
925	uint32_t u32Padding; /*< Explicit alignment padding. /
926	uint64_t u64IntInfo;
927	RTGCUINTPTR GCPtrFaultAddress;
928	} Event;
929
930	/** IO Block emulation state. */
931	struct
932	{
933	bool fEnabled;
934	uint8_t u8Align[7];
935
936	/** RIP at the start of the io code we wish to emulate in the recompiler. */
937	RTGCPTR GCPtrFunctionEip;
938
939	uint64_t cr0;
940	} EmulateIoBlock;
941
942	/* */
943	struct
944	{
945	/** Pending IO operation type. */
946	HMPENDINGIO enmType;
947	uint32_t u32Alignment0;
948	RTGCPTR GCPtrRip;
949	RTGCPTR GCPtrRipNext;
950	union
951	{
952	struct
953	{
954	uint32_t uPort;
955	uint32_t uAndVal;
956	uint32_t cbSize;
957	} Port;
958	uint64_t aRaw[2];
959	} s;
960	} PendingIO;
961
962	/** The PAE PDPEs used with Nested Paging (only valid when
963	* VMCPU_FF_HM_UPDATE_PAE_PDPES is set). */
964	X86PDPE aPdpes[4];
965
966	/** Current shadow paging mode. */
967	PGMMODE enmShadowMode;
968
969	/** The CPU ID of the CPU currently owning the VMCS. Set in
970	* HMR0Enter and cleared in HMR0Leave. */
971	RTCPUID idEnteredCpu;
972
973	/** VT-x/AMD-V VM-exit/\#VMXEXIT history, circular array. */
974	uint16_t auExitHistory[31];
975	/** The index of the next free slot in the history array. */
976	uint16_t idxExitHistoryFree;
977
978	/** For saving stack space, the disassembler state is allocated here instead of
979	* on the stack. */
980	DISCPUSTATE DisState;
981
982	STAMPROFILEADV StatEntry;
983	STAMPROFILEADV StatExit1;
984	STAMPROFILEADV StatExit2;
985	STAMPROFILEADV StatExitIO;
986	STAMPROFILEADV StatExitMovCRx;
987	STAMPROFILEADV StatExitXcptNmi;
988	STAMPROFILEADV StatLoadGuestState;
989	STAMPROFILEADV StatLoadGuestFpuState;
990	STAMPROFILEADV StatInGC;
991
992	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
993	STAMPROFILEADV StatWorldSwitch3264;
994	#endif
995	STAMPROFILEADV StatPoke;
996	STAMPROFILEADV StatSpinPoke;
997	STAMPROFILEADV StatSpinPokeFailed;
998
999	STAMCOUNTER StatInjectInterrupt;
1000	STAMCOUNTER StatInjectXcpt;
1001	STAMCOUNTER StatInjectPendingReflect;
1002	STAMCOUNTER StatInjectPendingInterpret;
1003
1004	STAMCOUNTER StatExitAll;
1005	STAMCOUNTER StatExitShadowNM;
1006	STAMCOUNTER StatExitGuestNM;
1007	STAMCOUNTER StatExitShadowPF; /*< Misleading, currently used for MMIO \#PFs as well. /
1008	STAMCOUNTER StatExitShadowPFEM;
1009	STAMCOUNTER StatExitGuestPF;
1010	STAMCOUNTER StatExitGuestUD;
1011	STAMCOUNTER StatExitGuestSS;
1012	STAMCOUNTER StatExitGuestNP;
1013	STAMCOUNTER StatExitGuestTS;
1014	STAMCOUNTER StatExitGuestGP;
1015	STAMCOUNTER StatExitGuestDE;
1016	STAMCOUNTER StatExitGuestDB;
1017	STAMCOUNTER StatExitGuestMF;
1018	STAMCOUNTER StatExitGuestBP;
1019	STAMCOUNTER StatExitGuestXF;
1020	STAMCOUNTER StatExitGuestXcpUnk;
1021	STAMCOUNTER StatExitInvlpg;
1022	STAMCOUNTER StatExitInvd;
1023	STAMCOUNTER StatExitWbinvd;
1024	STAMCOUNTER StatExitPause;
1025	STAMCOUNTER StatExitCpuid;
1026	STAMCOUNTER StatExitRdtsc;
1027	STAMCOUNTER StatExitRdtscp;
1028	STAMCOUNTER StatExitRdpmc;
1029	STAMCOUNTER StatExitVmcall;
1030	STAMCOUNTER StatExitRdrand;
1031	STAMCOUNTER StatExitCli;
1032	STAMCOUNTER StatExitSti;
1033	STAMCOUNTER StatExitPushf;
1034	STAMCOUNTER StatExitPopf;
1035	STAMCOUNTER StatExitIret;
1036	STAMCOUNTER StatExitInt;
1037	STAMCOUNTER StatExitCRxWrite[16];
1038	STAMCOUNTER StatExitCRxRead[16];
1039	STAMCOUNTER StatExitDRxWrite;
1040	STAMCOUNTER StatExitDRxRead;
1041	STAMCOUNTER StatExitRdmsr;
1042	STAMCOUNTER StatExitWrmsr;
1043	STAMCOUNTER StatExitClts;
1044	STAMCOUNTER StatExitXdtrAccess;
1045	STAMCOUNTER StatExitHlt;
1046	STAMCOUNTER StatExitMwait;
1047	STAMCOUNTER StatExitMonitor;
1048	STAMCOUNTER StatExitLmsw;
1049	STAMCOUNTER StatExitIOWrite;
1050	STAMCOUNTER StatExitIORead;
1051	STAMCOUNTER StatExitIOStringWrite;
1052	STAMCOUNTER StatExitIOStringRead;
1053	STAMCOUNTER StatExitIntWindow;
1054	STAMCOUNTER StatExitExtInt;
1055	STAMCOUNTER StatExitHostNmiInGC;
1056	STAMCOUNTER StatExitPreemptTimer;
1057	STAMCOUNTER StatExitTprBelowThreshold;
1058	STAMCOUNTER StatExitTaskSwitch;
1059	STAMCOUNTER StatExitMtf;
1060	STAMCOUNTER StatExitApicAccess;
1061	STAMCOUNTER StatPendingHostIrq;
1062
1063	STAMCOUNTER StatFlushPage;
1064	STAMCOUNTER StatFlushPageManual;
1065	STAMCOUNTER StatFlushPhysPageManual;
1066	STAMCOUNTER StatFlushTlb;
1067	STAMCOUNTER StatFlushTlbManual;
1068	STAMCOUNTER StatFlushTlbWorldSwitch;
1069	STAMCOUNTER StatNoFlushTlbWorldSwitch;
1070	STAMCOUNTER StatFlushEntire;
1071	STAMCOUNTER StatFlushAsid;
1072	STAMCOUNTER StatFlushNestedPaging;
1073	STAMCOUNTER StatFlushTlbInvlpgVirt;
1074	STAMCOUNTER StatFlushTlbInvlpgPhys;
1075	STAMCOUNTER StatTlbShootdown;
1076	STAMCOUNTER StatTlbShootdownFlush;
1077
1078	STAMCOUNTER StatSwitchTprMaskedIrq;
1079	STAMCOUNTER StatSwitchGuestIrq;
1080	STAMCOUNTER StatSwitchHmToR3FF;
1081	STAMCOUNTER StatSwitchExitToR3;
1082	STAMCOUNTER StatSwitchLongJmpToR3;
1083	STAMCOUNTER StatSwitchMaxResumeLoops;
1084	STAMCOUNTER StatSwitchHltToR3;
1085	STAMCOUNTER StatSwitchApicAccessToR3;
1086	STAMCOUNTER StatSwitchPreempt;
1087	STAMCOUNTER StatSwitchPreemptSaveHostState;
1088
1089	STAMCOUNTER StatTscParavirt;
1090	STAMCOUNTER StatTscOffset;
1091	STAMCOUNTER StatTscIntercept;
1092
1093	STAMCOUNTER StatExitReasonNpf;
1094	STAMCOUNTER StatDRxArmed;
1095	STAMCOUNTER StatDRxContextSwitch;
1096	STAMCOUNTER StatDRxIoCheck;
1097
1098	STAMCOUNTER StatLoadMinimal;
1099	STAMCOUNTER StatLoadFull;
1100	STAMCOUNTER StatLoadGuestFpu;
1101
1102	STAMCOUNTER StatVmxCheckBadRmSelBase;
1103	STAMCOUNTER StatVmxCheckBadRmSelLimit;
1104	STAMCOUNTER StatVmxCheckRmOk;
1105
1106	STAMCOUNTER StatVmxCheckBadSel;
1107	STAMCOUNTER StatVmxCheckBadRpl;
1108	STAMCOUNTER StatVmxCheckBadLdt;
1109	STAMCOUNTER StatVmxCheckBadTr;
1110	STAMCOUNTER StatVmxCheckPmOk;
1111
1112	STAMCOUNTER StatNestedExitReasonNpf;
1113
1114	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1115	STAMCOUNTER StatFpu64SwitchBack;
1116	STAMCOUNTER StatDebug64SwitchBack;
1117	#endif
1118
1119	#ifdef VBOX_WITH_STATISTICS
1120	R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
1121	R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
1122	R3PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqs;
1123	R0PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqsR0;
1124	R3PTRTYPE(PSTAMCOUNTER) paStatNestedExitReason;
1125	R0PTRTYPE(PSTAMCOUNTER) paStatNestedExitReasonR0;
1126	#endif
1127	#ifdef HM_PROFILE_EXIT_DISPATCH
1128	STAMPROFILEADV StatExitDispatch;
1129	#endif
1130	} HMCPU;
1131	/** Pointer to HM VMCPU instance data. */
1132	typedef HMCPU *PHMCPU;
1133	AssertCompileMemberAlignment(HMCPU, vmx, 8);
1134	AssertCompileMemberAlignment(HMCPU, svm, 8);
1135	AssertCompileMemberAlignment(HMCPU, Event, 8);
1136
1137	#ifdef IN_RING0
1138	VMMR0_INT_DECL(PHMGLOBALCPUINFO) hmR0GetCurrentCpu(void);
1139
1140	# ifdef VBOX_STRICT
1141	VMMR0_INT_DECL(void) hmR0DumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
1142	VMMR0_INT_DECL(void) hmR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg);
1143	# else
1144	# define hmR0DumpRegs(a, b ,c) do { } while (0)
1145	# define hmR0DumpDescriptor(a, b, c) do { } while (0)
1146	# endif /* VBOX_STRICT */
1147
1148	# ifdef VBOX_WITH_KERNEL_USING_XMM
1149	DECLASM(int) hmR0VMXStartVMWrapXMM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu, PFNHMVMXSTARTVM pfnStartVM);
1150	DECLASM(int) hmR0SVMRunWrapXMM(RTHCPHYS pVmcbHostPhys, RTHCPHYS pVmcbPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu, PFNHMSVMVMRUN pfnVMRun);
1151	# endif
1152
1153	#endif /* IN_RING0 */
1154
1155	int hmSvmEmulateMovTpr(PVMCPU pVCpu, PCPUMCTX pCtx);
1156
1157	/** @} */
1158
1159	RT_C_DECLS_END
1160
1161	#endif
1162

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source: vbox/trunk/src/VBox/VMM/include/HMInternal.h@ 72532

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