VirtualBox

source: vbox/trunk/src/VBox/VMM/include/HMInternal.h@ 72967

Last change on this file since 72967 was 72967, checked in by vboxsync, 6 years ago

VMM/HMSVM: bugref:9193 Stop passing pCtx around and use pVCpu->cpum.GstCtx instead where possible.
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1/* $Id: HMInternal.h 72967 2018-07-08 10:38:08Z vboxsync $ */
2/** @file
3 * HM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2017 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef ___HMInternal_h
19#define ___HMInternal_h
20
21#include <VBox/cdefs.h>
22#include <VBox/types.h>
23#include <VBox/vmm/em.h>
24#include <VBox/vmm/stam.h>
25#include <VBox/dis.h>
26#include <VBox/vmm/hm.h>
27#include <VBox/vmm/hm_vmx.h>
28#include <VBox/vmm/hm_svm.h>
29#include <VBox/vmm/pgm.h>
30#include <VBox/vmm/cpum.h>
31#include <VBox/vmm/trpm.h>
32#include <iprt/memobj.h>
33#include <iprt/cpuset.h>
34#include <iprt/mp.h>
35#include <iprt/avl.h>
36#include <iprt/string.h>
37
38#if HC_ARCH_BITS == 32 && defined(RT_OS_DARWIN)
39# error "32-bit darwin is no longer supported. Go back to 4.3 or earlier!"
40#endif
41
42#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_64_BITS_GUESTS)
43/* Enable 64 bits guest support. */
44# define VBOX_ENABLE_64_BITS_GUESTS
45#endif
46
47#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
48# define VMX_USE_CACHED_VMCS_ACCESSES
49#endif
50
51/** @def HM_PROFILE_EXIT_DISPATCH
52 * Enables profiling of the VM exit handler dispatching. */
53#if 0 || defined(DOXYGEN_RUNNING)
54# define HM_PROFILE_EXIT_DISPATCH
55#endif
56
57RT_C_DECLS_BEGIN
58
59
60/** @defgroup grp_hm_int Internal
61 * @ingroup grp_hm
62 * @internal
63 * @{
64 */
65
66/** @name HM_CHANGED_XXX
67 * HM CPU-context changed flags.
68 *
69 * These flags are used to keep track of which registers and state has been
70 * modified since they were imported back into the guest-CPU context.
71 *
72 * @{
73 */
74#define HM_CHANGED_HOST_CONTEXT UINT64_C(0x0000000000000001)
75#define HM_CHANGED_GUEST_RIP UINT64_C(0x0000000000000004)
76#define HM_CHANGED_GUEST_RFLAGS UINT64_C(0x0000000000000008)
77
78#define HM_CHANGED_GUEST_RAX UINT64_C(0x0000000000000010)
79#define HM_CHANGED_GUEST_RCX UINT64_C(0x0000000000000020)
80#define HM_CHANGED_GUEST_RDX UINT64_C(0x0000000000000040)
81#define HM_CHANGED_GUEST_RBX UINT64_C(0x0000000000000080)
82#define HM_CHANGED_GUEST_RSP UINT64_C(0x0000000000000100)
83#define HM_CHANGED_GUEST_RBP UINT64_C(0x0000000000000200)
84#define HM_CHANGED_GUEST_RSI UINT64_C(0x0000000000000400)
85#define HM_CHANGED_GUEST_RDI UINT64_C(0x0000000000000800)
86#define HM_CHANGED_GUEST_R8_R15 UINT64_C(0x0000000000001000)
87#define HM_CHANGED_GUEST_GPRS_MASK UINT64_C(0x0000000000001ff0)
88
89#define HM_CHANGED_GUEST_ES UINT64_C(0x0000000000002000)
90#define HM_CHANGED_GUEST_CS UINT64_C(0x0000000000004000)
91#define HM_CHANGED_GUEST_SS UINT64_C(0x0000000000008000)
92#define HM_CHANGED_GUEST_DS UINT64_C(0x0000000000010000)
93#define HM_CHANGED_GUEST_FS UINT64_C(0x0000000000020000)
94#define HM_CHANGED_GUEST_GS UINT64_C(0x0000000000040000)
95#define HM_CHANGED_GUEST_SREG_MASK UINT64_C(0x000000000007e000)
96
97#define HM_CHANGED_GUEST_GDTR UINT64_C(0x0000000000080000)
98#define HM_CHANGED_GUEST_IDTR UINT64_C(0x0000000000100000)
99#define HM_CHANGED_GUEST_LDTR UINT64_C(0x0000000000200000)
100#define HM_CHANGED_GUEST_TR UINT64_C(0x0000000000400000)
101#define HM_CHANGED_GUEST_TABLE_MASK UINT64_C(0x0000000000780000)
102
103#define HM_CHANGED_GUEST_CR0 UINT64_C(0x0000000000800000)
104#define HM_CHANGED_GUEST_CR2 UINT64_C(0x0000000001000000)
105#define HM_CHANGED_GUEST_CR3 UINT64_C(0x0000000002000000)
106#define HM_CHANGED_GUEST_CR4 UINT64_C(0x0000000004000000)
107#define HM_CHANGED_GUEST_CR_MASK UINT64_C(0x0000000007800000)
108
109#define HM_CHANGED_GUEST_APIC_TPR UINT64_C(0x0000000008000000)
110#define HM_CHANGED_GUEST_EFER_MSR UINT64_C(0x0000000010000000)
111
112#define HM_CHANGED_GUEST_DR0_DR3 UINT64_C(0x0000000020000000)
113#define HM_CHANGED_GUEST_DR6 UINT64_C(0x0000000040000000)
114#define HM_CHANGED_GUEST_DR7 UINT64_C(0x0000000080000000)
115#define HM_CHANGED_GUEST_DR_MASK UINT64_C(0x00000000e0000000)
116
117#define HM_CHANGED_GUEST_X87 UINT64_C(0x0000000100000000)
118#define HM_CHANGED_GUEST_SSE_AVX UINT64_C(0x0000000200000000)
119#define HM_CHANGED_GUEST_OTHER_XSAVE UINT64_C(0x0000000400000000)
120#define HM_CHANGED_GUEST_XCRx UINT64_C(0x0000000800000000)
121
122#define HM_CHANGED_GUEST_KERNEL_GS_BASE UINT64_C(0x0000001000000000)
123#define HM_CHANGED_GUEST_SYSCALL_MSRS UINT64_C(0x0000002000000000)
124#define HM_CHANGED_GUEST_SYSENTER_CS_MSR UINT64_C(0x0000004000000000)
125#define HM_CHANGED_GUEST_SYSENTER_EIP_MSR UINT64_C(0x0000008000000000)
126#define HM_CHANGED_GUEST_SYSENTER_ESP_MSR UINT64_C(0x0000010000000000)
127#define HM_CHANGED_GUEST_SYSENTER_MSR_MASK UINT64_C(0x000001c000000000)
128#define HM_CHANGED_GUEST_TSC_AUX UINT64_C(0x0000020000000000)
129#define HM_CHANGED_GUEST_OTHER_MSRS UINT64_C(0x0000040000000000)
130#define HM_CHANGED_GUEST_ALL_MSRS ( HM_CHANGED_GUEST_EFER \
131 | HM_CHANGED_GUEST_KERNEL_GS_BASE \
132 | HM_CHANGED_GUEST_SYSCALL_MSRS \
133 | HM_CHANGED_GUEST_SYSENTER_MSR_MASK \
134 | HM_CHANGED_GUEST_TSC_AUX \
135 | HM_CHANGED_GUEST_OTHER_MSRS)
136
137#define HM_CHANGED_GUEST_HWVIRT UINT64_C(0x0000080000000000)
138#define HM_CHANGED_GUEST_MASK UINT64_C(0x00000ffffffffffc)
139
140#define HM_CHANGED_KEEPER_STATE_MASK UINT64_C(0xffff000000000000)
141
142#define HM_CHANGED_VMX_GUEST_XCPT_INTERCEPTS UINT64_C(0x0001000000000000)
143#define HM_CHANGED_VMX_GUEST_AUTO_MSRS UINT64_C(0x0002000000000000)
144#define HM_CHANGED_VMX_GUEST_LAZY_MSRS UINT64_C(0x0004000000000000)
145#define HM_CHANGED_VMX_ENTRY_CTLS UINT64_C(0x0008000000000000)
146#define HM_CHANGED_VMX_EXIT_CTLS UINT64_C(0x0010000000000000)
147#define HM_CHANGED_VMX_MASK UINT64_C(0x001f000000000000)
148#define HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE ( HM_CHANGED_GUEST_DR_MASK \
149 | HM_CHANGED_VMX_GUEST_LAZY_MSRS)
150
151#define HM_CHANGED_SVM_GUEST_XCPT_INTERCEPTS UINT64_C(0x0001000000000000)
152#define HM_CHANGED_SVM_MASK UINT64_C(0x0001000000000000)
153#define HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE HM_CHANGED_GUEST_DR_MASK
154
155#define HM_CHANGED_ALL_GUEST ( HM_CHANGED_GUEST_MASK \
156 | HM_CHANGED_KEEPER_STATE_MASK)
157
158/** Mask of what state might have changed when IEM raised an exception.
159 This is a combination IEM_CPUMCTX_EXTRN_MUST_MASK and IEM_CPUMCTX_EXTRN_XCPT_MASK. */
160#define HM_CHANGED_XCPT_RAISED_MASK ( HM_CHANGED_GUEST_GPRS_MASK \
161 | HM_CHANGED_GUEST_RIP \
162 | HM_CHANGED_GUEST_RFLAGS \
163 | HM_CHANGED_GUEST_SS \
164 | HM_CHANGED_GUEST_CS \
165 | HM_CHANGED_GUEST_CR0 \
166 | HM_CHANGED_GUEST_CR3 \
167 | HM_CHANGED_GUEST_CR4 \
168 | HM_CHANGED_GUEST_APIC_TPR \
169 | HM_CHANGED_GUEST_EFER_MSR \
170 | HM_CHANGED_GUEST_DR7 \
171 | HM_CHANGED_GUEST_CR2 \
172 | HM_CHANGED_GUEST_SREG_MASK \
173 | HM_CHANGED_GUEST_TABLE_MASK)
174
175#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
176/** Mask of what state might have changed when \#VMEXIT is emulated. */
177# define HM_CHANGED_SVM_VMEXIT_MASK ( HM_CHANGED_GUEST_RSP \
178 | HM_CHANGED_GUEST_RAX \
179 | HM_CHANGED_GUEST_RIP \
180 | HM_CHANGED_GUEST_RFLAGS \
181 | HM_CHANGED_GUEST_CS \
182 | HM_CHANGED_GUEST_SS \
183 | HM_CHANGED_GUEST_DS \
184 | HM_CHANGED_GUEST_ES \
185 | HM_CHANGED_GUEST_GDTR \
186 | HM_CHANGED_GUEST_IDTR \
187 | HM_CHANGED_GUEST_CR_MASK \
188 | HM_CHANGED_GUEST_EFER_MSR \
189 | HM_CHANGED_GUEST_DR6 \
190 | HM_CHANGED_GUEST_DR7 \
191 | HM_CHANGED_GUEST_OTHER_MSRS \
192 | HM_CHANGED_GUEST_HWVIRT \
193 | HM_CHANGED_SVM_MASK \
194 | HM_CHANGED_GUEST_APIC_TPR)
195
196/** Mask of what state might have changed when \#VMEXIT is emulated. */
197# define HM_CHANGED_SVM_VMRUN_MASK HM_CHANGED_SVM_VMEXIT_MASK
198#endif
199/** @} */
200
201/** Maximum number of exit reason statistics counters. */
202#define MAX_EXITREASON_STAT 0x100
203#define MASK_EXITREASON_STAT 0xff
204#define MASK_INJECT_IRQ_STAT 0xff
205
206/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
207#define HM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
208/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
209#define HM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2 * PAGE_SIZE + 1)
210/** Total guest mapped memory needed. */
211#define HM_VTX_TOTAL_DEVHEAP_MEM (HM_EPT_IDENTITY_PG_TABLE_SIZE + HM_VTX_TSS_SIZE)
212
213
214/** @name Macros for enabling and disabling preemption.
215 * These are really just for hiding the RTTHREADPREEMPTSTATE and asserting that
216 * preemption has already been disabled when there is no context hook.
217 * @{ */
218#ifdef VBOX_STRICT
219# define HM_DISABLE_PREEMPT() \
220 RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
221 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD) || VMMR0ThreadCtxHookIsEnabled(pVCpu)); \
222 RTThreadPreemptDisable(&PreemptStateInternal)
223#else
224# define HM_DISABLE_PREEMPT() \
225 RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
226 RTThreadPreemptDisable(&PreemptStateInternal)
227#endif /* VBOX_STRICT */
228#define HM_RESTORE_PREEMPT() do { RTThreadPreemptRestore(&PreemptStateInternal); } while(0)
229/** @} */
230
231
232/** @name HM saved state versions.
233 * @{
234 */
235#define HM_SAVED_STATE_VERSION HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT
236#define HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT 6
237#define HM_SAVED_STATE_VERSION_TPR_PATCHING 5
238#define HM_SAVED_STATE_VERSION_NO_TPR_PATCHING 4
239#define HM_SAVED_STATE_VERSION_2_0_X 3
240/** @} */
241
242
243/**
244 * Global per-cpu information. (host)
245 */
246typedef struct HMGLOBALCPUINFO
247{
248 /** The CPU ID. */
249 RTCPUID idCpu;
250 /** The VM_HSAVE_AREA (AMD-V) / VMXON region (Intel) memory backing. */
251 RTR0MEMOBJ hMemObj;
252 /** The physical address of the first page in hMemObj (it's a
253 * physcially contigous allocation if it spans multiple pages). */
254 RTHCPHYS HCPhysMemObj;
255 /** The address of the memory (for pfnEnable). */
256 void *pvMemObj;
257 /** Current ASID (AMD-V) / VPID (Intel). */
258 uint32_t uCurrentAsid;
259 /** TLB flush count. */
260 uint32_t cTlbFlushes;
261 /** Whether to flush each new ASID/VPID before use. */
262 bool fFlushAsidBeforeUse;
263 /** Configured for VT-x or AMD-V. */
264 bool fConfigured;
265 /** Set if the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active. */
266 bool fIgnoreAMDVInUseError;
267 /** In use by our code. (for power suspend) */
268 bool volatile fInUse;
269#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
270 /** Nested-guest union (put data common to SVM/VMX outside the union). */
271 union
272 {
273 /** Nested-guest SVM data. */
274 struct
275 {
276 /** The active nested-guest MSR permission bitmap memory backing. */
277 RTR0MEMOBJ hNstGstMsrpm;
278 /** The physical address of the first page in hNstGstMsrpm (physcially
279 * contiguous allocation). */
280 RTHCPHYS HCPhysNstGstMsrpm;
281 /** The address of the active nested-guest MSRPM. */
282 void *pvNstGstMsrpm;
283 } svm;
284 /** @todo Nested-VMX. */
285 } n;
286#endif
287} HMGLOBALCPUINFO;
288/** Pointer to the per-cpu global information. */
289typedef HMGLOBALCPUINFO *PHMGLOBALCPUINFO;
290
291typedef enum
292{
293 HMPENDINGIO_INVALID = 0,
294 HMPENDINGIO_PORT_READ,
295 /* not implemented: HMPENDINGIO_STRING_READ, */
296 /* not implemented: HMPENDINGIO_STRING_WRITE, */
297 /** The usual 32-bit paranoia. */
298 HMPENDINGIO_32BIT_HACK = 0x7fffffff
299} HMPENDINGIO;
300
301
302typedef enum
303{
304 HMTPRINSTR_INVALID,
305 HMTPRINSTR_READ,
306 HMTPRINSTR_READ_SHR4,
307 HMTPRINSTR_WRITE_REG,
308 HMTPRINSTR_WRITE_IMM,
309 HMTPRINSTR_JUMP_REPLACEMENT,
310 /** The usual 32-bit paranoia. */
311 HMTPRINSTR_32BIT_HACK = 0x7fffffff
312} HMTPRINSTR;
313
314typedef struct
315{
316 /** The key is the address of patched instruction. (32 bits GC ptr) */
317 AVLOU32NODECORE Core;
318 /** Original opcode. */
319 uint8_t aOpcode[16];
320 /** Instruction size. */
321 uint32_t cbOp;
322 /** Replacement opcode. */
323 uint8_t aNewOpcode[16];
324 /** Replacement instruction size. */
325 uint32_t cbNewOp;
326 /** Instruction type. */
327 HMTPRINSTR enmType;
328 /** Source operand. */
329 uint32_t uSrcOperand;
330 /** Destination operand. */
331 uint32_t uDstOperand;
332 /** Number of times the instruction caused a fault. */
333 uint32_t cFaults;
334 /** Patch address of the jump replacement. */
335 RTGCPTR32 pJumpTarget;
336} HMTPRPATCH;
337/** Pointer to HMTPRPATCH. */
338typedef HMTPRPATCH *PHMTPRPATCH;
339/** Pointer to a const HMTPRPATCH. */
340typedef const HMTPRPATCH *PCHMTPRPATCH;
341
342
343/**
344 * Makes a HMEXITSTAT::uKey value from a program counter and an exit code.
345 *
346 * @returns 64-bit key
347 * @param a_uPC The RIP + CS.BASE value of the exit.
348 * @param a_uExit The exit code.
349 * @todo Add CPL?
350 */
351#define HMEXITSTAT_MAKE_KEY(a_uPC, a_uExit) (((a_uPC) & UINT64_C(0x0000ffffffffffff)) | (uint64_t)(a_uExit) << 48)
352
353typedef struct HMEXITINFO
354{
355 /** See HMEXITSTAT_MAKE_KEY(). */
356 uint64_t uKey;
357 /** Number of recent hits (depreciates with time). */
358 uint32_t volatile cHits;
359 /** The age + lock. */
360 uint16_t volatile uAge;
361 /** Action or action table index. */
362 uint16_t iAction;
363} HMEXITINFO;
364AssertCompileSize(HMEXITINFO, 16); /* Lots of these guys, so don't add any unnecessary stuff! */
365
366typedef struct HMEXITHISTORY
367{
368 /** The exit timestamp. */
369 uint64_t uTscExit;
370 /** The index of the corresponding HMEXITINFO entry.
371 * UINT32_MAX if none (too many collisions, race, whatever). */
372 uint32_t iExitInfo;
373 /** Figure out later, needed for padding now. */
374 uint32_t uSomeClueOrSomething;
375} HMEXITHISTORY;
376
377/**
378 * Switcher function, HC to the special 64-bit RC.
379 *
380 * @param pVM The cross context VM structure.
381 * @param offCpumVCpu Offset from pVM->cpum to pVM->aCpus[idCpu].cpum.
382 * @returns Return code indicating the action to take.
383 */
384typedef DECLCALLBACK(int) FNHMSWITCHERHC(PVM pVM, uint32_t offCpumVCpu);
385/** Pointer to switcher function. */
386typedef FNHMSWITCHERHC *PFNHMSWITCHERHC;
387
388/**
389 * HM VM Instance data.
390 * Changes to this must checked against the padding of the hm union in VM!
391 */
392typedef struct HM
393{
394 /** Set when we've initialized VMX or SVM. */
395 bool fInitialized;
396 /** Set if nested paging is enabled. */
397 bool fNestedPaging;
398 /** Set if nested paging is allowed. */
399 bool fAllowNestedPaging;
400 /** Set if large pages are enabled (requires nested paging). */
401 bool fLargePages;
402 /** Set if we can support 64-bit guests or not. */
403 bool fAllow64BitGuests;
404 /** Set when TPR patching is allowed. */
405 bool fTprPatchingAllowed;
406 /** Set when we initialize VT-x or AMD-V once for all CPUs. */
407 bool fGlobalInit;
408 /** Set when TPR patching is active. */
409 bool fTPRPatchingActive;
410 /** Set when the debug facility has breakpoints/events enabled that requires
411 * us to use the debug execution loop in ring-0. */
412 bool fUseDebugLoop;
413 /** Set if hardware APIC virtualization is enabled. */
414 bool fVirtApicRegs;
415 /** Set if posted interrupt processing is enabled. */
416 bool fPostedIntrs;
417 /** Set if indirect branch prediction barrier on VM exit. */
418 bool fIbpbOnVmExit;
419 /** Set if indirect branch prediction barrier on VM entry. */
420 bool fIbpbOnVmEntry;
421 /** Set if host manages speculation control settings. */
422 bool fSpecCtrlByHost;
423 /** Explicit padding. */
424 bool afPadding[2];
425
426 /** Maximum ASID allowed. */
427 uint32_t uMaxAsid;
428 /** The maximum number of resumes loops allowed in ring-0 (safety precaution).
429 * This number is set much higher when RTThreadPreemptIsPending is reliable. */
430 uint32_t cMaxResumeLoops;
431
432 /** Host kernel flags that HM might need to know (SUPKERNELFEATURES_XXX). */
433 uint32_t fHostKernelFeatures;
434
435 /** Size of the guest patch memory block. */
436 uint32_t cbGuestPatchMem;
437 /** Guest allocated memory for patching purposes. */
438 RTGCPTR pGuestPatchMem;
439 /** Current free pointer inside the patch block. */
440 RTGCPTR pFreeGuestPatchMem;
441
442#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
443 /** 32 to 64 bits switcher entrypoint. */
444 R0PTRTYPE(PFNHMSWITCHERHC) pfnHost32ToGuest64R0;
445 RTR0PTR pvR0Alignment0;
446#endif
447
448 struct
449 {
450 /** Set by the ring-0 side of HM to indicate VMX is supported by the
451 * CPU. */
452 bool fSupported;
453 /** Set when we've enabled VMX. */
454 bool fEnabled;
455 /** Set if VPID is supported. */
456 bool fVpid;
457 /** Set if VT-x VPID is allowed. */
458 bool fAllowVpid;
459 /** Set if unrestricted guest execution is in use (real and protected mode without paging). */
460 bool fUnrestrictedGuest;
461 /** Set if unrestricted guest execution is allowed to be used. */
462 bool fAllowUnrestricted;
463 /** Set if the preemption timer is in use or not. */
464 bool fUsePreemptTimer;
465 /** The shift mask employed by the VMX-Preemption timer. */
466 uint8_t cPreemptTimerShift;
467
468 /** Virtual address of the TSS page used for real mode emulation. */
469 R3PTRTYPE(PVBOXTSS) pRealModeTSS;
470 /** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
471 R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
472
473 /** Physical address of the APIC-access page. */
474 RTHCPHYS HCPhysApicAccess;
475 /** R0 memory object for the APIC-access page. */
476 RTR0MEMOBJ hMemObjApicAccess;
477 /** Virtual address of the APIC-access page. */
478 R0PTRTYPE(uint8_t *) pbApicAccess;
479
480#ifdef VBOX_WITH_CRASHDUMP_MAGIC
481 RTHCPHYS HCPhysScratch;
482 RTR0MEMOBJ hMemObjScratch;
483 R0PTRTYPE(uint8_t *) pbScratch;
484#endif
485
486 /** Tagged-TLB flush type. */
487 VMXTLBFLUSHTYPE enmTlbFlushType;
488 /** Flush type to use for INVEPT. */
489 VMXTLBFLUSHEPT enmTlbFlushEpt;
490 /** Flush type to use for INVVPID. */
491 VMXTLBFLUSHVPID enmTlbFlushVpid;
492
493 /** Pause-loop exiting (PLE) gap in ticks. */
494 uint32_t cPleGapTicks;
495 /** Pause-loop exiting (PLE) window in ticks. */
496 uint32_t cPleWindowTicks;
497 uint32_t u32Alignment0;
498
499 /** Host CR4 value (set by ring-0 VMX init) */
500 uint64_t u64HostCr4;
501 /** Host SMM monitor control (set by ring-0 VMX init) */
502 uint64_t u64HostSmmMonitorCtl;
503 /** Host EFER value (set by ring-0 VMX init) */
504 uint64_t u64HostEfer;
505 /** Whether the CPU supports VMCS fields for swapping EFER. */
506 bool fSupportsVmcsEfer;
507 uint8_t u8Alignment2[7];
508
509 /** VMX MSR values. */
510 VMXMSRS Msrs;
511
512 /** Host-physical address for a failing VMXON instruction. */
513 RTHCPHYS HCPhysVmxEnableError;
514 } vmx;
515
516 struct
517 {
518 /** Set by the ring-0 side of HM to indicate SVM is supported by the
519 * CPU. */
520 bool fSupported;
521 /** Set when we've enabled SVM. */
522 bool fEnabled;
523 /** Set if erratum 170 affects the AMD cpu. */
524 bool fAlwaysFlushTLB;
525 /** Set when the hack to ignore VERR_SVM_IN_USE is active. */
526 bool fIgnoreInUseError;
527 /** Whether to use virtualized VMSAVE/VMLOAD feature. */
528 bool fVirtVmsaveVmload;
529 /** Whether to use virtual GIF feature. */
530 bool fVGif;
531 uint8_t u8Alignment0[2];
532
533 /** Physical address of the IO bitmap (12kb). */
534 RTHCPHYS HCPhysIOBitmap;
535 /** R0 memory object for the IO bitmap (12kb). */
536 RTR0MEMOBJ hMemObjIOBitmap;
537 /** Virtual address of the IO bitmap. */
538 R0PTRTYPE(void *) pvIOBitmap;
539
540 /* HWCR MSR (for diagnostics) */
541 uint64_t u64MsrHwcr;
542
543 /** SVM revision. */
544 uint32_t u32Rev;
545 /** SVM feature bits from cpuid 0x8000000a */
546 uint32_t u32Features;
547
548 /** Pause filter counter. */
549 uint16_t cPauseFilter;
550 /** Pause filter treshold in ticks. */
551 uint16_t cPauseFilterThresholdTicks;
552 uint32_t u32Alignment0;
553 } svm;
554
555 /**
556 * AVL tree with all patches (active or disabled) sorted by guest instruction
557 * address.
558 */
559 AVLOU32TREE PatchTree;
560 uint32_t cPatches;
561 HMTPRPATCH aPatches[64];
562
563 struct
564 {
565 uint32_t u32AMDFeatureECX;
566 uint32_t u32AMDFeatureEDX;
567 } cpuid;
568
569 /** Last recorded error code during HM ring-0 init. */
570 int32_t rcInit;
571
572 /** HMR0Init was run */
573 bool fHMR0Init;
574 bool u8Alignment1[3];
575
576 STAMCOUNTER StatTprPatchSuccess;
577 STAMCOUNTER StatTprPatchFailure;
578 STAMCOUNTER StatTprReplaceSuccessCr8;
579 STAMCOUNTER StatTprReplaceSuccessVmc;
580 STAMCOUNTER StatTprReplaceFailure;
581} HM;
582/** Pointer to HM VM instance data. */
583typedef HM *PHM;
584
585AssertCompileMemberAlignment(HM, StatTprPatchSuccess, 8);
586
587/* Maximum number of cached entries. */
588#define VMCSCACHE_MAX_ENTRY 128
589
590/**
591 * Structure for storing read and write VMCS actions.
592 */
593typedef struct VMCSCACHE
594{
595#ifdef VBOX_WITH_CRASHDUMP_MAGIC
596 /* Magic marker for searching in crash dumps. */
597 uint8_t aMagic[16];
598 uint64_t uMagic;
599 uint64_t u64TimeEntry;
600 uint64_t u64TimeSwitch;
601 uint64_t cResume;
602 uint64_t interPD;
603 uint64_t pSwitcher;
604 uint32_t uPos;
605 uint32_t idCpu;
606#endif
607 /* CR2 is saved here for EPT syncing. */
608 uint64_t cr2;
609 struct
610 {
611 uint32_t cValidEntries;
612 uint32_t uAlignment;
613 uint32_t aField[VMCSCACHE_MAX_ENTRY];
614 uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
615 } Write;
616 struct
617 {
618 uint32_t cValidEntries;
619 uint32_t uAlignment;
620 uint32_t aField[VMCSCACHE_MAX_ENTRY];
621 uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
622 } Read;
623#ifdef VBOX_STRICT
624 struct
625 {
626 RTHCPHYS HCPhysCpuPage;
627 RTHCPHYS HCPhysVmcs;
628 RTGCPTR pCache;
629 RTGCPTR pCtx;
630 } TestIn;
631 struct
632 {
633 RTHCPHYS HCPhysVmcs;
634 RTGCPTR pCache;
635 RTGCPTR pCtx;
636 uint64_t eflags;
637 uint64_t cr8;
638 } TestOut;
639 struct
640 {
641 uint64_t param1;
642 uint64_t param2;
643 uint64_t param3;
644 uint64_t param4;
645 } ScratchPad;
646#endif
647} VMCSCACHE;
648/** Pointer to VMCSCACHE. */
649typedef VMCSCACHE *PVMCSCACHE;
650AssertCompileSizeAlignment(VMCSCACHE, 8);
651
652/**
653 * VMX StartVM function.
654 *
655 * @returns VBox status code (no informational stuff).
656 * @param fResume Whether to use VMRESUME (true) or VMLAUNCH (false).
657 * @param pCtx The CPU register context.
658 * @param pCache The VMCS cache.
659 * @param pVM Pointer to the cross context VM structure.
660 * @param pVCpu Pointer to the cross context per-CPU structure.
661 */
662typedef DECLCALLBACK(int) FNHMVMXSTARTVM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);
663/** Pointer to a VMX StartVM function. */
664typedef R0PTRTYPE(FNHMVMXSTARTVM *) PFNHMVMXSTARTVM;
665
666/** SVM VMRun function. */
667typedef DECLCALLBACK(int) FNHMSVMVMRUN(RTHCPHYS pVmcbHostPhys, RTHCPHYS pVmcbPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu);
668/** Pointer to a SVM VMRun function. */
669typedef R0PTRTYPE(FNHMSVMVMRUN *) PFNHMSVMVMRUN;
670
671/**
672 * HM VMCPU Instance data.
673 *
674 * Note! If you change members of this struct, make sure to check if the
675 * assembly counterpart in HMInternal.mac needs to be updated as well.
676 */
677typedef struct HMCPU
678{
679 /** Set when the TLB has been checked until we return from the world switch. */
680 bool volatile fCheckedTLBFlush;
681 /** Set if we need to flush the TLB during the world switch. */
682 bool fForceTLBFlush;
683 /** Set when we're using VT-x or AMD-V at that moment. */
684 bool fActive;
685 /** Whether we've completed the inner HM leave function. */
686 bool fLeaveDone;
687 /** Whether we're using the hyper DR7 or guest DR7. */
688 bool fUsingHyperDR7;
689 /** Set if XCR0 needs to be loaded and saved when entering and exiting guest
690 * code execution. */
691 bool fLoadSaveGuestXcr0;
692
693 /** Whether we should use the debug loop because of single stepping or special
694 * debug breakpoints / events are armed. */
695 bool fUseDebugLoop;
696 /** Whether we are currently executing in the debug loop.
697 * Mainly for assertions. */
698 bool fUsingDebugLoop;
699 /** Set if we using the debug loop and wish to intercept RDTSC. */
700 bool fDebugWantRdTscExit;
701 /** Whether we're executing a single instruction. */
702 bool fSingleInstruction;
703 /** Set if we need to clear the trap flag because of single stepping. */
704 bool fClearTrapFlag;
705
706 /** Whether \#UD needs to be intercepted (required by certain GIM providers). */
707 bool fGIMTrapXcptUD;
708 uint8_t u8Alignment0[4];
709
710 /** World switch exit counter. */
711 uint32_t volatile cWorldSwitchExits;
712 /** The last CPU we were executing code on (NIL_RTCPUID for the first time). */
713 RTCPUID idLastCpu;
714 /** TLB flush count. */
715 uint32_t cTlbFlushes;
716 /** Current ASID in use by the VM. */
717 uint32_t uCurrentAsid;
718 /** An additional error code used for some gurus. */
719 uint32_t u32HMError;
720 /** The last exit-to-ring-3 reason. */
721 int32_t rcLastExitToR3;
722 /** CPU-context changed flags (see HM_CHANGED_xxx). */
723 uint64_t fCtxChanged;
724 /** Host's TSC_AUX MSR (used when RDTSCP doesn't cause VM-exits). */
725 uint64_t u64HostTscAux;
726
727 struct
728 {
729 /** Ring 0 handlers for VT-x. */
730 PFNHMVMXSTARTVM pfnStartVM;
731#if HC_ARCH_BITS == 32
732 uint32_t u32Alignment0;
733#endif
734 /** Current VMX_VMCS32_CTRL_PIN_EXEC. */
735 uint32_t u32PinCtls;
736 /** Current VMX_VMCS32_CTRL_PROC_EXEC. */
737 uint32_t u32ProcCtls;
738 /** Current VMX_VMCS32_CTRL_PROC_EXEC2. */
739 uint32_t u32ProcCtls2;
740 /** Current VMX_VMCS32_CTRL_EXIT. */
741 uint32_t u32ExitCtls;
742 /** Current VMX_VMCS32_CTRL_ENTRY. */
743 uint32_t u32EntryCtls;
744
745 /** Current CR0 mask. */
746 uint32_t u32Cr0Mask;
747 /** Current CR4 mask. */
748 uint32_t u32Cr4Mask;
749 /** Current exception bitmap. */
750 uint32_t u32XcptBitmap;
751 /** The updated-guest-state mask. */
752 uint32_t au32Alignment0[2];
753
754 /** Physical address of the VM control structure (VMCS). */
755 RTHCPHYS HCPhysVmcs;
756 /** R0 memory object for the VM control structure (VMCS). */
757 RTR0MEMOBJ hMemObjVmcs;
758 /** Virtual address of the VM control structure (VMCS). */
759 R0PTRTYPE(void *) pvVmcs;
760
761 /** Physical address of the virtual APIC page for TPR caching. */
762 RTHCPHYS HCPhysVirtApic;
763 /** Padding. */
764 R0PTRTYPE(void *) pvAlignment0;
765 /** Virtual address of the virtual APIC page for TPR caching. */
766 R0PTRTYPE(uint8_t *) pbVirtApic;
767
768 /** Physical address of the MSR bitmap. */
769 RTHCPHYS HCPhysMsrBitmap;
770 /** R0 memory object for the MSR bitmap. */
771 RTR0MEMOBJ hMemObjMsrBitmap;
772 /** Virtual address of the MSR bitmap. */
773 R0PTRTYPE(void *) pvMsrBitmap;
774
775 /** Physical address of the VM-entry MSR-load and VM-exit MSR-store area (used
776 * for guest MSRs). */
777 RTHCPHYS HCPhysGuestMsr;
778 /** R0 memory object of the VM-entry MSR-load and VM-exit MSR-store area
779 * (used for guest MSRs). */
780 RTR0MEMOBJ hMemObjGuestMsr;
781 /** Virtual address of the VM-entry MSR-load and VM-exit MSR-store area (used
782 * for guest MSRs). */
783 R0PTRTYPE(void *) pvGuestMsr;
784
785 /** Physical address of the VM-exit MSR-load area (used for host MSRs). */
786 RTHCPHYS HCPhysHostMsr;
787 /** R0 memory object for the VM-exit MSR-load area (used for host MSRs). */
788 RTR0MEMOBJ hMemObjHostMsr;
789 /** Virtual address of the VM-exit MSR-load area (used for host MSRs). */
790 R0PTRTYPE(void *) pvHostMsr;
791
792 /** Current EPTP. */
793 RTHCPHYS HCPhysEPTP;
794
795 /** Number of guest/host MSR pairs in the auto-load/store area. */
796 uint32_t cMsrs;
797 /** Whether the host MSR values are up-to-date in the auto-load/store area. */
798 bool fUpdatedHostMsrs;
799 uint8_t u8Alignment0[3];
800
801 /** Host LSTAR MSR value to restore lazily while leaving VT-x. */
802 uint64_t u64HostLStarMsr;
803 /** Host STAR MSR value to restore lazily while leaving VT-x. */
804 uint64_t u64HostStarMsr;
805 /** Host SF_MASK MSR value to restore lazily while leaving VT-x. */
806 uint64_t u64HostSFMaskMsr;
807 /** Host KernelGS-Base MSR value to restore lazily while leaving VT-x. */
808 uint64_t u64HostKernelGSBaseMsr;
809 /** A mask of which MSRs have been swapped and need restoration. */
810 uint32_t fLazyMsrs;
811 uint32_t u32Alignment2;
812
813 /** The cached APIC-base MSR used for identifying when to map the HC physical APIC-access page. */
814 uint64_t u64MsrApicBase;
815 /** Last use TSC offset value. (cached) */
816 uint64_t u64TscOffset;
817
818 /** VMCS cache. */
819 VMCSCACHE VMCSCache;
820
821 /** Real-mode emulation state. */
822 struct
823 {
824 X86DESCATTR AttrCS;
825 X86DESCATTR AttrDS;
826 X86DESCATTR AttrES;
827 X86DESCATTR AttrFS;
828 X86DESCATTR AttrGS;
829 X86DESCATTR AttrSS;
830 X86EFLAGS Eflags;
831 uint32_t fRealOnV86Active;
832 } RealMode;
833
834 /** VT-x error-reporting (mainly for ring-3 propagation). */
835 struct
836 {
837 uint64_t u64VMCSPhys;
838 uint32_t u32VMCSRevision;
839 uint32_t u32InstrError;
840 uint32_t u32ExitReason;
841 RTCPUID idEnteredCpu;
842 RTCPUID idCurrentCpu;
843 uint32_t u32Alignment0;
844 } LastError;
845
846 /** Current state of the VMCS. */
847 uint32_t uVmcsState;
848 /** Which host-state bits to restore before being preempted. */
849 uint32_t fRestoreHostFlags;
850 /** The host-state restoration structure. */
851 VMXRESTOREHOST RestoreHost;
852
853 /** Set if guest was executing in real mode (extra checks). */
854 bool fWasInRealMode;
855 /** Set if guest switched to 64-bit mode on a 32-bit host. */
856 bool fSwitchedTo64on32;
857
858 uint8_t u8Alignment1[6];
859 } vmx;
860
861 struct
862 {
863 /** Ring 0 handlers for VT-x. */
864 PFNHMSVMVMRUN pfnVMRun;
865#if HC_ARCH_BITS == 32
866 uint32_t u32Alignment0;
867#endif
868
869 /** Physical address of the host VMCB which holds additional host-state. */
870 RTHCPHYS HCPhysVmcbHost;
871 /** R0 memory object for the host VMCB which holds additional host-state. */
872 RTR0MEMOBJ hMemObjVmcbHost;
873 /** Padding. */
874 R0PTRTYPE(void *) pvPadding;
875
876 /** Physical address of the guest VMCB. */
877 RTHCPHYS HCPhysVmcb;
878 /** R0 memory object for the guest VMCB. */
879 RTR0MEMOBJ hMemObjVmcb;
880 /** Pointer to the guest VMCB. */
881 R0PTRTYPE(PSVMVMCB) pVmcb;
882
883 /** Physical address of the MSR bitmap (8 KB). */
884 RTHCPHYS HCPhysMsrBitmap;
885 /** R0 memory object for the MSR bitmap (8 KB). */
886 RTR0MEMOBJ hMemObjMsrBitmap;
887 /** Pointer to the MSR bitmap. */
888 R0PTRTYPE(void *) pvMsrBitmap;
889
890 /** Whether VTPR with V_INTR_MASKING set is in effect, indicating
891 * we should check if the VTPR changed on every VM-exit. */
892 bool fSyncVTpr;
893 uint8_t u8Alignment0[7];
894
895 /** Cache of the nested-guest's VMCB fields that we modify in order to run the
896 * nested-guest using AMD-V. This will be restored on \#VMEXIT. */
897 SVMNESTEDVMCBCACHE NstGstVmcbCache;
898 } svm;
899
900 /** Event injection state. */
901 struct
902 {
903 uint32_t fPending;
904 uint32_t u32ErrCode;
905 uint32_t cbInstr;
906 uint32_t u32Padding; /**< Explicit alignment padding. */
907 uint64_t u64IntInfo;
908 RTGCUINTPTR GCPtrFaultAddress;
909 } Event;
910
911 /** IO Block emulation state. */
912 struct
913 {
914 bool fEnabled;
915 uint8_t u8Align[7];
916
917 /** RIP at the start of the io code we wish to emulate in the recompiler. */
918 RTGCPTR GCPtrFunctionEip;
919
920 uint64_t cr0;
921 } EmulateIoBlock;
922
923 /* Pending IO operation. */
924 struct
925 {
926 /** Pending IO operation type. */
927 HMPENDINGIO enmType;
928 uint32_t u32Alignment0;
929 RTGCPTR GCPtrRip;
930 RTGCPTR GCPtrRipNext;
931 union
932 {
933 struct
934 {
935 uint32_t uPort;
936 uint32_t uAndVal;
937 uint32_t cbSize;
938 } Port;
939 uint64_t aRaw[2];
940 } s;
941 } PendingIO;
942
943 /** The PAE PDPEs used with Nested Paging (only valid when
944 * VMCPU_FF_HM_UPDATE_PAE_PDPES is set). */
945 X86PDPE aPdpes[4];
946
947 /** Current shadow paging mode. */
948 PGMMODE enmShadowMode;
949
950 /** The CPU ID of the CPU currently owning the VMCS. Set in
951 * HMR0Enter and cleared in HMR0Leave. */
952 RTCPUID idEnteredCpu;
953
954 /** For saving stack space, the disassembler state is allocated here instead of
955 * on the stack. */
956 DISCPUSTATE DisState;
957
958 STAMPROFILEADV StatEntry;
959 STAMPROFILEADV StatPreExit;
960 STAMPROFILEADV StatExitHandling;
961 STAMPROFILEADV StatExitIO;
962 STAMPROFILEADV StatExitMovCRx;
963 STAMPROFILEADV StatExitXcptNmi;
964 STAMPROFILEADV StatImportGuestState;
965 STAMPROFILEADV StatExportGuestState;
966 STAMPROFILEADV StatLoadGuestFpuState;
967 STAMPROFILEADV StatInGC;
968
969#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
970 STAMPROFILEADV StatWorldSwitch3264;
971#endif
972 STAMPROFILEADV StatPoke;
973 STAMPROFILEADV StatSpinPoke;
974 STAMPROFILEADV StatSpinPokeFailed;
975
976 STAMCOUNTER StatInjectInterrupt;
977 STAMCOUNTER StatInjectXcpt;
978 STAMCOUNTER StatInjectPendingReflect;
979 STAMCOUNTER StatInjectPendingInterpret;
980
981 STAMCOUNTER StatExitAll;
982 STAMCOUNTER StatExitShadowNM;
983 STAMCOUNTER StatExitGuestNM;
984 STAMCOUNTER StatExitShadowPF; /**< Misleading, currently used for MMIO \#PFs as well. */
985 STAMCOUNTER StatExitShadowPFEM;
986 STAMCOUNTER StatExitGuestPF;
987 STAMCOUNTER StatExitGuestUD;
988 STAMCOUNTER StatExitGuestSS;
989 STAMCOUNTER StatExitGuestNP;
990 STAMCOUNTER StatExitGuestTS;
991 STAMCOUNTER StatExitGuestGP;
992 STAMCOUNTER StatExitGuestDE;
993 STAMCOUNTER StatExitGuestDB;
994 STAMCOUNTER StatExitGuestMF;
995 STAMCOUNTER StatExitGuestBP;
996 STAMCOUNTER StatExitGuestXF;
997 STAMCOUNTER StatExitGuestXcpUnk;
998 STAMCOUNTER StatExitCli;
999 STAMCOUNTER StatExitSti;
1000 STAMCOUNTER StatExitPushf;
1001 STAMCOUNTER StatExitPopf;
1002 STAMCOUNTER StatExitIret;
1003 STAMCOUNTER StatExitInt;
1004 STAMCOUNTER StatExitHlt;
1005 STAMCOUNTER StatExitDRxWrite;
1006 STAMCOUNTER StatExitDRxRead;
1007 STAMCOUNTER StatExitCR0Read;
1008 STAMCOUNTER StatExitCR2Read;
1009 STAMCOUNTER StatExitCR3Read;
1010 STAMCOUNTER StatExitCR4Read;
1011 STAMCOUNTER StatExitCR8Read;
1012 STAMCOUNTER StatExitCR0Write;
1013 STAMCOUNTER StatExitCR2Write;
1014 STAMCOUNTER StatExitCR3Write;
1015 STAMCOUNTER StatExitCR4Write;
1016 STAMCOUNTER StatExitCR8Write;
1017 STAMCOUNTER StatExitRdmsr;
1018 STAMCOUNTER StatExitWrmsr;
1019 STAMCOUNTER StatExitClts;
1020 STAMCOUNTER StatExitXdtrAccess;
1021 STAMCOUNTER StatExitMwait;
1022 STAMCOUNTER StatExitMonitor;
1023 STAMCOUNTER StatExitLmsw;
1024 STAMCOUNTER StatExitIOWrite;
1025 STAMCOUNTER StatExitIORead;
1026 STAMCOUNTER StatExitIOStringWrite;
1027 STAMCOUNTER StatExitIOStringRead;
1028 STAMCOUNTER StatExitIntWindow;
1029 STAMCOUNTER StatExitExtInt;
1030 STAMCOUNTER StatExitHostNmiInGC;
1031 STAMCOUNTER StatExitPreemptTimer;
1032 STAMCOUNTER StatExitTprBelowThreshold;
1033 STAMCOUNTER StatExitTaskSwitch;
1034 STAMCOUNTER StatExitMtf;
1035 STAMCOUNTER StatExitApicAccess;
1036 STAMCOUNTER StatPendingHostIrq;
1037
1038 STAMCOUNTER StatFlushPage;
1039 STAMCOUNTER StatFlushPageManual;
1040 STAMCOUNTER StatFlushPhysPageManual;
1041 STAMCOUNTER StatFlushTlb;
1042 STAMCOUNTER StatFlushTlbManual;
1043 STAMCOUNTER StatFlushTlbWorldSwitch;
1044 STAMCOUNTER StatNoFlushTlbWorldSwitch;
1045 STAMCOUNTER StatFlushEntire;
1046 STAMCOUNTER StatFlushAsid;
1047 STAMCOUNTER StatFlushNestedPaging;
1048 STAMCOUNTER StatFlushTlbInvlpgVirt;
1049 STAMCOUNTER StatFlushTlbInvlpgPhys;
1050 STAMCOUNTER StatTlbShootdown;
1051 STAMCOUNTER StatTlbShootdownFlush;
1052
1053 STAMCOUNTER StatSwitchTprMaskedIrq;
1054 STAMCOUNTER StatSwitchGuestIrq;
1055 STAMCOUNTER StatSwitchHmToR3FF;
1056 STAMCOUNTER StatSwitchExitToR3;
1057 STAMCOUNTER StatSwitchLongJmpToR3;
1058 STAMCOUNTER StatSwitchMaxResumeLoops;
1059 STAMCOUNTER StatSwitchHltToR3;
1060 STAMCOUNTER StatSwitchApicAccessToR3;
1061 STAMCOUNTER StatSwitchPreempt;
1062 STAMCOUNTER StatSwitchPreemptExportHostState;
1063
1064 STAMCOUNTER StatTscParavirt;
1065 STAMCOUNTER StatTscOffset;
1066 STAMCOUNTER StatTscIntercept;
1067
1068 STAMCOUNTER StatExitReasonNpf;
1069 STAMCOUNTER StatDRxArmed;
1070 STAMCOUNTER StatDRxContextSwitch;
1071 STAMCOUNTER StatDRxIoCheck;
1072
1073 STAMCOUNTER StatExportMinimal;
1074 STAMCOUNTER StatExportFull;
1075 STAMCOUNTER StatLoadGuestFpu;
1076
1077 STAMCOUNTER StatVmxCheckBadRmSelBase;
1078 STAMCOUNTER StatVmxCheckBadRmSelLimit;
1079 STAMCOUNTER StatVmxCheckRmOk;
1080
1081 STAMCOUNTER StatVmxCheckBadSel;
1082 STAMCOUNTER StatVmxCheckBadRpl;
1083 STAMCOUNTER StatVmxCheckBadLdt;
1084 STAMCOUNTER StatVmxCheckBadTr;
1085 STAMCOUNTER StatVmxCheckPmOk;
1086
1087 STAMCOUNTER StatNestedExitReasonNpf;
1088
1089#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1090 STAMCOUNTER StatFpu64SwitchBack;
1091 STAMCOUNTER StatDebug64SwitchBack;
1092#endif
1093
1094#ifdef VBOX_WITH_STATISTICS
1095 R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
1096 R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
1097 R3PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqs;
1098 R0PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqsR0;
1099 R3PTRTYPE(PSTAMCOUNTER) paStatNestedExitReason;
1100 R0PTRTYPE(PSTAMCOUNTER) paStatNestedExitReasonR0;
1101#endif
1102#ifdef HM_PROFILE_EXIT_DISPATCH
1103 STAMPROFILEADV StatExitDispatch;
1104#endif
1105} HMCPU;
1106/** Pointer to HM VMCPU instance data. */
1107typedef HMCPU *PHMCPU;
1108AssertCompileMemberAlignment(HMCPU, cWorldSwitchExits, 4);
1109AssertCompileMemberAlignment(HMCPU, fCtxChanged, 8);
1110AssertCompileMemberAlignment(HMCPU, vmx, 8);
1111AssertCompileMemberAlignment(HMCPU, svm, 8);
1112AssertCompileMemberAlignment(HMCPU, Event, 8);
1113
1114#ifdef IN_RING0
1115VMMR0_INT_DECL(PHMGLOBALCPUINFO) hmR0GetCurrentCpu(void);
1116VMMR0_INT_DECL(int) hmR0EnterCpu(PVMCPU pVCpu);
1117
1118# ifdef VBOX_STRICT
1119VMMR0_INT_DECL(void) hmR0DumpRegs(PVMCPU pVCpu, PCPUMCTX pCtx);
1120VMMR0_INT_DECL(void) hmR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg);
1121# endif
1122
1123# ifdef VBOX_WITH_KERNEL_USING_XMM
1124DECLASM(int) hmR0VMXStartVMWrapXMM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu, PFNHMVMXSTARTVM pfnStartVM);
1125DECLASM(int) hmR0SVMRunWrapXMM(RTHCPHYS pVmcbHostPhys, RTHCPHYS pVmcbPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu, PFNHMSVMVMRUN pfnVMRun);
1126# endif
1127#endif /* IN_RING0 */
1128
1129int hmSvmEmulateMovTpr(PVMCPU pVCpu);
1130
1131/** @} */
1132
1133RT_C_DECLS_END
1134
1135#endif
1136
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