HMInternal.h@ 74074

Last change on this file since 74074 was 73606, checked in by vboxsync, 6 years ago

VMM: Nested VMX: bugref:9180 Various bits:

IEM: Started VMXON, VMXOFF implementation, use IEM_OPCODE_GET_NEXT_RM.
IEM: Fixed INVPCID C impl, removed unused IEMExecDecodedInvpcid.
IEM: Updated iemCImpl_load_CrX to check for CR0/CR4 fixed bits in VMX.
IEM: Update offModRm to reset/re-initialize where needed.
CPUM: Added VMX root, non-root mode and other bits and updated a few places where they're used.
HM: Started adding fine-grained VMX instruction failure diagnostics.
HM: Made VM instruction error an enum.
HM: Added HMVMXAll.cpp for all context VMX code.
Ensure building with VBOX_WITH_NESTED_HWVIRT_[SVM|VMX] does the right thing based on host CPU.
CPUM: Added dumping of nested-VMX CPUMCTX state.
HMVMXR0: Added memory operand decoding.
HMVMXR0: VMX instr. privilege checks (CR0/CR4 read shadows are not consulted, so we need to do them)
HM: Added some more bit-field representaions.
Recompiler: Refuse to run when in nested-VMX guest code.

Property svn:eol-style set to native
Property svn:keywords set to Id Revision

File size: 45.2 KB

Line
1	/* $Id: HMInternal.h 73606 2018-08-10 07:38:56Z vboxsync $ */
2	/** @file
3	* HM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef ___HMInternal_h
19	#define ___HMInternal_h
20
21	#include <VBox/cdefs.h>
22	#include <VBox/types.h>
23	#include <VBox/vmm/stam.h>
24	#include <VBox/dis.h>
25	#include <VBox/vmm/hm.h>
26	#include <VBox/vmm/hm_vmx.h>
27	#include <VBox/vmm/hm_svm.h>
28	#include <VBox/vmm/pgm.h>
29	#include <VBox/vmm/cpum.h>
30	#include <VBox/vmm/trpm.h>
31	#include <iprt/memobj.h>
32	#include <iprt/cpuset.h>
33	#include <iprt/mp.h>
34	#include <iprt/avl.h>
35	#include <iprt/string.h>
36
37	#if HC_ARCH_BITS == 32 && defined(RT_OS_DARWIN)
38	# error "32-bit darwin is no longer supported. Go back to 4.3 or earlier!"
39	#endif
40
41	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_64_BITS_GUESTS)
42	/* Enable 64 bits guest support. */
43	# define VBOX_ENABLE_64_BITS_GUESTS
44	#endif
45
46	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
47	# define VMX_USE_CACHED_VMCS_ACCESSES
48	#endif
49
50	/** @def HM_PROFILE_EXIT_DISPATCH
51	* Enables profiling of the VM exit handler dispatching. */
52	#if 0 \|\| defined(DOXYGEN_RUNNING)
53	# define HM_PROFILE_EXIT_DISPATCH
54	#endif
55
56	RT_C_DECLS_BEGIN
57
58
59	/** @defgroup grp_hm_int Internal
60	* @ingroup grp_hm
61	* @internal
62	* @{
63	*/
64
65	/** @name HM_CHANGED_XXX
66	* HM CPU-context changed flags.
67	*
68	* These flags are used to keep track of which registers and state has been
69	* modified since they were imported back into the guest-CPU context.
70	*
71	* @{
72	*/
73	#define HM_CHANGED_HOST_CONTEXT UINT64_C(0x0000000000000001)
74	#define HM_CHANGED_GUEST_RIP UINT64_C(0x0000000000000004)
75	#define HM_CHANGED_GUEST_RFLAGS UINT64_C(0x0000000000000008)
76
77	#define HM_CHANGED_GUEST_RAX UINT64_C(0x0000000000000010)
78	#define HM_CHANGED_GUEST_RCX UINT64_C(0x0000000000000020)
79	#define HM_CHANGED_GUEST_RDX UINT64_C(0x0000000000000040)
80	#define HM_CHANGED_GUEST_RBX UINT64_C(0x0000000000000080)
81	#define HM_CHANGED_GUEST_RSP UINT64_C(0x0000000000000100)
82	#define HM_CHANGED_GUEST_RBP UINT64_C(0x0000000000000200)
83	#define HM_CHANGED_GUEST_RSI UINT64_C(0x0000000000000400)
84	#define HM_CHANGED_GUEST_RDI UINT64_C(0x0000000000000800)
85	#define HM_CHANGED_GUEST_R8_R15 UINT64_C(0x0000000000001000)
86	#define HM_CHANGED_GUEST_GPRS_MASK UINT64_C(0x0000000000001ff0)
87
88	#define HM_CHANGED_GUEST_ES UINT64_C(0x0000000000002000)
89	#define HM_CHANGED_GUEST_CS UINT64_C(0x0000000000004000)
90	#define HM_CHANGED_GUEST_SS UINT64_C(0x0000000000008000)
91	#define HM_CHANGED_GUEST_DS UINT64_C(0x0000000000010000)
92	#define HM_CHANGED_GUEST_FS UINT64_C(0x0000000000020000)
93	#define HM_CHANGED_GUEST_GS UINT64_C(0x0000000000040000)
94	#define HM_CHANGED_GUEST_SREG_MASK UINT64_C(0x000000000007e000)
95
96	#define HM_CHANGED_GUEST_GDTR UINT64_C(0x0000000000080000)
97	#define HM_CHANGED_GUEST_IDTR UINT64_C(0x0000000000100000)
98	#define HM_CHANGED_GUEST_LDTR UINT64_C(0x0000000000200000)
99	#define HM_CHANGED_GUEST_TR UINT64_C(0x0000000000400000)
100	#define HM_CHANGED_GUEST_TABLE_MASK UINT64_C(0x0000000000780000)
101
102	#define HM_CHANGED_GUEST_CR0 UINT64_C(0x0000000000800000)
103	#define HM_CHANGED_GUEST_CR2 UINT64_C(0x0000000001000000)
104	#define HM_CHANGED_GUEST_CR3 UINT64_C(0x0000000002000000)
105	#define HM_CHANGED_GUEST_CR4 UINT64_C(0x0000000004000000)
106	#define HM_CHANGED_GUEST_CR_MASK UINT64_C(0x0000000007800000)
107
108	#define HM_CHANGED_GUEST_APIC_TPR UINT64_C(0x0000000008000000)
109	#define HM_CHANGED_GUEST_EFER_MSR UINT64_C(0x0000000010000000)
110
111	#define HM_CHANGED_GUEST_DR0_DR3 UINT64_C(0x0000000020000000)
112	#define HM_CHANGED_GUEST_DR6 UINT64_C(0x0000000040000000)
113	#define HM_CHANGED_GUEST_DR7 UINT64_C(0x0000000080000000)
114	#define HM_CHANGED_GUEST_DR_MASK UINT64_C(0x00000000e0000000)
115
116	#define HM_CHANGED_GUEST_X87 UINT64_C(0x0000000100000000)
117	#define HM_CHANGED_GUEST_SSE_AVX UINT64_C(0x0000000200000000)
118	#define HM_CHANGED_GUEST_OTHER_XSAVE UINT64_C(0x0000000400000000)
119	#define HM_CHANGED_GUEST_XCRx UINT64_C(0x0000000800000000)
120
121	#define HM_CHANGED_GUEST_KERNEL_GS_BASE UINT64_C(0x0000001000000000)
122	#define HM_CHANGED_GUEST_SYSCALL_MSRS UINT64_C(0x0000002000000000)
123	#define HM_CHANGED_GUEST_SYSENTER_CS_MSR UINT64_C(0x0000004000000000)
124	#define HM_CHANGED_GUEST_SYSENTER_EIP_MSR UINT64_C(0x0000008000000000)
125	#define HM_CHANGED_GUEST_SYSENTER_ESP_MSR UINT64_C(0x0000010000000000)
126	#define HM_CHANGED_GUEST_SYSENTER_MSR_MASK UINT64_C(0x000001c000000000)
127	#define HM_CHANGED_GUEST_TSC_AUX UINT64_C(0x0000020000000000)
128	#define HM_CHANGED_GUEST_OTHER_MSRS UINT64_C(0x0000040000000000)
129	#define HM_CHANGED_GUEST_ALL_MSRS ( HM_CHANGED_GUEST_EFER \
130	\| HM_CHANGED_GUEST_KERNEL_GS_BASE \
131	\| HM_CHANGED_GUEST_SYSCALL_MSRS \
132	\| HM_CHANGED_GUEST_SYSENTER_MSR_MASK \
133	\| HM_CHANGED_GUEST_TSC_AUX \
134	\| HM_CHANGED_GUEST_OTHER_MSRS)
135
136	#define HM_CHANGED_GUEST_HWVIRT UINT64_C(0x0000080000000000)
137	#define HM_CHANGED_GUEST_MASK UINT64_C(0x00000ffffffffffc)
138
139	#define HM_CHANGED_KEEPER_STATE_MASK UINT64_C(0xffff000000000000)
140
141	#define HM_CHANGED_VMX_GUEST_XCPT_INTERCEPTS UINT64_C(0x0001000000000000)
142	#define HM_CHANGED_VMX_GUEST_AUTO_MSRS UINT64_C(0x0002000000000000)
143	#define HM_CHANGED_VMX_GUEST_LAZY_MSRS UINT64_C(0x0004000000000000)
144	#define HM_CHANGED_VMX_ENTRY_CTLS UINT64_C(0x0008000000000000)
145	#define HM_CHANGED_VMX_EXIT_CTLS UINT64_C(0x0010000000000000)
146	#define HM_CHANGED_VMX_MASK UINT64_C(0x001f000000000000)
147	#define HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE ( HM_CHANGED_GUEST_DR_MASK \
148	\| HM_CHANGED_VMX_GUEST_LAZY_MSRS)
149
150	#define HM_CHANGED_SVM_GUEST_XCPT_INTERCEPTS UINT64_C(0x0001000000000000)
151	#define HM_CHANGED_SVM_MASK UINT64_C(0x0001000000000000)
152	#define HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE HM_CHANGED_GUEST_DR_MASK
153
154	#define HM_CHANGED_ALL_GUEST ( HM_CHANGED_GUEST_MASK \
155	\| HM_CHANGED_KEEPER_STATE_MASK)
156
157	/** Mask of what state might have changed when IEM raised an exception.
158	* This is a based on IEM_CPUMCTX_EXTRN_XCPT_MASK. */
159	#define HM_CHANGED_RAISED_XCPT_MASK ( HM_CHANGED_GUEST_GPRS_MASK \
160	\| HM_CHANGED_GUEST_RIP \
161	\| HM_CHANGED_GUEST_RFLAGS \
162	\| HM_CHANGED_GUEST_SS \
163	\| HM_CHANGED_GUEST_CS \
164	\| HM_CHANGED_GUEST_CR0 \
165	\| HM_CHANGED_GUEST_CR3 \
166	\| HM_CHANGED_GUEST_CR4 \
167	\| HM_CHANGED_GUEST_APIC_TPR \
168	\| HM_CHANGED_GUEST_EFER_MSR \
169	\| HM_CHANGED_GUEST_DR7 \
170	\| HM_CHANGED_GUEST_CR2 \
171	\| HM_CHANGED_GUEST_SREG_MASK \
172	\| HM_CHANGED_GUEST_TABLE_MASK)
173
174	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
175	/** Mask of what state might have changed when \#VMEXIT is emulated. */
176	# define HM_CHANGED_SVM_VMEXIT_MASK ( HM_CHANGED_GUEST_RSP \
177	\| HM_CHANGED_GUEST_RAX \
178	\| HM_CHANGED_GUEST_RIP \
179	\| HM_CHANGED_GUEST_RFLAGS \
180	\| HM_CHANGED_GUEST_CS \
181	\| HM_CHANGED_GUEST_SS \
182	\| HM_CHANGED_GUEST_DS \
183	\| HM_CHANGED_GUEST_ES \
184	\| HM_CHANGED_GUEST_GDTR \
185	\| HM_CHANGED_GUEST_IDTR \
186	\| HM_CHANGED_GUEST_CR_MASK \
187	\| HM_CHANGED_GUEST_EFER_MSR \
188	\| HM_CHANGED_GUEST_DR6 \
189	\| HM_CHANGED_GUEST_DR7 \
190	\| HM_CHANGED_GUEST_OTHER_MSRS \
191	\| HM_CHANGED_GUEST_HWVIRT \
192	\| HM_CHANGED_SVM_MASK \
193	\| HM_CHANGED_GUEST_APIC_TPR)
194
195	/** Mask of what state might have changed when \#VMEXIT is emulated. */
196	# define HM_CHANGED_SVM_VMRUN_MASK HM_CHANGED_SVM_VMEXIT_MASK
197	#endif
198	/** @} */
199
200	/** Maximum number of exit reason statistics counters. */
201	#define MAX_EXITREASON_STAT 0x100
202	#define MASK_EXITREASON_STAT 0xff
203	#define MASK_INJECT_IRQ_STAT 0xff
204
205	/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
206	#define HM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
207	/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
208	#define HM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2 * PAGE_SIZE + 1)
209	/** Total guest mapped memory needed. */
210	#define HM_VTX_TOTAL_DEVHEAP_MEM (HM_EPT_IDENTITY_PG_TABLE_SIZE + HM_VTX_TSS_SIZE)
211
212
213	/** @name Macros for enabling and disabling preemption.
214	* These are really just for hiding the RTTHREADPREEMPTSTATE and asserting that
215	* preemption has already been disabled when there is no context hook.
216	* @{ */
217	#ifdef VBOX_STRICT
218	# define HM_DISABLE_PREEMPT(a_pVCpu) \
219	RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
220	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD) \|\| VMMR0ThreadCtxHookIsEnabled((a_pVCpu))); \
221	RTThreadPreemptDisable(&PreemptStateInternal)
222	#else
223	# define HM_DISABLE_PREEMPT(a_pVCpu) \
224	RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
225	RTThreadPreemptDisable(&PreemptStateInternal)
226	#endif /* VBOX_STRICT */
227	#define HM_RESTORE_PREEMPT() do { RTThreadPreemptRestore(&PreemptStateInternal); } while(0)
228	/** @} */
229
230
231	/** @name HM saved state versions.
232	* @{
233	*/
234	#define HM_SAVED_STATE_VERSION HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT
235	#define HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT 6
236	#define HM_SAVED_STATE_VERSION_TPR_PATCHING 5
237	#define HM_SAVED_STATE_VERSION_NO_TPR_PATCHING 4
238	#define HM_SAVED_STATE_VERSION_2_0_X 3
239	/** @} */
240
241
242	/**
243	* Global per-cpu information. (host)
244	*/
245	typedef struct HMGLOBALCPUINFO
246	{
247	/** The CPU ID. */
248	RTCPUID idCpu;
249	/** The VM_HSAVE_AREA (AMD-V) / VMXON region (Intel) memory backing. */
250	RTR0MEMOBJ hMemObj;
251	/** The physical address of the first page in hMemObj (it's a
252	* physcially contigous allocation if it spans multiple pages). */
253	RTHCPHYS HCPhysMemObj;
254	/** The address of the memory (for pfnEnable). */
255	void *pvMemObj;
256	/** Current ASID (AMD-V) / VPID (Intel). */
257	uint32_t uCurrentAsid;
258	/** TLB flush count. */
259	uint32_t cTlbFlushes;
260	/** Whether to flush each new ASID/VPID before use. */
261	bool fFlushAsidBeforeUse;
262	/** Configured for VT-x or AMD-V. */
263	bool fConfigured;
264	/** Set if the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active. */
265	bool fIgnoreAMDVInUseError;
266	/** In use by our code. (for power suspend) */
267	bool volatile fInUse;
268	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
269	/** Nested-guest union (put data common to SVM/VMX outside the union). */
270	union
271	{
272	/** Nested-guest SVM data. */
273	struct
274	{
275	/** The active nested-guest MSR permission bitmap memory backing. */
276	RTR0MEMOBJ hNstGstMsrpm;
277	/** The physical address of the first page in hNstGstMsrpm (physcially
278	* contiguous allocation). */
279	RTHCPHYS HCPhysNstGstMsrpm;
280	/** The address of the active nested-guest MSRPM. */
281	void *pvNstGstMsrpm;
282	} svm;
283	/** @todo Nested-VMX. */
284	} n;
285	#endif
286	} HMGLOBALCPUINFO;
287	/** Pointer to the per-cpu global information. */
288	typedef HMGLOBALCPUINFO *PHMGLOBALCPUINFO;
289
290	typedef enum
291	{
292	HMPENDINGIO_INVALID = 0,
293	HMPENDINGIO_PORT_READ,
294	/* not implemented: HMPENDINGIO_STRING_READ, */
295	/* not implemented: HMPENDINGIO_STRING_WRITE, */
296	/** The usual 32-bit paranoia. */
297	HMPENDINGIO_32BIT_HACK = 0x7fffffff
298	} HMPENDINGIO;
299
300
301	typedef enum
302	{
303	HMTPRINSTR_INVALID,
304	HMTPRINSTR_READ,
305	HMTPRINSTR_READ_SHR4,
306	HMTPRINSTR_WRITE_REG,
307	HMTPRINSTR_WRITE_IMM,
308	HMTPRINSTR_JUMP_REPLACEMENT,
309	/** The usual 32-bit paranoia. */
310	HMTPRINSTR_32BIT_HACK = 0x7fffffff
311	} HMTPRINSTR;
312
313	typedef struct
314	{
315	/** The key is the address of patched instruction. (32 bits GC ptr) */
316	AVLOU32NODECORE Core;
317	/** Original opcode. */
318	uint8_t aOpcode[16];
319	/** Instruction size. */
320	uint32_t cbOp;
321	/** Replacement opcode. */
322	uint8_t aNewOpcode[16];
323	/** Replacement instruction size. */
324	uint32_t cbNewOp;
325	/** Instruction type. */
326	HMTPRINSTR enmType;
327	/** Source operand. */
328	uint32_t uSrcOperand;
329	/** Destination operand. */
330	uint32_t uDstOperand;
331	/** Number of times the instruction caused a fault. */
332	uint32_t cFaults;
333	/** Patch address of the jump replacement. */
334	RTGCPTR32 pJumpTarget;
335	} HMTPRPATCH;
336	/** Pointer to HMTPRPATCH. */
337	typedef HMTPRPATCH *PHMTPRPATCH;
338	/** Pointer to a const HMTPRPATCH. */
339	typedef const HMTPRPATCH *PCHMTPRPATCH;
340
341
342	/**
343	* Makes a HMEXITSTAT::uKey value from a program counter and an exit code.
344	*
345	* @returns 64-bit key
346	* @param a_uPC The RIP + CS.BASE value of the exit.
347	* @param a_uExit The exit code.
348	* @todo Add CPL?
349	*/
350	#define HMEXITSTAT_MAKE_KEY(a_uPC, a_uExit) (((a_uPC) & UINT64_C(0x0000ffffffffffff)) \| (uint64_t)(a_uExit) << 48)
351
352	typedef struct HMEXITINFO
353	{
354	/** See HMEXITSTAT_MAKE_KEY(). */
355	uint64_t uKey;
356	/** Number of recent hits (depreciates with time). */
357	uint32_t volatile cHits;
358	/** The age + lock. */
359	uint16_t volatile uAge;
360	/** Action or action table index. */
361	uint16_t iAction;
362	} HMEXITINFO;
363	AssertCompileSize(HMEXITINFO, 16); /* Lots of these guys, so don't add any unnecessary stuff! */
364
365	typedef struct HMEXITHISTORY
366	{
367	/** The exit timestamp. */
368	uint64_t uTscExit;
369	/** The index of the corresponding HMEXITINFO entry.
370	* UINT32_MAX if none (too many collisions, race, whatever). */
371	uint32_t iExitInfo;
372	/** Figure out later, needed for padding now. */
373	uint32_t uSomeClueOrSomething;
374	} HMEXITHISTORY;
375
376	/**
377	* Switcher function, HC to the special 64-bit RC.
378	*
379	* @param pVM The cross context VM structure.
380	* @param offCpumVCpu Offset from pVM->cpum to pVM->aCpus[idCpu].cpum.
381	* @returns Return code indicating the action to take.
382	*/
383	typedef DECLCALLBACK(int) FNHMSWITCHERHC(PVM pVM, uint32_t offCpumVCpu);
384	/** Pointer to switcher function. */
385	typedef FNHMSWITCHERHC *PFNHMSWITCHERHC;
386
387	/**
388	* HM VM Instance data.
389	* Changes to this must checked against the padding of the hm union in VM!
390	*/
391	typedef struct HM
392	{
393	/** Set when we've initialized VMX or SVM. */
394	bool fInitialized;
395	/** Set if nested paging is enabled. */
396	bool fNestedPaging;
397	/** Set if nested paging is allowed. */
398	bool fAllowNestedPaging;
399	/** Set if large pages are enabled (requires nested paging). */
400	bool fLargePages;
401	/** Set if we can support 64-bit guests or not. */
402	bool fAllow64BitGuests;
403	/** Set when TPR patching is allowed. */
404	bool fTprPatchingAllowed;
405	/** Set when we initialize VT-x or AMD-V once for all CPUs. */
406	bool fGlobalInit;
407	/** Set when TPR patching is active. */
408	bool fTPRPatchingActive;
409	/** Set when the debug facility has breakpoints/events enabled that requires
410	* us to use the debug execution loop in ring-0. */
411	bool fUseDebugLoop;
412	/** Set if hardware APIC virtualization is enabled. */
413	bool fVirtApicRegs;
414	/** Set if posted interrupt processing is enabled. */
415	bool fPostedIntrs;
416	/** Set if indirect branch prediction barrier on VM exit. */
417	bool fIbpbOnVmExit;
418	/** Set if indirect branch prediction barrier on VM entry. */
419	bool fIbpbOnVmEntry;
420	/** Set if host manages speculation control settings. */
421	bool fSpecCtrlByHost;
422	/** Explicit padding. */
423	bool afPadding[2];
424
425	/** Maximum ASID allowed. */
426	uint32_t uMaxAsid;
427	/** The maximum number of resumes loops allowed in ring-0 (safety precaution).
428	* This number is set much higher when RTThreadPreemptIsPending is reliable. */
429	uint32_t cMaxResumeLoops;
430
431	/** Host kernel flags that HM might need to know (SUPKERNELFEATURES_XXX). */
432	uint32_t fHostKernelFeatures;
433
434	/** Size of the guest patch memory block. */
435	uint32_t cbGuestPatchMem;
436	/** Guest allocated memory for patching purposes. */
437	RTGCPTR pGuestPatchMem;
438	/** Current free pointer inside the patch block. */
439	RTGCPTR pFreeGuestPatchMem;
440
441	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
442	/** 32 to 64 bits switcher entrypoint. */
443	R0PTRTYPE(PFNHMSWITCHERHC) pfnHost32ToGuest64R0;
444	RTR0PTR pvR0Alignment0;
445	#endif
446
447	struct
448	{
449	/** Set by the ring-0 side of HM to indicate VMX is supported by the
450	* CPU. */
451	bool fSupported;
452	/** Set when we've enabled VMX. */
453	bool fEnabled;
454	/** Set if VPID is supported. */
455	bool fVpid;
456	/** Set if VT-x VPID is allowed. */
457	bool fAllowVpid;
458	/** Set if unrestricted guest execution is in use (real and protected mode without paging). */
459	bool fUnrestrictedGuest;
460	/** Set if unrestricted guest execution is allowed to be used. */
461	bool fAllowUnrestricted;
462	/** Set if the preemption timer is in use or not. */
463	bool fUsePreemptTimer;
464	/** The shift mask employed by the VMX-Preemption timer. */
465	uint8_t cPreemptTimerShift;
466
467	/** Virtual address of the TSS page used for real mode emulation. */
468	R3PTRTYPE(PVBOXTSS) pRealModeTSS;
469	/** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
470	R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
471
472	/** Physical address of the APIC-access page. */
473	RTHCPHYS HCPhysApicAccess;
474	/** R0 memory object for the APIC-access page. */
475	RTR0MEMOBJ hMemObjApicAccess;
476	/** Virtual address of the APIC-access page. */
477	R0PTRTYPE(uint8_t *) pbApicAccess;
478
479	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
480	RTHCPHYS HCPhysScratch;
481	RTR0MEMOBJ hMemObjScratch;
482	R0PTRTYPE(uint8_t *) pbScratch;
483	#endif
484
485	/** Tagged-TLB flush type. */
486	VMXTLBFLUSHTYPE enmTlbFlushType;
487	/** Flush type to use for INVEPT. */
488	VMXTLBFLUSHEPT enmTlbFlushEpt;
489	/** Flush type to use for INVVPID. */
490	VMXTLBFLUSHVPID enmTlbFlushVpid;
491
492	/** Pause-loop exiting (PLE) gap in ticks. */
493	uint32_t cPleGapTicks;
494	/** Pause-loop exiting (PLE) window in ticks. */
495	uint32_t cPleWindowTicks;
496	uint32_t u32Alignment0;
497
498	/** Host CR4 value (set by ring-0 VMX init) */
499	uint64_t u64HostCr4;
500	/** Host SMM monitor control (set by ring-0 VMX init) */
501	uint64_t u64HostSmmMonitorCtl;
502	/** Host EFER value (set by ring-0 VMX init) */
503	uint64_t u64HostEfer;
504	/** Whether the CPU supports VMCS fields for swapping EFER. */
505	bool fSupportsVmcsEfer;
506	uint8_t u8Alignment2[7];
507
508	/** VMX MSR values. */
509	VMXMSRS Msrs;
510
511	/** Host-physical address for a failing VMXON instruction. */
512	RTHCPHYS HCPhysVmxEnableError;
513	} vmx;
514
515	struct
516	{
517	/** Set by the ring-0 side of HM to indicate SVM is supported by the
518	* CPU. */
519	bool fSupported;
520	/** Set when we've enabled SVM. */
521	bool fEnabled;
522	/** Set if erratum 170 affects the AMD cpu. */
523	bool fAlwaysFlushTLB;
524	/** Set when the hack to ignore VERR_SVM_IN_USE is active. */
525	bool fIgnoreInUseError;
526	/** Whether to use virtualized VMSAVE/VMLOAD feature. */
527	bool fVirtVmsaveVmload;
528	/** Whether to use virtual GIF feature. */
529	bool fVGif;
530	uint8_t u8Alignment0[2];
531
532	/** Physical address of the IO bitmap (12kb). */
533	RTHCPHYS HCPhysIOBitmap;
534	/** R0 memory object for the IO bitmap (12kb). */
535	RTR0MEMOBJ hMemObjIOBitmap;
536	/** Virtual address of the IO bitmap. */
537	R0PTRTYPE(void *) pvIOBitmap;
538
539	/* HWCR MSR (for diagnostics) */
540	uint64_t u64MsrHwcr;
541
542	/** SVM revision. */
543	uint32_t u32Rev;
544	/** SVM feature bits from cpuid 0x8000000a */
545	uint32_t u32Features;
546
547	/** Pause filter counter. */
548	uint16_t cPauseFilter;
549	/** Pause filter treshold in ticks. */
550	uint16_t cPauseFilterThresholdTicks;
551	uint32_t u32Alignment0;
552	} svm;
553
554	/**
555	* AVL tree with all patches (active or disabled) sorted by guest instruction
556	* address.
557	*/
558	AVLOU32TREE PatchTree;
559	uint32_t cPatches;
560	HMTPRPATCH aPatches[64];
561
562	/** Last recorded error code during HM ring-0 init. */
563	int32_t rcInit;
564
565	/** HMR0Init was run */
566	bool fHMR0Init;
567	bool u8Alignment1[3];
568
569	STAMCOUNTER StatTprPatchSuccess;
570	STAMCOUNTER StatTprPatchFailure;
571	STAMCOUNTER StatTprReplaceSuccessCr8;
572	STAMCOUNTER StatTprReplaceSuccessVmc;
573	STAMCOUNTER StatTprReplaceFailure;
574	} HM;
575	/** Pointer to HM VM instance data. */
576	typedef HM *PHM;
577
578	AssertCompileMemberAlignment(HM, StatTprPatchSuccess, 8);
579
580	/* Maximum number of cached entries. */
581	#define VMCSCACHE_MAX_ENTRY 128
582
583	/**
584	* Structure for storing read and write VMCS actions.
585	*/
586	typedef struct VMCSCACHE
587	{
588	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
589	/* Magic marker for searching in crash dumps. */
590	uint8_t aMagic[16];
591	uint64_t uMagic;
592	uint64_t u64TimeEntry;
593	uint64_t u64TimeSwitch;
594	uint64_t cResume;
595	uint64_t interPD;
596	uint64_t pSwitcher;
597	uint32_t uPos;
598	uint32_t idCpu;
599	#endif
600	/* CR2 is saved here for EPT syncing. */
601	uint64_t cr2;
602	struct
603	{
604	uint32_t cValidEntries;
605	uint32_t uAlignment;
606	uint32_t aField[VMCSCACHE_MAX_ENTRY];
607	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
608	} Write;
609	struct
610	{
611	uint32_t cValidEntries;
612	uint32_t uAlignment;
613	uint32_t aField[VMCSCACHE_MAX_ENTRY];
614	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
615	} Read;
616	#ifdef VBOX_STRICT
617	struct
618	{
619	RTHCPHYS HCPhysCpuPage;
620	RTHCPHYS HCPhysVmcs;
621	RTGCPTR pCache;
622	RTGCPTR pCtx;
623	} TestIn;
624	struct
625	{
626	RTHCPHYS HCPhysVmcs;
627	RTGCPTR pCache;
628	RTGCPTR pCtx;
629	uint64_t eflags;
630	uint64_t cr8;
631	} TestOut;
632	struct
633	{
634	uint64_t param1;
635	uint64_t param2;
636	uint64_t param3;
637	uint64_t param4;
638	} ScratchPad;
639	#endif
640	} VMCSCACHE;
641	/** Pointer to VMCSCACHE. */
642	typedef VMCSCACHE *PVMCSCACHE;
643	AssertCompileSizeAlignment(VMCSCACHE, 8);
644
645	/**
646	* VMX StartVM function.
647	*
648	* @returns VBox status code (no informational stuff).
649	* @param fResume Whether to use VMRESUME (true) or VMLAUNCH (false).
650	* @param pCtx The CPU register context.
651	* @param pCache The VMCS cache.
652	* @param pVM Pointer to the cross context VM structure.
653	* @param pVCpu Pointer to the cross context per-CPU structure.
654	*/
655	typedef DECLCALLBACK(int) FNHMVMXSTARTVM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);
656	/** Pointer to a VMX StartVM function. */
657	typedef R0PTRTYPE(FNHMVMXSTARTVM *) PFNHMVMXSTARTVM;
658
659	/** SVM VMRun function. */
660	typedef DECLCALLBACK(int) FNHMSVMVMRUN(RTHCPHYS pVmcbHostPhys, RTHCPHYS pVmcbPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu);
661	/** Pointer to a SVM VMRun function. */
662	typedef R0PTRTYPE(FNHMSVMVMRUN *) PFNHMSVMVMRUN;
663
664	/**
665	* HM VMCPU Instance data.
666	*
667	* Note! If you change members of this struct, make sure to check if the
668	* assembly counterpart in HMInternal.mac needs to be updated as well.
669	*/
670	typedef struct HMCPU
671	{
672	/** Set when the TLB has been checked until we return from the world switch. */
673	bool volatile fCheckedTLBFlush;
674	/** Set if we need to flush the TLB during the world switch. */
675	bool fForceTLBFlush;
676	/** Set when we're using VT-x or AMD-V at that moment. */
677	bool fActive;
678	/** Whether we've completed the inner HM leave function. */
679	bool fLeaveDone;
680	/** Whether we're using the hyper DR7 or guest DR7. */
681	bool fUsingHyperDR7;
682	/** Set if XCR0 needs to be saved/restored when entering/exiting guest code
683	* execution. */
684	bool fLoadSaveGuestXcr0;
685
686	/** Whether we should use the debug loop because of single stepping or special
687	* debug breakpoints / events are armed. */
688	bool fUseDebugLoop;
689	/** Whether we are currently executing in the debug loop.
690	* Mainly for assertions. */
691	bool fUsingDebugLoop;
692	/** Set if we using the debug loop and wish to intercept RDTSC. */
693	bool fDebugWantRdTscExit;
694	/** Whether we're executing a single instruction. */
695	bool fSingleInstruction;
696	/** Set if we need to clear the trap flag because of single stepping. */
697	bool fClearTrapFlag;
698
699	/** Whether \#UD needs to be intercepted (required by certain GIM providers). */
700	bool fGIMTrapXcptUD;
701	uint8_t u8Alignment0[4];
702
703	/** World switch exit counter. */
704	uint32_t volatile cWorldSwitchExits;
705	/** The last CPU we were executing code on (NIL_RTCPUID for the first time). */
706	RTCPUID idLastCpu;
707	/** TLB flush count. */
708	uint32_t cTlbFlushes;
709	/** Current ASID in use by the VM. */
710	uint32_t uCurrentAsid;
711	/** An additional error code used for some gurus. */
712	uint32_t u32HMError;
713	/** The last exit-to-ring-3 reason. */
714	int32_t rcLastExitToR3;
715	/** CPU-context changed flags (see HM_CHANGED_xxx). */
716	uint64_t fCtxChanged;
717	/** Host's TSC_AUX MSR (used when RDTSCP doesn't cause VM-exits). */
718	uint64_t u64HostTscAux;
719
720	struct
721	{
722	/** Ring 0 handlers for VT-x. */
723	PFNHMVMXSTARTVM pfnStartVM;
724	#if HC_ARCH_BITS == 32
725	uint32_t u32Alignment0;
726	#endif
727	/** Current pin-based VM-execution controls. */
728	uint32_t u32PinCtls;
729	/** Current processor-based VM-execution controls. */
730	uint32_t u32ProcCtls;
731	/** Current secondary processor-based VM-execution controls. */
732	uint32_t u32ProcCtls2;
733	/** Current VM-entry controls. */
734	uint32_t u32EntryCtls;
735	/** Current VM-exit controls. */
736	uint32_t u32ExitCtls;
737
738	/** Current CR0 mask. */
739	uint32_t u32Cr0Mask;
740	/** Current CR4 mask. */
741	uint32_t u32Cr4Mask;
742	/** Current exception bitmap. */
743	uint32_t u32XcptBitmap;
744	/** The updated-guest-state mask. */
745	uint32_t au32Alignment0[2];
746
747	/** Physical address of the VM control structure (VMCS). */
748	RTHCPHYS HCPhysVmcs;
749	/** R0 memory object for the VM control structure (VMCS). */
750	RTR0MEMOBJ hMemObjVmcs;
751	/** Virtual address of the VM control structure (VMCS). */
752	R0PTRTYPE(void *) pvVmcs;
753
754	/** Physical address of the virtual APIC page for TPR caching. */
755	RTHCPHYS HCPhysVirtApic;
756	/** Padding. */
757	R0PTRTYPE(void *) pvAlignment0;
758	/** Virtual address of the virtual APIC page for TPR caching. */
759	R0PTRTYPE(uint8_t *) pbVirtApic;
760
761	/** Physical address of the MSR bitmap. */
762	RTHCPHYS HCPhysMsrBitmap;
763	/** R0 memory object for the MSR bitmap. */
764	RTR0MEMOBJ hMemObjMsrBitmap;
765	/** Virtual address of the MSR bitmap. */
766	R0PTRTYPE(void *) pvMsrBitmap;
767
768	/** Physical address of the VM-entry MSR-load and VM-exit MSR-store area (used
769	* for guest MSRs). */
770	RTHCPHYS HCPhysGuestMsr;
771	/** R0 memory object of the VM-entry MSR-load and VM-exit MSR-store area
772	* (used for guest MSRs). */
773	RTR0MEMOBJ hMemObjGuestMsr;
774	/** Virtual address of the VM-entry MSR-load and VM-exit MSR-store area (used
775	* for guest MSRs). */
776	R0PTRTYPE(void *) pvGuestMsr;
777
778	/** Physical address of the VM-exit MSR-load area (used for host MSRs). */
779	RTHCPHYS HCPhysHostMsr;
780	/** R0 memory object for the VM-exit MSR-load area (used for host MSRs). */
781	RTR0MEMOBJ hMemObjHostMsr;
782	/** Virtual address of the VM-exit MSR-load area (used for host MSRs). */
783	R0PTRTYPE(void *) pvHostMsr;
784
785	/** Current EPTP. */
786	RTHCPHYS HCPhysEPTP;
787
788	/** Number of guest/host MSR pairs in the auto-load/store area. */
789	uint32_t cMsrs;
790	/** Whether the host MSR values are up-to-date in the auto-load/store area. */
791	bool fUpdatedHostMsrs;
792	uint8_t u8Alignment0[3];
793
794	/** Host LSTAR MSR value to restore lazily while leaving VT-x. */
795	uint64_t u64HostLStarMsr;
796	/** Host STAR MSR value to restore lazily while leaving VT-x. */
797	uint64_t u64HostStarMsr;
798	/** Host SF_MASK MSR value to restore lazily while leaving VT-x. */
799	uint64_t u64HostSFMaskMsr;
800	/** Host KernelGS-Base MSR value to restore lazily while leaving VT-x. */
801	uint64_t u64HostKernelGSBaseMsr;
802	/** A mask of which MSRs have been swapped and need restoration. */
803	uint32_t fLazyMsrs;
804	uint32_t u32Alignment2;
805
806	/** The cached APIC-base MSR used for identifying when to map the HC physical APIC-access page. */
807	uint64_t u64MsrApicBase;
808	/** Last use TSC offset value. (cached) */
809	uint64_t u64TscOffset;
810
811	/** VMCS cache. */
812	VMCSCACHE VMCSCache;
813
814	/** Real-mode emulation state. */
815	struct
816	{
817	X86DESCATTR AttrCS;
818	X86DESCATTR AttrDS;
819	X86DESCATTR AttrES;
820	X86DESCATTR AttrFS;
821	X86DESCATTR AttrGS;
822	X86DESCATTR AttrSS;
823	X86EFLAGS Eflags;
824	bool fRealOnV86Active;
825	} RealMode;
826
827	/** VT-x error-reporting (mainly for ring-3 propagation). */
828	struct
829	{
830	uint64_t u64VMCSPhys;
831	uint32_t u32VMCSRevision;
832	uint32_t u32InstrError;
833	uint32_t u32ExitReason;
834	RTCPUID idEnteredCpu;
835	RTCPUID idCurrentCpu;
836	uint32_t u32Alignment0;
837	} LastError;
838
839	/** Current state of the VMCS. */
840	uint32_t uVmcsState;
841	/** Which host-state bits to restore before being preempted. */
842	uint32_t fRestoreHostFlags;
843	/** The host-state restoration structure. */
844	VMXRESTOREHOST RestoreHost;
845
846	/** Set if guest was executing in real mode (extra checks). */
847	bool fWasInRealMode;
848	/** Set if guest switched to 64-bit mode on a 32-bit host. */
849	bool fSwitchedTo64on32;
850
851	uint8_t u8Alignment1[6];
852	} vmx;
853
854	struct
855	{
856	/** Ring 0 handlers for VT-x. */
857	PFNHMSVMVMRUN pfnVMRun;
858	#if HC_ARCH_BITS == 32
859	uint32_t u32Alignment0;
860	#endif
861
862	/** Physical address of the host VMCB which holds additional host-state. */
863	RTHCPHYS HCPhysVmcbHost;
864	/** R0 memory object for the host VMCB which holds additional host-state. */
865	RTR0MEMOBJ hMemObjVmcbHost;
866	/** Padding. */
867	R0PTRTYPE(void *) pvPadding;
868
869	/** Physical address of the guest VMCB. */
870	RTHCPHYS HCPhysVmcb;
871	/** R0 memory object for the guest VMCB. */
872	RTR0MEMOBJ hMemObjVmcb;
873	/** Pointer to the guest VMCB. */
874	R0PTRTYPE(PSVMVMCB) pVmcb;
875
876	/** Physical address of the MSR bitmap (8 KB). */
877	RTHCPHYS HCPhysMsrBitmap;
878	/** R0 memory object for the MSR bitmap (8 KB). */
879	RTR0MEMOBJ hMemObjMsrBitmap;
880	/** Pointer to the MSR bitmap. */
881	R0PTRTYPE(void *) pvMsrBitmap;
882
883	/** Whether VTPR with V_INTR_MASKING set is in effect, indicating
884	* we should check if the VTPR changed on every VM-exit. */
885	bool fSyncVTpr;
886	uint8_t u8Alignment0[7];
887
888	/** Cache of the nested-guest's VMCB fields that we modify in order to run the
889	* nested-guest using AMD-V. This will be restored on \#VMEXIT. */
890	SVMNESTEDVMCBCACHE NstGstVmcbCache;
891	} svm;
892
893	/** Event injection state. */
894	struct
895	{
896	uint32_t fPending;
897	uint32_t u32ErrCode;
898	uint32_t cbInstr;
899	uint32_t u32Padding; /*< Explicit alignment padding. /
900	uint64_t u64IntInfo;
901	RTGCUINTPTR GCPtrFaultAddress;
902	} Event;
903
904	/** The PAE PDPEs used with Nested Paging (only valid when
905	* VMCPU_FF_HM_UPDATE_PAE_PDPES is set). */
906	X86PDPE aPdpes[4];
907
908	/** Current shadow paging mode for updating CR4. */
909	PGMMODE enmShadowMode;
910
911	/** The CPU ID of the CPU currently owning the VMCS. Set in
912	* HMR0Enter and cleared in HMR0Leave. */
913	RTCPUID idEnteredCpu;
914
915	/** For saving stack space, the disassembler state is allocated here instead of
916	* on the stack. */
917	DISCPUSTATE DisState;
918
919	STAMPROFILEADV StatEntry;
920	STAMPROFILEADV StatPreExit;
921	STAMPROFILEADV StatExitHandling;
922	STAMPROFILEADV StatExitIO;
923	STAMPROFILEADV StatExitMovCRx;
924	STAMPROFILEADV StatExitXcptNmi;
925	STAMPROFILEADV StatImportGuestState;
926	STAMPROFILEADV StatExportGuestState;
927	STAMPROFILEADV StatLoadGuestFpuState;
928	STAMPROFILEADV StatInGC;
929	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
930	STAMPROFILEADV StatWorldSwitch3264;
931	#endif
932	STAMPROFILEADV StatPoke;
933	STAMPROFILEADV StatSpinPoke;
934	STAMPROFILEADV StatSpinPokeFailed;
935
936	STAMCOUNTER StatInjectInterrupt;
937	STAMCOUNTER StatInjectXcpt;
938	STAMCOUNTER StatInjectPendingReflect;
939	STAMCOUNTER StatInjectPendingInterpret;
940
941	STAMCOUNTER StatExitAll;
942	STAMCOUNTER StatExitShadowNM;
943	STAMCOUNTER StatExitGuestNM;
944	STAMCOUNTER StatExitShadowPF; /*< Misleading, currently used for MMIO \#PFs as well. /
945	STAMCOUNTER StatExitShadowPFEM;
946	STAMCOUNTER StatExitGuestPF;
947	STAMCOUNTER StatExitGuestUD;
948	STAMCOUNTER StatExitGuestSS;
949	STAMCOUNTER StatExitGuestNP;
950	STAMCOUNTER StatExitGuestTS;
951	STAMCOUNTER StatExitGuestGP;
952	STAMCOUNTER StatExitGuestDE;
953	STAMCOUNTER StatExitGuestDB;
954	STAMCOUNTER StatExitGuestMF;
955	STAMCOUNTER StatExitGuestBP;
956	STAMCOUNTER StatExitGuestXF;
957	STAMCOUNTER StatExitGuestXcpUnk;
958	STAMCOUNTER StatExitCli;
959	STAMCOUNTER StatExitSti;
960	STAMCOUNTER StatExitPushf;
961	STAMCOUNTER StatExitPopf;
962	STAMCOUNTER StatExitIret;
963	STAMCOUNTER StatExitInt;
964	STAMCOUNTER StatExitHlt;
965	STAMCOUNTER StatExitDRxWrite;
966	STAMCOUNTER StatExitDRxRead;
967	STAMCOUNTER StatExitCR0Read;
968	STAMCOUNTER StatExitCR2Read;
969	STAMCOUNTER StatExitCR3Read;
970	STAMCOUNTER StatExitCR4Read;
971	STAMCOUNTER StatExitCR8Read;
972	STAMCOUNTER StatExitCR0Write;
973	STAMCOUNTER StatExitCR2Write;
974	STAMCOUNTER StatExitCR3Write;
975	STAMCOUNTER StatExitCR4Write;
976	STAMCOUNTER StatExitCR8Write;
977	STAMCOUNTER StatExitRdmsr;
978	STAMCOUNTER StatExitWrmsr;
979	STAMCOUNTER StatExitClts;
980	STAMCOUNTER StatExitXdtrAccess;
981	STAMCOUNTER StatExitMwait;
982	STAMCOUNTER StatExitMonitor;
983	STAMCOUNTER StatExitLmsw;
984	STAMCOUNTER StatExitIOWrite;
985	STAMCOUNTER StatExitIORead;
986	STAMCOUNTER StatExitIOStringWrite;
987	STAMCOUNTER StatExitIOStringRead;
988	STAMCOUNTER StatExitIntWindow;
989	STAMCOUNTER StatExitExtInt;
990	STAMCOUNTER StatExitHostNmiInGC;
991	STAMCOUNTER StatExitPreemptTimer;
992	STAMCOUNTER StatExitTprBelowThreshold;
993	STAMCOUNTER StatExitTaskSwitch;
994	STAMCOUNTER StatExitMtf;
995	STAMCOUNTER StatExitApicAccess;
996	STAMCOUNTER StatExitReasonNpf;
997
998	STAMCOUNTER StatNestedExitReasonNpf;
999
1000	STAMCOUNTER StatFlushPage;
1001	STAMCOUNTER StatFlushPageManual;
1002	STAMCOUNTER StatFlushPhysPageManual;
1003	STAMCOUNTER StatFlushTlb;
1004	STAMCOUNTER StatFlushTlbManual;
1005	STAMCOUNTER StatFlushTlbWorldSwitch;
1006	STAMCOUNTER StatNoFlushTlbWorldSwitch;
1007	STAMCOUNTER StatFlushEntire;
1008	STAMCOUNTER StatFlushAsid;
1009	STAMCOUNTER StatFlushNestedPaging;
1010	STAMCOUNTER StatFlushTlbInvlpgVirt;
1011	STAMCOUNTER StatFlushTlbInvlpgPhys;
1012	STAMCOUNTER StatTlbShootdown;
1013	STAMCOUNTER StatTlbShootdownFlush;
1014
1015	STAMCOUNTER StatSwitchPendingHostIrq;
1016	STAMCOUNTER StatSwitchTprMaskedIrq;
1017	STAMCOUNTER StatSwitchGuestIrq;
1018	STAMCOUNTER StatSwitchHmToR3FF;
1019	STAMCOUNTER StatSwitchExitToR3;
1020	STAMCOUNTER StatSwitchLongJmpToR3;
1021	STAMCOUNTER StatSwitchMaxResumeLoops;
1022	STAMCOUNTER StatSwitchHltToR3;
1023	STAMCOUNTER StatSwitchApicAccessToR3;
1024	STAMCOUNTER StatSwitchPreempt;
1025	STAMCOUNTER StatSwitchPreemptExportHostState;
1026
1027	STAMCOUNTER StatTscParavirt;
1028	STAMCOUNTER StatTscOffset;
1029	STAMCOUNTER StatTscIntercept;
1030
1031	STAMCOUNTER StatDRxArmed;
1032	STAMCOUNTER StatDRxContextSwitch;
1033	STAMCOUNTER StatDRxIoCheck;
1034
1035	STAMCOUNTER StatExportMinimal;
1036	STAMCOUNTER StatExportFull;
1037	STAMCOUNTER StatLoadGuestFpu;
1038
1039	STAMCOUNTER StatVmxCheckBadRmSelBase;
1040	STAMCOUNTER StatVmxCheckBadRmSelLimit;
1041	STAMCOUNTER StatVmxCheckRmOk;
1042	STAMCOUNTER StatVmxCheckBadSel;
1043	STAMCOUNTER StatVmxCheckBadRpl;
1044	STAMCOUNTER StatVmxCheckBadLdt;
1045	STAMCOUNTER StatVmxCheckBadTr;
1046	STAMCOUNTER StatVmxCheckPmOk;
1047
1048	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1049	STAMCOUNTER StatFpu64SwitchBack;
1050	STAMCOUNTER StatDebug64SwitchBack;
1051	#endif
1052	#ifdef VBOX_WITH_STATISTICS
1053	R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
1054	R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
1055	R3PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqs;
1056	R0PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqsR0;
1057	R3PTRTYPE(PSTAMCOUNTER) paStatNestedExitReason;
1058	R0PTRTYPE(PSTAMCOUNTER) paStatNestedExitReasonR0;
1059	#endif
1060	#ifdef HM_PROFILE_EXIT_DISPATCH
1061	STAMPROFILEADV StatExitDispatch;
1062	#endif
1063	} HMCPU;
1064	/** Pointer to HM VMCPU instance data. */
1065	typedef HMCPU *PHMCPU;
1066	AssertCompileMemberAlignment(HMCPU, cWorldSwitchExits, 4);
1067	AssertCompileMemberAlignment(HMCPU, fCtxChanged, 8);
1068	AssertCompileMemberAlignment(HMCPU, vmx, 8);
1069	AssertCompileMemberAlignment(HMCPU, svm, 8);
1070	AssertCompileMemberAlignment(HMCPU, Event, 8);
1071
1072	#ifdef IN_RING0
1073	VMMR0_INT_DECL(PHMGLOBALCPUINFO) hmR0GetCurrentCpu(void);
1074	VMMR0_INT_DECL(int) hmR0EnterCpu(PVMCPU pVCpu);
1075
1076	# ifdef VBOX_STRICT
1077	VMMR0_INT_DECL(void) hmR0DumpRegs(PVMCPU pVCpu);
1078	VMMR0_INT_DECL(void) hmR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg);
1079	# endif
1080
1081	# ifdef VBOX_WITH_KERNEL_USING_XMM
1082	DECLASM(int) hmR0VMXStartVMWrapXMM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu, PFNHMVMXSTARTVM pfnStartVM);
1083	DECLASM(int) hmR0SVMRunWrapXMM(RTHCPHYS pVmcbHostPhys, RTHCPHYS pVmcbPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu, PFNHMSVMVMRUN pfnVMRun);
1084	# endif
1085	#endif /* IN_RING0 */
1086
1087	int hmSvmEmulateMovTpr(PVMCPU pVCpu);
1088
1089	/** @} */
1090
1091	RT_C_DECLS_END
1092
1093	#endif
1094

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source: vbox/trunk/src/VBox/VMM/include/HMInternal.h@ 74074

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