VirtualBox

source: vbox/trunk/src/VBox/VMM/include/HMInternal.h@ 78359

Last change on this file since 78359 was 78222, checked in by vboxsync, 6 years ago

HMInternal.h: Nested VMX: bugref:9180 Build fix.
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1/* $Id: HMInternal.h 78222 2019-04-20 04:23:29Z vboxsync $ */
2/** @file
3 * HM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef VMM_INCLUDED_SRC_include_HMInternal_h
19#define VMM_INCLUDED_SRC_include_HMInternal_h
20#ifndef RT_WITHOUT_PRAGMA_ONCE
21# pragma once
22#endif
23
24#include <VBox/cdefs.h>
25#include <VBox/types.h>
26#include <VBox/vmm/stam.h>
27#include <VBox/dis.h>
28#include <VBox/vmm/hm.h>
29#include <VBox/vmm/hm_vmx.h>
30#include <VBox/vmm/hm_svm.h>
31#include <VBox/vmm/pgm.h>
32#include <VBox/vmm/cpum.h>
33#include <VBox/vmm/trpm.h>
34#include <iprt/memobj.h>
35#include <iprt/cpuset.h>
36#include <iprt/mp.h>
37#include <iprt/avl.h>
38#include <iprt/string.h>
39
40#if HC_ARCH_BITS == 32 && defined(RT_OS_DARWIN)
41# error "32-bit darwin is no longer supported. Go back to 4.3 or earlier!"
42#endif
43
44#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_64_BITS_GUESTS)
45/* Enable 64 bits guest support. */
46# define VBOX_ENABLE_64_BITS_GUESTS
47#endif
48
49#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
50# define VMX_USE_CACHED_VMCS_ACCESSES
51#endif
52
53/** @def HM_PROFILE_EXIT_DISPATCH
54 * Enables profiling of the VM exit handler dispatching. */
55#if 0 || defined(DOXYGEN_RUNNING)
56# define HM_PROFILE_EXIT_DISPATCH
57#endif
58
59RT_C_DECLS_BEGIN
60
61
62/** @defgroup grp_hm_int Internal
63 * @ingroup grp_hm
64 * @internal
65 * @{
66 */
67
68/** @name HM_CHANGED_XXX
69 * HM CPU-context changed flags.
70 *
71 * These flags are used to keep track of which registers and state has been
72 * modified since they were imported back into the guest-CPU context.
73 *
74 * @{
75 */
76#define HM_CHANGED_HOST_CONTEXT UINT64_C(0x0000000000000001)
77#define HM_CHANGED_GUEST_RIP UINT64_C(0x0000000000000004)
78#define HM_CHANGED_GUEST_RFLAGS UINT64_C(0x0000000000000008)
79
80#define HM_CHANGED_GUEST_RAX UINT64_C(0x0000000000000010)
81#define HM_CHANGED_GUEST_RCX UINT64_C(0x0000000000000020)
82#define HM_CHANGED_GUEST_RDX UINT64_C(0x0000000000000040)
83#define HM_CHANGED_GUEST_RBX UINT64_C(0x0000000000000080)
84#define HM_CHANGED_GUEST_RSP UINT64_C(0x0000000000000100)
85#define HM_CHANGED_GUEST_RBP UINT64_C(0x0000000000000200)
86#define HM_CHANGED_GUEST_RSI UINT64_C(0x0000000000000400)
87#define HM_CHANGED_GUEST_RDI UINT64_C(0x0000000000000800)
88#define HM_CHANGED_GUEST_R8_R15 UINT64_C(0x0000000000001000)
89#define HM_CHANGED_GUEST_GPRS_MASK UINT64_C(0x0000000000001ff0)
90
91#define HM_CHANGED_GUEST_ES UINT64_C(0x0000000000002000)
92#define HM_CHANGED_GUEST_CS UINT64_C(0x0000000000004000)
93#define HM_CHANGED_GUEST_SS UINT64_C(0x0000000000008000)
94#define HM_CHANGED_GUEST_DS UINT64_C(0x0000000000010000)
95#define HM_CHANGED_GUEST_FS UINT64_C(0x0000000000020000)
96#define HM_CHANGED_GUEST_GS UINT64_C(0x0000000000040000)
97#define HM_CHANGED_GUEST_SREG_MASK UINT64_C(0x000000000007e000)
98
99#define HM_CHANGED_GUEST_GDTR UINT64_C(0x0000000000080000)
100#define HM_CHANGED_GUEST_IDTR UINT64_C(0x0000000000100000)
101#define HM_CHANGED_GUEST_LDTR UINT64_C(0x0000000000200000)
102#define HM_CHANGED_GUEST_TR UINT64_C(0x0000000000400000)
103#define HM_CHANGED_GUEST_TABLE_MASK UINT64_C(0x0000000000780000)
104
105#define HM_CHANGED_GUEST_CR0 UINT64_C(0x0000000000800000)
106#define HM_CHANGED_GUEST_CR2 UINT64_C(0x0000000001000000)
107#define HM_CHANGED_GUEST_CR3 UINT64_C(0x0000000002000000)
108#define HM_CHANGED_GUEST_CR4 UINT64_C(0x0000000004000000)
109#define HM_CHANGED_GUEST_CR_MASK UINT64_C(0x0000000007800000)
110
111#define HM_CHANGED_GUEST_APIC_TPR UINT64_C(0x0000000008000000)
112#define HM_CHANGED_GUEST_EFER_MSR UINT64_C(0x0000000010000000)
113
114#define HM_CHANGED_GUEST_DR0_DR3 UINT64_C(0x0000000020000000)
115#define HM_CHANGED_GUEST_DR6 UINT64_C(0x0000000040000000)
116#define HM_CHANGED_GUEST_DR7 UINT64_C(0x0000000080000000)
117#define HM_CHANGED_GUEST_DR_MASK UINT64_C(0x00000000e0000000)
118
119#define HM_CHANGED_GUEST_X87 UINT64_C(0x0000000100000000)
120#define HM_CHANGED_GUEST_SSE_AVX UINT64_C(0x0000000200000000)
121#define HM_CHANGED_GUEST_OTHER_XSAVE UINT64_C(0x0000000400000000)
122#define HM_CHANGED_GUEST_XCRx UINT64_C(0x0000000800000000)
123
124#define HM_CHANGED_GUEST_KERNEL_GS_BASE UINT64_C(0x0000001000000000)
125#define HM_CHANGED_GUEST_SYSCALL_MSRS UINT64_C(0x0000002000000000)
126#define HM_CHANGED_GUEST_SYSENTER_CS_MSR UINT64_C(0x0000004000000000)
127#define HM_CHANGED_GUEST_SYSENTER_EIP_MSR UINT64_C(0x0000008000000000)
128#define HM_CHANGED_GUEST_SYSENTER_ESP_MSR UINT64_C(0x0000010000000000)
129#define HM_CHANGED_GUEST_SYSENTER_MSR_MASK UINT64_C(0x000001c000000000)
130#define HM_CHANGED_GUEST_TSC_AUX UINT64_C(0x0000020000000000)
131#define HM_CHANGED_GUEST_OTHER_MSRS UINT64_C(0x0000040000000000)
132#define HM_CHANGED_GUEST_ALL_MSRS ( HM_CHANGED_GUEST_EFER \
133 | HM_CHANGED_GUEST_KERNEL_GS_BASE \
134 | HM_CHANGED_GUEST_SYSCALL_MSRS \
135 | HM_CHANGED_GUEST_SYSENTER_MSR_MASK \
136 | HM_CHANGED_GUEST_TSC_AUX \
137 | HM_CHANGED_GUEST_OTHER_MSRS)
138
139#define HM_CHANGED_GUEST_HWVIRT UINT64_C(0x0000080000000000)
140#define HM_CHANGED_GUEST_MASK UINT64_C(0x00000ffffffffffc)
141
142#define HM_CHANGED_KEEPER_STATE_MASK UINT64_C(0xffff000000000000)
143
144/** @todo r=ramshankar: Remove "GUEST" from XCPT_INTERCEPTS. */
145#define HM_CHANGED_VMX_GUEST_XCPT_INTERCEPTS UINT64_C(0x0001000000000000)
146#define HM_CHANGED_VMX_GUEST_AUTO_MSRS UINT64_C(0x0002000000000000)
147#define HM_CHANGED_VMX_GUEST_LAZY_MSRS UINT64_C(0x0004000000000000)
148#define HM_CHANGED_VMX_ENTRY_EXIT_CTLS UINT64_C(0x0008000000000000)
149#define HM_CHANGED_VMX_MASK UINT64_C(0x000f000000000000)
150#define HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE ( HM_CHANGED_GUEST_DR_MASK \
151 | HM_CHANGED_VMX_GUEST_LAZY_MSRS)
152
153/** @todo r=ramshankar: Remove "GUEST" from XCPT_INTERCEPTS. */
154#define HM_CHANGED_SVM_GUEST_XCPT_INTERCEPTS UINT64_C(0x0001000000000000)
155#define HM_CHANGED_SVM_MASK UINT64_C(0x0001000000000000)
156#define HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE HM_CHANGED_GUEST_DR_MASK
157
158#define HM_CHANGED_ALL_GUEST ( HM_CHANGED_GUEST_MASK \
159 | HM_CHANGED_KEEPER_STATE_MASK)
160
161/** Mask of what state might have changed when IEM raised an exception.
162 * This is a based on IEM_CPUMCTX_EXTRN_XCPT_MASK. */
163#define HM_CHANGED_RAISED_XCPT_MASK ( HM_CHANGED_GUEST_GPRS_MASK \
164 | HM_CHANGED_GUEST_RIP \
165 | HM_CHANGED_GUEST_RFLAGS \
166 | HM_CHANGED_GUEST_SS \
167 | HM_CHANGED_GUEST_CS \
168 | HM_CHANGED_GUEST_CR0 \
169 | HM_CHANGED_GUEST_CR3 \
170 | HM_CHANGED_GUEST_CR4 \
171 | HM_CHANGED_GUEST_APIC_TPR \
172 | HM_CHANGED_GUEST_EFER_MSR \
173 | HM_CHANGED_GUEST_DR7 \
174 | HM_CHANGED_GUEST_CR2 \
175 | HM_CHANGED_GUEST_SREG_MASK \
176 | HM_CHANGED_GUEST_TABLE_MASK)
177
178#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
179/** Mask of what state might have changed when \#VMEXIT is emulated. */
180# define HM_CHANGED_SVM_VMEXIT_MASK ( HM_CHANGED_GUEST_RSP \
181 | HM_CHANGED_GUEST_RAX \
182 | HM_CHANGED_GUEST_RIP \
183 | HM_CHANGED_GUEST_RFLAGS \
184 | HM_CHANGED_GUEST_CS \
185 | HM_CHANGED_GUEST_SS \
186 | HM_CHANGED_GUEST_DS \
187 | HM_CHANGED_GUEST_ES \
188 | HM_CHANGED_GUEST_GDTR \
189 | HM_CHANGED_GUEST_IDTR \
190 | HM_CHANGED_GUEST_CR_MASK \
191 | HM_CHANGED_GUEST_EFER_MSR \
192 | HM_CHANGED_GUEST_DR6 \
193 | HM_CHANGED_GUEST_DR7 \
194 | HM_CHANGED_GUEST_OTHER_MSRS \
195 | HM_CHANGED_GUEST_HWVIRT \
196 | HM_CHANGED_SVM_MASK \
197 | HM_CHANGED_GUEST_APIC_TPR)
198
199/** Mask of what state might have changed when \#VMEXIT is emulated. */
200# define HM_CHANGED_SVM_VMRUN_MASK HM_CHANGED_SVM_VMEXIT_MASK
201#endif
202/** @} */
203
204/** Maximum number of exit reason statistics counters. */
205#define MAX_EXITREASON_STAT 0x100
206#define MASK_EXITREASON_STAT 0xff
207#define MASK_INJECT_IRQ_STAT 0xff
208
209/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
210#define HM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
211/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
212#define HM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2 * PAGE_SIZE + 1)
213/** Total guest mapped memory needed. */
214#define HM_VTX_TOTAL_DEVHEAP_MEM (HM_EPT_IDENTITY_PG_TABLE_SIZE + HM_VTX_TSS_SIZE)
215
216
217/** @name Macros for enabling and disabling preemption.
218 * These are really just for hiding the RTTHREADPREEMPTSTATE and asserting that
219 * preemption has already been disabled when there is no context hook.
220 * @{ */
221#ifdef VBOX_STRICT
222# define HM_DISABLE_PREEMPT(a_pVCpu) \
223 RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
224 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD) || VMMR0ThreadCtxHookIsEnabled((a_pVCpu))); \
225 RTThreadPreemptDisable(&PreemptStateInternal)
226#else
227# define HM_DISABLE_PREEMPT(a_pVCpu) \
228 RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
229 RTThreadPreemptDisable(&PreemptStateInternal)
230#endif /* VBOX_STRICT */
231#define HM_RESTORE_PREEMPT() do { RTThreadPreemptRestore(&PreemptStateInternal); } while(0)
232/** @} */
233
234
235/** @name HM saved state versions.
236 * @{
237 */
238#define HM_SAVED_STATE_VERSION HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT
239#define HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT 6
240#define HM_SAVED_STATE_VERSION_TPR_PATCHING 5
241#define HM_SAVED_STATE_VERSION_NO_TPR_PATCHING 4
242#define HM_SAVED_STATE_VERSION_2_0_X 3
243/** @} */
244
245
246/**
247 * HM physical (host) CPU information.
248 */
249typedef struct HMPHYSCPU
250{
251 /** The CPU ID. */
252 RTCPUID idCpu;
253 /** The VM_HSAVE_AREA (AMD-V) / VMXON region (Intel) memory backing. */
254 RTR0MEMOBJ hMemObj;
255 /** The physical address of the first page in hMemObj (it's a
256 * physcially contigous allocation if it spans multiple pages). */
257 RTHCPHYS HCPhysMemObj;
258 /** The address of the memory (for pfnEnable). */
259 void *pvMemObj;
260 /** Current ASID (AMD-V) / VPID (Intel). */
261 uint32_t uCurrentAsid;
262 /** TLB flush count. */
263 uint32_t cTlbFlushes;
264 /** Whether to flush each new ASID/VPID before use. */
265 bool fFlushAsidBeforeUse;
266 /** Configured for VT-x or AMD-V. */
267 bool fConfigured;
268 /** Set if the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active. */
269 bool fIgnoreAMDVInUseError;
270 /** In use by our code. (for power suspend) */
271 bool volatile fInUse;
272#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
273 /** Nested-guest union (put data common to SVM/VMX outside the union). */
274 union
275 {
276 /** Nested-guest SVM data. */
277 struct
278 {
279 /** The active nested-guest MSR permission bitmap memory backing. */
280 RTR0MEMOBJ hNstGstMsrpm;
281 /** The physical address of the first page in hNstGstMsrpm (physcially
282 * contiguous allocation). */
283 RTHCPHYS HCPhysNstGstMsrpm;
284 /** The address of the active nested-guest MSRPM. */
285 void *pvNstGstMsrpm;
286 } svm;
287 /** @todo Nested-VMX. */
288 } n;
289#endif
290} HMPHYSCPU;
291/** Pointer to HMPHYSCPU struct. */
292typedef HMPHYSCPU *PHMPHYSCPU;
293/** Pointer to a const HMPHYSCPU struct. */
294typedef const HMPHYSCPU *PCHMPHYSCPU;
295
296/**
297 * TPR-instruction type.
298 */
299typedef enum
300{
301 HMTPRINSTR_INVALID,
302 HMTPRINSTR_READ,
303 HMTPRINSTR_READ_SHR4,
304 HMTPRINSTR_WRITE_REG,
305 HMTPRINSTR_WRITE_IMM,
306 HMTPRINSTR_JUMP_REPLACEMENT,
307 /** The usual 32-bit paranoia. */
308 HMTPRINSTR_32BIT_HACK = 0x7fffffff
309} HMTPRINSTR;
310
311/**
312 * TPR patch information.
313 */
314typedef struct
315{
316 /** The key is the address of patched instruction. (32 bits GC ptr) */
317 AVLOU32NODECORE Core;
318 /** Original opcode. */
319 uint8_t aOpcode[16];
320 /** Instruction size. */
321 uint32_t cbOp;
322 /** Replacement opcode. */
323 uint8_t aNewOpcode[16];
324 /** Replacement instruction size. */
325 uint32_t cbNewOp;
326 /** Instruction type. */
327 HMTPRINSTR enmType;
328 /** Source operand. */
329 uint32_t uSrcOperand;
330 /** Destination operand. */
331 uint32_t uDstOperand;
332 /** Number of times the instruction caused a fault. */
333 uint32_t cFaults;
334 /** Patch address of the jump replacement. */
335 RTGCPTR32 pJumpTarget;
336} HMTPRPATCH;
337/** Pointer to HMTPRPATCH. */
338typedef HMTPRPATCH *PHMTPRPATCH;
339/** Pointer to a const HMTPRPATCH. */
340typedef const HMTPRPATCH *PCHMTPRPATCH;
341
342
343/**
344 * Makes a HMEXITSTAT::uKey value from a program counter and an exit code.
345 *
346 * @returns 64-bit key
347 * @param a_uPC The RIP + CS.BASE value of the exit.
348 * @param a_uExit The exit code.
349 * @todo Add CPL?
350 */
351#define HMEXITSTAT_MAKE_KEY(a_uPC, a_uExit) (((a_uPC) & UINT64_C(0x0000ffffffffffff)) | (uint64_t)(a_uExit) << 48)
352
353typedef struct HMEXITINFO
354{
355 /** See HMEXITSTAT_MAKE_KEY(). */
356 uint64_t uKey;
357 /** Number of recent hits (depreciates with time). */
358 uint32_t volatile cHits;
359 /** The age + lock. */
360 uint16_t volatile uAge;
361 /** Action or action table index. */
362 uint16_t iAction;
363} HMEXITINFO;
364AssertCompileSize(HMEXITINFO, 16); /* Lots of these guys, so don't add any unnecessary stuff! */
365
366typedef struct HMEXITHISTORY
367{
368 /** The exit timestamp. */
369 uint64_t uTscExit;
370 /** The index of the corresponding HMEXITINFO entry.
371 * UINT32_MAX if none (too many collisions, race, whatever). */
372 uint32_t iExitInfo;
373 /** Figure out later, needed for padding now. */
374 uint32_t uSomeClueOrSomething;
375} HMEXITHISTORY;
376
377/**
378 * Switcher function, HC to the special 64-bit RC.
379 *
380 * @param pVM The cross context VM structure.
381 * @param offCpumVCpu Offset from pVM->cpum to pVM->aCpus[idCpu].cpum.
382 * @returns Return code indicating the action to take.
383 */
384typedef DECLCALLBACK(int) FNHMSWITCHERHC(PVM pVM, uint32_t offCpumVCpu);
385/** Pointer to switcher function. */
386typedef FNHMSWITCHERHC *PFNHMSWITCHERHC;
387
388/** @def HM_UNION_NM
389 * For compilers (like DTrace) that does not grok nameless unions, we have a
390 * little hack to make them palatable.
391 */
392/** @def HM_STRUCT_NM
393 * For compilers (like DTrace) that does not grok nameless structs (it is
394 * non-standard C++), we have a little hack to make them palatable.
395 */
396#ifdef VBOX_FOR_DTRACE_LIB
397# define HM_UNION_NM(a_Nm) a_Nm
398# define HM_STRUCT_NM(a_Nm) a_Nm
399#elif defined(IPRT_WITHOUT_NAMED_UNIONS_AND_STRUCTS)
400# define HM_UNION_NM(a_Nm) a_Nm
401# define HM_STRUCT_NM(a_Nm) a_Nm
402#else
403# define HM_UNION_NM(a_Nm)
404# define HM_STRUCT_NM(a_Nm)
405#endif
406
407/**
408 * HM event.
409 *
410 * VT-x and AMD-V common event injection structure.
411 */
412typedef struct HMEVENT
413{
414 /** Whether the event is pending. */
415 uint32_t fPending;
416 /** The error-code associated with the event. */
417 uint32_t u32ErrCode;
418 /** The length of the instruction in bytes (only relevant for software
419 * interrupts or software exceptions). */
420 uint32_t cbInstr;
421 /** Alignment. */
422 uint32_t u32Padding;
423 /** The encoded event (VM-entry interruption-information for VT-x or EVENTINJ
424 * for SVM). */
425 uint64_t u64IntInfo;
426 /** Guest virtual address if this is a page-fault event. */
427 RTGCUINTPTR GCPtrFaultAddress;
428} HMEVENT;
429/** Pointer to a HMEVENT struct. */
430typedef HMEVENT *PHMEVENT;
431/** Pointer to a const HMEVENT struct. */
432typedef const HMEVENT *PCHMEVENT;
433AssertCompileSizeAlignment(HMEVENT, 8);
434
435/**
436 * HM VM Instance data.
437 * Changes to this must checked against the padding of the hm union in VM!
438 */
439typedef struct HM
440{
441 /** Set when we've initialized VMX or SVM. */
442 bool fInitialized;
443 /** Set if nested paging is enabled. */
444 bool fNestedPaging;
445 /** Set if nested paging is allowed. */
446 bool fAllowNestedPaging;
447 /** Set if large pages are enabled (requires nested paging). */
448 bool fLargePages;
449 /** Set if we can support 64-bit guests or not. */
450 bool fAllow64BitGuests;
451 /** Set when TPR patching is allowed. */
452 bool fTprPatchingAllowed;
453 /** Set when we initialize VT-x or AMD-V once for all CPUs. */
454 bool fGlobalInit;
455 /** Set when TPR patching is active. */
456 bool fTPRPatchingActive;
457 /** Set when the debug facility has breakpoints/events enabled that requires
458 * us to use the debug execution loop in ring-0. */
459 bool fUseDebugLoop;
460 /** Set if hardware APIC virtualization is enabled. */
461 bool fVirtApicRegs;
462 /** Set if posted interrupt processing is enabled. */
463 bool fPostedIntrs;
464 /** Set if indirect branch prediction barrier on VM exit. */
465 bool fIbpbOnVmExit;
466 /** Set if indirect branch prediction barrier on VM entry. */
467 bool fIbpbOnVmEntry;
468 /** Set if level 1 data cache should be flushed on VM entry. */
469 bool fL1dFlushOnVmEntry;
470 /** Set if level 1 data cache should be flushed on EMT scheduling. */
471 bool fL1dFlushOnSched;
472 /** Set if host manages speculation control settings. */
473 bool fSpecCtrlByHost;
474
475 /** Maximum ASID allowed. */
476 uint32_t uMaxAsid;
477 /** The maximum number of resumes loops allowed in ring-0 (safety precaution).
478 * This number is set much higher when RTThreadPreemptIsPending is reliable. */
479 uint32_t cMaxResumeLoops;
480
481 /** Host kernel flags that HM might need to know (SUPKERNELFEATURES_XXX). */
482 uint32_t fHostKernelFeatures;
483
484 /** Size of the guest patch memory block. */
485 uint32_t cbGuestPatchMem;
486 /** Guest allocated memory for patching purposes. */
487 RTGCPTR pGuestPatchMem;
488 /** Current free pointer inside the patch block. */
489 RTGCPTR pFreeGuestPatchMem;
490
491#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
492 /** 32 to 64 bits switcher entrypoint. */
493 R0PTRTYPE(PFNHMSWITCHERHC) pfnHost32ToGuest64R0;
494 RTR0PTR pvR0Alignment0;
495#endif
496
497 struct
498 {
499 /** Set by the ring-0 side of HM to indicate VMX is supported by the
500 * CPU. */
501 bool fSupported;
502 /** Set when we've enabled VMX. */
503 bool fEnabled;
504 /** Set if VPID is supported. */
505 bool fVpid;
506 /** Set if VT-x VPID is allowed. */
507 bool fAllowVpid;
508 /** Set if unrestricted guest execution is in use (real and protected mode without paging). */
509 bool fUnrestrictedGuest;
510 /** Set if unrestricted guest execution is allowed to be used. */
511 bool fAllowUnrestricted;
512 /** Set if the preemption timer is in use or not. */
513 bool fUsePreemptTimer;
514 /** The shift mask employed by the VMX-Preemption timer. */
515 uint8_t cPreemptTimerShift;
516
517 /** Virtual address of the TSS page used for real mode emulation. */
518 R3PTRTYPE(PVBOXTSS) pRealModeTSS;
519 /** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
520 R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
521
522 /** Physical address of the APIC-access page. */
523 RTHCPHYS HCPhysApicAccess;
524 /** R0 memory object for the APIC-access page. */
525 RTR0MEMOBJ hMemObjApicAccess;
526 /** Virtual address of the APIC-access page. */
527 R0PTRTYPE(uint8_t *) pbApicAccess;
528
529#ifdef VBOX_WITH_CRASHDUMP_MAGIC
530 RTHCPHYS HCPhysScratch;
531 RTR0MEMOBJ hMemObjScratch;
532 R0PTRTYPE(uint8_t *) pbScratch;
533#endif
534
535 /** Tagged-TLB flush type. */
536 VMXTLBFLUSHTYPE enmTlbFlushType;
537 /** Flush type to use for INVEPT. */
538 VMXTLBFLUSHEPT enmTlbFlushEpt;
539 /** Flush type to use for INVVPID. */
540 VMXTLBFLUSHVPID enmTlbFlushVpid;
541
542 /** Pause-loop exiting (PLE) gap in ticks. */
543 uint32_t cPleGapTicks;
544 /** Pause-loop exiting (PLE) window in ticks. */
545 uint32_t cPleWindowTicks;
546 uint32_t u32Alignment0;
547
548 /** Host CR4 value (set by ring-0 VMX init) */
549 uint64_t u64HostCr4;
550 /** Host SMM monitor control (set by ring-0 VMX init) */
551 uint64_t u64HostSmmMonitorCtl;
552 /** Host EFER value (set by ring-0 VMX init) */
553 uint64_t u64HostMsrEfer;
554 /** Whether the CPU supports VMCS fields for swapping EFER. */
555 bool fSupportsVmcsEfer;
556 uint8_t u8Alignment2[7];
557
558 /** VMX MSR values. */
559 VMXMSRS Msrs;
560
561 /** Host-physical address for a failing VMXON instruction. */
562 RTHCPHYS HCPhysVmxEnableError;
563 } vmx;
564
565 struct
566 {
567 /** Set by the ring-0 side of HM to indicate SVM is supported by the
568 * CPU. */
569 bool fSupported;
570 /** Set when we've enabled SVM. */
571 bool fEnabled;
572 /** Set if erratum 170 affects the AMD cpu. */
573 bool fAlwaysFlushTLB;
574 /** Set when the hack to ignore VERR_SVM_IN_USE is active. */
575 bool fIgnoreInUseError;
576 /** Whether to use virtualized VMSAVE/VMLOAD feature. */
577 bool fVirtVmsaveVmload;
578 /** Whether to use virtual GIF feature. */
579 bool fVGif;
580 uint8_t u8Alignment0[2];
581
582 /** Physical address of the IO bitmap (12kb). */
583 RTHCPHYS HCPhysIOBitmap;
584 /** R0 memory object for the IO bitmap (12kb). */
585 RTR0MEMOBJ hMemObjIOBitmap;
586 /** Virtual address of the IO bitmap. */
587 R0PTRTYPE(void *) pvIOBitmap;
588
589 /* HWCR MSR (for diagnostics) */
590 uint64_t u64MsrHwcr;
591
592 /** SVM revision. */
593 uint32_t u32Rev;
594 /** SVM feature bits from cpuid 0x8000000a */
595 uint32_t u32Features;
596
597 /** Pause filter counter. */
598 uint16_t cPauseFilter;
599 /** Pause filter treshold in ticks. */
600 uint16_t cPauseFilterThresholdTicks;
601 uint32_t u32Alignment0;
602 } svm;
603
604 /**
605 * AVL tree with all patches (active or disabled) sorted by guest instruction
606 * address.
607 */
608 AVLOU32TREE PatchTree;
609 uint32_t cPatches;
610 HMTPRPATCH aPatches[64];
611
612 /** Last recorded error code during HM ring-0 init. */
613 int32_t rcInit;
614
615 /** HMR0Init was run */
616 bool fHMR0Init;
617 bool u8Alignment1[3];
618
619 STAMCOUNTER StatTprPatchSuccess;
620 STAMCOUNTER StatTprPatchFailure;
621 STAMCOUNTER StatTprReplaceSuccessCr8;
622 STAMCOUNTER StatTprReplaceSuccessVmc;
623 STAMCOUNTER StatTprReplaceFailure;
624} HM;
625/** Pointer to HM VM instance data. */
626typedef HM *PHM;
627
628AssertCompileMemberAlignment(HM, StatTprPatchSuccess, 8);
629
630/* Maximum number of cached entries. */
631#define VMX_VMCS_CACHE_MAX_ENTRY 128
632
633/**
634 * Cache of a VMCS for batch reads or writes.
635 */
636typedef struct VMXVMCSCACHE
637{
638#ifdef VBOX_WITH_CRASHDUMP_MAGIC
639 /* Magic marker for searching in crash dumps. */
640 uint8_t aMagic[16];
641 uint64_t uMagic;
642 uint64_t u64TimeEntry;
643 uint64_t u64TimeSwitch;
644 uint64_t cResume;
645 uint64_t interPD;
646 uint64_t pSwitcher;
647 uint32_t uPos;
648 uint32_t idCpu;
649#endif
650 /* CR2 is saved here for EPT syncing. */
651 uint64_t cr2;
652 struct
653 {
654 uint32_t cValidEntries;
655 uint32_t uAlignment;
656 uint32_t aField[VMX_VMCS_CACHE_MAX_ENTRY];
657 uint64_t aFieldVal[VMX_VMCS_CACHE_MAX_ENTRY];
658 } Write;
659 struct
660 {
661 uint32_t cValidEntries;
662 uint32_t uAlignment;
663 uint32_t aField[VMX_VMCS_CACHE_MAX_ENTRY];
664 uint64_t aFieldVal[VMX_VMCS_CACHE_MAX_ENTRY];
665 } Read;
666#ifdef VBOX_STRICT
667 struct
668 {
669 RTHCPHYS HCPhysCpuPage;
670 RTHCPHYS HCPhysVmcs;
671 RTGCPTR pCache;
672 RTGCPTR pCtx;
673 } TestIn;
674 struct
675 {
676 RTHCPHYS HCPhysVmcs;
677 RTGCPTR pCache;
678 RTGCPTR pCtx;
679 uint64_t eflags;
680 uint64_t cr8;
681 } TestOut;
682 struct
683 {
684 uint64_t param1;
685 uint64_t param2;
686 uint64_t param3;
687 uint64_t param4;
688 } ScratchPad;
689#endif
690} VMXVMCSCACHE;
691/** Pointer to VMXVMCSCACHE. */
692typedef VMXVMCSCACHE *PVMXVMCSCACHE;
693AssertCompileSizeAlignment(VMXVMCSCACHE, 8);
694
695/**
696 * VMX StartVM function.
697 *
698 * @returns VBox status code (no informational stuff).
699 * @param fResume Whether to use VMRESUME (true) or VMLAUNCH (false).
700 * @param pCtx The CPU register context.
701 * @param pVmcsCache The VMCS batch cache.
702 * @param pVM Pointer to the cross context VM structure.
703 * @param pVCpu Pointer to the cross context per-CPU structure.
704 */
705typedef DECLCALLBACK(int) FNHMVMXSTARTVM(RTHCUINT fResume, PCPUMCTX pCtx, PVMXVMCSCACHE pVmcsCache, PVM pVM, PVMCPU pVCpu);
706/** Pointer to a VMX StartVM function. */
707typedef R0PTRTYPE(FNHMVMXSTARTVM *) PFNHMVMXSTARTVM;
708
709/** SVM VMRun function. */
710typedef DECLCALLBACK(int) FNHMSVMVMRUN(RTHCPHYS pVmcbHostPhys, RTHCPHYS pVmcbPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu);
711/** Pointer to a SVM VMRun function. */
712typedef R0PTRTYPE(FNHMSVMVMRUN *) PFNHMSVMVMRUN;
713
714/**
715 * VMX VMCS information.
716 *
717 * This structure provides information maintained for and during the executing of a
718 * guest (or nested-guest) VMCS (VM control structure) using hardware-assisted VMX.
719 */
720typedef struct VMXVMCSINFO
721{
722 /** @name VMLAUNCH/VMRESUME information.
723 * @{ */
724 /** Ring-0 pointer to the hardware-assisted VMX execution function. */
725 PFNHMVMXSTARTVM pfnStartVM;
726#if HC_ARCH_BITS == 32
727 uint32_t u32Alignment0;
728#endif
729 /** @} */
730
731 /** @name VMCS and related data structures.
732 * @{ */
733 /** Host-physical address of the VMCS. */
734 RTHCPHYS HCPhysVmcs;
735 /** R0 memory object for the VMCS. */
736 RTR0MEMOBJ hMemObjVmcs;
737 /** Host-virtual address of the VMCS. */
738 R0PTRTYPE(void *) pvVmcs;
739
740 /** Host-physical address of the virtual APIC page. */
741 RTHCPHYS HCPhysVirtApic;
742 /** Alignment. */
743 R0PTRTYPE(void *) pvAlignment0;
744 /** Host-virtual address of the virtual-APIC page. */
745 R0PTRTYPE(uint8_t *) pbVirtApic;
746
747 /** Host-physical address of the MSR bitmap. */
748 RTHCPHYS HCPhysMsrBitmap;
749 /** R0 memory object for the MSR bitmap. */
750 RTR0MEMOBJ hMemObjMsrBitmap;
751 /** Host-virtual address of the MSR bitmap. */
752 R0PTRTYPE(void *) pvMsrBitmap;
753
754 /** Host-physical address of the VM-entry MSR-load area. */
755 RTHCPHYS HCPhysGuestMsrLoad;
756 /** R0 memory object of the VM-entry MSR-load area. */
757 RTR0MEMOBJ hMemObjGuestMsrLoad;
758 /** Host-virtual address of the VM-entry MSR-load area. */
759 R0PTRTYPE(void *) pvGuestMsrLoad;
760
761 /** Host-physical address of the VM-exit MSR-store area. */
762 RTHCPHYS HCPhysGuestMsrStore;
763 /** R0 memory object of the VM-exit MSR-store area. */
764 RTR0MEMOBJ hMemObjGuestMsrStore;
765 /** Host-virtual address of the VM-exit MSR-store area. */
766 R0PTRTYPE(void *) pvGuestMsrStore;
767
768 /** Host-physical address of the VM-exit MSR-load area. */
769 RTHCPHYS HCPhysHostMsrLoad;
770 /** R0 memory object for the VM-exit MSR-load area. */
771 RTR0MEMOBJ hMemObjHostMsrLoad;
772 /** Host-virtual address of the VM-exit MSR-load area. */
773 R0PTRTYPE(void *) pvHostMsrLoad;
774
775 /** Host-physical address of the EPTP. */
776 RTHCPHYS HCPhysEPTP;
777 /** Number of guest MSRs in the VM-entry MSR-load area. */
778 uint32_t cEntryMsrLoad;
779 /** Number of guest MSRs in the VM-exit MSR-store area. */
780 uint32_t cExitMsrStore;
781 /** Number of host MSRs in the VM-exit MSR-load area. */
782 uint32_t cExitMsrLoad;
783 /** Padding. */
784 uint32_t u32Padding0;
785 /** @} */
786
787 /** @name Auxiliary information.
788 * @{ */
789 /** The VMCS launch state, see VMX_V_VMCS_LAUNCH_STATE_XXX. */
790 uint32_t fVmcsState;
791 /** Set if guest was executing in real mode (extra checks). */
792 bool fWasInRealMode;
793 /** Set if the guest switched to 64-bit mode on a 32-bit host. */
794 bool fSwitchedTo64on32;
795 /** Padding. */
796 bool afPadding0[2];
797 /** @} */
798
799 /** @name Cache of execution related VMCS fields.
800 * @{ */
801 /** Pin-based VM-execution controls. */
802 uint32_t u32PinCtls;
803 /** Processor-based VM-execution controls. */
804 uint32_t u32ProcCtls;
805 /** Secondary processor-based VM-execution controls. */
806 uint32_t u32ProcCtls2;
807 /** VM-entry controls. */
808 uint32_t u32EntryCtls;
809 /** VM-exit controls. */
810 uint32_t u32ExitCtls;
811 /** Exception bitmap. */
812 uint32_t u32XcptBitmap;
813 /** CR0 guest/host mask. */
814 uint64_t u64Cr0Mask;
815 /** CR4 guest/host mask. */
816 uint64_t u64Cr4Mask;
817 /** Page-fault exception error-code mask. */
818 uint32_t u32XcptPFMask;
819 /** Page-fault exception error-code match. */
820 uint32_t u32XcptPFMatch;
821 /** TSC offset. */
822 uint64_t u64TscOffset;
823 /** VMCS link pointer. */
824 uint64_t u64VmcsLinkPtr;
825 /** @} */
826
827 /** @name Real-mode emulation state.
828 * @{ */
829 struct
830 {
831 X86DESCATTR AttrCS;
832 X86DESCATTR AttrDS;
833 X86DESCATTR AttrES;
834 X86DESCATTR AttrFS;
835 X86DESCATTR AttrGS;
836 X86DESCATTR AttrSS;
837 X86EFLAGS Eflags;
838 bool fRealOnV86Active;
839 bool afPadding1[3];
840 } RealMode;
841 /** @} */
842
843 /** Padding. */
844 uint64_t au64Padding[2];
845} VMXVMCSINFO;
846/** Pointer to a VMXVMCSINFO struct. */
847typedef VMXVMCSINFO *PVMXVMCSINFO;
848/** Pointer to a const VMXVMCSINFO struct. */
849typedef const VMXVMCSINFO *PCVMXVMCSINFO;
850AssertCompileSizeAlignment(VMXVMCSINFO, 8);
851AssertCompileMemberAlignment(VMXVMCSINFO, fVmcsState, 8);
852AssertCompileMemberAlignment(VMXVMCSINFO, u32PinCtls, 8);
853AssertCompileMemberAlignment(VMXVMCSINFO, u64VmcsLinkPtr, 8);
854
855/**
856 * HM VMCPU Instance data.
857 *
858 * Note! If you change members of this struct, make sure to check if the
859 * assembly counterpart in HMInternal.mac needs to be updated as well.
860 */
861typedef struct HMCPU
862{
863 /** Set when the TLB has been checked until we return from the world switch. */
864 bool volatile fCheckedTLBFlush;
865 /** Set if we need to flush the TLB during the world switch. */
866 bool fForceTLBFlush;
867 /** Set when we're using VT-x or AMD-V at that moment. */
868 bool fActive;
869 /** Whether we've completed the inner HM leave function. */
870 bool fLeaveDone;
871 /** Whether we're using the hyper DR7 or guest DR7. */
872 bool fUsingHyperDR7;
873 /** Set if XCR0 needs to be saved/restored when entering/exiting guest code
874 * execution. */
875 bool fLoadSaveGuestXcr0;
876
877 /** Whether we should use the debug loop because of single stepping or special
878 * debug breakpoints / events are armed. */
879 bool fUseDebugLoop;
880 /** Whether we are currently executing in the debug loop.
881 * Mainly for assertions. */
882 bool fUsingDebugLoop;
883 /** Set if we using the debug loop and wish to intercept RDTSC. */
884 bool fDebugWantRdTscExit;
885 /** Whether we're executing a single instruction. */
886 bool fSingleInstruction;
887 /** Set if we need to clear the trap flag because of single stepping. */
888 bool fClearTrapFlag;
889
890 /** Whether \#UD needs to be intercepted (required by certain GIM providers). */
891 bool fGIMTrapXcptUD;
892 /** Whether \#GP needs to be intercept for mesa driver workaround. */
893 bool fTrapXcptGpForLovelyMesaDrv;
894 uint8_t u8Alignment0[3];
895
896 /** World switch exit counter. */
897 uint32_t volatile cWorldSwitchExits;
898 /** The last CPU we were executing code on (NIL_RTCPUID for the first time). */
899 RTCPUID idLastCpu;
900 /** TLB flush count. */
901 uint32_t cTlbFlushes;
902 /** Current ASID in use by the VM. */
903 uint32_t uCurrentAsid;
904 /** An additional error code used for some gurus. */
905 uint32_t u32HMError;
906 /** The last exit-to-ring-3 reason. */
907 int32_t rcLastExitToR3;
908 /** CPU-context changed flags (see HM_CHANGED_xxx). */
909 uint64_t fCtxChanged;
910 /** Host's TSC_AUX MSR (used when RDTSCP doesn't cause VM-exits). */
911 uint64_t u64HostTscAux; /** @todo r=ramshankar: Can be removed and put in SVMTRANSIENT instead! */
912
913 union /* no tag! */
914 {
915 /** VT-x data. */
916 struct
917 {
918 /** @name Guest information.
919 * @{ */
920 /** Guest VMCS information. */
921 VMXVMCSINFO VmcsInfo;
922 /** Nested-guest VMCS information. */
923 VMXVMCSINFO VmcsInfoNstGst;
924 /** Whether the nested-guest VMCS was the last current VMCS. */
925 bool fSwitchedToNstGstVmcs;
926 /** Whether the static guest VMCS controls has been merged with the
927 * nested-guest VMCS controls. */
928 bool fMergedNstGstCtls;
929 /** Alignment. */
930 bool afAlignment0[6];
931 /** Cached guest APIC-base MSR for identifying when to map the APIC-access page. */
932 uint64_t u64GstMsrApicBase;
933 /** VMCS cache for batched vmread/vmwrites. */
934 VMXVMCSCACHE VmcsCache;
935 /** @} */
936
937 /** @name Host information.
938 * @{ */
939 /** Host LSTAR MSR to restore lazily while leaving VT-x. */
940 uint64_t u64HostMsrLStar;
941 /** Host STAR MSR to restore lazily while leaving VT-x. */
942 uint64_t u64HostMsrStar;
943 /** Host SF_MASK MSR to restore lazily while leaving VT-x. */
944 uint64_t u64HostMsrSfMask;
945 /** Host KernelGS-Base MSR to restore lazily while leaving VT-x. */
946 uint64_t u64HostMsrKernelGsBase;
947 /** The mask of lazy MSRs swap/restore state, see VMX_LAZY_MSRS_XXX. */
948 uint32_t fLazyMsrs;
949 /** Whether the host MSR values are up-to-date in the auto-load/store MSR area. */
950 bool fUpdatedHostAutoMsrs;
951 /** Alignment. */
952 uint8_t au8Alignment0[3];
953 /** Which host-state bits to restore before being preempted. */
954 uint32_t fRestoreHostFlags;
955 /** Alignment. */
956 uint32_t u32Alignment0;
957 /** The host-state restoration structure. */
958 VMXRESTOREHOST RestoreHost;
959 /** @} */
960
961 /** @name Error reporting and diagnostics.
962 * @{ */
963 /** VT-x error-reporting (mainly for ring-3 propagation). */
964 struct
965 {
966 RTHCPHYS HCPhysCurrentVmcs;
967 uint32_t u32VmcsRev;
968 uint32_t u32InstrError;
969 uint32_t u32ExitReason;
970 uint32_t u32Alignment0;
971 RTCPUID idEnteredCpu;
972 RTCPUID idCurrentCpu;
973 } LastError;
974 /** @} */
975 } vmx;
976
977 /** SVM data. */
978 struct
979 {
980 /** Ring 0 handlers for VT-x. */
981 PFNHMSVMVMRUN pfnVMRun;
982#if HC_ARCH_BITS == 32
983 uint32_t u32Alignment0;
984#endif
985
986 /** Physical address of the host VMCB which holds additional host-state. */
987 RTHCPHYS HCPhysVmcbHost;
988 /** R0 memory object for the host VMCB which holds additional host-state. */
989 RTR0MEMOBJ hMemObjVmcbHost;
990 /** Padding. */
991 R0PTRTYPE(void *) pvPadding;
992
993 /** Physical address of the guest VMCB. */
994 RTHCPHYS HCPhysVmcb;
995 /** R0 memory object for the guest VMCB. */
996 RTR0MEMOBJ hMemObjVmcb;
997 /** Pointer to the guest VMCB. */
998 R0PTRTYPE(PSVMVMCB) pVmcb;
999
1000 /** Physical address of the MSR bitmap (8 KB). */
1001 RTHCPHYS HCPhysMsrBitmap;
1002 /** R0 memory object for the MSR bitmap (8 KB). */
1003 RTR0MEMOBJ hMemObjMsrBitmap;
1004 /** Pointer to the MSR bitmap. */
1005 R0PTRTYPE(void *) pvMsrBitmap;
1006
1007 /** Whether VTPR with V_INTR_MASKING set is in effect, indicating
1008 * we should check if the VTPR changed on every VM-exit. */
1009 bool fSyncVTpr;
1010 uint8_t au8Alignment0[7];
1011
1012 /** Cache of the nested-guest's VMCB fields that we modify in order to run the
1013 * nested-guest using AMD-V. This will be restored on \#VMEXIT. */
1014 SVMNESTEDVMCBCACHE NstGstVmcbCache;
1015 } svm;
1016 } HM_UNION_NM(u);
1017
1018 /** Event injection state. */
1019 HMEVENT Event;
1020
1021 /** The PAE PDPEs used with Nested Paging (only valid when
1022 * VMCPU_FF_HM_UPDATE_PAE_PDPES is set). */
1023 X86PDPE aPdpes[4];
1024
1025 /** Current shadow paging mode for updating CR4. */
1026 PGMMODE enmShadowMode;
1027
1028 /** The CPU ID of the CPU currently owning the VMCS. Set in
1029 * HMR0Enter and cleared in HMR0Leave. */
1030 RTCPUID idEnteredCpu;
1031
1032 /** For saving stack space, the disassembler state is allocated here instead of
1033 * on the stack. */
1034 DISCPUSTATE DisState;
1035
1036 STAMPROFILEADV StatEntry;
1037 STAMPROFILEADV StatPreExit;
1038 STAMPROFILEADV StatExitHandling;
1039 STAMPROFILEADV StatExitIO;
1040 STAMPROFILEADV StatExitMovCRx;
1041 STAMPROFILEADV StatExitXcptNmi;
1042 STAMPROFILEADV StatImportGuestState;
1043 STAMPROFILEADV StatExportGuestState;
1044 STAMPROFILEADV StatLoadGuestFpuState;
1045 STAMPROFILEADV StatInGC;
1046#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1047 STAMPROFILEADV StatWorldSwitch3264;
1048#endif
1049 STAMPROFILEADV StatPoke;
1050 STAMPROFILEADV StatSpinPoke;
1051 STAMPROFILEADV StatSpinPokeFailed;
1052
1053 STAMCOUNTER StatInjectInterrupt;
1054 STAMCOUNTER StatInjectXcpt;
1055 STAMCOUNTER StatInjectPendingReflect;
1056 STAMCOUNTER StatInjectPendingInterpret;
1057
1058 STAMCOUNTER StatExitAll;
1059 STAMCOUNTER StatExitShadowNM;
1060 STAMCOUNTER StatExitGuestNM;
1061 STAMCOUNTER StatExitShadowPF; /**< Misleading, currently used for MMIO \#PFs as well. */
1062 STAMCOUNTER StatExitShadowPFEM;
1063 STAMCOUNTER StatExitGuestPF;
1064 STAMCOUNTER StatExitGuestUD;
1065 STAMCOUNTER StatExitGuestSS;
1066 STAMCOUNTER StatExitGuestNP;
1067 STAMCOUNTER StatExitGuestTS;
1068 STAMCOUNTER StatExitGuestGP;
1069 STAMCOUNTER StatExitGuestDE;
1070 STAMCOUNTER StatExitGuestDB;
1071 STAMCOUNTER StatExitGuestMF;
1072 STAMCOUNTER StatExitGuestBP;
1073 STAMCOUNTER StatExitGuestXF;
1074 STAMCOUNTER StatExitGuestXcpUnk;
1075 STAMCOUNTER StatExitDRxWrite;
1076 STAMCOUNTER StatExitDRxRead;
1077 STAMCOUNTER StatExitCR0Read;
1078 STAMCOUNTER StatExitCR2Read;
1079 STAMCOUNTER StatExitCR3Read;
1080 STAMCOUNTER StatExitCR4Read;
1081 STAMCOUNTER StatExitCR8Read;
1082 STAMCOUNTER StatExitCR0Write;
1083 STAMCOUNTER StatExitCR2Write;
1084 STAMCOUNTER StatExitCR3Write;
1085 STAMCOUNTER StatExitCR4Write;
1086 STAMCOUNTER StatExitCR8Write;
1087 STAMCOUNTER StatExitRdmsr;
1088 STAMCOUNTER StatExitWrmsr;
1089 STAMCOUNTER StatExitClts;
1090 STAMCOUNTER StatExitXdtrAccess;
1091 STAMCOUNTER StatExitLmsw;
1092 STAMCOUNTER StatExitIOWrite;
1093 STAMCOUNTER StatExitIORead;
1094 STAMCOUNTER StatExitIOStringWrite;
1095 STAMCOUNTER StatExitIOStringRead;
1096 STAMCOUNTER StatExitIntWindow;
1097 STAMCOUNTER StatExitExtInt;
1098 STAMCOUNTER StatExitHostNmiInGC;
1099 STAMCOUNTER StatExitPreemptTimer;
1100 STAMCOUNTER StatExitTprBelowThreshold;
1101 STAMCOUNTER StatExitTaskSwitch;
1102 STAMCOUNTER StatExitApicAccess;
1103 STAMCOUNTER StatExitReasonNpf;
1104
1105 STAMCOUNTER StatNestedExitReasonNpf;
1106
1107 STAMCOUNTER StatFlushPage;
1108 STAMCOUNTER StatFlushPageManual;
1109 STAMCOUNTER StatFlushPhysPageManual;
1110 STAMCOUNTER StatFlushTlb;
1111 STAMCOUNTER StatFlushTlbManual;
1112 STAMCOUNTER StatFlushTlbWorldSwitch;
1113 STAMCOUNTER StatNoFlushTlbWorldSwitch;
1114 STAMCOUNTER StatFlushEntire;
1115 STAMCOUNTER StatFlushAsid;
1116 STAMCOUNTER StatFlushNestedPaging;
1117 STAMCOUNTER StatFlushTlbInvlpgVirt;
1118 STAMCOUNTER StatFlushTlbInvlpgPhys;
1119 STAMCOUNTER StatTlbShootdown;
1120 STAMCOUNTER StatTlbShootdownFlush;
1121
1122 STAMCOUNTER StatSwitchPendingHostIrq;
1123 STAMCOUNTER StatSwitchTprMaskedIrq;
1124 STAMCOUNTER StatSwitchGuestIrq;
1125 STAMCOUNTER StatSwitchHmToR3FF;
1126 STAMCOUNTER StatSwitchExitToR3;
1127 STAMCOUNTER StatSwitchLongJmpToR3;
1128 STAMCOUNTER StatSwitchMaxResumeLoops;
1129 STAMCOUNTER StatSwitchHltToR3;
1130 STAMCOUNTER StatSwitchApicAccessToR3;
1131 STAMCOUNTER StatSwitchPreempt;
1132 STAMCOUNTER StatSwitchPreemptExportHostState;
1133
1134 STAMCOUNTER StatTscParavirt;
1135 STAMCOUNTER StatTscOffset;
1136 STAMCOUNTER StatTscIntercept;
1137
1138 STAMCOUNTER StatDRxArmed;
1139 STAMCOUNTER StatDRxContextSwitch;
1140 STAMCOUNTER StatDRxIoCheck;
1141
1142 STAMCOUNTER StatExportMinimal;
1143 STAMCOUNTER StatExportFull;
1144 STAMCOUNTER StatLoadGuestFpu;
1145
1146 STAMCOUNTER StatVmxCheckBadRmSelBase;
1147 STAMCOUNTER StatVmxCheckBadRmSelLimit;
1148 STAMCOUNTER StatVmxCheckBadRmSelAttr;
1149 STAMCOUNTER StatVmxCheckBadV86SelBase;
1150 STAMCOUNTER StatVmxCheckBadV86SelLimit;
1151 STAMCOUNTER StatVmxCheckBadV86SelAttr;
1152 STAMCOUNTER StatVmxCheckRmOk;
1153 STAMCOUNTER StatVmxCheckBadSel;
1154 STAMCOUNTER StatVmxCheckBadRpl;
1155 STAMCOUNTER StatVmxCheckPmOk;
1156
1157#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1158 STAMCOUNTER StatFpu64SwitchBack;
1159 STAMCOUNTER StatDebug64SwitchBack;
1160#endif
1161#ifdef VBOX_WITH_STATISTICS
1162 R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
1163 R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
1164 R3PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqs;
1165 R0PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqsR0;
1166 R3PTRTYPE(PSTAMCOUNTER) paStatNestedExitReason;
1167 R0PTRTYPE(PSTAMCOUNTER) paStatNestedExitReasonR0;
1168#endif
1169#ifdef HM_PROFILE_EXIT_DISPATCH
1170 STAMPROFILEADV StatExitDispatch;
1171#endif
1172} HMCPU;
1173/** Pointer to HM VMCPU instance data. */
1174typedef HMCPU *PHMCPU;
1175AssertCompileMemberAlignment(HMCPU, cWorldSwitchExits, 4);
1176AssertCompileMemberAlignment(HMCPU, fCtxChanged, 8);
1177AssertCompileMemberAlignment(HMCPU, HM_UNION_NM(u.) vmx, 8);
1178AssertCompileMemberAlignment(HMCPU, HM_UNION_NM(u.) svm, 8);
1179AssertCompileMemberAlignment(HMCPU, Event, 8);
1180
1181#ifdef IN_RING0
1182VMMR0_INT_DECL(PHMPHYSCPU) hmR0GetCurrentCpu(void);
1183VMMR0_INT_DECL(int) hmR0EnterCpu(PVMCPU pVCpu);
1184
1185# ifdef VBOX_STRICT
1186VMMR0_INT_DECL(void) hmR0DumpRegs(PVMCPU pVCpu);
1187VMMR0_INT_DECL(void) hmR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg);
1188# endif
1189
1190# ifdef VBOX_WITH_KERNEL_USING_XMM
1191DECLASM(int) hmR0VMXStartVMWrapXMM(RTHCUINT fResume, PCPUMCTX pCtx, PVMXVMCSCACHE pVmcsCache, PVM pVM,
1192 PVMCPU pVCpu, PFNHMVMXSTARTVM pfnStartVM);
1193DECLASM(int) hmR0SVMRunWrapXMM(RTHCPHYS pVmcbHostPhys, RTHCPHYS pVmcbPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu,
1194 PFNHMSVMVMRUN pfnVMRun);
1195# endif
1196#endif /* IN_RING0 */
1197
1198VMM_INT_DECL(int) hmEmulateSvmMovTpr(PVMCPU pVCpu);
1199
1200VMM_INT_DECL(PVMXVMCSINFO) hmGetVmxActiveVmcsInfo(PVMCPU pVCpu);
1201
1202/** @} */
1203
1204RT_C_DECLS_END
1205
1206#endif /* !VMM_INCLUDED_SRC_include_HMInternal_h */
1207
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