VirtualBox

source: vbox/trunk/src/VBox/VMM/include/HMInternal.h@ 79090

Last change on this file since 79090 was 78707, checked in by vboxsync, 6 years ago

VMM: Nested VMX: bugref:9180 Renamed HM_CHANGED_[VMX|SVM]_GUEST_XCPT_INTERCEPTS.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id Revision
File size: 49.6 KB
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1/* $Id: HMInternal.h 78707 2019-05-24 04:57:21Z vboxsync $ */
2/** @file
3 * HM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef VMM_INCLUDED_SRC_include_HMInternal_h
19#define VMM_INCLUDED_SRC_include_HMInternal_h
20#ifndef RT_WITHOUT_PRAGMA_ONCE
21# pragma once
22#endif
23
24#include <VBox/cdefs.h>
25#include <VBox/types.h>
26#include <VBox/vmm/stam.h>
27#include <VBox/dis.h>
28#include <VBox/vmm/hm.h>
29#include <VBox/vmm/hm_vmx.h>
30#include <VBox/vmm/hm_svm.h>
31#include <VBox/vmm/pgm.h>
32#include <VBox/vmm/cpum.h>
33#include <VBox/vmm/trpm.h>
34#include <iprt/memobj.h>
35#include <iprt/cpuset.h>
36#include <iprt/mp.h>
37#include <iprt/avl.h>
38#include <iprt/string.h>
39
40#if HC_ARCH_BITS == 32 && defined(RT_OS_DARWIN)
41# error "32-bit darwin is no longer supported. Go back to 4.3 or earlier!"
42#endif
43
44#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_64_BITS_GUESTS)
45/* Enable 64 bits guest support. */
46# define VBOX_ENABLE_64_BITS_GUESTS
47#endif
48
49#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
50# define VMX_USE_CACHED_VMCS_ACCESSES
51#endif
52
53/** @def HM_PROFILE_EXIT_DISPATCH
54 * Enables profiling of the VM exit handler dispatching. */
55#if 0 || defined(DOXYGEN_RUNNING)
56# define HM_PROFILE_EXIT_DISPATCH
57#endif
58
59RT_C_DECLS_BEGIN
60
61
62/** @defgroup grp_hm_int Internal
63 * @ingroup grp_hm
64 * @internal
65 * @{
66 */
67
68/** @name HM_CHANGED_XXX
69 * HM CPU-context changed flags.
70 *
71 * These flags are used to keep track of which registers and state has been
72 * modified since they were imported back into the guest-CPU context.
73 *
74 * @{
75 */
76#define HM_CHANGED_HOST_CONTEXT UINT64_C(0x0000000000000001)
77#define HM_CHANGED_GUEST_RIP UINT64_C(0x0000000000000004)
78#define HM_CHANGED_GUEST_RFLAGS UINT64_C(0x0000000000000008)
79
80#define HM_CHANGED_GUEST_RAX UINT64_C(0x0000000000000010)
81#define HM_CHANGED_GUEST_RCX UINT64_C(0x0000000000000020)
82#define HM_CHANGED_GUEST_RDX UINT64_C(0x0000000000000040)
83#define HM_CHANGED_GUEST_RBX UINT64_C(0x0000000000000080)
84#define HM_CHANGED_GUEST_RSP UINT64_C(0x0000000000000100)
85#define HM_CHANGED_GUEST_RBP UINT64_C(0x0000000000000200)
86#define HM_CHANGED_GUEST_RSI UINT64_C(0x0000000000000400)
87#define HM_CHANGED_GUEST_RDI UINT64_C(0x0000000000000800)
88#define HM_CHANGED_GUEST_R8_R15 UINT64_C(0x0000000000001000)
89#define HM_CHANGED_GUEST_GPRS_MASK UINT64_C(0x0000000000001ff0)
90
91#define HM_CHANGED_GUEST_ES UINT64_C(0x0000000000002000)
92#define HM_CHANGED_GUEST_CS UINT64_C(0x0000000000004000)
93#define HM_CHANGED_GUEST_SS UINT64_C(0x0000000000008000)
94#define HM_CHANGED_GUEST_DS UINT64_C(0x0000000000010000)
95#define HM_CHANGED_GUEST_FS UINT64_C(0x0000000000020000)
96#define HM_CHANGED_GUEST_GS UINT64_C(0x0000000000040000)
97#define HM_CHANGED_GUEST_SREG_MASK UINT64_C(0x000000000007e000)
98
99#define HM_CHANGED_GUEST_GDTR UINT64_C(0x0000000000080000)
100#define HM_CHANGED_GUEST_IDTR UINT64_C(0x0000000000100000)
101#define HM_CHANGED_GUEST_LDTR UINT64_C(0x0000000000200000)
102#define HM_CHANGED_GUEST_TR UINT64_C(0x0000000000400000)
103#define HM_CHANGED_GUEST_TABLE_MASK UINT64_C(0x0000000000780000)
104
105#define HM_CHANGED_GUEST_CR0 UINT64_C(0x0000000000800000)
106#define HM_CHANGED_GUEST_CR2 UINT64_C(0x0000000001000000)
107#define HM_CHANGED_GUEST_CR3 UINT64_C(0x0000000002000000)
108#define HM_CHANGED_GUEST_CR4 UINT64_C(0x0000000004000000)
109#define HM_CHANGED_GUEST_CR_MASK UINT64_C(0x0000000007800000)
110
111#define HM_CHANGED_GUEST_APIC_TPR UINT64_C(0x0000000008000000)
112#define HM_CHANGED_GUEST_EFER_MSR UINT64_C(0x0000000010000000)
113
114#define HM_CHANGED_GUEST_DR0_DR3 UINT64_C(0x0000000020000000)
115#define HM_CHANGED_GUEST_DR6 UINT64_C(0x0000000040000000)
116#define HM_CHANGED_GUEST_DR7 UINT64_C(0x0000000080000000)
117#define HM_CHANGED_GUEST_DR_MASK UINT64_C(0x00000000e0000000)
118
119#define HM_CHANGED_GUEST_X87 UINT64_C(0x0000000100000000)
120#define HM_CHANGED_GUEST_SSE_AVX UINT64_C(0x0000000200000000)
121#define HM_CHANGED_GUEST_OTHER_XSAVE UINT64_C(0x0000000400000000)
122#define HM_CHANGED_GUEST_XCRx UINT64_C(0x0000000800000000)
123
124#define HM_CHANGED_GUEST_KERNEL_GS_BASE UINT64_C(0x0000001000000000)
125#define HM_CHANGED_GUEST_SYSCALL_MSRS UINT64_C(0x0000002000000000)
126#define HM_CHANGED_GUEST_SYSENTER_CS_MSR UINT64_C(0x0000004000000000)
127#define HM_CHANGED_GUEST_SYSENTER_EIP_MSR UINT64_C(0x0000008000000000)
128#define HM_CHANGED_GUEST_SYSENTER_ESP_MSR UINT64_C(0x0000010000000000)
129#define HM_CHANGED_GUEST_SYSENTER_MSR_MASK UINT64_C(0x000001c000000000)
130#define HM_CHANGED_GUEST_TSC_AUX UINT64_C(0x0000020000000000)
131#define HM_CHANGED_GUEST_OTHER_MSRS UINT64_C(0x0000040000000000)
132#define HM_CHANGED_GUEST_ALL_MSRS ( HM_CHANGED_GUEST_EFER \
133 | HM_CHANGED_GUEST_KERNEL_GS_BASE \
134 | HM_CHANGED_GUEST_SYSCALL_MSRS \
135 | HM_CHANGED_GUEST_SYSENTER_MSR_MASK \
136 | HM_CHANGED_GUEST_TSC_AUX \
137 | HM_CHANGED_GUEST_OTHER_MSRS)
138
139#define HM_CHANGED_GUEST_HWVIRT UINT64_C(0x0000080000000000)
140#define HM_CHANGED_GUEST_MASK UINT64_C(0x00000ffffffffffc)
141
142#define HM_CHANGED_KEEPER_STATE_MASK UINT64_C(0xffff000000000000)
143
144#define HM_CHANGED_VMX_XCPT_INTERCEPTS UINT64_C(0x0001000000000000)
145#define HM_CHANGED_VMX_GUEST_AUTO_MSRS UINT64_C(0x0002000000000000)
146#define HM_CHANGED_VMX_GUEST_LAZY_MSRS UINT64_C(0x0004000000000000)
147#define HM_CHANGED_VMX_ENTRY_EXIT_CTLS UINT64_C(0x0008000000000000)
148#define HM_CHANGED_VMX_MASK UINT64_C(0x000f000000000000)
149#define HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE ( HM_CHANGED_GUEST_DR_MASK \
150 | HM_CHANGED_VMX_GUEST_LAZY_MSRS)
151
152#define HM_CHANGED_SVM_XCPT_INTERCEPTS UINT64_C(0x0001000000000000)
153#define HM_CHANGED_SVM_MASK UINT64_C(0x0001000000000000)
154#define HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE HM_CHANGED_GUEST_DR_MASK
155
156#define HM_CHANGED_ALL_GUEST ( HM_CHANGED_GUEST_MASK \
157 | HM_CHANGED_KEEPER_STATE_MASK)
158
159/** Mask of what state might have changed when IEM raised an exception.
160 * This is a based on IEM_CPUMCTX_EXTRN_XCPT_MASK. */
161#define HM_CHANGED_RAISED_XCPT_MASK ( HM_CHANGED_GUEST_GPRS_MASK \
162 | HM_CHANGED_GUEST_RIP \
163 | HM_CHANGED_GUEST_RFLAGS \
164 | HM_CHANGED_GUEST_SS \
165 | HM_CHANGED_GUEST_CS \
166 | HM_CHANGED_GUEST_CR0 \
167 | HM_CHANGED_GUEST_CR3 \
168 | HM_CHANGED_GUEST_CR4 \
169 | HM_CHANGED_GUEST_APIC_TPR \
170 | HM_CHANGED_GUEST_EFER_MSR \
171 | HM_CHANGED_GUEST_DR7 \
172 | HM_CHANGED_GUEST_CR2 \
173 | HM_CHANGED_GUEST_SREG_MASK \
174 | HM_CHANGED_GUEST_TABLE_MASK)
175
176#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
177/** Mask of what state might have changed when \#VMEXIT is emulated. */
178# define HM_CHANGED_SVM_VMEXIT_MASK ( HM_CHANGED_GUEST_RSP \
179 | HM_CHANGED_GUEST_RAX \
180 | HM_CHANGED_GUEST_RIP \
181 | HM_CHANGED_GUEST_RFLAGS \
182 | HM_CHANGED_GUEST_CS \
183 | HM_CHANGED_GUEST_SS \
184 | HM_CHANGED_GUEST_DS \
185 | HM_CHANGED_GUEST_ES \
186 | HM_CHANGED_GUEST_GDTR \
187 | HM_CHANGED_GUEST_IDTR \
188 | HM_CHANGED_GUEST_CR_MASK \
189 | HM_CHANGED_GUEST_EFER_MSR \
190 | HM_CHANGED_GUEST_DR6 \
191 | HM_CHANGED_GUEST_DR7 \
192 | HM_CHANGED_GUEST_OTHER_MSRS \
193 | HM_CHANGED_GUEST_HWVIRT \
194 | HM_CHANGED_SVM_MASK \
195 | HM_CHANGED_GUEST_APIC_TPR)
196
197/** Mask of what state might have changed when \#VMEXIT is emulated. */
198# define HM_CHANGED_SVM_VMRUN_MASK HM_CHANGED_SVM_VMEXIT_MASK
199#endif
200/** @} */
201
202/** Maximum number of exit reason statistics counters. */
203#define MAX_EXITREASON_STAT 0x100
204#define MASK_EXITREASON_STAT 0xff
205#define MASK_INJECT_IRQ_STAT 0xff
206
207/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
208#define HM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
209/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
210#define HM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2 * PAGE_SIZE + 1)
211/** Total guest mapped memory needed. */
212#define HM_VTX_TOTAL_DEVHEAP_MEM (HM_EPT_IDENTITY_PG_TABLE_SIZE + HM_VTX_TSS_SIZE)
213
214
215/** @name Macros for enabling and disabling preemption.
216 * These are really just for hiding the RTTHREADPREEMPTSTATE and asserting that
217 * preemption has already been disabled when there is no context hook.
218 * @{ */
219#ifdef VBOX_STRICT
220# define HM_DISABLE_PREEMPT(a_pVCpu) \
221 RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
222 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD) || VMMR0ThreadCtxHookIsEnabled((a_pVCpu))); \
223 RTThreadPreemptDisable(&PreemptStateInternal)
224#else
225# define HM_DISABLE_PREEMPT(a_pVCpu) \
226 RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
227 RTThreadPreemptDisable(&PreemptStateInternal)
228#endif /* VBOX_STRICT */
229#define HM_RESTORE_PREEMPT() do { RTThreadPreemptRestore(&PreemptStateInternal); } while(0)
230/** @} */
231
232
233/** @name HM saved state versions.
234 * @{
235 */
236#define HM_SAVED_STATE_VERSION HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT
237#define HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT 6
238#define HM_SAVED_STATE_VERSION_TPR_PATCHING 5
239#define HM_SAVED_STATE_VERSION_NO_TPR_PATCHING 4
240#define HM_SAVED_STATE_VERSION_2_0_X 3
241/** @} */
242
243
244/**
245 * HM physical (host) CPU information.
246 */
247typedef struct HMPHYSCPU
248{
249 /** The CPU ID. */
250 RTCPUID idCpu;
251 /** The VM_HSAVE_AREA (AMD-V) / VMXON region (Intel) memory backing. */
252 RTR0MEMOBJ hMemObj;
253 /** The physical address of the first page in hMemObj (it's a
254 * physcially contigous allocation if it spans multiple pages). */
255 RTHCPHYS HCPhysMemObj;
256 /** The address of the memory (for pfnEnable). */
257 void *pvMemObj;
258 /** Current ASID (AMD-V) / VPID (Intel). */
259 uint32_t uCurrentAsid;
260 /** TLB flush count. */
261 uint32_t cTlbFlushes;
262 /** Whether to flush each new ASID/VPID before use. */
263 bool fFlushAsidBeforeUse;
264 /** Configured for VT-x or AMD-V. */
265 bool fConfigured;
266 /** Set if the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active. */
267 bool fIgnoreAMDVInUseError;
268 /** In use by our code. (for power suspend) */
269 bool volatile fInUse;
270#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
271 /** Nested-guest union (put data common to SVM/VMX outside the union). */
272 union
273 {
274 /** Nested-guest SVM data. */
275 struct
276 {
277 /** The active nested-guest MSR permission bitmap memory backing. */
278 RTR0MEMOBJ hNstGstMsrpm;
279 /** The physical address of the first page in hNstGstMsrpm (physcially
280 * contiguous allocation). */
281 RTHCPHYS HCPhysNstGstMsrpm;
282 /** The address of the active nested-guest MSRPM. */
283 void *pvNstGstMsrpm;
284 } svm;
285 /** @todo Nested-VMX. */
286 } n;
287#endif
288} HMPHYSCPU;
289/** Pointer to HMPHYSCPU struct. */
290typedef HMPHYSCPU *PHMPHYSCPU;
291/** Pointer to a const HMPHYSCPU struct. */
292typedef const HMPHYSCPU *PCHMPHYSCPU;
293
294/**
295 * TPR-instruction type.
296 */
297typedef enum
298{
299 HMTPRINSTR_INVALID,
300 HMTPRINSTR_READ,
301 HMTPRINSTR_READ_SHR4,
302 HMTPRINSTR_WRITE_REG,
303 HMTPRINSTR_WRITE_IMM,
304 HMTPRINSTR_JUMP_REPLACEMENT,
305 /** The usual 32-bit paranoia. */
306 HMTPRINSTR_32BIT_HACK = 0x7fffffff
307} HMTPRINSTR;
308
309/**
310 * TPR patch information.
311 */
312typedef struct
313{
314 /** The key is the address of patched instruction. (32 bits GC ptr) */
315 AVLOU32NODECORE Core;
316 /** Original opcode. */
317 uint8_t aOpcode[16];
318 /** Instruction size. */
319 uint32_t cbOp;
320 /** Replacement opcode. */
321 uint8_t aNewOpcode[16];
322 /** Replacement instruction size. */
323 uint32_t cbNewOp;
324 /** Instruction type. */
325 HMTPRINSTR enmType;
326 /** Source operand. */
327 uint32_t uSrcOperand;
328 /** Destination operand. */
329 uint32_t uDstOperand;
330 /** Number of times the instruction caused a fault. */
331 uint32_t cFaults;
332 /** Patch address of the jump replacement. */
333 RTGCPTR32 pJumpTarget;
334} HMTPRPATCH;
335/** Pointer to HMTPRPATCH. */
336typedef HMTPRPATCH *PHMTPRPATCH;
337/** Pointer to a const HMTPRPATCH. */
338typedef const HMTPRPATCH *PCHMTPRPATCH;
339
340
341/**
342 * Makes a HMEXITSTAT::uKey value from a program counter and an exit code.
343 *
344 * @returns 64-bit key
345 * @param a_uPC The RIP + CS.BASE value of the exit.
346 * @param a_uExit The exit code.
347 * @todo Add CPL?
348 */
349#define HMEXITSTAT_MAKE_KEY(a_uPC, a_uExit) (((a_uPC) & UINT64_C(0x0000ffffffffffff)) | (uint64_t)(a_uExit) << 48)
350
351typedef struct HMEXITINFO
352{
353 /** See HMEXITSTAT_MAKE_KEY(). */
354 uint64_t uKey;
355 /** Number of recent hits (depreciates with time). */
356 uint32_t volatile cHits;
357 /** The age + lock. */
358 uint16_t volatile uAge;
359 /** Action or action table index. */
360 uint16_t iAction;
361} HMEXITINFO;
362AssertCompileSize(HMEXITINFO, 16); /* Lots of these guys, so don't add any unnecessary stuff! */
363
364typedef struct HMEXITHISTORY
365{
366 /** The exit timestamp. */
367 uint64_t uTscExit;
368 /** The index of the corresponding HMEXITINFO entry.
369 * UINT32_MAX if none (too many collisions, race, whatever). */
370 uint32_t iExitInfo;
371 /** Figure out later, needed for padding now. */
372 uint32_t uSomeClueOrSomething;
373} HMEXITHISTORY;
374
375/**
376 * Switcher function, HC to the special 64-bit RC.
377 *
378 * @param pVM The cross context VM structure.
379 * @param offCpumVCpu Offset from pVM->cpum to pVM->aCpus[idCpu].cpum.
380 * @returns Return code indicating the action to take.
381 */
382typedef DECLCALLBACK(int) FNHMSWITCHERHC(PVM pVM, uint32_t offCpumVCpu);
383/** Pointer to switcher function. */
384typedef FNHMSWITCHERHC *PFNHMSWITCHERHC;
385
386/** @def HM_UNION_NM
387 * For compilers (like DTrace) that does not grok nameless unions, we have a
388 * little hack to make them palatable.
389 */
390/** @def HM_STRUCT_NM
391 * For compilers (like DTrace) that does not grok nameless structs (it is
392 * non-standard C++), we have a little hack to make them palatable.
393 */
394#ifdef VBOX_FOR_DTRACE_LIB
395# define HM_UNION_NM(a_Nm) a_Nm
396# define HM_STRUCT_NM(a_Nm) a_Nm
397#elif defined(IPRT_WITHOUT_NAMED_UNIONS_AND_STRUCTS)
398# define HM_UNION_NM(a_Nm) a_Nm
399# define HM_STRUCT_NM(a_Nm) a_Nm
400#else
401# define HM_UNION_NM(a_Nm)
402# define HM_STRUCT_NM(a_Nm)
403#endif
404
405/**
406 * HM event.
407 *
408 * VT-x and AMD-V common event injection structure.
409 */
410typedef struct HMEVENT
411{
412 /** Whether the event is pending. */
413 uint32_t fPending;
414 /** The error-code associated with the event. */
415 uint32_t u32ErrCode;
416 /** The length of the instruction in bytes (only relevant for software
417 * interrupts or software exceptions). */
418 uint32_t cbInstr;
419 /** Alignment. */
420 uint32_t u32Padding;
421 /** The encoded event (VM-entry interruption-information for VT-x or EVENTINJ
422 * for SVM). */
423 uint64_t u64IntInfo;
424 /** Guest virtual address if this is a page-fault event. */
425 RTGCUINTPTR GCPtrFaultAddress;
426} HMEVENT;
427/** Pointer to a HMEVENT struct. */
428typedef HMEVENT *PHMEVENT;
429/** Pointer to a const HMEVENT struct. */
430typedef const HMEVENT *PCHMEVENT;
431AssertCompileSizeAlignment(HMEVENT, 8);
432
433/**
434 * HM VM Instance data.
435 * Changes to this must checked against the padding of the hm union in VM!
436 */
437typedef struct HM
438{
439 /** Set when we've initialized VMX or SVM. */
440 bool fInitialized;
441 /** Set if nested paging is enabled. */
442 bool fNestedPaging;
443 /** Set if nested paging is allowed. */
444 bool fAllowNestedPaging;
445 /** Set if large pages are enabled (requires nested paging). */
446 bool fLargePages;
447 /** Set if we can support 64-bit guests or not. */
448 bool fAllow64BitGuests;
449 /** Set when TPR patching is allowed. */
450 bool fTprPatchingAllowed;
451 /** Set when we initialize VT-x or AMD-V once for all CPUs. */
452 bool fGlobalInit;
453 /** Set when TPR patching is active. */
454 bool fTPRPatchingActive;
455 /** Set when the debug facility has breakpoints/events enabled that requires
456 * us to use the debug execution loop in ring-0. */
457 bool fUseDebugLoop;
458 /** Set if hardware APIC virtualization is enabled. */
459 bool fVirtApicRegs;
460 /** Set if posted interrupt processing is enabled. */
461 bool fPostedIntrs;
462 /** Set if indirect branch prediction barrier on VM exit. */
463 bool fIbpbOnVmExit;
464 /** Set if indirect branch prediction barrier on VM entry. */
465 bool fIbpbOnVmEntry;
466 /** Set if level 1 data cache should be flushed on VM entry. */
467 bool fL1dFlushOnVmEntry;
468 /** Set if level 1 data cache should be flushed on EMT scheduling. */
469 bool fL1dFlushOnSched;
470 /** Set if host manages speculation control settings. */
471 bool fSpecCtrlByHost;
472 /** Set if MDS related buffers should be cleared on VM entry. */
473 bool fMdsClearOnVmEntry;
474 /** Set if MDS related buffers should be cleared on EMT scheduling. */
475 bool fMdsClearOnSched;
476 /** Alignment padding. */
477 bool afPaddingMinus1[6];
478
479 /** Maximum ASID allowed. */
480 uint32_t uMaxAsid;
481 /** The maximum number of resumes loops allowed in ring-0 (safety precaution).
482 * This number is set much higher when RTThreadPreemptIsPending is reliable. */
483 uint32_t cMaxResumeLoops;
484
485 /** Host kernel flags that HM might need to know (SUPKERNELFEATURES_XXX). */
486 uint32_t fHostKernelFeatures;
487
488 /** Size of the guest patch memory block. */
489 uint32_t cbGuestPatchMem;
490 /** Guest allocated memory for patching purposes. */
491 RTGCPTR pGuestPatchMem;
492 /** Current free pointer inside the patch block. */
493 RTGCPTR pFreeGuestPatchMem;
494
495#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
496 /** 32 to 64 bits switcher entrypoint. */
497 R0PTRTYPE(PFNHMSWITCHERHC) pfnHost32ToGuest64R0;
498 RTR0PTR pvR0Alignment0;
499#endif
500
501 struct
502 {
503 /** Set by the ring-0 side of HM to indicate VMX is supported by the
504 * CPU. */
505 bool fSupported;
506 /** Set when we've enabled VMX. */
507 bool fEnabled;
508 /** Set if VPID is supported. */
509 bool fVpid;
510 /** Set if VT-x VPID is allowed. */
511 bool fAllowVpid;
512 /** Set if unrestricted guest execution is in use (real and protected mode without paging). */
513 bool fUnrestrictedGuest;
514 /** Set if unrestricted guest execution is allowed to be used. */
515 bool fAllowUnrestricted;
516 /** Set if the preemption timer is in use or not. */
517 bool fUsePreemptTimer;
518 /** The shift mask employed by the VMX-Preemption timer. */
519 uint8_t cPreemptTimerShift;
520
521 /** Virtual address of the TSS page used for real mode emulation. */
522 R3PTRTYPE(PVBOXTSS) pRealModeTSS;
523 /** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
524 R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
525
526 /** Physical address of the APIC-access page. */
527 RTHCPHYS HCPhysApicAccess;
528 /** R0 memory object for the APIC-access page. */
529 RTR0MEMOBJ hMemObjApicAccess;
530 /** Virtual address of the APIC-access page. */
531 R0PTRTYPE(uint8_t *) pbApicAccess;
532
533#ifdef VBOX_WITH_CRASHDUMP_MAGIC
534 RTHCPHYS HCPhysScratch;
535 RTR0MEMOBJ hMemObjScratch;
536 R0PTRTYPE(uint8_t *) pbScratch;
537#endif
538
539 /** Tagged-TLB flush type. */
540 VMXTLBFLUSHTYPE enmTlbFlushType;
541 /** Flush type to use for INVEPT. */
542 VMXTLBFLUSHEPT enmTlbFlushEpt;
543 /** Flush type to use for INVVPID. */
544 VMXTLBFLUSHVPID enmTlbFlushVpid;
545
546 /** Pause-loop exiting (PLE) gap in ticks. */
547 uint32_t cPleGapTicks;
548 /** Pause-loop exiting (PLE) window in ticks. */
549 uint32_t cPleWindowTicks;
550 uint32_t u32Alignment0;
551
552 /** Host CR4 value (set by ring-0 VMX init) */
553 uint64_t u64HostCr4;
554 /** Host SMM monitor control (set by ring-0 VMX init) */
555 uint64_t u64HostSmmMonitorCtl;
556 /** Host EFER value (set by ring-0 VMX init) */
557 uint64_t u64HostMsrEfer;
558 /** Whether the CPU supports VMCS fields for swapping EFER. */
559 bool fSupportsVmcsEfer;
560 uint8_t u8Alignment2[7];
561
562 /** VMX MSR values. */
563 VMXMSRS Msrs;
564
565 /** Host-physical address for a failing VMXON instruction. */
566 RTHCPHYS HCPhysVmxEnableError;
567 } vmx;
568
569 struct
570 {
571 /** Set by the ring-0 side of HM to indicate SVM is supported by the
572 * CPU. */
573 bool fSupported;
574 /** Set when we've enabled SVM. */
575 bool fEnabled;
576 /** Set if erratum 170 affects the AMD cpu. */
577 bool fAlwaysFlushTLB;
578 /** Set when the hack to ignore VERR_SVM_IN_USE is active. */
579 bool fIgnoreInUseError;
580 /** Whether to use virtualized VMSAVE/VMLOAD feature. */
581 bool fVirtVmsaveVmload;
582 /** Whether to use virtual GIF feature. */
583 bool fVGif;
584 uint8_t u8Alignment0[2];
585
586 /** Physical address of the IO bitmap (12kb). */
587 RTHCPHYS HCPhysIOBitmap;
588 /** R0 memory object for the IO bitmap (12kb). */
589 RTR0MEMOBJ hMemObjIOBitmap;
590 /** Virtual address of the IO bitmap. */
591 R0PTRTYPE(void *) pvIOBitmap;
592
593 /* HWCR MSR (for diagnostics) */
594 uint64_t u64MsrHwcr;
595
596 /** SVM revision. */
597 uint32_t u32Rev;
598 /** SVM feature bits from cpuid 0x8000000a */
599 uint32_t u32Features;
600
601 /** Pause filter counter. */
602 uint16_t cPauseFilter;
603 /** Pause filter treshold in ticks. */
604 uint16_t cPauseFilterThresholdTicks;
605 uint32_t u32Alignment0;
606 } svm;
607
608 /**
609 * AVL tree with all patches (active or disabled) sorted by guest instruction
610 * address.
611 */
612 AVLOU32TREE PatchTree;
613 uint32_t cPatches;
614 HMTPRPATCH aPatches[64];
615
616 /** Last recorded error code during HM ring-0 init. */
617 int32_t rcInit;
618
619 /** HMR0Init was run */
620 bool fHMR0Init;
621 bool u8Alignment1[3];
622
623 STAMCOUNTER StatTprPatchSuccess;
624 STAMCOUNTER StatTprPatchFailure;
625 STAMCOUNTER StatTprReplaceSuccessCr8;
626 STAMCOUNTER StatTprReplaceSuccessVmc;
627 STAMCOUNTER StatTprReplaceFailure;
628} HM;
629/** Pointer to HM VM instance data. */
630typedef HM *PHM;
631
632AssertCompileMemberAlignment(HM, StatTprPatchSuccess, 8);
633
634/* Maximum number of cached entries. */
635#define VMX_VMCS_CACHE_MAX_ENTRY 128
636
637/**
638 * Cache of a VMCS for batch reads or writes.
639 */
640typedef struct VMXVMCSCACHE
641{
642#ifdef VBOX_WITH_CRASHDUMP_MAGIC
643 /* Magic marker for searching in crash dumps. */
644 uint8_t aMagic[16];
645 uint64_t uMagic;
646 uint64_t u64TimeEntry;
647 uint64_t u64TimeSwitch;
648 uint64_t cResume;
649 uint64_t interPD;
650 uint64_t pSwitcher;
651 uint32_t uPos;
652 uint32_t idCpu;
653#endif
654 /* CR2 is saved here for EPT syncing. */
655 uint64_t cr2;
656 struct
657 {
658 uint32_t cValidEntries;
659 uint32_t uAlignment;
660 uint32_t aField[VMX_VMCS_CACHE_MAX_ENTRY];
661 uint64_t aFieldVal[VMX_VMCS_CACHE_MAX_ENTRY];
662 } Write;
663 struct
664 {
665 uint32_t cValidEntries;
666 uint32_t uAlignment;
667 uint32_t aField[VMX_VMCS_CACHE_MAX_ENTRY];
668 uint64_t aFieldVal[VMX_VMCS_CACHE_MAX_ENTRY];
669 } Read;
670#ifdef VBOX_STRICT
671 struct
672 {
673 RTHCPHYS HCPhysCpuPage;
674 RTHCPHYS HCPhysVmcs;
675 RTGCPTR pCache;
676 RTGCPTR pCtx;
677 } TestIn;
678 struct
679 {
680 RTHCPHYS HCPhysVmcs;
681 RTGCPTR pCache;
682 RTGCPTR pCtx;
683 uint64_t eflags;
684 uint64_t cr8;
685 } TestOut;
686 struct
687 {
688 uint64_t param1;
689 uint64_t param2;
690 uint64_t param3;
691 uint64_t param4;
692 } ScratchPad;
693#endif
694} VMXVMCSCACHE;
695/** Pointer to VMXVMCSCACHE. */
696typedef VMXVMCSCACHE *PVMXVMCSCACHE;
697AssertCompileSizeAlignment(VMXVMCSCACHE, 8);
698
699/**
700 * VMX StartVM function.
701 *
702 * @returns VBox status code (no informational stuff).
703 * @param fResume Whether to use VMRESUME (true) or VMLAUNCH (false).
704 * @param pCtx The CPU register context.
705 * @param pVmcsCache The VMCS batch cache.
706 * @param pVM Pointer to the cross context VM structure.
707 * @param pVCpu Pointer to the cross context per-CPU structure.
708 */
709typedef DECLCALLBACK(int) FNHMVMXSTARTVM(RTHCUINT fResume, PCPUMCTX pCtx, PVMXVMCSCACHE pVmcsCache, PVM pVM, PVMCPU pVCpu);
710/** Pointer to a VMX StartVM function. */
711typedef R0PTRTYPE(FNHMVMXSTARTVM *) PFNHMVMXSTARTVM;
712
713/** SVM VMRun function. */
714typedef DECLCALLBACK(int) FNHMSVMVMRUN(RTHCPHYS pVmcbHostPhys, RTHCPHYS pVmcbPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu);
715/** Pointer to a SVM VMRun function. */
716typedef R0PTRTYPE(FNHMSVMVMRUN *) PFNHMSVMVMRUN;
717
718/**
719 * VMX VMCS information.
720 *
721 * This structure provides information maintained for and during the executing of a
722 * guest (or nested-guest) VMCS (VM control structure) using hardware-assisted VMX.
723 */
724typedef struct VMXVMCSINFO
725{
726 /** @name VMLAUNCH/VMRESUME information.
727 * @{ */
728 /** Ring-0 pointer to the hardware-assisted VMX execution function. */
729 PFNHMVMXSTARTVM pfnStartVM;
730#if HC_ARCH_BITS == 32
731 uint32_t u32Alignment0;
732#endif
733 /** @} */
734
735 /** @name VMCS and related data structures.
736 * @{ */
737 /** Host-physical address of the VMCS. */
738 RTHCPHYS HCPhysVmcs;
739 /** R0 memory object for the VMCS. */
740 RTR0MEMOBJ hMemObjVmcs;
741 /** Host-virtual address of the VMCS. */
742 R0PTRTYPE(void *) pvVmcs;
743
744 /** Host-physical address of the virtual APIC page. */
745 RTHCPHYS HCPhysVirtApic;
746 /** Alignment. */
747 R0PTRTYPE(void *) pvAlignment0;
748 /** Host-virtual address of the virtual-APIC page. */
749 R0PTRTYPE(uint8_t *) pbVirtApic;
750
751 /** Host-physical address of the MSR bitmap. */
752 RTHCPHYS HCPhysMsrBitmap;
753 /** R0 memory object for the MSR bitmap. */
754 RTR0MEMOBJ hMemObjMsrBitmap;
755 /** Host-virtual address of the MSR bitmap. */
756 R0PTRTYPE(void *) pvMsrBitmap;
757
758 /** Host-physical address of the VM-entry MSR-load area. */
759 RTHCPHYS HCPhysGuestMsrLoad;
760 /** R0 memory object of the VM-entry MSR-load area. */
761 RTR0MEMOBJ hMemObjGuestMsrLoad;
762 /** Host-virtual address of the VM-entry MSR-load area. */
763 R0PTRTYPE(void *) pvGuestMsrLoad;
764
765 /** Host-physical address of the VM-exit MSR-store area. */
766 RTHCPHYS HCPhysGuestMsrStore;
767 /** R0 memory object of the VM-exit MSR-store area. */
768 RTR0MEMOBJ hMemObjGuestMsrStore;
769 /** Host-virtual address of the VM-exit MSR-store area. */
770 R0PTRTYPE(void *) pvGuestMsrStore;
771
772 /** Host-physical address of the VM-exit MSR-load area. */
773 RTHCPHYS HCPhysHostMsrLoad;
774 /** R0 memory object for the VM-exit MSR-load area. */
775 RTR0MEMOBJ hMemObjHostMsrLoad;
776 /** Host-virtual address of the VM-exit MSR-load area. */
777 R0PTRTYPE(void *) pvHostMsrLoad;
778
779 /** Host-physical address of the EPTP. */
780 RTHCPHYS HCPhysEPTP;
781 /** Number of guest MSRs in the VM-entry MSR-load area. */
782 uint32_t cEntryMsrLoad;
783 /** Number of guest MSRs in the VM-exit MSR-store area. */
784 uint32_t cExitMsrStore;
785 /** Number of host MSRs in the VM-exit MSR-load area. */
786 uint32_t cExitMsrLoad;
787 /** Padding. */
788 uint32_t u32Padding0;
789 /** @} */
790
791 /** @name Auxiliary information.
792 * @{ */
793 /** The VMCS launch state, see VMX_V_VMCS_LAUNCH_STATE_XXX. */
794 uint32_t fVmcsState;
795 /** Set if guest was executing in real mode (extra checks). */
796 bool fWasInRealMode;
797 /** Set if the guest switched to 64-bit mode on a 32-bit host. */
798 bool fSwitchedTo64on32;
799 /** Padding. */
800 bool afPadding0[2];
801 /** @} */
802
803 /** @name Cache of execution related VMCS fields.
804 * @{ */
805 /** Pin-based VM-execution controls. */
806 uint32_t u32PinCtls;
807 /** Processor-based VM-execution controls. */
808 uint32_t u32ProcCtls;
809 /** Secondary processor-based VM-execution controls. */
810 uint32_t u32ProcCtls2;
811 /** VM-entry controls. */
812 uint32_t u32EntryCtls;
813 /** VM-exit controls. */
814 uint32_t u32ExitCtls;
815 /** Exception bitmap. */
816 uint32_t u32XcptBitmap;
817 /** CR0 guest/host mask. */
818 uint64_t u64Cr0Mask;
819 /** CR4 guest/host mask. */
820 uint64_t u64Cr4Mask;
821 /** Page-fault exception error-code mask. */
822 uint32_t u32XcptPFMask;
823 /** Page-fault exception error-code match. */
824 uint32_t u32XcptPFMatch;
825 /** TSC offset. */
826 uint64_t u64TscOffset;
827 /** VMCS link pointer. */
828 uint64_t u64VmcsLinkPtr;
829 /** @} */
830
831 /** @name Real-mode emulation state.
832 * @{ */
833 struct
834 {
835 X86DESCATTR AttrCS;
836 X86DESCATTR AttrDS;
837 X86DESCATTR AttrES;
838 X86DESCATTR AttrFS;
839 X86DESCATTR AttrGS;
840 X86DESCATTR AttrSS;
841 X86EFLAGS Eflags;
842 bool fRealOnV86Active;
843 bool afPadding1[3];
844 } RealMode;
845 /** @} */
846
847 /** Padding. */
848 uint64_t au64Padding[2];
849} VMXVMCSINFO;
850/** Pointer to a VMXVMCSINFO struct. */
851typedef VMXVMCSINFO *PVMXVMCSINFO;
852/** Pointer to a const VMXVMCSINFO struct. */
853typedef const VMXVMCSINFO *PCVMXVMCSINFO;
854AssertCompileSizeAlignment(VMXVMCSINFO, 8);
855AssertCompileMemberAlignment(VMXVMCSINFO, fVmcsState, 8);
856AssertCompileMemberAlignment(VMXVMCSINFO, u32PinCtls, 8);
857AssertCompileMemberAlignment(VMXVMCSINFO, u64VmcsLinkPtr, 8);
858
859/**
860 * HM VMCPU Instance data.
861 *
862 * Note! If you change members of this struct, make sure to check if the
863 * assembly counterpart in HMInternal.mac needs to be updated as well.
864 */
865typedef struct HMCPU
866{
867 /** Set when the TLB has been checked until we return from the world switch. */
868 bool volatile fCheckedTLBFlush;
869 /** Set if we need to flush the TLB during the world switch. */
870 bool fForceTLBFlush;
871 /** Set when we're using VT-x or AMD-V at that moment. */
872 bool fActive;
873 /** Whether we've completed the inner HM leave function. */
874 bool fLeaveDone;
875 /** Whether we're using the hyper DR7 or guest DR7. */
876 bool fUsingHyperDR7;
877 /** Set if XCR0 needs to be saved/restored when entering/exiting guest code
878 * execution. */
879 bool fLoadSaveGuestXcr0;
880
881 /** Whether we should use the debug loop because of single stepping or special
882 * debug breakpoints / events are armed. */
883 bool fUseDebugLoop;
884 /** Whether we are currently executing in the debug loop.
885 * Mainly for assertions. */
886 bool fUsingDebugLoop;
887 /** Set if we using the debug loop and wish to intercept RDTSC. */
888 bool fDebugWantRdTscExit;
889 /** Whether we're executing a single instruction. */
890 bool fSingleInstruction;
891 /** Set if we need to clear the trap flag because of single stepping. */
892 bool fClearTrapFlag;
893
894 /** Whether \#UD needs to be intercepted (required by certain GIM providers). */
895 bool fGIMTrapXcptUD;
896 /** Whether \#GP needs to be intercept for mesa driver workaround. */
897 bool fTrapXcptGpForLovelyMesaDrv;
898 uint8_t u8Alignment0[3];
899
900 /** World switch exit counter. */
901 uint32_t volatile cWorldSwitchExits;
902 /** The last CPU we were executing code on (NIL_RTCPUID for the first time). */
903 RTCPUID idLastCpu;
904 /** TLB flush count. */
905 uint32_t cTlbFlushes;
906 /** Current ASID in use by the VM. */
907 uint32_t uCurrentAsid;
908 /** An additional error code used for some gurus. */
909 uint32_t u32HMError;
910 /** The last exit-to-ring-3 reason. */
911 int32_t rcLastExitToR3;
912 /** CPU-context changed flags (see HM_CHANGED_xxx). */
913 uint64_t fCtxChanged;
914 /** Host's TSC_AUX MSR (used when RDTSCP doesn't cause VM-exits). */
915 uint64_t u64HostTscAux; /** @todo r=ramshankar: Can be removed and put in SVMTRANSIENT instead! */
916
917 union /* no tag! */
918 {
919 /** VT-x data. */
920 struct
921 {
922 /** @name Guest information.
923 * @{ */
924 /** Guest VMCS information. */
925 VMXVMCSINFO VmcsInfo;
926 /** Nested-guest VMCS information. */
927 VMXVMCSINFO VmcsInfoNstGst;
928 /** Whether the nested-guest VMCS was the last current VMCS. */
929 bool fSwitchedToNstGstVmcs;
930 /** Whether the static guest VMCS controls has been merged with the
931 * nested-guest VMCS controls. */
932 bool fMergedNstGstCtls;
933 /** Alignment. */
934 bool afAlignment0[6];
935 /** Cached guest APIC-base MSR for identifying when to map the APIC-access page. */
936 uint64_t u64GstMsrApicBase;
937 /** VMCS cache for batched vmread/vmwrites. */
938 VMXVMCSCACHE VmcsCache;
939 /** @} */
940
941 /** @name Host information.
942 * @{ */
943 /** Host LSTAR MSR to restore lazily while leaving VT-x. */
944 uint64_t u64HostMsrLStar;
945 /** Host STAR MSR to restore lazily while leaving VT-x. */
946 uint64_t u64HostMsrStar;
947 /** Host SF_MASK MSR to restore lazily while leaving VT-x. */
948 uint64_t u64HostMsrSfMask;
949 /** Host KernelGS-Base MSR to restore lazily while leaving VT-x. */
950 uint64_t u64HostMsrKernelGsBase;
951 /** The mask of lazy MSRs swap/restore state, see VMX_LAZY_MSRS_XXX. */
952 uint32_t fLazyMsrs;
953 /** Whether the host MSR values are up-to-date in the auto-load/store MSR area. */
954 bool fUpdatedHostAutoMsrs;
955 /** Alignment. */
956 uint8_t au8Alignment0[3];
957 /** Which host-state bits to restore before being preempted. */
958 uint32_t fRestoreHostFlags;
959 /** Alignment. */
960 uint32_t u32Alignment0;
961 /** The host-state restoration structure. */
962 VMXRESTOREHOST RestoreHost;
963 /** @} */
964
965 /** @name Error reporting and diagnostics.
966 * @{ */
967 /** VT-x error-reporting (mainly for ring-3 propagation). */
968 struct
969 {
970 RTHCPHYS HCPhysCurrentVmcs;
971 uint32_t u32VmcsRev;
972 uint32_t u32InstrError;
973 uint32_t u32ExitReason;
974 uint32_t u32Alignment0;
975 RTCPUID idEnteredCpu;
976 RTCPUID idCurrentCpu;
977 } LastError;
978 /** @} */
979 } vmx;
980
981 /** SVM data. */
982 struct
983 {
984 /** Ring 0 handlers for VT-x. */
985 PFNHMSVMVMRUN pfnVMRun;
986#if HC_ARCH_BITS == 32
987 uint32_t u32Alignment0;
988#endif
989
990 /** Physical address of the host VMCB which holds additional host-state. */
991 RTHCPHYS HCPhysVmcbHost;
992 /** R0 memory object for the host VMCB which holds additional host-state. */
993 RTR0MEMOBJ hMemObjVmcbHost;
994 /** Padding. */
995 R0PTRTYPE(void *) pvPadding;
996
997 /** Physical address of the guest VMCB. */
998 RTHCPHYS HCPhysVmcb;
999 /** R0 memory object for the guest VMCB. */
1000 RTR0MEMOBJ hMemObjVmcb;
1001 /** Pointer to the guest VMCB. */
1002 R0PTRTYPE(PSVMVMCB) pVmcb;
1003
1004 /** Physical address of the MSR bitmap (8 KB). */
1005 RTHCPHYS HCPhysMsrBitmap;
1006 /** R0 memory object for the MSR bitmap (8 KB). */
1007 RTR0MEMOBJ hMemObjMsrBitmap;
1008 /** Pointer to the MSR bitmap. */
1009 R0PTRTYPE(void *) pvMsrBitmap;
1010
1011 /** Whether VTPR with V_INTR_MASKING set is in effect, indicating
1012 * we should check if the VTPR changed on every VM-exit. */
1013 bool fSyncVTpr;
1014 uint8_t au8Alignment0[7];
1015
1016 /** Cache of the nested-guest's VMCB fields that we modify in order to run the
1017 * nested-guest using AMD-V. This will be restored on \#VMEXIT. */
1018 SVMNESTEDVMCBCACHE NstGstVmcbCache;
1019 } svm;
1020 } HM_UNION_NM(u);
1021
1022 /** Event injection state. */
1023 HMEVENT Event;
1024
1025 /** The PAE PDPEs used with Nested Paging (only valid when
1026 * VMCPU_FF_HM_UPDATE_PAE_PDPES is set). */
1027 X86PDPE aPdpes[4];
1028
1029 /** Current shadow paging mode for updating CR4. */
1030 PGMMODE enmShadowMode;
1031
1032 /** The CPU ID of the CPU currently owning the VMCS. Set in
1033 * HMR0Enter and cleared in HMR0Leave. */
1034 RTCPUID idEnteredCpu;
1035
1036 /** For saving stack space, the disassembler state is allocated here instead of
1037 * on the stack. */
1038 DISCPUSTATE DisState;
1039
1040 STAMPROFILEADV StatEntry;
1041 STAMPROFILEADV StatPreExit;
1042 STAMPROFILEADV StatExitHandling;
1043 STAMPROFILEADV StatExitIO;
1044 STAMPROFILEADV StatExitMovCRx;
1045 STAMPROFILEADV StatExitXcptNmi;
1046 STAMPROFILEADV StatImportGuestState;
1047 STAMPROFILEADV StatExportGuestState;
1048 STAMPROFILEADV StatLoadGuestFpuState;
1049 STAMPROFILEADV StatInGC;
1050#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1051 STAMPROFILEADV StatWorldSwitch3264;
1052#endif
1053 STAMPROFILEADV StatPoke;
1054 STAMPROFILEADV StatSpinPoke;
1055 STAMPROFILEADV StatSpinPokeFailed;
1056
1057 STAMCOUNTER StatInjectInterrupt;
1058 STAMCOUNTER StatInjectXcpt;
1059 STAMCOUNTER StatInjectPendingReflect;
1060 STAMCOUNTER StatInjectPendingInterpret;
1061
1062 STAMCOUNTER StatExitAll;
1063 STAMCOUNTER StatExitShadowNM;
1064 STAMCOUNTER StatExitGuestNM;
1065 STAMCOUNTER StatExitShadowPF; /**< Misleading, currently used for MMIO \#PFs as well. */
1066 STAMCOUNTER StatExitShadowPFEM;
1067 STAMCOUNTER StatExitGuestPF;
1068 STAMCOUNTER StatExitGuestUD;
1069 STAMCOUNTER StatExitGuestSS;
1070 STAMCOUNTER StatExitGuestNP;
1071 STAMCOUNTER StatExitGuestTS;
1072 STAMCOUNTER StatExitGuestGP;
1073 STAMCOUNTER StatExitGuestDE;
1074 STAMCOUNTER StatExitGuestDB;
1075 STAMCOUNTER StatExitGuestMF;
1076 STAMCOUNTER StatExitGuestBP;
1077 STAMCOUNTER StatExitGuestXF;
1078 STAMCOUNTER StatExitGuestXcpUnk;
1079 STAMCOUNTER StatExitDRxWrite;
1080 STAMCOUNTER StatExitDRxRead;
1081 STAMCOUNTER StatExitCR0Read;
1082 STAMCOUNTER StatExitCR2Read;
1083 STAMCOUNTER StatExitCR3Read;
1084 STAMCOUNTER StatExitCR4Read;
1085 STAMCOUNTER StatExitCR8Read;
1086 STAMCOUNTER StatExitCR0Write;
1087 STAMCOUNTER StatExitCR2Write;
1088 STAMCOUNTER StatExitCR3Write;
1089 STAMCOUNTER StatExitCR4Write;
1090 STAMCOUNTER StatExitCR8Write;
1091 STAMCOUNTER StatExitRdmsr;
1092 STAMCOUNTER StatExitWrmsr;
1093 STAMCOUNTER StatExitClts;
1094 STAMCOUNTER StatExitXdtrAccess;
1095 STAMCOUNTER StatExitLmsw;
1096 STAMCOUNTER StatExitIOWrite;
1097 STAMCOUNTER StatExitIORead;
1098 STAMCOUNTER StatExitIOStringWrite;
1099 STAMCOUNTER StatExitIOStringRead;
1100 STAMCOUNTER StatExitIntWindow;
1101 STAMCOUNTER StatExitExtInt;
1102 STAMCOUNTER StatExitHostNmiInGC;
1103 STAMCOUNTER StatExitPreemptTimer;
1104 STAMCOUNTER StatExitTprBelowThreshold;
1105 STAMCOUNTER StatExitTaskSwitch;
1106 STAMCOUNTER StatExitApicAccess;
1107 STAMCOUNTER StatExitReasonNpf;
1108
1109 STAMCOUNTER StatNestedExitReasonNpf;
1110
1111 STAMCOUNTER StatFlushPage;
1112 STAMCOUNTER StatFlushPageManual;
1113 STAMCOUNTER StatFlushPhysPageManual;
1114 STAMCOUNTER StatFlushTlb;
1115 STAMCOUNTER StatFlushTlbManual;
1116 STAMCOUNTER StatFlushTlbWorldSwitch;
1117 STAMCOUNTER StatNoFlushTlbWorldSwitch;
1118 STAMCOUNTER StatFlushEntire;
1119 STAMCOUNTER StatFlushAsid;
1120 STAMCOUNTER StatFlushNestedPaging;
1121 STAMCOUNTER StatFlushTlbInvlpgVirt;
1122 STAMCOUNTER StatFlushTlbInvlpgPhys;
1123 STAMCOUNTER StatTlbShootdown;
1124 STAMCOUNTER StatTlbShootdownFlush;
1125
1126 STAMCOUNTER StatSwitchPendingHostIrq;
1127 STAMCOUNTER StatSwitchTprMaskedIrq;
1128 STAMCOUNTER StatSwitchGuestIrq;
1129 STAMCOUNTER StatSwitchHmToR3FF;
1130 STAMCOUNTER StatSwitchExitToR3;
1131 STAMCOUNTER StatSwitchLongJmpToR3;
1132 STAMCOUNTER StatSwitchMaxResumeLoops;
1133 STAMCOUNTER StatSwitchHltToR3;
1134 STAMCOUNTER StatSwitchApicAccessToR3;
1135 STAMCOUNTER StatSwitchPreempt;
1136 STAMCOUNTER StatSwitchPreemptExportHostState;
1137
1138 STAMCOUNTER StatTscParavirt;
1139 STAMCOUNTER StatTscOffset;
1140 STAMCOUNTER StatTscIntercept;
1141
1142 STAMCOUNTER StatDRxArmed;
1143 STAMCOUNTER StatDRxContextSwitch;
1144 STAMCOUNTER StatDRxIoCheck;
1145
1146 STAMCOUNTER StatExportMinimal;
1147 STAMCOUNTER StatExportFull;
1148 STAMCOUNTER StatLoadGuestFpu;
1149
1150 STAMCOUNTER StatVmxCheckBadRmSelBase;
1151 STAMCOUNTER StatVmxCheckBadRmSelLimit;
1152 STAMCOUNTER StatVmxCheckBadRmSelAttr;
1153 STAMCOUNTER StatVmxCheckBadV86SelBase;
1154 STAMCOUNTER StatVmxCheckBadV86SelLimit;
1155 STAMCOUNTER StatVmxCheckBadV86SelAttr;
1156 STAMCOUNTER StatVmxCheckRmOk;
1157 STAMCOUNTER StatVmxCheckBadSel;
1158 STAMCOUNTER StatVmxCheckBadRpl;
1159 STAMCOUNTER StatVmxCheckPmOk;
1160
1161#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1162 STAMCOUNTER StatFpu64SwitchBack;
1163 STAMCOUNTER StatDebug64SwitchBack;
1164#endif
1165#ifdef VBOX_WITH_STATISTICS
1166 R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
1167 R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
1168 R3PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqs;
1169 R0PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqsR0;
1170 R3PTRTYPE(PSTAMCOUNTER) paStatNestedExitReason;
1171 R0PTRTYPE(PSTAMCOUNTER) paStatNestedExitReasonR0;
1172#endif
1173#ifdef HM_PROFILE_EXIT_DISPATCH
1174 STAMPROFILEADV StatExitDispatch;
1175#endif
1176} HMCPU;
1177/** Pointer to HM VMCPU instance data. */
1178typedef HMCPU *PHMCPU;
1179AssertCompileMemberAlignment(HMCPU, cWorldSwitchExits, 4);
1180AssertCompileMemberAlignment(HMCPU, fCtxChanged, 8);
1181AssertCompileMemberAlignment(HMCPU, HM_UNION_NM(u.) vmx, 8);
1182AssertCompileMemberAlignment(HMCPU, HM_UNION_NM(u.) svm, 8);
1183AssertCompileMemberAlignment(HMCPU, Event, 8);
1184
1185#ifdef IN_RING0
1186VMMR0_INT_DECL(PHMPHYSCPU) hmR0GetCurrentCpu(void);
1187VMMR0_INT_DECL(int) hmR0EnterCpu(PVMCPU pVCpu);
1188
1189# ifdef VBOX_STRICT
1190VMMR0_INT_DECL(void) hmR0DumpRegs(PVMCPU pVCpu);
1191VMMR0_INT_DECL(void) hmR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg);
1192# endif
1193
1194# ifdef VBOX_WITH_KERNEL_USING_XMM
1195DECLASM(int) hmR0VMXStartVMWrapXMM(RTHCUINT fResume, PCPUMCTX pCtx, PVMXVMCSCACHE pVmcsCache, PVM pVM,
1196 PVMCPU pVCpu, PFNHMVMXSTARTVM pfnStartVM);
1197DECLASM(int) hmR0SVMRunWrapXMM(RTHCPHYS pVmcbHostPhys, RTHCPHYS pVmcbPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu,
1198 PFNHMSVMVMRUN pfnVMRun);
1199# endif
1200DECLASM(void) hmR0MdsClear(void);
1201#endif /* IN_RING0 */
1202
1203VMM_INT_DECL(int) hmEmulateSvmMovTpr(PVMCPU pVCpu);
1204
1205VMM_INT_DECL(PVMXVMCSINFO) hmGetVmxActiveVmcsInfo(PVMCPU pVCpu);
1206
1207/** @} */
1208
1209RT_C_DECLS_END
1210
1211#endif /* !VMM_INCLUDED_SRC_include_HMInternal_h */
1212
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