VirtualBox

source: vbox/trunk/src/VBox/VMM/include/HMInternal.h@ 80143

Last change on this file since 80143 was 80080, checked in by vboxsync, 6 years ago

VMM: Kicking out raw-mode and 32-bit hosts - HM, VMMSWITCHER, ++. bugref:9517 bugref:9511
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File size: 53.2 KB
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1/* $Id: HMInternal.h 80080 2019-07-31 16:12:31Z vboxsync $ */
2/** @file
3 * HM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef VMM_INCLUDED_SRC_include_HMInternal_h
19#define VMM_INCLUDED_SRC_include_HMInternal_h
20#ifndef RT_WITHOUT_PRAGMA_ONCE
21# pragma once
22#endif
23
24#include <VBox/cdefs.h>
25#include <VBox/types.h>
26#include <VBox/vmm/stam.h>
27#include <VBox/dis.h>
28#include <VBox/vmm/hm.h>
29#include <VBox/vmm/hm_vmx.h>
30#include <VBox/vmm/hm_svm.h>
31#include <VBox/vmm/pgm.h>
32#include <VBox/vmm/cpum.h>
33#include <VBox/vmm/trpm.h>
34#include <iprt/memobj.h>
35#include <iprt/cpuset.h>
36#include <iprt/mp.h>
37#include <iprt/avl.h>
38#include <iprt/string.h>
39
40#if HC_ARCH_BITS == 32
41# error "32-bit hosts are no longer supported. Go back to 6.0 or earlier!"
42#endif
43
44/** @def HM_PROFILE_EXIT_DISPATCH
45 * Enables profiling of the VM exit handler dispatching. */
46#if 0 || defined(DOXYGEN_RUNNING)
47# define HM_PROFILE_EXIT_DISPATCH
48#endif
49
50RT_C_DECLS_BEGIN
51
52
53/** @defgroup grp_hm_int Internal
54 * @ingroup grp_hm
55 * @internal
56 * @{
57 */
58
59/** @name HM_CHANGED_XXX
60 * HM CPU-context changed flags.
61 *
62 * These flags are used to keep track of which registers and state has been
63 * modified since they were imported back into the guest-CPU context.
64 *
65 * @{
66 */
67#define HM_CHANGED_HOST_CONTEXT UINT64_C(0x0000000000000001)
68#define HM_CHANGED_GUEST_RIP UINT64_C(0x0000000000000004)
69#define HM_CHANGED_GUEST_RFLAGS UINT64_C(0x0000000000000008)
70
71#define HM_CHANGED_GUEST_RAX UINT64_C(0x0000000000000010)
72#define HM_CHANGED_GUEST_RCX UINT64_C(0x0000000000000020)
73#define HM_CHANGED_GUEST_RDX UINT64_C(0x0000000000000040)
74#define HM_CHANGED_GUEST_RBX UINT64_C(0x0000000000000080)
75#define HM_CHANGED_GUEST_RSP UINT64_C(0x0000000000000100)
76#define HM_CHANGED_GUEST_RBP UINT64_C(0x0000000000000200)
77#define HM_CHANGED_GUEST_RSI UINT64_C(0x0000000000000400)
78#define HM_CHANGED_GUEST_RDI UINT64_C(0x0000000000000800)
79#define HM_CHANGED_GUEST_R8_R15 UINT64_C(0x0000000000001000)
80#define HM_CHANGED_GUEST_GPRS_MASK UINT64_C(0x0000000000001ff0)
81
82#define HM_CHANGED_GUEST_ES UINT64_C(0x0000000000002000)
83#define HM_CHANGED_GUEST_CS UINT64_C(0x0000000000004000)
84#define HM_CHANGED_GUEST_SS UINT64_C(0x0000000000008000)
85#define HM_CHANGED_GUEST_DS UINT64_C(0x0000000000010000)
86#define HM_CHANGED_GUEST_FS UINT64_C(0x0000000000020000)
87#define HM_CHANGED_GUEST_GS UINT64_C(0x0000000000040000)
88#define HM_CHANGED_GUEST_SREG_MASK UINT64_C(0x000000000007e000)
89
90#define HM_CHANGED_GUEST_GDTR UINT64_C(0x0000000000080000)
91#define HM_CHANGED_GUEST_IDTR UINT64_C(0x0000000000100000)
92#define HM_CHANGED_GUEST_LDTR UINT64_C(0x0000000000200000)
93#define HM_CHANGED_GUEST_TR UINT64_C(0x0000000000400000)
94#define HM_CHANGED_GUEST_TABLE_MASK UINT64_C(0x0000000000780000)
95
96#define HM_CHANGED_GUEST_CR0 UINT64_C(0x0000000000800000)
97#define HM_CHANGED_GUEST_CR2 UINT64_C(0x0000000001000000)
98#define HM_CHANGED_GUEST_CR3 UINT64_C(0x0000000002000000)
99#define HM_CHANGED_GUEST_CR4 UINT64_C(0x0000000004000000)
100#define HM_CHANGED_GUEST_CR_MASK UINT64_C(0x0000000007800000)
101
102#define HM_CHANGED_GUEST_APIC_TPR UINT64_C(0x0000000008000000)
103#define HM_CHANGED_GUEST_EFER_MSR UINT64_C(0x0000000010000000)
104
105#define HM_CHANGED_GUEST_DR0_DR3 UINT64_C(0x0000000020000000)
106#define HM_CHANGED_GUEST_DR6 UINT64_C(0x0000000040000000)
107#define HM_CHANGED_GUEST_DR7 UINT64_C(0x0000000080000000)
108#define HM_CHANGED_GUEST_DR_MASK UINT64_C(0x00000000e0000000)
109
110#define HM_CHANGED_GUEST_X87 UINT64_C(0x0000000100000000)
111#define HM_CHANGED_GUEST_SSE_AVX UINT64_C(0x0000000200000000)
112#define HM_CHANGED_GUEST_OTHER_XSAVE UINT64_C(0x0000000400000000)
113#define HM_CHANGED_GUEST_XCRx UINT64_C(0x0000000800000000)
114
115#define HM_CHANGED_GUEST_KERNEL_GS_BASE UINT64_C(0x0000001000000000)
116#define HM_CHANGED_GUEST_SYSCALL_MSRS UINT64_C(0x0000002000000000)
117#define HM_CHANGED_GUEST_SYSENTER_CS_MSR UINT64_C(0x0000004000000000)
118#define HM_CHANGED_GUEST_SYSENTER_EIP_MSR UINT64_C(0x0000008000000000)
119#define HM_CHANGED_GUEST_SYSENTER_ESP_MSR UINT64_C(0x0000010000000000)
120#define HM_CHANGED_GUEST_SYSENTER_MSR_MASK UINT64_C(0x000001c000000000)
121#define HM_CHANGED_GUEST_TSC_AUX UINT64_C(0x0000020000000000)
122#define HM_CHANGED_GUEST_OTHER_MSRS UINT64_C(0x0000040000000000)
123#define HM_CHANGED_GUEST_ALL_MSRS ( HM_CHANGED_GUEST_EFER \
124 | HM_CHANGED_GUEST_KERNEL_GS_BASE \
125 | HM_CHANGED_GUEST_SYSCALL_MSRS \
126 | HM_CHANGED_GUEST_SYSENTER_MSR_MASK \
127 | HM_CHANGED_GUEST_TSC_AUX \
128 | HM_CHANGED_GUEST_OTHER_MSRS)
129
130#define HM_CHANGED_GUEST_HWVIRT UINT64_C(0x0000080000000000)
131#define HM_CHANGED_GUEST_MASK UINT64_C(0x00000ffffffffffc)
132
133#define HM_CHANGED_KEEPER_STATE_MASK UINT64_C(0xffff000000000000)
134
135#define HM_CHANGED_VMX_XCPT_INTERCEPTS UINT64_C(0x0001000000000000)
136#define HM_CHANGED_VMX_GUEST_AUTO_MSRS UINT64_C(0x0002000000000000)
137#define HM_CHANGED_VMX_GUEST_LAZY_MSRS UINT64_C(0x0004000000000000)
138#define HM_CHANGED_VMX_ENTRY_EXIT_CTLS UINT64_C(0x0008000000000000)
139#define HM_CHANGED_VMX_MASK UINT64_C(0x000f000000000000)
140#define HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE ( HM_CHANGED_GUEST_DR_MASK \
141 | HM_CHANGED_VMX_GUEST_LAZY_MSRS)
142
143#define HM_CHANGED_SVM_XCPT_INTERCEPTS UINT64_C(0x0001000000000000)
144#define HM_CHANGED_SVM_MASK UINT64_C(0x0001000000000000)
145#define HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE HM_CHANGED_GUEST_DR_MASK
146
147#define HM_CHANGED_ALL_GUEST ( HM_CHANGED_GUEST_MASK \
148 | HM_CHANGED_KEEPER_STATE_MASK)
149
150/** Mask of what state might have changed when IEM raised an exception.
151 * This is a based on IEM_CPUMCTX_EXTRN_XCPT_MASK. */
152#define HM_CHANGED_RAISED_XCPT_MASK ( HM_CHANGED_GUEST_GPRS_MASK \
153 | HM_CHANGED_GUEST_RIP \
154 | HM_CHANGED_GUEST_RFLAGS \
155 | HM_CHANGED_GUEST_SS \
156 | HM_CHANGED_GUEST_CS \
157 | HM_CHANGED_GUEST_CR0 \
158 | HM_CHANGED_GUEST_CR3 \
159 | HM_CHANGED_GUEST_CR4 \
160 | HM_CHANGED_GUEST_APIC_TPR \
161 | HM_CHANGED_GUEST_EFER_MSR \
162 | HM_CHANGED_GUEST_DR7 \
163 | HM_CHANGED_GUEST_CR2 \
164 | HM_CHANGED_GUEST_SREG_MASK \
165 | HM_CHANGED_GUEST_TABLE_MASK)
166
167#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
168/** Mask of what state might have changed when \#VMEXIT is emulated. */
169# define HM_CHANGED_SVM_VMEXIT_MASK ( HM_CHANGED_GUEST_RSP \
170 | HM_CHANGED_GUEST_RAX \
171 | HM_CHANGED_GUEST_RIP \
172 | HM_CHANGED_GUEST_RFLAGS \
173 | HM_CHANGED_GUEST_CS \
174 | HM_CHANGED_GUEST_SS \
175 | HM_CHANGED_GUEST_DS \
176 | HM_CHANGED_GUEST_ES \
177 | HM_CHANGED_GUEST_GDTR \
178 | HM_CHANGED_GUEST_IDTR \
179 | HM_CHANGED_GUEST_CR_MASK \
180 | HM_CHANGED_GUEST_EFER_MSR \
181 | HM_CHANGED_GUEST_DR6 \
182 | HM_CHANGED_GUEST_DR7 \
183 | HM_CHANGED_GUEST_OTHER_MSRS \
184 | HM_CHANGED_GUEST_HWVIRT \
185 | HM_CHANGED_SVM_MASK \
186 | HM_CHANGED_GUEST_APIC_TPR)
187
188/** Mask of what state might have changed when VMRUN is emulated. */
189# define HM_CHANGED_SVM_VMRUN_MASK HM_CHANGED_SVM_VMEXIT_MASK
190#endif
191#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
192/** Mask of what state might have changed when VM-exit is emulated.
193 *
194 * This is currently unused, but keeping it here in case we can get away a bit more
195 * fine-grained state handling.
196 *
197 * @note Update IEM_CPUMCTX_EXTRN_VMX_VMEXIT_MASK when this changes. */
198# define HM_CHANGED_VMX_VMEXIT_MASK ( HM_CHANGED_GUEST_CR0 | HM_CHANGED_GUEST_CR3 | HM_CHANGED_GUEST_CR4 \
199 | HM_CHANGED_GUEST_DR7 | HM_CHANGED_GUEST_DR6 \
200 | HM_CHANGED_GUEST_EFER_MSR \
201 | HM_CHANGED_GUEST_SYSENTER_MSR_MASK \
202 | HM_CHANGED_GUEST_OTHER_MSRS /* for PAT MSR */ \
203 | HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RSP | HM_CHANGED_GUEST_RFLAGS \
204 | HM_CHANGED_GUEST_SREG_MASK \
205 | HM_CHANGED_GUEST_TR \
206 | HM_CHANGED_GUEST_LDTR | HM_CHANGED_GUEST_GDTR | HM_CHANGED_GUEST_IDTR \
207 | HM_CHANGED_GUEST_HWVIRT )
208#endif
209/** @} */
210
211/** Maximum number of exit reason statistics counters. */
212#define MAX_EXITREASON_STAT 0x100
213#define MASK_EXITREASON_STAT 0xff
214#define MASK_INJECT_IRQ_STAT 0xff
215
216/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
217#define HM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
218/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
219#define HM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2 * PAGE_SIZE + 1)
220/** Total guest mapped memory needed. */
221#define HM_VTX_TOTAL_DEVHEAP_MEM (HM_EPT_IDENTITY_PG_TABLE_SIZE + HM_VTX_TSS_SIZE)
222
223
224/** @name Macros for enabling and disabling preemption.
225 * These are really just for hiding the RTTHREADPREEMPTSTATE and asserting that
226 * preemption has already been disabled when there is no context hook.
227 * @{ */
228#ifdef VBOX_STRICT
229# define HM_DISABLE_PREEMPT(a_pVCpu) \
230 RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
231 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD) || VMMR0ThreadCtxHookIsEnabled((a_pVCpu))); \
232 RTThreadPreemptDisable(&PreemptStateInternal)
233#else
234# define HM_DISABLE_PREEMPT(a_pVCpu) \
235 RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
236 RTThreadPreemptDisable(&PreemptStateInternal)
237#endif /* VBOX_STRICT */
238#define HM_RESTORE_PREEMPT() do { RTThreadPreemptRestore(&PreemptStateInternal); } while(0)
239/** @} */
240
241
242/** @name HM saved state versions.
243 * @{
244 */
245#define HM_SAVED_STATE_VERSION HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT
246#define HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT 6
247#define HM_SAVED_STATE_VERSION_TPR_PATCHING 5
248#define HM_SAVED_STATE_VERSION_NO_TPR_PATCHING 4
249#define HM_SAVED_STATE_VERSION_2_0_X 3
250/** @} */
251
252
253/**
254 * HM physical (host) CPU information.
255 */
256typedef struct HMPHYSCPU
257{
258 /** The CPU ID. */
259 RTCPUID idCpu;
260 /** The VM_HSAVE_AREA (AMD-V) / VMXON region (Intel) memory backing. */
261 RTR0MEMOBJ hMemObj;
262 /** The physical address of the first page in hMemObj (it's a
263 * physcially contigous allocation if it spans multiple pages). */
264 RTHCPHYS HCPhysMemObj;
265 /** The address of the memory (for pfnEnable). */
266 void *pvMemObj;
267 /** Current ASID (AMD-V) / VPID (Intel). */
268 uint32_t uCurrentAsid;
269 /** TLB flush count. */
270 uint32_t cTlbFlushes;
271 /** Whether to flush each new ASID/VPID before use. */
272 bool fFlushAsidBeforeUse;
273 /** Configured for VT-x or AMD-V. */
274 bool fConfigured;
275 /** Set if the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active. */
276 bool fIgnoreAMDVInUseError;
277 /** In use by our code. (for power suspend) */
278 bool volatile fInUse;
279#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
280 /** Nested-guest union (put data common to SVM/VMX outside the union). */
281 union
282 {
283 /** Nested-guest SVM data. */
284 struct
285 {
286 /** The active nested-guest MSR permission bitmap memory backing. */
287 RTR0MEMOBJ hNstGstMsrpm;
288 /** The physical address of the first page in hNstGstMsrpm (physcially
289 * contiguous allocation). */
290 RTHCPHYS HCPhysNstGstMsrpm;
291 /** The address of the active nested-guest MSRPM. */
292 void *pvNstGstMsrpm;
293 } svm;
294 /** @todo Nested-VMX. */
295 } n;
296#endif
297} HMPHYSCPU;
298/** Pointer to HMPHYSCPU struct. */
299typedef HMPHYSCPU *PHMPHYSCPU;
300/** Pointer to a const HMPHYSCPU struct. */
301typedef const HMPHYSCPU *PCHMPHYSCPU;
302
303/**
304 * TPR-instruction type.
305 */
306typedef enum
307{
308 HMTPRINSTR_INVALID,
309 HMTPRINSTR_READ,
310 HMTPRINSTR_READ_SHR4,
311 HMTPRINSTR_WRITE_REG,
312 HMTPRINSTR_WRITE_IMM,
313 HMTPRINSTR_JUMP_REPLACEMENT,
314 /** The usual 32-bit paranoia. */
315 HMTPRINSTR_32BIT_HACK = 0x7fffffff
316} HMTPRINSTR;
317
318/**
319 * TPR patch information.
320 */
321typedef struct
322{
323 /** The key is the address of patched instruction. (32 bits GC ptr) */
324 AVLOU32NODECORE Core;
325 /** Original opcode. */
326 uint8_t aOpcode[16];
327 /** Instruction size. */
328 uint32_t cbOp;
329 /** Replacement opcode. */
330 uint8_t aNewOpcode[16];
331 /** Replacement instruction size. */
332 uint32_t cbNewOp;
333 /** Instruction type. */
334 HMTPRINSTR enmType;
335 /** Source operand. */
336 uint32_t uSrcOperand;
337 /** Destination operand. */
338 uint32_t uDstOperand;
339 /** Number of times the instruction caused a fault. */
340 uint32_t cFaults;
341 /** Patch address of the jump replacement. */
342 RTGCPTR32 pJumpTarget;
343} HMTPRPATCH;
344/** Pointer to HMTPRPATCH. */
345typedef HMTPRPATCH *PHMTPRPATCH;
346/** Pointer to a const HMTPRPATCH. */
347typedef const HMTPRPATCH *PCHMTPRPATCH;
348
349
350/**
351 * Makes a HMEXITSTAT::uKey value from a program counter and an exit code.
352 *
353 * @returns 64-bit key
354 * @param a_uPC The RIP + CS.BASE value of the exit.
355 * @param a_uExit The exit code.
356 * @todo Add CPL?
357 */
358#define HMEXITSTAT_MAKE_KEY(a_uPC, a_uExit) (((a_uPC) & UINT64_C(0x0000ffffffffffff)) | (uint64_t)(a_uExit) << 48)
359
360typedef struct HMEXITINFO
361{
362 /** See HMEXITSTAT_MAKE_KEY(). */
363 uint64_t uKey;
364 /** Number of recent hits (depreciates with time). */
365 uint32_t volatile cHits;
366 /** The age + lock. */
367 uint16_t volatile uAge;
368 /** Action or action table index. */
369 uint16_t iAction;
370} HMEXITINFO;
371AssertCompileSize(HMEXITINFO, 16); /* Lots of these guys, so don't add any unnecessary stuff! */
372
373typedef struct HMEXITHISTORY
374{
375 /** The exit timestamp. */
376 uint64_t uTscExit;
377 /** The index of the corresponding HMEXITINFO entry.
378 * UINT32_MAX if none (too many collisions, race, whatever). */
379 uint32_t iExitInfo;
380 /** Figure out later, needed for padding now. */
381 uint32_t uSomeClueOrSomething;
382} HMEXITHISTORY;
383
384/**
385 * Switcher function, HC to the special 64-bit RC.
386 *
387 * @param pVM The cross context VM structure.
388 * @param offCpumVCpu Offset from pVM->cpum to pVM->aCpus[idCpu].cpum.
389 * @returns Return code indicating the action to take.
390 */
391typedef DECLCALLBACK(int) FNHMSWITCHERHC(PVM pVM, uint32_t offCpumVCpu);
392/** Pointer to switcher function. */
393typedef FNHMSWITCHERHC *PFNHMSWITCHERHC;
394
395/** @def HM_UNION_NM
396 * For compilers (like DTrace) that does not grok nameless unions, we have a
397 * little hack to make them palatable.
398 */
399/** @def HM_STRUCT_NM
400 * For compilers (like DTrace) that does not grok nameless structs (it is
401 * non-standard C++), we have a little hack to make them palatable.
402 */
403#ifdef VBOX_FOR_DTRACE_LIB
404# define HM_UNION_NM(a_Nm) a_Nm
405# define HM_STRUCT_NM(a_Nm) a_Nm
406#elif defined(IPRT_WITHOUT_NAMED_UNIONS_AND_STRUCTS)
407# define HM_UNION_NM(a_Nm) a_Nm
408# define HM_STRUCT_NM(a_Nm) a_Nm
409#else
410# define HM_UNION_NM(a_Nm)
411# define HM_STRUCT_NM(a_Nm)
412#endif
413
414/**
415 * HM event.
416 *
417 * VT-x and AMD-V common event injection structure.
418 */
419typedef struct HMEVENT
420{
421 /** Whether the event is pending. */
422 uint32_t fPending;
423 /** The error-code associated with the event. */
424 uint32_t u32ErrCode;
425 /** The length of the instruction in bytes (only relevant for software
426 * interrupts or software exceptions). */
427 uint32_t cbInstr;
428 /** Alignment. */
429 uint32_t u32Padding;
430 /** The encoded event (VM-entry interruption-information for VT-x or EVENTINJ
431 * for SVM). */
432 uint64_t u64IntInfo;
433 /** Guest virtual address if this is a page-fault event. */
434 RTGCUINTPTR GCPtrFaultAddress;
435} HMEVENT;
436/** Pointer to a HMEVENT struct. */
437typedef HMEVENT *PHMEVENT;
438/** Pointer to a const HMEVENT struct. */
439typedef const HMEVENT *PCHMEVENT;
440AssertCompileSizeAlignment(HMEVENT, 8);
441
442/**
443 * HM VM Instance data.
444 * Changes to this must checked against the padding of the hm union in VM!
445 */
446typedef struct HM
447{
448 /** Set when we've initialized VMX or SVM. */
449 bool fInitialized;
450 /** Set if nested paging is enabled. */
451 bool fNestedPaging;
452 /** Set if nested paging is allowed. */
453 bool fAllowNestedPaging;
454 /** Set if large pages are enabled (requires nested paging). */
455 bool fLargePages;
456 /** Set if we can support 64-bit guests or not. */
457 bool fAllow64BitGuests;
458 /** Set when TPR patching is allowed. */
459 bool fTprPatchingAllowed;
460 /** Set when we initialize VT-x or AMD-V once for all CPUs. */
461 bool fGlobalInit;
462 /** Set when TPR patching is active. */
463 bool fTPRPatchingActive;
464 /** Set when the debug facility has breakpoints/events enabled that requires
465 * us to use the debug execution loop in ring-0. */
466 bool fUseDebugLoop;
467 /** Set if hardware APIC virtualization is enabled. */
468 bool fVirtApicRegs;
469 /** Set if posted interrupt processing is enabled. */
470 bool fPostedIntrs;
471 /** Set if indirect branch prediction barrier on VM exit. */
472 bool fIbpbOnVmExit;
473 /** Set if indirect branch prediction barrier on VM entry. */
474 bool fIbpbOnVmEntry;
475 /** Set if level 1 data cache should be flushed on VM entry. */
476 bool fL1dFlushOnVmEntry;
477 /** Set if level 1 data cache should be flushed on EMT scheduling. */
478 bool fL1dFlushOnSched;
479 /** Set if host manages speculation control settings. */
480 bool fSpecCtrlByHost;
481 /** Set if MDS related buffers should be cleared on VM entry. */
482 bool fMdsClearOnVmEntry;
483 /** Set if MDS related buffers should be cleared on EMT scheduling. */
484 bool fMdsClearOnSched;
485 /** Alignment padding. */
486 bool afPaddingMinus1[6];
487
488 /** Maximum ASID allowed. */
489 uint32_t uMaxAsid;
490 /** The maximum number of resumes loops allowed in ring-0 (safety precaution).
491 * This number is set much higher when RTThreadPreemptIsPending is reliable. */
492 uint32_t cMaxResumeLoops;
493
494 /** Host kernel flags that HM might need to know (SUPKERNELFEATURES_XXX). */
495 uint32_t fHostKernelFeatures;
496
497 /** Size of the guest patch memory block. */
498 uint32_t cbGuestPatchMem;
499 /** Guest allocated memory for patching purposes. */
500 RTGCPTR pGuestPatchMem;
501 /** Current free pointer inside the patch block. */
502 RTGCPTR pFreeGuestPatchMem;
503
504 struct
505 {
506 /** Set by the ring-0 side of HM to indicate VMX is supported by the
507 * CPU. */
508 bool fSupported;
509 /** Set when we've enabled VMX. */
510 bool fEnabled;
511 /** Set if VPID is supported. */
512 bool fVpid;
513 /** Set if VT-x VPID is allowed. */
514 bool fAllowVpid;
515 /** Set if unrestricted guest execution is in use (real and protected mode
516 * without paging). */
517 bool fUnrestrictedGuest;
518 /** Set if unrestricted guest execution is allowed to be used. */
519 bool fAllowUnrestricted;
520 /** Set if the preemption timer is in use or not. */
521 bool fUsePreemptTimer;
522 /** The shift mask employed by the VMX-Preemption timer. */
523 uint8_t cPreemptTimerShift;
524
525 /** Virtual address of the TSS page used for real mode emulation. */
526 R3PTRTYPE(PVBOXTSS) pRealModeTSS;
527 /** Virtual address of the identity page table used for real mode and protected
528 * mode without paging emulation in EPT mode. */
529 R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
530
531 /** Physical address of the APIC-access page. */
532 RTHCPHYS HCPhysApicAccess;
533 /** R0 memory object for the APIC-access page. */
534 RTR0MEMOBJ hMemObjApicAccess;
535 /** Virtual address of the APIC-access page. */
536 R0PTRTYPE(uint8_t *) pbApicAccess;
537
538 /** Physical address of the VMREAD bitmap. */
539 RTHCPHYS HCPhysVmreadBitmap;
540 /** Ring-0 memory object for the VMREAD bitmap. */
541 RTR0MEMOBJ hMemObjVmreadBitmap;
542 /** Pointer to the VMREAD bitmap. */
543 R0PTRTYPE(void *) pvVmreadBitmap;
544
545 /** Physical address of the VMWRITE bitmap. */
546 RTHCPHYS HCPhysVmwriteBitmap;
547 /** Ring-0 memory object for the VMWRITE bitmap. */
548 RTR0MEMOBJ hMemObjVmwriteBitmap;
549 /** Pointer to the VMWRITE bitmap. */
550 R0PTRTYPE(void *) pvVmwriteBitmap;
551
552#ifdef VBOX_WITH_CRASHDUMP_MAGIC
553 /** Physical address of the crash-dump scratch area. */
554 RTHCPHYS HCPhysScratch;
555 /** Ring-0 memory object for the crash-dump scratch area. */
556 RTR0MEMOBJ hMemObjScratch;
557 /** Pointer to the crash-dump scratch bitmap. */
558 R0PTRTYPE(uint8_t *) pbScratch;
559#endif
560
561 /** Tagged-TLB flush type. */
562 VMXTLBFLUSHTYPE enmTlbFlushType;
563 /** Flush type to use for INVEPT. */
564 VMXTLBFLUSHEPT enmTlbFlushEpt;
565 /** Flush type to use for INVVPID. */
566 VMXTLBFLUSHVPID enmTlbFlushVpid;
567
568 /** Pause-loop exiting (PLE) gap in ticks. */
569 uint32_t cPleGapTicks;
570 /** Pause-loop exiting (PLE) window in ticks. */
571 uint32_t cPleWindowTicks;
572 uint32_t u32Alignment0;
573
574 /** Host CR4 value (set by ring-0 VMX init) */
575 uint64_t u64HostCr4;
576 /** Host SMM monitor control (set by ring-0 VMX init) */
577 uint64_t u64HostSmmMonitorCtl;
578 /** Host EFER value (set by ring-0 VMX init) */
579 uint64_t u64HostMsrEfer;
580 /** Whether the CPU supports VMCS fields for swapping EFER. */
581 bool fSupportsVmcsEfer;
582 /** Whether to use VMCS shadowing. */
583 bool fUseVmcsShadowing;
584 uint8_t u8Alignment2[6];
585
586 /** VMX MSR values. */
587 VMXMSRS Msrs;
588
589 /** Host-physical address for a failing VMXON instruction. */
590 RTHCPHYS HCPhysVmxEnableError;
591
592 /** Pointer to the shadow VMCS read-only fields array. */
593 R0PTRTYPE(uint32_t *) paShadowVmcsRoFields;
594 /** Pointer to the shadow VMCS read/write fields array. */
595 R0PTRTYPE(uint32_t *) paShadowVmcsFields;
596 /** Number of elements in the shadow VMCS read-only fields array. */
597 uint32_t cShadowVmcsRoFields;
598 /** Number of elements in the shadow VMCS read-write fields array. */
599 uint32_t cShadowVmcsFields;
600 } vmx;
601
602 struct
603 {
604 /** Set by the ring-0 side of HM to indicate SVM is supported by the
605 * CPU. */
606 bool fSupported;
607 /** Set when we've enabled SVM. */
608 bool fEnabled;
609 /** Set if erratum 170 affects the AMD cpu. */
610 bool fAlwaysFlushTLB;
611 /** Set when the hack to ignore VERR_SVM_IN_USE is active. */
612 bool fIgnoreInUseError;
613 /** Whether to use virtualized VMSAVE/VMLOAD feature. */
614 bool fVirtVmsaveVmload;
615 /** Whether to use virtual GIF feature. */
616 bool fVGif;
617 uint8_t u8Alignment0[2];
618
619 /** Physical address of the IO bitmap (12kb). */
620 RTHCPHYS HCPhysIOBitmap;
621 /** R0 memory object for the IO bitmap (12kb). */
622 RTR0MEMOBJ hMemObjIOBitmap;
623 /** Virtual address of the IO bitmap. */
624 R0PTRTYPE(void *) pvIOBitmap;
625
626 /* HWCR MSR (for diagnostics) */
627 uint64_t u64MsrHwcr;
628
629 /** SVM revision. */
630 uint32_t u32Rev;
631 /** SVM feature bits from cpuid 0x8000000a */
632 uint32_t u32Features;
633
634 /** Pause filter counter. */
635 uint16_t cPauseFilter;
636 /** Pause filter treshold in ticks. */
637 uint16_t cPauseFilterThresholdTicks;
638 uint32_t u32Alignment0;
639 } svm;
640
641 /**
642 * AVL tree with all patches (active or disabled) sorted by guest instruction
643 * address.
644 */
645 AVLOU32TREE PatchTree;
646 uint32_t cPatches;
647 HMTPRPATCH aPatches[64];
648
649 /** Last recorded error code during HM ring-0 init. */
650 int32_t rcInit;
651
652 /** HMR0Init was run */
653 bool fHMR0Init;
654 bool u8Alignment1[3];
655
656 STAMCOUNTER StatTprPatchSuccess;
657 STAMCOUNTER StatTprPatchFailure;
658 STAMCOUNTER StatTprReplaceSuccessCr8;
659 STAMCOUNTER StatTprReplaceSuccessVmc;
660 STAMCOUNTER StatTprReplaceFailure;
661} HM;
662/** Pointer to HM VM instance data. */
663typedef HM *PHM;
664
665AssertCompileMemberAlignment(HM, StatTprPatchSuccess, 8);
666
667/* Maximum number of cached entries. */
668#define VMX_VMCS_CACHE_MAX_ENTRY 128
669
670/**
671 * Cache of a VMCS for batch reads or writes.
672 */
673typedef struct VMXVMCSCACHE
674{
675#ifdef VBOX_WITH_CRASHDUMP_MAGIC
676 /* Magic marker for searching in crash dumps. */
677 uint8_t aMagic[16];
678 uint64_t uMagic;
679 uint64_t u64TimeEntry;
680 uint64_t u64TimeSwitch;
681 uint64_t cResume;
682 uint64_t interPD;
683 uint64_t pSwitcher;
684 uint32_t uPos;
685 uint32_t idCpu;
686#endif
687 /* CR2 is saved here for EPT syncing. */
688 uint64_t cr2;
689 struct
690 {
691 uint32_t cValidEntries;
692 uint32_t uAlignment;
693 uint32_t aField[VMX_VMCS_CACHE_MAX_ENTRY];
694 uint64_t aFieldVal[VMX_VMCS_CACHE_MAX_ENTRY];
695 } Write;
696 struct
697 {
698 uint32_t cValidEntries;
699 uint32_t uAlignment;
700 uint32_t aField[VMX_VMCS_CACHE_MAX_ENTRY];
701 uint64_t aFieldVal[VMX_VMCS_CACHE_MAX_ENTRY];
702 } Read;
703#ifdef VBOX_STRICT
704 struct
705 {
706 RTHCPHYS HCPhysCpuPage;
707 RTHCPHYS HCPhysVmcs;
708 RTGCPTR pCache;
709 RTGCPTR pCtx;
710 } TestIn;
711 struct
712 {
713 RTHCPHYS HCPhysVmcs;
714 RTGCPTR pCache;
715 RTGCPTR pCtx;
716 uint64_t eflags;
717 uint64_t cr8;
718 } TestOut;
719 struct
720 {
721 uint64_t param1;
722 uint64_t param2;
723 uint64_t param3;
724 uint64_t param4;
725 } ScratchPad;
726#endif
727} VMXVMCSCACHE;
728/** Pointer to VMXVMCSCACHE. */
729typedef VMXVMCSCACHE *PVMXVMCSCACHE;
730AssertCompileSizeAlignment(VMXVMCSCACHE, 8);
731
732/**
733 * VMX StartVM function.
734 *
735 * @returns VBox status code (no informational stuff).
736 * @param fResume Whether to use VMRESUME (true) or VMLAUNCH (false).
737 * @param pCtx The CPU register context.
738 * @param pVmcsCache The VMCS batch cache.
739 * @param pVM Pointer to the cross context VM structure.
740 * @param pVCpu Pointer to the cross context per-CPU structure.
741 */
742typedef DECLCALLBACK(int) FNHMVMXSTARTVM(RTHCUINT fResume, PCPUMCTX pCtx, PVMXVMCSCACHE pVmcsCache, PVM pVM, PVMCPU pVCpu);
743/** Pointer to a VMX StartVM function. */
744typedef R0PTRTYPE(FNHMVMXSTARTVM *) PFNHMVMXSTARTVM;
745
746/** SVM VMRun function. */
747typedef DECLCALLBACK(int) FNHMSVMVMRUN(RTHCPHYS pVmcbHostPhys, RTHCPHYS pVmcbPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu);
748/** Pointer to a SVM VMRun function. */
749typedef R0PTRTYPE(FNHMSVMVMRUN *) PFNHMSVMVMRUN;
750
751/**
752 * VMX VMCS information.
753 *
754 * This structure provides information maintained for and during the executing of a
755 * guest (or nested-guest) VMCS (VM control structure) using hardware-assisted VMX.
756 */
757typedef struct VMXVMCSINFO
758{
759 /** @name VMLAUNCH/VMRESUME information.
760 * @{ */
761 /** Ring-0 pointer to the hardware-assisted VMX execution function. */
762 PFNHMVMXSTARTVM pfnStartVM;
763#if HC_ARCH_BITS == 32
764 uint32_t u32Alignment0;
765#endif
766 /** @} */
767
768 /** @name VMCS and related data structures.
769 * @{ */
770 /** Host-physical address of the VMCS. */
771 RTHCPHYS HCPhysVmcs;
772 /** R0 memory object for the VMCS. */
773 RTR0MEMOBJ hMemObjVmcs;
774 /** Host-virtual address of the VMCS. */
775 R0PTRTYPE(void *) pvVmcs;
776
777 /** Host-physical address of the shadow VMCS. */
778 RTHCPHYS HCPhysShadowVmcs;
779 /** R0 memory object for the shadow VMCS. */
780 RTR0MEMOBJ hMemObjShadowVmcs;
781 /** Host-virtual address of the shadow VMCS. */
782 R0PTRTYPE(void *) pvShadowVmcs;
783
784 /** Host-physical address of the virtual APIC page. */
785 RTHCPHYS HCPhysVirtApic;
786 /** Alignment. */
787 R0PTRTYPE(void *) pvAlignment0;
788 /** Host-virtual address of the virtual-APIC page. */
789 R0PTRTYPE(uint8_t *) pbVirtApic;
790
791 /** Host-physical address of the MSR bitmap. */
792 RTHCPHYS HCPhysMsrBitmap;
793 /** R0 memory object for the MSR bitmap. */
794 RTR0MEMOBJ hMemObjMsrBitmap;
795 /** Host-virtual address of the MSR bitmap. */
796 R0PTRTYPE(void *) pvMsrBitmap;
797
798 /** Host-physical address of the VM-entry MSR-load area. */
799 RTHCPHYS HCPhysGuestMsrLoad;
800 /** R0 memory object of the VM-entry MSR-load area. */
801 RTR0MEMOBJ hMemObjGuestMsrLoad;
802 /** Host-virtual address of the VM-entry MSR-load area. */
803 R0PTRTYPE(void *) pvGuestMsrLoad;
804
805 /** Host-physical address of the VM-exit MSR-store area. */
806 RTHCPHYS HCPhysGuestMsrStore;
807 /** R0 memory object of the VM-exit MSR-store area. */
808 RTR0MEMOBJ hMemObjGuestMsrStore;
809 /** Host-virtual address of the VM-exit MSR-store area. */
810 R0PTRTYPE(void *) pvGuestMsrStore;
811
812 /** Host-physical address of the VM-exit MSR-load area. */
813 RTHCPHYS HCPhysHostMsrLoad;
814 /** R0 memory object for the VM-exit MSR-load area. */
815 RTR0MEMOBJ hMemObjHostMsrLoad;
816 /** Host-virtual address of the VM-exit MSR-load area. */
817 R0PTRTYPE(void *) pvHostMsrLoad;
818
819 /** Host-physical address of the EPTP. */
820 RTHCPHYS HCPhysEPTP;
821 /** Number of guest MSRs in the VM-entry MSR-load area. */
822 uint32_t cEntryMsrLoad;
823 /** Number of guest MSRs in the VM-exit MSR-store area. */
824 uint32_t cExitMsrStore;
825 /** Number of host MSRs in the VM-exit MSR-load area. */
826 uint32_t cExitMsrLoad;
827 /** Padding. */
828 uint32_t u32Padding0;
829 /** @} */
830
831 /** @name Auxiliary information.
832 * @{ */
833 /** The VMCS launch state, see VMX_V_VMCS_LAUNCH_STATE_XXX. */
834 uint32_t fVmcsState;
835 /** The VMCS launch state of the shadow VMCS, see VMX_V_VMCS_LAUNCH_STATE_XXX. */
836 uint32_t fShadowVmcsState;
837 /** Set if guest was executing in real mode (extra checks). */
838 bool fWasInRealMode;
839 /** Set if the guest switched to 64-bit mode on a 32-bit host. */
840 bool fSwitchedTo64on32Obsolete;
841 /** Padding. */
842 bool afPadding0[6];
843 /** The host CPU for which we have currently exported the host state. */
844 RTCPUID idHostCpu;
845 /** Padding. */
846 uint32_t u32Padding1;
847 /** @} */
848
849 /** @name Cache of execution related VMCS fields.
850 * @{ */
851 /** Pin-based VM-execution controls. */
852 uint32_t u32PinCtls;
853 /** Processor-based VM-execution controls. */
854 uint32_t u32ProcCtls;
855 /** Secondary processor-based VM-execution controls. */
856 uint32_t u32ProcCtls2;
857 /** VM-entry controls. */
858 uint32_t u32EntryCtls;
859 /** VM-exit controls. */
860 uint32_t u32ExitCtls;
861 /** Exception bitmap. */
862 uint32_t u32XcptBitmap;
863 /** CR0 guest/host mask. */
864 uint64_t u64Cr0Mask;
865 /** CR4 guest/host mask. */
866 uint64_t u64Cr4Mask;
867 /** Page-fault exception error-code mask. */
868 uint32_t u32XcptPFMask;
869 /** Page-fault exception error-code match. */
870 uint32_t u32XcptPFMatch;
871 /** TSC offset. */
872 uint64_t u64TscOffset;
873 /** VMCS link pointer. */
874 uint64_t u64VmcsLinkPtr;
875 /** @} */
876
877 /** @name Real-mode emulation state.
878 * @{ */
879 struct
880 {
881 X86DESCATTR AttrCS;
882 X86DESCATTR AttrDS;
883 X86DESCATTR AttrES;
884 X86DESCATTR AttrFS;
885 X86DESCATTR AttrGS;
886 X86DESCATTR AttrSS;
887 X86EFLAGS Eflags;
888 bool fRealOnV86Active;
889 bool afPadding1[3];
890 } RealMode;
891 /** @} */
892
893 /** Padding. */
894 uint64_t au64Padding[2];
895} VMXVMCSINFO;
896/** Pointer to a VMXVMCSINFO struct. */
897typedef VMXVMCSINFO *PVMXVMCSINFO;
898/** Pointer to a const VMXVMCSINFO struct. */
899typedef const VMXVMCSINFO *PCVMXVMCSINFO;
900AssertCompileSizeAlignment(VMXVMCSINFO, 8);
901AssertCompileMemberAlignment(VMXVMCSINFO, fVmcsState, 8);
902AssertCompileMemberAlignment(VMXVMCSINFO, u32PinCtls, 8);
903AssertCompileMemberAlignment(VMXVMCSINFO, u64VmcsLinkPtr, 8);
904
905/**
906 * HM VMCPU Instance data.
907 *
908 * Note! If you change members of this struct, make sure to check if the
909 * assembly counterpart in HMInternal.mac needs to be updated as well.
910 */
911typedef struct HMCPU
912{
913 /** Set when the TLB has been checked until we return from the world switch. */
914 bool volatile fCheckedTLBFlush;
915 /** Set if we need to flush the TLB during the world switch. */
916 bool fForceTLBFlush;
917 /** Set when we're using VT-x or AMD-V at that moment. */
918 bool fActive;
919 /** Whether we've completed the inner HM leave function. */
920 bool fLeaveDone;
921 /** Whether we're using the hyper DR7 or guest DR7. */
922 bool fUsingHyperDR7;
923 /** Set if XCR0 needs to be saved/restored when entering/exiting guest code
924 * execution. */
925 bool fLoadSaveGuestXcr0;
926
927 /** Whether we should use the debug loop because of single stepping or special
928 * debug breakpoints / events are armed. */
929 bool fUseDebugLoop;
930 /** Whether we are currently executing in the debug loop.
931 * Mainly for assertions. */
932 bool fUsingDebugLoop;
933 /** Set if we using the debug loop and wish to intercept RDTSC. */
934 bool fDebugWantRdTscExit;
935 /** Whether we're executing a single instruction. */
936 bool fSingleInstruction;
937 /** Set if we need to clear the trap flag because of single stepping. */
938 bool fClearTrapFlag;
939
940 /** Whether \#UD needs to be intercepted (required by certain GIM providers). */
941 bool fGIMTrapXcptUD;
942 /** Whether \#GP needs to be intercept for mesa driver workaround. */
943 bool fTrapXcptGpForLovelyMesaDrv;
944 uint8_t u8Alignment0[3];
945
946 /** World switch exit counter. */
947 uint32_t volatile cWorldSwitchExits;
948 /** The last CPU we were executing code on (NIL_RTCPUID for the first time). */
949 RTCPUID idLastCpu;
950 /** TLB flush count. */
951 uint32_t cTlbFlushes;
952 /** Current ASID in use by the VM. */
953 uint32_t uCurrentAsid;
954 /** An additional error code used for some gurus. */
955 uint32_t u32HMError;
956 /** The last exit-to-ring-3 reason. */
957 int32_t rcLastExitToR3;
958 /** CPU-context changed flags (see HM_CHANGED_xxx). */
959 uint64_t fCtxChanged;
960
961 union /* no tag! */
962 {
963 /** VT-x data. */
964 struct
965 {
966 /** @name Guest information.
967 * @{ */
968 /** Guest VMCS information. */
969 VMXVMCSINFO VmcsInfo;
970 /** Nested-guest VMCS information. */
971 VMXVMCSINFO VmcsInfoNstGst;
972 /** Whether the nested-guest VMCS was the last current VMCS. */
973 bool fSwitchedToNstGstVmcs;
974 /** Whether the static guest VMCS controls has been merged with the
975 * nested-guest VMCS controls. */
976 bool fMergedNstGstCtls;
977 /** Whether the nested-guest VMCS has been copied to the shadow VMCS. */
978 bool fCopiedNstGstToShadowVmcs;
979 /** Whether flushing the TLB is required due to switching to/from the
980 * nested-geust. */
981 bool fSwitchedNstGstFlushTlb;
982
983 bool fVirtApicPageLocked;
984 /** Alignment. */
985 bool afAlignment0[3];
986 /** Cached guest APIC-base MSR for identifying when to map the APIC-access page. */
987 uint64_t u64GstMsrApicBase;
988 /** VMCS cache for batched vmread/vmwrites. */
989 VMXVMCSCACHE VmcsCache;
990 PGMPAGEMAPLOCK PgMapLockVirtApic;
991 /** @} */
992
993 /** @name Host information.
994 * @{ */
995 /** Host LSTAR MSR to restore lazily while leaving VT-x. */
996 uint64_t u64HostMsrLStar;
997 /** Host STAR MSR to restore lazily while leaving VT-x. */
998 uint64_t u64HostMsrStar;
999 /** Host SF_MASK MSR to restore lazily while leaving VT-x. */
1000 uint64_t u64HostMsrSfMask;
1001 /** Host KernelGS-Base MSR to restore lazily while leaving VT-x. */
1002 uint64_t u64HostMsrKernelGsBase;
1003 /** The mask of lazy MSRs swap/restore state, see VMX_LAZY_MSRS_XXX. */
1004 uint32_t fLazyMsrs;
1005 /** Whether the host MSR values are up-to-date in the auto-load/store MSR area. */
1006 bool fUpdatedHostAutoMsrs;
1007 /** Alignment. */
1008 uint8_t au8Alignment0[3];
1009 /** Which host-state bits to restore before being preempted. */
1010 uint32_t fRestoreHostFlags;
1011 /** Alignment. */
1012 uint32_t u32Alignment0;
1013 /** The host-state restoration structure. */
1014 VMXRESTOREHOST RestoreHost;
1015 /** @} */
1016
1017 /** @name Error reporting and diagnostics.
1018 * @{ */
1019 /** VT-x error-reporting (mainly for ring-3 propagation). */
1020 struct
1021 {
1022 RTHCPHYS HCPhysCurrentVmcs;
1023 uint32_t u32VmcsRev;
1024 uint32_t u32InstrError;
1025 uint32_t u32ExitReason;
1026 uint32_t u32Alignment0;
1027 RTCPUID idEnteredCpu;
1028 RTCPUID idCurrentCpu;
1029 } LastError;
1030 /** @} */
1031 } vmx;
1032
1033 /** SVM data. */
1034 struct
1035 {
1036 /** Ring 0 handlers for VT-x. */
1037 PFNHMSVMVMRUN pfnVMRun;
1038#if HC_ARCH_BITS == 32
1039 uint32_t u32Alignment0;
1040#endif
1041
1042 /** Physical address of the host VMCB which holds additional host-state. */
1043 RTHCPHYS HCPhysVmcbHost;
1044 /** R0 memory object for the host VMCB which holds additional host-state. */
1045 RTR0MEMOBJ hMemObjVmcbHost;
1046 /** Padding. */
1047 R0PTRTYPE(void *) pvPadding;
1048
1049 /** Physical address of the guest VMCB. */
1050 RTHCPHYS HCPhysVmcb;
1051 /** R0 memory object for the guest VMCB. */
1052 RTR0MEMOBJ hMemObjVmcb;
1053 /** Pointer to the guest VMCB. */
1054 R0PTRTYPE(PSVMVMCB) pVmcb;
1055
1056 /** Physical address of the MSR bitmap (8 KB). */
1057 RTHCPHYS HCPhysMsrBitmap;
1058 /** R0 memory object for the MSR bitmap (8 KB). */
1059 RTR0MEMOBJ hMemObjMsrBitmap;
1060 /** Pointer to the MSR bitmap. */
1061 R0PTRTYPE(void *) pvMsrBitmap;
1062
1063 /** Whether VTPR with V_INTR_MASKING set is in effect, indicating
1064 * we should check if the VTPR changed on every VM-exit. */
1065 bool fSyncVTpr;
1066 uint8_t au8Alignment0[7];
1067
1068 /** Host's TSC_AUX MSR (used when RDTSCP doesn't cause VM-exits). */
1069 uint64_t u64HostTscAux;
1070
1071 /** Cache of the nested-guest's VMCB fields that we modify in order to run the
1072 * nested-guest using AMD-V. This will be restored on \#VMEXIT. */
1073 SVMNESTEDVMCBCACHE NstGstVmcbCache;
1074 } svm;
1075 } HM_UNION_NM(u);
1076
1077 /** Event injection state. */
1078 HMEVENT Event;
1079
1080 /** The PAE PDPEs used with Nested Paging (only valid when
1081 * VMCPU_FF_HM_UPDATE_PAE_PDPES is set). */
1082 X86PDPE aPdpes[4];
1083
1084 /** Current shadow paging mode for updating CR4. */
1085 PGMMODE enmShadowMode;
1086
1087 /** The CPU ID of the CPU currently owning the VMCS. Set in
1088 * HMR0Enter and cleared in HMR0Leave. */
1089 RTCPUID idEnteredCpu;
1090
1091 /** For saving stack space, the disassembler state is allocated here instead of
1092 * on the stack. */
1093 DISCPUSTATE DisState;
1094
1095 STAMPROFILEADV StatEntry;
1096 STAMPROFILEADV StatPreExit;
1097 STAMPROFILEADV StatExitHandling;
1098 STAMPROFILEADV StatExitIO;
1099 STAMPROFILEADV StatExitMovCRx;
1100 STAMPROFILEADV StatExitXcptNmi;
1101 STAMPROFILEADV StatExitVmentry;
1102 STAMPROFILEADV StatImportGuestState;
1103 STAMPROFILEADV StatExportGuestState;
1104 STAMPROFILEADV StatLoadGuestFpuState;
1105 STAMPROFILEADV StatInGC;
1106 STAMPROFILEADV StatPoke;
1107 STAMPROFILEADV StatSpinPoke;
1108 STAMPROFILEADV StatSpinPokeFailed;
1109
1110 STAMCOUNTER StatInjectInterrupt;
1111 STAMCOUNTER StatInjectXcpt;
1112 STAMCOUNTER StatInjectReflect;
1113 STAMCOUNTER StatInjectConvertDF;
1114 STAMCOUNTER StatInjectInterpret;
1115 STAMCOUNTER StatInjectReflectNPF;
1116
1117 STAMCOUNTER StatExitAll;
1118 STAMCOUNTER StatNestedExitAll;
1119 STAMCOUNTER StatExitShadowNM;
1120 STAMCOUNTER StatExitGuestNM;
1121 STAMCOUNTER StatExitShadowPF; /**< Misleading, currently used for MMIO \#PFs as well. */
1122 STAMCOUNTER StatExitShadowPFEM;
1123 STAMCOUNTER StatExitGuestPF;
1124 STAMCOUNTER StatExitGuestUD;
1125 STAMCOUNTER StatExitGuestSS;
1126 STAMCOUNTER StatExitGuestNP;
1127 STAMCOUNTER StatExitGuestTS;
1128 STAMCOUNTER StatExitGuestOF;
1129 STAMCOUNTER StatExitGuestGP;
1130 STAMCOUNTER StatExitGuestDE;
1131 STAMCOUNTER StatExitGuestDF;
1132 STAMCOUNTER StatExitGuestBR;
1133 STAMCOUNTER StatExitGuestAC;
1134 STAMCOUNTER StatExitGuestDB;
1135 STAMCOUNTER StatExitGuestMF;
1136 STAMCOUNTER StatExitGuestBP;
1137 STAMCOUNTER StatExitGuestXF;
1138 STAMCOUNTER StatExitGuestXcpUnk;
1139 STAMCOUNTER StatExitDRxWrite;
1140 STAMCOUNTER StatExitDRxRead;
1141 STAMCOUNTER StatExitCR0Read;
1142 STAMCOUNTER StatExitCR2Read;
1143 STAMCOUNTER StatExitCR3Read;
1144 STAMCOUNTER StatExitCR4Read;
1145 STAMCOUNTER StatExitCR8Read;
1146 STAMCOUNTER StatExitCR0Write;
1147 STAMCOUNTER StatExitCR2Write;
1148 STAMCOUNTER StatExitCR3Write;
1149 STAMCOUNTER StatExitCR4Write;
1150 STAMCOUNTER StatExitCR8Write;
1151 STAMCOUNTER StatExitRdmsr;
1152 STAMCOUNTER StatExitWrmsr;
1153 STAMCOUNTER StatExitClts;
1154 STAMCOUNTER StatExitXdtrAccess;
1155 STAMCOUNTER StatExitLmsw;
1156 STAMCOUNTER StatExitIOWrite;
1157 STAMCOUNTER StatExitIORead;
1158 STAMCOUNTER StatExitIOStringWrite;
1159 STAMCOUNTER StatExitIOStringRead;
1160 STAMCOUNTER StatExitIntWindow;
1161 STAMCOUNTER StatExitExtInt;
1162 STAMCOUNTER StatExitHostNmiInGC;
1163 STAMCOUNTER StatExitHostNmiInGCIpi;
1164 STAMCOUNTER StatExitPreemptTimer;
1165 STAMCOUNTER StatExitTprBelowThreshold;
1166 STAMCOUNTER StatExitTaskSwitch;
1167 STAMCOUNTER StatExitApicAccess;
1168 STAMCOUNTER StatExitReasonNpf;
1169
1170 STAMCOUNTER StatNestedExitReasonNpf;
1171
1172 STAMCOUNTER StatFlushPage;
1173 STAMCOUNTER StatFlushPageManual;
1174 STAMCOUNTER StatFlushPhysPageManual;
1175 STAMCOUNTER StatFlushTlb;
1176 STAMCOUNTER StatFlushTlbNstGst;
1177 STAMCOUNTER StatFlushTlbManual;
1178 STAMCOUNTER StatFlushTlbWorldSwitch;
1179 STAMCOUNTER StatNoFlushTlbWorldSwitch;
1180 STAMCOUNTER StatFlushEntire;
1181 STAMCOUNTER StatFlushAsid;
1182 STAMCOUNTER StatFlushNestedPaging;
1183 STAMCOUNTER StatFlushTlbInvlpgVirt;
1184 STAMCOUNTER StatFlushTlbInvlpgPhys;
1185 STAMCOUNTER StatTlbShootdown;
1186 STAMCOUNTER StatTlbShootdownFlush;
1187
1188 STAMCOUNTER StatSwitchPendingHostIrq;
1189 STAMCOUNTER StatSwitchTprMaskedIrq;
1190 STAMCOUNTER StatSwitchGuestIrq;
1191 STAMCOUNTER StatSwitchHmToR3FF;
1192 STAMCOUNTER StatSwitchVmReq;
1193 STAMCOUNTER StatSwitchPgmPoolFlush;
1194 STAMCOUNTER StatSwitchDma;
1195 STAMCOUNTER StatSwitchExitToR3;
1196 STAMCOUNTER StatSwitchLongJmpToR3;
1197 STAMCOUNTER StatSwitchMaxResumeLoops;
1198 STAMCOUNTER StatSwitchHltToR3;
1199 STAMCOUNTER StatSwitchApicAccessToR3;
1200 STAMCOUNTER StatSwitchPreempt;
1201 STAMCOUNTER StatSwitchNstGstVmexit;
1202
1203 STAMCOUNTER StatTscParavirt;
1204 STAMCOUNTER StatTscOffset;
1205 STAMCOUNTER StatTscIntercept;
1206
1207 STAMCOUNTER StatDRxArmed;
1208 STAMCOUNTER StatDRxContextSwitch;
1209 STAMCOUNTER StatDRxIoCheck;
1210
1211 STAMCOUNTER StatExportMinimal;
1212 STAMCOUNTER StatExportFull;
1213 STAMCOUNTER StatLoadGuestFpu;
1214 STAMCOUNTER StatExportHostState;
1215
1216 STAMCOUNTER StatVmxCheckBadRmSelBase;
1217 STAMCOUNTER StatVmxCheckBadRmSelLimit;
1218 STAMCOUNTER StatVmxCheckBadRmSelAttr;
1219 STAMCOUNTER StatVmxCheckBadV86SelBase;
1220 STAMCOUNTER StatVmxCheckBadV86SelLimit;
1221 STAMCOUNTER StatVmxCheckBadV86SelAttr;
1222 STAMCOUNTER StatVmxCheckRmOk;
1223 STAMCOUNTER StatVmxCheckBadSel;
1224 STAMCOUNTER StatVmxCheckBadRpl;
1225 STAMCOUNTER StatVmxCheckPmOk;
1226
1227#ifdef VBOX_WITH_STATISTICS
1228 R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
1229 R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
1230 R3PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqs;
1231 R0PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqsR0;
1232 R3PTRTYPE(PSTAMCOUNTER) paStatNestedExitReason;
1233 R0PTRTYPE(PSTAMCOUNTER) paStatNestedExitReasonR0;
1234#endif
1235#ifdef HM_PROFILE_EXIT_DISPATCH
1236 STAMPROFILEADV StatExitDispatch;
1237#endif
1238} HMCPU;
1239/** Pointer to HM VMCPU instance data. */
1240typedef HMCPU *PHMCPU;
1241AssertCompileMemberAlignment(HMCPU, cWorldSwitchExits, 4);
1242AssertCompileMemberAlignment(HMCPU, fCtxChanged, 8);
1243AssertCompileMemberAlignment(HMCPU, HM_UNION_NM(u.) vmx, 8);
1244AssertCompileMemberAlignment(HMCPU, HM_UNION_NM(u.) svm, 8);
1245AssertCompileMemberAlignment(HMCPU, Event, 8);
1246
1247#ifdef IN_RING0
1248VMMR0_INT_DECL(PHMPHYSCPU) hmR0GetCurrentCpu(void);
1249VMMR0_INT_DECL(int) hmR0EnterCpu(PVMCPU pVCpu);
1250
1251# ifdef VBOX_STRICT
1252VMMR0_INT_DECL(void) hmR0DumpRegs(PVMCPU pVCpu);
1253VMMR0_INT_DECL(void) hmR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg);
1254# endif
1255
1256# ifdef VBOX_WITH_KERNEL_USING_XMM
1257DECLASM(int) hmR0VMXStartVMWrapXMM(RTHCUINT fResume, PCPUMCTX pCtx, PVMXVMCSCACHE pVmcsCache, PVM pVM,
1258 PVMCPU pVCpu, PFNHMVMXSTARTVM pfnStartVM);
1259DECLASM(int) hmR0SVMRunWrapXMM(RTHCPHYS pVmcbHostPhys, RTHCPHYS pVmcbPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu,
1260 PFNHMSVMVMRUN pfnVMRun);
1261# endif
1262DECLASM(void) hmR0MdsClear(void);
1263#endif /* IN_RING0 */
1264
1265VMM_INT_DECL(int) hmEmulateSvmMovTpr(PVMCPU pVCpu);
1266
1267VMM_INT_DECL(PVMXVMCSINFO) hmGetVmxActiveVmcsInfo(PVMCPU pVCpu);
1268
1269/** @} */
1270
1271RT_C_DECLS_END
1272
1273#endif /* !VMM_INCLUDED_SRC_include_HMInternal_h */
1274
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