HMInternal.h@ 87359

Last change on this file since 87359 was 87359, checked in by vboxsync, 4 years ago
VMM/HMSVM: Straighten out the svm vmrun assembly code by having different version for each of the 3 branch conditions. The C code changes which one it calls when the conditions changes (only one which does so at runtime). Should be better for spectre fighting and general mojo.
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File size: 54.0 KB

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1	/* $Id: HMInternal.h 87359 2021-01-21 19:56:26Z vboxsync $ */
2	/** @file
3	* HM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef VMM_INCLUDED_SRC_include_HMInternal_h
19	#define VMM_INCLUDED_SRC_include_HMInternal_h
20	#ifndef RT_WITHOUT_PRAGMA_ONCE
21	# pragma once
22	#endif
23
24	#include <VBox/cdefs.h>
25	#include <VBox/types.h>
26	#include <VBox/vmm/stam.h>
27	#include <VBox/dis.h>
28	#include <VBox/vmm/hm.h>
29	#include <VBox/vmm/hm_vmx.h>
30	#include <VBox/vmm/hm_svm.h>
31	#include <VBox/vmm/pgm.h>
32	#include <VBox/vmm/cpum.h>
33	#include <VBox/vmm/trpm.h>
34	#include <iprt/memobj.h>
35	#include <iprt/cpuset.h>
36	#include <iprt/mp.h>
37	#include <iprt/avl.h>
38	#include <iprt/string.h>
39
40	#if HC_ARCH_BITS == 32
41	# error "32-bit hosts are no longer supported. Go back to 6.0 or earlier!"
42	#endif
43
44	/** @def HM_PROFILE_EXIT_DISPATCH
45	* Enables profiling of the VM exit handler dispatching. */
46	#if 0 \|\| defined(DOXYGEN_RUNNING)
47	# define HM_PROFILE_EXIT_DISPATCH
48	#endif
49
50	RT_C_DECLS_BEGIN
51
52
53	/** @defgroup grp_hm_int Internal
54	* @ingroup grp_hm
55	* @internal
56	* @{
57	*/
58
59	/** @name HM_CHANGED_XXX
60	* HM CPU-context changed flags.
61	*
62	* These flags are used to keep track of which registers and state has been
63	* modified since they were imported back into the guest-CPU context.
64	*
65	* @{
66	*/
67	#define HM_CHANGED_HOST_CONTEXT UINT64_C(0x0000000000000001)
68	#define HM_CHANGED_GUEST_RIP UINT64_C(0x0000000000000004)
69	#define HM_CHANGED_GUEST_RFLAGS UINT64_C(0x0000000000000008)
70
71	#define HM_CHANGED_GUEST_RAX UINT64_C(0x0000000000000010)
72	#define HM_CHANGED_GUEST_RCX UINT64_C(0x0000000000000020)
73	#define HM_CHANGED_GUEST_RDX UINT64_C(0x0000000000000040)
74	#define HM_CHANGED_GUEST_RBX UINT64_C(0x0000000000000080)
75	#define HM_CHANGED_GUEST_RSP UINT64_C(0x0000000000000100)
76	#define HM_CHANGED_GUEST_RBP UINT64_C(0x0000000000000200)
77	#define HM_CHANGED_GUEST_RSI UINT64_C(0x0000000000000400)
78	#define HM_CHANGED_GUEST_RDI UINT64_C(0x0000000000000800)
79	#define HM_CHANGED_GUEST_R8_R15 UINT64_C(0x0000000000001000)
80	#define HM_CHANGED_GUEST_GPRS_MASK UINT64_C(0x0000000000001ff0)
81
82	#define HM_CHANGED_GUEST_ES UINT64_C(0x0000000000002000)
83	#define HM_CHANGED_GUEST_CS UINT64_C(0x0000000000004000)
84	#define HM_CHANGED_GUEST_SS UINT64_C(0x0000000000008000)
85	#define HM_CHANGED_GUEST_DS UINT64_C(0x0000000000010000)
86	#define HM_CHANGED_GUEST_FS UINT64_C(0x0000000000020000)
87	#define HM_CHANGED_GUEST_GS UINT64_C(0x0000000000040000)
88	#define HM_CHANGED_GUEST_SREG_MASK UINT64_C(0x000000000007e000)
89
90	#define HM_CHANGED_GUEST_GDTR UINT64_C(0x0000000000080000)
91	#define HM_CHANGED_GUEST_IDTR UINT64_C(0x0000000000100000)
92	#define HM_CHANGED_GUEST_LDTR UINT64_C(0x0000000000200000)
93	#define HM_CHANGED_GUEST_TR UINT64_C(0x0000000000400000)
94	#define HM_CHANGED_GUEST_TABLE_MASK UINT64_C(0x0000000000780000)
95
96	#define HM_CHANGED_GUEST_CR0 UINT64_C(0x0000000000800000)
97	#define HM_CHANGED_GUEST_CR2 UINT64_C(0x0000000001000000)
98	#define HM_CHANGED_GUEST_CR3 UINT64_C(0x0000000002000000)
99	#define HM_CHANGED_GUEST_CR4 UINT64_C(0x0000000004000000)
100	#define HM_CHANGED_GUEST_CR_MASK UINT64_C(0x0000000007800000)
101
102	#define HM_CHANGED_GUEST_APIC_TPR UINT64_C(0x0000000008000000)
103	#define HM_CHANGED_GUEST_EFER_MSR UINT64_C(0x0000000010000000)
104
105	#define HM_CHANGED_GUEST_DR0_DR3 UINT64_C(0x0000000020000000)
106	#define HM_CHANGED_GUEST_DR6 UINT64_C(0x0000000040000000)
107	#define HM_CHANGED_GUEST_DR7 UINT64_C(0x0000000080000000)
108	#define HM_CHANGED_GUEST_DR_MASK UINT64_C(0x00000000e0000000)
109
110	#define HM_CHANGED_GUEST_X87 UINT64_C(0x0000000100000000)
111	#define HM_CHANGED_GUEST_SSE_AVX UINT64_C(0x0000000200000000)
112	#define HM_CHANGED_GUEST_OTHER_XSAVE UINT64_C(0x0000000400000000)
113	#define HM_CHANGED_GUEST_XCRx UINT64_C(0x0000000800000000)
114
115	#define HM_CHANGED_GUEST_KERNEL_GS_BASE UINT64_C(0x0000001000000000)
116	#define HM_CHANGED_GUEST_SYSCALL_MSRS UINT64_C(0x0000002000000000)
117	#define HM_CHANGED_GUEST_SYSENTER_CS_MSR UINT64_C(0x0000004000000000)
118	#define HM_CHANGED_GUEST_SYSENTER_EIP_MSR UINT64_C(0x0000008000000000)
119	#define HM_CHANGED_GUEST_SYSENTER_ESP_MSR UINT64_C(0x0000010000000000)
120	#define HM_CHANGED_GUEST_SYSENTER_MSR_MASK UINT64_C(0x000001c000000000)
121	#define HM_CHANGED_GUEST_TSC_AUX UINT64_C(0x0000020000000000)
122	#define HM_CHANGED_GUEST_OTHER_MSRS UINT64_C(0x0000040000000000)
123	#define HM_CHANGED_GUEST_ALL_MSRS ( HM_CHANGED_GUEST_EFER \
124	\| HM_CHANGED_GUEST_KERNEL_GS_BASE \
125	\| HM_CHANGED_GUEST_SYSCALL_MSRS \
126	\| HM_CHANGED_GUEST_SYSENTER_MSR_MASK \
127	\| HM_CHANGED_GUEST_TSC_AUX \
128	\| HM_CHANGED_GUEST_OTHER_MSRS)
129
130	#define HM_CHANGED_GUEST_HWVIRT UINT64_C(0x0000080000000000)
131	#define HM_CHANGED_GUEST_MASK UINT64_C(0x00000ffffffffffc)
132
133	#define HM_CHANGED_KEEPER_STATE_MASK UINT64_C(0xffff000000000000)
134
135	#define HM_CHANGED_VMX_XCPT_INTERCEPTS UINT64_C(0x0001000000000000)
136	#define HM_CHANGED_VMX_GUEST_AUTO_MSRS UINT64_C(0x0002000000000000)
137	#define HM_CHANGED_VMX_GUEST_LAZY_MSRS UINT64_C(0x0004000000000000)
138	#define HM_CHANGED_VMX_ENTRY_EXIT_CTLS UINT64_C(0x0008000000000000)
139	#define HM_CHANGED_VMX_MASK UINT64_C(0x000f000000000000)
140	#define HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE ( HM_CHANGED_GUEST_DR_MASK \
141	\| HM_CHANGED_VMX_GUEST_LAZY_MSRS)
142
143	#define HM_CHANGED_SVM_XCPT_INTERCEPTS UINT64_C(0x0001000000000000)
144	#define HM_CHANGED_SVM_MASK UINT64_C(0x0001000000000000)
145	#define HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE HM_CHANGED_GUEST_DR_MASK
146
147	#define HM_CHANGED_ALL_GUEST ( HM_CHANGED_GUEST_MASK \
148	\| HM_CHANGED_KEEPER_STATE_MASK)
149
150	/** Mask of what state might have changed when IEM raised an exception.
151	* This is a based on IEM_CPUMCTX_EXTRN_XCPT_MASK. */
152	#define HM_CHANGED_RAISED_XCPT_MASK ( HM_CHANGED_GUEST_GPRS_MASK \
153	\| HM_CHANGED_GUEST_RIP \
154	\| HM_CHANGED_GUEST_RFLAGS \
155	\| HM_CHANGED_GUEST_SS \
156	\| HM_CHANGED_GUEST_CS \
157	\| HM_CHANGED_GUEST_CR0 \
158	\| HM_CHANGED_GUEST_CR3 \
159	\| HM_CHANGED_GUEST_CR4 \
160	\| HM_CHANGED_GUEST_APIC_TPR \
161	\| HM_CHANGED_GUEST_EFER_MSR \
162	\| HM_CHANGED_GUEST_DR7 \
163	\| HM_CHANGED_GUEST_CR2 \
164	\| HM_CHANGED_GUEST_SREG_MASK \
165	\| HM_CHANGED_GUEST_TABLE_MASK)
166
167	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
168	/** Mask of what state might have changed when \#VMEXIT is emulated. */
169	# define HM_CHANGED_SVM_VMEXIT_MASK ( HM_CHANGED_GUEST_RSP \
170	\| HM_CHANGED_GUEST_RAX \
171	\| HM_CHANGED_GUEST_RIP \
172	\| HM_CHANGED_GUEST_RFLAGS \
173	\| HM_CHANGED_GUEST_CS \
174	\| HM_CHANGED_GUEST_SS \
175	\| HM_CHANGED_GUEST_DS \
176	\| HM_CHANGED_GUEST_ES \
177	\| HM_CHANGED_GUEST_GDTR \
178	\| HM_CHANGED_GUEST_IDTR \
179	\| HM_CHANGED_GUEST_CR_MASK \
180	\| HM_CHANGED_GUEST_EFER_MSR \
181	\| HM_CHANGED_GUEST_DR6 \
182	\| HM_CHANGED_GUEST_DR7 \
183	\| HM_CHANGED_GUEST_OTHER_MSRS \
184	\| HM_CHANGED_GUEST_HWVIRT \
185	\| HM_CHANGED_SVM_MASK \
186	\| HM_CHANGED_GUEST_APIC_TPR)
187
188	/** Mask of what state might have changed when VMRUN is emulated. */
189	# define HM_CHANGED_SVM_VMRUN_MASK HM_CHANGED_SVM_VMEXIT_MASK
190	#endif
191	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
192	/** Mask of what state might have changed when VM-exit is emulated.
193	*
194	* This is currently unused, but keeping it here in case we can get away a bit more
195	* fine-grained state handling.
196	*
197	* @note Update IEM_CPUMCTX_EXTRN_VMX_VMEXIT_MASK when this changes. */
198	# define HM_CHANGED_VMX_VMEXIT_MASK ( HM_CHANGED_GUEST_CR0 \| HM_CHANGED_GUEST_CR3 \| HM_CHANGED_GUEST_CR4 \
199	\| HM_CHANGED_GUEST_DR7 \| HM_CHANGED_GUEST_DR6 \
200	\| HM_CHANGED_GUEST_EFER_MSR \
201	\| HM_CHANGED_GUEST_SYSENTER_MSR_MASK \
202	\| HM_CHANGED_GUEST_OTHER_MSRS /* for PAT MSR */ \
203	\| HM_CHANGED_GUEST_RIP \| HM_CHANGED_GUEST_RSP \| HM_CHANGED_GUEST_RFLAGS \
204	\| HM_CHANGED_GUEST_SREG_MASK \
205	\| HM_CHANGED_GUEST_TR \
206	\| HM_CHANGED_GUEST_LDTR \| HM_CHANGED_GUEST_GDTR \| HM_CHANGED_GUEST_IDTR \
207	\| HM_CHANGED_GUEST_HWVIRT )
208	#endif
209	/** @} */
210
211	/** Maximum number of exit reason statistics counters. */
212	#define MAX_EXITREASON_STAT 0x100
213	#define MASK_EXITREASON_STAT 0xff
214	#define MASK_INJECT_IRQ_STAT 0xff
215
216	/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
217	#define HM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
218	/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
219	#define HM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2 * PAGE_SIZE + 1)
220	/** Total guest mapped memory needed. */
221	#define HM_VTX_TOTAL_DEVHEAP_MEM (HM_EPT_IDENTITY_PG_TABLE_SIZE + HM_VTX_TSS_SIZE)
222
223
224	/** @name Macros for enabling and disabling preemption.
225	* These are really just for hiding the RTTHREADPREEMPTSTATE and asserting that
226	* preemption has already been disabled when there is no context hook.
227	* @{ */
228	#ifdef VBOX_STRICT
229	# define HM_DISABLE_PREEMPT(a_pVCpu) \
230	RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
231	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD) \|\| VMMR0ThreadCtxHookIsEnabled((a_pVCpu))); \
232	RTThreadPreemptDisable(&PreemptStateInternal)
233	#else
234	# define HM_DISABLE_PREEMPT(a_pVCpu) \
235	RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
236	RTThreadPreemptDisable(&PreemptStateInternal)
237	#endif /* VBOX_STRICT */
238	#define HM_RESTORE_PREEMPT() do { RTThreadPreemptRestore(&PreemptStateInternal); } while(0)
239	/** @} */
240
241
242	/** @name HM saved state versions.
243	* @{
244	*/
245	#define HM_SAVED_STATE_VERSION HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT
246	#define HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT 6
247	#define HM_SAVED_STATE_VERSION_TPR_PATCHING 5
248	#define HM_SAVED_STATE_VERSION_NO_TPR_PATCHING 4
249	#define HM_SAVED_STATE_VERSION_2_0_X 3
250	/** @} */
251
252
253	/**
254	* HM physical (host) CPU information.
255	*/
256	typedef struct HMPHYSCPU
257	{
258	/** The CPU ID. */
259	RTCPUID idCpu;
260	/** The VM_HSAVE_AREA (AMD-V) / VMXON region (Intel) memory backing. */
261	RTR0MEMOBJ hMemObj;
262	/** The physical address of the first page in hMemObj (it's a
263	* physcially contigous allocation if it spans multiple pages). */
264	RTHCPHYS HCPhysMemObj;
265	/** The address of the memory (for pfnEnable). */
266	void *pvMemObj;
267	/** Current ASID (AMD-V) / VPID (Intel). */
268	uint32_t uCurrentAsid;
269	/** TLB flush count. */
270	uint32_t cTlbFlushes;
271	/** Whether to flush each new ASID/VPID before use. */
272	bool fFlushAsidBeforeUse;
273	/** Configured for VT-x or AMD-V. */
274	bool fConfigured;
275	/** Set if the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active. */
276	bool fIgnoreAMDVInUseError;
277	/** Whether CR4.VMXE was already enabled prior to us enabling it. */
278	bool fVmxeAlreadyEnabled;
279	/** In use by our code. (for power suspend) */
280	bool volatile fInUse;
281	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
282	/** Nested-guest union (put data common to SVM/VMX outside the union). */
283	union
284	{
285	/** Nested-guest SVM data. */
286	struct
287	{
288	/** The active nested-guest MSR permission bitmap memory backing. */
289	RTR0MEMOBJ hNstGstMsrpm;
290	/** The physical address of the first page in hNstGstMsrpm (physcially
291	* contiguous allocation). */
292	RTHCPHYS HCPhysNstGstMsrpm;
293	/** The address of the active nested-guest MSRPM. */
294	void *pvNstGstMsrpm;
295	} svm;
296	/** @todo Nested-VMX. */
297	} n;
298	#endif
299	} HMPHYSCPU;
300	/** Pointer to HMPHYSCPU struct. */
301	typedef HMPHYSCPU *PHMPHYSCPU;
302	/** Pointer to a const HMPHYSCPU struct. */
303	typedef const HMPHYSCPU *PCHMPHYSCPU;
304
305	/**
306	* TPR-instruction type.
307	*/
308	typedef enum
309	{
310	HMTPRINSTR_INVALID,
311	HMTPRINSTR_READ,
312	HMTPRINSTR_READ_SHR4,
313	HMTPRINSTR_WRITE_REG,
314	HMTPRINSTR_WRITE_IMM,
315	HMTPRINSTR_JUMP_REPLACEMENT,
316	/** The usual 32-bit paranoia. */
317	HMTPRINSTR_32BIT_HACK = 0x7fffffff
318	} HMTPRINSTR;
319
320	/**
321	* TPR patch information.
322	*/
323	typedef struct
324	{
325	/** The key is the address of patched instruction. (32 bits GC ptr) */
326	AVLOU32NODECORE Core;
327	/** Original opcode. */
328	uint8_t aOpcode[16];
329	/** Instruction size. */
330	uint32_t cbOp;
331	/** Replacement opcode. */
332	uint8_t aNewOpcode[16];
333	/** Replacement instruction size. */
334	uint32_t cbNewOp;
335	/** Instruction type. */
336	HMTPRINSTR enmType;
337	/** Source operand. */
338	uint32_t uSrcOperand;
339	/** Destination operand. */
340	uint32_t uDstOperand;
341	/** Number of times the instruction caused a fault. */
342	uint32_t cFaults;
343	/** Patch address of the jump replacement. */
344	RTGCPTR32 pJumpTarget;
345	} HMTPRPATCH;
346	/** Pointer to HMTPRPATCH. */
347	typedef HMTPRPATCH *PHMTPRPATCH;
348	/** Pointer to a const HMTPRPATCH. */
349	typedef const HMTPRPATCH *PCHMTPRPATCH;
350
351
352	/**
353	* Makes a HMEXITSTAT::uKey value from a program counter and an exit code.
354	*
355	* @returns 64-bit key
356	* @param a_uPC The RIP + CS.BASE value of the exit.
357	* @param a_uExit The exit code.
358	* @todo Add CPL?
359	*/
360	#define HMEXITSTAT_MAKE_KEY(a_uPC, a_uExit) (((a_uPC) & UINT64_C(0x0000ffffffffffff)) \| (uint64_t)(a_uExit) << 48)
361
362	typedef struct HMEXITINFO
363	{
364	/** See HMEXITSTAT_MAKE_KEY(). */
365	uint64_t uKey;
366	/** Number of recent hits (depreciates with time). */
367	uint32_t volatile cHits;
368	/** The age + lock. */
369	uint16_t volatile uAge;
370	/** Action or action table index. */
371	uint16_t iAction;
372	} HMEXITINFO;
373	AssertCompileSize(HMEXITINFO, 16); /* Lots of these guys, so don't add any unnecessary stuff! */
374
375	typedef struct HMEXITHISTORY
376	{
377	/** The exit timestamp. */
378	uint64_t uTscExit;
379	/** The index of the corresponding HMEXITINFO entry.
380	* UINT32_MAX if none (too many collisions, race, whatever). */
381	uint32_t iExitInfo;
382	/** Figure out later, needed for padding now. */
383	uint32_t uSomeClueOrSomething;
384	} HMEXITHISTORY;
385
386	/**
387	* Switcher function, HC to the special 64-bit RC.
388	*
389	* @param pVM The cross context VM structure.
390	* @param offCpumVCpu Offset from pVM->cpum to pVM->aCpus[idCpu].cpum.
391	* @returns Return code indicating the action to take.
392	*/
393	typedef DECLCALLBACKTYPE(int, FNHMSWITCHERHC,(PVM pVM, uint32_t offCpumVCpu));
394	/** Pointer to switcher function. */
395	typedef FNHMSWITCHERHC *PFNHMSWITCHERHC;
396
397	/** @def HM_UNION_NM
398	* For compilers (like DTrace) that does not grok nameless unions, we have a
399	* little hack to make them palatable.
400	*/
401	/** @def HM_STRUCT_NM
402	* For compilers (like DTrace) that does not grok nameless structs (it is
403	* non-standard C++), we have a little hack to make them palatable.
404	*/
405	/** @def HM_NAMELESS_UNION_TAG
406	* For tagging a nameless union so tstASMStructs.cpp can find check the nested
407	* structures within the union.
408	*/
409	#ifdef VBOX_FOR_DTRACE_LIB
410	# define HM_UNION_NM(a_Nm) a_Nm
411	# define HM_STRUCT_NM(a_Nm) a_Nm
412	# define HM_NAMELESS_UNION_TAG(a_Tag)
413	#elif defined(IPRT_WITHOUT_NAMED_UNIONS_AND_STRUCTS)
414	# define HM_UNION_NM(a_Nm) a_Nm
415	# define HM_STRUCT_NM(a_Nm) a_Nm
416	# define HM_NAMELESS_UNION_TAG(a_Tag) a_Tag
417	#else
418	# define HM_UNION_NM(a_Nm)
419	# define HM_STRUCT_NM(a_Nm)
420	# define HM_NAMELESS_UNION_TAG(a_Tag)
421	#endif
422
423	/**
424	* HM event.
425	*
426	* VT-x and AMD-V common event injection structure.
427	*/
428	typedef struct HMEVENT
429	{
430	/** Whether the event is pending. */
431	uint32_t fPending;
432	/** The error-code associated with the event. */
433	uint32_t u32ErrCode;
434	/** The length of the instruction in bytes (only relevant for software
435	* interrupts or software exceptions). */
436	uint32_t cbInstr;
437	/** Alignment. */
438	uint32_t u32Padding;
439	/** The encoded event (VM-entry interruption-information for VT-x or EVENTINJ
440	* for SVM). */
441	uint64_t u64IntInfo;
442	/** Guest virtual address if this is a page-fault event. */
443	RTGCUINTPTR GCPtrFaultAddress;
444	} HMEVENT;
445	/** Pointer to a HMEVENT struct. */
446	typedef HMEVENT *PHMEVENT;
447	/** Pointer to a const HMEVENT struct. */
448	typedef const HMEVENT *PCHMEVENT;
449	AssertCompileSizeAlignment(HMEVENT, 8);
450
451	/**
452	* HM VM Instance data.
453	* Changes to this must checked against the padding of the hm union in VM!
454	*/
455	typedef struct HM
456	{
457	/** Set if nested paging is enabled. */
458	bool fNestedPaging;
459	/** Set when we've initialized VMX or SVM. */
460	bool fInitialized;
461	/** Set if large pages are enabled (requires nested paging). */
462	bool fLargePages;
463	/** Set if we can support 64-bit guests or not. */
464	bool fAllow64BitGuests;
465	/** Set when TPR patching is allowed. */
466	bool fTprPatchingAllowed;
467	/** Set when we initialize VT-x or AMD-V once for all CPUs. */
468	bool fGlobalInit;
469	/** Set when TPR patching is active. */
470	bool fTPRPatchingActive;
471	/** Set when the debug facility has breakpoints/events enabled that requires
472	* us to use the debug execution loop in ring-0. */
473	bool fUseDebugLoop;
474	/** Set if hardware APIC virtualization is enabled. */
475	bool fVirtApicRegs;
476	/** Set if posted interrupt processing is enabled. */
477	bool fPostedIntrs;
478	/** Set if indirect branch prediction barrier on VM exit. */
479	bool fIbpbOnVmExit;
480	/** Set if indirect branch prediction barrier on VM entry. */
481	bool fIbpbOnVmEntry;
482	/** Set if level 1 data cache should be flushed on VM entry. */
483	bool fL1dFlushOnVmEntry;
484	/** Set if level 1 data cache should be flushed on EMT scheduling. */
485	bool fL1dFlushOnSched;
486	/** Set if host manages speculation control settings. */
487	bool fSpecCtrlByHost;
488	/** Set if MDS related buffers should be cleared on VM entry. */
489	bool fMdsClearOnVmEntry;
490	/** Set if MDS related buffers should be cleared on EMT scheduling. */
491	bool fMdsClearOnSched;
492	/** Alignment padding. */
493	bool afPaddingMinus1[7];
494
495	/** Maximum ASID allowed. */
496	uint32_t uMaxAsid;
497	/** The maximum number of resumes loops allowed in ring-0 (safety precaution).
498	* This number is set much higher when RTThreadPreemptIsPending is reliable. */
499	uint32_t cMaxResumeLoops;
500
501	/** Host kernel flags that HM might need to know (SUPKERNELFEATURES_XXX). */
502	uint32_t fHostKernelFeatures;
503
504	/** Size of the guest patch memory block. */
505	uint32_t cbGuestPatchMem;
506	/** Guest allocated memory for patching purposes. */
507	RTGCPTR pGuestPatchMem;
508	/** Current free pointer inside the patch block. */
509	RTGCPTR pFreeGuestPatchMem;
510
511	struct
512	{
513	/** Set by the ring-0 side of HM to indicate VMX is supported by the
514	* CPU. */
515	bool fSupported;
516	/** Set when we've enabled VMX. */
517	bool fEnabled;
518	/** Set if VPID is supported. */
519	bool fVpid;
520	/** Set if VT-x VPID is allowed. */
521	bool fAllowVpid;
522	/** Set if unrestricted guest execution is in use (real and protected mode
523	* without paging). */
524	bool fUnrestrictedGuest;
525	/** Set if the preemption timer is in use or not. */
526	bool fUsePreemptTimer;
527	/** The shift mask employed by the VMX-Preemption timer. */
528	uint8_t cPreemptTimerShift;
529	/** Padding. */
530	bool afPadding0;
531
532	/** Virtual address of the APIC-access page. */
533	R0PTRTYPE(uint8_t *) pbApicAccess;
534	/** Pointer to the VMREAD bitmap. */
535	R0PTRTYPE(void *) pvVmreadBitmap;
536	/** Pointer to the VMWRITE bitmap. */
537	R0PTRTYPE(void *) pvVmwriteBitmap;
538
539	/** Pointer to the shadow VMCS read-only fields array. */
540	R0PTRTYPE(uint32_t *) paShadowVmcsRoFields;
541	/** Pointer to the shadow VMCS read/write fields array. */
542	R0PTRTYPE(uint32_t *) paShadowVmcsFields;
543	/** Number of elements in the shadow VMCS read-only fields array. */
544	uint32_t cShadowVmcsRoFields;
545	/** Number of elements in the shadow VMCS read-write fields array. */
546	uint32_t cShadowVmcsFields;
547
548	/** Tagged-TLB flush type. */
549	VMXTLBFLUSHTYPE enmTlbFlushType;
550	/** Flush type to use for INVEPT. */
551	VMXTLBFLUSHEPT enmTlbFlushEpt;
552	/** Flush type to use for INVVPID. */
553	VMXTLBFLUSHVPID enmTlbFlushVpid;
554
555	/** Pause-loop exiting (PLE) gap in ticks. */
556	uint32_t cPleGapTicks;
557	/** Pause-loop exiting (PLE) window in ticks. */
558	uint32_t cPleWindowTicks;
559	uint32_t u32Alignment0;
560
561	/** Host CR4 value (set by ring-0 VMX init) */
562	uint64_t u64HostCr4;
563	/** Host SMM monitor control (set by ring-0 VMX init) */
564	uint64_t u64HostSmmMonitorCtl;
565	/** Host EFER value (set by ring-0 VMX init) */
566	uint64_t u64HostMsrEfer;
567	/** Whether the CPU supports VMCS fields for swapping EFER. */
568	bool fSupportsVmcsEfer;
569	/** Whether to use VMCS shadowing. */
570	bool fUseVmcsShadowing;
571	/** Set if Last Branch Record (LBR) is enabled. */
572	bool fLbr;
573	uint8_t u8Alignment2[5];
574
575	/** The first valid host LBR branch-from-IP stack range. */
576	uint32_t idLbrFromIpMsrFirst;
577	/** The last valid host LBR branch-from-IP stack range. */
578	uint32_t idLbrFromIpMsrLast;
579
580	/** The first valid host LBR branch-to-IP stack range. */
581	uint32_t idLbrToIpMsrFirst;
582	/** The last valid host LBR branch-to-IP stack range. */
583	uint32_t idLbrToIpMsrLast;
584
585	/** The host LBR TOS (top-of-stack) MSR id. */
586	uint32_t idLbrTosMsr;
587	/** Padding. */
588	uint32_t u32Alignment1;
589
590	/** VMX MSR values. */
591	VMXMSRS Msrs;
592
593	/** Host-physical address for a failing VMXON instruction. */
594	RTHCPHYS HCPhysVmxEnableError;
595	/** Host-physical address of the APIC-access page. */
596	RTHCPHYS HCPhysApicAccess;
597	/** Host-physical address of the VMREAD bitmap. */
598	RTHCPHYS HCPhysVmreadBitmap;
599	/** Host-physical address of the VMWRITE bitmap. */
600	RTHCPHYS HCPhysVmwriteBitmap;
601	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
602	/** Host-physical address of the crash-dump scratch area. */
603	RTHCPHYS HCPhysScratch;
604	#endif
605
606	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
607	/** Pointer to the crash-dump scratch bitmap. */
608	R0PTRTYPE(uint8_t *) pbScratch;
609	#endif
610	/** Virtual address of the TSS page used for real mode emulation. */
611	R3PTRTYPE(PVBOXTSS) pRealModeTSS;
612	/** Virtual address of the identity page table used for real mode and protected
613	* mode without paging emulation in EPT mode. */
614	R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
615
616	/** Ring-0 memory object for per-VM VMX structures. */
617	RTR0MEMOBJ hMemObj;
618	} vmx;
619
620	struct
621	{
622	/** Set by the ring-0 side of HM to indicate SVM is supported by the
623	* CPU. */
624	bool fSupported;
625	/** Set when we've enabled SVM. */
626	bool fEnabled;
627	/** Set if erratum 170 affects the AMD cpu. */
628	bool fAlwaysFlushTLB;
629	/** Set when the hack to ignore VERR_SVM_IN_USE is active. */
630	bool fIgnoreInUseError;
631	/** Whether to use virtualized VMSAVE/VMLOAD feature. */
632	bool fVirtVmsaveVmload;
633	/** Whether to use virtual GIF feature. */
634	bool fVGif;
635	/** Whether to use LBR virtualization feature. */
636	bool fLbrVirt;
637	uint8_t u8Alignment0[1];
638
639	/** Physical address of the IO bitmap (12kb). */
640	RTHCPHYS HCPhysIOBitmap;
641	/** R0 memory object for the IO bitmap (12kb). */
642	RTR0MEMOBJ hMemObjIOBitmap;
643	/** Virtual address of the IO bitmap. */
644	R0PTRTYPE(void *) pvIOBitmap;
645
646	/* HWCR MSR (for diagnostics) */
647	uint64_t u64MsrHwcr;
648
649	/** SVM revision. */
650	uint32_t u32Rev;
651	/** SVM feature bits from cpuid 0x8000000a */
652	uint32_t u32Features;
653
654	/** Pause filter counter. */
655	uint16_t cPauseFilter;
656	/** Pause filter treshold in ticks. */
657	uint16_t cPauseFilterThresholdTicks;
658	uint32_t u32Alignment0;
659	} svm;
660
661	/**
662	* AVL tree with all patches (active or disabled) sorted by guest instruction
663	* address.
664	*/
665	AVLOU32TREE PatchTree;
666	uint32_t cPatches;
667	HMTPRPATCH aPatches[64];
668
669	/** Last recorded error code during HM ring-0 init. */
670	int32_t rcInit;
671
672	/** HMR0Init was run */
673	bool fHMR0Init;
674	bool u8Alignment1[3];
675
676	STAMCOUNTER StatTprPatchSuccess;
677	STAMCOUNTER StatTprPatchFailure;
678	STAMCOUNTER StatTprReplaceSuccessCr8;
679	STAMCOUNTER StatTprReplaceSuccessVmc;
680	STAMCOUNTER StatTprReplaceFailure;
681	} HM;
682	/** Pointer to HM VM instance data. */
683	typedef HM *PHM;
684	AssertCompileMemberAlignment(HM, StatTprPatchSuccess, 8);
685	AssertCompileMemberAlignment(HM, vmx, 8);
686	AssertCompileMemberAlignment(HM, svm, 8);
687
688
689	/**
690	* VMX StartVM function.
691	*
692	* @returns VBox status code (no informational stuff).
693	* @param fResume Whether to use VMRESUME (true) or VMLAUNCH (false).
694	* @param pCtx The CPU register context.
695	* @param pvUnused Unused argument.
696	* @param pVM Pointer to the cross context VM structure.
697	* @param pVCpu Pointer to the cross context per-CPU structure.
698	*/
699	typedef DECLCALLBACKTYPE(int, FNHMVMXSTARTVM,(RTHCUINT fResume, PCPUMCTX pCtx, void *pvUnused, PVMCC pVM, PVMCPUCC pVCpu));
700	/** Pointer to a VMX StartVM function. */
701	typedef R0PTRTYPE(FNHMVMXSTARTVM *) PFNHMVMXSTARTVM;
702
703	/** SVM VMRun function, see SVMR0VMRun(). */
704	typedef DECLCALLBACKTYPE(int, FNHMSVMVMRUN,(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhysVMCB));
705	/** Pointer to a SVM VMRun function. */
706	typedef R0PTRTYPE(FNHMSVMVMRUN *) PFNHMSVMVMRUN;
707
708	/**
709	* VMX VMCS information.
710	*
711	* This structure provides information maintained for and during the executing of a
712	* guest (or nested-guest) VMCS (VM control structure) using hardware-assisted VMX.
713	*
714	* Note! The members here are ordered and aligned based on estimated frequency of
715	* usage and grouped to fit within a cache line in hot code paths. Even subtle
716	* changes here have a noticeable effect in the bootsector benchmarks. Modify with
717	* care.
718	*/
719	typedef struct VMXVMCSINFO
720	{
721	/** @name Auxiliary information.
722	* @{ */
723	/** Ring-0 pointer to the hardware-assisted VMX execution function. */
724	PFNHMVMXSTARTVM pfnStartVM;
725	/** Host-physical address of the EPTP. */
726	RTHCPHYS HCPhysEPTP;
727	/** The VMCS launch state, see VMX_V_VMCS_LAUNCH_STATE_XXX. */
728	uint32_t fVmcsState;
729	/** The VMCS launch state of the shadow VMCS, see VMX_V_VMCS_LAUNCH_STATE_XXX. */
730	uint32_t fShadowVmcsState;
731	/** The host CPU for which its state has been exported to this VMCS. */
732	RTCPUID idHostCpuState;
733	/** The host CPU on which we last executed this VMCS. */
734	RTCPUID idHostCpuExec;
735	/** Number of guest MSRs in the VM-entry MSR-load area. */
736	uint32_t cEntryMsrLoad;
737	/** Number of guest MSRs in the VM-exit MSR-store area. */
738	uint32_t cExitMsrStore;
739	/** Number of host MSRs in the VM-exit MSR-load area. */
740	uint32_t cExitMsrLoad;
741	/** @} */
742
743	/** @name Cache of execution related VMCS fields.
744	* @{ */
745	/** Pin-based VM-execution controls. */
746	uint32_t u32PinCtls;
747	/** Processor-based VM-execution controls. */
748	uint32_t u32ProcCtls;
749	/** Secondary processor-based VM-execution controls. */
750	uint32_t u32ProcCtls2;
751	/** VM-entry controls. */
752	uint32_t u32EntryCtls;
753	/** VM-exit controls. */
754	uint32_t u32ExitCtls;
755	/** Exception bitmap. */
756	uint32_t u32XcptBitmap;
757	/** Page-fault exception error-code mask. */
758	uint32_t u32XcptPFMask;
759	/** Page-fault exception error-code match. */
760	uint32_t u32XcptPFMatch;
761	/** Padding. */
762	uint32_t u32Alignment0;
763	/** TSC offset. */
764	uint64_t u64TscOffset;
765	/** VMCS link pointer. */
766	uint64_t u64VmcsLinkPtr;
767	/** CR0 guest/host mask. */
768	uint64_t u64Cr0Mask;
769	/** CR4 guest/host mask. */
770	uint64_t u64Cr4Mask;
771	/** @} */
772
773	/** @name Host-virtual address of VMCS and related data structures.
774	* @{ */
775	/** The VMCS. */
776	R0PTRTYPE(void *) pvVmcs;
777	/** The shadow VMCS. */
778	R0PTRTYPE(void *) pvShadowVmcs;
779	/** The virtual-APIC page. */
780	R0PTRTYPE(uint8_t *) pbVirtApic;
781	/** The MSR bitmap. */
782	R0PTRTYPE(void *) pvMsrBitmap;
783	/** The VM-entry MSR-load area. */
784	R0PTRTYPE(void *) pvGuestMsrLoad;
785	/** The VM-exit MSR-store area. */
786	R0PTRTYPE(void *) pvGuestMsrStore;
787	/** The VM-exit MSR-load area. */
788	R0PTRTYPE(void *) pvHostMsrLoad;
789	/** @} */
790
791	/** @name Real-mode emulation state.
792	* @{ */
793	/** Set if guest was executing in real mode (extra checks). */
794	bool fWasInRealMode;
795	/** Set if the guest switched to 64-bit mode on a 32-bit host. */
796	bool fSwitchedTo64on32Obsolete;
797	/** Padding. */
798	bool afPadding0[6];
799	struct
800	{
801	X86DESCATTR AttrCS;
802	X86DESCATTR AttrDS;
803	X86DESCATTR AttrES;
804	X86DESCATTR AttrFS;
805	X86DESCATTR AttrGS;
806	X86DESCATTR AttrSS;
807	X86EFLAGS Eflags;
808	bool fRealOnV86Active;
809	bool afPadding1[3];
810	} RealMode;
811	/** @} */
812
813	/** @name Host-physical address of VMCS and related data structures.
814	* @{ */
815	/** The VMCS. */
816	RTHCPHYS HCPhysVmcs;
817	/** The shadow VMCS. */
818	RTHCPHYS HCPhysShadowVmcs;
819	/** The virtual APIC page. */
820	RTHCPHYS HCPhysVirtApic;
821	/** The MSR bitmap. */
822	RTHCPHYS HCPhysMsrBitmap;
823	/** The VM-entry MSR-load area. */
824	RTHCPHYS HCPhysGuestMsrLoad;
825	/** The VM-exit MSR-store area. */
826	RTHCPHYS HCPhysGuestMsrStore;
827	/** The VM-exit MSR-load area. */
828	RTHCPHYS HCPhysHostMsrLoad;
829	/** @} */
830
831	/** @name R0-memory objects address for VMCS and related data structures.
832	* @{ */
833	/** R0-memory object for VMCS and related data structures. */
834	RTR0MEMOBJ hMemObj;
835	/** @} */
836
837	/** @name LBR MSR data.
838	* @{ */
839	/** List of LastBranch-From-IP MSRs. */
840	uint64_t au64LbrFromIpMsr[32];
841	/** List of LastBranch-To-IP MSRs. */
842	uint64_t au64LbrToIpMsr[32];
843	/** The MSR containing the index to the most recent branch record. */
844	uint64_t u64LbrTosMsr;
845	/** @} */
846	} VMXVMCSINFO;
847	/** Pointer to a VMXVMCSINFO struct. */
848	typedef VMXVMCSINFO *PVMXVMCSINFO;
849	/** Pointer to a const VMXVMCSINFO struct. */
850	typedef const VMXVMCSINFO *PCVMXVMCSINFO;
851	AssertCompileSizeAlignment(VMXVMCSINFO, 8);
852	AssertCompileMemberAlignment(VMXVMCSINFO, pfnStartVM, 8);
853	AssertCompileMemberAlignment(VMXVMCSINFO, u32PinCtls, 4);
854	AssertCompileMemberAlignment(VMXVMCSINFO, u64VmcsLinkPtr, 8);
855	AssertCompileMemberAlignment(VMXVMCSINFO, pvVmcs, 8);
856	AssertCompileMemberAlignment(VMXVMCSINFO, pvShadowVmcs, 8);
857	AssertCompileMemberAlignment(VMXVMCSINFO, pbVirtApic, 8);
858	AssertCompileMemberAlignment(VMXVMCSINFO, pvMsrBitmap, 8);
859	AssertCompileMemberAlignment(VMXVMCSINFO, pvGuestMsrLoad, 8);
860	AssertCompileMemberAlignment(VMXVMCSINFO, pvGuestMsrStore, 8);
861	AssertCompileMemberAlignment(VMXVMCSINFO, pvHostMsrLoad, 8);
862	AssertCompileMemberAlignment(VMXVMCSINFO, HCPhysVmcs, 8);
863	AssertCompileMemberAlignment(VMXVMCSINFO, hMemObj, 8);
864
865	/**
866	* HM VMCPU Instance data.
867	*
868	* Note! If you change members of this struct, make sure to check if the
869	* assembly counterpart in HMInternal.mac needs to be updated as well.
870	*
871	* Note! The members here are ordered and aligned based on estimated frequency of
872	* usage and grouped to fit within a cache line in hot code paths. Even subtle
873	* changes here have a noticeable effect in the bootsector benchmarks. Modify with
874	* care.
875	*/
876	typedef struct HMCPU
877	{
878	/** Set when the TLB has been checked until we return from the world switch. */
879	bool volatile fCheckedTLBFlush;
880	/** Set when we're using VT-x or AMD-V at that moment. */
881	bool fActive;
882	/** Whether we've completed the inner HM leave function. */
883	bool fLeaveDone;
884	/** Whether we're using the hyper DR7 or guest DR7. */
885	bool fUsingHyperDR7;
886
887	/** Set if we need to flush the TLB during the world switch. */
888	bool fForceTLBFlush;
889	/** Whether we should use the debug loop because of single stepping or special
890	* debug breakpoints / events are armed. */
891	bool fUseDebugLoop;
892	/** Whether we are currently executing in the debug loop.
893	* Mainly for assertions. */
894	bool fUsingDebugLoop;
895	/** Set if we using the debug loop and wish to intercept RDTSC. */
896	bool fDebugWantRdTscExit;
897
898	/** Set if XCR0 needs to be saved/restored when entering/exiting guest code
899	* execution. */
900	bool fLoadSaveGuestXcr0;
901	/** Whether \#UD needs to be intercepted (required by certain GIM providers). */
902	bool fGIMTrapXcptUD;
903	/** Whether \#GP needs to be intercepted for mesa driver workaround. */
904	bool fTrapXcptGpForLovelyMesaDrv;
905	/** Whether we're executing a single instruction. */
906	bool fSingleInstruction;
907
908	/** Set if we need to clear the trap flag because of single stepping. */
909	bool fClearTrapFlag;
910	bool afAlignment0[3];
911
912	/** World switch exit counter. */
913	uint32_t volatile cWorldSwitchExits;
914	/** The last CPU we were executing code on (NIL_RTCPUID for the first time). */
915	RTCPUID idLastCpu;
916	/** TLB flush count. */
917	uint32_t cTlbFlushes;
918	/** Current ASID in use by the VM. */
919	uint32_t uCurrentAsid;
920	/** An additional error code used for some gurus. */
921	uint32_t u32HMError;
922	/** The last exit-to-ring-3 reason. */
923	int32_t rcLastExitToR3;
924	/** CPU-context changed flags (see HM_CHANGED_xxx). */
925	uint64_t fCtxChanged;
926
927	union HM_NAMELESS_UNION_TAG(HMCPUUNION) /* no tag! */
928	{
929	/** VT-x data. */
930	struct HM_NAMELESS_UNION_TAG(HMCPUVMX)
931	{
932	/** @name Guest information.
933	* @{ */
934	/** Guest VMCS information. */
935	VMXVMCSINFO VmcsInfo;
936	/** Nested-guest VMCS information. */
937	VMXVMCSINFO VmcsInfoNstGst;
938	/** Whether the nested-guest VMCS was the last current VMCS. */
939	bool fSwitchedToNstGstVmcs;
940	/** Whether the static guest VMCS controls has been merged with the
941	* nested-guest VMCS controls. */
942	bool fMergedNstGstCtls;
943	/** Whether the nested-guest VMCS has been copied to the shadow VMCS. */
944	bool fCopiedNstGstToShadowVmcs;
945	/** Whether flushing the TLB is required due to switching to/from the
946	* nested-guest. */
947	bool fSwitchedNstGstFlushTlb;
948	/** Alignment. */
949	bool afAlignment0[4];
950	/** Cached guest APIC-base MSR for identifying when to map the APIC-access page. */
951	uint64_t u64GstMsrApicBase;
952	/** @} */
953
954	/** @name Host information.
955	* @{ */
956	/** Host LSTAR MSR to restore lazily while leaving VT-x. */
957	uint64_t u64HostMsrLStar;
958	/** Host STAR MSR to restore lazily while leaving VT-x. */
959	uint64_t u64HostMsrStar;
960	/** Host SF_MASK MSR to restore lazily while leaving VT-x. */
961	uint64_t u64HostMsrSfMask;
962	/** Host KernelGS-Base MSR to restore lazily while leaving VT-x. */
963	uint64_t u64HostMsrKernelGsBase;
964	/** The mask of lazy MSRs swap/restore state, see VMX_LAZY_MSRS_XXX. */
965	uint32_t fLazyMsrs;
966	/** Whether the host MSR values are up-to-date in the auto-load/store MSR area. */
967	bool fUpdatedHostAutoMsrs;
968	/** Alignment. */
969	uint8_t au8Alignment0[3];
970	/** Which host-state bits to restore before being preempted. */
971	uint32_t fRestoreHostFlags;
972	/** Alignment. */
973	uint32_t u32Alignment0;
974	/** The host-state restoration structure. */
975	VMXRESTOREHOST RestoreHost;
976	/** @} */
977
978	/** @name Error reporting and diagnostics.
979	* @{ */
980	/** VT-x error-reporting (mainly for ring-3 propagation). */
981	struct
982	{
983	RTCPUID idCurrentCpu;
984	RTCPUID idEnteredCpu;
985	RTHCPHYS HCPhysCurrentVmcs;
986	uint32_t u32VmcsRev;
987	uint32_t u32InstrError;
988	uint32_t u32ExitReason;
989	uint32_t u32GuestIntrState;
990	} LastError;
991	/** @} */
992	} vmx;
993
994	/** SVM data. */
995	struct HM_NAMELESS_UNION_TAG(HMCPUSVM)
996	{
997	/** Ring 0 handlers for VT-x. */
998	PFNHMSVMVMRUN pfnVMRun;
999
1000	/** Physical address of the host VMCB which holds additional host-state. */
1001	RTHCPHYS HCPhysVmcbHost;
1002	/** R0 memory object for the host VMCB which holds additional host-state. */
1003	RTR0MEMOBJ hMemObjVmcbHost;
1004	/** Padding.
1005	* @todo remove, pointless now */
1006	R0PTRTYPE(void *) pvPadding;
1007
1008	/** Physical address of the guest VMCB. */
1009	RTHCPHYS HCPhysVmcb;
1010	/** R0 memory object for the guest VMCB. */
1011	RTR0MEMOBJ hMemObjVmcb;
1012	/** Pointer to the guest VMCB. */
1013	R0PTRTYPE(PSVMVMCB) pVmcb;
1014
1015	/** Physical address of the MSR bitmap (8 KB). */
1016	RTHCPHYS HCPhysMsrBitmap;
1017	/** R0 memory object for the MSR bitmap (8 KB). */
1018	RTR0MEMOBJ hMemObjMsrBitmap;
1019	/** Pointer to the MSR bitmap. */
1020	R0PTRTYPE(void *) pvMsrBitmap;
1021
1022	/** Whether VTPR with V_INTR_MASKING set is in effect, indicating
1023	* we should check if the VTPR changed on every VM-exit. */
1024	bool fSyncVTpr;
1025	/** Whether to emulate long mode support for sysenter/sysexit like intel CPUs
1026	* does. This means intercepting \#UD to emulate the instructions in
1027	* long-mode and to intercept reads and writes to the SYSENTER MSRs in order to
1028	* preserve the upper 32 bits written to them (AMD will ignore and discard). */
1029	bool fEmulateLongModeSysEnterExit;
1030	uint8_t au8Alignment0[6];
1031
1032	/** Host's TSC_AUX MSR (used when RDTSCP doesn't cause VM-exits). */
1033	uint64_t u64HostTscAux;
1034
1035	/** Cache of the nested-guest's VMCB fields that we modify in order to run the
1036	* nested-guest using AMD-V. This will be restored on \#VMEXIT. */
1037	SVMNESTEDVMCBCACHE NstGstVmcbCache;
1038	} svm;
1039	} HM_UNION_NM(u);
1040
1041	/** Event injection state. */
1042	HMEVENT Event;
1043
1044	/** The CPU ID of the CPU currently owning the VMCS. Set in
1045	* HMR0Enter and cleared in HMR0Leave. */
1046	RTCPUID idEnteredCpu;
1047
1048	/** Current shadow paging mode for updating CR4. */
1049	PGMMODE enmShadowMode;
1050
1051	/** The PAE PDPEs used with Nested Paging (only valid when
1052	* VMCPU_FF_HM_UPDATE_PAE_PDPES is set). */
1053	X86PDPE aPdpes[4];
1054
1055	/** For saving stack space, the disassembler state is allocated here instead of
1056	* on the stack. */
1057	DISCPUSTATE DisState;
1058
1059	STAMPROFILEADV StatEntry;
1060	STAMPROFILEADV StatPreExit;
1061	STAMPROFILEADV StatExitHandling;
1062	STAMPROFILEADV StatExitIO;
1063	STAMPROFILEADV StatExitMovCRx;
1064	STAMPROFILEADV StatExitXcptNmi;
1065	STAMPROFILEADV StatExitVmentry;
1066	STAMPROFILEADV StatImportGuestState;
1067	STAMPROFILEADV StatExportGuestState;
1068	STAMPROFILEADV StatLoadGuestFpuState;
1069	STAMPROFILEADV StatInGC;
1070	STAMPROFILEADV StatPoke;
1071	STAMPROFILEADV StatSpinPoke;
1072	STAMPROFILEADV StatSpinPokeFailed;
1073
1074	STAMCOUNTER StatInjectInterrupt;
1075	STAMCOUNTER StatInjectXcpt;
1076	STAMCOUNTER StatInjectReflect;
1077	STAMCOUNTER StatInjectConvertDF;
1078	STAMCOUNTER StatInjectInterpret;
1079	STAMCOUNTER StatInjectReflectNPF;
1080
1081	STAMCOUNTER StatExitAll;
1082	STAMCOUNTER StatNestedExitAll;
1083	STAMCOUNTER StatExitShadowNM;
1084	STAMCOUNTER StatExitGuestNM;
1085	STAMCOUNTER StatExitShadowPF; /*< Misleading, currently used for MMIO \#PFs as well. /
1086	STAMCOUNTER StatExitShadowPFEM;
1087	STAMCOUNTER StatExitGuestPF;
1088	STAMCOUNTER StatExitGuestUD;
1089	STAMCOUNTER StatExitGuestSS;
1090	STAMCOUNTER StatExitGuestNP;
1091	STAMCOUNTER StatExitGuestTS;
1092	STAMCOUNTER StatExitGuestOF;
1093	STAMCOUNTER StatExitGuestGP;
1094	STAMCOUNTER StatExitGuestDE;
1095	STAMCOUNTER StatExitGuestDF;
1096	STAMCOUNTER StatExitGuestBR;
1097	STAMCOUNTER StatExitGuestAC;
1098	STAMCOUNTER StatExitGuestDB;
1099	STAMCOUNTER StatExitGuestMF;
1100	STAMCOUNTER StatExitGuestBP;
1101	STAMCOUNTER StatExitGuestXF;
1102	STAMCOUNTER StatExitGuestXcpUnk;
1103	STAMCOUNTER StatExitDRxWrite;
1104	STAMCOUNTER StatExitDRxRead;
1105	STAMCOUNTER StatExitCR0Read;
1106	STAMCOUNTER StatExitCR2Read;
1107	STAMCOUNTER StatExitCR3Read;
1108	STAMCOUNTER StatExitCR4Read;
1109	STAMCOUNTER StatExitCR8Read;
1110	STAMCOUNTER StatExitCR0Write;
1111	STAMCOUNTER StatExitCR2Write;
1112	STAMCOUNTER StatExitCR3Write;
1113	STAMCOUNTER StatExitCR4Write;
1114	STAMCOUNTER StatExitCR8Write;
1115	STAMCOUNTER StatExitRdmsr;
1116	STAMCOUNTER StatExitWrmsr;
1117	STAMCOUNTER StatExitClts;
1118	STAMCOUNTER StatExitXdtrAccess;
1119	STAMCOUNTER StatExitLmsw;
1120	STAMCOUNTER StatExitIOWrite;
1121	STAMCOUNTER StatExitIORead;
1122	STAMCOUNTER StatExitIOStringWrite;
1123	STAMCOUNTER StatExitIOStringRead;
1124	STAMCOUNTER StatExitIntWindow;
1125	STAMCOUNTER StatExitExtInt;
1126	STAMCOUNTER StatExitHostNmiInGC;
1127	STAMCOUNTER StatExitHostNmiInGCIpi;
1128	STAMCOUNTER StatExitPreemptTimer;
1129	STAMCOUNTER StatExitTprBelowThreshold;
1130	STAMCOUNTER StatExitTaskSwitch;
1131	STAMCOUNTER StatExitApicAccess;
1132	STAMCOUNTER StatExitReasonNpf;
1133
1134	STAMCOUNTER StatNestedExitReasonNpf;
1135
1136	STAMCOUNTER StatFlushPage;
1137	STAMCOUNTER StatFlushPageManual;
1138	STAMCOUNTER StatFlushPhysPageManual;
1139	STAMCOUNTER StatFlushTlb;
1140	STAMCOUNTER StatFlushTlbNstGst;
1141	STAMCOUNTER StatFlushTlbManual;
1142	STAMCOUNTER StatFlushTlbWorldSwitch;
1143	STAMCOUNTER StatNoFlushTlbWorldSwitch;
1144	STAMCOUNTER StatFlushEntire;
1145	STAMCOUNTER StatFlushAsid;
1146	STAMCOUNTER StatFlushNestedPaging;
1147	STAMCOUNTER StatFlushTlbInvlpgVirt;
1148	STAMCOUNTER StatFlushTlbInvlpgPhys;
1149	STAMCOUNTER StatTlbShootdown;
1150	STAMCOUNTER StatTlbShootdownFlush;
1151
1152	STAMCOUNTER StatSwitchPendingHostIrq;
1153	STAMCOUNTER StatSwitchTprMaskedIrq;
1154	STAMCOUNTER StatSwitchGuestIrq;
1155	STAMCOUNTER StatSwitchHmToR3FF;
1156	STAMCOUNTER StatSwitchVmReq;
1157	STAMCOUNTER StatSwitchPgmPoolFlush;
1158	STAMCOUNTER StatSwitchDma;
1159	STAMCOUNTER StatSwitchExitToR3;
1160	STAMCOUNTER StatSwitchLongJmpToR3;
1161	STAMCOUNTER StatSwitchMaxResumeLoops;
1162	STAMCOUNTER StatSwitchHltToR3;
1163	STAMCOUNTER StatSwitchApicAccessToR3;
1164	STAMCOUNTER StatSwitchPreempt;
1165	STAMCOUNTER StatSwitchNstGstVmexit;
1166
1167	STAMCOUNTER StatTscParavirt;
1168	STAMCOUNTER StatTscOffset;
1169	STAMCOUNTER StatTscIntercept;
1170
1171	STAMCOUNTER StatDRxArmed;
1172	STAMCOUNTER StatDRxContextSwitch;
1173	STAMCOUNTER StatDRxIoCheck;
1174
1175	STAMCOUNTER StatExportMinimal;
1176	STAMCOUNTER StatExportFull;
1177	STAMCOUNTER StatLoadGuestFpu;
1178	STAMCOUNTER StatExportHostState;
1179
1180	STAMCOUNTER StatVmxCheckBadRmSelBase;
1181	STAMCOUNTER StatVmxCheckBadRmSelLimit;
1182	STAMCOUNTER StatVmxCheckBadRmSelAttr;
1183	STAMCOUNTER StatVmxCheckBadV86SelBase;
1184	STAMCOUNTER StatVmxCheckBadV86SelLimit;
1185	STAMCOUNTER StatVmxCheckBadV86SelAttr;
1186	STAMCOUNTER StatVmxCheckRmOk;
1187	STAMCOUNTER StatVmxCheckBadSel;
1188	STAMCOUNTER StatVmxCheckBadRpl;
1189	STAMCOUNTER StatVmxCheckPmOk;
1190
1191	#ifdef VBOX_WITH_STATISTICS
1192	R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
1193	R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
1194	R3PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqs;
1195	R0PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqsR0;
1196	R3PTRTYPE(PSTAMCOUNTER) paStatInjectedXcpts;
1197	R0PTRTYPE(PSTAMCOUNTER) paStatInjectedXcptsR0;
1198	R3PTRTYPE(PSTAMCOUNTER) paStatNestedExitReason;
1199	R0PTRTYPE(PSTAMCOUNTER) paStatNestedExitReasonR0;
1200	#endif
1201	#ifdef HM_PROFILE_EXIT_DISPATCH
1202	STAMPROFILEADV StatExitDispatch;
1203	#endif
1204	} HMCPU;
1205	/** Pointer to HM VMCPU instance data. */
1206	typedef HMCPU *PHMCPU;
1207	AssertCompileMemberAlignment(HMCPU, fCheckedTLBFlush, 4);
1208	AssertCompileMemberAlignment(HMCPU, fForceTLBFlush, 4);
1209	AssertCompileMemberAlignment(HMCPU, cWorldSwitchExits, 4);
1210	AssertCompileMemberAlignment(HMCPU, fCtxChanged, 8);
1211	AssertCompileMemberAlignment(HMCPU, HM_UNION_NM(u.) vmx, 8);
1212	AssertCompileMemberAlignment(HMCPU, HM_UNION_NM(u.) vmx.VmcsInfo, 8);
1213	AssertCompileMemberAlignment(HMCPU, HM_UNION_NM(u.) vmx.VmcsInfoNstGst, 8);
1214	AssertCompileMemberAlignment(HMCPU, HM_UNION_NM(u.) vmx.RestoreHost, 8);
1215	AssertCompileMemberAlignment(HMCPU, HM_UNION_NM(u.) svm, 8);
1216	AssertCompileMemberAlignment(HMCPU, Event, 8);
1217
1218	#ifdef IN_RING0
1219	VMMR0_INT_DECL(PHMPHYSCPU) hmR0GetCurrentCpu(void);
1220	VMMR0_INT_DECL(int) hmR0EnterCpu(PVMCPUCC pVCpu);
1221
1222	# ifdef VBOX_STRICT
1223	# define HM_DUMP_REG_FLAGS_GPRS RT_BIT(0)
1224	# define HM_DUMP_REG_FLAGS_FPU RT_BIT(1)
1225	# define HM_DUMP_REG_FLAGS_MSRS RT_BIT(2)
1226	# define HM_DUMP_REG_FLAGS_ALL (HM_DUMP_REG_FLAGS_GPRS \| HM_DUMP_REG_FLAGS_FPU \| HM_DUMP_REG_FLAGS_MSRS)
1227
1228	VMMR0_INT_DECL(void) hmR0DumpRegs(PVMCPUCC pVCpu, uint32_t fFlags);
1229	VMMR0_INT_DECL(void) hmR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg);
1230	# endif
1231
1232	# ifdef VBOX_WITH_KERNEL_USING_XMM
1233	DECLASM(int) hmR0VMXStartVMWrapXMM(RTHCUINT fResume, PCPUMCTX pCtx, void *pvUnused, PVMCC pVM, PVMCPUCC pVCpu,
1234	PFNHMVMXSTARTVM pfnStartVM);
1235	DECLASM(int) hmR0SVMRunWrapXMM(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB, PFNHMSVMVMRUN pfnVMRun);
1236	# endif
1237	DECLASM(void) hmR0MdsClear(void);
1238	#endif /* IN_RING0 */
1239
1240	VMM_INT_DECL(int) hmEmulateSvmMovTpr(PVMCC pVM, PVMCPUCC pVCpu);
1241
1242	VMM_INT_DECL(PVMXVMCSINFO) hmGetVmxActiveVmcsInfo(PVMCPU pVCpu);
1243
1244	/** @} */
1245
1246	RT_C_DECLS_END
1247
1248	#endif /* !VMM_INCLUDED_SRC_include_HMInternal_h */
1249

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source: vbox/trunk/src/VBox/VMM/include/HMInternal.h@ 87359

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