VirtualBox

source: vbox/trunk/src/VBox/VMM/include/HMInternal.h@ 87504

Last change on this file since 87504 was 87504, checked in by vboxsync, 4 years ago

VMM/HMSVM: Moving more stuff to HMR0PERVCPU. bugref:9217
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1/* $Id: HMInternal.h 87504 2021-02-01 15:12:21Z vboxsync $ */
2/** @file
3 * HM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef VMM_INCLUDED_SRC_include_HMInternal_h
19#define VMM_INCLUDED_SRC_include_HMInternal_h
20#ifndef RT_WITHOUT_PRAGMA_ONCE
21# pragma once
22#endif
23
24#include <VBox/cdefs.h>
25#include <VBox/types.h>
26#include <VBox/vmm/stam.h>
27#include <VBox/dis.h>
28#include <VBox/vmm/hm.h>
29#include <VBox/vmm/hm_vmx.h>
30#include <VBox/vmm/hm_svm.h>
31#include <VBox/vmm/pgm.h>
32#include <VBox/vmm/cpum.h>
33#include <VBox/vmm/trpm.h>
34#include <iprt/memobj.h>
35#include <iprt/cpuset.h>
36#include <iprt/mp.h>
37#include <iprt/avl.h>
38#include <iprt/string.h>
39
40#if HC_ARCH_BITS == 32
41# error "32-bit hosts are no longer supported. Go back to 6.0 or earlier!"
42#endif
43
44/** @def HM_PROFILE_EXIT_DISPATCH
45 * Enables profiling of the VM exit handler dispatching. */
46#if 0 || defined(DOXYGEN_RUNNING)
47# define HM_PROFILE_EXIT_DISPATCH
48#endif
49
50RT_C_DECLS_BEGIN
51
52
53/** @defgroup grp_hm_int Internal
54 * @ingroup grp_hm
55 * @internal
56 * @{
57 */
58
59/** @name HM_CHANGED_XXX
60 * HM CPU-context changed flags.
61 *
62 * These flags are used to keep track of which registers and state has been
63 * modified since they were imported back into the guest-CPU context.
64 *
65 * @{
66 */
67#define HM_CHANGED_HOST_CONTEXT UINT64_C(0x0000000000000001)
68#define HM_CHANGED_GUEST_RIP UINT64_C(0x0000000000000004)
69#define HM_CHANGED_GUEST_RFLAGS UINT64_C(0x0000000000000008)
70
71#define HM_CHANGED_GUEST_RAX UINT64_C(0x0000000000000010)
72#define HM_CHANGED_GUEST_RCX UINT64_C(0x0000000000000020)
73#define HM_CHANGED_GUEST_RDX UINT64_C(0x0000000000000040)
74#define HM_CHANGED_GUEST_RBX UINT64_C(0x0000000000000080)
75#define HM_CHANGED_GUEST_RSP UINT64_C(0x0000000000000100)
76#define HM_CHANGED_GUEST_RBP UINT64_C(0x0000000000000200)
77#define HM_CHANGED_GUEST_RSI UINT64_C(0x0000000000000400)
78#define HM_CHANGED_GUEST_RDI UINT64_C(0x0000000000000800)
79#define HM_CHANGED_GUEST_R8_R15 UINT64_C(0x0000000000001000)
80#define HM_CHANGED_GUEST_GPRS_MASK UINT64_C(0x0000000000001ff0)
81
82#define HM_CHANGED_GUEST_ES UINT64_C(0x0000000000002000)
83#define HM_CHANGED_GUEST_CS UINT64_C(0x0000000000004000)
84#define HM_CHANGED_GUEST_SS UINT64_C(0x0000000000008000)
85#define HM_CHANGED_GUEST_DS UINT64_C(0x0000000000010000)
86#define HM_CHANGED_GUEST_FS UINT64_C(0x0000000000020000)
87#define HM_CHANGED_GUEST_GS UINT64_C(0x0000000000040000)
88#define HM_CHANGED_GUEST_SREG_MASK UINT64_C(0x000000000007e000)
89
90#define HM_CHANGED_GUEST_GDTR UINT64_C(0x0000000000080000)
91#define HM_CHANGED_GUEST_IDTR UINT64_C(0x0000000000100000)
92#define HM_CHANGED_GUEST_LDTR UINT64_C(0x0000000000200000)
93#define HM_CHANGED_GUEST_TR UINT64_C(0x0000000000400000)
94#define HM_CHANGED_GUEST_TABLE_MASK UINT64_C(0x0000000000780000)
95
96#define HM_CHANGED_GUEST_CR0 UINT64_C(0x0000000000800000)
97#define HM_CHANGED_GUEST_CR2 UINT64_C(0x0000000001000000)
98#define HM_CHANGED_GUEST_CR3 UINT64_C(0x0000000002000000)
99#define HM_CHANGED_GUEST_CR4 UINT64_C(0x0000000004000000)
100#define HM_CHANGED_GUEST_CR_MASK UINT64_C(0x0000000007800000)
101
102#define HM_CHANGED_GUEST_APIC_TPR UINT64_C(0x0000000008000000)
103#define HM_CHANGED_GUEST_EFER_MSR UINT64_C(0x0000000010000000)
104
105#define HM_CHANGED_GUEST_DR0_DR3 UINT64_C(0x0000000020000000)
106#define HM_CHANGED_GUEST_DR6 UINT64_C(0x0000000040000000)
107#define HM_CHANGED_GUEST_DR7 UINT64_C(0x0000000080000000)
108#define HM_CHANGED_GUEST_DR_MASK UINT64_C(0x00000000e0000000)
109
110#define HM_CHANGED_GUEST_X87 UINT64_C(0x0000000100000000)
111#define HM_CHANGED_GUEST_SSE_AVX UINT64_C(0x0000000200000000)
112#define HM_CHANGED_GUEST_OTHER_XSAVE UINT64_C(0x0000000400000000)
113#define HM_CHANGED_GUEST_XCRx UINT64_C(0x0000000800000000)
114
115#define HM_CHANGED_GUEST_KERNEL_GS_BASE UINT64_C(0x0000001000000000)
116#define HM_CHANGED_GUEST_SYSCALL_MSRS UINT64_C(0x0000002000000000)
117#define HM_CHANGED_GUEST_SYSENTER_CS_MSR UINT64_C(0x0000004000000000)
118#define HM_CHANGED_GUEST_SYSENTER_EIP_MSR UINT64_C(0x0000008000000000)
119#define HM_CHANGED_GUEST_SYSENTER_ESP_MSR UINT64_C(0x0000010000000000)
120#define HM_CHANGED_GUEST_SYSENTER_MSR_MASK UINT64_C(0x000001c000000000)
121#define HM_CHANGED_GUEST_TSC_AUX UINT64_C(0x0000020000000000)
122#define HM_CHANGED_GUEST_OTHER_MSRS UINT64_C(0x0000040000000000)
123#define HM_CHANGED_GUEST_ALL_MSRS ( HM_CHANGED_GUEST_EFER \
124 | HM_CHANGED_GUEST_KERNEL_GS_BASE \
125 | HM_CHANGED_GUEST_SYSCALL_MSRS \
126 | HM_CHANGED_GUEST_SYSENTER_MSR_MASK \
127 | HM_CHANGED_GUEST_TSC_AUX \
128 | HM_CHANGED_GUEST_OTHER_MSRS)
129
130#define HM_CHANGED_GUEST_HWVIRT UINT64_C(0x0000080000000000)
131#define HM_CHANGED_GUEST_MASK UINT64_C(0x00000ffffffffffc)
132
133#define HM_CHANGED_KEEPER_STATE_MASK UINT64_C(0xffff000000000000)
134
135#define HM_CHANGED_VMX_XCPT_INTERCEPTS UINT64_C(0x0001000000000000)
136#define HM_CHANGED_VMX_GUEST_AUTO_MSRS UINT64_C(0x0002000000000000)
137#define HM_CHANGED_VMX_GUEST_LAZY_MSRS UINT64_C(0x0004000000000000)
138#define HM_CHANGED_VMX_ENTRY_EXIT_CTLS UINT64_C(0x0008000000000000)
139#define HM_CHANGED_VMX_MASK UINT64_C(0x000f000000000000)
140#define HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE ( HM_CHANGED_GUEST_DR_MASK \
141 | HM_CHANGED_VMX_GUEST_LAZY_MSRS)
142
143#define HM_CHANGED_SVM_XCPT_INTERCEPTS UINT64_C(0x0001000000000000)
144#define HM_CHANGED_SVM_MASK UINT64_C(0x0001000000000000)
145#define HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE HM_CHANGED_GUEST_DR_MASK
146
147#define HM_CHANGED_ALL_GUEST ( HM_CHANGED_GUEST_MASK \
148 | HM_CHANGED_KEEPER_STATE_MASK)
149
150/** Mask of what state might have changed when IEM raised an exception.
151 * This is a based on IEM_CPUMCTX_EXTRN_XCPT_MASK. */
152#define HM_CHANGED_RAISED_XCPT_MASK ( HM_CHANGED_GUEST_GPRS_MASK \
153 | HM_CHANGED_GUEST_RIP \
154 | HM_CHANGED_GUEST_RFLAGS \
155 | HM_CHANGED_GUEST_SS \
156 | HM_CHANGED_GUEST_CS \
157 | HM_CHANGED_GUEST_CR0 \
158 | HM_CHANGED_GUEST_CR3 \
159 | HM_CHANGED_GUEST_CR4 \
160 | HM_CHANGED_GUEST_APIC_TPR \
161 | HM_CHANGED_GUEST_EFER_MSR \
162 | HM_CHANGED_GUEST_DR7 \
163 | HM_CHANGED_GUEST_CR2 \
164 | HM_CHANGED_GUEST_SREG_MASK \
165 | HM_CHANGED_GUEST_TABLE_MASK)
166
167#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
168/** Mask of what state might have changed when \#VMEXIT is emulated. */
169# define HM_CHANGED_SVM_VMEXIT_MASK ( HM_CHANGED_GUEST_RSP \
170 | HM_CHANGED_GUEST_RAX \
171 | HM_CHANGED_GUEST_RIP \
172 | HM_CHANGED_GUEST_RFLAGS \
173 | HM_CHANGED_GUEST_CS \
174 | HM_CHANGED_GUEST_SS \
175 | HM_CHANGED_GUEST_DS \
176 | HM_CHANGED_GUEST_ES \
177 | HM_CHANGED_GUEST_GDTR \
178 | HM_CHANGED_GUEST_IDTR \
179 | HM_CHANGED_GUEST_CR_MASK \
180 | HM_CHANGED_GUEST_EFER_MSR \
181 | HM_CHANGED_GUEST_DR6 \
182 | HM_CHANGED_GUEST_DR7 \
183 | HM_CHANGED_GUEST_OTHER_MSRS \
184 | HM_CHANGED_GUEST_HWVIRT \
185 | HM_CHANGED_SVM_MASK \
186 | HM_CHANGED_GUEST_APIC_TPR)
187
188/** Mask of what state might have changed when VMRUN is emulated. */
189# define HM_CHANGED_SVM_VMRUN_MASK HM_CHANGED_SVM_VMEXIT_MASK
190#endif
191#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
192/** Mask of what state might have changed when VM-exit is emulated.
193 *
194 * This is currently unused, but keeping it here in case we can get away a bit more
195 * fine-grained state handling.
196 *
197 * @note Update IEM_CPUMCTX_EXTRN_VMX_VMEXIT_MASK when this changes. */
198# define HM_CHANGED_VMX_VMEXIT_MASK ( HM_CHANGED_GUEST_CR0 | HM_CHANGED_GUEST_CR3 | HM_CHANGED_GUEST_CR4 \
199 | HM_CHANGED_GUEST_DR7 | HM_CHANGED_GUEST_DR6 \
200 | HM_CHANGED_GUEST_EFER_MSR \
201 | HM_CHANGED_GUEST_SYSENTER_MSR_MASK \
202 | HM_CHANGED_GUEST_OTHER_MSRS /* for PAT MSR */ \
203 | HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RSP | HM_CHANGED_GUEST_RFLAGS \
204 | HM_CHANGED_GUEST_SREG_MASK \
205 | HM_CHANGED_GUEST_TR \
206 | HM_CHANGED_GUEST_LDTR | HM_CHANGED_GUEST_GDTR | HM_CHANGED_GUEST_IDTR \
207 | HM_CHANGED_GUEST_HWVIRT )
208#endif
209/** @} */
210
211/** Maximum number of exit reason statistics counters. */
212#define MAX_EXITREASON_STAT 0x100
213#define MASK_EXITREASON_STAT 0xff
214#define MASK_INJECT_IRQ_STAT 0xff
215
216/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
217#define HM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
218/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
219#define HM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2 * PAGE_SIZE + 1)
220/** Total guest mapped memory needed. */
221#define HM_VTX_TOTAL_DEVHEAP_MEM (HM_EPT_IDENTITY_PG_TABLE_SIZE + HM_VTX_TSS_SIZE)
222
223
224/** @name Macros for enabling and disabling preemption.
225 * These are really just for hiding the RTTHREADPREEMPTSTATE and asserting that
226 * preemption has already been disabled when there is no context hook.
227 * @{ */
228#ifdef VBOX_STRICT
229# define HM_DISABLE_PREEMPT(a_pVCpu) \
230 RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
231 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD) || VMMR0ThreadCtxHookIsEnabled((a_pVCpu))); \
232 RTThreadPreemptDisable(&PreemptStateInternal)
233#else
234# define HM_DISABLE_PREEMPT(a_pVCpu) \
235 RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
236 RTThreadPreemptDisable(&PreemptStateInternal)
237#endif /* VBOX_STRICT */
238#define HM_RESTORE_PREEMPT() do { RTThreadPreemptRestore(&PreemptStateInternal); } while(0)
239/** @} */
240
241
242/** @name HM saved state versions.
243 * @{
244 */
245#define HM_SAVED_STATE_VERSION HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT
246#define HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT 6
247#define HM_SAVED_STATE_VERSION_TPR_PATCHING 5
248#define HM_SAVED_STATE_VERSION_NO_TPR_PATCHING 4
249#define HM_SAVED_STATE_VERSION_2_0_X 3
250/** @} */
251
252
253/**
254 * HM physical (host) CPU information.
255 */
256typedef struct HMPHYSCPU
257{
258 /** The CPU ID. */
259 RTCPUID idCpu;
260 /** The VM_HSAVE_AREA (AMD-V) / VMXON region (Intel) memory backing. */
261 RTR0MEMOBJ hMemObj;
262 /** The physical address of the first page in hMemObj (it's a
263 * physcially contigous allocation if it spans multiple pages). */
264 RTHCPHYS HCPhysMemObj;
265 /** The address of the memory (for pfnEnable). */
266 void *pvMemObj;
267 /** Current ASID (AMD-V) / VPID (Intel). */
268 uint32_t uCurrentAsid;
269 /** TLB flush count. */
270 uint32_t cTlbFlushes;
271 /** Whether to flush each new ASID/VPID before use. */
272 bool fFlushAsidBeforeUse;
273 /** Configured for VT-x or AMD-V. */
274 bool fConfigured;
275 /** Set if the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active. */
276 bool fIgnoreAMDVInUseError;
277 /** Whether CR4.VMXE was already enabled prior to us enabling it. */
278 bool fVmxeAlreadyEnabled;
279 /** In use by our code. (for power suspend) */
280 bool volatile fInUse;
281#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
282 /** Nested-guest union (put data common to SVM/VMX outside the union). */
283 union
284 {
285 /** Nested-guest SVM data. */
286 struct
287 {
288 /** The active nested-guest MSR permission bitmap memory backing. */
289 RTR0MEMOBJ hNstGstMsrpm;
290 /** The physical address of the first page in hNstGstMsrpm (physcially
291 * contiguous allocation). */
292 RTHCPHYS HCPhysNstGstMsrpm;
293 /** The address of the active nested-guest MSRPM. */
294 void *pvNstGstMsrpm;
295 } svm;
296 /** @todo Nested-VMX. */
297 } n;
298#endif
299} HMPHYSCPU;
300/** Pointer to HMPHYSCPU struct. */
301typedef HMPHYSCPU *PHMPHYSCPU;
302/** Pointer to a const HMPHYSCPU struct. */
303typedef const HMPHYSCPU *PCHMPHYSCPU;
304
305/**
306 * TPR-instruction type.
307 */
308typedef enum
309{
310 HMTPRINSTR_INVALID,
311 HMTPRINSTR_READ,
312 HMTPRINSTR_READ_SHR4,
313 HMTPRINSTR_WRITE_REG,
314 HMTPRINSTR_WRITE_IMM,
315 HMTPRINSTR_JUMP_REPLACEMENT,
316 /** The usual 32-bit paranoia. */
317 HMTPRINSTR_32BIT_HACK = 0x7fffffff
318} HMTPRINSTR;
319
320/**
321 * TPR patch information.
322 */
323typedef struct
324{
325 /** The key is the address of patched instruction. (32 bits GC ptr) */
326 AVLOU32NODECORE Core;
327 /** Original opcode. */
328 uint8_t aOpcode[16];
329 /** Instruction size. */
330 uint32_t cbOp;
331 /** Replacement opcode. */
332 uint8_t aNewOpcode[16];
333 /** Replacement instruction size. */
334 uint32_t cbNewOp;
335 /** Instruction type. */
336 HMTPRINSTR enmType;
337 /** Source operand. */
338 uint32_t uSrcOperand;
339 /** Destination operand. */
340 uint32_t uDstOperand;
341 /** Number of times the instruction caused a fault. */
342 uint32_t cFaults;
343 /** Patch address of the jump replacement. */
344 RTGCPTR32 pJumpTarget;
345} HMTPRPATCH;
346/** Pointer to HMTPRPATCH. */
347typedef HMTPRPATCH *PHMTPRPATCH;
348/** Pointer to a const HMTPRPATCH. */
349typedef const HMTPRPATCH *PCHMTPRPATCH;
350
351
352/**
353 * Makes a HMEXITSTAT::uKey value from a program counter and an exit code.
354 *
355 * @returns 64-bit key
356 * @param a_uPC The RIP + CS.BASE value of the exit.
357 * @param a_uExit The exit code.
358 * @todo Add CPL?
359 */
360#define HMEXITSTAT_MAKE_KEY(a_uPC, a_uExit) (((a_uPC) & UINT64_C(0x0000ffffffffffff)) | (uint64_t)(a_uExit) << 48)
361
362typedef struct HMEXITINFO
363{
364 /** See HMEXITSTAT_MAKE_KEY(). */
365 uint64_t uKey;
366 /** Number of recent hits (depreciates with time). */
367 uint32_t volatile cHits;
368 /** The age + lock. */
369 uint16_t volatile uAge;
370 /** Action or action table index. */
371 uint16_t iAction;
372} HMEXITINFO;
373AssertCompileSize(HMEXITINFO, 16); /* Lots of these guys, so don't add any unnecessary stuff! */
374
375typedef struct HMEXITHISTORY
376{
377 /** The exit timestamp. */
378 uint64_t uTscExit;
379 /** The index of the corresponding HMEXITINFO entry.
380 * UINT32_MAX if none (too many collisions, race, whatever). */
381 uint32_t iExitInfo;
382 /** Figure out later, needed for padding now. */
383 uint32_t uSomeClueOrSomething;
384} HMEXITHISTORY;
385
386/**
387 * Switcher function, HC to the special 64-bit RC.
388 *
389 * @param pVM The cross context VM structure.
390 * @param offCpumVCpu Offset from pVM->cpum to pVM->aCpus[idCpu].cpum.
391 * @returns Return code indicating the action to take.
392 */
393typedef DECLCALLBACKTYPE(int, FNHMSWITCHERHC,(PVM pVM, uint32_t offCpumVCpu));
394/** Pointer to switcher function. */
395typedef FNHMSWITCHERHC *PFNHMSWITCHERHC;
396
397
398/**
399 * HM event.
400 *
401 * VT-x and AMD-V common event injection structure.
402 */
403typedef struct HMEVENT
404{
405 /** Whether the event is pending. */
406 uint32_t fPending;
407 /** The error-code associated with the event. */
408 uint32_t u32ErrCode;
409 /** The length of the instruction in bytes (only relevant for software
410 * interrupts or software exceptions). */
411 uint32_t cbInstr;
412 /** Alignment. */
413 uint32_t u32Padding;
414 /** The encoded event (VM-entry interruption-information for VT-x or EVENTINJ
415 * for SVM). */
416 uint64_t u64IntInfo;
417 /** Guest virtual address if this is a page-fault event. */
418 RTGCUINTPTR GCPtrFaultAddress;
419} HMEVENT;
420/** Pointer to a HMEVENT struct. */
421typedef HMEVENT *PHMEVENT;
422/** Pointer to a const HMEVENT struct. */
423typedef const HMEVENT *PCHMEVENT;
424AssertCompileSizeAlignment(HMEVENT, 8);
425
426/**
427 * HM VM Instance data.
428 * Changes to this must checked against the padding of the hm union in VM!
429 */
430typedef struct HM
431{
432 /** Set if nested paging is enabled. */
433 bool fNestedPaging;
434 /** Set when we've initialized VMX or SVM. */
435 bool fInitialized;
436 /** Set if large pages are enabled (requires nested paging). */
437 bool fLargePages;
438 /** Set if we can support 64-bit guests or not. */
439 bool fAllow64BitGuests;
440 /** Set when TPR patching is allowed. */
441 bool fTprPatchingAllowed;
442 /** Set when we initialize VT-x or AMD-V once for all CPUs. */
443 bool fGlobalInit;
444 /** Set when TPR patching is active. */
445 bool fTPRPatchingActive;
446 /** Set when the debug facility has breakpoints/events enabled that requires
447 * us to use the debug execution loop in ring-0. */
448 bool fUseDebugLoop;
449 /** Set if hardware APIC virtualization is enabled. */
450 bool fVirtApicRegs;
451 /** Set if posted interrupt processing is enabled. */
452 bool fPostedIntrs;
453 /** Set if indirect branch prediction barrier on VM exit. */
454 bool fIbpbOnVmExit;
455 /** Set if indirect branch prediction barrier on VM entry. */
456 bool fIbpbOnVmEntry;
457 /** Set if level 1 data cache should be flushed on VM entry. */
458 bool fL1dFlushOnVmEntry;
459 /** Set if level 1 data cache should be flushed on EMT scheduling. */
460 bool fL1dFlushOnSched;
461 /** Set if host manages speculation control settings. */
462 bool fSpecCtrlByHost;
463 /** Set if MDS related buffers should be cleared on VM entry. */
464 bool fMdsClearOnVmEntry;
465 /** Set if MDS related buffers should be cleared on EMT scheduling. */
466 bool fMdsClearOnSched;
467 /** Alignment padding. */
468 bool afPaddingMinus1[7];
469
470 /** Maximum ASID allowed. */
471 uint32_t uMaxAsid;
472 /** The maximum number of resumes loops allowed in ring-0 (safety precaution).
473 * This number is set much higher when RTThreadPreemptIsPending is reliable. */
474 uint32_t cMaxResumeLoops;
475
476 /** Host kernel flags that HM might need to know (SUPKERNELFEATURES_XXX). */
477 uint32_t fHostKernelFeatures;
478
479 /** Size of the guest patch memory block. */
480 uint32_t cbGuestPatchMem;
481 /** Guest allocated memory for patching purposes. */
482 RTGCPTR pGuestPatchMem;
483 /** Current free pointer inside the patch block. */
484 RTGCPTR pFreeGuestPatchMem;
485
486 struct
487 {
488 /** Set by the ring-0 side of HM to indicate VMX is supported by the
489 * CPU. */
490 bool fSupported;
491 /** Set when we've enabled VMX. */
492 bool fEnabled;
493 /** Set if VPID is supported. */
494 bool fVpid;
495 /** Set if VT-x VPID is allowed. */
496 bool fAllowVpid;
497 /** Set if unrestricted guest execution is in use (real and protected mode
498 * without paging). */
499 bool fUnrestrictedGuest;
500 /** Set if the preemption timer is in use or not. */
501 bool fUsePreemptTimer;
502 /** The shift mask employed by the VMX-Preemption timer. */
503 uint8_t cPreemptTimerShift;
504 /** Padding. */
505 bool afPadding0;
506
507 /** Virtual address of the APIC-access page. */
508 R0PTRTYPE(uint8_t *) pbApicAccess;
509 /** Pointer to the VMREAD bitmap. */
510 R0PTRTYPE(void *) pvVmreadBitmap;
511 /** Pointer to the VMWRITE bitmap. */
512 R0PTRTYPE(void *) pvVmwriteBitmap;
513
514 /** Pointer to the shadow VMCS read-only fields array. */
515 R0PTRTYPE(uint32_t *) paShadowVmcsRoFields;
516 /** Pointer to the shadow VMCS read/write fields array. */
517 R0PTRTYPE(uint32_t *) paShadowVmcsFields;
518 /** Number of elements in the shadow VMCS read-only fields array. */
519 uint32_t cShadowVmcsRoFields;
520 /** Number of elements in the shadow VMCS read-write fields array. */
521 uint32_t cShadowVmcsFields;
522
523 /** Tagged-TLB flush type. */
524 VMXTLBFLUSHTYPE enmTlbFlushType;
525 /** Flush type to use for INVEPT. */
526 VMXTLBFLUSHEPT enmTlbFlushEpt;
527 /** Flush type to use for INVVPID. */
528 VMXTLBFLUSHVPID enmTlbFlushVpid;
529
530 /** Pause-loop exiting (PLE) gap in ticks. */
531 uint32_t cPleGapTicks;
532 /** Pause-loop exiting (PLE) window in ticks. */
533 uint32_t cPleWindowTicks;
534 uint32_t u32Alignment0;
535
536 /** Host CR4 value (set by ring-0 VMX init) */
537 uint64_t u64HostCr4;
538 /** Host SMM monitor control (set by ring-0 VMX init) */
539 uint64_t u64HostSmmMonitorCtl;
540 /** Host EFER value (set by ring-0 VMX init) */
541 uint64_t u64HostMsrEfer;
542 /** Whether the CPU supports VMCS fields for swapping EFER. */
543 bool fSupportsVmcsEfer;
544 /** Whether to use VMCS shadowing. */
545 bool fUseVmcsShadowing;
546 /** Set if Last Branch Record (LBR) is enabled. */
547 bool fLbr;
548 uint8_t u8Alignment2[5];
549
550 /** The first valid host LBR branch-from-IP stack range. */
551 uint32_t idLbrFromIpMsrFirst;
552 /** The last valid host LBR branch-from-IP stack range. */
553 uint32_t idLbrFromIpMsrLast;
554
555 /** The first valid host LBR branch-to-IP stack range. */
556 uint32_t idLbrToIpMsrFirst;
557 /** The last valid host LBR branch-to-IP stack range. */
558 uint32_t idLbrToIpMsrLast;
559
560 /** The host LBR TOS (top-of-stack) MSR id. */
561 uint32_t idLbrTosMsr;
562 /** Padding. */
563 uint32_t u32Alignment1;
564
565 /** VMX MSR values. */
566 VMXMSRS Msrs;
567
568 /** Host-physical address for a failing VMXON instruction. */
569 RTHCPHYS HCPhysVmxEnableError;
570 /** Host-physical address of the APIC-access page. */
571 RTHCPHYS HCPhysApicAccess;
572 /** Host-physical address of the VMREAD bitmap. */
573 RTHCPHYS HCPhysVmreadBitmap;
574 /** Host-physical address of the VMWRITE bitmap. */
575 RTHCPHYS HCPhysVmwriteBitmap;
576#ifdef VBOX_WITH_CRASHDUMP_MAGIC
577 /** Host-physical address of the crash-dump scratch area. */
578 RTHCPHYS HCPhysScratch;
579#endif
580
581#ifdef VBOX_WITH_CRASHDUMP_MAGIC
582 /** Pointer to the crash-dump scratch bitmap. */
583 R0PTRTYPE(uint8_t *) pbScratch;
584#endif
585 /** Virtual address of the TSS page used for real mode emulation. */
586 R3PTRTYPE(PVBOXTSS) pRealModeTSS;
587 /** Virtual address of the identity page table used for real mode and protected
588 * mode without paging emulation in EPT mode. */
589 R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
590
591 /** Ring-0 memory object for per-VM VMX structures. */
592 RTR0MEMOBJ hMemObj;
593 } vmx;
594
595 struct
596 {
597 /** Set by the ring-0 side of HM to indicate SVM is supported by the
598 * CPU. */
599 bool fSupported;
600 /** Set when we've enabled SVM. */
601 bool fEnabled;
602 /** Set if erratum 170 affects the AMD cpu. */
603 bool fAlwaysFlushTLB;
604 /** Set when the hack to ignore VERR_SVM_IN_USE is active. */
605 bool fIgnoreInUseError;
606 /** Whether to use virtualized VMSAVE/VMLOAD feature. */
607 bool fVirtVmsaveVmload;
608 /** Whether to use virtual GIF feature. */
609 bool fVGif;
610 /** Whether to use LBR virtualization feature. */
611 bool fLbrVirt;
612 uint8_t u8Alignment0[1];
613
614 /** Physical address of the IO bitmap (12kb). */
615 RTHCPHYS HCPhysIOBitmap;
616 /** R0 memory object for the IO bitmap (12kb). */
617 RTR0MEMOBJ hMemObjIOBitmap;
618 /** Virtual address of the IO bitmap. */
619 R0PTRTYPE(void *) pvIOBitmap;
620
621 /* HWCR MSR (for diagnostics) */
622 uint64_t u64MsrHwcr;
623
624 /** SVM revision. */
625 uint32_t u32Rev;
626 /** SVM feature bits from cpuid 0x8000000a */
627 uint32_t u32Features;
628
629 /** Pause filter counter. */
630 uint16_t cPauseFilter;
631 /** Pause filter treshold in ticks. */
632 uint16_t cPauseFilterThresholdTicks;
633 uint32_t u32Alignment0;
634 } svm;
635
636 /**
637 * AVL tree with all patches (active or disabled) sorted by guest instruction
638 * address.
639 */
640 AVLOU32TREE PatchTree;
641 uint32_t cPatches;
642 HMTPRPATCH aPatches[64];
643
644 /** Last recorded error code during HM ring-0 init. */
645 int32_t rcInit;
646
647 /** HMR0Init was run */
648 bool fHMR0Init;
649 bool u8Alignment1[3];
650
651 STAMCOUNTER StatTprPatchSuccess;
652 STAMCOUNTER StatTprPatchFailure;
653 STAMCOUNTER StatTprReplaceSuccessCr8;
654 STAMCOUNTER StatTprReplaceSuccessVmc;
655 STAMCOUNTER StatTprReplaceFailure;
656} HM;
657/** Pointer to HM VM instance data. */
658typedef HM *PHM;
659AssertCompileMemberAlignment(HM, StatTprPatchSuccess, 8);
660AssertCompileMemberAlignment(HM, vmx, 8);
661AssertCompileMemberAlignment(HM, svm, 8);
662
663
664/** @addtogroup grp_hm_int_svm SVM Internal
665 * @{ */
666/** SVM VMRun function, see SVMR0VMRun(). */
667typedef DECLCALLBACKTYPE(int, FNHMSVMVMRUN,(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhysVMCB));
668/** Pointer to a SVM VMRun function. */
669typedef R0PTRTYPE(FNHMSVMVMRUN *) PFNHMSVMVMRUN;
670/** @} */
671
672
673/** @addtogroup grp_hm_int_vmx VMX Internal
674 * @{ */
675/**
676 * VMX VMCS information, shared.
677 *
678 * This structure provides information maintained for and during the executing of a
679 * guest (or nested-guest) VMCS (VM control structure) using hardware-assisted VMX.
680 *
681 * Note! The members here are ordered and aligned based on estimated frequency of
682 * usage and grouped to fit within a cache line in hot code paths. Even subtle
683 * changes here have a noticeable effect in the bootsector benchmarks. Modify with
684 * care.
685 */
686typedef struct VMXVMCSINFOSHARED
687{
688 /** @name Real-mode emulation state.
689 * @{ */
690 /** Set if guest was executing in real mode (extra checks). */
691 bool fWasInRealMode;
692 /** Padding. */
693 bool afPadding0[7];
694 struct
695 {
696 X86DESCATTR AttrCS;
697 X86DESCATTR AttrDS;
698 X86DESCATTR AttrES;
699 X86DESCATTR AttrFS;
700 X86DESCATTR AttrGS;
701 X86DESCATTR AttrSS;
702 X86EFLAGS Eflags;
703 bool fRealOnV86Active;
704 bool afPadding1[3];
705 } RealMode;
706 /** @} */
707
708 /** @name LBR MSR data.
709 * @{ */
710 /** List of LastBranch-From-IP MSRs. */
711 uint64_t au64LbrFromIpMsr[32];
712 /** List of LastBranch-To-IP MSRs. */
713 uint64_t au64LbrToIpMsr[32];
714 /** The MSR containing the index to the most recent branch record. */
715 uint64_t u64LbrTosMsr;
716 /** @} */
717} VMXVMCSINFOSHARED;
718/** Pointer to a VMXVMCSINFOSHARED struct. */
719typedef VMXVMCSINFOSHARED *PVMXVMCSINFOSHARED;
720/** Pointer to a const VMXVMCSINFOSHARED struct. */
721typedef const VMXVMCSINFOSHARED *PCVMXVMCSINFOSHARED;
722AssertCompileSizeAlignment(VMXVMCSINFOSHARED, 8);
723
724
725/**
726 * VMX VMCS information, ring-0 only.
727 *
728 * This structure provides information maintained for and during the executing of a
729 * guest (or nested-guest) VMCS (VM control structure) using hardware-assisted VMX.
730 *
731 * Note! The members here are ordered and aligned based on estimated frequency of
732 * usage and grouped to fit within a cache line in hot code paths. Even subtle
733 * changes here have a noticeable effect in the bootsector benchmarks. Modify with
734 * care.
735 */
736typedef struct VMXVMCSINFO
737{
738 /** Pointer to the bits we share with ring-3. */
739 R0PTRTYPE(PVMXVMCSINFOSHARED) pShared;
740
741 /** @name Auxiliary information.
742 * @{ */
743 /** Host-physical address of the EPTP. */
744 RTHCPHYS HCPhysEPTP;
745 /** The VMCS launch state, see VMX_V_VMCS_LAUNCH_STATE_XXX. */
746 uint32_t fVmcsState;
747 /** The VMCS launch state of the shadow VMCS, see VMX_V_VMCS_LAUNCH_STATE_XXX. */
748 uint32_t fShadowVmcsState;
749 /** The host CPU for which its state has been exported to this VMCS. */
750 RTCPUID idHostCpuState;
751 /** The host CPU on which we last executed this VMCS. */
752 RTCPUID idHostCpuExec;
753 /** Number of guest MSRs in the VM-entry MSR-load area. */
754 uint32_t cEntryMsrLoad;
755 /** Number of guest MSRs in the VM-exit MSR-store area. */
756 uint32_t cExitMsrStore;
757 /** Number of host MSRs in the VM-exit MSR-load area. */
758 uint32_t cExitMsrLoad;
759 /** @} */
760
761 /** @name Cache of execution related VMCS fields.
762 * @{ */
763 /** Pin-based VM-execution controls. */
764 uint32_t u32PinCtls;
765 /** Processor-based VM-execution controls. */
766 uint32_t u32ProcCtls;
767 /** Secondary processor-based VM-execution controls. */
768 uint32_t u32ProcCtls2;
769 /** VM-entry controls. */
770 uint32_t u32EntryCtls;
771 /** VM-exit controls. */
772 uint32_t u32ExitCtls;
773 /** Exception bitmap. */
774 uint32_t u32XcptBitmap;
775 /** Page-fault exception error-code mask. */
776 uint32_t u32XcptPFMask;
777 /** Page-fault exception error-code match. */
778 uint32_t u32XcptPFMatch;
779 /** Padding. */
780 uint32_t u32Alignment0;
781 /** TSC offset. */
782 uint64_t u64TscOffset;
783 /** VMCS link pointer. */
784 uint64_t u64VmcsLinkPtr;
785 /** CR0 guest/host mask. */
786 uint64_t u64Cr0Mask;
787 /** CR4 guest/host mask. */
788 uint64_t u64Cr4Mask;
789 /** Current VMX_VMCS_HOST_RIP value (only used in HMR0A.asm). */
790 uint64_t uHostRip;
791 /** Current VMX_VMCS_HOST_RSP value (only used in HMR0A.asm). */
792 uint64_t uHostRsp;
793 /** @} */
794
795 /** @name Host-virtual address of VMCS and related data structures.
796 * @{ */
797 /** The VMCS. */
798 R0PTRTYPE(void *) pvVmcs;
799 /** The shadow VMCS. */
800 R0PTRTYPE(void *) pvShadowVmcs;
801 /** The virtual-APIC page. */
802 R0PTRTYPE(uint8_t *) pbVirtApic;
803 /** The MSR bitmap. */
804 R0PTRTYPE(void *) pvMsrBitmap;
805 /** The VM-entry MSR-load area. */
806 R0PTRTYPE(void *) pvGuestMsrLoad;
807 /** The VM-exit MSR-store area. */
808 R0PTRTYPE(void *) pvGuestMsrStore;
809 /** The VM-exit MSR-load area. */
810 R0PTRTYPE(void *) pvHostMsrLoad;
811 /** @} */
812
813 /** @name Host-physical address of VMCS and related data structures.
814 * @{ */
815 /** The VMCS. */
816 RTHCPHYS HCPhysVmcs;
817 /** The shadow VMCS. */
818 RTHCPHYS HCPhysShadowVmcs;
819 /** The virtual APIC page. */
820 RTHCPHYS HCPhysVirtApic;
821 /** The MSR bitmap. */
822 RTHCPHYS HCPhysMsrBitmap;
823 /** The VM-entry MSR-load area. */
824 RTHCPHYS HCPhysGuestMsrLoad;
825 /** The VM-exit MSR-store area. */
826 RTHCPHYS HCPhysGuestMsrStore;
827 /** The VM-exit MSR-load area. */
828 RTHCPHYS HCPhysHostMsrLoad;
829 /** @} */
830
831 /** @name R0-memory objects address for VMCS and related data structures.
832 * @{ */
833 /** R0-memory object for VMCS and related data structures. */
834 RTR0MEMOBJ hMemObj;
835 /** @} */
836} VMXVMCSINFO;
837/** Pointer to a VMXVMCSINFOR0 struct. */
838typedef VMXVMCSINFO *PVMXVMCSINFO;
839/** Pointer to a const VMXVMCSINFO struct. */
840typedef const VMXVMCSINFO *PCVMXVMCSINFO;
841AssertCompileSizeAlignment(VMXVMCSINFO, 8);
842AssertCompileMemberAlignment(VMXVMCSINFO, u32PinCtls, 4);
843AssertCompileMemberAlignment(VMXVMCSINFO, u64VmcsLinkPtr, 8);
844AssertCompileMemberAlignment(VMXVMCSINFO, pvVmcs, 8);
845AssertCompileMemberAlignment(VMXVMCSINFO, pvShadowVmcs, 8);
846AssertCompileMemberAlignment(VMXVMCSINFO, pbVirtApic, 8);
847AssertCompileMemberAlignment(VMXVMCSINFO, pvMsrBitmap, 8);
848AssertCompileMemberAlignment(VMXVMCSINFO, pvGuestMsrLoad, 8);
849AssertCompileMemberAlignment(VMXVMCSINFO, pvGuestMsrStore, 8);
850AssertCompileMemberAlignment(VMXVMCSINFO, pvHostMsrLoad, 8);
851AssertCompileMemberAlignment(VMXVMCSINFO, HCPhysVmcs, 8);
852AssertCompileMemberAlignment(VMXVMCSINFO, hMemObj, 8);
853
854
855/** @name Host-state restoration flags.
856 * @note If you change these values don't forget to update the assembly
857 * defines as well!
858 * @{
859 */
860#define VMX_RESTORE_HOST_SEL_DS RT_BIT(0)
861#define VMX_RESTORE_HOST_SEL_ES RT_BIT(1)
862#define VMX_RESTORE_HOST_SEL_FS RT_BIT(2)
863#define VMX_RESTORE_HOST_SEL_GS RT_BIT(3)
864#define VMX_RESTORE_HOST_SEL_TR RT_BIT(4)
865#define VMX_RESTORE_HOST_GDTR RT_BIT(5)
866#define VMX_RESTORE_HOST_IDTR RT_BIT(6)
867#define VMX_RESTORE_HOST_GDT_READ_ONLY RT_BIT(7)
868#define VMX_RESTORE_HOST_GDT_NEED_WRITABLE RT_BIT(8)
869#define VMX_RESTORE_HOST_CAN_USE_WRFSBASE_AND_WRGSBASE RT_BIT(9)
870/**
871 * This _must_ be the top most bit, so that we can easily that that it and
872 * something else is set w/o having to do two checks like this:
873 * @code
874 * if ( (pVCpu->hm.s.vmx.fRestoreHostFlags & VMX_RESTORE_HOST_REQUIRED)
875 * && (pVCpu->hm.s.vmx.fRestoreHostFlags & ~VMX_RESTORE_HOST_REQUIRED))
876 * @endcode
877 * Instead we can then do:
878 * @code
879 * if (pVCpu->hm.s.vmx.fRestoreHostFlags > VMX_RESTORE_HOST_REQUIRED)
880 * @endcode
881 */
882#define VMX_RESTORE_HOST_REQUIRED RT_BIT(10)
883/** @} */
884
885/**
886 * Host-state restoration structure.
887 *
888 * This holds host-state fields that require manual restoration.
889 * Assembly version found in HMInternal.mac (should be automatically verified).
890 */
891typedef struct VMXRESTOREHOST
892{
893 RTSEL uHostSelDS; /**< 0x00 */
894 RTSEL uHostSelES; /**< 0x02 */
895 RTSEL uHostSelFS; /**< 0x04 */
896 X86XDTR64 HostGdtr; /**< 0x06 - should be aligned by its 64-bit member. */
897 RTSEL uHostSelGS; /**< 0x10 */
898 RTSEL uHostSelTR; /**< 0x12 */
899 RTSEL uHostSelSS; /**< 0x14 - not restored, just for fetching */
900 X86XDTR64 HostGdtrRw; /**< 0x16 - should be aligned by its 64-bit member. */
901 RTSEL uHostSelCS; /**< 0x20 - not restored, just for fetching */
902 uint8_t abPadding1[4]; /**< 0x22 */
903 X86XDTR64 HostIdtr; /**< 0x26 - should be aligned by its 64-bit member. */
904 uint64_t uHostFSBase; /**< 0x30 */
905 uint64_t uHostGSBase; /**< 0x38 */
906} VMXRESTOREHOST;
907/** Pointer to VMXRESTOREHOST. */
908typedef VMXRESTOREHOST *PVMXRESTOREHOST;
909AssertCompileSize(X86XDTR64, 10);
910AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtr.uAddr, 0x08);
911AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtrRw.uAddr, 0x18);
912AssertCompileMemberOffset(VMXRESTOREHOST, HostIdtr.uAddr, 0x28);
913AssertCompileMemberOffset(VMXRESTOREHOST, uHostFSBase, 0x30);
914AssertCompileSize(VMXRESTOREHOST, 64);
915AssertCompileSizeAlignment(VMXRESTOREHOST, 8);
916
917/**
918 * VMX StartVM function.
919 *
920 * @returns VBox status code (no informational stuff).
921 * @param pVmcsInfo Pointer to the VMCS info (for cached host RIP and RSP).
922 * @param pVCpu Pointer to the cross context per-CPU structure.
923 * @param fResume Whether to use VMRESUME (true) or VMLAUNCH (false).
924 */
925typedef DECLCALLBACKTYPE(int, FNHMVMXSTARTVM,(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume));
926/** Pointer to a VMX StartVM function. */
927typedef R0PTRTYPE(FNHMVMXSTARTVM *) PFNHMVMXSTARTVM;
928/** @} */
929
930/**
931 * HM VMCPU Instance data.
932 *
933 * Note! If you change members of this struct, make sure to check if the
934 * assembly counterpart in HMInternal.mac needs to be updated as well.
935 *
936 * Note! The members here are ordered and aligned based on estimated frequency of
937 * usage and grouped to fit within a cache line in hot code paths. Even subtle
938 * changes here have a noticeable effect in the bootsector benchmarks. Modify with
939 * care.
940 */
941typedef struct HMCPU
942{
943 /** Set when the TLB has been checked until we return from the world switch. */
944 bool volatile fCheckedTLBFlush;
945 /** Set when we're using VT-x or AMD-V at that moment.
946 * @todo r=bird: Misleading description. For AMD-V this will be set the first
947 * time HMCanExecuteGuest() is called and only cleared again by
948 * HMR3ResetCpu(). For VT-x it will be set by HMCanExecuteGuest when we
949 * can execute something in VT-x mode, and cleared if we cannot.
950 *
951 * The field is much more about recording the last HMCanExecuteGuest
952 * return value than anything about any "moment". */
953 bool fActive;
954
955 /** Whether we should use the debug loop because of single stepping or special
956 * debug breakpoints / events are armed. */
957 bool fUseDebugLoop;
958
959 /** Whether \#UD needs to be intercepted (required by certain GIM providers). */
960 bool fGIMTrapXcptUD;
961 /** Whether \#GP needs to be intercepted for mesa driver workaround. */
962 bool fTrapXcptGpForLovelyMesaDrv;
963 /** Whether we're executing a single instruction. */
964 bool fSingleInstruction;
965
966 bool afAlignment0[2];
967
968 /** An additional error code used for some gurus. */
969 uint32_t u32HMError;
970 /** The last exit-to-ring-3 reason. */
971 int32_t rcLastExitToR3;
972 /** CPU-context changed flags (see HM_CHANGED_xxx). */
973 uint64_t fCtxChanged;
974
975 /** VT-x data. */
976 struct HMCPUVMX
977 {
978 /** @name Guest information.
979 * @{ */
980 /** Guest VMCS information shared with ring-3. */
981 VMXVMCSINFOSHARED VmcsInfo;
982 /** Nested-guest VMCS information shared with ring-3. */
983 VMXVMCSINFOSHARED VmcsInfoNstGst;
984 /** Whether the nested-guest VMCS was the last current VMCS (shadow copy for ring-3).
985 * @see HMR0PERVCPU::vmx.fSwitchedToNstGstVmcs */
986 bool fSwitchedToNstGstVmcsCopyForRing3;
987 /** Whether the static guest VMCS controls has been merged with the
988 * nested-guest VMCS controls. */
989 bool fMergedNstGstCtls;
990 /** Whether the nested-guest VMCS has been copied to the shadow VMCS. */
991 bool fCopiedNstGstToShadowVmcs;
992 /** Whether flushing the TLB is required due to switching to/from the
993 * nested-guest. */
994 bool fSwitchedNstGstFlushTlb;
995 /** Alignment. */
996 bool afAlignment0[4];
997 /** Cached guest APIC-base MSR for identifying when to map the APIC-access page. */
998 uint64_t u64GstMsrApicBase;
999 /** @} */
1000
1001 /** @name Error reporting and diagnostics.
1002 * @{ */
1003 /** VT-x error-reporting (mainly for ring-3 propagation). */
1004 struct
1005 {
1006 RTCPUID idCurrentCpu;
1007 RTCPUID idEnteredCpu;
1008 RTHCPHYS HCPhysCurrentVmcs;
1009 uint32_t u32VmcsRev;
1010 uint32_t u32InstrError;
1011 uint32_t u32ExitReason;
1012 uint32_t u32GuestIntrState;
1013 } LastError;
1014 /** @} */
1015 } vmx;
1016
1017 /** SVM data. */
1018 struct HMCPUSVM
1019 {
1020 /** Whether to emulate long mode support for sysenter/sysexit like intel CPUs
1021 * does. This means intercepting \#UD to emulate the instructions in
1022 * long-mode and to intercept reads and writes to the SYSENTER MSRs in order to
1023 * preserve the upper 32 bits written to them (AMD will ignore and discard). */
1024 bool fEmulateLongModeSysEnterExit;
1025 uint8_t au8Alignment0[7];
1026
1027 /** Cache of the nested-guest's VMCB fields that we modify in order to run the
1028 * nested-guest using AMD-V. This will be restored on \#VMEXIT. */
1029 SVMNESTEDVMCBCACHE NstGstVmcbCache;
1030 } svm;
1031
1032 /** Event injection state. */
1033 HMEVENT Event;
1034
1035 /** Current shadow paging mode for updating CR4.
1036 * @todo move later (@bugref{9217}). */
1037 PGMMODE enmShadowMode;
1038 uint32_t u32TemporaryPadding;
1039
1040 /** The PAE PDPEs used with Nested Paging (only valid when
1041 * VMCPU_FF_HM_UPDATE_PAE_PDPES is set). */
1042 X86PDPE aPdpes[4];
1043
1044 /* These two comes because they are accessed from assembly and we don't
1045 want to detail all the stats in the assembly version of this structure. */
1046 STAMCOUNTER StatVmxWriteHostRip;
1047 STAMCOUNTER StatVmxWriteHostRsp;
1048 STAMCOUNTER StatVmxVmLaunch;
1049 STAMCOUNTER StatVmxVmResume;
1050
1051 STAMPROFILEADV StatEntry;
1052 STAMPROFILEADV StatPreExit;
1053 STAMPROFILEADV StatExitHandling;
1054 STAMPROFILEADV StatExitIO;
1055 STAMPROFILEADV StatExitMovCRx;
1056 STAMPROFILEADV StatExitXcptNmi;
1057 STAMPROFILEADV StatExitVmentry;
1058 STAMPROFILEADV StatImportGuestState;
1059 STAMPROFILEADV StatExportGuestState;
1060 STAMPROFILEADV StatLoadGuestFpuState;
1061 STAMPROFILEADV StatInGC;
1062 STAMPROFILEADV StatPoke;
1063 STAMPROFILEADV StatSpinPoke;
1064 STAMPROFILEADV StatSpinPokeFailed;
1065
1066 STAMCOUNTER StatInjectInterrupt;
1067 STAMCOUNTER StatInjectXcpt;
1068 STAMCOUNTER StatInjectReflect;
1069 STAMCOUNTER StatInjectConvertDF;
1070 STAMCOUNTER StatInjectInterpret;
1071 STAMCOUNTER StatInjectReflectNPF;
1072
1073 STAMCOUNTER StatExitAll;
1074 STAMCOUNTER StatNestedExitAll;
1075 STAMCOUNTER StatExitShadowNM;
1076 STAMCOUNTER StatExitGuestNM;
1077 STAMCOUNTER StatExitShadowPF; /**< Misleading, currently used for MMIO \#PFs as well. */
1078 STAMCOUNTER StatExitShadowPFEM;
1079 STAMCOUNTER StatExitGuestPF;
1080 STAMCOUNTER StatExitGuestUD;
1081 STAMCOUNTER StatExitGuestSS;
1082 STAMCOUNTER StatExitGuestNP;
1083 STAMCOUNTER StatExitGuestTS;
1084 STAMCOUNTER StatExitGuestOF;
1085 STAMCOUNTER StatExitGuestGP;
1086 STAMCOUNTER StatExitGuestDE;
1087 STAMCOUNTER StatExitGuestDF;
1088 STAMCOUNTER StatExitGuestBR;
1089 STAMCOUNTER StatExitGuestAC;
1090 STAMCOUNTER StatExitGuestDB;
1091 STAMCOUNTER StatExitGuestMF;
1092 STAMCOUNTER StatExitGuestBP;
1093 STAMCOUNTER StatExitGuestXF;
1094 STAMCOUNTER StatExitGuestXcpUnk;
1095 STAMCOUNTER StatExitDRxWrite;
1096 STAMCOUNTER StatExitDRxRead;
1097 STAMCOUNTER StatExitCR0Read;
1098 STAMCOUNTER StatExitCR2Read;
1099 STAMCOUNTER StatExitCR3Read;
1100 STAMCOUNTER StatExitCR4Read;
1101 STAMCOUNTER StatExitCR8Read;
1102 STAMCOUNTER StatExitCR0Write;
1103 STAMCOUNTER StatExitCR2Write;
1104 STAMCOUNTER StatExitCR3Write;
1105 STAMCOUNTER StatExitCR4Write;
1106 STAMCOUNTER StatExitCR8Write;
1107 STAMCOUNTER StatExitRdmsr;
1108 STAMCOUNTER StatExitWrmsr;
1109 STAMCOUNTER StatExitClts;
1110 STAMCOUNTER StatExitXdtrAccess;
1111 STAMCOUNTER StatExitLmsw;
1112 STAMCOUNTER StatExitIOWrite;
1113 STAMCOUNTER StatExitIORead;
1114 STAMCOUNTER StatExitIOStringWrite;
1115 STAMCOUNTER StatExitIOStringRead;
1116 STAMCOUNTER StatExitIntWindow;
1117 STAMCOUNTER StatExitExtInt;
1118 STAMCOUNTER StatExitHostNmiInGC;
1119 STAMCOUNTER StatExitHostNmiInGCIpi;
1120 STAMCOUNTER StatExitPreemptTimer;
1121 STAMCOUNTER StatExitTprBelowThreshold;
1122 STAMCOUNTER StatExitTaskSwitch;
1123 STAMCOUNTER StatExitApicAccess;
1124 STAMCOUNTER StatExitReasonNpf;
1125
1126 STAMCOUNTER StatNestedExitReasonNpf;
1127
1128 STAMCOUNTER StatFlushPage;
1129 STAMCOUNTER StatFlushPageManual;
1130 STAMCOUNTER StatFlushPhysPageManual;
1131 STAMCOUNTER StatFlushTlb;
1132 STAMCOUNTER StatFlushTlbNstGst;
1133 STAMCOUNTER StatFlushTlbManual;
1134 STAMCOUNTER StatFlushTlbWorldSwitch;
1135 STAMCOUNTER StatNoFlushTlbWorldSwitch;
1136 STAMCOUNTER StatFlushEntire;
1137 STAMCOUNTER StatFlushAsid;
1138 STAMCOUNTER StatFlushNestedPaging;
1139 STAMCOUNTER StatFlushTlbInvlpgVirt;
1140 STAMCOUNTER StatFlushTlbInvlpgPhys;
1141 STAMCOUNTER StatTlbShootdown;
1142 STAMCOUNTER StatTlbShootdownFlush;
1143
1144 STAMCOUNTER StatSwitchPendingHostIrq;
1145 STAMCOUNTER StatSwitchTprMaskedIrq;
1146 STAMCOUNTER StatSwitchGuestIrq;
1147 STAMCOUNTER StatSwitchHmToR3FF;
1148 STAMCOUNTER StatSwitchVmReq;
1149 STAMCOUNTER StatSwitchPgmPoolFlush;
1150 STAMCOUNTER StatSwitchDma;
1151 STAMCOUNTER StatSwitchExitToR3;
1152 STAMCOUNTER StatSwitchLongJmpToR3;
1153 STAMCOUNTER StatSwitchMaxResumeLoops;
1154 STAMCOUNTER StatSwitchHltToR3;
1155 STAMCOUNTER StatSwitchApicAccessToR3;
1156 STAMCOUNTER StatSwitchPreempt;
1157 STAMCOUNTER StatSwitchNstGstVmexit;
1158
1159 STAMCOUNTER StatTscParavirt;
1160 STAMCOUNTER StatTscOffset;
1161 STAMCOUNTER StatTscIntercept;
1162
1163 STAMCOUNTER StatDRxArmed;
1164 STAMCOUNTER StatDRxContextSwitch;
1165 STAMCOUNTER StatDRxIoCheck;
1166
1167 STAMCOUNTER StatExportMinimal;
1168 STAMCOUNTER StatExportFull;
1169 STAMCOUNTER StatLoadGuestFpu;
1170 STAMCOUNTER StatExportHostState;
1171
1172 STAMCOUNTER StatVmxCheckBadRmSelBase;
1173 STAMCOUNTER StatVmxCheckBadRmSelLimit;
1174 STAMCOUNTER StatVmxCheckBadRmSelAttr;
1175 STAMCOUNTER StatVmxCheckBadV86SelBase;
1176 STAMCOUNTER StatVmxCheckBadV86SelLimit;
1177 STAMCOUNTER StatVmxCheckBadV86SelAttr;
1178 STAMCOUNTER StatVmxCheckRmOk;
1179 STAMCOUNTER StatVmxCheckBadSel;
1180 STAMCOUNTER StatVmxCheckBadRpl;
1181 STAMCOUNTER StatVmxCheckPmOk;
1182
1183#ifdef VBOX_WITH_STATISTICS
1184 R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
1185 R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
1186 R3PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqs;
1187 R0PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqsR0;
1188 R3PTRTYPE(PSTAMCOUNTER) paStatInjectedXcpts;
1189 R0PTRTYPE(PSTAMCOUNTER) paStatInjectedXcptsR0;
1190 R3PTRTYPE(PSTAMCOUNTER) paStatNestedExitReason;
1191 R0PTRTYPE(PSTAMCOUNTER) paStatNestedExitReasonR0;
1192#endif
1193#ifdef HM_PROFILE_EXIT_DISPATCH
1194 STAMPROFILEADV StatExitDispatch;
1195#endif
1196} HMCPU;
1197/** Pointer to HM VMCPU instance data. */
1198typedef HMCPU *PHMCPU;
1199AssertCompileMemberAlignment(HMCPU, fCheckedTLBFlush, 4);
1200AssertCompileMemberAlignment(HMCPU, fCtxChanged, 8);
1201AssertCompileMemberAlignment(HMCPU, vmx, 8);
1202AssertCompileMemberAlignment(HMCPU, vmx.VmcsInfo, 8);
1203AssertCompileMemberAlignment(HMCPU, vmx.VmcsInfoNstGst, 8);
1204AssertCompileMemberAlignment(HMCPU, svm, 8);
1205AssertCompileMemberAlignment(HMCPU, Event, 8);
1206
1207
1208/**
1209 * HM per-VCpu ring-0 only instance data.
1210 */
1211typedef struct HMR0PERVCPU
1212{
1213 /** World switch exit counter. */
1214 uint32_t volatile cWorldSwitchExits;
1215 /** TLB flush count. */
1216 uint32_t cTlbFlushes;
1217 /** The last CPU we were executing code on (NIL_RTCPUID for the first time). */
1218 RTCPUID idLastCpu;
1219 /** The CPU ID of the CPU currently owning the VMCS. Set in
1220 * HMR0Enter and cleared in HMR0Leave. */
1221 RTCPUID idEnteredCpu;
1222 /** Current ASID in use by the VM. */
1223 uint32_t uCurrentAsid;
1224
1225 /** Set if we need to flush the TLB during the world switch. */
1226 bool fForceTLBFlush;
1227 /** Whether we've completed the inner HM leave function. */
1228 bool fLeaveDone;
1229 /** Whether we're using the hyper DR7 or guest DR7. */
1230 bool fUsingHyperDR7;
1231 /** Whether we are currently executing in the debug loop.
1232 * Mainly for assertions. */
1233 bool fUsingDebugLoop;
1234 /** Set if we using the debug loop and wish to intercept RDTSC. */
1235 bool fDebugWantRdTscExit;
1236 /** Set if XCR0 needs to be saved/restored when entering/exiting guest code
1237 * execution. */
1238 bool fLoadSaveGuestXcr0;
1239 /** Set if we need to clear the trap flag because of single stepping. */
1240 bool fClearTrapFlag;
1241
1242 bool afPadding1[5];
1243
1244 /** VT-x data. */
1245 struct HMR0CPUVMX
1246 {
1247 /** Ring-0 pointer to the hardware-assisted VMX execution function. */
1248 PFNHMVMXSTARTVM pfnStartVm;
1249
1250 /** @name Guest information.
1251 * @{ */
1252 /** Guest VMCS information. */
1253 VMXVMCSINFO VmcsInfo;
1254 /** Nested-guest VMCS information. */
1255 VMXVMCSINFO VmcsInfoNstGst;
1256 /* Whether the nested-guest VMCS was the last current VMCS (authoritative copy).
1257 * @see HMCPU::vmx.fSwitchedToNstGstVmcsCopyForRing3 */
1258 bool fSwitchedToNstGstVmcs;
1259 bool afAlignment0[7];
1260 /** @} */
1261
1262 /** @name Host information.
1263 * @{ */
1264 /** Host LSTAR MSR to restore lazily while leaving VT-x. */
1265 uint64_t u64HostMsrLStar;
1266 /** Host STAR MSR to restore lazily while leaving VT-x. */
1267 uint64_t u64HostMsrStar;
1268 /** Host SF_MASK MSR to restore lazily while leaving VT-x. */
1269 uint64_t u64HostMsrSfMask;
1270 /** Host KernelGS-Base MSR to restore lazily while leaving VT-x. */
1271 uint64_t u64HostMsrKernelGsBase;
1272 /** The mask of lazy MSRs swap/restore state, see VMX_LAZY_MSRS_XXX. */
1273 uint32_t fLazyMsrs;
1274 /** Whether the host MSR values are up-to-date in the auto-load/store MSR area. */
1275 bool fUpdatedHostAutoMsrs;
1276 /** Alignment. */
1277 uint8_t au8Alignment0[3];
1278 /** Which host-state bits to restore before being preempted, see
1279 * VMX_RESTORE_HOST_XXX. */
1280 uint32_t fRestoreHostFlags;
1281 /** Alignment. */
1282 uint32_t u32Alignment0;
1283 /** The host-state restoration structure. */
1284 VMXRESTOREHOST RestoreHost;
1285 /** @} */
1286 } vmx;
1287
1288 /** SVM data. */
1289 struct HMR0CPUSVM
1290 {
1291 /** Ring 0 handlers for VT-x. */
1292 PFNHMSVMVMRUN pfnVMRun;
1293
1294 /** Physical address of the host VMCB which holds additional host-state. */
1295 RTHCPHYS HCPhysVmcbHost;
1296 /** R0 memory object for the host VMCB which holds additional host-state. */
1297 RTR0MEMOBJ hMemObjVmcbHost;
1298
1299 /** Physical address of the guest VMCB. */
1300 RTHCPHYS HCPhysVmcb;
1301 /** R0 memory object for the guest VMCB. */
1302 RTR0MEMOBJ hMemObjVmcb;
1303 /** Pointer to the guest VMCB. */
1304 R0PTRTYPE(PSVMVMCB) pVmcb;
1305
1306 /** Physical address of the MSR bitmap (8 KB). */
1307 RTHCPHYS HCPhysMsrBitmap;
1308 /** R0 memory object for the MSR bitmap (8 KB). */
1309 RTR0MEMOBJ hMemObjMsrBitmap;
1310 /** Pointer to the MSR bitmap. */
1311 R0PTRTYPE(void *) pvMsrBitmap;
1312
1313 /** Whether VTPR with V_INTR_MASKING set is in effect, indicating
1314 * we should check if the VTPR changed on every VM-exit. */
1315 bool fSyncVTpr;
1316 bool afAlignment[7];
1317
1318 /** Host's TSC_AUX MSR (used when RDTSCP doesn't cause VM-exits). */
1319 uint64_t u64HostTscAux;
1320
1321 /** For saving stack space, the disassembler state is allocated here
1322 * instead of on the stack. */
1323 DISCPUSTATE DisState;
1324 } svm;
1325} HMR0PERVCPU;
1326/** Pointer to HM ring-0 VMCPU instance data. */
1327typedef HMR0PERVCPU *PHMR0PERVCPU;
1328AssertCompileMemberAlignment(HMR0PERVCPU, cWorldSwitchExits, 4);
1329AssertCompileMemberAlignment(HMR0PERVCPU, fForceTLBFlush, 4);
1330AssertCompileMemberAlignment(HMR0PERVCPU, vmx.RestoreHost, 8);
1331
1332
1333#ifdef IN_RING0
1334VMMR0_INT_DECL(PHMPHYSCPU) hmR0GetCurrentCpu(void);
1335VMMR0_INT_DECL(int) hmR0EnterCpu(PVMCPUCC pVCpu);
1336
1337# ifdef VBOX_STRICT
1338# define HM_DUMP_REG_FLAGS_GPRS RT_BIT(0)
1339# define HM_DUMP_REG_FLAGS_FPU RT_BIT(1)
1340# define HM_DUMP_REG_FLAGS_MSRS RT_BIT(2)
1341# define HM_DUMP_REG_FLAGS_ALL (HM_DUMP_REG_FLAGS_GPRS | HM_DUMP_REG_FLAGS_FPU | HM_DUMP_REG_FLAGS_MSRS)
1342
1343VMMR0_INT_DECL(void) hmR0DumpRegs(PVMCPUCC pVCpu, uint32_t fFlags);
1344VMMR0_INT_DECL(void) hmR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg);
1345# endif
1346
1347DECLASM(void) hmR0MdsClear(void);
1348#endif /* IN_RING0 */
1349
1350
1351/** @addtogroup grp_hm_int_svm SVM Internal
1352 * @{ */
1353VMM_INT_DECL(int) hmEmulateSvmMovTpr(PVMCC pVM, PVMCPUCC pVCpu);
1354
1355/**
1356 * Prepares for and executes VMRUN (64-bit register context).
1357 *
1358 * @returns VBox status code (no informational stuff).
1359 * @param pVM The cross context VM structure. (Not used.)
1360 * @param pVCpu The cross context virtual CPU structure.
1361 * @param HCPhyspVMCB Physical address of the VMCB.
1362 *
1363 * @remarks With spectre mitigations and the usual need for speed (/ micro
1364 * optimizations), we have a bunch of variations of this code depending
1365 * on a few precoditions. In release builds, the code is entirely
1366 * without conditionals. Debug builds have a couple of assertions that
1367 * shouldn't ever be triggered.
1368 *
1369 * @{
1370 */
1371DECLASM(int) hmR0SvmVmRun_SansXcr0_SansIbpbEntry_SansIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1372DECLASM(int) hmR0SvmVmRun_WithXcr0_SansIbpbEntry_SansIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1373DECLASM(int) hmR0SvmVmRun_SansXcr0_WithIbpbEntry_SansIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1374DECLASM(int) hmR0SvmVmRun_WithXcr0_WithIbpbEntry_SansIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1375DECLASM(int) hmR0SvmVmRun_SansXcr0_SansIbpbEntry_WithIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1376DECLASM(int) hmR0SvmVmRun_WithXcr0_SansIbpbEntry_WithIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1377DECLASM(int) hmR0SvmVmRun_SansXcr0_WithIbpbEntry_WithIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1378DECLASM(int) hmR0SvmVmRun_WithXcr0_WithIbpbEntry_WithIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1379/** @} */
1380
1381/** @} */
1382
1383
1384/** @addtogroup grp_hm_int_vmx VMX Internal
1385 * @{ */
1386VMM_INT_DECL(PVMXVMCSINFOSHARED) hmGetVmxActiveVmcsInfoShared(PVMCPUCC pVCpu);
1387
1388/**
1389 * Used on platforms with poor inline assembly support to retrieve all the
1390 * info from the CPU and put it in the @a pRestoreHost structure.
1391 */
1392DECLASM(void) hmR0VmxExportHostSegmentRegsAsmHlp(PVMXRESTOREHOST pRestoreHost, bool fHaveFsGsBase);
1393
1394/**
1395 * Restores some host-state fields that need not be done on every VM-exit.
1396 *
1397 * @returns VBox status code.
1398 * @param fRestoreHostFlags Flags of which host registers needs to be
1399 * restored.
1400 * @param pRestoreHost Pointer to the host-restore structure.
1401 */
1402DECLASM(int) VMXRestoreHostState(uint32_t fRestoreHostFlags, PVMXRESTOREHOST pRestoreHost);
1403
1404/**
1405 * VMX StartVM functions.
1406 *
1407 * @returns VBox status code (no informational stuff).
1408 * @param pVM Pointer to the cross context VM structure.
1409 * @param pVCpu Pointer to the cross context per-CPU structure.
1410 * @param fResume Whether to use VMRESUME (true) or VMLAUNCH (false).
1411 *
1412 * @remarks With spectre mitigations and the usual need for speed (/ micro
1413 * optimizations), we have a bunch of variations of this code depending
1414 * on a few precoditions. In release builds, the code is entirely
1415 * without conditionals. Debug builds have a couple of assertions that
1416 * shouldn't ever be triggered.
1417 *
1418 * @{
1419 */
1420DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_SansL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1421DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_SansL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1422DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_SansL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1423DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_SansL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1424DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_WithL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1425DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_WithL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1426DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_WithL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1427DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_WithL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1428DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_SansL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1429DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_SansL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1430DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_SansL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1431DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_SansL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1432DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_WithL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1433DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_WithL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1434DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_WithL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1435DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_WithL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1436DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_SansL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1437DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_SansL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1438DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_SansL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1439DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_SansL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1440DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_WithL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1441DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_WithL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1442DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_WithL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1443DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_WithL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1444DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_SansL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1445DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_SansL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1446DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_SansL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1447DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_SansL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1448DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_WithL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1449DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_WithL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1450DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_WithL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1451DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_WithL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1452/** @} */
1453
1454/** @} */
1455
1456/** @} */
1457
1458RT_C_DECLS_END
1459
1460#endif /* !VMM_INCLUDED_SRC_include_HMInternal_h */
1461
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