VirtualBox

source: vbox/trunk/src/VBox/VMM/include/HMInternal.h@ 87518

Last change on this file since 87518 was 87518, checked in by vboxsync, 4 years ago

VMM/HM: Make a R0 copy of HM::fAllow64BitGuests on setup (for VT-x). bugref:9217
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id Revision
File size: 68.3 KB
Line 
1/* $Id: HMInternal.h 87518 2021-02-01 21:01:16Z vboxsync $ */
2/** @file
3 * HM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef VMM_INCLUDED_SRC_include_HMInternal_h
19#define VMM_INCLUDED_SRC_include_HMInternal_h
20#ifndef RT_WITHOUT_PRAGMA_ONCE
21# pragma once
22#endif
23
24#include <VBox/cdefs.h>
25#include <VBox/types.h>
26#include <VBox/vmm/stam.h>
27#include <VBox/dis.h>
28#include <VBox/vmm/hm.h>
29#include <VBox/vmm/hm_vmx.h>
30#include <VBox/vmm/hm_svm.h>
31#include <VBox/vmm/pgm.h>
32#include <VBox/vmm/cpum.h>
33#include <VBox/vmm/trpm.h>
34#include <iprt/memobj.h>
35#include <iprt/cpuset.h>
36#include <iprt/mp.h>
37#include <iprt/avl.h>
38#include <iprt/string.h>
39
40#if HC_ARCH_BITS == 32
41# error "32-bit hosts are no longer supported. Go back to 6.0 or earlier!"
42#endif
43
44/** @def HM_PROFILE_EXIT_DISPATCH
45 * Enables profiling of the VM exit handler dispatching. */
46#if 0 || defined(DOXYGEN_RUNNING)
47# define HM_PROFILE_EXIT_DISPATCH
48#endif
49
50RT_C_DECLS_BEGIN
51
52
53/** @defgroup grp_hm_int Internal
54 * @ingroup grp_hm
55 * @internal
56 * @{
57 */
58
59/** @name HM_CHANGED_XXX
60 * HM CPU-context changed flags.
61 *
62 * These flags are used to keep track of which registers and state has been
63 * modified since they were imported back into the guest-CPU context.
64 *
65 * @{
66 */
67#define HM_CHANGED_HOST_CONTEXT UINT64_C(0x0000000000000001)
68#define HM_CHANGED_GUEST_RIP UINT64_C(0x0000000000000004)
69#define HM_CHANGED_GUEST_RFLAGS UINT64_C(0x0000000000000008)
70
71#define HM_CHANGED_GUEST_RAX UINT64_C(0x0000000000000010)
72#define HM_CHANGED_GUEST_RCX UINT64_C(0x0000000000000020)
73#define HM_CHANGED_GUEST_RDX UINT64_C(0x0000000000000040)
74#define HM_CHANGED_GUEST_RBX UINT64_C(0x0000000000000080)
75#define HM_CHANGED_GUEST_RSP UINT64_C(0x0000000000000100)
76#define HM_CHANGED_GUEST_RBP UINT64_C(0x0000000000000200)
77#define HM_CHANGED_GUEST_RSI UINT64_C(0x0000000000000400)
78#define HM_CHANGED_GUEST_RDI UINT64_C(0x0000000000000800)
79#define HM_CHANGED_GUEST_R8_R15 UINT64_C(0x0000000000001000)
80#define HM_CHANGED_GUEST_GPRS_MASK UINT64_C(0x0000000000001ff0)
81
82#define HM_CHANGED_GUEST_ES UINT64_C(0x0000000000002000)
83#define HM_CHANGED_GUEST_CS UINT64_C(0x0000000000004000)
84#define HM_CHANGED_GUEST_SS UINT64_C(0x0000000000008000)
85#define HM_CHANGED_GUEST_DS UINT64_C(0x0000000000010000)
86#define HM_CHANGED_GUEST_FS UINT64_C(0x0000000000020000)
87#define HM_CHANGED_GUEST_GS UINT64_C(0x0000000000040000)
88#define HM_CHANGED_GUEST_SREG_MASK UINT64_C(0x000000000007e000)
89
90#define HM_CHANGED_GUEST_GDTR UINT64_C(0x0000000000080000)
91#define HM_CHANGED_GUEST_IDTR UINT64_C(0x0000000000100000)
92#define HM_CHANGED_GUEST_LDTR UINT64_C(0x0000000000200000)
93#define HM_CHANGED_GUEST_TR UINT64_C(0x0000000000400000)
94#define HM_CHANGED_GUEST_TABLE_MASK UINT64_C(0x0000000000780000)
95
96#define HM_CHANGED_GUEST_CR0 UINT64_C(0x0000000000800000)
97#define HM_CHANGED_GUEST_CR2 UINT64_C(0x0000000001000000)
98#define HM_CHANGED_GUEST_CR3 UINT64_C(0x0000000002000000)
99#define HM_CHANGED_GUEST_CR4 UINT64_C(0x0000000004000000)
100#define HM_CHANGED_GUEST_CR_MASK UINT64_C(0x0000000007800000)
101
102#define HM_CHANGED_GUEST_APIC_TPR UINT64_C(0x0000000008000000)
103#define HM_CHANGED_GUEST_EFER_MSR UINT64_C(0x0000000010000000)
104
105#define HM_CHANGED_GUEST_DR0_DR3 UINT64_C(0x0000000020000000)
106#define HM_CHANGED_GUEST_DR6 UINT64_C(0x0000000040000000)
107#define HM_CHANGED_GUEST_DR7 UINT64_C(0x0000000080000000)
108#define HM_CHANGED_GUEST_DR_MASK UINT64_C(0x00000000e0000000)
109
110#define HM_CHANGED_GUEST_X87 UINT64_C(0x0000000100000000)
111#define HM_CHANGED_GUEST_SSE_AVX UINT64_C(0x0000000200000000)
112#define HM_CHANGED_GUEST_OTHER_XSAVE UINT64_C(0x0000000400000000)
113#define HM_CHANGED_GUEST_XCRx UINT64_C(0x0000000800000000)
114
115#define HM_CHANGED_GUEST_KERNEL_GS_BASE UINT64_C(0x0000001000000000)
116#define HM_CHANGED_GUEST_SYSCALL_MSRS UINT64_C(0x0000002000000000)
117#define HM_CHANGED_GUEST_SYSENTER_CS_MSR UINT64_C(0x0000004000000000)
118#define HM_CHANGED_GUEST_SYSENTER_EIP_MSR UINT64_C(0x0000008000000000)
119#define HM_CHANGED_GUEST_SYSENTER_ESP_MSR UINT64_C(0x0000010000000000)
120#define HM_CHANGED_GUEST_SYSENTER_MSR_MASK UINT64_C(0x000001c000000000)
121#define HM_CHANGED_GUEST_TSC_AUX UINT64_C(0x0000020000000000)
122#define HM_CHANGED_GUEST_OTHER_MSRS UINT64_C(0x0000040000000000)
123#define HM_CHANGED_GUEST_ALL_MSRS ( HM_CHANGED_GUEST_EFER \
124 | HM_CHANGED_GUEST_KERNEL_GS_BASE \
125 | HM_CHANGED_GUEST_SYSCALL_MSRS \
126 | HM_CHANGED_GUEST_SYSENTER_MSR_MASK \
127 | HM_CHANGED_GUEST_TSC_AUX \
128 | HM_CHANGED_GUEST_OTHER_MSRS)
129
130#define HM_CHANGED_GUEST_HWVIRT UINT64_C(0x0000080000000000)
131#define HM_CHANGED_GUEST_MASK UINT64_C(0x00000ffffffffffc)
132
133#define HM_CHANGED_KEEPER_STATE_MASK UINT64_C(0xffff000000000000)
134
135#define HM_CHANGED_VMX_XCPT_INTERCEPTS UINT64_C(0x0001000000000000)
136#define HM_CHANGED_VMX_GUEST_AUTO_MSRS UINT64_C(0x0002000000000000)
137#define HM_CHANGED_VMX_GUEST_LAZY_MSRS UINT64_C(0x0004000000000000)
138#define HM_CHANGED_VMX_ENTRY_EXIT_CTLS UINT64_C(0x0008000000000000)
139#define HM_CHANGED_VMX_MASK UINT64_C(0x000f000000000000)
140#define HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE ( HM_CHANGED_GUEST_DR_MASK \
141 | HM_CHANGED_VMX_GUEST_LAZY_MSRS)
142
143#define HM_CHANGED_SVM_XCPT_INTERCEPTS UINT64_C(0x0001000000000000)
144#define HM_CHANGED_SVM_MASK UINT64_C(0x0001000000000000)
145#define HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE HM_CHANGED_GUEST_DR_MASK
146
147#define HM_CHANGED_ALL_GUEST ( HM_CHANGED_GUEST_MASK \
148 | HM_CHANGED_KEEPER_STATE_MASK)
149
150/** Mask of what state might have changed when IEM raised an exception.
151 * This is a based on IEM_CPUMCTX_EXTRN_XCPT_MASK. */
152#define HM_CHANGED_RAISED_XCPT_MASK ( HM_CHANGED_GUEST_GPRS_MASK \
153 | HM_CHANGED_GUEST_RIP \
154 | HM_CHANGED_GUEST_RFLAGS \
155 | HM_CHANGED_GUEST_SS \
156 | HM_CHANGED_GUEST_CS \
157 | HM_CHANGED_GUEST_CR0 \
158 | HM_CHANGED_GUEST_CR3 \
159 | HM_CHANGED_GUEST_CR4 \
160 | HM_CHANGED_GUEST_APIC_TPR \
161 | HM_CHANGED_GUEST_EFER_MSR \
162 | HM_CHANGED_GUEST_DR7 \
163 | HM_CHANGED_GUEST_CR2 \
164 | HM_CHANGED_GUEST_SREG_MASK \
165 | HM_CHANGED_GUEST_TABLE_MASK)
166
167#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
168/** Mask of what state might have changed when \#VMEXIT is emulated. */
169# define HM_CHANGED_SVM_VMEXIT_MASK ( HM_CHANGED_GUEST_RSP \
170 | HM_CHANGED_GUEST_RAX \
171 | HM_CHANGED_GUEST_RIP \
172 | HM_CHANGED_GUEST_RFLAGS \
173 | HM_CHANGED_GUEST_CS \
174 | HM_CHANGED_GUEST_SS \
175 | HM_CHANGED_GUEST_DS \
176 | HM_CHANGED_GUEST_ES \
177 | HM_CHANGED_GUEST_GDTR \
178 | HM_CHANGED_GUEST_IDTR \
179 | HM_CHANGED_GUEST_CR_MASK \
180 | HM_CHANGED_GUEST_EFER_MSR \
181 | HM_CHANGED_GUEST_DR6 \
182 | HM_CHANGED_GUEST_DR7 \
183 | HM_CHANGED_GUEST_OTHER_MSRS \
184 | HM_CHANGED_GUEST_HWVIRT \
185 | HM_CHANGED_SVM_MASK \
186 | HM_CHANGED_GUEST_APIC_TPR)
187
188/** Mask of what state might have changed when VMRUN is emulated. */
189# define HM_CHANGED_SVM_VMRUN_MASK HM_CHANGED_SVM_VMEXIT_MASK
190#endif
191#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
192/** Mask of what state might have changed when VM-exit is emulated.
193 *
194 * This is currently unused, but keeping it here in case we can get away a bit more
195 * fine-grained state handling.
196 *
197 * @note Update IEM_CPUMCTX_EXTRN_VMX_VMEXIT_MASK when this changes. */
198# define HM_CHANGED_VMX_VMEXIT_MASK ( HM_CHANGED_GUEST_CR0 | HM_CHANGED_GUEST_CR3 | HM_CHANGED_GUEST_CR4 \
199 | HM_CHANGED_GUEST_DR7 | HM_CHANGED_GUEST_DR6 \
200 | HM_CHANGED_GUEST_EFER_MSR \
201 | HM_CHANGED_GUEST_SYSENTER_MSR_MASK \
202 | HM_CHANGED_GUEST_OTHER_MSRS /* for PAT MSR */ \
203 | HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RSP | HM_CHANGED_GUEST_RFLAGS \
204 | HM_CHANGED_GUEST_SREG_MASK \
205 | HM_CHANGED_GUEST_TR \
206 | HM_CHANGED_GUEST_LDTR | HM_CHANGED_GUEST_GDTR | HM_CHANGED_GUEST_IDTR \
207 | HM_CHANGED_GUEST_HWVIRT )
208#endif
209/** @} */
210
211/** Maximum number of exit reason statistics counters. */
212#define MAX_EXITREASON_STAT 0x100
213#define MASK_EXITREASON_STAT 0xff
214#define MASK_INJECT_IRQ_STAT 0xff
215
216/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
217#define HM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
218/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
219#define HM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2 * PAGE_SIZE + 1)
220/** Total guest mapped memory needed. */
221#define HM_VTX_TOTAL_DEVHEAP_MEM (HM_EPT_IDENTITY_PG_TABLE_SIZE + HM_VTX_TSS_SIZE)
222
223
224/** @name Macros for enabling and disabling preemption.
225 * These are really just for hiding the RTTHREADPREEMPTSTATE and asserting that
226 * preemption has already been disabled when there is no context hook.
227 * @{ */
228#ifdef VBOX_STRICT
229# define HM_DISABLE_PREEMPT(a_pVCpu) \
230 RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
231 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD) || VMMR0ThreadCtxHookIsEnabled((a_pVCpu))); \
232 RTThreadPreemptDisable(&PreemptStateInternal)
233#else
234# define HM_DISABLE_PREEMPT(a_pVCpu) \
235 RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
236 RTThreadPreemptDisable(&PreemptStateInternal)
237#endif /* VBOX_STRICT */
238#define HM_RESTORE_PREEMPT() do { RTThreadPreemptRestore(&PreemptStateInternal); } while(0)
239/** @} */
240
241
242/** @name HM saved state versions.
243 * @{
244 */
245#define HM_SAVED_STATE_VERSION HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT
246#define HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT 6
247#define HM_SAVED_STATE_VERSION_TPR_PATCHING 5
248#define HM_SAVED_STATE_VERSION_NO_TPR_PATCHING 4
249#define HM_SAVED_STATE_VERSION_2_0_X 3
250/** @} */
251
252
253/**
254 * HM physical (host) CPU information.
255 */
256typedef struct HMPHYSCPU
257{
258 /** The CPU ID. */
259 RTCPUID idCpu;
260 /** The VM_HSAVE_AREA (AMD-V) / VMXON region (Intel) memory backing. */
261 RTR0MEMOBJ hMemObj;
262 /** The physical address of the first page in hMemObj (it's a
263 * physcially contigous allocation if it spans multiple pages). */
264 RTHCPHYS HCPhysMemObj;
265 /** The address of the memory (for pfnEnable). */
266 void *pvMemObj;
267 /** Current ASID (AMD-V) / VPID (Intel). */
268 uint32_t uCurrentAsid;
269 /** TLB flush count. */
270 uint32_t cTlbFlushes;
271 /** Whether to flush each new ASID/VPID before use. */
272 bool fFlushAsidBeforeUse;
273 /** Configured for VT-x or AMD-V. */
274 bool fConfigured;
275 /** Set if the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active. */
276 bool fIgnoreAMDVInUseError;
277 /** Whether CR4.VMXE was already enabled prior to us enabling it. */
278 bool fVmxeAlreadyEnabled;
279 /** In use by our code. (for power suspend) */
280 bool volatile fInUse;
281#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
282 /** Nested-guest union (put data common to SVM/VMX outside the union). */
283 union
284 {
285 /** Nested-guest SVM data. */
286 struct
287 {
288 /** The active nested-guest MSR permission bitmap memory backing. */
289 RTR0MEMOBJ hNstGstMsrpm;
290 /** The physical address of the first page in hNstGstMsrpm (physcially
291 * contiguous allocation). */
292 RTHCPHYS HCPhysNstGstMsrpm;
293 /** The address of the active nested-guest MSRPM. */
294 void *pvNstGstMsrpm;
295 } svm;
296 /** @todo Nested-VMX. */
297 } n;
298#endif
299} HMPHYSCPU;
300/** Pointer to HMPHYSCPU struct. */
301typedef HMPHYSCPU *PHMPHYSCPU;
302/** Pointer to a const HMPHYSCPU struct. */
303typedef const HMPHYSCPU *PCHMPHYSCPU;
304
305/**
306 * TPR-instruction type.
307 */
308typedef enum
309{
310 HMTPRINSTR_INVALID,
311 HMTPRINSTR_READ,
312 HMTPRINSTR_READ_SHR4,
313 HMTPRINSTR_WRITE_REG,
314 HMTPRINSTR_WRITE_IMM,
315 HMTPRINSTR_JUMP_REPLACEMENT,
316 /** The usual 32-bit paranoia. */
317 HMTPRINSTR_32BIT_HACK = 0x7fffffff
318} HMTPRINSTR;
319
320/**
321 * TPR patch information.
322 */
323typedef struct
324{
325 /** The key is the address of patched instruction. (32 bits GC ptr) */
326 AVLOU32NODECORE Core;
327 /** Original opcode. */
328 uint8_t aOpcode[16];
329 /** Instruction size. */
330 uint32_t cbOp;
331 /** Replacement opcode. */
332 uint8_t aNewOpcode[16];
333 /** Replacement instruction size. */
334 uint32_t cbNewOp;
335 /** Instruction type. */
336 HMTPRINSTR enmType;
337 /** Source operand. */
338 uint32_t uSrcOperand;
339 /** Destination operand. */
340 uint32_t uDstOperand;
341 /** Number of times the instruction caused a fault. */
342 uint32_t cFaults;
343 /** Patch address of the jump replacement. */
344 RTGCPTR32 pJumpTarget;
345} HMTPRPATCH;
346/** Pointer to HMTPRPATCH. */
347typedef HMTPRPATCH *PHMTPRPATCH;
348/** Pointer to a const HMTPRPATCH. */
349typedef const HMTPRPATCH *PCHMTPRPATCH;
350
351
352/**
353 * Makes a HMEXITSTAT::uKey value from a program counter and an exit code.
354 *
355 * @returns 64-bit key
356 * @param a_uPC The RIP + CS.BASE value of the exit.
357 * @param a_uExit The exit code.
358 * @todo Add CPL?
359 */
360#define HMEXITSTAT_MAKE_KEY(a_uPC, a_uExit) (((a_uPC) & UINT64_C(0x0000ffffffffffff)) | (uint64_t)(a_uExit) << 48)
361
362typedef struct HMEXITINFO
363{
364 /** See HMEXITSTAT_MAKE_KEY(). */
365 uint64_t uKey;
366 /** Number of recent hits (depreciates with time). */
367 uint32_t volatile cHits;
368 /** The age + lock. */
369 uint16_t volatile uAge;
370 /** Action or action table index. */
371 uint16_t iAction;
372} HMEXITINFO;
373AssertCompileSize(HMEXITINFO, 16); /* Lots of these guys, so don't add any unnecessary stuff! */
374
375typedef struct HMEXITHISTORY
376{
377 /** The exit timestamp. */
378 uint64_t uTscExit;
379 /** The index of the corresponding HMEXITINFO entry.
380 * UINT32_MAX if none (too many collisions, race, whatever). */
381 uint32_t iExitInfo;
382 /** Figure out later, needed for padding now. */
383 uint32_t uSomeClueOrSomething;
384} HMEXITHISTORY;
385
386/**
387 * Switcher function, HC to the special 64-bit RC.
388 *
389 * @param pVM The cross context VM structure.
390 * @param offCpumVCpu Offset from pVM->cpum to pVM->aCpus[idCpu].cpum.
391 * @returns Return code indicating the action to take.
392 */
393typedef DECLCALLBACKTYPE(int, FNHMSWITCHERHC,(PVM pVM, uint32_t offCpumVCpu));
394/** Pointer to switcher function. */
395typedef FNHMSWITCHERHC *PFNHMSWITCHERHC;
396
397
398/**
399 * HM event.
400 *
401 * VT-x and AMD-V common event injection structure.
402 */
403typedef struct HMEVENT
404{
405 /** Whether the event is pending. */
406 uint32_t fPending;
407 /** The error-code associated with the event. */
408 uint32_t u32ErrCode;
409 /** The length of the instruction in bytes (only relevant for software
410 * interrupts or software exceptions). */
411 uint32_t cbInstr;
412 /** Alignment. */
413 uint32_t u32Padding;
414 /** The encoded event (VM-entry interruption-information for VT-x or EVENTINJ
415 * for SVM). */
416 uint64_t u64IntInfo;
417 /** Guest virtual address if this is a page-fault event. */
418 RTGCUINTPTR GCPtrFaultAddress;
419} HMEVENT;
420/** Pointer to a HMEVENT struct. */
421typedef HMEVENT *PHMEVENT;
422/** Pointer to a const HMEVENT struct. */
423typedef const HMEVENT *PCHMEVENT;
424AssertCompileSizeAlignment(HMEVENT, 8);
425
426/**
427 * HM VM Instance data.
428 * Changes to this must checked against the padding of the hm union in VM!
429 */
430typedef struct HM
431{
432 /** Set if nested paging is enabled.
433 * Config value that is copied to HMR0PERVM::fNestedPaging on setup. */
434 bool fNestedPagingCfg;
435 /** Set when we've finalized the VMX / SVM initialization in ring-3
436 * (hmR3InitFinalizeR0Intel / hmR3InitFinalizeR0Amd). */
437 bool fInitialized;
438 /** Set if large pages are enabled (requires nested paging).
439 * Config only, passed on the PGM where it really belongs.
440 * @todo move to PGM */
441 bool fLargePages;
442 /** Set if we can support 64-bit guests or not.
443 * Config value that is copied to HMR0PERVM::fAllow64BitGuests on setup. */
444 bool fAllow64BitGuestsCfg;
445 /** Set when TPR patching is allowed. */
446 bool fTprPatchingAllowed;
447 /** Set when we initialize VT-x or AMD-V once for all CPUs. */
448 bool fGlobalInit;
449 /** Set when TPR patching is active. */
450 bool fTPRPatchingActive;
451 /** Set when the debug facility has breakpoints/events enabled that requires
452 * us to use the debug execution loop in ring-0. */
453 bool fUseDebugLoop;
454 /** Set if hardware APIC virtualization is enabled. */
455 bool fVirtApicRegs;
456 /** Set if posted interrupt processing is enabled. */
457 bool fPostedIntrs;
458 /** Set if indirect branch prediction barrier on VM exit. */
459 bool fIbpbOnVmExit;
460 /** Set if indirect branch prediction barrier on VM entry. */
461 bool fIbpbOnVmEntry;
462 /** Set if level 1 data cache should be flushed on VM entry. */
463 bool fL1dFlushOnVmEntry;
464 /** Set if level 1 data cache should be flushed on EMT scheduling. */
465 bool fL1dFlushOnSched;
466 /** Set if host manages speculation control settings. */
467 bool fSpecCtrlByHost;
468 /** Set if MDS related buffers should be cleared on VM entry. */
469 bool fMdsClearOnVmEntry;
470 /** Set if MDS related buffers should be cleared on EMT scheduling. */
471 bool fMdsClearOnSched;
472 /** Alignment padding. */
473 bool afPaddingMinus1[3];
474
475 /** The maximum number of resumes loops allowed in ring-0 (safety precaution).
476 * This number is set much higher when RTThreadPreemptIsPending is reliable. */
477 uint32_t cMaxResumeLoops;
478
479 /** Maximum ASID allowed. */
480 uint32_t uMaxAsid;
481
482 /** Host kernel flags that HM might need to know (SUPKERNELFEATURES_XXX). */
483 uint32_t fHostKernelFeatures;
484
485 struct
486 {
487 /** Set by the ring-0 side of HM to indicate VMX is supported by the
488 * CPU. */
489 bool fSupported;
490 /** Set when we've enabled VMX. */
491 bool fEnabled;
492 /** Set if VPID is supported. */
493 bool fVpid;
494 /** Set if VT-x VPID is allowed. */
495 bool fAllowVpid;
496 /** Set if unrestricted guest execution is in use (real and protected mode
497 * without paging). */
498 bool fUnrestrictedGuest;
499 /** Set if the preemption timer is in use or not. */
500 bool fUsePreemptTimer;
501 /** The shift mask employed by the VMX-Preemption timer. */
502 uint8_t cPreemptTimerShift;
503 /** Padding. */
504 bool afPadding0;
505
506 /** Virtual address of the APIC-access page. */
507 R0PTRTYPE(uint8_t *) pbApicAccess;
508 /** Pointer to the VMREAD bitmap. */
509 R0PTRTYPE(void *) pvVmreadBitmap;
510 /** Pointer to the VMWRITE bitmap. */
511 R0PTRTYPE(void *) pvVmwriteBitmap;
512
513 /** Pointer to the shadow VMCS read-only fields array. */
514 R0PTRTYPE(uint32_t *) paShadowVmcsRoFields;
515 /** Pointer to the shadow VMCS read/write fields array. */
516 R0PTRTYPE(uint32_t *) paShadowVmcsFields;
517 /** Number of elements in the shadow VMCS read-only fields array. */
518 uint32_t cShadowVmcsRoFields;
519 /** Number of elements in the shadow VMCS read-write fields array. */
520 uint32_t cShadowVmcsFields;
521
522 /** Tagged-TLB flush type. */
523 VMXTLBFLUSHTYPE enmTlbFlushType;
524 /** Flush type to use for INVEPT. */
525 VMXTLBFLUSHEPT enmTlbFlushEpt;
526 /** Flush type to use for INVVPID. */
527 VMXTLBFLUSHVPID enmTlbFlushVpid;
528
529 /** Pause-loop exiting (PLE) gap in ticks. */
530 uint32_t cPleGapTicks;
531 /** Pause-loop exiting (PLE) window in ticks. */
532 uint32_t cPleWindowTicks;
533 uint32_t u32Alignment0;
534
535 /** Host CR4 value (set by ring-0 VMX init) */
536 uint64_t u64HostCr4;
537 /** Host SMM monitor control (set by ring-0 VMX init) */
538 uint64_t u64HostSmmMonitorCtl;
539 /** Host EFER value (set by ring-0 VMX init) */
540 uint64_t u64HostMsrEfer;
541 /** Whether the CPU supports VMCS fields for swapping EFER. */
542 bool fSupportsVmcsEfer;
543 /** Whether to use VMCS shadowing. */
544 bool fUseVmcsShadowing;
545 /** Set if Last Branch Record (LBR) is enabled. */
546 bool fLbr;
547 uint8_t u8Alignment2[5];
548
549 /** The first valid host LBR branch-from-IP stack range. */
550 uint32_t idLbrFromIpMsrFirst;
551 /** The last valid host LBR branch-from-IP stack range. */
552 uint32_t idLbrFromIpMsrLast;
553
554 /** The first valid host LBR branch-to-IP stack range. */
555 uint32_t idLbrToIpMsrFirst;
556 /** The last valid host LBR branch-to-IP stack range. */
557 uint32_t idLbrToIpMsrLast;
558
559 /** The host LBR TOS (top-of-stack) MSR id. */
560 uint32_t idLbrTosMsr;
561 /** Padding. */
562 uint32_t u32Alignment1;
563
564 /** VMX MSR values. */
565 VMXMSRS Msrs;
566
567 /** Host-physical address for a failing VMXON instruction. */
568 RTHCPHYS HCPhysVmxEnableError;
569 /** Host-physical address of the APIC-access page. */
570 RTHCPHYS HCPhysApicAccess;
571 /** Host-physical address of the VMREAD bitmap. */
572 RTHCPHYS HCPhysVmreadBitmap;
573 /** Host-physical address of the VMWRITE bitmap. */
574 RTHCPHYS HCPhysVmwriteBitmap;
575#ifdef VBOX_WITH_CRASHDUMP_MAGIC
576 /** Host-physical address of the crash-dump scratch area. */
577 RTHCPHYS HCPhysScratch;
578#endif
579
580#ifdef VBOX_WITH_CRASHDUMP_MAGIC
581 /** Pointer to the crash-dump scratch bitmap. */
582 R0PTRTYPE(uint8_t *) pbScratch;
583#endif
584 /** Virtual address of the TSS page used for real mode emulation. */
585 R3PTRTYPE(PVBOXTSS) pRealModeTSS;
586 /** Virtual address of the identity page table used for real mode and protected
587 * mode without paging emulation in EPT mode. */
588 R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
589
590 /** Ring-0 memory object for per-VM VMX structures. */
591 RTR0MEMOBJ hMemObj;
592 } vmx;
593
594 struct
595 {
596 /** Set by the ring-0 side of HM to indicate SVM is supported by the CPU. */
597 bool fSupported;
598 /** Set when we've enabled SVM. */
599 bool fEnabled;
600 /** Set when the hack to ignore VERR_SVM_IN_USE is active.
601 * @todo Safe? */
602 bool fIgnoreInUseError;
603 /** Whether to use virtualized VMSAVE/VMLOAD feature. */
604 bool fVirtVmsaveVmload;
605 /** Whether to use virtual GIF feature. */
606 bool fVGif;
607 /** Whether to use LBR virtualization feature. */
608 bool fLbrVirt;
609 uint8_t u8Alignment0[2];
610
611 /* HWCR MSR (for diagnostics) */
612 uint64_t u64MsrHwcr;
613
614 /** SVM revision. */
615 uint32_t u32Rev;
616 /** SVM feature bits from cpuid 0x8000000a, ring-3 copy. */
617 uint32_t fFeaturesForRing3;
618
619 /** Pause filter counter. */
620 uint16_t cPauseFilter;
621 /** Pause filter treshold in ticks. */
622 uint16_t cPauseFilterThresholdTicks;
623 uint32_t u32Alignment0;
624 } svm;
625
626 /** AVL tree with all patches (active or disabled) sorted by guest instruction address.
627 * @todo For @bugref{9217} this AVL tree must be eliminated and instead
628 * sort aPatches by address and do a safe binary search on it. */
629 AVLOU32TREE PatchTree;
630 uint32_t cPatches;
631 HMTPRPATCH aPatches[64];
632
633 /** Guest allocated memory for patching purposes. */
634 RTGCPTR pGuestPatchMem;
635 /** Current free pointer inside the patch block. */
636 RTGCPTR pFreeGuestPatchMem;
637 /** Size of the guest patch memory block. */
638 uint32_t cbGuestPatchMem;
639
640 /** Last recorded error code during HM ring-0 init. */
641 int32_t rcInit;
642
643 STAMCOUNTER StatTprPatchSuccess;
644 STAMCOUNTER StatTprPatchFailure;
645 STAMCOUNTER StatTprReplaceSuccessCr8;
646 STAMCOUNTER StatTprReplaceSuccessVmc;
647 STAMCOUNTER StatTprReplaceFailure;
648} HM;
649/** Pointer to HM VM instance data. */
650typedef HM *PHM;
651AssertCompileMemberAlignment(HM, StatTprPatchSuccess, 8);
652AssertCompileMemberAlignment(HM, vmx, 8);
653AssertCompileMemberAlignment(HM, svm, 8);
654
655
656/**
657 * Per-VM ring-0 instance data for HM.
658 */
659typedef struct HMR0PERVM
660{
661 /** Set if nested paging is enabled. */
662 bool fNestedPaging;
663 /** Set if we can support 64-bit guests or not. */
664 bool fAllow64BitGuests;
665
666 bool afAlignment0[6];
667
668 /** SVM specific data. */
669 struct HMR0SVMVM
670 {
671 /** Set if erratum 170 affects the AMD cpu. */
672 bool fAlwaysFlushTLB;
673 bool afAlignment0[3];
674 /** SVM feature bits from cpuid 0x8000000a, safe ring-0 copy. */
675 uint32_t fFeatures;
676 } svm;
677} HMR0PERVM;
678/** Pointer to HM's per-VM ring-0 instance data. */
679typedef HMR0PERVM *PHMR0PERVM;
680
681
682/** @addtogroup grp_hm_int_svm SVM Internal
683 * @{ */
684/** SVM VMRun function, see SVMR0VMRun(). */
685typedef DECLCALLBACKTYPE(int, FNHMSVMVMRUN,(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhysVMCB));
686/** Pointer to a SVM VMRun function. */
687typedef R0PTRTYPE(FNHMSVMVMRUN *) PFNHMSVMVMRUN;
688
689/**
690 * SVM nested-guest VMCB cache.
691 *
692 * Contains VMCB fields from the nested-guest VMCB before they're modified by
693 * SVM R0 code for hardware-assisted SVM execution of a nested-guest.
694 *
695 * A VMCB field needs to be cached when it needs to be modified for execution using
696 * hardware-assisted SVM and any of the following are true:
697 * - If the original field needs to be inspected during execution of the
698 * nested-guest or \#VMEXIT processing.
699 * - If the field is written back to memory on \#VMEXIT by the physical CPU.
700 *
701 * A VMCB field needs to be restored only when the field is written back to
702 * memory on \#VMEXIT by the physical CPU and thus would be visible to the
703 * guest.
704 *
705 * @remarks Please update hmR3InfoSvmNstGstVmcbCache() when changes are made to
706 * this structure.
707 */
708typedef struct SVMNESTEDVMCBCACHE
709{
710 /** Cache of CRX read intercepts. */
711 uint16_t u16InterceptRdCRx;
712 /** Cache of CRX write intercepts. */
713 uint16_t u16InterceptWrCRx;
714 /** Cache of DRX read intercepts. */
715 uint16_t u16InterceptRdDRx;
716 /** Cache of DRX write intercepts. */
717 uint16_t u16InterceptWrDRx;
718
719 /** Cache of the pause-filter threshold. */
720 uint16_t u16PauseFilterThreshold;
721 /** Cache of the pause-filter count. */
722 uint16_t u16PauseFilterCount;
723
724 /** Cache of exception intercepts. */
725 uint32_t u32InterceptXcpt;
726 /** Cache of control intercepts. */
727 uint64_t u64InterceptCtrl;
728
729 /** Cache of the TSC offset. */
730 uint64_t u64TSCOffset;
731
732 /** Cache of V_INTR_MASKING bit. */
733 bool fVIntrMasking;
734 /** Cache of the nested-paging bit. */
735 bool fNestedPaging;
736 /** Cache of the LBR virtualization bit. */
737 bool fLbrVirt;
738 /** Whether the VMCB is cached by HM. */
739 bool fCacheValid;
740 /** Alignment. */
741 bool afPadding0[4];
742} SVMNESTEDVMCBCACHE;
743/** Pointer to the SVMNESTEDVMCBCACHE structure. */
744typedef SVMNESTEDVMCBCACHE *PSVMNESTEDVMCBCACHE;
745/** Pointer to a const SVMNESTEDVMCBCACHE structure. */
746typedef const SVMNESTEDVMCBCACHE *PCSVMNESTEDVMCBCACHE;
747AssertCompileSizeAlignment(SVMNESTEDVMCBCACHE, 8);
748
749/** @} */
750
751
752/** @addtogroup grp_hm_int_vmx VMX Internal
753 * @{ */
754/**
755 * VMX VMCS information, shared.
756 *
757 * This structure provides information maintained for and during the executing of a
758 * guest (or nested-guest) VMCS (VM control structure) using hardware-assisted VMX.
759 *
760 * Note! The members here are ordered and aligned based on estimated frequency of
761 * usage and grouped to fit within a cache line in hot code paths. Even subtle
762 * changes here have a noticeable effect in the bootsector benchmarks. Modify with
763 * care.
764 */
765typedef struct VMXVMCSINFOSHARED
766{
767 /** @name Real-mode emulation state.
768 * @{ */
769 /** Set if guest was executing in real mode (extra checks). */
770 bool fWasInRealMode;
771 /** Padding. */
772 bool afPadding0[7];
773 struct
774 {
775 X86DESCATTR AttrCS;
776 X86DESCATTR AttrDS;
777 X86DESCATTR AttrES;
778 X86DESCATTR AttrFS;
779 X86DESCATTR AttrGS;
780 X86DESCATTR AttrSS;
781 X86EFLAGS Eflags;
782 bool fRealOnV86Active;
783 bool afPadding1[3];
784 } RealMode;
785 /** @} */
786
787 /** @name LBR MSR data.
788 * @{ */
789 /** List of LastBranch-From-IP MSRs. */
790 uint64_t au64LbrFromIpMsr[32];
791 /** List of LastBranch-To-IP MSRs. */
792 uint64_t au64LbrToIpMsr[32];
793 /** The MSR containing the index to the most recent branch record. */
794 uint64_t u64LbrTosMsr;
795 /** @} */
796} VMXVMCSINFOSHARED;
797/** Pointer to a VMXVMCSINFOSHARED struct. */
798typedef VMXVMCSINFOSHARED *PVMXVMCSINFOSHARED;
799/** Pointer to a const VMXVMCSINFOSHARED struct. */
800typedef const VMXVMCSINFOSHARED *PCVMXVMCSINFOSHARED;
801AssertCompileSizeAlignment(VMXVMCSINFOSHARED, 8);
802
803
804/**
805 * VMX VMCS information, ring-0 only.
806 *
807 * This structure provides information maintained for and during the executing of a
808 * guest (or nested-guest) VMCS (VM control structure) using hardware-assisted VMX.
809 *
810 * Note! The members here are ordered and aligned based on estimated frequency of
811 * usage and grouped to fit within a cache line in hot code paths. Even subtle
812 * changes here have a noticeable effect in the bootsector benchmarks. Modify with
813 * care.
814 */
815typedef struct VMXVMCSINFO
816{
817 /** Pointer to the bits we share with ring-3. */
818 R0PTRTYPE(PVMXVMCSINFOSHARED) pShared;
819
820 /** @name Auxiliary information.
821 * @{ */
822 /** Host-physical address of the EPTP. */
823 RTHCPHYS HCPhysEPTP;
824 /** The VMCS launch state, see VMX_V_VMCS_LAUNCH_STATE_XXX. */
825 uint32_t fVmcsState;
826 /** The VMCS launch state of the shadow VMCS, see VMX_V_VMCS_LAUNCH_STATE_XXX. */
827 uint32_t fShadowVmcsState;
828 /** The host CPU for which its state has been exported to this VMCS. */
829 RTCPUID idHostCpuState;
830 /** The host CPU on which we last executed this VMCS. */
831 RTCPUID idHostCpuExec;
832 /** Number of guest MSRs in the VM-entry MSR-load area. */
833 uint32_t cEntryMsrLoad;
834 /** Number of guest MSRs in the VM-exit MSR-store area. */
835 uint32_t cExitMsrStore;
836 /** Number of host MSRs in the VM-exit MSR-load area. */
837 uint32_t cExitMsrLoad;
838 /** @} */
839
840 /** @name Cache of execution related VMCS fields.
841 * @{ */
842 /** Pin-based VM-execution controls. */
843 uint32_t u32PinCtls;
844 /** Processor-based VM-execution controls. */
845 uint32_t u32ProcCtls;
846 /** Secondary processor-based VM-execution controls. */
847 uint32_t u32ProcCtls2;
848 /** VM-entry controls. */
849 uint32_t u32EntryCtls;
850 /** VM-exit controls. */
851 uint32_t u32ExitCtls;
852 /** Exception bitmap. */
853 uint32_t u32XcptBitmap;
854 /** Page-fault exception error-code mask. */
855 uint32_t u32XcptPFMask;
856 /** Page-fault exception error-code match. */
857 uint32_t u32XcptPFMatch;
858 /** Padding. */
859 uint32_t u32Alignment0;
860 /** TSC offset. */
861 uint64_t u64TscOffset;
862 /** VMCS link pointer. */
863 uint64_t u64VmcsLinkPtr;
864 /** CR0 guest/host mask. */
865 uint64_t u64Cr0Mask;
866 /** CR4 guest/host mask. */
867 uint64_t u64Cr4Mask;
868 /** Current VMX_VMCS_HOST_RIP value (only used in HMR0A.asm). */
869 uint64_t uHostRip;
870 /** Current VMX_VMCS_HOST_RSP value (only used in HMR0A.asm). */
871 uint64_t uHostRsp;
872 /** @} */
873
874 /** @name Host-virtual address of VMCS and related data structures.
875 * @{ */
876 /** The VMCS. */
877 R0PTRTYPE(void *) pvVmcs;
878 /** The shadow VMCS. */
879 R0PTRTYPE(void *) pvShadowVmcs;
880 /** The virtual-APIC page. */
881 R0PTRTYPE(uint8_t *) pbVirtApic;
882 /** The MSR bitmap. */
883 R0PTRTYPE(void *) pvMsrBitmap;
884 /** The VM-entry MSR-load area. */
885 R0PTRTYPE(void *) pvGuestMsrLoad;
886 /** The VM-exit MSR-store area. */
887 R0PTRTYPE(void *) pvGuestMsrStore;
888 /** The VM-exit MSR-load area. */
889 R0PTRTYPE(void *) pvHostMsrLoad;
890 /** @} */
891
892 /** @name Host-physical address of VMCS and related data structures.
893 * @{ */
894 /** The VMCS. */
895 RTHCPHYS HCPhysVmcs;
896 /** The shadow VMCS. */
897 RTHCPHYS HCPhysShadowVmcs;
898 /** The virtual APIC page. */
899 RTHCPHYS HCPhysVirtApic;
900 /** The MSR bitmap. */
901 RTHCPHYS HCPhysMsrBitmap;
902 /** The VM-entry MSR-load area. */
903 RTHCPHYS HCPhysGuestMsrLoad;
904 /** The VM-exit MSR-store area. */
905 RTHCPHYS HCPhysGuestMsrStore;
906 /** The VM-exit MSR-load area. */
907 RTHCPHYS HCPhysHostMsrLoad;
908 /** @} */
909
910 /** @name R0-memory objects address for VMCS and related data structures.
911 * @{ */
912 /** R0-memory object for VMCS and related data structures. */
913 RTR0MEMOBJ hMemObj;
914 /** @} */
915} VMXVMCSINFO;
916/** Pointer to a VMXVMCSINFOR0 struct. */
917typedef VMXVMCSINFO *PVMXVMCSINFO;
918/** Pointer to a const VMXVMCSINFO struct. */
919typedef const VMXVMCSINFO *PCVMXVMCSINFO;
920AssertCompileSizeAlignment(VMXVMCSINFO, 8);
921AssertCompileMemberAlignment(VMXVMCSINFO, u32PinCtls, 4);
922AssertCompileMemberAlignment(VMXVMCSINFO, u64VmcsLinkPtr, 8);
923AssertCompileMemberAlignment(VMXVMCSINFO, pvVmcs, 8);
924AssertCompileMemberAlignment(VMXVMCSINFO, pvShadowVmcs, 8);
925AssertCompileMemberAlignment(VMXVMCSINFO, pbVirtApic, 8);
926AssertCompileMemberAlignment(VMXVMCSINFO, pvMsrBitmap, 8);
927AssertCompileMemberAlignment(VMXVMCSINFO, pvGuestMsrLoad, 8);
928AssertCompileMemberAlignment(VMXVMCSINFO, pvGuestMsrStore, 8);
929AssertCompileMemberAlignment(VMXVMCSINFO, pvHostMsrLoad, 8);
930AssertCompileMemberAlignment(VMXVMCSINFO, HCPhysVmcs, 8);
931AssertCompileMemberAlignment(VMXVMCSINFO, hMemObj, 8);
932
933
934/** @name Host-state restoration flags.
935 * @note If you change these values don't forget to update the assembly
936 * defines as well!
937 * @{
938 */
939#define VMX_RESTORE_HOST_SEL_DS RT_BIT(0)
940#define VMX_RESTORE_HOST_SEL_ES RT_BIT(1)
941#define VMX_RESTORE_HOST_SEL_FS RT_BIT(2)
942#define VMX_RESTORE_HOST_SEL_GS RT_BIT(3)
943#define VMX_RESTORE_HOST_SEL_TR RT_BIT(4)
944#define VMX_RESTORE_HOST_GDTR RT_BIT(5)
945#define VMX_RESTORE_HOST_IDTR RT_BIT(6)
946#define VMX_RESTORE_HOST_GDT_READ_ONLY RT_BIT(7)
947#define VMX_RESTORE_HOST_GDT_NEED_WRITABLE RT_BIT(8)
948#define VMX_RESTORE_HOST_CAN_USE_WRFSBASE_AND_WRGSBASE RT_BIT(9)
949/**
950 * This _must_ be the top most bit, so that we can easily that that it and
951 * something else is set w/o having to do two checks like this:
952 * @code
953 * if ( (pVCpu->hm.s.vmx.fRestoreHostFlags & VMX_RESTORE_HOST_REQUIRED)
954 * && (pVCpu->hm.s.vmx.fRestoreHostFlags & ~VMX_RESTORE_HOST_REQUIRED))
955 * @endcode
956 * Instead we can then do:
957 * @code
958 * if (pVCpu->hm.s.vmx.fRestoreHostFlags > VMX_RESTORE_HOST_REQUIRED)
959 * @endcode
960 */
961#define VMX_RESTORE_HOST_REQUIRED RT_BIT(10)
962/** @} */
963
964/**
965 * Host-state restoration structure.
966 *
967 * This holds host-state fields that require manual restoration.
968 * Assembly version found in HMInternal.mac (should be automatically verified).
969 */
970typedef struct VMXRESTOREHOST
971{
972 RTSEL uHostSelDS; /**< 0x00 */
973 RTSEL uHostSelES; /**< 0x02 */
974 RTSEL uHostSelFS; /**< 0x04 */
975 X86XDTR64 HostGdtr; /**< 0x06 - should be aligned by its 64-bit member. */
976 RTSEL uHostSelGS; /**< 0x10 */
977 RTSEL uHostSelTR; /**< 0x12 */
978 RTSEL uHostSelSS; /**< 0x14 - not restored, just for fetching */
979 X86XDTR64 HostGdtrRw; /**< 0x16 - should be aligned by its 64-bit member. */
980 RTSEL uHostSelCS; /**< 0x20 - not restored, just for fetching */
981 uint8_t abPadding1[4]; /**< 0x22 */
982 X86XDTR64 HostIdtr; /**< 0x26 - should be aligned by its 64-bit member. */
983 uint64_t uHostFSBase; /**< 0x30 */
984 uint64_t uHostGSBase; /**< 0x38 */
985} VMXRESTOREHOST;
986/** Pointer to VMXRESTOREHOST. */
987typedef VMXRESTOREHOST *PVMXRESTOREHOST;
988AssertCompileSize(X86XDTR64, 10);
989AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtr.uAddr, 0x08);
990AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtrRw.uAddr, 0x18);
991AssertCompileMemberOffset(VMXRESTOREHOST, HostIdtr.uAddr, 0x28);
992AssertCompileMemberOffset(VMXRESTOREHOST, uHostFSBase, 0x30);
993AssertCompileSize(VMXRESTOREHOST, 64);
994AssertCompileSizeAlignment(VMXRESTOREHOST, 8);
995
996/**
997 * VMX StartVM function.
998 *
999 * @returns VBox status code (no informational stuff).
1000 * @param pVmcsInfo Pointer to the VMCS info (for cached host RIP and RSP).
1001 * @param pVCpu Pointer to the cross context per-CPU structure.
1002 * @param fResume Whether to use VMRESUME (true) or VMLAUNCH (false).
1003 */
1004typedef DECLCALLBACKTYPE(int, FNHMVMXSTARTVM,(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume));
1005/** Pointer to a VMX StartVM function. */
1006typedef R0PTRTYPE(FNHMVMXSTARTVM *) PFNHMVMXSTARTVM;
1007/** @} */
1008
1009/**
1010 * HM VMCPU Instance data.
1011 *
1012 * Note! If you change members of this struct, make sure to check if the
1013 * assembly counterpart in HMInternal.mac needs to be updated as well.
1014 *
1015 * Note! The members here are ordered and aligned based on estimated frequency of
1016 * usage and grouped to fit within a cache line in hot code paths. Even subtle
1017 * changes here have a noticeable effect in the bootsector benchmarks. Modify with
1018 * care.
1019 */
1020typedef struct HMCPU
1021{
1022 /** Set when the TLB has been checked until we return from the world switch. */
1023 bool volatile fCheckedTLBFlush;
1024 /** Set when we're using VT-x or AMD-V at that moment.
1025 * @todo r=bird: Misleading description. For AMD-V this will be set the first
1026 * time HMCanExecuteGuest() is called and only cleared again by
1027 * HMR3ResetCpu(). For VT-x it will be set by HMCanExecuteGuest when we
1028 * can execute something in VT-x mode, and cleared if we cannot.
1029 *
1030 * The field is much more about recording the last HMCanExecuteGuest
1031 * return value than anything about any "moment". */
1032 bool fActive;
1033
1034 /** Whether we should use the debug loop because of single stepping or special
1035 * debug breakpoints / events are armed. */
1036 bool fUseDebugLoop;
1037
1038 /** Whether \#UD needs to be intercepted (required by certain GIM providers). */
1039 bool fGIMTrapXcptUD;
1040 /** Whether \#GP needs to be intercepted for mesa driver workaround. */
1041 bool fTrapXcptGpForLovelyMesaDrv;
1042 /** Whether we're executing a single instruction. */
1043 bool fSingleInstruction;
1044
1045 bool afAlignment0[2];
1046
1047 /** An additional error code used for some gurus. */
1048 uint32_t u32HMError;
1049 /** The last exit-to-ring-3 reason. */
1050 int32_t rcLastExitToR3;
1051 /** CPU-context changed flags (see HM_CHANGED_xxx). */
1052 uint64_t fCtxChanged;
1053
1054 /** VT-x data. */
1055 struct HMCPUVMX
1056 {
1057 /** @name Guest information.
1058 * @{ */
1059 /** Guest VMCS information shared with ring-3. */
1060 VMXVMCSINFOSHARED VmcsInfo;
1061 /** Nested-guest VMCS information shared with ring-3. */
1062 VMXVMCSINFOSHARED VmcsInfoNstGst;
1063 /** Whether the nested-guest VMCS was the last current VMCS (shadow copy for ring-3).
1064 * @see HMR0PERVCPU::vmx.fSwitchedToNstGstVmcs */
1065 bool fSwitchedToNstGstVmcsCopyForRing3;
1066 /** Whether the static guest VMCS controls has been merged with the
1067 * nested-guest VMCS controls. */
1068 bool fMergedNstGstCtls;
1069 /** Whether the nested-guest VMCS has been copied to the shadow VMCS. */
1070 bool fCopiedNstGstToShadowVmcs;
1071 /** Whether flushing the TLB is required due to switching to/from the
1072 * nested-guest. */
1073 bool fSwitchedNstGstFlushTlb;
1074 /** Alignment. */
1075 bool afAlignment0[4];
1076 /** Cached guest APIC-base MSR for identifying when to map the APIC-access page. */
1077 uint64_t u64GstMsrApicBase;
1078 /** @} */
1079
1080 /** @name Error reporting and diagnostics.
1081 * @{ */
1082 /** VT-x error-reporting (mainly for ring-3 propagation). */
1083 struct
1084 {
1085 RTCPUID idCurrentCpu;
1086 RTCPUID idEnteredCpu;
1087 RTHCPHYS HCPhysCurrentVmcs;
1088 uint32_t u32VmcsRev;
1089 uint32_t u32InstrError;
1090 uint32_t u32ExitReason;
1091 uint32_t u32GuestIntrState;
1092 } LastError;
1093 /** @} */
1094 } vmx;
1095
1096 /** SVM data. */
1097 struct HMCPUSVM
1098 {
1099 /** Whether to emulate long mode support for sysenter/sysexit like intel CPUs
1100 * does. This means intercepting \#UD to emulate the instructions in
1101 * long-mode and to intercept reads and writes to the SYSENTER MSRs in order to
1102 * preserve the upper 32 bits written to them (AMD will ignore and discard). */
1103 bool fEmulateLongModeSysEnterExit;
1104 uint8_t au8Alignment0[7];
1105
1106 /** Cache of the nested-guest's VMCB fields that we modify in order to run the
1107 * nested-guest using AMD-V. This will be restored on \#VMEXIT. */
1108 SVMNESTEDVMCBCACHE NstGstVmcbCache;
1109 } svm;
1110
1111 /** Event injection state. */
1112 HMEVENT Event;
1113
1114 /** Current shadow paging mode for updating CR4.
1115 * @todo move later (@bugref{9217}). */
1116 PGMMODE enmShadowMode;
1117 uint32_t u32TemporaryPadding;
1118
1119 /** The PAE PDPEs used with Nested Paging (only valid when
1120 * VMCPU_FF_HM_UPDATE_PAE_PDPES is set). */
1121 X86PDPE aPdpes[4];
1122
1123 /* These two comes because they are accessed from assembly and we don't
1124 want to detail all the stats in the assembly version of this structure. */
1125 STAMCOUNTER StatVmxWriteHostRip;
1126 STAMCOUNTER StatVmxWriteHostRsp;
1127 STAMCOUNTER StatVmxVmLaunch;
1128 STAMCOUNTER StatVmxVmResume;
1129
1130 STAMPROFILEADV StatEntry;
1131 STAMPROFILEADV StatPreExit;
1132 STAMPROFILEADV StatExitHandling;
1133 STAMPROFILEADV StatExitIO;
1134 STAMPROFILEADV StatExitMovCRx;
1135 STAMPROFILEADV StatExitXcptNmi;
1136 STAMPROFILEADV StatExitVmentry;
1137 STAMPROFILEADV StatImportGuestState;
1138 STAMPROFILEADV StatExportGuestState;
1139 STAMPROFILEADV StatLoadGuestFpuState;
1140 STAMPROFILEADV StatInGC;
1141 STAMPROFILEADV StatPoke;
1142 STAMPROFILEADV StatSpinPoke;
1143 STAMPROFILEADV StatSpinPokeFailed;
1144
1145 STAMCOUNTER StatInjectInterrupt;
1146 STAMCOUNTER StatInjectXcpt;
1147 STAMCOUNTER StatInjectReflect;
1148 STAMCOUNTER StatInjectConvertDF;
1149 STAMCOUNTER StatInjectInterpret;
1150 STAMCOUNTER StatInjectReflectNPF;
1151
1152 STAMCOUNTER StatExitAll;
1153 STAMCOUNTER StatNestedExitAll;
1154 STAMCOUNTER StatExitShadowNM;
1155 STAMCOUNTER StatExitGuestNM;
1156 STAMCOUNTER StatExitShadowPF; /**< Misleading, currently used for MMIO \#PFs as well. */
1157 STAMCOUNTER StatExitShadowPFEM;
1158 STAMCOUNTER StatExitGuestPF;
1159 STAMCOUNTER StatExitGuestUD;
1160 STAMCOUNTER StatExitGuestSS;
1161 STAMCOUNTER StatExitGuestNP;
1162 STAMCOUNTER StatExitGuestTS;
1163 STAMCOUNTER StatExitGuestOF;
1164 STAMCOUNTER StatExitGuestGP;
1165 STAMCOUNTER StatExitGuestDE;
1166 STAMCOUNTER StatExitGuestDF;
1167 STAMCOUNTER StatExitGuestBR;
1168 STAMCOUNTER StatExitGuestAC;
1169 STAMCOUNTER StatExitGuestDB;
1170 STAMCOUNTER StatExitGuestMF;
1171 STAMCOUNTER StatExitGuestBP;
1172 STAMCOUNTER StatExitGuestXF;
1173 STAMCOUNTER StatExitGuestXcpUnk;
1174 STAMCOUNTER StatExitDRxWrite;
1175 STAMCOUNTER StatExitDRxRead;
1176 STAMCOUNTER StatExitCR0Read;
1177 STAMCOUNTER StatExitCR2Read;
1178 STAMCOUNTER StatExitCR3Read;
1179 STAMCOUNTER StatExitCR4Read;
1180 STAMCOUNTER StatExitCR8Read;
1181 STAMCOUNTER StatExitCR0Write;
1182 STAMCOUNTER StatExitCR2Write;
1183 STAMCOUNTER StatExitCR3Write;
1184 STAMCOUNTER StatExitCR4Write;
1185 STAMCOUNTER StatExitCR8Write;
1186 STAMCOUNTER StatExitRdmsr;
1187 STAMCOUNTER StatExitWrmsr;
1188 STAMCOUNTER StatExitClts;
1189 STAMCOUNTER StatExitXdtrAccess;
1190 STAMCOUNTER StatExitLmsw;
1191 STAMCOUNTER StatExitIOWrite;
1192 STAMCOUNTER StatExitIORead;
1193 STAMCOUNTER StatExitIOStringWrite;
1194 STAMCOUNTER StatExitIOStringRead;
1195 STAMCOUNTER StatExitIntWindow;
1196 STAMCOUNTER StatExitExtInt;
1197 STAMCOUNTER StatExitHostNmiInGC;
1198 STAMCOUNTER StatExitHostNmiInGCIpi;
1199 STAMCOUNTER StatExitPreemptTimer;
1200 STAMCOUNTER StatExitTprBelowThreshold;
1201 STAMCOUNTER StatExitTaskSwitch;
1202 STAMCOUNTER StatExitApicAccess;
1203 STAMCOUNTER StatExitReasonNpf;
1204
1205 STAMCOUNTER StatNestedExitReasonNpf;
1206
1207 STAMCOUNTER StatFlushPage;
1208 STAMCOUNTER StatFlushPageManual;
1209 STAMCOUNTER StatFlushPhysPageManual;
1210 STAMCOUNTER StatFlushTlb;
1211 STAMCOUNTER StatFlushTlbNstGst;
1212 STAMCOUNTER StatFlushTlbManual;
1213 STAMCOUNTER StatFlushTlbWorldSwitch;
1214 STAMCOUNTER StatNoFlushTlbWorldSwitch;
1215 STAMCOUNTER StatFlushEntire;
1216 STAMCOUNTER StatFlushAsid;
1217 STAMCOUNTER StatFlushNestedPaging;
1218 STAMCOUNTER StatFlushTlbInvlpgVirt;
1219 STAMCOUNTER StatFlushTlbInvlpgPhys;
1220 STAMCOUNTER StatTlbShootdown;
1221 STAMCOUNTER StatTlbShootdownFlush;
1222
1223 STAMCOUNTER StatSwitchPendingHostIrq;
1224 STAMCOUNTER StatSwitchTprMaskedIrq;
1225 STAMCOUNTER StatSwitchGuestIrq;
1226 STAMCOUNTER StatSwitchHmToR3FF;
1227 STAMCOUNTER StatSwitchVmReq;
1228 STAMCOUNTER StatSwitchPgmPoolFlush;
1229 STAMCOUNTER StatSwitchDma;
1230 STAMCOUNTER StatSwitchExitToR3;
1231 STAMCOUNTER StatSwitchLongJmpToR3;
1232 STAMCOUNTER StatSwitchMaxResumeLoops;
1233 STAMCOUNTER StatSwitchHltToR3;
1234 STAMCOUNTER StatSwitchApicAccessToR3;
1235 STAMCOUNTER StatSwitchPreempt;
1236 STAMCOUNTER StatSwitchNstGstVmexit;
1237
1238 STAMCOUNTER StatTscParavirt;
1239 STAMCOUNTER StatTscOffset;
1240 STAMCOUNTER StatTscIntercept;
1241
1242 STAMCOUNTER StatDRxArmed;
1243 STAMCOUNTER StatDRxContextSwitch;
1244 STAMCOUNTER StatDRxIoCheck;
1245
1246 STAMCOUNTER StatExportMinimal;
1247 STAMCOUNTER StatExportFull;
1248 STAMCOUNTER StatLoadGuestFpu;
1249 STAMCOUNTER StatExportHostState;
1250
1251 STAMCOUNTER StatVmxCheckBadRmSelBase;
1252 STAMCOUNTER StatVmxCheckBadRmSelLimit;
1253 STAMCOUNTER StatVmxCheckBadRmSelAttr;
1254 STAMCOUNTER StatVmxCheckBadV86SelBase;
1255 STAMCOUNTER StatVmxCheckBadV86SelLimit;
1256 STAMCOUNTER StatVmxCheckBadV86SelAttr;
1257 STAMCOUNTER StatVmxCheckRmOk;
1258 STAMCOUNTER StatVmxCheckBadSel;
1259 STAMCOUNTER StatVmxCheckBadRpl;
1260 STAMCOUNTER StatVmxCheckPmOk;
1261
1262#ifdef VBOX_WITH_STATISTICS
1263 R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
1264 R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
1265 R3PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqs;
1266 R0PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqsR0;
1267 R3PTRTYPE(PSTAMCOUNTER) paStatInjectedXcpts;
1268 R0PTRTYPE(PSTAMCOUNTER) paStatInjectedXcptsR0;
1269 R3PTRTYPE(PSTAMCOUNTER) paStatNestedExitReason;
1270 R0PTRTYPE(PSTAMCOUNTER) paStatNestedExitReasonR0;
1271#endif
1272#ifdef HM_PROFILE_EXIT_DISPATCH
1273 STAMPROFILEADV StatExitDispatch;
1274#endif
1275} HMCPU;
1276/** Pointer to HM VMCPU instance data. */
1277typedef HMCPU *PHMCPU;
1278AssertCompileMemberAlignment(HMCPU, fCheckedTLBFlush, 4);
1279AssertCompileMemberAlignment(HMCPU, fCtxChanged, 8);
1280AssertCompileMemberAlignment(HMCPU, vmx, 8);
1281AssertCompileMemberAlignment(HMCPU, vmx.VmcsInfo, 8);
1282AssertCompileMemberAlignment(HMCPU, vmx.VmcsInfoNstGst, 8);
1283AssertCompileMemberAlignment(HMCPU, svm, 8);
1284AssertCompileMemberAlignment(HMCPU, Event, 8);
1285
1286
1287/**
1288 * HM per-VCpu ring-0 only instance data.
1289 */
1290typedef struct HMR0PERVCPU
1291{
1292 /** World switch exit counter. */
1293 uint32_t volatile cWorldSwitchExits;
1294 /** TLB flush count. */
1295 uint32_t cTlbFlushes;
1296 /** The last CPU we were executing code on (NIL_RTCPUID for the first time). */
1297 RTCPUID idLastCpu;
1298 /** The CPU ID of the CPU currently owning the VMCS. Set in
1299 * HMR0Enter and cleared in HMR0Leave. */
1300 RTCPUID idEnteredCpu;
1301 /** Current ASID in use by the VM. */
1302 uint32_t uCurrentAsid;
1303
1304 /** Set if we need to flush the TLB during the world switch. */
1305 bool fForceTLBFlush;
1306 /** Whether we've completed the inner HM leave function. */
1307 bool fLeaveDone;
1308 /** Whether we're using the hyper DR7 or guest DR7. */
1309 bool fUsingHyperDR7;
1310 /** Whether we are currently executing in the debug loop.
1311 * Mainly for assertions. */
1312 bool fUsingDebugLoop;
1313 /** Set if we using the debug loop and wish to intercept RDTSC. */
1314 bool fDebugWantRdTscExit;
1315 /** Set if XCR0 needs to be saved/restored when entering/exiting guest code
1316 * execution. */
1317 bool fLoadSaveGuestXcr0;
1318 /** Set if we need to clear the trap flag because of single stepping. */
1319 bool fClearTrapFlag;
1320
1321 bool afPadding1[5];
1322
1323 /** VT-x data. */
1324 struct HMR0CPUVMX
1325 {
1326 /** Ring-0 pointer to the hardware-assisted VMX execution function. */
1327 PFNHMVMXSTARTVM pfnStartVm;
1328
1329 /** @name Guest information.
1330 * @{ */
1331 /** Guest VMCS information. */
1332 VMXVMCSINFO VmcsInfo;
1333 /** Nested-guest VMCS information. */
1334 VMXVMCSINFO VmcsInfoNstGst;
1335 /* Whether the nested-guest VMCS was the last current VMCS (authoritative copy).
1336 * @see HMCPU::vmx.fSwitchedToNstGstVmcsCopyForRing3 */
1337 bool fSwitchedToNstGstVmcs;
1338 bool afAlignment0[7];
1339 /** @} */
1340
1341 /** @name Host information.
1342 * @{ */
1343 /** Host LSTAR MSR to restore lazily while leaving VT-x. */
1344 uint64_t u64HostMsrLStar;
1345 /** Host STAR MSR to restore lazily while leaving VT-x. */
1346 uint64_t u64HostMsrStar;
1347 /** Host SF_MASK MSR to restore lazily while leaving VT-x. */
1348 uint64_t u64HostMsrSfMask;
1349 /** Host KernelGS-Base MSR to restore lazily while leaving VT-x. */
1350 uint64_t u64HostMsrKernelGsBase;
1351 /** The mask of lazy MSRs swap/restore state, see VMX_LAZY_MSRS_XXX. */
1352 uint32_t fLazyMsrs;
1353 /** Whether the host MSR values are up-to-date in the auto-load/store MSR area. */
1354 bool fUpdatedHostAutoMsrs;
1355 /** Alignment. */
1356 uint8_t au8Alignment0[3];
1357 /** Which host-state bits to restore before being preempted, see
1358 * VMX_RESTORE_HOST_XXX. */
1359 uint32_t fRestoreHostFlags;
1360 /** Alignment. */
1361 uint32_t u32Alignment0;
1362 /** The host-state restoration structure. */
1363 VMXRESTOREHOST RestoreHost;
1364 /** @} */
1365 } vmx;
1366
1367 /** SVM data. */
1368 struct HMR0CPUSVM
1369 {
1370 /** Ring 0 handlers for VT-x. */
1371 PFNHMSVMVMRUN pfnVMRun;
1372
1373 /** Physical address of the host VMCB which holds additional host-state. */
1374 RTHCPHYS HCPhysVmcbHost;
1375 /** R0 memory object for the host VMCB which holds additional host-state. */
1376 RTR0MEMOBJ hMemObjVmcbHost;
1377
1378 /** Physical address of the guest VMCB. */
1379 RTHCPHYS HCPhysVmcb;
1380 /** R0 memory object for the guest VMCB. */
1381 RTR0MEMOBJ hMemObjVmcb;
1382 /** Pointer to the guest VMCB. */
1383 R0PTRTYPE(PSVMVMCB) pVmcb;
1384
1385 /** Physical address of the MSR bitmap (8 KB). */
1386 RTHCPHYS HCPhysMsrBitmap;
1387 /** R0 memory object for the MSR bitmap (8 KB). */
1388 RTR0MEMOBJ hMemObjMsrBitmap;
1389 /** Pointer to the MSR bitmap. */
1390 R0PTRTYPE(void *) pvMsrBitmap;
1391
1392 /** Whether VTPR with V_INTR_MASKING set is in effect, indicating
1393 * we should check if the VTPR changed on every VM-exit. */
1394 bool fSyncVTpr;
1395 bool afAlignment[7];
1396
1397 /** Host's TSC_AUX MSR (used when RDTSCP doesn't cause VM-exits). */
1398 uint64_t u64HostTscAux;
1399
1400 /** For saving stack space, the disassembler state is allocated here
1401 * instead of on the stack. */
1402 DISCPUSTATE DisState;
1403 } svm;
1404} HMR0PERVCPU;
1405/** Pointer to HM ring-0 VMCPU instance data. */
1406typedef HMR0PERVCPU *PHMR0PERVCPU;
1407AssertCompileMemberAlignment(HMR0PERVCPU, cWorldSwitchExits, 4);
1408AssertCompileMemberAlignment(HMR0PERVCPU, fForceTLBFlush, 4);
1409AssertCompileMemberAlignment(HMR0PERVCPU, vmx.RestoreHost, 8);
1410
1411
1412#ifdef IN_RING0
1413VMMR0_INT_DECL(PHMPHYSCPU) hmR0GetCurrentCpu(void);
1414VMMR0_INT_DECL(int) hmR0EnterCpu(PVMCPUCC pVCpu);
1415
1416# ifdef VBOX_STRICT
1417# define HM_DUMP_REG_FLAGS_GPRS RT_BIT(0)
1418# define HM_DUMP_REG_FLAGS_FPU RT_BIT(1)
1419# define HM_DUMP_REG_FLAGS_MSRS RT_BIT(2)
1420# define HM_DUMP_REG_FLAGS_ALL (HM_DUMP_REG_FLAGS_GPRS | HM_DUMP_REG_FLAGS_FPU | HM_DUMP_REG_FLAGS_MSRS)
1421
1422VMMR0_INT_DECL(void) hmR0DumpRegs(PVMCPUCC pVCpu, uint32_t fFlags);
1423VMMR0_INT_DECL(void) hmR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg);
1424# endif
1425
1426DECLASM(void) hmR0MdsClear(void);
1427#endif /* IN_RING0 */
1428
1429
1430/** @addtogroup grp_hm_int_svm SVM Internal
1431 * @{ */
1432VMM_INT_DECL(int) hmEmulateSvmMovTpr(PVMCC pVM, PVMCPUCC pVCpu);
1433
1434/**
1435 * Prepares for and executes VMRUN (64-bit register context).
1436 *
1437 * @returns VBox status code (no informational stuff).
1438 * @param pVM The cross context VM structure. (Not used.)
1439 * @param pVCpu The cross context virtual CPU structure.
1440 * @param HCPhyspVMCB Physical address of the VMCB.
1441 *
1442 * @remarks With spectre mitigations and the usual need for speed (/ micro
1443 * optimizations), we have a bunch of variations of this code depending
1444 * on a few precoditions. In release builds, the code is entirely
1445 * without conditionals. Debug builds have a couple of assertions that
1446 * shouldn't ever be triggered.
1447 *
1448 * @{
1449 */
1450DECLASM(int) hmR0SvmVmRun_SansXcr0_SansIbpbEntry_SansIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1451DECLASM(int) hmR0SvmVmRun_WithXcr0_SansIbpbEntry_SansIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1452DECLASM(int) hmR0SvmVmRun_SansXcr0_WithIbpbEntry_SansIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1453DECLASM(int) hmR0SvmVmRun_WithXcr0_WithIbpbEntry_SansIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1454DECLASM(int) hmR0SvmVmRun_SansXcr0_SansIbpbEntry_WithIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1455DECLASM(int) hmR0SvmVmRun_WithXcr0_SansIbpbEntry_WithIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1456DECLASM(int) hmR0SvmVmRun_SansXcr0_WithIbpbEntry_WithIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1457DECLASM(int) hmR0SvmVmRun_WithXcr0_WithIbpbEntry_WithIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1458/** @} */
1459
1460/** @} */
1461
1462
1463/** @addtogroup grp_hm_int_vmx VMX Internal
1464 * @{ */
1465VMM_INT_DECL(PVMXVMCSINFOSHARED) hmGetVmxActiveVmcsInfoShared(PVMCPUCC pVCpu);
1466
1467/**
1468 * Used on platforms with poor inline assembly support to retrieve all the
1469 * info from the CPU and put it in the @a pRestoreHost structure.
1470 */
1471DECLASM(void) hmR0VmxExportHostSegmentRegsAsmHlp(PVMXRESTOREHOST pRestoreHost, bool fHaveFsGsBase);
1472
1473/**
1474 * Restores some host-state fields that need not be done on every VM-exit.
1475 *
1476 * @returns VBox status code.
1477 * @param fRestoreHostFlags Flags of which host registers needs to be
1478 * restored.
1479 * @param pRestoreHost Pointer to the host-restore structure.
1480 */
1481DECLASM(int) VMXRestoreHostState(uint32_t fRestoreHostFlags, PVMXRESTOREHOST pRestoreHost);
1482
1483/**
1484 * VMX StartVM functions.
1485 *
1486 * @returns VBox status code (no informational stuff).
1487 * @param pVM Pointer to the cross context VM structure.
1488 * @param pVCpu Pointer to the cross context per-CPU structure.
1489 * @param fResume Whether to use VMRESUME (true) or VMLAUNCH (false).
1490 *
1491 * @remarks With spectre mitigations and the usual need for speed (/ micro
1492 * optimizations), we have a bunch of variations of this code depending
1493 * on a few precoditions. In release builds, the code is entirely
1494 * without conditionals. Debug builds have a couple of assertions that
1495 * shouldn't ever be triggered.
1496 *
1497 * @{
1498 */
1499DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_SansL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1500DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_SansL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1501DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_SansL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1502DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_SansL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1503DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_WithL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1504DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_WithL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1505DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_WithL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1506DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_WithL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1507DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_SansL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1508DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_SansL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1509DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_SansL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1510DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_SansL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1511DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_WithL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1512DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_WithL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1513DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_WithL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1514DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_WithL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1515DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_SansL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1516DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_SansL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1517DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_SansL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1518DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_SansL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1519DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_WithL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1520DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_WithL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1521DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_WithL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1522DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_WithL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1523DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_SansL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1524DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_SansL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1525DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_SansL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1526DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_SansL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1527DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_WithL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1528DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_WithL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1529DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_WithL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1530DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_WithL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1531/** @} */
1532
1533/** @} */
1534
1535/** @} */
1536
1537RT_C_DECLS_END
1538
1539#endif /* !VMM_INCLUDED_SRC_include_HMInternal_h */
1540
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette