VirtualBox

source: vbox/trunk/src/VBox/VMM/include/HMInternal.h@ 87519

Last change on this file since 87519 was 87519, checked in by vboxsync, 4 years ago

VMM/HM: Make a R0 copy of HM::cMaxResumeLoopsCfg and do proper validation. bugref:9217
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File size: 68.9 KB
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1/* $Id: HMInternal.h 87519 2021-02-01 21:17:51Z vboxsync $ */
2/** @file
3 * HM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef VMM_INCLUDED_SRC_include_HMInternal_h
19#define VMM_INCLUDED_SRC_include_HMInternal_h
20#ifndef RT_WITHOUT_PRAGMA_ONCE
21# pragma once
22#endif
23
24#include <VBox/cdefs.h>
25#include <VBox/types.h>
26#include <VBox/vmm/stam.h>
27#include <VBox/dis.h>
28#include <VBox/vmm/hm.h>
29#include <VBox/vmm/hm_vmx.h>
30#include <VBox/vmm/hm_svm.h>
31#include <VBox/vmm/pgm.h>
32#include <VBox/vmm/cpum.h>
33#include <VBox/vmm/trpm.h>
34#include <iprt/memobj.h>
35#include <iprt/cpuset.h>
36#include <iprt/mp.h>
37#include <iprt/avl.h>
38#include <iprt/string.h>
39
40#if HC_ARCH_BITS == 32
41# error "32-bit hosts are no longer supported. Go back to 6.0 or earlier!"
42#endif
43
44/** @def HM_PROFILE_EXIT_DISPATCH
45 * Enables profiling of the VM exit handler dispatching. */
46#if 0 || defined(DOXYGEN_RUNNING)
47# define HM_PROFILE_EXIT_DISPATCH
48#endif
49
50RT_C_DECLS_BEGIN
51
52
53/** @defgroup grp_hm_int Internal
54 * @ingroup grp_hm
55 * @internal
56 * @{
57 */
58
59/** @name HM_CHANGED_XXX
60 * HM CPU-context changed flags.
61 *
62 * These flags are used to keep track of which registers and state has been
63 * modified since they were imported back into the guest-CPU context.
64 *
65 * @{
66 */
67#define HM_CHANGED_HOST_CONTEXT UINT64_C(0x0000000000000001)
68#define HM_CHANGED_GUEST_RIP UINT64_C(0x0000000000000004)
69#define HM_CHANGED_GUEST_RFLAGS UINT64_C(0x0000000000000008)
70
71#define HM_CHANGED_GUEST_RAX UINT64_C(0x0000000000000010)
72#define HM_CHANGED_GUEST_RCX UINT64_C(0x0000000000000020)
73#define HM_CHANGED_GUEST_RDX UINT64_C(0x0000000000000040)
74#define HM_CHANGED_GUEST_RBX UINT64_C(0x0000000000000080)
75#define HM_CHANGED_GUEST_RSP UINT64_C(0x0000000000000100)
76#define HM_CHANGED_GUEST_RBP UINT64_C(0x0000000000000200)
77#define HM_CHANGED_GUEST_RSI UINT64_C(0x0000000000000400)
78#define HM_CHANGED_GUEST_RDI UINT64_C(0x0000000000000800)
79#define HM_CHANGED_GUEST_R8_R15 UINT64_C(0x0000000000001000)
80#define HM_CHANGED_GUEST_GPRS_MASK UINT64_C(0x0000000000001ff0)
81
82#define HM_CHANGED_GUEST_ES UINT64_C(0x0000000000002000)
83#define HM_CHANGED_GUEST_CS UINT64_C(0x0000000000004000)
84#define HM_CHANGED_GUEST_SS UINT64_C(0x0000000000008000)
85#define HM_CHANGED_GUEST_DS UINT64_C(0x0000000000010000)
86#define HM_CHANGED_GUEST_FS UINT64_C(0x0000000000020000)
87#define HM_CHANGED_GUEST_GS UINT64_C(0x0000000000040000)
88#define HM_CHANGED_GUEST_SREG_MASK UINT64_C(0x000000000007e000)
89
90#define HM_CHANGED_GUEST_GDTR UINT64_C(0x0000000000080000)
91#define HM_CHANGED_GUEST_IDTR UINT64_C(0x0000000000100000)
92#define HM_CHANGED_GUEST_LDTR UINT64_C(0x0000000000200000)
93#define HM_CHANGED_GUEST_TR UINT64_C(0x0000000000400000)
94#define HM_CHANGED_GUEST_TABLE_MASK UINT64_C(0x0000000000780000)
95
96#define HM_CHANGED_GUEST_CR0 UINT64_C(0x0000000000800000)
97#define HM_CHANGED_GUEST_CR2 UINT64_C(0x0000000001000000)
98#define HM_CHANGED_GUEST_CR3 UINT64_C(0x0000000002000000)
99#define HM_CHANGED_GUEST_CR4 UINT64_C(0x0000000004000000)
100#define HM_CHANGED_GUEST_CR_MASK UINT64_C(0x0000000007800000)
101
102#define HM_CHANGED_GUEST_APIC_TPR UINT64_C(0x0000000008000000)
103#define HM_CHANGED_GUEST_EFER_MSR UINT64_C(0x0000000010000000)
104
105#define HM_CHANGED_GUEST_DR0_DR3 UINT64_C(0x0000000020000000)
106#define HM_CHANGED_GUEST_DR6 UINT64_C(0x0000000040000000)
107#define HM_CHANGED_GUEST_DR7 UINT64_C(0x0000000080000000)
108#define HM_CHANGED_GUEST_DR_MASK UINT64_C(0x00000000e0000000)
109
110#define HM_CHANGED_GUEST_X87 UINT64_C(0x0000000100000000)
111#define HM_CHANGED_GUEST_SSE_AVX UINT64_C(0x0000000200000000)
112#define HM_CHANGED_GUEST_OTHER_XSAVE UINT64_C(0x0000000400000000)
113#define HM_CHANGED_GUEST_XCRx UINT64_C(0x0000000800000000)
114
115#define HM_CHANGED_GUEST_KERNEL_GS_BASE UINT64_C(0x0000001000000000)
116#define HM_CHANGED_GUEST_SYSCALL_MSRS UINT64_C(0x0000002000000000)
117#define HM_CHANGED_GUEST_SYSENTER_CS_MSR UINT64_C(0x0000004000000000)
118#define HM_CHANGED_GUEST_SYSENTER_EIP_MSR UINT64_C(0x0000008000000000)
119#define HM_CHANGED_GUEST_SYSENTER_ESP_MSR UINT64_C(0x0000010000000000)
120#define HM_CHANGED_GUEST_SYSENTER_MSR_MASK UINT64_C(0x000001c000000000)
121#define HM_CHANGED_GUEST_TSC_AUX UINT64_C(0x0000020000000000)
122#define HM_CHANGED_GUEST_OTHER_MSRS UINT64_C(0x0000040000000000)
123#define HM_CHANGED_GUEST_ALL_MSRS ( HM_CHANGED_GUEST_EFER \
124 | HM_CHANGED_GUEST_KERNEL_GS_BASE \
125 | HM_CHANGED_GUEST_SYSCALL_MSRS \
126 | HM_CHANGED_GUEST_SYSENTER_MSR_MASK \
127 | HM_CHANGED_GUEST_TSC_AUX \
128 | HM_CHANGED_GUEST_OTHER_MSRS)
129
130#define HM_CHANGED_GUEST_HWVIRT UINT64_C(0x0000080000000000)
131#define HM_CHANGED_GUEST_MASK UINT64_C(0x00000ffffffffffc)
132
133#define HM_CHANGED_KEEPER_STATE_MASK UINT64_C(0xffff000000000000)
134
135#define HM_CHANGED_VMX_XCPT_INTERCEPTS UINT64_C(0x0001000000000000)
136#define HM_CHANGED_VMX_GUEST_AUTO_MSRS UINT64_C(0x0002000000000000)
137#define HM_CHANGED_VMX_GUEST_LAZY_MSRS UINT64_C(0x0004000000000000)
138#define HM_CHANGED_VMX_ENTRY_EXIT_CTLS UINT64_C(0x0008000000000000)
139#define HM_CHANGED_VMX_MASK UINT64_C(0x000f000000000000)
140#define HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE ( HM_CHANGED_GUEST_DR_MASK \
141 | HM_CHANGED_VMX_GUEST_LAZY_MSRS)
142
143#define HM_CHANGED_SVM_XCPT_INTERCEPTS UINT64_C(0x0001000000000000)
144#define HM_CHANGED_SVM_MASK UINT64_C(0x0001000000000000)
145#define HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE HM_CHANGED_GUEST_DR_MASK
146
147#define HM_CHANGED_ALL_GUEST ( HM_CHANGED_GUEST_MASK \
148 | HM_CHANGED_KEEPER_STATE_MASK)
149
150/** Mask of what state might have changed when IEM raised an exception.
151 * This is a based on IEM_CPUMCTX_EXTRN_XCPT_MASK. */
152#define HM_CHANGED_RAISED_XCPT_MASK ( HM_CHANGED_GUEST_GPRS_MASK \
153 | HM_CHANGED_GUEST_RIP \
154 | HM_CHANGED_GUEST_RFLAGS \
155 | HM_CHANGED_GUEST_SS \
156 | HM_CHANGED_GUEST_CS \
157 | HM_CHANGED_GUEST_CR0 \
158 | HM_CHANGED_GUEST_CR3 \
159 | HM_CHANGED_GUEST_CR4 \
160 | HM_CHANGED_GUEST_APIC_TPR \
161 | HM_CHANGED_GUEST_EFER_MSR \
162 | HM_CHANGED_GUEST_DR7 \
163 | HM_CHANGED_GUEST_CR2 \
164 | HM_CHANGED_GUEST_SREG_MASK \
165 | HM_CHANGED_GUEST_TABLE_MASK)
166
167#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
168/** Mask of what state might have changed when \#VMEXIT is emulated. */
169# define HM_CHANGED_SVM_VMEXIT_MASK ( HM_CHANGED_GUEST_RSP \
170 | HM_CHANGED_GUEST_RAX \
171 | HM_CHANGED_GUEST_RIP \
172 | HM_CHANGED_GUEST_RFLAGS \
173 | HM_CHANGED_GUEST_CS \
174 | HM_CHANGED_GUEST_SS \
175 | HM_CHANGED_GUEST_DS \
176 | HM_CHANGED_GUEST_ES \
177 | HM_CHANGED_GUEST_GDTR \
178 | HM_CHANGED_GUEST_IDTR \
179 | HM_CHANGED_GUEST_CR_MASK \
180 | HM_CHANGED_GUEST_EFER_MSR \
181 | HM_CHANGED_GUEST_DR6 \
182 | HM_CHANGED_GUEST_DR7 \
183 | HM_CHANGED_GUEST_OTHER_MSRS \
184 | HM_CHANGED_GUEST_HWVIRT \
185 | HM_CHANGED_SVM_MASK \
186 | HM_CHANGED_GUEST_APIC_TPR)
187
188/** Mask of what state might have changed when VMRUN is emulated. */
189# define HM_CHANGED_SVM_VMRUN_MASK HM_CHANGED_SVM_VMEXIT_MASK
190#endif
191#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
192/** Mask of what state might have changed when VM-exit is emulated.
193 *
194 * This is currently unused, but keeping it here in case we can get away a bit more
195 * fine-grained state handling.
196 *
197 * @note Update IEM_CPUMCTX_EXTRN_VMX_VMEXIT_MASK when this changes. */
198# define HM_CHANGED_VMX_VMEXIT_MASK ( HM_CHANGED_GUEST_CR0 | HM_CHANGED_GUEST_CR3 | HM_CHANGED_GUEST_CR4 \
199 | HM_CHANGED_GUEST_DR7 | HM_CHANGED_GUEST_DR6 \
200 | HM_CHANGED_GUEST_EFER_MSR \
201 | HM_CHANGED_GUEST_SYSENTER_MSR_MASK \
202 | HM_CHANGED_GUEST_OTHER_MSRS /* for PAT MSR */ \
203 | HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RSP | HM_CHANGED_GUEST_RFLAGS \
204 | HM_CHANGED_GUEST_SREG_MASK \
205 | HM_CHANGED_GUEST_TR \
206 | HM_CHANGED_GUEST_LDTR | HM_CHANGED_GUEST_GDTR | HM_CHANGED_GUEST_IDTR \
207 | HM_CHANGED_GUEST_HWVIRT )
208#endif
209/** @} */
210
211/** Maximum number of exit reason statistics counters. */
212#define MAX_EXITREASON_STAT 0x100
213#define MASK_EXITREASON_STAT 0xff
214#define MASK_INJECT_IRQ_STAT 0xff
215
216/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
217#define HM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
218/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
219#define HM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2 * PAGE_SIZE + 1)
220/** Total guest mapped memory needed. */
221#define HM_VTX_TOTAL_DEVHEAP_MEM (HM_EPT_IDENTITY_PG_TABLE_SIZE + HM_VTX_TSS_SIZE)
222
223
224/** @name Macros for enabling and disabling preemption.
225 * These are really just for hiding the RTTHREADPREEMPTSTATE and asserting that
226 * preemption has already been disabled when there is no context hook.
227 * @{ */
228#ifdef VBOX_STRICT
229# define HM_DISABLE_PREEMPT(a_pVCpu) \
230 RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
231 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD) || VMMR0ThreadCtxHookIsEnabled((a_pVCpu))); \
232 RTThreadPreemptDisable(&PreemptStateInternal)
233#else
234# define HM_DISABLE_PREEMPT(a_pVCpu) \
235 RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
236 RTThreadPreemptDisable(&PreemptStateInternal)
237#endif /* VBOX_STRICT */
238#define HM_RESTORE_PREEMPT() do { RTThreadPreemptRestore(&PreemptStateInternal); } while(0)
239/** @} */
240
241
242/** @name HM saved state versions.
243 * @{
244 */
245#define HM_SAVED_STATE_VERSION HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT
246#define HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT 6
247#define HM_SAVED_STATE_VERSION_TPR_PATCHING 5
248#define HM_SAVED_STATE_VERSION_NO_TPR_PATCHING 4
249#define HM_SAVED_STATE_VERSION_2_0_X 3
250/** @} */
251
252
253/**
254 * HM physical (host) CPU information.
255 */
256typedef struct HMPHYSCPU
257{
258 /** The CPU ID. */
259 RTCPUID idCpu;
260 /** The VM_HSAVE_AREA (AMD-V) / VMXON region (Intel) memory backing. */
261 RTR0MEMOBJ hMemObj;
262 /** The physical address of the first page in hMemObj (it's a
263 * physcially contigous allocation if it spans multiple pages). */
264 RTHCPHYS HCPhysMemObj;
265 /** The address of the memory (for pfnEnable). */
266 void *pvMemObj;
267 /** Current ASID (AMD-V) / VPID (Intel). */
268 uint32_t uCurrentAsid;
269 /** TLB flush count. */
270 uint32_t cTlbFlushes;
271 /** Whether to flush each new ASID/VPID before use. */
272 bool fFlushAsidBeforeUse;
273 /** Configured for VT-x or AMD-V. */
274 bool fConfigured;
275 /** Set if the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active. */
276 bool fIgnoreAMDVInUseError;
277 /** Whether CR4.VMXE was already enabled prior to us enabling it. */
278 bool fVmxeAlreadyEnabled;
279 /** In use by our code. (for power suspend) */
280 bool volatile fInUse;
281#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
282 /** Nested-guest union (put data common to SVM/VMX outside the union). */
283 union
284 {
285 /** Nested-guest SVM data. */
286 struct
287 {
288 /** The active nested-guest MSR permission bitmap memory backing. */
289 RTR0MEMOBJ hNstGstMsrpm;
290 /** The physical address of the first page in hNstGstMsrpm (physcially
291 * contiguous allocation). */
292 RTHCPHYS HCPhysNstGstMsrpm;
293 /** The address of the active nested-guest MSRPM. */
294 void *pvNstGstMsrpm;
295 } svm;
296 /** @todo Nested-VMX. */
297 } n;
298#endif
299} HMPHYSCPU;
300/** Pointer to HMPHYSCPU struct. */
301typedef HMPHYSCPU *PHMPHYSCPU;
302/** Pointer to a const HMPHYSCPU struct. */
303typedef const HMPHYSCPU *PCHMPHYSCPU;
304
305/**
306 * TPR-instruction type.
307 */
308typedef enum
309{
310 HMTPRINSTR_INVALID,
311 HMTPRINSTR_READ,
312 HMTPRINSTR_READ_SHR4,
313 HMTPRINSTR_WRITE_REG,
314 HMTPRINSTR_WRITE_IMM,
315 HMTPRINSTR_JUMP_REPLACEMENT,
316 /** The usual 32-bit paranoia. */
317 HMTPRINSTR_32BIT_HACK = 0x7fffffff
318} HMTPRINSTR;
319
320/**
321 * TPR patch information.
322 */
323typedef struct
324{
325 /** The key is the address of patched instruction. (32 bits GC ptr) */
326 AVLOU32NODECORE Core;
327 /** Original opcode. */
328 uint8_t aOpcode[16];
329 /** Instruction size. */
330 uint32_t cbOp;
331 /** Replacement opcode. */
332 uint8_t aNewOpcode[16];
333 /** Replacement instruction size. */
334 uint32_t cbNewOp;
335 /** Instruction type. */
336 HMTPRINSTR enmType;
337 /** Source operand. */
338 uint32_t uSrcOperand;
339 /** Destination operand. */
340 uint32_t uDstOperand;
341 /** Number of times the instruction caused a fault. */
342 uint32_t cFaults;
343 /** Patch address of the jump replacement. */
344 RTGCPTR32 pJumpTarget;
345} HMTPRPATCH;
346/** Pointer to HMTPRPATCH. */
347typedef HMTPRPATCH *PHMTPRPATCH;
348/** Pointer to a const HMTPRPATCH. */
349typedef const HMTPRPATCH *PCHMTPRPATCH;
350
351
352/**
353 * Makes a HMEXITSTAT::uKey value from a program counter and an exit code.
354 *
355 * @returns 64-bit key
356 * @param a_uPC The RIP + CS.BASE value of the exit.
357 * @param a_uExit The exit code.
358 * @todo Add CPL?
359 */
360#define HMEXITSTAT_MAKE_KEY(a_uPC, a_uExit) (((a_uPC) & UINT64_C(0x0000ffffffffffff)) | (uint64_t)(a_uExit) << 48)
361
362typedef struct HMEXITINFO
363{
364 /** See HMEXITSTAT_MAKE_KEY(). */
365 uint64_t uKey;
366 /** Number of recent hits (depreciates with time). */
367 uint32_t volatile cHits;
368 /** The age + lock. */
369 uint16_t volatile uAge;
370 /** Action or action table index. */
371 uint16_t iAction;
372} HMEXITINFO;
373AssertCompileSize(HMEXITINFO, 16); /* Lots of these guys, so don't add any unnecessary stuff! */
374
375typedef struct HMEXITHISTORY
376{
377 /** The exit timestamp. */
378 uint64_t uTscExit;
379 /** The index of the corresponding HMEXITINFO entry.
380 * UINT32_MAX if none (too many collisions, race, whatever). */
381 uint32_t iExitInfo;
382 /** Figure out later, needed for padding now. */
383 uint32_t uSomeClueOrSomething;
384} HMEXITHISTORY;
385
386/**
387 * Switcher function, HC to the special 64-bit RC.
388 *
389 * @param pVM The cross context VM structure.
390 * @param offCpumVCpu Offset from pVM->cpum to pVM->aCpus[idCpu].cpum.
391 * @returns Return code indicating the action to take.
392 */
393typedef DECLCALLBACKTYPE(int, FNHMSWITCHERHC,(PVM pVM, uint32_t offCpumVCpu));
394/** Pointer to switcher function. */
395typedef FNHMSWITCHERHC *PFNHMSWITCHERHC;
396
397
398/**
399 * HM event.
400 *
401 * VT-x and AMD-V common event injection structure.
402 */
403typedef struct HMEVENT
404{
405 /** Whether the event is pending. */
406 uint32_t fPending;
407 /** The error-code associated with the event. */
408 uint32_t u32ErrCode;
409 /** The length of the instruction in bytes (only relevant for software
410 * interrupts or software exceptions). */
411 uint32_t cbInstr;
412 /** Alignment. */
413 uint32_t u32Padding;
414 /** The encoded event (VM-entry interruption-information for VT-x or EVENTINJ
415 * for SVM). */
416 uint64_t u64IntInfo;
417 /** Guest virtual address if this is a page-fault event. */
418 RTGCUINTPTR GCPtrFaultAddress;
419} HMEVENT;
420/** Pointer to a HMEVENT struct. */
421typedef HMEVENT *PHMEVENT;
422/** Pointer to a const HMEVENT struct. */
423typedef const HMEVENT *PCHMEVENT;
424AssertCompileSizeAlignment(HMEVENT, 8);
425
426/**
427 * HM VM Instance data.
428 * Changes to this must checked against the padding of the hm union in VM!
429 */
430typedef struct HM
431{
432 /** Set if nested paging is enabled.
433 * Config value that is copied to HMR0PERVM::fNestedPaging on setup. */
434 bool fNestedPagingCfg;
435 /** Set when we've finalized the VMX / SVM initialization in ring-3
436 * (hmR3InitFinalizeR0Intel / hmR3InitFinalizeR0Amd). */
437 bool fInitialized;
438 /** Set if large pages are enabled (requires nested paging).
439 * Config only, passed on the PGM where it really belongs.
440 * @todo move to PGM */
441 bool fLargePages;
442 /** Set if we can support 64-bit guests or not.
443 * Config value that is copied to HMR0PERVM::fAllow64BitGuests on setup. */
444 bool fAllow64BitGuestsCfg;
445 /** Set when we initialize VT-x or AMD-V once for all CPUs. */
446 bool fGlobalInit;
447 /** Set when TPR patching is allowed. */
448 bool fTprPatchingAllowed;
449 /** Set when TPR patching is active. */
450 bool fTPRPatchingActive;
451 /** Set when the debug facility has breakpoints/events enabled that requires
452 * us to use the debug execution loop in ring-0. */
453 bool fUseDebugLoop;
454 /** Set if hardware APIC virtualization is enabled.
455 * @todo Not really used by HM, move to APIC where it's actually used. */
456 bool fVirtApicRegs;
457 /** Set if posted interrupt processing is enabled.
458 * @todo Not really used by HM, move to APIC where it's actually used. */
459 bool fPostedIntrs;
460 /** Set if indirect branch prediction barrier on VM exit.
461 * @todo 9217: copy to ring-0 and validate capability */
462 bool fIbpbOnVmExit;
463 /** Set if indirect branch prediction barrier on VM entry.
464 * @todo 9217: copy to ring-0 and validate capability */
465 bool fIbpbOnVmEntry;
466 /** Set if level 1 data cache should be flushed on VM entry.
467 * @todo 9217: copy to ring-0 and validate capability */
468 bool fL1dFlushOnVmEntry;
469 /** Set if level 1 data cache should be flushed on EMT scheduling.
470 * @todo 9217: copy to ring-0 and validate capability */
471 bool fL1dFlushOnSched;
472 /** Set if host manages speculation control settings.
473 * @todo doesn't do anything ... */
474 bool fSpecCtrlByHost;
475 /** Set if MDS related buffers should be cleared on VM entry. */
476 bool fMdsClearOnVmEntry;
477 /** Set if MDS related buffers should be cleared on EMT scheduling. */
478 bool fMdsClearOnSched;
479 /** Alignment padding. */
480 bool afPaddingMinus1[3];
481
482 /** The maximum number of resumes loops allowed in ring-0 (safety precaution).
483 * This number is set much higher when RTThreadPreemptIsPending is reliable. */
484 uint32_t cMaxResumeLoopsCfg;
485
486 /** Maximum ASID allowed. */
487 uint32_t uMaxAsid;
488
489 /** Host kernel flags that HM might need to know (SUPKERNELFEATURES_XXX). */
490 uint32_t fHostKernelFeatures;
491
492 struct
493 {
494 /** Set by the ring-0 side of HM to indicate VMX is supported by the
495 * CPU. */
496 bool fSupported;
497 /** Set when we've enabled VMX. */
498 bool fEnabled;
499 /** Set if VPID is supported. */
500 bool fVpid;
501 /** Set if VT-x VPID is allowed. */
502 bool fAllowVpid;
503 /** Set if unrestricted guest execution is in use (real and protected mode
504 * without paging). */
505 bool fUnrestrictedGuest;
506 /** Set if the preemption timer is in use or not. */
507 bool fUsePreemptTimer;
508 /** The shift mask employed by the VMX-Preemption timer. */
509 uint8_t cPreemptTimerShift;
510 /** Padding. */
511 bool afPadding0;
512
513 /** Virtual address of the APIC-access page. */
514 R0PTRTYPE(uint8_t *) pbApicAccess;
515 /** Pointer to the VMREAD bitmap. */
516 R0PTRTYPE(void *) pvVmreadBitmap;
517 /** Pointer to the VMWRITE bitmap. */
518 R0PTRTYPE(void *) pvVmwriteBitmap;
519
520 /** Pointer to the shadow VMCS read-only fields array. */
521 R0PTRTYPE(uint32_t *) paShadowVmcsRoFields;
522 /** Pointer to the shadow VMCS read/write fields array. */
523 R0PTRTYPE(uint32_t *) paShadowVmcsFields;
524 /** Number of elements in the shadow VMCS read-only fields array. */
525 uint32_t cShadowVmcsRoFields;
526 /** Number of elements in the shadow VMCS read-write fields array. */
527 uint32_t cShadowVmcsFields;
528
529 /** Tagged-TLB flush type. */
530 VMXTLBFLUSHTYPE enmTlbFlushType;
531 /** Flush type to use for INVEPT. */
532 VMXTLBFLUSHEPT enmTlbFlushEpt;
533 /** Flush type to use for INVVPID. */
534 VMXTLBFLUSHVPID enmTlbFlushVpid;
535
536 /** Pause-loop exiting (PLE) gap in ticks. */
537 uint32_t cPleGapTicks;
538 /** Pause-loop exiting (PLE) window in ticks. */
539 uint32_t cPleWindowTicks;
540 uint32_t u32Alignment0;
541
542 /** Host CR4 value (set by ring-0 VMX init) */
543 uint64_t u64HostCr4;
544 /** Host SMM monitor control (set by ring-0 VMX init) */
545 uint64_t u64HostSmmMonitorCtl;
546 /** Host EFER value (set by ring-0 VMX init) */
547 uint64_t u64HostMsrEfer;
548 /** Whether the CPU supports VMCS fields for swapping EFER. */
549 bool fSupportsVmcsEfer;
550 /** Whether to use VMCS shadowing. */
551 bool fUseVmcsShadowing;
552 /** Set if Last Branch Record (LBR) is enabled. */
553 bool fLbr;
554 uint8_t u8Alignment2[5];
555
556 /** The first valid host LBR branch-from-IP stack range. */
557 uint32_t idLbrFromIpMsrFirst;
558 /** The last valid host LBR branch-from-IP stack range. */
559 uint32_t idLbrFromIpMsrLast;
560
561 /** The first valid host LBR branch-to-IP stack range. */
562 uint32_t idLbrToIpMsrFirst;
563 /** The last valid host LBR branch-to-IP stack range. */
564 uint32_t idLbrToIpMsrLast;
565
566 /** The host LBR TOS (top-of-stack) MSR id. */
567 uint32_t idLbrTosMsr;
568 /** Padding. */
569 uint32_t u32Alignment1;
570
571 /** VMX MSR values. */
572 VMXMSRS Msrs;
573
574 /** Host-physical address for a failing VMXON instruction. */
575 RTHCPHYS HCPhysVmxEnableError;
576 /** Host-physical address of the APIC-access page. */
577 RTHCPHYS HCPhysApicAccess;
578 /** Host-physical address of the VMREAD bitmap. */
579 RTHCPHYS HCPhysVmreadBitmap;
580 /** Host-physical address of the VMWRITE bitmap. */
581 RTHCPHYS HCPhysVmwriteBitmap;
582#ifdef VBOX_WITH_CRASHDUMP_MAGIC
583 /** Host-physical address of the crash-dump scratch area. */
584 RTHCPHYS HCPhysScratch;
585#endif
586
587#ifdef VBOX_WITH_CRASHDUMP_MAGIC
588 /** Pointer to the crash-dump scratch bitmap. */
589 R0PTRTYPE(uint8_t *) pbScratch;
590#endif
591 /** Virtual address of the TSS page used for real mode emulation. */
592 R3PTRTYPE(PVBOXTSS) pRealModeTSS;
593 /** Virtual address of the identity page table used for real mode and protected
594 * mode without paging emulation in EPT mode. */
595 R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
596
597 /** Ring-0 memory object for per-VM VMX structures. */
598 RTR0MEMOBJ hMemObj;
599 } vmx;
600
601 struct
602 {
603 /** Set by the ring-0 side of HM to indicate SVM is supported by the CPU. */
604 bool fSupported;
605 /** Set when we've enabled SVM. */
606 bool fEnabled;
607 /** Set when the hack to ignore VERR_SVM_IN_USE is active.
608 * @todo Safe? */
609 bool fIgnoreInUseError;
610 /** Whether to use virtualized VMSAVE/VMLOAD feature. */
611 bool fVirtVmsaveVmload;
612 /** Whether to use virtual GIF feature. */
613 bool fVGif;
614 /** Whether to use LBR virtualization feature. */
615 bool fLbrVirt;
616 uint8_t u8Alignment0[2];
617
618 /* HWCR MSR (for diagnostics) */
619 uint64_t u64MsrHwcr;
620
621 /** SVM revision. */
622 uint32_t u32Rev;
623 /** SVM feature bits from cpuid 0x8000000a, ring-3 copy. */
624 uint32_t fFeaturesForRing3;
625
626 /** Pause filter counter. */
627 uint16_t cPauseFilter;
628 /** Pause filter treshold in ticks. */
629 uint16_t cPauseFilterThresholdTicks;
630 uint32_t u32Alignment0;
631 } svm;
632
633 /** AVL tree with all patches (active or disabled) sorted by guest instruction address.
634 * @todo For @bugref{9217} this AVL tree must be eliminated and instead
635 * sort aPatches by address and do a safe binary search on it. */
636 AVLOU32TREE PatchTree;
637 uint32_t cPatches;
638 HMTPRPATCH aPatches[64];
639
640 /** Guest allocated memory for patching purposes. */
641 RTGCPTR pGuestPatchMem;
642 /** Current free pointer inside the patch block. */
643 RTGCPTR pFreeGuestPatchMem;
644 /** Size of the guest patch memory block. */
645 uint32_t cbGuestPatchMem;
646
647 /** Last recorded error code during HM ring-0 init. */
648 int32_t rcInit;
649
650 STAMCOUNTER StatTprPatchSuccess;
651 STAMCOUNTER StatTprPatchFailure;
652 STAMCOUNTER StatTprReplaceSuccessCr8;
653 STAMCOUNTER StatTprReplaceSuccessVmc;
654 STAMCOUNTER StatTprReplaceFailure;
655} HM;
656/** Pointer to HM VM instance data. */
657typedef HM *PHM;
658AssertCompileMemberAlignment(HM, StatTprPatchSuccess, 8);
659AssertCompileMemberAlignment(HM, vmx, 8);
660AssertCompileMemberAlignment(HM, svm, 8);
661
662
663/**
664 * Per-VM ring-0 instance data for HM.
665 */
666typedef struct HMR0PERVM
667{
668 /** Set if nested paging is enabled. */
669 bool fNestedPaging;
670 /** Set if we can support 64-bit guests or not. */
671 bool fAllow64BitGuests;
672
673 bool afAlignment0[2];
674
675 /** The maximum number of resumes loops allowed in ring-0 (safety precaution).
676 * This number is set much higher when RTThreadPreemptIsPending is reliable. */
677 uint32_t cMaxResumeLoops;
678
679 /** SVM specific data. */
680 struct HMR0SVMVM
681 {
682 /** Set if erratum 170 affects the AMD cpu. */
683 bool fAlwaysFlushTLB;
684 bool afAlignment0[3];
685 /** SVM feature bits from cpuid 0x8000000a, safe ring-0 copy. */
686 uint32_t fFeatures;
687 } svm;
688} HMR0PERVM;
689/** Pointer to HM's per-VM ring-0 instance data. */
690typedef HMR0PERVM *PHMR0PERVM;
691
692
693/** @addtogroup grp_hm_int_svm SVM Internal
694 * @{ */
695/** SVM VMRun function, see SVMR0VMRun(). */
696typedef DECLCALLBACKTYPE(int, FNHMSVMVMRUN,(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhysVMCB));
697/** Pointer to a SVM VMRun function. */
698typedef R0PTRTYPE(FNHMSVMVMRUN *) PFNHMSVMVMRUN;
699
700/**
701 * SVM nested-guest VMCB cache.
702 *
703 * Contains VMCB fields from the nested-guest VMCB before they're modified by
704 * SVM R0 code for hardware-assisted SVM execution of a nested-guest.
705 *
706 * A VMCB field needs to be cached when it needs to be modified for execution using
707 * hardware-assisted SVM and any of the following are true:
708 * - If the original field needs to be inspected during execution of the
709 * nested-guest or \#VMEXIT processing.
710 * - If the field is written back to memory on \#VMEXIT by the physical CPU.
711 *
712 * A VMCB field needs to be restored only when the field is written back to
713 * memory on \#VMEXIT by the physical CPU and thus would be visible to the
714 * guest.
715 *
716 * @remarks Please update hmR3InfoSvmNstGstVmcbCache() when changes are made to
717 * this structure.
718 */
719typedef struct SVMNESTEDVMCBCACHE
720{
721 /** Cache of CRX read intercepts. */
722 uint16_t u16InterceptRdCRx;
723 /** Cache of CRX write intercepts. */
724 uint16_t u16InterceptWrCRx;
725 /** Cache of DRX read intercepts. */
726 uint16_t u16InterceptRdDRx;
727 /** Cache of DRX write intercepts. */
728 uint16_t u16InterceptWrDRx;
729
730 /** Cache of the pause-filter threshold. */
731 uint16_t u16PauseFilterThreshold;
732 /** Cache of the pause-filter count. */
733 uint16_t u16PauseFilterCount;
734
735 /** Cache of exception intercepts. */
736 uint32_t u32InterceptXcpt;
737 /** Cache of control intercepts. */
738 uint64_t u64InterceptCtrl;
739
740 /** Cache of the TSC offset. */
741 uint64_t u64TSCOffset;
742
743 /** Cache of V_INTR_MASKING bit. */
744 bool fVIntrMasking;
745 /** Cache of the nested-paging bit. */
746 bool fNestedPaging;
747 /** Cache of the LBR virtualization bit. */
748 bool fLbrVirt;
749 /** Whether the VMCB is cached by HM. */
750 bool fCacheValid;
751 /** Alignment. */
752 bool afPadding0[4];
753} SVMNESTEDVMCBCACHE;
754/** Pointer to the SVMNESTEDVMCBCACHE structure. */
755typedef SVMNESTEDVMCBCACHE *PSVMNESTEDVMCBCACHE;
756/** Pointer to a const SVMNESTEDVMCBCACHE structure. */
757typedef const SVMNESTEDVMCBCACHE *PCSVMNESTEDVMCBCACHE;
758AssertCompileSizeAlignment(SVMNESTEDVMCBCACHE, 8);
759
760/** @} */
761
762
763/** @addtogroup grp_hm_int_vmx VMX Internal
764 * @{ */
765/**
766 * VMX VMCS information, shared.
767 *
768 * This structure provides information maintained for and during the executing of a
769 * guest (or nested-guest) VMCS (VM control structure) using hardware-assisted VMX.
770 *
771 * Note! The members here are ordered and aligned based on estimated frequency of
772 * usage and grouped to fit within a cache line in hot code paths. Even subtle
773 * changes here have a noticeable effect in the bootsector benchmarks. Modify with
774 * care.
775 */
776typedef struct VMXVMCSINFOSHARED
777{
778 /** @name Real-mode emulation state.
779 * @{ */
780 /** Set if guest was executing in real mode (extra checks). */
781 bool fWasInRealMode;
782 /** Padding. */
783 bool afPadding0[7];
784 struct
785 {
786 X86DESCATTR AttrCS;
787 X86DESCATTR AttrDS;
788 X86DESCATTR AttrES;
789 X86DESCATTR AttrFS;
790 X86DESCATTR AttrGS;
791 X86DESCATTR AttrSS;
792 X86EFLAGS Eflags;
793 bool fRealOnV86Active;
794 bool afPadding1[3];
795 } RealMode;
796 /** @} */
797
798 /** @name LBR MSR data.
799 * @{ */
800 /** List of LastBranch-From-IP MSRs. */
801 uint64_t au64LbrFromIpMsr[32];
802 /** List of LastBranch-To-IP MSRs. */
803 uint64_t au64LbrToIpMsr[32];
804 /** The MSR containing the index to the most recent branch record. */
805 uint64_t u64LbrTosMsr;
806 /** @} */
807} VMXVMCSINFOSHARED;
808/** Pointer to a VMXVMCSINFOSHARED struct. */
809typedef VMXVMCSINFOSHARED *PVMXVMCSINFOSHARED;
810/** Pointer to a const VMXVMCSINFOSHARED struct. */
811typedef const VMXVMCSINFOSHARED *PCVMXVMCSINFOSHARED;
812AssertCompileSizeAlignment(VMXVMCSINFOSHARED, 8);
813
814
815/**
816 * VMX VMCS information, ring-0 only.
817 *
818 * This structure provides information maintained for and during the executing of a
819 * guest (or nested-guest) VMCS (VM control structure) using hardware-assisted VMX.
820 *
821 * Note! The members here are ordered and aligned based on estimated frequency of
822 * usage and grouped to fit within a cache line in hot code paths. Even subtle
823 * changes here have a noticeable effect in the bootsector benchmarks. Modify with
824 * care.
825 */
826typedef struct VMXVMCSINFO
827{
828 /** Pointer to the bits we share with ring-3. */
829 R0PTRTYPE(PVMXVMCSINFOSHARED) pShared;
830
831 /** @name Auxiliary information.
832 * @{ */
833 /** Host-physical address of the EPTP. */
834 RTHCPHYS HCPhysEPTP;
835 /** The VMCS launch state, see VMX_V_VMCS_LAUNCH_STATE_XXX. */
836 uint32_t fVmcsState;
837 /** The VMCS launch state of the shadow VMCS, see VMX_V_VMCS_LAUNCH_STATE_XXX. */
838 uint32_t fShadowVmcsState;
839 /** The host CPU for which its state has been exported to this VMCS. */
840 RTCPUID idHostCpuState;
841 /** The host CPU on which we last executed this VMCS. */
842 RTCPUID idHostCpuExec;
843 /** Number of guest MSRs in the VM-entry MSR-load area. */
844 uint32_t cEntryMsrLoad;
845 /** Number of guest MSRs in the VM-exit MSR-store area. */
846 uint32_t cExitMsrStore;
847 /** Number of host MSRs in the VM-exit MSR-load area. */
848 uint32_t cExitMsrLoad;
849 /** @} */
850
851 /** @name Cache of execution related VMCS fields.
852 * @{ */
853 /** Pin-based VM-execution controls. */
854 uint32_t u32PinCtls;
855 /** Processor-based VM-execution controls. */
856 uint32_t u32ProcCtls;
857 /** Secondary processor-based VM-execution controls. */
858 uint32_t u32ProcCtls2;
859 /** VM-entry controls. */
860 uint32_t u32EntryCtls;
861 /** VM-exit controls. */
862 uint32_t u32ExitCtls;
863 /** Exception bitmap. */
864 uint32_t u32XcptBitmap;
865 /** Page-fault exception error-code mask. */
866 uint32_t u32XcptPFMask;
867 /** Page-fault exception error-code match. */
868 uint32_t u32XcptPFMatch;
869 /** Padding. */
870 uint32_t u32Alignment0;
871 /** TSC offset. */
872 uint64_t u64TscOffset;
873 /** VMCS link pointer. */
874 uint64_t u64VmcsLinkPtr;
875 /** CR0 guest/host mask. */
876 uint64_t u64Cr0Mask;
877 /** CR4 guest/host mask. */
878 uint64_t u64Cr4Mask;
879 /** Current VMX_VMCS_HOST_RIP value (only used in HMR0A.asm). */
880 uint64_t uHostRip;
881 /** Current VMX_VMCS_HOST_RSP value (only used in HMR0A.asm). */
882 uint64_t uHostRsp;
883 /** @} */
884
885 /** @name Host-virtual address of VMCS and related data structures.
886 * @{ */
887 /** The VMCS. */
888 R0PTRTYPE(void *) pvVmcs;
889 /** The shadow VMCS. */
890 R0PTRTYPE(void *) pvShadowVmcs;
891 /** The virtual-APIC page. */
892 R0PTRTYPE(uint8_t *) pbVirtApic;
893 /** The MSR bitmap. */
894 R0PTRTYPE(void *) pvMsrBitmap;
895 /** The VM-entry MSR-load area. */
896 R0PTRTYPE(void *) pvGuestMsrLoad;
897 /** The VM-exit MSR-store area. */
898 R0PTRTYPE(void *) pvGuestMsrStore;
899 /** The VM-exit MSR-load area. */
900 R0PTRTYPE(void *) pvHostMsrLoad;
901 /** @} */
902
903 /** @name Host-physical address of VMCS and related data structures.
904 * @{ */
905 /** The VMCS. */
906 RTHCPHYS HCPhysVmcs;
907 /** The shadow VMCS. */
908 RTHCPHYS HCPhysShadowVmcs;
909 /** The virtual APIC page. */
910 RTHCPHYS HCPhysVirtApic;
911 /** The MSR bitmap. */
912 RTHCPHYS HCPhysMsrBitmap;
913 /** The VM-entry MSR-load area. */
914 RTHCPHYS HCPhysGuestMsrLoad;
915 /** The VM-exit MSR-store area. */
916 RTHCPHYS HCPhysGuestMsrStore;
917 /** The VM-exit MSR-load area. */
918 RTHCPHYS HCPhysHostMsrLoad;
919 /** @} */
920
921 /** @name R0-memory objects address for VMCS and related data structures.
922 * @{ */
923 /** R0-memory object for VMCS and related data structures. */
924 RTR0MEMOBJ hMemObj;
925 /** @} */
926} VMXVMCSINFO;
927/** Pointer to a VMXVMCSINFOR0 struct. */
928typedef VMXVMCSINFO *PVMXVMCSINFO;
929/** Pointer to a const VMXVMCSINFO struct. */
930typedef const VMXVMCSINFO *PCVMXVMCSINFO;
931AssertCompileSizeAlignment(VMXVMCSINFO, 8);
932AssertCompileMemberAlignment(VMXVMCSINFO, u32PinCtls, 4);
933AssertCompileMemberAlignment(VMXVMCSINFO, u64VmcsLinkPtr, 8);
934AssertCompileMemberAlignment(VMXVMCSINFO, pvVmcs, 8);
935AssertCompileMemberAlignment(VMXVMCSINFO, pvShadowVmcs, 8);
936AssertCompileMemberAlignment(VMXVMCSINFO, pbVirtApic, 8);
937AssertCompileMemberAlignment(VMXVMCSINFO, pvMsrBitmap, 8);
938AssertCompileMemberAlignment(VMXVMCSINFO, pvGuestMsrLoad, 8);
939AssertCompileMemberAlignment(VMXVMCSINFO, pvGuestMsrStore, 8);
940AssertCompileMemberAlignment(VMXVMCSINFO, pvHostMsrLoad, 8);
941AssertCompileMemberAlignment(VMXVMCSINFO, HCPhysVmcs, 8);
942AssertCompileMemberAlignment(VMXVMCSINFO, hMemObj, 8);
943
944
945/** @name Host-state restoration flags.
946 * @note If you change these values don't forget to update the assembly
947 * defines as well!
948 * @{
949 */
950#define VMX_RESTORE_HOST_SEL_DS RT_BIT(0)
951#define VMX_RESTORE_HOST_SEL_ES RT_BIT(1)
952#define VMX_RESTORE_HOST_SEL_FS RT_BIT(2)
953#define VMX_RESTORE_HOST_SEL_GS RT_BIT(3)
954#define VMX_RESTORE_HOST_SEL_TR RT_BIT(4)
955#define VMX_RESTORE_HOST_GDTR RT_BIT(5)
956#define VMX_RESTORE_HOST_IDTR RT_BIT(6)
957#define VMX_RESTORE_HOST_GDT_READ_ONLY RT_BIT(7)
958#define VMX_RESTORE_HOST_GDT_NEED_WRITABLE RT_BIT(8)
959#define VMX_RESTORE_HOST_CAN_USE_WRFSBASE_AND_WRGSBASE RT_BIT(9)
960/**
961 * This _must_ be the top most bit, so that we can easily that that it and
962 * something else is set w/o having to do two checks like this:
963 * @code
964 * if ( (pVCpu->hm.s.vmx.fRestoreHostFlags & VMX_RESTORE_HOST_REQUIRED)
965 * && (pVCpu->hm.s.vmx.fRestoreHostFlags & ~VMX_RESTORE_HOST_REQUIRED))
966 * @endcode
967 * Instead we can then do:
968 * @code
969 * if (pVCpu->hm.s.vmx.fRestoreHostFlags > VMX_RESTORE_HOST_REQUIRED)
970 * @endcode
971 */
972#define VMX_RESTORE_HOST_REQUIRED RT_BIT(10)
973/** @} */
974
975/**
976 * Host-state restoration structure.
977 *
978 * This holds host-state fields that require manual restoration.
979 * Assembly version found in HMInternal.mac (should be automatically verified).
980 */
981typedef struct VMXRESTOREHOST
982{
983 RTSEL uHostSelDS; /**< 0x00 */
984 RTSEL uHostSelES; /**< 0x02 */
985 RTSEL uHostSelFS; /**< 0x04 */
986 X86XDTR64 HostGdtr; /**< 0x06 - should be aligned by its 64-bit member. */
987 RTSEL uHostSelGS; /**< 0x10 */
988 RTSEL uHostSelTR; /**< 0x12 */
989 RTSEL uHostSelSS; /**< 0x14 - not restored, just for fetching */
990 X86XDTR64 HostGdtrRw; /**< 0x16 - should be aligned by its 64-bit member. */
991 RTSEL uHostSelCS; /**< 0x20 - not restored, just for fetching */
992 uint8_t abPadding1[4]; /**< 0x22 */
993 X86XDTR64 HostIdtr; /**< 0x26 - should be aligned by its 64-bit member. */
994 uint64_t uHostFSBase; /**< 0x30 */
995 uint64_t uHostGSBase; /**< 0x38 */
996} VMXRESTOREHOST;
997/** Pointer to VMXRESTOREHOST. */
998typedef VMXRESTOREHOST *PVMXRESTOREHOST;
999AssertCompileSize(X86XDTR64, 10);
1000AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtr.uAddr, 0x08);
1001AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtrRw.uAddr, 0x18);
1002AssertCompileMemberOffset(VMXRESTOREHOST, HostIdtr.uAddr, 0x28);
1003AssertCompileMemberOffset(VMXRESTOREHOST, uHostFSBase, 0x30);
1004AssertCompileSize(VMXRESTOREHOST, 64);
1005AssertCompileSizeAlignment(VMXRESTOREHOST, 8);
1006
1007/**
1008 * VMX StartVM function.
1009 *
1010 * @returns VBox status code (no informational stuff).
1011 * @param pVmcsInfo Pointer to the VMCS info (for cached host RIP and RSP).
1012 * @param pVCpu Pointer to the cross context per-CPU structure.
1013 * @param fResume Whether to use VMRESUME (true) or VMLAUNCH (false).
1014 */
1015typedef DECLCALLBACKTYPE(int, FNHMVMXSTARTVM,(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume));
1016/** Pointer to a VMX StartVM function. */
1017typedef R0PTRTYPE(FNHMVMXSTARTVM *) PFNHMVMXSTARTVM;
1018/** @} */
1019
1020/**
1021 * HM VMCPU Instance data.
1022 *
1023 * Note! If you change members of this struct, make sure to check if the
1024 * assembly counterpart in HMInternal.mac needs to be updated as well.
1025 *
1026 * Note! The members here are ordered and aligned based on estimated frequency of
1027 * usage and grouped to fit within a cache line in hot code paths. Even subtle
1028 * changes here have a noticeable effect in the bootsector benchmarks. Modify with
1029 * care.
1030 */
1031typedef struct HMCPU
1032{
1033 /** Set when the TLB has been checked until we return from the world switch. */
1034 bool volatile fCheckedTLBFlush;
1035 /** Set when we're using VT-x or AMD-V at that moment.
1036 * @todo r=bird: Misleading description. For AMD-V this will be set the first
1037 * time HMCanExecuteGuest() is called and only cleared again by
1038 * HMR3ResetCpu(). For VT-x it will be set by HMCanExecuteGuest when we
1039 * can execute something in VT-x mode, and cleared if we cannot.
1040 *
1041 * The field is much more about recording the last HMCanExecuteGuest
1042 * return value than anything about any "moment". */
1043 bool fActive;
1044
1045 /** Whether we should use the debug loop because of single stepping or special
1046 * debug breakpoints / events are armed. */
1047 bool fUseDebugLoop;
1048
1049 /** Whether \#UD needs to be intercepted (required by certain GIM providers). */
1050 bool fGIMTrapXcptUD;
1051 /** Whether \#GP needs to be intercepted for mesa driver workaround. */
1052 bool fTrapXcptGpForLovelyMesaDrv;
1053 /** Whether we're executing a single instruction. */
1054 bool fSingleInstruction;
1055
1056 bool afAlignment0[2];
1057
1058 /** An additional error code used for some gurus. */
1059 uint32_t u32HMError;
1060 /** The last exit-to-ring-3 reason. */
1061 int32_t rcLastExitToR3;
1062 /** CPU-context changed flags (see HM_CHANGED_xxx). */
1063 uint64_t fCtxChanged;
1064
1065 /** VT-x data. */
1066 struct HMCPUVMX
1067 {
1068 /** @name Guest information.
1069 * @{ */
1070 /** Guest VMCS information shared with ring-3. */
1071 VMXVMCSINFOSHARED VmcsInfo;
1072 /** Nested-guest VMCS information shared with ring-3. */
1073 VMXVMCSINFOSHARED VmcsInfoNstGst;
1074 /** Whether the nested-guest VMCS was the last current VMCS (shadow copy for ring-3).
1075 * @see HMR0PERVCPU::vmx.fSwitchedToNstGstVmcs */
1076 bool fSwitchedToNstGstVmcsCopyForRing3;
1077 /** Whether the static guest VMCS controls has been merged with the
1078 * nested-guest VMCS controls. */
1079 bool fMergedNstGstCtls;
1080 /** Whether the nested-guest VMCS has been copied to the shadow VMCS. */
1081 bool fCopiedNstGstToShadowVmcs;
1082 /** Whether flushing the TLB is required due to switching to/from the
1083 * nested-guest. */
1084 bool fSwitchedNstGstFlushTlb;
1085 /** Alignment. */
1086 bool afAlignment0[4];
1087 /** Cached guest APIC-base MSR for identifying when to map the APIC-access page. */
1088 uint64_t u64GstMsrApicBase;
1089 /** @} */
1090
1091 /** @name Error reporting and diagnostics.
1092 * @{ */
1093 /** VT-x error-reporting (mainly for ring-3 propagation). */
1094 struct
1095 {
1096 RTCPUID idCurrentCpu;
1097 RTCPUID idEnteredCpu;
1098 RTHCPHYS HCPhysCurrentVmcs;
1099 uint32_t u32VmcsRev;
1100 uint32_t u32InstrError;
1101 uint32_t u32ExitReason;
1102 uint32_t u32GuestIntrState;
1103 } LastError;
1104 /** @} */
1105 } vmx;
1106
1107 /** SVM data. */
1108 struct HMCPUSVM
1109 {
1110 /** Whether to emulate long mode support for sysenter/sysexit like intel CPUs
1111 * does. This means intercepting \#UD to emulate the instructions in
1112 * long-mode and to intercept reads and writes to the SYSENTER MSRs in order to
1113 * preserve the upper 32 bits written to them (AMD will ignore and discard). */
1114 bool fEmulateLongModeSysEnterExit;
1115 uint8_t au8Alignment0[7];
1116
1117 /** Cache of the nested-guest's VMCB fields that we modify in order to run the
1118 * nested-guest using AMD-V. This will be restored on \#VMEXIT. */
1119 SVMNESTEDVMCBCACHE NstGstVmcbCache;
1120 } svm;
1121
1122 /** Event injection state. */
1123 HMEVENT Event;
1124
1125 /** Current shadow paging mode for updating CR4.
1126 * @todo move later (@bugref{9217}). */
1127 PGMMODE enmShadowMode;
1128 uint32_t u32TemporaryPadding;
1129
1130 /** The PAE PDPEs used with Nested Paging (only valid when
1131 * VMCPU_FF_HM_UPDATE_PAE_PDPES is set). */
1132 X86PDPE aPdpes[4];
1133
1134 /* These two comes because they are accessed from assembly and we don't
1135 want to detail all the stats in the assembly version of this structure. */
1136 STAMCOUNTER StatVmxWriteHostRip;
1137 STAMCOUNTER StatVmxWriteHostRsp;
1138 STAMCOUNTER StatVmxVmLaunch;
1139 STAMCOUNTER StatVmxVmResume;
1140
1141 STAMPROFILEADV StatEntry;
1142 STAMPROFILEADV StatPreExit;
1143 STAMPROFILEADV StatExitHandling;
1144 STAMPROFILEADV StatExitIO;
1145 STAMPROFILEADV StatExitMovCRx;
1146 STAMPROFILEADV StatExitXcptNmi;
1147 STAMPROFILEADV StatExitVmentry;
1148 STAMPROFILEADV StatImportGuestState;
1149 STAMPROFILEADV StatExportGuestState;
1150 STAMPROFILEADV StatLoadGuestFpuState;
1151 STAMPROFILEADV StatInGC;
1152 STAMPROFILEADV StatPoke;
1153 STAMPROFILEADV StatSpinPoke;
1154 STAMPROFILEADV StatSpinPokeFailed;
1155
1156 STAMCOUNTER StatInjectInterrupt;
1157 STAMCOUNTER StatInjectXcpt;
1158 STAMCOUNTER StatInjectReflect;
1159 STAMCOUNTER StatInjectConvertDF;
1160 STAMCOUNTER StatInjectInterpret;
1161 STAMCOUNTER StatInjectReflectNPF;
1162
1163 STAMCOUNTER StatExitAll;
1164 STAMCOUNTER StatNestedExitAll;
1165 STAMCOUNTER StatExitShadowNM;
1166 STAMCOUNTER StatExitGuestNM;
1167 STAMCOUNTER StatExitShadowPF; /**< Misleading, currently used for MMIO \#PFs as well. */
1168 STAMCOUNTER StatExitShadowPFEM;
1169 STAMCOUNTER StatExitGuestPF;
1170 STAMCOUNTER StatExitGuestUD;
1171 STAMCOUNTER StatExitGuestSS;
1172 STAMCOUNTER StatExitGuestNP;
1173 STAMCOUNTER StatExitGuestTS;
1174 STAMCOUNTER StatExitGuestOF;
1175 STAMCOUNTER StatExitGuestGP;
1176 STAMCOUNTER StatExitGuestDE;
1177 STAMCOUNTER StatExitGuestDF;
1178 STAMCOUNTER StatExitGuestBR;
1179 STAMCOUNTER StatExitGuestAC;
1180 STAMCOUNTER StatExitGuestDB;
1181 STAMCOUNTER StatExitGuestMF;
1182 STAMCOUNTER StatExitGuestBP;
1183 STAMCOUNTER StatExitGuestXF;
1184 STAMCOUNTER StatExitGuestXcpUnk;
1185 STAMCOUNTER StatExitDRxWrite;
1186 STAMCOUNTER StatExitDRxRead;
1187 STAMCOUNTER StatExitCR0Read;
1188 STAMCOUNTER StatExitCR2Read;
1189 STAMCOUNTER StatExitCR3Read;
1190 STAMCOUNTER StatExitCR4Read;
1191 STAMCOUNTER StatExitCR8Read;
1192 STAMCOUNTER StatExitCR0Write;
1193 STAMCOUNTER StatExitCR2Write;
1194 STAMCOUNTER StatExitCR3Write;
1195 STAMCOUNTER StatExitCR4Write;
1196 STAMCOUNTER StatExitCR8Write;
1197 STAMCOUNTER StatExitRdmsr;
1198 STAMCOUNTER StatExitWrmsr;
1199 STAMCOUNTER StatExitClts;
1200 STAMCOUNTER StatExitXdtrAccess;
1201 STAMCOUNTER StatExitLmsw;
1202 STAMCOUNTER StatExitIOWrite;
1203 STAMCOUNTER StatExitIORead;
1204 STAMCOUNTER StatExitIOStringWrite;
1205 STAMCOUNTER StatExitIOStringRead;
1206 STAMCOUNTER StatExitIntWindow;
1207 STAMCOUNTER StatExitExtInt;
1208 STAMCOUNTER StatExitHostNmiInGC;
1209 STAMCOUNTER StatExitHostNmiInGCIpi;
1210 STAMCOUNTER StatExitPreemptTimer;
1211 STAMCOUNTER StatExitTprBelowThreshold;
1212 STAMCOUNTER StatExitTaskSwitch;
1213 STAMCOUNTER StatExitApicAccess;
1214 STAMCOUNTER StatExitReasonNpf;
1215
1216 STAMCOUNTER StatNestedExitReasonNpf;
1217
1218 STAMCOUNTER StatFlushPage;
1219 STAMCOUNTER StatFlushPageManual;
1220 STAMCOUNTER StatFlushPhysPageManual;
1221 STAMCOUNTER StatFlushTlb;
1222 STAMCOUNTER StatFlushTlbNstGst;
1223 STAMCOUNTER StatFlushTlbManual;
1224 STAMCOUNTER StatFlushTlbWorldSwitch;
1225 STAMCOUNTER StatNoFlushTlbWorldSwitch;
1226 STAMCOUNTER StatFlushEntire;
1227 STAMCOUNTER StatFlushAsid;
1228 STAMCOUNTER StatFlushNestedPaging;
1229 STAMCOUNTER StatFlushTlbInvlpgVirt;
1230 STAMCOUNTER StatFlushTlbInvlpgPhys;
1231 STAMCOUNTER StatTlbShootdown;
1232 STAMCOUNTER StatTlbShootdownFlush;
1233
1234 STAMCOUNTER StatSwitchPendingHostIrq;
1235 STAMCOUNTER StatSwitchTprMaskedIrq;
1236 STAMCOUNTER StatSwitchGuestIrq;
1237 STAMCOUNTER StatSwitchHmToR3FF;
1238 STAMCOUNTER StatSwitchVmReq;
1239 STAMCOUNTER StatSwitchPgmPoolFlush;
1240 STAMCOUNTER StatSwitchDma;
1241 STAMCOUNTER StatSwitchExitToR3;
1242 STAMCOUNTER StatSwitchLongJmpToR3;
1243 STAMCOUNTER StatSwitchMaxResumeLoops;
1244 STAMCOUNTER StatSwitchHltToR3;
1245 STAMCOUNTER StatSwitchApicAccessToR3;
1246 STAMCOUNTER StatSwitchPreempt;
1247 STAMCOUNTER StatSwitchNstGstVmexit;
1248
1249 STAMCOUNTER StatTscParavirt;
1250 STAMCOUNTER StatTscOffset;
1251 STAMCOUNTER StatTscIntercept;
1252
1253 STAMCOUNTER StatDRxArmed;
1254 STAMCOUNTER StatDRxContextSwitch;
1255 STAMCOUNTER StatDRxIoCheck;
1256
1257 STAMCOUNTER StatExportMinimal;
1258 STAMCOUNTER StatExportFull;
1259 STAMCOUNTER StatLoadGuestFpu;
1260 STAMCOUNTER StatExportHostState;
1261
1262 STAMCOUNTER StatVmxCheckBadRmSelBase;
1263 STAMCOUNTER StatVmxCheckBadRmSelLimit;
1264 STAMCOUNTER StatVmxCheckBadRmSelAttr;
1265 STAMCOUNTER StatVmxCheckBadV86SelBase;
1266 STAMCOUNTER StatVmxCheckBadV86SelLimit;
1267 STAMCOUNTER StatVmxCheckBadV86SelAttr;
1268 STAMCOUNTER StatVmxCheckRmOk;
1269 STAMCOUNTER StatVmxCheckBadSel;
1270 STAMCOUNTER StatVmxCheckBadRpl;
1271 STAMCOUNTER StatVmxCheckPmOk;
1272
1273#ifdef VBOX_WITH_STATISTICS
1274 R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
1275 R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
1276 R3PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqs;
1277 R0PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqsR0;
1278 R3PTRTYPE(PSTAMCOUNTER) paStatInjectedXcpts;
1279 R0PTRTYPE(PSTAMCOUNTER) paStatInjectedXcptsR0;
1280 R3PTRTYPE(PSTAMCOUNTER) paStatNestedExitReason;
1281 R0PTRTYPE(PSTAMCOUNTER) paStatNestedExitReasonR0;
1282#endif
1283#ifdef HM_PROFILE_EXIT_DISPATCH
1284 STAMPROFILEADV StatExitDispatch;
1285#endif
1286} HMCPU;
1287/** Pointer to HM VMCPU instance data. */
1288typedef HMCPU *PHMCPU;
1289AssertCompileMemberAlignment(HMCPU, fCheckedTLBFlush, 4);
1290AssertCompileMemberAlignment(HMCPU, fCtxChanged, 8);
1291AssertCompileMemberAlignment(HMCPU, vmx, 8);
1292AssertCompileMemberAlignment(HMCPU, vmx.VmcsInfo, 8);
1293AssertCompileMemberAlignment(HMCPU, vmx.VmcsInfoNstGst, 8);
1294AssertCompileMemberAlignment(HMCPU, svm, 8);
1295AssertCompileMemberAlignment(HMCPU, Event, 8);
1296
1297
1298/**
1299 * HM per-VCpu ring-0 only instance data.
1300 */
1301typedef struct HMR0PERVCPU
1302{
1303 /** World switch exit counter. */
1304 uint32_t volatile cWorldSwitchExits;
1305 /** TLB flush count. */
1306 uint32_t cTlbFlushes;
1307 /** The last CPU we were executing code on (NIL_RTCPUID for the first time). */
1308 RTCPUID idLastCpu;
1309 /** The CPU ID of the CPU currently owning the VMCS. Set in
1310 * HMR0Enter and cleared in HMR0Leave. */
1311 RTCPUID idEnteredCpu;
1312 /** Current ASID in use by the VM. */
1313 uint32_t uCurrentAsid;
1314
1315 /** Set if we need to flush the TLB during the world switch. */
1316 bool fForceTLBFlush;
1317 /** Whether we've completed the inner HM leave function. */
1318 bool fLeaveDone;
1319 /** Whether we're using the hyper DR7 or guest DR7. */
1320 bool fUsingHyperDR7;
1321 /** Whether we are currently executing in the debug loop.
1322 * Mainly for assertions. */
1323 bool fUsingDebugLoop;
1324 /** Set if we using the debug loop and wish to intercept RDTSC. */
1325 bool fDebugWantRdTscExit;
1326 /** Set if XCR0 needs to be saved/restored when entering/exiting guest code
1327 * execution. */
1328 bool fLoadSaveGuestXcr0;
1329 /** Set if we need to clear the trap flag because of single stepping. */
1330 bool fClearTrapFlag;
1331
1332 bool afPadding1[5];
1333
1334 /** VT-x data. */
1335 struct HMR0CPUVMX
1336 {
1337 /** Ring-0 pointer to the hardware-assisted VMX execution function. */
1338 PFNHMVMXSTARTVM pfnStartVm;
1339
1340 /** @name Guest information.
1341 * @{ */
1342 /** Guest VMCS information. */
1343 VMXVMCSINFO VmcsInfo;
1344 /** Nested-guest VMCS information. */
1345 VMXVMCSINFO VmcsInfoNstGst;
1346 /* Whether the nested-guest VMCS was the last current VMCS (authoritative copy).
1347 * @see HMCPU::vmx.fSwitchedToNstGstVmcsCopyForRing3 */
1348 bool fSwitchedToNstGstVmcs;
1349 bool afAlignment0[7];
1350 /** @} */
1351
1352 /** @name Host information.
1353 * @{ */
1354 /** Host LSTAR MSR to restore lazily while leaving VT-x. */
1355 uint64_t u64HostMsrLStar;
1356 /** Host STAR MSR to restore lazily while leaving VT-x. */
1357 uint64_t u64HostMsrStar;
1358 /** Host SF_MASK MSR to restore lazily while leaving VT-x. */
1359 uint64_t u64HostMsrSfMask;
1360 /** Host KernelGS-Base MSR to restore lazily while leaving VT-x. */
1361 uint64_t u64HostMsrKernelGsBase;
1362 /** The mask of lazy MSRs swap/restore state, see VMX_LAZY_MSRS_XXX. */
1363 uint32_t fLazyMsrs;
1364 /** Whether the host MSR values are up-to-date in the auto-load/store MSR area. */
1365 bool fUpdatedHostAutoMsrs;
1366 /** Alignment. */
1367 uint8_t au8Alignment0[3];
1368 /** Which host-state bits to restore before being preempted, see
1369 * VMX_RESTORE_HOST_XXX. */
1370 uint32_t fRestoreHostFlags;
1371 /** Alignment. */
1372 uint32_t u32Alignment0;
1373 /** The host-state restoration structure. */
1374 VMXRESTOREHOST RestoreHost;
1375 /** @} */
1376 } vmx;
1377
1378 /** SVM data. */
1379 struct HMR0CPUSVM
1380 {
1381 /** Ring 0 handlers for VT-x. */
1382 PFNHMSVMVMRUN pfnVMRun;
1383
1384 /** Physical address of the host VMCB which holds additional host-state. */
1385 RTHCPHYS HCPhysVmcbHost;
1386 /** R0 memory object for the host VMCB which holds additional host-state. */
1387 RTR0MEMOBJ hMemObjVmcbHost;
1388
1389 /** Physical address of the guest VMCB. */
1390 RTHCPHYS HCPhysVmcb;
1391 /** R0 memory object for the guest VMCB. */
1392 RTR0MEMOBJ hMemObjVmcb;
1393 /** Pointer to the guest VMCB. */
1394 R0PTRTYPE(PSVMVMCB) pVmcb;
1395
1396 /** Physical address of the MSR bitmap (8 KB). */
1397 RTHCPHYS HCPhysMsrBitmap;
1398 /** R0 memory object for the MSR bitmap (8 KB). */
1399 RTR0MEMOBJ hMemObjMsrBitmap;
1400 /** Pointer to the MSR bitmap. */
1401 R0PTRTYPE(void *) pvMsrBitmap;
1402
1403 /** Whether VTPR with V_INTR_MASKING set is in effect, indicating
1404 * we should check if the VTPR changed on every VM-exit. */
1405 bool fSyncVTpr;
1406 bool afAlignment[7];
1407
1408 /** Host's TSC_AUX MSR (used when RDTSCP doesn't cause VM-exits). */
1409 uint64_t u64HostTscAux;
1410
1411 /** For saving stack space, the disassembler state is allocated here
1412 * instead of on the stack. */
1413 DISCPUSTATE DisState;
1414 } svm;
1415} HMR0PERVCPU;
1416/** Pointer to HM ring-0 VMCPU instance data. */
1417typedef HMR0PERVCPU *PHMR0PERVCPU;
1418AssertCompileMemberAlignment(HMR0PERVCPU, cWorldSwitchExits, 4);
1419AssertCompileMemberAlignment(HMR0PERVCPU, fForceTLBFlush, 4);
1420AssertCompileMemberAlignment(HMR0PERVCPU, vmx.RestoreHost, 8);
1421
1422
1423#ifdef IN_RING0
1424VMMR0_INT_DECL(PHMPHYSCPU) hmR0GetCurrentCpu(void);
1425VMMR0_INT_DECL(int) hmR0EnterCpu(PVMCPUCC pVCpu);
1426
1427# ifdef VBOX_STRICT
1428# define HM_DUMP_REG_FLAGS_GPRS RT_BIT(0)
1429# define HM_DUMP_REG_FLAGS_FPU RT_BIT(1)
1430# define HM_DUMP_REG_FLAGS_MSRS RT_BIT(2)
1431# define HM_DUMP_REG_FLAGS_ALL (HM_DUMP_REG_FLAGS_GPRS | HM_DUMP_REG_FLAGS_FPU | HM_DUMP_REG_FLAGS_MSRS)
1432
1433VMMR0_INT_DECL(void) hmR0DumpRegs(PVMCPUCC pVCpu, uint32_t fFlags);
1434VMMR0_INT_DECL(void) hmR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg);
1435# endif
1436
1437DECLASM(void) hmR0MdsClear(void);
1438#endif /* IN_RING0 */
1439
1440
1441/** @addtogroup grp_hm_int_svm SVM Internal
1442 * @{ */
1443VMM_INT_DECL(int) hmEmulateSvmMovTpr(PVMCC pVM, PVMCPUCC pVCpu);
1444
1445/**
1446 * Prepares for and executes VMRUN (64-bit register context).
1447 *
1448 * @returns VBox status code (no informational stuff).
1449 * @param pVM The cross context VM structure. (Not used.)
1450 * @param pVCpu The cross context virtual CPU structure.
1451 * @param HCPhyspVMCB Physical address of the VMCB.
1452 *
1453 * @remarks With spectre mitigations and the usual need for speed (/ micro
1454 * optimizations), we have a bunch of variations of this code depending
1455 * on a few precoditions. In release builds, the code is entirely
1456 * without conditionals. Debug builds have a couple of assertions that
1457 * shouldn't ever be triggered.
1458 *
1459 * @{
1460 */
1461DECLASM(int) hmR0SvmVmRun_SansXcr0_SansIbpbEntry_SansIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1462DECLASM(int) hmR0SvmVmRun_WithXcr0_SansIbpbEntry_SansIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1463DECLASM(int) hmR0SvmVmRun_SansXcr0_WithIbpbEntry_SansIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1464DECLASM(int) hmR0SvmVmRun_WithXcr0_WithIbpbEntry_SansIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1465DECLASM(int) hmR0SvmVmRun_SansXcr0_SansIbpbEntry_WithIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1466DECLASM(int) hmR0SvmVmRun_WithXcr0_SansIbpbEntry_WithIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1467DECLASM(int) hmR0SvmVmRun_SansXcr0_WithIbpbEntry_WithIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1468DECLASM(int) hmR0SvmVmRun_WithXcr0_WithIbpbEntry_WithIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1469/** @} */
1470
1471/** @} */
1472
1473
1474/** @addtogroup grp_hm_int_vmx VMX Internal
1475 * @{ */
1476VMM_INT_DECL(PVMXVMCSINFOSHARED) hmGetVmxActiveVmcsInfoShared(PVMCPUCC pVCpu);
1477
1478/**
1479 * Used on platforms with poor inline assembly support to retrieve all the
1480 * info from the CPU and put it in the @a pRestoreHost structure.
1481 */
1482DECLASM(void) hmR0VmxExportHostSegmentRegsAsmHlp(PVMXRESTOREHOST pRestoreHost, bool fHaveFsGsBase);
1483
1484/**
1485 * Restores some host-state fields that need not be done on every VM-exit.
1486 *
1487 * @returns VBox status code.
1488 * @param fRestoreHostFlags Flags of which host registers needs to be
1489 * restored.
1490 * @param pRestoreHost Pointer to the host-restore structure.
1491 */
1492DECLASM(int) VMXRestoreHostState(uint32_t fRestoreHostFlags, PVMXRESTOREHOST pRestoreHost);
1493
1494/**
1495 * VMX StartVM functions.
1496 *
1497 * @returns VBox status code (no informational stuff).
1498 * @param pVM Pointer to the cross context VM structure.
1499 * @param pVCpu Pointer to the cross context per-CPU structure.
1500 * @param fResume Whether to use VMRESUME (true) or VMLAUNCH (false).
1501 *
1502 * @remarks With spectre mitigations and the usual need for speed (/ micro
1503 * optimizations), we have a bunch of variations of this code depending
1504 * on a few precoditions. In release builds, the code is entirely
1505 * without conditionals. Debug builds have a couple of assertions that
1506 * shouldn't ever be triggered.
1507 *
1508 * @{
1509 */
1510DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_SansL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1511DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_SansL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1512DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_SansL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1513DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_SansL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1514DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_WithL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1515DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_WithL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1516DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_WithL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1517DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_WithL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1518DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_SansL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1519DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_SansL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1520DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_SansL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1521DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_SansL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1522DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_WithL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1523DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_WithL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1524DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_WithL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1525DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_WithL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1526DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_SansL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1527DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_SansL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1528DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_SansL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1529DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_SansL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1530DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_WithL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1531DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_WithL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1532DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_WithL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1533DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_WithL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1534DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_SansL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1535DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_SansL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1536DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_SansL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1537DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_SansL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1538DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_WithL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1539DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_WithL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1540DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_WithL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1541DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_WithL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1542/** @} */
1543
1544/** @} */
1545
1546/** @} */
1547
1548RT_C_DECLS_END
1549
1550#endif /* !VMM_INCLUDED_SRC_include_HMInternal_h */
1551
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