VirtualBox

source: vbox/trunk/src/VBox/VMM/include/HMInternal.h@ 87532

Last change on this file since 87532 was 87532, checked in by vboxsync, 4 years ago

VMM/HM: Moving the g_HmR0.hwvirt.svm.fSupported and g_HmR0.hwvirt.vmx.fSupported member out of the struct an into separate variables. bugref:9217
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id Revision
File size: 69.6 KB
Line 
1/* $Id: HMInternal.h 87532 2021-02-02 11:56:56Z vboxsync $ */
2/** @file
3 * HM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef VMM_INCLUDED_SRC_include_HMInternal_h
19#define VMM_INCLUDED_SRC_include_HMInternal_h
20#ifndef RT_WITHOUT_PRAGMA_ONCE
21# pragma once
22#endif
23
24#include <VBox/cdefs.h>
25#include <VBox/types.h>
26#include <VBox/vmm/stam.h>
27#include <VBox/dis.h>
28#include <VBox/vmm/hm.h>
29#include <VBox/vmm/hm_vmx.h>
30#include <VBox/vmm/hm_svm.h>
31#include <VBox/vmm/pgm.h>
32#include <VBox/vmm/cpum.h>
33#include <VBox/vmm/trpm.h>
34#include <iprt/memobj.h>
35#include <iprt/cpuset.h>
36#include <iprt/mp.h>
37#include <iprt/avl.h>
38#include <iprt/string.h>
39
40#if HC_ARCH_BITS == 32
41# error "32-bit hosts are no longer supported. Go back to 6.0 or earlier!"
42#endif
43
44/** @def HM_PROFILE_EXIT_DISPATCH
45 * Enables profiling of the VM exit handler dispatching. */
46#if 0 || defined(DOXYGEN_RUNNING)
47# define HM_PROFILE_EXIT_DISPATCH
48#endif
49
50RT_C_DECLS_BEGIN
51
52
53/** @defgroup grp_hm_int Internal
54 * @ingroup grp_hm
55 * @internal
56 * @{
57 */
58
59/** @name HM_CHANGED_XXX
60 * HM CPU-context changed flags.
61 *
62 * These flags are used to keep track of which registers and state has been
63 * modified since they were imported back into the guest-CPU context.
64 *
65 * @{
66 */
67#define HM_CHANGED_HOST_CONTEXT UINT64_C(0x0000000000000001)
68#define HM_CHANGED_GUEST_RIP UINT64_C(0x0000000000000004)
69#define HM_CHANGED_GUEST_RFLAGS UINT64_C(0x0000000000000008)
70
71#define HM_CHANGED_GUEST_RAX UINT64_C(0x0000000000000010)
72#define HM_CHANGED_GUEST_RCX UINT64_C(0x0000000000000020)
73#define HM_CHANGED_GUEST_RDX UINT64_C(0x0000000000000040)
74#define HM_CHANGED_GUEST_RBX UINT64_C(0x0000000000000080)
75#define HM_CHANGED_GUEST_RSP UINT64_C(0x0000000000000100)
76#define HM_CHANGED_GUEST_RBP UINT64_C(0x0000000000000200)
77#define HM_CHANGED_GUEST_RSI UINT64_C(0x0000000000000400)
78#define HM_CHANGED_GUEST_RDI UINT64_C(0x0000000000000800)
79#define HM_CHANGED_GUEST_R8_R15 UINT64_C(0x0000000000001000)
80#define HM_CHANGED_GUEST_GPRS_MASK UINT64_C(0x0000000000001ff0)
81
82#define HM_CHANGED_GUEST_ES UINT64_C(0x0000000000002000)
83#define HM_CHANGED_GUEST_CS UINT64_C(0x0000000000004000)
84#define HM_CHANGED_GUEST_SS UINT64_C(0x0000000000008000)
85#define HM_CHANGED_GUEST_DS UINT64_C(0x0000000000010000)
86#define HM_CHANGED_GUEST_FS UINT64_C(0x0000000000020000)
87#define HM_CHANGED_GUEST_GS UINT64_C(0x0000000000040000)
88#define HM_CHANGED_GUEST_SREG_MASK UINT64_C(0x000000000007e000)
89
90#define HM_CHANGED_GUEST_GDTR UINT64_C(0x0000000000080000)
91#define HM_CHANGED_GUEST_IDTR UINT64_C(0x0000000000100000)
92#define HM_CHANGED_GUEST_LDTR UINT64_C(0x0000000000200000)
93#define HM_CHANGED_GUEST_TR UINT64_C(0x0000000000400000)
94#define HM_CHANGED_GUEST_TABLE_MASK UINT64_C(0x0000000000780000)
95
96#define HM_CHANGED_GUEST_CR0 UINT64_C(0x0000000000800000)
97#define HM_CHANGED_GUEST_CR2 UINT64_C(0x0000000001000000)
98#define HM_CHANGED_GUEST_CR3 UINT64_C(0x0000000002000000)
99#define HM_CHANGED_GUEST_CR4 UINT64_C(0x0000000004000000)
100#define HM_CHANGED_GUEST_CR_MASK UINT64_C(0x0000000007800000)
101
102#define HM_CHANGED_GUEST_APIC_TPR UINT64_C(0x0000000008000000)
103#define HM_CHANGED_GUEST_EFER_MSR UINT64_C(0x0000000010000000)
104
105#define HM_CHANGED_GUEST_DR0_DR3 UINT64_C(0x0000000020000000)
106#define HM_CHANGED_GUEST_DR6 UINT64_C(0x0000000040000000)
107#define HM_CHANGED_GUEST_DR7 UINT64_C(0x0000000080000000)
108#define HM_CHANGED_GUEST_DR_MASK UINT64_C(0x00000000e0000000)
109
110#define HM_CHANGED_GUEST_X87 UINT64_C(0x0000000100000000)
111#define HM_CHANGED_GUEST_SSE_AVX UINT64_C(0x0000000200000000)
112#define HM_CHANGED_GUEST_OTHER_XSAVE UINT64_C(0x0000000400000000)
113#define HM_CHANGED_GUEST_XCRx UINT64_C(0x0000000800000000)
114
115#define HM_CHANGED_GUEST_KERNEL_GS_BASE UINT64_C(0x0000001000000000)
116#define HM_CHANGED_GUEST_SYSCALL_MSRS UINT64_C(0x0000002000000000)
117#define HM_CHANGED_GUEST_SYSENTER_CS_MSR UINT64_C(0x0000004000000000)
118#define HM_CHANGED_GUEST_SYSENTER_EIP_MSR UINT64_C(0x0000008000000000)
119#define HM_CHANGED_GUEST_SYSENTER_ESP_MSR UINT64_C(0x0000010000000000)
120#define HM_CHANGED_GUEST_SYSENTER_MSR_MASK UINT64_C(0x000001c000000000)
121#define HM_CHANGED_GUEST_TSC_AUX UINT64_C(0x0000020000000000)
122#define HM_CHANGED_GUEST_OTHER_MSRS UINT64_C(0x0000040000000000)
123#define HM_CHANGED_GUEST_ALL_MSRS ( HM_CHANGED_GUEST_EFER \
124 | HM_CHANGED_GUEST_KERNEL_GS_BASE \
125 | HM_CHANGED_GUEST_SYSCALL_MSRS \
126 | HM_CHANGED_GUEST_SYSENTER_MSR_MASK \
127 | HM_CHANGED_GUEST_TSC_AUX \
128 | HM_CHANGED_GUEST_OTHER_MSRS)
129
130#define HM_CHANGED_GUEST_HWVIRT UINT64_C(0x0000080000000000)
131#define HM_CHANGED_GUEST_MASK UINT64_C(0x00000ffffffffffc)
132
133#define HM_CHANGED_KEEPER_STATE_MASK UINT64_C(0xffff000000000000)
134
135#define HM_CHANGED_VMX_XCPT_INTERCEPTS UINT64_C(0x0001000000000000)
136#define HM_CHANGED_VMX_GUEST_AUTO_MSRS UINT64_C(0x0002000000000000)
137#define HM_CHANGED_VMX_GUEST_LAZY_MSRS UINT64_C(0x0004000000000000)
138#define HM_CHANGED_VMX_ENTRY_EXIT_CTLS UINT64_C(0x0008000000000000)
139#define HM_CHANGED_VMX_MASK UINT64_C(0x000f000000000000)
140#define HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE ( HM_CHANGED_GUEST_DR_MASK \
141 | HM_CHANGED_VMX_GUEST_LAZY_MSRS)
142
143#define HM_CHANGED_SVM_XCPT_INTERCEPTS UINT64_C(0x0001000000000000)
144#define HM_CHANGED_SVM_MASK UINT64_C(0x0001000000000000)
145#define HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE HM_CHANGED_GUEST_DR_MASK
146
147#define HM_CHANGED_ALL_GUEST ( HM_CHANGED_GUEST_MASK \
148 | HM_CHANGED_KEEPER_STATE_MASK)
149
150/** Mask of what state might have changed when IEM raised an exception.
151 * This is a based on IEM_CPUMCTX_EXTRN_XCPT_MASK. */
152#define HM_CHANGED_RAISED_XCPT_MASK ( HM_CHANGED_GUEST_GPRS_MASK \
153 | HM_CHANGED_GUEST_RIP \
154 | HM_CHANGED_GUEST_RFLAGS \
155 | HM_CHANGED_GUEST_SS \
156 | HM_CHANGED_GUEST_CS \
157 | HM_CHANGED_GUEST_CR0 \
158 | HM_CHANGED_GUEST_CR3 \
159 | HM_CHANGED_GUEST_CR4 \
160 | HM_CHANGED_GUEST_APIC_TPR \
161 | HM_CHANGED_GUEST_EFER_MSR \
162 | HM_CHANGED_GUEST_DR7 \
163 | HM_CHANGED_GUEST_CR2 \
164 | HM_CHANGED_GUEST_SREG_MASK \
165 | HM_CHANGED_GUEST_TABLE_MASK)
166
167#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
168/** Mask of what state might have changed when \#VMEXIT is emulated. */
169# define HM_CHANGED_SVM_VMEXIT_MASK ( HM_CHANGED_GUEST_RSP \
170 | HM_CHANGED_GUEST_RAX \
171 | HM_CHANGED_GUEST_RIP \
172 | HM_CHANGED_GUEST_RFLAGS \
173 | HM_CHANGED_GUEST_CS \
174 | HM_CHANGED_GUEST_SS \
175 | HM_CHANGED_GUEST_DS \
176 | HM_CHANGED_GUEST_ES \
177 | HM_CHANGED_GUEST_GDTR \
178 | HM_CHANGED_GUEST_IDTR \
179 | HM_CHANGED_GUEST_CR_MASK \
180 | HM_CHANGED_GUEST_EFER_MSR \
181 | HM_CHANGED_GUEST_DR6 \
182 | HM_CHANGED_GUEST_DR7 \
183 | HM_CHANGED_GUEST_OTHER_MSRS \
184 | HM_CHANGED_GUEST_HWVIRT \
185 | HM_CHANGED_SVM_MASK \
186 | HM_CHANGED_GUEST_APIC_TPR)
187
188/** Mask of what state might have changed when VMRUN is emulated. */
189# define HM_CHANGED_SVM_VMRUN_MASK HM_CHANGED_SVM_VMEXIT_MASK
190#endif
191#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
192/** Mask of what state might have changed when VM-exit is emulated.
193 *
194 * This is currently unused, but keeping it here in case we can get away a bit more
195 * fine-grained state handling.
196 *
197 * @note Update IEM_CPUMCTX_EXTRN_VMX_VMEXIT_MASK when this changes. */
198# define HM_CHANGED_VMX_VMEXIT_MASK ( HM_CHANGED_GUEST_CR0 | HM_CHANGED_GUEST_CR3 | HM_CHANGED_GUEST_CR4 \
199 | HM_CHANGED_GUEST_DR7 | HM_CHANGED_GUEST_DR6 \
200 | HM_CHANGED_GUEST_EFER_MSR \
201 | HM_CHANGED_GUEST_SYSENTER_MSR_MASK \
202 | HM_CHANGED_GUEST_OTHER_MSRS /* for PAT MSR */ \
203 | HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RSP | HM_CHANGED_GUEST_RFLAGS \
204 | HM_CHANGED_GUEST_SREG_MASK \
205 | HM_CHANGED_GUEST_TR \
206 | HM_CHANGED_GUEST_LDTR | HM_CHANGED_GUEST_GDTR | HM_CHANGED_GUEST_IDTR \
207 | HM_CHANGED_GUEST_HWVIRT )
208#endif
209/** @} */
210
211/** Maximum number of exit reason statistics counters. */
212#define MAX_EXITREASON_STAT 0x100
213#define MASK_EXITREASON_STAT 0xff
214#define MASK_INJECT_IRQ_STAT 0xff
215
216/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
217#define HM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
218/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
219#define HM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2 * PAGE_SIZE + 1)
220/** Total guest mapped memory needed. */
221#define HM_VTX_TOTAL_DEVHEAP_MEM (HM_EPT_IDENTITY_PG_TABLE_SIZE + HM_VTX_TSS_SIZE)
222
223
224/** @name Macros for enabling and disabling preemption.
225 * These are really just for hiding the RTTHREADPREEMPTSTATE and asserting that
226 * preemption has already been disabled when there is no context hook.
227 * @{ */
228#ifdef VBOX_STRICT
229# define HM_DISABLE_PREEMPT(a_pVCpu) \
230 RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
231 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD) || VMMR0ThreadCtxHookIsEnabled((a_pVCpu))); \
232 RTThreadPreemptDisable(&PreemptStateInternal)
233#else
234# define HM_DISABLE_PREEMPT(a_pVCpu) \
235 RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
236 RTThreadPreemptDisable(&PreemptStateInternal)
237#endif /* VBOX_STRICT */
238#define HM_RESTORE_PREEMPT() do { RTThreadPreemptRestore(&PreemptStateInternal); } while(0)
239/** @} */
240
241
242/** @name HM saved state versions.
243 * @{
244 */
245#define HM_SAVED_STATE_VERSION HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT
246#define HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT 6
247#define HM_SAVED_STATE_VERSION_TPR_PATCHING 5
248#define HM_SAVED_STATE_VERSION_NO_TPR_PATCHING 4
249#define HM_SAVED_STATE_VERSION_2_0_X 3
250/** @} */
251
252
253/**
254 * HM physical (host) CPU information.
255 */
256typedef struct HMPHYSCPU
257{
258 /** The CPU ID. */
259 RTCPUID idCpu;
260 /** The VM_HSAVE_AREA (AMD-V) / VMXON region (Intel) memory backing. */
261 RTR0MEMOBJ hMemObj;
262 /** The physical address of the first page in hMemObj (it's a
263 * physcially contigous allocation if it spans multiple pages). */
264 RTHCPHYS HCPhysMemObj;
265 /** The address of the memory (for pfnEnable). */
266 void *pvMemObj;
267 /** Current ASID (AMD-V) / VPID (Intel). */
268 uint32_t uCurrentAsid;
269 /** TLB flush count. */
270 uint32_t cTlbFlushes;
271 /** Whether to flush each new ASID/VPID before use. */
272 bool fFlushAsidBeforeUse;
273 /** Configured for VT-x or AMD-V. */
274 bool fConfigured;
275 /** Set if the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active. */
276 bool fIgnoreAMDVInUseError;
277 /** Whether CR4.VMXE was already enabled prior to us enabling it. */
278 bool fVmxeAlreadyEnabled;
279 /** In use by our code. (for power suspend) */
280 bool volatile fInUse;
281#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
282 /** Nested-guest union (put data common to SVM/VMX outside the union). */
283 union
284 {
285 /** Nested-guest SVM data. */
286 struct
287 {
288 /** The active nested-guest MSR permission bitmap memory backing. */
289 RTR0MEMOBJ hNstGstMsrpm;
290 /** The physical address of the first page in hNstGstMsrpm (physcially
291 * contiguous allocation). */
292 RTHCPHYS HCPhysNstGstMsrpm;
293 /** The address of the active nested-guest MSRPM. */
294 void *pvNstGstMsrpm;
295 } svm;
296 /** @todo Nested-VMX. */
297 } n;
298#endif
299} HMPHYSCPU;
300/** Pointer to HMPHYSCPU struct. */
301typedef HMPHYSCPU *PHMPHYSCPU;
302/** Pointer to a const HMPHYSCPU struct. */
303typedef const HMPHYSCPU *PCHMPHYSCPU;
304
305/**
306 * TPR-instruction type.
307 */
308typedef enum
309{
310 HMTPRINSTR_INVALID,
311 HMTPRINSTR_READ,
312 HMTPRINSTR_READ_SHR4,
313 HMTPRINSTR_WRITE_REG,
314 HMTPRINSTR_WRITE_IMM,
315 HMTPRINSTR_JUMP_REPLACEMENT,
316 /** The usual 32-bit paranoia. */
317 HMTPRINSTR_32BIT_HACK = 0x7fffffff
318} HMTPRINSTR;
319
320/**
321 * TPR patch information.
322 */
323typedef struct
324{
325 /** The key is the address of patched instruction. (32 bits GC ptr) */
326 AVLOU32NODECORE Core;
327 /** Original opcode. */
328 uint8_t aOpcode[16];
329 /** Instruction size. */
330 uint32_t cbOp;
331 /** Replacement opcode. */
332 uint8_t aNewOpcode[16];
333 /** Replacement instruction size. */
334 uint32_t cbNewOp;
335 /** Instruction type. */
336 HMTPRINSTR enmType;
337 /** Source operand. */
338 uint32_t uSrcOperand;
339 /** Destination operand. */
340 uint32_t uDstOperand;
341 /** Number of times the instruction caused a fault. */
342 uint32_t cFaults;
343 /** Patch address of the jump replacement. */
344 RTGCPTR32 pJumpTarget;
345} HMTPRPATCH;
346/** Pointer to HMTPRPATCH. */
347typedef HMTPRPATCH *PHMTPRPATCH;
348/** Pointer to a const HMTPRPATCH. */
349typedef const HMTPRPATCH *PCHMTPRPATCH;
350
351
352/**
353 * Makes a HMEXITSTAT::uKey value from a program counter and an exit code.
354 *
355 * @returns 64-bit key
356 * @param a_uPC The RIP + CS.BASE value of the exit.
357 * @param a_uExit The exit code.
358 * @todo Add CPL?
359 */
360#define HMEXITSTAT_MAKE_KEY(a_uPC, a_uExit) (((a_uPC) & UINT64_C(0x0000ffffffffffff)) | (uint64_t)(a_uExit) << 48)
361
362typedef struct HMEXITINFO
363{
364 /** See HMEXITSTAT_MAKE_KEY(). */
365 uint64_t uKey;
366 /** Number of recent hits (depreciates with time). */
367 uint32_t volatile cHits;
368 /** The age + lock. */
369 uint16_t volatile uAge;
370 /** Action or action table index. */
371 uint16_t iAction;
372} HMEXITINFO;
373AssertCompileSize(HMEXITINFO, 16); /* Lots of these guys, so don't add any unnecessary stuff! */
374
375typedef struct HMEXITHISTORY
376{
377 /** The exit timestamp. */
378 uint64_t uTscExit;
379 /** The index of the corresponding HMEXITINFO entry.
380 * UINT32_MAX if none (too many collisions, race, whatever). */
381 uint32_t iExitInfo;
382 /** Figure out later, needed for padding now. */
383 uint32_t uSomeClueOrSomething;
384} HMEXITHISTORY;
385
386/**
387 * Switcher function, HC to the special 64-bit RC.
388 *
389 * @param pVM The cross context VM structure.
390 * @param offCpumVCpu Offset from pVM->cpum to pVM->aCpus[idCpu].cpum.
391 * @returns Return code indicating the action to take.
392 */
393typedef DECLCALLBACKTYPE(int, FNHMSWITCHERHC,(PVM pVM, uint32_t offCpumVCpu));
394/** Pointer to switcher function. */
395typedef FNHMSWITCHERHC *PFNHMSWITCHERHC;
396
397
398/**
399 * HM event.
400 *
401 * VT-x and AMD-V common event injection structure.
402 */
403typedef struct HMEVENT
404{
405 /** Whether the event is pending. */
406 uint32_t fPending;
407 /** The error-code associated with the event. */
408 uint32_t u32ErrCode;
409 /** The length of the instruction in bytes (only relevant for software
410 * interrupts or software exceptions). */
411 uint32_t cbInstr;
412 /** Alignment. */
413 uint32_t u32Padding;
414 /** The encoded event (VM-entry interruption-information for VT-x or EVENTINJ
415 * for SVM). */
416 uint64_t u64IntInfo;
417 /** Guest virtual address if this is a page-fault event. */
418 RTGCUINTPTR GCPtrFaultAddress;
419} HMEVENT;
420/** Pointer to a HMEVENT struct. */
421typedef HMEVENT *PHMEVENT;
422/** Pointer to a const HMEVENT struct. */
423typedef const HMEVENT *PCHMEVENT;
424AssertCompileSizeAlignment(HMEVENT, 8);
425
426/**
427 * HM VM Instance data.
428 * Changes to this must checked against the padding of the hm union in VM!
429 */
430typedef struct HM
431{
432 /** Set if nested paging is enabled.
433 * Config value that is copied to HMR0PERVM::fNestedPaging on setup. */
434 bool fNestedPagingCfg;
435 /** Set when we've finalized the VMX / SVM initialization in ring-3
436 * (hmR3InitFinalizeR0Intel / hmR3InitFinalizeR0Amd). */
437 bool fInitialized;
438 /** Set if large pages are enabled (requires nested paging).
439 * Config only, passed on the PGM where it really belongs.
440 * @todo move to PGM */
441 bool fLargePages;
442 /** Set if we can support 64-bit guests or not.
443 * Config value that is copied to HMR0PERVM::fAllow64BitGuests on setup. */
444 bool fAllow64BitGuestsCfg;
445 /** Set when we initialize VT-x or AMD-V once for all CPUs. */
446 bool fGlobalInit;
447 /** Set when TPR patching is allowed. */
448 bool fTprPatchingAllowed;
449 /** Set when TPR patching is active. */
450 bool fTPRPatchingActive;
451 /** Set when the debug facility has breakpoints/events enabled that requires
452 * us to use the debug execution loop in ring-0. */
453 bool fUseDebugLoop;
454 /** Set if hardware APIC virtualization is enabled.
455 * @todo Not really used by HM, move to APIC where it's actually used. */
456 bool fVirtApicRegs;
457 /** Set if posted interrupt processing is enabled.
458 * @todo Not really used by HM, move to APIC where it's actually used. */
459 bool fPostedIntrs;
460
461 /** @name Processed into HMR0PERVCPU::fWorldSwitcher by ring-0 on VM init.
462 * @{ */
463 /** Set if indirect branch prediction barrier on VM exit. */
464 bool fIbpbOnVmExit;
465 /** Set if indirect branch prediction barrier on VM entry. */
466 bool fIbpbOnVmEntry;
467 /** Set if level 1 data cache should be flushed on VM entry. */
468 bool fL1dFlushOnVmEntry;
469 /** Set if level 1 data cache should be flushed on EMT scheduling. */
470 bool fL1dFlushOnSched;
471 /** Set if MDS related buffers should be cleared on VM entry. */
472 bool fMdsClearOnVmEntry;
473 /** Set if MDS related buffers should be cleared on EMT scheduling. */
474 bool fMdsClearOnSched;
475 /** Set if host manages speculation control settings.
476 * @todo doesn't do anything ... */
477 bool fSpecCtrlByHost;
478 /** @} */
479
480 /** Alignment padding. */
481 bool afPaddingMinus1[3];
482
483 /** The maximum number of resumes loops allowed in ring-0 (safety precaution).
484 * This number is set much higher when RTThreadPreemptIsPending is reliable. */
485 uint32_t cMaxResumeLoopsCfg;
486
487 struct
488 {
489 /** Set by the ring-0 side of HM to indicate VMX is supported by the
490 * CPU. */
491 bool fSupported;
492 /** Set when we've enabled VMX. */
493 bool fEnabled;
494 /** Set if VPID is supported. */
495 bool fVpid;
496 /** Set if VT-x VPID is allowed. */
497 bool fAllowVpid;
498 /** Set if unrestricted guest execution is in use (real and protected mode
499 * without paging). */
500 bool fUnrestrictedGuest;
501 /** Set if the preemption timer is in use or not. */
502 bool fUsePreemptTimer;
503 /** The shift mask employed by the VMX-Preemption timer. */
504 uint8_t cPreemptTimerShift;
505 /** Padding. */
506 bool afPadding0;
507
508 /** Tagged-TLB flush type. */
509 VMXTLBFLUSHTYPE enmTlbFlushType;
510 /** Flush type to use for INVEPT. */
511 VMXTLBFLUSHEPT enmTlbFlushEpt;
512 /** Flush type to use for INVVPID. */
513 VMXTLBFLUSHVPID enmTlbFlushVpid;
514
515 /** Pause-loop exiting (PLE) gap in ticks. */
516 uint32_t cPleGapTicks;
517 /** Pause-loop exiting (PLE) window in ticks. */
518 uint32_t cPleWindowTicks;
519 uint32_t u32Alignment0;
520
521 /** Host CR4 value (set by ring-0 VMX init) */
522 uint64_t u64HostCr4;
523 /** Host SMM monitor control (set by ring-0 VMX init) */
524 uint64_t u64HostSmmMonitorCtl;
525 /** Host EFER value (set by ring-0 VMX init) */
526 uint64_t u64HostMsrEfer;
527 /** Whether the CPU supports VMCS fields for swapping EFER. */
528 bool fSupportsVmcsEfer;
529 /** Whether to use VMCS shadowing. */
530 bool fUseVmcsShadowing;
531 /** Set if Last Branch Record (LBR) is enabled. */
532 bool fLbr;
533 uint8_t u8Alignment2[5];
534
535 /** The first valid host LBR branch-from-IP stack range. */
536 uint32_t idLbrFromIpMsrFirst;
537 /** The last valid host LBR branch-from-IP stack range. */
538 uint32_t idLbrFromIpMsrLast;
539
540 /** The first valid host LBR branch-to-IP stack range. */
541 uint32_t idLbrToIpMsrFirst;
542 /** The last valid host LBR branch-to-IP stack range. */
543 uint32_t idLbrToIpMsrLast;
544
545 /** The host LBR TOS (top-of-stack) MSR id. */
546 uint32_t idLbrTosMsr;
547 /** Padding. */
548 uint32_t u32Alignment1;
549
550 /** Host-physical address for a failing VMXON instruction (diagnostics). */
551 RTHCPHYS HCPhysVmxEnableError;
552
553 /** VMX MSR values. */
554 VMXMSRS Msrs;
555
556 /** Virtual address of the TSS page used for real mode emulation. */
557 R3PTRTYPE(PVBOXTSS) pRealModeTSS;
558 /** Virtual address of the identity page table used for real mode and protected
559 * mode without paging emulation in EPT mode. */
560 R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
561 } vmx;
562
563 struct
564 {
565 /** Set by the ring-0 side of HM to indicate SVM is supported by the CPU. */
566 bool fSupported;
567 /** Set when we've enabled SVM. */
568 bool fEnabled;
569 /** Set when the hack to ignore VERR_SVM_IN_USE is active.
570 * @todo Safe? */
571 bool fIgnoreInUseError;
572 /** Whether to use virtualized VMSAVE/VMLOAD feature. */
573 bool fVirtVmsaveVmload;
574 /** Whether to use virtual GIF feature. */
575 bool fVGif;
576 /** Whether to use LBR virtualization feature. */
577 bool fLbrVirt;
578 uint8_t u8Alignment0[2];
579
580 /** HWCR MSR (for diagnostics). */
581 uint64_t u64MsrHwcr;
582
583 /** SVM revision. */
584 uint32_t u32Rev;
585 /** SVM feature bits from cpuid 0x8000000a, ring-3 copy. */
586 uint32_t fFeaturesForRing3;
587
588 /** Pause filter counter. */
589 uint16_t cPauseFilter;
590 /** Pause filter treshold in ticks. */
591 uint16_t cPauseFilterThresholdTicks;
592 uint32_t u32Alignment0;
593 } svm;
594
595 /** AVL tree with all patches (active or disabled) sorted by guest instruction address.
596 * @todo For @bugref{9217} this AVL tree must be eliminated and instead
597 * sort aPatches by address and do a safe binary search on it. */
598 AVLOU32TREE PatchTree;
599 uint32_t cPatches;
600 HMTPRPATCH aPatches[64];
601
602 /** Guest allocated memory for patching purposes. */
603 RTGCPTR pGuestPatchMem;
604 /** Current free pointer inside the patch block. */
605 RTGCPTR pFreeGuestPatchMem;
606 /** Size of the guest patch memory block. */
607 uint32_t cbGuestPatchMem;
608
609 /** Last recorded error code during HM ring-0 init. */
610 int32_t rcInit;
611 /** Maximum ASID allowed.
612 * This is mainly for the release log. */
613 uint32_t uMaxAsidForLog;
614 /** World switcher flags (HM_WSF_XXX) for the release log. */
615 uint32_t fWorldSwitcherForLog;
616
617 STAMCOUNTER StatTprPatchSuccess;
618 STAMCOUNTER StatTprPatchFailure;
619 STAMCOUNTER StatTprReplaceSuccessCr8;
620 STAMCOUNTER StatTprReplaceSuccessVmc;
621 STAMCOUNTER StatTprReplaceFailure;
622} HM;
623/** Pointer to HM VM instance data. */
624typedef HM *PHM;
625AssertCompileMemberAlignment(HM, StatTprPatchSuccess, 8);
626AssertCompileMemberAlignment(HM, vmx, 8);
627AssertCompileMemberAlignment(HM, svm, 8);
628
629
630/**
631 * Per-VM ring-0 instance data for HM.
632 */
633typedef struct HMR0PERVM
634{
635 /** Set if nested paging is enabled. */
636 bool fNestedPaging;
637 /** Set if we can support 64-bit guests or not. */
638 bool fAllow64BitGuests;
639 bool afAlignment0[2+4];
640
641 /** The maximum number of resumes loops allowed in ring-0 (safety precaution).
642 * This number is set much higher when RTThreadPreemptIsPending is reliable. */
643 uint32_t cMaxResumeLoops;
644
645 /** Host kernel flags that HM might need to know (SUPKERNELFEATURES_XXX). */
646 uint32_t fHostKernelFeatures;
647
648 /** VT-x specific data. */
649 struct HMR0VMXVM
650 {
651 /** Virtual address of the APIC-access page. */
652 R0PTRTYPE(uint8_t *) pbApicAccess;
653 /** Pointer to the VMREAD bitmap. */
654 R0PTRTYPE(void *) pvVmreadBitmap;
655 /** Pointer to the VMWRITE bitmap. */
656 R0PTRTYPE(void *) pvVmwriteBitmap;
657
658 /** Pointer to the shadow VMCS read-only fields array. */
659 R0PTRTYPE(uint32_t *) paShadowVmcsRoFields;
660 /** Pointer to the shadow VMCS read/write fields array. */
661 R0PTRTYPE(uint32_t *) paShadowVmcsFields;
662 /** Number of elements in the shadow VMCS read-only fields array. */
663 uint32_t cShadowVmcsRoFields;
664 /** Number of elements in the shadow VMCS read-write fields array. */
665 uint32_t cShadowVmcsFields;
666
667 /** Host-physical address of the APIC-access page. */
668 RTHCPHYS HCPhysApicAccess;
669 /** Host-physical address of the VMREAD bitmap. */
670 RTHCPHYS HCPhysVmreadBitmap;
671 /** Host-physical address of the VMWRITE bitmap. */
672 RTHCPHYS HCPhysVmwriteBitmap;
673
674#ifdef VBOX_WITH_CRASHDUMP_MAGIC
675 /** Host-physical address of the crash-dump scratch area. */
676 RTHCPHYS HCPhysScratch;
677 /** Pointer to the crash-dump scratch bitmap. */
678 R0PTRTYPE(uint8_t *) pbScratch;
679#endif
680
681 /** Ring-0 memory object for per-VM VMX structures. */
682 RTR0MEMOBJ hMemObj;
683 } vmx;
684
685 /** AMD-V specific data. */
686 struct HMR0SVMVM
687 {
688 /** Set if erratum 170 affects the AMD cpu. */
689 bool fAlwaysFlushTLB;
690 bool afAlignment0[3];
691 /** SVM feature bits from cpuid 0x8000000a, safe ring-0 copy. */
692 uint32_t fFeatures;
693 } svm;
694} HMR0PERVM;
695/** Pointer to HM's per-VM ring-0 instance data. */
696typedef HMR0PERVM *PHMR0PERVM;
697
698
699/** @addtogroup grp_hm_int_svm SVM Internal
700 * @{ */
701/** SVM VMRun function, see SVMR0VMRun(). */
702typedef DECLCALLBACKTYPE(int, FNHMSVMVMRUN,(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhysVMCB));
703/** Pointer to a SVM VMRun function. */
704typedef R0PTRTYPE(FNHMSVMVMRUN *) PFNHMSVMVMRUN;
705
706/**
707 * SVM nested-guest VMCB cache.
708 *
709 * Contains VMCB fields from the nested-guest VMCB before they're modified by
710 * SVM R0 code for hardware-assisted SVM execution of a nested-guest.
711 *
712 * A VMCB field needs to be cached when it needs to be modified for execution using
713 * hardware-assisted SVM and any of the following are true:
714 * - If the original field needs to be inspected during execution of the
715 * nested-guest or \#VMEXIT processing.
716 * - If the field is written back to memory on \#VMEXIT by the physical CPU.
717 *
718 * A VMCB field needs to be restored only when the field is written back to
719 * memory on \#VMEXIT by the physical CPU and thus would be visible to the
720 * guest.
721 *
722 * @remarks Please update hmR3InfoSvmNstGstVmcbCache() when changes are made to
723 * this structure.
724 */
725typedef struct SVMNESTEDVMCBCACHE
726{
727 /** Cache of CRX read intercepts. */
728 uint16_t u16InterceptRdCRx;
729 /** Cache of CRX write intercepts. */
730 uint16_t u16InterceptWrCRx;
731 /** Cache of DRX read intercepts. */
732 uint16_t u16InterceptRdDRx;
733 /** Cache of DRX write intercepts. */
734 uint16_t u16InterceptWrDRx;
735
736 /** Cache of the pause-filter threshold. */
737 uint16_t u16PauseFilterThreshold;
738 /** Cache of the pause-filter count. */
739 uint16_t u16PauseFilterCount;
740
741 /** Cache of exception intercepts. */
742 uint32_t u32InterceptXcpt;
743 /** Cache of control intercepts. */
744 uint64_t u64InterceptCtrl;
745
746 /** Cache of the TSC offset. */
747 uint64_t u64TSCOffset;
748
749 /** Cache of V_INTR_MASKING bit. */
750 bool fVIntrMasking;
751 /** Cache of the nested-paging bit. */
752 bool fNestedPaging;
753 /** Cache of the LBR virtualization bit. */
754 bool fLbrVirt;
755 /** Whether the VMCB is cached by HM. */
756 bool fCacheValid;
757 /** Alignment. */
758 bool afPadding0[4];
759} SVMNESTEDVMCBCACHE;
760/** Pointer to the SVMNESTEDVMCBCACHE structure. */
761typedef SVMNESTEDVMCBCACHE *PSVMNESTEDVMCBCACHE;
762/** Pointer to a const SVMNESTEDVMCBCACHE structure. */
763typedef const SVMNESTEDVMCBCACHE *PCSVMNESTEDVMCBCACHE;
764AssertCompileSizeAlignment(SVMNESTEDVMCBCACHE, 8);
765
766/** @} */
767
768
769/** @addtogroup grp_hm_int_vmx VMX Internal
770 * @{ */
771/**
772 * VMX VMCS information, shared.
773 *
774 * This structure provides information maintained for and during the executing of a
775 * guest (or nested-guest) VMCS (VM control structure) using hardware-assisted VMX.
776 *
777 * Note! The members here are ordered and aligned based on estimated frequency of
778 * usage and grouped to fit within a cache line in hot code paths. Even subtle
779 * changes here have a noticeable effect in the bootsector benchmarks. Modify with
780 * care.
781 */
782typedef struct VMXVMCSINFOSHARED
783{
784 /** @name Real-mode emulation state.
785 * @{ */
786 /** Set if guest was executing in real mode (extra checks). */
787 bool fWasInRealMode;
788 /** Padding. */
789 bool afPadding0[7];
790 struct
791 {
792 X86DESCATTR AttrCS;
793 X86DESCATTR AttrDS;
794 X86DESCATTR AttrES;
795 X86DESCATTR AttrFS;
796 X86DESCATTR AttrGS;
797 X86DESCATTR AttrSS;
798 X86EFLAGS Eflags;
799 bool fRealOnV86Active;
800 bool afPadding1[3];
801 } RealMode;
802 /** @} */
803
804 /** @name LBR MSR data.
805 * @{ */
806 /** List of LastBranch-From-IP MSRs. */
807 uint64_t au64LbrFromIpMsr[32];
808 /** List of LastBranch-To-IP MSRs. */
809 uint64_t au64LbrToIpMsr[32];
810 /** The MSR containing the index to the most recent branch record. */
811 uint64_t u64LbrTosMsr;
812 /** @} */
813} VMXVMCSINFOSHARED;
814/** Pointer to a VMXVMCSINFOSHARED struct. */
815typedef VMXVMCSINFOSHARED *PVMXVMCSINFOSHARED;
816/** Pointer to a const VMXVMCSINFOSHARED struct. */
817typedef const VMXVMCSINFOSHARED *PCVMXVMCSINFOSHARED;
818AssertCompileSizeAlignment(VMXVMCSINFOSHARED, 8);
819
820
821/**
822 * VMX VMCS information, ring-0 only.
823 *
824 * This structure provides information maintained for and during the executing of a
825 * guest (or nested-guest) VMCS (VM control structure) using hardware-assisted VMX.
826 *
827 * Note! The members here are ordered and aligned based on estimated frequency of
828 * usage and grouped to fit within a cache line in hot code paths. Even subtle
829 * changes here have a noticeable effect in the bootsector benchmarks. Modify with
830 * care.
831 */
832typedef struct VMXVMCSINFO
833{
834 /** Pointer to the bits we share with ring-3. */
835 R0PTRTYPE(PVMXVMCSINFOSHARED) pShared;
836
837 /** @name Auxiliary information.
838 * @{ */
839 /** Host-physical address of the EPTP. */
840 RTHCPHYS HCPhysEPTP;
841 /** The VMCS launch state, see VMX_V_VMCS_LAUNCH_STATE_XXX. */
842 uint32_t fVmcsState;
843 /** The VMCS launch state of the shadow VMCS, see VMX_V_VMCS_LAUNCH_STATE_XXX. */
844 uint32_t fShadowVmcsState;
845 /** The host CPU for which its state has been exported to this VMCS. */
846 RTCPUID idHostCpuState;
847 /** The host CPU on which we last executed this VMCS. */
848 RTCPUID idHostCpuExec;
849 /** Number of guest MSRs in the VM-entry MSR-load area. */
850 uint32_t cEntryMsrLoad;
851 /** Number of guest MSRs in the VM-exit MSR-store area. */
852 uint32_t cExitMsrStore;
853 /** Number of host MSRs in the VM-exit MSR-load area. */
854 uint32_t cExitMsrLoad;
855 /** @} */
856
857 /** @name Cache of execution related VMCS fields.
858 * @{ */
859 /** Pin-based VM-execution controls. */
860 uint32_t u32PinCtls;
861 /** Processor-based VM-execution controls. */
862 uint32_t u32ProcCtls;
863 /** Secondary processor-based VM-execution controls. */
864 uint32_t u32ProcCtls2;
865 /** VM-entry controls. */
866 uint32_t u32EntryCtls;
867 /** VM-exit controls. */
868 uint32_t u32ExitCtls;
869 /** Exception bitmap. */
870 uint32_t u32XcptBitmap;
871 /** Page-fault exception error-code mask. */
872 uint32_t u32XcptPFMask;
873 /** Page-fault exception error-code match. */
874 uint32_t u32XcptPFMatch;
875 /** Padding. */
876 uint32_t u32Alignment0;
877 /** TSC offset. */
878 uint64_t u64TscOffset;
879 /** VMCS link pointer. */
880 uint64_t u64VmcsLinkPtr;
881 /** CR0 guest/host mask. */
882 uint64_t u64Cr0Mask;
883 /** CR4 guest/host mask. */
884 uint64_t u64Cr4Mask;
885 /** Current VMX_VMCS_HOST_RIP value (only used in HMR0A.asm). */
886 uint64_t uHostRip;
887 /** Current VMX_VMCS_HOST_RSP value (only used in HMR0A.asm). */
888 uint64_t uHostRsp;
889 /** @} */
890
891 /** @name Host-virtual address of VMCS and related data structures.
892 * @{ */
893 /** The VMCS. */
894 R0PTRTYPE(void *) pvVmcs;
895 /** The shadow VMCS. */
896 R0PTRTYPE(void *) pvShadowVmcs;
897 /** The virtual-APIC page. */
898 R0PTRTYPE(uint8_t *) pbVirtApic;
899 /** The MSR bitmap. */
900 R0PTRTYPE(void *) pvMsrBitmap;
901 /** The VM-entry MSR-load area. */
902 R0PTRTYPE(void *) pvGuestMsrLoad;
903 /** The VM-exit MSR-store area. */
904 R0PTRTYPE(void *) pvGuestMsrStore;
905 /** The VM-exit MSR-load area. */
906 R0PTRTYPE(void *) pvHostMsrLoad;
907 /** @} */
908
909 /** @name Host-physical address of VMCS and related data structures.
910 * @{ */
911 /** The VMCS. */
912 RTHCPHYS HCPhysVmcs;
913 /** The shadow VMCS. */
914 RTHCPHYS HCPhysShadowVmcs;
915 /** The virtual APIC page. */
916 RTHCPHYS HCPhysVirtApic;
917 /** The MSR bitmap. */
918 RTHCPHYS HCPhysMsrBitmap;
919 /** The VM-entry MSR-load area. */
920 RTHCPHYS HCPhysGuestMsrLoad;
921 /** The VM-exit MSR-store area. */
922 RTHCPHYS HCPhysGuestMsrStore;
923 /** The VM-exit MSR-load area. */
924 RTHCPHYS HCPhysHostMsrLoad;
925 /** @} */
926
927 /** @name R0-memory objects address for VMCS and related data structures.
928 * @{ */
929 /** R0-memory object for VMCS and related data structures. */
930 RTR0MEMOBJ hMemObj;
931 /** @} */
932} VMXVMCSINFO;
933/** Pointer to a VMXVMCSINFOR0 struct. */
934typedef VMXVMCSINFO *PVMXVMCSINFO;
935/** Pointer to a const VMXVMCSINFO struct. */
936typedef const VMXVMCSINFO *PCVMXVMCSINFO;
937AssertCompileSizeAlignment(VMXVMCSINFO, 8);
938AssertCompileMemberAlignment(VMXVMCSINFO, u32PinCtls, 4);
939AssertCompileMemberAlignment(VMXVMCSINFO, u64VmcsLinkPtr, 8);
940AssertCompileMemberAlignment(VMXVMCSINFO, pvVmcs, 8);
941AssertCompileMemberAlignment(VMXVMCSINFO, pvShadowVmcs, 8);
942AssertCompileMemberAlignment(VMXVMCSINFO, pbVirtApic, 8);
943AssertCompileMemberAlignment(VMXVMCSINFO, pvMsrBitmap, 8);
944AssertCompileMemberAlignment(VMXVMCSINFO, pvGuestMsrLoad, 8);
945AssertCompileMemberAlignment(VMXVMCSINFO, pvGuestMsrStore, 8);
946AssertCompileMemberAlignment(VMXVMCSINFO, pvHostMsrLoad, 8);
947AssertCompileMemberAlignment(VMXVMCSINFO, HCPhysVmcs, 8);
948AssertCompileMemberAlignment(VMXVMCSINFO, hMemObj, 8);
949
950
951/** @name Host-state restoration flags.
952 * @note If you change these values don't forget to update the assembly
953 * defines as well!
954 * @{
955 */
956#define VMX_RESTORE_HOST_SEL_DS RT_BIT(0)
957#define VMX_RESTORE_HOST_SEL_ES RT_BIT(1)
958#define VMX_RESTORE_HOST_SEL_FS RT_BIT(2)
959#define VMX_RESTORE_HOST_SEL_GS RT_BIT(3)
960#define VMX_RESTORE_HOST_SEL_TR RT_BIT(4)
961#define VMX_RESTORE_HOST_GDTR RT_BIT(5)
962#define VMX_RESTORE_HOST_IDTR RT_BIT(6)
963#define VMX_RESTORE_HOST_GDT_READ_ONLY RT_BIT(7)
964#define VMX_RESTORE_HOST_GDT_NEED_WRITABLE RT_BIT(8)
965#define VMX_RESTORE_HOST_CAN_USE_WRFSBASE_AND_WRGSBASE RT_BIT(9)
966/**
967 * This _must_ be the top most bit, so that we can easily that that it and
968 * something else is set w/o having to do two checks like this:
969 * @code
970 * if ( (pVCpu->hm.s.vmx.fRestoreHostFlags & VMX_RESTORE_HOST_REQUIRED)
971 * && (pVCpu->hm.s.vmx.fRestoreHostFlags & ~VMX_RESTORE_HOST_REQUIRED))
972 * @endcode
973 * Instead we can then do:
974 * @code
975 * if (pVCpu->hm.s.vmx.fRestoreHostFlags > VMX_RESTORE_HOST_REQUIRED)
976 * @endcode
977 */
978#define VMX_RESTORE_HOST_REQUIRED RT_BIT(10)
979/** @} */
980
981/**
982 * Host-state restoration structure.
983 *
984 * This holds host-state fields that require manual restoration.
985 * Assembly version found in HMInternal.mac (should be automatically verified).
986 */
987typedef struct VMXRESTOREHOST
988{
989 RTSEL uHostSelDS; /**< 0x00 */
990 RTSEL uHostSelES; /**< 0x02 */
991 RTSEL uHostSelFS; /**< 0x04 */
992 X86XDTR64 HostGdtr; /**< 0x06 - should be aligned by its 64-bit member. */
993 RTSEL uHostSelGS; /**< 0x10 */
994 RTSEL uHostSelTR; /**< 0x12 */
995 RTSEL uHostSelSS; /**< 0x14 - not restored, just for fetching */
996 X86XDTR64 HostGdtrRw; /**< 0x16 - should be aligned by its 64-bit member. */
997 RTSEL uHostSelCS; /**< 0x20 - not restored, just for fetching */
998 uint8_t abPadding1[4]; /**< 0x22 */
999 X86XDTR64 HostIdtr; /**< 0x26 - should be aligned by its 64-bit member. */
1000 uint64_t uHostFSBase; /**< 0x30 */
1001 uint64_t uHostGSBase; /**< 0x38 */
1002} VMXRESTOREHOST;
1003/** Pointer to VMXRESTOREHOST. */
1004typedef VMXRESTOREHOST *PVMXRESTOREHOST;
1005AssertCompileSize(X86XDTR64, 10);
1006AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtr.uAddr, 0x08);
1007AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtrRw.uAddr, 0x18);
1008AssertCompileMemberOffset(VMXRESTOREHOST, HostIdtr.uAddr, 0x28);
1009AssertCompileMemberOffset(VMXRESTOREHOST, uHostFSBase, 0x30);
1010AssertCompileSize(VMXRESTOREHOST, 64);
1011AssertCompileSizeAlignment(VMXRESTOREHOST, 8);
1012
1013/**
1014 * VMX StartVM function.
1015 *
1016 * @returns VBox status code (no informational stuff).
1017 * @param pVmcsInfo Pointer to the VMCS info (for cached host RIP and RSP).
1018 * @param pVCpu Pointer to the cross context per-CPU structure.
1019 * @param fResume Whether to use VMRESUME (true) or VMLAUNCH (false).
1020 */
1021typedef DECLCALLBACKTYPE(int, FNHMVMXSTARTVM,(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume));
1022/** Pointer to a VMX StartVM function. */
1023typedef R0PTRTYPE(FNHMVMXSTARTVM *) PFNHMVMXSTARTVM;
1024/** @} */
1025
1026/**
1027 * HM VMCPU Instance data.
1028 *
1029 * Note! If you change members of this struct, make sure to check if the
1030 * assembly counterpart in HMInternal.mac needs to be updated as well.
1031 *
1032 * Note! The members here are ordered and aligned based on estimated frequency of
1033 * usage and grouped to fit within a cache line in hot code paths. Even subtle
1034 * changes here have a noticeable effect in the bootsector benchmarks. Modify with
1035 * care.
1036 */
1037typedef struct HMCPU
1038{
1039 /** Set when the TLB has been checked until we return from the world switch. */
1040 bool volatile fCheckedTLBFlush;
1041 /** Set when we're using VT-x or AMD-V at that moment.
1042 * @todo r=bird: Misleading description. For AMD-V this will be set the first
1043 * time HMCanExecuteGuest() is called and only cleared again by
1044 * HMR3ResetCpu(). For VT-x it will be set by HMCanExecuteGuest when we
1045 * can execute something in VT-x mode, and cleared if we cannot.
1046 *
1047 * The field is much more about recording the last HMCanExecuteGuest
1048 * return value than anything about any "moment". */
1049 bool fActive;
1050
1051 /** Whether we should use the debug loop because of single stepping or special
1052 * debug breakpoints / events are armed. */
1053 bool fUseDebugLoop;
1054
1055 /** Whether \#UD needs to be intercepted (required by certain GIM providers). */
1056 bool fGIMTrapXcptUD;
1057 /** Whether \#GP needs to be intercepted for mesa driver workaround. */
1058 bool fTrapXcptGpForLovelyMesaDrv;
1059 /** Whether we're executing a single instruction. */
1060 bool fSingleInstruction;
1061
1062 bool afAlignment0[2];
1063
1064 /** An additional error code used for some gurus. */
1065 uint32_t u32HMError;
1066 /** The last exit-to-ring-3 reason. */
1067 int32_t rcLastExitToR3;
1068 /** CPU-context changed flags (see HM_CHANGED_xxx). */
1069 uint64_t fCtxChanged;
1070
1071 /** VT-x data. */
1072 struct HMCPUVMX
1073 {
1074 /** @name Guest information.
1075 * @{ */
1076 /** Guest VMCS information shared with ring-3. */
1077 VMXVMCSINFOSHARED VmcsInfo;
1078 /** Nested-guest VMCS information shared with ring-3. */
1079 VMXVMCSINFOSHARED VmcsInfoNstGst;
1080 /** Whether the nested-guest VMCS was the last current VMCS (shadow copy for ring-3).
1081 * @see HMR0PERVCPU::vmx.fSwitchedToNstGstVmcs */
1082 bool fSwitchedToNstGstVmcsCopyForRing3;
1083 /** Whether the static guest VMCS controls has been merged with the
1084 * nested-guest VMCS controls. */
1085 bool fMergedNstGstCtls;
1086 /** Whether the nested-guest VMCS has been copied to the shadow VMCS. */
1087 bool fCopiedNstGstToShadowVmcs;
1088 /** Whether flushing the TLB is required due to switching to/from the
1089 * nested-guest. */
1090 bool fSwitchedNstGstFlushTlb;
1091 /** Alignment. */
1092 bool afAlignment0[4];
1093 /** Cached guest APIC-base MSR for identifying when to map the APIC-access page. */
1094 uint64_t u64GstMsrApicBase;
1095 /** @} */
1096
1097 /** @name Error reporting and diagnostics.
1098 * @{ */
1099 /** VT-x error-reporting (mainly for ring-3 propagation). */
1100 struct
1101 {
1102 RTCPUID idCurrentCpu;
1103 RTCPUID idEnteredCpu;
1104 RTHCPHYS HCPhysCurrentVmcs;
1105 uint32_t u32VmcsRev;
1106 uint32_t u32InstrError;
1107 uint32_t u32ExitReason;
1108 uint32_t u32GuestIntrState;
1109 } LastError;
1110 /** @} */
1111 } vmx;
1112
1113 /** SVM data. */
1114 struct HMCPUSVM
1115 {
1116 /** Whether to emulate long mode support for sysenter/sysexit like intel CPUs
1117 * does. This means intercepting \#UD to emulate the instructions in
1118 * long-mode and to intercept reads and writes to the SYSENTER MSRs in order to
1119 * preserve the upper 32 bits written to them (AMD will ignore and discard). */
1120 bool fEmulateLongModeSysEnterExit;
1121 uint8_t au8Alignment0[7];
1122
1123 /** Cache of the nested-guest's VMCB fields that we modify in order to run the
1124 * nested-guest using AMD-V. This will be restored on \#VMEXIT. */
1125 SVMNESTEDVMCBCACHE NstGstVmcbCache;
1126 } svm;
1127
1128 /** Event injection state. */
1129 HMEVENT Event;
1130
1131 /** Current shadow paging mode for updating CR4.
1132 * @todo move later (@bugref{9217}). */
1133 PGMMODE enmShadowMode;
1134 uint32_t u32TemporaryPadding;
1135
1136 /** The PAE PDPEs used with Nested Paging (only valid when
1137 * VMCPU_FF_HM_UPDATE_PAE_PDPES is set). */
1138 X86PDPE aPdpes[4];
1139
1140 /* These two comes because they are accessed from assembly and we don't
1141 want to detail all the stats in the assembly version of this structure. */
1142 STAMCOUNTER StatVmxWriteHostRip;
1143 STAMCOUNTER StatVmxWriteHostRsp;
1144 STAMCOUNTER StatVmxVmLaunch;
1145 STAMCOUNTER StatVmxVmResume;
1146
1147 STAMPROFILEADV StatEntry;
1148 STAMPROFILEADV StatPreExit;
1149 STAMPROFILEADV StatExitHandling;
1150 STAMPROFILEADV StatExitIO;
1151 STAMPROFILEADV StatExitMovCRx;
1152 STAMPROFILEADV StatExitXcptNmi;
1153 STAMPROFILEADV StatExitVmentry;
1154 STAMPROFILEADV StatImportGuestState;
1155 STAMPROFILEADV StatExportGuestState;
1156 STAMPROFILEADV StatLoadGuestFpuState;
1157 STAMPROFILEADV StatInGC;
1158 STAMPROFILEADV StatPoke;
1159 STAMPROFILEADV StatSpinPoke;
1160 STAMPROFILEADV StatSpinPokeFailed;
1161
1162 STAMCOUNTER StatInjectInterrupt;
1163 STAMCOUNTER StatInjectXcpt;
1164 STAMCOUNTER StatInjectReflect;
1165 STAMCOUNTER StatInjectConvertDF;
1166 STAMCOUNTER StatInjectInterpret;
1167 STAMCOUNTER StatInjectReflectNPF;
1168
1169 STAMCOUNTER StatExitAll;
1170 STAMCOUNTER StatNestedExitAll;
1171 STAMCOUNTER StatExitShadowNM;
1172 STAMCOUNTER StatExitGuestNM;
1173 STAMCOUNTER StatExitShadowPF; /**< Misleading, currently used for MMIO \#PFs as well. */
1174 STAMCOUNTER StatExitShadowPFEM;
1175 STAMCOUNTER StatExitGuestPF;
1176 STAMCOUNTER StatExitGuestUD;
1177 STAMCOUNTER StatExitGuestSS;
1178 STAMCOUNTER StatExitGuestNP;
1179 STAMCOUNTER StatExitGuestTS;
1180 STAMCOUNTER StatExitGuestOF;
1181 STAMCOUNTER StatExitGuestGP;
1182 STAMCOUNTER StatExitGuestDE;
1183 STAMCOUNTER StatExitGuestDF;
1184 STAMCOUNTER StatExitGuestBR;
1185 STAMCOUNTER StatExitGuestAC;
1186 STAMCOUNTER StatExitGuestDB;
1187 STAMCOUNTER StatExitGuestMF;
1188 STAMCOUNTER StatExitGuestBP;
1189 STAMCOUNTER StatExitGuestXF;
1190 STAMCOUNTER StatExitGuestXcpUnk;
1191 STAMCOUNTER StatExitDRxWrite;
1192 STAMCOUNTER StatExitDRxRead;
1193 STAMCOUNTER StatExitCR0Read;
1194 STAMCOUNTER StatExitCR2Read;
1195 STAMCOUNTER StatExitCR3Read;
1196 STAMCOUNTER StatExitCR4Read;
1197 STAMCOUNTER StatExitCR8Read;
1198 STAMCOUNTER StatExitCR0Write;
1199 STAMCOUNTER StatExitCR2Write;
1200 STAMCOUNTER StatExitCR3Write;
1201 STAMCOUNTER StatExitCR4Write;
1202 STAMCOUNTER StatExitCR8Write;
1203 STAMCOUNTER StatExitRdmsr;
1204 STAMCOUNTER StatExitWrmsr;
1205 STAMCOUNTER StatExitClts;
1206 STAMCOUNTER StatExitXdtrAccess;
1207 STAMCOUNTER StatExitLmsw;
1208 STAMCOUNTER StatExitIOWrite;
1209 STAMCOUNTER StatExitIORead;
1210 STAMCOUNTER StatExitIOStringWrite;
1211 STAMCOUNTER StatExitIOStringRead;
1212 STAMCOUNTER StatExitIntWindow;
1213 STAMCOUNTER StatExitExtInt;
1214 STAMCOUNTER StatExitHostNmiInGC;
1215 STAMCOUNTER StatExitHostNmiInGCIpi;
1216 STAMCOUNTER StatExitPreemptTimer;
1217 STAMCOUNTER StatExitTprBelowThreshold;
1218 STAMCOUNTER StatExitTaskSwitch;
1219 STAMCOUNTER StatExitApicAccess;
1220 STAMCOUNTER StatExitReasonNpf;
1221
1222 STAMCOUNTER StatNestedExitReasonNpf;
1223
1224 STAMCOUNTER StatFlushPage;
1225 STAMCOUNTER StatFlushPageManual;
1226 STAMCOUNTER StatFlushPhysPageManual;
1227 STAMCOUNTER StatFlushTlb;
1228 STAMCOUNTER StatFlushTlbNstGst;
1229 STAMCOUNTER StatFlushTlbManual;
1230 STAMCOUNTER StatFlushTlbWorldSwitch;
1231 STAMCOUNTER StatNoFlushTlbWorldSwitch;
1232 STAMCOUNTER StatFlushEntire;
1233 STAMCOUNTER StatFlushAsid;
1234 STAMCOUNTER StatFlushNestedPaging;
1235 STAMCOUNTER StatFlushTlbInvlpgVirt;
1236 STAMCOUNTER StatFlushTlbInvlpgPhys;
1237 STAMCOUNTER StatTlbShootdown;
1238 STAMCOUNTER StatTlbShootdownFlush;
1239
1240 STAMCOUNTER StatSwitchPendingHostIrq;
1241 STAMCOUNTER StatSwitchTprMaskedIrq;
1242 STAMCOUNTER StatSwitchGuestIrq;
1243 STAMCOUNTER StatSwitchHmToR3FF;
1244 STAMCOUNTER StatSwitchVmReq;
1245 STAMCOUNTER StatSwitchPgmPoolFlush;
1246 STAMCOUNTER StatSwitchDma;
1247 STAMCOUNTER StatSwitchExitToR3;
1248 STAMCOUNTER StatSwitchLongJmpToR3;
1249 STAMCOUNTER StatSwitchMaxResumeLoops;
1250 STAMCOUNTER StatSwitchHltToR3;
1251 STAMCOUNTER StatSwitchApicAccessToR3;
1252 STAMCOUNTER StatSwitchPreempt;
1253 STAMCOUNTER StatSwitchNstGstVmexit;
1254
1255 STAMCOUNTER StatTscParavirt;
1256 STAMCOUNTER StatTscOffset;
1257 STAMCOUNTER StatTscIntercept;
1258
1259 STAMCOUNTER StatDRxArmed;
1260 STAMCOUNTER StatDRxContextSwitch;
1261 STAMCOUNTER StatDRxIoCheck;
1262
1263 STAMCOUNTER StatExportMinimal;
1264 STAMCOUNTER StatExportFull;
1265 STAMCOUNTER StatLoadGuestFpu;
1266 STAMCOUNTER StatExportHostState;
1267
1268 STAMCOUNTER StatVmxCheckBadRmSelBase;
1269 STAMCOUNTER StatVmxCheckBadRmSelLimit;
1270 STAMCOUNTER StatVmxCheckBadRmSelAttr;
1271 STAMCOUNTER StatVmxCheckBadV86SelBase;
1272 STAMCOUNTER StatVmxCheckBadV86SelLimit;
1273 STAMCOUNTER StatVmxCheckBadV86SelAttr;
1274 STAMCOUNTER StatVmxCheckRmOk;
1275 STAMCOUNTER StatVmxCheckBadSel;
1276 STAMCOUNTER StatVmxCheckBadRpl;
1277 STAMCOUNTER StatVmxCheckPmOk;
1278
1279#ifdef VBOX_WITH_STATISTICS
1280 R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
1281 R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
1282 R3PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqs;
1283 R0PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqsR0;
1284 R3PTRTYPE(PSTAMCOUNTER) paStatInjectedXcpts;
1285 R0PTRTYPE(PSTAMCOUNTER) paStatInjectedXcptsR0;
1286 R3PTRTYPE(PSTAMCOUNTER) paStatNestedExitReason;
1287 R0PTRTYPE(PSTAMCOUNTER) paStatNestedExitReasonR0;
1288#endif
1289#ifdef HM_PROFILE_EXIT_DISPATCH
1290 STAMPROFILEADV StatExitDispatch;
1291#endif
1292} HMCPU;
1293/** Pointer to HM VMCPU instance data. */
1294typedef HMCPU *PHMCPU;
1295AssertCompileMemberAlignment(HMCPU, fCheckedTLBFlush, 4);
1296AssertCompileMemberAlignment(HMCPU, fCtxChanged, 8);
1297AssertCompileMemberAlignment(HMCPU, vmx, 8);
1298AssertCompileMemberAlignment(HMCPU, vmx.VmcsInfo, 8);
1299AssertCompileMemberAlignment(HMCPU, vmx.VmcsInfoNstGst, 8);
1300AssertCompileMemberAlignment(HMCPU, svm, 8);
1301AssertCompileMemberAlignment(HMCPU, Event, 8);
1302
1303
1304/**
1305 * HM per-VCpu ring-0 only instance data.
1306 */
1307typedef struct HMR0PERVCPU
1308{
1309 /** World switch exit counter. */
1310 uint32_t volatile cWorldSwitchExits;
1311 /** TLB flush count. */
1312 uint32_t cTlbFlushes;
1313 /** The last CPU we were executing code on (NIL_RTCPUID for the first time). */
1314 RTCPUID idLastCpu;
1315 /** The CPU ID of the CPU currently owning the VMCS. Set in
1316 * HMR0Enter and cleared in HMR0Leave. */
1317 RTCPUID idEnteredCpu;
1318 /** Current ASID in use by the VM. */
1319 uint32_t uCurrentAsid;
1320
1321 /** Set if we need to flush the TLB during the world switch. */
1322 bool fForceTLBFlush;
1323 /** Whether we've completed the inner HM leave function. */
1324 bool fLeaveDone;
1325 /** Whether we're using the hyper DR7 or guest DR7. */
1326 bool fUsingHyperDR7;
1327 /** Whether we are currently executing in the debug loop.
1328 * Mainly for assertions. */
1329 bool fUsingDebugLoop;
1330 /** Set if we using the debug loop and wish to intercept RDTSC. */
1331 bool fDebugWantRdTscExit;
1332 /** Set if XCR0 needs to be saved/restored when entering/exiting guest code
1333 * execution. */
1334 bool fLoadSaveGuestXcr0;
1335 /** Set if we need to clear the trap flag because of single stepping. */
1336 bool fClearTrapFlag;
1337
1338 bool afPadding1[1];
1339 /** World switcher flags (HM_WSF_XXX - was CPUMCTX::fWorldSwitcher in 6.1). */
1340 uint32_t fWorldSwitcher;
1341
1342 /** VT-x data. */
1343 struct HMR0CPUVMX
1344 {
1345 /** Ring-0 pointer to the hardware-assisted VMX execution function. */
1346 PFNHMVMXSTARTVM pfnStartVm;
1347
1348 /** @name Guest information.
1349 * @{ */
1350 /** Guest VMCS information. */
1351 VMXVMCSINFO VmcsInfo;
1352 /** Nested-guest VMCS information. */
1353 VMXVMCSINFO VmcsInfoNstGst;
1354 /* Whether the nested-guest VMCS was the last current VMCS (authoritative copy).
1355 * @see HMCPU::vmx.fSwitchedToNstGstVmcsCopyForRing3 */
1356 bool fSwitchedToNstGstVmcs;
1357 bool afAlignment0[7];
1358 /** @} */
1359
1360 /** @name Host information.
1361 * @{ */
1362 /** Host LSTAR MSR to restore lazily while leaving VT-x. */
1363 uint64_t u64HostMsrLStar;
1364 /** Host STAR MSR to restore lazily while leaving VT-x. */
1365 uint64_t u64HostMsrStar;
1366 /** Host SF_MASK MSR to restore lazily while leaving VT-x. */
1367 uint64_t u64HostMsrSfMask;
1368 /** Host KernelGS-Base MSR to restore lazily while leaving VT-x. */
1369 uint64_t u64HostMsrKernelGsBase;
1370 /** The mask of lazy MSRs swap/restore state, see VMX_LAZY_MSRS_XXX. */
1371 uint32_t fLazyMsrs;
1372 /** Whether the host MSR values are up-to-date in the auto-load/store MSR area. */
1373 bool fUpdatedHostAutoMsrs;
1374 /** Alignment. */
1375 uint8_t au8Alignment0[3];
1376 /** Which host-state bits to restore before being preempted, see
1377 * VMX_RESTORE_HOST_XXX. */
1378 uint32_t fRestoreHostFlags;
1379 /** Alignment. */
1380 uint32_t u32Alignment0;
1381 /** The host-state restoration structure. */
1382 VMXRESTOREHOST RestoreHost;
1383 /** @} */
1384 } vmx;
1385
1386 /** SVM data. */
1387 struct HMR0CPUSVM
1388 {
1389 /** Ring 0 handlers for VT-x. */
1390 PFNHMSVMVMRUN pfnVMRun;
1391
1392 /** Physical address of the host VMCB which holds additional host-state. */
1393 RTHCPHYS HCPhysVmcbHost;
1394 /** R0 memory object for the host VMCB which holds additional host-state. */
1395 RTR0MEMOBJ hMemObjVmcbHost;
1396
1397 /** Physical address of the guest VMCB. */
1398 RTHCPHYS HCPhysVmcb;
1399 /** R0 memory object for the guest VMCB. */
1400 RTR0MEMOBJ hMemObjVmcb;
1401 /** Pointer to the guest VMCB. */
1402 R0PTRTYPE(PSVMVMCB) pVmcb;
1403
1404 /** Physical address of the MSR bitmap (8 KB). */
1405 RTHCPHYS HCPhysMsrBitmap;
1406 /** R0 memory object for the MSR bitmap (8 KB). */
1407 RTR0MEMOBJ hMemObjMsrBitmap;
1408 /** Pointer to the MSR bitmap. */
1409 R0PTRTYPE(void *) pvMsrBitmap;
1410
1411 /** Whether VTPR with V_INTR_MASKING set is in effect, indicating
1412 * we should check if the VTPR changed on every VM-exit. */
1413 bool fSyncVTpr;
1414 bool afAlignment[7];
1415
1416 /** Host's TSC_AUX MSR (used when RDTSCP doesn't cause VM-exits). */
1417 uint64_t u64HostTscAux;
1418
1419 /** For saving stack space, the disassembler state is allocated here
1420 * instead of on the stack. */
1421 DISCPUSTATE DisState;
1422 } svm;
1423} HMR0PERVCPU;
1424/** Pointer to HM ring-0 VMCPU instance data. */
1425typedef HMR0PERVCPU *PHMR0PERVCPU;
1426AssertCompileMemberAlignment(HMR0PERVCPU, cWorldSwitchExits, 4);
1427AssertCompileMemberAlignment(HMR0PERVCPU, fForceTLBFlush, 4);
1428AssertCompileMemberAlignment(HMR0PERVCPU, vmx.RestoreHost, 8);
1429
1430
1431/** @name HM_WSF_XXX - @bugref{9453}, @bugref{9087}
1432 * @{ */
1433/** Touch IA32_PRED_CMD.IBPB on VM exit. */
1434#define HM_WSF_IBPB_EXIT RT_BIT_32(0)
1435/** Touch IA32_PRED_CMD.IBPB on VM entry. */
1436#define HM_WSF_IBPB_ENTRY RT_BIT_32(1)
1437/** Touch IA32_FLUSH_CMD.L1D on VM entry. */
1438#define HM_WSF_L1D_ENTRY RT_BIT_32(2)
1439/** Flush MDS buffers on VM entry. */
1440#define HM_WSF_MDS_ENTRY RT_BIT_32(3)
1441/** @} */
1442
1443
1444#ifdef IN_RING0
1445extern bool g_fHmVmxSupported;
1446extern bool g_fHmSvmSupported;
1447extern uint32_t g_uHmMaxAsid;
1448
1449VMMR0_INT_DECL(PHMPHYSCPU) hmR0GetCurrentCpu(void);
1450VMMR0_INT_DECL(int) hmR0EnterCpu(PVMCPUCC pVCpu);
1451
1452# ifdef VBOX_STRICT
1453# define HM_DUMP_REG_FLAGS_GPRS RT_BIT(0)
1454# define HM_DUMP_REG_FLAGS_FPU RT_BIT(1)
1455# define HM_DUMP_REG_FLAGS_MSRS RT_BIT(2)
1456# define HM_DUMP_REG_FLAGS_ALL (HM_DUMP_REG_FLAGS_GPRS | HM_DUMP_REG_FLAGS_FPU | HM_DUMP_REG_FLAGS_MSRS)
1457
1458VMMR0_INT_DECL(void) hmR0DumpRegs(PVMCPUCC pVCpu, uint32_t fFlags);
1459VMMR0_INT_DECL(void) hmR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg);
1460# endif
1461
1462DECLASM(void) hmR0MdsClear(void);
1463#endif /* IN_RING0 */
1464
1465
1466/** @addtogroup grp_hm_int_svm SVM Internal
1467 * @{ */
1468VMM_INT_DECL(int) hmEmulateSvmMovTpr(PVMCC pVM, PVMCPUCC pVCpu);
1469
1470/**
1471 * Prepares for and executes VMRUN (64-bit register context).
1472 *
1473 * @returns VBox status code (no informational stuff).
1474 * @param pVM The cross context VM structure. (Not used.)
1475 * @param pVCpu The cross context virtual CPU structure.
1476 * @param HCPhyspVMCB Physical address of the VMCB.
1477 *
1478 * @remarks With spectre mitigations and the usual need for speed (/ micro
1479 * optimizations), we have a bunch of variations of this code depending
1480 * on a few precoditions. In release builds, the code is entirely
1481 * without conditionals. Debug builds have a couple of assertions that
1482 * shouldn't ever be triggered.
1483 *
1484 * @{
1485 */
1486DECLASM(int) hmR0SvmVmRun_SansXcr0_SansIbpbEntry_SansIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1487DECLASM(int) hmR0SvmVmRun_WithXcr0_SansIbpbEntry_SansIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1488DECLASM(int) hmR0SvmVmRun_SansXcr0_WithIbpbEntry_SansIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1489DECLASM(int) hmR0SvmVmRun_WithXcr0_WithIbpbEntry_SansIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1490DECLASM(int) hmR0SvmVmRun_SansXcr0_SansIbpbEntry_WithIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1491DECLASM(int) hmR0SvmVmRun_WithXcr0_SansIbpbEntry_WithIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1492DECLASM(int) hmR0SvmVmRun_SansXcr0_WithIbpbEntry_WithIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1493DECLASM(int) hmR0SvmVmRun_WithXcr0_WithIbpbEntry_WithIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1494/** @} */
1495
1496/** @} */
1497
1498
1499/** @addtogroup grp_hm_int_vmx VMX Internal
1500 * @{ */
1501VMM_INT_DECL(PVMXVMCSINFOSHARED) hmGetVmxActiveVmcsInfoShared(PVMCPUCC pVCpu);
1502
1503/**
1504 * Used on platforms with poor inline assembly support to retrieve all the
1505 * info from the CPU and put it in the @a pRestoreHost structure.
1506 */
1507DECLASM(void) hmR0VmxExportHostSegmentRegsAsmHlp(PVMXRESTOREHOST pRestoreHost, bool fHaveFsGsBase);
1508
1509/**
1510 * Restores some host-state fields that need not be done on every VM-exit.
1511 *
1512 * @returns VBox status code.
1513 * @param fRestoreHostFlags Flags of which host registers needs to be
1514 * restored.
1515 * @param pRestoreHost Pointer to the host-restore structure.
1516 */
1517DECLASM(int) VMXRestoreHostState(uint32_t fRestoreHostFlags, PVMXRESTOREHOST pRestoreHost);
1518
1519/**
1520 * VMX StartVM functions.
1521 *
1522 * @returns VBox status code (no informational stuff).
1523 * @param pVM Pointer to the cross context VM structure.
1524 * @param pVCpu Pointer to the cross context per-CPU structure.
1525 * @param fResume Whether to use VMRESUME (true) or VMLAUNCH (false).
1526 *
1527 * @remarks With spectre mitigations and the usual need for speed (/ micro
1528 * optimizations), we have a bunch of variations of this code depending
1529 * on a few precoditions. In release builds, the code is entirely
1530 * without conditionals. Debug builds have a couple of assertions that
1531 * shouldn't ever be triggered.
1532 *
1533 * @{
1534 */
1535DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_SansL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1536DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_SansL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1537DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_SansL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1538DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_SansL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1539DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_WithL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1540DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_WithL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1541DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_WithL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1542DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_WithL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1543DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_SansL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1544DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_SansL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1545DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_SansL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1546DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_SansL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1547DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_WithL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1548DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_WithL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1549DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_WithL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1550DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_WithL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1551DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_SansL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1552DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_SansL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1553DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_SansL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1554DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_SansL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1555DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_WithL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1556DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_WithL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1557DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_WithL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1558DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_WithL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1559DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_SansL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1560DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_SansL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1561DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_SansL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1562DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_SansL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1563DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_WithL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1564DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_WithL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1565DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_WithL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1566DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_WithL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1567/** @} */
1568
1569/** @} */
1570
1571/** @} */
1572
1573RT_C_DECLS_END
1574
1575#endif /* !VMM_INCLUDED_SRC_include_HMInternal_h */
1576
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette