VirtualBox

source: vbox/trunk/src/VBox/VMM/include/HMInternal.h@ 87552

Last change on this file since 87552 was 87552, checked in by vboxsync, 4 years ago

VMM/HMVMX: Use g_uHmVmxHostMsrEfer instead of pVM->hm.s.vmx.u64HostMsrEfer in ring-0. bugref:9217
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1/* $Id: HMInternal.h 87552 2021-02-03 10:41:38Z vboxsync $ */
2/** @file
3 * HM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef VMM_INCLUDED_SRC_include_HMInternal_h
19#define VMM_INCLUDED_SRC_include_HMInternal_h
20#ifndef RT_WITHOUT_PRAGMA_ONCE
21# pragma once
22#endif
23
24#include <VBox/cdefs.h>
25#include <VBox/types.h>
26#include <VBox/vmm/stam.h>
27#include <VBox/dis.h>
28#include <VBox/vmm/hm.h>
29#include <VBox/vmm/hm_vmx.h>
30#include <VBox/vmm/hm_svm.h>
31#include <VBox/vmm/pgm.h>
32#include <VBox/vmm/cpum.h>
33#include <VBox/vmm/trpm.h>
34#include <iprt/memobj.h>
35#include <iprt/cpuset.h>
36#include <iprt/mp.h>
37#include <iprt/avl.h>
38#include <iprt/string.h>
39
40#if HC_ARCH_BITS == 32
41# error "32-bit hosts are no longer supported. Go back to 6.0 or earlier!"
42#endif
43
44/** @def HM_PROFILE_EXIT_DISPATCH
45 * Enables profiling of the VM exit handler dispatching. */
46#if 0 || defined(DOXYGEN_RUNNING)
47# define HM_PROFILE_EXIT_DISPATCH
48#endif
49
50RT_C_DECLS_BEGIN
51
52
53/** @defgroup grp_hm_int Internal
54 * @ingroup grp_hm
55 * @internal
56 * @{
57 */
58
59/** @name HM_CHANGED_XXX
60 * HM CPU-context changed flags.
61 *
62 * These flags are used to keep track of which registers and state has been
63 * modified since they were imported back into the guest-CPU context.
64 *
65 * @{
66 */
67#define HM_CHANGED_HOST_CONTEXT UINT64_C(0x0000000000000001)
68#define HM_CHANGED_GUEST_RIP UINT64_C(0x0000000000000004)
69#define HM_CHANGED_GUEST_RFLAGS UINT64_C(0x0000000000000008)
70
71#define HM_CHANGED_GUEST_RAX UINT64_C(0x0000000000000010)
72#define HM_CHANGED_GUEST_RCX UINT64_C(0x0000000000000020)
73#define HM_CHANGED_GUEST_RDX UINT64_C(0x0000000000000040)
74#define HM_CHANGED_GUEST_RBX UINT64_C(0x0000000000000080)
75#define HM_CHANGED_GUEST_RSP UINT64_C(0x0000000000000100)
76#define HM_CHANGED_GUEST_RBP UINT64_C(0x0000000000000200)
77#define HM_CHANGED_GUEST_RSI UINT64_C(0x0000000000000400)
78#define HM_CHANGED_GUEST_RDI UINT64_C(0x0000000000000800)
79#define HM_CHANGED_GUEST_R8_R15 UINT64_C(0x0000000000001000)
80#define HM_CHANGED_GUEST_GPRS_MASK UINT64_C(0x0000000000001ff0)
81
82#define HM_CHANGED_GUEST_ES UINT64_C(0x0000000000002000)
83#define HM_CHANGED_GUEST_CS UINT64_C(0x0000000000004000)
84#define HM_CHANGED_GUEST_SS UINT64_C(0x0000000000008000)
85#define HM_CHANGED_GUEST_DS UINT64_C(0x0000000000010000)
86#define HM_CHANGED_GUEST_FS UINT64_C(0x0000000000020000)
87#define HM_CHANGED_GUEST_GS UINT64_C(0x0000000000040000)
88#define HM_CHANGED_GUEST_SREG_MASK UINT64_C(0x000000000007e000)
89
90#define HM_CHANGED_GUEST_GDTR UINT64_C(0x0000000000080000)
91#define HM_CHANGED_GUEST_IDTR UINT64_C(0x0000000000100000)
92#define HM_CHANGED_GUEST_LDTR UINT64_C(0x0000000000200000)
93#define HM_CHANGED_GUEST_TR UINT64_C(0x0000000000400000)
94#define HM_CHANGED_GUEST_TABLE_MASK UINT64_C(0x0000000000780000)
95
96#define HM_CHANGED_GUEST_CR0 UINT64_C(0x0000000000800000)
97#define HM_CHANGED_GUEST_CR2 UINT64_C(0x0000000001000000)
98#define HM_CHANGED_GUEST_CR3 UINT64_C(0x0000000002000000)
99#define HM_CHANGED_GUEST_CR4 UINT64_C(0x0000000004000000)
100#define HM_CHANGED_GUEST_CR_MASK UINT64_C(0x0000000007800000)
101
102#define HM_CHANGED_GUEST_APIC_TPR UINT64_C(0x0000000008000000)
103#define HM_CHANGED_GUEST_EFER_MSR UINT64_C(0x0000000010000000)
104
105#define HM_CHANGED_GUEST_DR0_DR3 UINT64_C(0x0000000020000000)
106#define HM_CHANGED_GUEST_DR6 UINT64_C(0x0000000040000000)
107#define HM_CHANGED_GUEST_DR7 UINT64_C(0x0000000080000000)
108#define HM_CHANGED_GUEST_DR_MASK UINT64_C(0x00000000e0000000)
109
110#define HM_CHANGED_GUEST_X87 UINT64_C(0x0000000100000000)
111#define HM_CHANGED_GUEST_SSE_AVX UINT64_C(0x0000000200000000)
112#define HM_CHANGED_GUEST_OTHER_XSAVE UINT64_C(0x0000000400000000)
113#define HM_CHANGED_GUEST_XCRx UINT64_C(0x0000000800000000)
114
115#define HM_CHANGED_GUEST_KERNEL_GS_BASE UINT64_C(0x0000001000000000)
116#define HM_CHANGED_GUEST_SYSCALL_MSRS UINT64_C(0x0000002000000000)
117#define HM_CHANGED_GUEST_SYSENTER_CS_MSR UINT64_C(0x0000004000000000)
118#define HM_CHANGED_GUEST_SYSENTER_EIP_MSR UINT64_C(0x0000008000000000)
119#define HM_CHANGED_GUEST_SYSENTER_ESP_MSR UINT64_C(0x0000010000000000)
120#define HM_CHANGED_GUEST_SYSENTER_MSR_MASK UINT64_C(0x000001c000000000)
121#define HM_CHANGED_GUEST_TSC_AUX UINT64_C(0x0000020000000000)
122#define HM_CHANGED_GUEST_OTHER_MSRS UINT64_C(0x0000040000000000)
123#define HM_CHANGED_GUEST_ALL_MSRS ( HM_CHANGED_GUEST_EFER \
124 | HM_CHANGED_GUEST_KERNEL_GS_BASE \
125 | HM_CHANGED_GUEST_SYSCALL_MSRS \
126 | HM_CHANGED_GUEST_SYSENTER_MSR_MASK \
127 | HM_CHANGED_GUEST_TSC_AUX \
128 | HM_CHANGED_GUEST_OTHER_MSRS)
129
130#define HM_CHANGED_GUEST_HWVIRT UINT64_C(0x0000080000000000)
131#define HM_CHANGED_GUEST_MASK UINT64_C(0x00000ffffffffffc)
132
133#define HM_CHANGED_KEEPER_STATE_MASK UINT64_C(0xffff000000000000)
134
135#define HM_CHANGED_VMX_XCPT_INTERCEPTS UINT64_C(0x0001000000000000)
136#define HM_CHANGED_VMX_GUEST_AUTO_MSRS UINT64_C(0x0002000000000000)
137#define HM_CHANGED_VMX_GUEST_LAZY_MSRS UINT64_C(0x0004000000000000)
138#define HM_CHANGED_VMX_ENTRY_EXIT_CTLS UINT64_C(0x0008000000000000)
139#define HM_CHANGED_VMX_MASK UINT64_C(0x000f000000000000)
140#define HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE ( HM_CHANGED_GUEST_DR_MASK \
141 | HM_CHANGED_VMX_GUEST_LAZY_MSRS)
142
143#define HM_CHANGED_SVM_XCPT_INTERCEPTS UINT64_C(0x0001000000000000)
144#define HM_CHANGED_SVM_MASK UINT64_C(0x0001000000000000)
145#define HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE HM_CHANGED_GUEST_DR_MASK
146
147#define HM_CHANGED_ALL_GUEST ( HM_CHANGED_GUEST_MASK \
148 | HM_CHANGED_KEEPER_STATE_MASK)
149
150/** Mask of what state might have changed when IEM raised an exception.
151 * This is a based on IEM_CPUMCTX_EXTRN_XCPT_MASK. */
152#define HM_CHANGED_RAISED_XCPT_MASK ( HM_CHANGED_GUEST_GPRS_MASK \
153 | HM_CHANGED_GUEST_RIP \
154 | HM_CHANGED_GUEST_RFLAGS \
155 | HM_CHANGED_GUEST_SS \
156 | HM_CHANGED_GUEST_CS \
157 | HM_CHANGED_GUEST_CR0 \
158 | HM_CHANGED_GUEST_CR3 \
159 | HM_CHANGED_GUEST_CR4 \
160 | HM_CHANGED_GUEST_APIC_TPR \
161 | HM_CHANGED_GUEST_EFER_MSR \
162 | HM_CHANGED_GUEST_DR7 \
163 | HM_CHANGED_GUEST_CR2 \
164 | HM_CHANGED_GUEST_SREG_MASK \
165 | HM_CHANGED_GUEST_TABLE_MASK)
166
167#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
168/** Mask of what state might have changed when \#VMEXIT is emulated. */
169# define HM_CHANGED_SVM_VMEXIT_MASK ( HM_CHANGED_GUEST_RSP \
170 | HM_CHANGED_GUEST_RAX \
171 | HM_CHANGED_GUEST_RIP \
172 | HM_CHANGED_GUEST_RFLAGS \
173 | HM_CHANGED_GUEST_CS \
174 | HM_CHANGED_GUEST_SS \
175 | HM_CHANGED_GUEST_DS \
176 | HM_CHANGED_GUEST_ES \
177 | HM_CHANGED_GUEST_GDTR \
178 | HM_CHANGED_GUEST_IDTR \
179 | HM_CHANGED_GUEST_CR_MASK \
180 | HM_CHANGED_GUEST_EFER_MSR \
181 | HM_CHANGED_GUEST_DR6 \
182 | HM_CHANGED_GUEST_DR7 \
183 | HM_CHANGED_GUEST_OTHER_MSRS \
184 | HM_CHANGED_GUEST_HWVIRT \
185 | HM_CHANGED_SVM_MASK \
186 | HM_CHANGED_GUEST_APIC_TPR)
187
188/** Mask of what state might have changed when VMRUN is emulated. */
189# define HM_CHANGED_SVM_VMRUN_MASK HM_CHANGED_SVM_VMEXIT_MASK
190#endif
191#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
192/** Mask of what state might have changed when VM-exit is emulated.
193 *
194 * This is currently unused, but keeping it here in case we can get away a bit more
195 * fine-grained state handling.
196 *
197 * @note Update IEM_CPUMCTX_EXTRN_VMX_VMEXIT_MASK when this changes. */
198# define HM_CHANGED_VMX_VMEXIT_MASK ( HM_CHANGED_GUEST_CR0 | HM_CHANGED_GUEST_CR3 | HM_CHANGED_GUEST_CR4 \
199 | HM_CHANGED_GUEST_DR7 | HM_CHANGED_GUEST_DR6 \
200 | HM_CHANGED_GUEST_EFER_MSR \
201 | HM_CHANGED_GUEST_SYSENTER_MSR_MASK \
202 | HM_CHANGED_GUEST_OTHER_MSRS /* for PAT MSR */ \
203 | HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RSP | HM_CHANGED_GUEST_RFLAGS \
204 | HM_CHANGED_GUEST_SREG_MASK \
205 | HM_CHANGED_GUEST_TR \
206 | HM_CHANGED_GUEST_LDTR | HM_CHANGED_GUEST_GDTR | HM_CHANGED_GUEST_IDTR \
207 | HM_CHANGED_GUEST_HWVIRT )
208#endif
209/** @} */
210
211/** Maximum number of exit reason statistics counters. */
212#define MAX_EXITREASON_STAT 0x100
213#define MASK_EXITREASON_STAT 0xff
214#define MASK_INJECT_IRQ_STAT 0xff
215
216/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
217#define HM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
218/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
219#define HM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2 * PAGE_SIZE + 1)
220/** Total guest mapped memory needed. */
221#define HM_VTX_TOTAL_DEVHEAP_MEM (HM_EPT_IDENTITY_PG_TABLE_SIZE + HM_VTX_TSS_SIZE)
222
223
224/** @name Macros for enabling and disabling preemption.
225 * These are really just for hiding the RTTHREADPREEMPTSTATE and asserting that
226 * preemption has already been disabled when there is no context hook.
227 * @{ */
228#ifdef VBOX_STRICT
229# define HM_DISABLE_PREEMPT(a_pVCpu) \
230 RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
231 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD) || VMMR0ThreadCtxHookIsEnabled((a_pVCpu))); \
232 RTThreadPreemptDisable(&PreemptStateInternal)
233#else
234# define HM_DISABLE_PREEMPT(a_pVCpu) \
235 RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
236 RTThreadPreemptDisable(&PreemptStateInternal)
237#endif /* VBOX_STRICT */
238#define HM_RESTORE_PREEMPT() do { RTThreadPreemptRestore(&PreemptStateInternal); } while(0)
239/** @} */
240
241
242/** @name HM saved state versions.
243 * @{
244 */
245#define HM_SAVED_STATE_VERSION HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT
246#define HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT 6
247#define HM_SAVED_STATE_VERSION_TPR_PATCHING 5
248#define HM_SAVED_STATE_VERSION_NO_TPR_PATCHING 4
249#define HM_SAVED_STATE_VERSION_2_0_X 3
250/** @} */
251
252
253/**
254 * HM physical (host) CPU information.
255 */
256typedef struct HMPHYSCPU
257{
258 /** The CPU ID. */
259 RTCPUID idCpu;
260 /** The VM_HSAVE_AREA (AMD-V) / VMXON region (Intel) memory backing. */
261 RTR0MEMOBJ hMemObj;
262 /** The physical address of the first page in hMemObj (it's a
263 * physcially contigous allocation if it spans multiple pages). */
264 RTHCPHYS HCPhysMemObj;
265 /** The address of the memory (for pfnEnable). */
266 void *pvMemObj;
267 /** Current ASID (AMD-V) / VPID (Intel). */
268 uint32_t uCurrentAsid;
269 /** TLB flush count. */
270 uint32_t cTlbFlushes;
271 /** Whether to flush each new ASID/VPID before use. */
272 bool fFlushAsidBeforeUse;
273 /** Configured for VT-x or AMD-V. */
274 bool fConfigured;
275 /** Set if the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active. */
276 bool fIgnoreAMDVInUseError;
277 /** Whether CR4.VMXE was already enabled prior to us enabling it. */
278 bool fVmxeAlreadyEnabled;
279 /** In use by our code. (for power suspend) */
280 bool volatile fInUse;
281#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
282 /** Nested-guest union (put data common to SVM/VMX outside the union). */
283 union
284 {
285 /** Nested-guest SVM data. */
286 struct
287 {
288 /** The active nested-guest MSR permission bitmap memory backing. */
289 RTR0MEMOBJ hNstGstMsrpm;
290 /** The physical address of the first page in hNstGstMsrpm (physcially
291 * contiguous allocation). */
292 RTHCPHYS HCPhysNstGstMsrpm;
293 /** The address of the active nested-guest MSRPM. */
294 void *pvNstGstMsrpm;
295 } svm;
296 /** @todo Nested-VMX. */
297 } n;
298#endif
299} HMPHYSCPU;
300/** Pointer to HMPHYSCPU struct. */
301typedef HMPHYSCPU *PHMPHYSCPU;
302/** Pointer to a const HMPHYSCPU struct. */
303typedef const HMPHYSCPU *PCHMPHYSCPU;
304
305/**
306 * TPR-instruction type.
307 */
308typedef enum
309{
310 HMTPRINSTR_INVALID,
311 HMTPRINSTR_READ,
312 HMTPRINSTR_READ_SHR4,
313 HMTPRINSTR_WRITE_REG,
314 HMTPRINSTR_WRITE_IMM,
315 HMTPRINSTR_JUMP_REPLACEMENT,
316 /** The usual 32-bit paranoia. */
317 HMTPRINSTR_32BIT_HACK = 0x7fffffff
318} HMTPRINSTR;
319
320/**
321 * TPR patch information.
322 */
323typedef struct
324{
325 /** The key is the address of patched instruction. (32 bits GC ptr) */
326 AVLOU32NODECORE Core;
327 /** Original opcode. */
328 uint8_t aOpcode[16];
329 /** Instruction size. */
330 uint32_t cbOp;
331 /** Replacement opcode. */
332 uint8_t aNewOpcode[16];
333 /** Replacement instruction size. */
334 uint32_t cbNewOp;
335 /** Instruction type. */
336 HMTPRINSTR enmType;
337 /** Source operand. */
338 uint32_t uSrcOperand;
339 /** Destination operand. */
340 uint32_t uDstOperand;
341 /** Number of times the instruction caused a fault. */
342 uint32_t cFaults;
343 /** Patch address of the jump replacement. */
344 RTGCPTR32 pJumpTarget;
345} HMTPRPATCH;
346/** Pointer to HMTPRPATCH. */
347typedef HMTPRPATCH *PHMTPRPATCH;
348/** Pointer to a const HMTPRPATCH. */
349typedef const HMTPRPATCH *PCHMTPRPATCH;
350
351
352/**
353 * Makes a HMEXITSTAT::uKey value from a program counter and an exit code.
354 *
355 * @returns 64-bit key
356 * @param a_uPC The RIP + CS.BASE value of the exit.
357 * @param a_uExit The exit code.
358 * @todo Add CPL?
359 */
360#define HMEXITSTAT_MAKE_KEY(a_uPC, a_uExit) (((a_uPC) & UINT64_C(0x0000ffffffffffff)) | (uint64_t)(a_uExit) << 48)
361
362typedef struct HMEXITINFO
363{
364 /** See HMEXITSTAT_MAKE_KEY(). */
365 uint64_t uKey;
366 /** Number of recent hits (depreciates with time). */
367 uint32_t volatile cHits;
368 /** The age + lock. */
369 uint16_t volatile uAge;
370 /** Action or action table index. */
371 uint16_t iAction;
372} HMEXITINFO;
373AssertCompileSize(HMEXITINFO, 16); /* Lots of these guys, so don't add any unnecessary stuff! */
374
375typedef struct HMEXITHISTORY
376{
377 /** The exit timestamp. */
378 uint64_t uTscExit;
379 /** The index of the corresponding HMEXITINFO entry.
380 * UINT32_MAX if none (too many collisions, race, whatever). */
381 uint32_t iExitInfo;
382 /** Figure out later, needed for padding now. */
383 uint32_t uSomeClueOrSomething;
384} HMEXITHISTORY;
385
386/**
387 * Switcher function, HC to the special 64-bit RC.
388 *
389 * @param pVM The cross context VM structure.
390 * @param offCpumVCpu Offset from pVM->cpum to pVM->aCpus[idCpu].cpum.
391 * @returns Return code indicating the action to take.
392 */
393typedef DECLCALLBACKTYPE(int, FNHMSWITCHERHC,(PVM pVM, uint32_t offCpumVCpu));
394/** Pointer to switcher function. */
395typedef FNHMSWITCHERHC *PFNHMSWITCHERHC;
396
397
398/**
399 * HM event.
400 *
401 * VT-x and AMD-V common event injection structure.
402 */
403typedef struct HMEVENT
404{
405 /** Whether the event is pending. */
406 uint32_t fPending;
407 /** The error-code associated with the event. */
408 uint32_t u32ErrCode;
409 /** The length of the instruction in bytes (only relevant for software
410 * interrupts or software exceptions). */
411 uint32_t cbInstr;
412 /** Alignment. */
413 uint32_t u32Padding;
414 /** The encoded event (VM-entry interruption-information for VT-x or EVENTINJ
415 * for SVM). */
416 uint64_t u64IntInfo;
417 /** Guest virtual address if this is a page-fault event. */
418 RTGCUINTPTR GCPtrFaultAddress;
419} HMEVENT;
420/** Pointer to a HMEVENT struct. */
421typedef HMEVENT *PHMEVENT;
422/** Pointer to a const HMEVENT struct. */
423typedef const HMEVENT *PCHMEVENT;
424AssertCompileSizeAlignment(HMEVENT, 8);
425
426/**
427 * HM VM Instance data.
428 * Changes to this must checked against the padding of the hm union in VM!
429 */
430typedef struct HM
431{
432 /** Set if nested paging is enabled.
433 * Config value that is copied to HMR0PERVM::fNestedPaging on setup. */
434 bool fNestedPagingCfg;
435 /** Set when we've finalized the VMX / SVM initialization in ring-3
436 * (hmR3InitFinalizeR0Intel / hmR3InitFinalizeR0Amd). */
437 bool fInitialized;
438 /** Set if large pages are enabled (requires nested paging).
439 * Config only, passed on the PGM where it really belongs.
440 * @todo move to PGM */
441 bool fLargePages;
442 /** Set if we can support 64-bit guests or not.
443 * Config value that is copied to HMR0PERVM::fAllow64BitGuests on setup. */
444 bool fAllow64BitGuestsCfg;
445 /** Set when we initialize VT-x or AMD-V once for all CPUs. */
446 bool fGlobalInit;
447 /** Set when TPR patching is allowed. */
448 bool fTprPatchingAllowed;
449 /** Set when TPR patching is active. */
450 bool fTPRPatchingActive;
451 /** Set when the debug facility has breakpoints/events enabled that requires
452 * us to use the debug execution loop in ring-0. */
453 bool fUseDebugLoop;
454 /** Set if hardware APIC virtualization is enabled.
455 * @todo Not really used by HM, move to APIC where it's actually used. */
456 bool fVirtApicRegs;
457 /** Set if posted interrupt processing is enabled.
458 * @todo Not really used by HM, move to APIC where it's actually used. */
459 bool fPostedIntrs;
460
461 /** @name Processed into HMR0PERVCPU::fWorldSwitcher by ring-0 on VM init.
462 * @{ */
463 /** Set if indirect branch prediction barrier on VM exit. */
464 bool fIbpbOnVmExit;
465 /** Set if indirect branch prediction barrier on VM entry. */
466 bool fIbpbOnVmEntry;
467 /** Set if level 1 data cache should be flushed on VM entry. */
468 bool fL1dFlushOnVmEntry;
469 /** Set if level 1 data cache should be flushed on EMT scheduling. */
470 bool fL1dFlushOnSched;
471 /** Set if MDS related buffers should be cleared on VM entry. */
472 bool fMdsClearOnVmEntry;
473 /** Set if MDS related buffers should be cleared on EMT scheduling. */
474 bool fMdsClearOnSched;
475 /** Set if host manages speculation control settings.
476 * @todo doesn't do anything ... */
477 bool fSpecCtrlByHost;
478 /** @} */
479
480 /** Alignment padding. */
481 bool afPaddingMinus1[3];
482
483 /** The maximum number of resumes loops allowed in ring-0 (safety precaution).
484 * This number is set much higher when RTThreadPreemptIsPending is reliable. */
485 uint32_t cMaxResumeLoopsCfg;
486
487 struct
488 {
489 /** Set by the ring-0 side of HM to indicate VMX is supported by the CPU. */
490 bool fSupported;
491 /** Set when we've enabled VMX. */
492 bool fEnabled;
493 /** Set if VPID is supported (ring-3 copy). */
494 bool fVpidForRing3;
495 /** Set if VT-x VPID is allowed. */
496 bool fAllowVpid;
497 /** Set if unrestricted guest execution is in use (real and protected mode
498 * without paging). */
499 bool fUnrestrictedGuestCfg;
500 /** Set if the preemption timer should be used if available. Ring-0
501 * quietly clears this if the hardware doesn't support the preemption timer. */
502 bool fUsePreemptTimerCfg;
503 /** The shift mask employed by the VMX-Preemption timer (set by ring-0). */
504 uint8_t cPreemptTimerShift;
505 /** Padding. */
506 bool afPadding0[1];
507
508 /** Pause-loop exiting (PLE) gap in ticks. */
509 uint32_t cPleGapTicks;
510 /** Pause-loop exiting (PLE) window in ticks. */
511 uint32_t cPleWindowTicks;
512
513 /** Host CR4 value (set by ring-0 VMX init, for logging). */
514 uint64_t u64HostCr4;
515 /** Host SMM monitor control (set by ring-0 VMX init, for logging). */
516 uint64_t u64HostSmmMonitorCtl;
517 /** Host EFER value (set by ring-0 VMX init, for logging and guest NX). */
518 uint64_t u64HostMsrEfer;
519 /** Whether the CPU supports VMCS fields for swapping EFER. */
520 bool fSupportsVmcsEfer;
521 /** Whether to use VMCS shadowing. */
522 bool fUseVmcsShadowing;
523 /** Set if Last Branch Record (LBR) is enabled. */
524 bool fLbr;
525 uint8_t u8Alignment2[5];
526
527 /** The first valid host LBR branch-from-IP stack range. */
528 uint32_t idLbrFromIpMsrFirst;
529 /** The last valid host LBR branch-from-IP stack range. */
530 uint32_t idLbrFromIpMsrLast;
531
532 /** The first valid host LBR branch-to-IP stack range. */
533 uint32_t idLbrToIpMsrFirst;
534 /** The last valid host LBR branch-to-IP stack range. */
535 uint32_t idLbrToIpMsrLast;
536
537 /** The host LBR TOS (top-of-stack) MSR id. */
538 uint32_t idLbrTosMsr;
539 /** Padding. */
540 uint32_t u32Alignment1;
541
542 /** Host-physical address for a failing VMXON instruction (for diagnostics, ring-3). */
543 RTHCPHYS HCPhysVmxEnableError;
544 /** VMX MSR values (only for ring-3 consumption). */
545 VMXMSRS MsrsForRing3;
546 /** Tagged-TLB flush type (only for ring-3 consumption). */
547 VMXTLBFLUSHTYPE enmTlbFlushTypeForRing3;
548 /** Flush type to use for INVEPT (only for ring-3 consumption). */
549 VMXTLBFLUSHEPT enmTlbFlushEptForRing3;
550 /** Flush type to use for INVVPID (only for ring-3 consumption). */
551 VMXTLBFLUSHVPID enmTlbFlushVpidForRing3;
552 uint32_t u32Alignment2;
553
554 /** Virtual address of the TSS page used for real mode emulation. */
555 R3PTRTYPE(PVBOXTSS) pRealModeTSS;
556 /** Virtual address of the identity page table used for real mode and protected
557 * mode without paging emulation in EPT mode. */
558 R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
559 } vmx;
560
561 struct
562 {
563 /** Set by the ring-0 side of HM to indicate SVM is supported by the CPU. */
564 bool fSupported;
565 /** Set when we've enabled SVM. */
566 bool fEnabled;
567 /** Set when the hack to ignore VERR_SVM_IN_USE is active.
568 * @todo Safe? */
569 bool fIgnoreInUseError;
570 /** Whether to use virtualized VMSAVE/VMLOAD feature. */
571 bool fVirtVmsaveVmload;
572 /** Whether to use virtual GIF feature. */
573 bool fVGif;
574 /** Whether to use LBR virtualization feature. */
575 bool fLbrVirt;
576 uint8_t u8Alignment0[2];
577
578 /** HWCR MSR (for diagnostics). */
579 uint64_t u64MsrHwcr;
580
581 /** SVM revision. */
582 uint32_t u32Rev;
583 /** SVM feature bits from cpuid 0x8000000a, ring-3 copy. */
584 uint32_t fFeaturesForRing3;
585
586 /** Pause filter counter. */
587 uint16_t cPauseFilter;
588 /** Pause filter treshold in ticks. */
589 uint16_t cPauseFilterThresholdTicks;
590 uint32_t u32Alignment0;
591 } svm;
592
593 /** AVL tree with all patches (active or disabled) sorted by guest instruction address.
594 * @todo For @bugref{9217} this AVL tree must be eliminated and instead
595 * sort aPatches by address and do a safe binary search on it. */
596 AVLOU32TREE PatchTree;
597 uint32_t cPatches;
598 HMTPRPATCH aPatches[64];
599
600 /** Guest allocated memory for patching purposes. */
601 RTGCPTR pGuestPatchMem;
602 /** Current free pointer inside the patch block. */
603 RTGCPTR pFreeGuestPatchMem;
604 /** Size of the guest patch memory block. */
605 uint32_t cbGuestPatchMem;
606
607 /** Last recorded error code during HM ring-0 init. */
608 int32_t rcInit;
609 /** Maximum ASID allowed.
610 * This is mainly for the release log. */
611 uint32_t uMaxAsidForLog;
612 /** World switcher flags (HM_WSF_XXX) for the release log. */
613 uint32_t fWorldSwitcherForLog;
614
615 STAMCOUNTER StatTprPatchSuccess;
616 STAMCOUNTER StatTprPatchFailure;
617 STAMCOUNTER StatTprReplaceSuccessCr8;
618 STAMCOUNTER StatTprReplaceSuccessVmc;
619 STAMCOUNTER StatTprReplaceFailure;
620} HM;
621/** Pointer to HM VM instance data. */
622typedef HM *PHM;
623AssertCompileMemberAlignment(HM, StatTprPatchSuccess, 8);
624AssertCompileMemberAlignment(HM, vmx, 8);
625AssertCompileMemberAlignment(HM, svm, 8);
626
627
628/**
629 * Per-VM ring-0 instance data for HM.
630 */
631typedef struct HMR0PERVM
632{
633 /** Set if nested paging is enabled. */
634 bool fNestedPaging;
635 /** Set if we can support 64-bit guests or not. */
636 bool fAllow64BitGuests;
637 bool afAlignment0[2];
638
639 /** The maximum number of resumes loops allowed in ring-0 (safety precaution).
640 * This number is set much higher when RTThreadPreemptIsPending is reliable. */
641 uint32_t cMaxResumeLoops;
642
643 /** VT-x specific data. */
644 struct HMR0VMXVM
645 {
646 /** Set if unrestricted guest execution is in use (real and protected mode
647 * without paging). */
648 bool fUnrestrictedGuest;
649 /** Set if the preemption timer is in use. */
650 bool fUsePreemptTimer;
651 bool afAlignment1[2];
652 /** Set if VPID is supported (copy in HM::vmx::fVpidForRing3). */
653 bool fVpid;
654 /** Tagged-TLB flush type. */
655 VMXTLBFLUSHTYPE enmTlbFlushType;
656 /** Flush type to use for INVEPT. */
657 VMXTLBFLUSHEPT enmTlbFlushEpt;
658 /** Flush type to use for INVVPID. */
659 VMXTLBFLUSHVPID enmTlbFlushVpid;
660
661 /** Virtual address of the APIC-access page. */
662 R0PTRTYPE(uint8_t *) pbApicAccess;
663 /** Pointer to the VMREAD bitmap. */
664 R0PTRTYPE(void *) pvVmreadBitmap;
665 /** Pointer to the VMWRITE bitmap. */
666 R0PTRTYPE(void *) pvVmwriteBitmap;
667
668 /** Pointer to the shadow VMCS read-only fields array. */
669 R0PTRTYPE(uint32_t *) paShadowVmcsRoFields;
670 /** Pointer to the shadow VMCS read/write fields array. */
671 R0PTRTYPE(uint32_t *) paShadowVmcsFields;
672 /** Number of elements in the shadow VMCS read-only fields array. */
673 uint32_t cShadowVmcsRoFields;
674 /** Number of elements in the shadow VMCS read-write fields array. */
675 uint32_t cShadowVmcsFields;
676
677 /** Host-physical address of the APIC-access page. */
678 RTHCPHYS HCPhysApicAccess;
679 /** Host-physical address of the VMREAD bitmap. */
680 RTHCPHYS HCPhysVmreadBitmap;
681 /** Host-physical address of the VMWRITE bitmap. */
682 RTHCPHYS HCPhysVmwriteBitmap;
683
684#ifdef VBOX_WITH_CRASHDUMP_MAGIC
685 /** Host-physical address of the crash-dump scratch area. */
686 RTHCPHYS HCPhysScratch;
687 /** Pointer to the crash-dump scratch bitmap. */
688 R0PTRTYPE(uint8_t *) pbScratch;
689#endif
690
691 /** Ring-0 memory object for per-VM VMX structures. */
692 RTR0MEMOBJ hMemObj;
693 } vmx;
694
695 /** AMD-V specific data. */
696 struct HMR0SVMVM
697 {
698 /** Set if erratum 170 affects the AMD cpu. */
699 bool fAlwaysFlushTLB;
700 bool afAlignment0[3];
701 } svm;
702} HMR0PERVM;
703/** Pointer to HM's per-VM ring-0 instance data. */
704typedef HMR0PERVM *PHMR0PERVM;
705
706
707/** @addtogroup grp_hm_int_svm SVM Internal
708 * @{ */
709/** SVM VMRun function, see SVMR0VMRun(). */
710typedef DECLCALLBACKTYPE(int, FNHMSVMVMRUN,(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhysVMCB));
711/** Pointer to a SVM VMRun function. */
712typedef R0PTRTYPE(FNHMSVMVMRUN *) PFNHMSVMVMRUN;
713
714/**
715 * SVM nested-guest VMCB cache.
716 *
717 * Contains VMCB fields from the nested-guest VMCB before they're modified by
718 * SVM R0 code for hardware-assisted SVM execution of a nested-guest.
719 *
720 * A VMCB field needs to be cached when it needs to be modified for execution using
721 * hardware-assisted SVM and any of the following are true:
722 * - If the original field needs to be inspected during execution of the
723 * nested-guest or \#VMEXIT processing.
724 * - If the field is written back to memory on \#VMEXIT by the physical CPU.
725 *
726 * A VMCB field needs to be restored only when the field is written back to
727 * memory on \#VMEXIT by the physical CPU and thus would be visible to the
728 * guest.
729 *
730 * @remarks Please update hmR3InfoSvmNstGstVmcbCache() when changes are made to
731 * this structure.
732 */
733typedef struct SVMNESTEDVMCBCACHE
734{
735 /** Cache of CRX read intercepts. */
736 uint16_t u16InterceptRdCRx;
737 /** Cache of CRX write intercepts. */
738 uint16_t u16InterceptWrCRx;
739 /** Cache of DRX read intercepts. */
740 uint16_t u16InterceptRdDRx;
741 /** Cache of DRX write intercepts. */
742 uint16_t u16InterceptWrDRx;
743
744 /** Cache of the pause-filter threshold. */
745 uint16_t u16PauseFilterThreshold;
746 /** Cache of the pause-filter count. */
747 uint16_t u16PauseFilterCount;
748
749 /** Cache of exception intercepts. */
750 uint32_t u32InterceptXcpt;
751 /** Cache of control intercepts. */
752 uint64_t u64InterceptCtrl;
753
754 /** Cache of the TSC offset. */
755 uint64_t u64TSCOffset;
756
757 /** Cache of V_INTR_MASKING bit. */
758 bool fVIntrMasking;
759 /** Cache of the nested-paging bit. */
760 bool fNestedPaging;
761 /** Cache of the LBR virtualization bit. */
762 bool fLbrVirt;
763 /** Whether the VMCB is cached by HM. */
764 bool fCacheValid;
765 /** Alignment. */
766 bool afPadding0[4];
767} SVMNESTEDVMCBCACHE;
768/** Pointer to the SVMNESTEDVMCBCACHE structure. */
769typedef SVMNESTEDVMCBCACHE *PSVMNESTEDVMCBCACHE;
770/** Pointer to a const SVMNESTEDVMCBCACHE structure. */
771typedef const SVMNESTEDVMCBCACHE *PCSVMNESTEDVMCBCACHE;
772AssertCompileSizeAlignment(SVMNESTEDVMCBCACHE, 8);
773
774/** @} */
775
776
777/** @addtogroup grp_hm_int_vmx VMX Internal
778 * @{ */
779/**
780 * VMX VMCS information, shared.
781 *
782 * This structure provides information maintained for and during the executing of a
783 * guest (or nested-guest) VMCS (VM control structure) using hardware-assisted VMX.
784 *
785 * Note! The members here are ordered and aligned based on estimated frequency of
786 * usage and grouped to fit within a cache line in hot code paths. Even subtle
787 * changes here have a noticeable effect in the bootsector benchmarks. Modify with
788 * care.
789 */
790typedef struct VMXVMCSINFOSHARED
791{
792 /** @name Real-mode emulation state.
793 * @{ */
794 /** Set if guest was executing in real mode (extra checks). */
795 bool fWasInRealMode;
796 /** Padding. */
797 bool afPadding0[7];
798 struct
799 {
800 X86DESCATTR AttrCS;
801 X86DESCATTR AttrDS;
802 X86DESCATTR AttrES;
803 X86DESCATTR AttrFS;
804 X86DESCATTR AttrGS;
805 X86DESCATTR AttrSS;
806 X86EFLAGS Eflags;
807 bool fRealOnV86Active;
808 bool afPadding1[3];
809 } RealMode;
810 /** @} */
811
812 /** @name LBR MSR data.
813 * @{ */
814 /** List of LastBranch-From-IP MSRs. */
815 uint64_t au64LbrFromIpMsr[32];
816 /** List of LastBranch-To-IP MSRs. */
817 uint64_t au64LbrToIpMsr[32];
818 /** The MSR containing the index to the most recent branch record. */
819 uint64_t u64LbrTosMsr;
820 /** @} */
821} VMXVMCSINFOSHARED;
822/** Pointer to a VMXVMCSINFOSHARED struct. */
823typedef VMXVMCSINFOSHARED *PVMXVMCSINFOSHARED;
824/** Pointer to a const VMXVMCSINFOSHARED struct. */
825typedef const VMXVMCSINFOSHARED *PCVMXVMCSINFOSHARED;
826AssertCompileSizeAlignment(VMXVMCSINFOSHARED, 8);
827
828
829/**
830 * VMX VMCS information, ring-0 only.
831 *
832 * This structure provides information maintained for and during the executing of a
833 * guest (or nested-guest) VMCS (VM control structure) using hardware-assisted VMX.
834 *
835 * Note! The members here are ordered and aligned based on estimated frequency of
836 * usage and grouped to fit within a cache line in hot code paths. Even subtle
837 * changes here have a noticeable effect in the bootsector benchmarks. Modify with
838 * care.
839 */
840typedef struct VMXVMCSINFO
841{
842 /** Pointer to the bits we share with ring-3. */
843 R0PTRTYPE(PVMXVMCSINFOSHARED) pShared;
844
845 /** @name Auxiliary information.
846 * @{ */
847 /** Host-physical address of the EPTP. */
848 RTHCPHYS HCPhysEPTP;
849 /** The VMCS launch state, see VMX_V_VMCS_LAUNCH_STATE_XXX. */
850 uint32_t fVmcsState;
851 /** The VMCS launch state of the shadow VMCS, see VMX_V_VMCS_LAUNCH_STATE_XXX. */
852 uint32_t fShadowVmcsState;
853 /** The host CPU for which its state has been exported to this VMCS. */
854 RTCPUID idHostCpuState;
855 /** The host CPU on which we last executed this VMCS. */
856 RTCPUID idHostCpuExec;
857 /** Number of guest MSRs in the VM-entry MSR-load area. */
858 uint32_t cEntryMsrLoad;
859 /** Number of guest MSRs in the VM-exit MSR-store area. */
860 uint32_t cExitMsrStore;
861 /** Number of host MSRs in the VM-exit MSR-load area. */
862 uint32_t cExitMsrLoad;
863 /** @} */
864
865 /** @name Cache of execution related VMCS fields.
866 * @{ */
867 /** Pin-based VM-execution controls. */
868 uint32_t u32PinCtls;
869 /** Processor-based VM-execution controls. */
870 uint32_t u32ProcCtls;
871 /** Secondary processor-based VM-execution controls. */
872 uint32_t u32ProcCtls2;
873 /** VM-entry controls. */
874 uint32_t u32EntryCtls;
875 /** VM-exit controls. */
876 uint32_t u32ExitCtls;
877 /** Exception bitmap. */
878 uint32_t u32XcptBitmap;
879 /** Page-fault exception error-code mask. */
880 uint32_t u32XcptPFMask;
881 /** Page-fault exception error-code match. */
882 uint32_t u32XcptPFMatch;
883 /** Padding. */
884 uint32_t u32Alignment0;
885 /** TSC offset. */
886 uint64_t u64TscOffset;
887 /** VMCS link pointer. */
888 uint64_t u64VmcsLinkPtr;
889 /** CR0 guest/host mask. */
890 uint64_t u64Cr0Mask;
891 /** CR4 guest/host mask. */
892 uint64_t u64Cr4Mask;
893 /** Current VMX_VMCS_HOST_RIP value (only used in HMR0A.asm). */
894 uint64_t uHostRip;
895 /** Current VMX_VMCS_HOST_RSP value (only used in HMR0A.asm). */
896 uint64_t uHostRsp;
897 /** @} */
898
899 /** @name Host-virtual address of VMCS and related data structures.
900 * @{ */
901 /** The VMCS. */
902 R0PTRTYPE(void *) pvVmcs;
903 /** The shadow VMCS. */
904 R0PTRTYPE(void *) pvShadowVmcs;
905 /** The virtual-APIC page. */
906 R0PTRTYPE(uint8_t *) pbVirtApic;
907 /** The MSR bitmap. */
908 R0PTRTYPE(void *) pvMsrBitmap;
909 /** The VM-entry MSR-load area. */
910 R0PTRTYPE(void *) pvGuestMsrLoad;
911 /** The VM-exit MSR-store area. */
912 R0PTRTYPE(void *) pvGuestMsrStore;
913 /** The VM-exit MSR-load area. */
914 R0PTRTYPE(void *) pvHostMsrLoad;
915 /** @} */
916
917 /** @name Host-physical address of VMCS and related data structures.
918 * @{ */
919 /** The VMCS. */
920 RTHCPHYS HCPhysVmcs;
921 /** The shadow VMCS. */
922 RTHCPHYS HCPhysShadowVmcs;
923 /** The virtual APIC page. */
924 RTHCPHYS HCPhysVirtApic;
925 /** The MSR bitmap. */
926 RTHCPHYS HCPhysMsrBitmap;
927 /** The VM-entry MSR-load area. */
928 RTHCPHYS HCPhysGuestMsrLoad;
929 /** The VM-exit MSR-store area. */
930 RTHCPHYS HCPhysGuestMsrStore;
931 /** The VM-exit MSR-load area. */
932 RTHCPHYS HCPhysHostMsrLoad;
933 /** @} */
934
935 /** @name R0-memory objects address for VMCS and related data structures.
936 * @{ */
937 /** R0-memory object for VMCS and related data structures. */
938 RTR0MEMOBJ hMemObj;
939 /** @} */
940} VMXVMCSINFO;
941/** Pointer to a VMXVMCSINFOR0 struct. */
942typedef VMXVMCSINFO *PVMXVMCSINFO;
943/** Pointer to a const VMXVMCSINFO struct. */
944typedef const VMXVMCSINFO *PCVMXVMCSINFO;
945AssertCompileSizeAlignment(VMXVMCSINFO, 8);
946AssertCompileMemberAlignment(VMXVMCSINFO, u32PinCtls, 4);
947AssertCompileMemberAlignment(VMXVMCSINFO, u64VmcsLinkPtr, 8);
948AssertCompileMemberAlignment(VMXVMCSINFO, pvVmcs, 8);
949AssertCompileMemberAlignment(VMXVMCSINFO, pvShadowVmcs, 8);
950AssertCompileMemberAlignment(VMXVMCSINFO, pbVirtApic, 8);
951AssertCompileMemberAlignment(VMXVMCSINFO, pvMsrBitmap, 8);
952AssertCompileMemberAlignment(VMXVMCSINFO, pvGuestMsrLoad, 8);
953AssertCompileMemberAlignment(VMXVMCSINFO, pvGuestMsrStore, 8);
954AssertCompileMemberAlignment(VMXVMCSINFO, pvHostMsrLoad, 8);
955AssertCompileMemberAlignment(VMXVMCSINFO, HCPhysVmcs, 8);
956AssertCompileMemberAlignment(VMXVMCSINFO, hMemObj, 8);
957
958
959/** @name Host-state restoration flags.
960 * @note If you change these values don't forget to update the assembly
961 * defines as well!
962 * @{
963 */
964#define VMX_RESTORE_HOST_SEL_DS RT_BIT(0)
965#define VMX_RESTORE_HOST_SEL_ES RT_BIT(1)
966#define VMX_RESTORE_HOST_SEL_FS RT_BIT(2)
967#define VMX_RESTORE_HOST_SEL_GS RT_BIT(3)
968#define VMX_RESTORE_HOST_SEL_TR RT_BIT(4)
969#define VMX_RESTORE_HOST_GDTR RT_BIT(5)
970#define VMX_RESTORE_HOST_IDTR RT_BIT(6)
971#define VMX_RESTORE_HOST_GDT_READ_ONLY RT_BIT(7)
972#define VMX_RESTORE_HOST_GDT_NEED_WRITABLE RT_BIT(8)
973#define VMX_RESTORE_HOST_CAN_USE_WRFSBASE_AND_WRGSBASE RT_BIT(9)
974/**
975 * This _must_ be the top most bit, so that we can easily that that it and
976 * something else is set w/o having to do two checks like this:
977 * @code
978 * if ( (pVCpu->hm.s.vmx.fRestoreHostFlags & VMX_RESTORE_HOST_REQUIRED)
979 * && (pVCpu->hm.s.vmx.fRestoreHostFlags & ~VMX_RESTORE_HOST_REQUIRED))
980 * @endcode
981 * Instead we can then do:
982 * @code
983 * if (pVCpu->hm.s.vmx.fRestoreHostFlags > VMX_RESTORE_HOST_REQUIRED)
984 * @endcode
985 */
986#define VMX_RESTORE_HOST_REQUIRED RT_BIT(10)
987/** @} */
988
989/**
990 * Host-state restoration structure.
991 *
992 * This holds host-state fields that require manual restoration.
993 * Assembly version found in HMInternal.mac (should be automatically verified).
994 */
995typedef struct VMXRESTOREHOST
996{
997 RTSEL uHostSelDS; /**< 0x00 */
998 RTSEL uHostSelES; /**< 0x02 */
999 RTSEL uHostSelFS; /**< 0x04 */
1000 X86XDTR64 HostGdtr; /**< 0x06 - should be aligned by its 64-bit member. */
1001 RTSEL uHostSelGS; /**< 0x10 */
1002 RTSEL uHostSelTR; /**< 0x12 */
1003 RTSEL uHostSelSS; /**< 0x14 - not restored, just for fetching */
1004 X86XDTR64 HostGdtrRw; /**< 0x16 - should be aligned by its 64-bit member. */
1005 RTSEL uHostSelCS; /**< 0x20 - not restored, just for fetching */
1006 uint8_t abPadding1[4]; /**< 0x22 */
1007 X86XDTR64 HostIdtr; /**< 0x26 - should be aligned by its 64-bit member. */
1008 uint64_t uHostFSBase; /**< 0x30 */
1009 uint64_t uHostGSBase; /**< 0x38 */
1010} VMXRESTOREHOST;
1011/** Pointer to VMXRESTOREHOST. */
1012typedef VMXRESTOREHOST *PVMXRESTOREHOST;
1013AssertCompileSize(X86XDTR64, 10);
1014AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtr.uAddr, 0x08);
1015AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtrRw.uAddr, 0x18);
1016AssertCompileMemberOffset(VMXRESTOREHOST, HostIdtr.uAddr, 0x28);
1017AssertCompileMemberOffset(VMXRESTOREHOST, uHostFSBase, 0x30);
1018AssertCompileSize(VMXRESTOREHOST, 64);
1019AssertCompileSizeAlignment(VMXRESTOREHOST, 8);
1020
1021/**
1022 * VMX StartVM function.
1023 *
1024 * @returns VBox status code (no informational stuff).
1025 * @param pVmcsInfo Pointer to the VMCS info (for cached host RIP and RSP).
1026 * @param pVCpu Pointer to the cross context per-CPU structure.
1027 * @param fResume Whether to use VMRESUME (true) or VMLAUNCH (false).
1028 */
1029typedef DECLCALLBACKTYPE(int, FNHMVMXSTARTVM,(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume));
1030/** Pointer to a VMX StartVM function. */
1031typedef R0PTRTYPE(FNHMVMXSTARTVM *) PFNHMVMXSTARTVM;
1032/** @} */
1033
1034/**
1035 * HM VMCPU Instance data.
1036 *
1037 * Note! If you change members of this struct, make sure to check if the
1038 * assembly counterpart in HMInternal.mac needs to be updated as well.
1039 *
1040 * Note! The members here are ordered and aligned based on estimated frequency of
1041 * usage and grouped to fit within a cache line in hot code paths. Even subtle
1042 * changes here have a noticeable effect in the bootsector benchmarks. Modify with
1043 * care.
1044 */
1045typedef struct HMCPU
1046{
1047 /** Set when the TLB has been checked until we return from the world switch. */
1048 bool volatile fCheckedTLBFlush;
1049 /** Set when we're using VT-x or AMD-V at that moment.
1050 * @todo r=bird: Misleading description. For AMD-V this will be set the first
1051 * time HMCanExecuteGuest() is called and only cleared again by
1052 * HMR3ResetCpu(). For VT-x it will be set by HMCanExecuteGuest when we
1053 * can execute something in VT-x mode, and cleared if we cannot.
1054 *
1055 * The field is much more about recording the last HMCanExecuteGuest
1056 * return value than anything about any "moment". */
1057 bool fActive;
1058
1059 /** Whether we should use the debug loop because of single stepping or special
1060 * debug breakpoints / events are armed. */
1061 bool fUseDebugLoop;
1062
1063 /** Whether \#UD needs to be intercepted (required by certain GIM providers). */
1064 bool fGIMTrapXcptUD;
1065 /** Whether \#GP needs to be intercepted for mesa driver workaround. */
1066 bool fTrapXcptGpForLovelyMesaDrv;
1067 /** Whether we're executing a single instruction. */
1068 bool fSingleInstruction;
1069
1070 bool afAlignment0[2];
1071
1072 /** An additional error code used for some gurus. */
1073 uint32_t u32HMError;
1074 /** The last exit-to-ring-3 reason. */
1075 int32_t rcLastExitToR3;
1076 /** CPU-context changed flags (see HM_CHANGED_xxx). */
1077 uint64_t fCtxChanged;
1078
1079 /** VT-x data. */
1080 struct HMCPUVMX
1081 {
1082 /** @name Guest information.
1083 * @{ */
1084 /** Guest VMCS information shared with ring-3. */
1085 VMXVMCSINFOSHARED VmcsInfo;
1086 /** Nested-guest VMCS information shared with ring-3. */
1087 VMXVMCSINFOSHARED VmcsInfoNstGst;
1088 /** Whether the nested-guest VMCS was the last current VMCS (shadow copy for ring-3).
1089 * @see HMR0PERVCPU::vmx.fSwitchedToNstGstVmcs */
1090 bool fSwitchedToNstGstVmcsCopyForRing3;
1091 /** Whether the static guest VMCS controls has been merged with the
1092 * nested-guest VMCS controls. */
1093 bool fMergedNstGstCtls;
1094 /** Whether the nested-guest VMCS has been copied to the shadow VMCS. */
1095 bool fCopiedNstGstToShadowVmcs;
1096 /** Whether flushing the TLB is required due to switching to/from the
1097 * nested-guest. */
1098 bool fSwitchedNstGstFlushTlb;
1099 /** Alignment. */
1100 bool afAlignment0[4];
1101 /** Cached guest APIC-base MSR for identifying when to map the APIC-access page. */
1102 uint64_t u64GstMsrApicBase;
1103 /** @} */
1104
1105 /** @name Error reporting and diagnostics.
1106 * @{ */
1107 /** VT-x error-reporting (mainly for ring-3 propagation). */
1108 struct
1109 {
1110 RTCPUID idCurrentCpu;
1111 RTCPUID idEnteredCpu;
1112 RTHCPHYS HCPhysCurrentVmcs;
1113 uint32_t u32VmcsRev;
1114 uint32_t u32InstrError;
1115 uint32_t u32ExitReason;
1116 uint32_t u32GuestIntrState;
1117 } LastError;
1118 /** @} */
1119 } vmx;
1120
1121 /** SVM data. */
1122 struct HMCPUSVM
1123 {
1124 /** Whether to emulate long mode support for sysenter/sysexit like intel CPUs
1125 * does. This means intercepting \#UD to emulate the instructions in
1126 * long-mode and to intercept reads and writes to the SYSENTER MSRs in order to
1127 * preserve the upper 32 bits written to them (AMD will ignore and discard). */
1128 bool fEmulateLongModeSysEnterExit;
1129 uint8_t au8Alignment0[7];
1130
1131 /** Cache of the nested-guest's VMCB fields that we modify in order to run the
1132 * nested-guest using AMD-V. This will be restored on \#VMEXIT. */
1133 SVMNESTEDVMCBCACHE NstGstVmcbCache;
1134 } svm;
1135
1136 /** Event injection state. */
1137 HMEVENT Event;
1138
1139 /** Current shadow paging mode for updating CR4.
1140 * @todo move later (@bugref{9217}). */
1141 PGMMODE enmShadowMode;
1142 uint32_t u32TemporaryPadding;
1143
1144 /** The PAE PDPEs used with Nested Paging (only valid when
1145 * VMCPU_FF_HM_UPDATE_PAE_PDPES is set). */
1146 X86PDPE aPdpes[4];
1147
1148 /* These two comes because they are accessed from assembly and we don't
1149 want to detail all the stats in the assembly version of this structure. */
1150 STAMCOUNTER StatVmxWriteHostRip;
1151 STAMCOUNTER StatVmxWriteHostRsp;
1152 STAMCOUNTER StatVmxVmLaunch;
1153 STAMCOUNTER StatVmxVmResume;
1154
1155 STAMPROFILEADV StatEntry;
1156 STAMPROFILEADV StatPreExit;
1157 STAMPROFILEADV StatExitHandling;
1158 STAMPROFILEADV StatExitIO;
1159 STAMPROFILEADV StatExitMovCRx;
1160 STAMPROFILEADV StatExitXcptNmi;
1161 STAMPROFILEADV StatExitVmentry;
1162 STAMPROFILEADV StatImportGuestState;
1163 STAMPROFILEADV StatExportGuestState;
1164 STAMPROFILEADV StatLoadGuestFpuState;
1165 STAMPROFILEADV StatInGC;
1166 STAMPROFILEADV StatPoke;
1167 STAMPROFILEADV StatSpinPoke;
1168 STAMPROFILEADV StatSpinPokeFailed;
1169
1170 STAMCOUNTER StatInjectInterrupt;
1171 STAMCOUNTER StatInjectXcpt;
1172 STAMCOUNTER StatInjectReflect;
1173 STAMCOUNTER StatInjectConvertDF;
1174 STAMCOUNTER StatInjectInterpret;
1175 STAMCOUNTER StatInjectReflectNPF;
1176
1177 STAMCOUNTER StatExitAll;
1178 STAMCOUNTER StatNestedExitAll;
1179 STAMCOUNTER StatExitShadowNM;
1180 STAMCOUNTER StatExitGuestNM;
1181 STAMCOUNTER StatExitShadowPF; /**< Misleading, currently used for MMIO \#PFs as well. */
1182 STAMCOUNTER StatExitShadowPFEM;
1183 STAMCOUNTER StatExitGuestPF;
1184 STAMCOUNTER StatExitGuestUD;
1185 STAMCOUNTER StatExitGuestSS;
1186 STAMCOUNTER StatExitGuestNP;
1187 STAMCOUNTER StatExitGuestTS;
1188 STAMCOUNTER StatExitGuestOF;
1189 STAMCOUNTER StatExitGuestGP;
1190 STAMCOUNTER StatExitGuestDE;
1191 STAMCOUNTER StatExitGuestDF;
1192 STAMCOUNTER StatExitGuestBR;
1193 STAMCOUNTER StatExitGuestAC;
1194 STAMCOUNTER StatExitGuestDB;
1195 STAMCOUNTER StatExitGuestMF;
1196 STAMCOUNTER StatExitGuestBP;
1197 STAMCOUNTER StatExitGuestXF;
1198 STAMCOUNTER StatExitGuestXcpUnk;
1199 STAMCOUNTER StatExitDRxWrite;
1200 STAMCOUNTER StatExitDRxRead;
1201 STAMCOUNTER StatExitCR0Read;
1202 STAMCOUNTER StatExitCR2Read;
1203 STAMCOUNTER StatExitCR3Read;
1204 STAMCOUNTER StatExitCR4Read;
1205 STAMCOUNTER StatExitCR8Read;
1206 STAMCOUNTER StatExitCR0Write;
1207 STAMCOUNTER StatExitCR2Write;
1208 STAMCOUNTER StatExitCR3Write;
1209 STAMCOUNTER StatExitCR4Write;
1210 STAMCOUNTER StatExitCR8Write;
1211 STAMCOUNTER StatExitRdmsr;
1212 STAMCOUNTER StatExitWrmsr;
1213 STAMCOUNTER StatExitClts;
1214 STAMCOUNTER StatExitXdtrAccess;
1215 STAMCOUNTER StatExitLmsw;
1216 STAMCOUNTER StatExitIOWrite;
1217 STAMCOUNTER StatExitIORead;
1218 STAMCOUNTER StatExitIOStringWrite;
1219 STAMCOUNTER StatExitIOStringRead;
1220 STAMCOUNTER StatExitIntWindow;
1221 STAMCOUNTER StatExitExtInt;
1222 STAMCOUNTER StatExitHostNmiInGC;
1223 STAMCOUNTER StatExitHostNmiInGCIpi;
1224 STAMCOUNTER StatExitPreemptTimer;
1225 STAMCOUNTER StatExitTprBelowThreshold;
1226 STAMCOUNTER StatExitTaskSwitch;
1227 STAMCOUNTER StatExitApicAccess;
1228 STAMCOUNTER StatExitReasonNpf;
1229
1230 STAMCOUNTER StatNestedExitReasonNpf;
1231
1232 STAMCOUNTER StatFlushPage;
1233 STAMCOUNTER StatFlushPageManual;
1234 STAMCOUNTER StatFlushPhysPageManual;
1235 STAMCOUNTER StatFlushTlb;
1236 STAMCOUNTER StatFlushTlbNstGst;
1237 STAMCOUNTER StatFlushTlbManual;
1238 STAMCOUNTER StatFlushTlbWorldSwitch;
1239 STAMCOUNTER StatNoFlushTlbWorldSwitch;
1240 STAMCOUNTER StatFlushEntire;
1241 STAMCOUNTER StatFlushAsid;
1242 STAMCOUNTER StatFlushNestedPaging;
1243 STAMCOUNTER StatFlushTlbInvlpgVirt;
1244 STAMCOUNTER StatFlushTlbInvlpgPhys;
1245 STAMCOUNTER StatTlbShootdown;
1246 STAMCOUNTER StatTlbShootdownFlush;
1247
1248 STAMCOUNTER StatSwitchPendingHostIrq;
1249 STAMCOUNTER StatSwitchTprMaskedIrq;
1250 STAMCOUNTER StatSwitchGuestIrq;
1251 STAMCOUNTER StatSwitchHmToR3FF;
1252 STAMCOUNTER StatSwitchVmReq;
1253 STAMCOUNTER StatSwitchPgmPoolFlush;
1254 STAMCOUNTER StatSwitchDma;
1255 STAMCOUNTER StatSwitchExitToR3;
1256 STAMCOUNTER StatSwitchLongJmpToR3;
1257 STAMCOUNTER StatSwitchMaxResumeLoops;
1258 STAMCOUNTER StatSwitchHltToR3;
1259 STAMCOUNTER StatSwitchApicAccessToR3;
1260 STAMCOUNTER StatSwitchPreempt;
1261 STAMCOUNTER StatSwitchNstGstVmexit;
1262
1263 STAMCOUNTER StatTscParavirt;
1264 STAMCOUNTER StatTscOffset;
1265 STAMCOUNTER StatTscIntercept;
1266
1267 STAMCOUNTER StatDRxArmed;
1268 STAMCOUNTER StatDRxContextSwitch;
1269 STAMCOUNTER StatDRxIoCheck;
1270
1271 STAMCOUNTER StatExportMinimal;
1272 STAMCOUNTER StatExportFull;
1273 STAMCOUNTER StatLoadGuestFpu;
1274 STAMCOUNTER StatExportHostState;
1275
1276 STAMCOUNTER StatVmxCheckBadRmSelBase;
1277 STAMCOUNTER StatVmxCheckBadRmSelLimit;
1278 STAMCOUNTER StatVmxCheckBadRmSelAttr;
1279 STAMCOUNTER StatVmxCheckBadV86SelBase;
1280 STAMCOUNTER StatVmxCheckBadV86SelLimit;
1281 STAMCOUNTER StatVmxCheckBadV86SelAttr;
1282 STAMCOUNTER StatVmxCheckRmOk;
1283 STAMCOUNTER StatVmxCheckBadSel;
1284 STAMCOUNTER StatVmxCheckBadRpl;
1285 STAMCOUNTER StatVmxCheckPmOk;
1286
1287#ifdef VBOX_WITH_STATISTICS
1288 R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
1289 R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
1290 R3PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqs;
1291 R0PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqsR0;
1292 R3PTRTYPE(PSTAMCOUNTER) paStatInjectedXcpts;
1293 R0PTRTYPE(PSTAMCOUNTER) paStatInjectedXcptsR0;
1294 R3PTRTYPE(PSTAMCOUNTER) paStatNestedExitReason;
1295 R0PTRTYPE(PSTAMCOUNTER) paStatNestedExitReasonR0;
1296#endif
1297#ifdef HM_PROFILE_EXIT_DISPATCH
1298 STAMPROFILEADV StatExitDispatch;
1299#endif
1300} HMCPU;
1301/** Pointer to HM VMCPU instance data. */
1302typedef HMCPU *PHMCPU;
1303AssertCompileMemberAlignment(HMCPU, fCheckedTLBFlush, 4);
1304AssertCompileMemberAlignment(HMCPU, fCtxChanged, 8);
1305AssertCompileMemberAlignment(HMCPU, vmx, 8);
1306AssertCompileMemberAlignment(HMCPU, vmx.VmcsInfo, 8);
1307AssertCompileMemberAlignment(HMCPU, vmx.VmcsInfoNstGst, 8);
1308AssertCompileMemberAlignment(HMCPU, svm, 8);
1309AssertCompileMemberAlignment(HMCPU, Event, 8);
1310
1311
1312/**
1313 * HM per-VCpu ring-0 only instance data.
1314 */
1315typedef struct HMR0PERVCPU
1316{
1317 /** World switch exit counter. */
1318 uint32_t volatile cWorldSwitchExits;
1319 /** TLB flush count. */
1320 uint32_t cTlbFlushes;
1321 /** The last CPU we were executing code on (NIL_RTCPUID for the first time). */
1322 RTCPUID idLastCpu;
1323 /** The CPU ID of the CPU currently owning the VMCS. Set in
1324 * HMR0Enter and cleared in HMR0Leave. */
1325 RTCPUID idEnteredCpu;
1326 /** Current ASID in use by the VM. */
1327 uint32_t uCurrentAsid;
1328
1329 /** Set if we need to flush the TLB during the world switch. */
1330 bool fForceTLBFlush;
1331 /** Whether we've completed the inner HM leave function. */
1332 bool fLeaveDone;
1333 /** Whether we're using the hyper DR7 or guest DR7. */
1334 bool fUsingHyperDR7;
1335 /** Whether we are currently executing in the debug loop.
1336 * Mainly for assertions. */
1337 bool fUsingDebugLoop;
1338 /** Set if we using the debug loop and wish to intercept RDTSC. */
1339 bool fDebugWantRdTscExit;
1340 /** Set if XCR0 needs to be saved/restored when entering/exiting guest code
1341 * execution. */
1342 bool fLoadSaveGuestXcr0;
1343 /** Set if we need to clear the trap flag because of single stepping. */
1344 bool fClearTrapFlag;
1345
1346 bool afPadding1[1];
1347 /** World switcher flags (HM_WSF_XXX - was CPUMCTX::fWorldSwitcher in 6.1). */
1348 uint32_t fWorldSwitcher;
1349
1350 /** VT-x data. */
1351 struct HMR0CPUVMX
1352 {
1353 /** Ring-0 pointer to the hardware-assisted VMX execution function. */
1354 PFNHMVMXSTARTVM pfnStartVm;
1355
1356 /** @name Guest information.
1357 * @{ */
1358 /** Guest VMCS information. */
1359 VMXVMCSINFO VmcsInfo;
1360 /** Nested-guest VMCS information. */
1361 VMXVMCSINFO VmcsInfoNstGst;
1362 /* Whether the nested-guest VMCS was the last current VMCS (authoritative copy).
1363 * @see HMCPU::vmx.fSwitchedToNstGstVmcsCopyForRing3 */
1364 bool fSwitchedToNstGstVmcs;
1365 bool afAlignment0[7];
1366 /** @} */
1367
1368 /** @name Host information.
1369 * @{ */
1370 /** Host LSTAR MSR to restore lazily while leaving VT-x. */
1371 uint64_t u64HostMsrLStar;
1372 /** Host STAR MSR to restore lazily while leaving VT-x. */
1373 uint64_t u64HostMsrStar;
1374 /** Host SF_MASK MSR to restore lazily while leaving VT-x. */
1375 uint64_t u64HostMsrSfMask;
1376 /** Host KernelGS-Base MSR to restore lazily while leaving VT-x. */
1377 uint64_t u64HostMsrKernelGsBase;
1378 /** The mask of lazy MSRs swap/restore state, see VMX_LAZY_MSRS_XXX. */
1379 uint32_t fLazyMsrs;
1380 /** Whether the host MSR values are up-to-date in the auto-load/store MSR area. */
1381 bool fUpdatedHostAutoMsrs;
1382 /** Alignment. */
1383 uint8_t au8Alignment0[3];
1384 /** Which host-state bits to restore before being preempted, see
1385 * VMX_RESTORE_HOST_XXX. */
1386 uint32_t fRestoreHostFlags;
1387 /** Alignment. */
1388 uint32_t u32Alignment0;
1389 /** The host-state restoration structure. */
1390 VMXRESTOREHOST RestoreHost;
1391 /** @} */
1392 } vmx;
1393
1394 /** SVM data. */
1395 struct HMR0CPUSVM
1396 {
1397 /** Ring 0 handlers for VT-x. */
1398 PFNHMSVMVMRUN pfnVMRun;
1399
1400 /** Physical address of the host VMCB which holds additional host-state. */
1401 RTHCPHYS HCPhysVmcbHost;
1402 /** R0 memory object for the host VMCB which holds additional host-state. */
1403 RTR0MEMOBJ hMemObjVmcbHost;
1404
1405 /** Physical address of the guest VMCB. */
1406 RTHCPHYS HCPhysVmcb;
1407 /** R0 memory object for the guest VMCB. */
1408 RTR0MEMOBJ hMemObjVmcb;
1409 /** Pointer to the guest VMCB. */
1410 R0PTRTYPE(PSVMVMCB) pVmcb;
1411
1412 /** Physical address of the MSR bitmap (8 KB). */
1413 RTHCPHYS HCPhysMsrBitmap;
1414 /** R0 memory object for the MSR bitmap (8 KB). */
1415 RTR0MEMOBJ hMemObjMsrBitmap;
1416 /** Pointer to the MSR bitmap. */
1417 R0PTRTYPE(void *) pvMsrBitmap;
1418
1419 /** Whether VTPR with V_INTR_MASKING set is in effect, indicating
1420 * we should check if the VTPR changed on every VM-exit. */
1421 bool fSyncVTpr;
1422 bool afAlignment[7];
1423
1424 /** Host's TSC_AUX MSR (used when RDTSCP doesn't cause VM-exits). */
1425 uint64_t u64HostTscAux;
1426
1427 /** For saving stack space, the disassembler state is allocated here
1428 * instead of on the stack. */
1429 DISCPUSTATE DisState;
1430 } svm;
1431} HMR0PERVCPU;
1432/** Pointer to HM ring-0 VMCPU instance data. */
1433typedef HMR0PERVCPU *PHMR0PERVCPU;
1434AssertCompileMemberAlignment(HMR0PERVCPU, cWorldSwitchExits, 4);
1435AssertCompileMemberAlignment(HMR0PERVCPU, fForceTLBFlush, 4);
1436AssertCompileMemberAlignment(HMR0PERVCPU, vmx.RestoreHost, 8);
1437
1438
1439/** @name HM_WSF_XXX - @bugref{9453}, @bugref{9087}
1440 * @{ */
1441/** Touch IA32_PRED_CMD.IBPB on VM exit. */
1442#define HM_WSF_IBPB_EXIT RT_BIT_32(0)
1443/** Touch IA32_PRED_CMD.IBPB on VM entry. */
1444#define HM_WSF_IBPB_ENTRY RT_BIT_32(1)
1445/** Touch IA32_FLUSH_CMD.L1D on VM entry. */
1446#define HM_WSF_L1D_ENTRY RT_BIT_32(2)
1447/** Flush MDS buffers on VM entry. */
1448#define HM_WSF_MDS_ENTRY RT_BIT_32(3)
1449/** @} */
1450
1451
1452#ifdef IN_RING0
1453extern bool g_fHmVmxSupported;
1454extern uint32_t g_fHmHostKernelFeatures;
1455extern uint32_t g_uHmMaxAsid;
1456extern bool g_fHmVmxUsePreemptTimer;
1457extern uint8_t g_cHmVmxPreemptTimerShift;
1458extern uint64_t g_uHmVmxHostCr4;
1459extern uint64_t g_uHmVmxHostMsrEfer;
1460extern uint64_t g_uHmVmxHostSmmMonitorCtl;
1461extern bool g_fHmSvmSupported;
1462extern uint32_t g_uHmSvmRev;
1463extern uint32_t g_fHmSvmFeatures;
1464
1465extern SUPHWVIRTMSRS g_HmMsrs;
1466
1467
1468VMMR0_INT_DECL(PHMPHYSCPU) hmR0GetCurrentCpu(void);
1469VMMR0_INT_DECL(int) hmR0EnterCpu(PVMCPUCC pVCpu);
1470
1471# ifdef VBOX_STRICT
1472# define HM_DUMP_REG_FLAGS_GPRS RT_BIT(0)
1473# define HM_DUMP_REG_FLAGS_FPU RT_BIT(1)
1474# define HM_DUMP_REG_FLAGS_MSRS RT_BIT(2)
1475# define HM_DUMP_REG_FLAGS_ALL (HM_DUMP_REG_FLAGS_GPRS | HM_DUMP_REG_FLAGS_FPU | HM_DUMP_REG_FLAGS_MSRS)
1476
1477VMMR0_INT_DECL(void) hmR0DumpRegs(PVMCPUCC pVCpu, uint32_t fFlags);
1478VMMR0_INT_DECL(void) hmR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg);
1479# endif
1480
1481DECLASM(void) hmR0MdsClear(void);
1482#endif /* IN_RING0 */
1483
1484
1485/** @addtogroup grp_hm_int_svm SVM Internal
1486 * @{ */
1487VMM_INT_DECL(int) hmEmulateSvmMovTpr(PVMCC pVM, PVMCPUCC pVCpu);
1488
1489/**
1490 * Prepares for and executes VMRUN (64-bit register context).
1491 *
1492 * @returns VBox status code (no informational stuff).
1493 * @param pVM The cross context VM structure. (Not used.)
1494 * @param pVCpu The cross context virtual CPU structure.
1495 * @param HCPhyspVMCB Physical address of the VMCB.
1496 *
1497 * @remarks With spectre mitigations and the usual need for speed (/ micro
1498 * optimizations), we have a bunch of variations of this code depending
1499 * on a few precoditions. In release builds, the code is entirely
1500 * without conditionals. Debug builds have a couple of assertions that
1501 * shouldn't ever be triggered.
1502 *
1503 * @{
1504 */
1505DECLASM(int) hmR0SvmVmRun_SansXcr0_SansIbpbEntry_SansIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1506DECLASM(int) hmR0SvmVmRun_WithXcr0_SansIbpbEntry_SansIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1507DECLASM(int) hmR0SvmVmRun_SansXcr0_WithIbpbEntry_SansIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1508DECLASM(int) hmR0SvmVmRun_WithXcr0_WithIbpbEntry_SansIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1509DECLASM(int) hmR0SvmVmRun_SansXcr0_SansIbpbEntry_WithIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1510DECLASM(int) hmR0SvmVmRun_WithXcr0_SansIbpbEntry_WithIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1511DECLASM(int) hmR0SvmVmRun_SansXcr0_WithIbpbEntry_WithIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1512DECLASM(int) hmR0SvmVmRun_WithXcr0_WithIbpbEntry_WithIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1513/** @} */
1514
1515/** @} */
1516
1517
1518/** @addtogroup grp_hm_int_vmx VMX Internal
1519 * @{ */
1520VMM_INT_DECL(PVMXVMCSINFOSHARED) hmGetVmxActiveVmcsInfoShared(PVMCPUCC pVCpu);
1521
1522/**
1523 * Used on platforms with poor inline assembly support to retrieve all the
1524 * info from the CPU and put it in the @a pRestoreHost structure.
1525 */
1526DECLASM(void) hmR0VmxExportHostSegmentRegsAsmHlp(PVMXRESTOREHOST pRestoreHost, bool fHaveFsGsBase);
1527
1528/**
1529 * Restores some host-state fields that need not be done on every VM-exit.
1530 *
1531 * @returns VBox status code.
1532 * @param fRestoreHostFlags Flags of which host registers needs to be
1533 * restored.
1534 * @param pRestoreHost Pointer to the host-restore structure.
1535 */
1536DECLASM(int) VMXRestoreHostState(uint32_t fRestoreHostFlags, PVMXRESTOREHOST pRestoreHost);
1537
1538/**
1539 * VMX StartVM functions.
1540 *
1541 * @returns VBox status code (no informational stuff).
1542 * @param pVM Pointer to the cross context VM structure.
1543 * @param pVCpu Pointer to the cross context per-CPU structure.
1544 * @param fResume Whether to use VMRESUME (true) or VMLAUNCH (false).
1545 *
1546 * @remarks With spectre mitigations and the usual need for speed (/ micro
1547 * optimizations), we have a bunch of variations of this code depending
1548 * on a few precoditions. In release builds, the code is entirely
1549 * without conditionals. Debug builds have a couple of assertions that
1550 * shouldn't ever be triggered.
1551 *
1552 * @{
1553 */
1554DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_SansL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1555DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_SansL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1556DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_SansL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1557DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_SansL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1558DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_WithL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1559DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_WithL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1560DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_WithL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1561DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_WithL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1562DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_SansL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1563DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_SansL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1564DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_SansL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1565DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_SansL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1566DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_WithL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1567DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_WithL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1568DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_WithL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1569DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_WithL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1570DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_SansL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1571DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_SansL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1572DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_SansL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1573DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_SansL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1574DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_WithL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1575DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_WithL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1576DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_WithL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1577DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_WithL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1578DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_SansL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1579DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_SansL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1580DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_SansL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1581DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_SansL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1582DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_WithL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1583DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_WithL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1584DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_WithL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1585DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_WithL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1586/** @} */
1587
1588/** @} */
1589
1590/** @} */
1591
1592RT_C_DECLS_END
1593
1594#endif /* !VMM_INCLUDED_SRC_include_HMInternal_h */
1595
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