VirtualBox

source: vbox/trunk/src/VBox/VMM/include/HMInternal.h@ 91323

Last change on this file since 91323 was 91323, checked in by vboxsync, 3 years ago

VMM: bugref:10106 Fixed IA32_FEATURE_CONTROL MSR reported to the guest.
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File size: 73.2 KB
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1/* $Id: HMInternal.h 91323 2021-09-22 10:04:56Z vboxsync $ */
2/** @file
3 * HM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef VMM_INCLUDED_SRC_include_HMInternal_h
19#define VMM_INCLUDED_SRC_include_HMInternal_h
20#ifndef RT_WITHOUT_PRAGMA_ONCE
21# pragma once
22#endif
23
24#include <VBox/cdefs.h>
25#include <VBox/types.h>
26#include <VBox/vmm/stam.h>
27#include <VBox/dis.h>
28#include <VBox/vmm/hm.h>
29#include <VBox/vmm/hm_vmx.h>
30#include <VBox/vmm/hm_svm.h>
31#include <VBox/vmm/pgm.h>
32#include <VBox/vmm/cpum.h>
33#include <VBox/vmm/trpm.h>
34#include <iprt/memobj.h>
35#include <iprt/cpuset.h>
36#include <iprt/mp.h>
37#include <iprt/avl.h>
38#include <iprt/string.h>
39
40#if HC_ARCH_BITS == 32
41# error "32-bit hosts are no longer supported. Go back to 6.0 or earlier!"
42#endif
43
44/** @def HM_PROFILE_EXIT_DISPATCH
45 * Enables profiling of the VM exit handler dispatching. */
46#if 0 || defined(DOXYGEN_RUNNING)
47# define HM_PROFILE_EXIT_DISPATCH
48#endif
49
50RT_C_DECLS_BEGIN
51
52
53/** @defgroup grp_hm_int Internal
54 * @ingroup grp_hm
55 * @internal
56 * @{
57 */
58
59/** @name HM_CHANGED_XXX
60 * HM CPU-context changed flags.
61 *
62 * These flags are used to keep track of which registers and state has been
63 * modified since they were imported back into the guest-CPU context.
64 *
65 * @{
66 */
67#define HM_CHANGED_HOST_CONTEXT UINT64_C(0x0000000000000001)
68#define HM_CHANGED_GUEST_RIP UINT64_C(0x0000000000000004)
69#define HM_CHANGED_GUEST_RFLAGS UINT64_C(0x0000000000000008)
70
71#define HM_CHANGED_GUEST_RAX UINT64_C(0x0000000000000010)
72#define HM_CHANGED_GUEST_RCX UINT64_C(0x0000000000000020)
73#define HM_CHANGED_GUEST_RDX UINT64_C(0x0000000000000040)
74#define HM_CHANGED_GUEST_RBX UINT64_C(0x0000000000000080)
75#define HM_CHANGED_GUEST_RSP UINT64_C(0x0000000000000100)
76#define HM_CHANGED_GUEST_RBP UINT64_C(0x0000000000000200)
77#define HM_CHANGED_GUEST_RSI UINT64_C(0x0000000000000400)
78#define HM_CHANGED_GUEST_RDI UINT64_C(0x0000000000000800)
79#define HM_CHANGED_GUEST_R8_R15 UINT64_C(0x0000000000001000)
80#define HM_CHANGED_GUEST_GPRS_MASK UINT64_C(0x0000000000001ff0)
81
82#define HM_CHANGED_GUEST_ES UINT64_C(0x0000000000002000)
83#define HM_CHANGED_GUEST_CS UINT64_C(0x0000000000004000)
84#define HM_CHANGED_GUEST_SS UINT64_C(0x0000000000008000)
85#define HM_CHANGED_GUEST_DS UINT64_C(0x0000000000010000)
86#define HM_CHANGED_GUEST_FS UINT64_C(0x0000000000020000)
87#define HM_CHANGED_GUEST_GS UINT64_C(0x0000000000040000)
88#define HM_CHANGED_GUEST_SREG_MASK UINT64_C(0x000000000007e000)
89
90#define HM_CHANGED_GUEST_GDTR UINT64_C(0x0000000000080000)
91#define HM_CHANGED_GUEST_IDTR UINT64_C(0x0000000000100000)
92#define HM_CHANGED_GUEST_LDTR UINT64_C(0x0000000000200000)
93#define HM_CHANGED_GUEST_TR UINT64_C(0x0000000000400000)
94#define HM_CHANGED_GUEST_TABLE_MASK UINT64_C(0x0000000000780000)
95
96#define HM_CHANGED_GUEST_CR0 UINT64_C(0x0000000000800000)
97#define HM_CHANGED_GUEST_CR2 UINT64_C(0x0000000001000000)
98#define HM_CHANGED_GUEST_CR3 UINT64_C(0x0000000002000000)
99#define HM_CHANGED_GUEST_CR4 UINT64_C(0x0000000004000000)
100#define HM_CHANGED_GUEST_CR_MASK UINT64_C(0x0000000007800000)
101
102#define HM_CHANGED_GUEST_APIC_TPR UINT64_C(0x0000000008000000)
103#define HM_CHANGED_GUEST_EFER_MSR UINT64_C(0x0000000010000000)
104
105#define HM_CHANGED_GUEST_DR0_DR3 UINT64_C(0x0000000020000000)
106#define HM_CHANGED_GUEST_DR6 UINT64_C(0x0000000040000000)
107#define HM_CHANGED_GUEST_DR7 UINT64_C(0x0000000080000000)
108#define HM_CHANGED_GUEST_DR_MASK UINT64_C(0x00000000e0000000)
109
110#define HM_CHANGED_GUEST_X87 UINT64_C(0x0000000100000000)
111#define HM_CHANGED_GUEST_SSE_AVX UINT64_C(0x0000000200000000)
112#define HM_CHANGED_GUEST_OTHER_XSAVE UINT64_C(0x0000000400000000)
113#define HM_CHANGED_GUEST_XCRx UINT64_C(0x0000000800000000)
114
115#define HM_CHANGED_GUEST_KERNEL_GS_BASE UINT64_C(0x0000001000000000)
116#define HM_CHANGED_GUEST_SYSCALL_MSRS UINT64_C(0x0000002000000000)
117#define HM_CHANGED_GUEST_SYSENTER_CS_MSR UINT64_C(0x0000004000000000)
118#define HM_CHANGED_GUEST_SYSENTER_EIP_MSR UINT64_C(0x0000008000000000)
119#define HM_CHANGED_GUEST_SYSENTER_ESP_MSR UINT64_C(0x0000010000000000)
120#define HM_CHANGED_GUEST_SYSENTER_MSR_MASK UINT64_C(0x000001c000000000)
121#define HM_CHANGED_GUEST_TSC_AUX UINT64_C(0x0000020000000000)
122#define HM_CHANGED_GUEST_OTHER_MSRS UINT64_C(0x0000040000000000)
123#define HM_CHANGED_GUEST_ALL_MSRS ( HM_CHANGED_GUEST_EFER \
124 | HM_CHANGED_GUEST_KERNEL_GS_BASE \
125 | HM_CHANGED_GUEST_SYSCALL_MSRS \
126 | HM_CHANGED_GUEST_SYSENTER_MSR_MASK \
127 | HM_CHANGED_GUEST_TSC_AUX \
128 | HM_CHANGED_GUEST_OTHER_MSRS)
129
130#define HM_CHANGED_GUEST_HWVIRT UINT64_C(0x0000080000000000)
131#define HM_CHANGED_GUEST_MASK UINT64_C(0x00000ffffffffffc)
132
133#define HM_CHANGED_KEEPER_STATE_MASK UINT64_C(0xffff000000000000)
134
135#define HM_CHANGED_VMX_XCPT_INTERCEPTS UINT64_C(0x0001000000000000)
136#define HM_CHANGED_VMX_GUEST_AUTO_MSRS UINT64_C(0x0002000000000000)
137#define HM_CHANGED_VMX_GUEST_LAZY_MSRS UINT64_C(0x0004000000000000)
138#define HM_CHANGED_VMX_ENTRY_EXIT_CTLS UINT64_C(0x0008000000000000)
139#define HM_CHANGED_VMX_MASK UINT64_C(0x000f000000000000)
140#define HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE ( HM_CHANGED_GUEST_DR_MASK \
141 | HM_CHANGED_VMX_GUEST_LAZY_MSRS)
142
143#define HM_CHANGED_SVM_XCPT_INTERCEPTS UINT64_C(0x0001000000000000)
144#define HM_CHANGED_SVM_MASK UINT64_C(0x0001000000000000)
145#define HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE HM_CHANGED_GUEST_DR_MASK
146
147#define HM_CHANGED_ALL_GUEST ( HM_CHANGED_GUEST_MASK \
148 | HM_CHANGED_KEEPER_STATE_MASK)
149
150/** Mask of what state might have changed when IEM raised an exception.
151 * This is a based on IEM_CPUMCTX_EXTRN_XCPT_MASK. */
152#define HM_CHANGED_RAISED_XCPT_MASK ( HM_CHANGED_GUEST_GPRS_MASK \
153 | HM_CHANGED_GUEST_RIP \
154 | HM_CHANGED_GUEST_RFLAGS \
155 | HM_CHANGED_GUEST_SS \
156 | HM_CHANGED_GUEST_CS \
157 | HM_CHANGED_GUEST_CR0 \
158 | HM_CHANGED_GUEST_CR3 \
159 | HM_CHANGED_GUEST_CR4 \
160 | HM_CHANGED_GUEST_APIC_TPR \
161 | HM_CHANGED_GUEST_EFER_MSR \
162 | HM_CHANGED_GUEST_DR7 \
163 | HM_CHANGED_GUEST_CR2 \
164 | HM_CHANGED_GUEST_SREG_MASK \
165 | HM_CHANGED_GUEST_TABLE_MASK)
166
167#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
168/** Mask of what state might have changed when \#VMEXIT is emulated. */
169# define HM_CHANGED_SVM_VMEXIT_MASK ( HM_CHANGED_GUEST_RSP \
170 | HM_CHANGED_GUEST_RAX \
171 | HM_CHANGED_GUEST_RIP \
172 | HM_CHANGED_GUEST_RFLAGS \
173 | HM_CHANGED_GUEST_CS \
174 | HM_CHANGED_GUEST_SS \
175 | HM_CHANGED_GUEST_DS \
176 | HM_CHANGED_GUEST_ES \
177 | HM_CHANGED_GUEST_GDTR \
178 | HM_CHANGED_GUEST_IDTR \
179 | HM_CHANGED_GUEST_CR_MASK \
180 | HM_CHANGED_GUEST_EFER_MSR \
181 | HM_CHANGED_GUEST_DR6 \
182 | HM_CHANGED_GUEST_DR7 \
183 | HM_CHANGED_GUEST_OTHER_MSRS \
184 | HM_CHANGED_GUEST_HWVIRT \
185 | HM_CHANGED_SVM_MASK \
186 | HM_CHANGED_GUEST_APIC_TPR)
187
188/** Mask of what state might have changed when VMRUN is emulated. */
189# define HM_CHANGED_SVM_VMRUN_MASK HM_CHANGED_SVM_VMEXIT_MASK
190#endif
191#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
192/** Mask of what state might have changed when VM-exit is emulated.
193 *
194 * This is currently unused, but keeping it here in case we can get away a bit more
195 * fine-grained state handling.
196 *
197 * @note Update IEM_CPUMCTX_EXTRN_VMX_VMEXIT_MASK when this changes. */
198# define HM_CHANGED_VMX_VMEXIT_MASK ( HM_CHANGED_GUEST_CR0 | HM_CHANGED_GUEST_CR3 | HM_CHANGED_GUEST_CR4 \
199 | HM_CHANGED_GUEST_DR7 | HM_CHANGED_GUEST_DR6 \
200 | HM_CHANGED_GUEST_EFER_MSR \
201 | HM_CHANGED_GUEST_SYSENTER_MSR_MASK \
202 | HM_CHANGED_GUEST_OTHER_MSRS /* for PAT MSR */ \
203 | HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RSP | HM_CHANGED_GUEST_RFLAGS \
204 | HM_CHANGED_GUEST_SREG_MASK \
205 | HM_CHANGED_GUEST_TR \
206 | HM_CHANGED_GUEST_LDTR | HM_CHANGED_GUEST_GDTR | HM_CHANGED_GUEST_IDTR \
207 | HM_CHANGED_GUEST_HWVIRT )
208#endif
209/** @} */
210
211/** Maximum number of exit reason statistics counters. */
212#define MAX_EXITREASON_STAT 0x100
213#define MASK_EXITREASON_STAT 0xff
214#define MASK_INJECT_IRQ_STAT 0xff
215
216/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
217#define HM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
218/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
219#define HM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2 * PAGE_SIZE + 1)
220/** Total guest mapped memory needed. */
221#define HM_VTX_TOTAL_DEVHEAP_MEM (HM_EPT_IDENTITY_PG_TABLE_SIZE + HM_VTX_TSS_SIZE)
222
223
224/** @name Macros for enabling and disabling preemption.
225 * These are really just for hiding the RTTHREADPREEMPTSTATE and asserting that
226 * preemption has already been disabled when there is no context hook.
227 * @{ */
228#ifdef VBOX_STRICT
229# define HM_DISABLE_PREEMPT(a_pVCpu) \
230 RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
231 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD) || VMMR0ThreadCtxHookIsEnabled((a_pVCpu))); \
232 RTThreadPreemptDisable(&PreemptStateInternal)
233#else
234# define HM_DISABLE_PREEMPT(a_pVCpu) \
235 RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
236 RTThreadPreemptDisable(&PreemptStateInternal)
237#endif /* VBOX_STRICT */
238#define HM_RESTORE_PREEMPT() do { RTThreadPreemptRestore(&PreemptStateInternal); } while(0)
239/** @} */
240
241
242/** @name HM saved state versions.
243 * @{
244 */
245#define HM_SAVED_STATE_VERSION HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT
246#define HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT 6
247#define HM_SAVED_STATE_VERSION_TPR_PATCHING 5
248#define HM_SAVED_STATE_VERSION_NO_TPR_PATCHING 4
249#define HM_SAVED_STATE_VERSION_2_0_X 3
250/** @} */
251
252
253/**
254 * HM physical (host) CPU information.
255 */
256typedef struct HMPHYSCPU
257{
258 /** The CPU ID. */
259 RTCPUID idCpu;
260 /** The VM_HSAVE_AREA (AMD-V) / VMXON region (Intel) memory backing. */
261 RTR0MEMOBJ hMemObj;
262 /** The physical address of the first page in hMemObj (it's a
263 * physcially contigous allocation if it spans multiple pages). */
264 RTHCPHYS HCPhysMemObj;
265 /** The address of the memory (for pfnEnable). */
266 void *pvMemObj;
267 /** Current ASID (AMD-V) / VPID (Intel). */
268 uint32_t uCurrentAsid;
269 /** TLB flush count. */
270 uint32_t cTlbFlushes;
271 /** Whether to flush each new ASID/VPID before use. */
272 bool fFlushAsidBeforeUse;
273 /** Configured for VT-x or AMD-V. */
274 bool fConfigured;
275 /** Set if the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active. */
276 bool fIgnoreAMDVInUseError;
277 /** Whether CR4.VMXE was already enabled prior to us enabling it. */
278 bool fVmxeAlreadyEnabled;
279 /** In use by our code. (for power suspend) */
280 bool volatile fInUse;
281#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
282 /** Nested-guest union (put data common to SVM/VMX outside the union). */
283 union
284 {
285 /** Nested-guest SVM data. */
286 struct
287 {
288 /** The active nested-guest MSR permission bitmap memory backing. */
289 RTR0MEMOBJ hNstGstMsrpm;
290 /** The physical address of the first page in hNstGstMsrpm (physcially
291 * contiguous allocation). */
292 RTHCPHYS HCPhysNstGstMsrpm;
293 /** The address of the active nested-guest MSRPM. */
294 void *pvNstGstMsrpm;
295 } svm;
296 /** @todo Nested-VMX. */
297 } n;
298#endif
299} HMPHYSCPU;
300/** Pointer to HMPHYSCPU struct. */
301typedef HMPHYSCPU *PHMPHYSCPU;
302/** Pointer to a const HMPHYSCPU struct. */
303typedef const HMPHYSCPU *PCHMPHYSCPU;
304
305/**
306 * TPR-instruction type.
307 */
308typedef enum
309{
310 HMTPRINSTR_INVALID,
311 HMTPRINSTR_READ,
312 HMTPRINSTR_READ_SHR4,
313 HMTPRINSTR_WRITE_REG,
314 HMTPRINSTR_WRITE_IMM,
315 HMTPRINSTR_JUMP_REPLACEMENT,
316 /** The usual 32-bit paranoia. */
317 HMTPRINSTR_32BIT_HACK = 0x7fffffff
318} HMTPRINSTR;
319
320/**
321 * TPR patch information.
322 */
323typedef struct
324{
325 /** The key is the address of patched instruction. (32 bits GC ptr) */
326 AVLOU32NODECORE Core;
327 /** Original opcode. */
328 uint8_t aOpcode[16];
329 /** Instruction size. */
330 uint32_t cbOp;
331 /** Replacement opcode. */
332 uint8_t aNewOpcode[16];
333 /** Replacement instruction size. */
334 uint32_t cbNewOp;
335 /** Instruction type. */
336 HMTPRINSTR enmType;
337 /** Source operand. */
338 uint32_t uSrcOperand;
339 /** Destination operand. */
340 uint32_t uDstOperand;
341 /** Number of times the instruction caused a fault. */
342 uint32_t cFaults;
343 /** Patch address of the jump replacement. */
344 RTGCPTR32 pJumpTarget;
345} HMTPRPATCH;
346/** Pointer to HMTPRPATCH. */
347typedef HMTPRPATCH *PHMTPRPATCH;
348/** Pointer to a const HMTPRPATCH. */
349typedef const HMTPRPATCH *PCHMTPRPATCH;
350
351
352/**
353 * Makes a HMEXITSTAT::uKey value from a program counter and an exit code.
354 *
355 * @returns 64-bit key
356 * @param a_uPC The RIP + CS.BASE value of the exit.
357 * @param a_uExit The exit code.
358 * @todo Add CPL?
359 */
360#define HMEXITSTAT_MAKE_KEY(a_uPC, a_uExit) (((a_uPC) & UINT64_C(0x0000ffffffffffff)) | (uint64_t)(a_uExit) << 48)
361
362typedef struct HMEXITINFO
363{
364 /** See HMEXITSTAT_MAKE_KEY(). */
365 uint64_t uKey;
366 /** Number of recent hits (depreciates with time). */
367 uint32_t volatile cHits;
368 /** The age + lock. */
369 uint16_t volatile uAge;
370 /** Action or action table index. */
371 uint16_t iAction;
372} HMEXITINFO;
373AssertCompileSize(HMEXITINFO, 16); /* Lots of these guys, so don't add any unnecessary stuff! */
374
375typedef struct HMEXITHISTORY
376{
377 /** The exit timestamp. */
378 uint64_t uTscExit;
379 /** The index of the corresponding HMEXITINFO entry.
380 * UINT32_MAX if none (too many collisions, race, whatever). */
381 uint32_t iExitInfo;
382 /** Figure out later, needed for padding now. */
383 uint32_t uSomeClueOrSomething;
384} HMEXITHISTORY;
385
386/**
387 * Switcher function, HC to the special 64-bit RC.
388 *
389 * @param pVM The cross context VM structure.
390 * @param offCpumVCpu Offset from pVM->cpum to pVM->aCpus[idCpu].cpum.
391 * @returns Return code indicating the action to take.
392 */
393typedef DECLCALLBACKTYPE(int, FNHMSWITCHERHC,(PVM pVM, uint32_t offCpumVCpu));
394/** Pointer to switcher function. */
395typedef FNHMSWITCHERHC *PFNHMSWITCHERHC;
396
397
398/**
399 * HM event.
400 *
401 * VT-x and AMD-V common event injection structure.
402 */
403typedef struct HMEVENT
404{
405 /** Whether the event is pending. */
406 uint32_t fPending;
407 /** The error-code associated with the event. */
408 uint32_t u32ErrCode;
409 /** The length of the instruction in bytes (only relevant for software
410 * interrupts or software exceptions). */
411 uint32_t cbInstr;
412 /** Alignment. */
413 uint32_t u32Padding;
414 /** The encoded event (VM-entry interruption-information for VT-x or EVENTINJ
415 * for SVM). */
416 uint64_t u64IntInfo;
417 /** Guest virtual address if this is a page-fault event. */
418 RTGCUINTPTR GCPtrFaultAddress;
419} HMEVENT;
420/** Pointer to a HMEVENT struct. */
421typedef HMEVENT *PHMEVENT;
422/** Pointer to a const HMEVENT struct. */
423typedef const HMEVENT *PCHMEVENT;
424AssertCompileSizeAlignment(HMEVENT, 8);
425
426/**
427 * HM VM Instance data.
428 * Changes to this must checked against the padding of the hm union in VM!
429 */
430typedef struct HM
431{
432 /** Set when the debug facility has breakpoints/events enabled that requires
433 * us to use the debug execution loop in ring-0. */
434 bool fUseDebugLoop;
435 /** Set when TPR patching is allowed. */
436 bool fTprPatchingAllowed;
437 /** Set when TPR patching is active. */
438 bool fTprPatchingActive;
439 /** Alignment padding. */
440 bool afAlignment1[5];
441
442 struct
443 {
444 /** Set by the ring-0 side of HM to indicate VMX is supported by the CPU. */
445 bool fSupported;
446 /** Set when we've enabled VMX. */
447 bool fEnabled;
448 /** The shift mask employed by the VMX-Preemption timer (set by ring-0). */
449 uint8_t cPreemptTimerShift;
450 bool fAlignment1;
451
452 /** @name Configuration (gets copied if problematic)
453 * @{ */
454 /** Set if Last Branch Record (LBR) is enabled. */
455 bool fLbrCfg;
456 /** Set if VT-x VPID is allowed. */
457 bool fAllowVpid;
458 /** Set if unrestricted guest execution is in use (real and protected mode
459 * without paging). */
460 bool fUnrestrictedGuestCfg;
461 /** Set if the preemption timer should be used if available. Ring-0
462 * quietly clears this if the hardware doesn't support the preemption timer. */
463 bool fUsePreemptTimerCfg;
464 /** @} */
465
466 /** Pause-loop exiting (PLE) gap in ticks. */
467 uint32_t cPleGapTicks;
468 /** Pause-loop exiting (PLE) window in ticks. */
469 uint32_t cPleWindowTicks;
470
471 /** Virtual address of the TSS page used for real mode emulation. */
472 R3PTRTYPE(PVBOXTSS) pRealModeTSS;
473 /** Virtual address of the identity page table used for real mode and protected
474 * mode without paging emulation in EPT mode. */
475 R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
476 } vmx;
477
478 struct
479 {
480 /** Set by the ring-0 side of HM to indicate SVM is supported by the CPU. */
481 bool fSupported;
482 /** Set when we've enabled SVM. */
483 bool fEnabled;
484 /** Set when the hack to ignore VERR_SVM_IN_USE is active.
485 * @todo Safe? */
486 bool fIgnoreInUseError;
487 /** Whether to use virtualized VMSAVE/VMLOAD feature. */
488 bool fVirtVmsaveVmload;
489 /** Whether to use virtual GIF feature. */
490 bool fVGif;
491 /** Whether to use LBR virtualization feature. */
492 bool fLbrVirt;
493 bool afAlignment1[2];
494
495 /** Pause filter counter. */
496 uint16_t cPauseFilter;
497 /** Pause filter treshold in ticks. */
498 uint16_t cPauseFilterThresholdTicks;
499 uint32_t u32Alignment2;
500 } svm;
501
502 /** AVL tree with all patches (active or disabled) sorted by guest instruction address.
503 * @todo For @bugref{9217} this AVL tree must be eliminated and instead
504 * sort aPatches by address and do a safe binary search on it. */
505 AVLOU32TREE PatchTree;
506 uint32_t cPatches;
507 HMTPRPATCH aPatches[64];
508
509 /** Guest allocated memory for patching purposes. */
510 RTGCPTR pGuestPatchMem;
511 /** Current free pointer inside the patch block. */
512 RTGCPTR pFreeGuestPatchMem;
513 /** Size of the guest patch memory block. */
514 uint32_t cbGuestPatchMem;
515 uint32_t u32Alignment2;
516
517 /** For ring-3 use only. */
518 struct
519 {
520 /** Last recorded error code during HM ring-0 init. */
521 int32_t rcInit;
522 uint32_t u32Alignment3;
523
524 /** Maximum ASID allowed.
525 * This is mainly for the release log. */
526 uint32_t uMaxAsid;
527 /** World switcher flags (HM_WSF_XXX) for the release log. */
528 uint32_t fWorldSwitcher;
529
530 struct
531 {
532 /** Set if VPID is supported (ring-3 copy). */
533 bool fVpid;
534 /** Whether the CPU supports VMCS fields for swapping EFER (set by ring-0 VMX
535 * init, for logging). */
536 bool fSupportsVmcsEfer;
537 /** Whether to use VMCS shadowing. */
538 bool fUseVmcsShadowing;
539 bool fAlignment2;
540
541 /** Host CR4 value (set by ring-0 VMX init, for logging). */
542 uint64_t u64HostCr4;
543 /** Host SMM monitor control (set by ring-0 VMX init, for logging). */
544 uint64_t u64HostSmmMonitorCtl;
545 /** Host EFER value (set by ring-0 VMX init, for logging and guest NX). */
546 uint64_t u64HostMsrEfer;
547 /** Host IA32_FEATURE_CONTROL MSR (set by ring-0 VMX init, for logging). */
548 uint64_t u64HostFeatCtrl;
549
550 /** The first valid host LBR branch-from-IP stack range. */
551 uint32_t idLbrFromIpMsrFirst;
552 /** The last valid host LBR branch-from-IP stack range. */
553 uint32_t idLbrFromIpMsrLast;
554
555 /** The first valid host LBR branch-to-IP stack range. */
556 uint32_t idLbrToIpMsrFirst;
557 /** The last valid host LBR branch-to-IP stack range. */
558 uint32_t idLbrToIpMsrLast;
559
560 /** Host-physical address for a failing VMXON instruction (for diagnostics, ring-3). */
561 RTHCPHYS HCPhysVmxEnableError;
562 /** VMX MSR values (only for ring-3 consumption). */
563 VMXMSRS Msrs;
564
565 /** Tagged-TLB flush type (only for ring-3 consumption). */
566 VMXTLBFLUSHTYPE enmTlbFlushType;
567 /** Flush type to use for INVEPT (only for ring-3 consumption). */
568 VMXTLBFLUSHEPT enmTlbFlushEpt;
569 /** Flush type to use for INVVPID (only for ring-3 consumption). */
570 VMXTLBFLUSHVPID enmTlbFlushVpid;
571 } vmx;
572
573 struct
574 {
575 /** SVM revision. */
576 uint32_t u32Rev;
577 /** SVM feature bits from cpuid 0x8000000a, ring-3 copy. */
578 uint32_t fFeatures;
579 /** HWCR MSR (for diagnostics). */
580 uint64_t u64MsrHwcr;
581 } svm;
582 } ForR3;
583
584 /** @name Configuration not used (much) after VM setup
585 * @{ */
586 /** The maximum number of resumes loops allowed in ring-0 (safety precaution).
587 * This number is set much higher when RTThreadPreemptIsPending is reliable. */
588 uint32_t cMaxResumeLoopsCfg;
589 /** Set if nested paging is enabled.
590 * Config value that is copied to HMR0PERVM::fNestedPaging on setup. */
591 bool fNestedPagingCfg;
592 /** Set if large pages are enabled (requires nested paging).
593 * Config only, passed on the PGM where it really belongs.
594 * @todo move to PGM */
595 bool fLargePages;
596 /** Set if we can support 64-bit guests or not.
597 * Config value that is copied to HMR0PERVM::fAllow64BitGuests on setup. */
598 bool fAllow64BitGuestsCfg;
599 /** Set when we initialize VT-x or AMD-V once for all CPUs. */
600 bool fGlobalInit;
601 /** Set if hardware APIC virtualization is enabled.
602 * @todo Not really used by HM, move to APIC where it's actually used. */
603 bool fVirtApicRegs;
604 /** Set if posted interrupt processing is enabled.
605 * @todo Not really used by HM, move to APIC where it's actually used. */
606 bool fPostedIntrs;
607 /** @} */
608
609 /** @name Processed into HMR0PERVCPU::fWorldSwitcher by ring-0 on VM init.
610 * @{ */
611 /** Set if indirect branch prediction barrier on VM exit. */
612 bool fIbpbOnVmExit;
613 /** Set if indirect branch prediction barrier on VM entry. */
614 bool fIbpbOnVmEntry;
615 /** Set if level 1 data cache should be flushed on VM entry. */
616 bool fL1dFlushOnVmEntry;
617 /** Set if level 1 data cache should be flushed on EMT scheduling. */
618 bool fL1dFlushOnSched;
619 /** Set if MDS related buffers should be cleared on VM entry. */
620 bool fMdsClearOnVmEntry;
621 /** Set if MDS related buffers should be cleared on EMT scheduling. */
622 bool fMdsClearOnSched;
623 /** Set if host manages speculation control settings.
624 * @todo doesn't do anything ... */
625 bool fSpecCtrlByHost;
626 /** @} */
627
628 /** Set when we've finalized the VMX / SVM initialization in ring-3
629 * (hmR3InitFinalizeR0Intel / hmR3InitFinalizeR0Amd). */
630 bool fInitialized;
631
632 bool afAlignment2[6];
633
634 STAMCOUNTER StatTprPatchSuccess;
635 STAMCOUNTER StatTprPatchFailure;
636 STAMCOUNTER StatTprReplaceSuccessCr8;
637 STAMCOUNTER StatTprReplaceSuccessVmc;
638 STAMCOUNTER StatTprReplaceFailure;
639} HM;
640/** Pointer to HM VM instance data. */
641typedef HM *PHM;
642AssertCompileMemberAlignment(HM, StatTprPatchSuccess, 8);
643AssertCompileMemberAlignment(HM, vmx, 8);
644AssertCompileMemberAlignment(HM, svm, 8);
645AssertCompileMemberAlignment(HM, StatTprPatchSuccess, 8);
646AssertCompile(RTASSERT_OFFSET_OF(HM, PatchTree) <= 64); /* First cache line has the essentials for both VT-x and SVM operation. */
647
648
649/**
650 * Per-VM ring-0 instance data for HM.
651 */
652typedef struct HMR0PERVM
653{
654 /** The maximum number of resumes loops allowed in ring-0 (safety precaution).
655 * This number is set much higher when RTThreadPreemptIsPending is reliable. */
656 uint32_t cMaxResumeLoops;
657
658 /** Set if nested paging is enabled. */
659 bool fNestedPaging;
660 /** Set if we can support 64-bit guests or not. */
661 bool fAllow64BitGuests;
662 bool afAlignment1[1];
663
664 /** AMD-V specific data. */
665 struct HMR0SVMVM
666 {
667 /** Set if erratum 170 affects the AMD cpu. */
668 bool fAlwaysFlushTLB;
669 } svm;
670
671 /** VT-x specific data. */
672 struct HMR0VMXVM
673 {
674 /** Set if unrestricted guest execution is in use (real and protected mode
675 * without paging). */
676 bool fUnrestrictedGuest;
677 /** Set if the preemption timer is in use. */
678 bool fUsePreemptTimer;
679 /** Whether to use VMCS shadowing. */
680 bool fUseVmcsShadowing;
681 /** Set if Last Branch Record (LBR) is enabled. */
682 bool fLbr;
683 bool afAlignment2[3];
684
685 /** Set if VPID is supported (copy in HM::vmx::fVpidForRing3). */
686 bool fVpid;
687 /** Tagged-TLB flush type. */
688 VMXTLBFLUSHTYPE enmTlbFlushType;
689 /** Flush type to use for INVEPT. */
690 VMXTLBFLUSHEPT enmTlbFlushEpt;
691 /** Flush type to use for INVVPID. */
692 VMXTLBFLUSHVPID enmTlbFlushVpid;
693
694 /** The host LBR TOS (top-of-stack) MSR id. */
695 uint32_t idLbrTosMsr;
696
697 /** The first valid host LBR branch-from-IP stack range. */
698 uint32_t idLbrFromIpMsrFirst;
699 /** The last valid host LBR branch-from-IP stack range. */
700 uint32_t idLbrFromIpMsrLast;
701
702 /** The first valid host LBR branch-to-IP stack range. */
703 uint32_t idLbrToIpMsrFirst;
704 /** The last valid host LBR branch-to-IP stack range. */
705 uint32_t idLbrToIpMsrLast;
706
707 /** Pointer to the VMREAD bitmap. */
708 R0PTRTYPE(void *) pvVmreadBitmap;
709 /** Pointer to the VMWRITE bitmap. */
710 R0PTRTYPE(void *) pvVmwriteBitmap;
711
712 /** Pointer to the shadow VMCS read-only fields array. */
713 R0PTRTYPE(uint32_t *) paShadowVmcsRoFields;
714 /** Pointer to the shadow VMCS read/write fields array. */
715 R0PTRTYPE(uint32_t *) paShadowVmcsFields;
716 /** Number of elements in the shadow VMCS read-only fields array. */
717 uint32_t cShadowVmcsRoFields;
718 /** Number of elements in the shadow VMCS read-write fields array. */
719 uint32_t cShadowVmcsFields;
720
721 /** Host-physical address of the APIC-access page. */
722 RTHCPHYS HCPhysApicAccess;
723 /** Host-physical address of the VMREAD bitmap. */
724 RTHCPHYS HCPhysVmreadBitmap;
725 /** Host-physical address of the VMWRITE bitmap. */
726 RTHCPHYS HCPhysVmwriteBitmap;
727
728#ifdef VBOX_WITH_CRASHDUMP_MAGIC
729 /** Host-physical address of the crash-dump scratch area. */
730 RTHCPHYS HCPhysScratch;
731 /** Pointer to the crash-dump scratch bitmap. */
732 R0PTRTYPE(uint8_t *) pbScratch;
733#endif
734
735 /** Ring-0 memory object for per-VM VMX structures. */
736 RTR0MEMOBJ hMemObj;
737 /** Virtual address of the APIC-access page (not used). */
738 R0PTRTYPE(uint8_t *) pbApicAccess;
739 } vmx;
740} HMR0PERVM;
741/** Pointer to HM's per-VM ring-0 instance data. */
742typedef HMR0PERVM *PHMR0PERVM;
743
744
745/** @addtogroup grp_hm_int_svm SVM Internal
746 * @{ */
747/** SVM VMRun function, see SVMR0VMRun(). */
748typedef DECLCALLBACKTYPE(int, FNHMSVMVMRUN,(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhysVMCB));
749/** Pointer to a SVM VMRun function. */
750typedef R0PTRTYPE(FNHMSVMVMRUN *) PFNHMSVMVMRUN;
751
752/**
753 * SVM nested-guest VMCB cache.
754 *
755 * Contains VMCB fields from the nested-guest VMCB before they're modified by
756 * SVM R0 code for hardware-assisted SVM execution of a nested-guest.
757 *
758 * A VMCB field needs to be cached when it needs to be modified for execution using
759 * hardware-assisted SVM and any of the following are true:
760 * - If the original field needs to be inspected during execution of the
761 * nested-guest or \#VMEXIT processing.
762 * - If the field is written back to memory on \#VMEXIT by the physical CPU.
763 *
764 * A VMCB field needs to be restored only when the field is written back to
765 * memory on \#VMEXIT by the physical CPU and thus would be visible to the
766 * guest.
767 *
768 * @remarks Please update hmR3InfoSvmNstGstVmcbCache() when changes are made to
769 * this structure.
770 */
771typedef struct SVMNESTEDVMCBCACHE
772{
773 /** Cache of CRX read intercepts. */
774 uint16_t u16InterceptRdCRx;
775 /** Cache of CRX write intercepts. */
776 uint16_t u16InterceptWrCRx;
777 /** Cache of DRX read intercepts. */
778 uint16_t u16InterceptRdDRx;
779 /** Cache of DRX write intercepts. */
780 uint16_t u16InterceptWrDRx;
781
782 /** Cache of the pause-filter threshold. */
783 uint16_t u16PauseFilterThreshold;
784 /** Cache of the pause-filter count. */
785 uint16_t u16PauseFilterCount;
786
787 /** Cache of exception intercepts. */
788 uint32_t u32InterceptXcpt;
789 /** Cache of control intercepts. */
790 uint64_t u64InterceptCtrl;
791
792 /** Cache of the TSC offset. */
793 uint64_t u64TSCOffset;
794
795 /** Cache of V_INTR_MASKING bit. */
796 bool fVIntrMasking;
797 /** Cache of the nested-paging bit. */
798 bool fNestedPaging;
799 /** Cache of the LBR virtualization bit. */
800 bool fLbrVirt;
801 /** Whether the VMCB is cached by HM. */
802 bool fCacheValid;
803 /** Alignment. */
804 bool afPadding0[4];
805} SVMNESTEDVMCBCACHE;
806/** Pointer to the SVMNESTEDVMCBCACHE structure. */
807typedef SVMNESTEDVMCBCACHE *PSVMNESTEDVMCBCACHE;
808/** Pointer to a const SVMNESTEDVMCBCACHE structure. */
809typedef const SVMNESTEDVMCBCACHE *PCSVMNESTEDVMCBCACHE;
810AssertCompileSizeAlignment(SVMNESTEDVMCBCACHE, 8);
811
812/** @} */
813
814
815/** @addtogroup grp_hm_int_vmx VMX Internal
816 * @{ */
817/**
818 * VMX VMCS information, shared.
819 *
820 * This structure provides information maintained for and during the executing of a
821 * guest (or nested-guest) VMCS (VM control structure) using hardware-assisted VMX.
822 *
823 * Note! The members here are ordered and aligned based on estimated frequency of
824 * usage and grouped to fit within a cache line in hot code paths. Even subtle
825 * changes here have a noticeable effect in the bootsector benchmarks. Modify with
826 * care.
827 */
828typedef struct VMXVMCSINFOSHARED
829{
830 /** @name Real-mode emulation state.
831 * @{ */
832 /** Set if guest was executing in real mode (extra checks). */
833 bool fWasInRealMode;
834 /** Padding. */
835 bool afPadding0[7];
836 struct
837 {
838 X86DESCATTR AttrCS;
839 X86DESCATTR AttrDS;
840 X86DESCATTR AttrES;
841 X86DESCATTR AttrFS;
842 X86DESCATTR AttrGS;
843 X86DESCATTR AttrSS;
844 X86EFLAGS Eflags;
845 bool fRealOnV86Active;
846 bool afPadding1[3];
847 } RealMode;
848 /** @} */
849
850 /** @name LBR MSR data.
851 * @{ */
852 /** List of LastBranch-From-IP MSRs. */
853 uint64_t au64LbrFromIpMsr[32];
854 /** List of LastBranch-To-IP MSRs. */
855 uint64_t au64LbrToIpMsr[32];
856 /** The MSR containing the index to the most recent branch record. */
857 uint64_t u64LbrTosMsr;
858 /** @} */
859} VMXVMCSINFOSHARED;
860/** Pointer to a VMXVMCSINFOSHARED struct. */
861typedef VMXVMCSINFOSHARED *PVMXVMCSINFOSHARED;
862/** Pointer to a const VMXVMCSINFOSHARED struct. */
863typedef const VMXVMCSINFOSHARED *PCVMXVMCSINFOSHARED;
864AssertCompileSizeAlignment(VMXVMCSINFOSHARED, 8);
865
866
867/**
868 * VMX VMCS information, ring-0 only.
869 *
870 * This structure provides information maintained for and during the executing of a
871 * guest (or nested-guest) VMCS (VM control structure) using hardware-assisted VMX.
872 *
873 * Note! The members here are ordered and aligned based on estimated frequency of
874 * usage and grouped to fit within a cache line in hot code paths. Even subtle
875 * changes here have a noticeable effect in the bootsector benchmarks. Modify with
876 * care.
877 */
878typedef struct VMXVMCSINFO
879{
880 /** Pointer to the bits we share with ring-3. */
881 R0PTRTYPE(PVMXVMCSINFOSHARED) pShared;
882
883 /** @name Auxiliary information.
884 * @{ */
885 /** Host-physical address of the EPTP. */
886 RTHCPHYS HCPhysEPTP;
887 /** The VMCS launch state, see VMX_V_VMCS_LAUNCH_STATE_XXX. */
888 uint32_t fVmcsState;
889 /** The VMCS launch state of the shadow VMCS, see VMX_V_VMCS_LAUNCH_STATE_XXX. */
890 uint32_t fShadowVmcsState;
891 /** The host CPU for which its state has been exported to this VMCS. */
892 RTCPUID idHostCpuState;
893 /** The host CPU on which we last executed this VMCS. */
894 RTCPUID idHostCpuExec;
895 /** Number of guest MSRs in the VM-entry MSR-load area. */
896 uint32_t cEntryMsrLoad;
897 /** Number of guest MSRs in the VM-exit MSR-store area. */
898 uint32_t cExitMsrStore;
899 /** Number of host MSRs in the VM-exit MSR-load area. */
900 uint32_t cExitMsrLoad;
901 /** @} */
902
903 /** @name Cache of execution related VMCS fields.
904 * @{ */
905 /** Pin-based VM-execution controls. */
906 uint32_t u32PinCtls;
907 /** Processor-based VM-execution controls. */
908 uint32_t u32ProcCtls;
909 /** Secondary processor-based VM-execution controls. */
910 uint32_t u32ProcCtls2;
911 /** VM-entry controls. */
912 uint32_t u32EntryCtls;
913 /** VM-exit controls. */
914 uint32_t u32ExitCtls;
915 /** Exception bitmap. */
916 uint32_t u32XcptBitmap;
917 /** Page-fault exception error-code mask. */
918 uint32_t u32XcptPFMask;
919 /** Page-fault exception error-code match. */
920 uint32_t u32XcptPFMatch;
921 /** Padding. */
922 uint32_t u32Alignment0;
923 /** TSC offset. */
924 uint64_t u64TscOffset;
925 /** VMCS link pointer. */
926 uint64_t u64VmcsLinkPtr;
927 /** CR0 guest/host mask. */
928 uint64_t u64Cr0Mask;
929 /** CR4 guest/host mask. */
930 uint64_t u64Cr4Mask;
931 /** Current VMX_VMCS_HOST_RIP value (only used in HMR0A.asm). */
932 uint64_t uHostRip;
933 /** Current VMX_VMCS_HOST_RSP value (only used in HMR0A.asm). */
934 uint64_t uHostRsp;
935 /** @} */
936
937 /** @name Host-virtual address of VMCS and related data structures.
938 * @{ */
939 /** The VMCS. */
940 R0PTRTYPE(void *) pvVmcs;
941 /** The shadow VMCS. */
942 R0PTRTYPE(void *) pvShadowVmcs;
943 /** The virtual-APIC page. */
944 R0PTRTYPE(uint8_t *) pbVirtApic;
945 /** The MSR bitmap. */
946 R0PTRTYPE(void *) pvMsrBitmap;
947 /** The VM-entry MSR-load area. */
948 R0PTRTYPE(void *) pvGuestMsrLoad;
949 /** The VM-exit MSR-store area. */
950 R0PTRTYPE(void *) pvGuestMsrStore;
951 /** The VM-exit MSR-load area. */
952 R0PTRTYPE(void *) pvHostMsrLoad;
953 /** @} */
954
955 /** @name Host-physical address of VMCS and related data structures.
956 * @{ */
957 /** The VMCS. */
958 RTHCPHYS HCPhysVmcs;
959 /** The shadow VMCS. */
960 RTHCPHYS HCPhysShadowVmcs;
961 /** The virtual APIC page. */
962 RTHCPHYS HCPhysVirtApic;
963 /** The MSR bitmap. */
964 RTHCPHYS HCPhysMsrBitmap;
965 /** The VM-entry MSR-load area. */
966 RTHCPHYS HCPhysGuestMsrLoad;
967 /** The VM-exit MSR-store area. */
968 RTHCPHYS HCPhysGuestMsrStore;
969 /** The VM-exit MSR-load area. */
970 RTHCPHYS HCPhysHostMsrLoad;
971 /** @} */
972
973 /** @name R0-memory objects address for VMCS and related data structures.
974 * @{ */
975 /** R0-memory object for VMCS and related data structures. */
976 RTR0MEMOBJ hMemObj;
977 /** @} */
978} VMXVMCSINFO;
979/** Pointer to a VMXVMCSINFOR0 struct. */
980typedef VMXVMCSINFO *PVMXVMCSINFO;
981/** Pointer to a const VMXVMCSINFO struct. */
982typedef const VMXVMCSINFO *PCVMXVMCSINFO;
983AssertCompileSizeAlignment(VMXVMCSINFO, 8);
984AssertCompileMemberAlignment(VMXVMCSINFO, u32PinCtls, 4);
985AssertCompileMemberAlignment(VMXVMCSINFO, u64VmcsLinkPtr, 8);
986AssertCompileMemberAlignment(VMXVMCSINFO, pvVmcs, 8);
987AssertCompileMemberAlignment(VMXVMCSINFO, pvShadowVmcs, 8);
988AssertCompileMemberAlignment(VMXVMCSINFO, pbVirtApic, 8);
989AssertCompileMemberAlignment(VMXVMCSINFO, pvMsrBitmap, 8);
990AssertCompileMemberAlignment(VMXVMCSINFO, pvGuestMsrLoad, 8);
991AssertCompileMemberAlignment(VMXVMCSINFO, pvGuestMsrStore, 8);
992AssertCompileMemberAlignment(VMXVMCSINFO, pvHostMsrLoad, 8);
993AssertCompileMemberAlignment(VMXVMCSINFO, HCPhysVmcs, 8);
994AssertCompileMemberAlignment(VMXVMCSINFO, hMemObj, 8);
995
996
997/** @name Host-state restoration flags.
998 * @note If you change these values don't forget to update the assembly
999 * defines as well!
1000 * @{
1001 */
1002#define VMX_RESTORE_HOST_SEL_DS RT_BIT(0)
1003#define VMX_RESTORE_HOST_SEL_ES RT_BIT(1)
1004#define VMX_RESTORE_HOST_SEL_FS RT_BIT(2)
1005#define VMX_RESTORE_HOST_SEL_GS RT_BIT(3)
1006#define VMX_RESTORE_HOST_SEL_TR RT_BIT(4)
1007#define VMX_RESTORE_HOST_GDTR RT_BIT(5)
1008#define VMX_RESTORE_HOST_IDTR RT_BIT(6)
1009#define VMX_RESTORE_HOST_GDT_READ_ONLY RT_BIT(7)
1010#define VMX_RESTORE_HOST_GDT_NEED_WRITABLE RT_BIT(8)
1011#define VMX_RESTORE_HOST_CAN_USE_WRFSBASE_AND_WRGSBASE RT_BIT(9)
1012/**
1013 * This _must_ be the top most bit, so that we can easily check that it and
1014 * something else is set w/o having to do two checks like this:
1015 * @code
1016 * if ( (pVCpu->hm.s.vmx.fRestoreHostFlags & VMX_RESTORE_HOST_REQUIRED)
1017 * && (pVCpu->hm.s.vmx.fRestoreHostFlags & ~VMX_RESTORE_HOST_REQUIRED))
1018 * @endcode
1019 * Instead we can then do:
1020 * @code
1021 * if (pVCpu->hm.s.vmx.fRestoreHostFlags > VMX_RESTORE_HOST_REQUIRED)
1022 * @endcode
1023 */
1024#define VMX_RESTORE_HOST_REQUIRED RT_BIT(10)
1025/** @} */
1026
1027/**
1028 * Host-state restoration structure.
1029 *
1030 * This holds host-state fields that require manual restoration.
1031 * Assembly version found in HMInternal.mac (should be automatically verified).
1032 */
1033typedef struct VMXRESTOREHOST
1034{
1035 RTSEL uHostSelDS; /**< 0x00 */
1036 RTSEL uHostSelES; /**< 0x02 */
1037 RTSEL uHostSelFS; /**< 0x04 */
1038 X86XDTR64 HostGdtr; /**< 0x06 - should be aligned by its 64-bit member. */
1039 RTSEL uHostSelGS; /**< 0x10 */
1040 RTSEL uHostSelTR; /**< 0x12 */
1041 RTSEL uHostSelSS; /**< 0x14 - not restored, just for fetching */
1042 X86XDTR64 HostGdtrRw; /**< 0x16 - should be aligned by its 64-bit member. */
1043 RTSEL uHostSelCS; /**< 0x20 - not restored, just for fetching */
1044 uint8_t abPadding1[4]; /**< 0x22 */
1045 X86XDTR64 HostIdtr; /**< 0x26 - should be aligned by its 64-bit member. */
1046 uint64_t uHostFSBase; /**< 0x30 */
1047 uint64_t uHostGSBase; /**< 0x38 */
1048} VMXRESTOREHOST;
1049/** Pointer to VMXRESTOREHOST. */
1050typedef VMXRESTOREHOST *PVMXRESTOREHOST;
1051AssertCompileSize(X86XDTR64, 10);
1052AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtr.uAddr, 0x08);
1053AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtrRw.uAddr, 0x18);
1054AssertCompileMemberOffset(VMXRESTOREHOST, HostIdtr.uAddr, 0x28);
1055AssertCompileMemberOffset(VMXRESTOREHOST, uHostFSBase, 0x30);
1056AssertCompileSize(VMXRESTOREHOST, 64);
1057AssertCompileSizeAlignment(VMXRESTOREHOST, 8);
1058
1059/**
1060 * VMX StartVM function.
1061 *
1062 * @returns VBox status code (no informational stuff).
1063 * @param pVmcsInfo Pointer to the VMCS info (for cached host RIP and RSP).
1064 * @param pVCpu Pointer to the cross context per-CPU structure.
1065 * @param fResume Whether to use VMRESUME (true) or VMLAUNCH (false).
1066 */
1067typedef DECLCALLBACKTYPE(int, FNHMVMXSTARTVM,(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume));
1068/** Pointer to a VMX StartVM function. */
1069typedef R0PTRTYPE(FNHMVMXSTARTVM *) PFNHMVMXSTARTVM;
1070/** @} */
1071
1072/**
1073 * HM VMCPU Instance data.
1074 *
1075 * Note! If you change members of this struct, make sure to check if the
1076 * assembly counterpart in HMInternal.mac needs to be updated as well.
1077 *
1078 * Note! The members here are ordered and aligned based on estimated frequency of
1079 * usage and grouped to fit within a cache line in hot code paths. Even subtle
1080 * changes here have a noticeable effect in the bootsector benchmarks. Modify with
1081 * care.
1082 */
1083typedef struct HMCPU
1084{
1085 /** Set when the TLB has been checked until we return from the world switch. */
1086 bool volatile fCheckedTLBFlush;
1087 /** Set when we're using VT-x or AMD-V at that moment.
1088 * @todo r=bird: Misleading description. For AMD-V this will be set the first
1089 * time HMCanExecuteGuest() is called and only cleared again by
1090 * HMR3ResetCpu(). For VT-x it will be set by HMCanExecuteGuest when we
1091 * can execute something in VT-x mode, and cleared if we cannot.
1092 *
1093 * The field is much more about recording the last HMCanExecuteGuest
1094 * return value than anything about any "moment". */
1095 bool fActive;
1096
1097 /** Whether we should use the debug loop because of single stepping or special
1098 * debug breakpoints / events are armed. */
1099 bool fUseDebugLoop;
1100
1101 /** Whether \#UD needs to be intercepted (required by certain GIM providers). */
1102 bool fGIMTrapXcptUD;
1103 /** Whether \#GP needs to be intercepted for mesa driver workaround. */
1104 bool fTrapXcptGpForLovelyMesaDrv;
1105 /** Whether we're executing a single instruction. */
1106 bool fSingleInstruction;
1107
1108 bool afAlignment0[2];
1109
1110 /** An additional error code used for some gurus. */
1111 uint32_t u32HMError;
1112 /** The last exit-to-ring-3 reason. */
1113 int32_t rcLastExitToR3;
1114 /** CPU-context changed flags (see HM_CHANGED_xxx). */
1115 uint64_t fCtxChanged;
1116
1117 /** VT-x data. */
1118 struct HMCPUVMX
1119 {
1120 /** @name Guest information.
1121 * @{ */
1122 /** Guest VMCS information shared with ring-3. */
1123 VMXVMCSINFOSHARED VmcsInfo;
1124 /** Nested-guest VMCS information shared with ring-3. */
1125 VMXVMCSINFOSHARED VmcsInfoNstGst;
1126 /** Whether the nested-guest VMCS was the last current VMCS (shadow copy for ring-3).
1127 * @see HMR0PERVCPU::vmx.fSwitchedToNstGstVmcs */
1128 bool fSwitchedToNstGstVmcsCopyForRing3;
1129 /** Whether the static guest VMCS controls has been merged with the
1130 * nested-guest VMCS controls. */
1131 bool fMergedNstGstCtls;
1132 /** Whether the nested-guest VMCS has been copied to the shadow VMCS. */
1133 bool fCopiedNstGstToShadowVmcs;
1134 /** Whether flushing the TLB is required due to switching to/from the
1135 * nested-guest. */
1136 bool fSwitchedNstGstFlushTlb;
1137 /** Alignment. */
1138 bool afAlignment0[4];
1139 /** Cached guest APIC-base MSR for identifying when to map the APIC-access page. */
1140 uint64_t u64GstMsrApicBase;
1141 /** @} */
1142
1143 /** @name Error reporting and diagnostics.
1144 * @{ */
1145 /** VT-x error-reporting (mainly for ring-3 propagation). */
1146 struct
1147 {
1148 RTCPUID idCurrentCpu;
1149 RTCPUID idEnteredCpu;
1150 RTHCPHYS HCPhysCurrentVmcs;
1151 uint32_t u32VmcsRev;
1152 uint32_t u32InstrError;
1153 uint32_t u32ExitReason;
1154 uint32_t u32GuestIntrState;
1155 } LastError;
1156 /** @} */
1157 } vmx;
1158
1159 /** SVM data. */
1160 struct HMCPUSVM
1161 {
1162 /** Whether to emulate long mode support for sysenter/sysexit like intel CPUs
1163 * does. This means intercepting \#UD to emulate the instructions in
1164 * long-mode and to intercept reads and writes to the SYSENTER MSRs in order to
1165 * preserve the upper 32 bits written to them (AMD will ignore and discard). */
1166 bool fEmulateLongModeSysEnterExit;
1167 uint8_t au8Alignment0[7];
1168
1169 /** Cache of the nested-guest's VMCB fields that we modify in order to run the
1170 * nested-guest using AMD-V. This will be restored on \#VMEXIT. */
1171 SVMNESTEDVMCBCACHE NstGstVmcbCache;
1172 } svm;
1173
1174 /** Event injection state. */
1175 HMEVENT Event;
1176
1177 /** Current shadow paging mode for updating CR4.
1178 * @todo move later (@bugref{9217}). */
1179 PGMMODE enmShadowMode;
1180 uint32_t u32TemporaryPadding;
1181
1182 /** The PAE PDPEs used with Nested Paging (only valid when
1183 * VMCPU_FF_HM_UPDATE_PAE_PDPES is set). */
1184 X86PDPE aPdpes[4];
1185
1186 /* These two comes because they are accessed from assembly and we don't
1187 want to detail all the stats in the assembly version of this structure. */
1188 STAMCOUNTER StatVmxWriteHostRip;
1189 STAMCOUNTER StatVmxWriteHostRsp;
1190 STAMCOUNTER StatVmxVmLaunch;
1191 STAMCOUNTER StatVmxVmResume;
1192
1193 STAMPROFILEADV StatEntry;
1194 STAMPROFILEADV StatPreExit;
1195 STAMPROFILEADV StatExitHandling;
1196 STAMPROFILEADV StatExitIO;
1197 STAMPROFILEADV StatExitMovCRx;
1198 STAMPROFILEADV StatExitXcptNmi;
1199 STAMPROFILEADV StatExitVmentry;
1200 STAMPROFILEADV StatImportGuestState;
1201 STAMPROFILEADV StatExportGuestState;
1202 STAMPROFILEADV StatLoadGuestFpuState;
1203 STAMPROFILEADV StatInGC;
1204 STAMPROFILEADV StatPoke;
1205 STAMPROFILEADV StatSpinPoke;
1206 STAMPROFILEADV StatSpinPokeFailed;
1207
1208 STAMCOUNTER StatInjectInterrupt;
1209 STAMCOUNTER StatInjectXcpt;
1210 STAMCOUNTER StatInjectReflect;
1211 STAMCOUNTER StatInjectConvertDF;
1212 STAMCOUNTER StatInjectInterpret;
1213 STAMCOUNTER StatInjectReflectNPF;
1214
1215 STAMCOUNTER StatExitAll;
1216 STAMCOUNTER StatNestedExitAll;
1217 STAMCOUNTER StatExitShadowNM;
1218 STAMCOUNTER StatExitGuestNM;
1219 STAMCOUNTER StatExitShadowPF; /**< Misleading, currently used for MMIO \#PFs as well. */
1220 STAMCOUNTER StatExitShadowPFEM;
1221 STAMCOUNTER StatExitGuestPF;
1222 STAMCOUNTER StatExitGuestUD;
1223 STAMCOUNTER StatExitGuestSS;
1224 STAMCOUNTER StatExitGuestNP;
1225 STAMCOUNTER StatExitGuestTS;
1226 STAMCOUNTER StatExitGuestOF;
1227 STAMCOUNTER StatExitGuestGP;
1228 STAMCOUNTER StatExitGuestDE;
1229 STAMCOUNTER StatExitGuestDF;
1230 STAMCOUNTER StatExitGuestBR;
1231 STAMCOUNTER StatExitGuestAC;
1232 STAMCOUNTER StatExitGuestACSplitLock;
1233 STAMCOUNTER StatExitGuestDB;
1234 STAMCOUNTER StatExitGuestMF;
1235 STAMCOUNTER StatExitGuestBP;
1236 STAMCOUNTER StatExitGuestXF;
1237 STAMCOUNTER StatExitGuestXcpUnk;
1238 STAMCOUNTER StatExitDRxWrite;
1239 STAMCOUNTER StatExitDRxRead;
1240 STAMCOUNTER StatExitCR0Read;
1241 STAMCOUNTER StatExitCR2Read;
1242 STAMCOUNTER StatExitCR3Read;
1243 STAMCOUNTER StatExitCR4Read;
1244 STAMCOUNTER StatExitCR8Read;
1245 STAMCOUNTER StatExitCR0Write;
1246 STAMCOUNTER StatExitCR2Write;
1247 STAMCOUNTER StatExitCR3Write;
1248 STAMCOUNTER StatExitCR4Write;
1249 STAMCOUNTER StatExitCR8Write;
1250 STAMCOUNTER StatExitRdmsr;
1251 STAMCOUNTER StatExitWrmsr;
1252 STAMCOUNTER StatExitClts;
1253 STAMCOUNTER StatExitXdtrAccess;
1254 STAMCOUNTER StatExitLmsw;
1255 STAMCOUNTER StatExitIOWrite;
1256 STAMCOUNTER StatExitIORead;
1257 STAMCOUNTER StatExitIOStringWrite;
1258 STAMCOUNTER StatExitIOStringRead;
1259 STAMCOUNTER StatExitIntWindow;
1260 STAMCOUNTER StatExitExtInt;
1261 STAMCOUNTER StatExitHostNmiInGC;
1262 STAMCOUNTER StatExitHostNmiInGCIpi;
1263 STAMCOUNTER StatExitPreemptTimer;
1264 STAMCOUNTER StatExitTprBelowThreshold;
1265 STAMCOUNTER StatExitTaskSwitch;
1266 STAMCOUNTER StatExitApicAccess;
1267 STAMCOUNTER StatExitReasonNpf;
1268
1269 STAMCOUNTER StatNestedExitReasonNpf;
1270
1271 STAMCOUNTER StatFlushPage;
1272 STAMCOUNTER StatFlushPageManual;
1273 STAMCOUNTER StatFlushPhysPageManual;
1274 STAMCOUNTER StatFlushTlb;
1275 STAMCOUNTER StatFlushTlbNstGst;
1276 STAMCOUNTER StatFlushTlbManual;
1277 STAMCOUNTER StatFlushTlbWorldSwitch;
1278 STAMCOUNTER StatNoFlushTlbWorldSwitch;
1279 STAMCOUNTER StatFlushEntire;
1280 STAMCOUNTER StatFlushAsid;
1281 STAMCOUNTER StatFlushNestedPaging;
1282 STAMCOUNTER StatFlushTlbInvlpgVirt;
1283 STAMCOUNTER StatFlushTlbInvlpgPhys;
1284 STAMCOUNTER StatTlbShootdown;
1285 STAMCOUNTER StatTlbShootdownFlush;
1286
1287 STAMCOUNTER StatSwitchPendingHostIrq;
1288 STAMCOUNTER StatSwitchTprMaskedIrq;
1289 STAMCOUNTER StatSwitchGuestIrq;
1290 STAMCOUNTER StatSwitchHmToR3FF;
1291 STAMCOUNTER StatSwitchVmReq;
1292 STAMCOUNTER StatSwitchPgmPoolFlush;
1293 STAMCOUNTER StatSwitchDma;
1294 STAMCOUNTER StatSwitchExitToR3;
1295 STAMCOUNTER StatSwitchLongJmpToR3;
1296 STAMCOUNTER StatSwitchMaxResumeLoops;
1297 STAMCOUNTER StatSwitchHltToR3;
1298 STAMCOUNTER StatSwitchApicAccessToR3;
1299 STAMCOUNTER StatSwitchPreempt;
1300 STAMCOUNTER StatSwitchNstGstVmexit;
1301
1302 STAMCOUNTER StatTscParavirt;
1303 STAMCOUNTER StatTscOffset;
1304 STAMCOUNTER StatTscIntercept;
1305
1306 STAMCOUNTER StatDRxArmed;
1307 STAMCOUNTER StatDRxContextSwitch;
1308 STAMCOUNTER StatDRxIoCheck;
1309
1310 STAMCOUNTER StatExportMinimal;
1311 STAMCOUNTER StatExportFull;
1312 STAMCOUNTER StatLoadGuestFpu;
1313 STAMCOUNTER StatExportHostState;
1314
1315 STAMCOUNTER StatVmxCheckBadRmSelBase;
1316 STAMCOUNTER StatVmxCheckBadRmSelLimit;
1317 STAMCOUNTER StatVmxCheckBadRmSelAttr;
1318 STAMCOUNTER StatVmxCheckBadV86SelBase;
1319 STAMCOUNTER StatVmxCheckBadV86SelLimit;
1320 STAMCOUNTER StatVmxCheckBadV86SelAttr;
1321 STAMCOUNTER StatVmxCheckRmOk;
1322 STAMCOUNTER StatVmxCheckBadSel;
1323 STAMCOUNTER StatVmxCheckBadRpl;
1324 STAMCOUNTER StatVmxCheckPmOk;
1325
1326 STAMCOUNTER StatVmxPreemptionRecalcingDeadline;
1327 STAMCOUNTER StatVmxPreemptionRecalcingDeadlineExpired;
1328 STAMCOUNTER StatVmxPreemptionReusingDeadline;
1329 STAMCOUNTER StatVmxPreemptionReusingDeadlineExpired;
1330
1331#ifdef VBOX_WITH_STATISTICS
1332 STAMCOUNTER aStatExitReason[MAX_EXITREASON_STAT];
1333 STAMCOUNTER aStatNestedExitReason[MAX_EXITREASON_STAT];
1334 STAMCOUNTER aStatInjectedIrqs[256];
1335 STAMCOUNTER aStatInjectedXcpts[X86_XCPT_LAST + 1];
1336#endif
1337#ifdef HM_PROFILE_EXIT_DISPATCH
1338 STAMPROFILEADV StatExitDispatch;
1339#endif
1340} HMCPU;
1341/** Pointer to HM VMCPU instance data. */
1342typedef HMCPU *PHMCPU;
1343AssertCompileMemberAlignment(HMCPU, fCheckedTLBFlush, 4);
1344AssertCompileMemberAlignment(HMCPU, fCtxChanged, 8);
1345AssertCompileMemberAlignment(HMCPU, vmx, 8);
1346AssertCompileMemberAlignment(HMCPU, vmx.VmcsInfo, 8);
1347AssertCompileMemberAlignment(HMCPU, vmx.VmcsInfoNstGst, 8);
1348AssertCompileMemberAlignment(HMCPU, svm, 8);
1349AssertCompileMemberAlignment(HMCPU, Event, 8);
1350
1351
1352/**
1353 * HM per-VCpu ring-0 only instance data.
1354 */
1355typedef struct HMR0PERVCPU
1356{
1357 /** World switch exit counter. */
1358 uint32_t volatile cWorldSwitchExits;
1359 /** TLB flush count. */
1360 uint32_t cTlbFlushes;
1361 /** The last CPU we were executing code on (NIL_RTCPUID for the first time). */
1362 RTCPUID idLastCpu;
1363 /** The CPU ID of the CPU currently owning the VMCS. Set in
1364 * HMR0Enter and cleared in HMR0Leave. */
1365 RTCPUID idEnteredCpu;
1366 /** Current ASID in use by the VM. */
1367 uint32_t uCurrentAsid;
1368
1369 /** Set if we need to flush the TLB during the world switch. */
1370 bool fForceTLBFlush;
1371 /** Whether we've completed the inner HM leave function. */
1372 bool fLeaveDone;
1373 /** Whether we're using the hyper DR7 or guest DR7. */
1374 bool fUsingHyperDR7;
1375 /** Whether we are currently executing in the debug loop.
1376 * Mainly for assertions. */
1377 bool fUsingDebugLoop;
1378 /** Set if we using the debug loop and wish to intercept RDTSC. */
1379 bool fDebugWantRdTscExit;
1380 /** Set if XCR0 needs to be saved/restored when entering/exiting guest code
1381 * execution. */
1382 bool fLoadSaveGuestXcr0;
1383 /** Set if we need to clear the trap flag because of single stepping. */
1384 bool fClearTrapFlag;
1385
1386 bool afPadding1[1];
1387 /** World switcher flags (HM_WSF_XXX - was CPUMCTX::fWorldSwitcher in 6.1). */
1388 uint32_t fWorldSwitcher;
1389 /** The raw host TSC value from the last VM exit (set by HMR0A.asm). */
1390 uint64_t uTscExit;
1391
1392 /** VT-x data. */
1393 struct HMR0CPUVMX
1394 {
1395 /** Ring-0 pointer to the hardware-assisted VMX execution function. */
1396 PFNHMVMXSTARTVM pfnStartVm;
1397 /** Absolute TSC deadline. */
1398 uint64_t uTscDeadline;
1399 /** The deadline version number. */
1400 uint64_t uTscDeadlineVersion;
1401
1402 /** @name Guest information.
1403 * @{ */
1404 /** Guest VMCS information. */
1405 VMXVMCSINFO VmcsInfo;
1406 /** Nested-guest VMCS information. */
1407 VMXVMCSINFO VmcsInfoNstGst;
1408 /* Whether the nested-guest VMCS was the last current VMCS (authoritative copy).
1409 * @see HMCPU::vmx.fSwitchedToNstGstVmcsCopyForRing3 */
1410 bool fSwitchedToNstGstVmcs;
1411 bool afAlignment0[7];
1412 /** @} */
1413
1414 /** @name Host information.
1415 * @{ */
1416 /** Host LSTAR MSR to restore lazily while leaving VT-x. */
1417 uint64_t u64HostMsrLStar;
1418 /** Host STAR MSR to restore lazily while leaving VT-x. */
1419 uint64_t u64HostMsrStar;
1420 /** Host SF_MASK MSR to restore lazily while leaving VT-x. */
1421 uint64_t u64HostMsrSfMask;
1422 /** Host KernelGS-Base MSR to restore lazily while leaving VT-x. */
1423 uint64_t u64HostMsrKernelGsBase;
1424 /** The mask of lazy MSRs swap/restore state, see VMX_LAZY_MSRS_XXX. */
1425 uint32_t fLazyMsrs;
1426 /** Whether the host MSR values are up-to-date in the auto-load/store MSR area. */
1427 bool fUpdatedHostAutoMsrs;
1428 /** Alignment. */
1429 uint8_t au8Alignment0[3];
1430 /** Which host-state bits to restore before being preempted, see
1431 * VMX_RESTORE_HOST_XXX. */
1432 uint32_t fRestoreHostFlags;
1433 /** Alignment. */
1434 uint32_t u32Alignment0;
1435 /** The host-state restoration structure. */
1436 VMXRESTOREHOST RestoreHost;
1437 /** @} */
1438 } vmx;
1439
1440 /** SVM data. */
1441 struct HMR0CPUSVM
1442 {
1443 /** Ring 0 handlers for VT-x. */
1444 PFNHMSVMVMRUN pfnVMRun;
1445
1446 /** Physical address of the host VMCB which holds additional host-state. */
1447 RTHCPHYS HCPhysVmcbHost;
1448 /** R0 memory object for the host VMCB which holds additional host-state. */
1449 RTR0MEMOBJ hMemObjVmcbHost;
1450
1451 /** Physical address of the guest VMCB. */
1452 RTHCPHYS HCPhysVmcb;
1453 /** R0 memory object for the guest VMCB. */
1454 RTR0MEMOBJ hMemObjVmcb;
1455 /** Pointer to the guest VMCB. */
1456 R0PTRTYPE(PSVMVMCB) pVmcb;
1457
1458 /** Physical address of the MSR bitmap (8 KB). */
1459 RTHCPHYS HCPhysMsrBitmap;
1460 /** R0 memory object for the MSR bitmap (8 KB). */
1461 RTR0MEMOBJ hMemObjMsrBitmap;
1462 /** Pointer to the MSR bitmap. */
1463 R0PTRTYPE(void *) pvMsrBitmap;
1464
1465 /** Whether VTPR with V_INTR_MASKING set is in effect, indicating
1466 * we should check if the VTPR changed on every VM-exit. */
1467 bool fSyncVTpr;
1468 bool afAlignment[7];
1469
1470 /** Host's TSC_AUX MSR (used when RDTSCP doesn't cause VM-exits). */
1471 uint64_t u64HostTscAux;
1472
1473 /** For saving stack space, the disassembler state is allocated here
1474 * instead of on the stack. */
1475 DISCPUSTATE DisState;
1476 } svm;
1477} HMR0PERVCPU;
1478/** Pointer to HM ring-0 VMCPU instance data. */
1479typedef HMR0PERVCPU *PHMR0PERVCPU;
1480AssertCompileMemberAlignment(HMR0PERVCPU, cWorldSwitchExits, 4);
1481AssertCompileMemberAlignment(HMR0PERVCPU, fForceTLBFlush, 4);
1482AssertCompileMemberAlignment(HMR0PERVCPU, vmx.RestoreHost, 8);
1483
1484
1485/** @name HM_WSF_XXX - @bugref{9453}, @bugref{9087}
1486 * @note If you change these values don't forget to update the assembly
1487 * defines as well!
1488 * @{ */
1489/** Touch IA32_PRED_CMD.IBPB on VM exit. */
1490#define HM_WSF_IBPB_EXIT RT_BIT_32(0)
1491/** Touch IA32_PRED_CMD.IBPB on VM entry. */
1492#define HM_WSF_IBPB_ENTRY RT_BIT_32(1)
1493/** Touch IA32_FLUSH_CMD.L1D on VM entry. */
1494#define HM_WSF_L1D_ENTRY RT_BIT_32(2)
1495/** Flush MDS buffers on VM entry. */
1496#define HM_WSF_MDS_ENTRY RT_BIT_32(3)
1497
1498/** Touch IA32_FLUSH_CMD.L1D on VM scheduling. */
1499#define HM_WSF_L1D_SCHED RT_BIT_32(16)
1500/** Flush MDS buffers on VM scheduling. */
1501#define HM_WSF_MDS_SCHED RT_BIT_32(17)
1502/** @} */
1503
1504
1505#ifdef IN_RING0
1506extern bool g_fHmVmxSupported;
1507extern uint32_t g_fHmHostKernelFeatures;
1508extern uint32_t g_uHmMaxAsid;
1509extern bool g_fHmVmxUsePreemptTimer;
1510extern uint8_t g_cHmVmxPreemptTimerShift;
1511extern bool g_fHmVmxSupportsVmcsEfer;
1512extern uint64_t g_uHmVmxHostCr4;
1513extern uint64_t g_uHmVmxHostMsrEfer;
1514extern uint64_t g_uHmVmxHostSmmMonitorCtl;
1515extern bool g_fHmSvmSupported;
1516extern uint32_t g_uHmSvmRev;
1517extern uint32_t g_fHmSvmFeatures;
1518
1519extern SUPHWVIRTMSRS g_HmMsrs;
1520
1521
1522VMMR0_INT_DECL(PHMPHYSCPU) hmR0GetCurrentCpu(void);
1523VMMR0_INT_DECL(int) hmR0EnterCpu(PVMCPUCC pVCpu);
1524
1525# ifdef VBOX_STRICT
1526# define HM_DUMP_REG_FLAGS_GPRS RT_BIT(0)
1527# define HM_DUMP_REG_FLAGS_FPU RT_BIT(1)
1528# define HM_DUMP_REG_FLAGS_MSRS RT_BIT(2)
1529# define HM_DUMP_REG_FLAGS_ALL (HM_DUMP_REG_FLAGS_GPRS | HM_DUMP_REG_FLAGS_FPU | HM_DUMP_REG_FLAGS_MSRS)
1530
1531VMMR0_INT_DECL(void) hmR0DumpRegs(PVMCPUCC pVCpu, uint32_t fFlags);
1532VMMR0_INT_DECL(void) hmR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg);
1533# endif
1534
1535DECLASM(void) hmR0MdsClear(void);
1536#endif /* IN_RING0 */
1537
1538
1539/** @addtogroup grp_hm_int_svm SVM Internal
1540 * @{ */
1541VMM_INT_DECL(int) hmEmulateSvmMovTpr(PVMCC pVM, PVMCPUCC pVCpu);
1542
1543/**
1544 * Prepares for and executes VMRUN (64-bit register context).
1545 *
1546 * @returns VBox status code (no informational stuff).
1547 * @param pVM The cross context VM structure. (Not used.)
1548 * @param pVCpu The cross context virtual CPU structure.
1549 * @param HCPhyspVMCB Physical address of the VMCB.
1550 *
1551 * @remarks With spectre mitigations and the usual need for speed (/ micro
1552 * optimizations), we have a bunch of variations of this code depending
1553 * on a few precoditions. In release builds, the code is entirely
1554 * without conditionals. Debug builds have a couple of assertions that
1555 * shouldn't ever be triggered.
1556 *
1557 * @{
1558 */
1559DECLASM(int) hmR0SvmVmRun_SansXcr0_SansIbpbEntry_SansIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1560DECLASM(int) hmR0SvmVmRun_WithXcr0_SansIbpbEntry_SansIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1561DECLASM(int) hmR0SvmVmRun_SansXcr0_WithIbpbEntry_SansIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1562DECLASM(int) hmR0SvmVmRun_WithXcr0_WithIbpbEntry_SansIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1563DECLASM(int) hmR0SvmVmRun_SansXcr0_SansIbpbEntry_WithIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1564DECLASM(int) hmR0SvmVmRun_WithXcr0_SansIbpbEntry_WithIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1565DECLASM(int) hmR0SvmVmRun_SansXcr0_WithIbpbEntry_WithIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1566DECLASM(int) hmR0SvmVmRun_WithXcr0_WithIbpbEntry_WithIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1567/** @} */
1568
1569/** @} */
1570
1571
1572/** @addtogroup grp_hm_int_vmx VMX Internal
1573 * @{ */
1574VMM_INT_DECL(PVMXVMCSINFOSHARED) hmGetVmxActiveVmcsInfoShared(PVMCPUCC pVCpu);
1575
1576/**
1577 * Used on platforms with poor inline assembly support to retrieve all the
1578 * info from the CPU and put it in the @a pRestoreHost structure.
1579 */
1580DECLASM(void) hmR0VmxExportHostSegmentRegsAsmHlp(PVMXRESTOREHOST pRestoreHost, bool fHaveFsGsBase);
1581
1582/**
1583 * Restores some host-state fields that need not be done on every VM-exit.
1584 *
1585 * @returns VBox status code.
1586 * @param fRestoreHostFlags Flags of which host registers needs to be
1587 * restored.
1588 * @param pRestoreHost Pointer to the host-restore structure.
1589 */
1590DECLASM(int) VMXRestoreHostState(uint32_t fRestoreHostFlags, PVMXRESTOREHOST pRestoreHost);
1591
1592/**
1593 * VMX StartVM functions.
1594 *
1595 * @returns VBox status code (no informational stuff).
1596 * @param pVmcsInfo Pointer to the VMCS info (for cached host RIP and RSP).
1597 * @param pVCpu Pointer to the cross context per-CPU structure of the
1598 * calling EMT.
1599 * @param fResume Whether to use VMRESUME (true) or VMLAUNCH (false).
1600 *
1601 * @remarks With spectre mitigations and the usual need for speed (/ micro
1602 * optimizations), we have a bunch of variations of this code depending
1603 * on a few precoditions. In release builds, the code is entirely
1604 * without conditionals. Debug builds have a couple of assertions that
1605 * shouldn't ever be triggered.
1606 *
1607 * @{
1608 */
1609DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_SansL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1610DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_SansL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1611DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_SansL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1612DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_SansL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1613DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_WithL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1614DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_WithL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1615DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_WithL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1616DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_WithL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1617DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_SansL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1618DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_SansL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1619DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_SansL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1620DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_SansL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1621DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_WithL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1622DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_WithL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1623DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_WithL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1624DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_WithL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1625DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_SansL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1626DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_SansL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1627DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_SansL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1628DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_SansL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1629DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_WithL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1630DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_WithL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1631DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_WithL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1632DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_WithL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1633DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_SansL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1634DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_SansL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1635DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_SansL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1636DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_SansL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1637DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_WithL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1638DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_WithL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1639DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_WithL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1640DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_WithL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1641/** @} */
1642
1643/** @} */
1644
1645/** @} */
1646
1647RT_C_DECLS_END
1648
1649#endif /* !VMM_INCLUDED_SRC_include_HMInternal_h */
1650
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