VirtualBox

source: vbox/trunk/src/VBox/VMM/include/HMInternal.h@ 92780

Last change on this file since 92780 was 92359, checked in by vboxsync, 3 years ago

VMM/include: Seperate some things we require both for HM and the NEM/VMX template on darwin into a dedicated header, bugref:10136 [fix]
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File size: 55.3 KB
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1/* $Id: HMInternal.h 92359 2021-11-11 11:06:08Z vboxsync $ */
2/** @file
3 * HM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef VMM_INCLUDED_SRC_include_HMInternal_h
19#define VMM_INCLUDED_SRC_include_HMInternal_h
20#ifndef RT_WITHOUT_PRAGMA_ONCE
21# pragma once
22#endif
23
24#include <VBox/cdefs.h>
25#include <VBox/types.h>
26#include <VBox/vmm/stam.h>
27#include <VBox/dis.h>
28#include <VBox/vmm/hm.h>
29#include <VBox/vmm/hm_vmx.h>
30#include <VBox/vmm/hm_svm.h>
31#include <VBox/vmm/pgm.h>
32#include <VBox/vmm/cpum.h>
33#include <VBox/vmm/trpm.h>
34#include <iprt/memobj.h>
35#include <iprt/cpuset.h>
36#include <iprt/mp.h>
37#include <iprt/avl.h>
38#include <iprt/string.h>
39
40#include "HMVMXCommon.h"
41
42#if HC_ARCH_BITS == 32
43# error "32-bit hosts are no longer supported. Go back to 6.0 or earlier!"
44#endif
45
46/** @def HM_PROFILE_EXIT_DISPATCH
47 * Enables profiling of the VM exit handler dispatching. */
48#if 0 || defined(DOXYGEN_RUNNING)
49# define HM_PROFILE_EXIT_DISPATCH
50#endif
51
52RT_C_DECLS_BEGIN
53
54
55/** @defgroup grp_hm_int Internal
56 * @ingroup grp_hm
57 * @internal
58 * @{
59 */
60
61/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
62#define HM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
63/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
64#define HM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2 * PAGE_SIZE + 1)
65/** Total guest mapped memory needed. */
66#define HM_VTX_TOTAL_DEVHEAP_MEM (HM_EPT_IDENTITY_PG_TABLE_SIZE + HM_VTX_TSS_SIZE)
67
68
69/** @name Macros for enabling and disabling preemption.
70 * These are really just for hiding the RTTHREADPREEMPTSTATE and asserting that
71 * preemption has already been disabled when there is no context hook.
72 * @{ */
73#ifdef VBOX_STRICT
74# define HM_DISABLE_PREEMPT(a_pVCpu) \
75 RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
76 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD) || VMMR0ThreadCtxHookIsEnabled((a_pVCpu))); \
77 RTThreadPreemptDisable(&PreemptStateInternal)
78#else
79# define HM_DISABLE_PREEMPT(a_pVCpu) \
80 RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
81 RTThreadPreemptDisable(&PreemptStateInternal)
82#endif /* VBOX_STRICT */
83#define HM_RESTORE_PREEMPT() do { RTThreadPreemptRestore(&PreemptStateInternal); } while(0)
84/** @} */
85
86
87/** @name HM saved state versions.
88 * @{
89 */
90#define HM_SAVED_STATE_VERSION HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT
91#define HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT 6
92#define HM_SAVED_STATE_VERSION_TPR_PATCHING 5
93#define HM_SAVED_STATE_VERSION_NO_TPR_PATCHING 4
94#define HM_SAVED_STATE_VERSION_2_0_X 3
95/** @} */
96
97
98/**
99 * HM physical (host) CPU information.
100 */
101typedef struct HMPHYSCPU
102{
103 /** The CPU ID. */
104 RTCPUID idCpu;
105 /** The VM_HSAVE_AREA (AMD-V) / VMXON region (Intel) memory backing. */
106 RTR0MEMOBJ hMemObj;
107 /** The physical address of the first page in hMemObj (it's a
108 * physcially contigous allocation if it spans multiple pages). */
109 RTHCPHYS HCPhysMemObj;
110 /** The address of the memory (for pfnEnable). */
111 void *pvMemObj;
112 /** Current ASID (AMD-V) / VPID (Intel). */
113 uint32_t uCurrentAsid;
114 /** TLB flush count. */
115 uint32_t cTlbFlushes;
116 /** Whether to flush each new ASID/VPID before use. */
117 bool fFlushAsidBeforeUse;
118 /** Configured for VT-x or AMD-V. */
119 bool fConfigured;
120 /** Set if the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active. */
121 bool fIgnoreAMDVInUseError;
122 /** Whether CR4.VMXE was already enabled prior to us enabling it. */
123 bool fVmxeAlreadyEnabled;
124 /** In use by our code. (for power suspend) */
125 bool volatile fInUse;
126#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
127 /** Nested-guest union (put data common to SVM/VMX outside the union). */
128 union
129 {
130 /** Nested-guest SVM data. */
131 struct
132 {
133 /** The active nested-guest MSR permission bitmap memory backing. */
134 RTR0MEMOBJ hNstGstMsrpm;
135 /** The physical address of the first page in hNstGstMsrpm (physcially
136 * contiguous allocation). */
137 RTHCPHYS HCPhysNstGstMsrpm;
138 /** The address of the active nested-guest MSRPM. */
139 void *pvNstGstMsrpm;
140 } svm;
141 /** @todo Nested-VMX. */
142 } n;
143#endif
144} HMPHYSCPU;
145/** Pointer to HMPHYSCPU struct. */
146typedef HMPHYSCPU *PHMPHYSCPU;
147/** Pointer to a const HMPHYSCPU struct. */
148typedef const HMPHYSCPU *PCHMPHYSCPU;
149
150/**
151 * TPR-instruction type.
152 */
153typedef enum
154{
155 HMTPRINSTR_INVALID,
156 HMTPRINSTR_READ,
157 HMTPRINSTR_READ_SHR4,
158 HMTPRINSTR_WRITE_REG,
159 HMTPRINSTR_WRITE_IMM,
160 HMTPRINSTR_JUMP_REPLACEMENT,
161 /** The usual 32-bit paranoia. */
162 HMTPRINSTR_32BIT_HACK = 0x7fffffff
163} HMTPRINSTR;
164
165/**
166 * TPR patch information.
167 */
168typedef struct
169{
170 /** The key is the address of patched instruction. (32 bits GC ptr) */
171 AVLOU32NODECORE Core;
172 /** Original opcode. */
173 uint8_t aOpcode[16];
174 /** Instruction size. */
175 uint32_t cbOp;
176 /** Replacement opcode. */
177 uint8_t aNewOpcode[16];
178 /** Replacement instruction size. */
179 uint32_t cbNewOp;
180 /** Instruction type. */
181 HMTPRINSTR enmType;
182 /** Source operand. */
183 uint32_t uSrcOperand;
184 /** Destination operand. */
185 uint32_t uDstOperand;
186 /** Number of times the instruction caused a fault. */
187 uint32_t cFaults;
188 /** Patch address of the jump replacement. */
189 RTGCPTR32 pJumpTarget;
190} HMTPRPATCH;
191/** Pointer to HMTPRPATCH. */
192typedef HMTPRPATCH *PHMTPRPATCH;
193/** Pointer to a const HMTPRPATCH. */
194typedef const HMTPRPATCH *PCHMTPRPATCH;
195
196
197/**
198 * Makes a HMEXITSTAT::uKey value from a program counter and an exit code.
199 *
200 * @returns 64-bit key
201 * @param a_uPC The RIP + CS.BASE value of the exit.
202 * @param a_uExit The exit code.
203 * @todo Add CPL?
204 */
205#define HMEXITSTAT_MAKE_KEY(a_uPC, a_uExit) (((a_uPC) & UINT64_C(0x0000ffffffffffff)) | (uint64_t)(a_uExit) << 48)
206
207typedef struct HMEXITINFO
208{
209 /** See HMEXITSTAT_MAKE_KEY(). */
210 uint64_t uKey;
211 /** Number of recent hits (depreciates with time). */
212 uint32_t volatile cHits;
213 /** The age + lock. */
214 uint16_t volatile uAge;
215 /** Action or action table index. */
216 uint16_t iAction;
217} HMEXITINFO;
218AssertCompileSize(HMEXITINFO, 16); /* Lots of these guys, so don't add any unnecessary stuff! */
219
220typedef struct HMEXITHISTORY
221{
222 /** The exit timestamp. */
223 uint64_t uTscExit;
224 /** The index of the corresponding HMEXITINFO entry.
225 * UINT32_MAX if none (too many collisions, race, whatever). */
226 uint32_t iExitInfo;
227 /** Figure out later, needed for padding now. */
228 uint32_t uSomeClueOrSomething;
229} HMEXITHISTORY;
230
231/**
232 * Switcher function, HC to the special 64-bit RC.
233 *
234 * @param pVM The cross context VM structure.
235 * @param offCpumVCpu Offset from pVM->cpum to pVM->aCpus[idCpu].cpum.
236 * @returns Return code indicating the action to take.
237 */
238typedef DECLCALLBACKTYPE(int, FNHMSWITCHERHC,(PVM pVM, uint32_t offCpumVCpu));
239/** Pointer to switcher function. */
240typedef FNHMSWITCHERHC *PFNHMSWITCHERHC;
241
242
243/**
244 * HM VM Instance data.
245 * Changes to this must checked against the padding of the hm union in VM!
246 */
247typedef struct HM
248{
249 /** Set when the debug facility has breakpoints/events enabled that requires
250 * us to use the debug execution loop in ring-0. */
251 bool fUseDebugLoop;
252 /** Set when TPR patching is allowed. */
253 bool fTprPatchingAllowed;
254 /** Set when TPR patching is active. */
255 bool fTprPatchingActive;
256 /** Alignment padding. */
257 bool afAlignment1[5];
258
259 struct
260 {
261 /** Set by the ring-0 side of HM to indicate VMX is supported by the CPU. */
262 bool fSupported;
263 /** Set when we've enabled VMX. */
264 bool fEnabled;
265 /** The shift mask employed by the VMX-Preemption timer (set by ring-0). */
266 uint8_t cPreemptTimerShift;
267 bool fAlignment1;
268
269 /** @name Configuration (gets copied if problematic)
270 * @{ */
271 /** Set if Last Branch Record (LBR) is enabled. */
272 bool fLbrCfg;
273 /** Set if VT-x VPID is allowed. */
274 bool fAllowVpid;
275 /** Set if unrestricted guest execution is in use (real and protected mode
276 * without paging). */
277 bool fUnrestrictedGuestCfg;
278 /** Set if the preemption timer should be used if available. Ring-0
279 * quietly clears this if the hardware doesn't support the preemption timer. */
280 bool fUsePreemptTimerCfg;
281 /** @} */
282
283 /** Pause-loop exiting (PLE) gap in ticks. */
284 uint32_t cPleGapTicks;
285 /** Pause-loop exiting (PLE) window in ticks. */
286 uint32_t cPleWindowTicks;
287
288 /** Virtual address of the TSS page used for real mode emulation. */
289 R3PTRTYPE(PVBOXTSS) pRealModeTSS;
290 /** Virtual address of the identity page table used for real mode and protected
291 * mode without paging emulation in EPT mode. */
292 R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
293 } vmx;
294
295 struct
296 {
297 /** Set by the ring-0 side of HM to indicate SVM is supported by the CPU. */
298 bool fSupported;
299 /** Set when we've enabled SVM. */
300 bool fEnabled;
301 /** Set when the hack to ignore VERR_SVM_IN_USE is active.
302 * @todo Safe? */
303 bool fIgnoreInUseError;
304 /** Whether to use virtualized VMSAVE/VMLOAD feature. */
305 bool fVirtVmsaveVmload;
306 /** Whether to use virtual GIF feature. */
307 bool fVGif;
308 /** Whether to use LBR virtualization feature. */
309 bool fLbrVirt;
310 bool afAlignment1[2];
311
312 /** Pause filter counter. */
313 uint16_t cPauseFilter;
314 /** Pause filter treshold in ticks. */
315 uint16_t cPauseFilterThresholdTicks;
316 uint32_t u32Alignment2;
317 } svm;
318
319 /** AVL tree with all patches (active or disabled) sorted by guest instruction address.
320 * @todo For @bugref{9217} this AVL tree must be eliminated and instead
321 * sort aPatches by address and do a safe binary search on it. */
322 AVLOU32TREE PatchTree;
323 uint32_t cPatches;
324 HMTPRPATCH aPatches[64];
325
326 /** Guest allocated memory for patching purposes. */
327 RTGCPTR pGuestPatchMem;
328 /** Current free pointer inside the patch block. */
329 RTGCPTR pFreeGuestPatchMem;
330 /** Size of the guest patch memory block. */
331 uint32_t cbGuestPatchMem;
332 uint32_t u32Alignment2;
333
334 /** For ring-3 use only. */
335 struct
336 {
337 /** Last recorded error code during HM ring-0 init. */
338 int32_t rcInit;
339 uint32_t u32Alignment3;
340
341 /** Maximum ASID allowed.
342 * This is mainly for the release log. */
343 uint32_t uMaxAsid;
344 /** World switcher flags (HM_WSF_XXX) for the release log. */
345 uint32_t fWorldSwitcher;
346
347 struct
348 {
349 /** Set if VPID is supported (ring-3 copy). */
350 bool fVpid;
351 /** Whether the CPU supports VMCS fields for swapping EFER (set by ring-0 VMX
352 * init, for logging). */
353 bool fSupportsVmcsEfer;
354 /** Whether to use VMCS shadowing. */
355 bool fUseVmcsShadowing;
356 bool fAlignment2;
357
358 /** Host CR4 value (set by ring-0 VMX init, for logging). */
359 uint64_t u64HostCr4;
360 /** Host SMM monitor control (set by ring-0 VMX init, for logging). */
361 uint64_t u64HostSmmMonitorCtl;
362 /** Host EFER value (set by ring-0 VMX init, for logging and guest NX). */
363 uint64_t u64HostMsrEfer;
364 /** Host IA32_FEATURE_CONTROL MSR (set by ring-0 VMX init, for logging). */
365 uint64_t u64HostFeatCtrl;
366
367 /** The first valid host LBR branch-from-IP stack range. */
368 uint32_t idLbrFromIpMsrFirst;
369 /** The last valid host LBR branch-from-IP stack range. */
370 uint32_t idLbrFromIpMsrLast;
371
372 /** The first valid host LBR branch-to-IP stack range. */
373 uint32_t idLbrToIpMsrFirst;
374 /** The last valid host LBR branch-to-IP stack range. */
375 uint32_t idLbrToIpMsrLast;
376
377 /** Host-physical address for a failing VMXON instruction (for diagnostics, ring-3). */
378 RTHCPHYS HCPhysVmxEnableError;
379 /** VMX MSR values (only for ring-3 consumption). */
380 VMXMSRS Msrs;
381
382 /** Tagged-TLB flush type (only for ring-3 consumption). */
383 VMXTLBFLUSHTYPE enmTlbFlushType;
384 /** Flush type to use for INVEPT (only for ring-3 consumption). */
385 VMXTLBFLUSHEPT enmTlbFlushEpt;
386 /** Flush type to use for INVVPID (only for ring-3 consumption). */
387 VMXTLBFLUSHVPID enmTlbFlushVpid;
388 } vmx;
389
390 struct
391 {
392 /** SVM revision. */
393 uint32_t u32Rev;
394 /** SVM feature bits from cpuid 0x8000000a, ring-3 copy. */
395 uint32_t fFeatures;
396 /** HWCR MSR (for diagnostics). */
397 uint64_t u64MsrHwcr;
398 } svm;
399 } ForR3;
400
401 /** @name Configuration not used (much) after VM setup
402 * @{ */
403 /** The maximum number of resumes loops allowed in ring-0 (safety precaution).
404 * This number is set much higher when RTThreadPreemptIsPending is reliable. */
405 uint32_t cMaxResumeLoopsCfg;
406 /** Set if nested paging is enabled.
407 * Config value that is copied to HMR0PERVM::fNestedPaging on setup. */
408 bool fNestedPagingCfg;
409 /** Set if large pages are enabled (requires nested paging).
410 * Config only, passed on the PGM where it really belongs.
411 * @todo move to PGM */
412 bool fLargePages;
413 /** Set if we can support 64-bit guests or not.
414 * Config value that is copied to HMR0PERVM::fAllow64BitGuests on setup. */
415 bool fAllow64BitGuestsCfg;
416 /** Set when we initialize VT-x or AMD-V once for all CPUs. */
417 bool fGlobalInit;
418 /** Set if hardware APIC virtualization is enabled.
419 * @todo Not really used by HM, move to APIC where it's actually used. */
420 bool fVirtApicRegs;
421 /** Set if posted interrupt processing is enabled.
422 * @todo Not really used by HM, move to APIC where it's actually used. */
423 bool fPostedIntrs;
424 /** @} */
425
426 /** @name Processed into HMR0PERVCPU::fWorldSwitcher by ring-0 on VM init.
427 * @{ */
428 /** Set if indirect branch prediction barrier on VM exit. */
429 bool fIbpbOnVmExit;
430 /** Set if indirect branch prediction barrier on VM entry. */
431 bool fIbpbOnVmEntry;
432 /** Set if level 1 data cache should be flushed on VM entry. */
433 bool fL1dFlushOnVmEntry;
434 /** Set if level 1 data cache should be flushed on EMT scheduling. */
435 bool fL1dFlushOnSched;
436 /** Set if MDS related buffers should be cleared on VM entry. */
437 bool fMdsClearOnVmEntry;
438 /** Set if MDS related buffers should be cleared on EMT scheduling. */
439 bool fMdsClearOnSched;
440 /** Set if host manages speculation control settings.
441 * @todo doesn't do anything ... */
442 bool fSpecCtrlByHost;
443 /** @} */
444
445 /** Set when we've finalized the VMX / SVM initialization in ring-3
446 * (hmR3InitFinalizeR0Intel / hmR3InitFinalizeR0Amd). */
447 bool fInitialized;
448
449 bool afAlignment2[6];
450
451 STAMCOUNTER StatTprPatchSuccess;
452 STAMCOUNTER StatTprPatchFailure;
453 STAMCOUNTER StatTprReplaceSuccessCr8;
454 STAMCOUNTER StatTprReplaceSuccessVmc;
455 STAMCOUNTER StatTprReplaceFailure;
456} HM;
457/** Pointer to HM VM instance data. */
458typedef HM *PHM;
459AssertCompileMemberAlignment(HM, StatTprPatchSuccess, 8);
460AssertCompileMemberAlignment(HM, vmx, 8);
461AssertCompileMemberAlignment(HM, svm, 8);
462AssertCompileMemberAlignment(HM, StatTprPatchSuccess, 8);
463AssertCompile(RTASSERT_OFFSET_OF(HM, PatchTree) <= 64); /* First cache line has the essentials for both VT-x and SVM operation. */
464
465
466/**
467 * Per-VM ring-0 instance data for HM.
468 */
469typedef struct HMR0PERVM
470{
471 /** The maximum number of resumes loops allowed in ring-0 (safety precaution).
472 * This number is set much higher when RTThreadPreemptIsPending is reliable. */
473 uint32_t cMaxResumeLoops;
474
475 /** Set if nested paging is enabled. */
476 bool fNestedPaging;
477 /** Set if we can support 64-bit guests or not. */
478 bool fAllow64BitGuests;
479 bool afAlignment1[1];
480
481 /** AMD-V specific data. */
482 struct HMR0SVMVM
483 {
484 /** Set if erratum 170 affects the AMD cpu. */
485 bool fAlwaysFlushTLB;
486 } svm;
487
488 /** VT-x specific data. */
489 struct HMR0VMXVM
490 {
491 /** Set if unrestricted guest execution is in use (real and protected mode
492 * without paging). */
493 bool fUnrestrictedGuest;
494 /** Set if the preemption timer is in use. */
495 bool fUsePreemptTimer;
496 /** Whether to use VMCS shadowing. */
497 bool fUseVmcsShadowing;
498 /** Set if Last Branch Record (LBR) is enabled. */
499 bool fLbr;
500 bool afAlignment2[3];
501
502 /** Set if VPID is supported (copy in HM::vmx::fVpidForRing3). */
503 bool fVpid;
504 /** Tagged-TLB flush type. */
505 VMXTLBFLUSHTYPE enmTlbFlushType;
506 /** Flush type to use for INVEPT. */
507 VMXTLBFLUSHEPT enmTlbFlushEpt;
508 /** Flush type to use for INVVPID. */
509 VMXTLBFLUSHVPID enmTlbFlushVpid;
510
511 /** The host LBR TOS (top-of-stack) MSR id. */
512 uint32_t idLbrTosMsr;
513
514 /** The first valid host LBR branch-from-IP stack range. */
515 uint32_t idLbrFromIpMsrFirst;
516 /** The last valid host LBR branch-from-IP stack range. */
517 uint32_t idLbrFromIpMsrLast;
518
519 /** The first valid host LBR branch-to-IP stack range. */
520 uint32_t idLbrToIpMsrFirst;
521 /** The last valid host LBR branch-to-IP stack range. */
522 uint32_t idLbrToIpMsrLast;
523
524 /** Pointer to the VMREAD bitmap. */
525 R0PTRTYPE(void *) pvVmreadBitmap;
526 /** Pointer to the VMWRITE bitmap. */
527 R0PTRTYPE(void *) pvVmwriteBitmap;
528
529 /** Pointer to the shadow VMCS read-only fields array. */
530 R0PTRTYPE(uint32_t *) paShadowVmcsRoFields;
531 /** Pointer to the shadow VMCS read/write fields array. */
532 R0PTRTYPE(uint32_t *) paShadowVmcsFields;
533 /** Number of elements in the shadow VMCS read-only fields array. */
534 uint32_t cShadowVmcsRoFields;
535 /** Number of elements in the shadow VMCS read-write fields array. */
536 uint32_t cShadowVmcsFields;
537
538 /** Host-physical address of the APIC-access page. */
539 RTHCPHYS HCPhysApicAccess;
540 /** Host-physical address of the VMREAD bitmap. */
541 RTHCPHYS HCPhysVmreadBitmap;
542 /** Host-physical address of the VMWRITE bitmap. */
543 RTHCPHYS HCPhysVmwriteBitmap;
544
545#ifdef VBOX_WITH_CRASHDUMP_MAGIC
546 /** Host-physical address of the crash-dump scratch area. */
547 RTHCPHYS HCPhysScratch;
548 /** Pointer to the crash-dump scratch bitmap. */
549 R0PTRTYPE(uint8_t *) pbScratch;
550#endif
551
552 /** Ring-0 memory object for per-VM VMX structures. */
553 RTR0MEMOBJ hMemObj;
554 /** Virtual address of the APIC-access page (not used). */
555 R0PTRTYPE(uint8_t *) pbApicAccess;
556 } vmx;
557} HMR0PERVM;
558/** Pointer to HM's per-VM ring-0 instance data. */
559typedef HMR0PERVM *PHMR0PERVM;
560
561
562/** @addtogroup grp_hm_int_svm SVM Internal
563 * @{ */
564/** SVM VMRun function, see SVMR0VMRun(). */
565typedef DECLCALLBACKTYPE(int, FNHMSVMVMRUN,(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhysVMCB));
566/** Pointer to a SVM VMRun function. */
567typedef R0PTRTYPE(FNHMSVMVMRUN *) PFNHMSVMVMRUN;
568
569/**
570 * SVM nested-guest VMCB cache.
571 *
572 * Contains VMCB fields from the nested-guest VMCB before they're modified by
573 * SVM R0 code for hardware-assisted SVM execution of a nested-guest.
574 *
575 * A VMCB field needs to be cached when it needs to be modified for execution using
576 * hardware-assisted SVM and any of the following are true:
577 * - If the original field needs to be inspected during execution of the
578 * nested-guest or \#VMEXIT processing.
579 * - If the field is written back to memory on \#VMEXIT by the physical CPU.
580 *
581 * A VMCB field needs to be restored only when the field is written back to
582 * memory on \#VMEXIT by the physical CPU and thus would be visible to the
583 * guest.
584 *
585 * @remarks Please update hmR3InfoSvmNstGstVmcbCache() when changes are made to
586 * this structure.
587 */
588typedef struct SVMNESTEDVMCBCACHE
589{
590 /** Cache of CRX read intercepts. */
591 uint16_t u16InterceptRdCRx;
592 /** Cache of CRX write intercepts. */
593 uint16_t u16InterceptWrCRx;
594 /** Cache of DRX read intercepts. */
595 uint16_t u16InterceptRdDRx;
596 /** Cache of DRX write intercepts. */
597 uint16_t u16InterceptWrDRx;
598
599 /** Cache of the pause-filter threshold. */
600 uint16_t u16PauseFilterThreshold;
601 /** Cache of the pause-filter count. */
602 uint16_t u16PauseFilterCount;
603
604 /** Cache of exception intercepts. */
605 uint32_t u32InterceptXcpt;
606 /** Cache of control intercepts. */
607 uint64_t u64InterceptCtrl;
608
609 /** Cache of the TSC offset. */
610 uint64_t u64TSCOffset;
611
612 /** Cache of V_INTR_MASKING bit. */
613 bool fVIntrMasking;
614 /** Cache of the nested-paging bit. */
615 bool fNestedPaging;
616 /** Cache of the LBR virtualization bit. */
617 bool fLbrVirt;
618 /** Whether the VMCB is cached by HM. */
619 bool fCacheValid;
620 /** Alignment. */
621 bool afPadding0[4];
622} SVMNESTEDVMCBCACHE;
623/** Pointer to the SVMNESTEDVMCBCACHE structure. */
624typedef SVMNESTEDVMCBCACHE *PSVMNESTEDVMCBCACHE;
625/** Pointer to a const SVMNESTEDVMCBCACHE structure. */
626typedef const SVMNESTEDVMCBCACHE *PCSVMNESTEDVMCBCACHE;
627AssertCompileSizeAlignment(SVMNESTEDVMCBCACHE, 8);
628
629/** @} */
630
631/** @name Host-state restoration flags.
632 * @note If you change these values don't forget to update the assembly
633 * defines as well!
634 * @{
635 */
636#define VMX_RESTORE_HOST_SEL_DS RT_BIT(0)
637#define VMX_RESTORE_HOST_SEL_ES RT_BIT(1)
638#define VMX_RESTORE_HOST_SEL_FS RT_BIT(2)
639#define VMX_RESTORE_HOST_SEL_GS RT_BIT(3)
640#define VMX_RESTORE_HOST_SEL_TR RT_BIT(4)
641#define VMX_RESTORE_HOST_GDTR RT_BIT(5)
642#define VMX_RESTORE_HOST_IDTR RT_BIT(6)
643#define VMX_RESTORE_HOST_GDT_READ_ONLY RT_BIT(7)
644#define VMX_RESTORE_HOST_GDT_NEED_WRITABLE RT_BIT(8)
645#define VMX_RESTORE_HOST_CAN_USE_WRFSBASE_AND_WRGSBASE RT_BIT(9)
646/**
647 * This _must_ be the top most bit, so that we can easily check that it and
648 * something else is set w/o having to do two checks like this:
649 * @code
650 * if ( (pVCpu->hm.s.vmx.fRestoreHostFlags & VMX_RESTORE_HOST_REQUIRED)
651 * && (pVCpu->hm.s.vmx.fRestoreHostFlags & ~VMX_RESTORE_HOST_REQUIRED))
652 * @endcode
653 * Instead we can then do:
654 * @code
655 * if (pVCpu->hm.s.vmx.fRestoreHostFlags > VMX_RESTORE_HOST_REQUIRED)
656 * @endcode
657 */
658#define VMX_RESTORE_HOST_REQUIRED RT_BIT(10)
659/** @} */
660
661/**
662 * Host-state restoration structure.
663 *
664 * This holds host-state fields that require manual restoration.
665 * Assembly version found in HMInternal.mac (should be automatically verified).
666 */
667typedef struct VMXRESTOREHOST
668{
669 RTSEL uHostSelDS; /**< 0x00 */
670 RTSEL uHostSelES; /**< 0x02 */
671 RTSEL uHostSelFS; /**< 0x04 */
672 X86XDTR64 HostGdtr; /**< 0x06 - should be aligned by its 64-bit member. */
673 RTSEL uHostSelGS; /**< 0x10 */
674 RTSEL uHostSelTR; /**< 0x12 */
675 RTSEL uHostSelSS; /**< 0x14 - not restored, just for fetching */
676 X86XDTR64 HostGdtrRw; /**< 0x16 - should be aligned by its 64-bit member. */
677 RTSEL uHostSelCS; /**< 0x20 - not restored, just for fetching */
678 uint8_t abPadding1[4]; /**< 0x22 */
679 X86XDTR64 HostIdtr; /**< 0x26 - should be aligned by its 64-bit member. */
680 uint64_t uHostFSBase; /**< 0x30 */
681 uint64_t uHostGSBase; /**< 0x38 */
682} VMXRESTOREHOST;
683/** Pointer to VMXRESTOREHOST. */
684typedef VMXRESTOREHOST *PVMXRESTOREHOST;
685AssertCompileSize(X86XDTR64, 10);
686AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtr.uAddr, 0x08);
687AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtrRw.uAddr, 0x18);
688AssertCompileMemberOffset(VMXRESTOREHOST, HostIdtr.uAddr, 0x28);
689AssertCompileMemberOffset(VMXRESTOREHOST, uHostFSBase, 0x30);
690AssertCompileSize(VMXRESTOREHOST, 64);
691AssertCompileSizeAlignment(VMXRESTOREHOST, 8);
692
693/**
694 * VMX StartVM function.
695 *
696 * @returns VBox status code (no informational stuff).
697 * @param pVmcsInfo Pointer to the VMCS info (for cached host RIP and RSP).
698 * @param pVCpu Pointer to the cross context per-CPU structure.
699 * @param fResume Whether to use VMRESUME (true) or VMLAUNCH (false).
700 */
701typedef DECLCALLBACKTYPE(int, FNHMVMXSTARTVM,(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume));
702/** Pointer to a VMX StartVM function. */
703typedef R0PTRTYPE(FNHMVMXSTARTVM *) PFNHMVMXSTARTVM;
704/** @} */
705
706/**
707 * HM VMCPU Instance data.
708 *
709 * Note! If you change members of this struct, make sure to check if the
710 * assembly counterpart in HMInternal.mac needs to be updated as well.
711 *
712 * Note! The members here are ordered and aligned based on estimated frequency of
713 * usage and grouped to fit within a cache line in hot code paths. Even subtle
714 * changes here have a noticeable effect in the bootsector benchmarks. Modify with
715 * care.
716 */
717typedef struct HMCPU
718{
719 /** Set when the TLB has been checked until we return from the world switch. */
720 bool volatile fCheckedTLBFlush;
721 /** Set when we're using VT-x or AMD-V at that moment.
722 * @todo r=bird: Misleading description. For AMD-V this will be set the first
723 * time HMCanExecuteGuest() is called and only cleared again by
724 * HMR3ResetCpu(). For VT-x it will be set by HMCanExecuteGuest when we
725 * can execute something in VT-x mode, and cleared if we cannot.
726 *
727 * The field is much more about recording the last HMCanExecuteGuest
728 * return value than anything about any "moment". */
729 bool fActive;
730
731 /** Whether we should use the debug loop because of single stepping or special
732 * debug breakpoints / events are armed. */
733 bool fUseDebugLoop;
734
735 /** Whether \#UD needs to be intercepted (required by certain GIM providers). */
736 bool fGIMTrapXcptUD;
737 /** Whether \#GP needs to be intercepted for mesa driver workaround. */
738 bool fTrapXcptGpForLovelyMesaDrv;
739 /** Whether we're executing a single instruction. */
740 bool fSingleInstruction;
741
742 bool afAlignment0[2];
743
744 /** An additional error code used for some gurus. */
745 uint32_t u32HMError;
746 /** The last exit-to-ring-3 reason. */
747 int32_t rcLastExitToR3;
748 /** CPU-context changed flags (see HM_CHANGED_xxx). */
749 uint64_t fCtxChanged;
750
751 /** VT-x data. */
752 struct HMCPUVMX
753 {
754 /** @name Guest information.
755 * @{ */
756 /** Guest VMCS information shared with ring-3. */
757 VMXVMCSINFOSHARED VmcsInfo;
758 /** Nested-guest VMCS information shared with ring-3. */
759 VMXVMCSINFOSHARED VmcsInfoNstGst;
760 /** Whether the nested-guest VMCS was the last current VMCS (shadow copy for ring-3).
761 * @see HMR0PERVCPU::vmx.fSwitchedToNstGstVmcs */
762 bool fSwitchedToNstGstVmcsCopyForRing3;
763 /** Whether the static guest VMCS controls has been merged with the
764 * nested-guest VMCS controls. */
765 bool fMergedNstGstCtls;
766 /** Whether the nested-guest VMCS has been copied to the shadow VMCS. */
767 bool fCopiedNstGstToShadowVmcs;
768 /** Whether flushing the TLB is required due to switching to/from the
769 * nested-guest. */
770 bool fSwitchedNstGstFlushTlb;
771 /** Alignment. */
772 bool afAlignment0[4];
773 /** Cached guest APIC-base MSR for identifying when to map the APIC-access page. */
774 uint64_t u64GstMsrApicBase;
775 /** @} */
776
777 /** @name Error reporting and diagnostics.
778 * @{ */
779 /** VT-x error-reporting (mainly for ring-3 propagation). */
780 struct
781 {
782 RTCPUID idCurrentCpu;
783 RTCPUID idEnteredCpu;
784 RTHCPHYS HCPhysCurrentVmcs;
785 uint32_t u32VmcsRev;
786 uint32_t u32InstrError;
787 uint32_t u32ExitReason;
788 uint32_t u32GuestIntrState;
789 } LastError;
790 /** @} */
791 } vmx;
792
793 /** SVM data. */
794 struct HMCPUSVM
795 {
796 /** Whether to emulate long mode support for sysenter/sysexit like intel CPUs
797 * does. This means intercepting \#UD to emulate the instructions in
798 * long-mode and to intercept reads and writes to the SYSENTER MSRs in order to
799 * preserve the upper 32 bits written to them (AMD will ignore and discard). */
800 bool fEmulateLongModeSysEnterExit;
801 uint8_t au8Alignment0[7];
802
803 /** Cache of the nested-guest's VMCB fields that we modify in order to run the
804 * nested-guest using AMD-V. This will be restored on \#VMEXIT. */
805 SVMNESTEDVMCBCACHE NstGstVmcbCache;
806 } svm;
807
808 /** Event injection state. */
809 HMEVENT Event;
810
811 /** Current shadow paging mode for updating CR4.
812 * @todo move later (@bugref{9217}). */
813 PGMMODE enmShadowMode;
814 uint32_t u32TemporaryPadding;
815
816 /** The PAE PDPEs used with Nested Paging (only valid when
817 * VMCPU_FF_HM_UPDATE_PAE_PDPES is set). */
818 X86PDPE aPdpes[4];
819
820 /* These two comes because they are accessed from assembly and we don't
821 want to detail all the stats in the assembly version of this structure. */
822 STAMCOUNTER StatVmxWriteHostRip;
823 STAMCOUNTER StatVmxWriteHostRsp;
824 STAMCOUNTER StatVmxVmLaunch;
825 STAMCOUNTER StatVmxVmResume;
826
827 STAMPROFILEADV StatEntry;
828 STAMPROFILEADV StatPreExit;
829 STAMPROFILEADV StatExitHandling;
830 STAMPROFILEADV StatExitIO;
831 STAMPROFILEADV StatExitMovCRx;
832 STAMPROFILEADV StatExitXcptNmi;
833 STAMPROFILEADV StatExitVmentry;
834 STAMPROFILEADV StatImportGuestState;
835 STAMPROFILEADV StatExportGuestState;
836 STAMPROFILEADV StatLoadGuestFpuState;
837 STAMPROFILEADV StatInGC;
838 STAMPROFILEADV StatPoke;
839 STAMPROFILEADV StatSpinPoke;
840 STAMPROFILEADV StatSpinPokeFailed;
841
842 STAMCOUNTER StatInjectInterrupt;
843 STAMCOUNTER StatInjectXcpt;
844 STAMCOUNTER StatInjectReflect;
845 STAMCOUNTER StatInjectConvertDF;
846 STAMCOUNTER StatInjectInterpret;
847 STAMCOUNTER StatInjectReflectNPF;
848
849 STAMCOUNTER StatExitAll;
850 STAMCOUNTER StatNestedExitAll;
851 STAMCOUNTER StatExitShadowNM;
852 STAMCOUNTER StatExitGuestNM;
853 STAMCOUNTER StatExitShadowPF; /**< Misleading, currently used for MMIO \#PFs as well. */
854 STAMCOUNTER StatExitShadowPFEM;
855 STAMCOUNTER StatExitGuestPF;
856 STAMCOUNTER StatExitGuestUD;
857 STAMCOUNTER StatExitGuestSS;
858 STAMCOUNTER StatExitGuestNP;
859 STAMCOUNTER StatExitGuestTS;
860 STAMCOUNTER StatExitGuestOF;
861 STAMCOUNTER StatExitGuestGP;
862 STAMCOUNTER StatExitGuestDE;
863 STAMCOUNTER StatExitGuestDF;
864 STAMCOUNTER StatExitGuestBR;
865 STAMCOUNTER StatExitGuestAC;
866 STAMCOUNTER StatExitGuestACSplitLock;
867 STAMCOUNTER StatExitGuestDB;
868 STAMCOUNTER StatExitGuestMF;
869 STAMCOUNTER StatExitGuestBP;
870 STAMCOUNTER StatExitGuestXF;
871 STAMCOUNTER StatExitGuestXcpUnk;
872 STAMCOUNTER StatExitDRxWrite;
873 STAMCOUNTER StatExitDRxRead;
874 STAMCOUNTER StatExitCR0Read;
875 STAMCOUNTER StatExitCR2Read;
876 STAMCOUNTER StatExitCR3Read;
877 STAMCOUNTER StatExitCR4Read;
878 STAMCOUNTER StatExitCR8Read;
879 STAMCOUNTER StatExitCR0Write;
880 STAMCOUNTER StatExitCR2Write;
881 STAMCOUNTER StatExitCR3Write;
882 STAMCOUNTER StatExitCR4Write;
883 STAMCOUNTER StatExitCR8Write;
884 STAMCOUNTER StatExitRdmsr;
885 STAMCOUNTER StatExitWrmsr;
886 STAMCOUNTER StatExitClts;
887 STAMCOUNTER StatExitXdtrAccess;
888 STAMCOUNTER StatExitLmsw;
889 STAMCOUNTER StatExitIOWrite;
890 STAMCOUNTER StatExitIORead;
891 STAMCOUNTER StatExitIOStringWrite;
892 STAMCOUNTER StatExitIOStringRead;
893 STAMCOUNTER StatExitIntWindow;
894 STAMCOUNTER StatExitExtInt;
895 STAMCOUNTER StatExitHostNmiInGC;
896 STAMCOUNTER StatExitHostNmiInGCIpi;
897 STAMCOUNTER StatExitPreemptTimer;
898 STAMCOUNTER StatExitTprBelowThreshold;
899 STAMCOUNTER StatExitTaskSwitch;
900 STAMCOUNTER StatExitApicAccess;
901 STAMCOUNTER StatExitReasonNpf;
902
903 STAMCOUNTER StatNestedExitReasonNpf;
904
905 STAMCOUNTER StatFlushPage;
906 STAMCOUNTER StatFlushPageManual;
907 STAMCOUNTER StatFlushPhysPageManual;
908 STAMCOUNTER StatFlushTlb;
909 STAMCOUNTER StatFlushTlbNstGst;
910 STAMCOUNTER StatFlushTlbManual;
911 STAMCOUNTER StatFlushTlbWorldSwitch;
912 STAMCOUNTER StatNoFlushTlbWorldSwitch;
913 STAMCOUNTER StatFlushEntire;
914 STAMCOUNTER StatFlushAsid;
915 STAMCOUNTER StatFlushNestedPaging;
916 STAMCOUNTER StatFlushTlbInvlpgVirt;
917 STAMCOUNTER StatFlushTlbInvlpgPhys;
918 STAMCOUNTER StatTlbShootdown;
919 STAMCOUNTER StatTlbShootdownFlush;
920
921 STAMCOUNTER StatSwitchPendingHostIrq;
922 STAMCOUNTER StatSwitchTprMaskedIrq;
923 STAMCOUNTER StatSwitchGuestIrq;
924 STAMCOUNTER StatSwitchHmToR3FF;
925 STAMCOUNTER StatSwitchVmReq;
926 STAMCOUNTER StatSwitchPgmPoolFlush;
927 STAMCOUNTER StatSwitchDma;
928 STAMCOUNTER StatSwitchExitToR3;
929 STAMCOUNTER StatSwitchLongJmpToR3;
930 STAMCOUNTER StatSwitchMaxResumeLoops;
931 STAMCOUNTER StatSwitchHltToR3;
932 STAMCOUNTER StatSwitchApicAccessToR3;
933 STAMCOUNTER StatSwitchPreempt;
934 STAMCOUNTER StatSwitchNstGstVmexit;
935
936 STAMCOUNTER StatTscParavirt;
937 STAMCOUNTER StatTscOffset;
938 STAMCOUNTER StatTscIntercept;
939
940 STAMCOUNTER StatDRxArmed;
941 STAMCOUNTER StatDRxContextSwitch;
942 STAMCOUNTER StatDRxIoCheck;
943
944 STAMCOUNTER StatExportMinimal;
945 STAMCOUNTER StatExportFull;
946 STAMCOUNTER StatLoadGuestFpu;
947 STAMCOUNTER StatExportHostState;
948
949 STAMCOUNTER StatVmxCheckBadRmSelBase;
950 STAMCOUNTER StatVmxCheckBadRmSelLimit;
951 STAMCOUNTER StatVmxCheckBadRmSelAttr;
952 STAMCOUNTER StatVmxCheckBadV86SelBase;
953 STAMCOUNTER StatVmxCheckBadV86SelLimit;
954 STAMCOUNTER StatVmxCheckBadV86SelAttr;
955 STAMCOUNTER StatVmxCheckRmOk;
956 STAMCOUNTER StatVmxCheckBadSel;
957 STAMCOUNTER StatVmxCheckBadRpl;
958 STAMCOUNTER StatVmxCheckPmOk;
959
960 STAMCOUNTER StatVmxPreemptionRecalcingDeadline;
961 STAMCOUNTER StatVmxPreemptionRecalcingDeadlineExpired;
962 STAMCOUNTER StatVmxPreemptionReusingDeadline;
963 STAMCOUNTER StatVmxPreemptionReusingDeadlineExpired;
964
965#ifdef VBOX_WITH_STATISTICS
966 STAMCOUNTER aStatExitReason[MAX_EXITREASON_STAT];
967 STAMCOUNTER aStatNestedExitReason[MAX_EXITREASON_STAT];
968 STAMCOUNTER aStatInjectedIrqs[256];
969 STAMCOUNTER aStatInjectedXcpts[X86_XCPT_LAST + 1];
970#endif
971#ifdef HM_PROFILE_EXIT_DISPATCH
972 STAMPROFILEADV StatExitDispatch;
973#endif
974} HMCPU;
975/** Pointer to HM VMCPU instance data. */
976typedef HMCPU *PHMCPU;
977AssertCompileMemberAlignment(HMCPU, fCheckedTLBFlush, 4);
978AssertCompileMemberAlignment(HMCPU, fCtxChanged, 8);
979AssertCompileMemberAlignment(HMCPU, vmx, 8);
980AssertCompileMemberAlignment(HMCPU, vmx.VmcsInfo, 8);
981AssertCompileMemberAlignment(HMCPU, vmx.VmcsInfoNstGst, 8);
982AssertCompileMemberAlignment(HMCPU, svm, 8);
983AssertCompileMemberAlignment(HMCPU, Event, 8);
984
985
986/**
987 * HM per-VCpu ring-0 only instance data.
988 */
989typedef struct HMR0PERVCPU
990{
991 /** World switch exit counter. */
992 uint32_t volatile cWorldSwitchExits;
993 /** TLB flush count. */
994 uint32_t cTlbFlushes;
995 /** The last CPU we were executing code on (NIL_RTCPUID for the first time). */
996 RTCPUID idLastCpu;
997 /** The CPU ID of the CPU currently owning the VMCS. Set in
998 * HMR0Enter and cleared in HMR0Leave. */
999 RTCPUID idEnteredCpu;
1000 /** Current ASID in use by the VM. */
1001 uint32_t uCurrentAsid;
1002
1003 /** Set if we need to flush the TLB during the world switch. */
1004 bool fForceTLBFlush;
1005 /** Whether we've completed the inner HM leave function. */
1006 bool fLeaveDone;
1007 /** Whether we're using the hyper DR7 or guest DR7. */
1008 bool fUsingHyperDR7;
1009 /** Whether we are currently executing in the debug loop.
1010 * Mainly for assertions. */
1011 bool fUsingDebugLoop;
1012 /** Set if we using the debug loop and wish to intercept RDTSC. */
1013 bool fDebugWantRdTscExit;
1014 /** Set if XCR0 needs to be saved/restored when entering/exiting guest code
1015 * execution. */
1016 bool fLoadSaveGuestXcr0;
1017 /** Set if we need to clear the trap flag because of single stepping. */
1018 bool fClearTrapFlag;
1019
1020 bool afPadding1[1];
1021 /** World switcher flags (HM_WSF_XXX - was CPUMCTX::fWorldSwitcher in 6.1). */
1022 uint32_t fWorldSwitcher;
1023 /** The raw host TSC value from the last VM exit (set by HMR0A.asm). */
1024 uint64_t uTscExit;
1025
1026 /** VT-x data. */
1027 struct HMR0CPUVMX
1028 {
1029 /** Ring-0 pointer to the hardware-assisted VMX execution function. */
1030 PFNHMVMXSTARTVM pfnStartVm;
1031 /** Absolute TSC deadline. */
1032 uint64_t uTscDeadline;
1033 /** The deadline version number. */
1034 uint64_t uTscDeadlineVersion;
1035
1036 /** @name Guest information.
1037 * @{ */
1038 /** Guest VMCS information. */
1039 VMXVMCSINFO VmcsInfo;
1040 /** Nested-guest VMCS information. */
1041 VMXVMCSINFO VmcsInfoNstGst;
1042 /* Whether the nested-guest VMCS was the last current VMCS (authoritative copy).
1043 * @see HMCPU::vmx.fSwitchedToNstGstVmcsCopyForRing3 */
1044 bool fSwitchedToNstGstVmcs;
1045 bool afAlignment0[7];
1046 /** @} */
1047
1048 /** @name Host information.
1049 * @{ */
1050 /** Host LSTAR MSR to restore lazily while leaving VT-x. */
1051 uint64_t u64HostMsrLStar;
1052 /** Host STAR MSR to restore lazily while leaving VT-x. */
1053 uint64_t u64HostMsrStar;
1054 /** Host SF_MASK MSR to restore lazily while leaving VT-x. */
1055 uint64_t u64HostMsrSfMask;
1056 /** Host KernelGS-Base MSR to restore lazily while leaving VT-x. */
1057 uint64_t u64HostMsrKernelGsBase;
1058 /** The mask of lazy MSRs swap/restore state, see VMX_LAZY_MSRS_XXX. */
1059 uint32_t fLazyMsrs;
1060 /** Whether the host MSR values are up-to-date in the auto-load/store MSR area. */
1061 bool fUpdatedHostAutoMsrs;
1062 /** Alignment. */
1063 uint8_t au8Alignment0[3];
1064 /** Which host-state bits to restore before being preempted, see
1065 * VMX_RESTORE_HOST_XXX. */
1066 uint32_t fRestoreHostFlags;
1067 /** Alignment. */
1068 uint32_t u32Alignment0;
1069 /** The host-state restoration structure. */
1070 VMXRESTOREHOST RestoreHost;
1071 /** @} */
1072 } vmx;
1073
1074 /** SVM data. */
1075 struct HMR0CPUSVM
1076 {
1077 /** Ring 0 handlers for VT-x. */
1078 PFNHMSVMVMRUN pfnVMRun;
1079
1080 /** Physical address of the host VMCB which holds additional host-state. */
1081 RTHCPHYS HCPhysVmcbHost;
1082 /** R0 memory object for the host VMCB which holds additional host-state. */
1083 RTR0MEMOBJ hMemObjVmcbHost;
1084
1085 /** Physical address of the guest VMCB. */
1086 RTHCPHYS HCPhysVmcb;
1087 /** R0 memory object for the guest VMCB. */
1088 RTR0MEMOBJ hMemObjVmcb;
1089 /** Pointer to the guest VMCB. */
1090 R0PTRTYPE(PSVMVMCB) pVmcb;
1091
1092 /** Physical address of the MSR bitmap (8 KB). */
1093 RTHCPHYS HCPhysMsrBitmap;
1094 /** R0 memory object for the MSR bitmap (8 KB). */
1095 RTR0MEMOBJ hMemObjMsrBitmap;
1096 /** Pointer to the MSR bitmap. */
1097 R0PTRTYPE(void *) pvMsrBitmap;
1098
1099 /** Whether VTPR with V_INTR_MASKING set is in effect, indicating
1100 * we should check if the VTPR changed on every VM-exit. */
1101 bool fSyncVTpr;
1102 bool afAlignment[7];
1103
1104 /** Host's TSC_AUX MSR (used when RDTSCP doesn't cause VM-exits). */
1105 uint64_t u64HostTscAux;
1106
1107 /** For saving stack space, the disassembler state is allocated here
1108 * instead of on the stack. */
1109 DISCPUSTATE DisState;
1110 } svm;
1111} HMR0PERVCPU;
1112/** Pointer to HM ring-0 VMCPU instance data. */
1113typedef HMR0PERVCPU *PHMR0PERVCPU;
1114AssertCompileMemberAlignment(HMR0PERVCPU, cWorldSwitchExits, 4);
1115AssertCompileMemberAlignment(HMR0PERVCPU, fForceTLBFlush, 4);
1116AssertCompileMemberAlignment(HMR0PERVCPU, vmx.RestoreHost, 8);
1117
1118
1119/** @name HM_WSF_XXX - @bugref{9453}, @bugref{9087}
1120 * @note If you change these values don't forget to update the assembly
1121 * defines as well!
1122 * @{ */
1123/** Touch IA32_PRED_CMD.IBPB on VM exit. */
1124#define HM_WSF_IBPB_EXIT RT_BIT_32(0)
1125/** Touch IA32_PRED_CMD.IBPB on VM entry. */
1126#define HM_WSF_IBPB_ENTRY RT_BIT_32(1)
1127/** Touch IA32_FLUSH_CMD.L1D on VM entry. */
1128#define HM_WSF_L1D_ENTRY RT_BIT_32(2)
1129/** Flush MDS buffers on VM entry. */
1130#define HM_WSF_MDS_ENTRY RT_BIT_32(3)
1131
1132/** Touch IA32_FLUSH_CMD.L1D on VM scheduling. */
1133#define HM_WSF_L1D_SCHED RT_BIT_32(16)
1134/** Flush MDS buffers on VM scheduling. */
1135#define HM_WSF_MDS_SCHED RT_BIT_32(17)
1136/** @} */
1137
1138
1139#ifdef IN_RING0
1140extern bool g_fHmVmxSupported;
1141extern uint32_t g_fHmHostKernelFeatures;
1142extern uint32_t g_uHmMaxAsid;
1143extern bool g_fHmVmxUsePreemptTimer;
1144extern uint8_t g_cHmVmxPreemptTimerShift;
1145extern bool g_fHmVmxSupportsVmcsEfer;
1146extern uint64_t g_uHmVmxHostCr4;
1147extern uint64_t g_uHmVmxHostMsrEfer;
1148extern uint64_t g_uHmVmxHostSmmMonitorCtl;
1149extern bool g_fHmSvmSupported;
1150extern uint32_t g_uHmSvmRev;
1151extern uint32_t g_fHmSvmFeatures;
1152
1153extern SUPHWVIRTMSRS g_HmMsrs;
1154
1155
1156VMMR0_INT_DECL(PHMPHYSCPU) hmR0GetCurrentCpu(void);
1157VMMR0_INT_DECL(int) hmR0EnterCpu(PVMCPUCC pVCpu);
1158
1159# ifdef VBOX_STRICT
1160# define HM_DUMP_REG_FLAGS_GPRS RT_BIT(0)
1161# define HM_DUMP_REG_FLAGS_FPU RT_BIT(1)
1162# define HM_DUMP_REG_FLAGS_MSRS RT_BIT(2)
1163# define HM_DUMP_REG_FLAGS_ALL (HM_DUMP_REG_FLAGS_GPRS | HM_DUMP_REG_FLAGS_FPU | HM_DUMP_REG_FLAGS_MSRS)
1164
1165VMMR0_INT_DECL(void) hmR0DumpRegs(PVMCPUCC pVCpu, uint32_t fFlags);
1166VMMR0_INT_DECL(void) hmR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg);
1167# endif
1168
1169DECLASM(void) hmR0MdsClear(void);
1170#endif /* IN_RING0 */
1171
1172
1173/** @addtogroup grp_hm_int_svm SVM Internal
1174 * @{ */
1175VMM_INT_DECL(int) hmEmulateSvmMovTpr(PVMCC pVM, PVMCPUCC pVCpu);
1176
1177/**
1178 * Prepares for and executes VMRUN (64-bit register context).
1179 *
1180 * @returns VBox status code (no informational stuff).
1181 * @param pVM The cross context VM structure. (Not used.)
1182 * @param pVCpu The cross context virtual CPU structure.
1183 * @param HCPhyspVMCB Physical address of the VMCB.
1184 *
1185 * @remarks With spectre mitigations and the usual need for speed (/ micro
1186 * optimizations), we have a bunch of variations of this code depending
1187 * on a few precoditions. In release builds, the code is entirely
1188 * without conditionals. Debug builds have a couple of assertions that
1189 * shouldn't ever be triggered.
1190 *
1191 * @{
1192 */
1193DECLASM(int) hmR0SvmVmRun_SansXcr0_SansIbpbEntry_SansIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1194DECLASM(int) hmR0SvmVmRun_WithXcr0_SansIbpbEntry_SansIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1195DECLASM(int) hmR0SvmVmRun_SansXcr0_WithIbpbEntry_SansIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1196DECLASM(int) hmR0SvmVmRun_WithXcr0_WithIbpbEntry_SansIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1197DECLASM(int) hmR0SvmVmRun_SansXcr0_SansIbpbEntry_WithIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1198DECLASM(int) hmR0SvmVmRun_WithXcr0_SansIbpbEntry_WithIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1199DECLASM(int) hmR0SvmVmRun_SansXcr0_WithIbpbEntry_WithIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1200DECLASM(int) hmR0SvmVmRun_WithXcr0_WithIbpbEntry_WithIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1201/** @} */
1202
1203/** @} */
1204
1205
1206/** @addtogroup grp_hm_int_vmx VMX Internal
1207 * @{ */
1208VMM_INT_DECL(PVMXVMCSINFOSHARED) hmGetVmxActiveVmcsInfoShared(PVMCPUCC pVCpu);
1209
1210/**
1211 * Used on platforms with poor inline assembly support to retrieve all the
1212 * info from the CPU and put it in the @a pRestoreHost structure.
1213 */
1214DECLASM(void) hmR0VmxExportHostSegmentRegsAsmHlp(PVMXRESTOREHOST pRestoreHost, bool fHaveFsGsBase);
1215
1216/**
1217 * Restores some host-state fields that need not be done on every VM-exit.
1218 *
1219 * @returns VBox status code.
1220 * @param fRestoreHostFlags Flags of which host registers needs to be
1221 * restored.
1222 * @param pRestoreHost Pointer to the host-restore structure.
1223 */
1224DECLASM(int) VMXRestoreHostState(uint32_t fRestoreHostFlags, PVMXRESTOREHOST pRestoreHost);
1225
1226/**
1227 * VMX StartVM functions.
1228 *
1229 * @returns VBox status code (no informational stuff).
1230 * @param pVmcsInfo Pointer to the VMCS info (for cached host RIP and RSP).
1231 * @param pVCpu Pointer to the cross context per-CPU structure of the
1232 * calling EMT.
1233 * @param fResume Whether to use VMRESUME (true) or VMLAUNCH (false).
1234 *
1235 * @remarks With spectre mitigations and the usual need for speed (/ micro
1236 * optimizations), we have a bunch of variations of this code depending
1237 * on a few precoditions. In release builds, the code is entirely
1238 * without conditionals. Debug builds have a couple of assertions that
1239 * shouldn't ever be triggered.
1240 *
1241 * @{
1242 */
1243DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_SansL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1244DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_SansL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1245DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_SansL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1246DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_SansL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1247DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_WithL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1248DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_WithL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1249DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_WithL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1250DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_WithL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1251DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_SansL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1252DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_SansL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1253DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_SansL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1254DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_SansL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1255DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_WithL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1256DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_WithL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1257DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_WithL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1258DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_WithL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1259DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_SansL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1260DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_SansL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1261DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_SansL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1262DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_SansL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1263DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_WithL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1264DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_WithL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1265DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_WithL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1266DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_WithL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1267DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_SansL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1268DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_SansL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1269DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_SansL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1270DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_SansL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1271DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_WithL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1272DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_WithL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1273DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_WithL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1274DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_WithL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1275/** @} */
1276
1277/** @} */
1278
1279/** @} */
1280
1281RT_C_DECLS_END
1282
1283#endif /* !VMM_INCLUDED_SRC_include_HMInternal_h */
1284
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