VirtualBox

source: vbox/trunk/src/VBox/VMM/include/HMInternal.h@ 98103

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1/* $Id: HMInternal.h 98103 2023-01-17 14:15:46Z vboxsync $ */
2/** @file
3 * HM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VMM_INCLUDED_SRC_include_HMInternal_h
29#define VMM_INCLUDED_SRC_include_HMInternal_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34#include <VBox/cdefs.h>
35#include <VBox/types.h>
36#include <VBox/vmm/stam.h>
37#include <VBox/dis.h>
38#include <VBox/vmm/hm.h>
39#include <VBox/vmm/hm_vmx.h>
40#include <VBox/vmm/hm_svm.h>
41#include <VBox/vmm/pgm.h>
42#include <VBox/vmm/cpum.h>
43#include <VBox/vmm/trpm.h>
44#include <iprt/memobj.h>
45#include <iprt/cpuset.h>
46#include <iprt/mp.h>
47#include <iprt/avl.h>
48#include <iprt/string.h>
49
50#include "VMXInternal.h"
51#include "SVMInternal.h"
52
53#if HC_ARCH_BITS == 32
54# error "32-bit hosts are no longer supported. Go back to 6.0 or earlier!"
55#endif
56
57/** @def HM_PROFILE_EXIT_DISPATCH
58 * Enables profiling of the VM exit handler dispatching. */
59#if 0 || defined(DOXYGEN_RUNNING)
60# define HM_PROFILE_EXIT_DISPATCH
61#endif
62
63RT_C_DECLS_BEGIN
64
65
66/** @defgroup grp_hm_int Internal
67 * @ingroup grp_hm
68 * @internal
69 * @{
70 */
71
72/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
73#define HM_EPT_IDENTITY_PG_TABLE_SIZE HOST_PAGE_SIZE
74/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
75#define HM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2 * X86_PAGE_SIZE + 1)
76/** Total guest mapped memory needed. */
77#define HM_VTX_TOTAL_DEVHEAP_MEM (HM_EPT_IDENTITY_PG_TABLE_SIZE + HM_VTX_TSS_SIZE)
78
79
80/** @name Macros for enabling and disabling preemption.
81 * These are really just for hiding the RTTHREADPREEMPTSTATE and asserting that
82 * preemption has already been disabled when there is no context hook.
83 * @{ */
84#ifdef VBOX_STRICT
85# define HM_DISABLE_PREEMPT(a_pVCpu) \
86 RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
87 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD) || VMMR0ThreadCtxHookIsEnabled((a_pVCpu))); \
88 RTThreadPreemptDisable(&PreemptStateInternal)
89#else
90# define HM_DISABLE_PREEMPT(a_pVCpu) \
91 RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
92 RTThreadPreemptDisable(&PreemptStateInternal)
93#endif /* VBOX_STRICT */
94#define HM_RESTORE_PREEMPT() do { RTThreadPreemptRestore(&PreemptStateInternal); } while(0)
95/** @} */
96
97
98/** @name HM saved state versions.
99 * @{
100 */
101#define HM_SAVED_STATE_VERSION HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT
102#define HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT 6
103#define HM_SAVED_STATE_VERSION_TPR_PATCHING 5
104#define HM_SAVED_STATE_VERSION_NO_TPR_PATCHING 4
105#define HM_SAVED_STATE_VERSION_2_0_X 3
106/** @} */
107
108
109/**
110 * HM physical (host) CPU information.
111 */
112typedef struct HMPHYSCPU
113{
114 /** The CPU ID. */
115 RTCPUID idCpu;
116 /** The VM_HSAVE_AREA (AMD-V) / VMXON region (Intel) memory backing. */
117 RTR0MEMOBJ hMemObj;
118 /** The physical address of the first page in hMemObj (it's a
119 * physcially contigous allocation if it spans multiple pages). */
120 RTHCPHYS HCPhysMemObj;
121 /** The address of the memory (for pfnEnable). */
122 void *pvMemObj;
123 /** Current ASID (AMD-V) / VPID (Intel). */
124 uint32_t uCurrentAsid;
125 /** TLB flush count. */
126 uint32_t cTlbFlushes;
127 /** Whether to flush each new ASID/VPID before use. */
128 bool fFlushAsidBeforeUse;
129 /** Configured for VT-x or AMD-V. */
130 bool fConfigured;
131 /** Set if the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active. */
132 bool fIgnoreAMDVInUseError;
133 /** Whether CR4.VMXE was already enabled prior to us enabling it. */
134 bool fVmxeAlreadyEnabled;
135 /** In use by our code. (for power suspend) */
136 bool volatile fInUse;
137#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
138 /** Nested-guest union (put data common to SVM/VMX outside the union). */
139 union
140 {
141 /** Nested-guest SVM data. */
142 struct
143 {
144 /** The active nested-guest MSR permission bitmap memory backing. */
145 RTR0MEMOBJ hNstGstMsrpm;
146 /** The physical address of the first page in hNstGstMsrpm (physcially
147 * contiguous allocation). */
148 RTHCPHYS HCPhysNstGstMsrpm;
149 /** The address of the active nested-guest MSRPM. */
150 void *pvNstGstMsrpm;
151 } svm;
152 /** @todo Nested-VMX. */
153 } n;
154#endif
155} HMPHYSCPU;
156/** Pointer to HMPHYSCPU struct. */
157typedef HMPHYSCPU *PHMPHYSCPU;
158/** Pointer to a const HMPHYSCPU struct. */
159typedef const HMPHYSCPU *PCHMPHYSCPU;
160
161/**
162 * TPR-instruction type.
163 */
164typedef enum
165{
166 HMTPRINSTR_INVALID,
167 HMTPRINSTR_READ,
168 HMTPRINSTR_READ_SHR4,
169 HMTPRINSTR_WRITE_REG,
170 HMTPRINSTR_WRITE_IMM,
171 HMTPRINSTR_JUMP_REPLACEMENT,
172 /** The usual 32-bit paranoia. */
173 HMTPRINSTR_32BIT_HACK = 0x7fffffff
174} HMTPRINSTR;
175
176/**
177 * TPR patch information.
178 */
179typedef struct
180{
181 /** The key is the address of patched instruction. (32 bits GC ptr) */
182 AVLOU32NODECORE Core;
183 /** Original opcode. */
184 uint8_t aOpcode[16];
185 /** Instruction size. */
186 uint32_t cbOp;
187 /** Replacement opcode. */
188 uint8_t aNewOpcode[16];
189 /** Replacement instruction size. */
190 uint32_t cbNewOp;
191 /** Instruction type. */
192 HMTPRINSTR enmType;
193 /** Source operand. */
194 uint32_t uSrcOperand;
195 /** Destination operand. */
196 uint32_t uDstOperand;
197 /** Number of times the instruction caused a fault. */
198 uint32_t cFaults;
199 /** Patch address of the jump replacement. */
200 RTGCPTR32 pJumpTarget;
201} HMTPRPATCH;
202/** Pointer to HMTPRPATCH. */
203typedef HMTPRPATCH *PHMTPRPATCH;
204/** Pointer to a const HMTPRPATCH. */
205typedef const HMTPRPATCH *PCHMTPRPATCH;
206
207
208/**
209 * Makes a HMEXITSTAT::uKey value from a program counter and an exit code.
210 *
211 * @returns 64-bit key
212 * @param a_uPC The RIP + CS.BASE value of the exit.
213 * @param a_uExit The exit code.
214 * @todo Add CPL?
215 */
216#define HMEXITSTAT_MAKE_KEY(a_uPC, a_uExit) (((a_uPC) & UINT64_C(0x0000ffffffffffff)) | (uint64_t)(a_uExit) << 48)
217
218typedef struct HMEXITINFO
219{
220 /** See HMEXITSTAT_MAKE_KEY(). */
221 uint64_t uKey;
222 /** Number of recent hits (depreciates with time). */
223 uint32_t volatile cHits;
224 /** The age + lock. */
225 uint16_t volatile uAge;
226 /** Action or action table index. */
227 uint16_t iAction;
228} HMEXITINFO;
229AssertCompileSize(HMEXITINFO, 16); /* Lots of these guys, so don't add any unnecessary stuff! */
230
231typedef struct HMEXITHISTORY
232{
233 /** The exit timestamp. */
234 uint64_t uTscExit;
235 /** The index of the corresponding HMEXITINFO entry.
236 * UINT32_MAX if none (too many collisions, race, whatever). */
237 uint32_t iExitInfo;
238 /** Figure out later, needed for padding now. */
239 uint32_t uSomeClueOrSomething;
240} HMEXITHISTORY;
241
242/**
243 * Switcher function, HC to the special 64-bit RC.
244 *
245 * @param pVM The cross context VM structure.
246 * @param offCpumVCpu Offset from pVM->cpum to pVM->aCpus[idCpu].cpum.
247 * @returns Return code indicating the action to take.
248 */
249typedef DECLCALLBACKTYPE(int, FNHMSWITCHERHC,(PVM pVM, uint32_t offCpumVCpu));
250/** Pointer to switcher function. */
251typedef FNHMSWITCHERHC *PFNHMSWITCHERHC;
252
253
254/**
255 * HM VM Instance data.
256 * Changes to this must checked against the padding of the hm union in VM!
257 */
258typedef struct HM
259{
260 /** Set when the debug facility has breakpoints/events enabled that requires
261 * us to use the debug execution loop in ring-0. */
262 bool fUseDebugLoop;
263 /** Set when TPR patching is allowed. */
264 bool fTprPatchingAllowed;
265 /** Set when TPR patching is active. */
266 bool fTprPatchingActive;
267 /** Alignment padding. */
268 bool afAlignment1[5];
269
270 struct
271 {
272 /** Set by the ring-0 side of HM to indicate VMX is supported by the CPU. */
273 bool fSupported;
274 /** Set when we've enabled VMX. */
275 bool fEnabled;
276 /** The shift mask employed by the VMX-Preemption timer (set by ring-0). */
277 uint8_t cPreemptTimerShift;
278
279 /** @name Configuration (gets copied if problematic)
280 * @{ */
281 /** Set if Last Branch Record (LBR) is enabled. */
282 bool fLbrCfg;
283 /** Set if VT-x VPID is allowed. */
284 bool fAllowVpid;
285 /** Set if unrestricted guest execution is in use (real and protected mode
286 * without paging). */
287 bool fUnrestrictedGuestCfg;
288 /** Set if the preemption timer should be used if available. Ring-0
289 * quietly clears this if the hardware doesn't support the preemption timer. */
290 bool fUsePreemptTimerCfg;
291 /** Whether to always intercept MOV DRx: 1 (always), 0 (default), -1 (lazy).
292 * In the default case it is only always intercepted when setting DR6 to 0 on
293 * the host results in a value different from X86_DR6_RA1_MASK. */
294 int8_t fAlwaysInterceptMovDRxCfg;
295 /** @} */
296
297 /** Pause-loop exiting (PLE) gap in ticks. */
298 uint32_t cPleGapTicks;
299 /** Pause-loop exiting (PLE) window in ticks. */
300 uint32_t cPleWindowTicks;
301
302 /** Virtual address of the TSS page used for real mode emulation. */
303 R3PTRTYPE(PVBOXTSS) pRealModeTSS;
304 /** Virtual address of the identity page table used for real mode and protected
305 * mode without paging emulation in EPT mode. */
306 R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
307 } vmx;
308
309 struct
310 {
311 /** Set by the ring-0 side of HM to indicate SVM is supported by the CPU. */
312 bool fSupported;
313 /** Set when we've enabled SVM. */
314 bool fEnabled;
315 /** Set when the hack to ignore VERR_SVM_IN_USE is active.
316 * @todo Safe? */
317 bool fIgnoreInUseError;
318 /** Whether to use virtualized VMSAVE/VMLOAD feature. */
319 bool fVirtVmsaveVmload;
320 /** Whether to use virtual GIF feature. */
321 bool fVGif;
322 /** Whether to use LBR virtualization feature. */
323 bool fLbrVirt;
324 bool afAlignment1[2];
325
326 /** Pause filter counter. */
327 uint16_t cPauseFilter;
328 /** Pause filter treshold in ticks. */
329 uint16_t cPauseFilterThresholdTicks;
330 uint32_t u32Alignment2;
331 } svm;
332
333 /** AVL tree with all patches (active or disabled) sorted by guest instruction address.
334 * @todo For @bugref{9217} this AVL tree must be eliminated and instead
335 * sort aPatches by address and do a safe binary search on it. */
336 AVLOU32TREE PatchTree;
337 uint32_t cPatches;
338 HMTPRPATCH aPatches[64];
339
340 /** Guest allocated memory for patching purposes. */
341 RTGCPTR pGuestPatchMem;
342 /** Current free pointer inside the patch block. */
343 RTGCPTR pFreeGuestPatchMem;
344 /** Size of the guest patch memory block. */
345 uint32_t cbGuestPatchMem;
346 uint32_t u32Alignment2;
347
348 /** For ring-3 use only. */
349 struct
350 {
351 /** Last recorded error code during HM ring-0 init. */
352 int32_t rcInit;
353 uint32_t u32Alignment3;
354
355 /** Maximum ASID allowed.
356 * This is mainly for the release log. */
357 uint32_t uMaxAsid;
358 /** World switcher flags (HM_WSF_XXX) for the release log. */
359 uint32_t fWorldSwitcher;
360
361 struct
362 {
363 /** Set if VPID is supported (ring-3 copy). */
364 bool fVpid;
365 /** Whether the CPU supports VMCS fields for swapping EFER (set by ring-0 VMX
366 * init, for logging). */
367 bool fSupportsVmcsEfer;
368 /** Whether to use VMCS shadowing. */
369 bool fUseVmcsShadowing;
370 /** Whether MOV DRx is always intercepted or not (set by ring-0 VMX init, for
371 * logging). */
372 bool fAlwaysInterceptMovDRx;
373
374 /** Host CR4 value (set by ring-0 VMX init, for logging). */
375 uint64_t u64HostCr4;
376 /** Host SMM monitor control (set by ring-0 VMX init, for logging). */
377 uint64_t u64HostSmmMonitorCtl;
378 /** Host EFER value (set by ring-0 VMX init, for logging and guest NX). */
379 uint64_t u64HostMsrEfer;
380 /** Host IA32_FEATURE_CONTROL MSR (set by ring-0 VMX init, for logging). */
381 uint64_t u64HostFeatCtrl;
382 /** Host zero'ed DR6 value (set by ring-0 VMX init, for logging). */
383 uint64_t u64HostDr6Zeroed;
384
385 /** The first valid host LBR branch-from-IP stack range. */
386 uint32_t idLbrFromIpMsrFirst;
387 /** The last valid host LBR branch-from-IP stack range. */
388 uint32_t idLbrFromIpMsrLast;
389
390 /** The first valid host LBR branch-to-IP stack range. */
391 uint32_t idLbrToIpMsrFirst;
392 /** The last valid host LBR branch-to-IP stack range. */
393 uint32_t idLbrToIpMsrLast;
394
395 /** Host-physical address for a failing VMXON instruction (for diagnostics, ring-3). */
396 RTHCPHYS HCPhysVmxEnableError;
397 /** VMX MSR values (only for ring-3 consumption). */
398 VMXMSRS Msrs;
399
400 /** Tagged-TLB flush type (only for ring-3 consumption). */
401 VMXTLBFLUSHTYPE enmTlbFlushType;
402 /** Flush type to use for INVEPT (only for ring-3 consumption). */
403 VMXTLBFLUSHEPT enmTlbFlushEpt;
404 /** Flush type to use for INVVPID (only for ring-3 consumption). */
405 VMXTLBFLUSHVPID enmTlbFlushVpid;
406 } vmx;
407
408 struct
409 {
410 /** SVM revision. */
411 uint32_t u32Rev;
412 /** SVM feature bits from cpuid 0x8000000a, ring-3 copy. */
413 uint32_t fFeatures;
414 /** HWCR MSR (for diagnostics). */
415 uint64_t u64MsrHwcr;
416 } svm;
417 } ForR3;
418
419 /** @name Configuration not used (much) after VM setup
420 * @{ */
421 /** The maximum number of resumes loops allowed in ring-0 (safety precaution).
422 * This number is set much higher when RTThreadPreemptIsPending is reliable. */
423 uint32_t cMaxResumeLoopsCfg;
424 /** Set if nested paging is enabled.
425 * Config value that is copied to HMR0PERVM::fNestedPaging on setup. */
426 bool fNestedPagingCfg;
427 /** Set if large pages are enabled (requires nested paging).
428 * Config only, passed on the PGM where it really belongs.
429 * @todo move to PGM */
430 bool fLargePages;
431 /** Set if we can support 64-bit guests or not.
432 * Config value that is copied to HMR0PERVM::fAllow64BitGuests on setup. */
433 bool fAllow64BitGuestsCfg;
434 /** Set when we initialize VT-x or AMD-V once for all CPUs. */
435 bool fGlobalInit;
436 /** Set if hardware APIC virtualization is enabled.
437 * @todo Not really used by HM, move to APIC where it's actually used. */
438 bool fVirtApicRegs;
439 /** Set if posted interrupt processing is enabled.
440 * @todo Not really used by HM, move to APIC where it's actually used. */
441 bool fPostedIntrs;
442 /** VM needs workaround for missing TLB flush in OS/2, see ticketref:20625.
443 * @note Currently only heeded by AMD-V. */
444 bool fMissingOS2TlbFlushWorkaround;
445 /** @} */
446
447 /** @name Processed into HMR0PERVCPU::fWorldSwitcher by ring-0 on VM init.
448 * @{ */
449 /** Set if indirect branch prediction barrier on VM exit. */
450 bool fIbpbOnVmExit;
451 /** Set if indirect branch prediction barrier on VM entry. */
452 bool fIbpbOnVmEntry;
453 /** Set if level 1 data cache should be flushed on VM entry. */
454 bool fL1dFlushOnVmEntry;
455 /** Set if level 1 data cache should be flushed on EMT scheduling. */
456 bool fL1dFlushOnSched;
457 /** Set if MDS related buffers should be cleared on VM entry. */
458 bool fMdsClearOnVmEntry;
459 /** Set if MDS related buffers should be cleared on EMT scheduling. */
460 bool fMdsClearOnSched;
461 /** Set if host manages speculation control settings.
462 * @todo doesn't do anything ... */
463 bool fSpecCtrlByHost;
464 /** @} */
465
466 /** Set when we've finalized the VMX / SVM initialization in ring-3
467 * (hmR3InitFinalizeR0Intel / hmR3InitFinalizeR0Amd). */
468 bool fInitialized;
469
470 bool afAlignment2[5];
471
472 STAMCOUNTER StatTprPatchSuccess;
473 STAMCOUNTER StatTprPatchFailure;
474 STAMCOUNTER StatTprReplaceSuccessCr8;
475 STAMCOUNTER StatTprReplaceSuccessVmc;
476 STAMCOUNTER StatTprReplaceFailure;
477} HM;
478/** Pointer to HM VM instance data. */
479typedef HM *PHM;
480AssertCompileMemberAlignment(HM, StatTprPatchSuccess, 8);
481AssertCompileMemberAlignment(HM, vmx, 8);
482AssertCompileMemberAlignment(HM, svm, 8);
483AssertCompileMemberAlignment(HM, StatTprPatchSuccess, 8);
484AssertCompile(RTASSERT_OFFSET_OF(HM, PatchTree) <= 64); /* First cache line has the essentials for both VT-x and SVM operation. */
485
486
487/**
488 * Per-VM ring-0 instance data for HM.
489 */
490typedef struct HMR0PERVM
491{
492 /** The maximum number of resumes loops allowed in ring-0 (safety precaution).
493 * This number is set much higher when RTThreadPreemptIsPending is reliable. */
494 uint32_t cMaxResumeLoops;
495
496 /** Set if nested paging is enabled. */
497 bool fNestedPaging;
498 /** Set if we can support 64-bit guests or not. */
499 bool fAllow64BitGuests;
500 bool afAlignment1[1];
501
502 /** AMD-V specific data. */
503 struct HMR0SVMVM
504 {
505 /** Set if erratum 170 affects the AMD cpu. */
506 bool fAlwaysFlushTLB;
507 } svm;
508
509 /** VT-x specific data. */
510 struct HMR0VMXVM
511 {
512 /** Set if unrestricted guest execution is in use (real and protected mode
513 * without paging). */
514 bool fUnrestrictedGuest;
515 /** Set if the preemption timer is in use. */
516 bool fUsePreemptTimer;
517 /** Whether to use VMCS shadowing. */
518 bool fUseVmcsShadowing;
519 /** Set if Last Branch Record (LBR) is enabled. */
520 bool fLbr;
521 /** Set always intercept MOV DRx. */
522 bool fAlwaysInterceptMovDRx;
523 bool afAlignment2[2];
524
525 /** Set if VPID is supported (copy in HM::vmx::fVpidForRing3). */
526 bool fVpid;
527 /** Tagged-TLB flush type. */
528 VMXTLBFLUSHTYPE enmTlbFlushType;
529 /** Flush type to use for INVEPT. */
530 VMXTLBFLUSHEPT enmTlbFlushEpt;
531 /** Flush type to use for INVVPID. */
532 VMXTLBFLUSHVPID enmTlbFlushVpid;
533
534 /** The host LBR TOS (top-of-stack) MSR id. */
535 uint32_t idLbrTosMsr;
536
537 /** The first valid host LBR branch-from-IP stack range. */
538 uint32_t idLbrFromIpMsrFirst;
539 /** The last valid host LBR branch-from-IP stack range. */
540 uint32_t idLbrFromIpMsrLast;
541
542 /** The first valid host LBR branch-to-IP stack range. */
543 uint32_t idLbrToIpMsrFirst;
544 /** The last valid host LBR branch-to-IP stack range. */
545 uint32_t idLbrToIpMsrLast;
546
547 /** Pointer to the VMREAD bitmap. */
548 R0PTRTYPE(void *) pvVmreadBitmap;
549 /** Pointer to the VMWRITE bitmap. */
550 R0PTRTYPE(void *) pvVmwriteBitmap;
551
552 /** Pointer to the shadow VMCS read-only fields array. */
553 R0PTRTYPE(uint32_t *) paShadowVmcsRoFields;
554 /** Pointer to the shadow VMCS read/write fields array. */
555 R0PTRTYPE(uint32_t *) paShadowVmcsFields;
556 /** Number of elements in the shadow VMCS read-only fields array. */
557 uint32_t cShadowVmcsRoFields;
558 /** Number of elements in the shadow VMCS read-write fields array. */
559 uint32_t cShadowVmcsFields;
560
561 /** Host-physical address of the APIC-access page. */
562 RTHCPHYS HCPhysApicAccess;
563 /** Host-physical address of the VMREAD bitmap. */
564 RTHCPHYS HCPhysVmreadBitmap;
565 /** Host-physical address of the VMWRITE bitmap. */
566 RTHCPHYS HCPhysVmwriteBitmap;
567
568#ifdef VBOX_WITH_CRASHDUMP_MAGIC
569 /** Host-physical address of the crash-dump scratch area. */
570 RTHCPHYS HCPhysScratch;
571 /** Pointer to the crash-dump scratch bitmap. */
572 R0PTRTYPE(uint8_t *) pbScratch;
573#endif
574
575 /** Ring-0 memory object for per-VM VMX structures. */
576 RTR0MEMOBJ hMemObj;
577 /** Virtual address of the APIC-access page (not used). */
578 R0PTRTYPE(uint8_t *) pbApicAccess;
579 } vmx;
580} HMR0PERVM;
581/** Pointer to HM's per-VM ring-0 instance data. */
582typedef HMR0PERVM *PHMR0PERVM;
583
584
585/** @addtogroup grp_hm_int_svm SVM Internal
586 * @{ */
587/** SVM VMRun function, see SVMR0VMRun(). */
588typedef DECLCALLBACKTYPE(int, FNHMSVMVMRUN,(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhysVMCB));
589/** Pointer to a SVM VMRun function. */
590typedef R0PTRTYPE(FNHMSVMVMRUN *) PFNHMSVMVMRUN;
591
592/**
593 * SVM nested-guest VMCB cache.
594 *
595 * Contains VMCB fields from the nested-guest VMCB before they're modified by
596 * SVM R0 code for hardware-assisted SVM execution of a nested-guest.
597 *
598 * A VMCB field needs to be cached when it needs to be modified for execution using
599 * hardware-assisted SVM and any of the following are true:
600 * - If the original field needs to be inspected during execution of the
601 * nested-guest or \#VMEXIT processing.
602 * - If the field is written back to memory on \#VMEXIT by the physical CPU.
603 *
604 * A VMCB field needs to be restored only when the field is written back to
605 * memory on \#VMEXIT by the physical CPU and thus would be visible to the
606 * guest.
607 *
608 * @remarks Please update hmR3InfoSvmNstGstVmcbCache() when changes are made to
609 * this structure.
610 */
611typedef struct SVMNESTEDVMCBCACHE
612{
613 /** Cache of CRX read intercepts. */
614 uint16_t u16InterceptRdCRx;
615 /** Cache of CRX write intercepts. */
616 uint16_t u16InterceptWrCRx;
617 /** Cache of DRX read intercepts. */
618 uint16_t u16InterceptRdDRx;
619 /** Cache of DRX write intercepts. */
620 uint16_t u16InterceptWrDRx;
621
622 /** Cache of the pause-filter threshold. */
623 uint16_t u16PauseFilterThreshold;
624 /** Cache of the pause-filter count. */
625 uint16_t u16PauseFilterCount;
626
627 /** Cache of exception intercepts. */
628 uint32_t u32InterceptXcpt;
629 /** Cache of control intercepts. */
630 uint64_t u64InterceptCtrl;
631
632 /** Cache of the TSC offset. */
633 uint64_t u64TSCOffset;
634
635 /** Cache of V_INTR_MASKING bit. */
636 bool fVIntrMasking;
637 /** Cache of the nested-paging bit. */
638 bool fNestedPaging;
639 /** Cache of the LBR virtualization bit. */
640 bool fLbrVirt;
641 /** Whether the VMCB is cached by HM. */
642 bool fCacheValid;
643 /** Alignment. */
644 bool afPadding0[4];
645} SVMNESTEDVMCBCACHE;
646/** Pointer to the SVMNESTEDVMCBCACHE structure. */
647typedef SVMNESTEDVMCBCACHE *PSVMNESTEDVMCBCACHE;
648/** Pointer to a const SVMNESTEDVMCBCACHE structure. */
649typedef const SVMNESTEDVMCBCACHE *PCSVMNESTEDVMCBCACHE;
650AssertCompileSizeAlignment(SVMNESTEDVMCBCACHE, 8);
651
652/** @} */
653
654
655/** @addtogroup grp_hm_int_vmx VMX Internal
656 * @{ */
657
658/** @name Host-state restoration flags.
659 * @note If you change these values don't forget to update the assembly
660 * defines as well!
661 * @{
662 */
663#define VMX_RESTORE_HOST_SEL_DS RT_BIT(0)
664#define VMX_RESTORE_HOST_SEL_ES RT_BIT(1)
665#define VMX_RESTORE_HOST_SEL_FS RT_BIT(2)
666#define VMX_RESTORE_HOST_SEL_GS RT_BIT(3)
667#define VMX_RESTORE_HOST_SEL_TR RT_BIT(4)
668#define VMX_RESTORE_HOST_GDTR RT_BIT(5)
669#define VMX_RESTORE_HOST_IDTR RT_BIT(6)
670#define VMX_RESTORE_HOST_GDT_READ_ONLY RT_BIT(7)
671#define VMX_RESTORE_HOST_GDT_NEED_WRITABLE RT_BIT(8)
672#define VMX_RESTORE_HOST_CAN_USE_WRFSBASE_AND_WRGSBASE RT_BIT(9)
673/**
674 * This _must_ be the top most bit, so that we can easily check that it and
675 * something else is set w/o having to do two checks like this:
676 * @code
677 * if ( (pVCpu->hm.s.vmx.fRestoreHostFlags & VMX_RESTORE_HOST_REQUIRED)
678 * && (pVCpu->hm.s.vmx.fRestoreHostFlags & ~VMX_RESTORE_HOST_REQUIRED))
679 * @endcode
680 * Instead we can then do:
681 * @code
682 * if (pVCpu->hm.s.vmx.fRestoreHostFlags > VMX_RESTORE_HOST_REQUIRED)
683 * @endcode
684 */
685#define VMX_RESTORE_HOST_REQUIRED RT_BIT(10)
686/** @} */
687
688/**
689 * Host-state restoration structure.
690 *
691 * This holds host-state fields that require manual restoration.
692 * Assembly version found in HMInternal.mac (should be automatically verified).
693 */
694typedef struct VMXRESTOREHOST
695{
696 RTSEL uHostSelDS; /**< 0x00 */
697 RTSEL uHostSelES; /**< 0x02 */
698 RTSEL uHostSelFS; /**< 0x04 */
699 X86XDTR64 HostGdtr; /**< 0x06 - should be aligned by its 64-bit member. */
700 RTSEL uHostSelGS; /**< 0x10 */
701 RTSEL uHostSelTR; /**< 0x12 */
702 RTSEL uHostSelSS; /**< 0x14 - not restored, just for fetching */
703 X86XDTR64 HostGdtrRw; /**< 0x16 - should be aligned by its 64-bit member. */
704 RTSEL uHostSelCS; /**< 0x20 - not restored, just for fetching */
705 uint8_t abPadding1[4]; /**< 0x22 */
706 X86XDTR64 HostIdtr; /**< 0x26 - should be aligned by its 64-bit member. */
707 uint64_t uHostFSBase; /**< 0x30 */
708 uint64_t uHostGSBase; /**< 0x38 */
709} VMXRESTOREHOST;
710/** Pointer to VMXRESTOREHOST. */
711typedef VMXRESTOREHOST *PVMXRESTOREHOST;
712AssertCompileSize(X86XDTR64, 10);
713AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtr.uAddr, 0x08);
714AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtrRw.uAddr, 0x18);
715AssertCompileMemberOffset(VMXRESTOREHOST, HostIdtr.uAddr, 0x28);
716AssertCompileMemberOffset(VMXRESTOREHOST, uHostFSBase, 0x30);
717AssertCompileSize(VMXRESTOREHOST, 64);
718AssertCompileSizeAlignment(VMXRESTOREHOST, 8);
719
720/**
721 * VMX StartVM function.
722 *
723 * @returns VBox status code (no informational stuff).
724 * @param pVmcsInfo Pointer to the VMCS info (for cached host RIP and RSP).
725 * @param pVCpu Pointer to the cross context per-CPU structure.
726 * @param fResume Whether to use VMRESUME (true) or VMLAUNCH (false).
727 */
728typedef DECLCALLBACKTYPE(int, FNHMVMXSTARTVM,(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume));
729/** Pointer to a VMX StartVM function. */
730typedef R0PTRTYPE(FNHMVMXSTARTVM *) PFNHMVMXSTARTVM;
731/** @} */
732
733
734/**
735 * HM VMCPU Instance data.
736 *
737 * Note! If you change members of this struct, make sure to check if the
738 * assembly counterpart in HMInternal.mac needs to be updated as well.
739 *
740 * Note! The members here are ordered and aligned based on estimated frequency of
741 * usage and grouped to fit within a cache line in hot code paths. Even subtle
742 * changes here have a noticeable effect in the bootsector benchmarks. Modify with
743 * care.
744 */
745typedef struct HMCPU
746{
747 /** Set when the TLB has been checked until we return from the world switch. */
748 bool volatile fCheckedTLBFlush;
749 /** Set when we're using VT-x or AMD-V at that moment.
750 * @todo r=bird: Misleading description. For AMD-V this will be set the first
751 * time HMCanExecuteGuest() is called and only cleared again by
752 * HMR3ResetCpu(). For VT-x it will be set by HMCanExecuteGuest when we
753 * can execute something in VT-x mode, and cleared if we cannot.
754 *
755 * The field is much more about recording the last HMCanExecuteGuest
756 * return value than anything about any "moment". */
757 bool fActive;
758
759 /** Whether we should use the debug loop because of single stepping or special
760 * debug breakpoints / events are armed. */
761 bool fUseDebugLoop;
762
763 /** Whether \#UD needs to be intercepted (required by certain GIM providers). */
764 bool fGIMTrapXcptUD;
765 /** Whether \#GP needs to be intercepted for mesa driver workaround. */
766 bool fTrapXcptGpForLovelyMesaDrv;
767 /** Whether we're executing a single instruction. */
768 bool fSingleInstruction;
769 /** Whether \#DE needs to be intercepted (may be required by GCM). */
770 bool fGCMTrapXcptDE;
771
772 bool afAlignment0[1];
773
774 /** An additional error code used for some gurus. */
775 uint32_t u32HMError;
776 /** The last exit-to-ring-3 reason. */
777 int32_t rcLastExitToR3;
778 /** CPU-context changed flags (see HM_CHANGED_xxx). */
779 uint64_t fCtxChanged;
780
781 /** VT-x data. */
782 struct HMCPUVMX
783 {
784 /** @name Guest information.
785 * @{ */
786 /** Guest VMCS information shared with ring-3. */
787 VMXVMCSINFOSHARED VmcsInfo;
788 /** Nested-guest VMCS information shared with ring-3. */
789 VMXVMCSINFOSHARED VmcsInfoNstGst;
790 /** Whether the nested-guest VMCS was the last current VMCS (shadow copy for ring-3).
791 * @see HMR0PERVCPU::vmx.fSwitchedToNstGstVmcs */
792 bool fSwitchedToNstGstVmcsCopyForRing3;
793 /** Whether the static guest VMCS controls has been merged with the
794 * nested-guest VMCS controls. */
795 bool fMergedNstGstCtls;
796 /** Whether the nested-guest VMCS has been copied to the shadow VMCS. */
797 bool fCopiedNstGstToShadowVmcs;
798 /** Whether flushing the TLB is required due to switching to/from the
799 * nested-guest. */
800 bool fSwitchedNstGstFlushTlb;
801 /** Alignment. */
802 bool afAlignment0[4];
803 /** Cached guest APIC-base MSR for identifying when to map the APIC-access page. */
804 uint64_t u64GstMsrApicBase;
805 /** @} */
806
807 /** @name Error reporting and diagnostics.
808 * @{ */
809 /** VT-x error-reporting (mainly for ring-3 propagation). */
810 struct
811 {
812 RTCPUID idCurrentCpu;
813 RTCPUID idEnteredCpu;
814 RTHCPHYS HCPhysCurrentVmcs;
815 uint32_t u32VmcsRev;
816 uint32_t u32InstrError;
817 uint32_t u32ExitReason;
818 uint32_t u32GuestIntrState;
819 } LastError;
820 /** @} */
821 } vmx;
822
823 /** SVM data. */
824 struct HMCPUSVM
825 {
826 /** Whether to emulate long mode support for sysenter/sysexit like intel CPUs
827 * does. This means intercepting \#UD to emulate the instructions in
828 * long-mode and to intercept reads and writes to the SYSENTER MSRs in order to
829 * preserve the upper 32 bits written to them (AMD will ignore and discard). */
830 bool fEmulateLongModeSysEnterExit;
831 uint8_t au8Alignment0[7];
832
833 /** Cache of the nested-guest's VMCB fields that we modify in order to run the
834 * nested-guest using AMD-V. This will be restored on \#VMEXIT. */
835 SVMNESTEDVMCBCACHE NstGstVmcbCache;
836 } svm;
837
838 /** Event injection state. */
839 HMEVENT Event;
840
841 /** Current shadow paging mode for updating CR4.
842 * @todo move later (@bugref{9217}). */
843 PGMMODE enmShadowMode;
844 uint32_t u32TemporaryPadding;
845
846 /** The PAE PDPEs used with Nested Paging (only valid when
847 * VMCPU_FF_HM_UPDATE_PAE_PDPES is set). */
848 X86PDPE aPdpes[4];
849
850 /* These two comes because they are accessed from assembly and we don't
851 want to detail all the stats in the assembly version of this structure. */
852 STAMCOUNTER StatVmxWriteHostRip;
853 STAMCOUNTER StatVmxWriteHostRsp;
854 STAMCOUNTER StatVmxVmLaunch;
855 STAMCOUNTER StatVmxVmResume;
856
857 STAMPROFILEADV StatEntry;
858 STAMPROFILEADV StatPreExit;
859 STAMPROFILEADV StatExitHandling;
860 STAMPROFILEADV StatExitIO;
861 STAMPROFILEADV StatExitMovCRx;
862 STAMPROFILEADV StatExitXcptNmi;
863 STAMPROFILEADV StatExitVmentry;
864 STAMPROFILEADV StatImportGuestState;
865 STAMPROFILEADV StatExportGuestState;
866 STAMPROFILEADV StatLoadGuestFpuState;
867 STAMPROFILEADV StatInGC;
868 STAMPROFILEADV StatPoke;
869 STAMPROFILEADV StatSpinPoke;
870 STAMPROFILEADV StatSpinPokeFailed;
871
872 STAMCOUNTER StatInjectInterrupt;
873 STAMCOUNTER StatInjectXcpt;
874 STAMCOUNTER StatInjectReflect;
875 STAMCOUNTER StatInjectConvertDF;
876 STAMCOUNTER StatInjectInterpret;
877 STAMCOUNTER StatInjectReflectNPF;
878
879 STAMCOUNTER StatImportGuestStateFallback;
880 STAMCOUNTER StatReadToTransientFallback;
881
882 STAMCOUNTER StatExitAll;
883 STAMCOUNTER StatDebugExitAll;
884 STAMCOUNTER StatNestedExitAll;
885 STAMCOUNTER StatExitShadowNM;
886 STAMCOUNTER StatExitGuestNM;
887 STAMCOUNTER StatExitShadowPF; /**< Misleading, currently used for MMIO \#PFs as well. */
888 STAMCOUNTER StatExitShadowPFEM;
889 STAMCOUNTER StatExitGuestPF;
890 STAMCOUNTER StatExitGuestUD;
891 STAMCOUNTER StatExitGuestSS;
892 STAMCOUNTER StatExitGuestNP;
893 STAMCOUNTER StatExitGuestTS;
894 STAMCOUNTER StatExitGuestOF;
895 STAMCOUNTER StatExitGuestGP;
896 STAMCOUNTER StatExitGuestDE;
897 STAMCOUNTER StatExitGuestDF;
898 STAMCOUNTER StatExitGuestBR;
899 STAMCOUNTER StatExitGuestAC;
900 STAMCOUNTER StatExitGuestACSplitLock;
901 STAMCOUNTER StatExitGuestDB;
902 STAMCOUNTER StatExitGuestMF;
903 STAMCOUNTER StatExitGuestBP;
904 STAMCOUNTER StatExitGuestXF;
905 STAMCOUNTER StatExitGuestXcpUnk;
906 STAMCOUNTER StatExitDRxWrite;
907 STAMCOUNTER StatExitDRxRead;
908 STAMCOUNTER StatExitCR0Read;
909 STAMCOUNTER StatExitCR2Read;
910 STAMCOUNTER StatExitCR3Read;
911 STAMCOUNTER StatExitCR4Read;
912 STAMCOUNTER StatExitCR8Read;
913 STAMCOUNTER StatExitCR0Write;
914 STAMCOUNTER StatExitCR2Write;
915 STAMCOUNTER StatExitCR3Write;
916 STAMCOUNTER StatExitCR4Write;
917 STAMCOUNTER StatExitCR8Write;
918 STAMCOUNTER StatExitRdmsr;
919 STAMCOUNTER StatExitWrmsr;
920 STAMCOUNTER StatExitClts;
921 STAMCOUNTER StatExitXdtrAccess;
922 STAMCOUNTER StatExitLmsw;
923 STAMCOUNTER StatExitIOWrite;
924 STAMCOUNTER StatExitIORead;
925 STAMCOUNTER StatExitIOStringWrite;
926 STAMCOUNTER StatExitIOStringRead;
927 STAMCOUNTER StatExitIntWindow;
928 STAMCOUNTER StatExitExtInt;
929 STAMCOUNTER StatExitHostNmiInGC;
930 STAMCOUNTER StatExitHostNmiInGCIpi;
931 STAMCOUNTER StatExitPreemptTimer;
932 STAMCOUNTER StatExitTprBelowThreshold;
933 STAMCOUNTER StatExitTaskSwitch;
934 STAMCOUNTER StatExitApicAccess;
935 STAMCOUNTER StatExitReasonNpf;
936
937 STAMCOUNTER StatNestedExitReasonNpf;
938
939 STAMCOUNTER StatFlushPage;
940 STAMCOUNTER StatFlushPageManual;
941 STAMCOUNTER StatFlushPhysPageManual;
942 STAMCOUNTER StatFlushTlb;
943 STAMCOUNTER StatFlushTlbNstGst;
944 STAMCOUNTER StatFlushTlbManual;
945 STAMCOUNTER StatFlushTlbWorldSwitch;
946 STAMCOUNTER StatNoFlushTlbWorldSwitch;
947 STAMCOUNTER StatFlushEntire;
948 STAMCOUNTER StatFlushAsid;
949 STAMCOUNTER StatFlushNestedPaging;
950 STAMCOUNTER StatFlushTlbInvlpgVirt;
951 STAMCOUNTER StatFlushTlbInvlpgPhys;
952 STAMCOUNTER StatTlbShootdown;
953 STAMCOUNTER StatTlbShootdownFlush;
954
955 STAMCOUNTER StatSwitchPendingHostIrq;
956 STAMCOUNTER StatSwitchTprMaskedIrq;
957 STAMCOUNTER StatSwitchGuestIrq;
958 STAMCOUNTER StatSwitchHmToR3FF;
959 STAMCOUNTER StatSwitchVmReq;
960 STAMCOUNTER StatSwitchPgmPoolFlush;
961 STAMCOUNTER StatSwitchDma;
962 STAMCOUNTER StatSwitchExitToR3;
963 STAMCOUNTER StatSwitchLongJmpToR3;
964 STAMCOUNTER StatSwitchMaxResumeLoops;
965 STAMCOUNTER StatSwitchHltToR3;
966 STAMCOUNTER StatSwitchApicAccessToR3;
967 STAMCOUNTER StatSwitchPreempt;
968 STAMCOUNTER StatSwitchNstGstVmexit;
969
970 STAMCOUNTER StatTscParavirt;
971 STAMCOUNTER StatTscOffset;
972 STAMCOUNTER StatTscIntercept;
973
974 STAMCOUNTER StatDRxArmed;
975 STAMCOUNTER StatDRxContextSwitch;
976 STAMCOUNTER StatDRxIoCheck;
977
978 STAMCOUNTER StatExportMinimal;
979 STAMCOUNTER StatExportFull;
980 STAMCOUNTER StatLoadGuestFpu;
981 STAMCOUNTER StatExportHostState;
982
983 STAMCOUNTER StatVmxCheckBadRmSelBase;
984 STAMCOUNTER StatVmxCheckBadRmSelLimit;
985 STAMCOUNTER StatVmxCheckBadRmSelAttr;
986 STAMCOUNTER StatVmxCheckBadV86SelBase;
987 STAMCOUNTER StatVmxCheckBadV86SelLimit;
988 STAMCOUNTER StatVmxCheckBadV86SelAttr;
989 STAMCOUNTER StatVmxCheckRmOk;
990 STAMCOUNTER StatVmxCheckBadSel;
991 STAMCOUNTER StatVmxCheckBadRpl;
992 STAMCOUNTER StatVmxCheckPmOk;
993
994 STAMCOUNTER StatVmxPreemptionRecalcingDeadline;
995 STAMCOUNTER StatVmxPreemptionRecalcingDeadlineExpired;
996 STAMCOUNTER StatVmxPreemptionReusingDeadline;
997 STAMCOUNTER StatVmxPreemptionReusingDeadlineExpired;
998
999#ifdef VBOX_WITH_STATISTICS
1000 STAMCOUNTER aStatExitReason[MAX_EXITREASON_STAT];
1001 STAMCOUNTER aStatNestedExitReason[MAX_EXITREASON_STAT];
1002 STAMCOUNTER aStatInjectedIrqs[256];
1003 STAMCOUNTER aStatInjectedXcpts[X86_XCPT_LAST + 1];
1004#endif
1005#ifdef HM_PROFILE_EXIT_DISPATCH
1006 STAMPROFILEADV StatExitDispatch;
1007#endif
1008} HMCPU;
1009/** Pointer to HM VMCPU instance data. */
1010typedef HMCPU *PHMCPU;
1011AssertCompileMemberAlignment(HMCPU, fCheckedTLBFlush, 4);
1012AssertCompileMemberAlignment(HMCPU, fCtxChanged, 8);
1013AssertCompileMemberAlignment(HMCPU, vmx, 8);
1014AssertCompileMemberAlignment(HMCPU, vmx.VmcsInfo, 8);
1015AssertCompileMemberAlignment(HMCPU, vmx.VmcsInfoNstGst, 8);
1016AssertCompileMemberAlignment(HMCPU, svm, 8);
1017AssertCompileMemberAlignment(HMCPU, Event, 8);
1018
1019
1020/**
1021 * HM per-VCpu ring-0 only instance data.
1022 */
1023typedef struct HMR0PERVCPU
1024{
1025 /** World switch exit counter. */
1026 uint32_t volatile cWorldSwitchExits;
1027 /** TLB flush count. */
1028 uint32_t cTlbFlushes;
1029 /** The last CPU we were executing code on (NIL_RTCPUID for the first time). */
1030 RTCPUID idLastCpu;
1031 /** The CPU ID of the CPU currently owning the VMCS. Set in
1032 * HMR0Enter and cleared in HMR0Leave. */
1033 RTCPUID idEnteredCpu;
1034 /** Current ASID in use by the VM. */
1035 uint32_t uCurrentAsid;
1036
1037 /** Set if we need to flush the TLB during the world switch. */
1038 bool fForceTLBFlush;
1039 /** Whether we've completed the inner HM leave function. */
1040 bool fLeaveDone;
1041 /** Whether we're using the hyper DR7 or guest DR7. */
1042 bool fUsingHyperDR7;
1043 /** Whether we are currently executing in the debug loop.
1044 * Mainly for assertions. */
1045 bool fUsingDebugLoop;
1046 /** Set if we using the debug loop and wish to intercept RDTSC. */
1047 bool fDebugWantRdTscExit;
1048 /** Set if XCR0 needs to be saved/restored when entering/exiting guest code
1049 * execution. */
1050 bool fLoadSaveGuestXcr0;
1051 /** Set if we need to clear the trap flag because of single stepping. */
1052 bool fClearTrapFlag;
1053
1054 bool afPadding1[1];
1055 /** World switcher flags (HM_WSF_XXX - was CPUMCTX::fWorldSwitcher in 6.1). */
1056 uint32_t fWorldSwitcher;
1057 /** The raw host TSC value from the last VM exit (set by HMR0A.asm). */
1058 uint64_t uTscExit;
1059
1060 /** VT-x data. */
1061 struct HMR0CPUVMX
1062 {
1063 /** Ring-0 pointer to the hardware-assisted VMX execution function. */
1064 PFNHMVMXSTARTVM pfnStartVm;
1065 /** Absolute TSC deadline. */
1066 uint64_t uTscDeadline;
1067 /** The deadline version number. */
1068 uint64_t uTscDeadlineVersion;
1069
1070 /** @name Guest information.
1071 * @{ */
1072 /** Guest VMCS information. */
1073 VMXVMCSINFO VmcsInfo;
1074 /** Nested-guest VMCS information. */
1075 VMXVMCSINFO VmcsInfoNstGst;
1076 /* Whether the nested-guest VMCS was the last current VMCS (authoritative copy).
1077 * @see HMCPU::vmx.fSwitchedToNstGstVmcsCopyForRing3 */
1078 bool fSwitchedToNstGstVmcs;
1079 bool afAlignment0[7];
1080 /** Pointer to the VMX transient info during VM-exit. */
1081 PVMXTRANSIENT pVmxTransient;
1082 /** @} */
1083
1084 /** @name Host information.
1085 * @{ */
1086 /** Host LSTAR MSR to restore lazily while leaving VT-x. */
1087 uint64_t u64HostMsrLStar;
1088 /** Host STAR MSR to restore lazily while leaving VT-x. */
1089 uint64_t u64HostMsrStar;
1090 /** Host SF_MASK MSR to restore lazily while leaving VT-x. */
1091 uint64_t u64HostMsrSfMask;
1092 /** Host KernelGS-Base MSR to restore lazily while leaving VT-x. */
1093 uint64_t u64HostMsrKernelGsBase;
1094 /** The mask of lazy MSRs swap/restore state, see VMX_LAZY_MSRS_XXX. */
1095 uint32_t fLazyMsrs;
1096 /** Whether the host MSR values are up-to-date in the auto-load/store MSR area. */
1097 bool fUpdatedHostAutoMsrs;
1098 /** Alignment. */
1099 uint8_t au8Alignment0[3];
1100 /** Which host-state bits to restore before being preempted, see
1101 * VMX_RESTORE_HOST_XXX. */
1102 uint32_t fRestoreHostFlags;
1103 /** Alignment. */
1104 uint32_t u32Alignment0;
1105 /** The host-state restoration structure. */
1106 VMXRESTOREHOST RestoreHost;
1107 /** @} */
1108 } vmx;
1109
1110 /** SVM data. */
1111 struct HMR0CPUSVM
1112 {
1113 /** Ring 0 handlers for VT-x. */
1114 PFNHMSVMVMRUN pfnVMRun;
1115
1116 /** Physical address of the host VMCB which holds additional host-state. */
1117 RTHCPHYS HCPhysVmcbHost;
1118 /** R0 memory object for the host VMCB which holds additional host-state. */
1119 RTR0MEMOBJ hMemObjVmcbHost;
1120
1121 /** Physical address of the guest VMCB. */
1122 RTHCPHYS HCPhysVmcb;
1123 /** R0 memory object for the guest VMCB. */
1124 RTR0MEMOBJ hMemObjVmcb;
1125 /** Pointer to the guest VMCB. */
1126 R0PTRTYPE(PSVMVMCB) pVmcb;
1127
1128 /** Physical address of the MSR bitmap (8 KB). */
1129 RTHCPHYS HCPhysMsrBitmap;
1130 /** R0 memory object for the MSR bitmap (8 KB). */
1131 RTR0MEMOBJ hMemObjMsrBitmap;
1132 /** Pointer to the MSR bitmap. */
1133 R0PTRTYPE(void *) pvMsrBitmap;
1134
1135 /** Whether VTPR with V_INTR_MASKING set is in effect, indicating
1136 * we should check if the VTPR changed on every VM-exit. */
1137 bool fSyncVTpr;
1138 bool afAlignment[7];
1139
1140 /** Pointer to the SVM transient info during VM-exit. */
1141 PSVMTRANSIENT pSvmTransient;
1142 /** Host's TSC_AUX MSR (used when RDTSCP doesn't cause VM-exits). */
1143 uint64_t u64HostTscAux;
1144
1145 /** For saving stack space, the disassembler state is allocated here
1146 * instead of on the stack. */
1147 DISCPUSTATE DisState;
1148 } svm;
1149} HMR0PERVCPU;
1150/** Pointer to HM ring-0 VMCPU instance data. */
1151typedef HMR0PERVCPU *PHMR0PERVCPU;
1152AssertCompileMemberAlignment(HMR0PERVCPU, cWorldSwitchExits, 4);
1153AssertCompileMemberAlignment(HMR0PERVCPU, fForceTLBFlush, 4);
1154AssertCompileMemberAlignment(HMR0PERVCPU, vmx.RestoreHost, 8);
1155
1156
1157/** @name HM_WSF_XXX - @bugref{9453}, @bugref{9087}
1158 * @note If you change these values don't forget to update the assembly
1159 * defines as well!
1160 * @{ */
1161/** Touch IA32_PRED_CMD.IBPB on VM exit. */
1162#define HM_WSF_IBPB_EXIT RT_BIT_32(0)
1163/** Touch IA32_PRED_CMD.IBPB on VM entry. */
1164#define HM_WSF_IBPB_ENTRY RT_BIT_32(1)
1165/** Touch IA32_FLUSH_CMD.L1D on VM entry. */
1166#define HM_WSF_L1D_ENTRY RT_BIT_32(2)
1167/** Flush MDS buffers on VM entry. */
1168#define HM_WSF_MDS_ENTRY RT_BIT_32(3)
1169
1170/** Touch IA32_FLUSH_CMD.L1D on VM scheduling. */
1171#define HM_WSF_L1D_SCHED RT_BIT_32(16)
1172/** Flush MDS buffers on VM scheduling. */
1173#define HM_WSF_MDS_SCHED RT_BIT_32(17)
1174/** @} */
1175
1176
1177#ifdef IN_RING0
1178extern bool g_fHmVmxSupported;
1179extern uint32_t g_fHmHostKernelFeatures;
1180extern uint32_t g_uHmMaxAsid;
1181extern bool g_fHmVmxUsePreemptTimer;
1182extern uint8_t g_cHmVmxPreemptTimerShift;
1183extern bool g_fHmVmxSupportsVmcsEfer;
1184extern uint64_t g_uHmVmxHostCr4;
1185extern uint64_t g_uHmVmxHostMsrEfer;
1186extern uint64_t g_uHmVmxHostSmmMonitorCtl;
1187extern bool g_fHmSvmSupported;
1188extern uint32_t g_uHmSvmRev;
1189extern uint32_t g_fHmSvmFeatures;
1190
1191extern SUPHWVIRTMSRS g_HmMsrs;
1192
1193
1194VMMR0_INT_DECL(PHMPHYSCPU) hmR0GetCurrentCpu(void);
1195VMMR0_INT_DECL(int) hmR0EnterCpu(PVMCPUCC pVCpu);
1196
1197# ifdef VBOX_STRICT
1198# define HM_DUMP_REG_FLAGS_GPRS RT_BIT(0)
1199# define HM_DUMP_REG_FLAGS_FPU RT_BIT(1)
1200# define HM_DUMP_REG_FLAGS_MSRS RT_BIT(2)
1201# define HM_DUMP_REG_FLAGS_ALL (HM_DUMP_REG_FLAGS_GPRS | HM_DUMP_REG_FLAGS_FPU | HM_DUMP_REG_FLAGS_MSRS)
1202
1203VMMR0_INT_DECL(void) hmR0DumpRegs(PVMCPUCC pVCpu, uint32_t fFlags);
1204VMMR0_INT_DECL(void) hmR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg);
1205# endif
1206
1207DECLASM(void) hmR0MdsClear(void);
1208#endif /* IN_RING0 */
1209
1210
1211/** @addtogroup grp_hm_int_svm SVM Internal
1212 * @{ */
1213VMM_INT_DECL(int) hmEmulateSvmMovTpr(PVMCC pVM, PVMCPUCC pVCpu);
1214
1215/**
1216 * Prepares for and executes VMRUN (64-bit register context).
1217 *
1218 * @returns VBox status code (no informational stuff).
1219 * @param pVM The cross context VM structure. (Not used.)
1220 * @param pVCpu The cross context virtual CPU structure.
1221 * @param HCPhyspVMCB Physical address of the VMCB.
1222 *
1223 * @remarks With spectre mitigations and the usual need for speed (/ micro
1224 * optimizations), we have a bunch of variations of this code depending
1225 * on a few precoditions. In release builds, the code is entirely
1226 * without conditionals. Debug builds have a couple of assertions that
1227 * shouldn't ever be triggered.
1228 *
1229 * @{
1230 */
1231DECLASM(int) hmR0SvmVmRun_SansXcr0_SansIbpbEntry_SansIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1232DECLASM(int) hmR0SvmVmRun_WithXcr0_SansIbpbEntry_SansIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1233DECLASM(int) hmR0SvmVmRun_SansXcr0_WithIbpbEntry_SansIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1234DECLASM(int) hmR0SvmVmRun_WithXcr0_WithIbpbEntry_SansIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1235DECLASM(int) hmR0SvmVmRun_SansXcr0_SansIbpbEntry_WithIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1236DECLASM(int) hmR0SvmVmRun_WithXcr0_SansIbpbEntry_WithIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1237DECLASM(int) hmR0SvmVmRun_SansXcr0_WithIbpbEntry_WithIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1238DECLASM(int) hmR0SvmVmRun_WithXcr0_WithIbpbEntry_WithIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1239/** @} */
1240
1241/** @} */
1242
1243
1244/** @addtogroup grp_hm_int_vmx VMX Internal
1245 * @{ */
1246VMM_INT_DECL(PVMXVMCSINFOSHARED) hmGetVmxActiveVmcsInfoShared(PVMCPUCC pVCpu);
1247
1248/**
1249 * Used on platforms with poor inline assembly support to retrieve all the
1250 * info from the CPU and put it in the @a pRestoreHost structure.
1251 */
1252DECLASM(void) hmR0VmxExportHostSegmentRegsAsmHlp(PVMXRESTOREHOST pRestoreHost, bool fHaveFsGsBase);
1253
1254/**
1255 * Restores some host-state fields that need not be done on every VM-exit.
1256 *
1257 * @returns VBox status code.
1258 * @param fRestoreHostFlags Flags of which host registers needs to be
1259 * restored.
1260 * @param pRestoreHost Pointer to the host-restore structure.
1261 */
1262DECLASM(int) VMXRestoreHostState(uint32_t fRestoreHostFlags, PVMXRESTOREHOST pRestoreHost);
1263
1264/**
1265 * VMX StartVM functions.
1266 *
1267 * @returns VBox status code (no informational stuff).
1268 * @param pVmcsInfo Pointer to the VMCS info (for cached host RIP and RSP).
1269 * @param pVCpu Pointer to the cross context per-CPU structure of the
1270 * calling EMT.
1271 * @param fResume Whether to use VMRESUME (true) or VMLAUNCH (false).
1272 *
1273 * @remarks With spectre mitigations and the usual need for speed (/ micro
1274 * optimizations), we have a bunch of variations of this code depending
1275 * on a few precoditions. In release builds, the code is entirely
1276 * without conditionals. Debug builds have a couple of assertions that
1277 * shouldn't ever be triggered.
1278 *
1279 * @{
1280 */
1281DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_SansL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1282DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_SansL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1283DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_SansL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1284DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_SansL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1285DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_WithL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1286DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_WithL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1287DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_WithL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1288DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_WithL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1289DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_SansL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1290DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_SansL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1291DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_SansL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1292DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_SansL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1293DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_WithL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1294DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_WithL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1295DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_WithL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1296DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_WithL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1297DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_SansL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1298DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_SansL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1299DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_SansL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1300DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_SansL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1301DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_WithL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1302DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_WithL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1303DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_WithL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1304DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_WithL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1305DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_SansL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1306DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_SansL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1307DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_SansL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1308DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_SansL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1309DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_WithL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1310DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_WithL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1311DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_WithL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1312DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_WithL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1313/** @} */
1314
1315/** @} */
1316
1317/** @} */
1318
1319RT_C_DECLS_END
1320
1321#endif /* !VMM_INCLUDED_SRC_include_HMInternal_h */
1322
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