VirtualBox

source: vbox/trunk/src/VBox/VMM/include/HWACCMInternal.h@ 42044

Last change on this file since 42044 was 42044, checked in by vboxsync, 13 years ago

VMM/HWVMXR0: Fix for acquiring/signaling new ASIDs during host CPU suspend/resumes.
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1/* $Id: HWACCMInternal.h 42044 2012-07-09 06:04:54Z vboxsync $ */
2/** @file
3 * HM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2012 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef ___HWACCMInternal_h
19#define ___HWACCMInternal_h
20
21#include <VBox/cdefs.h>
22#include <VBox/types.h>
23#include <VBox/vmm/em.h>
24#include <VBox/vmm/stam.h>
25#include <VBox/dis.h>
26#include <VBox/vmm/hwaccm.h>
27#include <VBox/vmm/hwacc_vmx.h>
28#include <VBox/vmm/pgm.h>
29#include <VBox/vmm/cpum.h>
30#include <iprt/memobj.h>
31#include <iprt/cpuset.h>
32#include <iprt/mp.h>
33#include <iprt/avl.h>
34
35#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL) || defined (VBOX_WITH_64_BITS_GUESTS)
36/* Enable 64 bits guest support. */
37# define VBOX_ENABLE_64_BITS_GUESTS
38#endif
39
40#define VMX_USE_CACHED_VMCS_ACCESSES
41#define HWACCM_VMX_EMULATE_REALMODE
42
43
44#if 0
45/* Seeing somewhat random behaviour on my Nehalem system with auto-save of guest MSRs;
46 * for some strange reason the CPU doesn't save the MSRs during the VM-exit.
47 * Clearly visible with a dual VCPU configured OpenSolaris 200906 live cd VM.
48 *
49 * Note: change the assembly files when enabling this! (remove the manual auto load/save)
50 */
51#define VBOX_WITH_AUTO_MSR_LOAD_RESTORE
52#endif
53
54RT_C_DECLS_BEGIN
55
56
57/** @defgroup grp_hwaccm_int Internal
58 * @ingroup grp_hwaccm
59 * @internal
60 * @{
61 */
62
63
64/** Maximum number of exit reason statistics counters. */
65#define MAX_EXITREASON_STAT 0x100
66#define MASK_EXITREASON_STAT 0xff
67#define MASK_INJECT_IRQ_STAT 0xff
68
69/** @name Changed flags
70 * These flags are used to keep track of which important registers that
71 * have been changed since last they were reset.
72 * @{
73 */
74#define HWACCM_CHANGED_GUEST_FPU RT_BIT(0)
75#define HWACCM_CHANGED_GUEST_CR0 RT_BIT(1)
76#define HWACCM_CHANGED_GUEST_CR3 RT_BIT(2)
77#define HWACCM_CHANGED_GUEST_CR4 RT_BIT(3)
78#define HWACCM_CHANGED_GUEST_GDTR RT_BIT(4)
79#define HWACCM_CHANGED_GUEST_IDTR RT_BIT(5)
80#define HWACCM_CHANGED_GUEST_LDTR RT_BIT(6)
81#define HWACCM_CHANGED_GUEST_TR RT_BIT(7)
82#define HWACCM_CHANGED_GUEST_MSR RT_BIT(8)
83#define HWACCM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(9)
84#define HWACCM_CHANGED_GUEST_DEBUG RT_BIT(10)
85#define HWACCM_CHANGED_HOST_CONTEXT RT_BIT(11)
86
87#define HWACCM_CHANGED_ALL ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
88 | HWACCM_CHANGED_GUEST_CR0 \
89 | HWACCM_CHANGED_GUEST_CR3 \
90 | HWACCM_CHANGED_GUEST_CR4 \
91 | HWACCM_CHANGED_GUEST_GDTR \
92 | HWACCM_CHANGED_GUEST_IDTR \
93 | HWACCM_CHANGED_GUEST_LDTR \
94 | HWACCM_CHANGED_GUEST_TR \
95 | HWACCM_CHANGED_GUEST_MSR \
96 | HWACCM_CHANGED_GUEST_FPU \
97 | HWACCM_CHANGED_GUEST_DEBUG \
98 | HWACCM_CHANGED_HOST_CONTEXT)
99
100#define HWACCM_CHANGED_ALL_GUEST ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
101 | HWACCM_CHANGED_GUEST_CR0 \
102 | HWACCM_CHANGED_GUEST_CR3 \
103 | HWACCM_CHANGED_GUEST_CR4 \
104 | HWACCM_CHANGED_GUEST_GDTR \
105 | HWACCM_CHANGED_GUEST_IDTR \
106 | HWACCM_CHANGED_GUEST_LDTR \
107 | HWACCM_CHANGED_GUEST_TR \
108 | HWACCM_CHANGED_GUEST_MSR \
109 | HWACCM_CHANGED_GUEST_DEBUG \
110 | HWACCM_CHANGED_GUEST_FPU)
111
112/** @} */
113
114/** Maximum number of page flushes we are willing to remember before considering a full TLB flush. */
115#define HWACCM_MAX_TLB_SHOOTDOWN_PAGES 8
116
117/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
118#define HWACCM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
119/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
120#define HWACCM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2*PAGE_SIZE + 1)
121/** Total guest mapped memory needed. */
122#define HWACCM_VTX_TOTAL_DEVHEAP_MEM (HWACCM_EPT_IDENTITY_PG_TABLE_SIZE + HWACCM_VTX_TSS_SIZE)
123
124/** Enable for TPR guest patching. */
125#define VBOX_HWACCM_WITH_GUEST_PATCHING
126
127/** HWACCM SSM version
128 */
129#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
130# define HWACCM_SSM_VERSION 5
131# define HWACCM_SSM_VERSION_NO_PATCHING 4
132#else
133# define HWACCM_SSM_VERSION 4
134# define HWACCM_SSM_VERSION_NO_PATCHING 4
135#endif
136#define HWACCM_SSM_VERSION_2_0_X 3
137
138/**
139 * Global per-cpu information. (host)
140 */
141typedef struct HMGLOBLCPUINFO
142{
143 /** The CPU ID. */
144 RTCPUID idCpu;
145 /** The memory object */
146 RTR0MEMOBJ hMemObj;
147 /** Current ASID (AMD-V) / VPID (Intel). */
148 uint32_t uCurrentASID;
149 /** TLB flush count. */
150 uint32_t cTLBFlushes;
151 /** Whether to flush each new ASID/VPID before use. */
152 bool fFlushASIDBeforeUse;
153 /** Configured for VT-x or AMD-V. */
154 bool fConfigured;
155 /** Set if the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active. */
156 bool fIgnoreAMDVInUseError;
157 /** In use by our code. (for power suspend) */
158 volatile bool fInUse;
159 /** Toggle bit for signaling new ASIDs (during suspend/resume) */
160 bool fASIDState;
161} HMGLOBLCPUINFO;
162/** Pointer to the per-cpu global information. */
163typedef HMGLOBLCPUINFO *PHMGLOBLCPUINFO;
164
165typedef enum
166{
167 HWACCMPENDINGIO_INVALID = 0,
168 HWACCMPENDINGIO_PORT_READ,
169 HWACCMPENDINGIO_PORT_WRITE,
170 HWACCMPENDINGIO_STRING_READ,
171 HWACCMPENDINGIO_STRING_WRITE,
172 /** The usual 32-bit paranoia. */
173 HWACCMPENDINGIO_32BIT_HACK = 0x7fffffff
174} HWACCMPENDINGIO;
175
176
177typedef enum
178{
179 HWACCMTPRINSTR_INVALID,
180 HWACCMTPRINSTR_READ,
181 HWACCMTPRINSTR_READ_SHR4,
182 HWACCMTPRINSTR_WRITE_REG,
183 HWACCMTPRINSTR_WRITE_IMM,
184 HWACCMTPRINSTR_JUMP_REPLACEMENT,
185 /** The usual 32-bit paranoia. */
186 HWACCMTPRINSTR_32BIT_HACK = 0x7fffffff
187} HWACCMTPRINSTR;
188
189typedef struct
190{
191 /** The key is the address of patched instruction. (32 bits GC ptr) */
192 AVLOU32NODECORE Core;
193 /** Original opcode. */
194 uint8_t aOpcode[16];
195 /** Instruction size. */
196 uint32_t cbOp;
197 /** Replacement opcode. */
198 uint8_t aNewOpcode[16];
199 /** Replacement instruction size. */
200 uint32_t cbNewOp;
201 /** Instruction type. */
202 HWACCMTPRINSTR enmType;
203 /** Source operand. */
204 uint32_t uSrcOperand;
205 /** Destination operand. */
206 uint32_t uDstOperand;
207 /** Number of times the instruction caused a fault. */
208 uint32_t cFaults;
209 /** Patch address of the jump replacement. */
210 RTGCPTR32 pJumpTarget;
211} HWACCMTPRPATCH;
212/** Pointer to HWACCMTPRPATCH. */
213typedef HWACCMTPRPATCH *PHWACCMTPRPATCH;
214
215/**
216 * Switcher function, HC to RC.
217 *
218 * @param pVM Pointer to the VM.
219 * @param uOffsetVMCPU VMCPU offset from pVM
220 * @returns Return code indicating the action to take.
221 */
222typedef DECLCALLBACK (int) FNHWACCMSWITCHERHC(PVM pVM, uint32_t uOffsetVMCPU);
223/** Pointer to switcher function. */
224typedef FNHWACCMSWITCHERHC *PFNHWACCMSWITCHERHC;
225
226/**
227 * HWACCM VM Instance data.
228 * Changes to this must checked against the padding of the hwaccm union in VM!
229 */
230typedef struct HWACCM
231{
232 /** Set when we've initialized VMX or SVM. */
233 bool fInitialized;
234
235 /** Set when hardware acceleration is allowed. */
236 bool fAllowed;
237
238 /** Set if nested paging is enabled. */
239 bool fNestedPaging;
240
241 /** Set if nested paging is allowed. */
242 bool fAllowNestedPaging;
243
244 /** Set if large pages are enabled (requires nested paging). */
245 bool fLargePages;
246
247 /** Set if we can support 64-bit guests or not. */
248 bool fAllow64BitGuests;
249
250 /** Set if an IO-APIC is configured for this VM. */
251 bool fHasIoApic;
252
253 /** Set when TPR patching is allowed. */
254 bool fTRPPatchingAllowed;
255
256 /** Set when we initialize VT-x or AMD-V once for all CPUs. */
257 bool fGlobalInit;
258
259 /** Set when TPR patching is active. */
260 bool fTPRPatchingActive;
261 bool u8Alignment[6];
262
263 /** And mask for copying register contents. */
264 uint64_t u64RegisterMask;
265
266 /** Maximum ASID allowed. */
267 uint32_t uMaxASID;
268
269 /** The maximum number of resumes loops allowed in ring-0 (safety precaution).
270 * This number is set much higher when RTThreadPreemptIsPending is reliable. */
271 uint32_t cMaxResumeLoops;
272
273 /** Guest allocated memory for patching purposes. */
274 RTGCPTR pGuestPatchMem;
275 /** Current free pointer inside the patch block. */
276 RTGCPTR pFreeGuestPatchMem;
277 /** Size of the guest patch memory block. */
278 uint32_t cbGuestPatchMem;
279 uint32_t uPadding1;
280
281#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
282 /** 32 to 64 bits switcher entrypoint. */
283 R0PTRTYPE(PFNHWACCMSWITCHERHC) pfnHost32ToGuest64R0;
284
285 /* AMD-V 64 bits vmrun handler */
286 RTRCPTR pfnSVMGCVMRun64;
287
288 /* VT-x 64 bits vmlaunch handler */
289 RTRCPTR pfnVMXGCStartVM64;
290
291 /* RC handler to setup the 64 bits FPU state. */
292 RTRCPTR pfnSaveGuestFPU64;
293
294 /* RC handler to setup the 64 bits debug state. */
295 RTRCPTR pfnSaveGuestDebug64;
296
297 /* Test handler */
298 RTRCPTR pfnTest64;
299
300 RTRCPTR uAlignment[2];
301/*#elif defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
302 uint32_t u32Alignment[1]; */
303#endif
304
305 struct
306 {
307 /** Set by the ring-0 side of HWACCM to indicate VMX is supported by the
308 * CPU. */
309 bool fSupported;
310
311 /** Set when we've enabled VMX. */
312 bool fEnabled;
313
314 /** Set if VPID is supported. */
315 bool fVPID;
316
317 /** Set if VT-x VPID is allowed. */
318 bool fAllowVPID;
319
320 /** Set if unrestricted guest execution is allowed (real and protected mode without paging). */
321 bool fUnrestrictedGuest;
322
323 /** Whether we're using the preemption timer or not. */
324 bool fUsePreemptTimer;
325 /** The shift mask employed by the VMX-Preemption timer. */
326 uint8_t cPreemptTimerShift;
327
328 bool uAlignment[1];
329
330 /** Virtual address of the TSS page used for real mode emulation. */
331 R3PTRTYPE(PVBOXTSS) pRealModeTSS;
332
333 /** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
334 R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
335
336 /** R0 memory object for the APIC physical page (serves for filtering accesses). */
337 RTR0MEMOBJ pMemObjAPIC;
338 /** Physical address of the APIC physical page (serves for filtering accesses). */
339 RTHCPHYS pAPICPhys;
340 /** Virtual address of the APIC physical page (serves for filtering accesses). */
341 R0PTRTYPE(uint8_t *) pAPIC;
342
343 /** R0 memory object for the MSR entry load page (guest MSRs). */
344 RTR0MEMOBJ pMemObjMSREntryLoad;
345 /** Physical address of the MSR entry load page (guest MSRs). */
346 RTHCPHYS pMSREntryLoadPhys;
347 /** Virtual address of the MSR entry load page (guest MSRs). */
348 R0PTRTYPE(uint8_t *) pMSREntryLoad;
349
350#ifdef VBOX_WITH_CRASHDUMP_MAGIC
351 RTR0MEMOBJ pMemObjScratch;
352 RTHCPHYS pScratchPhys;
353 R0PTRTYPE(uint8_t *) pScratch;
354#endif
355 /** R0 memory object for the MSR exit store page (guest MSRs). */
356 RTR0MEMOBJ pMemObjMSRExitStore;
357 /** Physical address of the MSR exit store page (guest MSRs). */
358 RTHCPHYS pMSRExitStorePhys;
359 /** Virtual address of the MSR exit store page (guest MSRs). */
360 R0PTRTYPE(uint8_t *) pMSRExitStore;
361
362 /** R0 memory object for the MSR exit load page (host MSRs). */
363 RTR0MEMOBJ pMemObjMSRExitLoad;
364 /** Physical address of the MSR exit load page (host MSRs). */
365 RTHCPHYS pMSRExitLoadPhys;
366 /** Virtual address of the MSR exit load page (host MSRs). */
367 R0PTRTYPE(uint8_t *) pMSRExitLoad;
368
369 /** Ring 0 handlers for VT-x. */
370 DECLR0CALLBACKMEMBER(void, pfnSetupTaggedTLB, (PVM pVM, PVMCPU pVCpu));
371
372#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
373 uint32_t u32Alignment;
374#endif
375 /** Host CR4 value (set by ring-0 VMX init) */
376 uint64_t hostCR4;
377
378 /** Host EFER value (set by ring-0 VMX init) */
379 uint64_t hostEFER;
380
381 /** VMX MSR values */
382 struct
383 {
384 uint64_t feature_ctrl;
385 uint64_t vmx_basic_info;
386 VMX_CAPABILITY vmx_pin_ctls;
387 VMX_CAPABILITY vmx_proc_ctls;
388 VMX_CAPABILITY vmx_proc_ctls2;
389 VMX_CAPABILITY vmx_exit;
390 VMX_CAPABILITY vmx_entry;
391 uint64_t vmx_misc;
392 uint64_t vmx_cr0_fixed0;
393 uint64_t vmx_cr0_fixed1;
394 uint64_t vmx_cr4_fixed0;
395 uint64_t vmx_cr4_fixed1;
396 uint64_t vmx_vmcs_enum;
397 uint64_t vmx_eptcaps;
398 } msr;
399
400 /** Flush types for invept & invvpid; they depend on capabilities. */
401 VMX_FLUSH_EPT enmFlushEPT;
402 VMX_FLUSH_VPID enmFlushVPID;
403 } vmx;
404
405 struct
406 {
407 /** Set by the ring-0 side of HWACCM to indicate SVM is supported by the
408 * CPU. */
409 bool fSupported;
410 /** Set when we've enabled SVM. */
411 bool fEnabled;
412 /** Set if erratum 170 affects the AMD cpu. */
413 bool fAlwaysFlushTLB;
414 /** Set when the hack to ignore VERR_SVM_IN_USE is active. */
415 bool fIgnoreInUseError;
416
417 /** R0 memory object for the IO bitmap (12kb). */
418 RTR0MEMOBJ pMemObjIOBitmap;
419 /** Physical address of the IO bitmap (12kb). */
420 RTHCPHYS pIOBitmapPhys;
421 /** Virtual address of the IO bitmap. */
422 R0PTRTYPE(void *) pIOBitmap;
423
424 /* HWCR msr (for diagnostics) */
425 uint64_t msrHWCR;
426
427 /** SVM revision. */
428 uint32_t u32Rev;
429
430 /** SVM feature bits from cpuid 0x8000000a */
431 uint32_t u32Features;
432 } svm;
433
434 /**
435 * AVL tree with all patches (active or disabled) sorted by guest instruction address
436 */
437 AVLOU32TREE PatchTree;
438 uint32_t cPatches;
439 HWACCMTPRPATCH aPatches[64];
440
441 struct
442 {
443 uint32_t u32AMDFeatureECX;
444 uint32_t u32AMDFeatureEDX;
445 } cpuid;
446
447 /** Saved error from detection */
448 int32_t lLastError;
449
450 /** HWACCMR0Init was run */
451 bool fHWACCMR0Init;
452 bool u8Alignment1[7];
453
454 STAMCOUNTER StatTPRPatchSuccess;
455 STAMCOUNTER StatTPRPatchFailure;
456 STAMCOUNTER StatTPRReplaceSuccess;
457 STAMCOUNTER StatTPRReplaceFailure;
458} HWACCM;
459/** Pointer to HWACCM VM instance data. */
460typedef HWACCM *PHWACCM;
461
462/* Maximum number of cached entries. */
463#define VMCSCACHE_MAX_ENTRY 128
464
465/* Structure for storing read and write VMCS actions. */
466typedef struct VMCSCACHE
467{
468#ifdef VBOX_WITH_CRASHDUMP_MAGIC
469 /* Magic marker for searching in crash dumps. */
470 uint8_t aMagic[16];
471 uint64_t uMagic;
472 uint64_t u64TimeEntry;
473 uint64_t u64TimeSwitch;
474 uint64_t cResume;
475 uint64_t interPD;
476 uint64_t pSwitcher;
477 uint32_t uPos;
478 uint32_t idCpu;
479#endif
480 /* CR2 is saved here for EPT syncing. */
481 uint64_t cr2;
482 struct
483 {
484 uint32_t cValidEntries;
485 uint32_t uAlignment;
486 uint32_t aField[VMCSCACHE_MAX_ENTRY];
487 uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
488 } Write;
489 struct
490 {
491 uint32_t cValidEntries;
492 uint32_t uAlignment;
493 uint32_t aField[VMCSCACHE_MAX_ENTRY];
494 uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
495 } Read;
496#ifdef DEBUG
497 struct
498 {
499 RTHCPHYS HCPhysCpuPage;
500 RTHCPHYS HCPhysVMCS;
501 RTGCPTR pCache;
502 RTGCPTR pCtx;
503 } TestIn;
504 struct
505 {
506 RTHCPHYS HCPhysVMCS;
507 RTGCPTR pCache;
508 RTGCPTR pCtx;
509 uint64_t eflags;
510 uint64_t cr8;
511 } TestOut;
512 struct
513 {
514 uint64_t param1;
515 uint64_t param2;
516 uint64_t param3;
517 uint64_t param4;
518 } ScratchPad;
519#endif
520} VMCSCACHE;
521/** Pointer to VMCSCACHE. */
522typedef VMCSCACHE *PVMCSCACHE;
523
524/** VMX StartVM function. */
525typedef DECLCALLBACK(int) FNHWACCMVMXSTARTVM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);
526/** Pointer to a VMX StartVM function. */
527typedef R0PTRTYPE(FNHWACCMVMXSTARTVM *) PFNHWACCMVMXSTARTVM;
528
529/** SVM VMRun function. */
530typedef DECLCALLBACK(int) FNHWACCMSVMVMRUN(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu);
531/** Pointer to a SVM VMRun function. */
532typedef R0PTRTYPE(FNHWACCMSVMVMRUN *) PFNHWACCMSVMVMRUN;
533
534/**
535 * HWACCM VMCPU Instance data.
536 */
537typedef struct HWACCMCPU
538{
539 /** Old style FPU reporting trap mask override performed (optimization) */
540 bool fFPUOldStyleOverride;
541
542 /** Set if we don't have to flush the TLB on VM entry. */
543 bool fResumeVM;
544
545 /** Set if we need to flush the TLB during the world switch. */
546 bool fForceTLBFlush;
547
548 /** Toggle bit for acquiring a new ASID (during host CPU suspend/resume) */
549 bool fASIDState;
550
551 /** Set when we're using VT-x or AMD-V at that moment. */
552 bool fActive;
553
554 /** Set when the TLB has been checked until we return from the world switch. */
555 volatile bool fCheckedTLBFlush;
556 uint8_t bAlignment[2];
557
558 /** World switch exit counter. */
559 volatile uint32_t cWorldSwitchExits;
560
561 /** HWACCM_CHANGED_* flags. */
562 uint32_t fContextUseFlags;
563
564 /** Id of the last cpu we were executing code on (NIL_RTCPUID for the first time) */
565 RTCPUID idLastCpu;
566
567 /** TLB flush count */
568 uint32_t cTLBFlushes;
569
570 /** Current ASID in use by the VM */
571 uint32_t uCurrentASID;
572
573 uint32_t u32Alignment;
574
575 struct
576 {
577 /** Physical address of the VM control structure (VMCS). */
578 RTHCPHYS HCPhysVMCS;
579 /** R0 memory object for the VM control structure (VMCS). */
580 RTR0MEMOBJ hMemObjVMCS;
581 /** Virtual address of the VM control structure (VMCS). */
582 R0PTRTYPE(void *) pvVMCS;
583
584 /** Ring 0 handlers for VT-x. */
585 PFNHWACCMVMXSTARTVM pfnStartVM;
586
587#if HC_ARCH_BITS == 32
588 uint32_t u32Alignment;
589#endif
590
591 /** Current VMX_VMCS_CTRL_PROC_EXEC_CONTROLS. */
592 uint64_t proc_ctls;
593
594 /** Current VMX_VMCS_CTRL_PROC_EXEC2_CONTROLS. */
595 uint64_t proc_ctls2;
596
597 /** Physical address of the virtual APIC page for TPR caching. */
598 RTHCPHYS HCPhysVAPIC;
599 /** R0 memory object for the virtual APIC page for TPR caching. */
600 RTR0MEMOBJ hMemObjVAPIC;
601 /** Virtual address of the virtual APIC page for TPR caching. */
602 R0PTRTYPE(uint8_t *) pbVAPIC;
603
604 /** Current CR0 mask. */
605 uint64_t cr0_mask;
606 /** Current CR4 mask. */
607 uint64_t cr4_mask;
608
609 /** Current EPTP. */
610 RTHCPHYS GCPhysEPTP;
611
612 /** Physical address of the MSR bitmap (1 page). */
613 RTHCPHYS pMSRBitmapPhys;
614 /** R0 memory object for the MSR bitmap (1 page). */
615 RTR0MEMOBJ pMemObjMSRBitmap;
616 /** Virtual address of the MSR bitmap (1 page). */
617 R0PTRTYPE(uint8_t *) pMSRBitmap;
618
619#ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
620 /** Physical address of the guest MSR load area (1 page). */
621 RTHCPHYS pGuestMSRPhys;
622 /** R0 memory object for the guest MSR load area (1 page). */
623 RTR0MEMOBJ pMemObjGuestMSR;
624 /** Virtual address of the guest MSR load area (1 page). */
625 R0PTRTYPE(uint8_t *) pGuestMSR;
626
627 /** Physical address of the MSR load area (1 page). */
628 RTHCPHYS pHostMSRPhys;
629 /** R0 memory object for the MSR load area (1 page). */
630 RTR0MEMOBJ pMemObjHostMSR;
631 /** Virtual address of the MSR load area (1 page). */
632 R0PTRTYPE(uint8_t *) pHostMSR;
633#endif /* VBOX_WITH_AUTO_MSR_LOAD_RESTORE */
634
635 /* Number of automatically loaded/restored MSRs. */
636 uint32_t cCachedMSRs;
637 uint32_t uAlignement;
638
639 /* Last use TSC offset value. (cached) */
640 uint64_t u64TSCOffset;
641
642 /** VMCS cache. */
643 VMCSCACHE VMCSCache;
644
645 /** Real-mode emulation state. */
646 struct
647 {
648 X86EFLAGS eflags;
649 uint32_t fValid;
650 } RealMode;
651
652 struct
653 {
654 uint64_t u64VMCSPhys;
655 uint32_t ulVMCSRevision;
656 uint32_t ulInstrError;
657 uint32_t ulExitReason;
658 RTCPUID idEnteredCpu;
659 RTCPUID idCurrentCpu;
660 uint32_t padding;
661 } lasterror;
662
663 /** The last seen guest paging mode (by VT-x). */
664 PGMMODE enmLastSeenGuestMode;
665 /** Current guest paging mode (as seen by HWACCMR3PagingModeChanged). */
666 PGMMODE enmCurrGuestMode;
667 /** Previous guest paging mode (as seen by HWACCMR3PagingModeChanged). */
668 PGMMODE enmPrevGuestMode;
669 } vmx;
670
671 struct
672 {
673 /** R0 memory object for the host VM control block (VMCB). */
674 RTR0MEMOBJ pMemObjVMCBHost;
675 /** Physical address of the host VM control block (VMCB). */
676 RTHCPHYS pVMCBHostPhys;
677 /** Virtual address of the host VM control block (VMCB). */
678 R0PTRTYPE(void *) pVMCBHost;
679
680 /** R0 memory object for the VM control block (VMCB). */
681 RTR0MEMOBJ pMemObjVMCB;
682 /** Physical address of the VM control block (VMCB). */
683 RTHCPHYS pVMCBPhys;
684 /** Virtual address of the VM control block (VMCB). */
685 R0PTRTYPE(void *) pVMCB;
686
687 /** Ring 0 handlers for VT-x. */
688 PFNHWACCMSVMVMRUN pfnVMRun;
689
690 /** R0 memory object for the MSR bitmap (8kb). */
691 RTR0MEMOBJ pMemObjMSRBitmap;
692 /** Physical address of the MSR bitmap (8kb). */
693 RTHCPHYS pMSRBitmapPhys;
694 /** Virtual address of the MSR bitmap. */
695 R0PTRTYPE(void *) pMSRBitmap;
696 } svm;
697
698 /** Event injection state. */
699 struct
700 {
701 uint32_t fPending;
702 uint32_t errCode;
703 uint64_t intInfo;
704 } Event;
705
706 /** IO Block emulation state. */
707 struct
708 {
709 bool fEnabled;
710 uint8_t u8Align[7];
711
712 /** RIP at the start of the io code we wish to emulate in the recompiler. */
713 RTGCPTR GCPtrFunctionEip;
714
715 uint64_t cr0;
716 } EmulateIoBlock;
717
718 struct
719 {
720 /* Pending IO operation type. */
721 HWACCMPENDINGIO enmType;
722 uint32_t uPadding;
723 RTGCPTR GCPtrRip;
724 RTGCPTR GCPtrRipNext;
725 union
726 {
727 struct
728 {
729 unsigned uPort;
730 unsigned uAndVal;
731 unsigned cbSize;
732 } Port;
733 uint64_t aRaw[2];
734 } s;
735 } PendingIO;
736
737 /** Currently shadow paging mode. */
738 PGMMODE enmShadowMode;
739
740 /** The CPU ID of the CPU currently owning the VMCS. Set in
741 * HWACCMR0Enter and cleared in HWACCMR0Leave. */
742 RTCPUID idEnteredCpu;
743
744 /** To keep track of pending TLB shootdown pages. (SMP guest only) */
745 struct
746 {
747 RTGCPTR aPages[HWACCM_MAX_TLB_SHOOTDOWN_PAGES];
748 unsigned cPages;
749 } TlbShootdown;
750
751 /** For saving stack space, the disassembler state is allocated here instead of
752 * on the stack. */
753 DISCPUSTATE DisState;
754
755 uint32_t padding2[1];
756
757 STAMPROFILEADV StatEntry;
758 STAMPROFILEADV StatExit1;
759 STAMPROFILEADV StatExit2;
760#if 1 /* temporary for tracking down darwin issues. */
761 STAMPROFILEADV StatExit2Sub1;
762 STAMPROFILEADV StatExit2Sub2;
763 STAMPROFILEADV StatExit2Sub3;
764#endif
765 STAMPROFILEADV StatInGC;
766
767#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
768 STAMPROFILEADV StatWorldSwitch3264;
769#endif
770 STAMPROFILEADV StatPoke;
771 STAMPROFILEADV StatSpinPoke;
772 STAMPROFILEADV StatSpinPokeFailed;
773
774 STAMCOUNTER StatIntInject;
775
776 STAMCOUNTER StatExitShadowNM;
777 STAMCOUNTER StatExitGuestNM;
778 STAMCOUNTER StatExitShadowPF;
779 STAMCOUNTER StatExitShadowPFEM;
780 STAMCOUNTER StatExitGuestPF;
781 STAMCOUNTER StatExitGuestUD;
782 STAMCOUNTER StatExitGuestSS;
783 STAMCOUNTER StatExitGuestNP;
784 STAMCOUNTER StatExitGuestGP;
785 STAMCOUNTER StatExitGuestDE;
786 STAMCOUNTER StatExitGuestDB;
787 STAMCOUNTER StatExitGuestMF;
788 STAMCOUNTER StatExitGuestBP;
789 STAMCOUNTER StatExitGuestXF;
790 STAMCOUNTER StatExitGuestXcpUnk;
791 STAMCOUNTER StatExitInvpg;
792 STAMCOUNTER StatExitInvd;
793 STAMCOUNTER StatExitCpuid;
794 STAMCOUNTER StatExitRdtsc;
795 STAMCOUNTER StatExitRdtscp;
796 STAMCOUNTER StatExitRdpmc;
797 STAMCOUNTER StatExitCli;
798 STAMCOUNTER StatExitSti;
799 STAMCOUNTER StatExitPushf;
800 STAMCOUNTER StatExitPopf;
801 STAMCOUNTER StatExitIret;
802 STAMCOUNTER StatExitInt;
803 STAMCOUNTER StatExitCRxWrite[16];
804 STAMCOUNTER StatExitCRxRead[16];
805 STAMCOUNTER StatExitDRxWrite;
806 STAMCOUNTER StatExitDRxRead;
807 STAMCOUNTER StatExitRdmsr;
808 STAMCOUNTER StatExitWrmsr;
809 STAMCOUNTER StatExitCLTS;
810 STAMCOUNTER StatExitHlt;
811 STAMCOUNTER StatExitMwait;
812 STAMCOUNTER StatExitMonitor;
813 STAMCOUNTER StatExitLMSW;
814 STAMCOUNTER StatExitIOWrite;
815 STAMCOUNTER StatExitIORead;
816 STAMCOUNTER StatExitIOStringWrite;
817 STAMCOUNTER StatExitIOStringRead;
818 STAMCOUNTER StatExitIrqWindow;
819 STAMCOUNTER StatExitMaxResume;
820 STAMCOUNTER StatExitPreemptPending;
821 STAMCOUNTER StatExitMTF;
822 STAMCOUNTER StatIntReinject;
823 STAMCOUNTER StatPendingHostIrq;
824
825 STAMCOUNTER StatFlushPage;
826 STAMCOUNTER StatFlushPageManual;
827 STAMCOUNTER StatFlushPhysPageManual;
828 STAMCOUNTER StatFlushTLB;
829 STAMCOUNTER StatFlushTLBManual;
830 STAMCOUNTER StatFlushPageInvlpg;
831 STAMCOUNTER StatFlushTLBWorldSwitch;
832 STAMCOUNTER StatNoFlushTLBWorldSwitch;
833 STAMCOUNTER StatFlushTLBCRxChange;
834 STAMCOUNTER StatFlushASID;
835 STAMCOUNTER StatFlushTLBInvlpga;
836 STAMCOUNTER StatTlbShootdown;
837 STAMCOUNTER StatTlbShootdownFlush;
838
839 STAMCOUNTER StatSwitchGuestIrq;
840 STAMCOUNTER StatSwitchToR3;
841
842 STAMCOUNTER StatTSCOffset;
843 STAMCOUNTER StatTSCIntercept;
844 STAMCOUNTER StatTSCInterceptOverFlow;
845
846 STAMCOUNTER StatExitReasonNPF;
847 STAMCOUNTER StatDRxArmed;
848 STAMCOUNTER StatDRxContextSwitch;
849 STAMCOUNTER StatDRxIOCheck;
850
851 STAMCOUNTER StatLoadMinimal;
852 STAMCOUNTER StatLoadFull;
853
854#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
855 STAMCOUNTER StatFpu64SwitchBack;
856 STAMCOUNTER StatDebug64SwitchBack;
857#endif
858
859#ifdef VBOX_WITH_STATISTICS
860 R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
861 R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
862 R3PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqs;
863 R0PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqsR0;
864#endif
865} HWACCMCPU;
866/** Pointer to HWACCM VM instance data. */
867typedef HWACCMCPU *PHWACCMCPU;
868
869
870#ifdef IN_RING0
871
872VMMR0DECL(PHMGLOBLCPUINFO) HWACCMR0GetCurrentCpu(void);
873VMMR0DECL(PHMGLOBLCPUINFO) HWACCMR0GetCurrentCpuEx(RTCPUID idCpu);
874
875
876#ifdef VBOX_STRICT
877VMMR0DECL(void) HWACCMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
878VMMR0DECL(void) HWACCMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg);
879#else
880# define HWACCMDumpRegs(a, b ,c) do { } while (0)
881# define HWACCMR0DumpDescriptor(a, b, c) do { } while (0)
882#endif
883
884# ifdef VBOX_WITH_KERNEL_USING_XMM
885DECLASM(int) hwaccmR0VMXStartVMWrapXMM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu, PFNHWACCMVMXSTARTVM pfnStartVM);
886DECLASM(int) hwaccmR0SVMRunWrapXMM(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu, PFNHWACCMSVMVMRUN pfnVMRun);
887# endif
888
889# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
890/**
891 * Gets 64-bit GDTR and IDTR on darwin.
892 * @param pGdtr Where to store the 64-bit GDTR.
893 * @param pIdtr Where to store the 64-bit IDTR.
894 */
895DECLASM(void) hwaccmR0Get64bitGDTRandIDTR(PX86XDTR64 pGdtr, PX86XDTR64 pIdtr);
896
897/**
898 * Gets 64-bit CR3 on darwin.
899 * @returns CR3
900 */
901DECLASM(uint64_t) hwaccmR0Get64bitCR3(void);
902# endif
903
904#endif /* IN_RING0 */
905
906/** @} */
907
908RT_C_DECLS_END
909
910#endif
911
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