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source: vbox/trunk/src/VBox/VMM/include/IEMInternal-armv8.h@ 104881

Last change on this file since 104881 was 100966, checked in by vboxsync, 15 months ago

VMM/PGM,IEM: Prepare work for write monitoring page containing recompiled code. bugref:10369
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1/* $Id: IEMInternal-armv8.h 100966 2023-08-24 23:23:58Z vboxsync $ */
2/** @file
3 * IEM - Internal header file, ARMv8 variant.
4 */
5
6/*
7 * Copyright (C) 2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VMM_INCLUDED_SRC_include_IEMInternal_armv8_h
29#define VMM_INCLUDED_SRC_include_IEMInternal_armv8_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34#include <VBox/vmm/cpum.h>
35#include <VBox/vmm/iem.h>
36#include <VBox/vmm/pgm.h>
37#include <VBox/vmm/stam.h>
38#include <VBox/param.h>
39
40#include <iprt/setjmp-without-sigmask.h>
41
42
43RT_C_DECLS_BEGIN
44
45
46/** @defgroup grp_iem_int Internals
47 * @ingroup grp_iem
48 * @internal
49 * @{
50 */
51
52/** For expanding symbol in slickedit and other products tagging and
53 * crossreferencing IEM symbols. */
54#ifndef IEM_STATIC
55# define IEM_STATIC static
56#endif
57
58/** @def IEM_WITH_SETJMP
59 * Enables alternative status code handling using setjmps.
60 *
61 * This adds a bit of expense via the setjmp() call since it saves all the
62 * non-volatile registers. However, it eliminates return code checks and allows
63 * for more optimal return value passing (return regs instead of stack buffer).
64 */
65#if defined(DOXYGEN_RUNNING) || defined(RT_OS_WINDOWS) || 1
66# define IEM_WITH_SETJMP
67#endif
68
69/** @def IEM_WITH_THROW_CATCH
70 * Enables using C++ throw/catch as an alternative to setjmp/longjmp in user
71 * mode code when IEM_WITH_SETJMP is in effect.
72 *
73 * With GCC 11.3.1 and code TLB on linux, using throw/catch instead of
74 * setjmp/long resulted in bs2-test-1 running 3.00% faster and all but on test
75 * result value improving by more than 1%. (Best out of three.)
76 *
77 * With Visual C++ 2019 and code TLB on windows, using throw/catch instead of
78 * setjmp/long resulted in bs2-test-1 running 3.68% faster and all but some of
79 * the MMIO and CPUID tests ran noticeably faster. Variation is greater than on
80 * Linux, but it should be quite a bit faster for normal code.
81 */
82#if (defined(IEM_WITH_SETJMP) && defined(IN_RING3) && (defined(__GNUC__) || defined(_MSC_VER))) \
83 || defined(DOXYGEN_RUNNING)
84# define IEM_WITH_THROW_CATCH
85#endif
86
87/** @def IEM_DO_LONGJMP
88 *
89 * Wrapper around longjmp / throw.
90 *
91 * @param a_pVCpu The CPU handle.
92 * @param a_rc The status code jump back with / throw.
93 */
94#if defined(IEM_WITH_SETJMP) || defined(DOXYGEN_RUNNING)
95# ifdef IEM_WITH_THROW_CATCH
96# define IEM_DO_LONGJMP(a_pVCpu, a_rc) throw int(a_rc)
97# else
98# define IEM_DO_LONGJMP(a_pVCpu, a_rc) longjmp(*(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf), (a_rc))
99# endif
100#endif
101
102/** For use with IEM function that may do a longjmp (when enabled).
103 *
104 * Visual C++ has trouble longjmp'ing from/over functions with the noexcept
105 * attribute. So, we indicate that function that may be part of a longjmp may
106 * throw "exceptions" and that the compiler should definitely not generate and
107 * std::terminate calling unwind code.
108 *
109 * Here is one example of this ending in std::terminate:
110 * @code{.txt}
11100 00000041`cadfda10 00007ffc`5d5a1f9f ucrtbase!abort+0x4e
11201 00000041`cadfda40 00007ffc`57af229a ucrtbase!terminate+0x1f
11302 00000041`cadfda70 00007ffb`eec91030 VCRUNTIME140!__std_terminate+0xa [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\ehhelpers.cpp @ 192]
11403 00000041`cadfdaa0 00007ffb`eec92c6d VCRUNTIME140_1!_CallSettingFrame+0x20 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\handlers.asm @ 50]
11504 00000041`cadfdad0 00007ffb`eec93ae5 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToState+0x241 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 1085]
11605 00000041`cadfdc00 00007ffb`eec92258 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToEmptyState+0x2d [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 218]
11706 00000041`cadfdc30 00007ffb`eec940e9 VCRUNTIME140_1!__InternalCxxFrameHandler<__FrameHandler4>+0x194 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 304]
11807 00000041`cadfdcd0 00007ffc`5f9f249f VCRUNTIME140_1!__CxxFrameHandler4+0xa9 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 290]
11908 00000041`cadfdd40 00007ffc`5f980939 ntdll!RtlpExecuteHandlerForUnwind+0xf
12009 00000041`cadfdd70 00007ffc`5f9a0edd ntdll!RtlUnwindEx+0x339
1210a 00000041`cadfe490 00007ffc`57aff976 ntdll!RtlUnwind+0xcd
1220b 00000041`cadfea00 00007ffb`e1b5de01 VCRUNTIME140!__longjmp_internal+0xe6 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\longjmp.asm @ 140]
1230c (Inline Function) --------`-------- VBoxVMM!iemOpcodeGetNextU8SlowJmp+0x95 [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 1155]
1240d 00000041`cadfea50 00007ffb`e1b60f6b VBoxVMM!iemOpcodeGetNextU8Jmp+0xc1 [L:\vbox-intern\src\VBox\VMM\include\IEMInline.h @ 402]
1250e 00000041`cadfea90 00007ffb`e1cc6201 VBoxVMM!IEMExecForExits+0xdb [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 10185]
1260f 00000041`cadfec70 00007ffb`e1d0df8d VBoxVMM!EMHistoryExec+0x4f1 [L:\vbox-intern\src\VBox\VMM\VMMAll\EMAll.cpp @ 452]
12710 00000041`cadfed60 00007ffb`e1d0d4c0 VBoxVMM!nemR3WinHandleExitCpuId+0x79d [L:\vbox-intern\src\VBox\VMM\VMMAll\NEMAllNativeTemplate-win.cpp.h @ 1829] @encode
128 @endcode
129 *
130 * @see https://developercommunity.visualstudio.com/t/fragile-behavior-of-longjmp-called-from-noexcept-f/1532859
131 */
132#if defined(IEM_WITH_SETJMP) && (defined(_MSC_VER) || defined(IEM_WITH_THROW_CATCH))
133# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT_EX(false)
134#else
135# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT
136#endif
137
138/** @def IEM_CFG_TARGET_CPU
139 * The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
140 *
141 * By default we allow this to be configured by the user via the
142 * CPUM/GuestCpuName config string, but this comes at a slight cost during
143 * decoding. So, for applications of this code where there is no need to
144 * be dynamic wrt target CPU, just modify this define.
145 */
146#if !defined(IEM_CFG_TARGET_CPU) || defined(DOXYGEN_RUNNING)
147# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
148#endif
149
150//#define IEM_WITH_CODE_TLB // - work in progress
151//#define IEM_WITH_DATA_TLB // - work in progress
152
153
154//#define IEM_LOG_MEMORY_WRITES
155
156#if !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
157/** Instruction statistics. */
158typedef struct IEMINSTRSTATS
159{
160# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
161/** @todo # include "IEMInstructionStatisticsTmpl.h" */
162 uint8_t bDummy;
163# undef IEM_DO_INSTR_STAT
164} IEMINSTRSTATS;
165#else
166struct IEMINSTRSTATS;
167typedef struct IEMINSTRSTATS IEMINSTRSTATS;
168#endif
169/** Pointer to IEM instruction statistics. */
170typedef IEMINSTRSTATS *PIEMINSTRSTATS;
171
172
173/** @name IEMTARGETCPU_EFL_BEHAVIOR_XXX - IEMCPU::aidxTargetCpuEflFlavour
174 * @{ */
175#define IEMTARGETCPU_EFL_BEHAVIOR_NATIVE 0 /**< Native result; Intel EFLAGS when on non-x86 hosts. */
176#define IEMTARGETCPU_EFL_BEHAVIOR_RESERVED 1 /**< Reserved/dummy entry slot that's the same as 0. */
177#define IEMTARGETCPU_EFL_BEHAVIOR_MASK 1 /**< For masking the index before use. */
178/** Selects the right variant from a_aArray.
179 * pVCpu is implicit in the caller context. */
180#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT(a_aArray) \
181 (a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[1] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
182/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for when no native worker can
183 * be used because the host CPU does not support the operation. */
184#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_NON_NATIVE(a_aArray) \
185 (a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
186/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for a two dimentional
187 * array paralleling IEMCPU::aidxTargetCpuEflFlavour and a single bit index
188 * into the two.
189 * @sa IEM_SELECT_NATIVE_OR_FALLBACK */
190#if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)
191# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
192 (a_aaArray[a_fNative][pVCpu->iem.s.aidxTargetCpuEflFlavour[a_fNative] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
193#else
194# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
195 (a_aaArray[0][pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
196#endif
197/** @} */
198
199/**
200 * Branch types.
201 */
202typedef enum IEMBRANCH
203{
204 IEMBRANCH_JUMP = 1,
205 IEMBRANCH_CALL,
206 IEMBRANCH_TRAP,
207 IEMBRANCH_SOFTWARE_INT,
208 IEMBRANCH_HARDWARE_INT
209} IEMBRANCH;
210AssertCompileSize(IEMBRANCH, 4);
211
212
213/**
214 * INT instruction types.
215 */
216typedef enum IEMINT
217{
218 /** INT n instruction (opcode 0xcd imm). */
219 IEMINT_INTN = 0,
220 /** Single byte INT3 instruction (opcode 0xcc). */
221 IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
222 /** Single byte INTO instruction (opcode 0xce). */
223 IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
224 /** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
225 IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
226} IEMINT;
227AssertCompileSize(IEMINT, 4);
228
229
230typedef struct IEMTLBENTRY
231{
232 /** The TLB entry tag.
233 * Bits 35 thru 0 are made up of the virtual address shifted right 12 bits, this
234 * is ASSUMING a virtual address width of 48 bits.
235 *
236 * Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
237 *
238 * The TLB lookup code uses the current TLB revision, which won't ever be zero,
239 * enabling an extremely cheap TLB invalidation most of the time. When the TLB
240 * revision wraps around though, the tags needs to be zeroed.
241 *
242 * @note Try use SHRD instruction? After seeing
243 * https://gmplib.org/~tege/x86-timing.pdf, maybe not.
244 *
245 * @todo This will need to be reorganized for 57-bit wide virtual address and
246 * PCID (currently 12 bits) and ASID (currently 6 bits) support. We'll
247 * have to move the TLB entry versioning entirely to the
248 * fFlagsAndPhysRev member then, 57 bit wide VAs means we'll only have
249 * 19 bits left (64 - 57 + 12 = 19) and they'll almost entire be
250 * consumed by PCID and ASID (12 + 6 = 18).
251 */
252 uint64_t uTag;
253 /** Access flags and physical TLB revision.
254 *
255 * - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
256 * - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
257 * - Bit 2 - page tables - not user (complemented X86_PTE_US).
258 * - Bit 3 - pgm phys/virt - not directly writable.
259 * - Bit 4 - pgm phys page - not directly readable.
260 * - Bit 5 - page tables - not accessed (complemented X86_PTE_A).
261 * - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
262 * - Bit 7 - tlb entry - pMappingR3 member not valid.
263 * - Bits 63 thru 8 are used for the physical TLB revision number.
264 *
265 * We're using complemented bit meanings here because it makes it easy to check
266 * whether special action is required. For instance a user mode write access
267 * would do a "TEST fFlags, (X86_PTE_RW | X86_PTE_US | X86_PTE_D)" and a
268 * non-zero result would mean special handling needed because either it wasn't
269 * writable, or it wasn't user, or the page wasn't dirty. A user mode read
270 * access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
271 * need to check any PTE flag.
272 */
273 uint64_t fFlagsAndPhysRev;
274 /** The guest physical page address. */
275 uint64_t GCPhys;
276 /** Pointer to the ring-3 mapping. */
277 R3PTRTYPE(uint8_t *) pbMappingR3;
278#if HC_ARCH_BITS == 32
279 uint32_t u32Padding1;
280#endif
281} IEMTLBENTRY;
282AssertCompileSize(IEMTLBENTRY, 32);
283/** Pointer to an IEM TLB entry. */
284typedef IEMTLBENTRY *PIEMTLBENTRY;
285
286/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
287 * @{ */
288#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /**< Page tables: Not executable. */
289#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /**< Page tables: Not writable. */
290#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /**< Page tables: Not user accessible (supervisor only). */
291#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /**< Phys page: Not writable (access handler, ROM, whatever). */
292#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /**< Phys page: Not readable (MMIO / access handler, ROM) */
293#define IEMTLBE_F_PT_NO_ACCESSED RT_BIT_64(5) /**< Phys tables: Not accessed (need to be marked accessed). */
294#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /**< Page tables: Not dirty (needs to be made dirty on write). */
295#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(7) /**< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. */
296#define IEMTLBE_F_PG_UNASSIGNED RT_BIT_64(8) /**< Phys page: Unassigned memory (not RAM, ROM, MMIO2 or MMIO). */
297#define IEMTLBE_F_PG_CODE_PAGE RT_BIT_64(9) /**< Phys page: Code page. */
298#define IEMTLBE_F_PHYS_REV UINT64_C(0xfffffffffffffc00) /**< Physical revision mask. @sa IEMTLB_PHYS_REV_INCR */
299/** @} */
300
301
302/**
303 * An IEM TLB.
304 *
305 * We've got two of these, one for data and one for instructions.
306 */
307typedef struct IEMTLB
308{
309 /** The TLB entries.
310 * We've choosen 256 because that way we can obtain the result directly from a
311 * 8-bit register without an additional AND instruction. */
312 IEMTLBENTRY aEntries[256];
313 /** The TLB revision.
314 * This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
315 * by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
316 * the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
317 * (The revision zero indicates an invalid TLB entry.)
318 *
319 * The initial value is choosen to cause an early wraparound. */
320 uint64_t uTlbRevision;
321 /** The TLB physical address revision - shadow of PGM variable.
322 *
323 * This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
324 * incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
325 * a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
326 * as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
327 *
328 * The initial value is choosen to cause an early wraparound. */
329 uint64_t volatile uTlbPhysRev;
330
331 /* Statistics: */
332
333 /** TLB hits (VBOX_WITH_STATISTICS only). */
334 uint64_t cTlbHits;
335 /** TLB misses. */
336 uint32_t cTlbMisses;
337 /** Slow read path. */
338 uint32_t cTlbSlowReadPath;
339#if 0
340 /** TLB misses because of tag mismatch. */
341 uint32_t cTlbMissesTag;
342 /** TLB misses because of virtual access violation. */
343 uint32_t cTlbMissesVirtAccess;
344 /** TLB misses because of dirty bit. */
345 uint32_t cTlbMissesDirty;
346 /** TLB misses because of MMIO */
347 uint32_t cTlbMissesMmio;
348 /** TLB misses because of write access handlers. */
349 uint32_t cTlbMissesWriteHandler;
350 /** TLB misses because no r3(/r0) mapping. */
351 uint32_t cTlbMissesMapping;
352#endif
353 /** Alignment padding. */
354 uint32_t au32Padding[3+5];
355} IEMTLB;
356AssertCompileSizeAlignment(IEMTLB, 64);
357/** IEMTLB::uTlbRevision increment. */
358#define IEMTLB_REVISION_INCR RT_BIT_64(36)
359/** IEMTLB::uTlbRevision mask. */
360#define IEMTLB_REVISION_MASK (~(RT_BIT_64(36) - 1))
361/** IEMTLB::uTlbPhysRev increment.
362 * @sa IEMTLBE_F_PHYS_REV */
363#define IEMTLB_PHYS_REV_INCR RT_BIT_64(10)
364/**
365 * Calculates the TLB tag for a virtual address.
366 * @returns Tag value for indexing and comparing with IEMTLB::uTag.
367 * @param a_pTlb The TLB.
368 * @param a_GCPtr The virtual address.
369 */
370#define IEMTLB_CALC_TAG(a_pTlb, a_GCPtr) ( IEMTLB_CALC_TAG_NO_REV(a_GCPtr) | (a_pTlb)->uTlbRevision )
371/**
372 * Calculates the TLB tag for a virtual address but without TLB revision.
373 * @returns Tag value for indexing and comparing with IEMTLB::uTag.
374 * @param a_GCPtr The virtual address.
375 */
376#define IEMTLB_CALC_TAG_NO_REV(a_GCPtr) ( (((a_GCPtr) << 16) >> (GUEST_PAGE_SHIFT + 16)) )
377/**
378 * Converts a TLB tag value into a TLB index.
379 * @returns Index into IEMTLB::aEntries.
380 * @param a_uTag Value returned by IEMTLB_CALC_TAG.
381 */
382#define IEMTLB_TAG_TO_INDEX(a_uTag) ( (uint8_t)(a_uTag) )
383/**
384 * Converts a TLB tag value into a TLB index.
385 * @returns Index into IEMTLB::aEntries.
386 * @param a_pTlb The TLB.
387 * @param a_uTag Value returned by IEMTLB_CALC_TAG.
388 */
389#define IEMTLB_TAG_TO_ENTRY(a_pTlb, a_uTag) ( &(a_pTlb)->aEntries[IEMTLB_TAG_TO_INDEX(a_uTag)] )
390
391
392/**
393 * The per-CPU IEM state.
394 *
395 * @todo This is just a STUB currently!
396 */
397typedef struct IEMCPU
398{
399 /** Info status code that needs to be propagated to the IEM caller.
400 * This cannot be passed internally, as it would complicate all success
401 * checks within the interpreter making the code larger and almost impossible
402 * to get right. Instead, we'll store status codes to pass on here. Each
403 * source of these codes will perform appropriate sanity checks. */
404 int32_t rcPassUp; /* 0x00 */
405
406 /** The current CPU execution mode (CS). */
407 IEMMODE enmCpuMode; /* 0x04 */
408 /** The Exception Level (EL). */
409 uint8_t uEl; /* 0x05 */
410
411 /** Whether to bypass access handlers or not. */
412 bool fBypassHandlers : 1; /* 0x06.0 */
413 /** Whether there are pending hardware instruction breakpoints. */
414 bool fPendingInstructionBreakpoints : 1; /* 0x06.2 */
415 /** Whether there are pending hardware data breakpoints. */
416 bool fPendingDataBreakpoints : 1; /* 0x06.3 */
417
418 /* Unused/padding */
419 bool fUnused; /* 0x07 */
420
421 /** @name Decoder state.
422 * @{ */
423#ifndef IEM_WITH_OPAQUE_DECODER_STATE
424 /** The current instruction being executed. */
425 uint32_t u32Insn;
426 uint8_t abOpaqueDecoder[0x48 - 0x4 - 0x8];
427#else /* IEM_WITH_OPAQUE_DECODER_STATE */
428 uint8_t abOpaqueDecoder[0x48 - 0x8];
429#endif /* IEM_WITH_OPAQUE_DECODER_STATE */
430 /** @} */
431
432
433 /** The flags of the current exception / interrupt. */
434 uint32_t fCurXcpt; /* 0x48, 0x48 */
435 /** The current exception / interrupt. */
436 uint8_t uCurXcpt;
437 /** Exception / interrupt recursion depth. */
438 int8_t cXcptRecursions;
439
440 /** The number of active guest memory mappings. */
441 uint8_t cActiveMappings;
442 /** The next unused mapping index. */
443 uint8_t iNextMapping;
444 /** Records for tracking guest memory mappings. */
445 struct
446 {
447 /** The address of the mapped bytes. */
448 void *pv;
449 /** The access flags (IEM_ACCESS_XXX).
450 * IEM_ACCESS_INVALID if the entry is unused. */
451 uint32_t fAccess;
452#if HC_ARCH_BITS == 64
453 uint32_t u32Alignment4; /**< Alignment padding. */
454#endif
455 } aMemMappings[3];
456
457 /** Locking records for the mapped memory. */
458 union
459 {
460 PGMPAGEMAPLOCK Lock;
461 uint64_t au64Padding[2];
462 } aMemMappingLocks[3];
463
464 /** Bounce buffer info.
465 * This runs in parallel to aMemMappings. */
466 struct
467 {
468 /** The physical address of the first byte. */
469 RTGCPHYS GCPhysFirst;
470 /** The physical address of the second page. */
471 RTGCPHYS GCPhysSecond;
472 /** The number of bytes in the first page. */
473 uint16_t cbFirst;
474 /** The number of bytes in the second page. */
475 uint16_t cbSecond;
476 /** Whether it's unassigned memory. */
477 bool fUnassigned;
478 /** Explicit alignment padding. */
479 bool afAlignment5[3];
480 } aMemBbMappings[3];
481
482 /* Ensure that aBounceBuffers are aligned at a 32 byte boundrary. */
483 uint64_t abAlignment7[1];
484
485 /** Bounce buffer storage.
486 * This runs in parallel to aMemMappings and aMemBbMappings. */
487 struct
488 {
489 uint8_t ab[512];
490 } aBounceBuffers[3];
491
492
493 /** Pointer set jump buffer - ring-3 context. */
494 R3PTRTYPE(jmp_buf *) pJmpBufR3;
495
496 /** The error code for the current exception / interrupt. */
497 uint32_t uCurXcptErr;
498
499 /** @name Statistics
500 * @{ */
501 /** The number of instructions we've executed. */
502 uint32_t cInstructions;
503 /** The number of potential exits. */
504 uint32_t cPotentialExits;
505 /** The number of bytes data or stack written (mostly for IEMExecOneEx).
506 * This may contain uncommitted writes. */
507 uint32_t cbWritten;
508 /** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
509 uint32_t cRetInstrNotImplemented;
510 /** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
511 uint32_t cRetAspectNotImplemented;
512 /** Counts informational statuses returned (other than VINF_SUCCESS). */
513 uint32_t cRetInfStatuses;
514 /** Counts other error statuses returned. */
515 uint32_t cRetErrStatuses;
516 /** Number of times rcPassUp has been used. */
517 uint32_t cRetPassUpStatus;
518 /** Number of times RZ left with instruction commit pending for ring-3. */
519 uint32_t cPendingCommit;
520 /** Number of long jumps. */
521 uint32_t cLongJumps;
522 /** @} */
523
524 /** @name Target CPU information.
525 * @{ */
526#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
527 /** The target CPU. */
528 uint8_t uTargetCpu;
529#else
530 uint8_t bTargetCpuPadding;
531#endif
532 /** For selecting assembly works matching the target CPU EFLAGS behaviour, see
533 * IEMTARGETCPU_EFL_BEHAVIOR_XXX for values, with the 1st entry for when no
534 * native host support and the 2nd for when there is.
535 *
536 * The two values are typically indexed by a g_CpumHostFeatures bit.
537 *
538 * This is for instance used for the BSF & BSR instructions where AMD and
539 * Intel CPUs produce different EFLAGS. */
540 uint8_t aidxTargetCpuEflFlavour[2];
541
542 uint8_t bPadding;
543
544 /** The CPU vendor. */
545 CPUMCPUVENDOR enmCpuVendor;
546 /** @} */
547
548 /** @name Host CPU information.
549 * @{ */
550 /** The CPU vendor. */
551 CPUMCPUVENDOR enmHostCpuVendor;
552 /** @} */
553
554 /** Data TLB.
555 * @remarks Must be 64-byte aligned. */
556 IEMTLB DataTlb;
557 /** Instruction TLB.
558 * @remarks Must be 64-byte aligned. */
559 IEMTLB CodeTlb;
560
561 /** Exception statistics. */
562 STAMCOUNTER aStatXcpts[32];
563 /** Interrupt statistics. */
564 uint32_t aStatInts[256];
565
566#if defined(VBOX_WITH_STATISTICS) && !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
567 /** Instruction statistics for ring-3. */
568 IEMINSTRSTATS StatsR3;
569#endif
570} IEMCPU;
571AssertCompileMemberOffset(IEMCPU, fCurXcpt, 0x48);
572AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 8);
573AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 16);
574AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 32);
575AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 64);
576AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
577AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
578
579/** Pointer to the per-CPU IEM state. */
580typedef IEMCPU *PIEMCPU;
581/** Pointer to the const per-CPU IEM state. */
582typedef IEMCPU const *PCIEMCPU;
583
584
585/** @def IEM_GET_CTX
586 * Gets the guest CPU context for the calling EMT.
587 * @returns PCPUMCTX
588 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
589 */
590#define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
591
592/** @def IEM_CTX_ASSERT
593 * Asserts that the @a a_fExtrnMbz is present in the CPU context.
594 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
595 * @param a_fExtrnMbz The mask of CPUMCTX_EXTRN_XXX flags that must be zero.
596 */
597#define IEM_CTX_ASSERT(a_pVCpu, a_fExtrnMbz) AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
598 ("fExtrn=%#RX64 fExtrnMbz=%#RX64\n", (a_pVCpu)->cpum.GstCtx.fExtrn, \
599 (a_fExtrnMbz)))
600
601/** @def IEM_CTX_IMPORT_RET
602 * Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
603 *
604 * Will call the keep to import the bits as needed.
605 *
606 * Returns on import failure.
607 *
608 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
609 * @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
610 */
611#define IEM_CTX_IMPORT_RET(a_pVCpu, a_fExtrnImport) \
612 do { \
613 if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
614 { /* likely */ } \
615 else \
616 { \
617 int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
618 AssertRCReturn(rcCtxImport, rcCtxImport); \
619 } \
620 } while (0)
621
622/** @def IEM_CTX_IMPORT_NORET
623 * Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
624 *
625 * Will call the keep to import the bits as needed.
626 *
627 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
628 * @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
629 */
630#define IEM_CTX_IMPORT_NORET(a_pVCpu, a_fExtrnImport) \
631 do { \
632 if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
633 { /* likely */ } \
634 else \
635 { \
636 int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
637 AssertLogRelRC(rcCtxImport); \
638 } \
639 } while (0)
640
641/** @def IEM_CTX_IMPORT_JMP
642 * Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
643 *
644 * Will call the keep to import the bits as needed.
645 *
646 * Jumps on import failure.
647 *
648 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
649 * @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
650 */
651#define IEM_CTX_IMPORT_JMP(a_pVCpu, a_fExtrnImport) \
652 do { \
653 if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
654 { /* likely */ } \
655 else \
656 { \
657 int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
658 AssertRCStmt(rcCtxImport, IEM_DO_LONGJMP(pVCpu, rcCtxImport)); \
659 } \
660 } while (0)
661
662
663
664/** @def IEM_GET_TARGET_CPU
665 * Gets the current IEMTARGETCPU value.
666 * @returns IEMTARGETCPU value.
667 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
668 */
669#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
670# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
671#else
672# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
673#endif
674
675/** @def IEM_GET_INSTR_LEN
676 * Gets the instruction length. */
677/** @todo Thumb mode. */
678#ifdef IEM_WITH_CODE_TLB
679# define IEM_GET_INSTR_LEN(a_pVCpu) (sizeof(uint32_t))
680#else
681# define IEM_GET_INSTR_LEN(a_pVCpu) (sizeof(uint32_t))
682#endif
683
684
685/**
686 * Shared per-VM IEM data.
687 */
688typedef struct IEM
689{
690 uint8_t bDummy;
691} IEM;
692
693
694
695/** @name IEM_ACCESS_XXX - Access details.
696 * @{ */
697#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
698#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
699#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
700#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
701#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
702#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
703#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
704#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
705#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
706#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
707/** The writes are partial, so if initialize the bounce buffer with the
708 * orignal RAM content. */
709#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
710/** Used in aMemMappings to indicate that the entry is bounce buffered. */
711#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
712/** Bounce buffer with ring-3 write pending, first page. */
713#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
714/** Bounce buffer with ring-3 write pending, second page. */
715#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
716/** Not locked, accessed via the TLB. */
717#define IEM_ACCESS_NOT_LOCKED UINT32_C(0x00001000)
718/** Valid bit mask. */
719#define IEM_ACCESS_VALID_MASK UINT32_C(0x00001fff)
720/** Shift count for the TLB flags (upper word). */
721#define IEM_ACCESS_SHIFT_TLB_FLAGS 16
722
723/** Read+write data alias. */
724#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ | IEM_ACCESS_TYPE_WRITE | IEM_ACCESS_WHAT_DATA)
725/** Write data alias. */
726#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE | IEM_ACCESS_WHAT_DATA)
727/** Read data alias. */
728#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_DATA)
729/** Instruction fetch alias. */
730#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC | IEM_ACCESS_WHAT_CODE)
731/** Stack write alias. */
732#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE | IEM_ACCESS_WHAT_STACK)
733/** Stack read alias. */
734#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_STACK)
735/** Stack read+write alias. */
736#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ | IEM_ACCESS_TYPE_WRITE | IEM_ACCESS_WHAT_STACK)
737/** Read system table alias. */
738#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_SYS)
739/** Read+write system table alias. */
740#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ | IEM_ACCESS_TYPE_WRITE | IEM_ACCESS_WHAT_SYS)
741/** @} */
742
743/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
744#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
745
746/** @def IEM_DECL_IMPL_TYPE
747 * For typedef'ing an instruction implementation function.
748 *
749 * @param a_RetType The return type.
750 * @param a_Name The name of the type.
751 * @param a_ArgList The argument list enclosed in parentheses.
752 */
753
754/** @def IEM_DECL_IMPL_DEF
755 * For defining an instruction implementation function.
756 *
757 * @param a_RetType The return type.
758 * @param a_Name The name of the type.
759 * @param a_ArgList The argument list enclosed in parentheses.
760 */
761
762#if __cplusplus >= 201700 /* P0012R1 support */
763# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
764 a_RetType (VBOXCALL a_Name) a_ArgList RT_NOEXCEPT
765# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
766 a_RetType VBOXCALL a_Name a_ArgList RT_NOEXCEPT
767# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
768 a_RetType VBOXCALL a_Name a_ArgList RT_NOEXCEPT
769
770#else
771# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
772 a_RetType (VBOXCALL a_Name) a_ArgList
773# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
774 a_RetType VBOXCALL a_Name a_ArgList
775# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
776 a_RetType VBOXCALL a_Name a_ArgList
777
778#endif
779
780/** @name C instruction implementations for anything slightly complicated.
781 * @{ */
782
783/**
784 * For typedef'ing or declaring a C instruction implementation function taking
785 * no extra arguments.
786 *
787 * @param a_Name The name of the type.
788 */
789# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
790 IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
791/**
792 * For defining a C instruction implementation function taking no extra
793 * arguments.
794 *
795 * @param a_Name The name of the function
796 */
797# define IEM_CIMPL_DEF_0(a_Name) \
798 IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
799/**
800 * Prototype version of IEM_CIMPL_DEF_0.
801 */
802# define IEM_CIMPL_PROTO_0(a_Name) \
803 IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
804/**
805 * For calling a C instruction implementation function taking no extra
806 * arguments.
807 *
808 * This special call macro adds default arguments to the call and allow us to
809 * change these later.
810 *
811 * @param a_fn The name of the function.
812 */
813# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
814
815/**
816 * For typedef'ing or declaring a C instruction implementation function taking
817 * one extra argument.
818 *
819 * @param a_Name The name of the type.
820 * @param a_Type0 The argument type.
821 * @param a_Arg0 The argument name.
822 */
823# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
824 IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
825/**
826 * For defining a C instruction implementation function taking one extra
827 * argument.
828 *
829 * @param a_Name The name of the function
830 * @param a_Type0 The argument type.
831 * @param a_Arg0 The argument name.
832 */
833# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
834 IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
835/**
836 * Prototype version of IEM_CIMPL_DEF_1.
837 */
838# define IEM_CIMPL_PROTO_1(a_Name, a_Type0, a_Arg0) \
839 IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
840/**
841 * For calling a C instruction implementation function taking one extra
842 * argument.
843 *
844 * This special call macro adds default arguments to the call and allow us to
845 * change these later.
846 *
847 * @param a_fn The name of the function.
848 * @param a0 The name of the 1st argument.
849 */
850# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
851
852/**
853 * For typedef'ing or declaring a C instruction implementation function taking
854 * two extra arguments.
855 *
856 * @param a_Name The name of the type.
857 * @param a_Type0 The type of the 1st argument
858 * @param a_Arg0 The name of the 1st argument.
859 * @param a_Type1 The type of the 2nd argument.
860 * @param a_Arg1 The name of the 2nd argument.
861 */
862# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
863 IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
864/**
865 * For defining a C instruction implementation function taking two extra
866 * arguments.
867 *
868 * @param a_Name The name of the function.
869 * @param a_Type0 The type of the 1st argument
870 * @param a_Arg0 The name of the 1st argument.
871 * @param a_Type1 The type of the 2nd argument.
872 * @param a_Arg1 The name of the 2nd argument.
873 */
874# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
875 IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
876/**
877 * Prototype version of IEM_CIMPL_DEF_2.
878 */
879# define IEM_CIMPL_PROTO_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
880 IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
881/**
882 * For calling a C instruction implementation function taking two extra
883 * arguments.
884 *
885 * This special call macro adds default arguments to the call and allow us to
886 * change these later.
887 *
888 * @param a_fn The name of the function.
889 * @param a0 The name of the 1st argument.
890 * @param a1 The name of the 2nd argument.
891 */
892# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
893
894/**
895 * For typedef'ing or declaring a C instruction implementation function taking
896 * three extra arguments.
897 *
898 * @param a_Name The name of the type.
899 * @param a_Type0 The type of the 1st argument
900 * @param a_Arg0 The name of the 1st argument.
901 * @param a_Type1 The type of the 2nd argument.
902 * @param a_Arg1 The name of the 2nd argument.
903 * @param a_Type2 The type of the 3rd argument.
904 * @param a_Arg2 The name of the 3rd argument.
905 */
906# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
907 IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
908/**
909 * For defining a C instruction implementation function taking three extra
910 * arguments.
911 *
912 * @param a_Name The name of the function.
913 * @param a_Type0 The type of the 1st argument
914 * @param a_Arg0 The name of the 1st argument.
915 * @param a_Type1 The type of the 2nd argument.
916 * @param a_Arg1 The name of the 2nd argument.
917 * @param a_Type2 The type of the 3rd argument.
918 * @param a_Arg2 The name of the 3rd argument.
919 */
920# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
921 IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
922/**
923 * Prototype version of IEM_CIMPL_DEF_3.
924 */
925# define IEM_CIMPL_PROTO_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
926 IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
927/**
928 * For calling a C instruction implementation function taking three extra
929 * arguments.
930 *
931 * This special call macro adds default arguments to the call and allow us to
932 * change these later.
933 *
934 * @param a_fn The name of the function.
935 * @param a0 The name of the 1st argument.
936 * @param a1 The name of the 2nd argument.
937 * @param a2 The name of the 3rd argument.
938 */
939# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
940
941
942/**
943 * For typedef'ing or declaring a C instruction implementation function taking
944 * four extra arguments.
945 *
946 * @param a_Name The name of the type.
947 * @param a_Type0 The type of the 1st argument
948 * @param a_Arg0 The name of the 1st argument.
949 * @param a_Type1 The type of the 2nd argument.
950 * @param a_Arg1 The name of the 2nd argument.
951 * @param a_Type2 The type of the 3rd argument.
952 * @param a_Arg2 The name of the 3rd argument.
953 * @param a_Type3 The type of the 4th argument.
954 * @param a_Arg3 The name of the 4th argument.
955 */
956# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
957 IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
958/**
959 * For defining a C instruction implementation function taking four extra
960 * arguments.
961 *
962 * @param a_Name The name of the function.
963 * @param a_Type0 The type of the 1st argument
964 * @param a_Arg0 The name of the 1st argument.
965 * @param a_Type1 The type of the 2nd argument.
966 * @param a_Arg1 The name of the 2nd argument.
967 * @param a_Type2 The type of the 3rd argument.
968 * @param a_Arg2 The name of the 3rd argument.
969 * @param a_Type3 The type of the 4th argument.
970 * @param a_Arg3 The name of the 4th argument.
971 */
972# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
973 IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
974 a_Type2 a_Arg2, a_Type3 a_Arg3))
975/**
976 * Prototype version of IEM_CIMPL_DEF_4.
977 */
978# define IEM_CIMPL_PROTO_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
979 IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
980 a_Type2 a_Arg2, a_Type3 a_Arg3))
981/**
982 * For calling a C instruction implementation function taking four extra
983 * arguments.
984 *
985 * This special call macro adds default arguments to the call and allow us to
986 * change these later.
987 *
988 * @param a_fn The name of the function.
989 * @param a0 The name of the 1st argument.
990 * @param a1 The name of the 2nd argument.
991 * @param a2 The name of the 3rd argument.
992 * @param a3 The name of the 4th argument.
993 */
994# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
995
996
997/**
998 * For typedef'ing or declaring a C instruction implementation function taking
999 * five extra arguments.
1000 *
1001 * @param a_Name The name of the type.
1002 * @param a_Type0 The type of the 1st argument
1003 * @param a_Arg0 The name of the 1st argument.
1004 * @param a_Type1 The type of the 2nd argument.
1005 * @param a_Arg1 The name of the 2nd argument.
1006 * @param a_Type2 The type of the 3rd argument.
1007 * @param a_Arg2 The name of the 3rd argument.
1008 * @param a_Type3 The type of the 4th argument.
1009 * @param a_Arg3 The name of the 4th argument.
1010 * @param a_Type4 The type of the 5th argument.
1011 * @param a_Arg4 The name of the 5th argument.
1012 */
1013# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
1014 IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, \
1015 a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
1016 a_Type3 a_Arg3, a_Type4 a_Arg4))
1017/**
1018 * For defining a C instruction implementation function taking five extra
1019 * arguments.
1020 *
1021 * @param a_Name The name of the function.
1022 * @param a_Type0 The type of the 1st argument
1023 * @param a_Arg0 The name of the 1st argument.
1024 * @param a_Type1 The type of the 2nd argument.
1025 * @param a_Arg1 The name of the 2nd argument.
1026 * @param a_Type2 The type of the 3rd argument.
1027 * @param a_Arg2 The name of the 3rd argument.
1028 * @param a_Type3 The type of the 4th argument.
1029 * @param a_Arg3 The name of the 4th argument.
1030 * @param a_Type4 The type of the 5th argument.
1031 * @param a_Arg4 The name of the 5th argument.
1032 */
1033# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
1034 IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
1035 a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
1036/**
1037 * Prototype version of IEM_CIMPL_DEF_5.
1038 */
1039# define IEM_CIMPL_PROTO_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
1040 IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
1041 a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
1042/**
1043 * For calling a C instruction implementation function taking five extra
1044 * arguments.
1045 *
1046 * This special call macro adds default arguments to the call and allow us to
1047 * change these later.
1048 *
1049 * @param a_fn The name of the function.
1050 * @param a0 The name of the 1st argument.
1051 * @param a1 The name of the 2nd argument.
1052 * @param a2 The name of the 3rd argument.
1053 * @param a3 The name of the 4th argument.
1054 * @param a4 The name of the 5th argument.
1055 */
1056# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
1057
1058/** @} */
1059
1060
1061/** @name Opcode Decoder Function Types.
1062 * @{ */
1063
1064# if 0 /** @todo r=bird: This upsets doxygen. Generally, these macros and types probably won't change with the target arch.
1065 * Nor will probably the TLB definitions. So, we need some better splitting of this code. */
1066/** @typedef PFNIEMOP
1067 * Pointer to an opcode decoder function.
1068 */
1069
1070/** @def FNIEMOP_DEF
1071 * Define an opcode decoder function.
1072 *
1073 * We're using macors for this so that adding and removing parameters as well as
1074 * tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL
1075 *
1076 * @param a_Name The function name.
1077 */
1078#endif
1079
1080#if defined(__GNUC__) && defined(RT_ARCH_X86)
1081typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOP)(PVMCPUCC pVCpu);
1082# define FNIEMOP_DEF(a_Name) \
1083 IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu)
1084# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
1085 IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
1086# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
1087 IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
1088
1089#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
1090typedef VBOXSTRICTRC (__fastcall * PFNIEMOP)(PVMCPUCC pVCpu);
1091# define FNIEMOP_DEF(a_Name) \
1092 IEM_STATIC /*__declspec(naked)*/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
1093# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
1094 IEM_STATIC /*__declspec(naked)*/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
1095# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
1096 IEM_STATIC /*__declspec(naked)*/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
1097
1098#elif defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
1099typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
1100# define FNIEMOP_DEF(a_Name) \
1101 IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu)
1102# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
1103 IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
1104# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
1105 IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
1106
1107#else
1108typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
1109# define FNIEMOP_DEF(a_Name) \
1110 IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
1111# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
1112 IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
1113# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
1114 IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
1115
1116#endif
1117
1118/**
1119 * Call an opcode decoder function.
1120 *
1121 * We're using macors for this so that adding and removing parameters can be
1122 * done as we please. See FNIEMOP_DEF.
1123 */
1124#define FNIEMOP_CALL(a_pfn) (a_pfn)(pVCpu)
1125
1126/**
1127 * Call a common opcode decoder function taking one extra argument.
1128 *
1129 * We're using macors for this so that adding and removing parameters can be
1130 * done as we please. See FNIEMOP_DEF_1.
1131 */
1132#define FNIEMOP_CALL_1(a_pfn, a0) (a_pfn)(pVCpu, a0)
1133
1134/**
1135 * Call a common opcode decoder function taking one extra argument.
1136 *
1137 * We're using macors for this so that adding and removing parameters can be
1138 * done as we please. See FNIEMOP_DEF_1.
1139 */
1140#define FNIEMOP_CALL_2(a_pfn, a0, a1) (a_pfn)(pVCpu, a0, a1)
1141/** @} */
1142
1143
1144/** @name Misc Helpers
1145 * @{ */
1146
1147/** Used to shut up GCC warnings about variables that 'may be used uninitialized'
1148 * due to GCC lacking knowledge about the value range of a switch. */
1149#if RT_CPLUSPLUS_PREREQ(202000)
1150# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: [[unlikely]] AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
1151#else
1152# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
1153#endif
1154
1155/** Variant of IEM_NOT_REACHED_DEFAULT_CASE_RET that returns a custom value. */
1156#if RT_CPLUSPLUS_PREREQ(202000)
1157# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: [[unlikely]] AssertFailedReturn(a_RetValue)
1158#else
1159# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: AssertFailedReturn(a_RetValue)
1160#endif
1161
1162/**
1163 * Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
1164 * occation.
1165 */
1166#ifdef LOG_ENABLED
1167# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
1168 do { \
1169 /*Log*/ LogAlways(("%s: returning IEM_RETURN_ASPECT_NOT_IMPLEMENTED (line %d)\n", __FUNCTION__, __LINE__)); \
1170 return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
1171 } while (0)
1172#else
1173# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
1174 return VERR_IEM_ASPECT_NOT_IMPLEMENTED
1175#endif
1176
1177/**
1178 * Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
1179 * occation using the supplied logger statement.
1180 *
1181 * @param a_LoggerArgs What to log on failure.
1182 */
1183#ifdef LOG_ENABLED
1184# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
1185 do { \
1186 LogAlways((LOG_FN_FMT ": ", __PRETTY_FUNCTION__)); LogAlways(a_LoggerArgs); \
1187 /*LogFunc(a_LoggerArgs);*/ \
1188 return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
1189 } while (0)
1190#else
1191# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
1192 return VERR_IEM_ASPECT_NOT_IMPLEMENTED
1193#endif
1194
1195/** @} */
1196
1197void iemInitPendingBreakpointsSlow(PVMCPUCC pVCpu);
1198
1199
1200/** @name Raising Exceptions.
1201 * @{ */
1202VBOXSTRICTRC iemRaiseXcptOrInt(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags,
1203 uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
1204#ifdef IEM_WITH_SETJMP
1205DECL_NO_RETURN(void) iemRaiseXcptOrIntJmp(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector,
1206 uint32_t fFlags, uint16_t uErr, uint64_t uCr2) IEM_NOEXCEPT_MAY_LONGJMP;
1207#endif
1208VBOXSTRICTRC iemRaiseDivideError(PVMCPUCC pVCpu) RT_NOEXCEPT;
1209VBOXSTRICTRC iemRaiseDebugException(PVMCPUCC pVCpu) RT_NOEXCEPT;
1210VBOXSTRICTRC iemRaiseUndefinedOpcode(PVMCPUCC pVCpu) RT_NOEXCEPT;
1211VBOXSTRICTRC iemRaisePageFault(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) RT_NOEXCEPT;
1212#ifdef IEM_WITH_SETJMP
1213DECL_NO_RETURN(void) iemRaisePageFaultJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) IEM_NOEXCEPT_MAY_LONGJMP;
1214#endif
1215VBOXSTRICTRC iemRaiseMathFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
1216VBOXSTRICTRC iemRaiseAlignmentCheckException(PVMCPUCC pVCpu) RT_NOEXCEPT;
1217#ifdef IEM_WITH_SETJMP
1218DECL_NO_RETURN(void) iemRaiseAlignmentCheckExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
1219#endif
1220VBOXSTRICTRC iemRaiseSimdFpException(PVMCPUCC pVCpu) RT_NOEXCEPT;
1221
1222IEM_CIMPL_DEF_0(iemCImplRaiseDivideError);
1223IEM_CIMPL_DEF_0(iemCImplRaiseInvalidOpcode);
1224
1225/**
1226 * Macro for calling iemCImplRaiseDivideError().
1227 *
1228 * This enables us to add/remove arguments and force different levels of
1229 * inlining as we wish.
1230 *
1231 * @return Strict VBox status code.
1232 */
1233#define IEMOP_RAISE_DIVIDE_ERROR_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(iemCImplRaiseDivideError)
1234
1235/**
1236 * Macro for calling iemCImplRaiseInvalidOpcode().
1237 *
1238 * This enables us to add/remove arguments and force different levels of
1239 * inlining as we wish.
1240 *
1241 * @return Strict VBox status code.
1242 */
1243#define IEMOP_RAISE_INVALID_OPCODE_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(iemCImplRaiseInvalidOpcode)
1244/** @} */
1245
1246/** @name Memory access.
1247 * @{ */
1248
1249VBOXSTRICTRC iemMemMap(PVMCPUCC pVCpu, void **ppvMem, size_t cbMem, uint8_t iSegReg, RTGCPTR GCPtrMem,
1250 uint32_t fAccess, uint32_t uAlignCtl) RT_NOEXCEPT;
1251VBOXSTRICTRC iemMemCommitAndUnmap(PVMCPUCC pVCpu, void *pvMem, uint32_t fAccess) RT_NOEXCEPT;
1252#ifndef IN_RING3
1253VBOXSTRICTRC iemMemCommitAndUnmapPostponeTroubleToR3(PVMCPUCC pVCpu, void *pvMem, uint32_t fAccess) RT_NOEXCEPT;
1254#endif
1255void iemMemRollback(PVMCPUCC pVCpu) RT_NOEXCEPT;
1256VBOXSTRICTRC iemMemApplySegment(PVMCPUCC pVCpu, uint32_t fAccess, uint8_t iSegReg, size_t cbMem, PRTGCPTR pGCPtrMem) RT_NOEXCEPT;
1257VBOXSTRICTRC iemMemMarkSelDescAccessed(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
1258VBOXSTRICTRC iemMemPageTranslateAndCheckAccess(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t cbAccess, uint32_t fAccess, PRTGCPHYS pGCPhysMem) RT_NOEXCEPT;
1259
1260VBOXSTRICTRC iemMemFetchDataU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
1261VBOXSTRICTRC iemMemFetchDataU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
1262VBOXSTRICTRC iemMemFetchDataU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
1263VBOXSTRICTRC iemMemFetchDataU32_ZX_U64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
1264VBOXSTRICTRC iemMemFetchDataU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
1265VBOXSTRICTRC iemMemFetchDataR80(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
1266VBOXSTRICTRC iemMemFetchDataD80(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
1267VBOXSTRICTRC iemMemFetchDataU128(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
1268VBOXSTRICTRC iemMemFetchDataU256(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
1269#ifdef IEM_WITH_SETJMP
1270uint8_t iemMemFetchDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
1271uint16_t iemMemFetchDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
1272uint32_t iemMemFetchDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
1273uint64_t iemMemFetchDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
1274void iemMemFetchDataR80Jmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
1275void iemMemFetchDataD80Jmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
1276void iemMemFetchDataU128Jmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
1277void iemMemFetchDataU256Jmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
1278#endif
1279
1280VBOXSTRICTRC iemMemFetchSysU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
1281VBOXSTRICTRC iemMemFetchSysU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
1282VBOXSTRICTRC iemMemFetchSysU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
1283VBOXSTRICTRC iemMemFetchSysU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
1284
1285VBOXSTRICTRC iemMemStoreDataU8(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) RT_NOEXCEPT;
1286VBOXSTRICTRC iemMemStoreDataU16(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) RT_NOEXCEPT;
1287VBOXSTRICTRC iemMemStoreDataU32(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) RT_NOEXCEPT;
1288VBOXSTRICTRC iemMemStoreDataU64(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) RT_NOEXCEPT;
1289VBOXSTRICTRC iemMemStoreDataU128(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
1290VBOXSTRICTRC iemMemStoreDataU256(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
1291#ifdef IEM_WITH_SETJMP
1292void iemMemStoreDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
1293void iemMemStoreDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
1294void iemMemStoreDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
1295void iemMemStoreDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
1296void iemMemStoreDataU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
1297void iemMemStoreDataU256Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
1298#endif
1299
1300VBOXSTRICTRC iemMemStackPushBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
1301 void **ppvMem, uint64_t *puNewRsp) RT_NOEXCEPT;
1302VBOXSTRICTRC iemMemStackPushCommitSpecial(PVMCPUCC pVCpu, void *pvMem, uint64_t uNewRsp) RT_NOEXCEPT;
1303VBOXSTRICTRC iemMemStackPushU16(PVMCPUCC pVCpu, uint16_t u16Value) RT_NOEXCEPT;
1304VBOXSTRICTRC iemMemStackPushU32(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
1305VBOXSTRICTRC iemMemStackPushU64(PVMCPUCC pVCpu, uint64_t u64Value) RT_NOEXCEPT;
1306VBOXSTRICTRC iemMemStackPushU16Ex(PVMCPUCC pVCpu, uint16_t u16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
1307VBOXSTRICTRC iemMemStackPushU32Ex(PVMCPUCC pVCpu, uint32_t u32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
1308VBOXSTRICTRC iemMemStackPushU64Ex(PVMCPUCC pVCpu, uint64_t u64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
1309VBOXSTRICTRC iemMemStackPushU32SReg(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
1310VBOXSTRICTRC iemMemStackPopBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
1311 void const **ppvMem, uint64_t *puNewRsp) RT_NOEXCEPT;
1312VBOXSTRICTRC iemMemStackPopContinueSpecial(PVMCPUCC pVCpu, size_t off, size_t cbMem,
1313 void const **ppvMem, uint64_t uCurNewRsp) RT_NOEXCEPT;
1314VBOXSTRICTRC iemMemStackPopDoneSpecial(PVMCPUCC pVCpu, void const *pvMem) RT_NOEXCEPT;
1315VBOXSTRICTRC iemMemStackPopU16(PVMCPUCC pVCpu, uint16_t *pu16Value) RT_NOEXCEPT;
1316VBOXSTRICTRC iemMemStackPopU32(PVMCPUCC pVCpu, uint32_t *pu32Value) RT_NOEXCEPT;
1317VBOXSTRICTRC iemMemStackPopU64(PVMCPUCC pVCpu, uint64_t *pu64Value) RT_NOEXCEPT;
1318VBOXSTRICTRC iemMemStackPopU16Ex(PVMCPUCC pVCpu, uint16_t *pu16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
1319VBOXSTRICTRC iemMemStackPopU32Ex(PVMCPUCC pVCpu, uint32_t *pu32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
1320VBOXSTRICTRC iemMemStackPopU64Ex(PVMCPUCC pVCpu, uint64_t *pu64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
1321/** @} */
1322
1323/** @} */
1324
1325RT_C_DECLS_END
1326
1327#endif /* !VMM_INCLUDED_SRC_include_IEMInternal_armv8_h */
1328
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