VirtualBox

source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h@ 102570

Last change on this file since 102570 was 102557, checked in by vboxsync, 15 months ago

VMM/IEM: Try deal with running out of executable memory. bugref:10371

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1/* $Id: IEMInternal.h 102557 2023-12-08 22:13:00Z vboxsync $ */
2/** @file
3 * IEM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2011-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VMM_INCLUDED_SRC_include_IEMInternal_h
29#define VMM_INCLUDED_SRC_include_IEMInternal_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34#include <VBox/vmm/cpum.h>
35#include <VBox/vmm/iem.h>
36#include <VBox/vmm/pgm.h>
37#include <VBox/vmm/stam.h>
38#include <VBox/param.h>
39
40#include <iprt/setjmp-without-sigmask.h>
41#include <iprt/list.h>
42
43
44RT_C_DECLS_BEGIN
45
46
47/** @defgroup grp_iem_int Internals
48 * @ingroup grp_iem
49 * @internal
50 * @{
51 */
52
53/** For expanding symbol in slickedit and other products tagging and
54 * crossreferencing IEM symbols. */
55#ifndef IEM_STATIC
56# define IEM_STATIC static
57#endif
58
59/** @def IEM_WITH_SETJMP
60 * Enables alternative status code handling using setjmps.
61 *
62 * This adds a bit of expense via the setjmp() call since it saves all the
63 * non-volatile registers. However, it eliminates return code checks and allows
64 * for more optimal return value passing (return regs instead of stack buffer).
65 */
66#if defined(DOXYGEN_RUNNING) || defined(RT_OS_WINDOWS) || 1
67# define IEM_WITH_SETJMP
68#endif
69
70/** @def IEM_WITH_THROW_CATCH
71 * Enables using C++ throw/catch as an alternative to setjmp/longjmp in user
72 * mode code when IEM_WITH_SETJMP is in effect.
73 *
74 * With GCC 11.3.1 and code TLB on linux, using throw/catch instead of
75 * setjmp/long resulted in bs2-test-1 running 3.00% faster and all but on test
76 * result value improving by more than 1%. (Best out of three.)
77 *
78 * With Visual C++ 2019 and code TLB on windows, using throw/catch instead of
79 * setjmp/long resulted in bs2-test-1 running 3.68% faster and all but some of
80 * the MMIO and CPUID tests ran noticeably faster. Variation is greater than on
81 * Linux, but it should be quite a bit faster for normal code.
82 */
83#if (defined(__cplusplus) && defined(IEM_WITH_SETJMP) && defined(IN_RING3) && (defined(__GNUC__) || defined(_MSC_VER))) \
84 || defined(DOXYGEN_RUNNING)
85# define IEM_WITH_THROW_CATCH
86#endif
87
88/** @def IEM_DO_LONGJMP
89 *
90 * Wrapper around longjmp / throw.
91 *
92 * @param a_pVCpu The CPU handle.
93 * @param a_rc The status code jump back with / throw.
94 */
95#if defined(IEM_WITH_SETJMP) || defined(DOXYGEN_RUNNING)
96# ifdef IEM_WITH_THROW_CATCH
97# define IEM_DO_LONGJMP(a_pVCpu, a_rc) throw int(a_rc)
98# else
99# define IEM_DO_LONGJMP(a_pVCpu, a_rc) longjmp(*(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf), (a_rc))
100# endif
101#endif
102
103/** For use with IEM function that may do a longjmp (when enabled).
104 *
105 * Visual C++ has trouble longjmp'ing from/over functions with the noexcept
106 * attribute. So, we indicate that function that may be part of a longjmp may
107 * throw "exceptions" and that the compiler should definitely not generate and
108 * std::terminate calling unwind code.
109 *
110 * Here is one example of this ending in std::terminate:
111 * @code{.txt}
11200 00000041`cadfda10 00007ffc`5d5a1f9f ucrtbase!abort+0x4e
11301 00000041`cadfda40 00007ffc`57af229a ucrtbase!terminate+0x1f
11402 00000041`cadfda70 00007ffb`eec91030 VCRUNTIME140!__std_terminate+0xa [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\ehhelpers.cpp @ 192]
11503 00000041`cadfdaa0 00007ffb`eec92c6d VCRUNTIME140_1!_CallSettingFrame+0x20 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\handlers.asm @ 50]
11604 00000041`cadfdad0 00007ffb`eec93ae5 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToState+0x241 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 1085]
11705 00000041`cadfdc00 00007ffb`eec92258 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToEmptyState+0x2d [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 218]
11806 00000041`cadfdc30 00007ffb`eec940e9 VCRUNTIME140_1!__InternalCxxFrameHandler<__FrameHandler4>+0x194 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 304]
11907 00000041`cadfdcd0 00007ffc`5f9f249f VCRUNTIME140_1!__CxxFrameHandler4+0xa9 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 290]
12008 00000041`cadfdd40 00007ffc`5f980939 ntdll!RtlpExecuteHandlerForUnwind+0xf
12109 00000041`cadfdd70 00007ffc`5f9a0edd ntdll!RtlUnwindEx+0x339
1220a 00000041`cadfe490 00007ffc`57aff976 ntdll!RtlUnwind+0xcd
1230b 00000041`cadfea00 00007ffb`e1b5de01 VCRUNTIME140!__longjmp_internal+0xe6 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\longjmp.asm @ 140]
1240c (Inline Function) --------`-------- VBoxVMM!iemOpcodeGetNextU8SlowJmp+0x95 [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 1155]
1250d 00000041`cadfea50 00007ffb`e1b60f6b VBoxVMM!iemOpcodeGetNextU8Jmp+0xc1 [L:\vbox-intern\src\VBox\VMM\include\IEMInline.h @ 402]
1260e 00000041`cadfea90 00007ffb`e1cc6201 VBoxVMM!IEMExecForExits+0xdb [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 10185]
1270f 00000041`cadfec70 00007ffb`e1d0df8d VBoxVMM!EMHistoryExec+0x4f1 [L:\vbox-intern\src\VBox\VMM\VMMAll\EMAll.cpp @ 452]
12810 00000041`cadfed60 00007ffb`e1d0d4c0 VBoxVMM!nemR3WinHandleExitCpuId+0x79d [L:\vbox-intern\src\VBox\VMM\VMMAll\NEMAllNativeTemplate-win.cpp.h @ 1829] @encode
129 @endcode
130 *
131 * @see https://developercommunity.visualstudio.com/t/fragile-behavior-of-longjmp-called-from-noexcept-f/1532859
132 */
133#if defined(IEM_WITH_SETJMP) && (defined(_MSC_VER) || defined(IEM_WITH_THROW_CATCH))
134# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT_EX(false)
135#else
136# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT
137#endif
138
139#define IEM_IMPLEMENTS_TASKSWITCH
140
141/** @def IEM_WITH_3DNOW
142 * Includes the 3DNow decoding. */
143#if (!defined(IEM_WITH_3DNOW) && !defined(IEM_WITHOUT_3DNOW)) || defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
144# define IEM_WITH_3DNOW
145#endif
146
147/** @def IEM_WITH_THREE_0F_38
148 * Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
149#if (!defined(IEM_WITH_THREE_0F_38) && !defined(IEM_WITHOUT_THREE_0F_38)) || defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
150# define IEM_WITH_THREE_0F_38
151#endif
152
153/** @def IEM_WITH_THREE_0F_3A
154 * Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
155#if (!defined(IEM_WITH_THREE_0F_3A) && !defined(IEM_WITHOUT_THREE_0F_3A)) || defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
156# define IEM_WITH_THREE_0F_3A
157#endif
158
159/** @def IEM_WITH_VEX
160 * Includes the VEX decoding. */
161#if (!defined(IEM_WITH_VEX) && !defined(IEM_WITHOUT_VEX)) || defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
162# define IEM_WITH_VEX
163#endif
164
165/** @def IEM_CFG_TARGET_CPU
166 * The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
167 *
168 * By default we allow this to be configured by the user via the
169 * CPUM/GuestCpuName config string, but this comes at a slight cost during
170 * decoding. So, for applications of this code where there is no need to
171 * be dynamic wrt target CPU, just modify this define.
172 */
173#if !defined(IEM_CFG_TARGET_CPU) || defined(DOXYGEN_RUNNING)
174# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
175#endif
176
177//#define IEM_WITH_CODE_TLB // - work in progress
178//#define IEM_WITH_DATA_TLB // - work in progress
179
180
181/** @def IEM_USE_UNALIGNED_DATA_ACCESS
182 * Use unaligned accesses instead of elaborate byte assembly. */
183#if defined(RT_ARCH_AMD64) || defined(RT_ARCH_X86) || defined(DOXYGEN_RUNNING)
184# define IEM_USE_UNALIGNED_DATA_ACCESS
185#endif
186
187//#define IEM_LOG_MEMORY_WRITES
188
189#if !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
190/** Instruction statistics. */
191typedef struct IEMINSTRSTATS
192{
193# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
194# include "IEMInstructionStatisticsTmpl.h"
195# undef IEM_DO_INSTR_STAT
196} IEMINSTRSTATS;
197#else
198struct IEMINSTRSTATS;
199typedef struct IEMINSTRSTATS IEMINSTRSTATS;
200#endif
201/** Pointer to IEM instruction statistics. */
202typedef IEMINSTRSTATS *PIEMINSTRSTATS;
203
204
205/** @name IEMTARGETCPU_EFL_BEHAVIOR_XXX - IEMCPU::aidxTargetCpuEflFlavour
206 * @{ */
207#define IEMTARGETCPU_EFL_BEHAVIOR_NATIVE 0 /**< Native x86 EFLAGS result; Intel EFLAGS when on non-x86 hosts. */
208#define IEMTARGETCPU_EFL_BEHAVIOR_INTEL 1 /**< Intel EFLAGS result. */
209#define IEMTARGETCPU_EFL_BEHAVIOR_AMD 2 /**< AMD EFLAGS result */
210#define IEMTARGETCPU_EFL_BEHAVIOR_RESERVED 3 /**< Reserved/dummy entry slot that's the same as 0. */
211#define IEMTARGETCPU_EFL_BEHAVIOR_MASK 3 /**< For masking the index before use. */
212/** Selects the right variant from a_aArray.
213 * pVCpu is implicit in the caller context. */
214#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT(a_aArray) \
215 (a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[1] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
216/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for when no native worker can
217 * be used because the host CPU does not support the operation. */
218#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_NON_NATIVE(a_aArray) \
219 (a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
220/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for a two dimentional
221 * array paralleling IEMCPU::aidxTargetCpuEflFlavour and a single bit index
222 * into the two.
223 * @sa IEM_SELECT_NATIVE_OR_FALLBACK */
224#if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)
225# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
226 (a_aaArray[a_fNative][pVCpu->iem.s.aidxTargetCpuEflFlavour[a_fNative] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
227#else
228# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
229 (a_aaArray[0][pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
230#endif
231/** @} */
232
233/**
234 * Picks @a a_pfnNative or @a a_pfnFallback according to the host CPU feature
235 * indicator given by @a a_fCpumFeatureMember (CPUMFEATURES member).
236 *
237 * On non-x86 hosts, this will shortcut to the fallback w/o checking the
238 * indicator.
239 *
240 * @sa IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX
241 */
242#if (defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
243# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) \
244 (g_CpumHostFeatures.s.a_fCpumFeatureMember ? a_pfnNative : a_pfnFallback)
245#else
246# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) (a_pfnFallback)
247#endif
248
249
250/**
251 * Extended operand mode that includes a representation of 8-bit.
252 *
253 * This is used for packing down modes when invoking some C instruction
254 * implementations.
255 */
256typedef enum IEMMODEX
257{
258 IEMMODEX_16BIT = IEMMODE_16BIT,
259 IEMMODEX_32BIT = IEMMODE_32BIT,
260 IEMMODEX_64BIT = IEMMODE_64BIT,
261 IEMMODEX_8BIT
262} IEMMODEX;
263AssertCompileSize(IEMMODEX, 4);
264
265
266/**
267 * Branch types.
268 */
269typedef enum IEMBRANCH
270{
271 IEMBRANCH_JUMP = 1,
272 IEMBRANCH_CALL,
273 IEMBRANCH_TRAP,
274 IEMBRANCH_SOFTWARE_INT,
275 IEMBRANCH_HARDWARE_INT
276} IEMBRANCH;
277AssertCompileSize(IEMBRANCH, 4);
278
279
280/**
281 * INT instruction types.
282 */
283typedef enum IEMINT
284{
285 /** INT n instruction (opcode 0xcd imm). */
286 IEMINT_INTN = 0,
287 /** Single byte INT3 instruction (opcode 0xcc). */
288 IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
289 /** Single byte INTO instruction (opcode 0xce). */
290 IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
291 /** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
292 IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
293} IEMINT;
294AssertCompileSize(IEMINT, 4);
295
296
297/**
298 * A FPU result.
299 */
300typedef struct IEMFPURESULT
301{
302 /** The output value. */
303 RTFLOAT80U r80Result;
304 /** The output status. */
305 uint16_t FSW;
306} IEMFPURESULT;
307AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
308/** Pointer to a FPU result. */
309typedef IEMFPURESULT *PIEMFPURESULT;
310/** Pointer to a const FPU result. */
311typedef IEMFPURESULT const *PCIEMFPURESULT;
312
313
314/**
315 * A FPU result consisting of two output values and FSW.
316 */
317typedef struct IEMFPURESULTTWO
318{
319 /** The first output value. */
320 RTFLOAT80U r80Result1;
321 /** The output status. */
322 uint16_t FSW;
323 /** The second output value. */
324 RTFLOAT80U r80Result2;
325} IEMFPURESULTTWO;
326AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
327AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
328/** Pointer to a FPU result consisting of two output values and FSW. */
329typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
330/** Pointer to a const FPU result consisting of two output values and FSW. */
331typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
332
333
334/**
335 * IEM TLB entry.
336 *
337 * Lookup assembly:
338 * @code{.asm}
339 ; Calculate tag.
340 mov rax, [VA]
341 shl rax, 16
342 shr rax, 16 + X86_PAGE_SHIFT
343 or rax, [uTlbRevision]
344
345 ; Do indexing.
346 movzx ecx, al
347 lea rcx, [pTlbEntries + rcx]
348
349 ; Check tag.
350 cmp [rcx + IEMTLBENTRY.uTag], rax
351 jne .TlbMiss
352
353 ; Check access.
354 mov rax, ACCESS_FLAGS | MAPPING_R3_NOT_VALID | 0xffffff00
355 and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
356 cmp rax, [uTlbPhysRev]
357 jne .TlbMiss
358
359 ; Calc address and we're done.
360 mov eax, X86_PAGE_OFFSET_MASK
361 and eax, [VA]
362 or rax, [rcx + IEMTLBENTRY.pMappingR3]
363 %ifdef VBOX_WITH_STATISTICS
364 inc qword [cTlbHits]
365 %endif
366 jmp .Done
367
368 .TlbMiss:
369 mov r8d, ACCESS_FLAGS
370 mov rdx, [VA]
371 mov rcx, [pVCpu]
372 call iemTlbTypeMiss
373 .Done:
374
375 @endcode
376 *
377 */
378typedef struct IEMTLBENTRY
379{
380 /** The TLB entry tag.
381 * Bits 35 thru 0 are made up of the virtual address shifted right 12 bits, this
382 * is ASSUMING a virtual address width of 48 bits.
383 *
384 * Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
385 *
386 * The TLB lookup code uses the current TLB revision, which won't ever be zero,
387 * enabling an extremely cheap TLB invalidation most of the time. When the TLB
388 * revision wraps around though, the tags needs to be zeroed.
389 *
390 * @note Try use SHRD instruction? After seeing
391 * https://gmplib.org/~tege/x86-timing.pdf, maybe not.
392 *
393 * @todo This will need to be reorganized for 57-bit wide virtual address and
394 * PCID (currently 12 bits) and ASID (currently 6 bits) support. We'll
395 * have to move the TLB entry versioning entirely to the
396 * fFlagsAndPhysRev member then, 57 bit wide VAs means we'll only have
397 * 19 bits left (64 - 57 + 12 = 19) and they'll almost entire be
398 * consumed by PCID and ASID (12 + 6 = 18).
399 */
400 uint64_t uTag;
401 /** Access flags and physical TLB revision.
402 *
403 * - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
404 * - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
405 * - Bit 2 - page tables - not user (complemented X86_PTE_US).
406 * - Bit 3 - pgm phys/virt - not directly writable.
407 * - Bit 4 - pgm phys page - not directly readable.
408 * - Bit 5 - page tables - not accessed (complemented X86_PTE_A).
409 * - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
410 * - Bit 7 - tlb entry - pMappingR3 member not valid.
411 * - Bits 63 thru 8 are used for the physical TLB revision number.
412 *
413 * We're using complemented bit meanings here because it makes it easy to check
414 * whether special action is required. For instance a user mode write access
415 * would do a "TEST fFlags, (X86_PTE_RW | X86_PTE_US | X86_PTE_D)" and a
416 * non-zero result would mean special handling needed because either it wasn't
417 * writable, or it wasn't user, or the page wasn't dirty. A user mode read
418 * access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
419 * need to check any PTE flag.
420 */
421 uint64_t fFlagsAndPhysRev;
422 /** The guest physical page address. */
423 uint64_t GCPhys;
424 /** Pointer to the ring-3 mapping. */
425 R3PTRTYPE(uint8_t *) pbMappingR3;
426#if HC_ARCH_BITS == 32
427 uint32_t u32Padding1;
428#endif
429} IEMTLBENTRY;
430AssertCompileSize(IEMTLBENTRY, 32);
431/** Pointer to an IEM TLB entry. */
432typedef IEMTLBENTRY *PIEMTLBENTRY;
433
434/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
435 * @{ */
436#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /**< Page tables: Not executable. */
437#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /**< Page tables: Not writable. */
438#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /**< Page tables: Not user accessible (supervisor only). */
439#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /**< Phys page: Not writable (access handler, ROM, whatever). */
440#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /**< Phys page: Not readable (MMIO / access handler, ROM) */
441#define IEMTLBE_F_PT_NO_ACCESSED RT_BIT_64(5) /**< Phys tables: Not accessed (need to be marked accessed). */
442#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /**< Page tables: Not dirty (needs to be made dirty on write). */
443#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(7) /**< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. */
444#define IEMTLBE_F_PG_UNASSIGNED RT_BIT_64(8) /**< Phys page: Unassigned memory (not RAM, ROM, MMIO2 or MMIO). */
445#define IEMTLBE_F_PG_CODE_PAGE RT_BIT_64(9) /**< Phys page: Code page. */
446#define IEMTLBE_F_PHYS_REV UINT64_C(0xfffffffffffffc00) /**< Physical revision mask. @sa IEMTLB_PHYS_REV_INCR */
447/** @} */
448
449
450/**
451 * An IEM TLB.
452 *
453 * We've got two of these, one for data and one for instructions.
454 */
455typedef struct IEMTLB
456{
457 /** The TLB entries.
458 * We've choosen 256 because that way we can obtain the result directly from a
459 * 8-bit register without an additional AND instruction. */
460 IEMTLBENTRY aEntries[256];
461 /** The TLB revision.
462 * This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
463 * by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
464 * the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
465 * (The revision zero indicates an invalid TLB entry.)
466 *
467 * The initial value is choosen to cause an early wraparound. */
468 uint64_t uTlbRevision;
469 /** The TLB physical address revision - shadow of PGM variable.
470 *
471 * This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
472 * incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
473 * a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
474 * as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
475 *
476 * The initial value is choosen to cause an early wraparound. */
477 uint64_t volatile uTlbPhysRev;
478
479 /* Statistics: */
480
481 /** TLB hits (VBOX_WITH_STATISTICS only). */
482 uint64_t cTlbHits;
483 /** TLB misses. */
484 uint32_t cTlbMisses;
485 /** Slow read path. */
486 uint32_t cTlbSlowReadPath;
487 /** Safe read path. */
488 uint32_t cTlbSafeReadPath;
489 /** Safe write path. */
490 uint32_t cTlbSafeWritePath;
491#if 0
492 /** TLB misses because of tag mismatch. */
493 uint32_t cTlbMissesTag;
494 /** TLB misses because of virtual access violation. */
495 uint32_t cTlbMissesVirtAccess;
496 /** TLB misses because of dirty bit. */
497 uint32_t cTlbMissesDirty;
498 /** TLB misses because of MMIO */
499 uint32_t cTlbMissesMmio;
500 /** TLB misses because of write access handlers. */
501 uint32_t cTlbMissesWriteHandler;
502 /** TLB misses because no r3(/r0) mapping. */
503 uint32_t cTlbMissesMapping;
504#endif
505 /** Alignment padding. */
506 uint32_t au32Padding[6];
507} IEMTLB;
508AssertCompileSizeAlignment(IEMTLB, 64);
509/** IEMTLB::uTlbRevision increment. */
510#define IEMTLB_REVISION_INCR RT_BIT_64(36)
511/** IEMTLB::uTlbRevision mask. */
512#define IEMTLB_REVISION_MASK (~(RT_BIT_64(36) - 1))
513/** IEMTLB::uTlbPhysRev increment.
514 * @sa IEMTLBE_F_PHYS_REV */
515#define IEMTLB_PHYS_REV_INCR RT_BIT_64(10)
516/**
517 * Calculates the TLB tag for a virtual address.
518 * @returns Tag value for indexing and comparing with IEMTLB::uTag.
519 * @param a_pTlb The TLB.
520 * @param a_GCPtr The virtual address. Must be RTGCPTR or same size or
521 * the clearing of the top 16 bits won't work (if 32-bit
522 * we'll end up with mostly zeros).
523 */
524#define IEMTLB_CALC_TAG(a_pTlb, a_GCPtr) ( IEMTLB_CALC_TAG_NO_REV(a_GCPtr) | (a_pTlb)->uTlbRevision )
525/**
526 * Calculates the TLB tag for a virtual address but without TLB revision.
527 * @returns Tag value for indexing and comparing with IEMTLB::uTag.
528 * @param a_GCPtr The virtual address. Must be RTGCPTR or same size or
529 * the clearing of the top 16 bits won't work (if 32-bit
530 * we'll end up with mostly zeros).
531 */
532#define IEMTLB_CALC_TAG_NO_REV(a_GCPtr) ( (((a_GCPtr) << 16) >> (GUEST_PAGE_SHIFT + 16)) )
533/**
534 * Converts a TLB tag value into a TLB index.
535 * @returns Index into IEMTLB::aEntries.
536 * @param a_uTag Value returned by IEMTLB_CALC_TAG.
537 */
538#define IEMTLB_TAG_TO_INDEX(a_uTag) ( (uint8_t)(a_uTag) )
539/**
540 * Converts a TLB tag value into a TLB index.
541 * @returns Index into IEMTLB::aEntries.
542 * @param a_pTlb The TLB.
543 * @param a_uTag Value returned by IEMTLB_CALC_TAG.
544 */
545#define IEMTLB_TAG_TO_ENTRY(a_pTlb, a_uTag) ( &(a_pTlb)->aEntries[IEMTLB_TAG_TO_INDEX(a_uTag)] )
546
547
548/** @name IEM_MC_F_XXX - MC block flags/clues.
549 * @todo Merge with IEM_CIMPL_F_XXX
550 * @{ */
551#define IEM_MC_F_ONLY_8086 RT_BIT_32(0)
552#define IEM_MC_F_MIN_186 RT_BIT_32(1)
553#define IEM_MC_F_MIN_286 RT_BIT_32(2)
554#define IEM_MC_F_NOT_286_OR_OLDER IEM_MC_F_MIN_386
555#define IEM_MC_F_MIN_386 RT_BIT_32(3)
556#define IEM_MC_F_MIN_486 RT_BIT_32(4)
557#define IEM_MC_F_MIN_PENTIUM RT_BIT_32(5)
558#define IEM_MC_F_MIN_PENTIUM_II IEM_MC_F_MIN_PENTIUM
559#define IEM_MC_F_MIN_CORE IEM_MC_F_MIN_PENTIUM
560#define IEM_MC_F_64BIT RT_BIT_32(6)
561#define IEM_MC_F_NOT_64BIT RT_BIT_32(7)
562/** This is set by IEMAllN8vePython.py to indicate a variation without the
563 * flags-clearing-and-checking, when there is also a variation with that.
564 * @note Do not use this manully, it's only for python and for testing in
565 * the native recompiler! */
566#define IEM_MC_F_WITHOUT_FLAGS RT_BIT_32(8)
567/** @} */
568
569/** @name IEM_CIMPL_F_XXX - State change clues for CIMPL calls.
570 *
571 * These clues are mainly for the recompiler, so that it can emit correct code.
572 *
573 * They are processed by the python script and which also automatically
574 * calculates flags for MC blocks based on the statements, extending the use of
575 * these flags to describe MC block behavior to the recompiler core. The python
576 * script pass the flags to the IEM_MC2_END_EMIT_CALLS macro, but mainly for
577 * error checking purposes. The script emits the necessary fEndTb = true and
578 * similar statements as this reduces compile time a tiny bit.
579 *
580 * @{ */
581/** Flag set if direct branch, clear if absolute or indirect. */
582#define IEM_CIMPL_F_BRANCH_DIRECT RT_BIT_32(0)
583/** Flag set if indirect branch, clear if direct or relative.
584 * This is also used for all system control transfers (SYSCALL, SYSRET, INT, ++)
585 * as well as for return instructions (RET, IRET, RETF). */
586#define IEM_CIMPL_F_BRANCH_INDIRECT RT_BIT_32(1)
587/** Flag set if relative branch, clear if absolute or indirect. */
588#define IEM_CIMPL_F_BRANCH_RELATIVE RT_BIT_32(2)
589/** Flag set if conditional branch, clear if unconditional. */
590#define IEM_CIMPL_F_BRANCH_CONDITIONAL RT_BIT_32(3)
591/** Flag set if it's a far branch (changes CS). */
592#define IEM_CIMPL_F_BRANCH_FAR RT_BIT_32(4)
593/** Convenience: Testing any kind of branch. */
594#define IEM_CIMPL_F_BRANCH_ANY (IEM_CIMPL_F_BRANCH_DIRECT | IEM_CIMPL_F_BRANCH_INDIRECT | IEM_CIMPL_F_BRANCH_RELATIVE)
595
596/** Execution flags may change (IEMCPU::fExec). */
597#define IEM_CIMPL_F_MODE RT_BIT_32(5)
598/** May change significant portions of RFLAGS. */
599#define IEM_CIMPL_F_RFLAGS RT_BIT_32(6)
600/** May change the status bits (X86_EFL_STATUS_BITS) in RFLAGS. */
601#define IEM_CIMPL_F_STATUS_FLAGS RT_BIT_32(7)
602/** May trigger interrupt shadowing. */
603#define IEM_CIMPL_F_INHIBIT_SHADOW RT_BIT_32(8)
604/** May enable interrupts, so recheck IRQ immediately afterwards executing
605 * the instruction. */
606#define IEM_CIMPL_F_CHECK_IRQ_AFTER RT_BIT_32(9)
607/** May disable interrupts, so recheck IRQ immediately before executing the
608 * instruction. */
609#define IEM_CIMPL_F_CHECK_IRQ_BEFORE RT_BIT_32(10)
610/** Convenience: Check for IRQ both before and after an instruction. */
611#define IEM_CIMPL_F_CHECK_IRQ_BEFORE_AND_AFTER (IEM_CIMPL_F_CHECK_IRQ_BEFORE | IEM_CIMPL_F_CHECK_IRQ_AFTER)
612/** May trigger a VM exit (treated like IEM_CIMPL_F_MODE atm). */
613#define IEM_CIMPL_F_VMEXIT RT_BIT_32(11)
614/** May modify FPU state.
615 * @todo Not sure if this is useful yet. */
616#define IEM_CIMPL_F_FPU RT_BIT_32(12)
617/** REP prefixed instruction which may yield before updating PC.
618 * @todo Not sure if this is useful, REP functions now return non-zero
619 * status if they don't update the PC. */
620#define IEM_CIMPL_F_REP RT_BIT_32(13)
621/** I/O instruction.
622 * @todo Not sure if this is useful yet. */
623#define IEM_CIMPL_F_IO RT_BIT_32(14)
624/** Force end of TB after the instruction. */
625#define IEM_CIMPL_F_END_TB RT_BIT_32(15)
626/** Flag set if a branch may also modify the stack (push/pop return address). */
627#define IEM_CIMPL_F_BRANCH_STACK RT_BIT_32(16)
628/** Flag set if a branch may also modify the stack (push/pop return address)
629 * and switch it (load/restore SS:RSP). */
630#define IEM_CIMPL_F_BRANCH_STACK_FAR RT_BIT_32(17)
631/** Convenience: Raise exception (technically unnecessary, since it shouldn't return VINF_SUCCESS). */
632#define IEM_CIMPL_F_XCPT \
633 (IEM_CIMPL_F_BRANCH_INDIRECT | IEM_CIMPL_F_BRANCH_FAR | IEM_CIMPL_F_BRANCH_STACK_FAR \
634 | IEM_CIMPL_F_MODE | IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_VMEXIT)
635
636/** The block calls a C-implementation instruction function with two implicit arguments.
637 * Mutually exclusive with IEM_CIMPL_F_CALLS_AIMPL and
638 * IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
639 * @note The python scripts will add this is missing. */
640#define IEM_CIMPL_F_CALLS_CIMPL RT_BIT_32(18)
641/** The block calls an ASM-implementation instruction function.
642 * Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL and
643 * IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
644 * @note The python scripts will add this is missing. */
645#define IEM_CIMPL_F_CALLS_AIMPL RT_BIT_32(19)
646/** The block calls an ASM-implementation instruction function with an implicit
647 * X86FXSTATE pointer argument.
648 * Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL and IEM_CIMPL_F_CALLS_AIMPL.
649 * @note The python scripts will add this is missing. */
650#define IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE RT_BIT_32(20)
651/** @} */
652
653
654/** @name IEM_F_XXX - Execution mode flags (IEMCPU::fExec, IEMTB::fFlags).
655 *
656 * These flags are set when entering IEM and adjusted as code is executed, such
657 * that they will always contain the current values as instructions are
658 * finished.
659 *
660 * In recompiled execution mode, (most of) these flags are included in the
661 * translation block selection key and stored in IEMTB::fFlags alongside the
662 * IEMTB_F_XXX flags. The latter flags uses bits 31 thru 24, which are all zero
663 * in IEMCPU::fExec.
664 *
665 * @{ */
666/** Mode: The block target mode mask. */
667#define IEM_F_MODE_MASK UINT32_C(0x0000001f)
668/** Mode: The IEMMODE part of the IEMTB_F_MODE_MASK value. */
669#define IEM_F_MODE_CPUMODE_MASK UINT32_C(0x00000003)
670/** X86 Mode: Bit used to indicating pre-386 CPU in 16-bit mode (for eliminating
671 * conditional in EIP/IP updating), and flat wide open CS, SS, DS, and ES in
672 * 32-bit mode (for simplifying most memory accesses). */
673#define IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK UINT32_C(0x00000004)
674/** X86 Mode: Bit indicating protected mode, real mode (or SMM) when not set. */
675#define IEM_F_MODE_X86_PROT_MASK UINT32_C(0x00000008)
676/** X86 Mode: Bit used to indicate virtual 8086 mode (only 16-bit). */
677#define IEM_F_MODE_X86_V86_MASK UINT32_C(0x00000010)
678
679/** X86 Mode: 16-bit on 386 or later. */
680#define IEM_F_MODE_X86_16BIT UINT32_C(0x00000000)
681/** X86 Mode: 80286, 80186 and 8086/88 targetting blocks (EIP update opt). */
682#define IEM_F_MODE_X86_16BIT_PRE_386 UINT32_C(0x00000004)
683/** X86 Mode: 16-bit protected mode on 386 or later. */
684#define IEM_F_MODE_X86_16BIT_PROT UINT32_C(0x00000008)
685/** X86 Mode: 16-bit protected mode on 386 or later. */
686#define IEM_F_MODE_X86_16BIT_PROT_PRE_386 UINT32_C(0x0000000c)
687/** X86 Mode: 16-bit virtual 8086 protected mode (on 386 or later). */
688#define IEM_F_MODE_X86_16BIT_PROT_V86 UINT32_C(0x00000018)
689
690/** X86 Mode: 32-bit on 386 or later. */
691#define IEM_F_MODE_X86_32BIT UINT32_C(0x00000001)
692/** X86 Mode: 32-bit mode with wide open flat CS, SS, DS and ES. */
693#define IEM_F_MODE_X86_32BIT_FLAT UINT32_C(0x00000005)
694/** X86 Mode: 32-bit protected mode. */
695#define IEM_F_MODE_X86_32BIT_PROT UINT32_C(0x00000009)
696/** X86 Mode: 32-bit protected mode with wide open flat CS, SS, DS and ES. */
697#define IEM_F_MODE_X86_32BIT_PROT_FLAT UINT32_C(0x0000000d)
698
699/** X86 Mode: 64-bit (includes protected, but not the flat bit). */
700#define IEM_F_MODE_X86_64BIT UINT32_C(0x0000000a)
701
702
703/** Bypass access handlers when set. */
704#define IEM_F_BYPASS_HANDLERS UINT32_C(0x00010000)
705/** Have pending hardware instruction breakpoints. */
706#define IEM_F_PENDING_BRK_INSTR UINT32_C(0x00020000)
707/** Have pending hardware data breakpoints. */
708#define IEM_F_PENDING_BRK_DATA UINT32_C(0x00040000)
709
710/** X86: Have pending hardware I/O breakpoints. */
711#define IEM_F_PENDING_BRK_X86_IO UINT32_C(0x00000400)
712/** X86: Disregard the lock prefix (implied or not) when set. */
713#define IEM_F_X86_DISREGARD_LOCK UINT32_C(0x00000800)
714
715/** Pending breakpoint mask (what iemCalcExecDbgFlags works out). */
716#define IEM_F_PENDING_BRK_MASK (IEM_F_PENDING_BRK_INSTR | IEM_F_PENDING_BRK_DATA | IEM_F_PENDING_BRK_X86_IO)
717
718/** Caller configurable options. */
719#define IEM_F_USER_OPTS (IEM_F_BYPASS_HANDLERS | IEM_F_X86_DISREGARD_LOCK)
720
721/** X86: The current protection level (CPL) shift factor. */
722#define IEM_F_X86_CPL_SHIFT 8
723/** X86: The current protection level (CPL) mask. */
724#define IEM_F_X86_CPL_MASK UINT32_C(0x00000300)
725/** X86: The current protection level (CPL) shifted mask. */
726#define IEM_F_X86_CPL_SMASK UINT32_C(0x00000003)
727
728/** X86 execution context.
729 * The IEM_F_X86_CTX_XXX values are individual flags that can be combined (with
730 * the exception of IEM_F_X86_CTX_NORMAL). This allows running VMs from SMM
731 * mode. */
732#define IEM_F_X86_CTX_MASK UINT32_C(0x0000f000)
733/** X86 context: Plain regular execution context. */
734#define IEM_F_X86_CTX_NORMAL UINT32_C(0x00000000)
735/** X86 context: VT-x enabled. */
736#define IEM_F_X86_CTX_VMX UINT32_C(0x00001000)
737/** X86 context: AMD-V enabled. */
738#define IEM_F_X86_CTX_SVM UINT32_C(0x00002000)
739/** X86 context: In AMD-V or VT-x guest mode. */
740#define IEM_F_X86_CTX_IN_GUEST UINT32_C(0x00004000)
741/** X86 context: System management mode (SMM). */
742#define IEM_F_X86_CTX_SMM UINT32_C(0x00008000)
743
744/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
745 * iemRegFinishClearingRF() most for most situations (CPUMCTX_DBG_HIT_DRX_MASK
746 * and CPUMCTX_DBG_DBGF_MASK are covered by the IEM_F_PENDING_BRK_XXX bits
747 * alread). */
748
749/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
750 * iemRegFinishClearingRF() most for most situations
751 * (CPUMCTX_DBG_HIT_DRX_MASK and CPUMCTX_DBG_DBGF_MASK are covered by
752 * the IEM_F_PENDING_BRK_XXX bits alread). */
753
754/** @} */
755
756
757/** @name IEMTB_F_XXX - Translation block flags (IEMTB::fFlags).
758 *
759 * Extends the IEM_F_XXX flags (subject to IEMTB_F_IEM_F_MASK) to make up the
760 * translation block flags. The combined flag mask (subject to
761 * IEMTB_F_KEY_MASK) is used as part of the lookup key for translation blocks.
762 *
763 * @{ */
764/** Mask of IEM_F_XXX flags included in IEMTB_F_XXX. */
765#define IEMTB_F_IEM_F_MASK UINT32_C(0x00ffffff)
766
767/** Type: The block type mask. */
768#define IEMTB_F_TYPE_MASK UINT32_C(0x03000000)
769/** Type: Purly threaded recompiler (via tables). */
770#define IEMTB_F_TYPE_THREADED UINT32_C(0x01000000)
771/** Type: Native recompilation. */
772#define IEMTB_F_TYPE_NATIVE UINT32_C(0x02000000)
773
774/** Set when we're starting the block in an "interrupt shadow".
775 * We don't need to distingish between the two types of this mask, thus the one.
776 * @see CPUMCTX_INHIBIT_SHADOW, CPUMIsInInterruptShadow() */
777#define IEMTB_F_INHIBIT_SHADOW UINT32_C(0x04000000)
778/** Set when we're currently inhibiting NMIs
779 * @see CPUMCTX_INHIBIT_NMI, CPUMAreInterruptsInhibitedByNmi() */
780#define IEMTB_F_INHIBIT_NMI UINT32_C(0x08000000)
781
782/** Checks that EIP/IP is wihin CS.LIM before each instruction. Used when
783 * we're close the limit before starting a TB, as determined by
784 * iemGetTbFlagsForCurrentPc(). */
785#define IEMTB_F_CS_LIM_CHECKS UINT32_C(0x10000000)
786
787/** Mask of the IEMTB_F_XXX flags that are part of the TB lookup key.
788 * @note We skip the CPL as we don't currently generate ring-specific code,
789 * that's all handled in CIMPL functions.
790 *
791 * For the same reasons, we skip all of IEM_F_X86_CTX_MASK, with the
792 * exception of SMM (which we don't implement). */
793#define IEMTB_F_KEY_MASK ( (UINT32_MAX & ~(IEM_F_X86_CTX_MASK | IEM_F_X86_CPL_MASK | IEMTB_F_TYPE_MASK)) \
794 | IEM_F_X86_CTX_SMM)
795/** @} */
796
797AssertCompile( (IEM_F_MODE_X86_16BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
798AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
799AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_PROT_MASK));
800AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_V86_MASK));
801AssertCompile( (IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
802AssertCompile( IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
803AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_PROT_MASK));
804AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
805AssertCompile( (IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
806AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
807AssertCompile( IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
808AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_V86_MASK));
809AssertCompile( (IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
810AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
811AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_PROT_MASK);
812AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
813AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_PROT_MASK);
814AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
815AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_V86_MASK);
816
817AssertCompile( (IEM_F_MODE_X86_32BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
818AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
819AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_PROT_MASK));
820AssertCompile( (IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
821AssertCompile( IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
822AssertCompile(!(IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_PROT_MASK));
823AssertCompile( (IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
824AssertCompile(!(IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
825AssertCompile( IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
826AssertCompile( (IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
827AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
828AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_PROT_MASK);
829
830AssertCompile( (IEM_F_MODE_X86_64BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_64BIT);
831AssertCompile( IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_PROT_MASK);
832AssertCompile(!(IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
833
834/** Native instruction type for use with the native code generator.
835 * This is a byte (uint8_t) for x86 and amd64 and uint32_t for the other(s). */
836#if defined(RT_ARCH_AMD64) || defined(RT_ARCH_X86)
837typedef uint8_t IEMNATIVEINSTR;
838#else
839typedef uint32_t IEMNATIVEINSTR;
840#endif
841/** Pointer to a native instruction unit. */
842typedef IEMNATIVEINSTR *PIEMNATIVEINSTR;
843/** Pointer to a const native instruction unit. */
844typedef IEMNATIVEINSTR const *PCIEMNATIVEINSTR;
845
846/**
847 * A call for the threaded call table.
848 */
849typedef struct IEMTHRDEDCALLENTRY
850{
851 /** The function to call (IEMTHREADEDFUNCS). */
852 uint16_t enmFunction;
853 /** Instruction number in the TB (for statistics). */
854 uint8_t idxInstr;
855 uint8_t uUnused0;
856
857 /** Offset into IEMTB::pabOpcodes. */
858 uint16_t offOpcode;
859 /** The opcode length. */
860 uint8_t cbOpcode;
861 /** Index in to IEMTB::aRanges. */
862 uint8_t idxRange;
863
864 /** Generic parameters. */
865 uint64_t auParams[3];
866} IEMTHRDEDCALLENTRY;
867AssertCompileSize(IEMTHRDEDCALLENTRY, sizeof(uint64_t) * 4);
868/** Pointer to a threaded call entry. */
869typedef struct IEMTHRDEDCALLENTRY *PIEMTHRDEDCALLENTRY;
870/** Pointer to a const threaded call entry. */
871typedef IEMTHRDEDCALLENTRY const *PCIEMTHRDEDCALLENTRY;
872
873/**
874 * Native IEM TB 'function' typedef.
875 *
876 * This will throw/longjmp on occation.
877 *
878 * @note AMD64 doesn't have that many non-volatile registers and does sport
879 * 32-bit address displacments, so we don't need pCtx.
880 *
881 * On ARM64 pCtx allows us to directly address the whole register
882 * context without requiring a separate indexing register holding the
883 * offset. This saves an instruction loading the offset for each guest
884 * CPU context access, at the cost of a non-volatile register.
885 * Fortunately, ARM64 has quite a lot more registers.
886 */
887typedef
888#ifdef RT_ARCH_AMD64
889int FNIEMTBNATIVE(PVMCPUCC pVCpu)
890#else
891int FNIEMTBNATIVE(PVMCPUCC pVCpu, PCPUMCTX pCtx)
892#endif
893#if RT_CPLUSPLUS_PREREQ(201700)
894 IEM_NOEXCEPT_MAY_LONGJMP
895#endif
896 ;
897/** Pointer to a native IEM TB entry point function.
898 * This will throw/longjmp on occation. */
899typedef FNIEMTBNATIVE *PFNIEMTBNATIVE;
900
901
902/**
903 * Translation block debug info entry type.
904 */
905typedef enum IEMTBDBGENTRYTYPE
906{
907 kIemTbDbgEntryType_Invalid = 0,
908 /** The entry is for marking a native code position.
909 * Entries following this all apply to this position. */
910 kIemTbDbgEntryType_NativeOffset,
911 /** The entry is for a new guest instruction. */
912 kIemTbDbgEntryType_GuestInstruction,
913 /** Marks the start of a threaded call. */
914 kIemTbDbgEntryType_ThreadedCall,
915 /** Marks the location of a label. */
916 kIemTbDbgEntryType_Label,
917 /** Info about a host register shadowing a guest register. */
918 kIemTbDbgEntryType_GuestRegShadowing,
919 kIemTbDbgEntryType_End
920} IEMTBDBGENTRYTYPE;
921
922/**
923 * Translation block debug info entry.
924 */
925typedef union IEMTBDBGENTRY
926{
927 /** Plain 32-bit view. */
928 uint32_t u;
929
930 /** Generic view for getting at the type field. */
931 struct
932 {
933 /** IEMTBDBGENTRYTYPE */
934 uint32_t uType : 4;
935 uint32_t uTypeSpecific : 28;
936 } Gen;
937
938 struct
939 {
940 /** kIemTbDbgEntryType_ThreadedCall1. */
941 uint32_t uType : 4;
942 /** Native code offset. */
943 uint32_t offNative : 28;
944 } NativeOffset;
945
946 struct
947 {
948 /** kIemTbDbgEntryType_GuestInstruction. */
949 uint32_t uType : 4;
950 uint32_t uUnused : 4;
951 /** The IEM_F_XXX flags. */
952 uint32_t fExec : 24;
953 } GuestInstruction;
954
955 struct
956 {
957 /* kIemTbDbgEntryType_ThreadedCall. */
958 uint32_t uType : 4;
959 /** Set if the call was recompiled to native code, clear if just calling
960 * threaded function. */
961 uint32_t fRecompiled : 1;
962 uint32_t uUnused : 11;
963 /** The threaded call number (IEMTHREADEDFUNCS). */
964 uint32_t enmCall : 16;
965 } ThreadedCall;
966
967 struct
968 {
969 /* kIemTbDbgEntryType_Label. */
970 uint32_t uType : 4;
971 uint32_t uUnused : 4;
972 /** The label type (IEMNATIVELABELTYPE). */
973 uint32_t enmLabel : 8;
974 /** The label data. */
975 uint32_t uData : 16;
976 } Label;
977
978 struct
979 {
980 /* kIemTbDbgEntryType_GuestRegShadowing. */
981 uint32_t uType : 4;
982 uint32_t uUnused : 4;
983 /** The guest register being shadowed (IEMNATIVEGSTREG). */
984 uint32_t idxGstReg : 8;
985 /** The host new register number, UINT8_MAX if dropped. */
986 uint32_t idxHstReg : 8;
987 /** The previous host register number, UINT8_MAX if new. */
988 uint32_t idxHstRegPrev : 8;
989 } GuestRegShadowing;
990} IEMTBDBGENTRY;
991AssertCompileSize(IEMTBDBGENTRY, sizeof(uint32_t));
992/** Pointer to a debug info entry. */
993typedef IEMTBDBGENTRY *PIEMTBDBGENTRY;
994/** Pointer to a const debug info entry. */
995typedef IEMTBDBGENTRY const *PCIEMTBDBGENTRY;
996
997/**
998 * Translation block debug info.
999 */
1000typedef struct IEMTBDBG
1001{
1002 /** Number of entries in aEntries. */
1003 uint32_t cEntries;
1004 /** Debug info entries. */
1005 RT_FLEXIBLE_ARRAY_EXTENSION
1006 IEMTBDBGENTRY aEntries[RT_FLEXIBLE_ARRAY];
1007} IEMTBDBG;
1008/** Pointer to TB debug info. */
1009typedef IEMTBDBG *PIEMTBDBG;
1010/** Pointer to const TB debug info. */
1011typedef IEMTBDBG const *PCIEMTBDBG;
1012
1013
1014/**
1015 * Translation block.
1016 *
1017 * The current plan is to just keep TBs and associated lookup hash table private
1018 * to each VCpu as that simplifies TB removal greatly (no races) and generally
1019 * avoids using expensive atomic primitives for updating lists and stuff.
1020 */
1021#pragma pack(2) /* to prevent the Thrd structure from being padded unnecessarily */
1022typedef struct IEMTB
1023{
1024 /** Next block with the same hash table entry. */
1025 struct IEMTB *pNext;
1026 /** Usage counter. */
1027 uint32_t cUsed;
1028 /** The IEMCPU::msRecompilerPollNow last time it was used. */
1029 uint32_t msLastUsed;
1030
1031 /** @name What uniquely identifies the block.
1032 * @{ */
1033 RTGCPHYS GCPhysPc;
1034 /** IEMTB_F_XXX (i.e. IEM_F_XXX ++). */
1035 uint32_t fFlags;
1036 union
1037 {
1038 struct
1039 {
1040 /**< Relevant CS X86DESCATTR_XXX bits. */
1041 uint16_t fAttr;
1042 } x86;
1043 };
1044 /** @} */
1045
1046 /** Number of opcode ranges. */
1047 uint8_t cRanges;
1048 /** Statistics: Number of instructions in the block. */
1049 uint8_t cInstructions;
1050
1051 /** Type specific info. */
1052 union
1053 {
1054 struct
1055 {
1056 /** The call sequence table. */
1057 PIEMTHRDEDCALLENTRY paCalls;
1058 /** Number of calls in paCalls. */
1059 uint16_t cCalls;
1060 /** Number of calls allocated. */
1061 uint16_t cAllocated;
1062 } Thrd;
1063 struct
1064 {
1065 /** The native instructions (PFNIEMTBNATIVE). */
1066 PIEMNATIVEINSTR paInstructions;
1067 /** Number of instructions pointed to by paInstructions. */
1068 uint32_t cInstructions;
1069 } Native;
1070 /** Generic view for zeroing when freeing. */
1071 struct
1072 {
1073 uintptr_t uPtr;
1074 uint32_t uData;
1075 } Gen;
1076 };
1077
1078 /** The allocation chunk this TB belongs to. */
1079 uint8_t idxAllocChunk;
1080 uint8_t bUnused;
1081
1082 /** Number of bytes of opcodes stored in pabOpcodes.
1083 * @todo this field isn't really needed, aRanges keeps the actual info. */
1084 uint16_t cbOpcodes;
1085 /** Pointer to the opcode bytes this block was recompiled from. */
1086 uint8_t *pabOpcodes;
1087
1088 /** Debug info if enabled.
1089 * This is only generated by the native recompiler. */
1090 PIEMTBDBG pDbgInfo;
1091
1092 /* --- 64 byte cache line end --- */
1093
1094 /** Opcode ranges.
1095 *
1096 * The opcode checkers and maybe TLB loading functions will use this to figure
1097 * out what to do. The parameter will specify an entry and the opcode offset to
1098 * start at and the minimum number of bytes to verify (instruction length).
1099 *
1100 * When VT-x and AMD-V looks up the opcode bytes for an exitting instruction,
1101 * they'll first translate RIP (+ cbInstr - 1) to a physical address using the
1102 * code TLB (must have a valid entry for that address) and scan the ranges to
1103 * locate the corresponding opcodes. Probably.
1104 */
1105 struct IEMTBOPCODERANGE
1106 {
1107 /** Offset within pabOpcodes. */
1108 uint16_t offOpcodes;
1109 /** Number of bytes. */
1110 uint16_t cbOpcodes;
1111 /** The page offset. */
1112 RT_GCC_EXTENSION
1113 uint16_t offPhysPage : 12;
1114 /** Unused bits. */
1115 RT_GCC_EXTENSION
1116 uint16_t u2Unused : 2;
1117 /** Index into GCPhysPc + aGCPhysPages for the physical page address. */
1118 RT_GCC_EXTENSION
1119 uint16_t idxPhysPage : 2;
1120 } aRanges[8];
1121
1122 /** Physical pages that this TB covers.
1123 * The GCPhysPc w/o page offset is element zero, so starting here with 1. */
1124 RTGCPHYS aGCPhysPages[2];
1125} IEMTB;
1126#pragma pack()
1127AssertCompileMemberAlignment(IEMTB, GCPhysPc, sizeof(RTGCPHYS));
1128AssertCompileMemberAlignment(IEMTB, Thrd, sizeof(void *));
1129AssertCompileMemberAlignment(IEMTB, pabOpcodes, sizeof(void *));
1130AssertCompileMemberAlignment(IEMTB, pDbgInfo, sizeof(void *));
1131AssertCompileMemberAlignment(IEMTB, aGCPhysPages, sizeof(RTGCPHYS));
1132AssertCompileMemberOffset(IEMTB, aRanges, 64);
1133AssertCompileMemberSize(IEMTB, aRanges[0], 6);
1134#if 1
1135AssertCompileSize(IEMTB, 128);
1136# define IEMTB_SIZE_IS_POWER_OF_TWO /**< The IEMTB size is a power of two. */
1137#else
1138AssertCompileSize(IEMTB, 168);
1139# undef IEMTB_SIZE_IS_POWER_OF_TWO
1140#endif
1141
1142/** Pointer to a translation block. */
1143typedef IEMTB *PIEMTB;
1144/** Pointer to a const translation block. */
1145typedef IEMTB const *PCIEMTB;
1146
1147/**
1148 * A chunk of memory in the TB allocator.
1149 */
1150typedef struct IEMTBCHUNK
1151{
1152 /** Pointer to the translation blocks in this chunk. */
1153 PIEMTB paTbs;
1154#ifdef IN_RING0
1155 /** Allocation handle. */
1156 RTR0MEMOBJ hMemObj;
1157#endif
1158} IEMTBCHUNK;
1159
1160/**
1161 * A per-CPU translation block allocator.
1162 *
1163 * Because of how the IEMTBCACHE uses the lower 6 bits of the TB address to keep
1164 * the length of the collision list, and of course also for cache line alignment
1165 * reasons, the TBs must be allocated with at least 64-byte alignment.
1166 * Memory is there therefore allocated using one of the page aligned allocators.
1167 *
1168 *
1169 * To avoid wasting too much memory, it is allocated piecemeal as needed,
1170 * in chunks (IEMTBCHUNK) of 2 MiB or more. The TB has an 8-bit chunk index
1171 * that enables us to quickly calculate the allocation bitmap position when
1172 * freeing the translation block.
1173 */
1174typedef struct IEMTBALLOCATOR
1175{
1176 /** Magic value (IEMTBALLOCATOR_MAGIC). */
1177 uint32_t uMagic;
1178
1179#ifdef IEMTB_SIZE_IS_POWER_OF_TWO
1180 /** Mask corresponding to cTbsPerChunk - 1. */
1181 uint32_t fChunkMask;
1182 /** Shift count corresponding to cTbsPerChunk. */
1183 uint8_t cChunkShift;
1184#else
1185 uint32_t uUnused;
1186 uint8_t bUnused;
1187#endif
1188 /** Number of chunks we're allowed to allocate. */
1189 uint8_t cMaxChunks;
1190 /** Number of chunks currently populated. */
1191 uint16_t cAllocatedChunks;
1192 /** Number of translation blocks per chunk. */
1193 uint32_t cTbsPerChunk;
1194 /** Chunk size. */
1195 uint32_t cbPerChunk;
1196
1197 /** The maximum number of TBs. */
1198 uint32_t cMaxTbs;
1199 /** Total number of TBs in the populated chunks.
1200 * (cAllocatedChunks * cTbsPerChunk) */
1201 uint32_t cTotalTbs;
1202 /** The current number of TBs in use.
1203 * The number of free TBs: cAllocatedTbs - cInUseTbs; */
1204 uint32_t cInUseTbs;
1205 /** Statistics: Number of the cInUseTbs that are native ones. */
1206 uint32_t cNativeTbs;
1207 /** Statistics: Number of the cInUseTbs that are threaded ones. */
1208 uint32_t cThreadedTbs;
1209
1210 /** Where to start pruning TBs from when we're out.
1211 * See iemTbAllocatorAllocSlow for details. */
1212 uint32_t iPruneFrom;
1213 /** Hint about which bit to start scanning the bitmap from. */
1214 uint32_t iStartHint;
1215 /** Where to start pruning native TBs from when we're out of executable memory.
1216 * See iemTbAllocatorFreeupNativeSpace for details. */
1217 uint32_t iPruneNativeFrom;
1218 uint32_t uPadding;
1219
1220 /** Statistics: Number of TB allocation calls. */
1221 STAMCOUNTER StatAllocs;
1222 /** Statistics: Number of TB free calls. */
1223 STAMCOUNTER StatFrees;
1224 /** Statistics: Time spend pruning. */
1225 STAMPROFILE StatPrune;
1226 /** Statistics: Time spend pruning native TBs. */
1227 STAMPROFILE StatPruneNative;
1228
1229 /** The delayed free list (see iemTbAlloctorScheduleForFree). */
1230 PIEMTB pDelayedFreeHead;
1231
1232 /** Allocation chunks. */
1233 IEMTBCHUNK aChunks[256];
1234
1235 /** Allocation bitmap for all possible chunk chunks. */
1236 RT_FLEXIBLE_ARRAY_EXTENSION
1237 uint64_t bmAllocated[RT_FLEXIBLE_ARRAY];
1238} IEMTBALLOCATOR;
1239/** Pointer to a TB allocator. */
1240typedef struct IEMTBALLOCATOR *PIEMTBALLOCATOR;
1241
1242/** Magic value for the TB allocator (Emmet Harley Cohen). */
1243#define IEMTBALLOCATOR_MAGIC UINT32_C(0x19900525)
1244
1245
1246/**
1247 * A per-CPU translation block cache (hash table).
1248 *
1249 * The hash table is allocated once during IEM initialization and size double
1250 * the max TB count, rounded up to the nearest power of two (so we can use and
1251 * AND mask rather than a rest division when hashing).
1252 */
1253typedef struct IEMTBCACHE
1254{
1255 /** Magic value (IEMTBCACHE_MAGIC). */
1256 uint32_t uMagic;
1257 /** Size of the hash table. This is a power of two. */
1258 uint32_t cHash;
1259 /** The mask corresponding to cHash. */
1260 uint32_t uHashMask;
1261 uint32_t uPadding;
1262
1263 /** @name Statistics
1264 * @{ */
1265 /** Number of collisions ever. */
1266 STAMCOUNTER cCollisions;
1267
1268 /** Statistics: Number of TB lookup misses. */
1269 STAMCOUNTER cLookupMisses;
1270 /** Statistics: Number of TB lookup hits (debug only). */
1271 STAMCOUNTER cLookupHits;
1272 STAMCOUNTER auPadding2[3];
1273 /** Statistics: Collision list length pruning. */
1274 STAMPROFILE StatPrune;
1275 /** @} */
1276
1277 /** The hash table itself.
1278 * @note The lower 6 bits of the pointer is used for keeping the collision
1279 * list length, so we can take action when it grows too long.
1280 * This works because TBs are allocated using a 64 byte (or
1281 * higher) alignment from page aligned chunks of memory, so the lower
1282 * 6 bits of the address will always be zero.
1283 * See IEMTBCACHE_PTR_COUNT_MASK, IEMTBCACHE_PTR_MAKE and friends.
1284 */
1285 RT_FLEXIBLE_ARRAY_EXTENSION
1286 PIEMTB apHash[RT_FLEXIBLE_ARRAY];
1287} IEMTBCACHE;
1288/** Pointer to a per-CPU translation block cahce. */
1289typedef IEMTBCACHE *PIEMTBCACHE;
1290
1291/** Magic value for IEMTBCACHE (Johnny O'Neal). */
1292#define IEMTBCACHE_MAGIC UINT32_C(0x19561010)
1293
1294/** The collision count mask for IEMTBCACHE::apHash entries. */
1295#define IEMTBCACHE_PTR_COUNT_MASK ((uintptr_t)0x3f)
1296/** The max collision count for IEMTBCACHE::apHash entries before pruning. */
1297#define IEMTBCACHE_PTR_MAX_COUNT ((uintptr_t)0x30)
1298/** Combine a TB pointer and a collision list length into a value for an
1299 * IEMTBCACHE::apHash entry. */
1300#define IEMTBCACHE_PTR_MAKE(a_pTb, a_cCount) (PIEMTB)((uintptr_t)(a_pTb) | (a_cCount))
1301/** Combine a TB pointer and a collision list length into a value for an
1302 * IEMTBCACHE::apHash entry. */
1303#define IEMTBCACHE_PTR_GET_TB(a_pHashEntry) (PIEMTB)((uintptr_t)(a_pHashEntry) & ~IEMTBCACHE_PTR_COUNT_MASK)
1304/** Combine a TB pointer and a collision list length into a value for an
1305 * IEMTBCACHE::apHash entry. */
1306#define IEMTBCACHE_PTR_GET_COUNT(a_pHashEntry) ((uintptr_t)(a_pHashEntry) & IEMTBCACHE_PTR_COUNT_MASK)
1307
1308/**
1309 * Calculates the hash table slot for a TB from physical PC address and TB flags.
1310 */
1311#define IEMTBCACHE_HASH(a_paCache, a_fTbFlags, a_GCPhysPc) \
1312 IEMTBCACHE_HASH_NO_KEY_MASK(a_paCache, (a_fTbFlags) & IEMTB_F_KEY_MASK, a_GCPhysPc)
1313
1314/**
1315 * Calculates the hash table slot for a TB from physical PC address and TB
1316 * flags, ASSUMING the caller has applied IEMTB_F_KEY_MASK to @a a_fTbFlags.
1317 */
1318#define IEMTBCACHE_HASH_NO_KEY_MASK(a_paCache, a_fTbFlags, a_GCPhysPc) \
1319 (((uint32_t)(a_GCPhysPc) ^ (a_fTbFlags)) & (a_paCache)->uHashMask)
1320
1321
1322/** @name IEMBRANCHED_F_XXX - Branched indicator (IEMCPU::fTbBranched).
1323 *
1324 * These flags parallels the main IEM_CIMPL_F_BRANCH_XXX flags.
1325 *
1326 * @{ */
1327/** Value if no branching happened recently. */
1328#define IEMBRANCHED_F_NO UINT8_C(0x00)
1329/** Flag set if direct branch, clear if absolute or indirect. */
1330#define IEMBRANCHED_F_DIRECT UINT8_C(0x01)
1331/** Flag set if indirect branch, clear if direct or relative. */
1332#define IEMBRANCHED_F_INDIRECT UINT8_C(0x02)
1333/** Flag set if relative branch, clear if absolute or indirect. */
1334#define IEMBRANCHED_F_RELATIVE UINT8_C(0x04)
1335/** Flag set if conditional branch, clear if unconditional. */
1336#define IEMBRANCHED_F_CONDITIONAL UINT8_C(0x08)
1337/** Flag set if it's a far branch. */
1338#define IEMBRANCHED_F_FAR UINT8_C(0x10)
1339/** Flag set if the stack pointer is modified. */
1340#define IEMBRANCHED_F_STACK UINT8_C(0x20)
1341/** Flag set if the stack pointer and (maybe) the stack segment are modified. */
1342#define IEMBRANCHED_F_STACK_FAR UINT8_C(0x40)
1343/** Flag set (by IEM_MC_REL_JMP_XXX) if it's a zero bytes relative jump. */
1344#define IEMBRANCHED_F_ZERO UINT8_C(0x80)
1345/** @} */
1346
1347
1348/**
1349 * The per-CPU IEM state.
1350 */
1351typedef struct IEMCPU
1352{
1353 /** Info status code that needs to be propagated to the IEM caller.
1354 * This cannot be passed internally, as it would complicate all success
1355 * checks within the interpreter making the code larger and almost impossible
1356 * to get right. Instead, we'll store status codes to pass on here. Each
1357 * source of these codes will perform appropriate sanity checks. */
1358 int32_t rcPassUp; /* 0x00 */
1359 /** Execution flag, IEM_F_XXX. */
1360 uint32_t fExec; /* 0x04 */
1361
1362 /** @name Decoder state.
1363 * @{ */
1364#ifndef IEM_WITH_OPAQUE_DECODER_STATE
1365# ifdef IEM_WITH_CODE_TLB
1366 /** The offset of the next instruction byte. */
1367 uint32_t offInstrNextByte; /* 0x08 */
1368 /** The number of bytes available at pbInstrBuf for the current instruction.
1369 * This takes the max opcode length into account so that doesn't need to be
1370 * checked separately. */
1371 uint32_t cbInstrBuf; /* 0x0c */
1372 /** Pointer to the page containing RIP, user specified buffer or abOpcode.
1373 * This can be NULL if the page isn't mappable for some reason, in which
1374 * case we'll do fallback stuff.
1375 *
1376 * If we're executing an instruction from a user specified buffer,
1377 * IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
1378 * aligned pointer but pointer to the user data.
1379 *
1380 * For instructions crossing pages, this will start on the first page and be
1381 * advanced to the next page by the time we've decoded the instruction. This
1382 * therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
1383 */
1384 uint8_t const *pbInstrBuf; /* 0x10 */
1385# if ARCH_BITS == 32
1386 uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
1387# endif
1388 /** The program counter corresponding to pbInstrBuf.
1389 * This is set to a non-canonical address when we need to invalidate it. */
1390 uint64_t uInstrBufPc; /* 0x18 */
1391 /** The guest physical address corresponding to pbInstrBuf. */
1392 RTGCPHYS GCPhysInstrBuf; /* 0x20 */
1393 /** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
1394 * This takes the CS segment limit into account. */
1395 uint16_t cbInstrBufTotal; /* 0x28 */
1396 /** Offset into pbInstrBuf of the first byte of the current instruction.
1397 * Can be negative to efficiently handle cross page instructions. */
1398 int16_t offCurInstrStart; /* 0x2a */
1399
1400 /** The prefix mask (IEM_OP_PRF_XXX). */
1401 uint32_t fPrefixes; /* 0x2c */
1402 /** The extra REX ModR/M register field bit (REX.R << 3). */
1403 uint8_t uRexReg; /* 0x30 */
1404 /** The extra REX ModR/M r/m field, SIB base and opcode reg bit
1405 * (REX.B << 3). */
1406 uint8_t uRexB; /* 0x31 */
1407 /** The extra REX SIB index field bit (REX.X << 3). */
1408 uint8_t uRexIndex; /* 0x32 */
1409
1410 /** The effective segment register (X86_SREG_XXX). */
1411 uint8_t iEffSeg; /* 0x33 */
1412
1413 /** The offset of the ModR/M byte relative to the start of the instruction. */
1414 uint8_t offModRm; /* 0x34 */
1415
1416# ifdef IEM_WITH_CODE_TLB_AND_OPCODE_BUF
1417 /** The current offset into abOpcode. */
1418 uint8_t offOpcode; /* 0x35 */
1419# else
1420 uint8_t bUnused; /* 0x35 */
1421# endif
1422# else /* !IEM_WITH_CODE_TLB */
1423 /** The size of what has currently been fetched into abOpcode. */
1424 uint8_t cbOpcode; /* 0x08 */
1425 /** The current offset into abOpcode. */
1426 uint8_t offOpcode; /* 0x09 */
1427 /** The offset of the ModR/M byte relative to the start of the instruction. */
1428 uint8_t offModRm; /* 0x0a */
1429
1430 /** The effective segment register (X86_SREG_XXX). */
1431 uint8_t iEffSeg; /* 0x0b */
1432
1433 /** The prefix mask (IEM_OP_PRF_XXX). */
1434 uint32_t fPrefixes; /* 0x0c */
1435 /** The extra REX ModR/M register field bit (REX.R << 3). */
1436 uint8_t uRexReg; /* 0x10 */
1437 /** The extra REX ModR/M r/m field, SIB base and opcode reg bit
1438 * (REX.B << 3). */
1439 uint8_t uRexB; /* 0x11 */
1440 /** The extra REX SIB index field bit (REX.X << 3). */
1441 uint8_t uRexIndex; /* 0x12 */
1442
1443# endif /* !IEM_WITH_CODE_TLB */
1444
1445 /** The effective operand mode. */
1446 IEMMODE enmEffOpSize; /* 0x36, 0x13 */
1447 /** The default addressing mode. */
1448 IEMMODE enmDefAddrMode; /* 0x37, 0x14 */
1449 /** The effective addressing mode. */
1450 IEMMODE enmEffAddrMode; /* 0x38, 0x15 */
1451 /** The default operand mode. */
1452 IEMMODE enmDefOpSize; /* 0x39, 0x16 */
1453
1454 /** Prefix index (VEX.pp) for two byte and three byte tables. */
1455 uint8_t idxPrefix; /* 0x3a, 0x17 */
1456 /** 3rd VEX/EVEX/XOP register.
1457 * Please use IEM_GET_EFFECTIVE_VVVV to access. */
1458 uint8_t uVex3rdReg; /* 0x3b, 0x18 */
1459 /** The VEX/EVEX/XOP length field. */
1460 uint8_t uVexLength; /* 0x3c, 0x19 */
1461 /** Additional EVEX stuff. */
1462 uint8_t fEvexStuff; /* 0x3d, 0x1a */
1463
1464# ifndef IEM_WITH_CODE_TLB
1465 /** Explicit alignment padding. */
1466 uint8_t abAlignment2a[1]; /* 0x1b */
1467# endif
1468 /** The FPU opcode (FOP). */
1469 uint16_t uFpuOpcode; /* 0x3e, 0x1c */
1470# ifndef IEM_WITH_CODE_TLB
1471 /** Explicit alignment padding. */
1472 uint8_t abAlignment2b[2]; /* 0x1e */
1473# endif
1474
1475 /** The opcode bytes. */
1476 uint8_t abOpcode[15]; /* 0x40, 0x20 */
1477 /** Explicit alignment padding. */
1478# ifdef IEM_WITH_CODE_TLB
1479 //uint8_t abAlignment2c[0x4f - 0x4f]; /* 0x4f */
1480# else
1481 uint8_t abAlignment2c[0x4f - 0x2f]; /* 0x2f */
1482# endif
1483#else /* IEM_WITH_OPAQUE_DECODER_STATE */
1484 uint8_t abOpaqueDecoder[0x4f - 0x8];
1485#endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1486 /** @} */
1487
1488
1489 /** The number of active guest memory mappings. */
1490 uint8_t cActiveMappings; /* 0x4f, 0x4f */
1491
1492 /** Records for tracking guest memory mappings. */
1493 struct
1494 {
1495 /** The address of the mapped bytes. */
1496 R3R0PTRTYPE(void *) pv;
1497 /** The access flags (IEM_ACCESS_XXX).
1498 * IEM_ACCESS_INVALID if the entry is unused. */
1499 uint32_t fAccess;
1500#if HC_ARCH_BITS == 64
1501 uint32_t u32Alignment4; /**< Alignment padding. */
1502#endif
1503 } aMemMappings[3]; /* 0x50 LB 0x30 */
1504
1505 /** Locking records for the mapped memory. */
1506 union
1507 {
1508 PGMPAGEMAPLOCK Lock;
1509 uint64_t au64Padding[2];
1510 } aMemMappingLocks[3]; /* 0x80 LB 0x30 */
1511
1512 /** Bounce buffer info.
1513 * This runs in parallel to aMemMappings. */
1514 struct
1515 {
1516 /** The physical address of the first byte. */
1517 RTGCPHYS GCPhysFirst;
1518 /** The physical address of the second page. */
1519 RTGCPHYS GCPhysSecond;
1520 /** The number of bytes in the first page. */
1521 uint16_t cbFirst;
1522 /** The number of bytes in the second page. */
1523 uint16_t cbSecond;
1524 /** Whether it's unassigned memory. */
1525 bool fUnassigned;
1526 /** Explicit alignment padding. */
1527 bool afAlignment5[3];
1528 } aMemBbMappings[3]; /* 0xb0 LB 0x48 */
1529
1530 /** The flags of the current exception / interrupt. */
1531 uint32_t fCurXcpt; /* 0xf8 */
1532 /** The current exception / interrupt. */
1533 uint8_t uCurXcpt; /* 0xfc */
1534 /** Exception / interrupt recursion depth. */
1535 int8_t cXcptRecursions; /* 0xfb */
1536
1537 /** The next unused mapping index.
1538 * @todo try find room for this up with cActiveMappings. */
1539 uint8_t iNextMapping; /* 0xfd */
1540 uint8_t abAlignment7[1];
1541
1542 /** Bounce buffer storage.
1543 * This runs in parallel to aMemMappings and aMemBbMappings. */
1544 struct
1545 {
1546 uint8_t ab[512];
1547 } aBounceBuffers[3]; /* 0x100 LB 0x600 */
1548
1549
1550 /** Pointer set jump buffer - ring-3 context. */
1551 R3PTRTYPE(jmp_buf *) pJmpBufR3;
1552 /** Pointer set jump buffer - ring-0 context. */
1553 R0PTRTYPE(jmp_buf *) pJmpBufR0;
1554
1555 /** @todo Should move this near @a fCurXcpt later. */
1556 /** The CR2 for the current exception / interrupt. */
1557 uint64_t uCurXcptCr2;
1558 /** The error code for the current exception / interrupt. */
1559 uint32_t uCurXcptErr;
1560
1561 /** @name Statistics
1562 * @{ */
1563 /** The number of instructions we've executed. */
1564 uint32_t cInstructions;
1565 /** The number of potential exits. */
1566 uint32_t cPotentialExits;
1567 /** The number of bytes data or stack written (mostly for IEMExecOneEx).
1568 * This may contain uncommitted writes. */
1569 uint32_t cbWritten;
1570 /** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
1571 uint32_t cRetInstrNotImplemented;
1572 /** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
1573 uint32_t cRetAspectNotImplemented;
1574 /** Counts informational statuses returned (other than VINF_SUCCESS). */
1575 uint32_t cRetInfStatuses;
1576 /** Counts other error statuses returned. */
1577 uint32_t cRetErrStatuses;
1578 /** Number of times rcPassUp has been used. */
1579 uint32_t cRetPassUpStatus;
1580 /** Number of times RZ left with instruction commit pending for ring-3. */
1581 uint32_t cPendingCommit;
1582 /** Number of long jumps. */
1583 uint32_t cLongJumps;
1584 /** @} */
1585
1586 /** @name Target CPU information.
1587 * @{ */
1588#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
1589 /** The target CPU. */
1590 uint8_t uTargetCpu;
1591#else
1592 uint8_t bTargetCpuPadding;
1593#endif
1594 /** For selecting assembly works matching the target CPU EFLAGS behaviour, see
1595 * IEMTARGETCPU_EFL_BEHAVIOR_XXX for values, with the 1st entry for when no
1596 * native host support and the 2nd for when there is.
1597 *
1598 * The two values are typically indexed by a g_CpumHostFeatures bit.
1599 *
1600 * This is for instance used for the BSF & BSR instructions where AMD and
1601 * Intel CPUs produce different EFLAGS. */
1602 uint8_t aidxTargetCpuEflFlavour[2];
1603
1604 /** The CPU vendor. */
1605 CPUMCPUVENDOR enmCpuVendor;
1606 /** @} */
1607
1608 /** @name Host CPU information.
1609 * @{ */
1610 /** The CPU vendor. */
1611 CPUMCPUVENDOR enmHostCpuVendor;
1612 /** @} */
1613
1614 /** Counts RDMSR \#GP(0) LogRel(). */
1615 uint8_t cLogRelRdMsr;
1616 /** Counts WRMSR \#GP(0) LogRel(). */
1617 uint8_t cLogRelWrMsr;
1618 /** Alignment padding. */
1619 uint8_t abAlignment9[46];
1620
1621 /** @name Recompilation
1622 * @{ */
1623 /** Pointer to the current translation block.
1624 * This can either be one being executed or one being compiled. */
1625 R3PTRTYPE(PIEMTB) pCurTbR3;
1626 /** Fixed TB used for threaded recompilation.
1627 * This is allocated once with maxed-out sizes and re-used afterwards. */
1628 R3PTRTYPE(PIEMTB) pThrdCompileTbR3;
1629 /** Pointer to the ring-3 TB cache for this EMT. */
1630 R3PTRTYPE(PIEMTBCACHE) pTbCacheR3;
1631 /** The PC (RIP) at the start of pCurTbR3/pCurTbR0.
1632 * The TBs are based on physical addresses, so this is needed to correleated
1633 * RIP to opcode bytes stored in the TB (AMD-V / VT-x). */
1634 uint64_t uCurTbStartPc;
1635 /** Number of threaded TBs executed. */
1636 uint64_t cTbExecThreaded;
1637 /** Number of native TBs executed. */
1638 uint64_t cTbExecNative;
1639 /** Whether we need to check the opcode bytes for the current instruction.
1640 * This is set by a previous instruction if it modified memory or similar. */
1641 bool fTbCheckOpcodes;
1642 /** Indicates whether and how we just branched - IEMBRANCHED_F_XXX. */
1643 uint8_t fTbBranched;
1644 /** Set when GCPhysInstrBuf is updated because of a page crossing. */
1645 bool fTbCrossedPage;
1646 /** Whether to end the current TB. */
1647 bool fEndTb;
1648 /** Number of instructions before we need emit an IRQ check call again.
1649 * This helps making sure we don't execute too long w/o checking for
1650 * interrupts and immediately following instructions that may enable
1651 * interrupts (e.g. POPF, IRET, STI). With STI an additional hack is
1652 * required to make sure we check following the next instruction as well, see
1653 * fTbCurInstrIsSti. */
1654 uint8_t cInstrTillIrqCheck;
1655 /** Indicates that the current instruction is an STI. This is set by the
1656 * iemCImpl_sti code and subsequently cleared by the recompiler. */
1657 bool fTbCurInstrIsSti;
1658 /** The size of the IEMTB::pabOpcodes allocation in pThrdCompileTbR3. */
1659 uint16_t cbOpcodesAllocated;
1660 /** The current instruction number in a native TB.
1661 * This is set by code that may trigger an unexpected TB exit (throw/longjmp)
1662 * and will be picked up by the TB execution loop. Only used when
1663 * IEMNATIVE_WITH_INSTRUCTION_COUNTING is defined. */
1664 uint8_t idxTbCurInstr;
1665 /** Spaced reserved for recompiler data / alignment. */
1666 bool afRecompilerStuff1[3];
1667 /** The virtual sync time at the last timer poll call. */
1668 uint32_t msRecompilerPollNow;
1669 /** The IEM_CIMPL_F_XXX mask for the current instruction. */
1670 uint32_t fTbCurInstr;
1671 /** The IEM_CIMPL_F_XXX mask for the previous instruction. */
1672 uint32_t fTbPrevInstr;
1673 /** Previous GCPhysInstrBuf value - only valid if fTbCrossedPage is set. */
1674 RTGCPHYS GCPhysInstrBufPrev;
1675 /** Copy of IEMCPU::GCPhysInstrBuf after decoding a branch instruction.
1676 * This is used together with fTbBranched and GCVirtTbBranchSrcBuf to determin
1677 * whether a branch instruction jumps to a new page or stays within the
1678 * current one. */
1679 RTGCPHYS GCPhysTbBranchSrcBuf;
1680 /** Copy of IEMCPU::uInstrBufPc after decoding a branch instruction. */
1681 uint64_t GCVirtTbBranchSrcBuf;
1682 /** Pointer to the ring-3 TB allocator for this EMT. */
1683 R3PTRTYPE(PIEMTBALLOCATOR) pTbAllocatorR3;
1684 /** Pointer to the ring-3 executable memory allocator for this EMT. */
1685 R3PTRTYPE(struct IEMEXECMEMALLOCATOR *) pExecMemAllocatorR3;
1686 /** Pointer to the native recompiler state for ring-3. */
1687 R3PTRTYPE(struct IEMRECOMPILERSTATE *) pNativeRecompilerStateR3;
1688 /** Alignment padding. */
1689 uint64_t auAlignment10[3];
1690 /** Statistics: Times TB execution was broken off before reaching the end. */
1691 STAMCOUNTER StatTbExecBreaks;
1692 /** Statistics: Times BltIn_CheckIrq breaks out of the TB. */
1693 STAMCOUNTER StatCheckIrqBreaks;
1694 /** Statistics: Times BltIn_CheckMode breaks out of the TB. */
1695 STAMCOUNTER StatCheckModeBreaks;
1696 /** Statistics: Times a post jump target check missed and had to find new TB. */
1697 STAMCOUNTER StatCheckBranchMisses;
1698 /** Statistics: Times a jump or page crossing required a TB with CS.LIM checking. */
1699 STAMCOUNTER StatCheckNeedCsLimChecking;
1700 /** Native TB statistics: Number of fully recompiled TBs. */
1701 STAMCOUNTER StatNativeFullyRecompiledTbs;
1702 /** Threaded TB statistics: Number of instructions per TB. */
1703 STAMPROFILE StatTbThreadedInstr;
1704 /** Threaded TB statistics: Number of calls per TB. */
1705 STAMPROFILE StatTbThreadedCalls;
1706 /** Native TB statistics: Native code size per TB. */
1707 STAMPROFILE StatTbNativeCode;
1708 /** Native TB statistics: Profiling native recompilation. */
1709 STAMPROFILE StatNativeRecompilation;
1710 /** Native TB statistics: Number of calls per TB that were recompiled properly. */
1711 STAMPROFILE StatNativeCallsRecompiled;
1712 /** Native TB statistics: Number of threaded calls per TB that weren't recompiled. */
1713 STAMPROFILE StatNativeCallsThreaded;
1714 /** @} */
1715
1716 /** Data TLB.
1717 * @remarks Must be 64-byte aligned. */
1718 IEMTLB DataTlb;
1719 /** Instruction TLB.
1720 * @remarks Must be 64-byte aligned. */
1721 IEMTLB CodeTlb;
1722
1723 /** Exception statistics. */
1724 STAMCOUNTER aStatXcpts[32];
1725 /** Interrupt statistics. */
1726 uint32_t aStatInts[256];
1727
1728#if defined(VBOX_WITH_STATISTICS) && !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
1729 /** Instruction statistics for ring-0/raw-mode. */
1730 IEMINSTRSTATS StatsRZ;
1731 /** Instruction statistics for ring-3. */
1732 IEMINSTRSTATS StatsR3;
1733#endif
1734} IEMCPU;
1735AssertCompileMemberOffset(IEMCPU, cActiveMappings, 0x4f);
1736AssertCompileMemberAlignment(IEMCPU, aMemMappings, 16);
1737AssertCompileMemberAlignment(IEMCPU, aMemMappingLocks, 16);
1738AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 64);
1739AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
1740AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
1741
1742/** Pointer to the per-CPU IEM state. */
1743typedef IEMCPU *PIEMCPU;
1744/** Pointer to the const per-CPU IEM state. */
1745typedef IEMCPU const *PCIEMCPU;
1746
1747
1748/** @def IEM_GET_CTX
1749 * Gets the guest CPU context for the calling EMT.
1750 * @returns PCPUMCTX
1751 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1752 */
1753#define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
1754
1755/** @def IEM_CTX_ASSERT
1756 * Asserts that the @a a_fExtrnMbz is present in the CPU context.
1757 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1758 * @param a_fExtrnMbz The mask of CPUMCTX_EXTRN_XXX flags that must be zero.
1759 */
1760#define IEM_CTX_ASSERT(a_pVCpu, a_fExtrnMbz) \
1761 AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
1762 ("fExtrn=%#RX64 & fExtrnMbz=%#RX64 -> %#RX64\n", \
1763 (a_pVCpu)->cpum.GstCtx.fExtrn, (a_fExtrnMbz), (a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz) ))
1764
1765/** @def IEM_CTX_IMPORT_RET
1766 * Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
1767 *
1768 * Will call the keep to import the bits as needed.
1769 *
1770 * Returns on import failure.
1771 *
1772 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1773 * @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
1774 */
1775#define IEM_CTX_IMPORT_RET(a_pVCpu, a_fExtrnImport) \
1776 do { \
1777 if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
1778 { /* likely */ } \
1779 else \
1780 { \
1781 int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
1782 AssertRCReturn(rcCtxImport, rcCtxImport); \
1783 } \
1784 } while (0)
1785
1786/** @def IEM_CTX_IMPORT_NORET
1787 * Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
1788 *
1789 * Will call the keep to import the bits as needed.
1790 *
1791 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1792 * @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
1793 */
1794#define IEM_CTX_IMPORT_NORET(a_pVCpu, a_fExtrnImport) \
1795 do { \
1796 if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
1797 { /* likely */ } \
1798 else \
1799 { \
1800 int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
1801 AssertLogRelRC(rcCtxImport); \
1802 } \
1803 } while (0)
1804
1805/** @def IEM_CTX_IMPORT_JMP
1806 * Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
1807 *
1808 * Will call the keep to import the bits as needed.
1809 *
1810 * Jumps on import failure.
1811 *
1812 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1813 * @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
1814 */
1815#define IEM_CTX_IMPORT_JMP(a_pVCpu, a_fExtrnImport) \
1816 do { \
1817 if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
1818 { /* likely */ } \
1819 else \
1820 { \
1821 int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
1822 AssertRCStmt(rcCtxImport, IEM_DO_LONGJMP(pVCpu, rcCtxImport)); \
1823 } \
1824 } while (0)
1825
1826
1827
1828/** @def IEM_GET_TARGET_CPU
1829 * Gets the current IEMTARGETCPU value.
1830 * @returns IEMTARGETCPU value.
1831 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1832 */
1833#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
1834# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
1835#else
1836# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
1837#endif
1838
1839/** @def IEM_GET_INSTR_LEN
1840 * Gets the instruction length. */
1841#ifdef IEM_WITH_CODE_TLB
1842# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
1843#else
1844# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
1845#endif
1846
1847/** @def IEM_TRY_SETJMP
1848 * Wrapper around setjmp / try, hiding all the ugly differences.
1849 *
1850 * @note Use with extreme care as this is a fragile macro.
1851 * @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
1852 * @param a_rcTarget The variable that should receive the status code in case
1853 * of a longjmp/throw.
1854 */
1855/** @def IEM_TRY_SETJMP_AGAIN
1856 * For when setjmp / try is used again in the same variable scope as a previous
1857 * IEM_TRY_SETJMP invocation.
1858 */
1859/** @def IEM_CATCH_LONGJMP_BEGIN
1860 * Start wrapper for catch / setjmp-else.
1861 *
1862 * This will set up a scope.
1863 *
1864 * @note Use with extreme care as this is a fragile macro.
1865 * @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
1866 * @param a_rcTarget The variable that should receive the status code in case
1867 * of a longjmp/throw.
1868 */
1869/** @def IEM_CATCH_LONGJMP_END
1870 * End wrapper for catch / setjmp-else.
1871 *
1872 * This will close the scope set up by IEM_CATCH_LONGJMP_BEGIN and clean up the
1873 * state.
1874 *
1875 * @note Use with extreme care as this is a fragile macro.
1876 * @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
1877 */
1878#if defined(IEM_WITH_SETJMP) || defined(DOXYGEN_RUNNING)
1879# ifdef IEM_WITH_THROW_CATCH
1880# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
1881 a_rcTarget = VINF_SUCCESS; \
1882 try
1883# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
1884 IEM_TRY_SETJMP(a_pVCpu, a_rcTarget)
1885# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
1886 catch (int rcThrown) \
1887 { \
1888 a_rcTarget = rcThrown
1889# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
1890 } \
1891 ((void)0)
1892# else /* !IEM_WITH_THROW_CATCH */
1893# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
1894 jmp_buf JmpBuf; \
1895 jmp_buf * volatile pSavedJmpBuf = (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf); \
1896 (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
1897 if ((rcStrict = setjmp(JmpBuf)) == 0)
1898# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
1899 pSavedJmpBuf = (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf); \
1900 (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
1901 if ((rcStrict = setjmp(JmpBuf)) == 0)
1902# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
1903 else \
1904 { \
1905 ((void)0)
1906# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
1907 } \
1908 (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = pSavedJmpBuf
1909# endif /* !IEM_WITH_THROW_CATCH */
1910#endif /* IEM_WITH_SETJMP */
1911
1912
1913/**
1914 * Shared per-VM IEM data.
1915 */
1916typedef struct IEM
1917{
1918 /** The VMX APIC-access page handler type. */
1919 PGMPHYSHANDLERTYPE hVmxApicAccessPage;
1920#ifndef VBOX_WITHOUT_CPUID_HOST_CALL
1921 /** Set if the CPUID host call functionality is enabled. */
1922 bool fCpuIdHostCall;
1923#endif
1924} IEM;
1925
1926
1927
1928/** @name IEM_ACCESS_XXX - Access details.
1929 * @{ */
1930#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
1931#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
1932#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
1933#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
1934#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
1935#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
1936#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
1937#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
1938#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
1939#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
1940/** The writes are partial, so if initialize the bounce buffer with the
1941 * orignal RAM content. */
1942#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
1943/** Used in aMemMappings to indicate that the entry is bounce buffered. */
1944#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
1945/** Bounce buffer with ring-3 write pending, first page. */
1946#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
1947/** Bounce buffer with ring-3 write pending, second page. */
1948#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
1949/** Not locked, accessed via the TLB. */
1950#define IEM_ACCESS_NOT_LOCKED UINT32_C(0x00001000)
1951/** Valid bit mask. */
1952#define IEM_ACCESS_VALID_MASK UINT32_C(0x00001fff)
1953/** Shift count for the TLB flags (upper word). */
1954#define IEM_ACCESS_SHIFT_TLB_FLAGS 16
1955
1956/** Read+write data alias. */
1957#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ | IEM_ACCESS_TYPE_WRITE | IEM_ACCESS_WHAT_DATA)
1958/** Write data alias. */
1959#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE | IEM_ACCESS_WHAT_DATA)
1960/** Read data alias. */
1961#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_DATA)
1962/** Instruction fetch alias. */
1963#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC | IEM_ACCESS_WHAT_CODE)
1964/** Stack write alias. */
1965#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE | IEM_ACCESS_WHAT_STACK)
1966/** Stack read alias. */
1967#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_STACK)
1968/** Stack read+write alias. */
1969#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ | IEM_ACCESS_TYPE_WRITE | IEM_ACCESS_WHAT_STACK)
1970/** Read system table alias. */
1971#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ | IEM_ACCESS_WHAT_SYS)
1972/** Read+write system table alias. */
1973#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ | IEM_ACCESS_TYPE_WRITE | IEM_ACCESS_WHAT_SYS)
1974/** @} */
1975
1976/** @name Prefix constants (IEMCPU::fPrefixes)
1977 * @{ */
1978#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /**< CS segment prefix (0x2e). */
1979#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /**< SS segment prefix (0x36). */
1980#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /**< DS segment prefix (0x3e). */
1981#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /**< ES segment prefix (0x26). */
1982#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /**< FS segment prefix (0x64). */
1983#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /**< GS segment prefix (0x65). */
1984#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
1985
1986#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /**< Operand size prefix (0x66). */
1987#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /**< REX.W prefix (0x48-0x4f). */
1988#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /**< Address size prefix (0x67). */
1989
1990#define IEM_OP_PRF_LOCK RT_BIT_32(16) /**< Lock prefix (0xf0). */
1991#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /**< Repeat-not-zero prefix (0xf2). */
1992#define IEM_OP_PRF_REPZ RT_BIT_32(18) /**< Repeat-if-zero prefix (0xf3). */
1993
1994#define IEM_OP_PRF_REX RT_BIT_32(24) /**< Any REX prefix (0x40-0x4f). */
1995#define IEM_OP_PRF_REX_R RT_BIT_32(25) /**< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). */
1996#define IEM_OP_PRF_REX_B RT_BIT_32(26) /**< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). */
1997#define IEM_OP_PRF_REX_X RT_BIT_32(27) /**< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). */
1998/** Mask with all the REX prefix flags.
1999 * This is generally for use when needing to undo the REX prefixes when they
2000 * are followed legacy prefixes and therefore does not immediately preceed
2001 * the first opcode byte.
2002 * For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
2003#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX | IEM_OP_PRF_REX_R | IEM_OP_PRF_REX_B | IEM_OP_PRF_REX_X | IEM_OP_PRF_SIZE_REX_W )
2004
2005#define IEM_OP_PRF_VEX RT_BIT_32(28) /**< Indiciates VEX prefix. */
2006#define IEM_OP_PRF_EVEX RT_BIT_32(29) /**< Indiciates EVEX prefix. */
2007#define IEM_OP_PRF_XOP RT_BIT_32(30) /**< Indiciates XOP prefix. */
2008/** @} */
2009
2010/** @name IEMOPFORM_XXX - Opcode forms
2011 * @note These are ORed together with IEMOPHINT_XXX.
2012 * @{ */
2013/** ModR/M: reg, r/m */
2014#define IEMOPFORM_RM 0
2015/** ModR/M: reg, r/m (register) */
2016#define IEMOPFORM_RM_REG (IEMOPFORM_RM | IEMOPFORM_MOD3)
2017/** ModR/M: reg, r/m (memory) */
2018#define IEMOPFORM_RM_MEM (IEMOPFORM_RM | IEMOPFORM_NOT_MOD3)
2019/** ModR/M: reg, r/m */
2020#define IEMOPFORM_RMI 1
2021/** ModR/M: reg, r/m (register) */
2022#define IEMOPFORM_RMI_REG (IEMOPFORM_RM | IEMOPFORM_MOD3)
2023/** ModR/M: reg, r/m (memory) */
2024#define IEMOPFORM_RMI_MEM (IEMOPFORM_RM | IEMOPFORM_NOT_MOD3)
2025/** ModR/M: r/m, reg */
2026#define IEMOPFORM_MR 2
2027/** ModR/M: r/m (register), reg */
2028#define IEMOPFORM_MR_REG (IEMOPFORM_MR | IEMOPFORM_MOD3)
2029/** ModR/M: r/m (memory), reg */
2030#define IEMOPFORM_MR_MEM (IEMOPFORM_MR | IEMOPFORM_NOT_MOD3)
2031/** ModR/M: r/m, reg */
2032#define IEMOPFORM_MRI 3
2033/** ModR/M: r/m (register), reg */
2034#define IEMOPFORM_MRI_REG (IEMOPFORM_MR | IEMOPFORM_MOD3)
2035/** ModR/M: r/m (memory), reg */
2036#define IEMOPFORM_MRI_MEM (IEMOPFORM_MR | IEMOPFORM_NOT_MOD3)
2037/** ModR/M: r/m only */
2038#define IEMOPFORM_M 4
2039/** ModR/M: r/m only (register). */
2040#define IEMOPFORM_M_REG (IEMOPFORM_M | IEMOPFORM_MOD3)
2041/** ModR/M: r/m only (memory). */
2042#define IEMOPFORM_M_MEM (IEMOPFORM_M | IEMOPFORM_NOT_MOD3)
2043/** ModR/M: reg only */
2044#define IEMOPFORM_R 5
2045
2046/** VEX+ModR/M: reg, r/m */
2047#define IEMOPFORM_VEX_RM 8
2048/** VEX+ModR/M: reg, r/m (register) */
2049#define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM | IEMOPFORM_MOD3)
2050/** VEX+ModR/M: reg, r/m (memory) */
2051#define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM | IEMOPFORM_NOT_MOD3)
2052/** VEX+ModR/M: r/m, reg */
2053#define IEMOPFORM_VEX_MR 9
2054/** VEX+ModR/M: r/m (register), reg */
2055#define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR | IEMOPFORM_MOD3)
2056/** VEX+ModR/M: r/m (memory), reg */
2057#define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR | IEMOPFORM_NOT_MOD3)
2058/** VEX+ModR/M: r/m only */
2059#define IEMOPFORM_VEX_M 10
2060/** VEX+ModR/M: r/m only (register). */
2061#define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M | IEMOPFORM_MOD3)
2062/** VEX+ModR/M: r/m only (memory). */
2063#define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M | IEMOPFORM_NOT_MOD3)
2064/** VEX+ModR/M: reg only */
2065#define IEMOPFORM_VEX_R 11
2066/** VEX+ModR/M: reg, vvvv, r/m */
2067#define IEMOPFORM_VEX_RVM 12
2068/** VEX+ModR/M: reg, vvvv, r/m (register). */
2069#define IEMOPFORM_VEX_RVM_REG (IEMOPFORM_VEX_RVM | IEMOPFORM_MOD3)
2070/** VEX+ModR/M: reg, vvvv, r/m (memory). */
2071#define IEMOPFORM_VEX_RVM_MEM (IEMOPFORM_VEX_RVM | IEMOPFORM_NOT_MOD3)
2072/** VEX+ModR/M: reg, r/m, vvvv */
2073#define IEMOPFORM_VEX_RMV 13
2074/** VEX+ModR/M: reg, r/m, vvvv (register). */
2075#define IEMOPFORM_VEX_RMV_REG (IEMOPFORM_VEX_RMV | IEMOPFORM_MOD3)
2076/** VEX+ModR/M: reg, r/m, vvvv (memory). */
2077#define IEMOPFORM_VEX_RMV_MEM (IEMOPFORM_VEX_RMV | IEMOPFORM_NOT_MOD3)
2078/** VEX+ModR/M: reg, r/m, imm8 */
2079#define IEMOPFORM_VEX_RMI 14
2080/** VEX+ModR/M: reg, r/m, imm8 (register). */
2081#define IEMOPFORM_VEX_RMI_REG (IEMOPFORM_VEX_RMI | IEMOPFORM_MOD3)
2082/** VEX+ModR/M: reg, r/m, imm8 (memory). */
2083#define IEMOPFORM_VEX_RMI_MEM (IEMOPFORM_VEX_RMI | IEMOPFORM_NOT_MOD3)
2084/** VEX+ModR/M: r/m, vvvv, reg */
2085#define IEMOPFORM_VEX_MVR 15
2086/** VEX+ModR/M: r/m, vvvv, reg (register) */
2087#define IEMOPFORM_VEX_MVR_REG (IEMOPFORM_VEX_MVR | IEMOPFORM_MOD3)
2088/** VEX+ModR/M: r/m, vvvv, reg (memory) */
2089#define IEMOPFORM_VEX_MVR_MEM (IEMOPFORM_VEX_MVR | IEMOPFORM_NOT_MOD3)
2090/** VEX+ModR/M+/n: vvvv, r/m */
2091#define IEMOPFORM_VEX_VM 16
2092/** VEX+ModR/M+/n: vvvv, r/m (register) */
2093#define IEMOPFORM_VEX_VM_REG (IEMOPFORM_VEX_VM | IEMOPFORM_MOD3)
2094/** VEX+ModR/M+/n: vvvv, r/m (memory) */
2095#define IEMOPFORM_VEX_VM_MEM (IEMOPFORM_VEX_VM | IEMOPFORM_NOT_MOD3)
2096
2097/** Fixed register instruction, no R/M. */
2098#define IEMOPFORM_FIXED 32
2099
2100/** The r/m is a register. */
2101#define IEMOPFORM_MOD3 RT_BIT_32(8)
2102/** The r/m is a memory access. */
2103#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
2104/** @} */
2105
2106/** @name IEMOPHINT_XXX - Additional Opcode Hints
2107 * @note These are ORed together with IEMOPFORM_XXX.
2108 * @{ */
2109/** Ignores the operand size prefix (66h). */
2110#define IEMOPHINT_IGNORES_OZ_PFX RT_BIT_32(10)
2111/** Ignores REX.W (aka WIG). */
2112#define IEMOPHINT_IGNORES_REXW RT_BIT_32(11)
2113/** Both the operand size prefixes (66h + REX.W) are ignored. */
2114#define IEMOPHINT_IGNORES_OP_SIZES (IEMOPHINT_IGNORES_OZ_PFX | IEMOPHINT_IGNORES_REXW)
2115/** Allowed with the lock prefix. */
2116#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
2117/** The VEX.L value is ignored (aka LIG). */
2118#define IEMOPHINT_VEX_L_IGNORED RT_BIT_32(12)
2119/** The VEX.L value must be zero (i.e. 128-bit width only). */
2120#define IEMOPHINT_VEX_L_ZERO RT_BIT_32(13)
2121/** The VEX.V value must be zero. */
2122#define IEMOPHINT_VEX_V_ZERO RT_BIT_32(14)
2123
2124/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
2125#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
2126/** @} */
2127
2128/**
2129 * Possible hardware task switch sources.
2130 */
2131typedef enum IEMTASKSWITCH
2132{
2133 /** Task switch caused by an interrupt/exception. */
2134 IEMTASKSWITCH_INT_XCPT = 1,
2135 /** Task switch caused by a far CALL. */
2136 IEMTASKSWITCH_CALL,
2137 /** Task switch caused by a far JMP. */
2138 IEMTASKSWITCH_JUMP,
2139 /** Task switch caused by an IRET. */
2140 IEMTASKSWITCH_IRET
2141} IEMTASKSWITCH;
2142AssertCompileSize(IEMTASKSWITCH, 4);
2143
2144/**
2145 * Possible CrX load (write) sources.
2146 */
2147typedef enum IEMACCESSCRX
2148{
2149 /** CrX access caused by 'mov crX' instruction. */
2150 IEMACCESSCRX_MOV_CRX,
2151 /** CrX (CR0) write caused by 'lmsw' instruction. */
2152 IEMACCESSCRX_LMSW,
2153 /** CrX (CR0) write caused by 'clts' instruction. */
2154 IEMACCESSCRX_CLTS,
2155 /** CrX (CR0) read caused by 'smsw' instruction. */
2156 IEMACCESSCRX_SMSW
2157} IEMACCESSCRX;
2158
2159#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2160/** @name IEM_SLAT_FAIL_XXX - Second-level address translation failure information.
2161 *
2162 * These flags provide further context to SLAT page-walk failures that could not be
2163 * determined by PGM (e.g, PGM is not privy to memory access permissions).
2164 *
2165 * @{
2166 */
2167/** Translating a nested-guest linear address failed accessing a nested-guest
2168 * physical address. */
2169# define IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR RT_BIT_32(0)
2170/** Translating a nested-guest linear address failed accessing a
2171 * paging-structure entry or updating accessed/dirty bits. */
2172# define IEM_SLAT_FAIL_LINEAR_TO_PAGE_TABLE RT_BIT_32(1)
2173/** @} */
2174
2175DECLCALLBACK(FNPGMPHYSHANDLER) iemVmxApicAccessPageHandler;
2176# ifndef IN_RING3
2177DECLCALLBACK(FNPGMRZPHYSPFHANDLER) iemVmxApicAccessPagePfHandler;
2178# endif
2179#endif
2180
2181/**
2182 * Indicates to the verifier that the given flag set is undefined.
2183 *
2184 * Can be invoked again to add more flags.
2185 *
2186 * This is a NOOP if the verifier isn't compiled in.
2187 *
2188 * @note We're temporarily keeping this until code is converted to new
2189 * disassembler style opcode handling.
2190 */
2191#define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
2192
2193
2194/** @def IEM_DECL_IMPL_TYPE
2195 * For typedef'ing an instruction implementation function.
2196 *
2197 * @param a_RetType The return type.
2198 * @param a_Name The name of the type.
2199 * @param a_ArgList The argument list enclosed in parentheses.
2200 */
2201
2202/** @def IEM_DECL_IMPL_DEF
2203 * For defining an instruction implementation function.
2204 *
2205 * @param a_RetType The return type.
2206 * @param a_Name The name of the type.
2207 * @param a_ArgList The argument list enclosed in parentheses.
2208 */
2209
2210#if defined(__GNUC__) && defined(RT_ARCH_X86)
2211# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2212 __attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
2213# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2214 __attribute__((__fastcall__, __nothrow__)) DECL_HIDDEN_ONLY(a_RetType) a_Name a_ArgList
2215# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2216 __attribute__((__fastcall__, __nothrow__)) DECL_HIDDEN_ONLY(a_RetType) a_Name a_ArgList
2217
2218#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
2219# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2220 a_RetType (__fastcall a_Name) a_ArgList
2221# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2222 a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
2223# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2224 a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
2225
2226#elif __cplusplus >= 201700 /* P0012R1 support */
2227# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2228 a_RetType (VBOXCALL a_Name) a_ArgList RT_NOEXCEPT
2229# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2230 DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList RT_NOEXCEPT
2231# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2232 DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList RT_NOEXCEPT
2233
2234#else
2235# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2236 a_RetType (VBOXCALL a_Name) a_ArgList
2237# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2238 DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList
2239# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2240 DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList
2241
2242#endif
2243
2244/** Defined in IEMAllAImplC.cpp but also used by IEMAllAImplA.asm. */
2245RT_C_DECLS_BEGIN
2246extern uint8_t const g_afParity[256];
2247RT_C_DECLS_END
2248
2249
2250/** @name Arithmetic assignment operations on bytes (binary).
2251 * @{ */
2252typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU8, (uint8_t *pu8Dst, uint8_t u8Src, uint32_t *pEFlags));
2253typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
2254FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
2255FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
2256FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
2257FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
2258FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
2259FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
2260FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
2261/** @} */
2262
2263/** @name Arithmetic assignment operations on words (binary).
2264 * @{ */
2265typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU16, (uint16_t *pu16Dst, uint16_t u16Src, uint32_t *pEFlags));
2266typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
2267FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
2268FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
2269FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
2270FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
2271FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
2272FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
2273FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
2274/** @} */
2275
2276/** @name Arithmetic assignment operations on double words (binary).
2277 * @{ */
2278typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU32, (uint32_t *pu32Dst, uint32_t u32Src, uint32_t *pEFlags));
2279typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
2280FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
2281FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
2282FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
2283FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
2284FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
2285FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
2286FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
2287FNIEMAIMPLBINU32 iemAImpl_blsi_u32, iemAImpl_blsi_u32_fallback;
2288FNIEMAIMPLBINU32 iemAImpl_blsr_u32, iemAImpl_blsr_u32_fallback;
2289FNIEMAIMPLBINU32 iemAImpl_blsmsk_u32, iemAImpl_blsmsk_u32_fallback;
2290/** @} */
2291
2292/** @name Arithmetic assignment operations on quad words (binary).
2293 * @{ */
2294typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU64, (uint64_t *pu64Dst, uint64_t u64Src, uint32_t *pEFlags));
2295typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
2296FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
2297FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
2298FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
2299FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
2300FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
2301FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
2302FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
2303FNIEMAIMPLBINU64 iemAImpl_blsi_u64, iemAImpl_blsi_u64_fallback;
2304FNIEMAIMPLBINU64 iemAImpl_blsr_u64, iemAImpl_blsr_u64_fallback;
2305FNIEMAIMPLBINU64 iemAImpl_blsmsk_u64, iemAImpl_blsmsk_u64_fallback;
2306/** @} */
2307
2308typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINROU8,(uint8_t const *pu8Dst, uint8_t u8Src, uint32_t *pEFlags));
2309typedef FNIEMAIMPLBINROU8 *PFNIEMAIMPLBINROU8;
2310typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINROU16,(uint16_t const *pu16Dst, uint16_t u16Src, uint32_t *pEFlags));
2311typedef FNIEMAIMPLBINROU16 *PFNIEMAIMPLBINROU16;
2312typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINROU32,(uint32_t const *pu32Dst, uint32_t u32Src, uint32_t *pEFlags));
2313typedef FNIEMAIMPLBINROU32 *PFNIEMAIMPLBINROU32;
2314typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINROU64,(uint64_t const *pu64Dst, uint64_t u64Src, uint32_t *pEFlags));
2315typedef FNIEMAIMPLBINROU64 *PFNIEMAIMPLBINROU64;
2316
2317/** @name Compare operations (thrown in with the binary ops).
2318 * @{ */
2319FNIEMAIMPLBINROU8 iemAImpl_cmp_u8;
2320FNIEMAIMPLBINROU16 iemAImpl_cmp_u16;
2321FNIEMAIMPLBINROU32 iemAImpl_cmp_u32;
2322FNIEMAIMPLBINROU64 iemAImpl_cmp_u64;
2323/** @} */
2324
2325/** @name Test operations (thrown in with the binary ops).
2326 * @{ */
2327FNIEMAIMPLBINROU8 iemAImpl_test_u8;
2328FNIEMAIMPLBINROU16 iemAImpl_test_u16;
2329FNIEMAIMPLBINROU32 iemAImpl_test_u32;
2330FNIEMAIMPLBINROU64 iemAImpl_test_u64;
2331/** @} */
2332
2333/** @name Bit operations operations (thrown in with the binary ops).
2334 * @{ */
2335FNIEMAIMPLBINROU16 iemAImpl_bt_u16;
2336FNIEMAIMPLBINROU32 iemAImpl_bt_u32;
2337FNIEMAIMPLBINROU64 iemAImpl_bt_u64;
2338FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
2339FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
2340FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
2341FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
2342FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
2343FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
2344FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
2345FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
2346FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
2347/** @} */
2348
2349/** @name Arithmetic three operand operations on double words (binary).
2350 * @{ */
2351typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32, (uint32_t *pu32Dst, uint32_t u32Src1, uint32_t u32Src2, uint32_t *pEFlags));
2352typedef FNIEMAIMPLBINVEXU32 *PFNIEMAIMPLBINVEXU32;
2353FNIEMAIMPLBINVEXU32 iemAImpl_andn_u32, iemAImpl_andn_u32_fallback;
2354FNIEMAIMPLBINVEXU32 iemAImpl_bextr_u32, iemAImpl_bextr_u32_fallback;
2355FNIEMAIMPLBINVEXU32 iemAImpl_bzhi_u32, iemAImpl_bzhi_u32_fallback;
2356/** @} */
2357
2358/** @name Arithmetic three operand operations on quad words (binary).
2359 * @{ */
2360typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64, (uint64_t *pu64Dst, uint64_t u64Src1, uint64_t u64Src2, uint32_t *pEFlags));
2361typedef FNIEMAIMPLBINVEXU64 *PFNIEMAIMPLBINVEXU64;
2362FNIEMAIMPLBINVEXU64 iemAImpl_andn_u64, iemAImpl_andn_u64_fallback;
2363FNIEMAIMPLBINVEXU64 iemAImpl_bextr_u64, iemAImpl_bextr_u64_fallback;
2364FNIEMAIMPLBINVEXU64 iemAImpl_bzhi_u64, iemAImpl_bzhi_u64_fallback;
2365/** @} */
2366
2367/** @name Arithmetic three operand operations on double words w/o EFLAGS (binary).
2368 * @{ */
2369typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32NOEFL, (uint32_t *pu32Dst, uint32_t u32Src1, uint32_t u32Src2));
2370typedef FNIEMAIMPLBINVEXU32NOEFL *PFNIEMAIMPLBINVEXU32NOEFL;
2371FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pdep_u32, iemAImpl_pdep_u32_fallback;
2372FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pext_u32, iemAImpl_pext_u32_fallback;
2373FNIEMAIMPLBINVEXU32NOEFL iemAImpl_sarx_u32, iemAImpl_sarx_u32_fallback;
2374FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shlx_u32, iemAImpl_shlx_u32_fallback;
2375FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shrx_u32, iemAImpl_shrx_u32_fallback;
2376FNIEMAIMPLBINVEXU32NOEFL iemAImpl_rorx_u32;
2377/** @} */
2378
2379/** @name Arithmetic three operand operations on quad words w/o EFLAGS (binary).
2380 * @{ */
2381typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64NOEFL, (uint64_t *pu64Dst, uint64_t u64Src1, uint64_t u64Src2));
2382typedef FNIEMAIMPLBINVEXU64NOEFL *PFNIEMAIMPLBINVEXU64NOEFL;
2383FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pdep_u64, iemAImpl_pdep_u64_fallback;
2384FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pext_u64, iemAImpl_pext_u64_fallback;
2385FNIEMAIMPLBINVEXU64NOEFL iemAImpl_sarx_u64, iemAImpl_sarx_u64_fallback;
2386FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shlx_u64, iemAImpl_shlx_u64_fallback;
2387FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shrx_u64, iemAImpl_shrx_u64_fallback;
2388FNIEMAIMPLBINVEXU64NOEFL iemAImpl_rorx_u64;
2389/** @} */
2390
2391/** @name MULX 32-bit and 64-bit.
2392 * @{ */
2393typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU32, (uint32_t *puDst1, uint32_t *puDst2, uint32_t uSrc1, uint32_t uSrc2));
2394typedef FNIEMAIMPLMULXVEXU32 *PFNIEMAIMPLMULXVEXU32;
2395FNIEMAIMPLMULXVEXU32 iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback;
2396
2397typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU64, (uint64_t *puDst1, uint64_t *puDst2, uint64_t uSrc1, uint64_t uSrc2));
2398typedef FNIEMAIMPLMULXVEXU64 *PFNIEMAIMPLMULXVEXU64;
2399FNIEMAIMPLMULXVEXU64 iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback;
2400/** @} */
2401
2402
2403/** @name Exchange memory with register operations.
2404 * @{ */
2405IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_locked, (uint8_t *pu8Mem, uint8_t *pu8Reg));
2406IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_locked,(uint16_t *pu16Mem, uint16_t *pu16Reg));
2407IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_locked,(uint32_t *pu32Mem, uint32_t *pu32Reg));
2408IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_locked,(uint64_t *pu64Mem, uint64_t *pu64Reg));
2409IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_unlocked, (uint8_t *pu8Mem, uint8_t *pu8Reg));
2410IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_unlocked,(uint16_t *pu16Mem, uint16_t *pu16Reg));
2411IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_unlocked,(uint32_t *pu32Mem, uint32_t *pu32Reg));
2412IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_unlocked,(uint64_t *pu64Mem, uint64_t *pu64Reg));
2413/** @} */
2414
2415/** @name Exchange and add operations.
2416 * @{ */
2417IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t *pu8Dst, uint8_t *pu8Reg, uint32_t *pEFlags));
2418IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t *pu16Dst, uint16_t *pu16Reg, uint32_t *pEFlags));
2419IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t *pu32Dst, uint32_t *pu32Reg, uint32_t *pEFlags));
2420IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t *pu64Dst, uint64_t *pu64Reg, uint32_t *pEFlags));
2421IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t *pu8Dst, uint8_t *pu8Reg, uint32_t *pEFlags));
2422IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t *pu16Dst, uint16_t *pu16Reg, uint32_t *pEFlags));
2423IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t *pu32Dst, uint32_t *pu32Reg, uint32_t *pEFlags));
2424IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t *pu64Dst, uint64_t *pu64Reg, uint32_t *pEFlags));
2425/** @} */
2426
2427/** @name Compare and exchange.
2428 * @{ */
2429IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t *pu8Dst, uint8_t *puAl, uint8_t uSrcReg, uint32_t *pEFlags));
2430IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t *pu8Dst, uint8_t *puAl, uint8_t uSrcReg, uint32_t *pEFlags));
2431IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t *pu16Dst, uint16_t *puAx, uint16_t uSrcReg, uint32_t *pEFlags));
2432IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t *pu16Dst, uint16_t *puAx, uint16_t uSrcReg, uint32_t *pEFlags));
2433IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t *pu32Dst, uint32_t *puEax, uint32_t uSrcReg, uint32_t *pEFlags));
2434IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t *pu32Dst, uint32_t *puEax, uint32_t uSrcReg, uint32_t *pEFlags));
2435#if ARCH_BITS == 32
2436IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t *pu64Dst, uint64_t *puRax, uint64_t *puSrcReg, uint32_t *pEFlags));
2437IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t *pu64Dst, uint64_t *puRax, uint64_t *puSrcReg, uint32_t *pEFlags));
2438#else
2439IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t *pu64Dst, uint64_t *puRax, uint64_t uSrcReg, uint32_t *pEFlags));
2440IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t *pu64Dst, uint64_t *puRax, uint64_t uSrcReg, uint32_t *pEFlags));
2441#endif
2442IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
2443 uint32_t *pEFlags));
2444IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
2445 uint32_t *pEFlags));
2446IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
2447 uint32_t *pEFlags));
2448IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
2449 uint32_t *pEFlags));
2450#ifndef RT_ARCH_ARM64
2451IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
2452 PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
2453#endif
2454/** @} */
2455
2456/** @name Memory ordering
2457 * @{ */
2458typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
2459typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
2460IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
2461IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
2462IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
2463#ifndef RT_ARCH_ARM64
2464IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
2465#endif
2466/** @} */
2467
2468/** @name Double precision shifts
2469 * @{ */
2470typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t *pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t *pEFlags));
2471typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
2472typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t *pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t *pEFlags));
2473typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
2474typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t *pEFlags));
2475typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
2476FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16, iemAImpl_shld_u16_amd, iemAImpl_shld_u16_intel;
2477FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32, iemAImpl_shld_u32_amd, iemAImpl_shld_u32_intel;
2478FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64, iemAImpl_shld_u64_amd, iemAImpl_shld_u64_intel;
2479FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16, iemAImpl_shrd_u16_amd, iemAImpl_shrd_u16_intel;
2480FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32, iemAImpl_shrd_u32_amd, iemAImpl_shrd_u32_intel;
2481FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64, iemAImpl_shrd_u64_amd, iemAImpl_shrd_u64_intel;
2482/** @} */
2483
2484
2485/** @name Bit search operations (thrown in with the binary ops).
2486 * @{ */
2487FNIEMAIMPLBINU16 iemAImpl_bsf_u16, iemAImpl_bsf_u16_amd, iemAImpl_bsf_u16_intel;
2488FNIEMAIMPLBINU32 iemAImpl_bsf_u32, iemAImpl_bsf_u32_amd, iemAImpl_bsf_u32_intel;
2489FNIEMAIMPLBINU64 iemAImpl_bsf_u64, iemAImpl_bsf_u64_amd, iemAImpl_bsf_u64_intel;
2490FNIEMAIMPLBINU16 iemAImpl_bsr_u16, iemAImpl_bsr_u16_amd, iemAImpl_bsr_u16_intel;
2491FNIEMAIMPLBINU32 iemAImpl_bsr_u32, iemAImpl_bsr_u32_amd, iemAImpl_bsr_u32_intel;
2492FNIEMAIMPLBINU64 iemAImpl_bsr_u64, iemAImpl_bsr_u64_amd, iemAImpl_bsr_u64_intel;
2493FNIEMAIMPLBINU16 iemAImpl_lzcnt_u16, iemAImpl_lzcnt_u16_amd, iemAImpl_lzcnt_u16_intel;
2494FNIEMAIMPLBINU32 iemAImpl_lzcnt_u32, iemAImpl_lzcnt_u32_amd, iemAImpl_lzcnt_u32_intel;
2495FNIEMAIMPLBINU64 iemAImpl_lzcnt_u64, iemAImpl_lzcnt_u64_amd, iemAImpl_lzcnt_u64_intel;
2496FNIEMAIMPLBINU16 iemAImpl_tzcnt_u16, iemAImpl_tzcnt_u16_amd, iemAImpl_tzcnt_u16_intel;
2497FNIEMAIMPLBINU32 iemAImpl_tzcnt_u32, iemAImpl_tzcnt_u32_amd, iemAImpl_tzcnt_u32_intel;
2498FNIEMAIMPLBINU64 iemAImpl_tzcnt_u64, iemAImpl_tzcnt_u64_amd, iemAImpl_tzcnt_u64_intel;
2499FNIEMAIMPLBINU16 iemAImpl_popcnt_u16, iemAImpl_popcnt_u16_fallback;
2500FNIEMAIMPLBINU32 iemAImpl_popcnt_u32, iemAImpl_popcnt_u32_fallback;
2501FNIEMAIMPLBINU64 iemAImpl_popcnt_u64, iemAImpl_popcnt_u64_fallback;
2502/** @} */
2503
2504/** @name Signed multiplication operations (thrown in with the binary ops).
2505 * @{ */
2506FNIEMAIMPLBINU16 iemAImpl_imul_two_u16, iemAImpl_imul_two_u16_amd, iemAImpl_imul_two_u16_intel;
2507FNIEMAIMPLBINU32 iemAImpl_imul_two_u32, iemAImpl_imul_two_u32_amd, iemAImpl_imul_two_u32_intel;
2508FNIEMAIMPLBINU64 iemAImpl_imul_two_u64, iemAImpl_imul_two_u64_amd, iemAImpl_imul_two_u64_intel;
2509/** @} */
2510
2511/** @name Arithmetic assignment operations on bytes (unary).
2512 * @{ */
2513typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t *pu8Dst, uint32_t *pEFlags));
2514typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
2515FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
2516FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
2517FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
2518FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
2519/** @} */
2520
2521/** @name Arithmetic assignment operations on words (unary).
2522 * @{ */
2523typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t *pu16Dst, uint32_t *pEFlags));
2524typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
2525FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
2526FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
2527FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
2528FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
2529/** @} */
2530
2531/** @name Arithmetic assignment operations on double words (unary).
2532 * @{ */
2533typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t *pu32Dst, uint32_t *pEFlags));
2534typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
2535FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
2536FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
2537FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
2538FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
2539/** @} */
2540
2541/** @name Arithmetic assignment operations on quad words (unary).
2542 * @{ */
2543typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t *pu64Dst, uint32_t *pEFlags));
2544typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
2545FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
2546FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
2547FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
2548FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
2549/** @} */
2550
2551
2552/** @name Shift operations on bytes (Group 2).
2553 * @{ */
2554typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU8,(uint8_t *pu8Dst, uint8_t cShift, uint32_t *pEFlags));
2555typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
2556FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8, iemAImpl_rol_u8_amd, iemAImpl_rol_u8_intel;
2557FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8, iemAImpl_ror_u8_amd, iemAImpl_ror_u8_intel;
2558FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8, iemAImpl_rcl_u8_amd, iemAImpl_rcl_u8_intel;
2559FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8, iemAImpl_rcr_u8_amd, iemAImpl_rcr_u8_intel;
2560FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8, iemAImpl_shl_u8_amd, iemAImpl_shl_u8_intel;
2561FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8, iemAImpl_shr_u8_amd, iemAImpl_shr_u8_intel;
2562FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8, iemAImpl_sar_u8_amd, iemAImpl_sar_u8_intel;
2563/** @} */
2564
2565/** @name Shift operations on words (Group 2).
2566 * @{ */
2567typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU16,(uint16_t *pu16Dst, uint8_t cShift, uint32_t *pEFlags));
2568typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
2569FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16, iemAImpl_rol_u16_amd, iemAImpl_rol_u16_intel;
2570FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16, iemAImpl_ror_u16_amd, iemAImpl_ror_u16_intel;
2571FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16, iemAImpl_rcl_u16_amd, iemAImpl_rcl_u16_intel;
2572FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16, iemAImpl_rcr_u16_amd, iemAImpl_rcr_u16_intel;
2573FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16, iemAImpl_shl_u16_amd, iemAImpl_shl_u16_intel;
2574FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16, iemAImpl_shr_u16_amd, iemAImpl_shr_u16_intel;
2575FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16, iemAImpl_sar_u16_amd, iemAImpl_sar_u16_intel;
2576/** @} */
2577
2578/** @name Shift operations on double words (Group 2).
2579 * @{ */
2580typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU32,(uint32_t *pu32Dst, uint8_t cShift, uint32_t *pEFlags));
2581typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
2582FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32, iemAImpl_rol_u32_amd, iemAImpl_rol_u32_intel;
2583FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32, iemAImpl_ror_u32_amd, iemAImpl_ror_u32_intel;
2584FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32, iemAImpl_rcl_u32_amd, iemAImpl_rcl_u32_intel;
2585FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32, iemAImpl_rcr_u32_amd, iemAImpl_rcr_u32_intel;
2586FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32, iemAImpl_shl_u32_amd, iemAImpl_shl_u32_intel;
2587FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32, iemAImpl_shr_u32_amd, iemAImpl_shr_u32_intel;
2588FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32, iemAImpl_sar_u32_amd, iemAImpl_sar_u32_intel;
2589/** @} */
2590
2591/** @name Shift operations on words (Group 2).
2592 * @{ */
2593typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU64,(uint64_t *pu64Dst, uint8_t cShift, uint32_t *pEFlags));
2594typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
2595FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64, iemAImpl_rol_u64_amd, iemAImpl_rol_u64_intel;
2596FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64, iemAImpl_ror_u64_amd, iemAImpl_ror_u64_intel;
2597FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64, iemAImpl_rcl_u64_amd, iemAImpl_rcl_u64_intel;
2598FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64, iemAImpl_rcr_u64_amd, iemAImpl_rcr_u64_intel;
2599FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64, iemAImpl_shl_u64_amd, iemAImpl_shl_u64_intel;
2600FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64, iemAImpl_shr_u64_amd, iemAImpl_shr_u64_intel;
2601FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64, iemAImpl_sar_u64_amd, iemAImpl_sar_u64_intel;
2602/** @} */
2603
2604/** @name Multiplication and division operations.
2605 * @{ */
2606typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t *pu16AX, uint8_t u8FactorDivisor, uint32_t *pEFlags));
2607typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
2608FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_mul_u8_amd, iemAImpl_mul_u8_intel;
2609FNIEMAIMPLMULDIVU8 iemAImpl_imul_u8, iemAImpl_imul_u8_amd, iemAImpl_imul_u8_intel;
2610FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_div_u8_amd, iemAImpl_div_u8_intel;
2611FNIEMAIMPLMULDIVU8 iemAImpl_idiv_u8, iemAImpl_idiv_u8_amd, iemAImpl_idiv_u8_intel;
2612
2613typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t *pu16AX, uint16_t *pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
2614typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
2615FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_mul_u16_amd, iemAImpl_mul_u16_intel;
2616FNIEMAIMPLMULDIVU16 iemAImpl_imul_u16, iemAImpl_imul_u16_amd, iemAImpl_imul_u16_intel;
2617FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_div_u16_amd, iemAImpl_div_u16_intel;
2618FNIEMAIMPLMULDIVU16 iemAImpl_idiv_u16, iemAImpl_idiv_u16_amd, iemAImpl_idiv_u16_intel;
2619
2620typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t *pu32EAX, uint32_t *pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
2621typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
2622FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_mul_u32_amd, iemAImpl_mul_u32_intel;
2623FNIEMAIMPLMULDIVU32 iemAImpl_imul_u32, iemAImpl_imul_u32_amd, iemAImpl_imul_u32_intel;
2624FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_div_u32_amd, iemAImpl_div_u32_intel;
2625FNIEMAIMPLMULDIVU32 iemAImpl_idiv_u32, iemAImpl_idiv_u32_amd, iemAImpl_idiv_u32_intel;
2626
2627typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t *pu64RAX, uint64_t *pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
2628typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
2629FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_mul_u64_amd, iemAImpl_mul_u64_intel;
2630FNIEMAIMPLMULDIVU64 iemAImpl_imul_u64, iemAImpl_imul_u64_amd, iemAImpl_imul_u64_intel;
2631FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_div_u64_amd, iemAImpl_div_u64_intel;
2632FNIEMAIMPLMULDIVU64 iemAImpl_idiv_u64, iemAImpl_idiv_u64_amd, iemAImpl_idiv_u64_intel;
2633/** @} */
2634
2635/** @name Byte Swap.
2636 * @{ */
2637IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t *pu32Dst)); /* Yes, 32-bit register access. */
2638IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
2639IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
2640/** @} */
2641
2642/** @name Misc.
2643 * @{ */
2644FNIEMAIMPLBINU16 iemAImpl_arpl;
2645/** @} */
2646
2647/** @name RDRAND and RDSEED
2648 * @{ */
2649typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU16,(uint16_t *puDst, uint32_t *pEFlags));
2650typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU32,(uint32_t *puDst, uint32_t *pEFlags));
2651typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU64,(uint64_t *puDst, uint32_t *pEFlags));
2652typedef FNIEMAIMPLRDRANDSEEDU16 *PFNIEMAIMPLRDRANDSEEDU16;
2653typedef FNIEMAIMPLRDRANDSEEDU32 *PFNIEMAIMPLRDRANDSEEDU32;
2654typedef FNIEMAIMPLRDRANDSEEDU64 *PFNIEMAIMPLRDRANDSEEDU64;
2655
2656FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdrand_u16, iemAImpl_rdrand_u16_fallback;
2657FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdrand_u32, iemAImpl_rdrand_u32_fallback;
2658FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdrand_u64, iemAImpl_rdrand_u64_fallback;
2659FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdseed_u16, iemAImpl_rdseed_u16_fallback;
2660FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdseed_u32, iemAImpl_rdseed_u32_fallback;
2661FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdseed_u64, iemAImpl_rdseed_u64_fallback;
2662/** @} */
2663
2664/** @name ADOX and ADCX
2665 * @{ */
2666typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLADXU32,(uint32_t *puDst, uint32_t *pfEFlags, uint32_t uSrc));
2667typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLADXU64,(uint64_t *puDst, uint32_t *pfEFlags, uint64_t uSrc));
2668typedef FNIEMAIMPLADXU32 *PFNIEMAIMPLADXU32;
2669typedef FNIEMAIMPLADXU64 *PFNIEMAIMPLADXU64;
2670
2671FNIEMAIMPLADXU32 iemAImpl_adcx_u32, iemAImpl_adcx_u32_fallback;
2672FNIEMAIMPLADXU64 iemAImpl_adcx_u64, iemAImpl_adcx_u64_fallback;
2673FNIEMAIMPLADXU32 iemAImpl_adox_u32, iemAImpl_adox_u32_fallback;
2674FNIEMAIMPLADXU64 iemAImpl_adox_u64, iemAImpl_adox_u64_fallback;
2675/** @} */
2676
2677/** @name FPU operations taking a 32-bit float argument
2678 * @{ */
2679typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2680 PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
2681typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
2682
2683typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2684 PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
2685typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
2686
2687FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
2688FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
2689FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
2690FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
2691FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
2692FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
2693FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
2694
2695IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
2696IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2697 PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
2698/** @} */
2699
2700/** @name FPU operations taking a 64-bit float argument
2701 * @{ */
2702typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2703 PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
2704typedef FNIEMAIMPLFPUR64FSW *PFNIEMAIMPLFPUR64FSW;
2705
2706typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2707 PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
2708typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
2709
2710FNIEMAIMPLFPUR64FSW iemAImpl_fcom_r80_by_r64;
2711FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
2712FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
2713FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
2714FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
2715FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
2716FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
2717
2718IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
2719IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2720 PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
2721/** @} */
2722
2723/** @name FPU operations taking a 80-bit float argument
2724 * @{ */
2725typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2726 PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
2727typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
2728FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
2729FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
2730FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
2731FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
2732FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
2733FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
2734FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
2735FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
2736FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
2737
2738FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80, iemAImpl_fpatan_r80_by_r80_amd, iemAImpl_fpatan_r80_by_r80_intel;
2739FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80, iemAImpl_fyl2x_r80_by_r80_amd, iemAImpl_fyl2x_r80_by_r80_intel;
2740FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80, iemAImpl_fyl2xp1_r80_by_r80_amd, iemAImpl_fyl2xp1_r80_by_r80_intel;
2741
2742typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2743 PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
2744typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
2745FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
2746FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
2747
2748typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
2749 PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
2750typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
2751FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
2752FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
2753
2754typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
2755typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
2756FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
2757FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
2758FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80, iemAImpl_f2xm1_r80_amd, iemAImpl_f2xm1_r80_intel;
2759FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
2760FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
2761FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80, iemAImpl_fsin_r80_amd, iemAImpl_fsin_r80_intel;
2762FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80, iemAImpl_fcos_r80_amd, iemAImpl_fcos_r80_intel;
2763
2764typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
2765typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
2766FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
2767FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
2768
2769typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
2770typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
2771FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
2772FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
2773FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
2774FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
2775FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
2776FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
2777FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
2778
2779typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
2780 PCRTFLOAT80U pr80Val));
2781typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
2782FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80, iemAImpl_fptan_r80_r80_amd, iemAImpl_fptan_r80_r80_intel;
2783FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
2784FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80, iemAImpl_fsincos_r80_r80_amd, iemAImpl_fsincos_r80_r80_intel;
2785
2786IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
2787IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2788 PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
2789
2790IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_d80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTPBCD80U pd80Val));
2791IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_d80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2792 PRTPBCD80U pd80Dst, PCRTFLOAT80U pr80Src));
2793
2794/** @} */
2795
2796/** @name FPU operations taking a 16-bit signed integer argument
2797 * @{ */
2798typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2799 PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
2800typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
2801typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI16,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
2802 int16_t *pi16Dst, PCRTFLOAT80U pr80Src));
2803typedef FNIEMAIMPLFPUSTR80TOI16 *PFNIEMAIMPLFPUSTR80TOI16;
2804
2805FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
2806FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
2807FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
2808FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
2809FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
2810FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
2811
2812typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2813 PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
2814typedef FNIEMAIMPLFPUI16FSW *PFNIEMAIMPLFPUI16FSW;
2815FNIEMAIMPLFPUI16FSW iemAImpl_ficom_r80_by_i16;
2816
2817IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
2818FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fist_r80_to_i16;
2819FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fistt_r80_to_i16, iemAImpl_fistt_r80_to_i16_amd, iemAImpl_fistt_r80_to_i16_intel;
2820/** @} */
2821
2822/** @name FPU operations taking a 32-bit signed integer argument
2823 * @{ */
2824typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2825 PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
2826typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
2827typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI32,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
2828 int32_t *pi32Dst, PCRTFLOAT80U pr80Src));
2829typedef FNIEMAIMPLFPUSTR80TOI32 *PFNIEMAIMPLFPUSTR80TOI32;
2830
2831FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
2832FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
2833FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
2834FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
2835FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
2836FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
2837
2838typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2839 PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
2840typedef FNIEMAIMPLFPUI32FSW *PFNIEMAIMPLFPUI32FSW;
2841FNIEMAIMPLFPUI32FSW iemAImpl_ficom_r80_by_i32;
2842
2843IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
2844FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fist_r80_to_i32;
2845FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fistt_r80_to_i32;
2846/** @} */
2847
2848/** @name FPU operations taking a 64-bit signed integer argument
2849 * @{ */
2850typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI64,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
2851 int64_t *pi64Dst, PCRTFLOAT80U pr80Src));
2852typedef FNIEMAIMPLFPUSTR80TOI64 *PFNIEMAIMPLFPUSTR80TOI64;
2853
2854IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
2855FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fist_r80_to_i64;
2856FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fistt_r80_to_i64;
2857/** @} */
2858
2859
2860/** Temporary type representing a 256-bit vector register. */
2861typedef struct { uint64_t au64[4]; } IEMVMM256;
2862/** Temporary type pointing to a 256-bit vector register. */
2863typedef IEMVMM256 *PIEMVMM256;
2864/** Temporary type pointing to a const 256-bit vector register. */
2865typedef IEMVMM256 *PCIEMVMM256;
2866
2867
2868/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
2869 * @{ */
2870typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t *puDst, uint64_t const *puSrc));
2871typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
2872typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U128,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
2873typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
2874typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U128,(PX86XSAVEAREA pExtState, PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
2875typedef FNIEMAIMPLMEDIAF3U128 *PFNIEMAIMPLMEDIAF3U128;
2876typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U256,(PX86XSAVEAREA pExtState, PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
2877typedef FNIEMAIMPLMEDIAF3U256 *PFNIEMAIMPLMEDIAF3U256;
2878typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U64,(uint64_t *puDst, uint64_t const *puSrc));
2879typedef FNIEMAIMPLMEDIAOPTF2U64 *PFNIEMAIMPLMEDIAOPTF2U64;
2880typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128,(PRTUINT128U puDst, PCRTUINT128U puSrc));
2881typedef FNIEMAIMPLMEDIAOPTF2U128 *PFNIEMAIMPLMEDIAOPTF2U128;
2882typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
2883typedef FNIEMAIMPLMEDIAOPTF3U128 *PFNIEMAIMPLMEDIAOPTF3U128;
2884typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
2885typedef FNIEMAIMPLMEDIAOPTF3U256 *PFNIEMAIMPLMEDIAOPTF3U256;
2886typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256,(PRTUINT256U puDst, PCRTUINT256U puSrc));
2887typedef FNIEMAIMPLMEDIAOPTF2U256 *PFNIEMAIMPLMEDIAOPTF2U256;
2888FNIEMAIMPLMEDIAF2U64 iemAImpl_pshufb_u64, iemAImpl_pshufb_u64_fallback;
2889FNIEMAIMPLMEDIAF2U64 iemAImpl_pand_u64, iemAImpl_pandn_u64, iemAImpl_por_u64, iemAImpl_pxor_u64;
2890FNIEMAIMPLMEDIAF2U64 iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
2891FNIEMAIMPLMEDIAF2U64 iemAImpl_pcmpgtb_u64, iemAImpl_pcmpgtw_u64, iemAImpl_pcmpgtd_u64;
2892FNIEMAIMPLMEDIAF2U64 iemAImpl_paddb_u64, iemAImpl_paddsb_u64, iemAImpl_paddusb_u64;
2893FNIEMAIMPLMEDIAF2U64 iemAImpl_paddw_u64, iemAImpl_paddsw_u64, iemAImpl_paddusw_u64;
2894FNIEMAIMPLMEDIAF2U64 iemAImpl_paddd_u64;
2895FNIEMAIMPLMEDIAF2U64 iemAImpl_paddq_u64;
2896FNIEMAIMPLMEDIAF2U64 iemAImpl_psubb_u64, iemAImpl_psubsb_u64, iemAImpl_psubusb_u64;
2897FNIEMAIMPLMEDIAF2U64 iemAImpl_psubw_u64, iemAImpl_psubsw_u64, iemAImpl_psubusw_u64;
2898FNIEMAIMPLMEDIAF2U64 iemAImpl_psubd_u64;
2899FNIEMAIMPLMEDIAF2U64 iemAImpl_psubq_u64;
2900FNIEMAIMPLMEDIAF2U64 iemAImpl_pmaddwd_u64;
2901FNIEMAIMPLMEDIAF2U64 iemAImpl_pmullw_u64, iemAImpl_pmulhw_u64;
2902FNIEMAIMPLMEDIAF2U64 iemAImpl_pminub_u64, iemAImpl_pmaxub_u64;
2903FNIEMAIMPLMEDIAF2U64 iemAImpl_pminsw_u64, iemAImpl_pmaxsw_u64;
2904FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsb_u64, iemAImpl_pabsb_u64_fallback;
2905FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsw_u64, iemAImpl_pabsw_u64_fallback;
2906FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsd_u64, iemAImpl_pabsd_u64_fallback;
2907FNIEMAIMPLMEDIAF2U64 iemAImpl_psignb_u64, iemAImpl_psignb_u64_fallback;
2908FNIEMAIMPLMEDIAF2U64 iemAImpl_psignw_u64, iemAImpl_psignw_u64_fallback;
2909FNIEMAIMPLMEDIAF2U64 iemAImpl_psignd_u64, iemAImpl_psignd_u64_fallback;
2910FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddw_u64, iemAImpl_phaddw_u64_fallback;
2911FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddd_u64, iemAImpl_phaddd_u64_fallback;
2912FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubw_u64, iemAImpl_phsubw_u64_fallback;
2913FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubd_u64, iemAImpl_phsubd_u64_fallback;
2914FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddsw_u64, iemAImpl_phaddsw_u64_fallback;
2915FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubsw_u64, iemAImpl_phsubsw_u64_fallback;
2916FNIEMAIMPLMEDIAF2U64 iemAImpl_pmaddubsw_u64, iemAImpl_pmaddubsw_u64_fallback;
2917FNIEMAIMPLMEDIAF2U64 iemAImpl_pmulhrsw_u64, iemAImpl_pmulhrsw_u64_fallback;
2918FNIEMAIMPLMEDIAF2U64 iemAImpl_pmuludq_u64;
2919FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllw_u64, iemAImpl_psrlw_u64, iemAImpl_psraw_u64;
2920FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pslld_u64, iemAImpl_psrld_u64, iemAImpl_psrad_u64;
2921FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllq_u64, iemAImpl_psrlq_u64;
2922FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packsswb_u64, iemAImpl_packuswb_u64;
2923FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packssdw_u64;
2924FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhuw_u64;
2925FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pavgb_u64, iemAImpl_pavgw_u64;
2926FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psadbw_u64;
2927
2928FNIEMAIMPLMEDIAF2U128 iemAImpl_pshufb_u128, iemAImpl_pshufb_u128_fallback;
2929FNIEMAIMPLMEDIAF2U128 iemAImpl_pand_u128, iemAImpl_pandn_u128, iemAImpl_por_u128, iemAImpl_pxor_u128;
2930FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
2931FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpeqq_u128, iemAImpl_pcmpeqq_u128_fallback;
2932FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpgtb_u128, iemAImpl_pcmpgtw_u128, iemAImpl_pcmpgtd_u128;
2933FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpgtq_u128, iemAImpl_pcmpgtq_u128_fallback;
2934FNIEMAIMPLMEDIAF2U128 iemAImpl_paddb_u128, iemAImpl_paddsb_u128, iemAImpl_paddusb_u128;
2935FNIEMAIMPLMEDIAF2U128 iemAImpl_paddw_u128, iemAImpl_paddsw_u128, iemAImpl_paddusw_u128;
2936FNIEMAIMPLMEDIAF2U128 iemAImpl_paddd_u128;
2937FNIEMAIMPLMEDIAF2U128 iemAImpl_paddq_u128;
2938FNIEMAIMPLMEDIAF2U128 iemAImpl_psubb_u128, iemAImpl_psubsb_u128, iemAImpl_psubusb_u128;
2939FNIEMAIMPLMEDIAF2U128 iemAImpl_psubw_u128, iemAImpl_psubsw_u128, iemAImpl_psubusw_u128;
2940FNIEMAIMPLMEDIAF2U128 iemAImpl_psubd_u128;
2941FNIEMAIMPLMEDIAF2U128 iemAImpl_psubq_u128;
2942FNIEMAIMPLMEDIAF2U128 iemAImpl_pmullw_u128, iemAImpl_pmullw_u128_fallback;
2943FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulhw_u128;
2944FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulld_u128, iemAImpl_pmulld_u128_fallback;
2945FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaddwd_u128;
2946FNIEMAIMPLMEDIAF2U128 iemAImpl_pminub_u128;
2947FNIEMAIMPLMEDIAF2U128 iemAImpl_pminud_u128, iemAImpl_pminud_u128_fallback;
2948FNIEMAIMPLMEDIAF2U128 iemAImpl_pminuw_u128, iemAImpl_pminuw_u128_fallback;
2949FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsb_u128, iemAImpl_pminsb_u128_fallback;
2950FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsd_u128, iemAImpl_pminsd_u128_fallback;
2951FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsw_u128, iemAImpl_pminsw_u128_fallback;
2952FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxub_u128;
2953FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxud_u128, iemAImpl_pmaxud_u128_fallback;
2954FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxuw_u128, iemAImpl_pmaxuw_u128_fallback;
2955FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsb_u128, iemAImpl_pmaxsb_u128_fallback;
2956FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsw_u128;
2957FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsd_u128, iemAImpl_pmaxsd_u128_fallback;
2958FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsb_u128, iemAImpl_pabsb_u128_fallback;
2959FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsw_u128, iemAImpl_pabsw_u128_fallback;
2960FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsd_u128, iemAImpl_pabsd_u128_fallback;
2961FNIEMAIMPLMEDIAF2U128 iemAImpl_psignb_u128, iemAImpl_psignb_u128_fallback;
2962FNIEMAIMPLMEDIAF2U128 iemAImpl_psignw_u128, iemAImpl_psignw_u128_fallback;
2963FNIEMAIMPLMEDIAF2U128 iemAImpl_psignd_u128, iemAImpl_psignd_u128_fallback;
2964FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddw_u128, iemAImpl_phaddw_u128_fallback;
2965FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddd_u128, iemAImpl_phaddd_u128_fallback;
2966FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubw_u128, iemAImpl_phsubw_u128_fallback;
2967FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubd_u128, iemAImpl_phsubd_u128_fallback;
2968FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddsw_u128, iemAImpl_phaddsw_u128_fallback;
2969FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubsw_u128, iemAImpl_phsubsw_u128_fallback;
2970FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaddubsw_u128, iemAImpl_pmaddubsw_u128_fallback;
2971FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulhrsw_u128, iemAImpl_pmulhrsw_u128_fallback;
2972FNIEMAIMPLMEDIAF2U128 iemAImpl_pmuludq_u128;
2973FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packsswb_u128, iemAImpl_packuswb_u128;
2974FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packssdw_u128, iemAImpl_packusdw_u128;
2975FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllw_u128, iemAImpl_psrlw_u128, iemAImpl_psraw_u128;
2976FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pslld_u128, iemAImpl_psrld_u128, iemAImpl_psrad_u128;
2977FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllq_u128, iemAImpl_psrlq_u128;
2978FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhuw_u128;
2979FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pavgb_u128, iemAImpl_pavgw_u128;
2980FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psadbw_u128;
2981FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuldq_u128, iemAImpl_pmuldq_u128_fallback;
2982FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpcklps_u128, iemAImpl_unpcklpd_u128;
2983FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpckhps_u128, iemAImpl_unpckhpd_u128;
2984FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phminposuw_u128, iemAImpl_phminposuw_u128_fallback;
2985
2986FNIEMAIMPLMEDIAF3U128 iemAImpl_vpshufb_u128, iemAImpl_vpshufb_u128_fallback;
2987FNIEMAIMPLMEDIAF3U128 iemAImpl_vpand_u128, iemAImpl_vpand_u128_fallback;
2988FNIEMAIMPLMEDIAF3U128 iemAImpl_vpandn_u128, iemAImpl_vpandn_u128_fallback;
2989FNIEMAIMPLMEDIAF3U128 iemAImpl_vpor_u128, iemAImpl_vpor_u128_fallback;
2990FNIEMAIMPLMEDIAF3U128 iemAImpl_vpxor_u128, iemAImpl_vpxor_u128_fallback;
2991FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqb_u128, iemAImpl_vpcmpeqb_u128_fallback;
2992FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqw_u128, iemAImpl_vpcmpeqw_u128_fallback;
2993FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqd_u128, iemAImpl_vpcmpeqd_u128_fallback;
2994FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqq_u128, iemAImpl_vpcmpeqq_u128_fallback;
2995FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtb_u128, iemAImpl_vpcmpgtb_u128_fallback;
2996FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtw_u128, iemAImpl_vpcmpgtw_u128_fallback;
2997FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtd_u128, iemAImpl_vpcmpgtd_u128_fallback;
2998FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtq_u128, iemAImpl_vpcmpgtq_u128_fallback;
2999FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddb_u128, iemAImpl_vpaddb_u128_fallback;
3000FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddw_u128, iemAImpl_vpaddw_u128_fallback;
3001FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddd_u128, iemAImpl_vpaddd_u128_fallback;
3002FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddq_u128, iemAImpl_vpaddq_u128_fallback;
3003FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubb_u128, iemAImpl_vpsubb_u128_fallback;
3004FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubw_u128, iemAImpl_vpsubw_u128_fallback;
3005FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubd_u128, iemAImpl_vpsubd_u128_fallback;
3006FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubq_u128, iemAImpl_vpsubq_u128_fallback;
3007FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminub_u128, iemAImpl_vpminub_u128_fallback;
3008FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminuw_u128, iemAImpl_vpminuw_u128_fallback;
3009FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminud_u128, iemAImpl_vpminud_u128_fallback;
3010FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsb_u128, iemAImpl_vpminsb_u128_fallback;
3011FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsw_u128, iemAImpl_vpminsw_u128_fallback;
3012FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsd_u128, iemAImpl_vpminsd_u128_fallback;
3013FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxub_u128, iemAImpl_vpmaxub_u128_fallback;
3014FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxuw_u128, iemAImpl_vpmaxuw_u128_fallback;
3015FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxud_u128, iemAImpl_vpmaxud_u128_fallback;
3016FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsb_u128, iemAImpl_vpmaxsb_u128_fallback;
3017FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsw_u128, iemAImpl_vpmaxsw_u128_fallback;
3018FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsd_u128, iemAImpl_vpmaxsd_u128_fallback;
3019FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpacksswb_u128, iemAImpl_vpacksswb_u128_fallback;
3020FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackssdw_u128, iemAImpl_vpackssdw_u128_fallback;
3021FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackuswb_u128, iemAImpl_vpackuswb_u128_fallback;
3022FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackusdw_u128, iemAImpl_vpackusdw_u128_fallback;
3023FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmullw_u128, iemAImpl_vpmullw_u128_fallback;
3024FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulld_u128, iemAImpl_vpmulld_u128_fallback;
3025FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhw_u128, iemAImpl_vpmulhw_u128_fallback;
3026FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhuw_u128, iemAImpl_vpmulhuw_u128_fallback;
3027FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgb_u128, iemAImpl_vpavgb_u128_fallback;
3028FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgw_u128, iemAImpl_vpavgw_u128_fallback;
3029FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignb_u128, iemAImpl_vpsignb_u128_fallback;
3030FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignw_u128, iemAImpl_vpsignw_u128_fallback;
3031FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignd_u128, iemAImpl_vpsignd_u128_fallback;
3032FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddw_u128, iemAImpl_vphaddw_u128_fallback;
3033FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddd_u128, iemAImpl_vphaddd_u128_fallback;
3034FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubw_u128, iemAImpl_vphsubw_u128_fallback;
3035FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubd_u128, iemAImpl_vphsubd_u128_fallback;
3036FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddsw_u128, iemAImpl_vphaddsw_u128_fallback;
3037FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubsw_u128, iemAImpl_vphsubsw_u128_fallback;
3038FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddubsw_u128, iemAImpl_vpmaddubsw_u128_fallback;
3039FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhrsw_u128, iemAImpl_vpmulhrsw_u128_fallback;
3040FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsadbw_u128, iemAImpl_vpsadbw_u128_fallback;
3041FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuldq_u128, iemAImpl_vpmuldq_u128_fallback;
3042FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuludq_u128, iemAImpl_vpmuludq_u128_fallback;
3043FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsb_u128, iemAImpl_vpsubsb_u128_fallback;
3044FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsw_u128, iemAImpl_vpsubsw_u128_fallback;
3045FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusb_u128, iemAImpl_vpsubusb_u128_fallback;
3046FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusw_u128, iemAImpl_vpsubusw_u128_fallback;
3047FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusb_u128, iemAImpl_vpaddusb_u128_fallback;
3048FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusw_u128, iemAImpl_vpaddusw_u128_fallback;
3049FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsb_u128, iemAImpl_vpaddsb_u128_fallback;
3050FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsw_u128, iemAImpl_vpaddsw_u128_fallback;
3051
3052FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsb_u128, iemAImpl_vpabsb_u128_fallback;
3053FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsw_u128, iemAImpl_vpabsd_u128_fallback;
3054FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsd_u128, iemAImpl_vpabsw_u128_fallback;
3055FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vphminposuw_u128, iemAImpl_vphminposuw_u128_fallback;
3056
3057FNIEMAIMPLMEDIAF3U256 iemAImpl_vpshufb_u256, iemAImpl_vpshufb_u256_fallback;
3058FNIEMAIMPLMEDIAF3U256 iemAImpl_vpand_u256, iemAImpl_vpand_u256_fallback;
3059FNIEMAIMPLMEDIAF3U256 iemAImpl_vpandn_u256, iemAImpl_vpandn_u256_fallback;
3060FNIEMAIMPLMEDIAF3U256 iemAImpl_vpor_u256, iemAImpl_vpor_u256_fallback;
3061FNIEMAIMPLMEDIAF3U256 iemAImpl_vpxor_u256, iemAImpl_vpxor_u256_fallback;
3062FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqb_u256, iemAImpl_vpcmpeqb_u256_fallback;
3063FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqw_u256, iemAImpl_vpcmpeqw_u256_fallback;
3064FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqd_u256, iemAImpl_vpcmpeqd_u256_fallback;
3065FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqq_u256, iemAImpl_vpcmpeqq_u256_fallback;
3066FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtb_u256, iemAImpl_vpcmpgtb_u256_fallback;
3067FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtw_u256, iemAImpl_vpcmpgtw_u256_fallback;
3068FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtd_u256, iemAImpl_vpcmpgtd_u256_fallback;
3069FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtq_u256, iemAImpl_vpcmpgtq_u256_fallback;
3070FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddb_u256, iemAImpl_vpaddb_u256_fallback;
3071FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddw_u256, iemAImpl_vpaddw_u256_fallback;
3072FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddd_u256, iemAImpl_vpaddd_u256_fallback;
3073FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddq_u256, iemAImpl_vpaddq_u256_fallback;
3074FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubb_u256, iemAImpl_vpsubb_u256_fallback;
3075FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubw_u256, iemAImpl_vpsubw_u256_fallback;
3076FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubd_u256, iemAImpl_vpsubd_u256_fallback;
3077FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubq_u256, iemAImpl_vpsubq_u256_fallback;
3078FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminub_u256, iemAImpl_vpminub_u256_fallback;
3079FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminuw_u256, iemAImpl_vpminuw_u256_fallback;
3080FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminud_u256, iemAImpl_vpminud_u256_fallback;
3081FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsb_u256, iemAImpl_vpminsb_u256_fallback;
3082FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsw_u256, iemAImpl_vpminsw_u256_fallback;
3083FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsd_u256, iemAImpl_vpminsd_u256_fallback;
3084FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxub_u256, iemAImpl_vpmaxub_u256_fallback;
3085FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxuw_u256, iemAImpl_vpmaxuw_u256_fallback;
3086FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxud_u256, iemAImpl_vpmaxud_u256_fallback;
3087FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsb_u256, iemAImpl_vpmaxsb_u256_fallback;
3088FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsw_u256, iemAImpl_vpmaxsw_u256_fallback;
3089FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsd_u256, iemAImpl_vpmaxsd_u256_fallback;
3090FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpacksswb_u256, iemAImpl_vpacksswb_u256_fallback;
3091FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackssdw_u256, iemAImpl_vpackssdw_u256_fallback;
3092FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackuswb_u256, iemAImpl_vpackuswb_u256_fallback;
3093FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackusdw_u256, iemAImpl_vpackusdw_u256_fallback;
3094FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmullw_u256, iemAImpl_vpmullw_u256_fallback;
3095FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulld_u256, iemAImpl_vpmulld_u256_fallback;
3096FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhw_u256, iemAImpl_vpmulhw_u256_fallback;
3097FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhuw_u256, iemAImpl_vpmulhuw_u256_fallback;
3098FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgb_u256, iemAImpl_vpavgb_u256_fallback;
3099FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgw_u256, iemAImpl_vpavgw_u256_fallback;
3100FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignb_u256, iemAImpl_vpsignb_u256_fallback;
3101FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignw_u256, iemAImpl_vpsignw_u256_fallback;
3102FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignd_u256, iemAImpl_vpsignd_u256_fallback;
3103FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddw_u256, iemAImpl_vphaddw_u256_fallback;
3104FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddd_u256, iemAImpl_vphaddd_u256_fallback;
3105FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubw_u256, iemAImpl_vphsubw_u256_fallback;
3106FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubd_u256, iemAImpl_vphsubd_u256_fallback;
3107FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddsw_u256, iemAImpl_vphaddsw_u256_fallback;
3108FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubsw_u256, iemAImpl_vphsubsw_u256_fallback;
3109FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddubsw_u256, iemAImpl_vpmaddubsw_u256_fallback;
3110FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhrsw_u256, iemAImpl_vpmulhrsw_u256_fallback;
3111FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsadbw_u256, iemAImpl_vpsadbw_u256_fallback;
3112FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuldq_u256, iemAImpl_vpmuldq_u256_fallback;
3113FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuludq_u256, iemAImpl_vpmuludq_u256_fallback;
3114FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsb_u256, iemAImpl_vpsubsb_u256_fallback;
3115FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsw_u256, iemAImpl_vpsubsw_u256_fallback;
3116FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusb_u256, iemAImpl_vpsubusb_u256_fallback;
3117FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusw_u256, iemAImpl_vpsubusw_u256_fallback;
3118FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusb_u256, iemAImpl_vpaddusb_u256_fallback;
3119FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusw_u256, iemAImpl_vpaddusw_u256_fallback;
3120FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsb_u256, iemAImpl_vpaddsb_u256_fallback;
3121FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsw_u256, iemAImpl_vpaddsw_u256_fallback;
3122
3123FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsb_u256, iemAImpl_vpabsb_u256_fallback;
3124FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsw_u256, iemAImpl_vpabsw_u256_fallback;
3125FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsd_u256, iemAImpl_vpabsd_u256_fallback;
3126/** @} */
3127
3128/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
3129 * @{ */
3130FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
3131FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
3132FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpcklbw_u128, iemAImpl_vpunpcklbw_u128_fallback,
3133 iemAImpl_vpunpcklwd_u128, iemAImpl_vpunpcklwd_u128_fallback,
3134 iemAImpl_vpunpckldq_u128, iemAImpl_vpunpckldq_u128_fallback,
3135 iemAImpl_vpunpcklqdq_u128, iemAImpl_vpunpcklqdq_u128_fallback,
3136 iemAImpl_vunpcklps_u128, iemAImpl_vunpcklps_u128_fallback,
3137 iemAImpl_vunpcklpd_u128, iemAImpl_vunpcklpd_u128_fallback,
3138 iemAImpl_vunpckhps_u128, iemAImpl_vunpckhps_u128_fallback,
3139 iemAImpl_vunpckhpd_u128, iemAImpl_vunpckhpd_u128_fallback;
3140
3141FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpcklbw_u256, iemAImpl_vpunpcklbw_u256_fallback,
3142 iemAImpl_vpunpcklwd_u256, iemAImpl_vpunpcklwd_u256_fallback,
3143 iemAImpl_vpunpckldq_u256, iemAImpl_vpunpckldq_u256_fallback,
3144 iemAImpl_vpunpcklqdq_u256, iemAImpl_vpunpcklqdq_u256_fallback,
3145 iemAImpl_vunpcklps_u256, iemAImpl_vunpcklps_u256_fallback,
3146 iemAImpl_vunpcklpd_u256, iemAImpl_vunpcklpd_u256_fallback,
3147 iemAImpl_vunpckhps_u256, iemAImpl_vunpckhps_u256_fallback,
3148 iemAImpl_vunpckhpd_u256, iemAImpl_vunpckhpd_u256_fallback;
3149/** @} */
3150
3151/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
3152 * @{ */
3153FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
3154FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
3155FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpckhbw_u128, iemAImpl_vpunpckhbw_u128_fallback,
3156 iemAImpl_vpunpckhwd_u128, iemAImpl_vpunpckhwd_u128_fallback,
3157 iemAImpl_vpunpckhdq_u128, iemAImpl_vpunpckhdq_u128_fallback,
3158 iemAImpl_vpunpckhqdq_u128, iemAImpl_vpunpckhqdq_u128_fallback;
3159FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpckhbw_u256, iemAImpl_vpunpckhbw_u256_fallback,
3160 iemAImpl_vpunpckhwd_u256, iemAImpl_vpunpckhwd_u256_fallback,
3161 iemAImpl_vpunpckhdq_u256, iemAImpl_vpunpckhdq_u256_fallback,
3162 iemAImpl_vpunpckhqdq_u256, iemAImpl_vpunpckhqdq_u256_fallback;
3163/** @} */
3164
3165/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
3166 * @{ */
3167typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3168typedef FNIEMAIMPLMEDIAPSHUFU128 *PFNIEMAIMPLMEDIAPSHUFU128;
3169typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
3170typedef FNIEMAIMPLMEDIAPSHUFU256 *PFNIEMAIMPLMEDIAPSHUFU256;
3171IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw_u64,(uint64_t *puDst, uint64_t const *puSrc, uint8_t bEvil));
3172FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_pshufhw_u128, iemAImpl_pshuflw_u128, iemAImpl_pshufd_u128;
3173#ifndef IEM_WITHOUT_ASSEMBLY
3174FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256, iemAImpl_vpshuflw_u256, iemAImpl_vpshufd_u256;
3175#endif
3176FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256_fallback, iemAImpl_vpshuflw_u256_fallback, iemAImpl_vpshufd_u256_fallback;
3177/** @} */
3178
3179/** @name Media (SSE/MMX/AVX) operation: Shift Immediate Stuff (evil)
3180 * @{ */
3181typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU64,(uint64_t *puDst, uint8_t bShift));
3182typedef FNIEMAIMPLMEDIAPSHIFTU64 *PFNIEMAIMPLMEDIAPSHIFTU64;
3183typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU128,(PRTUINT128U puDst, uint8_t bShift));
3184typedef FNIEMAIMPLMEDIAPSHIFTU128 *PFNIEMAIMPLMEDIAPSHIFTU128;
3185typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU256,(PRTUINT256U puDst, uint8_t bShift));
3186typedef FNIEMAIMPLMEDIAPSHIFTU256 *PFNIEMAIMPLMEDIAPSHIFTU256;
3187FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psllw_imm_u64, iemAImpl_pslld_imm_u64, iemAImpl_psllq_imm_u64;
3188FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psrlw_imm_u64, iemAImpl_psrld_imm_u64, iemAImpl_psrlq_imm_u64;
3189FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psraw_imm_u64, iemAImpl_psrad_imm_u64;
3190FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psllw_imm_u128, iemAImpl_pslld_imm_u128, iemAImpl_psllq_imm_u128;
3191FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psrlw_imm_u128, iemAImpl_psrld_imm_u128, iemAImpl_psrlq_imm_u128;
3192FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psraw_imm_u128, iemAImpl_psrad_imm_u128;
3193FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_pslldq_imm_u128, iemAImpl_psrldq_imm_u128;
3194/** @} */
3195
3196/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
3197 * @{ */
3198IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(uint64_t *pu64Dst, uint64_t const *puSrc));
3199IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(uint64_t *pu64Dst, PCRTUINT128U puSrc));
3200#ifndef IEM_WITHOUT_ASSEMBLY
3201IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
3202#endif
3203IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256_fallback,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
3204/** @} */
3205
3206/** @name Media (SSE/MMX/AVX) operations: Variable Blend Packed Bytes/R32/R64.
3207 * @{ */
3208typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puMask));
3209typedef FNIEMAIMPLBLENDU128 *PFNIEMAIMPLBLENDU128;
3210typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, PCRTUINT128U puMask));
3211typedef FNIEMAIMPLAVXBLENDU128 *PFNIEMAIMPLAVXBLENDU128;
3212typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, PCRTUINT256U puMask));
3213typedef FNIEMAIMPLAVXBLENDU256 *PFNIEMAIMPLAVXBLENDU256;
3214
3215FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128;
3216FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128_fallback;
3217FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128;
3218FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128_fallback;
3219FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256;
3220FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256_fallback;
3221
3222FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128;
3223FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128_fallback;
3224FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128;
3225FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128_fallback;
3226FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256;
3227FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256_fallback;
3228
3229FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128;
3230FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128_fallback;
3231FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128;
3232FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128_fallback;
3233FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256;
3234FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256_fallback;
3235/** @} */
3236
3237
3238/** @name Media (SSE/MMX/AVX) operation: Sort this later
3239 * @{ */
3240IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
3241IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
3242IEM_DECL_IMPL_DEF(void, iemAImpl_vmovshdup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
3243IEM_DECL_IMPL_DEF(void, iemAImpl_vmovshdup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
3244IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
3245IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
3246
3247IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3248IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3249IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3250IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3251IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3252
3253IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3254IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3255IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3256IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3257IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3258
3259IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3260IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3261IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
3262IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3263IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3264
3265IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3266IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3267IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3268IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3269IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3270
3271IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3272IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3273IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3274IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3275IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3276
3277IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3278IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3279IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3280IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3281IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3282
3283IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3284IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3285IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3286IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3287IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3288
3289IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3290IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3291IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3292IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3293IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3294
3295IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3296IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3297IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
3298IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3299IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3300
3301IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3302IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3303IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3304IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3305IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3306
3307IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3308IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3309IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3310IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3311IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3312
3313IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3314IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3315IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3316IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3317IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3318
3319IEM_DECL_IMPL_DEF(void, iemAImpl_shufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3320IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3321IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3322IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3323IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3324
3325IEM_DECL_IMPL_DEF(void, iemAImpl_shufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3326IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3327IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3328IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3329IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3330
3331IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
3332IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64_fallback,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
3333
3334IEM_DECL_IMPL_DEF(void, iemAImpl_pinsrw_u64,(uint64_t *pu64Dst, uint16_t u16Src, uint8_t bEvil));
3335IEM_DECL_IMPL_DEF(void, iemAImpl_pinsrw_u128,(PRTUINT128U puDst, uint16_t u16Src, uint8_t bEvil));
3336IEM_DECL_IMPL_DEF(void, iemAImpl_vpinsrw_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint16_t u16Src, uint8_t bEvil));
3337IEM_DECL_IMPL_DEF(void, iemAImpl_vpinsrw_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint16_t u16Src, uint8_t bEvil));
3338
3339IEM_DECL_IMPL_DEF(void, iemAImpl_pextrw_u64,(uint16_t *pu16Dst, uint64_t u64Src, uint8_t bEvil));
3340IEM_DECL_IMPL_DEF(void, iemAImpl_pextrw_u128,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
3341IEM_DECL_IMPL_DEF(void, iemAImpl_vpextrw_u128,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
3342IEM_DECL_IMPL_DEF(void, iemAImpl_vpextrw_u128_fallback,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
3343
3344IEM_DECL_IMPL_DEF(void, iemAImpl_movmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3345IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3346IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3347IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3348IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3349
3350IEM_DECL_IMPL_DEF(void, iemAImpl_movmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3351IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3352IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3353IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3354IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3355
3356
3357typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3358typedef FNIEMAIMPLMEDIAOPTF2U128IMM8 *PFNIEMAIMPLMEDIAOPTF2U128IMM8;
3359typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3360typedef FNIEMAIMPLMEDIAOPTF3U128IMM8 *PFNIEMAIMPLMEDIAOPTF3U128IMM8;
3361typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3362typedef FNIEMAIMPLMEDIAOPTF3U256IMM8 *PFNIEMAIMPLMEDIAOPTF3U256IMM8;
3363
3364FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_palignr_u128, iemAImpl_palignr_u128_fallback;
3365FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pblendw_u128, iemAImpl_pblendw_u128_fallback;
3366FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendps_u128, iemAImpl_blendps_u128_fallback;
3367FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendpd_u128, iemAImpl_blendpd_u128_fallback;
3368
3369FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpalignr_u128, iemAImpl_vpalignr_u128_fallback;
3370FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendw_u128, iemAImpl_vpblendw_u128_fallback;
3371FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendps_u128, iemAImpl_vblendps_u128_fallback;
3372FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendpd_u128, iemAImpl_vblendpd_u128_fallback;
3373
3374FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpalignr_u256, iemAImpl_vpalignr_u256_fallback;
3375FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendw_u256, iemAImpl_vpblendw_u256_fallback;
3376FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendps_u256, iemAImpl_vblendps_u256_fallback;
3377FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendpd_u256, iemAImpl_vblendpd_u256_fallback;
3378FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2i128_u256, iemAImpl_vperm2i128_u256_fallback;
3379FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2f128_u256, iemAImpl_vperm2f128_u256_fallback;
3380
3381FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesimc_u128, iemAImpl_aesimc_u128_fallback;
3382FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenc_u128, iemAImpl_aesenc_u128_fallback;
3383FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenclast_u128, iemAImpl_aesenclast_u128_fallback;
3384FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdec_u128, iemAImpl_aesdec_u128_fallback;
3385FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdeclast_u128, iemAImpl_aesdeclast_u128_fallback;
3386
3387FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesimc_u128, iemAImpl_vaesimc_u128_fallback;
3388FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenc_u128, iemAImpl_vaesenc_u128_fallback;
3389FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenclast_u128, iemAImpl_vaesenclast_u128_fallback;
3390FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdec_u128, iemAImpl_vaesdec_u128_fallback;
3391FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdeclast_u128, iemAImpl_vaesdeclast_u128_fallback;
3392
3393FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_aeskeygenassist_u128, iemAImpl_aeskeygenassist_u128_fallback;
3394
3395FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vaeskeygenassist_u128, iemAImpl_vaeskeygenassist_u128_fallback;
3396
3397FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1nexte_u128, iemAImpl_sha1nexte_u128_fallback;
3398FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg1_u128, iemAImpl_sha1msg1_u128_fallback;
3399FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg2_u128, iemAImpl_sha1msg2_u128_fallback;
3400FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg1_u128, iemAImpl_sha256msg1_u128_fallback;
3401FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg2_u128, iemAImpl_sha256msg2_u128_fallback;
3402FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_sha1rnds4_u128, iemAImpl_sha1rnds4_u128_fallback;
3403IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
3404IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
3405
3406typedef struct IEMPCMPISTRXSRC
3407{
3408 RTUINT128U uSrc1;
3409 RTUINT128U uSrc2;
3410} IEMPCMPISTRXSRC;
3411typedef IEMPCMPISTRXSRC *PIEMPCMPISTRXSRC;
3412typedef const IEMPCMPISTRXSRC *PCIEMPCMPISTRXSRC;
3413
3414typedef struct IEMPCMPESTRXSRC
3415{
3416 RTUINT128U uSrc1;
3417 RTUINT128U uSrc2;
3418 uint64_t u64Rax;
3419 uint64_t u64Rdx;
3420} IEMPCMPESTRXSRC;
3421typedef IEMPCMPESTRXSRC *PIEMPCMPESTRXSRC;
3422typedef const IEMPCMPESTRXSRC *PCIEMPCMPESTRXSRC;
3423
3424typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPISTRIU128IMM8,(uint32_t *pu32Ecx, uint32_t *pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
3425typedef FNIEMAIMPLPCMPISTRIU128IMM8 *PFNIEMAIMPLPCMPISTRIU128IMM8;
3426typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRIU128IMM8,(uint32_t *pu32Ecx, uint32_t *pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
3427typedef FNIEMAIMPLPCMPESTRIU128IMM8 *PFNIEMAIMPLPCMPESTRIU128IMM8;
3428
3429typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPISTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
3430typedef FNIEMAIMPLPCMPISTRMU128IMM8 *PFNIEMAIMPLPCMPISTRMU128IMM8;
3431typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
3432typedef FNIEMAIMPLPCMPESTRMU128IMM8 *PFNIEMAIMPLPCMPESTRMU128IMM8;
3433
3434FNIEMAIMPLPCMPISTRIU128IMM8 iemAImpl_pcmpistri_u128, iemAImpl_pcmpistri_u128_fallback;
3435FNIEMAIMPLPCMPESTRIU128IMM8 iemAImpl_pcmpestri_u128, iemAImpl_pcmpestri_u128_fallback;
3436FNIEMAIMPLPCMPISTRMU128IMM8 iemAImpl_pcmpistrm_u128, iemAImpl_pcmpistrm_u128_fallback;
3437FNIEMAIMPLPCMPESTRMU128IMM8 iemAImpl_pcmpestrm_u128, iemAImpl_pcmpestrm_u128_fallback;
3438
3439FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pclmulqdq_u128, iemAImpl_pclmulqdq_u128_fallback;
3440FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpclmulqdq_u128, iemAImpl_vpclmulqdq_u128_fallback;
3441
3442FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_mpsadbw_u128, iemAImpl_mpsadbw_u128_fallback;
3443FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vmpsadbw_u128, iemAImpl_vmpsadbw_u128_fallback;
3444FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vmpsadbw_u256, iemAImpl_vmpsadbw_u256_fallback;
3445/** @} */
3446
3447/** @name Media Odds and Ends
3448 * @{ */
3449typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U8,(uint32_t *puDst, uint8_t uSrc));
3450typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U16,(uint32_t *puDst, uint16_t uSrc));
3451typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U32,(uint32_t *puDst, uint32_t uSrc));
3452typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U64,(uint32_t *puDst, uint64_t uSrc));
3453FNIEMAIMPLCR32U8 iemAImpl_crc32_u8, iemAImpl_crc32_u8_fallback;
3454FNIEMAIMPLCR32U16 iemAImpl_crc32_u16, iemAImpl_crc32_u16_fallback;
3455FNIEMAIMPLCR32U32 iemAImpl_crc32_u32, iemAImpl_crc32_u32_fallback;
3456FNIEMAIMPLCR32U64 iemAImpl_crc32_u64, iemAImpl_crc32_u64_fallback;
3457
3458typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL128,(PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint32_t *pEFlags));
3459typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL256,(PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint32_t *pEFlags));
3460FNIEMAIMPLF2EFL128 iemAImpl_ptest_u128;
3461FNIEMAIMPLF2EFL256 iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback;
3462
3463typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I32U64,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, int32_t *pi32Dst, const uint64_t *pu64Src)); /* pu64Src is a double precision floating point. */
3464typedef FNIEMAIMPLSSEF2I32U64 *PFNIEMAIMPLSSEF2I32U64;
3465typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I64U64,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, int64_t *pi64Dst, const uint64_t *pu64Src)); /* pu64Src is a double precision floating point. */
3466typedef FNIEMAIMPLSSEF2I64U64 *PFNIEMAIMPLSSEF2I64U64;
3467typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I32U32,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, int32_t *pi32Dst, const uint32_t *pu32Src)); /* pu32Src is a single precision floating point. */
3468typedef FNIEMAIMPLSSEF2I32U32 *PFNIEMAIMPLSSEF2I32U32;
3469typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I64U32,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, int64_t *pi64Dst, const uint32_t *pu32Src)); /* pu32Src is a single precision floating point. */
3470typedef FNIEMAIMPLSSEF2I64U32 *PFNIEMAIMPLSSEF2I64U32;
3471
3472FNIEMAIMPLSSEF2I32U64 iemAImpl_cvttsd2si_i32_r64;
3473FNIEMAIMPLSSEF2I32U64 iemAImpl_cvtsd2si_i32_r64;
3474
3475FNIEMAIMPLSSEF2I64U64 iemAImpl_cvttsd2si_i64_r64;
3476FNIEMAIMPLSSEF2I64U64 iemAImpl_cvtsd2si_i64_r64;
3477
3478FNIEMAIMPLSSEF2I32U32 iemAImpl_cvttss2si_i32_r32;
3479FNIEMAIMPLSSEF2I32U32 iemAImpl_cvtss2si_i32_r32;
3480
3481FNIEMAIMPLSSEF2I64U32 iemAImpl_cvttss2si_i64_r32;
3482FNIEMAIMPLSSEF2I64U32 iemAImpl_cvtss2si_i64_r32;
3483
3484typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R32I32,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, PRTFLOAT32U pr32Dst, const int32_t *pi32Src));
3485typedef FNIEMAIMPLSSEF2R32I32 *PFNIEMAIMPLSSEF2R32I32;
3486typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R32I64,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, PRTFLOAT32U pr32Dst, const int64_t *pi64Src));
3487typedef FNIEMAIMPLSSEF2R32I64 *PFNIEMAIMPLSSEF2R32I64;
3488
3489FNIEMAIMPLSSEF2R32I32 iemAImpl_cvtsi2ss_r32_i32;
3490FNIEMAIMPLSSEF2R32I64 iemAImpl_cvtsi2ss_r32_i64;
3491
3492typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R64I32,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, PRTFLOAT64U pr64Dst, const int32_t *pi32Src));
3493typedef FNIEMAIMPLSSEF2R64I32 *PFNIEMAIMPLSSEF2R64I32;
3494typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R64I64,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, PRTFLOAT64U pr64Dst, const int64_t *pi64Src));
3495typedef FNIEMAIMPLSSEF2R64I64 *PFNIEMAIMPLSSEF2R64I64;
3496
3497FNIEMAIMPLSSEF2R64I32 iemAImpl_cvtsi2sd_r64_i32;
3498FNIEMAIMPLSSEF2R64I64 iemAImpl_cvtsi2sd_r64_i64;
3499
3500
3501typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFLMXCSR128,(uint32_t *pfMxcsr, uint32_t *pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
3502typedef FNIEMAIMPLF2EFLMXCSR128 *PFNIEMAIMPLF2EFLMXCSR128;
3503
3504FNIEMAIMPLF2EFLMXCSR128 iemAImpl_ucomiss_u128;
3505FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback;
3506
3507FNIEMAIMPLF2EFLMXCSR128 iemAImpl_ucomisd_u128;
3508FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback;
3509
3510FNIEMAIMPLF2EFLMXCSR128 iemAImpl_comiss_u128;
3511FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback;
3512
3513FNIEMAIMPLF2EFLMXCSR128 iemAImpl_comisd_u128;
3514FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback;
3515
3516
3517typedef struct IEMMEDIAF2XMMSRC
3518{
3519 X86XMMREG uSrc1;
3520 X86XMMREG uSrc2;
3521} IEMMEDIAF2XMMSRC;
3522typedef IEMMEDIAF2XMMSRC *PIEMMEDIAF2XMMSRC;
3523typedef const IEMMEDIAF2XMMSRC *PCIEMMEDIAF2XMMSRC;
3524
3525typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRF2XMMIMM8,(uint32_t *pfMxcsr, PX86XMMREG puDst, PCIEMMEDIAF2XMMSRC puSrc, uint8_t bEvil));
3526typedef FNIEMAIMPLMXCSRF2XMMIMM8 *PFNIEMAIMPLMXCSRF2XMMIMM8;
3527
3528FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpps_u128;
3529FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmppd_u128;
3530FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpss_u128;
3531FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpsd_u128;
3532FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundss_u128;
3533FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundsd_u128;
3534
3535FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundps_u128, iemAImpl_roundps_u128_fallback;
3536FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundpd_u128, iemAImpl_roundpd_u128_fallback;
3537
3538FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_dpps_u128, iemAImpl_dpps_u128_fallback;
3539FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_dppd_u128, iemAImpl_dppd_u128_fallback;
3540
3541typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU64U128,(uint32_t *pfMxcsr, uint64_t *pu64Dst, PCX86XMMREG pSrc));
3542typedef FNIEMAIMPLMXCSRU64U128 *PFNIEMAIMPLMXCSRU64U128;
3543
3544FNIEMAIMPLMXCSRU64U128 iemAImpl_cvtpd2pi_u128;
3545FNIEMAIMPLMXCSRU64U128 iemAImpl_cvttpd2pi_u128;
3546
3547typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU128U64,(uint32_t *pfMxcsr, PX86XMMREG pDst, uint64_t u64Src));
3548typedef FNIEMAIMPLMXCSRU128U64 *PFNIEMAIMPLMXCSRU128U64;
3549
3550FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2ps_u128;
3551FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2pd_u128;
3552
3553typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU64U64,(uint32_t *pfMxcsr, uint64_t *pu64Dst, uint64_t u64Src));
3554typedef FNIEMAIMPLMXCSRU64U64 *PFNIEMAIMPLMXCSRU64U64;
3555
3556FNIEMAIMPLMXCSRU64U64 iemAImpl_cvtps2pi_u128;
3557FNIEMAIMPLMXCSRU64U64 iemAImpl_cvttps2pi_u128;
3558
3559/** @} */
3560
3561
3562/** @name Function tables.
3563 * @{
3564 */
3565
3566/**
3567 * Function table for a binary operator providing implementation based on
3568 * operand size.
3569 */
3570typedef struct IEMOPBINSIZES
3571{
3572 PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
3573 PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
3574 PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
3575 PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
3576} IEMOPBINSIZES;
3577/** Pointer to a binary operator function table. */
3578typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
3579
3580
3581/**
3582 * Function table for a unary operator providing implementation based on
3583 * operand size.
3584 */
3585typedef struct IEMOPUNARYSIZES
3586{
3587 PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
3588 PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
3589 PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
3590 PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
3591} IEMOPUNARYSIZES;
3592/** Pointer to a unary operator function table. */
3593typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
3594
3595
3596/**
3597 * Function table for a shift operator providing implementation based on
3598 * operand size.
3599 */
3600typedef struct IEMOPSHIFTSIZES
3601{
3602 PFNIEMAIMPLSHIFTU8 pfnNormalU8;
3603 PFNIEMAIMPLSHIFTU16 pfnNormalU16;
3604 PFNIEMAIMPLSHIFTU32 pfnNormalU32;
3605 PFNIEMAIMPLSHIFTU64 pfnNormalU64;
3606} IEMOPSHIFTSIZES;
3607/** Pointer to a shift operator function table. */
3608typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
3609
3610
3611/**
3612 * Function table for a multiplication or division operation.
3613 */
3614typedef struct IEMOPMULDIVSIZES
3615{
3616 PFNIEMAIMPLMULDIVU8 pfnU8;
3617 PFNIEMAIMPLMULDIVU16 pfnU16;
3618 PFNIEMAIMPLMULDIVU32 pfnU32;
3619 PFNIEMAIMPLMULDIVU64 pfnU64;
3620} IEMOPMULDIVSIZES;
3621/** Pointer to a multiplication or division operation function table. */
3622typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
3623
3624
3625/**
3626 * Function table for a double precision shift operator providing implementation
3627 * based on operand size.
3628 */
3629typedef struct IEMOPSHIFTDBLSIZES
3630{
3631 PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
3632 PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
3633 PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
3634} IEMOPSHIFTDBLSIZES;
3635/** Pointer to a double precision shift function table. */
3636typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
3637
3638
3639/**
3640 * Function table for media instruction taking two full sized media source
3641 * registers and one full sized destination register (AVX).
3642 */
3643typedef struct IEMOPMEDIAF3
3644{
3645 PFNIEMAIMPLMEDIAF3U128 pfnU128;
3646 PFNIEMAIMPLMEDIAF3U256 pfnU256;
3647} IEMOPMEDIAF3;
3648/** Pointer to a media operation function table for 3 full sized ops (AVX). */
3649typedef IEMOPMEDIAF3 const *PCIEMOPMEDIAF3;
3650
3651/** @def IEMOPMEDIAF3_INIT_VARS_EX
3652 * Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3653 * given functions as initializers. For use in AVX functions where a pair of
3654 * functions are only used once and the function table need not be public. */
3655#ifndef TST_IEM_CHECK_MC
3656# if (defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3657# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3658 static IEMOPMEDIAF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3659 static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3660# else
3661# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3662 static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3663# endif
3664#else
3665# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3666#endif
3667/** @def IEMOPMEDIAF3_INIT_VARS
3668 * Generate AVX function tables for the @a a_InstrNm instruction.
3669 * @sa IEMOPMEDIAF3_INIT_VARS_EX */
3670#define IEMOPMEDIAF3_INIT_VARS(a_InstrNm) \
3671 IEMOPMEDIAF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3672 RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3673
3674/**
3675 * Function table for media instruction taking two full sized media source
3676 * registers and one full sized destination register, but no additional state
3677 * (AVX).
3678 */
3679typedef struct IEMOPMEDIAOPTF3
3680{
3681 PFNIEMAIMPLMEDIAOPTF3U128 pfnU128;
3682 PFNIEMAIMPLMEDIAOPTF3U256 pfnU256;
3683} IEMOPMEDIAOPTF3;
3684/** Pointer to a media operation function table for 3 full sized ops (AVX). */
3685typedef IEMOPMEDIAOPTF3 const *PCIEMOPMEDIAOPTF3;
3686
3687/** @def IEMOPMEDIAOPTF3_INIT_VARS_EX
3688 * Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3689 * given functions as initializers. For use in AVX functions where a pair of
3690 * functions are only used once and the function table need not be public. */
3691#ifndef TST_IEM_CHECK_MC
3692# if (defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3693# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3694 static IEMOPMEDIAOPTF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3695 static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3696# else
3697# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3698 static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3699# endif
3700#else
3701# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3702#endif
3703/** @def IEMOPMEDIAOPTF3_INIT_VARS
3704 * Generate AVX function tables for the @a a_InstrNm instruction.
3705 * @sa IEMOPMEDIAOPTF3_INIT_VARS_EX */
3706#define IEMOPMEDIAOPTF3_INIT_VARS(a_InstrNm) \
3707 IEMOPMEDIAOPTF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3708 RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3709
3710/**
3711 * Function table for media instruction taking one full sized media source
3712 * registers and one full sized destination register, but no additional state
3713 * (AVX).
3714 */
3715typedef struct IEMOPMEDIAOPTF2
3716{
3717 PFNIEMAIMPLMEDIAOPTF2U128 pfnU128;
3718 PFNIEMAIMPLMEDIAOPTF2U256 pfnU256;
3719} IEMOPMEDIAOPTF2;
3720/** Pointer to a media operation function table for 2 full sized ops (AVX). */
3721typedef IEMOPMEDIAOPTF2 const *PCIEMOPMEDIAOPTF2;
3722
3723/** @def IEMOPMEDIAOPTF2_INIT_VARS_EX
3724 * Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3725 * given functions as initializers. For use in AVX functions where a pair of
3726 * functions are only used once and the function table need not be public. */
3727#ifndef TST_IEM_CHECK_MC
3728# if (defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3729# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3730 static IEMOPMEDIAOPTF2 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3731 static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3732# else
3733# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3734 static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3735# endif
3736#else
3737# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3738#endif
3739/** @def IEMOPMEDIAOPTF2_INIT_VARS
3740 * Generate AVX function tables for the @a a_InstrNm instruction.
3741 * @sa IEMOPMEDIAOPTF2_INIT_VARS_EX */
3742#define IEMOPMEDIAOPTF2_INIT_VARS(a_InstrNm) \
3743 IEMOPMEDIAOPTF2_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3744 RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3745
3746/**
3747 * Function table for media instruction taking two full sized media source
3748 * registers and one full sized destination register and an 8-bit immediate, but no additional state
3749 * (AVX).
3750 */
3751typedef struct IEMOPMEDIAOPTF3IMM8
3752{
3753 PFNIEMAIMPLMEDIAOPTF3U128IMM8 pfnU128;
3754 PFNIEMAIMPLMEDIAOPTF3U256IMM8 pfnU256;
3755} IEMOPMEDIAOPTF3IMM8;
3756/** Pointer to a media operation function table for 3 full sized ops (AVX). */
3757typedef IEMOPMEDIAOPTF3IMM8 const *PCIEMOPMEDIAOPTF3IMM8;
3758
3759/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX
3760 * Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3761 * given functions as initializers. For use in AVX functions where a pair of
3762 * functions are only used once and the function table need not be public. */
3763#ifndef TST_IEM_CHECK_MC
3764# if (defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3765# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3766 static IEMOPMEDIAOPTF3IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3767 static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3768# else
3769# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3770 static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3771# endif
3772#else
3773# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3774#endif
3775/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS
3776 * Generate AVX function tables for the @a a_InstrNm instruction.
3777 * @sa IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX */
3778#define IEMOPMEDIAOPTF3IMM8_INIT_VARS(a_InstrNm) \
3779 IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3780 RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3781/** @} */
3782
3783
3784/**
3785 * Function table for blend type instruction taking three full sized media source
3786 * registers and one full sized destination register, but no additional state
3787 * (AVX).
3788 */
3789typedef struct IEMOPBLENDOP
3790{
3791 PFNIEMAIMPLAVXBLENDU128 pfnU128;
3792 PFNIEMAIMPLAVXBLENDU256 pfnU256;
3793} IEMOPBLENDOP;
3794/** Pointer to a media operation function table for 4 full sized ops (AVX). */
3795typedef IEMOPBLENDOP const *PCIEMOPBLENDOP;
3796
3797/** @def IEMOPBLENDOP_INIT_VARS_EX
3798 * Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3799 * given functions as initializers. For use in AVX functions where a pair of
3800 * functions are only used once and the function table need not be public. */
3801#ifndef TST_IEM_CHECK_MC
3802# if (defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3803# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3804 static IEMOPBLENDOP const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3805 static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3806# else
3807# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3808 static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3809# endif
3810#else
3811# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3812#endif
3813/** @def IEMOPBLENDOP_INIT_VARS
3814 * Generate AVX function tables for the @a a_InstrNm instruction.
3815 * @sa IEMOPBLENDOP_INIT_VARS_EX */
3816#define IEMOPBLENDOP_INIT_VARS(a_InstrNm) \
3817 IEMOPBLENDOP_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3818 RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3819
3820
3821/** @name SSE/AVX single/double precision floating point operations.
3822 * @{ */
3823/**
3824 * A SSE result.
3825 */
3826typedef struct IEMSSERESULT
3827{
3828 /** The output value. */
3829 X86XMMREG uResult;
3830 /** The output status. */
3831 uint32_t MXCSR;
3832} IEMSSERESULT;
3833AssertCompileMemberOffset(IEMSSERESULT, MXCSR, 128 / 8);
3834/** Pointer to a SSE result. */
3835typedef IEMSSERESULT *PIEMSSERESULT;
3836/** Pointer to a const SSE result. */
3837typedef IEMSSERESULT const *PCIEMSSERESULT;
3838
3839
3840/**
3841 * A AVX128 result.
3842 */
3843typedef struct IEMAVX128RESULT
3844{
3845 /** The output value. */
3846 X86XMMREG uResult;
3847 /** The output status. */
3848 uint32_t MXCSR;
3849} IEMAVX128RESULT;
3850AssertCompileMemberOffset(IEMAVX128RESULT, MXCSR, 128 / 8);
3851/** Pointer to a AVX128 result. */
3852typedef IEMAVX128RESULT *PIEMAVX128RESULT;
3853/** Pointer to a const AVX128 result. */
3854typedef IEMAVX128RESULT const *PCIEMAVX128RESULT;
3855
3856
3857/**
3858 * A AVX256 result.
3859 */
3860typedef struct IEMAVX256RESULT
3861{
3862 /** The output value. */
3863 X86YMMREG uResult;
3864 /** The output status. */
3865 uint32_t MXCSR;
3866} IEMAVX256RESULT;
3867AssertCompileMemberOffset(IEMAVX256RESULT, MXCSR, 256 / 8);
3868/** Pointer to a AVX256 result. */
3869typedef IEMAVX256RESULT *PIEMAVX256RESULT;
3870/** Pointer to a const AVX256 result. */
3871typedef IEMAVX256RESULT const *PCIEMAVX256RESULT;
3872
3873
3874typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
3875typedef FNIEMAIMPLFPSSEF2U128 *PFNIEMAIMPLFPSSEF2U128;
3876typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128R32,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
3877typedef FNIEMAIMPLFPSSEF2U128R32 *PFNIEMAIMPLFPSSEF2U128R32;
3878typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128R64,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
3879typedef FNIEMAIMPLFPSSEF2U128R64 *PFNIEMAIMPLFPSSEF2U128R64;
3880
3881typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
3882typedef FNIEMAIMPLFPAVXF3U128 *PFNIEMAIMPLFPAVXF3U128;
3883typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128R32,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
3884typedef FNIEMAIMPLFPAVXF3U128R32 *PFNIEMAIMPLFPAVXF3U128R32;
3885typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128R64,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
3886typedef FNIEMAIMPLFPAVXF3U128R64 *PFNIEMAIMPLFPAVXF3U128R64;
3887
3888typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U256,(PX86XSAVEAREA pExtState, PIEMAVX256RESULT pResult, PCX86YMMREG puSrc1, PCX86YMMREG puSrc2));
3889typedef FNIEMAIMPLFPAVXF3U256 *PFNIEMAIMPLFPAVXF3U256;
3890
3891FNIEMAIMPLFPSSEF2U128 iemAImpl_addps_u128;
3892FNIEMAIMPLFPSSEF2U128 iemAImpl_addpd_u128;
3893FNIEMAIMPLFPSSEF2U128 iemAImpl_mulps_u128;
3894FNIEMAIMPLFPSSEF2U128 iemAImpl_mulpd_u128;
3895FNIEMAIMPLFPSSEF2U128 iemAImpl_subps_u128;
3896FNIEMAIMPLFPSSEF2U128 iemAImpl_subpd_u128;
3897FNIEMAIMPLFPSSEF2U128 iemAImpl_minps_u128;
3898FNIEMAIMPLFPSSEF2U128 iemAImpl_minpd_u128;
3899FNIEMAIMPLFPSSEF2U128 iemAImpl_divps_u128;
3900FNIEMAIMPLFPSSEF2U128 iemAImpl_divpd_u128;
3901FNIEMAIMPLFPSSEF2U128 iemAImpl_maxps_u128;
3902FNIEMAIMPLFPSSEF2U128 iemAImpl_maxpd_u128;
3903FNIEMAIMPLFPSSEF2U128 iemAImpl_haddps_u128;
3904FNIEMAIMPLFPSSEF2U128 iemAImpl_haddpd_u128;
3905FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubps_u128;
3906FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubpd_u128;
3907FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtps_u128;
3908FNIEMAIMPLFPSSEF2U128 iemAImpl_rsqrtps_u128;
3909FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtpd_u128;
3910FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubps_u128;
3911FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubpd_u128;
3912FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2ps_u128;
3913FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2pd_u128;
3914
3915FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2ps_u128;
3916FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2dq_u128;
3917FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttps2dq_u128;
3918FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttpd2dq_u128;
3919FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2pd_u128;
3920FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2dq_u128;
3921
3922FNIEMAIMPLFPSSEF2U128R32 iemAImpl_addss_u128_r32;
3923FNIEMAIMPLFPSSEF2U128R64 iemAImpl_addsd_u128_r64;
3924FNIEMAIMPLFPSSEF2U128R32 iemAImpl_mulss_u128_r32;
3925FNIEMAIMPLFPSSEF2U128R64 iemAImpl_mulsd_u128_r64;
3926FNIEMAIMPLFPSSEF2U128R32 iemAImpl_subss_u128_r32;
3927FNIEMAIMPLFPSSEF2U128R64 iemAImpl_subsd_u128_r64;
3928FNIEMAIMPLFPSSEF2U128R32 iemAImpl_minss_u128_r32;
3929FNIEMAIMPLFPSSEF2U128R64 iemAImpl_minsd_u128_r64;
3930FNIEMAIMPLFPSSEF2U128R32 iemAImpl_divss_u128_r32;
3931FNIEMAIMPLFPSSEF2U128R64 iemAImpl_divsd_u128_r64;
3932FNIEMAIMPLFPSSEF2U128R32 iemAImpl_maxss_u128_r32;
3933FNIEMAIMPLFPSSEF2U128R64 iemAImpl_maxsd_u128_r64;
3934FNIEMAIMPLFPSSEF2U128R32 iemAImpl_cvtss2sd_u128_r32;
3935FNIEMAIMPLFPSSEF2U128R64 iemAImpl_cvtsd2ss_u128_r64;
3936FNIEMAIMPLFPSSEF2U128R32 iemAImpl_sqrtss_u128_r32;
3937FNIEMAIMPLFPSSEF2U128R64 iemAImpl_sqrtsd_u128_r64;
3938FNIEMAIMPLFPSSEF2U128R32 iemAImpl_rsqrtss_u128_r32;
3939
3940FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddps_u128, iemAImpl_vaddps_u128_fallback;
3941FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddpd_u128, iemAImpl_vaddpd_u128_fallback;
3942FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulps_u128, iemAImpl_vmulps_u128_fallback;
3943FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulpd_u128, iemAImpl_vmulpd_u128_fallback;
3944FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubps_u128, iemAImpl_vsubps_u128_fallback;
3945FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubpd_u128, iemAImpl_vsubpd_u128_fallback;
3946FNIEMAIMPLFPAVXF3U128 iemAImpl_vminps_u128, iemAImpl_vminps_u128_fallback;
3947FNIEMAIMPLFPAVXF3U128 iemAImpl_vminpd_u128, iemAImpl_vminpd_u128_fallback;
3948FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivps_u128, iemAImpl_vdivps_u128_fallback;
3949FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivpd_u128, iemAImpl_vdivpd_u128_fallback;
3950FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxps_u128, iemAImpl_vmaxps_u128_fallback;
3951FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxpd_u128, iemAImpl_vmaxpd_u128_fallback;
3952FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddps_u128, iemAImpl_vhaddps_u128_fallback;
3953FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddpd_u128, iemAImpl_vhaddpd_u128_fallback;
3954FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubps_u128, iemAImpl_vhsubps_u128_fallback;
3955FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubpd_u128, iemAImpl_vhsubpd_u128_fallback;
3956FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtps_u128, iemAImpl_vsqrtps_u128_fallback;
3957FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtpd_u128, iemAImpl_vsqrtpd_u128_fallback;
3958FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubps_u128, iemAImpl_vaddsubps_u128_fallback;
3959FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubpd_u128, iemAImpl_vaddsubpd_u128_fallback;
3960FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtpd2ps_u128, iemAImpl_vcvtpd2ps_u128_fallback;
3961FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtps2pd_u128, iemAImpl_vcvtps2pd_u128_fallback;
3962
3963FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vaddss_u128_r32, iemAImpl_vaddss_u128_r32_fallback;
3964FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vaddsd_u128_r64, iemAImpl_vaddsd_u128_r64_fallback;
3965FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmulss_u128_r32, iemAImpl_vmulss_u128_r32_fallback;
3966FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmulsd_u128_r64, iemAImpl_vmulsd_u128_r64_fallback;
3967FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsubss_u128_r32, iemAImpl_vsubss_u128_r32_fallback;
3968FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsubsd_u128_r64, iemAImpl_vsubsd_u128_r64_fallback;
3969FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vminss_u128_r32, iemAImpl_vminss_u128_r32_fallback;
3970FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vminsd_u128_r64, iemAImpl_vminsd_u128_r64_fallback;
3971FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vdivss_u128_r32, iemAImpl_vdivss_u128_r32_fallback;
3972FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vdivsd_u128_r64, iemAImpl_vdivsd_u128_r64_fallback;
3973FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmaxss_u128_r32, iemAImpl_vmaxss_u128_r32_fallback;
3974FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmaxsd_u128_r64, iemAImpl_vmaxsd_u128_r64_fallback;
3975FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsqrtss_u128_r32, iemAImpl_vsqrtss_u128_r32_fallback;
3976FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsqrtsd_u128_r64, iemAImpl_vsqrtsd_u128_r64_fallback;
3977
3978FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddps_u256, iemAImpl_vaddps_u256_fallback;
3979FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddpd_u256, iemAImpl_vaddpd_u256_fallback;
3980FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulps_u256, iemAImpl_vmulps_u256_fallback;
3981FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulpd_u256, iemAImpl_vmulpd_u256_fallback;
3982FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubps_u256, iemAImpl_vsubps_u256_fallback;
3983FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubpd_u256, iemAImpl_vsubpd_u256_fallback;
3984FNIEMAIMPLFPAVXF3U256 iemAImpl_vminps_u256, iemAImpl_vminps_u256_fallback;
3985FNIEMAIMPLFPAVXF3U256 iemAImpl_vminpd_u256, iemAImpl_vminpd_u256_fallback;
3986FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivps_u256, iemAImpl_vdivps_u256_fallback;
3987FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivpd_u256, iemAImpl_vdivpd_u256_fallback;
3988FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxps_u256, iemAImpl_vmaxps_u256_fallback;
3989FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxpd_u256, iemAImpl_vmaxpd_u256_fallback;
3990FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddps_u256, iemAImpl_vhaddps_u256_fallback;
3991FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddpd_u256, iemAImpl_vhaddpd_u256_fallback;
3992FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubps_u256, iemAImpl_vhsubps_u256_fallback;
3993FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubpd_u256, iemAImpl_vhsubpd_u256_fallback;
3994FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubps_u256, iemAImpl_vhaddsubps_u256_fallback;
3995FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubpd_u256, iemAImpl_vhaddsubpd_u256_fallback;
3996FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtpd2ps_u256, iemAImpl_vcvtpd2ps_u256_fallback;
3997FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtps2pd_u256, iemAImpl_vcvtps2pd_u256_fallback;
3998/** @} */
3999
4000/** @name C instruction implementations for anything slightly complicated.
4001 * @{ */
4002
4003/**
4004 * For typedef'ing or declaring a C instruction implementation function taking
4005 * no extra arguments.
4006 *
4007 * @param a_Name The name of the type.
4008 */
4009# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
4010 IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
4011/**
4012 * For defining a C instruction implementation function taking no extra
4013 * arguments.
4014 *
4015 * @param a_Name The name of the function
4016 */
4017# define IEM_CIMPL_DEF_0(a_Name) \
4018 IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
4019/**
4020 * Prototype version of IEM_CIMPL_DEF_0.
4021 */
4022# define IEM_CIMPL_PROTO_0(a_Name) \
4023 IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
4024/**
4025 * For calling a C instruction implementation function taking no extra
4026 * arguments.
4027 *
4028 * This special call macro adds default arguments to the call and allow us to
4029 * change these later.
4030 *
4031 * @param a_fn The name of the function.
4032 */
4033# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
4034
4035/** Type for a C instruction implementation function taking no extra
4036 * arguments. */
4037typedef IEM_CIMPL_DECL_TYPE_0(FNIEMCIMPL0);
4038/** Function pointer type for a C instruction implementation function taking
4039 * no extra arguments. */
4040typedef FNIEMCIMPL0 *PFNIEMCIMPL0;
4041
4042/**
4043 * For typedef'ing or declaring a C instruction implementation function taking
4044 * one extra argument.
4045 *
4046 * @param a_Name The name of the type.
4047 * @param a_Type0 The argument type.
4048 * @param a_Arg0 The argument name.
4049 */
4050# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
4051 IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
4052/**
4053 * For defining a C instruction implementation function taking one extra
4054 * argument.
4055 *
4056 * @param a_Name The name of the function
4057 * @param a_Type0 The argument type.
4058 * @param a_Arg0 The argument name.
4059 */
4060# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
4061 IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
4062/**
4063 * Prototype version of IEM_CIMPL_DEF_1.
4064 */
4065# define IEM_CIMPL_PROTO_1(a_Name, a_Type0, a_Arg0) \
4066 IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
4067/**
4068 * For calling a C instruction implementation function taking one extra
4069 * argument.
4070 *
4071 * This special call macro adds default arguments to the call and allow us to
4072 * change these later.
4073 *
4074 * @param a_fn The name of the function.
4075 * @param a0 The name of the 1st argument.
4076 */
4077# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
4078
4079/**
4080 * For typedef'ing or declaring a C instruction implementation function taking
4081 * two extra arguments.
4082 *
4083 * @param a_Name The name of the type.
4084 * @param a_Type0 The type of the 1st argument
4085 * @param a_Arg0 The name of the 1st argument.
4086 * @param a_Type1 The type of the 2nd argument.
4087 * @param a_Arg1 The name of the 2nd argument.
4088 */
4089# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
4090 IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
4091/**
4092 * For defining a C instruction implementation function taking two extra
4093 * arguments.
4094 *
4095 * @param a_Name The name of the function.
4096 * @param a_Type0 The type of the 1st argument
4097 * @param a_Arg0 The name of the 1st argument.
4098 * @param a_Type1 The type of the 2nd argument.
4099 * @param a_Arg1 The name of the 2nd argument.
4100 */
4101# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
4102 IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
4103/**
4104 * Prototype version of IEM_CIMPL_DEF_2.
4105 */
4106# define IEM_CIMPL_PROTO_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
4107 IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
4108/**
4109 * For calling a C instruction implementation function taking two extra
4110 * arguments.
4111 *
4112 * This special call macro adds default arguments to the call and allow us to
4113 * change these later.
4114 *
4115 * @param a_fn The name of the function.
4116 * @param a0 The name of the 1st argument.
4117 * @param a1 The name of the 2nd argument.
4118 */
4119# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
4120
4121/**
4122 * For typedef'ing or declaring a C instruction implementation function taking
4123 * three extra arguments.
4124 *
4125 * @param a_Name The name of the type.
4126 * @param a_Type0 The type of the 1st argument
4127 * @param a_Arg0 The name of the 1st argument.
4128 * @param a_Type1 The type of the 2nd argument.
4129 * @param a_Arg1 The name of the 2nd argument.
4130 * @param a_Type2 The type of the 3rd argument.
4131 * @param a_Arg2 The name of the 3rd argument.
4132 */
4133# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
4134 IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
4135/**
4136 * For defining a C instruction implementation function taking three extra
4137 * arguments.
4138 *
4139 * @param a_Name The name of the function.
4140 * @param a_Type0 The type of the 1st argument
4141 * @param a_Arg0 The name of the 1st argument.
4142 * @param a_Type1 The type of the 2nd argument.
4143 * @param a_Arg1 The name of the 2nd argument.
4144 * @param a_Type2 The type of the 3rd argument.
4145 * @param a_Arg2 The name of the 3rd argument.
4146 */
4147# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
4148 IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
4149/**
4150 * Prototype version of IEM_CIMPL_DEF_3.
4151 */
4152# define IEM_CIMPL_PROTO_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
4153 IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
4154/**
4155 * For calling a C instruction implementation function taking three extra
4156 * arguments.
4157 *
4158 * This special call macro adds default arguments to the call and allow us to
4159 * change these later.
4160 *
4161 * @param a_fn The name of the function.
4162 * @param a0 The name of the 1st argument.
4163 * @param a1 The name of the 2nd argument.
4164 * @param a2 The name of the 3rd argument.
4165 */
4166# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
4167
4168
4169/**
4170 * For typedef'ing or declaring a C instruction implementation function taking
4171 * four extra arguments.
4172 *
4173 * @param a_Name The name of the type.
4174 * @param a_Type0 The type of the 1st argument
4175 * @param a_Arg0 The name of the 1st argument.
4176 * @param a_Type1 The type of the 2nd argument.
4177 * @param a_Arg1 The name of the 2nd argument.
4178 * @param a_Type2 The type of the 3rd argument.
4179 * @param a_Arg2 The name of the 3rd argument.
4180 * @param a_Type3 The type of the 4th argument.
4181 * @param a_Arg3 The name of the 4th argument.
4182 */
4183# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
4184 IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
4185/**
4186 * For defining a C instruction implementation function taking four extra
4187 * arguments.
4188 *
4189 * @param a_Name The name of the function.
4190 * @param a_Type0 The type of the 1st argument
4191 * @param a_Arg0 The name of the 1st argument.
4192 * @param a_Type1 The type of the 2nd argument.
4193 * @param a_Arg1 The name of the 2nd argument.
4194 * @param a_Type2 The type of the 3rd argument.
4195 * @param a_Arg2 The name of the 3rd argument.
4196 * @param a_Type3 The type of the 4th argument.
4197 * @param a_Arg3 The name of the 4th argument.
4198 */
4199# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
4200 IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4201 a_Type2 a_Arg2, a_Type3 a_Arg3))
4202/**
4203 * Prototype version of IEM_CIMPL_DEF_4.
4204 */
4205# define IEM_CIMPL_PROTO_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
4206 IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4207 a_Type2 a_Arg2, a_Type3 a_Arg3))
4208/**
4209 * For calling a C instruction implementation function taking four extra
4210 * arguments.
4211 *
4212 * This special call macro adds default arguments to the call and allow us to
4213 * change these later.
4214 *
4215 * @param a_fn The name of the function.
4216 * @param a0 The name of the 1st argument.
4217 * @param a1 The name of the 2nd argument.
4218 * @param a2 The name of the 3rd argument.
4219 * @param a3 The name of the 4th argument.
4220 */
4221# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
4222
4223
4224/**
4225 * For typedef'ing or declaring a C instruction implementation function taking
4226 * five extra arguments.
4227 *
4228 * @param a_Name The name of the type.
4229 * @param a_Type0 The type of the 1st argument
4230 * @param a_Arg0 The name of the 1st argument.
4231 * @param a_Type1 The type of the 2nd argument.
4232 * @param a_Arg1 The name of the 2nd argument.
4233 * @param a_Type2 The type of the 3rd argument.
4234 * @param a_Arg2 The name of the 3rd argument.
4235 * @param a_Type3 The type of the 4th argument.
4236 * @param a_Arg3 The name of the 4th argument.
4237 * @param a_Type4 The type of the 5th argument.
4238 * @param a_Arg4 The name of the 5th argument.
4239 */
4240# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
4241 IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, \
4242 a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
4243 a_Type3 a_Arg3, a_Type4 a_Arg4))
4244/**
4245 * For defining a C instruction implementation function taking five extra
4246 * arguments.
4247 *
4248 * @param a_Name The name of the function.
4249 * @param a_Type0 The type of the 1st argument
4250 * @param a_Arg0 The name of the 1st argument.
4251 * @param a_Type1 The type of the 2nd argument.
4252 * @param a_Arg1 The name of the 2nd argument.
4253 * @param a_Type2 The type of the 3rd argument.
4254 * @param a_Arg2 The name of the 3rd argument.
4255 * @param a_Type3 The type of the 4th argument.
4256 * @param a_Arg3 The name of the 4th argument.
4257 * @param a_Type4 The type of the 5th argument.
4258 * @param a_Arg4 The name of the 5th argument.
4259 */
4260# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
4261 IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4262 a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
4263/**
4264 * Prototype version of IEM_CIMPL_DEF_5.
4265 */
4266# define IEM_CIMPL_PROTO_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
4267 IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4268 a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
4269/**
4270 * For calling a C instruction implementation function taking five extra
4271 * arguments.
4272 *
4273 * This special call macro adds default arguments to the call and allow us to
4274 * change these later.
4275 *
4276 * @param a_fn The name of the function.
4277 * @param a0 The name of the 1st argument.
4278 * @param a1 The name of the 2nd argument.
4279 * @param a2 The name of the 3rd argument.
4280 * @param a3 The name of the 4th argument.
4281 * @param a4 The name of the 5th argument.
4282 */
4283# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
4284
4285/** @} */
4286
4287
4288/** @name Opcode Decoder Function Types.
4289 * @{ */
4290
4291/** @typedef PFNIEMOP
4292 * Pointer to an opcode decoder function.
4293 */
4294
4295/** @def FNIEMOP_DEF
4296 * Define an opcode decoder function.
4297 *
4298 * We're using macors for this so that adding and removing parameters as well as
4299 * tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL
4300 *
4301 * @param a_Name The function name.
4302 */
4303
4304/** @typedef PFNIEMOPRM
4305 * Pointer to an opcode decoder function with RM byte.
4306 */
4307
4308/** @def FNIEMOPRM_DEF
4309 * Define an opcode decoder function with RM byte.
4310 *
4311 * We're using macors for this so that adding and removing parameters as well as
4312 * tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL_1
4313 *
4314 * @param a_Name The function name.
4315 */
4316
4317#if defined(__GNUC__) && defined(RT_ARCH_X86)
4318typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOP)(PVMCPUCC pVCpu);
4319typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4320# define FNIEMOP_DEF(a_Name) \
4321 IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu)
4322# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4323 IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
4324# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4325 IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
4326
4327#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
4328typedef VBOXSTRICTRC (__fastcall * PFNIEMOP)(PVMCPUCC pVCpu);
4329typedef VBOXSTRICTRC (__fastcall * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4330# define FNIEMOP_DEF(a_Name) \
4331 IEM_STATIC /*__declspec(naked)*/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
4332# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4333 IEM_STATIC /*__declspec(naked)*/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
4334# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4335 IEM_STATIC /*__declspec(naked)*/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
4336
4337#elif defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
4338typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
4339typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4340# define FNIEMOP_DEF(a_Name) \
4341 IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu)
4342# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4343 IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
4344# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4345 IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
4346
4347#else
4348typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
4349typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4350# define FNIEMOP_DEF(a_Name) \
4351 IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
4352# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4353 IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
4354# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4355 IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
4356
4357#endif
4358#define FNIEMOPRM_DEF(a_Name) FNIEMOP_DEF_1(a_Name, uint8_t, bRm)
4359
4360/**
4361 * Call an opcode decoder function.
4362 *
4363 * We're using macors for this so that adding and removing parameters can be
4364 * done as we please. See FNIEMOP_DEF.
4365 */
4366#define FNIEMOP_CALL(a_pfn) (a_pfn)(pVCpu)
4367
4368/**
4369 * Call a common opcode decoder function taking one extra argument.
4370 *
4371 * We're using macors for this so that adding and removing parameters can be
4372 * done as we please. See FNIEMOP_DEF_1.
4373 */
4374#define FNIEMOP_CALL_1(a_pfn, a0) (a_pfn)(pVCpu, a0)
4375
4376/**
4377 * Call a common opcode decoder function taking one extra argument.
4378 *
4379 * We're using macors for this so that adding and removing parameters can be
4380 * done as we please. See FNIEMOP_DEF_1.
4381 */
4382#define FNIEMOP_CALL_2(a_pfn, a0, a1) (a_pfn)(pVCpu, a0, a1)
4383/** @} */
4384
4385
4386/** @name Misc Helpers
4387 * @{ */
4388
4389/** Used to shut up GCC warnings about variables that 'may be used uninitialized'
4390 * due to GCC lacking knowledge about the value range of a switch. */
4391#if RT_CPLUSPLUS_PREREQ(202000)
4392# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: [[unlikely]] AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
4393#else
4394# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
4395#endif
4396
4397/** Variant of IEM_NOT_REACHED_DEFAULT_CASE_RET that returns a custom value. */
4398#if RT_CPLUSPLUS_PREREQ(202000)
4399# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: [[unlikely]] AssertFailedReturn(a_RetValue)
4400#else
4401# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: AssertFailedReturn(a_RetValue)
4402#endif
4403
4404/**
4405 * Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
4406 * occation.
4407 */
4408#ifdef LOG_ENABLED
4409# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
4410 do { \
4411 /*Log*/ LogAlways(("%s: returning IEM_RETURN_ASPECT_NOT_IMPLEMENTED (line %d)\n", __FUNCTION__, __LINE__)); \
4412 return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
4413 } while (0)
4414#else
4415# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
4416 return VERR_IEM_ASPECT_NOT_IMPLEMENTED
4417#endif
4418
4419/**
4420 * Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
4421 * occation using the supplied logger statement.
4422 *
4423 * @param a_LoggerArgs What to log on failure.
4424 */
4425#ifdef LOG_ENABLED
4426# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
4427 do { \
4428 LogAlways((LOG_FN_FMT ": ", __PRETTY_FUNCTION__)); LogAlways(a_LoggerArgs); \
4429 /*LogFunc(a_LoggerArgs);*/ \
4430 return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
4431 } while (0)
4432#else
4433# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
4434 return VERR_IEM_ASPECT_NOT_IMPLEMENTED
4435#endif
4436
4437/**
4438 * Gets the CPU mode (from fExec) as a IEMMODE value.
4439 *
4440 * @returns IEMMODE
4441 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4442 */
4443#define IEM_GET_CPU_MODE(a_pVCpu) ((a_pVCpu)->iem.s.fExec & IEM_F_MODE_CPUMODE_MASK)
4444
4445/**
4446 * Check if we're currently executing in real or virtual 8086 mode.
4447 *
4448 * @returns @c true if it is, @c false if not.
4449 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4450 */
4451#define IEM_IS_REAL_OR_V86_MODE(a_pVCpu) (( ((a_pVCpu)->iem.s.fExec ^ IEM_F_MODE_X86_PROT_MASK) \
4452 & (IEM_F_MODE_X86_V86_MASK | IEM_F_MODE_X86_PROT_MASK)) != 0)
4453
4454/**
4455 * Check if we're currently executing in virtual 8086 mode.
4456 *
4457 * @returns @c true if it is, @c false if not.
4458 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4459 */
4460#define IEM_IS_V86_MODE(a_pVCpu) (((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_V86_MASK) != 0)
4461
4462/**
4463 * Check if we're currently executing in long mode.
4464 *
4465 * @returns @c true if it is, @c false if not.
4466 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4467 */
4468#define IEM_IS_LONG_MODE(a_pVCpu) (CPUMIsGuestInLongModeEx(IEM_GET_CTX(a_pVCpu)))
4469
4470/**
4471 * Check if we're currently executing in a 16-bit code segment.
4472 *
4473 * @returns @c true if it is, @c false if not.
4474 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4475 */
4476#define IEM_IS_16BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_16BIT)
4477
4478/**
4479 * Check if we're currently executing in a 32-bit code segment.
4480 *
4481 * @returns @c true if it is, @c false if not.
4482 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4483 */
4484#define IEM_IS_32BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_32BIT)
4485
4486/**
4487 * Check if we're currently executing in a 64-bit code segment.
4488 *
4489 * @returns @c true if it is, @c false if not.
4490 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4491 */
4492#define IEM_IS_64BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_64BIT)
4493
4494/**
4495 * Check if we're currently executing in real mode.
4496 *
4497 * @returns @c true if it is, @c false if not.
4498 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4499 */
4500#define IEM_IS_REAL_MODE(a_pVCpu) (!((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_PROT_MASK))
4501
4502/**
4503 * Gets the current protection level (CPL).
4504 *
4505 * @returns 0..3
4506 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4507 */
4508#define IEM_GET_CPL(a_pVCpu) (((a_pVCpu)->iem.s.fExec >> IEM_F_X86_CPL_SHIFT) & IEM_F_X86_CPL_SMASK)
4509
4510/**
4511 * Sets the current protection level (CPL).
4512 *
4513 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4514 */
4515#define IEM_SET_CPL(a_pVCpu, a_uCpl) \
4516 do { (a_pVCpu)->iem.s.fExec = ((a_pVCpu)->iem.s.fExec & ~IEM_F_X86_CPL_MASK) | ((a_uCpl) << IEM_F_X86_CPL_SHIFT); } while (0)
4517
4518/**
4519 * Returns a (const) pointer to the CPUMFEATURES for the guest CPU.
4520 * @returns PCCPUMFEATURES
4521 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4522 */
4523#define IEM_GET_GUEST_CPU_FEATURES(a_pVCpu) (&((a_pVCpu)->CTX_SUFF(pVM)->cpum.ro.GuestFeatures))
4524
4525/**
4526 * Returns a (const) pointer to the CPUMFEATURES for the host CPU.
4527 * @returns PCCPUMFEATURES
4528 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4529 */
4530#define IEM_GET_HOST_CPU_FEATURES(a_pVCpu) (&g_CpumHostFeatures.s)
4531
4532/**
4533 * Evaluates to true if we're presenting an Intel CPU to the guest.
4534 */
4535#define IEM_IS_GUEST_CPU_INTEL(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL )
4536
4537/**
4538 * Evaluates to true if we're presenting an AMD CPU to the guest.
4539 */
4540#define IEM_IS_GUEST_CPU_AMD(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_AMD || (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_HYGON )
4541
4542/**
4543 * Check if the address is canonical.
4544 */
4545#define IEM_IS_CANONICAL(a_u64Addr) X86_IS_CANONICAL(a_u64Addr)
4546
4547/** Checks if the ModR/M byte is in register mode or not. */
4548#define IEM_IS_MODRM_REG_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT) )
4549/** Checks if the ModR/M byte is in memory mode or not. */
4550#define IEM_IS_MODRM_MEM_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT) )
4551
4552/**
4553 * Gets the register (reg) part of a ModR/M encoding, with REX.R added in.
4554 *
4555 * For use during decoding.
4556 */
4557#define IEM_GET_MODRM_REG(a_pVCpu, a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | (a_pVCpu)->iem.s.uRexReg )
4558/**
4559 * Gets the r/m part of a ModR/M encoding as a register index, with REX.B added in.
4560 *
4561 * For use during decoding.
4562 */
4563#define IEM_GET_MODRM_RM(a_pVCpu, a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) | (a_pVCpu)->iem.s.uRexB )
4564
4565/**
4566 * Gets the register (reg) part of a ModR/M encoding, without REX.R.
4567 *
4568 * For use during decoding.
4569 */
4570#define IEM_GET_MODRM_REG_8(a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) )
4571/**
4572 * Gets the r/m part of a ModR/M encoding as a register index, without REX.B.
4573 *
4574 * For use during decoding.
4575 */
4576#define IEM_GET_MODRM_RM_8(a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) )
4577
4578/**
4579 * Gets the register (reg) part of a ModR/M encoding as an extended 8-bit
4580 * register index, with REX.R added in.
4581 *
4582 * For use during decoding.
4583 *
4584 * @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
4585 */
4586#define IEM_GET_MODRM_REG_EX8(a_pVCpu, a_bRm) \
4587 ( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
4588 || !((a_bRm) & (4 << X86_MODRM_REG_SHIFT)) /* IEM_GET_MODRM_REG(pVCpu, a_bRm) < 4 */ \
4589 ? IEM_GET_MODRM_REG(pVCpu, a_bRm) : (((a_bRm) >> X86_MODRM_REG_SHIFT) & 3) | 16)
4590/**
4591 * Gets the r/m part of a ModR/M encoding as an extended 8-bit register index,
4592 * with REX.B added in.
4593 *
4594 * For use during decoding.
4595 *
4596 * @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
4597 */
4598#define IEM_GET_MODRM_RM_EX8(a_pVCpu, a_bRm) \
4599 ( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
4600 || !((a_bRm) & 4) /* IEM_GET_MODRM_RM(pVCpu, a_bRm) < 4 */ \
4601 ? IEM_GET_MODRM_RM(pVCpu, a_bRm) : ((a_bRm) & 3) | 16)
4602
4603/**
4604 * Combines the prefix REX and ModR/M byte for passing to
4605 * iemOpHlpCalcRmEffAddrThreadedAddr64().
4606 *
4607 * @returns The ModRM byte but with bit 3 set to REX.B and bit 4 to REX.X.
4608 * The two bits are part of the REG sub-field, which isn't needed in
4609 * iemOpHlpCalcRmEffAddrThreadedAddr64().
4610 *
4611 * For use during decoding/recompiling.
4612 */
4613#define IEM_GET_MODRM_EX(a_pVCpu, a_bRm) \
4614 ( ((a_bRm) & ~X86_MODRM_REG_MASK) \
4615 | (uint8_t)( (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_REX_B | IEM_OP_PRF_REX_X)) >> (26 - 3) ) )
4616AssertCompile(IEM_OP_PRF_REX_B == RT_BIT_32(26));
4617AssertCompile(IEM_OP_PRF_REX_X == RT_BIT_32(27));
4618
4619/**
4620 * Gets the effective VEX.VVVV value.
4621 *
4622 * The 4th bit is ignored if not 64-bit code.
4623 * @returns effective V-register value.
4624 * @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4625 */
4626#define IEM_GET_EFFECTIVE_VVVV(a_pVCpu) \
4627 (IEM_IS_64BIT_CODE(a_pVCpu) ? (a_pVCpu)->iem.s.uVex3rdReg : (a_pVCpu)->iem.s.uVex3rdReg & 7)
4628
4629
4630/**
4631 * Checks if we're executing inside an AMD-V or VT-x guest.
4632 */
4633#if defined(VBOX_WITH_NESTED_HWVIRT_VMX) || defined(VBOX_WITH_NESTED_HWVIRT_SVM)
4634# define IEM_IS_IN_GUEST(a_pVCpu) RT_BOOL((a_pVCpu)->iem.s.fExec & IEM_F_X86_CTX_IN_GUEST)
4635#else
4636# define IEM_IS_IN_GUEST(a_pVCpu) false
4637#endif
4638
4639
4640#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
4641
4642/**
4643 * Check if the guest has entered VMX root operation.
4644 */
4645# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxRootMode(IEM_GET_CTX(a_pVCpu)))
4646
4647/**
4648 * Check if the guest has entered VMX non-root operation.
4649 */
4650# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) ( ((a_pVCpu)->iem.s.fExec & (IEM_F_X86_CTX_VMX | IEM_F_X86_CTX_IN_GUEST)) \
4651 == (IEM_F_X86_CTX_VMX | IEM_F_X86_CTX_IN_GUEST) )
4652
4653/**
4654 * Check if the nested-guest has the given Pin-based VM-execution control set.
4655 */
4656# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_PinCtl) (CPUMIsGuestVmxPinCtlsSet(IEM_GET_CTX(a_pVCpu), (a_PinCtl)))
4657
4658/**
4659 * Check if the nested-guest has the given Processor-based VM-execution control set.
4660 */
4661# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_ProcCtl) (CPUMIsGuestVmxProcCtlsSet(IEM_GET_CTX(a_pVCpu), (a_ProcCtl)))
4662
4663/**
4664 * Check if the nested-guest has the given Secondary Processor-based VM-execution
4665 * control set.
4666 */
4667# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_ProcCtl2) (CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(a_pVCpu), (a_ProcCtl2)))
4668
4669/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
4670# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
4671
4672/** Whether a shadow VMCS is present for the given VCPU. */
4673# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
4674
4675/** Gets the VMXON region pointer. */
4676# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
4677
4678/** Gets the guest-physical address of the current VMCS for the given VCPU. */
4679# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
4680
4681/** Whether a current VMCS is present for the given VCPU. */
4682# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
4683
4684/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
4685# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
4686 do \
4687 { \
4688 Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
4689 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
4690 } while (0)
4691
4692/** Clears any current VMCS for the given VCPU. */
4693# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
4694 do \
4695 { \
4696 (a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
4697 } while (0)
4698
4699/**
4700 * Invokes the VMX VM-exit handler for an instruction intercept.
4701 */
4702# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) \
4703 do { return iemVmxVmexitInstr((a_pVCpu), (a_uExitReason), (a_cbInstr)); } while (0)
4704
4705/**
4706 * Invokes the VMX VM-exit handler for an instruction intercept where the
4707 * instruction provides additional VM-exit information.
4708 */
4709# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) \
4710 do { return iemVmxVmexitInstrNeedsInfo((a_pVCpu), (a_uExitReason), (a_uInstrId), (a_cbInstr)); } while (0)
4711
4712/**
4713 * Invokes the VMX VM-exit handler for a task switch.
4714 */
4715# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) \
4716 do { return iemVmxVmexitTaskSwitch((a_pVCpu), (a_enmTaskSwitch), (a_SelNewTss), (a_cbInstr)); } while (0)
4717
4718/**
4719 * Invokes the VMX VM-exit handler for MWAIT.
4720 */
4721# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) \
4722 do { return iemVmxVmexitInstrMwait((a_pVCpu), (a_fMonitorArmed), (a_cbInstr)); } while (0)
4723
4724/**
4725 * Invokes the VMX VM-exit handler for EPT faults.
4726 */
4727# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) \
4728 do { return iemVmxVmexitEpt(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr); } while (0)
4729
4730/**
4731 * Invokes the VMX VM-exit handler.
4732 */
4733# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) \
4734 do { return iemVmxVmexit((a_pVCpu), (a_uExitReason), (a_uExitQual)); } while (0)
4735
4736#else
4737# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (false)
4738# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (false)
4739# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_cbInstr) (false)
4740# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_cbInstr) (false)
4741# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_cbInstr) (false)
4742# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4743# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4744# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4745# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4746# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4747# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) do { return VERR_VMX_IPE_1; } while (0)
4748
4749#endif
4750
4751#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4752/**
4753 * Checks if we're executing a guest using AMD-V.
4754 */
4755# define IEM_SVM_IS_IN_GUEST(a_pVCpu) ( (a_pVCpu->iem.s.fExec & (IEM_F_X86_CTX_SVM | IEM_F_X86_CTX_IN_GUEST)) \
4756 == (IEM_F_X86_CTX_SVM | IEM_F_X86_CTX_IN_GUEST))
4757/**
4758 * Check if an SVM control/instruction intercept is set.
4759 */
4760# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) \
4761 (IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmCtrlInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_Intercept)))
4762
4763/**
4764 * Check if an SVM read CRx intercept is set.
4765 */
4766# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
4767 (IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
4768
4769/**
4770 * Check if an SVM write CRx intercept is set.
4771 */
4772# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
4773 (IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
4774
4775/**
4776 * Check if an SVM read DRx intercept is set.
4777 */
4778# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
4779 (IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
4780
4781/**
4782 * Check if an SVM write DRx intercept is set.
4783 */
4784# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
4785 (IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
4786
4787/**
4788 * Check if an SVM exception intercept is set.
4789 */
4790# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) \
4791 (IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmXcptInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uVector)))
4792
4793/**
4794 * Invokes the SVM \#VMEXIT handler for the nested-guest.
4795 */
4796# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
4797 do { return iemSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2)); } while (0)
4798
4799/**
4800 * Invokes the 'MOV CRx' SVM \#VMEXIT handler after constructing the
4801 * corresponding decode assist information.
4802 */
4803# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) \
4804 do \
4805 { \
4806 uint64_t uExitInfo1; \
4807 if ( IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmDecodeAssists \
4808 && (a_enmAccessCrX) == IEMACCESSCRX_MOV_CRX) \
4809 uExitInfo1 = SVM_EXIT1_MOV_CRX_MASK | ((a_iGReg) & 7); \
4810 else \
4811 uExitInfo1 = 0; \
4812 IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, uExitInfo1, 0); \
4813 } while (0)
4814
4815/** Check and handles SVM nested-guest instruction intercept and updates
4816 * NRIP if needed.
4817 */
4818# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
4819 do \
4820 { \
4821 if (IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept)) \
4822 { \
4823 IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
4824 IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2); \
4825 } \
4826 } while (0)
4827
4828/** Checks and handles SVM nested-guest CR0 read intercept. */
4829# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
4830 do \
4831 { \
4832 if (!IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, 0)) \
4833 { /* probably likely */ } \
4834 else \
4835 { \
4836 IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
4837 IEM_SVM_VMEXIT_RET(a_pVCpu, SVM_EXIT_READ_CR0, a_uExitInfo1, a_uExitInfo2); \
4838 } \
4839 } while (0)
4840
4841/**
4842 * Updates the NextRIP (NRI) field in the nested-guest VMCB.
4843 */
4844# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) \
4845 do { \
4846 if (IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmNextRipSave) \
4847 CPUMGuestSvmUpdateNRip(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_cbInstr)); \
4848 } while (0)
4849
4850#else
4851# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) (false)
4852# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
4853# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
4854# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
4855# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
4856# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) (false)
4857# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { return VERR_SVM_IPE_1; } while (0)
4858# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) do { return VERR_SVM_IPE_1; } while (0)
4859# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, \
4860 a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
4861# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
4862# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) do { } while (0)
4863
4864#endif
4865
4866/** @} */
4867
4868uint32_t iemCalcExecDbgFlagsSlow(PVMCPUCC pVCpu);
4869VBOXSTRICTRC iemExecInjectPendingTrap(PVMCPUCC pVCpu);
4870
4871
4872/**
4873 * Selector descriptor table entry as fetched by iemMemFetchSelDesc.
4874 */
4875typedef union IEMSELDESC
4876{
4877 /** The legacy view. */
4878 X86DESC Legacy;
4879 /** The long mode view. */
4880 X86DESC64 Long;
4881} IEMSELDESC;
4882/** Pointer to a selector descriptor table entry. */
4883typedef IEMSELDESC *PIEMSELDESC;
4884
4885/** @name Raising Exceptions.
4886 * @{ */
4887VBOXSTRICTRC iemTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, uint32_t uNextEip, uint32_t fFlags,
4888 uint16_t uErr, uint64_t uCr2, RTSEL SelTSS, PIEMSELDESC pNewDescTSS) RT_NOEXCEPT;
4889
4890VBOXSTRICTRC iemRaiseXcptOrInt(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags,
4891 uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
4892#ifdef IEM_WITH_SETJMP
4893DECL_NO_RETURN(void) iemRaiseXcptOrIntJmp(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector,
4894 uint32_t fFlags, uint16_t uErr, uint64_t uCr2) IEM_NOEXCEPT_MAY_LONGJMP;
4895#endif
4896VBOXSTRICTRC iemRaiseDivideError(PVMCPUCC pVCpu) RT_NOEXCEPT;
4897VBOXSTRICTRC iemRaiseDebugException(PVMCPUCC pVCpu) RT_NOEXCEPT;
4898VBOXSTRICTRC iemRaiseBoundRangeExceeded(PVMCPUCC pVCpu) RT_NOEXCEPT;
4899VBOXSTRICTRC iemRaiseUndefinedOpcode(PVMCPUCC pVCpu) RT_NOEXCEPT;
4900VBOXSTRICTRC iemRaiseDeviceNotAvailable(PVMCPUCC pVCpu) RT_NOEXCEPT;
4901VBOXSTRICTRC iemRaiseTaskSwitchFaultWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
4902VBOXSTRICTRC iemRaiseTaskSwitchFaultCurrentTSS(PVMCPUCC pVCpu) RT_NOEXCEPT;
4903VBOXSTRICTRC iemRaiseTaskSwitchFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
4904VBOXSTRICTRC iemRaiseTaskSwitchFaultBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
4905/*VBOXSTRICTRC iemRaiseSelectorNotPresent(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;*/
4906VBOXSTRICTRC iemRaiseSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
4907VBOXSTRICTRC iemRaiseSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
4908VBOXSTRICTRC iemRaiseStackSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
4909VBOXSTRICTRC iemRaiseStackSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
4910VBOXSTRICTRC iemRaiseGeneralProtectionFault(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
4911VBOXSTRICTRC iemRaiseGeneralProtectionFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
4912#ifdef IEM_WITH_SETJMP
4913DECL_NO_RETURN(void) iemRaiseGeneralProtectionFault0Jmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4914#endif
4915VBOXSTRICTRC iemRaiseGeneralProtectionFaultBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
4916VBOXSTRICTRC iemRaiseNotCanonical(PVMCPUCC pVCpu) RT_NOEXCEPT;
4917VBOXSTRICTRC iemRaiseSelectorBounds(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
4918#ifdef IEM_WITH_SETJMP
4919DECL_NO_RETURN(void) iemRaiseSelectorBoundsJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
4920#endif
4921VBOXSTRICTRC iemRaiseSelectorBoundsBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
4922#ifdef IEM_WITH_SETJMP
4923DECL_NO_RETURN(void) iemRaiseSelectorBoundsBySelectorJmp(PVMCPUCC pVCpu, RTSEL Sel) IEM_NOEXCEPT_MAY_LONGJMP;
4924#endif
4925VBOXSTRICTRC iemRaiseSelectorInvalidAccess(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
4926#ifdef IEM_WITH_SETJMP
4927DECL_NO_RETURN(void) iemRaiseSelectorInvalidAccessJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
4928#endif
4929VBOXSTRICTRC iemRaisePageFault(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) RT_NOEXCEPT;
4930#ifdef IEM_WITH_SETJMP
4931DECL_NO_RETURN(void) iemRaisePageFaultJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) IEM_NOEXCEPT_MAY_LONGJMP;
4932#endif
4933VBOXSTRICTRC iemRaiseMathFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
4934VBOXSTRICTRC iemRaiseAlignmentCheckException(PVMCPUCC pVCpu) RT_NOEXCEPT;
4935#ifdef IEM_WITH_SETJMP
4936DECL_NO_RETURN(void) iemRaiseAlignmentCheckExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4937#endif
4938VBOXSTRICTRC iemRaiseSimdFpException(PVMCPUCC pVCpu) RT_NOEXCEPT;
4939
4940void iemLogSyscallProtModeInt(PVMCPUCC pVCpu, uint8_t u8Vector, uint8_t cbInstr);
4941
4942IEM_CIMPL_DEF_0(iemCImplRaiseDivideError);
4943IEM_CIMPL_DEF_0(iemCImplRaiseInvalidLockPrefix);
4944IEM_CIMPL_DEF_0(iemCImplRaiseInvalidOpcode);
4945
4946/**
4947 * Macro for calling iemCImplRaiseDivideError().
4948 *
4949 * This is for things that will _always_ decode to an \#DE, taking the
4950 * recompiler into consideration and everything.
4951 *
4952 * @return Strict VBox status code.
4953 */
4954#define IEMOP_RAISE_DIVIDE_ERROR_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseDivideError)
4955
4956/**
4957 * Macro for calling iemCImplRaiseInvalidLockPrefix().
4958 *
4959 * This is for things that will _always_ decode to an \#UD, taking the
4960 * recompiler into consideration and everything.
4961 *
4962 * @return Strict VBox status code.
4963 */
4964#define IEMOP_RAISE_INVALID_LOCK_PREFIX_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidLockPrefix)
4965
4966/**
4967 * Macro for calling iemCImplRaiseInvalidOpcode() for decode/static \#UDs.
4968 *
4969 * This is for things that will _always_ decode to an \#UD, taking the
4970 * recompiler into consideration and everything.
4971 *
4972 * @return Strict VBox status code.
4973 */
4974#define IEMOP_RAISE_INVALID_OPCODE_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidOpcode)
4975
4976/**
4977 * Macro for calling iemCImplRaiseInvalidOpcode() for runtime-style \#UDs.
4978 *
4979 * Using this macro means you've got _buggy_ _code_ and are doing things that
4980 * belongs exclusively in IEMAllCImpl.cpp during decoding.
4981 *
4982 * @return Strict VBox status code.
4983 * @see IEMOP_RAISE_INVALID_OPCODE_RET
4984 */
4985#define IEMOP_RAISE_INVALID_OPCODE_RUNTIME_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidOpcode)
4986
4987/** @} */
4988
4989/** @name Register Access.
4990 * @{ */
4991VBOXSTRICTRC iemRegRipRelativeJumpS8AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int8_t offNextInstr,
4992 IEMMODE enmEffOpSize) RT_NOEXCEPT;
4993VBOXSTRICTRC iemRegRipRelativeJumpS16AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int16_t offNextInstr) RT_NOEXCEPT;
4994VBOXSTRICTRC iemRegRipRelativeJumpS32AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int32_t offNextInstr,
4995 IEMMODE enmEffOpSize) RT_NOEXCEPT;
4996VBOXSTRICTRC iemRegRipJumpU16AndFinishClearningRF(PVMCPUCC pVCpu, uint16_t uNewRip) RT_NOEXCEPT;
4997VBOXSTRICTRC iemRegRipJumpU32AndFinishClearningRF(PVMCPUCC pVCpu, uint32_t uNewRip) RT_NOEXCEPT;
4998VBOXSTRICTRC iemRegRipJumpU64AndFinishClearningRF(PVMCPUCC pVCpu, uint64_t uNewRip) RT_NOEXCEPT;
4999/** @} */
5000
5001/** @name FPU access and helpers.
5002 * @{ */
5003void iemFpuPushResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
5004void iemFpuPushResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5005void iemFpuPushResultTwo(PVMCPUCC pVCpu, PIEMFPURESULTTWO pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
5006void iemFpuStoreResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
5007void iemFpuStoreResultThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
5008void iemFpuStoreResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
5009 uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5010void iemFpuStoreResultWithMemOpThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
5011 uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5012void iemFpuUpdateOpcodeAndIp(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5013void iemFpuUpdateFSW(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
5014void iemFpuUpdateFSWThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
5015void iemFpuUpdateFSWWithMemOp(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5016void iemFpuUpdateFSWThenPopPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
5017void iemFpuUpdateFSWWithMemOpThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5018void iemFpuStackUnderflow(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
5019void iemFpuStackUnderflowWithMemOp(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5020void iemFpuStackUnderflowThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
5021void iemFpuStackUnderflowWithMemOpThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5022void iemFpuStackUnderflowThenPopPop(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5023void iemFpuStackPushUnderflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5024void iemFpuStackPushUnderflowTwo(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5025void iemFpuStackPushOverflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5026void iemFpuStackPushOverflowWithMemOp(PVMCPUCC pVCpu, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5027/** @} */
5028
5029/** @name SSE+AVX SIMD access and helpers.
5030 * @{ */
5031void iemSseStoreResult(PVMCPUCC pVCpu, PCIEMSSERESULT pResult, uint8_t iXmmReg) RT_NOEXCEPT;
5032void iemSseUpdateMxcsr(PVMCPUCC pVCpu, uint32_t fMxcsr) RT_NOEXCEPT;
5033/** @} */
5034
5035/** @name Memory access.
5036 * @{ */
5037
5038/** Report a \#GP instead of \#AC and do not restrict to ring-3 */
5039#define IEM_MEMMAP_F_ALIGN_GP RT_BIT_32(16)
5040/** SSE access that should report a \#GP instead of \#AC, unless MXCSR.MM=1
5041 * when it works like normal \#AC. Always used with IEM_MEMMAP_F_ALIGN_GP. */
5042#define IEM_MEMMAP_F_ALIGN_SSE RT_BIT_32(17)
5043/** If \#AC is applicable, raise it. Always used with IEM_MEMMAP_F_ALIGN_GP.
5044 * Users include FXSAVE & FXRSTOR. */
5045#define IEM_MEMMAP_F_ALIGN_GP_OR_AC RT_BIT_32(18)
5046
5047VBOXSTRICTRC iemMemMap(PVMCPUCC pVCpu, void **ppvMem, uint8_t *pbUnmapInfo, size_t cbMem, uint8_t iSegReg, RTGCPTR GCPtrMem,
5048 uint32_t fAccess, uint32_t uAlignCtl) RT_NOEXCEPT;
5049VBOXSTRICTRC iemMemCommitAndUnmap(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5050#ifndef IN_RING3
5051VBOXSTRICTRC iemMemCommitAndUnmapPostponeTroubleToR3(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5052#endif
5053void iemMemRollbackAndUnmap(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5054void iemMemRollback(PVMCPUCC pVCpu) RT_NOEXCEPT;
5055VBOXSTRICTRC iemMemApplySegment(PVMCPUCC pVCpu, uint32_t fAccess, uint8_t iSegReg, size_t cbMem, PRTGCPTR pGCPtrMem) RT_NOEXCEPT;
5056VBOXSTRICTRC iemMemMarkSelDescAccessed(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5057VBOXSTRICTRC iemMemPageTranslateAndCheckAccess(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t cbAccess, uint32_t fAccess, PRTGCPHYS pGCPhysMem) RT_NOEXCEPT;
5058
5059void iemOpcodeFlushLight(PVMCPUCC pVCpu, uint8_t cbInstr);
5060void iemOpcodeFlushHeavy(PVMCPUCC pVCpu, uint8_t cbInstr);
5061#ifdef IEM_WITH_CODE_TLB
5062void iemOpcodeFetchBytesJmp(PVMCPUCC pVCpu, size_t cbDst, void *pvDst) IEM_NOEXCEPT_MAY_LONGJMP;
5063#else
5064VBOXSTRICTRC iemOpcodeFetchMoreBytes(PVMCPUCC pVCpu, size_t cbMin) RT_NOEXCEPT;
5065#endif
5066#ifdef IEM_WITH_SETJMP
5067uint8_t iemOpcodeGetNextU8SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5068uint16_t iemOpcodeGetNextU16SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5069uint32_t iemOpcodeGetNextU32SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5070uint64_t iemOpcodeGetNextU64SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5071#else
5072VBOXSTRICTRC iemOpcodeGetNextU8Slow(PVMCPUCC pVCpu, uint8_t *pb) RT_NOEXCEPT;
5073VBOXSTRICTRC iemOpcodeGetNextS8SxU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
5074VBOXSTRICTRC iemOpcodeGetNextS8SxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
5075VBOXSTRICTRC iemOpcodeGetNextS8SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5076VBOXSTRICTRC iemOpcodeGetNextU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
5077VBOXSTRICTRC iemOpcodeGetNextU16ZxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
5078VBOXSTRICTRC iemOpcodeGetNextU16ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5079VBOXSTRICTRC iemOpcodeGetNextU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
5080VBOXSTRICTRC iemOpcodeGetNextU32ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5081VBOXSTRICTRC iemOpcodeGetNextS32SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5082VBOXSTRICTRC iemOpcodeGetNextU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5083#endif
5084
5085VBOXSTRICTRC iemMemFetchDataU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5086VBOXSTRICTRC iemMemFetchDataU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5087VBOXSTRICTRC iemMemFetchDataU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5088VBOXSTRICTRC iemMemFetchDataU32_ZX_U64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5089VBOXSTRICTRC iemMemFetchDataU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5090VBOXSTRICTRC iemMemFetchDataU64AlignedU128(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5091VBOXSTRICTRC iemMemFetchDataR80(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5092VBOXSTRICTRC iemMemFetchDataD80(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5093VBOXSTRICTRC iemMemFetchDataU128(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5094VBOXSTRICTRC iemMemFetchDataU128AlignedSse(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5095VBOXSTRICTRC iemMemFetchDataU256(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5096VBOXSTRICTRC iemMemFetchDataU256AlignedSse(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5097VBOXSTRICTRC iemMemFetchDataXdtr(PVMCPUCC pVCpu, uint16_t *pcbLimit, PRTGCPTR pGCPtrBase, uint8_t iSegReg,
5098 RTGCPTR GCPtrMem, IEMMODE enmOpSize) RT_NOEXCEPT;
5099#ifdef IEM_WITH_SETJMP
5100uint8_t iemMemFetchDataU8SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5101uint16_t iemMemFetchDataU16SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5102uint32_t iemMemFetchDataU32SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5103uint32_t iemMemFlatFetchDataU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5104uint64_t iemMemFetchDataU64SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5105uint64_t iemMemFetchDataU64AlignedU128SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5106void iemMemFetchDataR80SafeJmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5107void iemMemFetchDataD80SafeJmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5108void iemMemFetchDataU128SafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5109void iemMemFetchDataU128AlignedSseSafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5110void iemMemFetchDataU256SafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5111void iemMemFetchDataU256AlignedSseSafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5112# if 0 /* these are inlined now */
5113uint8_t iemMemFetchDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5114uint16_t iemMemFetchDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5115uint32_t iemMemFetchDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5116uint32_t iemMemFlatFetchDataU32Jmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5117uint64_t iemMemFetchDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5118uint64_t iemMemFetchDataU64AlignedU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5119void iemMemFetchDataR80Jmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5120void iemMemFetchDataD80Jmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5121void iemMemFetchDataU128Jmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5122# endif
5123void iemMemFetchDataU128AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5124void iemMemFetchDataU256Jmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5125void iemMemFetchDataU256AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5126#endif
5127
5128VBOXSTRICTRC iemMemFetchSysU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5129VBOXSTRICTRC iemMemFetchSysU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5130VBOXSTRICTRC iemMemFetchSysU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5131VBOXSTRICTRC iemMemFetchSysU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5132VBOXSTRICTRC iemMemFetchSelDesc(PVMCPUCC pVCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt) RT_NOEXCEPT;
5133
5134VBOXSTRICTRC iemMemStoreDataU8(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) RT_NOEXCEPT;
5135VBOXSTRICTRC iemMemStoreDataU16(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) RT_NOEXCEPT;
5136VBOXSTRICTRC iemMemStoreDataU32(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) RT_NOEXCEPT;
5137VBOXSTRICTRC iemMemStoreDataU64(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) RT_NOEXCEPT;
5138VBOXSTRICTRC iemMemStoreDataU128(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
5139VBOXSTRICTRC iemMemStoreDataU128AlignedSse(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
5140VBOXSTRICTRC iemMemStoreDataU256(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
5141VBOXSTRICTRC iemMemStoreDataU256AlignedAvx(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
5142VBOXSTRICTRC iemMemStoreDataXdtr(PVMCPUCC pVCpu, uint16_t cbLimit, RTGCPTR GCPtrBase, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5143#ifdef IEM_WITH_SETJMP
5144void iemMemStoreDataU8SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
5145void iemMemStoreDataU16SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
5146void iemMemStoreDataU32SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
5147void iemMemStoreDataU64SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
5148void iemMemStoreDataU128SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5149void iemMemStoreDataU128AlignedSseSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5150void iemMemStoreDataU256SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5151void iemMemStoreDataU256AlignedAvxSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5152void iemMemStoreDataR80SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTFLOAT80U pr80Value) IEM_NOEXCEPT_MAY_LONGJMP;
5153void iemMemStoreDataD80SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTPBCD80U pd80Value) IEM_NOEXCEPT_MAY_LONGJMP;
5154#if 0
5155void iemMemStoreDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
5156void iemMemStoreDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
5157void iemMemStoreDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
5158void iemMemStoreDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
5159void iemMemStoreDataU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5160#endif
5161void iemMemStoreDataU128AlignedSseJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5162void iemMemStoreDataU256Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5163void iemMemStoreDataU256AlignedAvxJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5164#endif
5165
5166#ifdef IEM_WITH_SETJMP
5167uint8_t *iemMemMapDataU8RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5168uint8_t *iemMemMapDataU8WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5169uint8_t const *iemMemMapDataU8RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5170uint16_t *iemMemMapDataU16RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5171uint16_t *iemMemMapDataU16WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5172uint16_t const *iemMemMapDataU16RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5173uint32_t *iemMemMapDataU32RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5174uint32_t *iemMemMapDataU32WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5175uint32_t const *iemMemMapDataU32RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5176uint64_t *iemMemMapDataU64RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5177uint64_t *iemMemMapDataU64WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5178uint64_t const *iemMemMapDataU64RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5179PRTFLOAT80U iemMemMapDataR80RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5180PRTFLOAT80U iemMemMapDataR80WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5181PCRTFLOAT80U iemMemMapDataR80RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5182PRTPBCD80U iemMemMapDataD80RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5183PRTPBCD80U iemMemMapDataD80WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5184PCRTPBCD80U iemMemMapDataD80RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5185PRTUINT128U iemMemMapDataU128RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5186PRTUINT128U iemMemMapDataU128WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5187PCRTUINT128U iemMemMapDataU128RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5188
5189void iemMemCommitAndUnmapJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5190void iemMemCommitAndUnmapRwSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5191void iemMemCommitAndUnmapWoSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5192void iemMemCommitAndUnmapRoSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5193void iemMemRollbackAndUnmapWoSafe(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5194#endif
5195
5196VBOXSTRICTRC iemMemStackPushBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
5197 void **ppvMem, uint8_t *pbUnmapInfo, uint64_t *puNewRsp) RT_NOEXCEPT;
5198VBOXSTRICTRC iemMemStackPushCommitSpecial(PVMCPUCC pVCpu, uint8_t bUnmapInfo, uint64_t uNewRsp) RT_NOEXCEPT;
5199VBOXSTRICTRC iemMemStackPushU16(PVMCPUCC pVCpu, uint16_t u16Value) RT_NOEXCEPT;
5200VBOXSTRICTRC iemMemStackPushU32(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
5201VBOXSTRICTRC iemMemStackPushU64(PVMCPUCC pVCpu, uint64_t u64Value) RT_NOEXCEPT;
5202VBOXSTRICTRC iemMemStackPushU16Ex(PVMCPUCC pVCpu, uint16_t u16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5203VBOXSTRICTRC iemMemStackPushU32Ex(PVMCPUCC pVCpu, uint32_t u32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5204VBOXSTRICTRC iemMemStackPushU64Ex(PVMCPUCC pVCpu, uint64_t u64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5205VBOXSTRICTRC iemMemStackPushU32SReg(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
5206VBOXSTRICTRC iemMemStackPopBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
5207 void const **ppvMem, uint8_t *pbUnmapInfo, uint64_t *puNewRsp) RT_NOEXCEPT;
5208VBOXSTRICTRC iemMemStackPopContinueSpecial(PVMCPUCC pVCpu, size_t off, size_t cbMem,
5209 void const **ppvMem, uint8_t *pbUnmapInfo, uint64_t uCurNewRsp) RT_NOEXCEPT;
5210VBOXSTRICTRC iemMemStackPopDoneSpecial(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5211VBOXSTRICTRC iemMemStackPopU16(PVMCPUCC pVCpu, uint16_t *pu16Value) RT_NOEXCEPT;
5212VBOXSTRICTRC iemMemStackPopU32(PVMCPUCC pVCpu, uint32_t *pu32Value) RT_NOEXCEPT;
5213VBOXSTRICTRC iemMemStackPopU64(PVMCPUCC pVCpu, uint64_t *pu64Value) RT_NOEXCEPT;
5214VBOXSTRICTRC iemMemStackPopU16Ex(PVMCPUCC pVCpu, uint16_t *pu16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5215VBOXSTRICTRC iemMemStackPopU32Ex(PVMCPUCC pVCpu, uint32_t *pu32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5216VBOXSTRICTRC iemMemStackPopU64Ex(PVMCPUCC pVCpu, uint64_t *pu64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5217
5218#ifdef IEM_WITH_SETJMP
5219void iemMemStackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5220void iemMemStackPushU32SafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5221void iemMemStackPushU32SRegSafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5222void iemMemStackPushU64SafeJmp(PVMCPUCC pVCpu, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5223uint16_t iemMemStackPopU16SafeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5224uint32_t iemMemStackPopU32SafeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5225uint64_t iemMemStackPopU64SafeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5226
5227void iemMemFlat32StackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5228void iemMemFlat32StackPushU32SafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5229void iemMemFlat32StackPushU32SRegSafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5230uint16_t iemMemFlat32StackPopU16SafeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5231uint32_t iemMemFlat32StackPopU32SafeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5232
5233void iemMemFlat64StackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5234void iemMemFlat64StackPushU64SafeJmp(PVMCPUCC pVCpu, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5235uint16_t iemMemFlat64StackPopU16SafeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5236uint64_t iemMemFlat64StackPopU64SafeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5237#endif
5238
5239/** @} */
5240
5241/** @name IEMAllCImpl.cpp
5242 * @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/'
5243 * @{ */
5244IEM_CIMPL_PROTO_2(iemCImpl_pop_mem16, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5245IEM_CIMPL_PROTO_2(iemCImpl_pop_mem32, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5246IEM_CIMPL_PROTO_2(iemCImpl_pop_mem64, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5247IEM_CIMPL_PROTO_0(iemCImpl_popa_16);
5248IEM_CIMPL_PROTO_0(iemCImpl_popa_32);
5249IEM_CIMPL_PROTO_0(iemCImpl_pusha_16);
5250IEM_CIMPL_PROTO_0(iemCImpl_pusha_32);
5251IEM_CIMPL_PROTO_1(iemCImpl_pushf, IEMMODE, enmEffOpSize);
5252IEM_CIMPL_PROTO_1(iemCImpl_popf, IEMMODE, enmEffOpSize);
5253IEM_CIMPL_PROTO_1(iemCImpl_call_16, uint16_t, uNewPC);
5254IEM_CIMPL_PROTO_1(iemCImpl_call_rel_16, int16_t, offDisp);
5255IEM_CIMPL_PROTO_1(iemCImpl_call_32, uint32_t, uNewPC);
5256IEM_CIMPL_PROTO_1(iemCImpl_call_rel_32, int32_t, offDisp);
5257IEM_CIMPL_PROTO_1(iemCImpl_call_64, uint64_t, uNewPC);
5258IEM_CIMPL_PROTO_1(iemCImpl_call_rel_64, int64_t, offDisp);
5259IEM_CIMPL_PROTO_3(iemCImpl_FarJmp, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
5260IEM_CIMPL_PROTO_3(iemCImpl_callf, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
5261typedef IEM_CIMPL_DECL_TYPE_3(FNIEMCIMPLFARBRANCH, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
5262typedef FNIEMCIMPLFARBRANCH *PFNIEMCIMPLFARBRANCH;
5263IEM_CIMPL_PROTO_2(iemCImpl_retf, IEMMODE, enmEffOpSize, uint16_t, cbPop);
5264IEM_CIMPL_PROTO_0(iemCImpl_retn_16);
5265IEM_CIMPL_PROTO_0(iemCImpl_retn_32);
5266IEM_CIMPL_PROTO_0(iemCImpl_retn_64);
5267IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_16, uint16_t, cbPop);
5268IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_32, uint16_t, cbPop);
5269IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_64, uint16_t, cbPop);
5270IEM_CIMPL_PROTO_3(iemCImpl_enter, IEMMODE, enmEffOpSize, uint16_t, cbFrame, uint8_t, cParameters);
5271IEM_CIMPL_PROTO_1(iemCImpl_leave, IEMMODE, enmEffOpSize);
5272IEM_CIMPL_PROTO_2(iemCImpl_int, uint8_t, u8Int, IEMINT, enmInt);
5273IEM_CIMPL_PROTO_1(iemCImpl_iret_real_v8086, IEMMODE, enmEffOpSize);
5274IEM_CIMPL_PROTO_4(iemCImpl_iret_prot_v8086, uint32_t, uNewEip, uint16_t, uNewCs, uint32_t, uNewFlags, uint64_t, uNewRsp);
5275IEM_CIMPL_PROTO_1(iemCImpl_iret_prot_NestedTask, IEMMODE, enmEffOpSize);
5276IEM_CIMPL_PROTO_1(iemCImpl_iret_prot, IEMMODE, enmEffOpSize);
5277IEM_CIMPL_PROTO_1(iemCImpl_iret_64bit, IEMMODE, enmEffOpSize);
5278IEM_CIMPL_PROTO_1(iemCImpl_iret, IEMMODE, enmEffOpSize);
5279IEM_CIMPL_PROTO_0(iemCImpl_loadall286);
5280IEM_CIMPL_PROTO_0(iemCImpl_syscall);
5281IEM_CIMPL_PROTO_1(iemCImpl_sysret, IEMMODE, enmEffOpSize);
5282IEM_CIMPL_PROTO_0(iemCImpl_sysenter);
5283IEM_CIMPL_PROTO_1(iemCImpl_sysexit, IEMMODE, enmEffOpSize);
5284IEM_CIMPL_PROTO_2(iemCImpl_LoadSReg, uint8_t, iSegReg, uint16_t, uSel);
5285IEM_CIMPL_PROTO_2(iemCImpl_load_SReg, uint8_t, iSegReg, uint16_t, uSel);
5286IEM_CIMPL_PROTO_2(iemCImpl_pop_Sreg, uint8_t, iSegReg, IEMMODE, enmEffOpSize);
5287IEM_CIMPL_PROTO_5(iemCImpl_load_SReg_Greg, uint16_t, uSel, uint64_t, offSeg, uint8_t, iSegReg, uint8_t, iGReg, IEMMODE, enmEffOpSize);
5288IEM_CIMPL_PROTO_2(iemCImpl_VerX, uint16_t, uSel, bool, fWrite);
5289IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u64, uint64_t *, pu64Dst, uint16_t, uSel, bool, fIsLar);
5290IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u16, uint16_t *, pu16Dst, uint16_t, uSel, bool, fIsLar);
5291IEM_CIMPL_PROTO_3(iemCImpl_lgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
5292IEM_CIMPL_PROTO_2(iemCImpl_sgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5293IEM_CIMPL_PROTO_3(iemCImpl_lidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
5294IEM_CIMPL_PROTO_2(iemCImpl_sidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5295IEM_CIMPL_PROTO_1(iemCImpl_lldt, uint16_t, uNewLdt);
5296IEM_CIMPL_PROTO_2(iemCImpl_sldt_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
5297IEM_CIMPL_PROTO_2(iemCImpl_sldt_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5298IEM_CIMPL_PROTO_1(iemCImpl_ltr, uint16_t, uNewTr);
5299IEM_CIMPL_PROTO_2(iemCImpl_str_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
5300IEM_CIMPL_PROTO_2(iemCImpl_str_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5301IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Cd, uint8_t, iGReg, uint8_t, iCrReg);
5302IEM_CIMPL_PROTO_2(iemCImpl_smsw_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
5303IEM_CIMPL_PROTO_2(iemCImpl_smsw_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5304IEM_CIMPL_PROTO_4(iemCImpl_load_CrX, uint8_t, iCrReg, uint64_t, uNewCrX, IEMACCESSCRX, enmAccessCrX, uint8_t, iGReg);
5305IEM_CIMPL_PROTO_2(iemCImpl_mov_Cd_Rd, uint8_t, iCrReg, uint8_t, iGReg);
5306IEM_CIMPL_PROTO_2(iemCImpl_lmsw, uint16_t, u16NewMsw, RTGCPTR, GCPtrEffDst);
5307IEM_CIMPL_PROTO_0(iemCImpl_clts);
5308IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Dd, uint8_t, iGReg, uint8_t, iDrReg);
5309IEM_CIMPL_PROTO_2(iemCImpl_mov_Dd_Rd, uint8_t, iDrReg, uint8_t, iGReg);
5310IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Td, uint8_t, iGReg, uint8_t, iTrReg);
5311IEM_CIMPL_PROTO_2(iemCImpl_mov_Td_Rd, uint8_t, iTrReg, uint8_t, iGReg);
5312IEM_CIMPL_PROTO_1(iemCImpl_invlpg, RTGCPTR, GCPtrPage);
5313IEM_CIMPL_PROTO_3(iemCImpl_invpcid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvpcidDesc, uint64_t, uInvpcidType);
5314IEM_CIMPL_PROTO_0(iemCImpl_invd);
5315IEM_CIMPL_PROTO_0(iemCImpl_wbinvd);
5316IEM_CIMPL_PROTO_0(iemCImpl_rsm);
5317IEM_CIMPL_PROTO_0(iemCImpl_rdtsc);
5318IEM_CIMPL_PROTO_0(iemCImpl_rdtscp);
5319IEM_CIMPL_PROTO_0(iemCImpl_rdpmc);
5320IEM_CIMPL_PROTO_0(iemCImpl_rdmsr);
5321IEM_CIMPL_PROTO_0(iemCImpl_wrmsr);
5322IEM_CIMPL_PROTO_3(iemCImpl_in, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
5323IEM_CIMPL_PROTO_2(iemCImpl_in_eAX_DX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
5324IEM_CIMPL_PROTO_3(iemCImpl_out, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
5325IEM_CIMPL_PROTO_2(iemCImpl_out_DX_eAX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
5326IEM_CIMPL_PROTO_0(iemCImpl_cli);
5327IEM_CIMPL_PROTO_0(iemCImpl_sti);
5328IEM_CIMPL_PROTO_0(iemCImpl_hlt);
5329IEM_CIMPL_PROTO_1(iemCImpl_monitor, uint8_t, iEffSeg);
5330IEM_CIMPL_PROTO_0(iemCImpl_mwait);
5331IEM_CIMPL_PROTO_0(iemCImpl_swapgs);
5332IEM_CIMPL_PROTO_0(iemCImpl_cpuid);
5333IEM_CIMPL_PROTO_1(iemCImpl_aad, uint8_t, bImm);
5334IEM_CIMPL_PROTO_1(iemCImpl_aam, uint8_t, bImm);
5335IEM_CIMPL_PROTO_0(iemCImpl_daa);
5336IEM_CIMPL_PROTO_0(iemCImpl_das);
5337IEM_CIMPL_PROTO_0(iemCImpl_aaa);
5338IEM_CIMPL_PROTO_0(iemCImpl_aas);
5339IEM_CIMPL_PROTO_3(iemCImpl_bound_16, int16_t, idxArray, int16_t, idxLowerBound, int16_t, idxUpperBound);
5340IEM_CIMPL_PROTO_3(iemCImpl_bound_32, int32_t, idxArray, int32_t, idxLowerBound, int32_t, idxUpperBound);
5341IEM_CIMPL_PROTO_0(iemCImpl_xgetbv);
5342IEM_CIMPL_PROTO_0(iemCImpl_xsetbv);
5343IEM_CIMPL_PROTO_5(iemCImpl_cmpxchg16b_fallback_rendezvous, PRTUINT128U, pu128Dst, PRTUINT128U, pu128RaxRdx,
5344 PRTUINT128U, pu128RbxRcx, uint32_t *, pEFlags, uint8_t, bUnmapInfo);
5345IEM_CIMPL_PROTO_2(iemCImpl_clflush_clflushopt, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5346IEM_CIMPL_PROTO_1(iemCImpl_finit, bool, fCheckXcpts);
5347IEM_CIMPL_PROTO_3(iemCImpl_fxsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5348IEM_CIMPL_PROTO_3(iemCImpl_fxrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5349IEM_CIMPL_PROTO_3(iemCImpl_xsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5350IEM_CIMPL_PROTO_3(iemCImpl_xrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5351IEM_CIMPL_PROTO_2(iemCImpl_stmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5352IEM_CIMPL_PROTO_2(iemCImpl_vstmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5353IEM_CIMPL_PROTO_2(iemCImpl_ldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5354IEM_CIMPL_PROTO_3(iemCImpl_fnstenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5355IEM_CIMPL_PROTO_3(iemCImpl_fnsave, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5356IEM_CIMPL_PROTO_3(iemCImpl_fldenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
5357IEM_CIMPL_PROTO_3(iemCImpl_frstor, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
5358IEM_CIMPL_PROTO_1(iemCImpl_fldcw, uint16_t, u16Fcw);
5359IEM_CIMPL_PROTO_2(iemCImpl_fxch_underflow, uint8_t, iStReg, uint16_t, uFpuOpcode);
5360IEM_CIMPL_PROTO_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, bool, fUCmp, uint32_t, uPopAndFpuOpcode);
5361IEM_CIMPL_PROTO_2(iemCImpl_rdseed, uint8_t, iReg, IEMMODE, enmEffOpSize);
5362IEM_CIMPL_PROTO_2(iemCImpl_rdrand, uint8_t, iReg, IEMMODE, enmEffOpSize);
5363/** @} */
5364
5365/** @name IEMAllCImplStrInstr.cpp.h
5366 * @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/' -e 's/RT_CONCAT4(//' \
5367 * -e 's/,ADDR_SIZE)/64/g' -e 's/,OP_SIZE,/64/g' -e 's/,OP_rAX,/rax/g' IEMAllCImplStrInstr.cpp.h
5368 * @{ */
5369IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr16, uint8_t, iEffSeg);
5370IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr16, uint8_t, iEffSeg);
5371IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m16);
5372IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m16);
5373IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr16, uint8_t, iEffSeg);
5374IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m16);
5375IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m16, int8_t, iEffSeg);
5376IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr16, bool, fIoChecked);
5377IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr16, bool, fIoChecked);
5378IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5379IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5380
5381IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr16, uint8_t, iEffSeg);
5382IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr16, uint8_t, iEffSeg);
5383IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m16);
5384IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m16);
5385IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr16, uint8_t, iEffSeg);
5386IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m16);
5387IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m16, int8_t, iEffSeg);
5388IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr16, bool, fIoChecked);
5389IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr16, bool, fIoChecked);
5390IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5391IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5392
5393IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr16, uint8_t, iEffSeg);
5394IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr16, uint8_t, iEffSeg);
5395IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m16);
5396IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m16);
5397IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr16, uint8_t, iEffSeg);
5398IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m16);
5399IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m16, int8_t, iEffSeg);
5400IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr16, bool, fIoChecked);
5401IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr16, bool, fIoChecked);
5402IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5403IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5404
5405
5406IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr32, uint8_t, iEffSeg);
5407IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr32, uint8_t, iEffSeg);
5408IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m32);
5409IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m32);
5410IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr32, uint8_t, iEffSeg);
5411IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m32);
5412IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m32, int8_t, iEffSeg);
5413IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr32, bool, fIoChecked);
5414IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr32, bool, fIoChecked);
5415IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5416IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5417
5418IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr32, uint8_t, iEffSeg);
5419IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr32, uint8_t, iEffSeg);
5420IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m32);
5421IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m32);
5422IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr32, uint8_t, iEffSeg);
5423IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m32);
5424IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m32, int8_t, iEffSeg);
5425IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr32, bool, fIoChecked);
5426IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr32, bool, fIoChecked);
5427IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5428IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5429
5430IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr32, uint8_t, iEffSeg);
5431IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr32, uint8_t, iEffSeg);
5432IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m32);
5433IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m32);
5434IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr32, uint8_t, iEffSeg);
5435IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m32);
5436IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m32, int8_t, iEffSeg);
5437IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr32, bool, fIoChecked);
5438IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr32, bool, fIoChecked);
5439IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5440IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5441
5442IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr32, uint8_t, iEffSeg);
5443IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr32, uint8_t, iEffSeg);
5444IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m32);
5445IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m32);
5446IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr32, uint8_t, iEffSeg);
5447IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m32);
5448IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m32, int8_t, iEffSeg);
5449IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr32, bool, fIoChecked);
5450IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr32, bool, fIoChecked);
5451IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5452IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5453
5454
5455IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr64, uint8_t, iEffSeg);
5456IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr64, uint8_t, iEffSeg);
5457IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m64);
5458IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m64);
5459IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr64, uint8_t, iEffSeg);
5460IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m64);
5461IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m64, int8_t, iEffSeg);
5462IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr64, bool, fIoChecked);
5463IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr64, bool, fIoChecked);
5464IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5465IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5466
5467IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr64, uint8_t, iEffSeg);
5468IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr64, uint8_t, iEffSeg);
5469IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m64);
5470IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m64);
5471IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr64, uint8_t, iEffSeg);
5472IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m64);
5473IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m64, int8_t, iEffSeg);
5474IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr64, bool, fIoChecked);
5475IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr64, bool, fIoChecked);
5476IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5477IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5478
5479IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr64, uint8_t, iEffSeg);
5480IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr64, uint8_t, iEffSeg);
5481IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m64);
5482IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m64);
5483IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr64, uint8_t, iEffSeg);
5484IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m64);
5485IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m64, int8_t, iEffSeg);
5486IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr64, bool, fIoChecked);
5487IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr64, bool, fIoChecked);
5488IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5489IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5490
5491IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr64, uint8_t, iEffSeg);
5492IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr64, uint8_t, iEffSeg);
5493IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m64);
5494IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m64);
5495IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr64, uint8_t, iEffSeg);
5496IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m64);
5497IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m64, int8_t, iEffSeg);
5498IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr64, bool, fIoChecked);
5499IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr64, bool, fIoChecked);
5500IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5501IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5502/** @} */
5503
5504#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5505VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT;
5506VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT;
5507VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT;
5508VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT;
5509VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT;
5510VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
5511VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALK pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT;
5512VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT;
5513VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT;
5514VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
5515 bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT;
5516VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
5517 bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT;
5518VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5519VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5520VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5521VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5522VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5523VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5524VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT;
5525VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
5526 RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT;
5527VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT;
5528VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT;
5529VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT;
5530uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT;
5531void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT;
5532VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
5533 uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT;
5534bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT;
5535IEM_CIMPL_PROTO_0(iemCImpl_vmxoff);
5536IEM_CIMPL_PROTO_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon);
5537IEM_CIMPL_PROTO_0(iemCImpl_vmlaunch);
5538IEM_CIMPL_PROTO_0(iemCImpl_vmresume);
5539IEM_CIMPL_PROTO_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
5540IEM_CIMPL_PROTO_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
5541IEM_CIMPL_PROTO_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
5542IEM_CIMPL_PROTO_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField);
5543IEM_CIMPL_PROTO_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField);
5544IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField);
5545IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg32, uint64_t *, pu32Dst, uint32_t, u32VmcsField);
5546IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField);
5547IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField);
5548IEM_CIMPL_PROTO_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType);
5549IEM_CIMPL_PROTO_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType);
5550IEM_CIMPL_PROTO_0(iemCImpl_vmx_pause);
5551#endif
5552
5553#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5554VBOXSTRICTRC iemSvmVmexit(PVMCPUCC pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2) RT_NOEXCEPT;
5555VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr, uint64_t uCr2) RT_NOEXCEPT;
5556VBOXSTRICTRC iemSvmHandleIOIntercept(PVMCPUCC pVCpu, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
5557 uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, uint8_t cbInstr) RT_NOEXCEPT;
5558VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPUCC pVCpu, uint32_t idMsr, bool fWrite, uint8_t cbInstr) RT_NOEXCEPT;
5559IEM_CIMPL_PROTO_0(iemCImpl_vmrun);
5560IEM_CIMPL_PROTO_0(iemCImpl_vmload);
5561IEM_CIMPL_PROTO_0(iemCImpl_vmsave);
5562IEM_CIMPL_PROTO_0(iemCImpl_clgi);
5563IEM_CIMPL_PROTO_0(iemCImpl_stgi);
5564IEM_CIMPL_PROTO_0(iemCImpl_invlpga);
5565IEM_CIMPL_PROTO_0(iemCImpl_skinit);
5566IEM_CIMPL_PROTO_0(iemCImpl_svm_pause);
5567#endif
5568
5569IEM_CIMPL_PROTO_0(iemCImpl_vmcall); /* vmx */
5570IEM_CIMPL_PROTO_0(iemCImpl_vmmcall); /* svm */
5571IEM_CIMPL_PROTO_1(iemCImpl_Hypercall, uint16_t, uDisOpcode); /* both */
5572
5573extern const PFNIEMOP g_apfnIemInterpretOnlyOneByteMap[256];
5574extern const PFNIEMOP g_apfnIemInterpretOnlyTwoByteMap[1024];
5575extern const PFNIEMOP g_apfnIemInterpretOnlyThreeByte0f3a[1024];
5576extern const PFNIEMOP g_apfnIemInterpretOnlyThreeByte0f38[1024];
5577extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap1[1024];
5578extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap2[1024];
5579extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap3[1024];
5580
5581/*
5582 * Recompiler related stuff.
5583 */
5584extern const PFNIEMOP g_apfnIemThreadedRecompilerOneByteMap[256];
5585extern const PFNIEMOP g_apfnIemThreadedRecompilerTwoByteMap[1024];
5586extern const PFNIEMOP g_apfnIemThreadedRecompilerThreeByte0f3a[1024];
5587extern const PFNIEMOP g_apfnIemThreadedRecompilerThreeByte0f38[1024];
5588extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap1[1024];
5589extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap2[1024];
5590extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap3[1024];
5591
5592DECLCALLBACK(int) iemTbInit(PVMCC pVM, uint32_t cInitialTbs, uint32_t cMaxTbs,
5593 uint64_t cbInitialExec, uint64_t cbMaxExec, uint32_t cbChunkExec);
5594void iemThreadedTbObsolete(PVMCPUCC pVCpu, PIEMTB pTb, bool fSafeToFree);
5595void iemTbAllocatorProcessDelayedFrees(PVMCPUCC pVCpu, PIEMTBALLOCATOR pTbAllocator);
5596void iemTbAllocatorFreeupNativeSpace(PVMCPUCC pVCpu, uint32_t cNeededInstrs);
5597
5598
5599/** @todo FNIEMTHREADEDFUNC and friends may need more work... */
5600#if defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
5601typedef VBOXSTRICTRC /*__attribute__((__nothrow__))*/ FNIEMTHREADEDFUNC(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
5602typedef FNIEMTHREADEDFUNC *PFNIEMTHREADEDFUNC;
5603# define IEM_DECL_IEMTHREADEDFUNC_DEF(a_Name) \
5604 VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2)
5605# define IEM_DECL_IEMTHREADEDFUNC_PROTO(a_Name) \
5606 VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2)
5607
5608#else
5609typedef VBOXSTRICTRC (FNIEMTHREADEDFUNC)(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
5610typedef FNIEMTHREADEDFUNC *PFNIEMTHREADEDFUNC;
5611# define IEM_DECL_IEMTHREADEDFUNC_DEF(a_Name) \
5612 VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2) IEM_NOEXCEPT_MAY_LONGJMP
5613# define IEM_DECL_IEMTHREADEDFUNC_PROTO(a_Name) \
5614 VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2) IEM_NOEXCEPT_MAY_LONGJMP
5615#endif
5616
5617
5618IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_DeferToCImpl0);
5619
5620IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckIrq);
5621IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckMode);
5622IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckHwInstrBps);
5623IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLim);
5624
5625IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodes);
5626IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodes);
5627IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesConsiderCsLim);
5628
5629/* Branching: */
5630IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndPcAndOpcodes);
5631IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckPcAndOpcodes);
5632IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckPcAndOpcodesConsiderCsLim);
5633
5634IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesLoadingTlb);
5635IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesLoadingTlb);
5636IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesLoadingTlbConsiderCsLim);
5637
5638/* Natural page crossing: */
5639IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesAcrossPageLoadingTlb);
5640IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesAcrossPageLoadingTlb);
5641IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesAcrossPageLoadingTlbConsiderCsLim);
5642
5643IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesOnNextPageLoadingTlb);
5644IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNextPageLoadingTlb);
5645IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNextPageLoadingTlbConsiderCsLim);
5646
5647IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesOnNewPageLoadingTlb);
5648IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNewPageLoadingTlb);
5649IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNewPageLoadingTlbConsiderCsLim);
5650
5651bool iemThreadedCompileEmitIrqCheckBefore(PVMCPUCC pVCpu, PIEMTB pTb);
5652bool iemThreadedCompileBeginEmitCallsComplications(PVMCPUCC pVCpu, PIEMTB pTb);
5653
5654/* Native recompiler public bits: */
5655DECLHIDDEN(PIEMTB) iemNativeRecompile(PVMCPUCC pVCpu, PIEMTB pTb) RT_NOEXCEPT;
5656DECLHIDDEN(void) iemNativeDisassembleTb(PCIEMTB pTb, PCDBGFINFOHLP pHlp) RT_NOEXCEPT;
5657int iemExecMemAllocatorInit(PVMCPU pVCpu, uint64_t cbMax, uint64_t cbInitial, uint32_t cbChunk);
5658void iemExecMemAllocatorFree(PVMCPU pVCpu, void *pv, size_t cb);
5659
5660
5661/** @} */
5662
5663RT_C_DECLS_END
5664
5665#endif /* !VMM_INCLUDED_SRC_include_IEMInternal_h */
5666
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