IEMInternal.h@ 103956

Last change on this file since 103956 was 103955, checked in by vboxsync, 13 months ago
VMM/IEM,DIS: Another mnemonic todo in vex map 3. bugref:9898
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1	/* $Id: IEMInternal.h 103955 2024-03-20 13:09:35Z vboxsync $ */
2	/** @file
3	* IEM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2011-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_IEMInternal_h
29	#define VMM_INCLUDED_SRC_include_IEMInternal_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#include <VBox/vmm/cpum.h>
35	#include <VBox/vmm/iem.h>
36	#include <VBox/vmm/pgm.h>
37	#include <VBox/vmm/stam.h>
38	#include <VBox/param.h>
39
40	#include <iprt/setjmp-without-sigmask.h>
41	#include <iprt/list.h>
42
43
44	RT_C_DECLS_BEGIN
45
46
47	/** @defgroup grp_iem_int Internals
48	* @ingroup grp_iem
49	* @internal
50	* @{
51	*/
52
53	/** For expanding symbol in slickedit and other products tagging and
54	* crossreferencing IEM symbols. */
55	#ifndef IEM_STATIC
56	# define IEM_STATIC static
57	#endif
58
59	/** @def IEM_WITH_SETJMP
60	* Enables alternative status code handling using setjmps.
61	*
62	* This adds a bit of expense via the setjmp() call since it saves all the
63	* non-volatile registers. However, it eliminates return code checks and allows
64	* for more optimal return value passing (return regs instead of stack buffer).
65	*/
66	#if defined(DOXYGEN_RUNNING) \|\| defined(RT_OS_WINDOWS) \|\| 1
67	# define IEM_WITH_SETJMP
68	#endif
69
70	/** @def IEM_WITH_THROW_CATCH
71	* Enables using C++ throw/catch as an alternative to setjmp/longjmp in user
72	* mode code when IEM_WITH_SETJMP is in effect.
73	*
74	* With GCC 11.3.1 and code TLB on linux, using throw/catch instead of
75	* setjmp/long resulted in bs2-test-1 running 3.00% faster and all but on test
76	* result value improving by more than 1%. (Best out of three.)
77	*
78	* With Visual C++ 2019 and code TLB on windows, using throw/catch instead of
79	* setjmp/long resulted in bs2-test-1 running 3.68% faster and all but some of
80	* the MMIO and CPUID tests ran noticeably faster. Variation is greater than on
81	* Linux, but it should be quite a bit faster for normal code.
82	*/
83	#if (defined(__cplusplus) && defined(IEM_WITH_SETJMP) && defined(IN_RING3) && (defined(__GNUC__) \|\| defined(_MSC_VER))) \
84	\|\| defined(DOXYGEN_RUNNING)
85	# define IEM_WITH_THROW_CATCH
86	#endif
87
88	/** @def IEMNATIVE_WITH_DELAYED_PC_UPDATING
89	* Enables the delayed PC updating optimization (see @bugref{10373}).
90	*/
91	#if defined(DOXYGEN_RUNNING) \|\| 1
92	# define IEMNATIVE_WITH_DELAYED_PC_UPDATING
93	#endif
94
95	/** Enables the SIMD register allocator @bugref{10614}. */
96	#if defined(DOXYGEN_RUNNING) \|\| 1
97	# define IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
98	#endif
99	/** Enables access to even callee saved registers. */
100	//# define IEMNATIVE_WITH_SIMD_REG_ACCESS_ALL_REGISTERS
101
102	/** @def VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
103	* Enables a quicker alternative to throw/longjmp for IEM_DO_LONGJMP when
104	* executing native translation blocks.
105	*
106	* This exploits the fact that we save all non-volatile registers in the TB
107	* prologue and thus just need to do the same as the TB epilogue to get the
108	* effect of a longjmp/throw. Since MSC marks XMM6 thru XMM15 as
109	* non-volatile (and does something even more crazy for ARM), this probably
110	* won't work reliably on Windows. */
111	#if defined(DOXYGEN_RUNNING) \|\| (!defined(RT_OS_WINDOWS) && (defined(RT_ARCH_ARM64) /\|\| defined(_RT_ARCH_AMD64)/))
112	# define VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
113	#endif
114	#ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
115	# if !defined(IN_RING3) \
116	\|\| !defined(VBOX_WITH_IEM_RECOMPILER) \
117	\|\| !defined(VBOX_WITH_IEM_NATIVE_RECOMPILER)
118	# undef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
119	# elif defined(RT_OS_WINDOWS)
120	# pragma message("VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP is not safe to use on windows")
121	# endif
122	#endif
123
124
125	/** @def IEM_DO_LONGJMP
126	*
127	* Wrapper around longjmp / throw.
128	*
129	* @param a_pVCpu The CPU handle.
130	* @param a_rc The status code jump back with / throw.
131	*/
132	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
133	# ifdef IEM_WITH_THROW_CATCH
134	# ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
135	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) do { \
136	if ((a_pVCpu)->iem.s.pvTbFramePointerR3) \
137	iemNativeTbLongJmp((a_pVCpu)->iem.s.pvTbFramePointerR3, (a_rc)); \
138	throw int(a_rc); \
139	} while (0)
140	# else
141	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) throw int(a_rc)
142	# endif
143	# else
144	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) longjmp(*(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf), (a_rc))
145	# endif
146	#endif
147
148	/** For use with IEM function that may do a longjmp (when enabled).
149	*
150	* Visual C++ has trouble longjmp'ing from/over functions with the noexcept
151	* attribute. So, we indicate that function that may be part of a longjmp may
152	* throw "exceptions" and that the compiler should definitely not generate and
153	* std::terminate calling unwind code.
154	*
155	* Here is one example of this ending in std::terminate:
156	* @code{.txt}
157	00 00000041`cadfda10 00007ffc`5d5a1f9f ucrtbase!abort+0x4e
158	01 00000041`cadfda40 00007ffc`57af229a ucrtbase!terminate+0x1f
159	02 00000041`cadfda70 00007ffb`eec91030 VCRUNTIME140!__std_terminate+0xa [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\ehhelpers.cpp @ 192]
160	03 00000041`cadfdaa0 00007ffb`eec92c6d VCRUNTIME140_1!_CallSettingFrame+0x20 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\handlers.asm @ 50]
161	04 00000041`cadfdad0 00007ffb`eec93ae5 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToState+0x241 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 1085]
162	05 00000041`cadfdc00 00007ffb`eec92258 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToEmptyState+0x2d [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 218]
163	06 00000041`cadfdc30 00007ffb`eec940e9 VCRUNTIME140_1!__InternalCxxFrameHandler<__FrameHandler4>+0x194 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 304]
164	07 00000041`cadfdcd0 00007ffc`5f9f249f VCRUNTIME140_1!__CxxFrameHandler4+0xa9 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 290]
165	08 00000041`cadfdd40 00007ffc`5f980939 ntdll!RtlpExecuteHandlerForUnwind+0xf
166	09 00000041`cadfdd70 00007ffc`5f9a0edd ntdll!RtlUnwindEx+0x339
167	0a 00000041`cadfe490 00007ffc`57aff976 ntdll!RtlUnwind+0xcd
168	0b 00000041`cadfea00 00007ffb`e1b5de01 VCRUNTIME140!__longjmp_internal+0xe6 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\longjmp.asm @ 140]
169	0c (Inline Function) --------`-------- VBoxVMM!iemOpcodeGetNextU8SlowJmp+0x95 [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 1155]
170	0d 00000041`cadfea50 00007ffb`e1b60f6b VBoxVMM!iemOpcodeGetNextU8Jmp+0xc1 [L:\vbox-intern\src\VBox\VMM\include\IEMInline.h @ 402]
171	0e 00000041`cadfea90 00007ffb`e1cc6201 VBoxVMM!IEMExecForExits+0xdb [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 10185]
172	0f 00000041`cadfec70 00007ffb`e1d0df8d VBoxVMM!EMHistoryExec+0x4f1 [L:\vbox-intern\src\VBox\VMM\VMMAll\EMAll.cpp @ 452]
173	10 00000041`cadfed60 00007ffb`e1d0d4c0 VBoxVMM!nemR3WinHandleExitCpuId+0x79d [L:\vbox-intern\src\VBox\VMM\VMMAll\NEMAllNativeTemplate-win.cpp.h @ 1829] @encode
174	@endcode
175	*
176	* @see https://developercommunity.visualstudio.com/t/fragile-behavior-of-longjmp-called-from-noexcept-f/1532859
177	*/
178	#if defined(IEM_WITH_SETJMP) && (defined(_MSC_VER) \|\| defined(IEM_WITH_THROW_CATCH))
179	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT_EX(false)
180	#else
181	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT
182	#endif
183
184	#define IEM_IMPLEMENTS_TASKSWITCH
185
186	/** @def IEM_WITH_3DNOW
187	* Includes the 3DNow decoding. */
188	#if (!defined(IEM_WITH_3DNOW) && !defined(IEM_WITHOUT_3DNOW)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
189	# define IEM_WITH_3DNOW
190	#endif
191
192	/** @def IEM_WITH_THREE_0F_38
193	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
194	#if (!defined(IEM_WITH_THREE_0F_38) && !defined(IEM_WITHOUT_THREE_0F_38)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
195	# define IEM_WITH_THREE_0F_38
196	#endif
197
198	/** @def IEM_WITH_THREE_0F_3A
199	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
200	#if (!defined(IEM_WITH_THREE_0F_3A) && !defined(IEM_WITHOUT_THREE_0F_3A)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
201	# define IEM_WITH_THREE_0F_3A
202	#endif
203
204	/** @def IEM_WITH_VEX
205	* Includes the VEX decoding. */
206	#if (!defined(IEM_WITH_VEX) && !defined(IEM_WITHOUT_VEX)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
207	# define IEM_WITH_VEX
208	#endif
209
210	/** @def IEM_CFG_TARGET_CPU
211	* The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
212	*
213	* By default we allow this to be configured by the user via the
214	* CPUM/GuestCpuName config string, but this comes at a slight cost during
215	* decoding. So, for applications of this code where there is no need to
216	* be dynamic wrt target CPU, just modify this define.
217	*/
218	#if !defined(IEM_CFG_TARGET_CPU) \|\| defined(DOXYGEN_RUNNING)
219	# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
220	#endif
221
222	//#define IEM_WITH_CODE_TLB // - work in progress
223	//#define IEM_WITH_DATA_TLB // - work in progress
224
225
226	/** @def IEM_USE_UNALIGNED_DATA_ACCESS
227	* Use unaligned accesses instead of elaborate byte assembly. */
228	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86) \|\| defined(DOXYGEN_RUNNING)
229	# define IEM_USE_UNALIGNED_DATA_ACCESS
230	#endif
231
232	//#define IEM_LOG_MEMORY_WRITES
233
234	#if !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
235	/** Instruction statistics. */
236	typedef struct IEMINSTRSTATS
237	{
238	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
239	# include "IEMInstructionStatisticsTmpl.h"
240	# undef IEM_DO_INSTR_STAT
241	} IEMINSTRSTATS;
242	#else
243	struct IEMINSTRSTATS;
244	typedef struct IEMINSTRSTATS IEMINSTRSTATS;
245	#endif
246	/** Pointer to IEM instruction statistics. */
247	typedef IEMINSTRSTATS *PIEMINSTRSTATS;
248
249
250	/** @name IEMTARGETCPU_EFL_BEHAVIOR_XXX - IEMCPU::aidxTargetCpuEflFlavour
251	* @{ */
252	#define IEMTARGETCPU_EFL_BEHAVIOR_NATIVE 0 /*< Native x86 EFLAGS result; Intel EFLAGS when on non-x86 hosts. /
253	#define IEMTARGETCPU_EFL_BEHAVIOR_INTEL 1 /*< Intel EFLAGS result. /
254	#define IEMTARGETCPU_EFL_BEHAVIOR_AMD 2 /*< AMD EFLAGS result /
255	#define IEMTARGETCPU_EFL_BEHAVIOR_RESERVED 3 /*< Reserved/dummy entry slot that's the same as 0. /
256	#define IEMTARGETCPU_EFL_BEHAVIOR_MASK 3 /*< For masking the index before use. /
257	/** Selects the right variant from a_aArray.
258	* pVCpu is implicit in the caller context. */
259	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT(a_aArray) \
260	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[1] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
261	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for when no native worker can
262	* be used because the host CPU does not support the operation. */
263	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_NON_NATIVE(a_aArray) \
264	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
265	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for a two dimentional
266	* array paralleling IEMCPU::aidxTargetCpuEflFlavour and a single bit index
267	* into the two.
268	* @sa IEM_SELECT_NATIVE_OR_FALLBACK */
269	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
270	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
271	(a_aaArray[a_fNative][pVCpu->iem.s.aidxTargetCpuEflFlavour[a_fNative] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
272	#else
273	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
274	(a_aaArray[0][pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
275	#endif
276	/** @} */
277
278	/**
279	* Picks @a a_pfnNative or @a a_pfnFallback according to the host CPU feature
280	* indicator given by @a a_fCpumFeatureMember (CPUMFEATURES member).
281	*
282	* On non-x86 hosts, this will shortcut to the fallback w/o checking the
283	* indicator.
284	*
285	* @sa IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX
286	*/
287	#if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
288	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) \
289	(g_CpumHostFeatures.s.a_fCpumFeatureMember ? a_pfnNative : a_pfnFallback)
290	#else
291	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) (a_pfnFallback)
292	#endif
293
294
295	/**
296	* Extended operand mode that includes a representation of 8-bit.
297	*
298	* This is used for packing down modes when invoking some C instruction
299	* implementations.
300	*/
301	typedef enum IEMMODEX
302	{
303	IEMMODEX_16BIT = IEMMODE_16BIT,
304	IEMMODEX_32BIT = IEMMODE_32BIT,
305	IEMMODEX_64BIT = IEMMODE_64BIT,
306	IEMMODEX_8BIT
307	} IEMMODEX;
308	AssertCompileSize(IEMMODEX, 4);
309
310
311	/**
312	* Branch types.
313	*/
314	typedef enum IEMBRANCH
315	{
316	IEMBRANCH_JUMP = 1,
317	IEMBRANCH_CALL,
318	IEMBRANCH_TRAP,
319	IEMBRANCH_SOFTWARE_INT,
320	IEMBRANCH_HARDWARE_INT
321	} IEMBRANCH;
322	AssertCompileSize(IEMBRANCH, 4);
323
324
325	/**
326	* INT instruction types.
327	*/
328	typedef enum IEMINT
329	{
330	/** INT n instruction (opcode 0xcd imm). */
331	IEMINT_INTN = 0,
332	/** Single byte INT3 instruction (opcode 0xcc). */
333	IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
334	/** Single byte INTO instruction (opcode 0xce). */
335	IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
336	/** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
337	IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
338	} IEMINT;
339	AssertCompileSize(IEMINT, 4);
340
341
342	/**
343	* A FPU result.
344	*/
345	typedef struct IEMFPURESULT
346	{
347	/** The output value. */
348	RTFLOAT80U r80Result;
349	/** The output status. */
350	uint16_t FSW;
351	} IEMFPURESULT;
352	AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
353	/** Pointer to a FPU result. */
354	typedef IEMFPURESULT *PIEMFPURESULT;
355	/** Pointer to a const FPU result. */
356	typedef IEMFPURESULT const *PCIEMFPURESULT;
357
358
359	/**
360	* A FPU result consisting of two output values and FSW.
361	*/
362	typedef struct IEMFPURESULTTWO
363	{
364	/** The first output value. */
365	RTFLOAT80U r80Result1;
366	/** The output status. */
367	uint16_t FSW;
368	/** The second output value. */
369	RTFLOAT80U r80Result2;
370	} IEMFPURESULTTWO;
371	AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
372	AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
373	/** Pointer to a FPU result consisting of two output values and FSW. */
374	typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
375	/** Pointer to a const FPU result consisting of two output values and FSW. */
376	typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
377
378
379	/**
380	* IEM TLB entry.
381	*
382	* Lookup assembly:
383	* @code{.asm}
384	; Calculate tag.
385	mov rax, [VA]
386	shl rax, 16
387	shr rax, 16 + X86_PAGE_SHIFT
388	or rax, [uTlbRevision]
389
390	; Do indexing.
391	movzx ecx, al
392	lea rcx, [pTlbEntries + rcx]
393
394	; Check tag.
395	cmp [rcx + IEMTLBENTRY.uTag], rax
396	jne .TlbMiss
397
398	; Check access.
399	mov rax, ACCESS_FLAGS \| MAPPING_R3_NOT_VALID \| 0xffffff00
400	and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
401	cmp rax, [uTlbPhysRev]
402	jne .TlbMiss
403
404	; Calc address and we're done.
405	mov eax, X86_PAGE_OFFSET_MASK
406	and eax, [VA]
407	or rax, [rcx + IEMTLBENTRY.pMappingR3]
408	%ifdef VBOX_WITH_STATISTICS
409	inc qword [cTlbHits]
410	%endif
411	jmp .Done
412
413	.TlbMiss:
414	mov r8d, ACCESS_FLAGS
415	mov rdx, [VA]
416	mov rcx, [pVCpu]
417	call iemTlbTypeMiss
418	.Done:
419
420	@endcode
421	*
422	*/
423	typedef struct IEMTLBENTRY
424	{
425	/** The TLB entry tag.
426	* Bits 35 thru 0 are made up of the virtual address shifted right 12 bits, this
427	* is ASSUMING a virtual address width of 48 bits.
428	*
429	* Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
430	*
431	* The TLB lookup code uses the current TLB revision, which won't ever be zero,
432	* enabling an extremely cheap TLB invalidation most of the time. When the TLB
433	* revision wraps around though, the tags needs to be zeroed.
434	*
435	* @note Try use SHRD instruction? After seeing
436	* https://gmplib.org/~tege/x86-timing.pdf, maybe not.
437	*
438	* @todo This will need to be reorganized for 57-bit wide virtual address and
439	* PCID (currently 12 bits) and ASID (currently 6 bits) support. We'll
440	* have to move the TLB entry versioning entirely to the
441	* fFlagsAndPhysRev member then, 57 bit wide VAs means we'll only have
442	* 19 bits left (64 - 57 + 12 = 19) and they'll almost entire be
443	* consumed by PCID and ASID (12 + 6 = 18).
444	*/
445	uint64_t uTag;
446	/** Access flags and physical TLB revision.
447	*
448	* - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
449	* - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
450	* - Bit 2 - page tables - not user (complemented X86_PTE_US).
451	* - Bit 3 - pgm phys/virt - not directly writable.
452	* - Bit 4 - pgm phys page - not directly readable.
453	* - Bit 5 - page tables - not accessed (complemented X86_PTE_A).
454	* - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
455	* - Bit 7 - tlb entry - pMappingR3 member not valid.
456	* - Bits 63 thru 8 are used for the physical TLB revision number.
457	*
458	* We're using complemented bit meanings here because it makes it easy to check
459	* whether special action is required. For instance a user mode write access
460	* would do a "TEST fFlags, (X86_PTE_RW \| X86_PTE_US \| X86_PTE_D)" and a
461	* non-zero result would mean special handling needed because either it wasn't
462	* writable, or it wasn't user, or the page wasn't dirty. A user mode read
463	* access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
464	* need to check any PTE flag.
465	*/
466	uint64_t fFlagsAndPhysRev;
467	/** The guest physical page address. */
468	uint64_t GCPhys;
469	/** Pointer to the ring-3 mapping. */
470	R3PTRTYPE(uint8_t *) pbMappingR3;
471	#if HC_ARCH_BITS == 32
472	uint32_t u32Padding1;
473	#endif
474	} IEMTLBENTRY;
475	AssertCompileSize(IEMTLBENTRY, 32);
476	/** Pointer to an IEM TLB entry. */
477	typedef IEMTLBENTRY *PIEMTLBENTRY;
478
479	/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
480	* @{ */
481	#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /*< Page tables: Not executable. /
482	#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /*< Page tables: Not writable. /
483	#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /*< Page tables: Not user accessible (supervisor only). /
484	#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /*< Phys page: Not writable (access handler, ROM, whatever). /
485	#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /*< Phys page: Not readable (MMIO / access handler, ROM) /
486	#define IEMTLBE_F_PT_NO_ACCESSED RT_BIT_64(5) /*< Phys tables: Not accessed (need to be marked accessed). /
487	#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /*< Page tables: Not dirty (needs to be made dirty on write). /
488	#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(7) /*< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. /
489	#define IEMTLBE_F_PG_UNASSIGNED RT_BIT_64(8) /*< Phys page: Unassigned memory (not RAM, ROM, MMIO2 or MMIO). /
490	#define IEMTLBE_F_PG_CODE_PAGE RT_BIT_64(9) /*< Phys page: Code page. /
491	#define IEMTLBE_F_PHYS_REV UINT64_C(0xfffffffffffffc00) /*< Physical revision mask. @sa IEMTLB_PHYS_REV_INCR /
492	/** @} */
493
494
495	/**
496	* An IEM TLB.
497	*
498	* We've got two of these, one for data and one for instructions.
499	*/
500	typedef struct IEMTLB
501	{
502	/** The TLB entries.
503	* We've choosen 256 because that way we can obtain the result directly from a
504	* 8-bit register without an additional AND instruction. */
505	IEMTLBENTRY aEntries[256];
506	/** The TLB revision.
507	* This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
508	* by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
509	* the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
510	* (The revision zero indicates an invalid TLB entry.)
511	*
512	* The initial value is choosen to cause an early wraparound. */
513	uint64_t uTlbRevision;
514	/** The TLB physical address revision - shadow of PGM variable.
515	*
516	* This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
517	* incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
518	* a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
519	* as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
520	*
521	* The initial value is choosen to cause an early wraparound. */
522	uint64_t volatile uTlbPhysRev;
523
524	/* Statistics: */
525
526	/** TLB hits (VBOX_WITH_STATISTICS only). */
527	uint64_t cTlbHits;
528	/** TLB misses. */
529	uint32_t cTlbMisses;
530	/** Slow read path. */
531	uint32_t cTlbSlowReadPath;
532	/** Safe read path. */
533	uint32_t cTlbSafeReadPath;
534	/** Safe write path. */
535	uint32_t cTlbSafeWritePath;
536	#if 0
537	/** TLB misses because of tag mismatch. */
538	uint32_t cTlbMissesTag;
539	/** TLB misses because of virtual access violation. */
540	uint32_t cTlbMissesVirtAccess;
541	/** TLB misses because of dirty bit. */
542	uint32_t cTlbMissesDirty;
543	/** TLB misses because of MMIO */
544	uint32_t cTlbMissesMmio;
545	/** TLB misses because of write access handlers. */
546	uint32_t cTlbMissesWriteHandler;
547	/** TLB misses because no r3(/r0) mapping. */
548	uint32_t cTlbMissesMapping;
549	#endif
550	/** Alignment padding. */
551	uint32_t au32Padding[6];
552	} IEMTLB;
553	AssertCompileSizeAlignment(IEMTLB, 64);
554	/** IEMTLB::uTlbRevision increment. */
555	#define IEMTLB_REVISION_INCR RT_BIT_64(36)
556	/** IEMTLB::uTlbRevision mask. */
557	#define IEMTLB_REVISION_MASK (~(RT_BIT_64(36) - 1))
558	/** IEMTLB::uTlbPhysRev increment.
559	* @sa IEMTLBE_F_PHYS_REV */
560	#define IEMTLB_PHYS_REV_INCR RT_BIT_64(10)
561	/**
562	* Calculates the TLB tag for a virtual address.
563	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
564	* @param a_pTlb The TLB.
565	* @param a_GCPtr The virtual address. Must be RTGCPTR or same size or
566	* the clearing of the top 16 bits won't work (if 32-bit
567	* we'll end up with mostly zeros).
568	*/
569	#define IEMTLB_CALC_TAG(a_pTlb, a_GCPtr) ( IEMTLB_CALC_TAG_NO_REV(a_GCPtr) \| (a_pTlb)->uTlbRevision )
570	/**
571	* Calculates the TLB tag for a virtual address but without TLB revision.
572	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
573	* @param a_GCPtr The virtual address. Must be RTGCPTR or same size or
574	* the clearing of the top 16 bits won't work (if 32-bit
575	* we'll end up with mostly zeros).
576	*/
577	#define IEMTLB_CALC_TAG_NO_REV(a_GCPtr) ( (((a_GCPtr) << 16) >> (GUEST_PAGE_SHIFT + 16)) )
578	/**
579	* Converts a TLB tag value into a TLB index.
580	* @returns Index into IEMTLB::aEntries.
581	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
582	*/
583	#define IEMTLB_TAG_TO_INDEX(a_uTag) ( (uint8_t)(a_uTag) )
584	/**
585	* Converts a TLB tag value into a TLB index.
586	* @returns Index into IEMTLB::aEntries.
587	* @param a_pTlb The TLB.
588	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
589	*/
590	#define IEMTLB_TAG_TO_ENTRY(a_pTlb, a_uTag) ( &(a_pTlb)->aEntries[IEMTLB_TAG_TO_INDEX(a_uTag)] )
591
592
593	/** @name IEM_MC_F_XXX - MC block flags/clues.
594	* @todo Merge with IEM_CIMPL_F_XXX
595	* @{ */
596	#define IEM_MC_F_ONLY_8086 RT_BIT_32(0)
597	#define IEM_MC_F_MIN_186 RT_BIT_32(1)
598	#define IEM_MC_F_MIN_286 RT_BIT_32(2)
599	#define IEM_MC_F_NOT_286_OR_OLDER IEM_MC_F_MIN_386
600	#define IEM_MC_F_MIN_386 RT_BIT_32(3)
601	#define IEM_MC_F_MIN_486 RT_BIT_32(4)
602	#define IEM_MC_F_MIN_PENTIUM RT_BIT_32(5)
603	#define IEM_MC_F_MIN_PENTIUM_II IEM_MC_F_MIN_PENTIUM
604	#define IEM_MC_F_MIN_CORE IEM_MC_F_MIN_PENTIUM
605	#define IEM_MC_F_64BIT RT_BIT_32(6)
606	#define IEM_MC_F_NOT_64BIT RT_BIT_32(7)
607	/** This is set by IEMAllN8vePython.py to indicate a variation without the
608	* flags-clearing-and-checking, when there is also a variation with that.
609	* @note Do not use this manully, it's only for python and for testing in
610	* the native recompiler! */
611	#define IEM_MC_F_WITHOUT_FLAGS RT_BIT_32(8)
612	/** @} */
613
614	/** @name IEM_CIMPL_F_XXX - State change clues for CIMPL calls.
615	*
616	* These clues are mainly for the recompiler, so that it can emit correct code.
617	*
618	* They are processed by the python script and which also automatically
619	* calculates flags for MC blocks based on the statements, extending the use of
620	* these flags to describe MC block behavior to the recompiler core. The python
621	* script pass the flags to the IEM_MC2_END_EMIT_CALLS macro, but mainly for
622	* error checking purposes. The script emits the necessary fEndTb = true and
623	* similar statements as this reduces compile time a tiny bit.
624	*
625	* @{ */
626	/** Flag set if direct branch, clear if absolute or indirect. */
627	#define IEM_CIMPL_F_BRANCH_DIRECT RT_BIT_32(0)
628	/** Flag set if indirect branch, clear if direct or relative.
629	* This is also used for all system control transfers (SYSCALL, SYSRET, INT, ++)
630	* as well as for return instructions (RET, IRET, RETF). */
631	#define IEM_CIMPL_F_BRANCH_INDIRECT RT_BIT_32(1)
632	/** Flag set if relative branch, clear if absolute or indirect. */
633	#define IEM_CIMPL_F_BRANCH_RELATIVE RT_BIT_32(2)
634	/** Flag set if conditional branch, clear if unconditional. */
635	#define IEM_CIMPL_F_BRANCH_CONDITIONAL RT_BIT_32(3)
636	/** Flag set if it's a far branch (changes CS). */
637	#define IEM_CIMPL_F_BRANCH_FAR RT_BIT_32(4)
638	/** Convenience: Testing any kind of branch. */
639	#define IEM_CIMPL_F_BRANCH_ANY (IEM_CIMPL_F_BRANCH_DIRECT \| IEM_CIMPL_F_BRANCH_INDIRECT \| IEM_CIMPL_F_BRANCH_RELATIVE)
640
641	/** Execution flags may change (IEMCPU::fExec). */
642	#define IEM_CIMPL_F_MODE RT_BIT_32(5)
643	/** May change significant portions of RFLAGS. */
644	#define IEM_CIMPL_F_RFLAGS RT_BIT_32(6)
645	/** May change the status bits (X86_EFL_STATUS_BITS) in RFLAGS. */
646	#define IEM_CIMPL_F_STATUS_FLAGS RT_BIT_32(7)
647	/** May trigger interrupt shadowing. */
648	#define IEM_CIMPL_F_INHIBIT_SHADOW RT_BIT_32(8)
649	/** May enable interrupts, so recheck IRQ immediately afterwards executing
650	* the instruction. */
651	#define IEM_CIMPL_F_CHECK_IRQ_AFTER RT_BIT_32(9)
652	/** May disable interrupts, so recheck IRQ immediately before executing the
653	* instruction. */
654	#define IEM_CIMPL_F_CHECK_IRQ_BEFORE RT_BIT_32(10)
655	/** Convenience: Check for IRQ both before and after an instruction. */
656	#define IEM_CIMPL_F_CHECK_IRQ_BEFORE_AND_AFTER (IEM_CIMPL_F_CHECK_IRQ_BEFORE \| IEM_CIMPL_F_CHECK_IRQ_AFTER)
657	/** May trigger a VM exit (treated like IEM_CIMPL_F_MODE atm). */
658	#define IEM_CIMPL_F_VMEXIT RT_BIT_32(11)
659	/** May modify FPU state.
660	* @todo Not sure if this is useful yet. */
661	#define IEM_CIMPL_F_FPU RT_BIT_32(12)
662	/** REP prefixed instruction which may yield before updating PC.
663	* @todo Not sure if this is useful, REP functions now return non-zero
664	* status if they don't update the PC. */
665	#define IEM_CIMPL_F_REP RT_BIT_32(13)
666	/** I/O instruction.
667	* @todo Not sure if this is useful yet. */
668	#define IEM_CIMPL_F_IO RT_BIT_32(14)
669	/** Force end of TB after the instruction. */
670	#define IEM_CIMPL_F_END_TB RT_BIT_32(15)
671	/** Flag set if a branch may also modify the stack (push/pop return address). */
672	#define IEM_CIMPL_F_BRANCH_STACK RT_BIT_32(16)
673	/** Flag set if a branch may also modify the stack (push/pop return address)
674	* and switch it (load/restore SS:RSP). */
675	#define IEM_CIMPL_F_BRANCH_STACK_FAR RT_BIT_32(17)
676	/** Convenience: Raise exception (technically unnecessary, since it shouldn't return VINF_SUCCESS). */
677	#define IEM_CIMPL_F_XCPT \
678	(IEM_CIMPL_F_BRANCH_INDIRECT \| IEM_CIMPL_F_BRANCH_FAR \| IEM_CIMPL_F_BRANCH_STACK_FAR \
679	\| IEM_CIMPL_F_MODE \| IEM_CIMPL_F_RFLAGS \| IEM_CIMPL_F_VMEXIT)
680
681	/** The block calls a C-implementation instruction function with two implicit arguments.
682	* Mutually exclusive with IEM_CIMPL_F_CALLS_AIMPL and
683	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
684	* @note The python scripts will add this is missing. */
685	#define IEM_CIMPL_F_CALLS_CIMPL RT_BIT_32(18)
686	/** The block calls an ASM-implementation instruction function.
687	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL and
688	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
689	* @note The python scripts will add this is missing. */
690	#define IEM_CIMPL_F_CALLS_AIMPL RT_BIT_32(19)
691	/** The block calls an ASM-implementation instruction function with an implicit
692	* X86FXSTATE pointer argument.
693	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL and IEM_CIMPL_F_CALLS_AIMPL.
694	* @note The python scripts will add this is missing. */
695	#define IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE RT_BIT_32(20)
696	/** @} */
697
698
699	/** @name IEM_F_XXX - Execution mode flags (IEMCPU::fExec, IEMTB::fFlags).
700	*
701	* These flags are set when entering IEM and adjusted as code is executed, such
702	* that they will always contain the current values as instructions are
703	* finished.
704	*
705	* In recompiled execution mode, (most of) these flags are included in the
706	* translation block selection key and stored in IEMTB::fFlags alongside the
707	* IEMTB_F_XXX flags. The latter flags uses bits 31 thru 24, which are all zero
708	* in IEMCPU::fExec.
709	*
710	* @{ */
711	/** Mode: The block target mode mask. */
712	#define IEM_F_MODE_MASK UINT32_C(0x0000001f)
713	/** Mode: The IEMMODE part of the IEMTB_F_MODE_MASK value. */
714	#define IEM_F_MODE_CPUMODE_MASK UINT32_C(0x00000003)
715	/** X86 Mode: Bit used to indicating pre-386 CPU in 16-bit mode (for eliminating
716	* conditional in EIP/IP updating), and flat wide open CS, SS, DS, and ES in
717	* 32-bit mode (for simplifying most memory accesses). */
718	#define IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK UINT32_C(0x00000004)
719	/** X86 Mode: Bit indicating protected mode, real mode (or SMM) when not set. */
720	#define IEM_F_MODE_X86_PROT_MASK UINT32_C(0x00000008)
721	/** X86 Mode: Bit used to indicate virtual 8086 mode (only 16-bit). */
722	#define IEM_F_MODE_X86_V86_MASK UINT32_C(0x00000010)
723
724	/** X86 Mode: 16-bit on 386 or later. */
725	#define IEM_F_MODE_X86_16BIT UINT32_C(0x00000000)
726	/** X86 Mode: 80286, 80186 and 8086/88 targetting blocks (EIP update opt). */
727	#define IEM_F_MODE_X86_16BIT_PRE_386 UINT32_C(0x00000004)
728	/** X86 Mode: 16-bit protected mode on 386 or later. */
729	#define IEM_F_MODE_X86_16BIT_PROT UINT32_C(0x00000008)
730	/** X86 Mode: 16-bit protected mode on 386 or later. */
731	#define IEM_F_MODE_X86_16BIT_PROT_PRE_386 UINT32_C(0x0000000c)
732	/** X86 Mode: 16-bit virtual 8086 protected mode (on 386 or later). */
733	#define IEM_F_MODE_X86_16BIT_PROT_V86 UINT32_C(0x00000018)
734
735	/** X86 Mode: 32-bit on 386 or later. */
736	#define IEM_F_MODE_X86_32BIT UINT32_C(0x00000001)
737	/** X86 Mode: 32-bit mode with wide open flat CS, SS, DS and ES. */
738	#define IEM_F_MODE_X86_32BIT_FLAT UINT32_C(0x00000005)
739	/** X86 Mode: 32-bit protected mode. */
740	#define IEM_F_MODE_X86_32BIT_PROT UINT32_C(0x00000009)
741	/** X86 Mode: 32-bit protected mode with wide open flat CS, SS, DS and ES. */
742	#define IEM_F_MODE_X86_32BIT_PROT_FLAT UINT32_C(0x0000000d)
743
744	/** X86 Mode: 64-bit (includes protected, but not the flat bit). */
745	#define IEM_F_MODE_X86_64BIT UINT32_C(0x0000000a)
746
747	/** X86 Mode: Checks if @a a_fExec represent a FLAT mode. */
748	#define IEM_F_MODE_X86_IS_FLAT(a_fExec) ( ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_64BIT \
749	\|\| ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_32BIT_PROT_FLAT \
750	\|\| ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_32BIT_FLAT)
751
752	/** Bypass access handlers when set. */
753	#define IEM_F_BYPASS_HANDLERS UINT32_C(0x00010000)
754	/** Have pending hardware instruction breakpoints. */
755	#define IEM_F_PENDING_BRK_INSTR UINT32_C(0x00020000)
756	/** Have pending hardware data breakpoints. */
757	#define IEM_F_PENDING_BRK_DATA UINT32_C(0x00040000)
758
759	/** X86: Have pending hardware I/O breakpoints. */
760	#define IEM_F_PENDING_BRK_X86_IO UINT32_C(0x00000400)
761	/** X86: Disregard the lock prefix (implied or not) when set. */
762	#define IEM_F_X86_DISREGARD_LOCK UINT32_C(0x00000800)
763
764	/** Pending breakpoint mask (what iemCalcExecDbgFlags works out). */
765	#define IEM_F_PENDING_BRK_MASK (IEM_F_PENDING_BRK_INSTR \| IEM_F_PENDING_BRK_DATA \| IEM_F_PENDING_BRK_X86_IO)
766
767	/** Caller configurable options. */
768	#define IEM_F_USER_OPTS (IEM_F_BYPASS_HANDLERS \| IEM_F_X86_DISREGARD_LOCK)
769
770	/** X86: The current protection level (CPL) shift factor. */
771	#define IEM_F_X86_CPL_SHIFT 8
772	/** X86: The current protection level (CPL) mask. */
773	#define IEM_F_X86_CPL_MASK UINT32_C(0x00000300)
774	/** X86: The current protection level (CPL) shifted mask. */
775	#define IEM_F_X86_CPL_SMASK UINT32_C(0x00000003)
776
777	/** X86 execution context.
778	* The IEM_F_X86_CTX_XXX values are individual flags that can be combined (with
779	* the exception of IEM_F_X86_CTX_NORMAL). This allows running VMs from SMM
780	* mode. */
781	#define IEM_F_X86_CTX_MASK UINT32_C(0x0000f000)
782	/** X86 context: Plain regular execution context. */
783	#define IEM_F_X86_CTX_NORMAL UINT32_C(0x00000000)
784	/** X86 context: VT-x enabled. */
785	#define IEM_F_X86_CTX_VMX UINT32_C(0x00001000)
786	/** X86 context: AMD-V enabled. */
787	#define IEM_F_X86_CTX_SVM UINT32_C(0x00002000)
788	/** X86 context: In AMD-V or VT-x guest mode. */
789	#define IEM_F_X86_CTX_IN_GUEST UINT32_C(0x00004000)
790	/** X86 context: System management mode (SMM). */
791	#define IEM_F_X86_CTX_SMM UINT32_C(0x00008000)
792
793	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
794	* iemRegFinishClearingRF() most for most situations (CPUMCTX_DBG_HIT_DRX_MASK
795	* and CPUMCTX_DBG_DBGF_MASK are covered by the IEM_F_PENDING_BRK_XXX bits
796	* alread). */
797
798	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
799	* iemRegFinishClearingRF() most for most situations
800	* (CPUMCTX_DBG_HIT_DRX_MASK and CPUMCTX_DBG_DBGF_MASK are covered by
801	* the IEM_F_PENDING_BRK_XXX bits alread). */
802
803	/** @} */
804
805
806	/** @name IEMTB_F_XXX - Translation block flags (IEMTB::fFlags).
807	*
808	* Extends the IEM_F_XXX flags (subject to IEMTB_F_IEM_F_MASK) to make up the
809	* translation block flags. The combined flag mask (subject to
810	* IEMTB_F_KEY_MASK) is used as part of the lookup key for translation blocks.
811	*
812	* @{ */
813	/** Mask of IEM_F_XXX flags included in IEMTB_F_XXX. */
814	#define IEMTB_F_IEM_F_MASK UINT32_C(0x00ffffff)
815
816	/** Type: The block type mask. */
817	#define IEMTB_F_TYPE_MASK UINT32_C(0x03000000)
818	/** Type: Purly threaded recompiler (via tables). */
819	#define IEMTB_F_TYPE_THREADED UINT32_C(0x01000000)
820	/** Type: Native recompilation. */
821	#define IEMTB_F_TYPE_NATIVE UINT32_C(0x02000000)
822
823	/** Set when we're starting the block in an "interrupt shadow".
824	* We don't need to distingish between the two types of this mask, thus the one.
825	* @see CPUMCTX_INHIBIT_SHADOW, CPUMIsInInterruptShadow() */
826	#define IEMTB_F_INHIBIT_SHADOW UINT32_C(0x04000000)
827	/** Set when we're currently inhibiting NMIs
828	* @see CPUMCTX_INHIBIT_NMI, CPUMAreInterruptsInhibitedByNmi() */
829	#define IEMTB_F_INHIBIT_NMI UINT32_C(0x08000000)
830
831	/** Checks that EIP/IP is wihin CS.LIM before each instruction. Used when
832	* we're close the limit before starting a TB, as determined by
833	* iemGetTbFlagsForCurrentPc(). */
834	#define IEMTB_F_CS_LIM_CHECKS UINT32_C(0x10000000)
835
836	/** Mask of the IEMTB_F_XXX flags that are part of the TB lookup key.
837	*
838	* @note We skip all of IEM_F_X86_CTX_MASK, with the exception of SMM (which we
839	* don't implement), because we don't currently generate any context
840	* specific code - that's all handled in CIMPL functions.
841	*
842	* For the threaded recompiler we don't generate any CPL specific code
843	* either, but the native recompiler does for memory access (saves getting
844	* the CPL from fExec and turning it into IEMTLBE_F_PT_NO_USER).
845	* Since most OSes will not share code between rings, this shouldn't
846	* have any real effect on TB/memory/recompiling load.
847	*/
848	#define IEMTB_F_KEY_MASK ((UINT32_MAX & ~(IEM_F_X86_CTX_MASK \| IEMTB_F_TYPE_MASK)) \| IEM_F_X86_CTX_SMM)
849	/** @} */
850
851	AssertCompile( (IEM_F_MODE_X86_16BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
852	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
853	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_PROT_MASK));
854	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_V86_MASK));
855	AssertCompile( (IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
856	AssertCompile( IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
857	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_PROT_MASK));
858	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
859	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
860	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
861	AssertCompile( IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
862	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_V86_MASK));
863	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
864	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
865	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_PROT_MASK);
866	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
867	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_PROT_MASK);
868	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
869	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_V86_MASK);
870
871	AssertCompile( (IEM_F_MODE_X86_32BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
872	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
873	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_PROT_MASK));
874	AssertCompile( (IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
875	AssertCompile( IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
876	AssertCompile(!(IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_PROT_MASK));
877	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
878	AssertCompile(!(IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
879	AssertCompile( IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
880	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
881	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
882	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_PROT_MASK);
883
884	AssertCompile( (IEM_F_MODE_X86_64BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_64BIT);
885	AssertCompile( IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_PROT_MASK);
886	AssertCompile(!(IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
887
888	/** Native instruction type for use with the native code generator.
889	* This is a byte (uint8_t) for x86 and amd64 and uint32_t for the other(s). */
890	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
891	typedef uint8_t IEMNATIVEINSTR;
892	#else
893	typedef uint32_t IEMNATIVEINSTR;
894	#endif
895	/** Pointer to a native instruction unit. */
896	typedef IEMNATIVEINSTR *PIEMNATIVEINSTR;
897	/** Pointer to a const native instruction unit. */
898	typedef IEMNATIVEINSTR const *PCIEMNATIVEINSTR;
899
900	/**
901	* A call for the threaded call table.
902	*/
903	typedef struct IEMTHRDEDCALLENTRY
904	{
905	/** The function to call (IEMTHREADEDFUNCS). */
906	uint16_t enmFunction;
907	/** Instruction number in the TB (for statistics). */
908	uint8_t idxInstr;
909	uint8_t uUnused0;
910
911	/** Offset into IEMTB::pabOpcodes. */
912	uint16_t offOpcode;
913	/** The opcode length. */
914	uint8_t cbOpcode;
915	/** Index in to IEMTB::aRanges. */
916	uint8_t idxRange;
917
918	/** Generic parameters. */
919	uint64_t auParams[3];
920	} IEMTHRDEDCALLENTRY;
921	AssertCompileSize(IEMTHRDEDCALLENTRY, sizeof(uint64_t) * 4);
922	/** Pointer to a threaded call entry. */
923	typedef struct IEMTHRDEDCALLENTRY *PIEMTHRDEDCALLENTRY;
924	/** Pointer to a const threaded call entry. */
925	typedef IEMTHRDEDCALLENTRY const *PCIEMTHRDEDCALLENTRY;
926
927	/**
928	* Native IEM TB 'function' typedef.
929	*
930	* This will throw/longjmp on occation.
931	*
932	* @note AMD64 doesn't have that many non-volatile registers and does sport
933	* 32-bit address displacments, so we don't need pCtx.
934	*
935	* On ARM64 pCtx allows us to directly address the whole register
936	* context without requiring a separate indexing register holding the
937	* offset. This saves an instruction loading the offset for each guest
938	* CPU context access, at the cost of a non-volatile register.
939	* Fortunately, ARM64 has quite a lot more registers.
940	*/
941	typedef
942	#ifdef RT_ARCH_AMD64
943	int FNIEMTBNATIVE(PVMCPUCC pVCpu)
944	#else
945	int FNIEMTBNATIVE(PVMCPUCC pVCpu, PCPUMCTX pCtx)
946	#endif
947	#if RT_CPLUSPLUS_PREREQ(201700)
948	IEM_NOEXCEPT_MAY_LONGJMP
949	#endif
950	;
951	/** Pointer to a native IEM TB entry point function.
952	* This will throw/longjmp on occation. */
953	typedef FNIEMTBNATIVE *PFNIEMTBNATIVE;
954
955
956	/**
957	* Translation block debug info entry type.
958	*/
959	typedef enum IEMTBDBGENTRYTYPE
960	{
961	kIemTbDbgEntryType_Invalid = 0,
962	/** The entry is for marking a native code position.
963	* Entries following this all apply to this position. */
964	kIemTbDbgEntryType_NativeOffset,
965	/** The entry is for a new guest instruction. */
966	kIemTbDbgEntryType_GuestInstruction,
967	/** Marks the start of a threaded call. */
968	kIemTbDbgEntryType_ThreadedCall,
969	/** Marks the location of a label. */
970	kIemTbDbgEntryType_Label,
971	/** Info about a host register shadowing a guest register. */
972	kIemTbDbgEntryType_GuestRegShadowing,
973	#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
974	/** Info about a host SIMD register shadowing a guest SIMD register. */
975	kIemTbDbgEntryType_GuestSimdRegShadowing,
976	#endif
977	#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING
978	/** Info about a delayed RIP update. */
979	kIemTbDbgEntryType_DelayedPcUpdate,
980	#endif
981	kIemTbDbgEntryType_End
982	} IEMTBDBGENTRYTYPE;
983
984	/**
985	* Translation block debug info entry.
986	*/
987	typedef union IEMTBDBGENTRY
988	{
989	/** Plain 32-bit view. */
990	uint32_t u;
991
992	/** Generic view for getting at the type field. */
993	struct
994	{
995	/** IEMTBDBGENTRYTYPE */
996	uint32_t uType : 4;
997	uint32_t uTypeSpecific : 28;
998	} Gen;
999
1000	struct
1001	{
1002	/** kIemTbDbgEntryType_ThreadedCall1. */
1003	uint32_t uType : 4;
1004	/** Native code offset. */
1005	uint32_t offNative : 28;
1006	} NativeOffset;
1007
1008	struct
1009	{
1010	/** kIemTbDbgEntryType_GuestInstruction. */
1011	uint32_t uType : 4;
1012	uint32_t uUnused : 4;
1013	/** The IEM_F_XXX flags. */
1014	uint32_t fExec : 24;
1015	} GuestInstruction;
1016
1017	struct
1018	{
1019	/* kIemTbDbgEntryType_ThreadedCall. */
1020	uint32_t uType : 4;
1021	/** Set if the call was recompiled to native code, clear if just calling
1022	* threaded function. */
1023	uint32_t fRecompiled : 1;
1024	uint32_t uUnused : 11;
1025	/** The threaded call number (IEMTHREADEDFUNCS). */
1026	uint32_t enmCall : 16;
1027	} ThreadedCall;
1028
1029	struct
1030	{
1031	/* kIemTbDbgEntryType_Label. */
1032	uint32_t uType : 4;
1033	uint32_t uUnused : 4;
1034	/** The label type (IEMNATIVELABELTYPE). */
1035	uint32_t enmLabel : 8;
1036	/** The label data. */
1037	uint32_t uData : 16;
1038	} Label;
1039
1040	struct
1041	{
1042	/* kIemTbDbgEntryType_GuestRegShadowing. */
1043	uint32_t uType : 4;
1044	uint32_t uUnused : 4;
1045	/** The guest register being shadowed (IEMNATIVEGSTREG). */
1046	uint32_t idxGstReg : 8;
1047	/** The host new register number, UINT8_MAX if dropped. */
1048	uint32_t idxHstReg : 8;
1049	/** The previous host register number, UINT8_MAX if new. */
1050	uint32_t idxHstRegPrev : 8;
1051	} GuestRegShadowing;
1052
1053	#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
1054	struct
1055	{
1056	/* kIemTbDbgEntryType_GuestSimdRegShadowing. */
1057	uint32_t uType : 4;
1058	uint32_t uUnused : 4;
1059	/** The guest register being shadowed (IEMNATIVEGSTSIMDREG). */
1060	uint32_t idxGstSimdReg : 8;
1061	/** The host new register number, UINT8_MAX if dropped. */
1062	uint32_t idxHstSimdReg : 8;
1063	/** The previous host register number, UINT8_MAX if new. */
1064	uint32_t idxHstSimdRegPrev : 8;
1065	} GuestSimdRegShadowing;
1066	#endif
1067
1068	#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING
1069	struct
1070	{
1071	/* kIemTbDbgEntryType_DelayedPcUpdate. */
1072	uint32_t uType : 4;
1073	/* The instruction offset added to the program counter. */
1074	uint32_t offPc : 14;
1075	/** Number of instructions skipped. */
1076	uint32_t cInstrSkipped : 14;
1077	} DelayedPcUpdate;
1078	#endif
1079
1080	} IEMTBDBGENTRY;
1081	AssertCompileSize(IEMTBDBGENTRY, sizeof(uint32_t));
1082	/** Pointer to a debug info entry. */
1083	typedef IEMTBDBGENTRY *PIEMTBDBGENTRY;
1084	/** Pointer to a const debug info entry. */
1085	typedef IEMTBDBGENTRY const *PCIEMTBDBGENTRY;
1086
1087	/**
1088	* Translation block debug info.
1089	*/
1090	typedef struct IEMTBDBG
1091	{
1092	/** Number of entries in aEntries. */
1093	uint32_t cEntries;
1094	/** Debug info entries. */
1095	RT_FLEXIBLE_ARRAY_EXTENSION
1096	IEMTBDBGENTRY aEntries[RT_FLEXIBLE_ARRAY];
1097	} IEMTBDBG;
1098	/** Pointer to TB debug info. */
1099	typedef IEMTBDBG *PIEMTBDBG;
1100	/** Pointer to const TB debug info. */
1101	typedef IEMTBDBG const *PCIEMTBDBG;
1102
1103
1104	/**
1105	* Translation block.
1106	*
1107	* The current plan is to just keep TBs and associated lookup hash table private
1108	* to each VCpu as that simplifies TB removal greatly (no races) and generally
1109	* avoids using expensive atomic primitives for updating lists and stuff.
1110	*/
1111	#pragma pack(2) /* to prevent the Thrd structure from being padded unnecessarily */
1112	typedef struct IEMTB
1113	{
1114	/** Next block with the same hash table entry. */
1115	struct IEMTB *pNext;
1116	/** Usage counter. */
1117	uint32_t cUsed;
1118	/** The IEMCPU::msRecompilerPollNow last time it was used. */
1119	uint32_t msLastUsed;
1120
1121	/** @name What uniquely identifies the block.
1122	* @{ */
1123	RTGCPHYS GCPhysPc;
1124	/** IEMTB_F_XXX (i.e. IEM_F_XXX ++). */
1125	uint32_t fFlags;
1126	union
1127	{
1128	struct
1129	{
1130	/*< Relevant CS X86DESCATTR_XXX bits. /
1131	uint16_t fAttr;
1132	} x86;
1133	};
1134	/** @} */
1135
1136	/** Number of opcode ranges. */
1137	uint8_t cRanges;
1138	/** Statistics: Number of instructions in the block. */
1139	uint8_t cInstructions;
1140
1141	/** Type specific info. */
1142	union
1143	{
1144	struct
1145	{
1146	/** The call sequence table. */
1147	PIEMTHRDEDCALLENTRY paCalls;
1148	/** Number of calls in paCalls. */
1149	uint16_t cCalls;
1150	/** Number of calls allocated. */
1151	uint16_t cAllocated;
1152	} Thrd;
1153	struct
1154	{
1155	/** The native instructions (PFNIEMTBNATIVE). */
1156	PIEMNATIVEINSTR paInstructions;
1157	/** Number of instructions pointed to by paInstructions. */
1158	uint32_t cInstructions;
1159	} Native;
1160	/** Generic view for zeroing when freeing. */
1161	struct
1162	{
1163	uintptr_t uPtr;
1164	uint32_t uData;
1165	} Gen;
1166	};
1167
1168	/** The allocation chunk this TB belongs to. */
1169	uint8_t idxAllocChunk;
1170	uint8_t bUnused;
1171
1172	/** Number of bytes of opcodes stored in pabOpcodes.
1173	* @todo this field isn't really needed, aRanges keeps the actual info. */
1174	uint16_t cbOpcodes;
1175	/** Pointer to the opcode bytes this block was recompiled from. */
1176	uint8_t *pabOpcodes;
1177
1178	/** Debug info if enabled.
1179	* This is only generated by the native recompiler. */
1180	PIEMTBDBG pDbgInfo;
1181
1182	/* --- 64 byte cache line end --- */
1183
1184	/** Opcode ranges.
1185	*
1186	* The opcode checkers and maybe TLB loading functions will use this to figure
1187	* out what to do. The parameter will specify an entry and the opcode offset to
1188	* start at and the minimum number of bytes to verify (instruction length).
1189	*
1190	* When VT-x and AMD-V looks up the opcode bytes for an exitting instruction,
1191	* they'll first translate RIP (+ cbInstr - 1) to a physical address using the
1192	* code TLB (must have a valid entry for that address) and scan the ranges to
1193	* locate the corresponding opcodes. Probably.
1194	*/
1195	struct IEMTBOPCODERANGE
1196	{
1197	/** Offset within pabOpcodes. */
1198	uint16_t offOpcodes;
1199	/** Number of bytes. */
1200	uint16_t cbOpcodes;
1201	/** The page offset. */
1202	RT_GCC_EXTENSION
1203	uint16_t offPhysPage : 12;
1204	/** Unused bits. */
1205	RT_GCC_EXTENSION
1206	uint16_t u2Unused : 2;
1207	/** Index into GCPhysPc + aGCPhysPages for the physical page address. */
1208	RT_GCC_EXTENSION
1209	uint16_t idxPhysPage : 2;
1210	} aRanges[8];
1211
1212	/** Physical pages that this TB covers.
1213	* The GCPhysPc w/o page offset is element zero, so starting here with 1. */
1214	RTGCPHYS aGCPhysPages[2];
1215	} IEMTB;
1216	#pragma pack()
1217	AssertCompileMemberAlignment(IEMTB, GCPhysPc, sizeof(RTGCPHYS));
1218	AssertCompileMemberAlignment(IEMTB, Thrd, sizeof(void *));
1219	AssertCompileMemberAlignment(IEMTB, pabOpcodes, sizeof(void *));
1220	AssertCompileMemberAlignment(IEMTB, pDbgInfo, sizeof(void *));
1221	AssertCompileMemberAlignment(IEMTB, aGCPhysPages, sizeof(RTGCPHYS));
1222	AssertCompileMemberOffset(IEMTB, aRanges, 64);
1223	AssertCompileMemberSize(IEMTB, aRanges[0], 6);
1224	#if 1
1225	AssertCompileSize(IEMTB, 128);
1226	# define IEMTB_SIZE_IS_POWER_OF_TWO /*< The IEMTB size is a power of two. /
1227	#else
1228	AssertCompileSize(IEMTB, 168);
1229	# undef IEMTB_SIZE_IS_POWER_OF_TWO
1230	#endif
1231
1232	/** Pointer to a translation block. */
1233	typedef IEMTB *PIEMTB;
1234	/** Pointer to a const translation block. */
1235	typedef IEMTB const *PCIEMTB;
1236
1237	/**
1238	* A chunk of memory in the TB allocator.
1239	*/
1240	typedef struct IEMTBCHUNK
1241	{
1242	/** Pointer to the translation blocks in this chunk. */
1243	PIEMTB paTbs;
1244	#ifdef IN_RING0
1245	/** Allocation handle. */
1246	RTR0MEMOBJ hMemObj;
1247	#endif
1248	} IEMTBCHUNK;
1249
1250	/**
1251	* A per-CPU translation block allocator.
1252	*
1253	* Because of how the IEMTBCACHE uses the lower 6 bits of the TB address to keep
1254	* the length of the collision list, and of course also for cache line alignment
1255	* reasons, the TBs must be allocated with at least 64-byte alignment.
1256	* Memory is there therefore allocated using one of the page aligned allocators.
1257	*
1258	*
1259	* To avoid wasting too much memory, it is allocated piecemeal as needed,
1260	* in chunks (IEMTBCHUNK) of 2 MiB or more. The TB has an 8-bit chunk index
1261	* that enables us to quickly calculate the allocation bitmap position when
1262	* freeing the translation block.
1263	*/
1264	typedef struct IEMTBALLOCATOR
1265	{
1266	/** Magic value (IEMTBALLOCATOR_MAGIC). */
1267	uint32_t uMagic;
1268
1269	#ifdef IEMTB_SIZE_IS_POWER_OF_TWO
1270	/** Mask corresponding to cTbsPerChunk - 1. */
1271	uint32_t fChunkMask;
1272	/** Shift count corresponding to cTbsPerChunk. */
1273	uint8_t cChunkShift;
1274	#else
1275	uint32_t uUnused;
1276	uint8_t bUnused;
1277	#endif
1278	/** Number of chunks we're allowed to allocate. */
1279	uint8_t cMaxChunks;
1280	/** Number of chunks currently populated. */
1281	uint16_t cAllocatedChunks;
1282	/** Number of translation blocks per chunk. */
1283	uint32_t cTbsPerChunk;
1284	/** Chunk size. */
1285	uint32_t cbPerChunk;
1286
1287	/** The maximum number of TBs. */
1288	uint32_t cMaxTbs;
1289	/** Total number of TBs in the populated chunks.
1290	* (cAllocatedChunks * cTbsPerChunk) */
1291	uint32_t cTotalTbs;
1292	/** The current number of TBs in use.
1293	* The number of free TBs: cAllocatedTbs - cInUseTbs; */
1294	uint32_t cInUseTbs;
1295	/** Statistics: Number of the cInUseTbs that are native ones. */
1296	uint32_t cNativeTbs;
1297	/** Statistics: Number of the cInUseTbs that are threaded ones. */
1298	uint32_t cThreadedTbs;
1299
1300	/** Where to start pruning TBs from when we're out.
1301	* See iemTbAllocatorAllocSlow for details. */
1302	uint32_t iPruneFrom;
1303	/** Hint about which bit to start scanning the bitmap from. */
1304	uint32_t iStartHint;
1305	/** Where to start pruning native TBs from when we're out of executable memory.
1306	* See iemTbAllocatorFreeupNativeSpace for details. */
1307	uint32_t iPruneNativeFrom;
1308	uint32_t uPadding;
1309
1310	/** Statistics: Number of TB allocation calls. */
1311	STAMCOUNTER StatAllocs;
1312	/** Statistics: Number of TB free calls. */
1313	STAMCOUNTER StatFrees;
1314	/** Statistics: Time spend pruning. */
1315	STAMPROFILE StatPrune;
1316	/** Statistics: Time spend pruning native TBs. */
1317	STAMPROFILE StatPruneNative;
1318
1319	/** The delayed free list (see iemTbAlloctorScheduleForFree). */
1320	PIEMTB pDelayedFreeHead;
1321
1322	/** Allocation chunks. */
1323	IEMTBCHUNK aChunks[256];
1324
1325	/** Allocation bitmap for all possible chunk chunks. */
1326	RT_FLEXIBLE_ARRAY_EXTENSION
1327	uint64_t bmAllocated[RT_FLEXIBLE_ARRAY];
1328	} IEMTBALLOCATOR;
1329	/** Pointer to a TB allocator. */
1330	typedef struct IEMTBALLOCATOR *PIEMTBALLOCATOR;
1331
1332	/** Magic value for the TB allocator (Emmet Harley Cohen). */
1333	#define IEMTBALLOCATOR_MAGIC UINT32_C(0x19900525)
1334
1335
1336	/**
1337	* A per-CPU translation block cache (hash table).
1338	*
1339	* The hash table is allocated once during IEM initialization and size double
1340	* the max TB count, rounded up to the nearest power of two (so we can use and
1341	* AND mask rather than a rest division when hashing).
1342	*/
1343	typedef struct IEMTBCACHE
1344	{
1345	/** Magic value (IEMTBCACHE_MAGIC). */
1346	uint32_t uMagic;
1347	/** Size of the hash table. This is a power of two. */
1348	uint32_t cHash;
1349	/** The mask corresponding to cHash. */
1350	uint32_t uHashMask;
1351	uint32_t uPadding;
1352
1353	/** @name Statistics
1354	* @{ */
1355	/** Number of collisions ever. */
1356	STAMCOUNTER cCollisions;
1357
1358	/** Statistics: Number of TB lookup misses. */
1359	STAMCOUNTER cLookupMisses;
1360	/** Statistics: Number of TB lookup hits (debug only). */
1361	STAMCOUNTER cLookupHits;
1362	STAMCOUNTER auPadding2[3];
1363	/** Statistics: Collision list length pruning. */
1364	STAMPROFILE StatPrune;
1365	/** @} */
1366
1367	/** The hash table itself.
1368	* @note The lower 6 bits of the pointer is used for keeping the collision
1369	* list length, so we can take action when it grows too long.
1370	* This works because TBs are allocated using a 64 byte (or
1371	* higher) alignment from page aligned chunks of memory, so the lower
1372	* 6 bits of the address will always be zero.
1373	* See IEMTBCACHE_PTR_COUNT_MASK, IEMTBCACHE_PTR_MAKE and friends.
1374	*/
1375	RT_FLEXIBLE_ARRAY_EXTENSION
1376	PIEMTB apHash[RT_FLEXIBLE_ARRAY];
1377	} IEMTBCACHE;
1378	/** Pointer to a per-CPU translation block cahce. */
1379	typedef IEMTBCACHE *PIEMTBCACHE;
1380
1381	/** Magic value for IEMTBCACHE (Johnny O'Neal). */
1382	#define IEMTBCACHE_MAGIC UINT32_C(0x19561010)
1383
1384	/** The collision count mask for IEMTBCACHE::apHash entries. */
1385	#define IEMTBCACHE_PTR_COUNT_MASK ((uintptr_t)0x3f)
1386	/** The max collision count for IEMTBCACHE::apHash entries before pruning. */
1387	#define IEMTBCACHE_PTR_MAX_COUNT ((uintptr_t)0x30)
1388	/** Combine a TB pointer and a collision list length into a value for an
1389	* IEMTBCACHE::apHash entry. */
1390	#define IEMTBCACHE_PTR_MAKE(a_pTb, a_cCount) (PIEMTB)((uintptr_t)(a_pTb) \| (a_cCount))
1391	/** Combine a TB pointer and a collision list length into a value for an
1392	* IEMTBCACHE::apHash entry. */
1393	#define IEMTBCACHE_PTR_GET_TB(a_pHashEntry) (PIEMTB)((uintptr_t)(a_pHashEntry) & ~IEMTBCACHE_PTR_COUNT_MASK)
1394	/** Combine a TB pointer and a collision list length into a value for an
1395	* IEMTBCACHE::apHash entry. */
1396	#define IEMTBCACHE_PTR_GET_COUNT(a_pHashEntry) ((uintptr_t)(a_pHashEntry) & IEMTBCACHE_PTR_COUNT_MASK)
1397
1398	/**
1399	* Calculates the hash table slot for a TB from physical PC address and TB flags.
1400	*/
1401	#define IEMTBCACHE_HASH(a_paCache, a_fTbFlags, a_GCPhysPc) \
1402	IEMTBCACHE_HASH_NO_KEY_MASK(a_paCache, (a_fTbFlags) & IEMTB_F_KEY_MASK, a_GCPhysPc)
1403
1404	/**
1405	* Calculates the hash table slot for a TB from physical PC address and TB
1406	* flags, ASSUMING the caller has applied IEMTB_F_KEY_MASK to @a a_fTbFlags.
1407	*/
1408	#define IEMTBCACHE_HASH_NO_KEY_MASK(a_paCache, a_fTbFlags, a_GCPhysPc) \
1409	(((uint32_t)(a_GCPhysPc) ^ (a_fTbFlags)) & (a_paCache)->uHashMask)
1410
1411
1412	/** @name IEMBRANCHED_F_XXX - Branched indicator (IEMCPU::fTbBranched).
1413	*
1414	* These flags parallels the main IEM_CIMPL_F_BRANCH_XXX flags.
1415	*
1416	* @{ */
1417	/** Value if no branching happened recently. */
1418	#define IEMBRANCHED_F_NO UINT8_C(0x00)
1419	/** Flag set if direct branch, clear if absolute or indirect. */
1420	#define IEMBRANCHED_F_DIRECT UINT8_C(0x01)
1421	/** Flag set if indirect branch, clear if direct or relative. */
1422	#define IEMBRANCHED_F_INDIRECT UINT8_C(0x02)
1423	/** Flag set if relative branch, clear if absolute or indirect. */
1424	#define IEMBRANCHED_F_RELATIVE UINT8_C(0x04)
1425	/** Flag set if conditional branch, clear if unconditional. */
1426	#define IEMBRANCHED_F_CONDITIONAL UINT8_C(0x08)
1427	/** Flag set if it's a far branch. */
1428	#define IEMBRANCHED_F_FAR UINT8_C(0x10)
1429	/** Flag set if the stack pointer is modified. */
1430	#define IEMBRANCHED_F_STACK UINT8_C(0x20)
1431	/** Flag set if the stack pointer and (maybe) the stack segment are modified. */
1432	#define IEMBRANCHED_F_STACK_FAR UINT8_C(0x40)
1433	/** Flag set (by IEM_MC_REL_JMP_XXX) if it's a zero bytes relative jump. */
1434	#define IEMBRANCHED_F_ZERO UINT8_C(0x80)
1435	/** @} */
1436
1437
1438	/**
1439	* The per-CPU IEM state.
1440	*/
1441	typedef struct IEMCPU
1442	{
1443	/** Info status code that needs to be propagated to the IEM caller.
1444	* This cannot be passed internally, as it would complicate all success
1445	* checks within the interpreter making the code larger and almost impossible
1446	* to get right. Instead, we'll store status codes to pass on here. Each
1447	* source of these codes will perform appropriate sanity checks. */
1448	int32_t rcPassUp; /* 0x00 */
1449	/** Execution flag, IEM_F_XXX. */
1450	uint32_t fExec; /* 0x04 */
1451
1452	/** @name Decoder state.
1453	* @{ */
1454	#ifdef IEM_WITH_CODE_TLB
1455	/** The offset of the next instruction byte. */
1456	uint32_t offInstrNextByte; /* 0x08 */
1457	/** The number of bytes available at pbInstrBuf for the current instruction.
1458	* This takes the max opcode length into account so that doesn't need to be
1459	* checked separately. */
1460	uint32_t cbInstrBuf; /* 0x0c */
1461	/** Pointer to the page containing RIP, user specified buffer or abOpcode.
1462	* This can be NULL if the page isn't mappable for some reason, in which
1463	* case we'll do fallback stuff.
1464	*
1465	* If we're executing an instruction from a user specified buffer,
1466	* IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
1467	* aligned pointer but pointer to the user data.
1468	*
1469	* For instructions crossing pages, this will start on the first page and be
1470	* advanced to the next page by the time we've decoded the instruction. This
1471	* therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
1472	*/
1473	uint8_t const pbInstrBuf; / 0x10 */
1474	# if ARCH_BITS == 32
1475	uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
1476	# endif
1477	/** The program counter corresponding to pbInstrBuf.
1478	* This is set to a non-canonical address when we need to invalidate it. */
1479	uint64_t uInstrBufPc; /* 0x18 */
1480	/** The guest physical address corresponding to pbInstrBuf. */
1481	RTGCPHYS GCPhysInstrBuf; /* 0x20 */
1482	/** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
1483	* This takes the CS segment limit into account.
1484	* @note Set to zero when the code TLB is flushed to trigger TLB reload. */
1485	uint16_t cbInstrBufTotal; /* 0x28 */
1486	# ifndef IEM_WITH_OPAQUE_DECODER_STATE
1487	/** Offset into pbInstrBuf of the first byte of the current instruction.
1488	* Can be negative to efficiently handle cross page instructions. */
1489	int16_t offCurInstrStart; /* 0x2a */
1490
1491	/** The prefix mask (IEM_OP_PRF_XXX). */
1492	uint32_t fPrefixes; /* 0x2c */
1493	/** The extra REX ModR/M register field bit (REX.R << 3). */
1494	uint8_t uRexReg; /* 0x30 */
1495	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
1496	* (REX.B << 3). */
1497	uint8_t uRexB; /* 0x31 */
1498	/** The extra REX SIB index field bit (REX.X << 3). */
1499	uint8_t uRexIndex; /* 0x32 */
1500
1501	/** The effective segment register (X86_SREG_XXX). */
1502	uint8_t iEffSeg; /* 0x33 */
1503
1504	/** The offset of the ModR/M byte relative to the start of the instruction. */
1505	uint8_t offModRm; /* 0x34 */
1506
1507	# ifdef IEM_WITH_CODE_TLB_AND_OPCODE_BUF
1508	/** The current offset into abOpcode. */
1509	uint8_t offOpcode; /* 0x35 */
1510	# else
1511	uint8_t bUnused; /* 0x35 */
1512	# endif
1513	# else /* IEM_WITH_OPAQUE_DECODER_STATE */
1514	uint8_t abOpaqueDecoderPart1[0x36 - 0x2a];
1515	# endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1516
1517	#else /* !IEM_WITH_CODE_TLB */
1518	# ifndef IEM_WITH_OPAQUE_DECODER_STATE
1519	/** The size of what has currently been fetched into abOpcode. */
1520	uint8_t cbOpcode; /* 0x08 */
1521	/** The current offset into abOpcode. */
1522	uint8_t offOpcode; /* 0x09 */
1523	/** The offset of the ModR/M byte relative to the start of the instruction. */
1524	uint8_t offModRm; /* 0x0a */
1525
1526	/** The effective segment register (X86_SREG_XXX). */
1527	uint8_t iEffSeg; /* 0x0b */
1528
1529	/** The prefix mask (IEM_OP_PRF_XXX). */
1530	uint32_t fPrefixes; /* 0x0c */
1531	/** The extra REX ModR/M register field bit (REX.R << 3). */
1532	uint8_t uRexReg; /* 0x10 */
1533	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
1534	* (REX.B << 3). */
1535	uint8_t uRexB; /* 0x11 */
1536	/** The extra REX SIB index field bit (REX.X << 3). */
1537	uint8_t uRexIndex; /* 0x12 */
1538
1539	# else /* IEM_WITH_OPAQUE_DECODER_STATE */
1540	uint8_t abOpaqueDecoderPart1[0x13 - 0x08];
1541	# endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1542	#endif /* !IEM_WITH_CODE_TLB */
1543
1544	#ifndef IEM_WITH_OPAQUE_DECODER_STATE
1545	/** The effective operand mode. */
1546	IEMMODE enmEffOpSize; /* 0x36, 0x13 */
1547	/** The default addressing mode. */
1548	IEMMODE enmDefAddrMode; /* 0x37, 0x14 */
1549	/** The effective addressing mode. */
1550	IEMMODE enmEffAddrMode; /* 0x38, 0x15 */
1551	/** The default operand mode. */
1552	IEMMODE enmDefOpSize; /* 0x39, 0x16 */
1553
1554	/** Prefix index (VEX.pp) for two byte and three byte tables. */
1555	uint8_t idxPrefix; /* 0x3a, 0x17 */
1556	/** 3rd VEX/EVEX/XOP register.
1557	* Please use IEM_GET_EFFECTIVE_VVVV to access. */
1558	uint8_t uVex3rdReg; /* 0x3b, 0x18 */
1559	/** The VEX/EVEX/XOP length field. */
1560	uint8_t uVexLength; /* 0x3c, 0x19 */
1561	/** Additional EVEX stuff. */
1562	uint8_t fEvexStuff; /* 0x3d, 0x1a */
1563
1564	# ifndef IEM_WITH_CODE_TLB
1565	/** Explicit alignment padding. */
1566	uint8_t abAlignment2a[1]; /* 0x1b */
1567	# endif
1568	/** The FPU opcode (FOP). */
1569	uint16_t uFpuOpcode; /* 0x3e, 0x1c */
1570	# ifndef IEM_WITH_CODE_TLB
1571	/** Explicit alignment padding. */
1572	uint8_t abAlignment2b[2]; /* 0x1e */
1573	# endif
1574
1575	/** The opcode bytes. */
1576	uint8_t abOpcode[15]; /* 0x40, 0x20 */
1577	/** Explicit alignment padding. */
1578	# ifdef IEM_WITH_CODE_TLB
1579	//uint8_t abAlignment2c[0x4f - 0x4f]; /* 0x4f */
1580	# else
1581	uint8_t abAlignment2c[0x4f - 0x2f]; /* 0x2f */
1582	# endif
1583
1584	#else /* IEM_WITH_OPAQUE_DECODER_STATE */
1585	# ifdef IEM_WITH_CODE_TLB
1586	uint8_t abOpaqueDecoderPart2[0x4f - 0x36];
1587	# else
1588	uint8_t abOpaqueDecoderPart2[0x4f - 0x13];
1589	# endif
1590	#endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1591	/** @} */
1592
1593
1594	/** The number of active guest memory mappings. */
1595	uint8_t cActiveMappings; /* 0x4f, 0x4f */
1596
1597	/** Records for tracking guest memory mappings. */
1598	struct
1599	{
1600	/** The address of the mapped bytes. */
1601	R3R0PTRTYPE(void *) pv;
1602	/** The access flags (IEM_ACCESS_XXX).
1603	* IEM_ACCESS_INVALID if the entry is unused. */
1604	uint32_t fAccess;
1605	#if HC_ARCH_BITS == 64
1606	uint32_t u32Alignment4; /*< Alignment padding. /
1607	#endif
1608	} aMemMappings[3]; /* 0x50 LB 0x30 */
1609
1610	/** Locking records for the mapped memory. */
1611	union
1612	{
1613	PGMPAGEMAPLOCK Lock;
1614	uint64_t au64Padding[2];
1615	} aMemMappingLocks[3]; /* 0x80 LB 0x30 */
1616
1617	/** Bounce buffer info.
1618	* This runs in parallel to aMemMappings. */
1619	struct
1620	{
1621	/** The physical address of the first byte. */
1622	RTGCPHYS GCPhysFirst;
1623	/** The physical address of the second page. */
1624	RTGCPHYS GCPhysSecond;
1625	/** The number of bytes in the first page. */
1626	uint16_t cbFirst;
1627	/** The number of bytes in the second page. */
1628	uint16_t cbSecond;
1629	/** Whether it's unassigned memory. */
1630	bool fUnassigned;
1631	/** Explicit alignment padding. */
1632	bool afAlignment5[3];
1633	} aMemBbMappings[3]; /* 0xb0 LB 0x48 */
1634
1635	/** The flags of the current exception / interrupt. */
1636	uint32_t fCurXcpt; /* 0xf8 */
1637	/** The current exception / interrupt. */
1638	uint8_t uCurXcpt; /* 0xfc */
1639	/** Exception / interrupt recursion depth. */
1640	int8_t cXcptRecursions; /* 0xfb */
1641
1642	/** The next unused mapping index.
1643	* @todo try find room for this up with cActiveMappings. */
1644	uint8_t iNextMapping; /* 0xfd */
1645	uint8_t abAlignment7[1];
1646
1647	/** Bounce buffer storage.
1648	* This runs in parallel to aMemMappings and aMemBbMappings. */
1649	struct
1650	{
1651	uint8_t ab[512];
1652	} aBounceBuffers[3]; /* 0x100 LB 0x600 */
1653
1654
1655	/** Pointer set jump buffer - ring-3 context. */
1656	R3PTRTYPE(jmp_buf *) pJmpBufR3;
1657	/** Pointer set jump buffer - ring-0 context. */
1658	R0PTRTYPE(jmp_buf *) pJmpBufR0;
1659
1660	/** @todo Should move this near @a fCurXcpt later. */
1661	/** The CR2 for the current exception / interrupt. */
1662	uint64_t uCurXcptCr2;
1663	/** The error code for the current exception / interrupt. */
1664	uint32_t uCurXcptErr;
1665
1666	/** @name Statistics
1667	* @{ */
1668	/** The number of instructions we've executed. */
1669	uint32_t cInstructions;
1670	/** The number of potential exits. */
1671	uint32_t cPotentialExits;
1672	/** The number of bytes data or stack written (mostly for IEMExecOneEx).
1673	* This may contain uncommitted writes. */
1674	uint32_t cbWritten;
1675	/** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
1676	uint32_t cRetInstrNotImplemented;
1677	/** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
1678	uint32_t cRetAspectNotImplemented;
1679	/** Counts informational statuses returned (other than VINF_SUCCESS). */
1680	uint32_t cRetInfStatuses;
1681	/** Counts other error statuses returned. */
1682	uint32_t cRetErrStatuses;
1683	/** Number of times rcPassUp has been used. */
1684	uint32_t cRetPassUpStatus;
1685	/** Number of times RZ left with instruction commit pending for ring-3. */
1686	uint32_t cPendingCommit;
1687	/** Number of misaligned (host sense) atomic instruction accesses. */
1688	uint32_t cMisalignedAtomics;
1689	/** Number of long jumps. */
1690	uint32_t cLongJumps;
1691	/** @} */
1692
1693	/** @name Target CPU information.
1694	* @{ */
1695	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
1696	/** The target CPU. */
1697	uint8_t uTargetCpu;
1698	#else
1699	uint8_t bTargetCpuPadding;
1700	#endif
1701	/** For selecting assembly works matching the target CPU EFLAGS behaviour, see
1702	* IEMTARGETCPU_EFL_BEHAVIOR_XXX for values, with the 1st entry for when no
1703	* native host support and the 2nd for when there is.
1704	*
1705	* The two values are typically indexed by a g_CpumHostFeatures bit.
1706	*
1707	* This is for instance used for the BSF & BSR instructions where AMD and
1708	* Intel CPUs produce different EFLAGS. */
1709	uint8_t aidxTargetCpuEflFlavour[2];
1710
1711	/** The CPU vendor. */
1712	CPUMCPUVENDOR enmCpuVendor;
1713	/** @} */
1714
1715	/** @name Host CPU information.
1716	* @{ */
1717	/** The CPU vendor. */
1718	CPUMCPUVENDOR enmHostCpuVendor;
1719	/** @} */
1720
1721	/** Counts RDMSR \#GP(0) LogRel(). */
1722	uint8_t cLogRelRdMsr;
1723	/** Counts WRMSR \#GP(0) LogRel(). */
1724	uint8_t cLogRelWrMsr;
1725	/** Alignment padding. */
1726	uint8_t abAlignment9[42];
1727
1728	/** @name Recompilation
1729	* @{ */
1730	/** Pointer to the current translation block.
1731	* This can either be one being executed or one being compiled. */
1732	R3PTRTYPE(PIEMTB) pCurTbR3;
1733	#ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
1734	/** Frame pointer for the last native TB to execute. */
1735	R3PTRTYPE(void *) pvTbFramePointerR3;
1736	#else
1737	R3PTRTYPE(void *) pvUnusedR3;
1738	#endif
1739	/** Fixed TB used for threaded recompilation.
1740	* This is allocated once with maxed-out sizes and re-used afterwards. */
1741	R3PTRTYPE(PIEMTB) pThrdCompileTbR3;
1742	/** Pointer to the ring-3 TB cache for this EMT. */
1743	R3PTRTYPE(PIEMTBCACHE) pTbCacheR3;
1744	/** The PC (RIP) at the start of pCurTbR3/pCurTbR0.
1745	* The TBs are based on physical addresses, so this is needed to correleated
1746	* RIP to opcode bytes stored in the TB (AMD-V / VT-x). */
1747	uint64_t uCurTbStartPc;
1748	/** Number of threaded TBs executed. */
1749	uint64_t cTbExecThreaded;
1750	/** Number of native TBs executed. */
1751	uint64_t cTbExecNative;
1752	/** Whether we need to check the opcode bytes for the current instruction.
1753	* This is set by a previous instruction if it modified memory or similar. */
1754	bool fTbCheckOpcodes;
1755	/** Indicates whether and how we just branched - IEMBRANCHED_F_XXX. */
1756	uint8_t fTbBranched;
1757	/** Set when GCPhysInstrBuf is updated because of a page crossing. */
1758	bool fTbCrossedPage;
1759	/** Whether to end the current TB. */
1760	bool fEndTb;
1761	/** Number of instructions before we need emit an IRQ check call again.
1762	* This helps making sure we don't execute too long w/o checking for
1763	* interrupts and immediately following instructions that may enable
1764	* interrupts (e.g. POPF, IRET, STI). With STI an additional hack is
1765	* required to make sure we check following the next instruction as well, see
1766	* fTbCurInstrIsSti. */
1767	uint8_t cInstrTillIrqCheck;
1768	/** Indicates that the current instruction is an STI. This is set by the
1769	* iemCImpl_sti code and subsequently cleared by the recompiler. */
1770	bool fTbCurInstrIsSti;
1771	/** The size of the IEMTB::pabOpcodes allocation in pThrdCompileTbR3. */
1772	uint16_t cbOpcodesAllocated;
1773	/** The current instruction number in a native TB.
1774	* This is set by code that may trigger an unexpected TB exit (throw/longjmp)
1775	* and will be picked up by the TB execution loop. Only used when
1776	* IEMNATIVE_WITH_INSTRUCTION_COUNTING is defined. */
1777	uint8_t idxTbCurInstr;
1778	/** Spaced reserved for recompiler data / alignment. */
1779	bool afRecompilerStuff1[3];
1780	/** The virtual sync time at the last timer poll call. */
1781	uint32_t msRecompilerPollNow;
1782	/** The IEM_CIMPL_F_XXX mask for the current instruction. */
1783	uint32_t fTbCurInstr;
1784	/** The IEM_CIMPL_F_XXX mask for the previous instruction. */
1785	uint32_t fTbPrevInstr;
1786	/** Previous GCPhysInstrBuf value - only valid if fTbCrossedPage is set. */
1787	RTGCPHYS GCPhysInstrBufPrev;
1788	/** Strict: Tracking skipped EFLAGS calculations. Any bits set here are
1789	* currently not up to date in EFLAGS. */
1790	uint32_t fSkippingEFlags;
1791	uint32_t au32Padding[1];
1792	/** Pointer to the ring-3 TB allocator for this EMT. */
1793	R3PTRTYPE(PIEMTBALLOCATOR) pTbAllocatorR3;
1794	/** Pointer to the ring-3 executable memory allocator for this EMT. */
1795	R3PTRTYPE(struct IEMEXECMEMALLOCATOR *) pExecMemAllocatorR3;
1796	/** Pointer to the native recompiler state for ring-3. */
1797	R3PTRTYPE(struct IEMRECOMPILERSTATE *) pNativeRecompilerStateR3;
1798
1799	/** Statistics: Times TB execution was broken off before reaching the end. */
1800	STAMCOUNTER StatTbExecBreaks;
1801	/** Statistics: Times BltIn_CheckIrq breaks out of the TB. */
1802	STAMCOUNTER StatCheckIrqBreaks;
1803	/** Statistics: Times BltIn_CheckMode breaks out of the TB. */
1804	STAMCOUNTER StatCheckModeBreaks;
1805	/** Statistics: Times a post jump target check missed and had to find new TB. */
1806	STAMCOUNTER StatCheckBranchMisses;
1807	/** Statistics: Times a jump or page crossing required a TB with CS.LIM checking. */
1808	STAMCOUNTER StatCheckNeedCsLimChecking;
1809	/** Native TB statistics: Number of fully recompiled TBs. */
1810	STAMCOUNTER StatNativeFullyRecompiledTbs;
1811	/** Threaded TB statistics: Number of instructions per TB. */
1812	STAMPROFILE StatTbThreadedInstr;
1813	/** Threaded TB statistics: Number of calls per TB. */
1814	STAMPROFILE StatTbThreadedCalls;
1815	/** Native TB statistics: Native code size per TB. */
1816	STAMPROFILE StatTbNativeCode;
1817	/** Native TB statistics: Profiling native recompilation. */
1818	STAMPROFILE StatNativeRecompilation;
1819	/** Native TB statistics: Number of calls per TB that were recompiled properly. */
1820	STAMPROFILE StatNativeCallsRecompiled;
1821	/** Native TB statistics: Number of threaded calls per TB that weren't recompiled. */
1822	STAMPROFILE StatNativeCallsThreaded;
1823	/** Native recompiled execution: TLB hits for data fetches. */
1824	STAMCOUNTER StatNativeTlbHitsForFetch;
1825	/** Native recompiled execution: TLB hits for data stores. */
1826	STAMCOUNTER StatNativeTlbHitsForStore;
1827	/** Native recompiled execution: TLB hits for stack accesses. */
1828	STAMCOUNTER StatNativeTlbHitsForStack;
1829	/** Native recompiled execution: TLB hits for mapped accesses. */
1830	STAMCOUNTER StatNativeTlbHitsForMapped;
1831	/** Native recompiled execution: Code TLB misses for new page. */
1832	STAMCOUNTER StatNativeCodeTlbMissesNewPage;
1833	/** Native recompiled execution: Code TLB hits for new page. */
1834	STAMCOUNTER StatNativeCodeTlbHitsForNewPage;
1835	/** Native recompiled execution: Code TLB misses for new page with offset. */
1836	STAMCOUNTER StatNativeCodeTlbMissesNewPageWithOffset;
1837	/** Native recompiled execution: Code TLB hits for new page with offset. */
1838	STAMCOUNTER StatNativeCodeTlbHitsForNewPageWithOffset;
1839
1840	/** Native recompiler: Number of calls to iemNativeRegAllocFindFree. */
1841	STAMCOUNTER StatNativeRegFindFree;
1842	/** Native recompiler: Number of times iemNativeRegAllocFindFree needed
1843	* to free a variable. */
1844	STAMCOUNTER StatNativeRegFindFreeVar;
1845	/** Native recompiler: Number of times iemNativeRegAllocFindFree did
1846	* not need to free any variables. */
1847	STAMCOUNTER StatNativeRegFindFreeNoVar;
1848	/** Native recompiler: Liveness info freed shadowed guest registers in
1849	* iemNativeRegAllocFindFree. */
1850	STAMCOUNTER StatNativeRegFindFreeLivenessUnshadowed;
1851	/** Native recompiler: Liveness info helped with the allocation in
1852	* iemNativeRegAllocFindFree. */
1853	STAMCOUNTER StatNativeRegFindFreeLivenessHelped;
1854
1855	/** Native recompiler: Number of times status flags calc has been skipped. */
1856	STAMCOUNTER StatNativeEflSkippedArithmetic;
1857	/** Native recompiler: Number of times status flags calc has been skipped. */
1858	STAMCOUNTER StatNativeEflSkippedLogical;
1859
1860	/** Native recompiler: Number of opportunities to skip EFLAGS.CF updating. */
1861	STAMCOUNTER StatNativeLivenessEflCfSkippable;
1862	/** Native recompiler: Number of opportunities to skip EFLAGS.PF updating. */
1863	STAMCOUNTER StatNativeLivenessEflPfSkippable;
1864	/** Native recompiler: Number of opportunities to skip EFLAGS.AF updating. */
1865	STAMCOUNTER StatNativeLivenessEflAfSkippable;
1866	/** Native recompiler: Number of opportunities to skip EFLAGS.ZF updating. */
1867	STAMCOUNTER StatNativeLivenessEflZfSkippable;
1868	/** Native recompiler: Number of opportunities to skip EFLAGS.SF updating. */
1869	STAMCOUNTER StatNativeLivenessEflSfSkippable;
1870	/** Native recompiler: Number of opportunities to skip EFLAGS.OF updating. */
1871	STAMCOUNTER StatNativeLivenessEflOfSkippable;
1872	/** Native recompiler: Number of required EFLAGS.CF updates. */
1873	STAMCOUNTER StatNativeLivenessEflCfRequired;
1874	/** Native recompiler: Number of required EFLAGS.PF updates. */
1875	STAMCOUNTER StatNativeLivenessEflPfRequired;
1876	/** Native recompiler: Number of required EFLAGS.AF updates. */
1877	STAMCOUNTER StatNativeLivenessEflAfRequired;
1878	/** Native recompiler: Number of required EFLAGS.ZF updates. */
1879	STAMCOUNTER StatNativeLivenessEflZfRequired;
1880	/** Native recompiler: Number of required EFLAGS.SF updates. */
1881	STAMCOUNTER StatNativeLivenessEflSfRequired;
1882	/** Native recompiler: Number of required EFLAGS.OF updates. */
1883	STAMCOUNTER StatNativeLivenessEflOfRequired;
1884	/** Native recompiler: Number of potentially delayable EFLAGS.CF updates. */
1885	STAMCOUNTER StatNativeLivenessEflCfDelayable;
1886	/** Native recompiler: Number of potentially delayable EFLAGS.PF updates. */
1887	STAMCOUNTER StatNativeLivenessEflPfDelayable;
1888	/** Native recompiler: Number of potentially delayable EFLAGS.AF updates. */
1889	STAMCOUNTER StatNativeLivenessEflAfDelayable;
1890	/** Native recompiler: Number of potentially delayable EFLAGS.ZF updates. */
1891	STAMCOUNTER StatNativeLivenessEflZfDelayable;
1892	/** Native recompiler: Number of potentially delayable EFLAGS.SF updates. */
1893	STAMCOUNTER StatNativeLivenessEflSfDelayable;
1894	/** Native recompiler: Number of potentially delayable EFLAGS.OF updates. */
1895	STAMCOUNTER StatNativeLivenessEflOfDelayable;
1896
1897	/** Native recompiler: Number of potential PC updates in total. */
1898	STAMCOUNTER StatNativePcUpdateTotal;
1899	/** Native recompiler: Number of PC updates which could be delayed. */
1900	STAMCOUNTER StatNativePcUpdateDelayed;
1901
1902	#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
1903	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() checks. */
1904	STAMCOUNTER StatNativeMaybeDeviceNotAvailXcptCheckPotential;
1905	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() checks. */
1906	STAMCOUNTER StatNativeMaybeSseXcptCheckPotential;
1907	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() checks. */
1908	STAMCOUNTER StatNativeMaybeAvxXcptCheckPotential;
1909
1910	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() checks omitted. */
1911	STAMCOUNTER StatNativeMaybeDeviceNotAvailXcptCheckOmitted;
1912	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() checks omitted. */
1913	STAMCOUNTER StatNativeMaybeSseXcptCheckOmitted;
1914	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() checks omitted. */
1915	STAMCOUNTER StatNativeMaybeAvxXcptCheckOmitted;
1916	#endif
1917
1918	uint64_t au64Padding[2];
1919	/** @} */
1920
1921	/** Data TLB.
1922	* @remarks Must be 64-byte aligned. */
1923	IEMTLB DataTlb;
1924	/** Instruction TLB.
1925	* @remarks Must be 64-byte aligned. */
1926	IEMTLB CodeTlb;
1927
1928	/** Exception statistics. */
1929	STAMCOUNTER aStatXcpts[32];
1930	/** Interrupt statistics. */
1931	uint32_t aStatInts[256];
1932
1933	#if defined(VBOX_WITH_STATISTICS) && !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
1934	/** Instruction statistics for ring-0/raw-mode. */
1935	IEMINSTRSTATS StatsRZ;
1936	/** Instruction statistics for ring-3. */
1937	IEMINSTRSTATS StatsR3;
1938	# ifdef VBOX_WITH_IEM_RECOMPILER
1939	/** Statistics per threaded function call.
1940	* Updated by both the threaded and native recompilers. */
1941	uint32_t acThreadedFuncStats[0x5000 /20480/];
1942	# endif
1943	#endif
1944	} IEMCPU;
1945	AssertCompileMemberOffset(IEMCPU, cActiveMappings, 0x4f);
1946	AssertCompileMemberAlignment(IEMCPU, aMemMappings, 16);
1947	AssertCompileMemberAlignment(IEMCPU, aMemMappingLocks, 16);
1948	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 64);
1949	AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
1950	AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
1951
1952	/** Pointer to the per-CPU IEM state. */
1953	typedef IEMCPU *PIEMCPU;
1954	/** Pointer to the const per-CPU IEM state. */
1955	typedef IEMCPU const *PCIEMCPU;
1956
1957
1958	/** @def IEM_GET_CTX
1959	* Gets the guest CPU context for the calling EMT.
1960	* @returns PCPUMCTX
1961	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1962	*/
1963	#define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
1964
1965	/** @def IEM_CTX_ASSERT
1966	* Asserts that the @a a_fExtrnMbz is present in the CPU context.
1967	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1968	* @param a_fExtrnMbz The mask of CPUMCTX_EXTRN_XXX flags that must be zero.
1969	*/
1970	#define IEM_CTX_ASSERT(a_pVCpu, a_fExtrnMbz) \
1971	AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
1972	("fExtrn=%#RX64 & fExtrnMbz=%#RX64 -> %#RX64\n", \
1973	(a_pVCpu)->cpum.GstCtx.fExtrn, (a_fExtrnMbz), (a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz) ))
1974
1975	/** @def IEM_CTX_IMPORT_RET
1976	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
1977	*
1978	* Will call the keep to import the bits as needed.
1979	*
1980	* Returns on import failure.
1981	*
1982	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1983	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
1984	*/
1985	#define IEM_CTX_IMPORT_RET(a_pVCpu, a_fExtrnImport) \
1986	do { \
1987	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
1988	{ /* likely */ } \
1989	else \
1990	{ \
1991	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
1992	AssertRCReturn(rcCtxImport, rcCtxImport); \
1993	} \
1994	} while (0)
1995
1996	/** @def IEM_CTX_IMPORT_NORET
1997	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
1998	*
1999	* Will call the keep to import the bits as needed.
2000	*
2001	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2002	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
2003	*/
2004	#define IEM_CTX_IMPORT_NORET(a_pVCpu, a_fExtrnImport) \
2005	do { \
2006	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
2007	{ /* likely */ } \
2008	else \
2009	{ \
2010	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
2011	AssertLogRelRC(rcCtxImport); \
2012	} \
2013	} while (0)
2014
2015	/** @def IEM_CTX_IMPORT_JMP
2016	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
2017	*
2018	* Will call the keep to import the bits as needed.
2019	*
2020	* Jumps on import failure.
2021	*
2022	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2023	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
2024	*/
2025	#define IEM_CTX_IMPORT_JMP(a_pVCpu, a_fExtrnImport) \
2026	do { \
2027	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
2028	{ /* likely */ } \
2029	else \
2030	{ \
2031	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
2032	AssertRCStmt(rcCtxImport, IEM_DO_LONGJMP(pVCpu, rcCtxImport)); \
2033	} \
2034	} while (0)
2035
2036
2037
2038	/** @def IEM_GET_TARGET_CPU
2039	* Gets the current IEMTARGETCPU value.
2040	* @returns IEMTARGETCPU value.
2041	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2042	*/
2043	#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
2044	# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
2045	#else
2046	# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
2047	#endif
2048
2049	/** @def IEM_GET_INSTR_LEN
2050	* Gets the instruction length. */
2051	#ifdef IEM_WITH_CODE_TLB
2052	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
2053	#else
2054	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
2055	#endif
2056
2057	/** @def IEM_TRY_SETJMP
2058	* Wrapper around setjmp / try, hiding all the ugly differences.
2059	*
2060	* @note Use with extreme care as this is a fragile macro.
2061	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2062	* @param a_rcTarget The variable that should receive the status code in case
2063	* of a longjmp/throw.
2064	*/
2065	/** @def IEM_TRY_SETJMP_AGAIN
2066	* For when setjmp / try is used again in the same variable scope as a previous
2067	* IEM_TRY_SETJMP invocation.
2068	*/
2069	/** @def IEM_CATCH_LONGJMP_BEGIN
2070	* Start wrapper for catch / setjmp-else.
2071	*
2072	* This will set up a scope.
2073	*
2074	* @note Use with extreme care as this is a fragile macro.
2075	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2076	* @param a_rcTarget The variable that should receive the status code in case
2077	* of a longjmp/throw.
2078	*/
2079	/** @def IEM_CATCH_LONGJMP_END
2080	* End wrapper for catch / setjmp-else.
2081	*
2082	* This will close the scope set up by IEM_CATCH_LONGJMP_BEGIN and clean up the
2083	* state.
2084	*
2085	* @note Use with extreme care as this is a fragile macro.
2086	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2087	*/
2088	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
2089	# ifdef IEM_WITH_THROW_CATCH
2090	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
2091	a_rcTarget = VINF_SUCCESS; \
2092	try
2093	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
2094	IEM_TRY_SETJMP(a_pVCpu, a_rcTarget)
2095	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
2096	catch (int rcThrown) \
2097	{ \
2098	a_rcTarget = rcThrown
2099	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
2100	} \
2101	((void)0)
2102	# else /* !IEM_WITH_THROW_CATCH */
2103	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
2104	jmp_buf JmpBuf; \
2105	jmp_buf * volatile pSavedJmpBuf = (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf); \
2106	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
2107	if ((rcStrict = setjmp(JmpBuf)) == 0)
2108	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
2109	pSavedJmpBuf = (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf); \
2110	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
2111	if ((rcStrict = setjmp(JmpBuf)) == 0)
2112	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
2113	else \
2114	{ \
2115	((void)0)
2116	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
2117	} \
2118	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = pSavedJmpBuf
2119	# endif /* !IEM_WITH_THROW_CATCH */
2120	#endif /* IEM_WITH_SETJMP */
2121
2122
2123	/**
2124	* Shared per-VM IEM data.
2125	*/
2126	typedef struct IEM
2127	{
2128	/** The VMX APIC-access page handler type. */
2129	PGMPHYSHANDLERTYPE hVmxApicAccessPage;
2130	#ifndef VBOX_WITHOUT_CPUID_HOST_CALL
2131	/** Set if the CPUID host call functionality is enabled. */
2132	bool fCpuIdHostCall;
2133	#endif
2134	} IEM;
2135
2136
2137
2138	/** @name IEM_ACCESS_XXX - Access details.
2139	* @{ */
2140	#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
2141	#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
2142	#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
2143	#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
2144	#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
2145	#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
2146	#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
2147	#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
2148	#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
2149	#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
2150	/** The writes are partial, so if initialize the bounce buffer with the
2151	* orignal RAM content. */
2152	#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
2153	/** Used in aMemMappings to indicate that the entry is bounce buffered. */
2154	#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
2155	/** Bounce buffer with ring-3 write pending, first page. */
2156	#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
2157	/** Bounce buffer with ring-3 write pending, second page. */
2158	#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
2159	/** Not locked, accessed via the TLB. */
2160	#define IEM_ACCESS_NOT_LOCKED UINT32_C(0x00001000)
2161	/** Atomic access.
2162	* This enables special alignment checks and the VINF_EM_EMULATE_SPLIT_LOCK
2163	* fallback for misaligned stuff. See @bugref{10547}. */
2164	#define IEM_ACCESS_ATOMIC UINT32_C(0x00002000)
2165	/** Valid bit mask. */
2166	#define IEM_ACCESS_VALID_MASK UINT32_C(0x00003fff)
2167	/** Shift count for the TLB flags (upper word). */
2168	#define IEM_ACCESS_SHIFT_TLB_FLAGS 16
2169
2170	/** Atomic read+write data alias. */
2171	#define IEM_ACCESS_DATA_ATOMIC (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA \| IEM_ACCESS_ATOMIC)
2172	/** Read+write data alias. */
2173	#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
2174	/** Write data alias. */
2175	#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
2176	/** Read data alias. */
2177	#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_DATA)
2178	/** Instruction fetch alias. */
2179	#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_WHAT_CODE)
2180	/** Stack write alias. */
2181	#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
2182	/** Stack read alias. */
2183	#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_STACK)
2184	/** Stack read+write alias. */
2185	#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
2186	/** Read system table alias. */
2187	#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_SYS)
2188	/** Read+write system table alias. */
2189	#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_SYS)
2190	/** @} */
2191
2192	/** @name Prefix constants (IEMCPU::fPrefixes)
2193	* @{ */
2194	#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /*< CS segment prefix (0x2e). /
2195	#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /*< SS segment prefix (0x36). /
2196	#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /*< DS segment prefix (0x3e). /
2197	#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /*< ES segment prefix (0x26). /
2198	#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /*< FS segment prefix (0x64). /
2199	#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /*< GS segment prefix (0x65). /
2200	#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
2201
2202	#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /*< Operand size prefix (0x66). /
2203	#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /*< REX.W prefix (0x48-0x4f). /
2204	#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /*< Address size prefix (0x67). /
2205
2206	#define IEM_OP_PRF_LOCK RT_BIT_32(16) /*< Lock prefix (0xf0). /
2207	#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /*< Repeat-not-zero prefix (0xf2). /
2208	#define IEM_OP_PRF_REPZ RT_BIT_32(18) /*< Repeat-if-zero prefix (0xf3). /
2209
2210	#define IEM_OP_PRF_REX RT_BIT_32(24) /*< Any REX prefix (0x40-0x4f). /
2211	#define IEM_OP_PRF_REX_B RT_BIT_32(25) /*< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). /
2212	#define IEM_OP_PRF_REX_X RT_BIT_32(26) /*< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). /
2213	#define IEM_OP_PRF_REX_R RT_BIT_32(27) /*< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). /
2214	/** Mask with all the REX prefix flags.
2215	* This is generally for use when needing to undo the REX prefixes when they
2216	* are followed legacy prefixes and therefore does not immediately preceed
2217	* the first opcode byte.
2218	* For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
2219	#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX \| IEM_OP_PRF_REX_R \| IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X \| IEM_OP_PRF_SIZE_REX_W )
2220
2221	#define IEM_OP_PRF_VEX RT_BIT_32(28) /*< Indiciates VEX prefix. /
2222	#define IEM_OP_PRF_EVEX RT_BIT_32(29) /*< Indiciates EVEX prefix. /
2223	#define IEM_OP_PRF_XOP RT_BIT_32(30) /*< Indiciates XOP prefix. /
2224	/** @} */
2225
2226	/** @name IEMOPFORM_XXX - Opcode forms
2227	* @note These are ORed together with IEMOPHINT_XXX.
2228	* @{ */
2229	/** ModR/M: reg, r/m */
2230	#define IEMOPFORM_RM 0
2231	/** ModR/M: reg, r/m (register) */
2232	#define IEMOPFORM_RM_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
2233	/** ModR/M: reg, r/m (memory) */
2234	#define IEMOPFORM_RM_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
2235	/** ModR/M: reg, r/m, imm */
2236	#define IEMOPFORM_RMI 1
2237	/** ModR/M: reg, r/m (register), imm */
2238	#define IEMOPFORM_RMI_REG (IEMOPFORM_RMI \| IEMOPFORM_MOD3)
2239	/** ModR/M: reg, r/m (memory), imm */
2240	#define IEMOPFORM_RMI_MEM (IEMOPFORM_RMI \| IEMOPFORM_NOT_MOD3)
2241	/** ModR/M: reg, r/m, xmm0 */
2242	#define IEMOPFORM_RM0 2
2243	/** ModR/M: reg, r/m (register), xmm0 */
2244	#define IEMOPFORM_RM0_REG (IEMOPFORM_RM0 \| IEMOPFORM_MOD3)
2245	/** ModR/M: reg, r/m (memory), xmm0 */
2246	#define IEMOPFORM_RM0_MEM (IEMOPFORM_RM0 \| IEMOPFORM_NOT_MOD3)
2247	/** ModR/M: r/m, reg */
2248	#define IEMOPFORM_MR 3
2249	/** ModR/M: r/m (register), reg */
2250	#define IEMOPFORM_MR_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
2251	/** ModR/M: r/m (memory), reg */
2252	#define IEMOPFORM_MR_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
2253	/** ModR/M: r/m, reg, imm */
2254	#define IEMOPFORM_MRI 4
2255	/** ModR/M: r/m (register), reg, imm */
2256	#define IEMOPFORM_MRI_REG (IEMOPFORM_MRI \| IEMOPFORM_MOD3)
2257	/** ModR/M: r/m (memory), reg, imm */
2258	#define IEMOPFORM_MRI_MEM (IEMOPFORM_MRI \| IEMOPFORM_NOT_MOD3)
2259	/** ModR/M: r/m only */
2260	#define IEMOPFORM_M 5
2261	/** ModR/M: r/m only (register). */
2262	#define IEMOPFORM_M_REG (IEMOPFORM_M \| IEMOPFORM_MOD3)
2263	/** ModR/M: r/m only (memory). */
2264	#define IEMOPFORM_M_MEM (IEMOPFORM_M \| IEMOPFORM_NOT_MOD3)
2265	/** ModR/M: r/m, imm */
2266	#define IEMOPFORM_MI 6
2267	/** ModR/M: r/m (register), imm */
2268	#define IEMOPFORM_MI_REG (IEMOPFORM_MI \| IEMOPFORM_MOD3)
2269	/** ModR/M: r/m (memory), imm */
2270	#define IEMOPFORM_MI_MEM (IEMOPFORM_MI \| IEMOPFORM_NOT_MOD3)
2271	/** ModR/M: r/m, 1 (shift and rotate instructions) */
2272	#define IEMOPFORM_M1 7
2273	/** ModR/M: r/m (register), 1. */
2274	#define IEMOPFORM_M1_REG (IEMOPFORM_M1 \| IEMOPFORM_MOD3)
2275	/** ModR/M: r/m (memory), 1. */
2276	#define IEMOPFORM_M1_MEM (IEMOPFORM_M1 \| IEMOPFORM_NOT_MOD3)
2277	/** ModR/M: r/m, CL (shift and rotate instructions)
2278	* @todo This should just've been a generic fixed register. But the python
2279	* code doesn't needs more convincing. */
2280	#define IEMOPFORM_M_CL 8
2281	/** ModR/M: r/m (register), CL. */
2282	#define IEMOPFORM_M_CL_REG (IEMOPFORM_M_CL \| IEMOPFORM_MOD3)
2283	/** ModR/M: r/m (memory), CL. */
2284	#define IEMOPFORM_M_CL_MEM (IEMOPFORM_M_CL \| IEMOPFORM_NOT_MOD3)
2285	/** ModR/M: reg only */
2286	#define IEMOPFORM_R 9
2287
2288	/** VEX+ModR/M: reg, r/m */
2289	#define IEMOPFORM_VEX_RM 16
2290	/** VEX+ModR/M: reg, r/m (register) */
2291	#define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM \| IEMOPFORM_MOD3)
2292	/** VEX+ModR/M: reg, r/m (memory) */
2293	#define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM \| IEMOPFORM_NOT_MOD3)
2294	/** VEX+ModR/M: r/m, reg */
2295	#define IEMOPFORM_VEX_MR 17
2296	/** VEX+ModR/M: r/m (register), reg */
2297	#define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR \| IEMOPFORM_MOD3)
2298	/** VEX+ModR/M: r/m (memory), reg */
2299	#define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR \| IEMOPFORM_NOT_MOD3)
2300	/** VEX+ModR/M: r/m, reg, imm8 */
2301	#define IEMOPFORM_VEX_MRI 18
2302	/** VEX+ModR/M: r/m (register), reg, imm8 */
2303	#define IEMOPFORM_VEX_MRI_REG (IEMOPFORM_VEX_MRI \| IEMOPFORM_MOD3)
2304	/** VEX+ModR/M: r/m (memory), reg, imm8 */
2305	#define IEMOPFORM_VEX_MRI_MEM (IEMOPFORM_VEX_MRI \| IEMOPFORM_NOT_MOD3)
2306	/** VEX+ModR/M: r/m only */
2307	#define IEMOPFORM_VEX_M 19
2308	/** VEX+ModR/M: r/m only (register). */
2309	#define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M \| IEMOPFORM_MOD3)
2310	/** VEX+ModR/M: r/m only (memory). */
2311	#define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M \| IEMOPFORM_NOT_MOD3)
2312	/** VEX+ModR/M: reg only */
2313	#define IEMOPFORM_VEX_R 20
2314	/** VEX+ModR/M: reg, vvvv, r/m */
2315	#define IEMOPFORM_VEX_RVM 21
2316	/** VEX+ModR/M: reg, vvvv, r/m (register). */
2317	#define IEMOPFORM_VEX_RVM_REG (IEMOPFORM_VEX_RVM \| IEMOPFORM_MOD3)
2318	/** VEX+ModR/M: reg, vvvv, r/m (memory). */
2319	#define IEMOPFORM_VEX_RVM_MEM (IEMOPFORM_VEX_RVM \| IEMOPFORM_NOT_MOD3)
2320	/** VEX+ModR/M: reg, vvvv, r/m, imm */
2321	#define IEMOPFORM_VEX_RVMI 22
2322	/** VEX+ModR/M: reg, vvvv, r/m (register), imm. */
2323	#define IEMOPFORM_VEX_RVMI_REG (IEMOPFORM_VEX_RVMI \| IEMOPFORM_MOD3)
2324	/** VEX+ModR/M: reg, vvvv, r/m (memory), imm. */
2325	#define IEMOPFORM_VEX_RVMI_MEM (IEMOPFORM_VEX_RVMI \| IEMOPFORM_NOT_MOD3)
2326	/** VEX+ModR/M: reg, vvvv, r/m, imm(reg) */
2327	#define IEMOPFORM_VEX_RVMR 23
2328	/** VEX+ModR/M: reg, vvvv, r/m (register), imm(reg). */
2329	#define IEMOPFORM_VEX_RVMR_REG (IEMOPFORM_VEX_RVMI \| IEMOPFORM_MOD3)
2330	/** VEX+ModR/M: reg, vvvv, r/m (memory), imm(reg). */
2331	#define IEMOPFORM_VEX_RVMR_MEM (IEMOPFORM_VEX_RVMI \| IEMOPFORM_NOT_MOD3)
2332	/** VEX+ModR/M: reg, r/m, vvvv */
2333	#define IEMOPFORM_VEX_RMV 24
2334	/** VEX+ModR/M: reg, r/m, vvvv (register). */
2335	#define IEMOPFORM_VEX_RMV_REG (IEMOPFORM_VEX_RMV \| IEMOPFORM_MOD3)
2336	/** VEX+ModR/M: reg, r/m, vvvv (memory). */
2337	#define IEMOPFORM_VEX_RMV_MEM (IEMOPFORM_VEX_RMV \| IEMOPFORM_NOT_MOD3)
2338	/** VEX+ModR/M: reg, r/m, imm8 */
2339	#define IEMOPFORM_VEX_RMI 25
2340	/** VEX+ModR/M: reg, r/m, imm8 (register). */
2341	#define IEMOPFORM_VEX_RMI_REG (IEMOPFORM_VEX_RMI \| IEMOPFORM_MOD3)
2342	/** VEX+ModR/M: reg, r/m, imm8 (memory). */
2343	#define IEMOPFORM_VEX_RMI_MEM (IEMOPFORM_VEX_RMI \| IEMOPFORM_NOT_MOD3)
2344	/** VEX+ModR/M: r/m, vvvv, reg */
2345	#define IEMOPFORM_VEX_MVR 26
2346	/** VEX+ModR/M: r/m, vvvv, reg (register) */
2347	#define IEMOPFORM_VEX_MVR_REG (IEMOPFORM_VEX_MVR \| IEMOPFORM_MOD3)
2348	/** VEX+ModR/M: r/m, vvvv, reg (memory) */
2349	#define IEMOPFORM_VEX_MVR_MEM (IEMOPFORM_VEX_MVR \| IEMOPFORM_NOT_MOD3)
2350	/** VEX+ModR/M+/n: vvvv, r/m */
2351	#define IEMOPFORM_VEX_VM 27
2352	/** VEX+ModR/M+/n: vvvv, r/m (register) */
2353	#define IEMOPFORM_VEX_VM_REG (IEMOPFORM_VEX_VM \| IEMOPFORM_MOD3)
2354	/** VEX+ModR/M+/n: vvvv, r/m (memory) */
2355	#define IEMOPFORM_VEX_VM_MEM (IEMOPFORM_VEX_VM \| IEMOPFORM_NOT_MOD3)
2356	/** VEX+ModR/M+/n: vvvv, r/m, imm8 */
2357	#define IEMOPFORM_VEX_VMI 28
2358	/** VEX+ModR/M+/n: vvvv, r/m, imm8 (register) */
2359	#define IEMOPFORM_VEX_VMI_REG (IEMOPFORM_VEX_VMI \| IEMOPFORM_MOD3)
2360	/** VEX+ModR/M+/n: vvvv, r/m, imm8 (memory) */
2361	#define IEMOPFORM_VEX_VMI_MEM (IEMOPFORM_VEX_VMI \| IEMOPFORM_NOT_MOD3)
2362
2363	/** Fixed register instruction, no R/M. */
2364	#define IEMOPFORM_FIXED 32
2365
2366	/** The r/m is a register. */
2367	#define IEMOPFORM_MOD3 RT_BIT_32(8)
2368	/** The r/m is a memory access. */
2369	#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
2370	/** @} */
2371
2372	/** @name IEMOPHINT_XXX - Additional Opcode Hints
2373	* @note These are ORed together with IEMOPFORM_XXX.
2374	* @{ */
2375	/** Ignores the operand size prefix (66h). */
2376	#define IEMOPHINT_IGNORES_OZ_PFX RT_BIT_32(10)
2377	/** Ignores REX.W (aka WIG). */
2378	#define IEMOPHINT_IGNORES_REXW RT_BIT_32(11)
2379	/** Both the operand size prefixes (66h + REX.W) are ignored. */
2380	#define IEMOPHINT_IGNORES_OP_SIZES (IEMOPHINT_IGNORES_OZ_PFX \| IEMOPHINT_IGNORES_REXW)
2381	/** Allowed with the lock prefix. */
2382	#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
2383	/** The VEX.L value is ignored (aka LIG). */
2384	#define IEMOPHINT_VEX_L_IGNORED RT_BIT_32(12)
2385	/** The VEX.L value must be zero (i.e. 128-bit width only). */
2386	#define IEMOPHINT_VEX_L_ZERO RT_BIT_32(13)
2387	/** The VEX.L value must be one (i.e. 256-bit width only). */
2388	#define IEMOPHINT_VEX_L_ONE RT_BIT_32(14)
2389	/** The VEX.V value must be zero. */
2390	#define IEMOPHINT_VEX_V_ZERO RT_BIT_32(15)
2391	/** The REX.W/VEX.V value must be zero. */
2392	#define IEMOPHINT_REX_W_ZERO RT_BIT_32(16)
2393	#define IEMOPHINT_VEX_W_ZERO IEMOPHINT_REX_W_ZERO
2394	/** The REX.W/VEX.V value must be one. */
2395	#define IEMOPHINT_REX_W_ONE RT_BIT_32(17)
2396	#define IEMOPHINT_VEX_W_ONE IEMOPHINT_REX_W_ONE
2397
2398	/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
2399	#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
2400	/** @} */
2401
2402	/**
2403	* Possible hardware task switch sources.
2404	*/
2405	typedef enum IEMTASKSWITCH
2406	{
2407	/** Task switch caused by an interrupt/exception. */
2408	IEMTASKSWITCH_INT_XCPT = 1,
2409	/** Task switch caused by a far CALL. */
2410	IEMTASKSWITCH_CALL,
2411	/** Task switch caused by a far JMP. */
2412	IEMTASKSWITCH_JUMP,
2413	/** Task switch caused by an IRET. */
2414	IEMTASKSWITCH_IRET
2415	} IEMTASKSWITCH;
2416	AssertCompileSize(IEMTASKSWITCH, 4);
2417
2418	/**
2419	* Possible CrX load (write) sources.
2420	*/
2421	typedef enum IEMACCESSCRX
2422	{
2423	/** CrX access caused by 'mov crX' instruction. */
2424	IEMACCESSCRX_MOV_CRX,
2425	/** CrX (CR0) write caused by 'lmsw' instruction. */
2426	IEMACCESSCRX_LMSW,
2427	/** CrX (CR0) write caused by 'clts' instruction. */
2428	IEMACCESSCRX_CLTS,
2429	/** CrX (CR0) read caused by 'smsw' instruction. */
2430	IEMACCESSCRX_SMSW
2431	} IEMACCESSCRX;
2432
2433	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2434	/** @name IEM_SLAT_FAIL_XXX - Second-level address translation failure information.
2435	*
2436	* These flags provide further context to SLAT page-walk failures that could not be
2437	* determined by PGM (e.g, PGM is not privy to memory access permissions).
2438	*
2439	* @{
2440	*/
2441	/** Translating a nested-guest linear address failed accessing a nested-guest
2442	* physical address. */
2443	# define IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR RT_BIT_32(0)
2444	/** Translating a nested-guest linear address failed accessing a
2445	* paging-structure entry or updating accessed/dirty bits. */
2446	# define IEM_SLAT_FAIL_LINEAR_TO_PAGE_TABLE RT_BIT_32(1)
2447	/** @} */
2448
2449	DECLCALLBACK(FNPGMPHYSHANDLER) iemVmxApicAccessPageHandler;
2450	# ifndef IN_RING3
2451	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) iemVmxApicAccessPagePfHandler;
2452	# endif
2453	#endif
2454
2455	/**
2456	* Indicates to the verifier that the given flag set is undefined.
2457	*
2458	* Can be invoked again to add more flags.
2459	*
2460	* This is a NOOP if the verifier isn't compiled in.
2461	*
2462	* @note We're temporarily keeping this until code is converted to new
2463	* disassembler style opcode handling.
2464	*/
2465	#define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
2466
2467
2468	/** @def IEM_DECL_IMPL_TYPE
2469	* For typedef'ing an instruction implementation function.
2470	*
2471	* @param a_RetType The return type.
2472	* @param a_Name The name of the type.
2473	* @param a_ArgList The argument list enclosed in parentheses.
2474	*/
2475
2476	/** @def IEM_DECL_IMPL_DEF
2477	* For defining an instruction implementation function.
2478	*
2479	* @param a_RetType The return type.
2480	* @param a_Name The name of the type.
2481	* @param a_ArgList The argument list enclosed in parentheses.
2482	*/
2483
2484	#if defined(__GNUC__) && defined(RT_ARCH_X86)
2485	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2486	__attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
2487	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2488	__attribute__((__fastcall__, __nothrow__)) DECL_HIDDEN_ONLY(a_RetType) a_Name a_ArgList
2489	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2490	__attribute__((__fastcall__, __nothrow__)) DECL_HIDDEN_ONLY(a_RetType) a_Name a_ArgList
2491
2492	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
2493	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2494	a_RetType (__fastcall a_Name) a_ArgList
2495	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2496	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
2497	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2498	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
2499
2500	#elif __cplusplus >= 201700 /* P0012R1 support */
2501	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2502	a_RetType (VBOXCALL a_Name) a_ArgList RT_NOEXCEPT
2503	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2504	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList RT_NOEXCEPT
2505	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2506	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList RT_NOEXCEPT
2507
2508	#else
2509	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2510	a_RetType (VBOXCALL a_Name) a_ArgList
2511	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2512	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList
2513	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2514	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList
2515
2516	#endif
2517
2518	/** Defined in IEMAllAImplC.cpp but also used by IEMAllAImplA.asm. */
2519	RT_C_DECLS_BEGIN
2520	extern uint8_t const g_afParity[256];
2521	RT_C_DECLS_END
2522
2523
2524	/** @name Arithmetic assignment operations on bytes (binary).
2525	* @{ */
2526	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU8, (uint8_t pu8Dst, uint8_t u8Src, uint32_t pEFlags));
2527	typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
2528	FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
2529	FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
2530	FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
2531	FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
2532	FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
2533	FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
2534	FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
2535	/** @} */
2536
2537	/** @name Arithmetic assignment operations on words (binary).
2538	* @{ */
2539	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU16, (uint16_t pu16Dst, uint16_t u16Src, uint32_t pEFlags));
2540	typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
2541	FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
2542	FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
2543	FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
2544	FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
2545	FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
2546	FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
2547	FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
2548	/** @} */
2549
2550	/** @name Arithmetic assignment operations on double words (binary).
2551	* @{ */
2552	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU32, (uint32_t pu32Dst, uint32_t u32Src, uint32_t pEFlags));
2553	typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
2554	FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
2555	FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
2556	FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
2557	FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
2558	FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
2559	FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
2560	FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
2561	FNIEMAIMPLBINU32 iemAImpl_blsi_u32, iemAImpl_blsi_u32_fallback;
2562	FNIEMAIMPLBINU32 iemAImpl_blsr_u32, iemAImpl_blsr_u32_fallback;
2563	FNIEMAIMPLBINU32 iemAImpl_blsmsk_u32, iemAImpl_blsmsk_u32_fallback;
2564	/** @} */
2565
2566	/** @name Arithmetic assignment operations on quad words (binary).
2567	* @{ */
2568	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU64, (uint64_t pu64Dst, uint64_t u64Src, uint32_t pEFlags));
2569	typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
2570	FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
2571	FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
2572	FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
2573	FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
2574	FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
2575	FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
2576	FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
2577	FNIEMAIMPLBINU64 iemAImpl_blsi_u64, iemAImpl_blsi_u64_fallback;
2578	FNIEMAIMPLBINU64 iemAImpl_blsr_u64, iemAImpl_blsr_u64_fallback;
2579	FNIEMAIMPLBINU64 iemAImpl_blsmsk_u64, iemAImpl_blsmsk_u64_fallback;
2580	/** @} */
2581
2582	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINROU8,(uint8_t const pu8Dst, uint8_t u8Src, uint32_t pEFlags));
2583	typedef FNIEMAIMPLBINROU8 *PFNIEMAIMPLBINROU8;
2584	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINROU16,(uint16_t const pu16Dst, uint16_t u16Src, uint32_t pEFlags));
2585	typedef FNIEMAIMPLBINROU16 *PFNIEMAIMPLBINROU16;
2586	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINROU32,(uint32_t const pu32Dst, uint32_t u32Src, uint32_t pEFlags));
2587	typedef FNIEMAIMPLBINROU32 *PFNIEMAIMPLBINROU32;
2588	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINROU64,(uint64_t const pu64Dst, uint64_t u64Src, uint32_t pEFlags));
2589	typedef FNIEMAIMPLBINROU64 *PFNIEMAIMPLBINROU64;
2590
2591	/** @name Compare operations (thrown in with the binary ops).
2592	* @{ */
2593	FNIEMAIMPLBINROU8 iemAImpl_cmp_u8;
2594	FNIEMAIMPLBINROU16 iemAImpl_cmp_u16;
2595	FNIEMAIMPLBINROU32 iemAImpl_cmp_u32;
2596	FNIEMAIMPLBINROU64 iemAImpl_cmp_u64;
2597	/** @} */
2598
2599	/** @name Test operations (thrown in with the binary ops).
2600	* @{ */
2601	FNIEMAIMPLBINROU8 iemAImpl_test_u8;
2602	FNIEMAIMPLBINROU16 iemAImpl_test_u16;
2603	FNIEMAIMPLBINROU32 iemAImpl_test_u32;
2604	FNIEMAIMPLBINROU64 iemAImpl_test_u64;
2605	/** @} */
2606
2607	/** @name Bit operations operations (thrown in with the binary ops).
2608	* @{ */
2609	FNIEMAIMPLBINROU16 iemAImpl_bt_u16;
2610	FNIEMAIMPLBINROU32 iemAImpl_bt_u32;
2611	FNIEMAIMPLBINROU64 iemAImpl_bt_u64;
2612	FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
2613	FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
2614	FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
2615	FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
2616	FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
2617	FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
2618	FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
2619	FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
2620	FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
2621	/** @} */
2622
2623	/** @name Arithmetic three operand operations on double words (binary).
2624	* @{ */
2625	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32, (uint32_t pu32Dst, uint32_t u32Src1, uint32_t u32Src2, uint32_t pEFlags));
2626	typedef FNIEMAIMPLBINVEXU32 *PFNIEMAIMPLBINVEXU32;
2627	FNIEMAIMPLBINVEXU32 iemAImpl_andn_u32, iemAImpl_andn_u32_fallback;
2628	FNIEMAIMPLBINVEXU32 iemAImpl_bextr_u32, iemAImpl_bextr_u32_fallback;
2629	FNIEMAIMPLBINVEXU32 iemAImpl_bzhi_u32, iemAImpl_bzhi_u32_fallback;
2630	/** @} */
2631
2632	/** @name Arithmetic three operand operations on quad words (binary).
2633	* @{ */
2634	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64, (uint64_t pu64Dst, uint64_t u64Src1, uint64_t u64Src2, uint32_t pEFlags));
2635	typedef FNIEMAIMPLBINVEXU64 *PFNIEMAIMPLBINVEXU64;
2636	FNIEMAIMPLBINVEXU64 iemAImpl_andn_u64, iemAImpl_andn_u64_fallback;
2637	FNIEMAIMPLBINVEXU64 iemAImpl_bextr_u64, iemAImpl_bextr_u64_fallback;
2638	FNIEMAIMPLBINVEXU64 iemAImpl_bzhi_u64, iemAImpl_bzhi_u64_fallback;
2639	/** @} */
2640
2641	/** @name Arithmetic three operand operations on double words w/o EFLAGS (binary).
2642	* @{ */
2643	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32NOEFL, (uint32_t *pu32Dst, uint32_t u32Src1, uint32_t u32Src2));
2644	typedef FNIEMAIMPLBINVEXU32NOEFL *PFNIEMAIMPLBINVEXU32NOEFL;
2645	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pdep_u32, iemAImpl_pdep_u32_fallback;
2646	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pext_u32, iemAImpl_pext_u32_fallback;
2647	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_sarx_u32, iemAImpl_sarx_u32_fallback;
2648	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shlx_u32, iemAImpl_shlx_u32_fallback;
2649	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shrx_u32, iemAImpl_shrx_u32_fallback;
2650	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_rorx_u32;
2651	/** @} */
2652
2653	/** @name Arithmetic three operand operations on quad words w/o EFLAGS (binary).
2654	* @{ */
2655	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64NOEFL, (uint64_t *pu64Dst, uint64_t u64Src1, uint64_t u64Src2));
2656	typedef FNIEMAIMPLBINVEXU64NOEFL *PFNIEMAIMPLBINVEXU64NOEFL;
2657	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pdep_u64, iemAImpl_pdep_u64_fallback;
2658	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pext_u64, iemAImpl_pext_u64_fallback;
2659	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_sarx_u64, iemAImpl_sarx_u64_fallback;
2660	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shlx_u64, iemAImpl_shlx_u64_fallback;
2661	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shrx_u64, iemAImpl_shrx_u64_fallback;
2662	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_rorx_u64;
2663	/** @} */
2664
2665	/** @name MULX 32-bit and 64-bit.
2666	* @{ */
2667	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU32, (uint32_t puDst1, uint32_t puDst2, uint32_t uSrc1, uint32_t uSrc2));
2668	typedef FNIEMAIMPLMULXVEXU32 *PFNIEMAIMPLMULXVEXU32;
2669	FNIEMAIMPLMULXVEXU32 iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback;
2670
2671	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU64, (uint64_t puDst1, uint64_t puDst2, uint64_t uSrc1, uint64_t uSrc2));
2672	typedef FNIEMAIMPLMULXVEXU64 *PFNIEMAIMPLMULXVEXU64;
2673	FNIEMAIMPLMULXVEXU64 iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback;
2674	/** @} */
2675
2676
2677	/** @name Exchange memory with register operations.
2678	* @{ */
2679	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_locked, (uint8_t pu8Mem, uint8_t pu8Reg));
2680	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_locked,(uint16_t pu16Mem, uint16_t pu16Reg));
2681	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_locked,(uint32_t pu32Mem, uint32_t pu32Reg));
2682	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_locked,(uint64_t pu64Mem, uint64_t pu64Reg));
2683	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_unlocked, (uint8_t pu8Mem, uint8_t pu8Reg));
2684	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_unlocked,(uint16_t pu16Mem, uint16_t pu16Reg));
2685	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_unlocked,(uint32_t pu32Mem, uint32_t pu32Reg));
2686	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_unlocked,(uint64_t pu64Mem, uint64_t pu64Reg));
2687	/** @} */
2688
2689	/** @name Exchange and add operations.
2690	* @{ */
2691	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
2692	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
2693	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
2694	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
2695	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
2696	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
2697	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
2698	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
2699	/** @} */
2700
2701	/** @name Compare and exchange.
2702	* @{ */
2703	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
2704	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
2705	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
2706	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
2707	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
2708	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
2709	#if ARCH_BITS == 32
2710	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
2711	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
2712	#else
2713	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
2714	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
2715	#endif
2716	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
2717	uint32_t *pEFlags));
2718	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
2719	uint32_t *pEFlags));
2720	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
2721	uint32_t *pEFlags));
2722	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
2723	uint32_t *pEFlags));
2724	#ifndef RT_ARCH_ARM64
2725	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
2726	PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
2727	#endif
2728	/** @} */
2729
2730	/** @name Memory ordering
2731	* @{ */
2732	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
2733	typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
2734	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
2735	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
2736	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
2737	#ifndef RT_ARCH_ARM64
2738	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
2739	#endif
2740	/** @} */
2741
2742	/** @name Double precision shifts
2743	* @{ */
2744	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t pEFlags));
2745	typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
2746	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t pEFlags));
2747	typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
2748	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t pEFlags));
2749	typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
2750	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16, iemAImpl_shld_u16_amd, iemAImpl_shld_u16_intel;
2751	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32, iemAImpl_shld_u32_amd, iemAImpl_shld_u32_intel;
2752	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64, iemAImpl_shld_u64_amd, iemAImpl_shld_u64_intel;
2753	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16, iemAImpl_shrd_u16_amd, iemAImpl_shrd_u16_intel;
2754	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32, iemAImpl_shrd_u32_amd, iemAImpl_shrd_u32_intel;
2755	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64, iemAImpl_shrd_u64_amd, iemAImpl_shrd_u64_intel;
2756	/** @} */
2757
2758
2759	/** @name Bit search operations (thrown in with the binary ops).
2760	* @{ */
2761	FNIEMAIMPLBINU16 iemAImpl_bsf_u16, iemAImpl_bsf_u16_amd, iemAImpl_bsf_u16_intel;
2762	FNIEMAIMPLBINU32 iemAImpl_bsf_u32, iemAImpl_bsf_u32_amd, iemAImpl_bsf_u32_intel;
2763	FNIEMAIMPLBINU64 iemAImpl_bsf_u64, iemAImpl_bsf_u64_amd, iemAImpl_bsf_u64_intel;
2764	FNIEMAIMPLBINU16 iemAImpl_bsr_u16, iemAImpl_bsr_u16_amd, iemAImpl_bsr_u16_intel;
2765	FNIEMAIMPLBINU32 iemAImpl_bsr_u32, iemAImpl_bsr_u32_amd, iemAImpl_bsr_u32_intel;
2766	FNIEMAIMPLBINU64 iemAImpl_bsr_u64, iemAImpl_bsr_u64_amd, iemAImpl_bsr_u64_intel;
2767	FNIEMAIMPLBINU16 iemAImpl_lzcnt_u16, iemAImpl_lzcnt_u16_amd, iemAImpl_lzcnt_u16_intel;
2768	FNIEMAIMPLBINU32 iemAImpl_lzcnt_u32, iemAImpl_lzcnt_u32_amd, iemAImpl_lzcnt_u32_intel;
2769	FNIEMAIMPLBINU64 iemAImpl_lzcnt_u64, iemAImpl_lzcnt_u64_amd, iemAImpl_lzcnt_u64_intel;
2770	FNIEMAIMPLBINU16 iemAImpl_tzcnt_u16, iemAImpl_tzcnt_u16_amd, iemAImpl_tzcnt_u16_intel;
2771	FNIEMAIMPLBINU32 iemAImpl_tzcnt_u32, iemAImpl_tzcnt_u32_amd, iemAImpl_tzcnt_u32_intel;
2772	FNIEMAIMPLBINU64 iemAImpl_tzcnt_u64, iemAImpl_tzcnt_u64_amd, iemAImpl_tzcnt_u64_intel;
2773	FNIEMAIMPLBINU16 iemAImpl_popcnt_u16, iemAImpl_popcnt_u16_fallback;
2774	FNIEMAIMPLBINU32 iemAImpl_popcnt_u32, iemAImpl_popcnt_u32_fallback;
2775	FNIEMAIMPLBINU64 iemAImpl_popcnt_u64, iemAImpl_popcnt_u64_fallback;
2776	/** @} */
2777
2778	/** @name Signed multiplication operations (thrown in with the binary ops).
2779	* @{ */
2780	FNIEMAIMPLBINU16 iemAImpl_imul_two_u16, iemAImpl_imul_two_u16_amd, iemAImpl_imul_two_u16_intel;
2781	FNIEMAIMPLBINU32 iemAImpl_imul_two_u32, iemAImpl_imul_two_u32_amd, iemAImpl_imul_two_u32_intel;
2782	FNIEMAIMPLBINU64 iemAImpl_imul_two_u64, iemAImpl_imul_two_u64_amd, iemAImpl_imul_two_u64_intel;
2783	/** @} */
2784
2785	/** @name Arithmetic assignment operations on bytes (unary).
2786	* @{ */
2787	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t pu8Dst, uint32_t pEFlags));
2788	typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
2789	FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
2790	FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
2791	FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
2792	FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
2793	/** @} */
2794
2795	/** @name Arithmetic assignment operations on words (unary).
2796	* @{ */
2797	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t pu16Dst, uint32_t pEFlags));
2798	typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
2799	FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
2800	FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
2801	FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
2802	FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
2803	/** @} */
2804
2805	/** @name Arithmetic assignment operations on double words (unary).
2806	* @{ */
2807	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t pu32Dst, uint32_t pEFlags));
2808	typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
2809	FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
2810	FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
2811	FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
2812	FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
2813	/** @} */
2814
2815	/** @name Arithmetic assignment operations on quad words (unary).
2816	* @{ */
2817	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t pu64Dst, uint32_t pEFlags));
2818	typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
2819	FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
2820	FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
2821	FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
2822	FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
2823	/** @} */
2824
2825
2826	/** @name Shift operations on bytes (Group 2).
2827	* @{ */
2828	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU8,(uint8_t pu8Dst, uint8_t cShift, uint32_t pEFlags));
2829	typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
2830	FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8, iemAImpl_rol_u8_amd, iemAImpl_rol_u8_intel;
2831	FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8, iemAImpl_ror_u8_amd, iemAImpl_ror_u8_intel;
2832	FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8, iemAImpl_rcl_u8_amd, iemAImpl_rcl_u8_intel;
2833	FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8, iemAImpl_rcr_u8_amd, iemAImpl_rcr_u8_intel;
2834	FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8, iemAImpl_shl_u8_amd, iemAImpl_shl_u8_intel;
2835	FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8, iemAImpl_shr_u8_amd, iemAImpl_shr_u8_intel;
2836	FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8, iemAImpl_sar_u8_amd, iemAImpl_sar_u8_intel;
2837	/** @} */
2838
2839	/** @name Shift operations on words (Group 2).
2840	* @{ */
2841	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU16,(uint16_t pu16Dst, uint8_t cShift, uint32_t pEFlags));
2842	typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
2843	FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16, iemAImpl_rol_u16_amd, iemAImpl_rol_u16_intel;
2844	FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16, iemAImpl_ror_u16_amd, iemAImpl_ror_u16_intel;
2845	FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16, iemAImpl_rcl_u16_amd, iemAImpl_rcl_u16_intel;
2846	FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16, iemAImpl_rcr_u16_amd, iemAImpl_rcr_u16_intel;
2847	FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16, iemAImpl_shl_u16_amd, iemAImpl_shl_u16_intel;
2848	FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16, iemAImpl_shr_u16_amd, iemAImpl_shr_u16_intel;
2849	FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16, iemAImpl_sar_u16_amd, iemAImpl_sar_u16_intel;
2850	/** @} */
2851
2852	/** @name Shift operations on double words (Group 2).
2853	* @{ */
2854	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU32,(uint32_t pu32Dst, uint8_t cShift, uint32_t pEFlags));
2855	typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
2856	FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32, iemAImpl_rol_u32_amd, iemAImpl_rol_u32_intel;
2857	FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32, iemAImpl_ror_u32_amd, iemAImpl_ror_u32_intel;
2858	FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32, iemAImpl_rcl_u32_amd, iemAImpl_rcl_u32_intel;
2859	FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32, iemAImpl_rcr_u32_amd, iemAImpl_rcr_u32_intel;
2860	FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32, iemAImpl_shl_u32_amd, iemAImpl_shl_u32_intel;
2861	FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32, iemAImpl_shr_u32_amd, iemAImpl_shr_u32_intel;
2862	FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32, iemAImpl_sar_u32_amd, iemAImpl_sar_u32_intel;
2863	/** @} */
2864
2865	/** @name Shift operations on words (Group 2).
2866	* @{ */
2867	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU64,(uint64_t pu64Dst, uint8_t cShift, uint32_t pEFlags));
2868	typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
2869	FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64, iemAImpl_rol_u64_amd, iemAImpl_rol_u64_intel;
2870	FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64, iemAImpl_ror_u64_amd, iemAImpl_ror_u64_intel;
2871	FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64, iemAImpl_rcl_u64_amd, iemAImpl_rcl_u64_intel;
2872	FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64, iemAImpl_rcr_u64_amd, iemAImpl_rcr_u64_intel;
2873	FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64, iemAImpl_shl_u64_amd, iemAImpl_shl_u64_intel;
2874	FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64, iemAImpl_shr_u64_amd, iemAImpl_shr_u64_intel;
2875	FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64, iemAImpl_sar_u64_amd, iemAImpl_sar_u64_intel;
2876	/** @} */
2877
2878	/** @name Multiplication and division operations.
2879	* @{ */
2880	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t pu16AX, uint8_t u8FactorDivisor, uint32_t pEFlags));
2881	typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
2882	FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_mul_u8_amd, iemAImpl_mul_u8_intel;
2883	FNIEMAIMPLMULDIVU8 iemAImpl_imul_u8, iemAImpl_imul_u8_amd, iemAImpl_imul_u8_intel;
2884	FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_div_u8_amd, iemAImpl_div_u8_intel;
2885	FNIEMAIMPLMULDIVU8 iemAImpl_idiv_u8, iemAImpl_idiv_u8_amd, iemAImpl_idiv_u8_intel;
2886
2887	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t pu16AX, uint16_t pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
2888	typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
2889	FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_mul_u16_amd, iemAImpl_mul_u16_intel;
2890	FNIEMAIMPLMULDIVU16 iemAImpl_imul_u16, iemAImpl_imul_u16_amd, iemAImpl_imul_u16_intel;
2891	FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_div_u16_amd, iemAImpl_div_u16_intel;
2892	FNIEMAIMPLMULDIVU16 iemAImpl_idiv_u16, iemAImpl_idiv_u16_amd, iemAImpl_idiv_u16_intel;
2893
2894	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t pu32EAX, uint32_t pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
2895	typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
2896	FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_mul_u32_amd, iemAImpl_mul_u32_intel;
2897	FNIEMAIMPLMULDIVU32 iemAImpl_imul_u32, iemAImpl_imul_u32_amd, iemAImpl_imul_u32_intel;
2898	FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_div_u32_amd, iemAImpl_div_u32_intel;
2899	FNIEMAIMPLMULDIVU32 iemAImpl_idiv_u32, iemAImpl_idiv_u32_amd, iemAImpl_idiv_u32_intel;
2900
2901	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t pu64RAX, uint64_t pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
2902	typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
2903	FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_mul_u64_amd, iemAImpl_mul_u64_intel;
2904	FNIEMAIMPLMULDIVU64 iemAImpl_imul_u64, iemAImpl_imul_u64_amd, iemAImpl_imul_u64_intel;
2905	FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_div_u64_amd, iemAImpl_div_u64_intel;
2906	FNIEMAIMPLMULDIVU64 iemAImpl_idiv_u64, iemAImpl_idiv_u64_amd, iemAImpl_idiv_u64_intel;
2907	/** @} */
2908
2909	/** @name Byte Swap.
2910	* @{ */
2911	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t pu32Dst)); / Yes, 32-bit register access. */
2912	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
2913	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
2914	/** @} */
2915
2916	/** @name Misc.
2917	* @{ */
2918	FNIEMAIMPLBINU16 iemAImpl_arpl;
2919	/** @} */
2920
2921	/** @name RDRAND and RDSEED
2922	* @{ */
2923	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU16,(uint16_t puDst, uint32_t pEFlags));
2924	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU32,(uint32_t puDst, uint32_t pEFlags));
2925	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU64,(uint64_t puDst, uint32_t pEFlags));
2926	typedef FNIEMAIMPLRDRANDSEEDU16 *PFNIEMAIMPLRDRANDSEEDU16;
2927	typedef FNIEMAIMPLRDRANDSEEDU32 *PFNIEMAIMPLRDRANDSEEDU32;
2928	typedef FNIEMAIMPLRDRANDSEEDU64 *PFNIEMAIMPLRDRANDSEEDU64;
2929
2930	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdrand_u16, iemAImpl_rdrand_u16_fallback;
2931	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdrand_u32, iemAImpl_rdrand_u32_fallback;
2932	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdrand_u64, iemAImpl_rdrand_u64_fallback;
2933	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdseed_u16, iemAImpl_rdseed_u16_fallback;
2934	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdseed_u32, iemAImpl_rdseed_u32_fallback;
2935	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdseed_u64, iemAImpl_rdseed_u64_fallback;
2936	/** @} */
2937
2938	/** @name ADOX and ADCX
2939	* @{ */
2940	FNIEMAIMPLBINU32 iemAImpl_adcx_u32, iemAImpl_adcx_u32_fallback;
2941	FNIEMAIMPLBINU64 iemAImpl_adcx_u64, iemAImpl_adcx_u64_fallback;
2942	FNIEMAIMPLBINU32 iemAImpl_adox_u32, iemAImpl_adox_u32_fallback;
2943	FNIEMAIMPLBINU64 iemAImpl_adox_u64, iemAImpl_adox_u64_fallback;
2944	/** @} */
2945
2946	/** @name FPU operations taking a 32-bit float argument
2947	* @{ */
2948	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2949	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
2950	typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
2951
2952	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2953	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
2954	typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
2955
2956	FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
2957	FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
2958	FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
2959	FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
2960	FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
2961	FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
2962	FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
2963
2964	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
2965	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2966	PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
2967	/** @} */
2968
2969	/** @name FPU operations taking a 64-bit float argument
2970	* @{ */
2971	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2972	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
2973	typedef FNIEMAIMPLFPUR64FSW *PFNIEMAIMPLFPUR64FSW;
2974
2975	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2976	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
2977	typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
2978
2979	FNIEMAIMPLFPUR64FSW iemAImpl_fcom_r80_by_r64;
2980	FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
2981	FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
2982	FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
2983	FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
2984	FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
2985	FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
2986
2987	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
2988	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2989	PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
2990	/** @} */
2991
2992	/** @name FPU operations taking a 80-bit float argument
2993	* @{ */
2994	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2995	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
2996	typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
2997	FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
2998	FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
2999	FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
3000	FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
3001	FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
3002	FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
3003	FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
3004	FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
3005	FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
3006
3007	FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80, iemAImpl_fpatan_r80_by_r80_amd, iemAImpl_fpatan_r80_by_r80_intel;
3008	FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80, iemAImpl_fyl2x_r80_by_r80_amd, iemAImpl_fyl2x_r80_by_r80_intel;
3009	FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80, iemAImpl_fyl2xp1_r80_by_r80_amd, iemAImpl_fyl2xp1_r80_by_r80_intel;
3010
3011	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3012	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
3013	typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
3014	FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
3015	FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
3016
3017	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
3018	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
3019	typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
3020	FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
3021	FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
3022
3023	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
3024	typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
3025	FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
3026	FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
3027	FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80, iemAImpl_f2xm1_r80_amd, iemAImpl_f2xm1_r80_intel;
3028	FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
3029	FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
3030	FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80, iemAImpl_fsin_r80_amd, iemAImpl_fsin_r80_intel;
3031	FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80, iemAImpl_fcos_r80_amd, iemAImpl_fcos_r80_intel;
3032
3033	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
3034	typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
3035	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
3036	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
3037
3038	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
3039	typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
3040	FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
3041	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
3042	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
3043	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
3044	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
3045	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
3046	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
3047
3048	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
3049	PCRTFLOAT80U pr80Val));
3050	typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
3051	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80, iemAImpl_fptan_r80_r80_amd, iemAImpl_fptan_r80_r80_intel;
3052	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
3053	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80, iemAImpl_fsincos_r80_r80_amd, iemAImpl_fsincos_r80_r80_intel;
3054
3055	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
3056	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3057	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
3058
3059	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_d80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTPBCD80U pd80Val));
3060	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_d80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3061	PRTPBCD80U pd80Dst, PCRTFLOAT80U pr80Src));
3062
3063	/** @} */
3064
3065	/** @name FPU operations taking a 16-bit signed integer argument
3066	* @{ */
3067	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3068	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
3069	typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
3070	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI16,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3071	int16_t *pi16Dst, PCRTFLOAT80U pr80Src));
3072	typedef FNIEMAIMPLFPUSTR80TOI16 *PFNIEMAIMPLFPUSTR80TOI16;
3073
3074	FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
3075	FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
3076	FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
3077	FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
3078	FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
3079	FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
3080
3081	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3082	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
3083	typedef FNIEMAIMPLFPUI16FSW *PFNIEMAIMPLFPUI16FSW;
3084	FNIEMAIMPLFPUI16FSW iemAImpl_ficom_r80_by_i16;
3085
3086	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
3087	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fist_r80_to_i16;
3088	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fistt_r80_to_i16, iemAImpl_fistt_r80_to_i16_amd, iemAImpl_fistt_r80_to_i16_intel;
3089	/** @} */
3090
3091	/** @name FPU operations taking a 32-bit signed integer argument
3092	* @{ */
3093	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3094	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
3095	typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
3096	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI32,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3097	int32_t *pi32Dst, PCRTFLOAT80U pr80Src));
3098	typedef FNIEMAIMPLFPUSTR80TOI32 *PFNIEMAIMPLFPUSTR80TOI32;
3099
3100	FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
3101	FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
3102	FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
3103	FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
3104	FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
3105	FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
3106
3107	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3108	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
3109	typedef FNIEMAIMPLFPUI32FSW *PFNIEMAIMPLFPUI32FSW;
3110	FNIEMAIMPLFPUI32FSW iemAImpl_ficom_r80_by_i32;
3111
3112	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
3113	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fist_r80_to_i32;
3114	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fistt_r80_to_i32;
3115	/** @} */
3116
3117	/** @name FPU operations taking a 64-bit signed integer argument
3118	* @{ */
3119	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI64,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3120	int64_t *pi64Dst, PCRTFLOAT80U pr80Src));
3121	typedef FNIEMAIMPLFPUSTR80TOI64 *PFNIEMAIMPLFPUSTR80TOI64;
3122
3123	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
3124	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fist_r80_to_i64;
3125	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fistt_r80_to_i64;
3126	/** @} */
3127
3128
3129	/** Temporary type representing a 256-bit vector register. */
3130	typedef struct { uint64_t au64[4]; } IEMVMM256;
3131	/** Temporary type pointing to a 256-bit vector register. */
3132	typedef IEMVMM256 *PIEMVMM256;
3133	/** Temporary type pointing to a const 256-bit vector register. */
3134	typedef IEMVMM256 *PCIEMVMM256;
3135
3136
3137	/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
3138	* @{ */
3139	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t puDst, uint64_t const puSrc));
3140	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
3141	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U128,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
3142	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
3143	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U128,(PX86XSAVEAREA pExtState, PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
3144	typedef FNIEMAIMPLMEDIAF3U128 *PFNIEMAIMPLMEDIAF3U128;
3145	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U256,(PX86XSAVEAREA pExtState, PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
3146	typedef FNIEMAIMPLMEDIAF3U256 *PFNIEMAIMPLMEDIAF3U256;
3147	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U64,(uint64_t puDst, uint64_t const puSrc));
3148	typedef FNIEMAIMPLMEDIAOPTF2U64 *PFNIEMAIMPLMEDIAOPTF2U64;
3149	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128,(PRTUINT128U puDst, PCRTUINT128U puSrc));
3150	typedef FNIEMAIMPLMEDIAOPTF2U128 *PFNIEMAIMPLMEDIAOPTF2U128;
3151	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
3152	typedef FNIEMAIMPLMEDIAOPTF3U128 *PFNIEMAIMPLMEDIAOPTF3U128;
3153	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
3154	typedef FNIEMAIMPLMEDIAOPTF3U256 *PFNIEMAIMPLMEDIAOPTF3U256;
3155	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256,(PRTUINT256U puDst, PCRTUINT256U puSrc));
3156	typedef FNIEMAIMPLMEDIAOPTF2U256 *PFNIEMAIMPLMEDIAOPTF2U256;
3157	FNIEMAIMPLMEDIAF2U64 iemAImpl_pshufb_u64, iemAImpl_pshufb_u64_fallback;
3158	FNIEMAIMPLMEDIAF2U64 iemAImpl_pand_u64, iemAImpl_pandn_u64, iemAImpl_por_u64, iemAImpl_pxor_u64;
3159	FNIEMAIMPLMEDIAF2U64 iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
3160	FNIEMAIMPLMEDIAF2U64 iemAImpl_pcmpgtb_u64, iemAImpl_pcmpgtw_u64, iemAImpl_pcmpgtd_u64;
3161	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddb_u64, iemAImpl_paddsb_u64, iemAImpl_paddusb_u64;
3162	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddw_u64, iemAImpl_paddsw_u64, iemAImpl_paddusw_u64;
3163	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddd_u64;
3164	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddq_u64;
3165	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubb_u64, iemAImpl_psubsb_u64, iemAImpl_psubusb_u64;
3166	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubw_u64, iemAImpl_psubsw_u64, iemAImpl_psubusw_u64;
3167	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubd_u64;
3168	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubq_u64;
3169	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmaddwd_u64, iemAImpl_pmaddwd_u64_fallback;
3170	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmullw_u64, iemAImpl_pmulhw_u64;
3171	FNIEMAIMPLMEDIAF2U64 iemAImpl_pminub_u64, iemAImpl_pmaxub_u64;
3172	FNIEMAIMPLMEDIAF2U64 iemAImpl_pminsw_u64, iemAImpl_pmaxsw_u64;
3173	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsb_u64, iemAImpl_pabsb_u64_fallback;
3174	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsw_u64, iemAImpl_pabsw_u64_fallback;
3175	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsd_u64, iemAImpl_pabsd_u64_fallback;
3176	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignb_u64, iemAImpl_psignb_u64_fallback;
3177	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignw_u64, iemAImpl_psignw_u64_fallback;
3178	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignd_u64, iemAImpl_psignd_u64_fallback;
3179	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddw_u64, iemAImpl_phaddw_u64_fallback;
3180	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddd_u64, iemAImpl_phaddd_u64_fallback;
3181	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubw_u64, iemAImpl_phsubw_u64_fallback;
3182	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubd_u64, iemAImpl_phsubd_u64_fallback;
3183	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddsw_u64, iemAImpl_phaddsw_u64_fallback;
3184	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubsw_u64, iemAImpl_phsubsw_u64_fallback;
3185	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmaddubsw_u64, iemAImpl_pmaddubsw_u64_fallback;
3186	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmulhrsw_u64, iemAImpl_pmulhrsw_u64_fallback;
3187	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmuludq_u64;
3188	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllw_u64, iemAImpl_psrlw_u64, iemAImpl_psraw_u64;
3189	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pslld_u64, iemAImpl_psrld_u64, iemAImpl_psrad_u64;
3190	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllq_u64, iemAImpl_psrlq_u64;
3191	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packsswb_u64, iemAImpl_packuswb_u64;
3192	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packssdw_u64;
3193	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhuw_u64;
3194	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pavgb_u64, iemAImpl_pavgw_u64;
3195	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psadbw_u64;
3196
3197	FNIEMAIMPLMEDIAF2U128 iemAImpl_pshufb_u128, iemAImpl_pshufb_u128_fallback;
3198	FNIEMAIMPLMEDIAF2U128 iemAImpl_pand_u128, iemAImpl_pandn_u128, iemAImpl_por_u128, iemAImpl_pxor_u128;
3199	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
3200	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpeqq_u128, iemAImpl_pcmpeqq_u128_fallback;
3201	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpgtb_u128, iemAImpl_pcmpgtw_u128, iemAImpl_pcmpgtd_u128;
3202	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpgtq_u128, iemAImpl_pcmpgtq_u128_fallback;
3203	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddb_u128, iemAImpl_paddsb_u128, iemAImpl_paddusb_u128;
3204	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddw_u128, iemAImpl_paddsw_u128, iemAImpl_paddusw_u128;
3205	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddd_u128;
3206	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddq_u128;
3207	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubb_u128, iemAImpl_psubsb_u128, iemAImpl_psubusb_u128;
3208	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubw_u128, iemAImpl_psubsw_u128, iemAImpl_psubusw_u128;
3209	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubd_u128;
3210	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubq_u128;
3211	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmullw_u128, iemAImpl_pmullw_u128_fallback;
3212	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulhw_u128;
3213	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulld_u128, iemAImpl_pmulld_u128_fallback;
3214	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaddwd_u128, iemAImpl_pmaddwd_u128_fallback;
3215	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminub_u128;
3216	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminud_u128, iemAImpl_pminud_u128_fallback;
3217	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminuw_u128, iemAImpl_pminuw_u128_fallback;
3218	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsb_u128, iemAImpl_pminsb_u128_fallback;
3219	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsd_u128, iemAImpl_pminsd_u128_fallback;
3220	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsw_u128, iemAImpl_pminsw_u128_fallback;
3221	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxub_u128;
3222	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxud_u128, iemAImpl_pmaxud_u128_fallback;
3223	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxuw_u128, iemAImpl_pmaxuw_u128_fallback;
3224	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsb_u128, iemAImpl_pmaxsb_u128_fallback;
3225	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsw_u128;
3226	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsd_u128, iemAImpl_pmaxsd_u128_fallback;
3227	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsb_u128, iemAImpl_pabsb_u128_fallback;
3228	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsw_u128, iemAImpl_pabsw_u128_fallback;
3229	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsd_u128, iemAImpl_pabsd_u128_fallback;
3230	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignb_u128, iemAImpl_psignb_u128_fallback;
3231	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignw_u128, iemAImpl_psignw_u128_fallback;
3232	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignd_u128, iemAImpl_psignd_u128_fallback;
3233	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddw_u128, iemAImpl_phaddw_u128_fallback;
3234	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddd_u128, iemAImpl_phaddd_u128_fallback;
3235	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubw_u128, iemAImpl_phsubw_u128_fallback;
3236	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubd_u128, iemAImpl_phsubd_u128_fallback;
3237	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddsw_u128, iemAImpl_phaddsw_u128_fallback;
3238	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubsw_u128, iemAImpl_phsubsw_u128_fallback;
3239	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaddubsw_u128, iemAImpl_pmaddubsw_u128_fallback;
3240	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulhrsw_u128, iemAImpl_pmulhrsw_u128_fallback;
3241	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmuludq_u128;
3242	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaddwd_u128, iemAImpl_pmaddwd_u128_fallback;
3243	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packsswb_u128, iemAImpl_packuswb_u128;
3244	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packssdw_u128, iemAImpl_packusdw_u128;
3245	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllw_u128, iemAImpl_psrlw_u128, iemAImpl_psraw_u128;
3246	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pslld_u128, iemAImpl_psrld_u128, iemAImpl_psrad_u128;
3247	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllq_u128, iemAImpl_psrlq_u128;
3248	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhuw_u128;
3249	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pavgb_u128, iemAImpl_pavgw_u128;
3250	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psadbw_u128;
3251	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuldq_u128, iemAImpl_pmuldq_u128_fallback;
3252	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpcklps_u128, iemAImpl_unpcklpd_u128;
3253	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpckhps_u128, iemAImpl_unpckhpd_u128;
3254	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phminposuw_u128, iemAImpl_phminposuw_u128_fallback;
3255
3256	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpshufb_u128, iemAImpl_vpshufb_u128_fallback;
3257	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpand_u128, iemAImpl_vpand_u128_fallback;
3258	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpandn_u128, iemAImpl_vpandn_u128_fallback;
3259	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpor_u128, iemAImpl_vpor_u128_fallback;
3260	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpxor_u128, iemAImpl_vpxor_u128_fallback;
3261	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqb_u128, iemAImpl_vpcmpeqb_u128_fallback;
3262	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqw_u128, iemAImpl_vpcmpeqw_u128_fallback;
3263	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqd_u128, iemAImpl_vpcmpeqd_u128_fallback;
3264	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqq_u128, iemAImpl_vpcmpeqq_u128_fallback;
3265	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtb_u128, iemAImpl_vpcmpgtb_u128_fallback;
3266	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtw_u128, iemAImpl_vpcmpgtw_u128_fallback;
3267	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtd_u128, iemAImpl_vpcmpgtd_u128_fallback;
3268	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtq_u128, iemAImpl_vpcmpgtq_u128_fallback;
3269	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddb_u128, iemAImpl_vpaddb_u128_fallback;
3270	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddw_u128, iemAImpl_vpaddw_u128_fallback;
3271	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddd_u128, iemAImpl_vpaddd_u128_fallback;
3272	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddq_u128, iemAImpl_vpaddq_u128_fallback;
3273	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubb_u128, iemAImpl_vpsubb_u128_fallback;
3274	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubw_u128, iemAImpl_vpsubw_u128_fallback;
3275	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubd_u128, iemAImpl_vpsubd_u128_fallback;
3276	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubq_u128, iemAImpl_vpsubq_u128_fallback;
3277	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminub_u128, iemAImpl_vpminub_u128_fallback;
3278	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminuw_u128, iemAImpl_vpminuw_u128_fallback;
3279	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminud_u128, iemAImpl_vpminud_u128_fallback;
3280	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsb_u128, iemAImpl_vpminsb_u128_fallback;
3281	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsw_u128, iemAImpl_vpminsw_u128_fallback;
3282	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsd_u128, iemAImpl_vpminsd_u128_fallback;
3283	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxub_u128, iemAImpl_vpmaxub_u128_fallback;
3284	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxuw_u128, iemAImpl_vpmaxuw_u128_fallback;
3285	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxud_u128, iemAImpl_vpmaxud_u128_fallback;
3286	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsb_u128, iemAImpl_vpmaxsb_u128_fallback;
3287	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsw_u128, iemAImpl_vpmaxsw_u128_fallback;
3288	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsd_u128, iemAImpl_vpmaxsd_u128_fallback;
3289	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpacksswb_u128, iemAImpl_vpacksswb_u128_fallback;
3290	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackssdw_u128, iemAImpl_vpackssdw_u128_fallback;
3291	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackuswb_u128, iemAImpl_vpackuswb_u128_fallback;
3292	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackusdw_u128, iemAImpl_vpackusdw_u128_fallback;
3293	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmullw_u128, iemAImpl_vpmullw_u128_fallback;
3294	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulld_u128, iemAImpl_vpmulld_u128_fallback;
3295	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhw_u128, iemAImpl_vpmulhw_u128_fallback;
3296	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhuw_u128, iemAImpl_vpmulhuw_u128_fallback;
3297	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgb_u128, iemAImpl_vpavgb_u128_fallback;
3298	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgw_u128, iemAImpl_vpavgw_u128_fallback;
3299	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignb_u128, iemAImpl_vpsignb_u128_fallback;
3300	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignw_u128, iemAImpl_vpsignw_u128_fallback;
3301	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignd_u128, iemAImpl_vpsignd_u128_fallback;
3302	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddw_u128, iemAImpl_vphaddw_u128_fallback;
3303	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddd_u128, iemAImpl_vphaddd_u128_fallback;
3304	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubw_u128, iemAImpl_vphsubw_u128_fallback;
3305	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubd_u128, iemAImpl_vphsubd_u128_fallback;
3306	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddsw_u128, iemAImpl_vphaddsw_u128_fallback;
3307	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubsw_u128, iemAImpl_vphsubsw_u128_fallback;
3308	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddubsw_u128, iemAImpl_vpmaddubsw_u128_fallback;
3309	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhrsw_u128, iemAImpl_vpmulhrsw_u128_fallback;
3310	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsadbw_u128, iemAImpl_vpsadbw_u128_fallback;
3311	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuldq_u128, iemAImpl_vpmuldq_u128_fallback;
3312	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuludq_u128, iemAImpl_vpmuludq_u128_fallback;
3313	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsb_u128, iemAImpl_vpsubsb_u128_fallback;
3314	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsw_u128, iemAImpl_vpsubsw_u128_fallback;
3315	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusb_u128, iemAImpl_vpsubusb_u128_fallback;
3316	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusw_u128, iemAImpl_vpsubusw_u128_fallback;
3317	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusb_u128, iemAImpl_vpaddusb_u128_fallback;
3318	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusw_u128, iemAImpl_vpaddusw_u128_fallback;
3319	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsb_u128, iemAImpl_vpaddsb_u128_fallback;
3320	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsw_u128, iemAImpl_vpaddsw_u128_fallback;
3321	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllw_u128, iemAImpl_vpsllw_u128_fallback;
3322	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpslld_u128, iemAImpl_vpslld_u128_fallback;
3323	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllq_u128, iemAImpl_vpsllq_u128_fallback;
3324	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsraw_u128, iemAImpl_vpsraw_u128_fallback;
3325	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrad_u128, iemAImpl_vpsrad_u128_fallback;
3326	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlw_u128, iemAImpl_vpsrlw_u128_fallback;
3327	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrld_u128, iemAImpl_vpsrld_u128_fallback;
3328	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlq_u128, iemAImpl_vpsrlq_u128_fallback;
3329	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddwd_u128, iemAImpl_vpmaddwd_u128_fallback;
3330
3331	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsb_u128, iemAImpl_vpabsb_u128_fallback;
3332	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsw_u128, iemAImpl_vpabsd_u128_fallback;
3333	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsd_u128, iemAImpl_vpabsw_u128_fallback;
3334	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vphminposuw_u128, iemAImpl_vphminposuw_u128_fallback;
3335
3336	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpshufb_u256, iemAImpl_vpshufb_u256_fallback;
3337	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpand_u256, iemAImpl_vpand_u256_fallback;
3338	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpandn_u256, iemAImpl_vpandn_u256_fallback;
3339	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpor_u256, iemAImpl_vpor_u256_fallback;
3340	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpxor_u256, iemAImpl_vpxor_u256_fallback;
3341	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqb_u256, iemAImpl_vpcmpeqb_u256_fallback;
3342	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqw_u256, iemAImpl_vpcmpeqw_u256_fallback;
3343	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqd_u256, iemAImpl_vpcmpeqd_u256_fallback;
3344	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqq_u256, iemAImpl_vpcmpeqq_u256_fallback;
3345	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtb_u256, iemAImpl_vpcmpgtb_u256_fallback;
3346	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtw_u256, iemAImpl_vpcmpgtw_u256_fallback;
3347	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtd_u256, iemAImpl_vpcmpgtd_u256_fallback;
3348	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtq_u256, iemAImpl_vpcmpgtq_u256_fallback;
3349	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddb_u256, iemAImpl_vpaddb_u256_fallback;
3350	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddw_u256, iemAImpl_vpaddw_u256_fallback;
3351	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddd_u256, iemAImpl_vpaddd_u256_fallback;
3352	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddq_u256, iemAImpl_vpaddq_u256_fallback;
3353	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubb_u256, iemAImpl_vpsubb_u256_fallback;
3354	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubw_u256, iemAImpl_vpsubw_u256_fallback;
3355	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubd_u256, iemAImpl_vpsubd_u256_fallback;
3356	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubq_u256, iemAImpl_vpsubq_u256_fallback;
3357	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminub_u256, iemAImpl_vpminub_u256_fallback;
3358	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminuw_u256, iemAImpl_vpminuw_u256_fallback;
3359	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminud_u256, iemAImpl_vpminud_u256_fallback;
3360	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsb_u256, iemAImpl_vpminsb_u256_fallback;
3361	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsw_u256, iemAImpl_vpminsw_u256_fallback;
3362	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsd_u256, iemAImpl_vpminsd_u256_fallback;
3363	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxub_u256, iemAImpl_vpmaxub_u256_fallback;
3364	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxuw_u256, iemAImpl_vpmaxuw_u256_fallback;
3365	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxud_u256, iemAImpl_vpmaxud_u256_fallback;
3366	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsb_u256, iemAImpl_vpmaxsb_u256_fallback;
3367	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsw_u256, iemAImpl_vpmaxsw_u256_fallback;
3368	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsd_u256, iemAImpl_vpmaxsd_u256_fallback;
3369	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpacksswb_u256, iemAImpl_vpacksswb_u256_fallback;
3370	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackssdw_u256, iemAImpl_vpackssdw_u256_fallback;
3371	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackuswb_u256, iemAImpl_vpackuswb_u256_fallback;
3372	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackusdw_u256, iemAImpl_vpackusdw_u256_fallback;
3373	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmullw_u256, iemAImpl_vpmullw_u256_fallback;
3374	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulld_u256, iemAImpl_vpmulld_u256_fallback;
3375	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhw_u256, iemAImpl_vpmulhw_u256_fallback;
3376	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhuw_u256, iemAImpl_vpmulhuw_u256_fallback;
3377	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgb_u256, iemAImpl_vpavgb_u256_fallback;
3378	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgw_u256, iemAImpl_vpavgw_u256_fallback;
3379	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignb_u256, iemAImpl_vpsignb_u256_fallback;
3380	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignw_u256, iemAImpl_vpsignw_u256_fallback;
3381	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignd_u256, iemAImpl_vpsignd_u256_fallback;
3382	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddw_u256, iemAImpl_vphaddw_u256_fallback;
3383	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddd_u256, iemAImpl_vphaddd_u256_fallback;
3384	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubw_u256, iemAImpl_vphsubw_u256_fallback;
3385	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubd_u256, iemAImpl_vphsubd_u256_fallback;
3386	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddsw_u256, iemAImpl_vphaddsw_u256_fallback;
3387	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubsw_u256, iemAImpl_vphsubsw_u256_fallback;
3388	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddubsw_u256, iemAImpl_vpmaddubsw_u256_fallback;
3389	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhrsw_u256, iemAImpl_vpmulhrsw_u256_fallback;
3390	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsadbw_u256, iemAImpl_vpsadbw_u256_fallback;
3391	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuldq_u256, iemAImpl_vpmuldq_u256_fallback;
3392	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuludq_u256, iemAImpl_vpmuludq_u256_fallback;
3393	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsb_u256, iemAImpl_vpsubsb_u256_fallback;
3394	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsw_u256, iemAImpl_vpsubsw_u256_fallback;
3395	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusb_u256, iemAImpl_vpsubusb_u256_fallback;
3396	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusw_u256, iemAImpl_vpsubusw_u256_fallback;
3397	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusb_u256, iemAImpl_vpaddusb_u256_fallback;
3398	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusw_u256, iemAImpl_vpaddusw_u256_fallback;
3399	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsb_u256, iemAImpl_vpaddsb_u256_fallback;
3400	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsw_u256, iemAImpl_vpaddsw_u256_fallback;
3401	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllw_u256, iemAImpl_vpsllw_u256_fallback;
3402	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpslld_u256, iemAImpl_vpslld_u256_fallback;
3403	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllq_u256, iemAImpl_vpsllq_u256_fallback;
3404	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsraw_u256, iemAImpl_vpsraw_u256_fallback;
3405	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrad_u256, iemAImpl_vpsrad_u256_fallback;
3406	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlw_u256, iemAImpl_vpsrlw_u256_fallback;
3407	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrld_u256, iemAImpl_vpsrld_u256_fallback;
3408	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlq_u256, iemAImpl_vpsrlq_u256_fallback;
3409	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddwd_u256, iemAImpl_vpmaddwd_u256_fallback;
3410
3411	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsb_u256, iemAImpl_vpabsb_u256_fallback;
3412	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsw_u256, iemAImpl_vpabsw_u256_fallback;
3413	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsd_u256, iemAImpl_vpabsd_u256_fallback;
3414	/** @} */
3415
3416	/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
3417	* @{ */
3418	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
3419	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
3420	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpcklbw_u128, iemAImpl_vpunpcklbw_u128_fallback,
3421	iemAImpl_vpunpcklwd_u128, iemAImpl_vpunpcklwd_u128_fallback,
3422	iemAImpl_vpunpckldq_u128, iemAImpl_vpunpckldq_u128_fallback,
3423	iemAImpl_vpunpcklqdq_u128, iemAImpl_vpunpcklqdq_u128_fallback,
3424	iemAImpl_vunpcklps_u128, iemAImpl_vunpcklps_u128_fallback,
3425	iemAImpl_vunpcklpd_u128, iemAImpl_vunpcklpd_u128_fallback,
3426	iemAImpl_vunpckhps_u128, iemAImpl_vunpckhps_u128_fallback,
3427	iemAImpl_vunpckhpd_u128, iemAImpl_vunpckhpd_u128_fallback;
3428
3429	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpcklbw_u256, iemAImpl_vpunpcklbw_u256_fallback,
3430	iemAImpl_vpunpcklwd_u256, iemAImpl_vpunpcklwd_u256_fallback,
3431	iemAImpl_vpunpckldq_u256, iemAImpl_vpunpckldq_u256_fallback,
3432	iemAImpl_vpunpcklqdq_u256, iemAImpl_vpunpcklqdq_u256_fallback,
3433	iemAImpl_vunpcklps_u256, iemAImpl_vunpcklps_u256_fallback,
3434	iemAImpl_vunpcklpd_u256, iemAImpl_vunpcklpd_u256_fallback,
3435	iemAImpl_vunpckhps_u256, iemAImpl_vunpckhps_u256_fallback,
3436	iemAImpl_vunpckhpd_u256, iemAImpl_vunpckhpd_u256_fallback;
3437	/** @} */
3438
3439	/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
3440	* @{ */
3441	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
3442	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
3443	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpckhbw_u128, iemAImpl_vpunpckhbw_u128_fallback,
3444	iemAImpl_vpunpckhwd_u128, iemAImpl_vpunpckhwd_u128_fallback,
3445	iemAImpl_vpunpckhdq_u128, iemAImpl_vpunpckhdq_u128_fallback,
3446	iemAImpl_vpunpckhqdq_u128, iemAImpl_vpunpckhqdq_u128_fallback;
3447	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpckhbw_u256, iemAImpl_vpunpckhbw_u256_fallback,
3448	iemAImpl_vpunpckhwd_u256, iemAImpl_vpunpckhwd_u256_fallback,
3449	iemAImpl_vpunpckhdq_u256, iemAImpl_vpunpckhdq_u256_fallback,
3450	iemAImpl_vpunpckhqdq_u256, iemAImpl_vpunpckhqdq_u256_fallback;
3451	/** @} */
3452
3453	/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
3454	* @{ */
3455	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3456	typedef FNIEMAIMPLMEDIAPSHUFU128 *PFNIEMAIMPLMEDIAPSHUFU128;
3457	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
3458	typedef FNIEMAIMPLMEDIAPSHUFU256 *PFNIEMAIMPLMEDIAPSHUFU256;
3459	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw_u64,(uint64_t puDst, uint64_t const puSrc, uint8_t bEvil));
3460	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_pshufhw_u128, iemAImpl_pshuflw_u128, iemAImpl_pshufd_u128;
3461	#ifndef IEM_WITHOUT_ASSEMBLY
3462	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256, iemAImpl_vpshuflw_u256, iemAImpl_vpshufd_u256;
3463	#endif
3464	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256_fallback, iemAImpl_vpshuflw_u256_fallback, iemAImpl_vpshufd_u256_fallback;
3465	/** @} */
3466
3467	/** @name Media (SSE/MMX/AVX) operation: Shift Immediate Stuff (evil)
3468	* @{ */
3469	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU64,(uint64_t *puDst, uint8_t bShift));
3470	typedef FNIEMAIMPLMEDIAPSHIFTU64 *PFNIEMAIMPLMEDIAPSHIFTU64;
3471	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU128,(PRTUINT128U puDst, uint8_t bShift));
3472	typedef FNIEMAIMPLMEDIAPSHIFTU128 *PFNIEMAIMPLMEDIAPSHIFTU128;
3473	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU256,(PRTUINT256U puDst, uint8_t bShift));
3474	typedef FNIEMAIMPLMEDIAPSHIFTU256 *PFNIEMAIMPLMEDIAPSHIFTU256;
3475	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psllw_imm_u64, iemAImpl_pslld_imm_u64, iemAImpl_psllq_imm_u64;
3476	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psrlw_imm_u64, iemAImpl_psrld_imm_u64, iemAImpl_psrlq_imm_u64;
3477	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psraw_imm_u64, iemAImpl_psrad_imm_u64;
3478	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psllw_imm_u128, iemAImpl_pslld_imm_u128, iemAImpl_psllq_imm_u128;
3479	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psrlw_imm_u128, iemAImpl_psrld_imm_u128, iemAImpl_psrlq_imm_u128;
3480	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psraw_imm_u128, iemAImpl_psrad_imm_u128;
3481	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_pslldq_imm_u128, iemAImpl_psrldq_imm_u128;
3482	/** @} */
3483
3484	/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
3485	* @{ */
3486	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(uint64_t pu64Dst, uint64_t const puSrc));
3487	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(uint64_t *pu64Dst, PCRTUINT128U puSrc));
3488	#ifndef IEM_WITHOUT_ASSEMBLY
3489	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
3490	#endif
3491	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256_fallback,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
3492	/** @} */
3493
3494	/** @name Media (SSE/MMX/AVX) operations: Variable Blend Packed Bytes/R32/R64.
3495	* @{ */
3496	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puMask));
3497	typedef FNIEMAIMPLBLENDU128 *PFNIEMAIMPLBLENDU128;
3498	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, PCRTUINT128U puMask));
3499	typedef FNIEMAIMPLAVXBLENDU128 *PFNIEMAIMPLAVXBLENDU128;
3500	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, PCRTUINT256U puMask));
3501	typedef FNIEMAIMPLAVXBLENDU256 *PFNIEMAIMPLAVXBLENDU256;
3502
3503	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128;
3504	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128_fallback;
3505	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128;
3506	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128_fallback;
3507	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256;
3508	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256_fallback;
3509
3510	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128;
3511	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128_fallback;
3512	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128;
3513	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128_fallback;
3514	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256;
3515	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256_fallback;
3516
3517	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128;
3518	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128_fallback;
3519	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128;
3520	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128_fallback;
3521	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256;
3522	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256_fallback;
3523	/** @} */
3524
3525
3526	/** @name Media (SSE/MMX/AVX) operation: Sort this later
3527	* @{ */
3528	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
3529	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
3530	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovshdup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
3531	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovshdup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
3532	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
3533	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
3534
3535	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3536	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3537	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3538	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3539	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3540
3541	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3542	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3543	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3544	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3545	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3546
3547	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3548	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3549	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
3550	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3551	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3552
3553	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3554	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3555	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3556	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3557	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3558
3559	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3560	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3561	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3562	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3563	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3564
3565	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3566	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3567	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3568	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3569	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3570
3571	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3572	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3573	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3574	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3575	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3576
3577	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3578	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3579	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3580	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3581	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3582
3583	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3584	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3585	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
3586	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3587	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3588
3589	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3590	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3591	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3592	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3593	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3594
3595	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3596	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3597	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3598	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3599	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3600
3601	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3602	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3603	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3604	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3605	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3606
3607	IEM_DECL_IMPL_DEF(void, iemAImpl_shufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3608	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3609	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3610	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3611	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3612
3613	IEM_DECL_IMPL_DEF(void, iemAImpl_shufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3614	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3615	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3616	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3617	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3618
3619	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
3620	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64_fallback,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
3621
3622	IEM_DECL_IMPL_DEF(void, iemAImpl_pinsrw_u64,(uint64_t *pu64Dst, uint16_t u16Src, uint8_t bEvil));
3623	IEM_DECL_IMPL_DEF(void, iemAImpl_pinsrw_u128,(PRTUINT128U puDst, uint16_t u16Src, uint8_t bEvil));
3624	IEM_DECL_IMPL_DEF(void, iemAImpl_vpinsrw_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint16_t u16Src, uint8_t bEvil));
3625	IEM_DECL_IMPL_DEF(void, iemAImpl_vpinsrw_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint16_t u16Src, uint8_t bEvil));
3626
3627	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3628	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3629	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3630	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3631	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3632
3633	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3634	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3635	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3636	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3637	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3638
3639
3640	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3641	typedef FNIEMAIMPLMEDIAOPTF2U128IMM8 *PFNIEMAIMPLMEDIAOPTF2U128IMM8;
3642	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
3643	typedef FNIEMAIMPLMEDIAOPTF2U256IMM8 *PFNIEMAIMPLMEDIAOPTF2U256IMM8;
3644	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3645	typedef FNIEMAIMPLMEDIAOPTF3U128IMM8 *PFNIEMAIMPLMEDIAOPTF3U128IMM8;
3646	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3647	typedef FNIEMAIMPLMEDIAOPTF3U256IMM8 *PFNIEMAIMPLMEDIAOPTF3U256IMM8;
3648
3649	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_palignr_u128, iemAImpl_palignr_u128_fallback;
3650	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pblendw_u128, iemAImpl_pblendw_u128_fallback;
3651	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendps_u128, iemAImpl_blendps_u128_fallback;
3652	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendpd_u128, iemAImpl_blendpd_u128_fallback;
3653
3654	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpalignr_u128, iemAImpl_vpalignr_u128_fallback;
3655	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendw_u128, iemAImpl_vpblendw_u128_fallback;
3656	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendd_u128, iemAImpl_vpblendd_u128_fallback;
3657	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendps_u128, iemAImpl_vblendps_u128_fallback;
3658	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendpd_u128, iemAImpl_vblendpd_u128_fallback;
3659
3660	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpalignr_u256, iemAImpl_vpalignr_u256_fallback;
3661	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendw_u256, iemAImpl_vpblendw_u256_fallback;
3662	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendd_u256, iemAImpl_vpblendd_u256_fallback;
3663	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendps_u256, iemAImpl_vblendps_u256_fallback;
3664	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendpd_u256, iemAImpl_vblendpd_u256_fallback;
3665	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2i128_u256, iemAImpl_vperm2i128_u256_fallback;
3666	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2f128_u256, iemAImpl_vperm2f128_u256_fallback;
3667
3668	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesimc_u128, iemAImpl_aesimc_u128_fallback;
3669	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenc_u128, iemAImpl_aesenc_u128_fallback;
3670	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenclast_u128, iemAImpl_aesenclast_u128_fallback;
3671	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdec_u128, iemAImpl_aesdec_u128_fallback;
3672	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdeclast_u128, iemAImpl_aesdeclast_u128_fallback;
3673
3674	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesimc_u128, iemAImpl_vaesimc_u128_fallback;
3675	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenc_u128, iemAImpl_vaesenc_u128_fallback;
3676	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenclast_u128, iemAImpl_vaesenclast_u128_fallback;
3677	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdec_u128, iemAImpl_vaesdec_u128_fallback;
3678	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdeclast_u128, iemAImpl_vaesdeclast_u128_fallback;
3679
3680	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_aeskeygenassist_u128, iemAImpl_aeskeygenassist_u128_fallback;
3681
3682	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vaeskeygenassist_u128, iemAImpl_vaeskeygenassist_u128_fallback;
3683
3684	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1nexte_u128, iemAImpl_sha1nexte_u128_fallback;
3685	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg1_u128, iemAImpl_sha1msg1_u128_fallback;
3686	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg2_u128, iemAImpl_sha1msg2_u128_fallback;
3687	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg1_u128, iemAImpl_sha256msg1_u128_fallback;
3688	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg2_u128, iemAImpl_sha256msg2_u128_fallback;
3689	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_sha1rnds4_u128, iemAImpl_sha1rnds4_u128_fallback;
3690	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
3691	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
3692
3693	typedef struct IEMPCMPISTRXSRC
3694	{
3695	RTUINT128U uSrc1;
3696	RTUINT128U uSrc2;
3697	} IEMPCMPISTRXSRC;
3698	typedef IEMPCMPISTRXSRC *PIEMPCMPISTRXSRC;
3699	typedef const IEMPCMPISTRXSRC *PCIEMPCMPISTRXSRC;
3700
3701	typedef struct IEMPCMPESTRXSRC
3702	{
3703	RTUINT128U uSrc1;
3704	RTUINT128U uSrc2;
3705	uint64_t u64Rax;
3706	uint64_t u64Rdx;
3707	} IEMPCMPESTRXSRC;
3708	typedef IEMPCMPESTRXSRC *PIEMPCMPESTRXSRC;
3709	typedef const IEMPCMPESTRXSRC *PCIEMPCMPESTRXSRC;
3710
3711	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPISTRIU128IMM8,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
3712	typedef FNIEMAIMPLPCMPISTRIU128IMM8 *PFNIEMAIMPLPCMPISTRIU128IMM8;
3713	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRIU128IMM8,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
3714	typedef FNIEMAIMPLPCMPESTRIU128IMM8 *PFNIEMAIMPLPCMPESTRIU128IMM8;
3715
3716	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPISTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
3717	typedef FNIEMAIMPLPCMPISTRMU128IMM8 *PFNIEMAIMPLPCMPISTRMU128IMM8;
3718	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
3719	typedef FNIEMAIMPLPCMPESTRMU128IMM8 *PFNIEMAIMPLPCMPESTRMU128IMM8;
3720
3721	FNIEMAIMPLPCMPISTRIU128IMM8 iemAImpl_pcmpistri_u128, iemAImpl_pcmpistri_u128_fallback;
3722	FNIEMAIMPLPCMPESTRIU128IMM8 iemAImpl_pcmpestri_u128, iemAImpl_pcmpestri_u128_fallback;
3723	FNIEMAIMPLPCMPISTRMU128IMM8 iemAImpl_pcmpistrm_u128, iemAImpl_pcmpistrm_u128_fallback;
3724	FNIEMAIMPLPCMPESTRMU128IMM8 iemAImpl_pcmpestrm_u128, iemAImpl_pcmpestrm_u128_fallback;
3725
3726	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pclmulqdq_u128, iemAImpl_pclmulqdq_u128_fallback;
3727	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpclmulqdq_u128, iemAImpl_vpclmulqdq_u128_fallback;
3728
3729	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_mpsadbw_u128, iemAImpl_mpsadbw_u128_fallback;
3730	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vmpsadbw_u128, iemAImpl_vmpsadbw_u128_fallback;
3731	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vmpsadbw_u256, iemAImpl_vmpsadbw_u256_fallback;
3732
3733	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsllw_imm_u128, iemAImpl_vpsllw_imm_u128_fallback;
3734	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsllw_imm_u256, iemAImpl_vpsllw_imm_u256_fallback;
3735	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpslld_imm_u128, iemAImpl_vpslld_imm_u128_fallback;
3736	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpslld_imm_u256, iemAImpl_vpslld_imm_u256_fallback;
3737	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsllq_imm_u128, iemAImpl_vpsllq_imm_u128_fallback;
3738	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsllq_imm_u256, iemAImpl_vpsllq_imm_u256_fallback;
3739
3740	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsraw_imm_u128, iemAImpl_vpsraw_imm_u128_fallback;
3741	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsraw_imm_u256, iemAImpl_vpsraw_imm_u256_fallback;
3742	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrad_imm_u128, iemAImpl_vpsrad_imm_u128_fallback;
3743	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrad_imm_u256, iemAImpl_vpsrad_imm_u256_fallback;
3744
3745	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrlw_imm_u128, iemAImpl_vpsrlw_imm_u128_fallback;
3746	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrlw_imm_u256, iemAImpl_vpsrlw_imm_u256_fallback;
3747	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrld_imm_u128, iemAImpl_vpsrld_imm_u128_fallback;
3748	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrld_imm_u256, iemAImpl_vpsrld_imm_u256_fallback;
3749	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrlq_imm_u128, iemAImpl_vpsrlq_imm_u128_fallback;
3750	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrlq_imm_u256, iemAImpl_vpsrlq_imm_u256_fallback;
3751	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrldq_imm_u128, iemAImpl_vpsrldq_imm_u128_fallback;
3752	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrldq_imm_u256, iemAImpl_vpsrldq_imm_u256_fallback;
3753
3754	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpermilps_u128, iemAImpl_vpermilps_u128_fallback;
3755	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_vpermilps_imm_u128, iemAImpl_vpermilps_imm_u128_fallback;
3756	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpermilps_u256, iemAImpl_vpermilps_u256_fallback;
3757	FNIEMAIMPLMEDIAOPTF2U256IMM8 iemAImpl_vpermilps_imm_u256, iemAImpl_vpermilps_imm_u256_fallback;
3758
3759	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpermilpd_u128, iemAImpl_vpermilpd_u128_fallback;
3760	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_vpermilpd_imm_u128, iemAImpl_vpermilpd_imm_u128_fallback;
3761	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpermilpd_u256, iemAImpl_vpermilpd_u256_fallback;
3762	FNIEMAIMPLMEDIAOPTF2U256IMM8 iemAImpl_vpermilpd_imm_u256, iemAImpl_vpermilpd_imm_u256_fallback;
3763
3764	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllvd_u128, iemAImpl_vpsllvd_u128_fallback;
3765	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllvd_u256, iemAImpl_vpsllvd_u256_fallback;
3766	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllvq_u128, iemAImpl_vpsllvq_u128_fallback;
3767	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllvq_u256, iemAImpl_vpsllvq_u256_fallback;
3768	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsravd_u128, iemAImpl_vpsravd_u128_fallback;
3769	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsravd_u256, iemAImpl_vpsravd_u256_fallback;
3770	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlvd_u128, iemAImpl_vpsrlvd_u128_fallback;
3771	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlvd_u256, iemAImpl_vpsrlvd_u256_fallback;
3772	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlvq_u128, iemAImpl_vpsrlvq_u128_fallback;
3773	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlvq_u256, iemAImpl_vpsrlvq_u256_fallback;
3774	/** @} */
3775
3776	/** @name Media Odds and Ends
3777	* @{ */
3778	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U8,(uint32_t *puDst, uint8_t uSrc));
3779	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U16,(uint32_t *puDst, uint16_t uSrc));
3780	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U32,(uint32_t *puDst, uint32_t uSrc));
3781	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U64,(uint32_t *puDst, uint64_t uSrc));
3782	FNIEMAIMPLCR32U8 iemAImpl_crc32_u8, iemAImpl_crc32_u8_fallback;
3783	FNIEMAIMPLCR32U16 iemAImpl_crc32_u16, iemAImpl_crc32_u16_fallback;
3784	FNIEMAIMPLCR32U32 iemAImpl_crc32_u32, iemAImpl_crc32_u32_fallback;
3785	FNIEMAIMPLCR32U64 iemAImpl_crc32_u64, iemAImpl_crc32_u64_fallback;
3786
3787	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL128,(PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint32_t *pEFlags));
3788	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL256,(PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint32_t *pEFlags));
3789	FNIEMAIMPLF2EFL128 iemAImpl_ptest_u128;
3790	FNIEMAIMPLF2EFL256 iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback;
3791
3792	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I32U64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int32_t pi32Dst, const uint64_t pu64Src)); / pu64Src is a double precision floating point. */
3793	typedef FNIEMAIMPLSSEF2I32U64 *PFNIEMAIMPLSSEF2I32U64;
3794	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I64U64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int64_t pi64Dst, const uint64_t pu64Src)); / pu64Src is a double precision floating point. */
3795	typedef FNIEMAIMPLSSEF2I64U64 *PFNIEMAIMPLSSEF2I64U64;
3796	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I32U32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int32_t pi32Dst, const uint32_t pu32Src)); / pu32Src is a single precision floating point. */
3797	typedef FNIEMAIMPLSSEF2I32U32 *PFNIEMAIMPLSSEF2I32U32;
3798	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I64U32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int64_t pi64Dst, const uint32_t pu32Src)); / pu32Src is a single precision floating point. */
3799	typedef FNIEMAIMPLSSEF2I64U32 *PFNIEMAIMPLSSEF2I64U32;
3800
3801	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvttsd2si_i32_r64;
3802	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvtsd2si_i32_r64;
3803
3804	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvttsd2si_i64_r64;
3805	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvtsd2si_i64_r64;
3806
3807	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvttss2si_i32_r32;
3808	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvtss2si_i32_r32;
3809
3810	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvttss2si_i64_r32;
3811	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvtss2si_i64_r32;
3812
3813	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R32I32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT32U pr32Dst, const int32_t pi32Src));
3814	typedef FNIEMAIMPLSSEF2R32I32 *PFNIEMAIMPLSSEF2R32I32;
3815	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R32I64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT32U pr32Dst, const int64_t pi64Src));
3816	typedef FNIEMAIMPLSSEF2R32I64 *PFNIEMAIMPLSSEF2R32I64;
3817
3818	FNIEMAIMPLSSEF2R32I32 iemAImpl_cvtsi2ss_r32_i32;
3819	FNIEMAIMPLSSEF2R32I64 iemAImpl_cvtsi2ss_r32_i64;
3820
3821	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R64I32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT64U pr64Dst, const int32_t pi32Src));
3822	typedef FNIEMAIMPLSSEF2R64I32 *PFNIEMAIMPLSSEF2R64I32;
3823	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R64I64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT64U pr64Dst, const int64_t pi64Src));
3824	typedef FNIEMAIMPLSSEF2R64I64 *PFNIEMAIMPLSSEF2R64I64;
3825
3826	FNIEMAIMPLSSEF2R64I32 iemAImpl_cvtsi2sd_r64_i32;
3827	FNIEMAIMPLSSEF2R64I64 iemAImpl_cvtsi2sd_r64_i64;
3828
3829
3830	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFLMXCSR128,(uint32_t pfMxcsr, uint32_t pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
3831	typedef FNIEMAIMPLF2EFLMXCSR128 *PFNIEMAIMPLF2EFLMXCSR128;
3832
3833	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_ucomiss_u128;
3834	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback;
3835
3836	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_ucomisd_u128;
3837	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback;
3838
3839	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_comiss_u128;
3840	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback;
3841
3842	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_comisd_u128;
3843	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback;
3844
3845
3846	typedef struct IEMMEDIAF2XMMSRC
3847	{
3848	X86XMMREG uSrc1;
3849	X86XMMREG uSrc2;
3850	} IEMMEDIAF2XMMSRC;
3851	typedef IEMMEDIAF2XMMSRC *PIEMMEDIAF2XMMSRC;
3852	typedef const IEMMEDIAF2XMMSRC *PCIEMMEDIAF2XMMSRC;
3853
3854	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRF2XMMIMM8,(uint32_t *pfMxcsr, PX86XMMREG puDst, PCIEMMEDIAF2XMMSRC puSrc, uint8_t bEvil));
3855	typedef FNIEMAIMPLMXCSRF2XMMIMM8 *PFNIEMAIMPLMXCSRF2XMMIMM8;
3856
3857	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpps_u128;
3858	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmppd_u128;
3859	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpss_u128;
3860	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpsd_u128;
3861	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundss_u128;
3862	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundsd_u128;
3863
3864	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundps_u128, iemAImpl_roundps_u128_fallback;
3865	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundpd_u128, iemAImpl_roundpd_u128_fallback;
3866
3867	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_dpps_u128, iemAImpl_dpps_u128_fallback;
3868	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_dppd_u128, iemAImpl_dppd_u128_fallback;
3869
3870	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU64U128,(uint32_t pfMxcsr, uint64_t pu64Dst, PCX86XMMREG pSrc));
3871	typedef FNIEMAIMPLMXCSRU64U128 *PFNIEMAIMPLMXCSRU64U128;
3872
3873	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvtpd2pi_u128;
3874	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvttpd2pi_u128;
3875
3876	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU128U64,(uint32_t *pfMxcsr, PX86XMMREG pDst, uint64_t u64Src));
3877	typedef FNIEMAIMPLMXCSRU128U64 *PFNIEMAIMPLMXCSRU128U64;
3878
3879	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2ps_u128;
3880	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2pd_u128;
3881
3882	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU64U64,(uint32_t pfMxcsr, uint64_t pu64Dst, uint64_t u64Src));
3883	typedef FNIEMAIMPLMXCSRU64U64 *PFNIEMAIMPLMXCSRU64U64;
3884
3885	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvtps2pi_u128;
3886	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvttps2pi_u128;
3887
3888	/** @} */
3889
3890
3891	/** @name Function tables.
3892	* @{
3893	*/
3894
3895	/**
3896	* Function table for a binary operator providing implementation based on
3897	* operand size.
3898	*/
3899	typedef struct IEMOPBINSIZES
3900	{
3901	PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
3902	PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
3903	PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
3904	PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
3905	} IEMOPBINSIZES;
3906	/** Pointer to a binary operator function table. */
3907	typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
3908
3909
3910	/**
3911	* Function table for a unary operator providing implementation based on
3912	* operand size.
3913	*/
3914	typedef struct IEMOPUNARYSIZES
3915	{
3916	PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
3917	PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
3918	PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
3919	PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
3920	} IEMOPUNARYSIZES;
3921	/** Pointer to a unary operator function table. */
3922	typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
3923
3924
3925	/**
3926	* Function table for a shift operator providing implementation based on
3927	* operand size.
3928	*/
3929	typedef struct IEMOPSHIFTSIZES
3930	{
3931	PFNIEMAIMPLSHIFTU8 pfnNormalU8;
3932	PFNIEMAIMPLSHIFTU16 pfnNormalU16;
3933	PFNIEMAIMPLSHIFTU32 pfnNormalU32;
3934	PFNIEMAIMPLSHIFTU64 pfnNormalU64;
3935	} IEMOPSHIFTSIZES;
3936	/** Pointer to a shift operator function table. */
3937	typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
3938
3939
3940	/**
3941	* Function table for a multiplication or division operation.
3942	*/
3943	typedef struct IEMOPMULDIVSIZES
3944	{
3945	PFNIEMAIMPLMULDIVU8 pfnU8;
3946	PFNIEMAIMPLMULDIVU16 pfnU16;
3947	PFNIEMAIMPLMULDIVU32 pfnU32;
3948	PFNIEMAIMPLMULDIVU64 pfnU64;
3949	} IEMOPMULDIVSIZES;
3950	/** Pointer to a multiplication or division operation function table. */
3951	typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
3952
3953
3954	/**
3955	* Function table for a double precision shift operator providing implementation
3956	* based on operand size.
3957	*/
3958	typedef struct IEMOPSHIFTDBLSIZES
3959	{
3960	PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
3961	PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
3962	PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
3963	} IEMOPSHIFTDBLSIZES;
3964	/** Pointer to a double precision shift function table. */
3965	typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
3966
3967
3968	/**
3969	* Function table for media instruction taking two full sized media source
3970	* registers and one full sized destination register (AVX).
3971	*/
3972	typedef struct IEMOPMEDIAF3
3973	{
3974	PFNIEMAIMPLMEDIAF3U128 pfnU128;
3975	PFNIEMAIMPLMEDIAF3U256 pfnU256;
3976	} IEMOPMEDIAF3;
3977	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
3978	typedef IEMOPMEDIAF3 const *PCIEMOPMEDIAF3;
3979
3980	/** @def IEMOPMEDIAF3_INIT_VARS_EX
3981	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3982	* given functions as initializers. For use in AVX functions where a pair of
3983	* functions are only used once and the function table need not be public. */
3984	#ifndef TST_IEM_CHECK_MC
3985	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3986	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3987	static IEMOPMEDIAF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3988	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3989	# else
3990	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3991	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3992	# endif
3993	#else
3994	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3995	#endif
3996	/** @def IEMOPMEDIAF3_INIT_VARS
3997	* Generate AVX function tables for the @a a_InstrNm instruction.
3998	* @sa IEMOPMEDIAF3_INIT_VARS_EX */
3999	#define IEMOPMEDIAF3_INIT_VARS(a_InstrNm) \
4000	IEMOPMEDIAF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4001	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4002
4003	/**
4004	* Function table for media instruction taking two full sized media source
4005	* registers and one full sized destination register, but no additional state
4006	* (AVX).
4007	*/
4008	typedef struct IEMOPMEDIAOPTF3
4009	{
4010	PFNIEMAIMPLMEDIAOPTF3U128 pfnU128;
4011	PFNIEMAIMPLMEDIAOPTF3U256 pfnU256;
4012	} IEMOPMEDIAOPTF3;
4013	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
4014	typedef IEMOPMEDIAOPTF3 const *PCIEMOPMEDIAOPTF3;
4015
4016	/** @def IEMOPMEDIAOPTF3_INIT_VARS_EX
4017	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4018	* given functions as initializers. For use in AVX functions where a pair of
4019	* functions are only used once and the function table need not be public. */
4020	#ifndef TST_IEM_CHECK_MC
4021	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4022	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4023	static IEMOPMEDIAOPTF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4024	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4025	# else
4026	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4027	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4028	# endif
4029	#else
4030	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4031	#endif
4032	/** @def IEMOPMEDIAOPTF3_INIT_VARS
4033	* Generate AVX function tables for the @a a_InstrNm instruction.
4034	* @sa IEMOPMEDIAOPTF3_INIT_VARS_EX */
4035	#define IEMOPMEDIAOPTF3_INIT_VARS(a_InstrNm) \
4036	IEMOPMEDIAOPTF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4037	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4038
4039	/**
4040	* Function table for media instruction taking one full sized media source
4041	* registers and one full sized destination register, but no additional state
4042	* (AVX).
4043	*/
4044	typedef struct IEMOPMEDIAOPTF2
4045	{
4046	PFNIEMAIMPLMEDIAOPTF2U128 pfnU128;
4047	PFNIEMAIMPLMEDIAOPTF2U256 pfnU256;
4048	} IEMOPMEDIAOPTF2;
4049	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
4050	typedef IEMOPMEDIAOPTF2 const *PCIEMOPMEDIAOPTF2;
4051
4052	/** @def IEMOPMEDIAOPTF2_INIT_VARS_EX
4053	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4054	* given functions as initializers. For use in AVX functions where a pair of
4055	* functions are only used once and the function table need not be public. */
4056	#ifndef TST_IEM_CHECK_MC
4057	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4058	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4059	static IEMOPMEDIAOPTF2 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4060	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4061	# else
4062	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4063	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4064	# endif
4065	#else
4066	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4067	#endif
4068	/** @def IEMOPMEDIAOPTF2_INIT_VARS
4069	* Generate AVX function tables for the @a a_InstrNm instruction.
4070	* @sa IEMOPMEDIAOPTF2_INIT_VARS_EX */
4071	#define IEMOPMEDIAOPTF2_INIT_VARS(a_InstrNm) \
4072	IEMOPMEDIAOPTF2_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4073	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4074
4075	/**
4076	* Function table for media instruction taking one full sized media source
4077	* register and one full sized destination register and an 8-bit immediate, but no additional state
4078	* (AVX).
4079	*/
4080	typedef struct IEMOPMEDIAOPTF2IMM8
4081	{
4082	PFNIEMAIMPLMEDIAOPTF2U128IMM8 pfnU128;
4083	PFNIEMAIMPLMEDIAOPTF2U256IMM8 pfnU256;
4084	} IEMOPMEDIAOPTF2IMM8;
4085	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
4086	typedef IEMOPMEDIAOPTF2IMM8 const *PCIEMOPMEDIAOPTF2IMM8;
4087
4088	/** @def IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX
4089	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4090	* given functions as initializers. For use in AVX functions where a pair of
4091	* functions are only used once and the function table need not be public. */
4092	#ifndef TST_IEM_CHECK_MC
4093	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4094	# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4095	static IEMOPMEDIAOPTF2IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4096	static IEMOPMEDIAOPTF2IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4097	# else
4098	# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4099	static IEMOPMEDIAOPTF2IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4100	# endif
4101	#else
4102	# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4103	#endif
4104	/** @def IEMOPMEDIAOPTF2IMM8_INIT_VARS
4105	* Generate AVX function tables for the @a a_InstrNm instruction.
4106	* @sa IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX */
4107	#define IEMOPMEDIAOPTF2IMM8_INIT_VARS(a_InstrNm) \
4108	IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u256),\
4109	RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u256_fallback))
4110
4111	/**
4112	* Function table for media instruction taking two full sized media source
4113	* registers and one full sized destination register and an 8-bit immediate, but no additional state
4114	* (AVX).
4115	*/
4116	typedef struct IEMOPMEDIAOPTF3IMM8
4117	{
4118	PFNIEMAIMPLMEDIAOPTF3U128IMM8 pfnU128;
4119	PFNIEMAIMPLMEDIAOPTF3U256IMM8 pfnU256;
4120	} IEMOPMEDIAOPTF3IMM8;
4121	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
4122	typedef IEMOPMEDIAOPTF3IMM8 const *PCIEMOPMEDIAOPTF3IMM8;
4123
4124	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX
4125	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4126	* given functions as initializers. For use in AVX functions where a pair of
4127	* functions are only used once and the function table need not be public. */
4128	#ifndef TST_IEM_CHECK_MC
4129	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4130	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4131	static IEMOPMEDIAOPTF3IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4132	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4133	# else
4134	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4135	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4136	# endif
4137	#else
4138	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4139	#endif
4140	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS
4141	* Generate AVX function tables for the @a a_InstrNm instruction.
4142	* @sa IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX */
4143	#define IEMOPMEDIAOPTF3IMM8_INIT_VARS(a_InstrNm) \
4144	IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4145	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4146	/** @} */
4147
4148
4149	/**
4150	* Function table for blend type instruction taking three full sized media source
4151	* registers and one full sized destination register, but no additional state
4152	* (AVX).
4153	*/
4154	typedef struct IEMOPBLENDOP
4155	{
4156	PFNIEMAIMPLAVXBLENDU128 pfnU128;
4157	PFNIEMAIMPLAVXBLENDU256 pfnU256;
4158	} IEMOPBLENDOP;
4159	/** Pointer to a media operation function table for 4 full sized ops (AVX). */
4160	typedef IEMOPBLENDOP const *PCIEMOPBLENDOP;
4161
4162	/** @def IEMOPBLENDOP_INIT_VARS_EX
4163	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4164	* given functions as initializers. For use in AVX functions where a pair of
4165	* functions are only used once and the function table need not be public. */
4166	#ifndef TST_IEM_CHECK_MC
4167	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4168	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4169	static IEMOPBLENDOP const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4170	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4171	# else
4172	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4173	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4174	# endif
4175	#else
4176	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4177	#endif
4178	/** @def IEMOPBLENDOP_INIT_VARS
4179	* Generate AVX function tables for the @a a_InstrNm instruction.
4180	* @sa IEMOPBLENDOP_INIT_VARS_EX */
4181	#define IEMOPBLENDOP_INIT_VARS(a_InstrNm) \
4182	IEMOPBLENDOP_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4183	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4184
4185
4186	/** @name SSE/AVX single/double precision floating point operations.
4187	* @{ */
4188	/**
4189	* A SSE result.
4190	*/
4191	typedef struct IEMSSERESULT
4192	{
4193	/** The output value. */
4194	X86XMMREG uResult;
4195	/** The output status. */
4196	uint32_t MXCSR;
4197	} IEMSSERESULT;
4198	AssertCompileMemberOffset(IEMSSERESULT, MXCSR, 128 / 8);
4199	/** Pointer to a SSE result. */
4200	typedef IEMSSERESULT *PIEMSSERESULT;
4201	/** Pointer to a const SSE result. */
4202	typedef IEMSSERESULT const *PCIEMSSERESULT;
4203
4204
4205	/**
4206	* A AVX128 result.
4207	*/
4208	typedef struct IEMAVX128RESULT
4209	{
4210	/** The output value. */
4211	X86XMMREG uResult;
4212	/** The output status. */
4213	uint32_t MXCSR;
4214	} IEMAVX128RESULT;
4215	AssertCompileMemberOffset(IEMAVX128RESULT, MXCSR, 128 / 8);
4216	/** Pointer to a AVX128 result. */
4217	typedef IEMAVX128RESULT *PIEMAVX128RESULT;
4218	/** Pointer to a const AVX128 result. */
4219	typedef IEMAVX128RESULT const *PCIEMAVX128RESULT;
4220
4221
4222	/**
4223	* A AVX256 result.
4224	*/
4225	typedef struct IEMAVX256RESULT
4226	{
4227	/** The output value. */
4228	X86YMMREG uResult;
4229	/** The output status. */
4230	uint32_t MXCSR;
4231	} IEMAVX256RESULT;
4232	AssertCompileMemberOffset(IEMAVX256RESULT, MXCSR, 256 / 8);
4233	/** Pointer to a AVX256 result. */
4234	typedef IEMAVX256RESULT *PIEMAVX256RESULT;
4235	/** Pointer to a const AVX256 result. */
4236	typedef IEMAVX256RESULT const *PCIEMAVX256RESULT;
4237
4238
4239	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
4240	typedef FNIEMAIMPLFPSSEF2U128 *PFNIEMAIMPLFPSSEF2U128;
4241	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128R32,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
4242	typedef FNIEMAIMPLFPSSEF2U128R32 *PFNIEMAIMPLFPSSEF2U128R32;
4243	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128R64,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
4244	typedef FNIEMAIMPLFPSSEF2U128R64 *PFNIEMAIMPLFPSSEF2U128R64;
4245
4246	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
4247	typedef FNIEMAIMPLFPAVXF3U128 *PFNIEMAIMPLFPAVXF3U128;
4248	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128R32,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
4249	typedef FNIEMAIMPLFPAVXF3U128R32 *PFNIEMAIMPLFPAVXF3U128R32;
4250	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128R64,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
4251	typedef FNIEMAIMPLFPAVXF3U128R64 *PFNIEMAIMPLFPAVXF3U128R64;
4252
4253	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U256,(PX86XSAVEAREA pExtState, PIEMAVX256RESULT pResult, PCX86YMMREG puSrc1, PCX86YMMREG puSrc2));
4254	typedef FNIEMAIMPLFPAVXF3U256 *PFNIEMAIMPLFPAVXF3U256;
4255
4256	FNIEMAIMPLFPSSEF2U128 iemAImpl_addps_u128;
4257	FNIEMAIMPLFPSSEF2U128 iemAImpl_addpd_u128;
4258	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulps_u128;
4259	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulpd_u128;
4260	FNIEMAIMPLFPSSEF2U128 iemAImpl_subps_u128;
4261	FNIEMAIMPLFPSSEF2U128 iemAImpl_subpd_u128;
4262	FNIEMAIMPLFPSSEF2U128 iemAImpl_minps_u128;
4263	FNIEMAIMPLFPSSEF2U128 iemAImpl_minpd_u128;
4264	FNIEMAIMPLFPSSEF2U128 iemAImpl_divps_u128;
4265	FNIEMAIMPLFPSSEF2U128 iemAImpl_divpd_u128;
4266	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxps_u128;
4267	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxpd_u128;
4268	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddps_u128;
4269	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddpd_u128;
4270	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubps_u128;
4271	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubpd_u128;
4272	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtps_u128;
4273	FNIEMAIMPLFPSSEF2U128 iemAImpl_rsqrtps_u128;
4274	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtpd_u128;
4275	FNIEMAIMPLFPSSEF2U128 iemAImpl_rcpps_u128;
4276	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubps_u128;
4277	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubpd_u128;
4278	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2ps_u128;
4279	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2pd_u128;
4280
4281	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2ps_u128;
4282	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2dq_u128;
4283	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttps2dq_u128;
4284	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttpd2dq_u128;
4285	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2pd_u128;
4286	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2dq_u128;
4287
4288	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_addss_u128_r32;
4289	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_addsd_u128_r64;
4290	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_mulss_u128_r32;
4291	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_mulsd_u128_r64;
4292	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_subss_u128_r32;
4293	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_subsd_u128_r64;
4294	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_minss_u128_r32;
4295	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_minsd_u128_r64;
4296	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_divss_u128_r32;
4297	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_divsd_u128_r64;
4298	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_maxss_u128_r32;
4299	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_maxsd_u128_r64;
4300	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_cvtss2sd_u128_r32;
4301	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_cvtsd2ss_u128_r64;
4302	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_sqrtss_u128_r32;
4303	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_sqrtsd_u128_r64;
4304	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_rsqrtss_u128_r32;
4305	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_rcpss_u128_r32;
4306
4307	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddps_u128, iemAImpl_vaddps_u128_fallback;
4308	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddpd_u128, iemAImpl_vaddpd_u128_fallback;
4309	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulps_u128, iemAImpl_vmulps_u128_fallback;
4310	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulpd_u128, iemAImpl_vmulpd_u128_fallback;
4311	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubps_u128, iemAImpl_vsubps_u128_fallback;
4312	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubpd_u128, iemAImpl_vsubpd_u128_fallback;
4313	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminps_u128, iemAImpl_vminps_u128_fallback;
4314	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminpd_u128, iemAImpl_vminpd_u128_fallback;
4315	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivps_u128, iemAImpl_vdivps_u128_fallback;
4316	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivpd_u128, iemAImpl_vdivpd_u128_fallback;
4317	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxps_u128, iemAImpl_vmaxps_u128_fallback;
4318	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxpd_u128, iemAImpl_vmaxpd_u128_fallback;
4319	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddps_u128, iemAImpl_vhaddps_u128_fallback;
4320	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddpd_u128, iemAImpl_vhaddpd_u128_fallback;
4321	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubps_u128, iemAImpl_vhsubps_u128_fallback;
4322	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubpd_u128, iemAImpl_vhsubpd_u128_fallback;
4323	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtps_u128, iemAImpl_vsqrtps_u128_fallback;
4324	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtpd_u128, iemAImpl_vsqrtpd_u128_fallback;
4325	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubps_u128, iemAImpl_vaddsubps_u128_fallback;
4326	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubpd_u128, iemAImpl_vaddsubpd_u128_fallback;
4327	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtpd2ps_u128, iemAImpl_vcvtpd2ps_u128_fallback;
4328	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtps2pd_u128, iemAImpl_vcvtps2pd_u128_fallback;
4329
4330	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vaddss_u128_r32, iemAImpl_vaddss_u128_r32_fallback;
4331	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vaddsd_u128_r64, iemAImpl_vaddsd_u128_r64_fallback;
4332	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmulss_u128_r32, iemAImpl_vmulss_u128_r32_fallback;
4333	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmulsd_u128_r64, iemAImpl_vmulsd_u128_r64_fallback;
4334	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsubss_u128_r32, iemAImpl_vsubss_u128_r32_fallback;
4335	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsubsd_u128_r64, iemAImpl_vsubsd_u128_r64_fallback;
4336	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vminss_u128_r32, iemAImpl_vminss_u128_r32_fallback;
4337	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vminsd_u128_r64, iemAImpl_vminsd_u128_r64_fallback;
4338	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vdivss_u128_r32, iemAImpl_vdivss_u128_r32_fallback;
4339	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vdivsd_u128_r64, iemAImpl_vdivsd_u128_r64_fallback;
4340	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmaxss_u128_r32, iemAImpl_vmaxss_u128_r32_fallback;
4341	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmaxsd_u128_r64, iemAImpl_vmaxsd_u128_r64_fallback;
4342	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsqrtss_u128_r32, iemAImpl_vsqrtss_u128_r32_fallback;
4343	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsqrtsd_u128_r64, iemAImpl_vsqrtsd_u128_r64_fallback;
4344
4345	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddps_u256, iemAImpl_vaddps_u256_fallback;
4346	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddpd_u256, iemAImpl_vaddpd_u256_fallback;
4347	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulps_u256, iemAImpl_vmulps_u256_fallback;
4348	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulpd_u256, iemAImpl_vmulpd_u256_fallback;
4349	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubps_u256, iemAImpl_vsubps_u256_fallback;
4350	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubpd_u256, iemAImpl_vsubpd_u256_fallback;
4351	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminps_u256, iemAImpl_vminps_u256_fallback;
4352	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminpd_u256, iemAImpl_vminpd_u256_fallback;
4353	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivps_u256, iemAImpl_vdivps_u256_fallback;
4354	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivpd_u256, iemAImpl_vdivpd_u256_fallback;
4355	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxps_u256, iemAImpl_vmaxps_u256_fallback;
4356	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxpd_u256, iemAImpl_vmaxpd_u256_fallback;
4357	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddps_u256, iemAImpl_vhaddps_u256_fallback;
4358	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddpd_u256, iemAImpl_vhaddpd_u256_fallback;
4359	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubps_u256, iemAImpl_vhsubps_u256_fallback;
4360	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubpd_u256, iemAImpl_vhsubpd_u256_fallback;
4361	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubps_u256, iemAImpl_vhaddsubps_u256_fallback;
4362	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubpd_u256, iemAImpl_vhaddsubpd_u256_fallback;
4363	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtpd2ps_u256, iemAImpl_vcvtpd2ps_u256_fallback;
4364	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtps2pd_u256, iemAImpl_vcvtps2pd_u256_fallback;
4365	/** @} */
4366
4367	/** @name C instruction implementations for anything slightly complicated.
4368	* @{ */
4369
4370	/**
4371	* For typedef'ing or declaring a C instruction implementation function taking
4372	* no extra arguments.
4373	*
4374	* @param a_Name The name of the type.
4375	*/
4376	# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
4377	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
4378	/**
4379	* For defining a C instruction implementation function taking no extra
4380	* arguments.
4381	*
4382	* @param a_Name The name of the function
4383	*/
4384	# define IEM_CIMPL_DEF_0(a_Name) \
4385	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
4386	/**
4387	* Prototype version of IEM_CIMPL_DEF_0.
4388	*/
4389	# define IEM_CIMPL_PROTO_0(a_Name) \
4390	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
4391	/**
4392	* For calling a C instruction implementation function taking no extra
4393	* arguments.
4394	*
4395	* This special call macro adds default arguments to the call and allow us to
4396	* change these later.
4397	*
4398	* @param a_fn The name of the function.
4399	*/
4400	# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
4401
4402	/** Type for a C instruction implementation function taking no extra
4403	* arguments. */
4404	typedef IEM_CIMPL_DECL_TYPE_0(FNIEMCIMPL0);
4405	/** Function pointer type for a C instruction implementation function taking
4406	* no extra arguments. */
4407	typedef FNIEMCIMPL0 *PFNIEMCIMPL0;
4408
4409	/**
4410	* For typedef'ing or declaring a C instruction implementation function taking
4411	* one extra argument.
4412	*
4413	* @param a_Name The name of the type.
4414	* @param a_Type0 The argument type.
4415	* @param a_Arg0 The argument name.
4416	*/
4417	# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
4418	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
4419	/**
4420	* For defining a C instruction implementation function taking one extra
4421	* argument.
4422	*
4423	* @param a_Name The name of the function
4424	* @param a_Type0 The argument type.
4425	* @param a_Arg0 The argument name.
4426	*/
4427	# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
4428	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
4429	/**
4430	* Prototype version of IEM_CIMPL_DEF_1.
4431	*/
4432	# define IEM_CIMPL_PROTO_1(a_Name, a_Type0, a_Arg0) \
4433	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
4434	/**
4435	* For calling a C instruction implementation function taking one extra
4436	* argument.
4437	*
4438	* This special call macro adds default arguments to the call and allow us to
4439	* change these later.
4440	*
4441	* @param a_fn The name of the function.
4442	* @param a0 The name of the 1st argument.
4443	*/
4444	# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
4445
4446	/**
4447	* For typedef'ing or declaring a C instruction implementation function taking
4448	* two extra arguments.
4449	*
4450	* @param a_Name The name of the type.
4451	* @param a_Type0 The type of the 1st argument
4452	* @param a_Arg0 The name of the 1st argument.
4453	* @param a_Type1 The type of the 2nd argument.
4454	* @param a_Arg1 The name of the 2nd argument.
4455	*/
4456	# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
4457	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
4458	/**
4459	* For defining a C instruction implementation function taking two extra
4460	* arguments.
4461	*
4462	* @param a_Name The name of the function.
4463	* @param a_Type0 The type of the 1st argument
4464	* @param a_Arg0 The name of the 1st argument.
4465	* @param a_Type1 The type of the 2nd argument.
4466	* @param a_Arg1 The name of the 2nd argument.
4467	*/
4468	# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
4469	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
4470	/**
4471	* Prototype version of IEM_CIMPL_DEF_2.
4472	*/
4473	# define IEM_CIMPL_PROTO_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
4474	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
4475	/**
4476	* For calling a C instruction implementation function taking two extra
4477	* arguments.
4478	*
4479	* This special call macro adds default arguments to the call and allow us to
4480	* change these later.
4481	*
4482	* @param a_fn The name of the function.
4483	* @param a0 The name of the 1st argument.
4484	* @param a1 The name of the 2nd argument.
4485	*/
4486	# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
4487
4488	/**
4489	* For typedef'ing or declaring a C instruction implementation function taking
4490	* three extra arguments.
4491	*
4492	* @param a_Name The name of the type.
4493	* @param a_Type0 The type of the 1st argument
4494	* @param a_Arg0 The name of the 1st argument.
4495	* @param a_Type1 The type of the 2nd argument.
4496	* @param a_Arg1 The name of the 2nd argument.
4497	* @param a_Type2 The type of the 3rd argument.
4498	* @param a_Arg2 The name of the 3rd argument.
4499	*/
4500	# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
4501	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
4502	/**
4503	* For defining a C instruction implementation function taking three extra
4504	* arguments.
4505	*
4506	* @param a_Name The name of the function.
4507	* @param a_Type0 The type of the 1st argument
4508	* @param a_Arg0 The name of the 1st argument.
4509	* @param a_Type1 The type of the 2nd argument.
4510	* @param a_Arg1 The name of the 2nd argument.
4511	* @param a_Type2 The type of the 3rd argument.
4512	* @param a_Arg2 The name of the 3rd argument.
4513	*/
4514	# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
4515	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
4516	/**
4517	* Prototype version of IEM_CIMPL_DEF_3.
4518	*/
4519	# define IEM_CIMPL_PROTO_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
4520	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
4521	/**
4522	* For calling a C instruction implementation function taking three extra
4523	* arguments.
4524	*
4525	* This special call macro adds default arguments to the call and allow us to
4526	* change these later.
4527	*
4528	* @param a_fn The name of the function.
4529	* @param a0 The name of the 1st argument.
4530	* @param a1 The name of the 2nd argument.
4531	* @param a2 The name of the 3rd argument.
4532	*/
4533	# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
4534
4535
4536	/**
4537	* For typedef'ing or declaring a C instruction implementation function taking
4538	* four extra arguments.
4539	*
4540	* @param a_Name The name of the type.
4541	* @param a_Type0 The type of the 1st argument
4542	* @param a_Arg0 The name of the 1st argument.
4543	* @param a_Type1 The type of the 2nd argument.
4544	* @param a_Arg1 The name of the 2nd argument.
4545	* @param a_Type2 The type of the 3rd argument.
4546	* @param a_Arg2 The name of the 3rd argument.
4547	* @param a_Type3 The type of the 4th argument.
4548	* @param a_Arg3 The name of the 4th argument.
4549	*/
4550	# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
4551	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
4552	/**
4553	* For defining a C instruction implementation function taking four extra
4554	* arguments.
4555	*
4556	* @param a_Name The name of the function.
4557	* @param a_Type0 The type of the 1st argument
4558	* @param a_Arg0 The name of the 1st argument.
4559	* @param a_Type1 The type of the 2nd argument.
4560	* @param a_Arg1 The name of the 2nd argument.
4561	* @param a_Type2 The type of the 3rd argument.
4562	* @param a_Arg2 The name of the 3rd argument.
4563	* @param a_Type3 The type of the 4th argument.
4564	* @param a_Arg3 The name of the 4th argument.
4565	*/
4566	# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
4567	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4568	a_Type2 a_Arg2, a_Type3 a_Arg3))
4569	/**
4570	* Prototype version of IEM_CIMPL_DEF_4.
4571	*/
4572	# define IEM_CIMPL_PROTO_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
4573	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4574	a_Type2 a_Arg2, a_Type3 a_Arg3))
4575	/**
4576	* For calling a C instruction implementation function taking four extra
4577	* arguments.
4578	*
4579	* This special call macro adds default arguments to the call and allow us to
4580	* change these later.
4581	*
4582	* @param a_fn The name of the function.
4583	* @param a0 The name of the 1st argument.
4584	* @param a1 The name of the 2nd argument.
4585	* @param a2 The name of the 3rd argument.
4586	* @param a3 The name of the 4th argument.
4587	*/
4588	# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
4589
4590
4591	/**
4592	* For typedef'ing or declaring a C instruction implementation function taking
4593	* five extra arguments.
4594	*
4595	* @param a_Name The name of the type.
4596	* @param a_Type0 The type of the 1st argument
4597	* @param a_Arg0 The name of the 1st argument.
4598	* @param a_Type1 The type of the 2nd argument.
4599	* @param a_Arg1 The name of the 2nd argument.
4600	* @param a_Type2 The type of the 3rd argument.
4601	* @param a_Arg2 The name of the 3rd argument.
4602	* @param a_Type3 The type of the 4th argument.
4603	* @param a_Arg3 The name of the 4th argument.
4604	* @param a_Type4 The type of the 5th argument.
4605	* @param a_Arg4 The name of the 5th argument.
4606	*/
4607	# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
4608	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, \
4609	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
4610	a_Type3 a_Arg3, a_Type4 a_Arg4))
4611	/**
4612	* For defining a C instruction implementation function taking five extra
4613	* arguments.
4614	*
4615	* @param a_Name The name of the function.
4616	* @param a_Type0 The type of the 1st argument
4617	* @param a_Arg0 The name of the 1st argument.
4618	* @param a_Type1 The type of the 2nd argument.
4619	* @param a_Arg1 The name of the 2nd argument.
4620	* @param a_Type2 The type of the 3rd argument.
4621	* @param a_Arg2 The name of the 3rd argument.
4622	* @param a_Type3 The type of the 4th argument.
4623	* @param a_Arg3 The name of the 4th argument.
4624	* @param a_Type4 The type of the 5th argument.
4625	* @param a_Arg4 The name of the 5th argument.
4626	*/
4627	# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
4628	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4629	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
4630	/**
4631	* Prototype version of IEM_CIMPL_DEF_5.
4632	*/
4633	# define IEM_CIMPL_PROTO_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
4634	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4635	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
4636	/**
4637	* For calling a C instruction implementation function taking five extra
4638	* arguments.
4639	*
4640	* This special call macro adds default arguments to the call and allow us to
4641	* change these later.
4642	*
4643	* @param a_fn The name of the function.
4644	* @param a0 The name of the 1st argument.
4645	* @param a1 The name of the 2nd argument.
4646	* @param a2 The name of the 3rd argument.
4647	* @param a3 The name of the 4th argument.
4648	* @param a4 The name of the 5th argument.
4649	*/
4650	# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
4651
4652	/** @} */
4653
4654
4655	/** @name Opcode Decoder Function Types.
4656	* @{ */
4657
4658	/** @typedef PFNIEMOP
4659	* Pointer to an opcode decoder function.
4660	*/
4661
4662	/** @def FNIEMOP_DEF
4663	* Define an opcode decoder function.
4664	*
4665	* We're using macors for this so that adding and removing parameters as well as
4666	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL
4667	*
4668	* @param a_Name The function name.
4669	*/
4670
4671	/** @typedef PFNIEMOPRM
4672	* Pointer to an opcode decoder function with RM byte.
4673	*/
4674
4675	/** @def FNIEMOPRM_DEF
4676	* Define an opcode decoder function with RM byte.
4677	*
4678	* We're using macors for this so that adding and removing parameters as well as
4679	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL_1
4680	*
4681	* @param a_Name The function name.
4682	*/
4683
4684	#if defined(__GNUC__) && defined(RT_ARCH_X86)
4685	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOP)(PVMCPUCC pVCpu);
4686	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4687	# define FNIEMOP_DEF(a_Name) \
4688	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu)
4689	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4690	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
4691	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4692	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
4693
4694	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
4695	typedef VBOXSTRICTRC (__fastcall * PFNIEMOP)(PVMCPUCC pVCpu);
4696	typedef VBOXSTRICTRC (__fastcall * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4697	# define FNIEMOP_DEF(a_Name) \
4698	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
4699	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4700	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
4701	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4702	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
4703
4704	#elif defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
4705	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
4706	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4707	# define FNIEMOP_DEF(a_Name) \
4708	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu)
4709	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4710	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
4711	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4712	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
4713
4714	#else
4715	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
4716	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4717	# define FNIEMOP_DEF(a_Name) \
4718	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
4719	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4720	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
4721	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4722	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
4723
4724	#endif
4725	#define FNIEMOPRM_DEF(a_Name) FNIEMOP_DEF_1(a_Name, uint8_t, bRm)
4726
4727	/**
4728	* Call an opcode decoder function.
4729	*
4730	* We're using macors for this so that adding and removing parameters can be
4731	* done as we please. See FNIEMOP_DEF.
4732	*/
4733	#define FNIEMOP_CALL(a_pfn) (a_pfn)(pVCpu)
4734
4735	/**
4736	* Call a common opcode decoder function taking one extra argument.
4737	*
4738	* We're using macors for this so that adding and removing parameters can be
4739	* done as we please. See FNIEMOP_DEF_1.
4740	*/
4741	#define FNIEMOP_CALL_1(a_pfn, a0) (a_pfn)(pVCpu, a0)
4742
4743	/**
4744	* Call a common opcode decoder function taking one extra argument.
4745	*
4746	* We're using macors for this so that adding and removing parameters can be
4747	* done as we please. See FNIEMOP_DEF_1.
4748	*/
4749	#define FNIEMOP_CALL_2(a_pfn, a0, a1) (a_pfn)(pVCpu, a0, a1)
4750	/** @} */
4751
4752
4753	/** @name Misc Helpers
4754	* @{ */
4755
4756	/** Used to shut up GCC warnings about variables that 'may be used uninitialized'
4757	* due to GCC lacking knowledge about the value range of a switch. */
4758	#if RT_CPLUSPLUS_PREREQ(202000)
4759	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: [[unlikely]] AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
4760	#else
4761	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
4762	#endif
4763
4764	/** Variant of IEM_NOT_REACHED_DEFAULT_CASE_RET that returns a custom value. */
4765	#if RT_CPLUSPLUS_PREREQ(202000)
4766	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: [[unlikely]] AssertFailedReturn(a_RetValue)
4767	#else
4768	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: AssertFailedReturn(a_RetValue)
4769	#endif
4770
4771	/**
4772	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
4773	* occation.
4774	*/
4775	#ifdef LOG_ENABLED
4776	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
4777	do { \
4778	/Log/ LogAlways(("%s: returning IEM_RETURN_ASPECT_NOT_IMPLEMENTED (line %d)\n", __FUNCTION__, __LINE__)); \
4779	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
4780	} while (0)
4781	#else
4782	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
4783	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
4784	#endif
4785
4786	/**
4787	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
4788	* occation using the supplied logger statement.
4789	*
4790	* @param a_LoggerArgs What to log on failure.
4791	*/
4792	#ifdef LOG_ENABLED
4793	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
4794	do { \
4795	LogAlways((LOG_FN_FMT ": ", __PRETTY_FUNCTION__)); LogAlways(a_LoggerArgs); \
4796	/LogFunc(a_LoggerArgs);/ \
4797	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
4798	} while (0)
4799	#else
4800	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
4801	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
4802	#endif
4803
4804	/**
4805	* Gets the CPU mode (from fExec) as a IEMMODE value.
4806	*
4807	* @returns IEMMODE
4808	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4809	*/
4810	#define IEM_GET_CPU_MODE(a_pVCpu) ((a_pVCpu)->iem.s.fExec & IEM_F_MODE_CPUMODE_MASK)
4811
4812	/**
4813	* Check if we're currently executing in real or virtual 8086 mode.
4814	*
4815	* @returns @c true if it is, @c false if not.
4816	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4817	*/
4818	#define IEM_IS_REAL_OR_V86_MODE(a_pVCpu) (( ((a_pVCpu)->iem.s.fExec ^ IEM_F_MODE_X86_PROT_MASK) \
4819	& (IEM_F_MODE_X86_V86_MASK \| IEM_F_MODE_X86_PROT_MASK)) != 0)
4820
4821	/**
4822	* Check if we're currently executing in virtual 8086 mode.
4823	*
4824	* @returns @c true if it is, @c false if not.
4825	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4826	*/
4827	#define IEM_IS_V86_MODE(a_pVCpu) (((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_V86_MASK) != 0)
4828
4829	/**
4830	* Check if we're currently executing in long mode.
4831	*
4832	* @returns @c true if it is, @c false if not.
4833	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4834	*/
4835	#define IEM_IS_LONG_MODE(a_pVCpu) (CPUMIsGuestInLongModeEx(IEM_GET_CTX(a_pVCpu)))
4836
4837	/**
4838	* Check if we're currently executing in a 16-bit code segment.
4839	*
4840	* @returns @c true if it is, @c false if not.
4841	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4842	*/
4843	#define IEM_IS_16BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_16BIT)
4844
4845	/**
4846	* Check if we're currently executing in a 32-bit code segment.
4847	*
4848	* @returns @c true if it is, @c false if not.
4849	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4850	*/
4851	#define IEM_IS_32BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_32BIT)
4852
4853	/**
4854	* Check if we're currently executing in a 64-bit code segment.
4855	*
4856	* @returns @c true if it is, @c false if not.
4857	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4858	*/
4859	#define IEM_IS_64BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_64BIT)
4860
4861	/**
4862	* Check if we're currently executing in real mode.
4863	*
4864	* @returns @c true if it is, @c false if not.
4865	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4866	*/
4867	#define IEM_IS_REAL_MODE(a_pVCpu) (!((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_PROT_MASK))
4868
4869	/**
4870	* Gets the current protection level (CPL).
4871	*
4872	* @returns 0..3
4873	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4874	*/
4875	#define IEM_GET_CPL(a_pVCpu) (((a_pVCpu)->iem.s.fExec >> IEM_F_X86_CPL_SHIFT) & IEM_F_X86_CPL_SMASK)
4876
4877	/**
4878	* Sets the current protection level (CPL).
4879	*
4880	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4881	*/
4882	#define IEM_SET_CPL(a_pVCpu, a_uCpl) \
4883	do { (a_pVCpu)->iem.s.fExec = ((a_pVCpu)->iem.s.fExec & ~IEM_F_X86_CPL_MASK) \| ((a_uCpl) << IEM_F_X86_CPL_SHIFT); } while (0)
4884
4885	/**
4886	* Returns a (const) pointer to the CPUMFEATURES for the guest CPU.
4887	* @returns PCCPUMFEATURES
4888	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4889	*/
4890	#define IEM_GET_GUEST_CPU_FEATURES(a_pVCpu) (&((a_pVCpu)->CTX_SUFF(pVM)->cpum.ro.GuestFeatures))
4891
4892	/**
4893	* Returns a (const) pointer to the CPUMFEATURES for the host CPU.
4894	* @returns PCCPUMFEATURES
4895	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4896	*/
4897	#define IEM_GET_HOST_CPU_FEATURES(a_pVCpu) (&g_CpumHostFeatures.s)
4898
4899	/**
4900	* Evaluates to true if we're presenting an Intel CPU to the guest.
4901	*/
4902	#define IEM_IS_GUEST_CPU_INTEL(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL )
4903
4904	/**
4905	* Evaluates to true if we're presenting an AMD CPU to the guest.
4906	*/
4907	#define IEM_IS_GUEST_CPU_AMD(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_AMD \|\| (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_HYGON )
4908
4909	/**
4910	* Check if the address is canonical.
4911	*/
4912	#define IEM_IS_CANONICAL(a_u64Addr) X86_IS_CANONICAL(a_u64Addr)
4913
4914	/** Checks if the ModR/M byte is in register mode or not. */
4915	#define IEM_IS_MODRM_REG_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT) )
4916	/** Checks if the ModR/M byte is in memory mode or not. */
4917	#define IEM_IS_MODRM_MEM_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT) )
4918
4919	/**
4920	* Gets the register (reg) part of a ModR/M encoding, with REX.R added in.
4921	*
4922	* For use during decoding.
4923	*/
4924	#define IEM_GET_MODRM_REG(a_pVCpu, a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| (a_pVCpu)->iem.s.uRexReg )
4925	/**
4926	* Gets the r/m part of a ModR/M encoding as a register index, with REX.B added in.
4927	*
4928	* For use during decoding.
4929	*/
4930	#define IEM_GET_MODRM_RM(a_pVCpu, a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) \| (a_pVCpu)->iem.s.uRexB )
4931
4932	/**
4933	* Gets the register (reg) part of a ModR/M encoding, without REX.R.
4934	*
4935	* For use during decoding.
4936	*/
4937	#define IEM_GET_MODRM_REG_8(a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) )
4938	/**
4939	* Gets the r/m part of a ModR/M encoding as a register index, without REX.B.
4940	*
4941	* For use during decoding.
4942	*/
4943	#define IEM_GET_MODRM_RM_8(a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) )
4944
4945	/**
4946	* Gets the register (reg) part of a ModR/M encoding as an extended 8-bit
4947	* register index, with REX.R added in.
4948	*
4949	* For use during decoding.
4950	*
4951	* @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
4952	*/
4953	#define IEM_GET_MODRM_REG_EX8(a_pVCpu, a_bRm) \
4954	( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
4955	\|\| !((a_bRm) & (4 << X86_MODRM_REG_SHIFT)) /* IEM_GET_MODRM_REG(pVCpu, a_bRm) < 4 */ \
4956	? IEM_GET_MODRM_REG(pVCpu, a_bRm) : (((a_bRm) >> X86_MODRM_REG_SHIFT) & 3) \| 16)
4957	/**
4958	* Gets the r/m part of a ModR/M encoding as an extended 8-bit register index,
4959	* with REX.B added in.
4960	*
4961	* For use during decoding.
4962	*
4963	* @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
4964	*/
4965	#define IEM_GET_MODRM_RM_EX8(a_pVCpu, a_bRm) \
4966	( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
4967	\|\| !((a_bRm) & 4) /* IEM_GET_MODRM_RM(pVCpu, a_bRm) < 4 */ \
4968	? IEM_GET_MODRM_RM(pVCpu, a_bRm) : ((a_bRm) & 3) \| 16)
4969
4970	/**
4971	* Combines the prefix REX and ModR/M byte for passing to
4972	* iemOpHlpCalcRmEffAddrThreadedAddr64().
4973	*
4974	* @returns The ModRM byte but with bit 3 set to REX.B and bit 4 to REX.X.
4975	* The two bits are part of the REG sub-field, which isn't needed in
4976	* iemOpHlpCalcRmEffAddrThreadedAddr64().
4977	*
4978	* For use during decoding/recompiling.
4979	*/
4980	#define IEM_GET_MODRM_EX(a_pVCpu, a_bRm) \
4981	( ((a_bRm) & ~X86_MODRM_REG_MASK) \
4982	\| (uint8_t)( (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X)) >> (25 - 3) ) )
4983	AssertCompile(IEM_OP_PRF_REX_B == RT_BIT_32(25));
4984	AssertCompile(IEM_OP_PRF_REX_X == RT_BIT_32(26));
4985
4986	/**
4987	* Gets the effective VEX.VVVV value.
4988	*
4989	* The 4th bit is ignored if not 64-bit code.
4990	* @returns effective V-register value.
4991	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4992	*/
4993	#define IEM_GET_EFFECTIVE_VVVV(a_pVCpu) \
4994	(IEM_IS_64BIT_CODE(a_pVCpu) ? (a_pVCpu)->iem.s.uVex3rdReg : (a_pVCpu)->iem.s.uVex3rdReg & 7)
4995
4996
4997	/**
4998	* Gets the register (reg) part of a the special 4th register byte used by
4999	* vblendvps and vblendvpd.
5000	*
5001	* For use during decoding.
5002	*/
5003	#define IEM_GET_IMM8_REG(a_pVCpu, a_bRegImm8) \
5004	(IEM_IS_64BIT_CODE(a_pVCpu) ? (a_bRegImm8) >> 4 : ((a_bRegImm8) >> 4) & 7)
5005
5006
5007	/**
5008	* Checks if we're executing inside an AMD-V or VT-x guest.
5009	*/
5010	#if defined(VBOX_WITH_NESTED_HWVIRT_VMX) \|\| defined(VBOX_WITH_NESTED_HWVIRT_SVM)
5011	# define IEM_IS_IN_GUEST(a_pVCpu) RT_BOOL((a_pVCpu)->iem.s.fExec & IEM_F_X86_CTX_IN_GUEST)
5012	#else
5013	# define IEM_IS_IN_GUEST(a_pVCpu) false
5014	#endif
5015
5016
5017	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5018
5019	/**
5020	* Check if the guest has entered VMX root operation.
5021	*/
5022	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxRootMode(IEM_GET_CTX(a_pVCpu)))
5023
5024	/**
5025	* Check if the guest has entered VMX non-root operation.
5026	*/
5027	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) ( ((a_pVCpu)->iem.s.fExec & (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST)) \
5028	== (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST) )
5029
5030	/**
5031	* Check if the nested-guest has the given Pin-based VM-execution control set.
5032	*/
5033	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_PinCtl) (CPUMIsGuestVmxPinCtlsSet(IEM_GET_CTX(a_pVCpu), (a_PinCtl)))
5034
5035	/**
5036	* Check if the nested-guest has the given Processor-based VM-execution control set.
5037	*/
5038	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_ProcCtl) (CPUMIsGuestVmxProcCtlsSet(IEM_GET_CTX(a_pVCpu), (a_ProcCtl)))
5039
5040	/**
5041	* Check if the nested-guest has the given Secondary Processor-based VM-execution
5042	* control set.
5043	*/
5044	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_ProcCtl2) (CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(a_pVCpu), (a_ProcCtl2)))
5045
5046	/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
5047	# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
5048
5049	/** Whether a shadow VMCS is present for the given VCPU. */
5050	# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
5051
5052	/** Gets the VMXON region pointer. */
5053	# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
5054
5055	/** Gets the guest-physical address of the current VMCS for the given VCPU. */
5056	# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
5057
5058	/** Whether a current VMCS is present for the given VCPU. */
5059	# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
5060
5061	/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
5062	# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
5063	do \
5064	{ \
5065	Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
5066	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
5067	} while (0)
5068
5069	/** Clears any current VMCS for the given VCPU. */
5070	# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
5071	do \
5072	{ \
5073	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
5074	} while (0)
5075
5076	/**
5077	* Invokes the VMX VM-exit handler for an instruction intercept.
5078	*/
5079	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) \
5080	do { return iemVmxVmexitInstr((a_pVCpu), (a_uExitReason), (a_cbInstr)); } while (0)
5081
5082	/**
5083	* Invokes the VMX VM-exit handler for an instruction intercept where the
5084	* instruction provides additional VM-exit information.
5085	*/
5086	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) \
5087	do { return iemVmxVmexitInstrNeedsInfo((a_pVCpu), (a_uExitReason), (a_uInstrId), (a_cbInstr)); } while (0)
5088
5089	/**
5090	* Invokes the VMX VM-exit handler for a task switch.
5091	*/
5092	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) \
5093	do { return iemVmxVmexitTaskSwitch((a_pVCpu), (a_enmTaskSwitch), (a_SelNewTss), (a_cbInstr)); } while (0)
5094
5095	/**
5096	* Invokes the VMX VM-exit handler for MWAIT.
5097	*/
5098	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) \
5099	do { return iemVmxVmexitInstrMwait((a_pVCpu), (a_fMonitorArmed), (a_cbInstr)); } while (0)
5100
5101	/**
5102	* Invokes the VMX VM-exit handler for EPT faults.
5103	*/
5104	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) \
5105	do { return iemVmxVmexitEpt(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr); } while (0)
5106
5107	/**
5108	* Invokes the VMX VM-exit handler.
5109	*/
5110	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) \
5111	do { return iemVmxVmexit((a_pVCpu), (a_uExitReason), (a_uExitQual)); } while (0)
5112
5113	#else
5114	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (false)
5115	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (false)
5116	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_cbInstr) (false)
5117	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_cbInstr) (false)
5118	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_cbInstr) (false)
5119	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5120	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5121	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5122	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5123	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5124	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) do { return VERR_VMX_IPE_1; } while (0)
5125
5126	#endif
5127
5128	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5129	/**
5130	* Checks if we're executing a guest using AMD-V.
5131	*/
5132	# define IEM_SVM_IS_IN_GUEST(a_pVCpu) ( (a_pVCpu->iem.s.fExec & (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST)) \
5133	== (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST))
5134	/**
5135	* Check if an SVM control/instruction intercept is set.
5136	*/
5137	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) \
5138	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmCtrlInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_Intercept)))
5139
5140	/**
5141	* Check if an SVM read CRx intercept is set.
5142	*/
5143	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
5144	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
5145
5146	/**
5147	* Check if an SVM write CRx intercept is set.
5148	*/
5149	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
5150	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
5151
5152	/**
5153	* Check if an SVM read DRx intercept is set.
5154	*/
5155	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
5156	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
5157
5158	/**
5159	* Check if an SVM write DRx intercept is set.
5160	*/
5161	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
5162	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
5163
5164	/**
5165	* Check if an SVM exception intercept is set.
5166	*/
5167	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) \
5168	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmXcptInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uVector)))
5169
5170	/**
5171	* Invokes the SVM \#VMEXIT handler for the nested-guest.
5172	*/
5173	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
5174	do { return iemSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2)); } while (0)
5175
5176	/**
5177	* Invokes the 'MOV CRx' SVM \#VMEXIT handler after constructing the
5178	* corresponding decode assist information.
5179	*/
5180	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) \
5181	do \
5182	{ \
5183	uint64_t uExitInfo1; \
5184	if ( IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmDecodeAssists \
5185	&& (a_enmAccessCrX) == IEMACCESSCRX_MOV_CRX) \
5186	uExitInfo1 = SVM_EXIT1_MOV_CRX_MASK \| ((a_iGReg) & 7); \
5187	else \
5188	uExitInfo1 = 0; \
5189	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, uExitInfo1, 0); \
5190	} while (0)
5191
5192	/** Check and handles SVM nested-guest instruction intercept and updates
5193	* NRIP if needed.
5194	*/
5195	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
5196	do \
5197	{ \
5198	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept)) \
5199	{ \
5200	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
5201	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2); \
5202	} \
5203	} while (0)
5204
5205	/** Checks and handles SVM nested-guest CR0 read intercept. */
5206	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
5207	do \
5208	{ \
5209	if (!IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, 0)) \
5210	{ /* probably likely */ } \
5211	else \
5212	{ \
5213	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
5214	IEM_SVM_VMEXIT_RET(a_pVCpu, SVM_EXIT_READ_CR0, a_uExitInfo1, a_uExitInfo2); \
5215	} \
5216	} while (0)
5217
5218	/**
5219	* Updates the NextRIP (NRI) field in the nested-guest VMCB.
5220	*/
5221	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) \
5222	do { \
5223	if (IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmNextRipSave) \
5224	CPUMGuestSvmUpdateNRip(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_cbInstr)); \
5225	} while (0)
5226
5227	#else
5228	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) (false)
5229	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
5230	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
5231	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
5232	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
5233	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) (false)
5234	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { return VERR_SVM_IPE_1; } while (0)
5235	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) do { return VERR_SVM_IPE_1; } while (0)
5236	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, \
5237	a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
5238	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
5239	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) do { } while (0)
5240
5241	#endif
5242
5243	/** @} */
5244
5245	uint32_t iemCalcExecDbgFlagsSlow(PVMCPUCC pVCpu);
5246	VBOXSTRICTRC iemExecInjectPendingTrap(PVMCPUCC pVCpu);
5247
5248
5249	/**
5250	* Selector descriptor table entry as fetched by iemMemFetchSelDesc.
5251	*/
5252	typedef union IEMSELDESC
5253	{
5254	/** The legacy view. */
5255	X86DESC Legacy;
5256	/** The long mode view. */
5257	X86DESC64 Long;
5258	} IEMSELDESC;
5259	/** Pointer to a selector descriptor table entry. */
5260	typedef IEMSELDESC *PIEMSELDESC;
5261
5262	/** @name Raising Exceptions.
5263	* @{ */
5264	VBOXSTRICTRC iemTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, uint32_t uNextEip, uint32_t fFlags,
5265	uint16_t uErr, uint64_t uCr2, RTSEL SelTSS, PIEMSELDESC pNewDescTSS) RT_NOEXCEPT;
5266
5267	VBOXSTRICTRC iemRaiseXcptOrInt(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags,
5268	uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
5269	#ifdef IEM_WITH_SETJMP
5270	DECL_NO_RETURN(void) iemRaiseXcptOrIntJmp(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector,
5271	uint32_t fFlags, uint16_t uErr, uint64_t uCr2) IEM_NOEXCEPT_MAY_LONGJMP;
5272	#endif
5273	VBOXSTRICTRC iemRaiseDivideError(PVMCPUCC pVCpu) RT_NOEXCEPT;
5274	#ifdef IEM_WITH_SETJMP
5275	DECL_NO_RETURN(void) iemRaiseDivideErrorJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5276	#endif
5277	VBOXSTRICTRC iemRaiseDebugException(PVMCPUCC pVCpu) RT_NOEXCEPT;
5278	VBOXSTRICTRC iemRaiseBoundRangeExceeded(PVMCPUCC pVCpu) RT_NOEXCEPT;
5279	VBOXSTRICTRC iemRaiseUndefinedOpcode(PVMCPUCC pVCpu) RT_NOEXCEPT;
5280	#ifdef IEM_WITH_SETJMP
5281	DECL_NO_RETURN(void) iemRaiseUndefinedOpcodeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5282	#endif
5283	VBOXSTRICTRC iemRaiseDeviceNotAvailable(PVMCPUCC pVCpu) RT_NOEXCEPT;
5284	#ifdef IEM_WITH_SETJMP
5285	DECL_NO_RETURN(void) iemRaiseDeviceNotAvailableJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5286	#endif
5287	VBOXSTRICTRC iemRaiseTaskSwitchFaultWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5288	VBOXSTRICTRC iemRaiseTaskSwitchFaultCurrentTSS(PVMCPUCC pVCpu) RT_NOEXCEPT;
5289	VBOXSTRICTRC iemRaiseTaskSwitchFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
5290	VBOXSTRICTRC iemRaiseTaskSwitchFaultBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5291	/VBOXSTRICTRC iemRaiseSelectorNotPresent(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;/
5292	VBOXSTRICTRC iemRaiseSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5293	VBOXSTRICTRC iemRaiseSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5294	VBOXSTRICTRC iemRaiseStackSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5295	VBOXSTRICTRC iemRaiseStackSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5296	VBOXSTRICTRC iemRaiseGeneralProtectionFault(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5297	VBOXSTRICTRC iemRaiseGeneralProtectionFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
5298	#ifdef IEM_WITH_SETJMP
5299	DECL_NO_RETURN(void) iemRaiseGeneralProtectionFault0Jmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5300	#endif
5301	VBOXSTRICTRC iemRaiseGeneralProtectionFaultBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
5302	VBOXSTRICTRC iemRaiseNotCanonical(PVMCPUCC pVCpu) RT_NOEXCEPT;
5303	VBOXSTRICTRC iemRaiseSelectorBounds(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
5304	#ifdef IEM_WITH_SETJMP
5305	DECL_NO_RETURN(void) iemRaiseSelectorBoundsJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
5306	#endif
5307	VBOXSTRICTRC iemRaiseSelectorBoundsBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
5308	#ifdef IEM_WITH_SETJMP
5309	DECL_NO_RETURN(void) iemRaiseSelectorBoundsBySelectorJmp(PVMCPUCC pVCpu, RTSEL Sel) IEM_NOEXCEPT_MAY_LONGJMP;
5310	#endif
5311	VBOXSTRICTRC iemRaiseSelectorInvalidAccess(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
5312	#ifdef IEM_WITH_SETJMP
5313	DECL_NO_RETURN(void) iemRaiseSelectorInvalidAccessJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
5314	#endif
5315	VBOXSTRICTRC iemRaisePageFault(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) RT_NOEXCEPT;
5316	#ifdef IEM_WITH_SETJMP
5317	DECL_NO_RETURN(void) iemRaisePageFaultJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) IEM_NOEXCEPT_MAY_LONGJMP;
5318	#endif
5319	VBOXSTRICTRC iemRaiseMathFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
5320	#ifdef IEM_WITH_SETJMP
5321	DECL_NO_RETURN(void) iemRaiseMathFaultJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5322	#endif
5323	VBOXSTRICTRC iemRaiseAlignmentCheckException(PVMCPUCC pVCpu) RT_NOEXCEPT;
5324	#ifdef IEM_WITH_SETJMP
5325	DECL_NO_RETURN(void) iemRaiseAlignmentCheckExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5326	#endif
5327	VBOXSTRICTRC iemRaiseSimdFpException(PVMCPUCC pVCpu) RT_NOEXCEPT;
5328	#ifdef IEM_WITH_SETJMP
5329	DECL_NO_RETURN(void) iemRaiseSimdFpExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5330	#endif
5331
5332	void iemLogSyscallRealModeInt(PVMCPUCC pVCpu, uint8_t u8Vector, uint8_t cbInstr);
5333	void iemLogSyscallProtModeInt(PVMCPUCC pVCpu, uint8_t u8Vector, uint8_t cbInstr);
5334
5335	IEM_CIMPL_DEF_0(iemCImplRaiseDivideError);
5336	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidLockPrefix);
5337	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidOpcode);
5338
5339	/**
5340	* Macro for calling iemCImplRaiseDivideError().
5341	*
5342	* This is for things that will _always_ decode to an \#DE, taking the
5343	* recompiler into consideration and everything.
5344	*
5345	* @return Strict VBox status code.
5346	*/
5347	#define IEMOP_RAISE_DIVIDE_ERROR_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseDivideError)
5348
5349	/**
5350	* Macro for calling iemCImplRaiseInvalidLockPrefix().
5351	*
5352	* This is for things that will _always_ decode to an \#UD, taking the
5353	* recompiler into consideration and everything.
5354	*
5355	* @return Strict VBox status code.
5356	*/
5357	#define IEMOP_RAISE_INVALID_LOCK_PREFIX_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidLockPrefix)
5358
5359	/**
5360	* Macro for calling iemCImplRaiseInvalidOpcode() for decode/static \#UDs.
5361	*
5362	* This is for things that will _always_ decode to an \#UD, taking the
5363	* recompiler into consideration and everything.
5364	*
5365	* @return Strict VBox status code.
5366	*/
5367	#define IEMOP_RAISE_INVALID_OPCODE_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidOpcode)
5368
5369	/**
5370	* Macro for calling iemCImplRaiseInvalidOpcode() for runtime-style \#UDs.
5371	*
5372	* Using this macro means you've got _buggy_ _code_ and are doing things that
5373	* belongs exclusively in IEMAllCImpl.cpp during decoding.
5374	*
5375	* @return Strict VBox status code.
5376	* @see IEMOP_RAISE_INVALID_OPCODE_RET
5377	*/
5378	#define IEMOP_RAISE_INVALID_OPCODE_RUNTIME_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidOpcode)
5379
5380	/** @} */
5381
5382	/** @name Register Access.
5383	* @{ */
5384	VBOXSTRICTRC iemRegRipRelativeJumpS8AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int8_t offNextInstr,
5385	IEMMODE enmEffOpSize) RT_NOEXCEPT;
5386	VBOXSTRICTRC iemRegRipRelativeJumpS16AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int16_t offNextInstr) RT_NOEXCEPT;
5387	VBOXSTRICTRC iemRegRipRelativeJumpS32AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int32_t offNextInstr,
5388	IEMMODE enmEffOpSize) RT_NOEXCEPT;
5389	/** @} */
5390
5391	/** @name FPU access and helpers.
5392	* @{ */
5393	void iemFpuPushResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
5394	void iemFpuPushResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5395	void iemFpuPushResultTwo(PVMCPUCC pVCpu, PIEMFPURESULTTWO pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
5396	void iemFpuStoreResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
5397	void iemFpuStoreResultThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
5398	void iemFpuStoreResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
5399	uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5400	void iemFpuStoreResultWithMemOpThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
5401	uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5402	void iemFpuUpdateOpcodeAndIp(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5403	void iemFpuUpdateFSW(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
5404	void iemFpuUpdateFSWThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
5405	void iemFpuUpdateFSWWithMemOp(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5406	void iemFpuUpdateFSWThenPopPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
5407	void iemFpuUpdateFSWWithMemOpThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5408	void iemFpuStackUnderflow(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
5409	void iemFpuStackUnderflowWithMemOp(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5410	void iemFpuStackUnderflowThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
5411	void iemFpuStackUnderflowWithMemOpThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5412	void iemFpuStackUnderflowThenPopPop(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5413	void iemFpuStackPushUnderflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5414	void iemFpuStackPushUnderflowTwo(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5415	void iemFpuStackPushOverflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5416	void iemFpuStackPushOverflowWithMemOp(PVMCPUCC pVCpu, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5417	/** @} */
5418
5419	/** @name SSE+AVX SIMD access and helpers.
5420	* @{ */
5421	void iemSseStoreResult(PVMCPUCC pVCpu, PCIEMSSERESULT pResult, uint8_t iXmmReg) RT_NOEXCEPT;
5422	void iemSseUpdateMxcsr(PVMCPUCC pVCpu, uint32_t fMxcsr) RT_NOEXCEPT;
5423	/** @} */
5424
5425	/** @name Memory access.
5426	* @{ */
5427
5428	/** Report a \#GP instead of \#AC and do not restrict to ring-3 */
5429	#define IEM_MEMMAP_F_ALIGN_GP RT_BIT_32(16)
5430	/** SSE access that should report a \#GP instead of \#AC, unless MXCSR.MM=1
5431	* when it works like normal \#AC. Always used with IEM_MEMMAP_F_ALIGN_GP. */
5432	#define IEM_MEMMAP_F_ALIGN_SSE RT_BIT_32(17)
5433	/** If \#AC is applicable, raise it. Always used with IEM_MEMMAP_F_ALIGN_GP.
5434	* Users include FXSAVE & FXRSTOR. */
5435	#define IEM_MEMMAP_F_ALIGN_GP_OR_AC RT_BIT_32(18)
5436
5437	VBOXSTRICTRC iemMemMap(PVMCPUCC pVCpu, void *ppvMem, uint8_t pbUnmapInfo, size_t cbMem, uint8_t iSegReg, RTGCPTR GCPtrMem,
5438	uint32_t fAccess, uint32_t uAlignCtl) RT_NOEXCEPT;
5439	VBOXSTRICTRC iemMemCommitAndUnmap(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5440	#ifndef IN_RING3
5441	VBOXSTRICTRC iemMemCommitAndUnmapPostponeTroubleToR3(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5442	#endif
5443	void iemMemRollbackAndUnmap(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5444	void iemMemRollback(PVMCPUCC pVCpu) RT_NOEXCEPT;
5445	VBOXSTRICTRC iemMemApplySegment(PVMCPUCC pVCpu, uint32_t fAccess, uint8_t iSegReg, size_t cbMem, PRTGCPTR pGCPtrMem) RT_NOEXCEPT;
5446	VBOXSTRICTRC iemMemMarkSelDescAccessed(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5447	VBOXSTRICTRC iemMemPageTranslateAndCheckAccess(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t cbAccess, uint32_t fAccess, PRTGCPHYS pGCPhysMem) RT_NOEXCEPT;
5448
5449	void iemOpcodeFlushLight(PVMCPUCC pVCpu, uint8_t cbInstr);
5450	void iemOpcodeFlushHeavy(PVMCPUCC pVCpu, uint8_t cbInstr);
5451	#ifdef IEM_WITH_CODE_TLB
5452	void iemOpcodeFetchBytesJmp(PVMCPUCC pVCpu, size_t cbDst, void *pvDst) IEM_NOEXCEPT_MAY_LONGJMP;
5453	#else
5454	VBOXSTRICTRC iemOpcodeFetchMoreBytes(PVMCPUCC pVCpu, size_t cbMin) RT_NOEXCEPT;
5455	#endif
5456	#ifdef IEM_WITH_SETJMP
5457	uint8_t iemOpcodeGetNextU8SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5458	uint16_t iemOpcodeGetNextU16SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5459	uint32_t iemOpcodeGetNextU32SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5460	uint64_t iemOpcodeGetNextU64SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5461	#else
5462	VBOXSTRICTRC iemOpcodeGetNextU8Slow(PVMCPUCC pVCpu, uint8_t *pb) RT_NOEXCEPT;
5463	VBOXSTRICTRC iemOpcodeGetNextS8SxU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
5464	VBOXSTRICTRC iemOpcodeGetNextS8SxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
5465	VBOXSTRICTRC iemOpcodeGetNextS8SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5466	VBOXSTRICTRC iemOpcodeGetNextU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
5467	VBOXSTRICTRC iemOpcodeGetNextU16ZxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
5468	VBOXSTRICTRC iemOpcodeGetNextU16ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5469	VBOXSTRICTRC iemOpcodeGetNextU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
5470	VBOXSTRICTRC iemOpcodeGetNextU32ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5471	VBOXSTRICTRC iemOpcodeGetNextS32SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5472	VBOXSTRICTRC iemOpcodeGetNextU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5473	#endif
5474
5475	VBOXSTRICTRC iemMemFetchDataU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5476	VBOXSTRICTRC iemMemFetchDataU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5477	VBOXSTRICTRC iemMemFetchDataU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5478	VBOXSTRICTRC iemMemFetchDataU32_ZX_U64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5479	VBOXSTRICTRC iemMemFetchDataU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5480	VBOXSTRICTRC iemMemFetchDataU64AlignedU128(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5481	VBOXSTRICTRC iemMemFetchDataR80(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5482	VBOXSTRICTRC iemMemFetchDataD80(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5483	VBOXSTRICTRC iemMemFetchDataU128(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5484	VBOXSTRICTRC iemMemFetchDataU128NoAc(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5485	VBOXSTRICTRC iemMemFetchDataU128AlignedSse(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5486	VBOXSTRICTRC iemMemFetchDataU256(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5487	VBOXSTRICTRC iemMemFetchDataU256NoAc(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5488	VBOXSTRICTRC iemMemFetchDataU256AlignedAvx(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5489	VBOXSTRICTRC iemMemFetchDataXdtr(PVMCPUCC pVCpu, uint16_t *pcbLimit, PRTGCPTR pGCPtrBase, uint8_t iSegReg,
5490	RTGCPTR GCPtrMem, IEMMODE enmOpSize) RT_NOEXCEPT;
5491	#ifdef IEM_WITH_SETJMP
5492	uint8_t iemMemFetchDataU8SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5493	uint16_t iemMemFetchDataU16SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5494	uint32_t iemMemFetchDataU32SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5495	uint32_t iemMemFlatFetchDataU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5496	uint64_t iemMemFetchDataU64SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5497	uint64_t iemMemFetchDataU64AlignedU128SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5498	void iemMemFetchDataR80SafeJmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5499	void iemMemFetchDataD80SafeJmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5500	void iemMemFetchDataU128SafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5501	void iemMemFetchDataU128NoAcSafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5502	void iemMemFetchDataU128AlignedSseSafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5503	void iemMemFetchDataU256SafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5504	void iemMemFetchDataU256NoAcSafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5505	void iemMemFetchDataU256AlignedAvxSafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5506	# if 0 /* these are inlined now */
5507	uint8_t iemMemFetchDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5508	uint16_t iemMemFetchDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5509	uint32_t iemMemFetchDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5510	uint32_t iemMemFlatFetchDataU32Jmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5511	uint64_t iemMemFetchDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5512	uint64_t iemMemFetchDataU64AlignedU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5513	void iemMemFetchDataR80Jmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5514	void iemMemFetchDataD80Jmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5515	void iemMemFetchDataU128Jmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5516	void iemMemFetchDataU128NoAcJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5517	void iemMemFetchDataU128AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5518	void iemMemFetchDataU256NoAcJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5519	void iemMemFetchDataU256AlignedAvxJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5520	# endif
5521	void iemMemFetchDataU256Jmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5522	#endif
5523
5524	VBOXSTRICTRC iemMemFetchSysU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5525	VBOXSTRICTRC iemMemFetchSysU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5526	VBOXSTRICTRC iemMemFetchSysU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5527	VBOXSTRICTRC iemMemFetchSysU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5528	VBOXSTRICTRC iemMemFetchSelDesc(PVMCPUCC pVCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt) RT_NOEXCEPT;
5529
5530	VBOXSTRICTRC iemMemStoreDataU8(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) RT_NOEXCEPT;
5531	VBOXSTRICTRC iemMemStoreDataU16(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) RT_NOEXCEPT;
5532	VBOXSTRICTRC iemMemStoreDataU32(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) RT_NOEXCEPT;
5533	VBOXSTRICTRC iemMemStoreDataU64(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) RT_NOEXCEPT;
5534	VBOXSTRICTRC iemMemStoreDataU128(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
5535	VBOXSTRICTRC iemMemStoreDataU128NoAc(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
5536	VBOXSTRICTRC iemMemStoreDataU128AlignedSse(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
5537	VBOXSTRICTRC iemMemStoreDataU256(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
5538	VBOXSTRICTRC iemMemStoreDataU256NoAc(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
5539	VBOXSTRICTRC iemMemStoreDataU256AlignedAvx(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
5540	VBOXSTRICTRC iemMemStoreDataXdtr(PVMCPUCC pVCpu, uint16_t cbLimit, RTGCPTR GCPtrBase, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5541	#ifdef IEM_WITH_SETJMP
5542	void iemMemStoreDataU8SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
5543	void iemMemStoreDataU16SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
5544	void iemMemStoreDataU32SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
5545	void iemMemStoreDataU64SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
5546	void iemMemStoreDataU128SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5547	void iemMemStoreDataU128NoAcSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT128U pu128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5548	void iemMemStoreDataU128AlignedSseSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT128U pu128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5549	void iemMemStoreDataU256SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5550	void iemMemStoreDataU256NoAcSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5551	void iemMemStoreDataU256AlignedAvxSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5552	void iemMemStoreDataR80SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTFLOAT80U pr80Value) IEM_NOEXCEPT_MAY_LONGJMP;
5553	void iemMemStoreDataD80SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTPBCD80U pd80Value) IEM_NOEXCEPT_MAY_LONGJMP;
5554	#if 0
5555	void iemMemStoreDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
5556	void iemMemStoreDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
5557	void iemMemStoreDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
5558	void iemMemStoreDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
5559	void iemMemStoreDataU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5560	void iemMemStoreDataNoAcU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5561	void iemMemStoreDataU256NoAcJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5562	void iemMemStoreDataU256AlignedAvxJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5563	#endif
5564	void iemMemStoreDataU128AlignedSseJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5565	void iemMemStoreDataU256Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5566	#endif
5567
5568	#ifdef IEM_WITH_SETJMP
5569	uint8_t iemMemMapDataU8RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5570	uint8_t iemMemMapDataU8AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5571	uint8_t iemMemMapDataU8WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5572	uint8_t const iemMemMapDataU8RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5573	uint16_t iemMemMapDataU16RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5574	uint16_t iemMemMapDataU16AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5575	uint16_t iemMemMapDataU16WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5576	uint16_t const iemMemMapDataU16RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5577	uint32_t iemMemMapDataU32RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5578	uint32_t iemMemMapDataU32AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5579	uint32_t iemMemMapDataU32WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5580	uint32_t const iemMemMapDataU32RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5581	uint64_t iemMemMapDataU64RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5582	uint64_t iemMemMapDataU64AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5583	uint64_t iemMemMapDataU64WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5584	uint64_t const iemMemMapDataU64RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5585	PRTFLOAT80U iemMemMapDataR80RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5586	PRTFLOAT80U iemMemMapDataR80WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5587	PCRTFLOAT80U iemMemMapDataR80RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5588	PRTPBCD80U iemMemMapDataD80RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5589	PRTPBCD80U iemMemMapDataD80WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5590	PCRTPBCD80U iemMemMapDataD80RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5591	PRTUINT128U iemMemMapDataU128RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5592	PRTUINT128U iemMemMapDataU128AtSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5593	PRTUINT128U iemMemMapDataU128WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5594	PCRTUINT128U iemMemMapDataU128RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5595
5596	void iemMemCommitAndUnmapJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5597	void iemMemCommitAndUnmapRwSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5598	void iemMemCommitAndUnmapAtSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5599	void iemMemCommitAndUnmapWoSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5600	void iemMemCommitAndUnmapRoSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5601	void iemMemRollbackAndUnmapWoSafe(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5602	#endif
5603
5604	VBOXSTRICTRC iemMemStackPushBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
5605	void *ppvMem, uint8_t pbUnmapInfo, uint64_t *puNewRsp) RT_NOEXCEPT;
5606	VBOXSTRICTRC iemMemStackPushCommitSpecial(PVMCPUCC pVCpu, uint8_t bUnmapInfo, uint64_t uNewRsp) RT_NOEXCEPT;
5607	VBOXSTRICTRC iemMemStackPushU16(PVMCPUCC pVCpu, uint16_t u16Value) RT_NOEXCEPT;
5608	VBOXSTRICTRC iemMemStackPushU32(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
5609	VBOXSTRICTRC iemMemStackPushU64(PVMCPUCC pVCpu, uint64_t u64Value) RT_NOEXCEPT;
5610	VBOXSTRICTRC iemMemStackPushU16Ex(PVMCPUCC pVCpu, uint16_t u16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5611	VBOXSTRICTRC iemMemStackPushU32Ex(PVMCPUCC pVCpu, uint32_t u32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5612	VBOXSTRICTRC iemMemStackPushU64Ex(PVMCPUCC pVCpu, uint64_t u64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5613	VBOXSTRICTRC iemMemStackPushU32SReg(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
5614	VBOXSTRICTRC iemMemStackPopBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
5615	void const *ppvMem, uint8_t pbUnmapInfo, uint64_t *puNewRsp) RT_NOEXCEPT;
5616	VBOXSTRICTRC iemMemStackPopContinueSpecial(PVMCPUCC pVCpu, size_t off, size_t cbMem,
5617	void const *ppvMem, uint8_t pbUnmapInfo, uint64_t uCurNewRsp) RT_NOEXCEPT;
5618	VBOXSTRICTRC iemMemStackPopDoneSpecial(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5619	VBOXSTRICTRC iemMemStackPopU16(PVMCPUCC pVCpu, uint16_t *pu16Value) RT_NOEXCEPT;
5620	VBOXSTRICTRC iemMemStackPopU32(PVMCPUCC pVCpu, uint32_t *pu32Value) RT_NOEXCEPT;
5621	VBOXSTRICTRC iemMemStackPopU64(PVMCPUCC pVCpu, uint64_t *pu64Value) RT_NOEXCEPT;
5622	VBOXSTRICTRC iemMemStackPopU16Ex(PVMCPUCC pVCpu, uint16_t *pu16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5623	VBOXSTRICTRC iemMemStackPopU32Ex(PVMCPUCC pVCpu, uint32_t *pu32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5624	VBOXSTRICTRC iemMemStackPopU64Ex(PVMCPUCC pVCpu, uint64_t *pu64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5625
5626	#ifdef IEM_WITH_SETJMP
5627	void iemMemStackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5628	void iemMemStackPushU32SafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5629	void iemMemStackPushU32SRegSafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5630	void iemMemStackPushU64SafeJmp(PVMCPUCC pVCpu, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5631	void iemMemStackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5632	void iemMemStackPopGRegU32SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5633	void iemMemStackPopGRegU64SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5634
5635	void iemMemFlat32StackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5636	void iemMemFlat32StackPushU32SafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5637	void iemMemFlat32StackPushU32SRegSafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5638	void iemMemFlat32StackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5639	void iemMemFlat32StackPopGRegU32SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5640
5641	void iemMemFlat64StackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5642	void iemMemFlat64StackPushU64SafeJmp(PVMCPUCC pVCpu, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5643	void iemMemFlat64StackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5644	void iemMemFlat64StackPopGRegU64SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5645
5646	void iemMemStoreStackU16SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5647	void iemMemStoreStackU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5648	void iemMemStoreStackU32SRegSafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5649	void iemMemStoreStackU64SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5650
5651	uint16_t iemMemFetchStackU16SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5652	uint32_t iemMemFetchStackU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5653	uint64_t iemMemFetchStackU64SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5654
5655	#endif
5656
5657	/** @} */
5658
5659	/** @name IEMAllCImpl.cpp
5660	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/'
5661	* @{ */
5662	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem16, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5663	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem32, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5664	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem64, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5665	IEM_CIMPL_PROTO_0(iemCImpl_popa_16);
5666	IEM_CIMPL_PROTO_0(iemCImpl_popa_32);
5667	IEM_CIMPL_PROTO_0(iemCImpl_pusha_16);
5668	IEM_CIMPL_PROTO_0(iemCImpl_pusha_32);
5669	IEM_CIMPL_PROTO_1(iemCImpl_pushf, IEMMODE, enmEffOpSize);
5670	IEM_CIMPL_PROTO_1(iemCImpl_popf, IEMMODE, enmEffOpSize);
5671	IEM_CIMPL_PROTO_1(iemCImpl_call_16, uint16_t, uNewPC);
5672	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_16, int16_t, offDisp);
5673	IEM_CIMPL_PROTO_1(iemCImpl_call_32, uint32_t, uNewPC);
5674	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_32, int32_t, offDisp);
5675	IEM_CIMPL_PROTO_1(iemCImpl_call_64, uint64_t, uNewPC);
5676	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_64, int64_t, offDisp);
5677	IEM_CIMPL_PROTO_3(iemCImpl_FarJmp, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
5678	IEM_CIMPL_PROTO_3(iemCImpl_callf, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
5679	typedef IEM_CIMPL_DECL_TYPE_3(FNIEMCIMPLFARBRANCH, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
5680	typedef FNIEMCIMPLFARBRANCH *PFNIEMCIMPLFARBRANCH;
5681	IEM_CIMPL_PROTO_2(iemCImpl_retf, IEMMODE, enmEffOpSize, uint16_t, cbPop);
5682	IEM_CIMPL_PROTO_0(iemCImpl_retn_16);
5683	IEM_CIMPL_PROTO_0(iemCImpl_retn_32);
5684	IEM_CIMPL_PROTO_0(iemCImpl_retn_64);
5685	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_16, uint16_t, cbPop);
5686	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_32, uint16_t, cbPop);
5687	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_64, uint16_t, cbPop);
5688	IEM_CIMPL_PROTO_3(iemCImpl_enter, IEMMODE, enmEffOpSize, uint16_t, cbFrame, uint8_t, cParameters);
5689	IEM_CIMPL_PROTO_1(iemCImpl_leave, IEMMODE, enmEffOpSize);
5690	IEM_CIMPL_PROTO_2(iemCImpl_int, uint8_t, u8Int, IEMINT, enmInt);
5691	IEM_CIMPL_PROTO_1(iemCImpl_iret_real_v8086, IEMMODE, enmEffOpSize);
5692	IEM_CIMPL_PROTO_4(iemCImpl_iret_prot_v8086, uint32_t, uNewEip, uint16_t, uNewCs, uint32_t, uNewFlags, uint64_t, uNewRsp);
5693	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot_NestedTask, IEMMODE, enmEffOpSize);
5694	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot, IEMMODE, enmEffOpSize);
5695	IEM_CIMPL_PROTO_1(iemCImpl_iret_64bit, IEMMODE, enmEffOpSize);
5696	IEM_CIMPL_PROTO_1(iemCImpl_iret, IEMMODE, enmEffOpSize);
5697	IEM_CIMPL_PROTO_0(iemCImpl_loadall286);
5698	IEM_CIMPL_PROTO_0(iemCImpl_syscall);
5699	IEM_CIMPL_PROTO_1(iemCImpl_sysret, IEMMODE, enmEffOpSize);
5700	IEM_CIMPL_PROTO_0(iemCImpl_sysenter);
5701	IEM_CIMPL_PROTO_1(iemCImpl_sysexit, IEMMODE, enmEffOpSize);
5702	IEM_CIMPL_PROTO_2(iemCImpl_LoadSReg, uint8_t, iSegReg, uint16_t, uSel);
5703	IEM_CIMPL_PROTO_2(iemCImpl_load_SReg, uint8_t, iSegReg, uint16_t, uSel);
5704	IEM_CIMPL_PROTO_2(iemCImpl_pop_Sreg, uint8_t, iSegReg, IEMMODE, enmEffOpSize);
5705	IEM_CIMPL_PROTO_5(iemCImpl_load_SReg_Greg, uint16_t, uSel, uint64_t, offSeg, uint8_t, iSegReg, uint8_t, iGReg, IEMMODE, enmEffOpSize);
5706	IEM_CIMPL_PROTO_2(iemCImpl_VerX, uint16_t, uSel, bool, fWrite);
5707	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u64, uint64_t *, pu64Dst, uint16_t, uSel, bool, fIsLar);
5708	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u16, uint16_t *, pu16Dst, uint16_t, uSel, bool, fIsLar);
5709	IEM_CIMPL_PROTO_3(iemCImpl_lgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
5710	IEM_CIMPL_PROTO_2(iemCImpl_sgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5711	IEM_CIMPL_PROTO_3(iemCImpl_lidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
5712	IEM_CIMPL_PROTO_2(iemCImpl_sidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5713	IEM_CIMPL_PROTO_1(iemCImpl_lldt, uint16_t, uNewLdt);
5714	IEM_CIMPL_PROTO_2(iemCImpl_sldt_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
5715	IEM_CIMPL_PROTO_2(iemCImpl_sldt_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5716	IEM_CIMPL_PROTO_1(iemCImpl_ltr, uint16_t, uNewTr);
5717	IEM_CIMPL_PROTO_2(iemCImpl_str_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
5718	IEM_CIMPL_PROTO_2(iemCImpl_str_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5719	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Cd, uint8_t, iGReg, uint8_t, iCrReg);
5720	IEM_CIMPL_PROTO_2(iemCImpl_smsw_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
5721	IEM_CIMPL_PROTO_2(iemCImpl_smsw_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5722	IEM_CIMPL_PROTO_4(iemCImpl_load_CrX, uint8_t, iCrReg, uint64_t, uNewCrX, IEMACCESSCRX, enmAccessCrX, uint8_t, iGReg);
5723	IEM_CIMPL_PROTO_2(iemCImpl_mov_Cd_Rd, uint8_t, iCrReg, uint8_t, iGReg);
5724	IEM_CIMPL_PROTO_2(iemCImpl_lmsw, uint16_t, u16NewMsw, RTGCPTR, GCPtrEffDst);
5725	IEM_CIMPL_PROTO_0(iemCImpl_clts);
5726	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Dd, uint8_t, iGReg, uint8_t, iDrReg);
5727	IEM_CIMPL_PROTO_2(iemCImpl_mov_Dd_Rd, uint8_t, iDrReg, uint8_t, iGReg);
5728	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Td, uint8_t, iGReg, uint8_t, iTrReg);
5729	IEM_CIMPL_PROTO_2(iemCImpl_mov_Td_Rd, uint8_t, iTrReg, uint8_t, iGReg);
5730	IEM_CIMPL_PROTO_1(iemCImpl_invlpg, RTGCPTR, GCPtrPage);
5731	IEM_CIMPL_PROTO_3(iemCImpl_invpcid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvpcidDesc, uint64_t, uInvpcidType);
5732	IEM_CIMPL_PROTO_0(iemCImpl_invd);
5733	IEM_CIMPL_PROTO_0(iemCImpl_wbinvd);
5734	IEM_CIMPL_PROTO_0(iemCImpl_rsm);
5735	IEM_CIMPL_PROTO_0(iemCImpl_rdtsc);
5736	IEM_CIMPL_PROTO_0(iemCImpl_rdtscp);
5737	IEM_CIMPL_PROTO_0(iemCImpl_rdpmc);
5738	IEM_CIMPL_PROTO_0(iemCImpl_rdmsr);
5739	IEM_CIMPL_PROTO_0(iemCImpl_wrmsr);
5740	IEM_CIMPL_PROTO_3(iemCImpl_in, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
5741	IEM_CIMPL_PROTO_2(iemCImpl_in_eAX_DX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
5742	IEM_CIMPL_PROTO_3(iemCImpl_out, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
5743	IEM_CIMPL_PROTO_2(iemCImpl_out_DX_eAX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
5744	IEM_CIMPL_PROTO_0(iemCImpl_cli);
5745	IEM_CIMPL_PROTO_0(iemCImpl_sti);
5746	IEM_CIMPL_PROTO_0(iemCImpl_hlt);
5747	IEM_CIMPL_PROTO_1(iemCImpl_monitor, uint8_t, iEffSeg);
5748	IEM_CIMPL_PROTO_0(iemCImpl_mwait);
5749	IEM_CIMPL_PROTO_0(iemCImpl_swapgs);
5750	IEM_CIMPL_PROTO_0(iemCImpl_cpuid);
5751	IEM_CIMPL_PROTO_1(iemCImpl_aad, uint8_t, bImm);
5752	IEM_CIMPL_PROTO_1(iemCImpl_aam, uint8_t, bImm);
5753	IEM_CIMPL_PROTO_0(iemCImpl_daa);
5754	IEM_CIMPL_PROTO_0(iemCImpl_das);
5755	IEM_CIMPL_PROTO_0(iemCImpl_aaa);
5756	IEM_CIMPL_PROTO_0(iemCImpl_aas);
5757	IEM_CIMPL_PROTO_3(iemCImpl_bound_16, int16_t, idxArray, int16_t, idxLowerBound, int16_t, idxUpperBound);
5758	IEM_CIMPL_PROTO_3(iemCImpl_bound_32, int32_t, idxArray, int32_t, idxLowerBound, int32_t, idxUpperBound);
5759	IEM_CIMPL_PROTO_0(iemCImpl_xgetbv);
5760	IEM_CIMPL_PROTO_0(iemCImpl_xsetbv);
5761	IEM_CIMPL_PROTO_5(iemCImpl_cmpxchg16b_fallback_rendezvous, PRTUINT128U, pu128Dst, PRTUINT128U, pu128RaxRdx,
5762	PRTUINT128U, pu128RbxRcx, uint32_t *, pEFlags, uint8_t, bUnmapInfo);
5763	IEM_CIMPL_PROTO_2(iemCImpl_clflush_clflushopt, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5764	IEM_CIMPL_PROTO_1(iemCImpl_finit, bool, fCheckXcpts);
5765	IEM_CIMPL_PROTO_3(iemCImpl_fxsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5766	IEM_CIMPL_PROTO_3(iemCImpl_fxrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5767	IEM_CIMPL_PROTO_3(iemCImpl_xsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5768	IEM_CIMPL_PROTO_3(iemCImpl_xrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5769	IEM_CIMPL_PROTO_2(iemCImpl_stmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5770	IEM_CIMPL_PROTO_2(iemCImpl_vstmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5771	IEM_CIMPL_PROTO_2(iemCImpl_ldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5772	IEM_CIMPL_PROTO_3(iemCImpl_fnstenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5773	IEM_CIMPL_PROTO_3(iemCImpl_fnsave, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5774	IEM_CIMPL_PROTO_3(iemCImpl_fldenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
5775	IEM_CIMPL_PROTO_3(iemCImpl_frstor, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
5776	IEM_CIMPL_PROTO_1(iemCImpl_fldcw, uint16_t, u16Fcw);
5777	IEM_CIMPL_PROTO_2(iemCImpl_fxch_underflow, uint8_t, iStReg, uint16_t, uFpuOpcode);
5778	IEM_CIMPL_PROTO_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, bool, fUCmp, uint32_t, uPopAndFpuOpcode);
5779	IEM_CIMPL_PROTO_2(iemCImpl_rdseed, uint8_t, iReg, IEMMODE, enmEffOpSize);
5780	IEM_CIMPL_PROTO_2(iemCImpl_rdrand, uint8_t, iReg, IEMMODE, enmEffOpSize);
5781	/** @} */
5782
5783	/** @name IEMAllCImplStrInstr.cpp.h
5784	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/' -e 's/RT_CONCAT4(//' \
5785	* -e 's/,ADDR_SIZE)/64/g' -e 's/,OP_SIZE,/64/g' -e 's/,OP_rAX,/rax/g' IEMAllCImplStrInstr.cpp.h
5786	* @{ */
5787	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr16, uint8_t, iEffSeg);
5788	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr16, uint8_t, iEffSeg);
5789	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m16);
5790	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m16);
5791	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr16, uint8_t, iEffSeg);
5792	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m16);
5793	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m16, int8_t, iEffSeg);
5794	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr16, bool, fIoChecked);
5795	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr16, bool, fIoChecked);
5796	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5797	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5798
5799	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr16, uint8_t, iEffSeg);
5800	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr16, uint8_t, iEffSeg);
5801	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m16);
5802	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m16);
5803	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr16, uint8_t, iEffSeg);
5804	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m16);
5805	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m16, int8_t, iEffSeg);
5806	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr16, bool, fIoChecked);
5807	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr16, bool, fIoChecked);
5808	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5809	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5810
5811	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr16, uint8_t, iEffSeg);
5812	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr16, uint8_t, iEffSeg);
5813	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m16);
5814	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m16);
5815	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr16, uint8_t, iEffSeg);
5816	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m16);
5817	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m16, int8_t, iEffSeg);
5818	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr16, bool, fIoChecked);
5819	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr16, bool, fIoChecked);
5820	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5821	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5822
5823
5824	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr32, uint8_t, iEffSeg);
5825	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr32, uint8_t, iEffSeg);
5826	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m32);
5827	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m32);
5828	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr32, uint8_t, iEffSeg);
5829	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m32);
5830	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m32, int8_t, iEffSeg);
5831	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr32, bool, fIoChecked);
5832	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr32, bool, fIoChecked);
5833	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5834	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5835
5836	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr32, uint8_t, iEffSeg);
5837	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr32, uint8_t, iEffSeg);
5838	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m32);
5839	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m32);
5840	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr32, uint8_t, iEffSeg);
5841	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m32);
5842	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m32, int8_t, iEffSeg);
5843	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr32, bool, fIoChecked);
5844	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr32, bool, fIoChecked);
5845	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5846	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5847
5848	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr32, uint8_t, iEffSeg);
5849	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr32, uint8_t, iEffSeg);
5850	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m32);
5851	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m32);
5852	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr32, uint8_t, iEffSeg);
5853	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m32);
5854	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m32, int8_t, iEffSeg);
5855	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr32, bool, fIoChecked);
5856	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr32, bool, fIoChecked);
5857	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5858	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5859
5860	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr32, uint8_t, iEffSeg);
5861	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr32, uint8_t, iEffSeg);
5862	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m32);
5863	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m32);
5864	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr32, uint8_t, iEffSeg);
5865	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m32);
5866	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m32, int8_t, iEffSeg);
5867	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr32, bool, fIoChecked);
5868	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr32, bool, fIoChecked);
5869	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5870	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5871
5872
5873	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr64, uint8_t, iEffSeg);
5874	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr64, uint8_t, iEffSeg);
5875	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m64);
5876	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m64);
5877	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr64, uint8_t, iEffSeg);
5878	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m64);
5879	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m64, int8_t, iEffSeg);
5880	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr64, bool, fIoChecked);
5881	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr64, bool, fIoChecked);
5882	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5883	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5884
5885	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr64, uint8_t, iEffSeg);
5886	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr64, uint8_t, iEffSeg);
5887	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m64);
5888	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m64);
5889	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr64, uint8_t, iEffSeg);
5890	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m64);
5891	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m64, int8_t, iEffSeg);
5892	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr64, bool, fIoChecked);
5893	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr64, bool, fIoChecked);
5894	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5895	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5896
5897	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr64, uint8_t, iEffSeg);
5898	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr64, uint8_t, iEffSeg);
5899	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m64);
5900	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m64);
5901	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr64, uint8_t, iEffSeg);
5902	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m64);
5903	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m64, int8_t, iEffSeg);
5904	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr64, bool, fIoChecked);
5905	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr64, bool, fIoChecked);
5906	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5907	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5908
5909	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr64, uint8_t, iEffSeg);
5910	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr64, uint8_t, iEffSeg);
5911	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m64);
5912	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m64);
5913	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr64, uint8_t, iEffSeg);
5914	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m64);
5915	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m64, int8_t, iEffSeg);
5916	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr64, bool, fIoChecked);
5917	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr64, bool, fIoChecked);
5918	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5919	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5920	/** @} */
5921
5922	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5923	VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT;
5924	VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT;
5925	VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT;
5926	VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT;
5927	VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT;
5928	VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
5929	VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALK pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT;
5930	VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT;
5931	VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT;
5932	VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
5933	bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT;
5934	VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
5935	bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT;
5936	VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5937	VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5938	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5939	VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5940	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5941	VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5942	VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT;
5943	VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
5944	RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT;
5945	VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT;
5946	VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT;
5947	VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT;
5948	uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT;
5949	void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT;
5950	VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
5951	uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT;
5952	bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT;
5953	IEM_CIMPL_PROTO_0(iemCImpl_vmxoff);
5954	IEM_CIMPL_PROTO_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon);
5955	IEM_CIMPL_PROTO_0(iemCImpl_vmlaunch);
5956	IEM_CIMPL_PROTO_0(iemCImpl_vmresume);
5957	IEM_CIMPL_PROTO_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
5958	IEM_CIMPL_PROTO_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
5959	IEM_CIMPL_PROTO_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
5960	IEM_CIMPL_PROTO_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField);
5961	IEM_CIMPL_PROTO_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField);
5962	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField);
5963	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg32, uint64_t *, pu32Dst, uint32_t, u32VmcsField);
5964	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField);
5965	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField);
5966	IEM_CIMPL_PROTO_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType);
5967	IEM_CIMPL_PROTO_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType);
5968	IEM_CIMPL_PROTO_0(iemCImpl_vmx_pause);
5969	#endif
5970
5971	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5972	VBOXSTRICTRC iemSvmVmexit(PVMCPUCC pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2) RT_NOEXCEPT;
5973	VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr, uint64_t uCr2) RT_NOEXCEPT;
5974	VBOXSTRICTRC iemSvmHandleIOIntercept(PVMCPUCC pVCpu, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
5975	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, uint8_t cbInstr) RT_NOEXCEPT;
5976	VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPUCC pVCpu, uint32_t idMsr, bool fWrite, uint8_t cbInstr) RT_NOEXCEPT;
5977	IEM_CIMPL_PROTO_0(iemCImpl_vmrun);
5978	IEM_CIMPL_PROTO_0(iemCImpl_vmload);
5979	IEM_CIMPL_PROTO_0(iemCImpl_vmsave);
5980	IEM_CIMPL_PROTO_0(iemCImpl_clgi);
5981	IEM_CIMPL_PROTO_0(iemCImpl_stgi);
5982	IEM_CIMPL_PROTO_0(iemCImpl_invlpga);
5983	IEM_CIMPL_PROTO_0(iemCImpl_skinit);
5984	IEM_CIMPL_PROTO_0(iemCImpl_svm_pause);
5985	#endif
5986
5987	IEM_CIMPL_PROTO_0(iemCImpl_vmcall); /* vmx */
5988	IEM_CIMPL_PROTO_0(iemCImpl_vmmcall); /* svm */
5989	IEM_CIMPL_PROTO_1(iemCImpl_Hypercall, uint16_t, uDisOpcode); /* both */
5990
5991	extern const PFNIEMOP g_apfnIemInterpretOnlyOneByteMap[256];
5992	extern const PFNIEMOP g_apfnIemInterpretOnlyTwoByteMap[1024];
5993	extern const PFNIEMOP g_apfnIemInterpretOnlyThreeByte0f3a[1024];
5994	extern const PFNIEMOP g_apfnIemInterpretOnlyThreeByte0f38[1024];
5995	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap1[1024];
5996	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap2[1024];
5997	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap3[1024];
5998
5999	/*
6000	* Recompiler related stuff.
6001	*/
6002	extern const PFNIEMOP g_apfnIemThreadedRecompilerOneByteMap[256];
6003	extern const PFNIEMOP g_apfnIemThreadedRecompilerTwoByteMap[1024];
6004	extern const PFNIEMOP g_apfnIemThreadedRecompilerThreeByte0f3a[1024];
6005	extern const PFNIEMOP g_apfnIemThreadedRecompilerThreeByte0f38[1024];
6006	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap1[1024];
6007	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap2[1024];
6008	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap3[1024];
6009
6010	DECLCALLBACK(int) iemTbInit(PVMCC pVM, uint32_t cInitialTbs, uint32_t cMaxTbs,
6011	uint64_t cbInitialExec, uint64_t cbMaxExec, uint32_t cbChunkExec);
6012	void iemThreadedTbObsolete(PVMCPUCC pVCpu, PIEMTB pTb, bool fSafeToFree);
6013	void iemTbAllocatorProcessDelayedFrees(PVMCPUCC pVCpu, PIEMTBALLOCATOR pTbAllocator);
6014	void iemTbAllocatorFreeupNativeSpace(PVMCPUCC pVCpu, uint32_t cNeededInstrs);
6015	DECLHIDDEN(const char ) iemTbFlagsToString(uint32_t fFlags, char pszBuf, size_t cbBuf) RT_NOEXCEPT;
6016	DECLHIDDEN(void) iemThreadedDisassembleTb(PCIEMTB pTb, PCDBGFINFOHLP pHlp) RT_NOEXCEPT;
6017
6018
6019	/** @todo FNIEMTHREADEDFUNC and friends may need more work... */
6020	#if defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
6021	typedef VBOXSTRICTRC /__attribute__((__nothrow__))/ FNIEMTHREADEDFUNC(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
6022	typedef FNIEMTHREADEDFUNC *PFNIEMTHREADEDFUNC;
6023	# define IEM_DECL_IEMTHREADEDFUNC_DEF(a_Name) \
6024	VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2)
6025	# define IEM_DECL_IEMTHREADEDFUNC_PROTO(a_Name) \
6026	VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2)
6027
6028	#else
6029	typedef VBOXSTRICTRC (FNIEMTHREADEDFUNC)(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
6030	typedef FNIEMTHREADEDFUNC *PFNIEMTHREADEDFUNC;
6031	# define IEM_DECL_IEMTHREADEDFUNC_DEF(a_Name) \
6032	VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2) IEM_NOEXCEPT_MAY_LONGJMP
6033	# define IEM_DECL_IEMTHREADEDFUNC_PROTO(a_Name) \
6034	VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2) IEM_NOEXCEPT_MAY_LONGJMP
6035	#endif
6036
6037
6038	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_Nop);
6039	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_LogCpuState);
6040
6041	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_DeferToCImpl0);
6042
6043	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckIrq);
6044	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckMode);
6045	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckHwInstrBps);
6046	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLim);
6047
6048	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodes);
6049	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodes);
6050	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesConsiderCsLim);
6051
6052	/* Branching: */
6053	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndPcAndOpcodes);
6054	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckPcAndOpcodes);
6055	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckPcAndOpcodesConsiderCsLim);
6056
6057	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesLoadingTlb);
6058	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesLoadingTlb);
6059	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesLoadingTlbConsiderCsLim);
6060
6061	/* Natural page crossing: */
6062	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesAcrossPageLoadingTlb);
6063	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesAcrossPageLoadingTlb);
6064	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesAcrossPageLoadingTlbConsiderCsLim);
6065
6066	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesOnNextPageLoadingTlb);
6067	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNextPageLoadingTlb);
6068	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNextPageLoadingTlbConsiderCsLim);
6069
6070	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesOnNewPageLoadingTlb);
6071	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNewPageLoadingTlb);
6072	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNewPageLoadingTlbConsiderCsLim);
6073
6074	bool iemThreadedCompileEmitIrqCheckBefore(PVMCPUCC pVCpu, PIEMTB pTb);
6075	bool iemThreadedCompileBeginEmitCallsComplications(PVMCPUCC pVCpu, PIEMTB pTb);
6076
6077	/* Native recompiler public bits: */
6078	DECLHIDDEN(PIEMTB) iemNativeRecompile(PVMCPUCC pVCpu, PIEMTB pTb) RT_NOEXCEPT;
6079	DECLHIDDEN(void) iemNativeDisassembleTb(PCIEMTB pTb, PCDBGFINFOHLP pHlp) RT_NOEXCEPT;
6080	int iemExecMemAllocatorInit(PVMCPU pVCpu, uint64_t cbMax, uint64_t cbInitial, uint32_t cbChunk);
6081	void iemExecMemAllocatorFree(PVMCPU pVCpu, void *pv, size_t cb);
6082	DECLASM(DECL_NO_RETURN(void)) iemNativeTbLongJmp(void *pvFramePointer, int rc) RT_NOEXCEPT;
6083
6084
6085	/** @} */
6086
6087	RT_C_DECLS_END
6088
6089	#endif /* !VMM_INCLUDED_SRC_include_IEMInternal_h */
6090

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source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h@ 103956

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