IEMInternal.h@ 108178

Last change on this file since 108178 was 108178, checked in by vboxsync, 3 months ago
VMM/IEM: Eliminated unused enmHostCpuVendor IEMCPU member. jiraref:VBP-1531
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 357.1 KB

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1	/* $Id: IEMInternal.h 108178 2025-02-12 13:28:13Z vboxsync $ */
2	/** @file
3	* IEM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2011-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_IEMInternal_h
29	#define VMM_INCLUDED_SRC_include_IEMInternal_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#ifndef RT_IN_ASSEMBLER
35	# include <VBox/vmm/cpum.h>
36	# include <VBox/vmm/iem.h>
37	# include <VBox/vmm/pgm.h>
38	# include <VBox/vmm/stam.h>
39	# include <VBox/param.h>
40
41	# include <iprt/setjmp-without-sigmask.h>
42	# include <iprt/list.h>
43	#endif /* !RT_IN_ASSEMBLER */
44
45
46	RT_C_DECLS_BEGIN
47
48
49	/** @defgroup grp_iem_int Internals
50	* @ingroup grp_iem
51	* @internal
52	* @{
53	*/
54
55	/* Make doxygen happy w/o overcomplicating the #if checks. */
56	#ifdef DOXYGEN_RUNNING
57	# define IEM_WITH_THROW_CATCH
58	# define VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
59	#endif
60
61	/** For expanding symbol in slickedit and other products tagging and
62	* crossreferencing IEM symbols. */
63	#ifndef IEM_STATIC
64	# define IEM_STATIC static
65	#endif
66
67	/** @def IEM_WITH_SETJMP
68	* Enables alternative status code handling using setjmps.
69	*
70	* This adds a bit of expense via the setjmp() call since it saves all the
71	* non-volatile registers. However, it eliminates return code checks and allows
72	* for more optimal return value passing (return regs instead of stack buffer).
73	*/
74	#if defined(DOXYGEN_RUNNING) \|\| defined(RT_OS_WINDOWS) \|\| 1
75	# define IEM_WITH_SETJMP
76	#endif
77
78	/** @def IEM_WITH_THROW_CATCH
79	* Enables using C++ throw/catch as an alternative to setjmp/longjmp in user
80	* mode code when IEM_WITH_SETJMP is in effect.
81	*
82	* With GCC 11.3.1 and code TLB on linux, using throw/catch instead of
83	* setjmp/long resulted in bs2-test-1 running 3.00% faster and all but on test
84	* result value improving by more than 1%. (Best out of three.)
85	*
86	* With Visual C++ 2019 and code TLB on windows, using throw/catch instead of
87	* setjmp/long resulted in bs2-test-1 running 3.68% faster and all but some of
88	* the MMIO and CPUID tests ran noticeably faster. Variation is greater than on
89	* Linux, but it should be quite a bit faster for normal code.
90	*/
91	#if defined(__cplusplus) && defined(IEM_WITH_SETJMP) && defined(IN_RING3) && (defined(__GNUC__) \|\| defined(_MSC_VER)) /* ASM-NOINC-START */
92	# define IEM_WITH_THROW_CATCH
93	#endif /ASM-NOINC-END/
94
95	/** @def IEM_WITH_ADAPTIVE_TIMER_POLLING
96	* Enables the adaptive timer polling code.
97	*/
98	#if defined(DOXYGEN_RUNNING) \|\| 1
99	# define IEM_WITH_ADAPTIVE_TIMER_POLLING
100	#endif
101
102	/** @def IEM_WITH_INTRA_TB_JUMPS
103	* Enables loop-jumps within a TB (currently only to the first call).
104	*/
105	#if defined(DOXYGEN_RUNNING) \|\| 1
106	# define IEM_WITH_INTRA_TB_JUMPS
107	#endif
108
109	/** @def IEMNATIVE_WITH_DELAYED_PC_UPDATING
110	* Enables the delayed PC updating optimization (see @bugref{10373}).
111	*/
112	#if defined(DOXYGEN_RUNNING) \|\| 1
113	# define IEMNATIVE_WITH_DELAYED_PC_UPDATING
114	#endif
115	/** @def IEMNATIVE_WITH_DELAYED_PC_UPDATING_DEBUG
116	* Enabled delayed PC updating debugging code.
117	* This is an alternative to the ARM64-only IEMNATIVE_REG_FIXED_PC_DBG. */
118	#if defined(DOXYGEN_RUNNING) \|\| 0
119	# define IEMNATIVE_WITH_DELAYED_PC_UPDATING_DEBUG
120	#endif
121
122	/** Enables access to even callee saved registers. */
123	/# define IEMNATIVE_WITH_SIMD_REG_ACCESS_ALL_REGISTERS/
124
125	#if defined(DOXYGEN_RUNNING) \|\| 1
126	/** @def IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
127	* Delay the writeback or dirty registers as long as possible. */
128	# define IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
129	#endif
130
131	/** @def IEM_WITH_TLB_STATISTICS
132	* Enables all TLB statistics. */
133	#if defined(VBOX_WITH_STATISTICS) \|\| defined(DOXYGEN_RUNNING)
134	# define IEM_WITH_TLB_STATISTICS
135	#endif
136
137	/** @def IEMNATIVE_WITH_SIMD_FP_NATIVE_EMITTERS
138	* Enable this to use native emitters for certain SIMD FP operations. */
139	#if 1 \|\| defined(DOXYGEN_RUNNING)
140	# define IEMNATIVE_WITH_SIMD_FP_NATIVE_EMITTERS
141	#endif
142
143	/** @def VBOX_WITH_SAVE_THREADED_TBS_FOR_PROFILING
144	* Enable this to create a saved state file with the threaded translation
145	* blocks fed to the native recompiler on VCPU \#0. The resulting file can
146	* then be fed into the native recompiler for code profiling purposes.
147	* This is not a feature that should be normally be enabled! */
148	#if 0 \|\| defined(DOXYGEN_RUNNING)
149	# define VBOX_WITH_SAVE_THREADED_TBS_FOR_PROFILING
150	#endif
151
152	/** @def VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
153	* Enables a quicker alternative to throw/longjmp for IEM_DO_LONGJMP when
154	* executing native translation blocks.
155	*
156	* This exploits the fact that we save all non-volatile registers in the TB
157	* prologue and thus just need to do the same as the TB epilogue to get the
158	* effect of a longjmp/throw. Since MSC marks XMM6 thru XMM15 as
159	* non-volatile (and does something even more crazy for ARM), this probably
160	* won't work reliably on Windows. */
161	#ifdef RT_ARCH_ARM64
162	# ifndef RT_OS_WINDOWS
163	# define VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
164	# endif
165	#endif
166	/* ASM-NOINC-START */
167	#ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
168	# if !defined(IN_RING3) \
169	\|\| !defined(VBOX_WITH_IEM_RECOMPILER) \
170	\|\| !defined(VBOX_WITH_IEM_NATIVE_RECOMPILER)
171	# undef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
172	# elif defined(RT_OS_WINDOWS)
173	# pragma message("VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP is not safe to use on windows")
174	# endif
175	#endif
176
177
178	/** @def IEM_DO_LONGJMP
179	*
180	* Wrapper around longjmp / throw.
181	*
182	* @param a_pVCpu The CPU handle.
183	* @param a_rc The status code jump back with / throw.
184	*/
185	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
186	# ifdef IEM_WITH_THROW_CATCH
187	# ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
188	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) do { \
189	if ((a_pVCpu)->iem.s.pvTbFramePointerR3) \
190	iemNativeTbLongJmp((a_pVCpu)->iem.s.pvTbFramePointerR3, (a_rc)); \
191	throw int(a_rc); \
192	} while (0)
193	# else
194	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) throw int(a_rc)
195	# endif
196	# else
197	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) longjmp(*(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf), (a_rc))
198	# endif
199	#endif
200
201	/** For use with IEM function that may do a longjmp (when enabled).
202	*
203	* Visual C++ has trouble longjmp'ing from/over functions with the noexcept
204	* attribute. So, we indicate that function that may be part of a longjmp may
205	* throw "exceptions" and that the compiler should definitely not generate and
206	* std::terminate calling unwind code.
207	*
208	* Here is one example of this ending in std::terminate:
209	* @code{.txt}
210	00 00000041`cadfda10 00007ffc`5d5a1f9f ucrtbase!abort+0x4e
211	01 00000041`cadfda40 00007ffc`57af229a ucrtbase!terminate+0x1f
212	02 00000041`cadfda70 00007ffb`eec91030 VCRUNTIME140!__std_terminate+0xa [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\ehhelpers.cpp @ 192]
213	03 00000041`cadfdaa0 00007ffb`eec92c6d VCRUNTIME140_1!_CallSettingFrame+0x20 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\handlers.asm @ 50]
214	04 00000041`cadfdad0 00007ffb`eec93ae5 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToState+0x241 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 1085]
215	05 00000041`cadfdc00 00007ffb`eec92258 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToEmptyState+0x2d [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 218]
216	06 00000041`cadfdc30 00007ffb`eec940e9 VCRUNTIME140_1!__InternalCxxFrameHandler<__FrameHandler4>+0x194 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 304]
217	07 00000041`cadfdcd0 00007ffc`5f9f249f VCRUNTIME140_1!__CxxFrameHandler4+0xa9 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 290]
218	08 00000041`cadfdd40 00007ffc`5f980939 ntdll!RtlpExecuteHandlerForUnwind+0xf
219	09 00000041`cadfdd70 00007ffc`5f9a0edd ntdll!RtlUnwindEx+0x339
220	0a 00000041`cadfe490 00007ffc`57aff976 ntdll!RtlUnwind+0xcd
221	0b 00000041`cadfea00 00007ffb`e1b5de01 VCRUNTIME140!__longjmp_internal+0xe6 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\longjmp.asm @ 140]
222	0c (Inline Function) --------`-------- VBoxVMM!iemOpcodeGetNextU8SlowJmp+0x95 [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 1155]
223	0d 00000041`cadfea50 00007ffb`e1b60f6b VBoxVMM!iemOpcodeGetNextU8Jmp+0xc1 [L:\vbox-intern\src\VBox\VMM\include\IEMInline.h @ 402]
224	0e 00000041`cadfea90 00007ffb`e1cc6201 VBoxVMM!IEMExecForExits+0xdb [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 10185]
225	0f 00000041`cadfec70 00007ffb`e1d0df8d VBoxVMM!EMHistoryExec+0x4f1 [L:\vbox-intern\src\VBox\VMM\VMMAll\EMAll.cpp @ 452]
226	10 00000041`cadfed60 00007ffb`e1d0d4c0 VBoxVMM!nemR3WinHandleExitCpuId+0x79d [L:\vbox-intern\src\VBox\VMM\VMMAll\NEMAllNativeTemplate-win.cpp.h @ 1829] @encode
227	@endcode
228	*
229	* @see https://developercommunity.visualstudio.com/t/fragile-behavior-of-longjmp-called-from-noexcept-f/1532859
230	*/
231	#if defined(IEM_WITH_SETJMP) && (defined(_MSC_VER) \|\| defined(IEM_WITH_THROW_CATCH))
232	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT_EX(false)
233	#else
234	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT
235	#endif
236	/* ASM-NOINC-END */
237
238	#define IEM_IMPLEMENTS_TASKSWITCH
239
240	/** @def IEM_WITH_3DNOW
241	* Includes the 3DNow decoding. */
242	#if !defined(IEM_WITH_3DNOW) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
243	# ifndef IEM_WITHOUT_3DNOW
244	# define IEM_WITH_3DNOW
245	# endif
246	#endif
247
248	/** @def IEM_WITH_THREE_0F_38
249	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
250	#if !defined(IEM_WITH_THREE_0F_38) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
251	# ifndef IEM_WITHOUT_THREE_0F_38
252	# define IEM_WITH_THREE_0F_38
253	# endif
254	#endif
255
256	/** @def IEM_WITH_THREE_0F_3A
257	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
258	#if !defined(IEM_WITH_THREE_0F_3A) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
259	# ifndef IEM_WITHOUT_THREE_0F_3A
260	# define IEM_WITH_THREE_0F_3A
261	# endif
262	#endif
263
264	/** @def IEM_WITH_VEX
265	* Includes the VEX decoding. */
266	#if !defined(IEM_WITH_VEX) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
267	# ifndef IEM_WITHOUT_VEX
268	# define IEM_WITH_VEX
269	# endif
270	#endif
271
272	/** @def IEM_CFG_TARGET_CPU
273	* The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
274	*
275	* By default we allow this to be configured by the user via the
276	* CPUM/GuestCpuName config string, but this comes at a slight cost during
277	* decoding. So, for applications of this code where there is no need to
278	* be dynamic wrt target CPU, just modify this define.
279	*/
280	#if !defined(IEM_CFG_TARGET_CPU) \|\| defined(DOXYGEN_RUNNING)
281	# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
282	#endif
283
284	//#define IEM_WITH_CODE_TLB // - work in progress
285	//#define IEM_WITH_DATA_TLB // - work in progress
286
287
288	/** @def IEM_USE_UNALIGNED_DATA_ACCESS
289	* Use unaligned accesses instead of elaborate byte assembly. */
290	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86) \|\| defined(DOXYGEN_RUNNING) /ASM-NOINC/
291	# define IEM_USE_UNALIGNED_DATA_ACCESS
292	#endif /ASM-NOINC/
293
294	//#define IEM_LOG_MEMORY_WRITES
295
296
297
298	#ifndef RT_IN_ASSEMBLER /* ASM-NOINC-START - the rest of the file */
299
300	# if !defined(IEM_WITHOUT_INSTRUCTION_STATS) && !defined(DOXYGEN_RUNNING)
301	/** Instruction statistics. */
302	typedef struct IEMINSTRSTATS
303	{
304	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
305	# include "IEMInstructionStatisticsTmpl.h"
306	# undef IEM_DO_INSTR_STAT
307	} IEMINSTRSTATS;
308	#else
309	struct IEMINSTRSTATS;
310	typedef struct IEMINSTRSTATS IEMINSTRSTATS;
311	#endif
312	/** Pointer to IEM instruction statistics. */
313	typedef IEMINSTRSTATS *PIEMINSTRSTATS;
314
315
316	/** @name IEMTARGETCPU_EFL_BEHAVIOR_XXX - IEMCPU::aidxTargetCpuEflFlavour
317	* @{ */
318	#define IEMTARGETCPU_EFL_BEHAVIOR_NATIVE 0 /*< Native x86 EFLAGS result; Intel EFLAGS when on non-x86 hosts. /
319	#define IEMTARGETCPU_EFL_BEHAVIOR_INTEL 1 /*< Intel EFLAGS result. /
320	#define IEMTARGETCPU_EFL_BEHAVIOR_AMD 2 /*< AMD EFLAGS result /
321	#define IEMTARGETCPU_EFL_BEHAVIOR_RESERVED 3 /*< Reserved/dummy entry slot that's the same as 0. /
322	#define IEMTARGETCPU_EFL_BEHAVIOR_MASK 3 /*< For masking the index before use. /
323	/** Selects the right variant from a_aArray.
324	* pVCpu is implicit in the caller context. */
325	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT(a_aArray) \
326	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[1] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
327	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for when no native worker can
328	* be used because the host CPU does not support the operation. */
329	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_NON_NATIVE(a_aArray) \
330	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
331	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for a two dimentional
332	* array paralleling IEMCPU::aidxTargetCpuEflFlavour and a single bit index
333	* into the two.
334	* @sa IEM_SELECT_NATIVE_OR_FALLBACK */
335	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
336	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
337	(a_aaArray[a_fNative][pVCpu->iem.s.aidxTargetCpuEflFlavour[a_fNative] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
338	#else
339	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
340	(a_aaArray[0][pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
341	#endif
342	/** @} */
343
344	/**
345	* Picks @a a_pfnNative or @a a_pfnFallback according to the host CPU feature
346	* indicator given by @a a_fCpumFeatureMember (CPUMFEATURES member).
347	*
348	* On non-x86 hosts, this will shortcut to the fallback w/o checking the
349	* indicator.
350	*
351	* @sa IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX
352	*/
353	#if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
354	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) \
355	(g_CpumHostFeatures.s.a_fCpumFeatureMember ? a_pfnNative : a_pfnFallback)
356	#else
357	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) (a_pfnFallback)
358	#endif
359
360	/** @name Helpers for passing C++ template arguments to an
361	* IEM_MC_NATIVE_EMIT_3/4/5 style macro.
362	* @{
363	*/
364	#define IEM_TEMPL_ARG_1(a1) <a1>
365	#define IEM_TEMPL_ARG_2(a1, a2) <a1,a2>
366	#define IEM_TEMPL_ARG_3(a1, a2, a3) <a1,a2,a3>
367	/** @} */
368
369
370	/**
371	* Branch types.
372	*/
373	typedef enum IEMBRANCH
374	{
375	IEMBRANCH_JUMP = 1,
376	IEMBRANCH_CALL,
377	IEMBRANCH_TRAP,
378	IEMBRANCH_SOFTWARE_INT,
379	IEMBRANCH_HARDWARE_INT
380	} IEMBRANCH;
381	AssertCompileSize(IEMBRANCH, 4);
382
383
384	/**
385	* INT instruction types.
386	*/
387	typedef enum IEMINT
388	{
389	/** INT n instruction (opcode 0xcd imm). */
390	IEMINT_INTN = 0,
391	/** Single byte INT3 instruction (opcode 0xcc). */
392	IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
393	/** Single byte INTO instruction (opcode 0xce). */
394	IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
395	/** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
396	IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
397	} IEMINT;
398	AssertCompileSize(IEMINT, 4);
399
400
401	/**
402	* A FPU result.
403	*/
404	typedef struct IEMFPURESULT
405	{
406	/** The output value. */
407	RTFLOAT80U r80Result;
408	/** The output status. */
409	uint16_t FSW;
410	} IEMFPURESULT;
411	AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
412	/** Pointer to a FPU result. */
413	typedef IEMFPURESULT *PIEMFPURESULT;
414	/** Pointer to a const FPU result. */
415	typedef IEMFPURESULT const *PCIEMFPURESULT;
416
417
418	/**
419	* A FPU result consisting of two output values and FSW.
420	*/
421	typedef struct IEMFPURESULTTWO
422	{
423	/** The first output value. */
424	RTFLOAT80U r80Result1;
425	/** The output status. */
426	uint16_t FSW;
427	/** The second output value. */
428	RTFLOAT80U r80Result2;
429	} IEMFPURESULTTWO;
430	AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
431	AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
432	/** Pointer to a FPU result consisting of two output values and FSW. */
433	typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
434	/** Pointer to a const FPU result consisting of two output values and FSW. */
435	typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
436
437
438	/**
439	* IEM TLB entry.
440	*
441	* Lookup assembly:
442	* @code{.asm}
443	; Calculate tag.
444	mov rax, [VA]
445	shl rax, 16
446	shr rax, 16 + X86_PAGE_SHIFT
447	or rax, [uTlbRevision]
448
449	; Do indexing.
450	movzx ecx, al
451	lea rcx, [pTlbEntries + rcx]
452
453	; Check tag.
454	cmp [rcx + IEMTLBENTRY.uTag], rax
455	jne .TlbMiss
456
457	; Check access.
458	mov rax, ACCESS_FLAGS \| MAPPING_R3_NOT_VALID \| 0xffffff00
459	and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
460	cmp rax, [uTlbPhysRev]
461	jne .TlbMiss
462
463	; Calc address and we're done.
464	mov eax, X86_PAGE_OFFSET_MASK
465	and eax, [VA]
466	or rax, [rcx + IEMTLBENTRY.pMappingR3]
467	%ifdef VBOX_WITH_STATISTICS
468	inc qword [cTlbHits]
469	%endif
470	jmp .Done
471
472	.TlbMiss:
473	mov r8d, ACCESS_FLAGS
474	mov rdx, [VA]
475	mov rcx, [pVCpu]
476	call iemTlbTypeMiss
477	.Done:
478
479	@endcode
480	*
481	*/
482	typedef struct IEMTLBENTRY
483	{
484	/** The TLB entry tag.
485	* Bits 35 thru 0 are made up of the virtual address shifted right 12 bits, this
486	* is ASSUMING a virtual address width of 48 bits.
487	*
488	* Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
489	*
490	* The TLB lookup code uses the current TLB revision, which won't ever be zero,
491	* enabling an extremely cheap TLB invalidation most of the time. When the TLB
492	* revision wraps around though, the tags needs to be zeroed.
493	*
494	* @note Try use SHRD instruction? After seeing
495	* https://gmplib.org/~tege/x86-timing.pdf, maybe not.
496	*
497	* @todo This will need to be reorganized for 57-bit wide virtual address and
498	* PCID (currently 12 bits) and ASID (currently 6 bits) support. We'll
499	* have to move the TLB entry versioning entirely to the
500	* fFlagsAndPhysRev member then, 57 bit wide VAs means we'll only have
501	* 19 bits left (64 - 57 + 12 = 19) and they'll almost entire be
502	* consumed by PCID and ASID (12 + 6 = 18).
503	*/
504	uint64_t uTag;
505	/** Access flags and physical TLB revision.
506	*
507	* - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
508	* - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
509	* - Bit 2 - page tables - not user (complemented X86_PTE_US).
510	* - Bit 3 - pgm phys/virt - not directly writable.
511	* - Bit 4 - pgm phys page - not directly readable.
512	* - Bit 5 - page tables - not accessed (complemented X86_PTE_A).
513	* - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
514	* - Bit 7 - tlb entry - pMappingR3 member not valid.
515	* - Bits 63 thru 8 are used for the physical TLB revision number.
516	*
517	* We're using complemented bit meanings here because it makes it easy to check
518	* whether special action is required. For instance a user mode write access
519	* would do a "TEST fFlags, (X86_PTE_RW \| X86_PTE_US \| X86_PTE_D)" and a
520	* non-zero result would mean special handling needed because either it wasn't
521	* writable, or it wasn't user, or the page wasn't dirty. A user mode read
522	* access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
523	* need to check any PTE flag.
524	*/
525	uint64_t fFlagsAndPhysRev;
526	/** The guest physical page address. */
527	uint64_t GCPhys;
528	/** Pointer to the ring-3 mapping. */
529	R3PTRTYPE(uint8_t *) pbMappingR3;
530	#if HC_ARCH_BITS == 32
531	uint32_t u32Padding1;
532	#endif
533	} IEMTLBENTRY;
534	AssertCompileSize(IEMTLBENTRY, 32);
535	/** Pointer to an IEM TLB entry. */
536	typedef IEMTLBENTRY *PIEMTLBENTRY;
537	/** Pointer to a const IEM TLB entry. */
538	typedef IEMTLBENTRY const *PCIEMTLBENTRY;
539
540	/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
541	* @{ */
542	#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /*< Page tables: Not executable. /
543	#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /*< Page tables: Not writable. /
544	#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /*< Page tables: Not user accessible (supervisor only). /
545	#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /*< Phys page: Not writable (access handler, ROM, whatever). /
546	#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /*< Phys page: Not readable (MMIO / access handler, ROM) /
547	#define IEMTLBE_F_PT_NO_ACCESSED RT_BIT_64(5) /*< Phys tables: Not accessed (need to be marked accessed). /
548	#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /*< Page tables: Not dirty (needs to be made dirty on write). /
549	#define IEMTLBE_F_PT_LARGE_PAGE RT_BIT_64(7) /*< Page tables: Large 2 or 4 MiB page (for flushing). /
550	#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(8) /*< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. /
551	#define IEMTLBE_F_PG_UNASSIGNED RT_BIT_64(9) /*< Phys page: Unassigned memory (not RAM, ROM, MMIO2 or MMIO). /
552	#define IEMTLBE_F_PG_CODE_PAGE RT_BIT_64(10) /*< Phys page: Code page. /
553	#define IEMTLBE_F_PHYS_REV UINT64_C(0xfffffffffffff800) /*< Physical revision mask. @sa IEMTLB_PHYS_REV_INCR /
554	/** @} */
555	AssertCompile(PGMIEMGCPHYS2PTR_F_NO_WRITE == IEMTLBE_F_PG_NO_WRITE);
556	AssertCompile(PGMIEMGCPHYS2PTR_F_NO_READ == IEMTLBE_F_PG_NO_READ);
557	AssertCompile(PGMIEMGCPHYS2PTR_F_NO_MAPPINGR3 == IEMTLBE_F_NO_MAPPINGR3);
558	AssertCompile(PGMIEMGCPHYS2PTR_F_UNASSIGNED == IEMTLBE_F_PG_UNASSIGNED);
559	AssertCompile(PGMIEMGCPHYS2PTR_F_CODE_PAGE == IEMTLBE_F_PG_CODE_PAGE);
560	AssertCompile(PGM_WALKINFO_BIG_PAGE == IEMTLBE_F_PT_LARGE_PAGE);
561	/** The bits set by PGMPhysIemGCPhys2PtrNoLock. */
562	#define IEMTLBE_GCPHYS2PTR_MASK ( PGMIEMGCPHYS2PTR_F_NO_WRITE \
563	\| PGMIEMGCPHYS2PTR_F_NO_READ \
564	\| PGMIEMGCPHYS2PTR_F_NO_MAPPINGR3 \
565	\| PGMIEMGCPHYS2PTR_F_UNASSIGNED \
566	\| PGMIEMGCPHYS2PTR_F_CODE_PAGE \
567	\| IEMTLBE_F_PHYS_REV )
568
569
570	/** The TLB size (power of two).
571	* We initially chose 256 because that way we can obtain the result directly
572	* from a 8-bit register without an additional AND instruction.
573	* See also @bugref{10687}. */
574	#if defined(RT_ARCH_AMD64)
575	# define IEMTLB_ENTRY_COUNT 256
576	# define IEMTLB_ENTRY_COUNT_AS_POWER_OF_TWO 8
577	#else
578	# define IEMTLB_ENTRY_COUNT 8192
579	# define IEMTLB_ENTRY_COUNT_AS_POWER_OF_TWO 13
580	#endif
581	AssertCompile(RT_BIT_32(IEMTLB_ENTRY_COUNT_AS_POWER_OF_TWO) == IEMTLB_ENTRY_COUNT);
582
583	/** TLB slot format spec (assumes uint32_t or unsigned value). */
584	#if IEMTLB_ENTRY_COUNT <= 0x100 / 2
585	# define IEMTLB_SLOT_FMT "%02x"
586	#elif IEMTLB_ENTRY_COUNT <= 0x1000 / 2
587	# define IEMTLB_SLOT_FMT "%03x"
588	#elif IEMTLB_ENTRY_COUNT <= 0x10000 / 2
589	# define IEMTLB_SLOT_FMT "%04x"
590	#else
591	# define IEMTLB_SLOT_FMT "%05x"
592	#endif
593
594	/** Enable the large page bitmap TLB optimization.
595	*
596	* The idea here is to avoid scanning the full 32 KB (2MB pages, 2*512 TLB
597	* entries) or 64 KB (4MB pages, 2*1024 TLB entries) worth of TLB entries during
598	* invlpg when large pages are used, and instead just scan 128 or 256 bytes of
599	* the bmLargePage bitmap to determin which TLB entires that might be containing
600	* large pages and actually require checking.
601	*
602	* There is a good posibility of false positives since we currently don't clear
603	* the bitmap when flushing the TLB, but it should help reduce the workload when
604	* the large pages aren't fully loaded into the TLB in their entirity...
605	*/
606	#define IEMTLB_WITH_LARGE_PAGE_BITMAP
607
608	/**
609	* An IEM TLB.
610	*
611	* We've got two of these, one for data and one for instructions.
612	*/
613	typedef struct IEMTLB
614	{
615	/** The non-global TLB revision.
616	* This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
617	* by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
618	* the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
619	* (The revision zero indicates an invalid TLB entry.)
620	*
621	* The initial value is choosen to cause an early wraparound. */
622	uint64_t uTlbRevision;
623	/** The TLB physical address revision - shadow of PGM variable.
624	*
625	* This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
626	* incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
627	* a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
628	* as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
629	*
630	* The initial value is choosen to cause an early wraparound.
631	*
632	* @note This is placed between the two TLB revisions because we
633	* load it in pair with one or the other on arm64. */
634	uint64_t volatile uTlbPhysRev;
635	/** The global TLB revision.
636	* Same as uTlbRevision, but only increased for global flushes. */
637	uint64_t uTlbRevisionGlobal;
638
639	/** Large page tag range.
640	*
641	* This is used to avoid scanning a large page's worth of TLB entries for each
642	* INVLPG instruction, and only to do so iff we've loaded any and when the
643	* address is in this range. This is kept up to date when we loading new TLB
644	* entries.
645	*/
646	struct LARGEPAGERANGE
647	{
648	/** The lowest large page address tag, UINT64_MAX if none. */
649	uint64_t uFirstTag;
650	/** The highest large page address tag (with offset mask part set), 0 if none. */
651	uint64_t uLastTag;
652	}
653	/** Large page range for non-global pages. */
654	NonGlobalLargePageRange,
655	/** Large page range for global pages. */
656	GlobalLargePageRange;
657	/** Number of non-global entries for large pages loaded since last TLB flush. */
658	uint32_t cTlbNonGlobalLargePageCurLoads;
659	/** Number of global entries for large pages loaded since last TLB flush. */
660	uint32_t cTlbGlobalLargePageCurLoads;
661
662	/* Statistics: */
663
664	/** TLB hits in IEMAll.cpp code (IEM_WITH_TLB_STATISTICS only; both).
665	* @note For the data TLB this is only used in iemMemMap and and for direct (i.e.
666	* not via safe read/write path) calls to iemMemMapJmp. */
667	uint64_t cTlbCoreHits;
668	/** Safe read/write TLB hits in iemMemMapJmp (IEM_WITH_TLB_STATISTICS
669	* only; data tlb only). */
670	uint64_t cTlbSafeHits;
671	/** TLB hits in IEMAllMemRWTmplInline.cpp.h (data + IEM_WITH_TLB_STATISTICS only). */
672	uint64_t cTlbInlineCodeHits;
673
674	/** TLB misses in IEMAll.cpp code (both).
675	* @note For the data TLB this is only used in iemMemMap and for direct (i.e.
676	* not via safe read/write path) calls to iemMemMapJmp. So,
677	* for the data TLB this more like 'other misses', while for the code
678	* TLB is all misses. */
679	uint64_t cTlbCoreMisses;
680	/** Subset of cTlbCoreMisses that results in PTE.G=1 loads (odd entries). */
681	uint64_t cTlbCoreGlobalLoads;
682	/** Safe read/write TLB misses in iemMemMapJmp (so data only). */
683	uint64_t cTlbSafeMisses;
684	/** Subset of cTlbSafeMisses that results in PTE.G=1 loads (odd entries). */
685	uint64_t cTlbSafeGlobalLoads;
686	/** Safe read path taken (data only). */
687	uint64_t cTlbSafeReadPath;
688	/** Safe write path taken (data only). */
689	uint64_t cTlbSafeWritePath;
690
691	/** @name Details for native code TLB misses.
692	* @note These counts are included in the above counters (cTlbSafeReadPath,
693	* cTlbSafeWritePath, cTlbInlineCodeHits).
694	* @{ */
695	/** TLB misses in native code due to tag mismatch. */
696	STAMCOUNTER cTlbNativeMissTag;
697	/** TLB misses in native code due to flags or physical revision mismatch. */
698	STAMCOUNTER cTlbNativeMissFlagsAndPhysRev;
699	/** TLB misses in native code due to misaligned access. */
700	STAMCOUNTER cTlbNativeMissAlignment;
701	/** TLB misses in native code due to cross page access. */
702	uint32_t cTlbNativeMissCrossPage;
703	/** TLB misses in native code due to non-canonical address. */
704	uint32_t cTlbNativeMissNonCanonical;
705	/** @} */
706
707	/** Slow read path (code only). */
708	uint32_t cTlbSlowCodeReadPath;
709
710	/** Regular TLB flush count. */
711	uint32_t cTlsFlushes;
712	/** Global TLB flush count. */
713	uint32_t cTlsGlobalFlushes;
714	/** Revision rollovers. */
715	uint32_t cTlbRevisionRollovers;
716	/** Physical revision flushes. */
717	uint32_t cTlbPhysRevFlushes;
718	/** Physical revision rollovers. */
719	uint32_t cTlbPhysRevRollovers;
720
721	/** Number of INVLPG (and similar) operations. */
722	uint32_t cTlbInvlPg;
723	/** Subset of cTlbInvlPg that involved non-global large pages. */
724	uint32_t cTlbInvlPgLargeNonGlobal;
725	/** Subset of cTlbInvlPg that involved global large pages. */
726	uint32_t cTlbInvlPgLargeGlobal;
727
728	uint32_t au32Padding[13];
729
730	/** The TLB entries.
731	* Even entries are for PTE.G=0 and uses uTlbRevision.
732	* Odd entries are for PTE.G=1 and uses uTlbRevisionGlobal. */
733	IEMTLBENTRY aEntries[IEMTLB_ENTRY_COUNT * 2];
734	#ifdef IEMTLB_WITH_LARGE_PAGE_BITMAP
735	/** Bitmap tracking TLB entries for large pages.
736	* This duplicates IEMTLBE_F_PT_LARGE_PAGE for each TLB entry. */
737	uint64_t bmLargePage[IEMTLB_ENTRY_COUNT * 2 / 64];
738	#endif
739	} IEMTLB;
740	AssertCompileSizeAlignment(IEMTLB, 64);
741	#ifdef IEMTLB_WITH_LARGE_PAGE_BITMAP
742	AssertCompile(IEMTLB_ENTRY_COUNT >= 32 /* bmLargePage ASSUMPTION */);
743	#endif
744	/** The width (in bits) of the address portion of the TLB tag. */
745	#define IEMTLB_TAG_ADDR_WIDTH 36
746	/** IEMTLB::uTlbRevision increment. */
747	#define IEMTLB_REVISION_INCR RT_BIT_64(IEMTLB_TAG_ADDR_WIDTH)
748	/** IEMTLB::uTlbRevision mask. */
749	#define IEMTLB_REVISION_MASK (~(RT_BIT_64(IEMTLB_TAG_ADDR_WIDTH) - 1))
750
751	/** IEMTLB::uTlbPhysRev increment.
752	* @sa IEMTLBE_F_PHYS_REV */
753	#define IEMTLB_PHYS_REV_INCR RT_BIT_64(11)
754	AssertCompile(IEMTLBE_F_PHYS_REV == ~(IEMTLB_PHYS_REV_INCR - 1U));
755
756	/**
757	* Calculates the TLB tag for a virtual address but without TLB revision.
758	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
759	* @param a_GCPtr The virtual address. Must be RTGCPTR or same size or
760	* the clearing of the top 16 bits won't work (if 32-bit
761	* we'll end up with mostly zeros).
762	*/
763	#define IEMTLB_CALC_TAG_NO_REV(a_GCPtr) ( (((a_GCPtr) << 16) >> (GUEST_PAGE_SHIFT + 16)) )
764	/**
765	* Converts a TLB tag value into a even TLB index.
766	* @returns Index into IEMTLB::aEntries.
767	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
768	*/
769	#if IEMTLB_ENTRY_COUNT == 256
770	# define IEMTLB_TAG_TO_EVEN_INDEX(a_uTag) ( (uint8_t)(a_uTag) * 2U )
771	#else
772	# define IEMTLB_TAG_TO_EVEN_INDEX(a_uTag) ( ((a_uTag) & (IEMTLB_ENTRY_COUNT - 1U)) * 2U )
773	AssertCompile(RT_IS_POWER_OF_TWO(IEMTLB_ENTRY_COUNT));
774	#endif
775	/**
776	* Converts a TLB tag value into an even TLB index.
777	* @returns Pointer into IEMTLB::aEntries corresponding to .
778	* @param a_pTlb The TLB.
779	* @param a_uTag Value returned by IEMTLB_CALC_TAG or
780	* IEMTLB_CALC_TAG_NO_REV.
781	*/
782	#define IEMTLB_TAG_TO_EVEN_ENTRY(a_pTlb, a_uTag) ( &(a_pTlb)->aEntries[IEMTLB_TAG_TO_EVEN_INDEX(a_uTag)] )
783
784	/** Converts a GC address to an even TLB index. */
785	#define IEMTLB_ADDR_TO_EVEN_INDEX(a_GCPtr) IEMTLB_TAG_TO_EVEN_INDEX(IEMTLB_CALC_TAG_NO_REV(a_GCPtr))
786
787
788	/** @def IEM_WITH_TLB_TRACE
789	* Enables the TLB tracing.
790	* Adjust buffer size in IEMR3Init. */
791	#if defined(DOXYGEN_RUNNING) \|\| 0
792	# define IEM_WITH_TLB_TRACE
793	#endif
794
795	#ifdef IEM_WITH_TLB_TRACE
796
797	/** TLB trace entry types. */
798	typedef enum : uint8_t
799	{
800	kIemTlbTraceType_Invalid,
801	kIemTlbTraceType_InvlPg,
802	kIemTlbTraceType_EvictSlot,
803	kIemTlbTraceType_LargeEvictSlot,
804	kIemTlbTraceType_LargeScan,
805	kIemTlbTraceType_Flush,
806	kIemTlbTraceType_FlushGlobal,
807	kIemTlbTraceType_Load,
808	kIemTlbTraceType_LoadGlobal,
809	kIemTlbTraceType_Load_Cr0,
810	kIemTlbTraceType_Load_Cr3,
811	kIemTlbTraceType_Load_Cr4,
812	kIemTlbTraceType_Load_Efer,
813	kIemTlbTraceType_Irq,
814	kIemTlbTraceType_Xcpt,
815	kIemTlbTraceType_IRet,
816	kIemTlbTraceType_Tb_Compile,
817	kIemTlbTraceType_Tb_Exec_Threaded,
818	kIemTlbTraceType_Tb_Exec_Native,
819	kIemTlbTraceType_User0,
820	kIemTlbTraceType_User1,
821	kIemTlbTraceType_User2,
822	kIemTlbTraceType_User3,
823	} IEMTLBTRACETYPE;
824
825	/** TLB trace entry. */
826	typedef struct IEMTLBTRACEENTRY
827	{
828	/** The flattened RIP for the event. */
829	uint64_t rip;
830	/** The event type. */
831	IEMTLBTRACETYPE enmType;
832	/** Byte parameter - typically used as 'bool fDataTlb'. */
833	uint8_t bParam;
834	/** 16-bit parameter value. */
835	uint16_t u16Param;
836	/** 32-bit parameter value. */
837	uint32_t u32Param;
838	/** 64-bit parameter value. */
839	uint64_t u64Param;
840	/** 64-bit parameter value. */
841	uint64_t u64Param2;
842	} IEMTLBTRACEENTRY;
843	AssertCompileSize(IEMTLBTRACEENTRY, 32);
844	/** Pointer to a TLB trace entry. */
845	typedef IEMTLBTRACEENTRY *PIEMTLBTRACEENTRY;
846	/** Pointer to a const TLB trace entry. */
847	typedef IEMTLBTRACEENTRY const *PCIEMTLBTRACEENTRY;
848	#endif /* !IEM_WITH_TLB_TRACE */
849
850	#if defined(IEM_WITH_TLB_TRACE) && defined(IN_RING3) && 1
851	# define IEMTLBTRACE_INVLPG(a_pVCpu, a_GCPtr) \
852	iemTlbTrace(a_pVCpu, kIemTlbTraceType_InvlPg, a_GCPtr)
853	# define IEMTLBTRACE_EVICT_SLOT(a_pVCpu, a_GCPtrTag, a_GCPhys, a_idxSlot, a_fDataTlb) \
854	iemTlbTrace(a_pVCpu, kIemTlbTraceType_EvictSlot, a_GCPtrTag, a_GCPhys, a_fDataTlb, a_idxSlot)
855	# define IEMTLBTRACE_LARGE_EVICT_SLOT(a_pVCpu, a_GCPtrTag, a_GCPhys, a_idxSlot, a_fDataTlb) \
856	iemTlbTrace(a_pVCpu, kIemTlbTraceType_LargeEvictSlot, a_GCPtrTag, a_GCPhys, a_fDataTlb, a_idxSlot)
857	# define IEMTLBTRACE_LARGE_SCAN(a_pVCpu, a_fGlobal, a_fNonGlobal, a_fDataTlb) \
858	iemTlbTrace(a_pVCpu, kIemTlbTraceType_LargeScan, 0, 0, a_fDataTlb, (uint8_t)a_fGlobal \| ((uint8_t)a_fNonGlobal << 1))
859	# define IEMTLBTRACE_FLUSH(a_pVCpu, a_uRev, a_fDataTlb) \
860	iemTlbTrace(a_pVCpu, kIemTlbTraceType_Flush, a_uRev, 0, a_fDataTlb)
861	# define IEMTLBTRACE_FLUSH_GLOBAL(a_pVCpu, a_uRev, a_uGRev, a_fDataTlb) \
862	iemTlbTrace(a_pVCpu, kIemTlbTraceType_FlushGlobal, a_uRev, a_uGRev, a_fDataTlb)
863	# define IEMTLBTRACE_LOAD(a_pVCpu, a_GCPtr, a_GCPhys, a_fTlb, a_fDataTlb) \
864	iemTlbTrace(a_pVCpu, kIemTlbTraceType_Load, a_GCPtr, a_GCPhys, a_fDataTlb, a_fTlb)
865	# define IEMTLBTRACE_LOAD_GLOBAL(a_pVCpu, a_GCPtr, a_GCPhys, a_fTlb, a_fDataTlb) \
866	iemTlbTrace(a_pVCpu, kIemTlbTraceType_LoadGlobal, a_GCPtr, a_GCPhys, a_fDataTlb, a_fTlb)
867	#else
868	# define IEMTLBTRACE_INVLPG(a_pVCpu, a_GCPtr) do { } while (0)
869	# define IEMTLBTRACE_EVICT_SLOT(a_pVCpu, a_GCPtrTag, a_GCPhys, a_idxSlot, a_fDataTlb) do { } while (0)
870	# define IEMTLBTRACE_LARGE_EVICT_SLOT(a_pVCpu, a_GCPtrTag, a_GCPhys, a_idxSlot, a_fDataTlb) do { } while (0)
871	# define IEMTLBTRACE_LARGE_SCAN(a_pVCpu, a_fGlobal, a_fNonGlobal, a_fDataTlb) do { } while (0)
872	# define IEMTLBTRACE_FLUSH(a_pVCpu, a_uRev, a_fDataTlb) do { } while (0)
873	# define IEMTLBTRACE_FLUSH_GLOBAL(a_pVCpu, a_uRev, a_uGRev, a_fDataTlb) do { } while (0)
874	# define IEMTLBTRACE_LOAD(a_pVCpu, a_GCPtr, a_GCPhys, a_fTlb, a_fDataTlb) do { } while (0)
875	# define IEMTLBTRACE_LOAD_GLOBAL(a_pVCpu, a_GCPtr, a_GCPhys, a_fTlb, a_fDataTlb) do { } while (0)
876	#endif
877
878	#if defined(IEM_WITH_TLB_TRACE) && defined(IN_RING3) && 1
879	# define IEMTLBTRACE_LOAD_CR0(a_pVCpu, a_uNew, a_uOld) iemTlbTrace(a_pVCpu, kIemTlbTraceType_Load_Cr0, a_uNew, a_uOld)
880	# define IEMTLBTRACE_LOAD_CR3(a_pVCpu, a_uNew, a_uOld) iemTlbTrace(a_pVCpu, kIemTlbTraceType_Load_Cr3, a_uNew, a_uOld)
881	# define IEMTLBTRACE_LOAD_CR4(a_pVCpu, a_uNew, a_uOld) iemTlbTrace(a_pVCpu, kIemTlbTraceType_Load_Cr4, a_uNew, a_uOld)
882	# define IEMTLBTRACE_LOAD_EFER(a_pVCpu, a_uNew, a_uOld) iemTlbTrace(a_pVCpu, kIemTlbTraceType_Load_Efer, a_uNew, a_uOld)
883	#else
884	# define IEMTLBTRACE_LOAD_CR0(a_pVCpu, a_uNew, a_uOld) do { } while (0)
885	# define IEMTLBTRACE_LOAD_CR3(a_pVCpu, a_uNew, a_uOld) do { } while (0)
886	# define IEMTLBTRACE_LOAD_CR4(a_pVCpu, a_uNew, a_uOld) do { } while (0)
887	# define IEMTLBTRACE_LOAD_EFER(a_pVCpu, a_uNew, a_uOld) do { } while (0)
888	#endif
889
890	#if defined(IEM_WITH_TLB_TRACE) && defined(IN_RING3) && 1
891	# define IEMTLBTRACE_IRQ(a_pVCpu, a_uVector, a_fFlags, a_fEFlags) \
892	iemTlbTrace(a_pVCpu, kIemTlbTraceType_Irq, a_fEFlags, 0, a_uVector, a_fFlags)
893	# define IEMTLBTRACE_XCPT(a_pVCpu, a_uVector, a_uErr, a_uCr2, a_fFlags) \
894	iemTlbTrace(a_pVCpu, kIemTlbTraceType_Xcpt, a_uErr, a_uCr2, a_uVector, a_fFlags)
895	# define IEMTLBTRACE_IRET(a_pVCpu, a_uRetCs, a_uRetRip, a_fEFlags) \
896	iemTlbTrace(a_pVCpu, kIemTlbTraceType_IRet, a_uRetRip, a_fEFlags, 0, a_uRetCs)
897	#else
898	# define IEMTLBTRACE_IRQ(a_pVCpu, a_uVector, a_fFlags, a_fEFlags) do { } while (0)
899	# define IEMTLBTRACE_XCPT(a_pVCpu, a_uVector, a_uErr, a_uCr2, a_fFlags) do { } while (0)
900	# define IEMTLBTRACE_IRET(a_pVCpu, a_uRetCs, a_uRetRip, a_fEFlags) do { } while (0)
901	#endif
902
903	#if defined(IEM_WITH_TLB_TRACE) && defined(IN_RING3) && 1
904	# define IEMTLBTRACE_TB_COMPILE(a_pVCpu, a_GCPhysPc) \
905	iemTlbTrace(a_pVCpu, kIemTlbTraceType_Tb_Compile, a_GCPhysPc)
906	# define IEMTLBTRACE_TB_EXEC_THRD(a_pVCpu, a_pTb) \
907	iemTlbTrace(a_pVCpu, kIemTlbTraceType_Tb_Exec_Threaded, (a_pTb)->GCPhysPc, (uintptr_t)a_pTb, 0, (a_pTb)->cUsed)
908	# define IEMTLBTRACE_TB_EXEC_N8VE(a_pVCpu, a_pTb) \
909	iemTlbTrace(a_pVCpu, kIemTlbTraceType_Tb_Exec_Native, (a_pTb)->GCPhysPc, (uintptr_t)a_pTb, 0, (a_pTb)->cUsed)
910	#else
911	# define IEMTLBTRACE_TB_COMPILE(a_pVCpu, a_GCPhysPc) do { } while (0)
912	# define IEMTLBTRACE_TB_EXEC_THRD(a_pVCpu, a_pTb) do { } while (0)
913	# define IEMTLBTRACE_TB_EXEC_N8VE(a_pVCpu, a_pTb) do { } while (0)
914	#endif
915
916	#if defined(IEM_WITH_TLB_TRACE) && defined(IN_RING3) && 1
917	# define IEMTLBTRACE_USER0(a_pVCpu, a_u64Param1, a_u64Param2, a_u32Param, a_bParam) \
918	iemTlbTrace(a_pVCpu, kIemTlbTraceType_User0, a_u64Param1, a_u64Param2, a_bParam, a_u32Param)
919	# define IEMTLBTRACE_USER1(a_pVCpu, a_u64Param1, a_u64Param2, a_u32Param, a_bParam) \
920	iemTlbTrace(a_pVCpu, kIemTlbTraceType_User1, a_u64Param1, a_u64Param2, a_bParam, a_u32Param)
921	# define IEMTLBTRACE_USER2(a_pVCpu, a_u64Param1, a_u64Param2, a_u32Param, a_bParam) \
922	iemTlbTrace(a_pVCpu, kIemTlbTraceType_User2, a_u64Param1, a_u64Param2, a_bParam, a_u32Param)
923	# define IEMTLBTRACE_USER3(a_pVCpu, a_u64Param1, a_u64Param2, a_u32Param, a_bParam) \
924	iemTlbTrace(a_pVCpu, kIemTlbTraceType_User3, a_u64Param1, a_u64Param2, a_bParam, a_u32Param)
925	#else
926	# define IEMTLBTRACE_USER0(a_pVCpu, a_u64Param1, a_u64Param2, a_u32Param, a_bParam) do { } while (0)
927	# define IEMTLBTRACE_USER1(a_pVCpu, a_u64Param1, a_u64Param2, a_u32Param, a_bParam) do { } while (0)
928	# define IEMTLBTRACE_USER2(a_pVCpu, a_u64Param1, a_u64Param2, a_u32Param, a_bParam) do { } while (0)
929	# define IEMTLBTRACE_USER3(a_pVCpu, a_u64Param1, a_u64Param2, a_u32Param, a_bParam) do { } while (0)
930	#endif
931
932
933	/** @name IEM_MC_F_XXX - MC block flags/clues.
934	* @todo Merge with IEM_CIMPL_F_XXX
935	* @{ */
936	#define IEM_MC_F_ONLY_8086 RT_BIT_32(0)
937	#define IEM_MC_F_MIN_186 RT_BIT_32(1)
938	#define IEM_MC_F_MIN_286 RT_BIT_32(2)
939	#define IEM_MC_F_NOT_286_OR_OLDER IEM_MC_F_MIN_386
940	#define IEM_MC_F_MIN_386 RT_BIT_32(3)
941	#define IEM_MC_F_MIN_486 RT_BIT_32(4)
942	#define IEM_MC_F_MIN_PENTIUM RT_BIT_32(5)
943	#define IEM_MC_F_MIN_PENTIUM_II IEM_MC_F_MIN_PENTIUM
944	#define IEM_MC_F_MIN_CORE IEM_MC_F_MIN_PENTIUM
945	#define IEM_MC_F_64BIT RT_BIT_32(6)
946	#define IEM_MC_F_NOT_64BIT RT_BIT_32(7)
947	/** This is set by IEMAllN8vePython.py to indicate a variation with the
948	* flags-clearing-and-checking. */
949	#define IEM_MC_F_WITH_FLAGS RT_BIT_32(8)
950	/** This is set by IEMAllN8vePython.py to indicate a variation without the
951	* flags-clearing-and-checking, when there is also a variation with that.
952	* @note Do not set this manully, it's only for python and for testing in
953	* the native recompiler! */
954	#define IEM_MC_F_WITHOUT_FLAGS RT_BIT_32(9)
955	/** @} */
956
957	/** @name IEM_CIMPL_F_XXX - State change clues for CIMPL calls.
958	*
959	* These clues are mainly for the recompiler, so that it can emit correct code.
960	*
961	* They are processed by the python script and which also automatically
962	* calculates flags for MC blocks based on the statements, extending the use of
963	* these flags to describe MC block behavior to the recompiler core. The python
964	* script pass the flags to the IEM_MC2_END_EMIT_CALLS macro, but mainly for
965	* error checking purposes. The script emits the necessary fEndTb = true and
966	* similar statements as this reduces compile time a tiny bit.
967	*
968	* @{ */
969	/** Flag set if direct branch, clear if absolute or indirect. */
970	#define IEM_CIMPL_F_BRANCH_DIRECT RT_BIT_32(0)
971	/** Flag set if indirect branch, clear if direct or relative.
972	* This is also used for all system control transfers (SYSCALL, SYSRET, INT, ++)
973	* as well as for return instructions (RET, IRET, RETF). */
974	#define IEM_CIMPL_F_BRANCH_INDIRECT RT_BIT_32(1)
975	/** Flag set if relative branch, clear if absolute or indirect. */
976	#define IEM_CIMPL_F_BRANCH_RELATIVE RT_BIT_32(2)
977	/** Flag set if conditional branch, clear if unconditional. */
978	#define IEM_CIMPL_F_BRANCH_CONDITIONAL RT_BIT_32(3)
979	/** Flag set if it's a far branch (changes CS). */
980	#define IEM_CIMPL_F_BRANCH_FAR RT_BIT_32(4)
981	/** Convenience: Testing any kind of branch. */
982	#define IEM_CIMPL_F_BRANCH_ANY (IEM_CIMPL_F_BRANCH_DIRECT \| IEM_CIMPL_F_BRANCH_INDIRECT \| IEM_CIMPL_F_BRANCH_RELATIVE)
983
984	/** Execution flags may change (IEMCPU::fExec). */
985	#define IEM_CIMPL_F_MODE RT_BIT_32(5)
986	/** May change significant portions of RFLAGS. */
987	#define IEM_CIMPL_F_RFLAGS RT_BIT_32(6)
988	/** May change the status bits (X86_EFL_STATUS_BITS) in RFLAGS. */
989	#define IEM_CIMPL_F_STATUS_FLAGS RT_BIT_32(7)
990	/** May trigger interrupt shadowing. */
991	#define IEM_CIMPL_F_INHIBIT_SHADOW RT_BIT_32(8)
992	/** May enable interrupts, so recheck IRQ immediately afterwards executing
993	* the instruction. */
994	#define IEM_CIMPL_F_CHECK_IRQ_AFTER RT_BIT_32(9)
995	/** May disable interrupts, so recheck IRQ immediately before executing the
996	* instruction. */
997	#define IEM_CIMPL_F_CHECK_IRQ_BEFORE RT_BIT_32(10)
998	/** Convenience: Check for IRQ both before and after an instruction. */
999	#define IEM_CIMPL_F_CHECK_IRQ_BEFORE_AND_AFTER (IEM_CIMPL_F_CHECK_IRQ_BEFORE \| IEM_CIMPL_F_CHECK_IRQ_AFTER)
1000	/** May trigger a VM exit (treated like IEM_CIMPL_F_MODE atm). */
1001	#define IEM_CIMPL_F_VMEXIT RT_BIT_32(11)
1002	/** May modify FPU state.
1003	* @todo Not sure if this is useful yet. */
1004	#define IEM_CIMPL_F_FPU RT_BIT_32(12)
1005	/** REP prefixed instruction which may yield before updating PC.
1006	* @todo Not sure if this is useful, REP functions now return non-zero
1007	* status if they don't update the PC. */
1008	#define IEM_CIMPL_F_REP RT_BIT_32(13)
1009	/** I/O instruction.
1010	* @todo Not sure if this is useful yet. */
1011	#define IEM_CIMPL_F_IO RT_BIT_32(14)
1012	/** Force end of TB after the instruction. */
1013	#define IEM_CIMPL_F_END_TB RT_BIT_32(15)
1014	/** Flag set if a branch may also modify the stack (push/pop return address). */
1015	#define IEM_CIMPL_F_BRANCH_STACK RT_BIT_32(16)
1016	/** Flag set if a branch may also modify the stack (push/pop return address)
1017	* and switch it (load/restore SS:RSP). */
1018	#define IEM_CIMPL_F_BRANCH_STACK_FAR RT_BIT_32(17)
1019	/** Convenience: Raise exception (technically unnecessary, since it shouldn't return VINF_SUCCESS). */
1020	#define IEM_CIMPL_F_XCPT \
1021	(IEM_CIMPL_F_BRANCH_INDIRECT \| IEM_CIMPL_F_BRANCH_FAR \| IEM_CIMPL_F_BRANCH_STACK_FAR \
1022	\| IEM_CIMPL_F_MODE \| IEM_CIMPL_F_RFLAGS \| IEM_CIMPL_F_VMEXIT)
1023
1024	/** The block calls a C-implementation instruction function with two implicit arguments.
1025	* Mutually exclusive with IEM_CIMPL_F_CALLS_AIMPL and
1026	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
1027	* @note The python scripts will add this if missing. */
1028	#define IEM_CIMPL_F_CALLS_CIMPL RT_BIT_32(18)
1029	/** The block calls an ASM-implementation instruction function.
1030	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL and
1031	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
1032	* @note The python scripts will add this if missing. */
1033	#define IEM_CIMPL_F_CALLS_AIMPL RT_BIT_32(19)
1034	/** The block calls an ASM-implementation instruction function with an implicit
1035	* X86FXSTATE pointer argument.
1036	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL, IEM_CIMPL_F_CALLS_AIMPL and
1037	* IEM_CIMPL_F_CALLS_AIMPL_WITH_XSTATE.
1038	* @note The python scripts will add this if missing. */
1039	#define IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE RT_BIT_32(20)
1040	/** The block calls an ASM-implementation instruction function with an implicit
1041	* X86XSAVEAREA pointer argument.
1042	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL, IEM_CIMPL_F_CALLS_AIMPL and
1043	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
1044	* @note No different from IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE, so same value.
1045	* @note The python scripts will add this if missing. */
1046	#define IEM_CIMPL_F_CALLS_AIMPL_WITH_XSTATE IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE
1047	/** @} */
1048
1049
1050	/** @name IEM_F_XXX - Execution mode flags (IEMCPU::fExec, IEMTB::fFlags).
1051	*
1052	* These flags are set when entering IEM and adjusted as code is executed, such
1053	* that they will always contain the current values as instructions are
1054	* finished.
1055	*
1056	* In recompiled execution mode, (most of) these flags are included in the
1057	* translation block selection key and stored in IEMTB::fFlags alongside the
1058	* IEMTB_F_XXX flags. The latter flags uses bits 31 thru 24, which are all zero
1059	* in IEMCPU::fExec.
1060	*
1061	* @{ */
1062	/** Mode: The block target mode mask. */
1063	#define IEM_F_MODE_MASK UINT32_C(0x0000001f)
1064	/** Mode: The IEMMODE part of the IEMTB_F_MODE_MASK value. */
1065	#define IEM_F_MODE_CPUMODE_MASK UINT32_C(0x00000003)
1066	/** X86 Mode: Bit used to indicating pre-386 CPU in 16-bit mode (for eliminating
1067	* conditional in EIP/IP updating), and flat wide open CS, SS, DS, and ES in
1068	* 32-bit mode (for simplifying most memory accesses). */
1069	#define IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK UINT32_C(0x00000004)
1070	/** X86 Mode: Bit indicating protected mode, real mode (or SMM) when not set. */
1071	#define IEM_F_MODE_X86_PROT_MASK UINT32_C(0x00000008)
1072	/** X86 Mode: Bit used to indicate virtual 8086 mode (only 16-bit). */
1073	#define IEM_F_MODE_X86_V86_MASK UINT32_C(0x00000010)
1074
1075	/** X86 Mode: 16-bit on 386 or later. */
1076	#define IEM_F_MODE_X86_16BIT UINT32_C(0x00000000)
1077	/** X86 Mode: 80286, 80186 and 8086/88 targetting blocks (EIP update opt). */
1078	#define IEM_F_MODE_X86_16BIT_PRE_386 UINT32_C(0x00000004)
1079	/** X86 Mode: 16-bit protected mode on 386 or later. */
1080	#define IEM_F_MODE_X86_16BIT_PROT UINT32_C(0x00000008)
1081	/** X86 Mode: 16-bit protected mode on 386 or later. */
1082	#define IEM_F_MODE_X86_16BIT_PROT_PRE_386 UINT32_C(0x0000000c)
1083	/** X86 Mode: 16-bit virtual 8086 protected mode (on 386 or later). */
1084	#define IEM_F_MODE_X86_16BIT_PROT_V86 UINT32_C(0x00000018)
1085
1086	/** X86 Mode: 32-bit on 386 or later. */
1087	#define IEM_F_MODE_X86_32BIT UINT32_C(0x00000001)
1088	/** X86 Mode: 32-bit mode with wide open flat CS, SS, DS and ES. */
1089	#define IEM_F_MODE_X86_32BIT_FLAT UINT32_C(0x00000005)
1090	/** X86 Mode: 32-bit protected mode. */
1091	#define IEM_F_MODE_X86_32BIT_PROT UINT32_C(0x00000009)
1092	/** X86 Mode: 32-bit protected mode with wide open flat CS, SS, DS and ES. */
1093	#define IEM_F_MODE_X86_32BIT_PROT_FLAT UINT32_C(0x0000000d)
1094
1095	/** X86 Mode: 64-bit (includes protected, but not the flat bit). */
1096	#define IEM_F_MODE_X86_64BIT UINT32_C(0x0000000a)
1097
1098	/** X86 Mode: Checks if @a a_fExec represent a FLAT mode. */
1099	#define IEM_F_MODE_X86_IS_FLAT(a_fExec) ( ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_64BIT \
1100	\|\| ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_32BIT_PROT_FLAT \
1101	\|\| ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_32BIT_FLAT)
1102
1103	/** Bypass access handlers when set. */
1104	#define IEM_F_BYPASS_HANDLERS UINT32_C(0x00010000)
1105	/** Have pending hardware instruction breakpoints. */
1106	#define IEM_F_PENDING_BRK_INSTR UINT32_C(0x00020000)
1107	/** Have pending hardware data breakpoints. */
1108	#define IEM_F_PENDING_BRK_DATA UINT32_C(0x00040000)
1109
1110	/** X86: Have pending hardware I/O breakpoints. */
1111	#define IEM_F_PENDING_BRK_X86_IO UINT32_C(0x00000400)
1112	/** X86: Disregard the lock prefix (implied or not) when set. */
1113	#define IEM_F_X86_DISREGARD_LOCK UINT32_C(0x00000800)
1114
1115	/** Pending breakpoint mask (what iemCalcExecDbgFlags works out). */
1116	#define IEM_F_PENDING_BRK_MASK (IEM_F_PENDING_BRK_INSTR \| IEM_F_PENDING_BRK_DATA \| IEM_F_PENDING_BRK_X86_IO)
1117
1118	/** Caller configurable options. */
1119	#define IEM_F_USER_OPTS (IEM_F_BYPASS_HANDLERS \| IEM_F_X86_DISREGARD_LOCK)
1120
1121	/** X86: The current protection level (CPL) shift factor. */
1122	#define IEM_F_X86_CPL_SHIFT 8
1123	/** X86: The current protection level (CPL) mask. */
1124	#define IEM_F_X86_CPL_MASK UINT32_C(0x00000300)
1125	/** X86: The current protection level (CPL) shifted mask. */
1126	#define IEM_F_X86_CPL_SMASK UINT32_C(0x00000003)
1127
1128	/** X86: Alignment checks enabled (CR0.AM=1 & EFLAGS.AC=1). */
1129	#define IEM_F_X86_AC UINT32_C(0x00080000)
1130
1131	/** X86 execution context.
1132	* The IEM_F_X86_CTX_XXX values are individual flags that can be combined (with
1133	* the exception of IEM_F_X86_CTX_NORMAL). This allows running VMs from SMM
1134	* mode. */
1135	#define IEM_F_X86_CTX_MASK UINT32_C(0x0000f000)
1136	/** X86 context: Plain regular execution context. */
1137	#define IEM_F_X86_CTX_NORMAL UINT32_C(0x00000000)
1138	/** X86 context: VT-x enabled. */
1139	#define IEM_F_X86_CTX_VMX UINT32_C(0x00001000)
1140	/** X86 context: AMD-V enabled. */
1141	#define IEM_F_X86_CTX_SVM UINT32_C(0x00002000)
1142	/** X86 context: In AMD-V or VT-x guest mode. */
1143	#define IEM_F_X86_CTX_IN_GUEST UINT32_C(0x00004000)
1144	/** X86 context: System management mode (SMM). */
1145	#define IEM_F_X86_CTX_SMM UINT32_C(0x00008000)
1146
1147	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
1148	* iemRegFinishClearingRF() most for most situations (CPUMCTX_DBG_HIT_DRX_MASK
1149	* and CPUMCTX_DBG_DBGF_MASK are covered by the IEM_F_PENDING_BRK_XXX bits
1150	* alread). */
1151
1152	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
1153	* iemRegFinishClearingRF() most for most situations
1154	* (CPUMCTX_DBG_HIT_DRX_MASK and CPUMCTX_DBG_DBGF_MASK are covered by
1155	* the IEM_F_PENDING_BRK_XXX bits alread). */
1156
1157	/** @} */
1158
1159
1160	/** @name IEMTB_F_XXX - Translation block flags (IEMTB::fFlags).
1161	*
1162	* Extends the IEM_F_XXX flags (subject to IEMTB_F_IEM_F_MASK) to make up the
1163	* translation block flags. The combined flag mask (subject to
1164	* IEMTB_F_KEY_MASK) is used as part of the lookup key for translation blocks.
1165	*
1166	* @{ */
1167	/** Mask of IEM_F_XXX flags included in IEMTB_F_XXX. */
1168	#define IEMTB_F_IEM_F_MASK UINT32_C(0x00ffffff)
1169
1170	/** Type: The block type mask. */
1171	#define IEMTB_F_TYPE_MASK UINT32_C(0x03000000)
1172	/** Type: Purly threaded recompiler (via tables). */
1173	#define IEMTB_F_TYPE_THREADED UINT32_C(0x01000000)
1174	/** Type: Native recompilation. */
1175	#define IEMTB_F_TYPE_NATIVE UINT32_C(0x02000000)
1176
1177	/** Set when we're starting the block in an "interrupt shadow".
1178	* We don't need to distingish between the two types of this mask, thus the one.
1179	* @see CPUMCTX_INHIBIT_SHADOW, CPUMIsInInterruptShadow() */
1180	#define IEMTB_F_INHIBIT_SHADOW UINT32_C(0x04000000)
1181	/** Set when we're currently inhibiting NMIs
1182	* @see CPUMCTX_INHIBIT_NMI, CPUMAreInterruptsInhibitedByNmi() */
1183	#define IEMTB_F_INHIBIT_NMI UINT32_C(0x08000000)
1184
1185	/** Checks that EIP/IP is wihin CS.LIM before each instruction. Used when
1186	* we're close the limit before starting a TB, as determined by
1187	* iemGetTbFlagsForCurrentPc(). */
1188	#define IEMTB_F_CS_LIM_CHECKS UINT32_C(0x10000000)
1189
1190	/** Mask of the IEMTB_F_XXX flags that are part of the TB lookup key.
1191	*
1192	* @note We skip all of IEM_F_X86_CTX_MASK, with the exception of SMM (which we
1193	* don't implement), because we don't currently generate any context
1194	* specific code - that's all handled in CIMPL functions.
1195	*
1196	* For the threaded recompiler we don't generate any CPL specific code
1197	* either, but the native recompiler does for memory access (saves getting
1198	* the CPL from fExec and turning it into IEMTLBE_F_PT_NO_USER).
1199	* Since most OSes will not share code between rings, this shouldn't
1200	* have any real effect on TB/memory/recompiling load.
1201	*/
1202	#define IEMTB_F_KEY_MASK ((UINT32_MAX & ~(IEM_F_X86_CTX_MASK \| IEMTB_F_TYPE_MASK)) \| IEM_F_X86_CTX_SMM)
1203	/** @} */
1204
1205	AssertCompile( (IEM_F_MODE_X86_16BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
1206	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
1207	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_PROT_MASK));
1208	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_V86_MASK));
1209	AssertCompile( (IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
1210	AssertCompile( IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
1211	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_PROT_MASK));
1212	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
1213	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
1214	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
1215	AssertCompile( IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
1216	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_V86_MASK));
1217	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
1218	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
1219	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_PROT_MASK);
1220	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
1221	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_PROT_MASK);
1222	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
1223	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_V86_MASK);
1224
1225	AssertCompile( (IEM_F_MODE_X86_32BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
1226	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
1227	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_PROT_MASK));
1228	AssertCompile( (IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
1229	AssertCompile( IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
1230	AssertCompile(!(IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_PROT_MASK));
1231	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
1232	AssertCompile(!(IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
1233	AssertCompile( IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
1234	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
1235	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
1236	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_PROT_MASK);
1237
1238	AssertCompile( (IEM_F_MODE_X86_64BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_64BIT);
1239	AssertCompile( IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_PROT_MASK);
1240	AssertCompile(!(IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
1241
1242	/** Native instruction type for use with the native code generator.
1243	* This is a byte (uint8_t) for x86 and amd64 and uint32_t for the other(s). */
1244	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
1245	typedef uint8_t IEMNATIVEINSTR;
1246	#else
1247	typedef uint32_t IEMNATIVEINSTR;
1248	#endif
1249	/** Pointer to a native instruction unit. */
1250	typedef IEMNATIVEINSTR *PIEMNATIVEINSTR;
1251	/** Pointer to a const native instruction unit. */
1252	typedef IEMNATIVEINSTR const *PCIEMNATIVEINSTR;
1253
1254	/**
1255	* A call for the threaded call table.
1256	*/
1257	typedef struct IEMTHRDEDCALLENTRY
1258	{
1259	/** The function to call (IEMTHREADEDFUNCS). */
1260	uint16_t enmFunction;
1261
1262	/** Instruction number in the TB (for statistics). */
1263	uint8_t idxInstr;
1264	/** The opcode length. */
1265	uint8_t cbOpcode;
1266	/** Offset into IEMTB::pabOpcodes. */
1267	uint16_t offOpcode;
1268
1269	/** TB lookup table index (7 bits) and large size (1 bits).
1270	*
1271	* The default size is 1 entry, but for indirect calls and returns we set the
1272	* top bit and allocate 4 (IEM_TB_LOOKUP_TAB_LARGE_SIZE) entries. The large
1273	* tables uses RIP for selecting the entry to use, as it is assumed a hash table
1274	* lookup isn't that slow compared to sequentially trying out 4 TBs.
1275	*
1276	* By default lookup table entry 0 for a TB is reserved as a fallback for
1277	* calltable entries w/o explicit entreis, so this member will be non-zero if
1278	* there is a lookup entry associated with this call.
1279	*
1280	* @sa IEM_TB_LOOKUP_TAB_GET_SIZE, IEM_TB_LOOKUP_TAB_GET_IDX
1281	*/
1282	uint8_t uTbLookup;
1283
1284	/** Flags - IEMTHREADEDCALLENTRY_F_XXX. */
1285	uint8_t fFlags;
1286
1287	/** Generic parameters. */
1288	uint64_t auParams[3];
1289	} IEMTHRDEDCALLENTRY;
1290	AssertCompileSize(IEMTHRDEDCALLENTRY, sizeof(uint64_t) * 4);
1291	/** Pointer to a threaded call entry. */
1292	typedef struct IEMTHRDEDCALLENTRY *PIEMTHRDEDCALLENTRY;
1293	/** Pointer to a const threaded call entry. */
1294	typedef IEMTHRDEDCALLENTRY const *PCIEMTHRDEDCALLENTRY;
1295
1296	/** The number of TB lookup table entries for a large allocation
1297	* (IEMTHRDEDCALLENTRY::uTbLookup bit 7 set). */
1298	#define IEM_TB_LOOKUP_TAB_LARGE_SIZE 4
1299	/** Get the lookup table size from IEMTHRDEDCALLENTRY::uTbLookup. */
1300	#define IEM_TB_LOOKUP_TAB_GET_SIZE(a_uTbLookup) (!((a_uTbLookup) & 0x80) ? 1 : IEM_TB_LOOKUP_TAB_LARGE_SIZE)
1301	/** Get the first lookup table index from IEMTHRDEDCALLENTRY::uTbLookup. */
1302	#define IEM_TB_LOOKUP_TAB_GET_IDX(a_uTbLookup) ((a_uTbLookup) & 0x7f)
1303	/** Get the lookup table index from IEMTHRDEDCALLENTRY::uTbLookup and RIP. */
1304	#define IEM_TB_LOOKUP_TAB_GET_IDX_WITH_RIP(a_uTbLookup, a_Rip) \
1305	(!((a_uTbLookup) & 0x80) ? (a_uTbLookup) & 0x7f : ((a_uTbLookup) & 0x7f) + ((a_Rip) & (IEM_TB_LOOKUP_TAB_LARGE_SIZE - 1)) )
1306
1307	/** Make a IEMTHRDEDCALLENTRY::uTbLookup value. */
1308	#define IEM_TB_LOOKUP_TAB_MAKE(a_idxTable, a_fLarge) ((a_idxTable) \| ((a_fLarge) ? 0x80 : 0))
1309
1310
1311	/** The call entry is a jump target. */
1312	#define IEMTHREADEDCALLENTRY_F_JUMP_TARGET UINT8_C(0x01)
1313
1314
1315	/**
1316	* Native IEM TB 'function' typedef.
1317	*
1318	* This will throw/longjmp on occation.
1319	*
1320	* @note AMD64 doesn't have that many non-volatile registers and does sport
1321	* 32-bit address displacments, so we don't need pCtx.
1322	*
1323	* On ARM64 pCtx allows us to directly address the whole register
1324	* context without requiring a separate indexing register holding the
1325	* offset. This saves an instruction loading the offset for each guest
1326	* CPU context access, at the cost of a non-volatile register.
1327	* Fortunately, ARM64 has quite a lot more registers.
1328	*/
1329	typedef
1330	#ifdef RT_ARCH_AMD64
1331	int FNIEMTBNATIVE(PVMCPUCC pVCpu)
1332	#else
1333	int FNIEMTBNATIVE(PVMCPUCC pVCpu, PCPUMCTX pCtx)
1334	#endif
1335	#if RT_CPLUSPLUS_PREREQ(201700)
1336	IEM_NOEXCEPT_MAY_LONGJMP
1337	#endif
1338	;
1339	/** Pointer to a native IEM TB entry point function.
1340	* This will throw/longjmp on occation. */
1341	typedef FNIEMTBNATIVE *PFNIEMTBNATIVE;
1342
1343
1344	/**
1345	* Translation block.
1346	*
1347	* The current plan is to just keep TBs and associated lookup hash table private
1348	* to each VCpu as that simplifies TB removal greatly (no races) and generally
1349	* avoids using expensive atomic primitives for updating lists and stuff.
1350	*/
1351	#pragma pack(2) /* to prevent the Thrd structure from being padded unnecessarily */
1352	typedef struct IEMTB
1353	{
1354	/** Next block with the same hash table entry. */
1355	struct IEMTB *pNext;
1356	/** Usage counter. */
1357	uint32_t cUsed;
1358	/** The IEMCPU::msRecompilerPollNow last time it was used. */
1359	uint32_t msLastUsed;
1360
1361	/** @name What uniquely identifies the block.
1362	* @{ */
1363	RTGCPHYS GCPhysPc;
1364	/** IEMTB_F_XXX (i.e. IEM_F_XXX ++). */
1365	uint32_t fFlags;
1366	union
1367	{
1368	struct
1369	{
1370	/*< Relevant CS X86DESCATTR_XXX bits. /
1371	uint16_t fAttr;
1372	} x86;
1373	};
1374	/** @} */
1375
1376	/** Number of opcode ranges. */
1377	uint8_t cRanges;
1378	/** Statistics: Number of instructions in the block. */
1379	uint8_t cInstructions;
1380
1381	/** Type specific info. */
1382	union
1383	{
1384	struct
1385	{
1386	/** The call sequence table. */
1387	PIEMTHRDEDCALLENTRY paCalls;
1388	/** Number of calls in paCalls. */
1389	uint16_t cCalls;
1390	/** Number of calls allocated. */
1391	uint16_t cAllocated;
1392	} Thrd;
1393	struct
1394	{
1395	/** The native instructions (PFNIEMTBNATIVE). */
1396	PIEMNATIVEINSTR paInstructions;
1397	/** Number of instructions pointed to by paInstructions. */
1398	uint32_t cInstructions;
1399	} Native;
1400	/** Generic view for zeroing when freeing. */
1401	struct
1402	{
1403	uintptr_t uPtr;
1404	uint32_t uData;
1405	} Gen;
1406	};
1407
1408	/** The allocation chunk this TB belongs to. */
1409	uint8_t idxAllocChunk;
1410	/** The number of entries in the lookup table.
1411	* Because we're out of space, the TB lookup table is located before the
1412	* opcodes pointed to by pabOpcodes. */
1413	uint8_t cTbLookupEntries;
1414
1415	/** Number of bytes of opcodes stored in pabOpcodes.
1416	* @todo this field isn't really needed, aRanges keeps the actual info. */
1417	uint16_t cbOpcodes;
1418	/** Pointer to the opcode bytes this block was recompiled from.
1419	* This also points to the TB lookup table, which starts cTbLookupEntries
1420	* entries before the opcodes (we don't have room atm for another point). */
1421	uint8_t *pabOpcodes;
1422
1423	union
1424	{
1425	/** Native recompilation debug info if enabled.
1426	* This is only generated by the native recompiler. */
1427	struct IEMTBDBG *pDbgInfo;
1428	/** For threaded TBs and natives when debug info is disabled, this is the flat
1429	* PC corresponding to GCPhysPc. */
1430	RTGCPTR FlatPc;
1431	};
1432
1433	/* --- 64 byte cache line end --- */
1434
1435	/** Opcode ranges.
1436	*
1437	* The opcode checkers and maybe TLB loading functions will use this to figure
1438	* out what to do. The parameter will specify an entry and the opcode offset to
1439	* start at and the minimum number of bytes to verify (instruction length).
1440	*
1441	* When VT-x and AMD-V looks up the opcode bytes for an exitting instruction,
1442	* they'll first translate RIP (+ cbInstr - 1) to a physical address using the
1443	* code TLB (must have a valid entry for that address) and scan the ranges to
1444	* locate the corresponding opcodes. Probably.
1445	*/
1446	struct IEMTBOPCODERANGE
1447	{
1448	/** Offset within pabOpcodes. */
1449	uint16_t offOpcodes;
1450	/** Number of bytes. */
1451	uint16_t cbOpcodes;
1452	/** The page offset. */
1453	RT_GCC_EXTENSION
1454	uint16_t offPhysPage : 12;
1455	/** Unused bits. */
1456	RT_GCC_EXTENSION
1457	uint16_t u2Unused : 2;
1458	/** Index into GCPhysPc + aGCPhysPages for the physical page address. */
1459	RT_GCC_EXTENSION
1460	uint16_t idxPhysPage : 2;
1461	} aRanges[8];
1462
1463	/** Physical pages that this TB covers.
1464	* The GCPhysPc w/o page offset is element zero, so starting here with 1. */
1465	RTGCPHYS aGCPhysPages[2];
1466	} IEMTB;
1467	#pragma pack()
1468	AssertCompileMemberAlignment(IEMTB, GCPhysPc, sizeof(RTGCPHYS));
1469	AssertCompileMemberAlignment(IEMTB, Thrd, sizeof(void *));
1470	AssertCompileMemberAlignment(IEMTB, pabOpcodes, sizeof(void *));
1471	AssertCompileMemberAlignment(IEMTB, pDbgInfo, sizeof(void *));
1472	AssertCompileMemberAlignment(IEMTB, aGCPhysPages, sizeof(RTGCPHYS));
1473	AssertCompileMemberOffset(IEMTB, aRanges, 64);
1474	AssertCompileMemberSize(IEMTB, aRanges[0], 6);
1475	#if 1
1476	AssertCompileSize(IEMTB, 128);
1477	# define IEMTB_SIZE_IS_POWER_OF_TWO /*< The IEMTB size is a power of two. /
1478	#else
1479	AssertCompileSize(IEMTB, 168);
1480	# undef IEMTB_SIZE_IS_POWER_OF_TWO
1481	#endif
1482
1483	/** Pointer to a translation block. */
1484	typedef IEMTB *PIEMTB;
1485	/** Pointer to a const translation block. */
1486	typedef IEMTB const *PCIEMTB;
1487
1488	/** Gets address of the given TB lookup table entry. */
1489	#define IEMTB_GET_TB_LOOKUP_TAB_ENTRY(a_pTb, a_idx) \
1490	((PIEMTB )&(a_pTb)->pabOpcodes[-(int)((a_pTb)->cTbLookupEntries - (a_idx)) sizeof(PIEMTB)])
1491
1492	/**
1493	* Gets the physical address for a TB opcode range.
1494	*/
1495	DECL_FORCE_INLINE(RTGCPHYS) iemTbGetRangePhysPageAddr(PCIEMTB pTb, uint8_t idxRange)
1496	{
1497	Assert(idxRange < RT_MIN(pTb->cRanges, RT_ELEMENTS(pTb->aRanges)));
1498	uint8_t const idxPage = pTb->aRanges[idxRange].idxPhysPage;
1499	Assert(idxPage <= RT_ELEMENTS(pTb->aGCPhysPages));
1500	if (idxPage == 0)
1501	return pTb->GCPhysPc & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
1502	Assert(!(pTb->aGCPhysPages[idxPage - 1] & GUEST_PAGE_OFFSET_MASK));
1503	return pTb->aGCPhysPages[idxPage - 1];
1504	}
1505
1506
1507	/**
1508	* A chunk of memory in the TB allocator.
1509	*/
1510	typedef struct IEMTBCHUNK
1511	{
1512	/** Pointer to the translation blocks in this chunk. */
1513	PIEMTB paTbs;
1514	#ifdef IN_RING0
1515	/** Allocation handle. */
1516	RTR0MEMOBJ hMemObj;
1517	#endif
1518	} IEMTBCHUNK;
1519
1520	/**
1521	* A per-CPU translation block allocator.
1522	*
1523	* Because of how the IEMTBCACHE uses the lower 6 bits of the TB address to keep
1524	* the length of the collision list, and of course also for cache line alignment
1525	* reasons, the TBs must be allocated with at least 64-byte alignment.
1526	* Memory is there therefore allocated using one of the page aligned allocators.
1527	*
1528	*
1529	* To avoid wasting too much memory, it is allocated piecemeal as needed,
1530	* in chunks (IEMTBCHUNK) of 2 MiB or more. The TB has an 8-bit chunk index
1531	* that enables us to quickly calculate the allocation bitmap position when
1532	* freeing the translation block.
1533	*/
1534	typedef struct IEMTBALLOCATOR
1535	{
1536	/** Magic value (IEMTBALLOCATOR_MAGIC). */
1537	uint32_t uMagic;
1538
1539	#ifdef IEMTB_SIZE_IS_POWER_OF_TWO
1540	/** Mask corresponding to cTbsPerChunk - 1. */
1541	uint32_t fChunkMask;
1542	/** Shift count corresponding to cTbsPerChunk. */
1543	uint8_t cChunkShift;
1544	#else
1545	uint32_t uUnused;
1546	uint8_t bUnused;
1547	#endif
1548	/** Number of chunks we're allowed to allocate. */
1549	uint8_t cMaxChunks;
1550	/** Number of chunks currently populated. */
1551	uint16_t cAllocatedChunks;
1552	/** Number of translation blocks per chunk. */
1553	uint32_t cTbsPerChunk;
1554	/** Chunk size. */
1555	uint32_t cbPerChunk;
1556
1557	/** The maximum number of TBs. */
1558	uint32_t cMaxTbs;
1559	/** Total number of TBs in the populated chunks.
1560	* (cAllocatedChunks * cTbsPerChunk) */
1561	uint32_t cTotalTbs;
1562	/** The current number of TBs in use.
1563	* The number of free TBs: cAllocatedTbs - cInUseTbs; */
1564	uint32_t cInUseTbs;
1565	/** Statistics: Number of the cInUseTbs that are native ones. */
1566	uint32_t cNativeTbs;
1567	/** Statistics: Number of the cInUseTbs that are threaded ones. */
1568	uint32_t cThreadedTbs;
1569
1570	/** Where to start pruning TBs from when we're out.
1571	* See iemTbAllocatorAllocSlow for details. */
1572	uint32_t iPruneFrom;
1573	/** Where to start pruning native TBs from when we're out of executable memory.
1574	* See iemTbAllocatorFreeupNativeSpace for details. */
1575	uint32_t iPruneNativeFrom;
1576	uint64_t u64Padding;
1577
1578	/** Statistics: Number of TB allocation calls. */
1579	STAMCOUNTER StatAllocs;
1580	/** Statistics: Number of TB free calls. */
1581	STAMCOUNTER StatFrees;
1582	/** Statistics: Time spend pruning. */
1583	STAMPROFILE StatPrune;
1584	/** Statistics: Time spend pruning native TBs. */
1585	STAMPROFILE StatPruneNative;
1586
1587	/** The delayed free list (see iemTbAlloctorScheduleForFree). */
1588	PIEMTB pDelayedFreeHead;
1589	/* Head of the list of free TBs. */
1590	PIEMTB pTbsFreeHead;
1591
1592	/** Allocation chunks. */
1593	IEMTBCHUNK aChunks[256];
1594	} IEMTBALLOCATOR;
1595	/** Pointer to a TB allocator. */
1596	typedef struct IEMTBALLOCATOR *PIEMTBALLOCATOR;
1597
1598	/** Magic value for the TB allocator (Emmet Harley Cohen). */
1599	#define IEMTBALLOCATOR_MAGIC UINT32_C(0x19900525)
1600
1601
1602	/**
1603	* A per-CPU translation block cache (hash table).
1604	*
1605	* The hash table is allocated once during IEM initialization and size double
1606	* the max TB count, rounded up to the nearest power of two (so we can use and
1607	* AND mask rather than a rest division when hashing).
1608	*/
1609	typedef struct IEMTBCACHE
1610	{
1611	/** Magic value (IEMTBCACHE_MAGIC). */
1612	uint32_t uMagic;
1613	/** Size of the hash table. This is a power of two. */
1614	uint32_t cHash;
1615	/** The mask corresponding to cHash. */
1616	uint32_t uHashMask;
1617	uint32_t uPadding;
1618
1619	/** @name Statistics
1620	* @{ */
1621	/** Number of collisions ever. */
1622	STAMCOUNTER cCollisions;
1623
1624	/** Statistics: Number of TB lookup misses. */
1625	STAMCOUNTER cLookupMisses;
1626	/** Statistics: Number of TB lookup hits via hash table (debug only). */
1627	STAMCOUNTER cLookupHits;
1628	/** Statistics: Number of TB lookup hits via TB associated lookup table (debug only). */
1629	STAMCOUNTER cLookupHitsViaTbLookupTable;
1630	STAMCOUNTER auPadding2[2];
1631	/** Statistics: Collision list length pruning. */
1632	STAMPROFILE StatPrune;
1633	/** @} */
1634
1635	/** The hash table itself.
1636	* @note The lower 6 bits of the pointer is used for keeping the collision
1637	* list length, so we can take action when it grows too long.
1638	* This works because TBs are allocated using a 64 byte (or
1639	* higher) alignment from page aligned chunks of memory, so the lower
1640	* 6 bits of the address will always be zero.
1641	* See IEMTBCACHE_PTR_COUNT_MASK, IEMTBCACHE_PTR_MAKE and friends.
1642	*/
1643	RT_FLEXIBLE_ARRAY_EXTENSION
1644	PIEMTB apHash[RT_FLEXIBLE_ARRAY];
1645	} IEMTBCACHE;
1646	/** Pointer to a per-CPU translation block cache. */
1647	typedef IEMTBCACHE *PIEMTBCACHE;
1648
1649	/** Magic value for IEMTBCACHE (Johnny O'Neal). */
1650	#define IEMTBCACHE_MAGIC UINT32_C(0x19561010)
1651
1652	/** The collision count mask for IEMTBCACHE::apHash entries. */
1653	#define IEMTBCACHE_PTR_COUNT_MASK ((uintptr_t)0x3f)
1654	/** The max collision count for IEMTBCACHE::apHash entries before pruning. */
1655	#define IEMTBCACHE_PTR_MAX_COUNT ((uintptr_t)0x30)
1656	/** Combine a TB pointer and a collision list length into a value for an
1657	* IEMTBCACHE::apHash entry. */
1658	#define IEMTBCACHE_PTR_MAKE(a_pTb, a_cCount) (PIEMTB)((uintptr_t)(a_pTb) \| (a_cCount))
1659	/** Combine a TB pointer and a collision list length into a value for an
1660	* IEMTBCACHE::apHash entry. */
1661	#define IEMTBCACHE_PTR_GET_TB(a_pHashEntry) (PIEMTB)((uintptr_t)(a_pHashEntry) & ~IEMTBCACHE_PTR_COUNT_MASK)
1662	/** Combine a TB pointer and a collision list length into a value for an
1663	* IEMTBCACHE::apHash entry. */
1664	#define IEMTBCACHE_PTR_GET_COUNT(a_pHashEntry) ((uintptr_t)(a_pHashEntry) & IEMTBCACHE_PTR_COUNT_MASK)
1665
1666	/**
1667	* Calculates the hash table slot for a TB from physical PC address and TB flags.
1668	*/
1669	#define IEMTBCACHE_HASH(a_paCache, a_fTbFlags, a_GCPhysPc) \
1670	IEMTBCACHE_HASH_NO_KEY_MASK(a_paCache, (a_fTbFlags) & IEMTB_F_KEY_MASK, a_GCPhysPc)
1671
1672	/**
1673	* Calculates the hash table slot for a TB from physical PC address and TB
1674	* flags, ASSUMING the caller has applied IEMTB_F_KEY_MASK to @a a_fTbFlags.
1675	*/
1676	#define IEMTBCACHE_HASH_NO_KEY_MASK(a_paCache, a_fTbFlags, a_GCPhysPc) \
1677	(((uint32_t)(a_GCPhysPc) ^ (a_fTbFlags)) & (a_paCache)->uHashMask)
1678
1679
1680	/** @name IEMBRANCHED_F_XXX - Branched indicator (IEMCPU::fTbBranched).
1681	*
1682	* These flags parallels the main IEM_CIMPL_F_BRANCH_XXX flags.
1683	*
1684	* @{ */
1685	/** Value if no branching happened recently. */
1686	#define IEMBRANCHED_F_NO UINT8_C(0x00)
1687	/** Flag set if direct branch, clear if absolute or indirect. */
1688	#define IEMBRANCHED_F_DIRECT UINT8_C(0x01)
1689	/** Flag set if indirect branch, clear if direct or relative. */
1690	#define IEMBRANCHED_F_INDIRECT UINT8_C(0x02)
1691	/** Flag set if relative branch, clear if absolute or indirect. */
1692	#define IEMBRANCHED_F_RELATIVE UINT8_C(0x04)
1693	/** Flag set if conditional branch, clear if unconditional. */
1694	#define IEMBRANCHED_F_CONDITIONAL UINT8_C(0x08)
1695	/** Flag set if it's a far branch. */
1696	#define IEMBRANCHED_F_FAR UINT8_C(0x10)
1697	/** Flag set if the stack pointer is modified. */
1698	#define IEMBRANCHED_F_STACK UINT8_C(0x20)
1699	/** Flag set if the stack pointer and (maybe) the stack segment are modified. */
1700	#define IEMBRANCHED_F_STACK_FAR UINT8_C(0x40)
1701	/** Flag set (by IEM_MC_REL_JMP_XXX) if it's a zero bytes relative jump. */
1702	#define IEMBRANCHED_F_ZERO UINT8_C(0x80)
1703	/** @} */
1704
1705
1706	/**
1707	* The per-CPU IEM state.
1708	*/
1709	typedef struct IEMCPU
1710	{
1711	/** Info status code that needs to be propagated to the IEM caller.
1712	* This cannot be passed internally, as it would complicate all success
1713	* checks within the interpreter making the code larger and almost impossible
1714	* to get right. Instead, we'll store status codes to pass on here. Each
1715	* source of these codes will perform appropriate sanity checks. */
1716	int32_t rcPassUp; /* 0x00 */
1717	/** Execution flag, IEM_F_XXX. */
1718	uint32_t fExec; /* 0x04 */
1719
1720	/** @name Decoder state.
1721	* @{ */
1722	#ifdef IEM_WITH_CODE_TLB
1723	/** The offset of the next instruction byte. */
1724	uint32_t offInstrNextByte; /* 0x08 */
1725	/** The number of bytes available at pbInstrBuf for the current instruction.
1726	* This takes the max opcode length into account so that doesn't need to be
1727	* checked separately. */
1728	uint32_t cbInstrBuf; /* 0x0c */
1729	/** Pointer to the page containing RIP, user specified buffer or abOpcode.
1730	* This can be NULL if the page isn't mappable for some reason, in which
1731	* case we'll do fallback stuff.
1732	*
1733	* If we're executing an instruction from a user specified buffer,
1734	* IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
1735	* aligned pointer but pointer to the user data.
1736	*
1737	* For instructions crossing pages, this will start on the first page and be
1738	* advanced to the next page by the time we've decoded the instruction. This
1739	* therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
1740	*/
1741	uint8_t const pbInstrBuf; / 0x10 */
1742	# if ARCH_BITS == 32
1743	uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
1744	# endif
1745	/** The program counter corresponding to pbInstrBuf.
1746	* This is set to a non-canonical address when we need to invalidate it. */
1747	uint64_t uInstrBufPc; /* 0x18 */
1748	/** The guest physical address corresponding to pbInstrBuf. */
1749	RTGCPHYS GCPhysInstrBuf; /* 0x20 */
1750	/** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
1751	* This takes the CS segment limit into account.
1752	* @note Set to zero when the code TLB is flushed to trigger TLB reload. */
1753	uint16_t cbInstrBufTotal; /* 0x28 */
1754	/** Offset into pbInstrBuf of the first byte of the current instruction.
1755	* Can be negative to efficiently handle cross page instructions. */
1756	int16_t offCurInstrStart; /* 0x2a */
1757
1758	# ifndef IEM_WITH_OPAQUE_DECODER_STATE
1759	/** The prefix mask (IEM_OP_PRF_XXX). */
1760	uint32_t fPrefixes; /* 0x2c */
1761	/** The extra REX ModR/M register field bit (REX.R << 3). */
1762	uint8_t uRexReg; /* 0x30 */
1763	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
1764	* (REX.B << 3). */
1765	uint8_t uRexB; /* 0x31 */
1766	/** The extra REX SIB index field bit (REX.X << 3). */
1767	uint8_t uRexIndex; /* 0x32 */
1768
1769	/** The effective segment register (X86_SREG_XXX). */
1770	uint8_t iEffSeg; /* 0x33 */
1771
1772	/** The offset of the ModR/M byte relative to the start of the instruction. */
1773	uint8_t offModRm; /* 0x34 */
1774
1775	# ifdef IEM_WITH_CODE_TLB_AND_OPCODE_BUF
1776	/** The current offset into abOpcode. */
1777	uint8_t offOpcode; /* 0x35 */
1778	# else
1779	uint8_t bUnused; /* 0x35 */
1780	# endif
1781	# else /* IEM_WITH_OPAQUE_DECODER_STATE */
1782	uint8_t abOpaqueDecoderPart1[0x36 - 0x2c];
1783	# endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1784
1785	#else /* !IEM_WITH_CODE_TLB */
1786	# ifndef IEM_WITH_OPAQUE_DECODER_STATE
1787	/** The size of what has currently been fetched into abOpcode. */
1788	uint8_t cbOpcode; /* 0x08 */
1789	/** The current offset into abOpcode. */
1790	uint8_t offOpcode; /* 0x09 */
1791	/** The offset of the ModR/M byte relative to the start of the instruction. */
1792	uint8_t offModRm; /* 0x0a */
1793
1794	/** The effective segment register (X86_SREG_XXX). */
1795	uint8_t iEffSeg; /* 0x0b */
1796
1797	/** The prefix mask (IEM_OP_PRF_XXX). */
1798	uint32_t fPrefixes; /* 0x0c */
1799	/** The extra REX ModR/M register field bit (REX.R << 3). */
1800	uint8_t uRexReg; /* 0x10 */
1801	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
1802	* (REX.B << 3). */
1803	uint8_t uRexB; /* 0x11 */
1804	/** The extra REX SIB index field bit (REX.X << 3). */
1805	uint8_t uRexIndex; /* 0x12 */
1806
1807	# else /* IEM_WITH_OPAQUE_DECODER_STATE */
1808	uint8_t abOpaqueDecoderPart1[0x13 - 0x08];
1809	# endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1810	#endif /* !IEM_WITH_CODE_TLB */
1811
1812	#ifndef IEM_WITH_OPAQUE_DECODER_STATE
1813	/** The effective operand mode. */
1814	IEMMODE enmEffOpSize; /* 0x36, 0x13 */
1815	/** The default addressing mode. */
1816	IEMMODE enmDefAddrMode; /* 0x37, 0x14 */
1817	/** The effective addressing mode. */
1818	IEMMODE enmEffAddrMode; /* 0x38, 0x15 */
1819	/** The default operand mode. */
1820	IEMMODE enmDefOpSize; /* 0x39, 0x16 */
1821
1822	/** Prefix index (VEX.pp) for two byte and three byte tables. */
1823	uint8_t idxPrefix; /* 0x3a, 0x17 */
1824	/** 3rd VEX/EVEX/XOP register.
1825	* Please use IEM_GET_EFFECTIVE_VVVV to access. */
1826	uint8_t uVex3rdReg; /* 0x3b, 0x18 */
1827	/** The VEX/EVEX/XOP length field. */
1828	uint8_t uVexLength; /* 0x3c, 0x19 */
1829	/** Additional EVEX stuff. */
1830	uint8_t fEvexStuff; /* 0x3d, 0x1a */
1831
1832	# ifndef IEM_WITH_CODE_TLB
1833	/** Explicit alignment padding. */
1834	uint8_t abAlignment2a[1]; /* 0x1b */
1835	# endif
1836	/** The FPU opcode (FOP). */
1837	uint16_t uFpuOpcode; /* 0x3e, 0x1c */
1838	# ifndef IEM_WITH_CODE_TLB
1839	/** Explicit alignment padding. */
1840	uint8_t abAlignment2b[2]; /* 0x1e */
1841	# endif
1842
1843	/** The opcode bytes. */
1844	uint8_t abOpcode[15]; /* 0x40, 0x20 */
1845	/** Explicit alignment padding. */
1846	# ifdef IEM_WITH_CODE_TLB
1847	//uint8_t abAlignment2c[0x4f - 0x4f]; /* 0x4f */
1848	# else
1849	uint8_t abAlignment2c[0x4f - 0x2f]; /* 0x2f */
1850	# endif
1851
1852	#else /* IEM_WITH_OPAQUE_DECODER_STATE */
1853	# ifdef IEM_WITH_CODE_TLB
1854	uint8_t abOpaqueDecoderPart2[0x4f - 0x36];
1855	# else
1856	uint8_t abOpaqueDecoderPart2[0x4f - 0x13];
1857	# endif
1858	#endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1859	/** @} */
1860
1861
1862	/** The number of active guest memory mappings. */
1863	uint8_t cActiveMappings; /* 0x4f, 0x4f */
1864
1865	/** Records for tracking guest memory mappings. */
1866	struct
1867	{
1868	/** The address of the mapped bytes. */
1869	R3R0PTRTYPE(void *) pv;
1870	/** The access flags (IEM_ACCESS_XXX).
1871	* IEM_ACCESS_INVALID if the entry is unused. */
1872	uint32_t fAccess;
1873	#if HC_ARCH_BITS == 64
1874	uint32_t u32Alignment4; /*< Alignment padding. /
1875	#endif
1876	} aMemMappings[3]; /* 0x50 LB 0x30 */
1877
1878	/** Locking records for the mapped memory. */
1879	union
1880	{
1881	PGMPAGEMAPLOCK Lock;
1882	uint64_t au64Padding[2];
1883	} aMemMappingLocks[3]; /* 0x80 LB 0x30 */
1884
1885	/** Bounce buffer info.
1886	* This runs in parallel to aMemMappings. */
1887	struct
1888	{
1889	/** The physical address of the first byte. */
1890	RTGCPHYS GCPhysFirst;
1891	/** The physical address of the second page. */
1892	RTGCPHYS GCPhysSecond;
1893	/** The number of bytes in the first page. */
1894	uint16_t cbFirst;
1895	/** The number of bytes in the second page. */
1896	uint16_t cbSecond;
1897	/** Whether it's unassigned memory. */
1898	bool fUnassigned;
1899	/** Explicit alignment padding. */
1900	bool afAlignment5[3];
1901	} aMemBbMappings[3]; /* 0xb0 LB 0x48 */
1902
1903	/** The flags of the current exception / interrupt. */
1904	uint32_t fCurXcpt; /* 0xf8 */
1905	/** The current exception / interrupt. */
1906	uint8_t uCurXcpt; /* 0xfc */
1907	/** Exception / interrupt recursion depth. */
1908	int8_t cXcptRecursions; /* 0xfb */
1909
1910	/** The next unused mapping index.
1911	* @todo try find room for this up with cActiveMappings. */
1912	uint8_t iNextMapping; /* 0xfd */
1913	uint8_t abAlignment7[1];
1914
1915	/** Bounce buffer storage.
1916	* This runs in parallel to aMemMappings and aMemBbMappings. */
1917	struct
1918	{
1919	uint8_t ab[512];
1920	} aBounceBuffers[3]; /* 0x100 LB 0x600 */
1921
1922
1923	/** Pointer set jump buffer - ring-3 context. */
1924	R3PTRTYPE(jmp_buf *) pJmpBufR3;
1925	/** Pointer set jump buffer - ring-0 context. */
1926	R0PTRTYPE(jmp_buf *) pJmpBufR0;
1927
1928	/** @todo Should move this near @a fCurXcpt later. */
1929	/** The CR2 for the current exception / interrupt. */
1930	uint64_t uCurXcptCr2;
1931	/** The error code for the current exception / interrupt. */
1932	uint32_t uCurXcptErr;
1933
1934	/** @name Statistics
1935	* @{ */
1936	/** The number of instructions we've executed. */
1937	uint32_t cInstructions;
1938	/** The number of potential exits. */
1939	uint32_t cPotentialExits;
1940	/** The number of bytes data or stack written (mostly for IEMExecOneEx).
1941	* This may contain uncommitted writes. */
1942	uint32_t cbWritten;
1943	/** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
1944	uint32_t cRetInstrNotImplemented;
1945	/** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
1946	uint32_t cRetAspectNotImplemented;
1947	/** Counts informational statuses returned (other than VINF_SUCCESS). */
1948	uint32_t cRetInfStatuses;
1949	/** Counts other error statuses returned. */
1950	uint32_t cRetErrStatuses;
1951	/** Number of times rcPassUp has been used. */
1952	uint32_t cRetPassUpStatus;
1953	/** Number of times RZ left with instruction commit pending for ring-3. */
1954	uint32_t cPendingCommit;
1955	/** Number of misaligned (host sense) atomic instruction accesses. */
1956	uint32_t cMisalignedAtomics;
1957	/** Number of long jumps. */
1958	uint32_t cLongJumps;
1959	/** @} */
1960
1961	/** @name Target CPU information.
1962	* @{ */
1963	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
1964	/** The target CPU. */
1965	uint8_t uTargetCpu;
1966	#else
1967	uint8_t bTargetCpuPadding;
1968	#endif
1969	/** For selecting assembly works matching the target CPU EFLAGS behaviour, see
1970	* IEMTARGETCPU_EFL_BEHAVIOR_XXX for values, with the 1st entry for when no
1971	* native host support and the 2nd for when there is.
1972	*
1973	* The two values are typically indexed by a g_CpumHostFeatures bit.
1974	*
1975	* This is for instance used for the BSF & BSR instructions where AMD and
1976	* Intel CPUs produce different EFLAGS. */
1977	uint8_t aidxTargetCpuEflFlavour[2];
1978
1979	/** The CPU vendor. */
1980	CPUMCPUVENDOR enmCpuVendor;
1981	/** @} */
1982
1983	/** Counts RDMSR \#GP(0) LogRel(). */
1984	uint8_t cLogRelRdMsr;
1985	/** Counts WRMSR \#GP(0) LogRel(). */
1986	uint8_t cLogRelWrMsr;
1987	/** Alignment padding. */
1988	uint8_t abAlignment9[46];
1989
1990
1991	/** @name Recompiled Exection
1992	* @{ */
1993	/** Pointer to the current translation block.
1994	* This can either be one being executed or one being compiled. */
1995	R3PTRTYPE(PIEMTB) pCurTbR3;
1996	#ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
1997	/** Frame pointer for the last native TB to execute. */
1998	R3PTRTYPE(void *) pvTbFramePointerR3;
1999	#else
2000	R3PTRTYPE(void *) pvUnusedR3;
2001	#endif
2002	#ifdef IEMNATIVE_WITH_SIMD_FP_NATIVE_EMITTERS
2003	/** The saved host floating point control register (MXCSR on x86, FPCR on arm64)
2004	* needing restore when the TB finished, IEMNATIVE_SIMD_FP_CTRL_REG_NOT_MODIFIED indicates the TB
2005	* didn't modify it so we don't need to restore it. */
2006	# ifdef RT_ARCH_AMD64
2007	uint32_t uRegFpCtrl;
2008	/** Temporary copy of MXCSR for stmxcsr/ldmxcsr (so we don't have to fiddle with stack pointers). */
2009	uint32_t uRegMxcsrTmp;
2010	# elif defined(RT_ARCH_ARM64)
2011	uint64_t uRegFpCtrl;
2012	# else
2013	# error "Port me"
2014	# endif
2015	#else
2016	uint64_t u64Unused;
2017	#endif
2018	/** Pointer to the ring-3 TB cache for this EMT. */
2019	R3PTRTYPE(PIEMTBCACHE) pTbCacheR3;
2020	/** Pointer to the ring-3 TB lookup entry.
2021	* This either points to pTbLookupEntryDummyR3 or an actually lookuptable
2022	* entry, thus it can always safely be used w/o NULL checking. */
2023	R3PTRTYPE(PIEMTB *) ppTbLookupEntryR3;
2024	#if 0 /* unused */
2025	/** The PC (RIP) at the start of pCurTbR3/pCurTbR0.
2026	* The TBs are based on physical addresses, so this is needed to correleated
2027	* RIP to opcode bytes stored in the TB (AMD-V / VT-x). */
2028	uint64_t uCurTbStartPc;
2029	#endif
2030
2031	/** Number of threaded TBs executed. */
2032	uint64_t cTbExecThreaded;
2033	/** Number of native TBs executed. */
2034	uint64_t cTbExecNative;
2035
2036	/** The number of IRQ/FF checks till the next timer poll call. */
2037	uint32_t cTbsTillNextTimerPoll;
2038	/** The virtual sync time at the last timer poll call in milliseconds. */
2039	uint32_t msRecompilerPollNow;
2040	/** The virtual sync time at the last timer poll call in nanoseconds. */
2041	uint64_t nsRecompilerPollNow;
2042	/** The previous cTbsTillNextTimerPoll value. */
2043	uint32_t cTbsTillNextTimerPollPrev;
2044
2045	/** The current instruction number in a native TB.
2046	* This is set by code that may trigger an unexpected TB exit (throw/longjmp)
2047	* and will be picked up by the TB execution loop. Only used when
2048	* IEMNATIVE_WITH_INSTRUCTION_COUNTING is defined. */
2049	uint8_t idxTbCurInstr;
2050	/** @} */
2051
2052	/** @name Recompilation
2053	* @{ */
2054	/** Whether we need to check the opcode bytes for the current instruction.
2055	* This is set by a previous instruction if it modified memory or similar. */
2056	bool fTbCheckOpcodes;
2057	/** Indicates whether and how we just branched - IEMBRANCHED_F_XXX. */
2058	uint8_t fTbBranched;
2059	/** Set when GCPhysInstrBuf is updated because of a page crossing. */
2060	bool fTbCrossedPage;
2061	/** Whether to end the current TB. */
2062	bool fEndTb;
2063	/** Indicates that the current instruction is an STI. This is set by the
2064	* iemCImpl_sti code and subsequently cleared by the recompiler. */
2065	bool fTbCurInstrIsSti;
2066	/** Spaced reserved for recompiler data / alignment. */
2067	bool afRecompilerStuff1[1];
2068	/** Number of instructions before we need emit an IRQ check call again.
2069	* This helps making sure we don't execute too long w/o checking for
2070	* interrupts and immediately following instructions that may enable
2071	* interrupts (e.g. POPF, IRET, STI). With STI an additional hack is
2072	* required to make sure we check following the next instruction as well, see
2073	* fTbCurInstrIsSti. */
2074	uint8_t cInstrTillIrqCheck;
2075	/** The index of the last CheckIrq call during threaded recompilation. */
2076	uint16_t idxLastCheckIrqCallNo;
2077	/** The size of the IEMTB::pabOpcodes allocation in pThrdCompileTbR3. */
2078	uint16_t cbOpcodesAllocated;
2079	/** The IEMTB::cUsed value when to attempt native recompilation of a TB. */
2080	uint32_t uTbNativeRecompileAtUsedCount;
2081	/** The IEM_CIMPL_F_XXX mask for the current instruction. */
2082	uint32_t fTbCurInstr;
2083	/** The IEM_CIMPL_F_XXX mask for the previous instruction. */
2084	uint32_t fTbPrevInstr;
2085	/** Strict: Tracking skipped EFLAGS calculations. Any bits set here are
2086	* currently not up to date in EFLAGS. */
2087	uint32_t fSkippingEFlags;
2088	#if 0 /* unused */
2089	/** Previous GCPhysInstrBuf value - only valid if fTbCrossedPage is set. */
2090	RTGCPHYS GCPhysInstrBufPrev;
2091	#endif
2092
2093	/** Fixed TB used for threaded recompilation.
2094	* This is allocated once with maxed-out sizes and re-used afterwards. */
2095	R3PTRTYPE(PIEMTB) pThrdCompileTbR3;
2096	/** Pointer to the ring-3 TB allocator for this EMT. */
2097	R3PTRTYPE(PIEMTBALLOCATOR) pTbAllocatorR3;
2098	/** Pointer to the ring-3 executable memory allocator for this EMT. */
2099	R3PTRTYPE(struct IEMEXECMEMALLOCATOR *) pExecMemAllocatorR3;
2100	/** Pointer to the native recompiler state for ring-3. */
2101	R3PTRTYPE(struct IEMRECOMPILERSTATE *) pNativeRecompilerStateR3;
2102	/** Dummy entry for ppTbLookupEntryR3. */
2103	R3PTRTYPE(PIEMTB) pTbLookupEntryDummyR3;
2104	#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING_DEBUG
2105	/** The debug code advances this register as if it was CPUMCTX::rip and we
2106	* didn't do delayed PC updating. When CPUMCTX::rip is finally updated,
2107	* the result is compared with this value. */
2108	uint64_t uPcUpdatingDebug;
2109	#elif defined(VBOX_WITH_SAVE_THREADED_TBS_FOR_PROFILING)
2110	/** The SSM handle used for saving threaded TBs for recompiler profiling. */
2111	R3PTRTYPE(PSSMHANDLE) pSsmThreadedTbsForProfiling;
2112	#else
2113	uint64_t u64Placeholder;
2114	#endif
2115	/**
2116	* Whether we should use the host instruction invalidation APIs of the
2117	* host OS or our own version of it (macOS). */
2118	uint8_t fHostICacheInvalidation;
2119	#define IEMNATIVE_ICACHE_F_USE_HOST_API UINT8_C(0x01) /*< Use the host API (macOS) instead of our code. /
2120	#define IEMNATIVE_ICACHE_F_END_WITH_ISH UINT8_C(0x02) /*< Whether to end with a ISH barrier (arm). /
2121	bool afRecompilerStuff2[7];
2122	/** @} */
2123
2124	/** Dummy TLB entry used for accesses to pages with databreakpoints. */
2125	IEMTLBENTRY DataBreakpointTlbe;
2126
2127	/** Threaded TB statistics: Times TB execution was broken off before reaching the end. */
2128	STAMCOUNTER StatTbThreadedExecBreaks;
2129	/** Statistics: Times BltIn_CheckIrq breaks out of the TB. */
2130	STAMCOUNTER StatCheckIrqBreaks;
2131	/** Statistics: Times BltIn_CheckTimers breaks direct linking TBs. */
2132	STAMCOUNTER StatCheckTimersBreaks;
2133	/** Statistics: Times BltIn_CheckMode breaks out of the TB. */
2134	STAMCOUNTER StatCheckModeBreaks;
2135	/** Threaded TB statistics: Times execution break on call with lookup entries. */
2136	STAMCOUNTER StatTbThreadedExecBreaksWithLookup;
2137	/** Threaded TB statistics: Times execution break on call without lookup entries. */
2138	STAMCOUNTER StatTbThreadedExecBreaksWithoutLookup;
2139	/** Statistics: Times a post jump target check missed and had to find new TB. */
2140	STAMCOUNTER StatCheckBranchMisses;
2141	/** Statistics: Times a jump or page crossing required a TB with CS.LIM checking. */
2142	STAMCOUNTER StatCheckNeedCsLimChecking;
2143	/** Statistics: Times a loop was detected within a TB. */
2144	STAMCOUNTER StatTbLoopInTbDetected;
2145	/** Statistics: Times a loop back to the start of the TB was detected. */
2146	STAMCOUNTER StatTbLoopFullTbDetected;
2147	/** Statistics: Times a loop back to the start of the TB was detected, var 2. */
2148	STAMCOUNTER StatTbLoopFullTbDetected2;
2149	/** Exec memory allocator statistics: Number of times allocaintg executable memory failed. */
2150	STAMCOUNTER StatNativeExecMemInstrBufAllocFailed;
2151	/** Native TB statistics: Number of fully recompiled TBs. */
2152	STAMCOUNTER StatNativeFullyRecompiledTbs;
2153	/** TB statistics: Number of instructions per TB. */
2154	STAMPROFILE StatTbInstr;
2155	/** TB statistics: Number of TB lookup table entries per TB. */
2156	STAMPROFILE StatTbLookupEntries;
2157	/** Threaded TB statistics: Number of calls per TB. */
2158	STAMPROFILE StatTbThreadedCalls;
2159	/** Native TB statistics: Native code size per TB. */
2160	STAMPROFILE StatTbNativeCode;
2161	/** Native TB statistics: Profiling native recompilation. */
2162	STAMPROFILE StatNativeRecompilation;
2163	/** Native TB statistics: Number of calls per TB that were recompiled properly. */
2164	STAMPROFILE StatNativeCallsRecompiled;
2165	/** Native TB statistics: Number of threaded calls per TB that weren't recompiled. */
2166	STAMPROFILE StatNativeCallsThreaded;
2167	/** Native recompiled execution: TLB hits for data fetches. */
2168	STAMCOUNTER StatNativeTlbHitsForFetch;
2169	/** Native recompiled execution: TLB hits for data stores. */
2170	STAMCOUNTER StatNativeTlbHitsForStore;
2171	/** Native recompiled execution: TLB hits for stack accesses. */
2172	STAMCOUNTER StatNativeTlbHitsForStack;
2173	/** Native recompiled execution: TLB hits for mapped accesses. */
2174	STAMCOUNTER StatNativeTlbHitsForMapped;
2175	/** Native recompiled execution: Code TLB misses for new page. */
2176	STAMCOUNTER StatNativeCodeTlbMissesNewPage;
2177	/** Native recompiled execution: Code TLB hits for new page. */
2178	STAMCOUNTER StatNativeCodeTlbHitsForNewPage;
2179	/** Native recompiled execution: Code TLB misses for new page with offset. */
2180	STAMCOUNTER StatNativeCodeTlbMissesNewPageWithOffset;
2181	/** Native recompiled execution: Code TLB hits for new page with offset. */
2182	STAMCOUNTER StatNativeCodeTlbHitsForNewPageWithOffset;
2183
2184	/** Native recompiler: Number of calls to iemNativeRegAllocFindFree. */
2185	STAMCOUNTER StatNativeRegFindFree;
2186	/** Native recompiler: Number of times iemNativeRegAllocFindFree needed
2187	* to free a variable. */
2188	STAMCOUNTER StatNativeRegFindFreeVar;
2189	/** Native recompiler: Number of times iemNativeRegAllocFindFree did
2190	* not need to free any variables. */
2191	STAMCOUNTER StatNativeRegFindFreeNoVar;
2192	/** Native recompiler: Liveness info freed shadowed guest registers in
2193	* iemNativeRegAllocFindFree. */
2194	STAMCOUNTER StatNativeRegFindFreeLivenessUnshadowed;
2195	/** Native recompiler: Liveness info helped with the allocation in
2196	* iemNativeRegAllocFindFree. */
2197	STAMCOUNTER StatNativeRegFindFreeLivenessHelped;
2198
2199	/** Native recompiler: Number of times status flags calc has been skipped. */
2200	STAMCOUNTER StatNativeEflSkippedArithmetic;
2201	/** Native recompiler: Number of times status flags calc has been postponed. */
2202	STAMCOUNTER StatNativeEflPostponedArithmetic;
2203	/** Native recompiler: Total number instructions in this category. */
2204	STAMCOUNTER StatNativeEflTotalArithmetic;
2205
2206	/** Native recompiler: Number of times status flags calc has been skipped. */
2207	STAMCOUNTER StatNativeEflSkippedLogical;
2208	/** Native recompiler: Number of times status flags calc has been postponed. */
2209	STAMCOUNTER StatNativeEflPostponedLogical;
2210	/** Native recompiler: Total number instructions in this category. */
2211	STAMCOUNTER StatNativeEflTotalLogical;
2212
2213	/** Native recompiler: Number of times status flags calc has been skipped. */
2214	STAMCOUNTER StatNativeEflSkippedShift;
2215	/** Native recompiler: Number of times status flags calc has been postponed. */
2216	STAMCOUNTER StatNativeEflPostponedShift;
2217	/** Native recompiler: Total number instructions in this category. */
2218	STAMCOUNTER StatNativeEflTotalShift;
2219
2220	/** Native recompiler: Number of emits per postponement. */
2221	STAMPROFILE StatNativeEflPostponedEmits;
2222
2223	/** Native recompiler: Number of opportunities to skip EFLAGS.CF updating. */
2224	STAMCOUNTER StatNativeLivenessEflCfSkippable;
2225	/** Native recompiler: Number of opportunities to skip EFLAGS.PF updating. */
2226	STAMCOUNTER StatNativeLivenessEflPfSkippable;
2227	/** Native recompiler: Number of opportunities to skip EFLAGS.AF updating. */
2228	STAMCOUNTER StatNativeLivenessEflAfSkippable;
2229	/** Native recompiler: Number of opportunities to skip EFLAGS.ZF updating. */
2230	STAMCOUNTER StatNativeLivenessEflZfSkippable;
2231	/** Native recompiler: Number of opportunities to skip EFLAGS.SF updating. */
2232	STAMCOUNTER StatNativeLivenessEflSfSkippable;
2233	/** Native recompiler: Number of opportunities to skip EFLAGS.OF updating. */
2234	STAMCOUNTER StatNativeLivenessEflOfSkippable;
2235	/** Native recompiler: Number of required EFLAGS.CF updates. */
2236	STAMCOUNTER StatNativeLivenessEflCfRequired;
2237	/** Native recompiler: Number of required EFLAGS.PF updates. */
2238	STAMCOUNTER StatNativeLivenessEflPfRequired;
2239	/** Native recompiler: Number of required EFLAGS.AF updates. */
2240	STAMCOUNTER StatNativeLivenessEflAfRequired;
2241	/** Native recompiler: Number of required EFLAGS.ZF updates. */
2242	STAMCOUNTER StatNativeLivenessEflZfRequired;
2243	/** Native recompiler: Number of required EFLAGS.SF updates. */
2244	STAMCOUNTER StatNativeLivenessEflSfRequired;
2245	/** Native recompiler: Number of required EFLAGS.OF updates. */
2246	STAMCOUNTER StatNativeLivenessEflOfRequired;
2247	/** Native recompiler: Number of potentially delayable EFLAGS.CF updates. */
2248	STAMCOUNTER StatNativeLivenessEflCfDelayable;
2249	/** Native recompiler: Number of potentially delayable EFLAGS.PF updates. */
2250	STAMCOUNTER StatNativeLivenessEflPfDelayable;
2251	/** Native recompiler: Number of potentially delayable EFLAGS.AF updates. */
2252	STAMCOUNTER StatNativeLivenessEflAfDelayable;
2253	/** Native recompiler: Number of potentially delayable EFLAGS.ZF updates. */
2254	STAMCOUNTER StatNativeLivenessEflZfDelayable;
2255	/** Native recompiler: Number of potentially delayable EFLAGS.SF updates. */
2256	STAMCOUNTER StatNativeLivenessEflSfDelayable;
2257	/** Native recompiler: Number of potentially delayable EFLAGS.OF updates. */
2258	STAMCOUNTER StatNativeLivenessEflOfDelayable;
2259
2260	/** Native recompiler: Number of potential PC updates in total. */
2261	STAMCOUNTER StatNativePcUpdateTotal;
2262	/** Native recompiler: Number of PC updates which could be delayed. */
2263	STAMCOUNTER StatNativePcUpdateDelayed;
2264
2265	/** Native recompiler: Number of time we had complicated dirty shadow
2266	* register situations with the other branch in IEM_MC_ENDIF. */
2267	STAMCOUNTER StatNativeEndIfOtherBranchDirty;
2268
2269	/** Native recompiler: Number of calls to iemNativeSimdRegAllocFindFree. */
2270	STAMCOUNTER StatNativeSimdRegFindFree;
2271	/** Native recompiler: Number of times iemNativeSimdRegAllocFindFree needed
2272	* to free a variable. */
2273	STAMCOUNTER StatNativeSimdRegFindFreeVar;
2274	/** Native recompiler: Number of times iemNativeSimdRegAllocFindFree did
2275	* not need to free any variables. */
2276	STAMCOUNTER StatNativeSimdRegFindFreeNoVar;
2277	/** Native recompiler: Liveness info freed shadowed guest registers in
2278	* iemNativeSimdRegAllocFindFree. */
2279	STAMCOUNTER StatNativeSimdRegFindFreeLivenessUnshadowed;
2280	/** Native recompiler: Liveness info helped with the allocation in
2281	* iemNativeSimdRegAllocFindFree. */
2282	STAMCOUNTER StatNativeSimdRegFindFreeLivenessHelped;
2283
2284	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() checks. */
2285	STAMCOUNTER StatNativeMaybeDeviceNotAvailXcptCheckPotential;
2286	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() checks. */
2287	STAMCOUNTER StatNativeMaybeWaitDeviceNotAvailXcptCheckPotential;
2288	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() checks. */
2289	STAMCOUNTER StatNativeMaybeSseXcptCheckPotential;
2290	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() checks. */
2291	STAMCOUNTER StatNativeMaybeAvxXcptCheckPotential;
2292
2293	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() checks omitted. */
2294	STAMCOUNTER StatNativeMaybeDeviceNotAvailXcptCheckOmitted;
2295	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() checks omitted. */
2296	STAMCOUNTER StatNativeMaybeWaitDeviceNotAvailXcptCheckOmitted;
2297	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() checks omitted. */
2298	STAMCOUNTER StatNativeMaybeSseXcptCheckOmitted;
2299	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() checks omitted. */
2300	STAMCOUNTER StatNativeMaybeAvxXcptCheckOmitted;
2301
2302	/** Native recompiler: The TB finished executing completely without jumping to a an exit label.
2303	* Not availabe in release builds. */
2304	STAMCOUNTER StatNativeTbFinished;
2305	/** Native recompiler: The TB finished executing jumping to the ReturnBreak label. */
2306	STAMCOUNTER StatNativeTbExitReturnBreak;
2307	/** Native recompiler: The TB finished executing jumping to the ReturnBreakFF label. */
2308	STAMCOUNTER StatNativeTbExitReturnBreakFF;
2309	/** Native recompiler: The TB finished executing jumping to the ReturnWithFlags label. */
2310	STAMCOUNTER StatNativeTbExitReturnWithFlags;
2311	/** Native recompiler: The TB finished executing with other non-zero status. */
2312	STAMCOUNTER StatNativeTbExitReturnOtherStatus;
2313	/** Native recompiler: The TB finished executing via throw / long jump. */
2314	STAMCOUNTER StatNativeTbExitLongJump;
2315	/** Native recompiler: The TB finished executing jumping to the ReturnBreak
2316	* label, but directly jumped to the next TB, scenario \#1 w/o IRQ checks. */
2317	STAMCOUNTER StatNativeTbExitDirectLinking1NoIrq;
2318	/** Native recompiler: The TB finished executing jumping to the ReturnBreak
2319	* label, but directly jumped to the next TB, scenario \#1 with IRQ checks. */
2320	STAMCOUNTER StatNativeTbExitDirectLinking1Irq;
2321	/** Native recompiler: The TB finished executing jumping to the ReturnBreak
2322	* label, but directly jumped to the next TB, scenario \#1 w/o IRQ checks. */
2323	STAMCOUNTER StatNativeTbExitDirectLinking2NoIrq;
2324	/** Native recompiler: The TB finished executing jumping to the ReturnBreak
2325	* label, but directly jumped to the next TB, scenario \#2 with IRQ checks. */
2326	STAMCOUNTER StatNativeTbExitDirectLinking2Irq;
2327
2328	/** Native recompiler: The TB finished executing jumping to the RaiseDe label. */
2329	STAMCOUNTER StatNativeTbExitRaiseDe;
2330	/** Native recompiler: The TB finished executing jumping to the RaiseUd label. */
2331	STAMCOUNTER StatNativeTbExitRaiseUd;
2332	/** Native recompiler: The TB finished executing jumping to the RaiseSseRelated label. */
2333	STAMCOUNTER StatNativeTbExitRaiseSseRelated;
2334	/** Native recompiler: The TB finished executing jumping to the RaiseAvxRelated label. */
2335	STAMCOUNTER StatNativeTbExitRaiseAvxRelated;
2336	/** Native recompiler: The TB finished executing jumping to the RaiseSseAvxFpRelated label. */
2337	STAMCOUNTER StatNativeTbExitRaiseSseAvxFpRelated;
2338	/** Native recompiler: The TB finished executing jumping to the RaiseNm label. */
2339	STAMCOUNTER StatNativeTbExitRaiseNm;
2340	/** Native recompiler: The TB finished executing jumping to the RaiseGp0 label. */
2341	STAMCOUNTER StatNativeTbExitRaiseGp0;
2342	/** Native recompiler: The TB finished executing jumping to the RaiseMf label. */
2343	STAMCOUNTER StatNativeTbExitRaiseMf;
2344	/** Native recompiler: The TB finished executing jumping to the RaiseXf label. */
2345	STAMCOUNTER StatNativeTbExitRaiseXf;
2346	/** Native recompiler: The TB finished executing jumping to the ObsoleteTb label. */
2347	STAMCOUNTER StatNativeTbExitObsoleteTb;
2348
2349	/** Native recompiler: Number of full TB loops (jumps from end to start). */
2350	STAMCOUNTER StatNativeTbExitLoopFullTb;
2351
2352	/** Native recompiler: Failure situations with direct linking scenario \#1.
2353	* Counter with StatNativeTbExitReturnBreak. Not in release builds.
2354	* @{ */
2355	STAMCOUNTER StatNativeTbExitDirectLinking1NoTb;
2356	STAMCOUNTER StatNativeTbExitDirectLinking1MismatchGCPhysPc;
2357	STAMCOUNTER StatNativeTbExitDirectLinking1MismatchFlags;
2358	STAMCOUNTER StatNativeTbExitDirectLinking1PendingIrq;
2359	/** @} */
2360
2361	/** Native recompiler: Failure situations with direct linking scenario \#2.
2362	* Counter with StatNativeTbExitReturnBreak. Not in release builds.
2363	* @{ */
2364	STAMCOUNTER StatNativeTbExitDirectLinking2NoTb;
2365	STAMCOUNTER StatNativeTbExitDirectLinking2MismatchGCPhysPc;
2366	STAMCOUNTER StatNativeTbExitDirectLinking2MismatchFlags;
2367	STAMCOUNTER StatNativeTbExitDirectLinking2PendingIrq;
2368	/** @} */
2369
2370	/** iemMemMap and iemMemMapJmp statistics.
2371	* @{ */
2372	STAMCOUNTER StatMemMapJmp;
2373	STAMCOUNTER StatMemMapNoJmp;
2374	STAMCOUNTER StatMemBounceBufferCrossPage;
2375	STAMCOUNTER StatMemBounceBufferMapPhys;
2376	/** @} */
2377
2378	/** Timer polling statistics (debug only).
2379	* @{ */
2380	STAMPROFILE StatTimerPoll;
2381	STAMPROFILE StatTimerPollPoll;
2382	STAMPROFILE StatTimerPollRun;
2383	STAMCOUNTER StatTimerPollUnchanged;
2384	STAMCOUNTER StatTimerPollTiny;
2385	STAMCOUNTER StatTimerPollDefaultCalc;
2386	STAMCOUNTER StatTimerPollMax;
2387	STAMPROFILE StatTimerPollFactorDivision;
2388	STAMPROFILE StatTimerPollFactorMultiplication;
2389	/** @} */
2390
2391
2392	STAMCOUNTER aStatAdHoc[8];
2393
2394	#ifdef IEM_WITH_TLB_TRACE
2395	/uint64_t au64Padding[0];/
2396	#else
2397	uint64_t au64Padding[2];
2398	#endif
2399
2400	#ifdef IEM_WITH_TLB_TRACE
2401	/** The end (next) trace entry. */
2402	uint32_t idxTlbTraceEntry;
2403	/** Number of trace entries allocated expressed as a power of two. */
2404	uint32_t cTlbTraceEntriesShift;
2405	/** The trace entries. */
2406	PIEMTLBTRACEENTRY paTlbTraceEntries;
2407	#endif
2408
2409	/** Data TLB.
2410	* @remarks Must be 64-byte aligned. */
2411	IEMTLB DataTlb;
2412	/** Instruction TLB.
2413	* @remarks Must be 64-byte aligned. */
2414	IEMTLB CodeTlb;
2415
2416	/** Exception statistics. */
2417	STAMCOUNTER aStatXcpts[32];
2418	/** Interrupt statistics. */
2419	uint32_t aStatInts[256];
2420
2421	#if defined(VBOX_WITH_STATISTICS) && !defined(DOXYGEN_RUNNING) && !defined(IEM_WITHOUT_INSTRUCTION_STATS)
2422	/** Instruction statistics for ring-0/raw-mode. */
2423	IEMINSTRSTATS StatsRZ;
2424	/** Instruction statistics for ring-3. */
2425	IEMINSTRSTATS StatsR3;
2426	# ifdef VBOX_WITH_IEM_RECOMPILER
2427	/** Statistics per threaded function call.
2428	* Updated by both the threaded and native recompilers. */
2429	uint32_t acThreadedFuncStats[0x6000 /24576/];
2430	# endif
2431	#endif
2432	} IEMCPU;
2433	AssertCompileMemberOffset(IEMCPU, cActiveMappings, 0x4f);
2434	AssertCompileMemberAlignment(IEMCPU, aMemMappings, 16);
2435	AssertCompileMemberAlignment(IEMCPU, aMemMappingLocks, 16);
2436	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 64);
2437	AssertCompileMemberAlignment(IEMCPU, pCurTbR3, 64);
2438	AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
2439	AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
2440
2441	/** Pointer to the per-CPU IEM state. */
2442	typedef IEMCPU *PIEMCPU;
2443	/** Pointer to the const per-CPU IEM state. */
2444	typedef IEMCPU const *PCIEMCPU;
2445
2446	/** @def IEMNATIVE_SIMD_FP_CTRL_REG_NOT_MODIFIED
2447	* Value indicating the TB didn't modified the floating point control register.
2448	* @note Neither FPCR nor MXCSR accept this as a valid value (MXCSR is not fully populated,
2449	* FPCR has the upper 32-bit reserved), so this is safe. */
2450	#if defined(IEMNATIVE_WITH_SIMD_FP_NATIVE_EMITTERS) \|\| defined(DOXYGEN_RUNNING)
2451	# ifdef RT_ARCH_AMD64
2452	# define IEMNATIVE_SIMD_FP_CTRL_REG_NOT_MODIFIED UINT32_MAX
2453	# elif defined(RT_ARCH_ARM64)
2454	# define IEMNATIVE_SIMD_FP_CTRL_REG_NOT_MODIFIED UINT64_MAX
2455	# else
2456	# error "Port me"
2457	# endif
2458	#endif
2459
2460	/** @def IEM_GET_CTX
2461	* Gets the guest CPU context for the calling EMT.
2462	* @returns PCPUMCTX
2463	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2464	*/
2465	#define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
2466
2467	/** @def IEM_CTX_ASSERT
2468	* Asserts that the @a a_fExtrnMbz is present in the CPU context.
2469	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2470	* @param a_fExtrnMbz The mask of CPUMCTX_EXTRN_XXX flags that must be zero.
2471	*/
2472	#define IEM_CTX_ASSERT(a_pVCpu, a_fExtrnMbz) \
2473	AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
2474	("fExtrn=%#RX64 & fExtrnMbz=%#RX64 -> %#RX64\n", \
2475	(a_pVCpu)->cpum.GstCtx.fExtrn, (a_fExtrnMbz), (a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz) ))
2476
2477	/** @def IEM_CTX_IMPORT_RET
2478	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
2479	*
2480	* Will call the keep to import the bits as needed.
2481	*
2482	* Returns on import failure.
2483	*
2484	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2485	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
2486	*/
2487	#define IEM_CTX_IMPORT_RET(a_pVCpu, a_fExtrnImport) \
2488	do { \
2489	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
2490	{ /* likely */ } \
2491	else \
2492	{ \
2493	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
2494	AssertRCReturn(rcCtxImport, rcCtxImport); \
2495	} \
2496	} while (0)
2497
2498	/** @def IEM_CTX_IMPORT_NORET
2499	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
2500	*
2501	* Will call the keep to import the bits as needed.
2502	*
2503	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2504	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
2505	*/
2506	#define IEM_CTX_IMPORT_NORET(a_pVCpu, a_fExtrnImport) \
2507	do { \
2508	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
2509	{ /* likely */ } \
2510	else \
2511	{ \
2512	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
2513	AssertLogRelRC(rcCtxImport); \
2514	} \
2515	} while (0)
2516
2517	/** @def IEM_CTX_IMPORT_JMP
2518	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
2519	*
2520	* Will call the keep to import the bits as needed.
2521	*
2522	* Jumps on import failure.
2523	*
2524	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2525	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
2526	*/
2527	#define IEM_CTX_IMPORT_JMP(a_pVCpu, a_fExtrnImport) \
2528	do { \
2529	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
2530	{ /* likely */ } \
2531	else \
2532	{ \
2533	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
2534	AssertRCStmt(rcCtxImport, IEM_DO_LONGJMP(pVCpu, rcCtxImport)); \
2535	} \
2536	} while (0)
2537
2538
2539
2540	/** @def IEM_GET_TARGET_CPU
2541	* Gets the current IEMTARGETCPU value.
2542	* @returns IEMTARGETCPU value.
2543	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2544	*/
2545	#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
2546	# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
2547	#else
2548	# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
2549	#endif
2550
2551	/** @def IEM_GET_INSTR_LEN
2552	* Gets the instruction length. */
2553	#ifdef IEM_WITH_CODE_TLB
2554	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
2555	#else
2556	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
2557	#endif
2558
2559	/** @def IEM_TRY_SETJMP
2560	* Wrapper around setjmp / try, hiding all the ugly differences.
2561	*
2562	* @note Use with extreme care as this is a fragile macro.
2563	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2564	* @param a_rcTarget The variable that should receive the status code in case
2565	* of a longjmp/throw.
2566	*/
2567	/** @def IEM_TRY_SETJMP_AGAIN
2568	* For when setjmp / try is used again in the same variable scope as a previous
2569	* IEM_TRY_SETJMP invocation.
2570	*/
2571	/** @def IEM_CATCH_LONGJMP_BEGIN
2572	* Start wrapper for catch / setjmp-else.
2573	*
2574	* This will set up a scope.
2575	*
2576	* @note Use with extreme care as this is a fragile macro.
2577	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2578	* @param a_rcTarget The variable that should receive the status code in case
2579	* of a longjmp/throw.
2580	*/
2581	/** @def IEM_CATCH_LONGJMP_END
2582	* End wrapper for catch / setjmp-else.
2583	*
2584	* This will close the scope set up by IEM_CATCH_LONGJMP_BEGIN and clean up the
2585	* state.
2586	*
2587	* @note Use with extreme care as this is a fragile macro.
2588	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2589	*/
2590	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
2591	# ifdef IEM_WITH_THROW_CATCH
2592	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
2593	a_rcTarget = VINF_SUCCESS; \
2594	try
2595	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
2596	IEM_TRY_SETJMP(a_pVCpu, a_rcTarget)
2597	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
2598	catch (int rcThrown) \
2599	{ \
2600	a_rcTarget = rcThrown
2601	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
2602	} \
2603	((void)0)
2604	# else /* !IEM_WITH_THROW_CATCH */
2605	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
2606	jmp_buf JmpBuf; \
2607	jmp_buf * volatile pSavedJmpBuf = (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf); \
2608	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
2609	if ((rcStrict = setjmp(JmpBuf)) == 0)
2610	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
2611	pSavedJmpBuf = (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf); \
2612	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
2613	if ((rcStrict = setjmp(JmpBuf)) == 0)
2614	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
2615	else \
2616	{ \
2617	((void)0)
2618	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
2619	} \
2620	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = pSavedJmpBuf
2621	# endif /* !IEM_WITH_THROW_CATCH */
2622	#endif /* IEM_WITH_SETJMP */
2623
2624
2625	/**
2626	* Shared per-VM IEM data.
2627	*/
2628	typedef struct IEM
2629	{
2630	/** The VMX APIC-access page handler type. */
2631	PGMPHYSHANDLERTYPE hVmxApicAccessPage;
2632	#ifndef VBOX_WITHOUT_CPUID_HOST_CALL
2633	/** Set if the CPUID host call functionality is enabled. */
2634	bool fCpuIdHostCall;
2635	#endif
2636	} IEM;
2637
2638
2639
2640	/** @name IEM_ACCESS_XXX - Access details.
2641	* @{ */
2642	#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
2643	#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
2644	#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
2645	#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
2646	#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
2647	#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
2648	#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
2649	#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
2650	#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
2651	#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
2652	/** The writes are partial, so if initialize the bounce buffer with the
2653	* orignal RAM content. */
2654	#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
2655	/** Used in aMemMappings to indicate that the entry is bounce buffered. */
2656	#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
2657	/** Bounce buffer with ring-3 write pending, first page. */
2658	#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
2659	/** Bounce buffer with ring-3 write pending, second page. */
2660	#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
2661	/** Not locked, accessed via the TLB. */
2662	#define IEM_ACCESS_NOT_LOCKED UINT32_C(0x00001000)
2663	/** Atomic access.
2664	* This enables special alignment checks and the VINF_EM_EMULATE_SPLIT_LOCK
2665	* fallback for misaligned stuff. See @bugref{10547}. */
2666	#define IEM_ACCESS_ATOMIC UINT32_C(0x00002000)
2667	/** Valid bit mask. */
2668	#define IEM_ACCESS_VALID_MASK UINT32_C(0x00003fff)
2669	/** Shift count for the TLB flags (upper word). */
2670	#define IEM_ACCESS_SHIFT_TLB_FLAGS 16
2671
2672	/** Atomic read+write data alias. */
2673	#define IEM_ACCESS_DATA_ATOMIC (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA \| IEM_ACCESS_ATOMIC)
2674	/** Read+write data alias. */
2675	#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
2676	/** Write data alias. */
2677	#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
2678	/** Read data alias. */
2679	#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_DATA)
2680	/** Instruction fetch alias. */
2681	#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_WHAT_CODE)
2682	/** Stack write alias. */
2683	#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
2684	/** Stack read alias. */
2685	#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_STACK)
2686	/** Stack read+write alias. */
2687	#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
2688	/** Read system table alias. */
2689	#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_SYS)
2690	/** Read+write system table alias. */
2691	#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_SYS)
2692	/** @} */
2693
2694	/** @name Prefix constants (IEMCPU::fPrefixes)
2695	* @{ */
2696	#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /*< CS segment prefix (0x2e). /
2697	#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /*< SS segment prefix (0x36). /
2698	#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /*< DS segment prefix (0x3e). /
2699	#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /*< ES segment prefix (0x26). /
2700	#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /*< FS segment prefix (0x64). /
2701	#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /*< GS segment prefix (0x65). /
2702	#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
2703
2704	#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /*< Operand size prefix (0x66). /
2705	#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /*< REX.W prefix (0x48-0x4f). /
2706	#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /*< Address size prefix (0x67). /
2707
2708	#define IEM_OP_PRF_LOCK RT_BIT_32(16) /*< Lock prefix (0xf0). /
2709	#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /*< Repeat-not-zero prefix (0xf2). /
2710	#define IEM_OP_PRF_REPZ RT_BIT_32(18) /*< Repeat-if-zero prefix (0xf3). /
2711
2712	#define IEM_OP_PRF_REX RT_BIT_32(24) /*< Any REX prefix (0x40-0x4f). /
2713	#define IEM_OP_PRF_REX_B RT_BIT_32(25) /*< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). /
2714	#define IEM_OP_PRF_REX_X RT_BIT_32(26) /*< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). /
2715	#define IEM_OP_PRF_REX_R RT_BIT_32(27) /*< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). /
2716	/** Mask with all the REX prefix flags.
2717	* This is generally for use when needing to undo the REX prefixes when they
2718	* are followed legacy prefixes and therefore does not immediately preceed
2719	* the first opcode byte.
2720	* For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
2721	#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX \| IEM_OP_PRF_REX_R \| IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X \| IEM_OP_PRF_SIZE_REX_W )
2722
2723	#define IEM_OP_PRF_VEX RT_BIT_32(28) /*< Indiciates VEX prefix. /
2724	#define IEM_OP_PRF_EVEX RT_BIT_32(29) /*< Indiciates EVEX prefix. /
2725	#define IEM_OP_PRF_XOP RT_BIT_32(30) /*< Indiciates XOP prefix. /
2726	/** @} */
2727
2728	/** @name IEMOPFORM_XXX - Opcode forms
2729	* @note These are ORed together with IEMOPHINT_XXX.
2730	* @{ */
2731	/** ModR/M: reg, r/m */
2732	#define IEMOPFORM_RM 0
2733	/** ModR/M: reg, r/m (register) */
2734	#define IEMOPFORM_RM_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
2735	/** ModR/M: reg, r/m (memory) */
2736	#define IEMOPFORM_RM_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
2737	/** ModR/M: reg, r/m, imm */
2738	#define IEMOPFORM_RMI 1
2739	/** ModR/M: reg, r/m (register), imm */
2740	#define IEMOPFORM_RMI_REG (IEMOPFORM_RMI \| IEMOPFORM_MOD3)
2741	/** ModR/M: reg, r/m (memory), imm */
2742	#define IEMOPFORM_RMI_MEM (IEMOPFORM_RMI \| IEMOPFORM_NOT_MOD3)
2743	/** ModR/M: reg, r/m, xmm0 */
2744	#define IEMOPFORM_RM0 2
2745	/** ModR/M: reg, r/m (register), xmm0 */
2746	#define IEMOPFORM_RM0_REG (IEMOPFORM_RM0 \| IEMOPFORM_MOD3)
2747	/** ModR/M: reg, r/m (memory), xmm0 */
2748	#define IEMOPFORM_RM0_MEM (IEMOPFORM_RM0 \| IEMOPFORM_NOT_MOD3)
2749	/** ModR/M: r/m, reg */
2750	#define IEMOPFORM_MR 3
2751	/** ModR/M: r/m (register), reg */
2752	#define IEMOPFORM_MR_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
2753	/** ModR/M: r/m (memory), reg */
2754	#define IEMOPFORM_MR_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
2755	/** ModR/M: r/m, reg, imm */
2756	#define IEMOPFORM_MRI 4
2757	/** ModR/M: r/m (register), reg, imm */
2758	#define IEMOPFORM_MRI_REG (IEMOPFORM_MRI \| IEMOPFORM_MOD3)
2759	/** ModR/M: r/m (memory), reg, imm */
2760	#define IEMOPFORM_MRI_MEM (IEMOPFORM_MRI \| IEMOPFORM_NOT_MOD3)
2761	/** ModR/M: r/m only */
2762	#define IEMOPFORM_M 5
2763	/** ModR/M: r/m only (register). */
2764	#define IEMOPFORM_M_REG (IEMOPFORM_M \| IEMOPFORM_MOD3)
2765	/** ModR/M: r/m only (memory). */
2766	#define IEMOPFORM_M_MEM (IEMOPFORM_M \| IEMOPFORM_NOT_MOD3)
2767	/** ModR/M: r/m, imm */
2768	#define IEMOPFORM_MI 6
2769	/** ModR/M: r/m (register), imm */
2770	#define IEMOPFORM_MI_REG (IEMOPFORM_MI \| IEMOPFORM_MOD3)
2771	/** ModR/M: r/m (memory), imm */
2772	#define IEMOPFORM_MI_MEM (IEMOPFORM_MI \| IEMOPFORM_NOT_MOD3)
2773	/** ModR/M: r/m, 1 (shift and rotate instructions) */
2774	#define IEMOPFORM_M1 7
2775	/** ModR/M: r/m (register), 1. */
2776	#define IEMOPFORM_M1_REG (IEMOPFORM_M1 \| IEMOPFORM_MOD3)
2777	/** ModR/M: r/m (memory), 1. */
2778	#define IEMOPFORM_M1_MEM (IEMOPFORM_M1 \| IEMOPFORM_NOT_MOD3)
2779	/** ModR/M: r/m, CL (shift and rotate instructions)
2780	* @todo This should just've been a generic fixed register. But the python
2781	* code doesn't needs more convincing. */
2782	#define IEMOPFORM_M_CL 8
2783	/** ModR/M: r/m (register), CL. */
2784	#define IEMOPFORM_M_CL_REG (IEMOPFORM_M_CL \| IEMOPFORM_MOD3)
2785	/** ModR/M: r/m (memory), CL. */
2786	#define IEMOPFORM_M_CL_MEM (IEMOPFORM_M_CL \| IEMOPFORM_NOT_MOD3)
2787	/** ModR/M: reg only */
2788	#define IEMOPFORM_R 9
2789
2790	/** VEX+ModR/M: reg, r/m */
2791	#define IEMOPFORM_VEX_RM 16
2792	/** VEX+ModR/M: reg, r/m (register) */
2793	#define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM \| IEMOPFORM_MOD3)
2794	/** VEX+ModR/M: reg, r/m (memory) */
2795	#define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM \| IEMOPFORM_NOT_MOD3)
2796	/** VEX+ModR/M: r/m, reg */
2797	#define IEMOPFORM_VEX_MR 17
2798	/** VEX+ModR/M: r/m (register), reg */
2799	#define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR \| IEMOPFORM_MOD3)
2800	/** VEX+ModR/M: r/m (memory), reg */
2801	#define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR \| IEMOPFORM_NOT_MOD3)
2802	/** VEX+ModR/M: r/m, reg, imm8 */
2803	#define IEMOPFORM_VEX_MRI 18
2804	/** VEX+ModR/M: r/m (register), reg, imm8 */
2805	#define IEMOPFORM_VEX_MRI_REG (IEMOPFORM_VEX_MRI \| IEMOPFORM_MOD3)
2806	/** VEX+ModR/M: r/m (memory), reg, imm8 */
2807	#define IEMOPFORM_VEX_MRI_MEM (IEMOPFORM_VEX_MRI \| IEMOPFORM_NOT_MOD3)
2808	/** VEX+ModR/M: r/m only */
2809	#define IEMOPFORM_VEX_M 19
2810	/** VEX+ModR/M: r/m only (register). */
2811	#define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M \| IEMOPFORM_MOD3)
2812	/** VEX+ModR/M: r/m only (memory). */
2813	#define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M \| IEMOPFORM_NOT_MOD3)
2814	/** VEX+ModR/M: reg only */
2815	#define IEMOPFORM_VEX_R 20
2816	/** VEX+ModR/M: reg, vvvv, r/m */
2817	#define IEMOPFORM_VEX_RVM 21
2818	/** VEX+ModR/M: reg, vvvv, r/m (register). */
2819	#define IEMOPFORM_VEX_RVM_REG (IEMOPFORM_VEX_RVM \| IEMOPFORM_MOD3)
2820	/** VEX+ModR/M: reg, vvvv, r/m (memory). */
2821	#define IEMOPFORM_VEX_RVM_MEM (IEMOPFORM_VEX_RVM \| IEMOPFORM_NOT_MOD3)
2822	/** VEX+ModR/M: reg, vvvv, r/m, imm */
2823	#define IEMOPFORM_VEX_RVMI 22
2824	/** VEX+ModR/M: reg, vvvv, r/m (register), imm. */
2825	#define IEMOPFORM_VEX_RVMI_REG (IEMOPFORM_VEX_RVMI \| IEMOPFORM_MOD3)
2826	/** VEX+ModR/M: reg, vvvv, r/m (memory), imm. */
2827	#define IEMOPFORM_VEX_RVMI_MEM (IEMOPFORM_VEX_RVMI \| IEMOPFORM_NOT_MOD3)
2828	/** VEX+ModR/M: reg, vvvv, r/m, imm(reg) */
2829	#define IEMOPFORM_VEX_RVMR 23
2830	/** VEX+ModR/M: reg, vvvv, r/m (register), imm(reg). */
2831	#define IEMOPFORM_VEX_RVMR_REG (IEMOPFORM_VEX_RVMI \| IEMOPFORM_MOD3)
2832	/** VEX+ModR/M: reg, vvvv, r/m (memory), imm(reg). */
2833	#define IEMOPFORM_VEX_RVMR_MEM (IEMOPFORM_VEX_RVMI \| IEMOPFORM_NOT_MOD3)
2834	/** VEX+ModR/M: reg, r/m, vvvv */
2835	#define IEMOPFORM_VEX_RMV 24
2836	/** VEX+ModR/M: reg, r/m, vvvv (register). */
2837	#define IEMOPFORM_VEX_RMV_REG (IEMOPFORM_VEX_RMV \| IEMOPFORM_MOD3)
2838	/** VEX+ModR/M: reg, r/m, vvvv (memory). */
2839	#define IEMOPFORM_VEX_RMV_MEM (IEMOPFORM_VEX_RMV \| IEMOPFORM_NOT_MOD3)
2840	/** VEX+ModR/M: reg, r/m, imm8 */
2841	#define IEMOPFORM_VEX_RMI 25
2842	/** VEX+ModR/M: reg, r/m, imm8 (register). */
2843	#define IEMOPFORM_VEX_RMI_REG (IEMOPFORM_VEX_RMI \| IEMOPFORM_MOD3)
2844	/** VEX+ModR/M: reg, r/m, imm8 (memory). */
2845	#define IEMOPFORM_VEX_RMI_MEM (IEMOPFORM_VEX_RMI \| IEMOPFORM_NOT_MOD3)
2846	/** VEX+ModR/M: r/m, vvvv, reg */
2847	#define IEMOPFORM_VEX_MVR 26
2848	/** VEX+ModR/M: r/m, vvvv, reg (register) */
2849	#define IEMOPFORM_VEX_MVR_REG (IEMOPFORM_VEX_MVR \| IEMOPFORM_MOD3)
2850	/** VEX+ModR/M: r/m, vvvv, reg (memory) */
2851	#define IEMOPFORM_VEX_MVR_MEM (IEMOPFORM_VEX_MVR \| IEMOPFORM_NOT_MOD3)
2852	/** VEX+ModR/M+/n: vvvv, r/m */
2853	#define IEMOPFORM_VEX_VM 27
2854	/** VEX+ModR/M+/n: vvvv, r/m (register) */
2855	#define IEMOPFORM_VEX_VM_REG (IEMOPFORM_VEX_VM \| IEMOPFORM_MOD3)
2856	/** VEX+ModR/M+/n: vvvv, r/m (memory) */
2857	#define IEMOPFORM_VEX_VM_MEM (IEMOPFORM_VEX_VM \| IEMOPFORM_NOT_MOD3)
2858	/** VEX+ModR/M+/n: vvvv, r/m, imm8 */
2859	#define IEMOPFORM_VEX_VMI 28
2860	/** VEX+ModR/M+/n: vvvv, r/m, imm8 (register) */
2861	#define IEMOPFORM_VEX_VMI_REG (IEMOPFORM_VEX_VMI \| IEMOPFORM_MOD3)
2862	/** VEX+ModR/M+/n: vvvv, r/m, imm8 (memory) */
2863	#define IEMOPFORM_VEX_VMI_MEM (IEMOPFORM_VEX_VMI \| IEMOPFORM_NOT_MOD3)
2864
2865	/** Fixed register instruction, no R/M. */
2866	#define IEMOPFORM_FIXED 32
2867
2868	/** The r/m is a register. */
2869	#define IEMOPFORM_MOD3 RT_BIT_32(8)
2870	/** The r/m is a memory access. */
2871	#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
2872	/** @} */
2873
2874	/** @name IEMOPHINT_XXX - Additional Opcode Hints
2875	* @note These are ORed together with IEMOPFORM_XXX.
2876	* @{ */
2877	/** Ignores the operand size prefix (66h). */
2878	#define IEMOPHINT_IGNORES_OZ_PFX RT_BIT_32(10)
2879	/** Ignores REX.W (aka WIG). */
2880	#define IEMOPHINT_IGNORES_REXW RT_BIT_32(11)
2881	/** Both the operand size prefixes (66h + REX.W) are ignored. */
2882	#define IEMOPHINT_IGNORES_OP_SIZES (IEMOPHINT_IGNORES_OZ_PFX \| IEMOPHINT_IGNORES_REXW)
2883	/** Allowed with the lock prefix. */
2884	#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
2885	/** The VEX.L value is ignored (aka LIG). */
2886	#define IEMOPHINT_VEX_L_IGNORED RT_BIT_32(12)
2887	/** The VEX.L value must be zero (i.e. 128-bit width only). */
2888	#define IEMOPHINT_VEX_L_ZERO RT_BIT_32(13)
2889	/** The VEX.L value must be one (i.e. 256-bit width only). */
2890	#define IEMOPHINT_VEX_L_ONE RT_BIT_32(14)
2891	/** The VEX.V value must be zero. */
2892	#define IEMOPHINT_VEX_V_ZERO RT_BIT_32(15)
2893	/** The REX.W/VEX.V value must be zero. */
2894	#define IEMOPHINT_REX_W_ZERO RT_BIT_32(16)
2895	#define IEMOPHINT_VEX_W_ZERO IEMOPHINT_REX_W_ZERO
2896	/** The REX.W/VEX.V value must be one. */
2897	#define IEMOPHINT_REX_W_ONE RT_BIT_32(17)
2898	#define IEMOPHINT_VEX_W_ONE IEMOPHINT_REX_W_ONE
2899
2900	/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
2901	#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
2902	/** @} */
2903
2904	/**
2905	* Possible hardware task switch sources.
2906	*/
2907	typedef enum IEMTASKSWITCH
2908	{
2909	/** Task switch caused by an interrupt/exception. */
2910	IEMTASKSWITCH_INT_XCPT = 1,
2911	/** Task switch caused by a far CALL. */
2912	IEMTASKSWITCH_CALL,
2913	/** Task switch caused by a far JMP. */
2914	IEMTASKSWITCH_JUMP,
2915	/** Task switch caused by an IRET. */
2916	IEMTASKSWITCH_IRET
2917	} IEMTASKSWITCH;
2918	AssertCompileSize(IEMTASKSWITCH, 4);
2919
2920	/**
2921	* Possible CrX load (write) sources.
2922	*/
2923	typedef enum IEMACCESSCRX
2924	{
2925	/** CrX access caused by 'mov crX' instruction. */
2926	IEMACCESSCRX_MOV_CRX,
2927	/** CrX (CR0) write caused by 'lmsw' instruction. */
2928	IEMACCESSCRX_LMSW,
2929	/** CrX (CR0) write caused by 'clts' instruction. */
2930	IEMACCESSCRX_CLTS,
2931	/** CrX (CR0) read caused by 'smsw' instruction. */
2932	IEMACCESSCRX_SMSW
2933	} IEMACCESSCRX;
2934
2935	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2936	/** @name IEM_SLAT_FAIL_XXX - Second-level address translation failure information.
2937	*
2938	* These flags provide further context to SLAT page-walk failures that could not be
2939	* determined by PGM (e.g, PGM is not privy to memory access permissions).
2940	*
2941	* @{
2942	*/
2943	/** Translating a nested-guest linear address failed accessing a nested-guest
2944	* physical address. */
2945	# define IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR RT_BIT_32(0)
2946	/** Translating a nested-guest linear address failed accessing a
2947	* paging-structure entry or updating accessed/dirty bits. */
2948	# define IEM_SLAT_FAIL_LINEAR_TO_PAGE_TABLE RT_BIT_32(1)
2949	/** @} */
2950
2951	DECLCALLBACK(FNPGMPHYSHANDLER) iemVmxApicAccessPageHandler;
2952	# ifndef IN_RING3
2953	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) iemVmxApicAccessPagePfHandler;
2954	# endif
2955	#endif
2956
2957	/**
2958	* Indicates to the verifier that the given flag set is undefined.
2959	*
2960	* Can be invoked again to add more flags.
2961	*
2962	* This is a NOOP if the verifier isn't compiled in.
2963	*
2964	* @note We're temporarily keeping this until code is converted to new
2965	* disassembler style opcode handling.
2966	*/
2967	#define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
2968
2969
2970	/** @def IEM_DECL_MSC_GUARD_IGNORE
2971	* Disables control flow guards checks inside a method and any function pointers
2972	* referenced by it. */
2973	#if defined(_MSC_VER) && !defined(IN_RING0)
2974	# define IEM_DECL_MSC_GUARD_IGNORE __declspec(guard(ignore))
2975	#else
2976	# define IEM_DECL_MSC_GUARD_IGNORE
2977	#endif
2978
2979	/** @def IEM_DECL_MSC_GUARD_NONE
2980	* Disables control flow guards checks inside a method and but continue track
2981	* function pointers references by it. */
2982	#if defined(_MSC_VER) && !defined(IN_RING0)
2983	# define IEM_DECL_MSC_GUARD_NONE __declspec(guard(nocf))
2984	#else
2985	# define IEM_DECL_MSC_GUARD_NONE
2986	#endif
2987
2988
2989	/** @def IEM_DECL_IMPL_TYPE
2990	* For typedef'ing an instruction implementation function.
2991	*
2992	* @param a_RetType The return type.
2993	* @param a_Name The name of the type.
2994	* @param a_ArgList The argument list enclosed in parentheses.
2995	*/
2996
2997	/** @def IEM_DECL_IMPL_DEF
2998	* For defining an instruction implementation function.
2999	*
3000	* @param a_RetType The return type.
3001	* @param a_Name The name of the type.
3002	* @param a_ArgList The argument list enclosed in parentheses.
3003	*/
3004
3005	#if defined(__GNUC__) && defined(RT_ARCH_X86)
3006	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
3007	__attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
3008	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
3009	__attribute__((__fastcall__, __nothrow__)) DECL_HIDDEN_ONLY(a_RetType) a_Name a_ArgList
3010	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
3011	__attribute__((__fastcall__, __nothrow__)) DECL_HIDDEN_ONLY(a_RetType) a_Name a_ArgList
3012
3013	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
3014	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
3015	a_RetType (__fastcall a_Name) a_ArgList
3016	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
3017	IEM_DECL_MSC_GUARD_IGNORE a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
3018	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
3019	IEM_DECL_MSC_GUARD_IGNORE a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
3020
3021	#elif __cplusplus >= 201700 /* P0012R1 support */
3022	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
3023	a_RetType (VBOXCALL a_Name) a_ArgList RT_NOEXCEPT
3024	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
3025	IEM_DECL_MSC_GUARD_IGNORE DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList RT_NOEXCEPT
3026	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
3027	IEM_DECL_MSC_GUARD_IGNORE DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList RT_NOEXCEPT
3028
3029	#else
3030	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
3031	a_RetType (VBOXCALL a_Name) a_ArgList
3032	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
3033	IEM_DECL_MSC_GUARD_IGNORE DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList
3034	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
3035	IEM_DECL_MSC_GUARD_IGNORE DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList
3036
3037	#endif
3038
3039	/** Defined in IEMAllAImplC.cpp but also used by IEMAllAImplA.asm. */
3040	RT_C_DECLS_BEGIN
3041	extern uint8_t const g_afParity[256];
3042	RT_C_DECLS_END
3043
3044
3045	/** @name Arithmetic assignment operations on bytes (binary).
3046	* @{ */
3047	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU8, (uint32_t fEFlagsIn, uint8_t *pu8Dst, uint8_t u8Src));
3048	typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
3049	FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
3050	FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
3051	FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
3052	FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
3053	FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
3054	FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
3055	FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
3056	/** @} */
3057
3058	/** @name Arithmetic assignment operations on words (binary).
3059	* @{ */
3060	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU16, (uint32_t fEFlagsIn, uint16_t *pu16Dst, uint16_t u16Src));
3061	typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
3062	FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
3063	FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
3064	FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
3065	FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
3066	FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
3067	FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
3068	FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
3069	/** @} */
3070
3071
3072	/** @name Arithmetic assignment operations on double words (binary).
3073	* @{ */
3074	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU32, (uint32_t fEFlagsIn, uint32_t *pu32Dst, uint32_t u32Src));
3075	typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
3076	FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
3077	FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
3078	FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
3079	FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
3080	FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
3081	FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
3082	FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
3083	FNIEMAIMPLBINU32 iemAImpl_blsi_u32, iemAImpl_blsi_u32_fallback;
3084	FNIEMAIMPLBINU32 iemAImpl_blsr_u32, iemAImpl_blsr_u32_fallback;
3085	FNIEMAIMPLBINU32 iemAImpl_blsmsk_u32, iemAImpl_blsmsk_u32_fallback;
3086	/** @} */
3087
3088	/** @name Arithmetic assignment operations on quad words (binary).
3089	* @{ */
3090	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU64, (uint32_t fEFlagsIn, uint64_t *pu64Dst, uint64_t u64Src));
3091	typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
3092	FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
3093	FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
3094	FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
3095	FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
3096	FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
3097	FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
3098	FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
3099	FNIEMAIMPLBINU64 iemAImpl_blsi_u64, iemAImpl_blsi_u64_fallback;
3100	FNIEMAIMPLBINU64 iemAImpl_blsr_u64, iemAImpl_blsr_u64_fallback;
3101	FNIEMAIMPLBINU64 iemAImpl_blsmsk_u64, iemAImpl_blsmsk_u64_fallback;
3102	/** @} */
3103
3104	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU8, (uint32_t fEFlagsIn, uint8_t const *pu8Dst, uint8_t u8Src));
3105	typedef FNIEMAIMPLBINROU8 *PFNIEMAIMPLBINROU8;
3106	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU16,(uint32_t fEFlagsIn, uint16_t const *pu16Dst, uint16_t u16Src));
3107	typedef FNIEMAIMPLBINROU16 *PFNIEMAIMPLBINROU16;
3108	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU32,(uint32_t fEFlagsIn, uint32_t const *pu32Dst, uint32_t u32Src));
3109	typedef FNIEMAIMPLBINROU32 *PFNIEMAIMPLBINROU32;
3110	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU64,(uint32_t fEFlagsIn, uint64_t const *pu64Dst, uint64_t u64Src));
3111	typedef FNIEMAIMPLBINROU64 *PFNIEMAIMPLBINROU64;
3112
3113	/** @name Compare operations (thrown in with the binary ops).
3114	* @{ */
3115	FNIEMAIMPLBINROU8 iemAImpl_cmp_u8;
3116	FNIEMAIMPLBINROU16 iemAImpl_cmp_u16;
3117	FNIEMAIMPLBINROU32 iemAImpl_cmp_u32;
3118	FNIEMAIMPLBINROU64 iemAImpl_cmp_u64;
3119	/** @} */
3120
3121	/** @name Test operations (thrown in with the binary ops).
3122	* @{ */
3123	FNIEMAIMPLBINROU8 iemAImpl_test_u8;
3124	FNIEMAIMPLBINROU16 iemAImpl_test_u16;
3125	FNIEMAIMPLBINROU32 iemAImpl_test_u32;
3126	FNIEMAIMPLBINROU64 iemAImpl_test_u64;
3127	/** @} */
3128
3129	/** @name Bit operations operations (thrown in with the binary ops).
3130	* @{ */
3131	FNIEMAIMPLBINROU16 iemAImpl_bt_u16;
3132	FNIEMAIMPLBINROU32 iemAImpl_bt_u32;
3133	FNIEMAIMPLBINROU64 iemAImpl_bt_u64;
3134	FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
3135	FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
3136	FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
3137	FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
3138	FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
3139	FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
3140	FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
3141	FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
3142	FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
3143	/** @} */
3144
3145	/** @name Arithmetic three operand operations on double words (binary).
3146	* @{ */
3147	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32, (uint32_t pu32Dst, uint32_t u32Src1, uint32_t u32Src2, uint32_t pEFlags));
3148	typedef FNIEMAIMPLBINVEXU32 *PFNIEMAIMPLBINVEXU32;
3149	FNIEMAIMPLBINVEXU32 iemAImpl_andn_u32, iemAImpl_andn_u32_fallback;
3150	FNIEMAIMPLBINVEXU32 iemAImpl_bextr_u32, iemAImpl_bextr_u32_fallback;
3151	FNIEMAIMPLBINVEXU32 iemAImpl_bzhi_u32, iemAImpl_bzhi_u32_fallback;
3152	/** @} */
3153
3154	/** @name Arithmetic three operand operations on quad words (binary).
3155	* @{ */
3156	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64, (uint64_t pu64Dst, uint64_t u64Src1, uint64_t u64Src2, uint32_t pEFlags));
3157	typedef FNIEMAIMPLBINVEXU64 *PFNIEMAIMPLBINVEXU64;
3158	FNIEMAIMPLBINVEXU64 iemAImpl_andn_u64, iemAImpl_andn_u64_fallback;
3159	FNIEMAIMPLBINVEXU64 iemAImpl_bextr_u64, iemAImpl_bextr_u64_fallback;
3160	FNIEMAIMPLBINVEXU64 iemAImpl_bzhi_u64, iemAImpl_bzhi_u64_fallback;
3161	/** @} */
3162
3163	/** @name Arithmetic three operand operations on double words w/o EFLAGS (binary).
3164	* @{ */
3165	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32NOEFL, (uint32_t *pu32Dst, uint32_t u32Src1, uint32_t u32Src2));
3166	typedef FNIEMAIMPLBINVEXU32NOEFL *PFNIEMAIMPLBINVEXU32NOEFL;
3167	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pdep_u32, iemAImpl_pdep_u32_fallback;
3168	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pext_u32, iemAImpl_pext_u32_fallback;
3169	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_sarx_u32, iemAImpl_sarx_u32_fallback;
3170	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shlx_u32, iemAImpl_shlx_u32_fallback;
3171	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shrx_u32, iemAImpl_shrx_u32_fallback;
3172	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_rorx_u32;
3173	/** @} */
3174
3175	/** @name Arithmetic three operand operations on quad words w/o EFLAGS (binary).
3176	* @{ */
3177	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64NOEFL, (uint64_t *pu64Dst, uint64_t u64Src1, uint64_t u64Src2));
3178	typedef FNIEMAIMPLBINVEXU64NOEFL *PFNIEMAIMPLBINVEXU64NOEFL;
3179	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pdep_u64, iemAImpl_pdep_u64_fallback;
3180	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pext_u64, iemAImpl_pext_u64_fallback;
3181	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_sarx_u64, iemAImpl_sarx_u64_fallback;
3182	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shlx_u64, iemAImpl_shlx_u64_fallback;
3183	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shrx_u64, iemAImpl_shrx_u64_fallback;
3184	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_rorx_u64;
3185	/** @} */
3186
3187	/** @name MULX 32-bit and 64-bit.
3188	* @{ */
3189	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU32, (uint32_t puDst1, uint32_t puDst2, uint32_t uSrc1, uint32_t uSrc2));
3190	typedef FNIEMAIMPLMULXVEXU32 *PFNIEMAIMPLMULXVEXU32;
3191	FNIEMAIMPLMULXVEXU32 iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback;
3192
3193	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU64, (uint64_t puDst1, uint64_t puDst2, uint64_t uSrc1, uint64_t uSrc2));
3194	typedef FNIEMAIMPLMULXVEXU64 *PFNIEMAIMPLMULXVEXU64;
3195	FNIEMAIMPLMULXVEXU64 iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback;
3196	/** @} */
3197
3198
3199	/** @name Exchange memory with register operations.
3200	* @{ */
3201	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_locked, (uint8_t pu8Mem, uint8_t pu8Reg));
3202	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_locked,(uint16_t pu16Mem, uint16_t pu16Reg));
3203	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_locked,(uint32_t pu32Mem, uint32_t pu32Reg));
3204	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_locked,(uint64_t pu64Mem, uint64_t pu64Reg));
3205	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_unlocked, (uint8_t pu8Mem, uint8_t pu8Reg));
3206	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_unlocked,(uint16_t pu16Mem, uint16_t pu16Reg));
3207	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_unlocked,(uint32_t pu32Mem, uint32_t pu32Reg));
3208	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_unlocked,(uint64_t pu64Mem, uint64_t pu64Reg));
3209	/** @} */
3210
3211	/** @name Exchange and add operations.
3212	* @{ */
3213	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
3214	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
3215	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
3216	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
3217	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
3218	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
3219	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
3220	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
3221	/** @} */
3222
3223	/** @name Compare and exchange.
3224	* @{ */
3225	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
3226	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
3227	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
3228	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
3229	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
3230	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
3231	#if ARCH_BITS == 32
3232	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
3233	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
3234	#else
3235	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
3236	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
3237	#endif
3238	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
3239	uint32_t *pEFlags));
3240	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
3241	uint32_t *pEFlags));
3242	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
3243	uint32_t *pEFlags));
3244	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
3245	uint32_t *pEFlags));
3246	#ifndef RT_ARCH_ARM64
3247	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
3248	PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
3249	#endif
3250	/** @} */
3251
3252	/** @name Memory ordering
3253	* @{ */
3254	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
3255	typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
3256	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
3257	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
3258	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
3259	#ifndef RT_ARCH_ARM64
3260	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
3261	#endif
3262	/** @} */
3263
3264	/** @name Double precision shifts
3265	* @{ */
3266	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t pEFlags));
3267	typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
3268	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t pEFlags));
3269	typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
3270	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t pEFlags));
3271	typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
3272	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16, iemAImpl_shld_u16_amd, iemAImpl_shld_u16_intel;
3273	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32, iemAImpl_shld_u32_amd, iemAImpl_shld_u32_intel;
3274	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64, iemAImpl_shld_u64_amd, iemAImpl_shld_u64_intel;
3275	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16, iemAImpl_shrd_u16_amd, iemAImpl_shrd_u16_intel;
3276	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32, iemAImpl_shrd_u32_amd, iemAImpl_shrd_u32_intel;
3277	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64, iemAImpl_shrd_u64_amd, iemAImpl_shrd_u64_intel;
3278	/** @} */
3279
3280
3281	/** @name Bit search operations (thrown in with the binary ops).
3282	* @{ */
3283	FNIEMAIMPLBINU16 iemAImpl_bsf_u16, iemAImpl_bsf_u16_amd, iemAImpl_bsf_u16_intel;
3284	FNIEMAIMPLBINU32 iemAImpl_bsf_u32, iemAImpl_bsf_u32_amd, iemAImpl_bsf_u32_intel;
3285	FNIEMAIMPLBINU64 iemAImpl_bsf_u64, iemAImpl_bsf_u64_amd, iemAImpl_bsf_u64_intel;
3286	FNIEMAIMPLBINU16 iemAImpl_bsr_u16, iemAImpl_bsr_u16_amd, iemAImpl_bsr_u16_intel;
3287	FNIEMAIMPLBINU32 iemAImpl_bsr_u32, iemAImpl_bsr_u32_amd, iemAImpl_bsr_u32_intel;
3288	FNIEMAIMPLBINU64 iemAImpl_bsr_u64, iemAImpl_bsr_u64_amd, iemAImpl_bsr_u64_intel;
3289	FNIEMAIMPLBINU16 iemAImpl_lzcnt_u16, iemAImpl_lzcnt_u16_amd, iemAImpl_lzcnt_u16_intel;
3290	FNIEMAIMPLBINU32 iemAImpl_lzcnt_u32, iemAImpl_lzcnt_u32_amd, iemAImpl_lzcnt_u32_intel;
3291	FNIEMAIMPLBINU64 iemAImpl_lzcnt_u64, iemAImpl_lzcnt_u64_amd, iemAImpl_lzcnt_u64_intel;
3292	FNIEMAIMPLBINU16 iemAImpl_tzcnt_u16, iemAImpl_tzcnt_u16_amd, iemAImpl_tzcnt_u16_intel;
3293	FNIEMAIMPLBINU32 iemAImpl_tzcnt_u32, iemAImpl_tzcnt_u32_amd, iemAImpl_tzcnt_u32_intel;
3294	FNIEMAIMPLBINU64 iemAImpl_tzcnt_u64, iemAImpl_tzcnt_u64_amd, iemAImpl_tzcnt_u64_intel;
3295	FNIEMAIMPLBINU16 iemAImpl_popcnt_u16, iemAImpl_popcnt_u16_fallback;
3296	FNIEMAIMPLBINU32 iemAImpl_popcnt_u32, iemAImpl_popcnt_u32_fallback;
3297	FNIEMAIMPLBINU64 iemAImpl_popcnt_u64, iemAImpl_popcnt_u64_fallback;
3298	/** @} */
3299
3300	/** @name Signed multiplication operations (thrown in with the binary ops).
3301	* @{ */
3302	FNIEMAIMPLBINU16 iemAImpl_imul_two_u16, iemAImpl_imul_two_u16_amd, iemAImpl_imul_two_u16_intel;
3303	FNIEMAIMPLBINU32 iemAImpl_imul_two_u32, iemAImpl_imul_two_u32_amd, iemAImpl_imul_two_u32_intel;
3304	FNIEMAIMPLBINU64 iemAImpl_imul_two_u64, iemAImpl_imul_two_u64_amd, iemAImpl_imul_two_u64_intel;
3305	/** @} */
3306
3307	/** @name Arithmetic assignment operations on bytes (unary).
3308	* @{ */
3309	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t pu8Dst, uint32_t pEFlags));
3310	typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
3311	FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
3312	FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
3313	FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
3314	FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
3315	/** @} */
3316
3317	/** @name Arithmetic assignment operations on words (unary).
3318	* @{ */
3319	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t pu16Dst, uint32_t pEFlags));
3320	typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
3321	FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
3322	FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
3323	FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
3324	FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
3325	/** @} */
3326
3327	/** @name Arithmetic assignment operations on double words (unary).
3328	* @{ */
3329	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t pu32Dst, uint32_t pEFlags));
3330	typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
3331	FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
3332	FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
3333	FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
3334	FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
3335	/** @} */
3336
3337	/** @name Arithmetic assignment operations on quad words (unary).
3338	* @{ */
3339	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t pu64Dst, uint32_t pEFlags));
3340	typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
3341	FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
3342	FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
3343	FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
3344	FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
3345	/** @} */
3346
3347
3348	/** @name Shift operations on bytes (Group 2).
3349	* @{ */
3350	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU8,(uint32_t fEFlagsIn, uint8_t *pu8Dst, uint8_t cShift));
3351	typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
3352	FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8, iemAImpl_rol_u8_amd, iemAImpl_rol_u8_intel;
3353	FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8, iemAImpl_ror_u8_amd, iemAImpl_ror_u8_intel;
3354	FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8, iemAImpl_rcl_u8_amd, iemAImpl_rcl_u8_intel;
3355	FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8, iemAImpl_rcr_u8_amd, iemAImpl_rcr_u8_intel;
3356	FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8, iemAImpl_shl_u8_amd, iemAImpl_shl_u8_intel;
3357	FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8, iemAImpl_shr_u8_amd, iemAImpl_shr_u8_intel;
3358	FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8, iemAImpl_sar_u8_amd, iemAImpl_sar_u8_intel;
3359	/** @} */
3360
3361	/** @name Shift operations on words (Group 2).
3362	* @{ */
3363	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU16,(uint32_t fEFlagsIn, uint16_t *pu16Dst, uint8_t cShift));
3364	typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
3365	FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16, iemAImpl_rol_u16_amd, iemAImpl_rol_u16_intel;
3366	FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16, iemAImpl_ror_u16_amd, iemAImpl_ror_u16_intel;
3367	FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16, iemAImpl_rcl_u16_amd, iemAImpl_rcl_u16_intel;
3368	FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16, iemAImpl_rcr_u16_amd, iemAImpl_rcr_u16_intel;
3369	FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16, iemAImpl_shl_u16_amd, iemAImpl_shl_u16_intel;
3370	FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16, iemAImpl_shr_u16_amd, iemAImpl_shr_u16_intel;
3371	FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16, iemAImpl_sar_u16_amd, iemAImpl_sar_u16_intel;
3372	/** @} */
3373
3374	/** @name Shift operations on double words (Group 2).
3375	* @{ */
3376	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU32,(uint32_t fEFlagsIn, uint32_t *pu32Dst, uint8_t cShift));
3377	typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
3378	FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32, iemAImpl_rol_u32_amd, iemAImpl_rol_u32_intel;
3379	FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32, iemAImpl_ror_u32_amd, iemAImpl_ror_u32_intel;
3380	FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32, iemAImpl_rcl_u32_amd, iemAImpl_rcl_u32_intel;
3381	FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32, iemAImpl_rcr_u32_amd, iemAImpl_rcr_u32_intel;
3382	FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32, iemAImpl_shl_u32_amd, iemAImpl_shl_u32_intel;
3383	FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32, iemAImpl_shr_u32_amd, iemAImpl_shr_u32_intel;
3384	FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32, iemAImpl_sar_u32_amd, iemAImpl_sar_u32_intel;
3385	/** @} */
3386
3387	/** @name Shift operations on words (Group 2).
3388	* @{ */
3389	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU64,(uint32_t fEFlagsIn, uint64_t *pu64Dst, uint8_t cShift));
3390	typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
3391	FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64, iemAImpl_rol_u64_amd, iemAImpl_rol_u64_intel;
3392	FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64, iemAImpl_ror_u64_amd, iemAImpl_ror_u64_intel;
3393	FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64, iemAImpl_rcl_u64_amd, iemAImpl_rcl_u64_intel;
3394	FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64, iemAImpl_rcr_u64_amd, iemAImpl_rcr_u64_intel;
3395	FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64, iemAImpl_shl_u64_amd, iemAImpl_shl_u64_intel;
3396	FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64, iemAImpl_shr_u64_amd, iemAImpl_shr_u64_intel;
3397	FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64, iemAImpl_sar_u64_amd, iemAImpl_sar_u64_intel;
3398	/** @} */
3399
3400	/** @name Multiplication and division operations.
3401	* @{ */
3402	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMULDIVU8,(uint16_t *pu16AX, uint8_t u8FactorDivisor, uint32_t fEFlags));
3403	typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
3404	FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_mul_u8_amd, iemAImpl_mul_u8_intel;
3405	FNIEMAIMPLMULDIVU8 iemAImpl_imul_u8, iemAImpl_imul_u8_amd, iemAImpl_imul_u8_intel;
3406	FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_div_u8_amd, iemAImpl_div_u8_intel;
3407	FNIEMAIMPLMULDIVU8 iemAImpl_idiv_u8, iemAImpl_idiv_u8_amd, iemAImpl_idiv_u8_intel;
3408
3409	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMULDIVU16,(uint16_t pu16AX, uint16_t pu16DX, uint16_t u16FactorDivisor, uint32_t fEFlags));
3410	typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
3411	FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_mul_u16_amd, iemAImpl_mul_u16_intel;
3412	FNIEMAIMPLMULDIVU16 iemAImpl_imul_u16, iemAImpl_imul_u16_amd, iemAImpl_imul_u16_intel;
3413	FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_div_u16_amd, iemAImpl_div_u16_intel;
3414	FNIEMAIMPLMULDIVU16 iemAImpl_idiv_u16, iemAImpl_idiv_u16_amd, iemAImpl_idiv_u16_intel;
3415
3416	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMULDIVU32,(uint32_t pu32EAX, uint32_t pu32EDX, uint32_t u32FactorDivisor, uint32_t fEFlags));
3417	typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
3418	FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_mul_u32_amd, iemAImpl_mul_u32_intel;
3419	FNIEMAIMPLMULDIVU32 iemAImpl_imul_u32, iemAImpl_imul_u32_amd, iemAImpl_imul_u32_intel;
3420	FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_div_u32_amd, iemAImpl_div_u32_intel;
3421	FNIEMAIMPLMULDIVU32 iemAImpl_idiv_u32, iemAImpl_idiv_u32_amd, iemAImpl_idiv_u32_intel;
3422
3423	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMULDIVU64,(uint64_t pu64RAX, uint64_t pu64RDX, uint64_t u64FactorDivisor, uint32_t fEFlags));
3424	typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
3425	FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_mul_u64_amd, iemAImpl_mul_u64_intel;
3426	FNIEMAIMPLMULDIVU64 iemAImpl_imul_u64, iemAImpl_imul_u64_amd, iemAImpl_imul_u64_intel;
3427	FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_div_u64_amd, iemAImpl_div_u64_intel;
3428	FNIEMAIMPLMULDIVU64 iemAImpl_idiv_u64, iemAImpl_idiv_u64_amd, iemAImpl_idiv_u64_intel;
3429	/** @} */
3430
3431	/** @name Byte Swap.
3432	* @{ */
3433	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t pu32Dst)); / Yes, 32-bit register access. */
3434	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
3435	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
3436	/** @} */
3437
3438	/** @name Misc.
3439	* @{ */
3440	FNIEMAIMPLBINU16 iemAImpl_arpl;
3441	/** @} */
3442
3443	/** @name RDRAND and RDSEED
3444	* @{ */
3445	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU16,(uint16_t puDst, uint32_t pEFlags));
3446	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU32,(uint32_t puDst, uint32_t pEFlags));
3447	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU64,(uint64_t puDst, uint32_t pEFlags));
3448	typedef FNIEMAIMPLRDRANDSEEDU16 *PFNIEMAIMPLRDRANDSEEDU16;
3449	typedef FNIEMAIMPLRDRANDSEEDU32 *PFNIEMAIMPLRDRANDSEEDU32;
3450	typedef FNIEMAIMPLRDRANDSEEDU64 *PFNIEMAIMPLRDRANDSEEDU64;
3451
3452	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdrand_u16, iemAImpl_rdrand_u16_fallback;
3453	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdrand_u32, iemAImpl_rdrand_u32_fallback;
3454	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdrand_u64, iemAImpl_rdrand_u64_fallback;
3455	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdseed_u16, iemAImpl_rdseed_u16_fallback;
3456	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdseed_u32, iemAImpl_rdseed_u32_fallback;
3457	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdseed_u64, iemAImpl_rdseed_u64_fallback;
3458	/** @} */
3459
3460	/** @name ADOX and ADCX
3461	* @{ */
3462	FNIEMAIMPLBINU32 iemAImpl_adcx_u32, iemAImpl_adcx_u32_fallback;
3463	FNIEMAIMPLBINU64 iemAImpl_adcx_u64, iemAImpl_adcx_u64_fallback;
3464	FNIEMAIMPLBINU32 iemAImpl_adox_u32, iemAImpl_adox_u32_fallback;
3465	FNIEMAIMPLBINU64 iemAImpl_adox_u64, iemAImpl_adox_u64_fallback;
3466	/** @} */
3467
3468	/** @name FPU operations taking a 32-bit float argument
3469	* @{ */
3470	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3471	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
3472	typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
3473
3474	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3475	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
3476	typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
3477
3478	FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
3479	FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
3480	FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
3481	FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
3482	FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
3483	FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
3484	FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
3485
3486	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
3487	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3488	PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
3489	/** @} */
3490
3491	/** @name FPU operations taking a 64-bit float argument
3492	* @{ */
3493	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3494	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
3495	typedef FNIEMAIMPLFPUR64FSW *PFNIEMAIMPLFPUR64FSW;
3496
3497	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3498	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
3499	typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
3500
3501	FNIEMAIMPLFPUR64FSW iemAImpl_fcom_r80_by_r64;
3502	FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
3503	FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
3504	FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
3505	FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
3506	FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
3507	FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
3508
3509	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
3510	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3511	PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
3512	/** @} */
3513
3514	/** @name FPU operations taking a 80-bit float argument
3515	* @{ */
3516	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3517	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
3518	typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
3519	FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
3520	FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
3521	FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
3522	FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
3523	FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
3524	FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
3525	FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
3526	FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
3527	FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
3528
3529	FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80, iemAImpl_fpatan_r80_by_r80_amd, iemAImpl_fpatan_r80_by_r80_intel;
3530	FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80, iemAImpl_fyl2x_r80_by_r80_amd, iemAImpl_fyl2x_r80_by_r80_intel;
3531	FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80, iemAImpl_fyl2xp1_r80_by_r80_amd, iemAImpl_fyl2xp1_r80_by_r80_intel;
3532
3533	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3534	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
3535	typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
3536	FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
3537	FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
3538
3539	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
3540	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
3541	typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
3542	FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
3543	FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
3544
3545	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
3546	typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
3547	FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
3548	FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
3549	FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80, iemAImpl_f2xm1_r80_amd, iemAImpl_f2xm1_r80_intel;
3550	FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
3551	FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
3552	FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80, iemAImpl_fsin_r80_amd, iemAImpl_fsin_r80_intel;
3553	FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80, iemAImpl_fcos_r80_amd, iemAImpl_fcos_r80_intel;
3554
3555	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
3556	typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
3557	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
3558	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
3559
3560	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
3561	typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
3562	FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
3563	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
3564	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
3565	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
3566	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
3567	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
3568	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
3569
3570	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
3571	PCRTFLOAT80U pr80Val));
3572	typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
3573	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80, iemAImpl_fptan_r80_r80_amd, iemAImpl_fptan_r80_r80_intel;
3574	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
3575	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80, iemAImpl_fsincos_r80_r80_amd, iemAImpl_fsincos_r80_r80_intel;
3576
3577	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
3578	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3579	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
3580
3581	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_d80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTPBCD80U pd80Val));
3582	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_d80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3583	PRTPBCD80U pd80Dst, PCRTFLOAT80U pr80Src));
3584
3585	/** @} */
3586
3587	/** @name FPU operations taking a 16-bit signed integer argument
3588	* @{ */
3589	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3590	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
3591	typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
3592	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI16,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3593	int16_t *pi16Dst, PCRTFLOAT80U pr80Src));
3594	typedef FNIEMAIMPLFPUSTR80TOI16 *PFNIEMAIMPLFPUSTR80TOI16;
3595
3596	FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
3597	FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
3598	FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
3599	FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
3600	FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
3601	FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
3602
3603	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3604	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
3605	typedef FNIEMAIMPLFPUI16FSW *PFNIEMAIMPLFPUI16FSW;
3606	FNIEMAIMPLFPUI16FSW iemAImpl_ficom_r80_by_i16;
3607
3608	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
3609	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fist_r80_to_i16;
3610	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fistt_r80_to_i16, iemAImpl_fistt_r80_to_i16_amd, iemAImpl_fistt_r80_to_i16_intel;
3611	/** @} */
3612
3613	/** @name FPU operations taking a 32-bit signed integer argument
3614	* @{ */
3615	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3616	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
3617	typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
3618	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI32,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3619	int32_t *pi32Dst, PCRTFLOAT80U pr80Src));
3620	typedef FNIEMAIMPLFPUSTR80TOI32 *PFNIEMAIMPLFPUSTR80TOI32;
3621
3622	FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
3623	FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
3624	FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
3625	FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
3626	FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
3627	FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
3628
3629	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3630	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
3631	typedef FNIEMAIMPLFPUI32FSW *PFNIEMAIMPLFPUI32FSW;
3632	FNIEMAIMPLFPUI32FSW iemAImpl_ficom_r80_by_i32;
3633
3634	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
3635	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fist_r80_to_i32;
3636	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fistt_r80_to_i32;
3637	/** @} */
3638
3639	/** @name FPU operations taking a 64-bit signed integer argument
3640	* @{ */
3641	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI64,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3642	int64_t *pi64Dst, PCRTFLOAT80U pr80Src));
3643	typedef FNIEMAIMPLFPUSTR80TOI64 *PFNIEMAIMPLFPUSTR80TOI64;
3644
3645	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
3646	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fist_r80_to_i64;
3647	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fistt_r80_to_i64;
3648	/** @} */
3649
3650
3651	/** Temporary type representing a 256-bit vector register. */
3652	typedef struct { uint64_t au64[4]; } IEMVMM256;
3653	/** Temporary type pointing to a 256-bit vector register. */
3654	typedef IEMVMM256 *PIEMVMM256;
3655	/** Temporary type pointing to a const 256-bit vector register. */
3656	typedef IEMVMM256 *PCIEMVMM256;
3657
3658
3659	/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
3660	* @{ */
3661	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t puDst, uint64_t const puSrc));
3662	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
3663	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF2U128,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
3664	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
3665	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF2U256,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86YMMREG puSrc));
3666	typedef FNIEMAIMPLMEDIAF2U256 *PFNIEMAIMPLMEDIAF2U256;
3667	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF3U128,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
3668	typedef FNIEMAIMPLMEDIAF3U128 *PFNIEMAIMPLMEDIAF3U128;
3669	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF3U256,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86YMMREG puSrc1, PCX86YMMREG puSrc2));
3670	typedef FNIEMAIMPLMEDIAF3U256 *PFNIEMAIMPLMEDIAF3U256;
3671	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U64,(uint64_t puDst, uint64_t const puSrc));
3672	typedef FNIEMAIMPLMEDIAOPTF2U64 *PFNIEMAIMPLMEDIAOPTF2U64;
3673	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128,(PRTUINT128U puDst, PCRTUINT128U puSrc));
3674	typedef FNIEMAIMPLMEDIAOPTF2U128 *PFNIEMAIMPLMEDIAOPTF2U128;
3675	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
3676	typedef FNIEMAIMPLMEDIAOPTF3U128 *PFNIEMAIMPLMEDIAOPTF3U128;
3677	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
3678	typedef FNIEMAIMPLMEDIAOPTF3U256 *PFNIEMAIMPLMEDIAOPTF3U256;
3679	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256,(PRTUINT256U puDst, PCRTUINT256U puSrc));
3680	typedef FNIEMAIMPLMEDIAOPTF2U256 *PFNIEMAIMPLMEDIAOPTF2U256;
3681	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pshufb_u64, iemAImpl_pshufb_u64_fallback;
3682	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pand_u64, iemAImpl_pandn_u64, iemAImpl_por_u64, iemAImpl_pxor_u64;
3683	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
3684	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pcmpgtb_u64, iemAImpl_pcmpgtw_u64, iemAImpl_pcmpgtd_u64;
3685	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddb_u64, iemAImpl_paddsb_u64, iemAImpl_paddusb_u64;
3686	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddw_u64, iemAImpl_paddsw_u64, iemAImpl_paddusw_u64;
3687	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddd_u64;
3688	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddq_u64;
3689	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubb_u64, iemAImpl_psubsb_u64, iemAImpl_psubusb_u64;
3690	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubw_u64, iemAImpl_psubsw_u64, iemAImpl_psubusw_u64;
3691	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubd_u64;
3692	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubq_u64;
3693	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmaddwd_u64, iemAImpl_pmaddwd_u64_fallback;
3694	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmullw_u64, iemAImpl_pmulhw_u64;
3695	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pminub_u64, iemAImpl_pmaxub_u64;
3696	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pminsw_u64, iemAImpl_pmaxsw_u64;
3697	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pabsb_u64, iemAImpl_pabsb_u64_fallback;
3698	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pabsw_u64, iemAImpl_pabsw_u64_fallback;
3699	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pabsd_u64, iemAImpl_pabsd_u64_fallback;
3700	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psignb_u64, iemAImpl_psignb_u64_fallback;
3701	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psignw_u64, iemAImpl_psignw_u64_fallback;
3702	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psignd_u64, iemAImpl_psignd_u64_fallback;
3703	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phaddw_u64, iemAImpl_phaddw_u64_fallback;
3704	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phaddd_u64, iemAImpl_phaddd_u64_fallback;
3705	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phsubw_u64, iemAImpl_phsubw_u64_fallback;
3706	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phsubd_u64, iemAImpl_phsubd_u64_fallback;
3707	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phaddsw_u64, iemAImpl_phaddsw_u64_fallback;
3708	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phsubsw_u64, iemAImpl_phsubsw_u64_fallback;
3709	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmaddubsw_u64, iemAImpl_pmaddubsw_u64_fallback;
3710	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhrsw_u64, iemAImpl_pmulhrsw_u64_fallback;
3711	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmuludq_u64;
3712	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllw_u64, iemAImpl_psrlw_u64, iemAImpl_psraw_u64;
3713	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pslld_u64, iemAImpl_psrld_u64, iemAImpl_psrad_u64;
3714	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllq_u64, iemAImpl_psrlq_u64;
3715	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packsswb_u64, iemAImpl_packuswb_u64;
3716	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packssdw_u64;
3717	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhuw_u64;
3718	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pavgb_u64, iemAImpl_pavgw_u64;
3719	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psadbw_u64;
3720
3721	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pshufb_u128, iemAImpl_pshufb_u128_fallback;
3722	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pand_u128, iemAImpl_pandn_u128, iemAImpl_por_u128, iemAImpl_pxor_u128;
3723	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
3724	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpeqq_u128, iemAImpl_pcmpeqq_u128_fallback;
3725	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpgtb_u128, iemAImpl_pcmpgtw_u128, iemAImpl_pcmpgtd_u128;
3726	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpgtq_u128, iemAImpl_pcmpgtq_u128_fallback;
3727	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddb_u128, iemAImpl_paddsb_u128, iemAImpl_paddusb_u128;
3728	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddw_u128, iemAImpl_paddsw_u128, iemAImpl_paddusw_u128;
3729	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddd_u128;
3730	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddq_u128;
3731	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubb_u128, iemAImpl_psubsb_u128, iemAImpl_psubusb_u128;
3732	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubw_u128, iemAImpl_psubsw_u128, iemAImpl_psubusw_u128;
3733	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubd_u128;
3734	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubq_u128;
3735	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmullw_u128, iemAImpl_pmullw_u128_fallback;
3736	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhw_u128;
3737	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulld_u128, iemAImpl_pmulld_u128_fallback;
3738	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaddwd_u128, iemAImpl_pmaddwd_u128_fallback;
3739	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminub_u128;
3740	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminud_u128, iemAImpl_pminud_u128_fallback;
3741	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminuw_u128, iemAImpl_pminuw_u128_fallback;
3742	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminsb_u128, iemAImpl_pminsb_u128_fallback;
3743	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminsd_u128, iemAImpl_pminsd_u128_fallback;
3744	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminsw_u128, iemAImpl_pminsw_u128_fallback;
3745	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxub_u128;
3746	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxud_u128, iemAImpl_pmaxud_u128_fallback;
3747	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxuw_u128, iemAImpl_pmaxuw_u128_fallback;
3748	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxsb_u128, iemAImpl_pmaxsb_u128_fallback;
3749	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxsw_u128;
3750	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxsd_u128, iemAImpl_pmaxsd_u128_fallback;
3751	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pabsb_u128, iemAImpl_pabsb_u128_fallback;
3752	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pabsw_u128, iemAImpl_pabsw_u128_fallback;
3753	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pabsd_u128, iemAImpl_pabsd_u128_fallback;
3754	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psignb_u128, iemAImpl_psignb_u128_fallback;
3755	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psignw_u128, iemAImpl_psignw_u128_fallback;
3756	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psignd_u128, iemAImpl_psignd_u128_fallback;
3757	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phaddw_u128, iemAImpl_phaddw_u128_fallback;
3758	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phaddd_u128, iemAImpl_phaddd_u128_fallback;
3759	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phsubw_u128, iemAImpl_phsubw_u128_fallback;
3760	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phsubd_u128, iemAImpl_phsubd_u128_fallback;
3761	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phaddsw_u128, iemAImpl_phaddsw_u128_fallback;
3762	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phsubsw_u128, iemAImpl_phsubsw_u128_fallback;
3763	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaddubsw_u128, iemAImpl_pmaddubsw_u128_fallback;
3764	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhrsw_u128, iemAImpl_pmulhrsw_u128_fallback;
3765	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuludq_u128;
3766	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaddwd_u128, iemAImpl_pmaddwd_u128_fallback;
3767	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packsswb_u128, iemAImpl_packuswb_u128;
3768	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packssdw_u128, iemAImpl_packusdw_u128;
3769	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllw_u128, iemAImpl_psrlw_u128, iemAImpl_psraw_u128;
3770	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pslld_u128, iemAImpl_psrld_u128, iemAImpl_psrad_u128;
3771	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllq_u128, iemAImpl_psrlq_u128;
3772	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhuw_u128;
3773	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pavgb_u128, iemAImpl_pavgw_u128;
3774	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psadbw_u128;
3775	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuldq_u128, iemAImpl_pmuldq_u128_fallback;
3776	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpcklps_u128, iemAImpl_unpcklpd_u128;
3777	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpckhps_u128, iemAImpl_unpckhpd_u128;
3778	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phminposuw_u128, iemAImpl_phminposuw_u128_fallback;
3779
3780	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpshufb_u128, iemAImpl_vpshufb_u128_fallback;
3781	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpand_u128, iemAImpl_vpand_u128_fallback;
3782	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpandn_u128, iemAImpl_vpandn_u128_fallback;
3783	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpor_u128, iemAImpl_vpor_u128_fallback;
3784	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpxor_u128, iemAImpl_vpxor_u128_fallback;
3785	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqb_u128, iemAImpl_vpcmpeqb_u128_fallback;
3786	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqw_u128, iemAImpl_vpcmpeqw_u128_fallback;
3787	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqd_u128, iemAImpl_vpcmpeqd_u128_fallback;
3788	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqq_u128, iemAImpl_vpcmpeqq_u128_fallback;
3789	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtb_u128, iemAImpl_vpcmpgtb_u128_fallback;
3790	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtw_u128, iemAImpl_vpcmpgtw_u128_fallback;
3791	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtd_u128, iemAImpl_vpcmpgtd_u128_fallback;
3792	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtq_u128, iemAImpl_vpcmpgtq_u128_fallback;
3793	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddb_u128, iemAImpl_vpaddb_u128_fallback;
3794	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddw_u128, iemAImpl_vpaddw_u128_fallback;
3795	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddd_u128, iemAImpl_vpaddd_u128_fallback;
3796	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddq_u128, iemAImpl_vpaddq_u128_fallback;
3797	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubb_u128, iemAImpl_vpsubb_u128_fallback;
3798	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubw_u128, iemAImpl_vpsubw_u128_fallback;
3799	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubd_u128, iemAImpl_vpsubd_u128_fallback;
3800	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubq_u128, iemAImpl_vpsubq_u128_fallback;
3801	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminub_u128, iemAImpl_vpminub_u128_fallback;
3802	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminuw_u128, iemAImpl_vpminuw_u128_fallback;
3803	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminud_u128, iemAImpl_vpminud_u128_fallback;
3804	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminsb_u128, iemAImpl_vpminsb_u128_fallback;
3805	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminsw_u128, iemAImpl_vpminsw_u128_fallback;
3806	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminsd_u128, iemAImpl_vpminsd_u128_fallback;
3807	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxub_u128, iemAImpl_vpmaxub_u128_fallback;
3808	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxuw_u128, iemAImpl_vpmaxuw_u128_fallback;
3809	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxud_u128, iemAImpl_vpmaxud_u128_fallback;
3810	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxsb_u128, iemAImpl_vpmaxsb_u128_fallback;
3811	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxsw_u128, iemAImpl_vpmaxsw_u128_fallback;
3812	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxsd_u128, iemAImpl_vpmaxsd_u128_fallback;
3813	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpacksswb_u128, iemAImpl_vpacksswb_u128_fallback;
3814	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackssdw_u128, iemAImpl_vpackssdw_u128_fallback;
3815	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackuswb_u128, iemAImpl_vpackuswb_u128_fallback;
3816	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackusdw_u128, iemAImpl_vpackusdw_u128_fallback;
3817	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmullw_u128, iemAImpl_vpmullw_u128_fallback;
3818	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulld_u128, iemAImpl_vpmulld_u128_fallback;
3819	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhw_u128, iemAImpl_vpmulhw_u128_fallback;
3820	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhuw_u128, iemAImpl_vpmulhuw_u128_fallback;
3821	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgb_u128, iemAImpl_vpavgb_u128_fallback;
3822	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgw_u128, iemAImpl_vpavgw_u128_fallback;
3823	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignb_u128, iemAImpl_vpsignb_u128_fallback;
3824	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignw_u128, iemAImpl_vpsignw_u128_fallback;
3825	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignd_u128, iemAImpl_vpsignd_u128_fallback;
3826	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddw_u128, iemAImpl_vphaddw_u128_fallback;
3827	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddd_u128, iemAImpl_vphaddd_u128_fallback;
3828	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubw_u128, iemAImpl_vphsubw_u128_fallback;
3829	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubd_u128, iemAImpl_vphsubd_u128_fallback;
3830	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddsw_u128, iemAImpl_vphaddsw_u128_fallback;
3831	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubsw_u128, iemAImpl_vphsubsw_u128_fallback;
3832	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddubsw_u128, iemAImpl_vpmaddubsw_u128_fallback;
3833	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhrsw_u128, iemAImpl_vpmulhrsw_u128_fallback;
3834	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsadbw_u128, iemAImpl_vpsadbw_u128_fallback;
3835	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuldq_u128, iemAImpl_vpmuldq_u128_fallback;
3836	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuludq_u128, iemAImpl_vpmuludq_u128_fallback;
3837	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsb_u128, iemAImpl_vpsubsb_u128_fallback;
3838	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsw_u128, iemAImpl_vpsubsw_u128_fallback;
3839	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusb_u128, iemAImpl_vpsubusb_u128_fallback;
3840	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusw_u128, iemAImpl_vpsubusw_u128_fallback;
3841	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusb_u128, iemAImpl_vpaddusb_u128_fallback;
3842	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusw_u128, iemAImpl_vpaddusw_u128_fallback;
3843	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsb_u128, iemAImpl_vpaddsb_u128_fallback;
3844	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsw_u128, iemAImpl_vpaddsw_u128_fallback;
3845	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllw_u128, iemAImpl_vpsllw_u128_fallback;
3846	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpslld_u128, iemAImpl_vpslld_u128_fallback;
3847	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllq_u128, iemAImpl_vpsllq_u128_fallback;
3848	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsraw_u128, iemAImpl_vpsraw_u128_fallback;
3849	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrad_u128, iemAImpl_vpsrad_u128_fallback;
3850	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlw_u128, iemAImpl_vpsrlw_u128_fallback;
3851	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrld_u128, iemAImpl_vpsrld_u128_fallback;
3852	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlq_u128, iemAImpl_vpsrlq_u128_fallback;
3853	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddwd_u128, iemAImpl_vpmaddwd_u128_fallback;
3854
3855	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsb_u128, iemAImpl_vpabsb_u128_fallback;
3856	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsw_u128, iemAImpl_vpabsd_u128_fallback;
3857	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsd_u128, iemAImpl_vpabsw_u128_fallback;
3858	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vphminposuw_u128, iemAImpl_vphminposuw_u128_fallback;
3859
3860	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpshufb_u256, iemAImpl_vpshufb_u256_fallback;
3861	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpand_u256, iemAImpl_vpand_u256_fallback;
3862	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpandn_u256, iemAImpl_vpandn_u256_fallback;
3863	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpor_u256, iemAImpl_vpor_u256_fallback;
3864	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpxor_u256, iemAImpl_vpxor_u256_fallback;
3865	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqb_u256, iemAImpl_vpcmpeqb_u256_fallback;
3866	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqw_u256, iemAImpl_vpcmpeqw_u256_fallback;
3867	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqd_u256, iemAImpl_vpcmpeqd_u256_fallback;
3868	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqq_u256, iemAImpl_vpcmpeqq_u256_fallback;
3869	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtb_u256, iemAImpl_vpcmpgtb_u256_fallback;
3870	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtw_u256, iemAImpl_vpcmpgtw_u256_fallback;
3871	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtd_u256, iemAImpl_vpcmpgtd_u256_fallback;
3872	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtq_u256, iemAImpl_vpcmpgtq_u256_fallback;
3873	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddb_u256, iemAImpl_vpaddb_u256_fallback;
3874	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddw_u256, iemAImpl_vpaddw_u256_fallback;
3875	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddd_u256, iemAImpl_vpaddd_u256_fallback;
3876	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddq_u256, iemAImpl_vpaddq_u256_fallback;
3877	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubb_u256, iemAImpl_vpsubb_u256_fallback;
3878	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubw_u256, iemAImpl_vpsubw_u256_fallback;
3879	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubd_u256, iemAImpl_vpsubd_u256_fallback;
3880	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubq_u256, iemAImpl_vpsubq_u256_fallback;
3881	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminub_u256, iemAImpl_vpminub_u256_fallback;
3882	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminuw_u256, iemAImpl_vpminuw_u256_fallback;
3883	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminud_u256, iemAImpl_vpminud_u256_fallback;
3884	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminsb_u256, iemAImpl_vpminsb_u256_fallback;
3885	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminsw_u256, iemAImpl_vpminsw_u256_fallback;
3886	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminsd_u256, iemAImpl_vpminsd_u256_fallback;
3887	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxub_u256, iemAImpl_vpmaxub_u256_fallback;
3888	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxuw_u256, iemAImpl_vpmaxuw_u256_fallback;
3889	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxud_u256, iemAImpl_vpmaxud_u256_fallback;
3890	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxsb_u256, iemAImpl_vpmaxsb_u256_fallback;
3891	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxsw_u256, iemAImpl_vpmaxsw_u256_fallback;
3892	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxsd_u256, iemAImpl_vpmaxsd_u256_fallback;
3893	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpacksswb_u256, iemAImpl_vpacksswb_u256_fallback;
3894	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackssdw_u256, iemAImpl_vpackssdw_u256_fallback;
3895	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackuswb_u256, iemAImpl_vpackuswb_u256_fallback;
3896	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackusdw_u256, iemAImpl_vpackusdw_u256_fallback;
3897	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmullw_u256, iemAImpl_vpmullw_u256_fallback;
3898	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulld_u256, iemAImpl_vpmulld_u256_fallback;
3899	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhw_u256, iemAImpl_vpmulhw_u256_fallback;
3900	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhuw_u256, iemAImpl_vpmulhuw_u256_fallback;
3901	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgb_u256, iemAImpl_vpavgb_u256_fallback;
3902	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgw_u256, iemAImpl_vpavgw_u256_fallback;
3903	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignb_u256, iemAImpl_vpsignb_u256_fallback;
3904	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignw_u256, iemAImpl_vpsignw_u256_fallback;
3905	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignd_u256, iemAImpl_vpsignd_u256_fallback;
3906	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddw_u256, iemAImpl_vphaddw_u256_fallback;
3907	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddd_u256, iemAImpl_vphaddd_u256_fallback;
3908	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubw_u256, iemAImpl_vphsubw_u256_fallback;
3909	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubd_u256, iemAImpl_vphsubd_u256_fallback;
3910	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddsw_u256, iemAImpl_vphaddsw_u256_fallback;
3911	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubsw_u256, iemAImpl_vphsubsw_u256_fallback;
3912	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddubsw_u256, iemAImpl_vpmaddubsw_u256_fallback;
3913	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhrsw_u256, iemAImpl_vpmulhrsw_u256_fallback;
3914	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsadbw_u256, iemAImpl_vpsadbw_u256_fallback;
3915	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuldq_u256, iemAImpl_vpmuldq_u256_fallback;
3916	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuludq_u256, iemAImpl_vpmuludq_u256_fallback;
3917	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsb_u256, iemAImpl_vpsubsb_u256_fallback;
3918	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsw_u256, iemAImpl_vpsubsw_u256_fallback;
3919	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusb_u256, iemAImpl_vpsubusb_u256_fallback;
3920	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusw_u256, iemAImpl_vpsubusw_u256_fallback;
3921	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusb_u256, iemAImpl_vpaddusb_u256_fallback;
3922	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusw_u256, iemAImpl_vpaddusw_u256_fallback;
3923	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsb_u256, iemAImpl_vpaddsb_u256_fallback;
3924	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsw_u256, iemAImpl_vpaddsw_u256_fallback;
3925	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllw_u256, iemAImpl_vpsllw_u256_fallback;
3926	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpslld_u256, iemAImpl_vpslld_u256_fallback;
3927	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllq_u256, iemAImpl_vpsllq_u256_fallback;
3928	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsraw_u256, iemAImpl_vpsraw_u256_fallback;
3929	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrad_u256, iemAImpl_vpsrad_u256_fallback;
3930	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlw_u256, iemAImpl_vpsrlw_u256_fallback;
3931	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrld_u256, iemAImpl_vpsrld_u256_fallback;
3932	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlq_u256, iemAImpl_vpsrlq_u256_fallback;
3933	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddwd_u256, iemAImpl_vpmaddwd_u256_fallback;
3934	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpermps_u256, iemAImpl_vpermps_u256_fallback;
3935	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpermd_u256, iemAImpl_vpermd_u256_fallback;
3936
3937	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsb_u256, iemAImpl_vpabsb_u256_fallback;
3938	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsw_u256, iemAImpl_vpabsw_u256_fallback;
3939	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsd_u256, iemAImpl_vpabsd_u256_fallback;
3940	/** @} */
3941
3942	/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
3943	* @{ */
3944	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
3945	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
3946	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpcklbw_u128, iemAImpl_vpunpcklbw_u128_fallback,
3947	iemAImpl_vpunpcklwd_u128, iemAImpl_vpunpcklwd_u128_fallback,
3948	iemAImpl_vpunpckldq_u128, iemAImpl_vpunpckldq_u128_fallback,
3949	iemAImpl_vpunpcklqdq_u128, iemAImpl_vpunpcklqdq_u128_fallback,
3950	iemAImpl_vunpcklps_u128, iemAImpl_vunpcklps_u128_fallback,
3951	iemAImpl_vunpcklpd_u128, iemAImpl_vunpcklpd_u128_fallback,
3952	iemAImpl_vunpckhps_u128, iemAImpl_vunpckhps_u128_fallback,
3953	iemAImpl_vunpckhpd_u128, iemAImpl_vunpckhpd_u128_fallback;
3954
3955	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpcklbw_u256, iemAImpl_vpunpcklbw_u256_fallback,
3956	iemAImpl_vpunpcklwd_u256, iemAImpl_vpunpcklwd_u256_fallback,
3957	iemAImpl_vpunpckldq_u256, iemAImpl_vpunpckldq_u256_fallback,
3958	iemAImpl_vpunpcklqdq_u256, iemAImpl_vpunpcklqdq_u256_fallback,
3959	iemAImpl_vunpcklps_u256, iemAImpl_vunpcklps_u256_fallback,
3960	iemAImpl_vunpcklpd_u256, iemAImpl_vunpcklpd_u256_fallback,
3961	iemAImpl_vunpckhps_u256, iemAImpl_vunpckhps_u256_fallback,
3962	iemAImpl_vunpckhpd_u256, iemAImpl_vunpckhpd_u256_fallback;
3963	/** @} */
3964
3965	/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
3966	* @{ */
3967	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
3968	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
3969	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpckhbw_u128, iemAImpl_vpunpckhbw_u128_fallback,
3970	iemAImpl_vpunpckhwd_u128, iemAImpl_vpunpckhwd_u128_fallback,
3971	iemAImpl_vpunpckhdq_u128, iemAImpl_vpunpckhdq_u128_fallback,
3972	iemAImpl_vpunpckhqdq_u128, iemAImpl_vpunpckhqdq_u128_fallback;
3973	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpckhbw_u256, iemAImpl_vpunpckhbw_u256_fallback,
3974	iemAImpl_vpunpckhwd_u256, iemAImpl_vpunpckhwd_u256_fallback,
3975	iemAImpl_vpunpckhdq_u256, iemAImpl_vpunpckhdq_u256_fallback,
3976	iemAImpl_vpunpckhqdq_u256, iemAImpl_vpunpckhqdq_u256_fallback;
3977	/** @} */
3978
3979	/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
3980	* @{ */
3981	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3982	typedef FNIEMAIMPLMEDIAPSHUFU128 *PFNIEMAIMPLMEDIAPSHUFU128;
3983	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
3984	typedef FNIEMAIMPLMEDIAPSHUFU256 *PFNIEMAIMPLMEDIAPSHUFU256;
3985	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw_u64,(uint64_t puDst, uint64_t const puSrc, uint8_t bEvil));
3986	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_pshufhw_u128, iemAImpl_pshuflw_u128, iemAImpl_pshufd_u128;
3987	#ifndef IEM_WITHOUT_ASSEMBLY
3988	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256, iemAImpl_vpshuflw_u256, iemAImpl_vpshufd_u256;
3989	#endif
3990	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256_fallback, iemAImpl_vpshuflw_u256_fallback, iemAImpl_vpshufd_u256_fallback;
3991	/** @} */
3992
3993	/** @name Media (SSE/MMX/AVX) operation: Shift Immediate Stuff (evil)
3994	* @{ */
3995	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU64,(uint64_t *puDst, uint8_t bShift));
3996	typedef FNIEMAIMPLMEDIAPSHIFTU64 *PFNIEMAIMPLMEDIAPSHIFTU64;
3997	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU128,(PRTUINT128U puDst, uint8_t bShift));
3998	typedef FNIEMAIMPLMEDIAPSHIFTU128 *PFNIEMAIMPLMEDIAPSHIFTU128;
3999	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU256,(PRTUINT256U puDst, uint8_t bShift));
4000	typedef FNIEMAIMPLMEDIAPSHIFTU256 *PFNIEMAIMPLMEDIAPSHIFTU256;
4001	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psllw_imm_u64, iemAImpl_pslld_imm_u64, iemAImpl_psllq_imm_u64;
4002	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psrlw_imm_u64, iemAImpl_psrld_imm_u64, iemAImpl_psrlq_imm_u64;
4003	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psraw_imm_u64, iemAImpl_psrad_imm_u64;
4004	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psllw_imm_u128, iemAImpl_pslld_imm_u128, iemAImpl_psllq_imm_u128;
4005	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psrlw_imm_u128, iemAImpl_psrld_imm_u128, iemAImpl_psrlq_imm_u128;
4006	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psraw_imm_u128, iemAImpl_psrad_imm_u128;
4007	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_pslldq_imm_u128, iemAImpl_psrldq_imm_u128;
4008	/** @} */
4009
4010	/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
4011	* @{ */
4012	IEM_DECL_IMPL_DEF(void, iemAImpl_maskmovq_u64,(uint64_t puMem, uint64_t const puSrc, uint64_t const *puMsk));
4013	IEM_DECL_IMPL_DEF(void, iemAImpl_maskmovdqu_u128,(PRTUINT128U puMem, PCRTUINT128U puSrc, PCRTUINT128U puMsk));
4014	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(uint64_t pu64Dst, uint64_t const puSrc));
4015	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(uint64_t *pu64Dst, PCRTUINT128U puSrc));
4016	#ifndef IEM_WITHOUT_ASSEMBLY
4017	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
4018	#endif
4019	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256_fallback,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
4020	/** @} */
4021
4022	/** @name Media (SSE/MMX/AVX) operations: Variable Blend Packed Bytes/R32/R64.
4023	* @{ */
4024	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puMask));
4025	typedef FNIEMAIMPLBLENDU128 *PFNIEMAIMPLBLENDU128;
4026	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, PCRTUINT128U puMask));
4027	typedef FNIEMAIMPLAVXBLENDU128 *PFNIEMAIMPLAVXBLENDU128;
4028	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, PCRTUINT256U puMask));
4029	typedef FNIEMAIMPLAVXBLENDU256 *PFNIEMAIMPLAVXBLENDU256;
4030
4031	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128;
4032	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128_fallback;
4033	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128;
4034	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128_fallback;
4035	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256;
4036	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256_fallback;
4037
4038	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128;
4039	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128_fallback;
4040	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128;
4041	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128_fallback;
4042	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256;
4043	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256_fallback;
4044
4045	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128;
4046	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128_fallback;
4047	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128;
4048	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128_fallback;
4049	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256;
4050	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256_fallback;
4051	/** @} */
4052
4053
4054	/** @name Media (SSE/MMX/AVX) operation: Sort this later
4055	* @{ */
4056	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
4057	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
4058	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
4059	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4060	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4061
4062	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
4063	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
4064	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
4065	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4066	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4067
4068	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
4069	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
4070	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
4071	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4072	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4073
4074	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
4075	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
4076	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
4077	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4078	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4079
4080	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
4081	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
4082	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
4083	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4084	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4085
4086	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
4087	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
4088	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
4089	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4090	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4091
4092	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
4093	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
4094	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
4095	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4096	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4097
4098	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
4099	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
4100	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
4101	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4102	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4103
4104	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
4105	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
4106	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
4107	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4108	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4109
4110	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
4111	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
4112	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
4113	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4114	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4115
4116	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
4117	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
4118	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
4119	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4120	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4121
4122	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
4123	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
4124	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
4125	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4126	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4127
4128	IEM_DECL_IMPL_DEF(void, iemAImpl_shufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
4129	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
4130	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
4131	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
4132	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
4133
4134	IEM_DECL_IMPL_DEF(void, iemAImpl_shufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
4135	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
4136	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
4137	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
4138	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
4139
4140	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
4141	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64_fallback,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
4142
4143	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
4144	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
4145	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
4146	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
4147	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
4148
4149	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
4150	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
4151	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
4152	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
4153	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
4154
4155
4156	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
4157	typedef FNIEMAIMPLMEDIAOPTF2U128IMM8 *PFNIEMAIMPLMEDIAOPTF2U128IMM8;
4158	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
4159	typedef FNIEMAIMPLMEDIAOPTF2U256IMM8 *PFNIEMAIMPLMEDIAOPTF2U256IMM8;
4160	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
4161	typedef FNIEMAIMPLMEDIAOPTF3U128IMM8 *PFNIEMAIMPLMEDIAOPTF3U128IMM8;
4162	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
4163	typedef FNIEMAIMPLMEDIAOPTF3U256IMM8 *PFNIEMAIMPLMEDIAOPTF3U256IMM8;
4164
4165	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_palignr_u128, iemAImpl_palignr_u128_fallback;
4166	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pblendw_u128, iemAImpl_pblendw_u128_fallback;
4167	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendps_u128, iemAImpl_blendps_u128_fallback;
4168	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendpd_u128, iemAImpl_blendpd_u128_fallback;
4169
4170	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpalignr_u128, iemAImpl_vpalignr_u128_fallback;
4171	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendw_u128, iemAImpl_vpblendw_u128_fallback;
4172	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendd_u128, iemAImpl_vpblendd_u128_fallback;
4173	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendps_u128, iemAImpl_vblendps_u128_fallback;
4174	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendpd_u128, iemAImpl_vblendpd_u128_fallback;
4175
4176	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpalignr_u256, iemAImpl_vpalignr_u256_fallback;
4177	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendw_u256, iemAImpl_vpblendw_u256_fallback;
4178	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendd_u256, iemAImpl_vpblendd_u256_fallback;
4179	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendps_u256, iemAImpl_vblendps_u256_fallback;
4180	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendpd_u256, iemAImpl_vblendpd_u256_fallback;
4181	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2i128_u256, iemAImpl_vperm2i128_u256_fallback;
4182	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2f128_u256, iemAImpl_vperm2f128_u256_fallback;
4183
4184	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesimc_u128, iemAImpl_aesimc_u128_fallback;
4185	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenc_u128, iemAImpl_aesenc_u128_fallback;
4186	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenclast_u128, iemAImpl_aesenclast_u128_fallback;
4187	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdec_u128, iemAImpl_aesdec_u128_fallback;
4188	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdeclast_u128, iemAImpl_aesdeclast_u128_fallback;
4189
4190	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesimc_u128, iemAImpl_vaesimc_u128_fallback;
4191	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vaesenc_u128, iemAImpl_vaesenc_u128_fallback;
4192	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vaesenclast_u128, iemAImpl_vaesenclast_u128_fallback;
4193	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vaesdec_u128, iemAImpl_vaesdec_u128_fallback;
4194	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vaesdeclast_u128, iemAImpl_vaesdeclast_u128_fallback;
4195
4196	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_aeskeygenassist_u128, iemAImpl_aeskeygenassist_u128_fallback;
4197
4198	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_vaeskeygenassist_u128, iemAImpl_vaeskeygenassist_u128_fallback;
4199
4200	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1nexte_u128, iemAImpl_sha1nexte_u128_fallback;
4201	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg1_u128, iemAImpl_sha1msg1_u128_fallback;
4202	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg2_u128, iemAImpl_sha1msg2_u128_fallback;
4203	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg1_u128, iemAImpl_sha256msg1_u128_fallback;
4204	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg2_u128, iemAImpl_sha256msg2_u128_fallback;
4205	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_sha1rnds4_u128, iemAImpl_sha1rnds4_u128_fallback;
4206	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
4207	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
4208
4209	FNIEMAIMPLMEDIAOPTF2U256IMM8 iemAImpl_vpermq_u256, iemAImpl_vpermq_u256_fallback;
4210	FNIEMAIMPLMEDIAOPTF2U256IMM8 iemAImpl_vpermpd_u256, iemAImpl_vpermpd_u256_fallback;
4211
4212	typedef struct IEMPCMPISTRXSRC
4213	{
4214	RTUINT128U uSrc1;
4215	RTUINT128U uSrc2;
4216	} IEMPCMPISTRXSRC;
4217	typedef IEMPCMPISTRXSRC *PIEMPCMPISTRXSRC;
4218	typedef const IEMPCMPISTRXSRC *PCIEMPCMPISTRXSRC;
4219
4220	typedef struct IEMPCMPESTRXSRC
4221	{
4222	RTUINT128U uSrc1;
4223	RTUINT128U uSrc2;
4224	uint64_t u64Rax;
4225	uint64_t u64Rdx;
4226	} IEMPCMPESTRXSRC;
4227	typedef IEMPCMPESTRXSRC *PIEMPCMPESTRXSRC;
4228	typedef const IEMPCMPESTRXSRC *PCIEMPCMPESTRXSRC;
4229
4230	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLPCMPISTRIU128IMM8,(uint32_t *pEFlags, PCRTUINT128U pSrc1, PCRTUINT128U pSrc2, uint8_t bEvil));
4231	typedef FNIEMAIMPLPCMPISTRIU128IMM8 *PFNIEMAIMPLPCMPISTRIU128IMM8;
4232	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRIU128IMM8,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
4233	typedef FNIEMAIMPLPCMPESTRIU128IMM8 *PFNIEMAIMPLPCMPESTRIU128IMM8;
4234
4235	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPISTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
4236	typedef FNIEMAIMPLPCMPISTRMU128IMM8 *PFNIEMAIMPLPCMPISTRMU128IMM8;
4237	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
4238	typedef FNIEMAIMPLPCMPESTRMU128IMM8 *PFNIEMAIMPLPCMPESTRMU128IMM8;
4239
4240	FNIEMAIMPLPCMPISTRIU128IMM8 iemAImpl_pcmpistri_u128, iemAImpl_pcmpistri_u128_fallback;
4241	FNIEMAIMPLPCMPESTRIU128IMM8 iemAImpl_pcmpestri_u128, iemAImpl_pcmpestri_u128_fallback;
4242	FNIEMAIMPLPCMPISTRMU128IMM8 iemAImpl_pcmpistrm_u128, iemAImpl_pcmpistrm_u128_fallback;
4243	FNIEMAIMPLPCMPESTRMU128IMM8 iemAImpl_pcmpestrm_u128, iemAImpl_pcmpestrm_u128_fallback;
4244	FNIEMAIMPLPCMPISTRIU128IMM8 iemAImpl_vpcmpistri_u128, iemAImpl_vpcmpistri_u128_fallback;
4245	FNIEMAIMPLPCMPESTRIU128IMM8 iemAImpl_vpcmpestri_u128, iemAImpl_vpcmpestri_u128_fallback;
4246	FNIEMAIMPLPCMPISTRMU128IMM8 iemAImpl_vpcmpistrm_u128, iemAImpl_vpcmpistrm_u128_fallback;
4247	FNIEMAIMPLPCMPESTRMU128IMM8 iemAImpl_vpcmpestrm_u128, iemAImpl_vpcmpestrm_u128_fallback;
4248
4249
4250	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pclmulqdq_u128, iemAImpl_pclmulqdq_u128_fallback;
4251	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpclmulqdq_u128, iemAImpl_vpclmulqdq_u128_fallback;
4252
4253	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_mpsadbw_u128, iemAImpl_mpsadbw_u128_fallback;
4254	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vmpsadbw_u128, iemAImpl_vmpsadbw_u128_fallback;
4255	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vmpsadbw_u256, iemAImpl_vmpsadbw_u256_fallback;
4256
4257	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsllw_imm_u128, iemAImpl_vpsllw_imm_u128_fallback;
4258	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsllw_imm_u256, iemAImpl_vpsllw_imm_u256_fallback;
4259	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpslld_imm_u128, iemAImpl_vpslld_imm_u128_fallback;
4260	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpslld_imm_u256, iemAImpl_vpslld_imm_u256_fallback;
4261	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsllq_imm_u128, iemAImpl_vpsllq_imm_u128_fallback;
4262	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsllq_imm_u256, iemAImpl_vpsllq_imm_u256_fallback;
4263	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
4264	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
4265	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
4266	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
4267
4268	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsraw_imm_u128, iemAImpl_vpsraw_imm_u128_fallback;
4269	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsraw_imm_u256, iemAImpl_vpsraw_imm_u256_fallback;
4270	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrad_imm_u128, iemAImpl_vpsrad_imm_u128_fallback;
4271	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrad_imm_u256, iemAImpl_vpsrad_imm_u256_fallback;
4272
4273	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrlw_imm_u128, iemAImpl_vpsrlw_imm_u128_fallback;
4274	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrlw_imm_u256, iemAImpl_vpsrlw_imm_u256_fallback;
4275	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrld_imm_u128, iemAImpl_vpsrld_imm_u128_fallback;
4276	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrld_imm_u256, iemAImpl_vpsrld_imm_u256_fallback;
4277	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrlq_imm_u128, iemAImpl_vpsrlq_imm_u128_fallback;
4278	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrlq_imm_u256, iemAImpl_vpsrlq_imm_u256_fallback;
4279	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
4280	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
4281	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
4282	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
4283
4284	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpermilps_u128, iemAImpl_vpermilps_u128_fallback;
4285	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_vpermilps_imm_u128, iemAImpl_vpermilps_imm_u128_fallback;
4286	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpermilps_u256, iemAImpl_vpermilps_u256_fallback;
4287	FNIEMAIMPLMEDIAOPTF2U256IMM8 iemAImpl_vpermilps_imm_u256, iemAImpl_vpermilps_imm_u256_fallback;
4288
4289	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpermilpd_u128, iemAImpl_vpermilpd_u128_fallback;
4290	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_vpermilpd_imm_u128, iemAImpl_vpermilpd_imm_u128_fallback;
4291	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpermilpd_u256, iemAImpl_vpermilpd_u256_fallback;
4292	FNIEMAIMPLMEDIAOPTF2U256IMM8 iemAImpl_vpermilpd_imm_u256, iemAImpl_vpermilpd_imm_u256_fallback;
4293
4294	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllvd_u128, iemAImpl_vpsllvd_u128_fallback;
4295	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllvd_u256, iemAImpl_vpsllvd_u256_fallback;
4296	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllvq_u128, iemAImpl_vpsllvq_u128_fallback;
4297	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllvq_u256, iemAImpl_vpsllvq_u256_fallback;
4298	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsravd_u128, iemAImpl_vpsravd_u128_fallback;
4299	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsravd_u256, iemAImpl_vpsravd_u256_fallback;
4300	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlvd_u128, iemAImpl_vpsrlvd_u128_fallback;
4301	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlvd_u256, iemAImpl_vpsrlvd_u256_fallback;
4302	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlvq_u128, iemAImpl_vpsrlvq_u128_fallback;
4303	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlvq_u256, iemAImpl_vpsrlvq_u256_fallback;
4304	/** @} */
4305
4306	/** @name Media Odds and Ends
4307	* @{ */
4308	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U8,(uint32_t *puDst, uint8_t uSrc));
4309	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U16,(uint32_t *puDst, uint16_t uSrc));
4310	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U32,(uint32_t *puDst, uint32_t uSrc));
4311	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U64,(uint32_t *puDst, uint64_t uSrc));
4312	FNIEMAIMPLCR32U8 iemAImpl_crc32_u8, iemAImpl_crc32_u8_fallback;
4313	FNIEMAIMPLCR32U16 iemAImpl_crc32_u16, iemAImpl_crc32_u16_fallback;
4314	FNIEMAIMPLCR32U32 iemAImpl_crc32_u32, iemAImpl_crc32_u32_fallback;
4315	FNIEMAIMPLCR32U64 iemAImpl_crc32_u64, iemAImpl_crc32_u64_fallback;
4316
4317	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL128,(PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint32_t *pEFlags));
4318	typedef FNIEMAIMPLF2EFL128 *PFNIEMAIMPLF2EFL128;
4319	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL256,(PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint32_t *pEFlags));
4320	typedef FNIEMAIMPLF2EFL256 *PFNIEMAIMPLF2EFL256;
4321	FNIEMAIMPLF2EFL128 iemAImpl_ptest_u128;
4322	FNIEMAIMPLF2EFL256 iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback;
4323	FNIEMAIMPLF2EFL128 iemAImpl_vtestps_u128, iemAImpl_vtestps_u128_fallback;
4324	FNIEMAIMPLF2EFL256 iemAImpl_vtestps_u256, iemAImpl_vtestps_u256_fallback;
4325	FNIEMAIMPLF2EFL128 iemAImpl_vtestpd_u128, iemAImpl_vtestpd_u128_fallback;
4326	FNIEMAIMPLF2EFL256 iemAImpl_vtestpd_u256, iemAImpl_vtestpd_u256_fallback;
4327
4328	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I32U64,(uint32_t uMxCsrIn, int32_t pi32Dst, const uint64_t pu64Src)); /* pu64Src is a double precision floating point. */
4329	typedef FNIEMAIMPLSSEF2I32U64 *PFNIEMAIMPLSSEF2I32U64;
4330	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I64U64,(uint32_t uMxCsrIn, int64_t pi64Dst, const uint64_t pu64Src)); /* pu64Src is a double precision floating point. */
4331	typedef FNIEMAIMPLSSEF2I64U64 *PFNIEMAIMPLSSEF2I64U64;
4332	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I32U32,(uint32_t uMxCsrIn, int32_t pi32Dst, const uint32_t pu32Src)); /* pu32Src is a single precision floating point. */
4333	typedef FNIEMAIMPLSSEF2I32U32 *PFNIEMAIMPLSSEF2I32U32;
4334	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I64U32,(uint32_t uMxCsrIn, int64_t pi64Dst, const uint32_t pu32Src)); /* pu32Src is a single precision floating point. */
4335	typedef FNIEMAIMPLSSEF2I64U32 *PFNIEMAIMPLSSEF2I64U32;
4336	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I32R32,(uint32_t uMxCsrIn, int32_t *pi32Dst, PCRTFLOAT32U pr32Src));
4337	typedef FNIEMAIMPLSSEF2I32R32 *PFNIEMAIMPLSSEF2I32R32;
4338	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I64R32,(uint32_t uMxCsrIn, int64_t *pi64Dst, PCRTFLOAT32U pr32Src));
4339	typedef FNIEMAIMPLSSEF2I64R32 *PFNIEMAIMPLSSEF2I64R32;
4340	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I32R64,(uint32_t uMxCsrIn, int32_t *pi32Dst, PCRTFLOAT64U pr64Src));
4341	typedef FNIEMAIMPLSSEF2I32R64 *PFNIEMAIMPLSSEF2I32R64;
4342	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I64R64,(uint32_t uMxCsrIn, int64_t *pi64Dst, PCRTFLOAT64U pr64Src));
4343	typedef FNIEMAIMPLSSEF2I64R64 *PFNIEMAIMPLSSEF2I64R64;
4344
4345	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvttsd2si_i32_r64;
4346	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvtsd2si_i32_r64;
4347
4348	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvttsd2si_i64_r64;
4349	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvtsd2si_i64_r64;
4350
4351	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvttss2si_i32_r32;
4352	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvtss2si_i32_r32;
4353
4354	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvttss2si_i64_r32;
4355	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvtss2si_i64_r32;
4356
4357	FNIEMAIMPLSSEF2I32R32 iemAImpl_vcvttss2si_i32_r32, iemAImpl_vcvttss2si_i32_r32_fallback;
4358	FNIEMAIMPLSSEF2I64R32 iemAImpl_vcvttss2si_i64_r32, iemAImpl_vcvttss2si_i64_r32_fallback;
4359	FNIEMAIMPLSSEF2I32R32 iemAImpl_vcvtss2si_i32_r32, iemAImpl_vcvtss2si_i32_r32_fallback;
4360	FNIEMAIMPLSSEF2I64R32 iemAImpl_vcvtss2si_i64_r32, iemAImpl_vcvtss2si_i64_r32_fallback;
4361
4362	FNIEMAIMPLSSEF2I32R64 iemAImpl_vcvttss2si_i32_r64, iemAImpl_vcvttss2si_i32_r64_fallback;
4363	FNIEMAIMPLSSEF2I64R64 iemAImpl_vcvttss2si_i64_r64, iemAImpl_vcvttss2si_i64_r64_fallback;
4364	FNIEMAIMPLSSEF2I32R64 iemAImpl_vcvtss2si_i32_r64, iemAImpl_vcvtss2si_i32_r64_fallback;
4365	FNIEMAIMPLSSEF2I64R64 iemAImpl_vcvtss2si_i64_r64, iemAImpl_vcvtss2si_i64_r64_fallback;
4366
4367	FNIEMAIMPLSSEF2I32R32 iemAImpl_vcvttsd2si_i32_r32, iemAImpl_vcvttsd2si_i32_r32_fallback;
4368	FNIEMAIMPLSSEF2I64R32 iemAImpl_vcvttsd2si_i64_r32, iemAImpl_vcvttsd2si_i64_r32_fallback;
4369	FNIEMAIMPLSSEF2I32R32 iemAImpl_vcvtsd2si_i32_r32, iemAImpl_vcvtsd2si_i32_r32_fallback;
4370	FNIEMAIMPLSSEF2I64R32 iemAImpl_vcvtsd2si_i64_r32, iemAImpl_vcvtsd2si_i64_r32_fallback;
4371
4372	FNIEMAIMPLSSEF2I32R64 iemAImpl_vcvttsd2si_i32_r64, iemAImpl_vcvttsd2si_i32_r64_fallback;
4373	FNIEMAIMPLSSEF2I64R64 iemAImpl_vcvttsd2si_i64_r64, iemAImpl_vcvttsd2si_i64_r64_fallback;
4374	FNIEMAIMPLSSEF2I32R64 iemAImpl_vcvtsd2si_i32_r64, iemAImpl_vcvtsd2si_i32_r64_fallback;
4375	FNIEMAIMPLSSEF2I64R64 iemAImpl_vcvtsd2si_i64_r64, iemAImpl_vcvtsd2si_i64_r64_fallback;
4376
4377	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R32I32,(uint32_t uMxCsrIn, PRTFLOAT32U pr32Dst, const int32_t *pi32Src));
4378	typedef FNIEMAIMPLSSEF2R32I32 *PFNIEMAIMPLSSEF2R32I32;
4379	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R32I64,(uint32_t uMxCsrIn, PRTFLOAT32U pr32Dst, const int64_t *pi64Src));
4380	typedef FNIEMAIMPLSSEF2R32I64 *PFNIEMAIMPLSSEF2R32I64;
4381
4382	FNIEMAIMPLSSEF2R32I32 iemAImpl_cvtsi2ss_r32_i32;
4383	FNIEMAIMPLSSEF2R32I64 iemAImpl_cvtsi2ss_r32_i64;
4384
4385	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLAVXF3XMMI32,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc, const int32_t *pi32Src));
4386	typedef FNIEMAIMPLAVXF3XMMI32 *PFNIEMAIMPLAVXF3XMMI32;
4387	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLAVXF3XMMI64,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc, const int64_t *pi64Src));
4388	typedef FNIEMAIMPLAVXF3XMMI64 *PFNIEMAIMPLAVXF3XMMI64;
4389
4390	FNIEMAIMPLAVXF3XMMI32 iemAImpl_vcvtsi2ss_u128_i32, iemAImpl_vcvtsi2ss_u128_i32_fallback;
4391	FNIEMAIMPLAVXF3XMMI64 iemAImpl_vcvtsi2ss_u128_i64, iemAImpl_vcvtsi2ss_u128_i64_fallback;
4392
4393
4394	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R64I32,(uint32_t uMxCsrIn, PRTFLOAT64U pr64Dst, const int32_t *pi32Src));
4395	typedef FNIEMAIMPLSSEF2R64I32 *PFNIEMAIMPLSSEF2R64I32;
4396	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R64I64,(uint32_t uMxCsrIn, PRTFLOAT64U pr64Dst, const int64_t *pi64Src));
4397	typedef FNIEMAIMPLSSEF2R64I64 *PFNIEMAIMPLSSEF2R64I64;
4398
4399	FNIEMAIMPLSSEF2R64I32 iemAImpl_cvtsi2sd_r64_i32;
4400	FNIEMAIMPLSSEF2R64I64 iemAImpl_cvtsi2sd_r64_i64;
4401
4402	FNIEMAIMPLAVXF3XMMI32 iemAImpl_vcvtsi2sd_u128_i32, iemAImpl_vcvtsi2sd_u128_i32_fallback;
4403	FNIEMAIMPLAVXF3XMMI64 iemAImpl_vcvtsi2sd_u128_i64, iemAImpl_vcvtsi2sd_u128_i64_fallback;
4404
4405	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtps2pd_u128_u64,(uint32_t uMxCsrIn, PX86XMMREG puDst, const uint64_t pu64Src)); / Actually two single precision floating point values. */
4406	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtps2pd_u128_u64_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, const uint64_t pu64Src)); / Actually two single precision floating point values. */
4407	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtps2pd_u256_u128,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86XMMREG puSrc));
4408	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtps2pd_u256_u128_fallback,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86XMMREG puSrc));
4409
4410
4411	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtdq2pd_u128_u64,(uint32_t uMxCsrIn, PX86XMMREG puDst, const uint64_t pu64Src)); / Actually two single precision floating point values. */
4412	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtdq2pd_u128_u64_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, const uint64_t pu64Src)); / Actually two single precision floating point values. */
4413	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtdq2pd_u256_u128,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86XMMREG puSrc));
4414	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtdq2pd_u256_u128_fallback,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86XMMREG puSrc));
4415
4416
4417	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLF2EFLMXCSRR32R32,(uint32_t uMxCsrIn, uint32_t *pfEFlags, RTFLOAT32U uSrc1, RTFLOAT32U uSrc2));
4418	typedef FNIEMAIMPLF2EFLMXCSRR32R32 *PFNIEMAIMPLF2EFLMXCSRR32R32;
4419
4420	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLF2EFLMXCSRR64R64,(uint32_t uMxCsrIn, uint32_t *pfEFlags, RTFLOAT64U uSrc1, RTFLOAT64U uSrc2));
4421	typedef FNIEMAIMPLF2EFLMXCSRR64R64 *PFNIEMAIMPLF2EFLMXCSRR64R64;
4422
4423	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_ucomiss_u128;
4424	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback;
4425
4426	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_ucomisd_u128;
4427	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback;
4428
4429	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_comiss_u128;
4430	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback;
4431
4432	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_comisd_u128;
4433	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback;
4434
4435
4436	typedef struct IEMMEDIAF2XMMSRC
4437	{
4438	X86XMMREG uSrc1;
4439	X86XMMREG uSrc2;
4440	} IEMMEDIAF2XMMSRC;
4441	typedef IEMMEDIAF2XMMSRC *PIEMMEDIAF2XMMSRC;
4442	typedef const IEMMEDIAF2XMMSRC *PCIEMMEDIAF2XMMSRC;
4443
4444
4445	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF3XMMIMM8,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCIEMMEDIAF2XMMSRC puSrc, uint8_t bEvil));
4446	typedef FNIEMAIMPLMEDIAF3XMMIMM8 *PFNIEMAIMPLMEDIAF3XMMIMM8;
4447
4448
4449	typedef struct IEMMEDIAF2YMMSRC
4450	{
4451	X86YMMREG uSrc1;
4452	X86YMMREG uSrc2;
4453	} IEMMEDIAF2YMMSRC;
4454	typedef IEMMEDIAF2YMMSRC *PIEMMEDIAF2YMMSRC;
4455	typedef const IEMMEDIAF2YMMSRC *PCIEMMEDIAF2YMMSRC;
4456
4457
4458	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF3YMMIMM8,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCIEMMEDIAF2YMMSRC puSrc, uint8_t bEvil));
4459	typedef FNIEMAIMPLMEDIAF3YMMIMM8 *PFNIEMAIMPLMEDIAF3YMMIMM8;
4460
4461
4462	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_cmpps_u128;
4463	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_cmppd_u128;
4464	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_cmpss_u128;
4465	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_cmpsd_u128;
4466
4467	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vcmpps_u128, iemAImpl_vcmpps_u128_fallback;
4468	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vcmppd_u128, iemAImpl_vcmppd_u128_fallback;
4469	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vcmpss_u128, iemAImpl_vcmpss_u128_fallback;
4470	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vcmpsd_u128, iemAImpl_vcmpsd_u128_fallback;
4471
4472	FNIEMAIMPLMEDIAF3YMMIMM8 iemAImpl_vcmpps_u256, iemAImpl_vcmpps_u256_fallback;
4473	FNIEMAIMPLMEDIAF3YMMIMM8 iemAImpl_vcmppd_u256, iemAImpl_vcmppd_u256_fallback;
4474
4475	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_roundss_u128;
4476	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_roundsd_u128;
4477
4478	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_dpps_u128, iemAImpl_dpps_u128_fallback;
4479	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_dppd_u128, iemAImpl_dppd_u128_fallback;
4480
4481
4482	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF2U128IMM8,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc, uint8_t bEvil));
4483	typedef FNIEMAIMPLMEDIAF2U128IMM8 *PFNIEMAIMPLMEDIAF2U128IMM8;
4484
4485
4486	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF2U256IMM8,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86YMMREG puSrc, uint8_t bEvil));
4487	typedef FNIEMAIMPLMEDIAF2U256IMM8 *PFNIEMAIMPLMEDIAF2U256IMM8;
4488
4489
4490	FNIEMAIMPLMEDIAF2U128IMM8 iemAImpl_roundps_u128, iemAImpl_roundps_u128_fallback;
4491	FNIEMAIMPLMEDIAF2U128IMM8 iemAImpl_roundpd_u128, iemAImpl_roundpd_u128_fallback;
4492
4493	FNIEMAIMPLMEDIAF2U128IMM8 iemAImpl_vroundps_u128, iemAImpl_vroundps_u128_fallback;
4494	FNIEMAIMPLMEDIAF2U128IMM8 iemAImpl_vroundpd_u128, iemAImpl_vroundpd_u128_fallback;
4495
4496	FNIEMAIMPLMEDIAF2U256IMM8 iemAImpl_vroundps_u256, iemAImpl_vroundps_u256_fallback;
4497	FNIEMAIMPLMEDIAF2U256IMM8 iemAImpl_vroundpd_u256, iemAImpl_vroundpd_u256_fallback;
4498
4499	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vroundss_u128, iemAImpl_vroundss_u128_fallback;
4500	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vroundsd_u128, iemAImpl_vroundsd_u128_fallback;
4501
4502	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vdpps_u128, iemAImpl_vdpps_u128_fallback;
4503	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vdppd_u128, iemAImpl_vdppd_u128_fallback;
4504
4505	FNIEMAIMPLMEDIAF3YMMIMM8 iemAImpl_vdpps_u256, iemAImpl_vdpps_u256_fallback;
4506
4507
4508	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRU64U128,(uint32_t fMxCsrIn, uint64_t *pu64Dst, PCX86XMMREG pSrc));
4509	typedef FNIEMAIMPLMXCSRU64U128 *PFNIEMAIMPLMXCSRU64U128;
4510
4511	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvtpd2pi_u128;
4512	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvttpd2pi_u128;
4513
4514	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRU128U64,(uint32_t fMxCsrIn, PX86XMMREG pDst, uint64_t u64Src));
4515	typedef FNIEMAIMPLMXCSRU128U64 *PFNIEMAIMPLMXCSRU128U64;
4516
4517	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2ps_u128;
4518	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2pd_u128;
4519
4520	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRU64U64,(uint32_t fMxCsrIn, uint64_t *pu64Dst, uint64_t u64Src));
4521	typedef FNIEMAIMPLMXCSRU64U64 *PFNIEMAIMPLMXCSRU64U64;
4522
4523	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvtps2pi_u128;
4524	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvttps2pi_u128;
4525
4526	/** @} */
4527
4528
4529	/** @name Function tables.
4530	* @{
4531	*/
4532
4533	/**
4534	* Function table for a binary operator providing implementation based on
4535	* operand size.
4536	*/
4537	typedef struct IEMOPBINSIZES
4538	{
4539	PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
4540	PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
4541	PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
4542	PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
4543	} IEMOPBINSIZES;
4544	/** Pointer to a binary operator function table. */
4545	typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
4546
4547
4548	/**
4549	* Function table for a unary operator providing implementation based on
4550	* operand size.
4551	*/
4552	typedef struct IEMOPUNARYSIZES
4553	{
4554	PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
4555	PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
4556	PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
4557	PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
4558	} IEMOPUNARYSIZES;
4559	/** Pointer to a unary operator function table. */
4560	typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
4561
4562
4563	/**
4564	* Function table for a shift operator providing implementation based on
4565	* operand size.
4566	*/
4567	typedef struct IEMOPSHIFTSIZES
4568	{
4569	PFNIEMAIMPLSHIFTU8 pfnNormalU8;
4570	PFNIEMAIMPLSHIFTU16 pfnNormalU16;
4571	PFNIEMAIMPLSHIFTU32 pfnNormalU32;
4572	PFNIEMAIMPLSHIFTU64 pfnNormalU64;
4573	} IEMOPSHIFTSIZES;
4574	/** Pointer to a shift operator function table. */
4575	typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
4576
4577
4578	/**
4579	* Function table for a multiplication or division operation.
4580	*/
4581	typedef struct IEMOPMULDIVSIZES
4582	{
4583	PFNIEMAIMPLMULDIVU8 pfnU8;
4584	PFNIEMAIMPLMULDIVU16 pfnU16;
4585	PFNIEMAIMPLMULDIVU32 pfnU32;
4586	PFNIEMAIMPLMULDIVU64 pfnU64;
4587	} IEMOPMULDIVSIZES;
4588	/** Pointer to a multiplication or division operation function table. */
4589	typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
4590
4591
4592	/**
4593	* Function table for a double precision shift operator providing implementation
4594	* based on operand size.
4595	*/
4596	typedef struct IEMOPSHIFTDBLSIZES
4597	{
4598	PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
4599	PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
4600	PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
4601	} IEMOPSHIFTDBLSIZES;
4602	/** Pointer to a double precision shift function table. */
4603	typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
4604
4605
4606	/**
4607	* Function table for media instruction taking two full sized media source
4608	* registers and one full sized destination register (AVX).
4609	*/
4610	typedef struct IEMOPMEDIAF3
4611	{
4612	PFNIEMAIMPLMEDIAF3U128 pfnU128;
4613	PFNIEMAIMPLMEDIAF3U256 pfnU256;
4614	} IEMOPMEDIAF3;
4615	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
4616	typedef IEMOPMEDIAF3 const *PCIEMOPMEDIAF3;
4617
4618	/** @def IEMOPMEDIAF3_INIT_VARS_EX
4619	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4620	* given functions as initializers. For use in AVX functions where a pair of
4621	* functions are only used once and the function table need not be public. */
4622	#ifndef TST_IEM_CHECK_MC
4623	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4624	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4625	static IEMOPMEDIAF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4626	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4627	# else
4628	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4629	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4630	# endif
4631	#else
4632	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4633	#endif
4634	/** @def IEMOPMEDIAF3_INIT_VARS
4635	* Generate AVX function tables for the @a a_InstrNm instruction.
4636	* @sa IEMOPMEDIAF3_INIT_VARS_EX */
4637	#define IEMOPMEDIAF3_INIT_VARS(a_InstrNm) \
4638	IEMOPMEDIAF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4639	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4640
4641
4642	/**
4643	* Function table for media instruction taking one full sized media source
4644	* registers and one full sized destination register (AVX).
4645	*/
4646	typedef struct IEMOPMEDIAF2
4647	{
4648	PFNIEMAIMPLMEDIAF2U128 pfnU128;
4649	PFNIEMAIMPLMEDIAF2U256 pfnU256;
4650	} IEMOPMEDIAF2;
4651	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
4652	typedef IEMOPMEDIAF2 const *PCIEMOPMEDIAF2;
4653
4654	/** @def IEMOPMEDIAF2_INIT_VARS_EX
4655	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4656	* given functions as initializers. For use in AVX functions where a pair of
4657	* functions are only used once and the function table need not be public. */
4658	#ifndef TST_IEM_CHECK_MC
4659	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4660	# define IEMOPMEDIAF2_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4661	static IEMOPMEDIAF2 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4662	static IEMOPMEDIAF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4663	# else
4664	# define IEMOPMEDIAF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4665	static IEMOPMEDIAF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4666	# endif
4667	#else
4668	# define IEMOPMEDIAF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4669	#endif
4670	/** @def IEMOPMEDIAF2_INIT_VARS
4671	* Generate AVX function tables for the @a a_InstrNm instruction.
4672	* @sa IEMOPMEDIAF2_INIT_VARS_EX */
4673	#define IEMOPMEDIAF2_INIT_VARS(a_InstrNm) \
4674	IEMOPMEDIAF2_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4675	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4676
4677
4678	/**
4679	* Function table for media instruction taking two full sized media source
4680	* registers and one full sized destination register, but no additional state
4681	* (AVX).
4682	*/
4683	typedef struct IEMOPMEDIAOPTF3
4684	{
4685	PFNIEMAIMPLMEDIAOPTF3U128 pfnU128;
4686	PFNIEMAIMPLMEDIAOPTF3U256 pfnU256;
4687	} IEMOPMEDIAOPTF3;
4688	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
4689	typedef IEMOPMEDIAOPTF3 const *PCIEMOPMEDIAOPTF3;
4690
4691	/** @def IEMOPMEDIAOPTF3_INIT_VARS_EX
4692	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4693	* given functions as initializers. For use in AVX functions where a pair of
4694	* functions are only used once and the function table need not be public. */
4695	#ifndef TST_IEM_CHECK_MC
4696	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4697	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4698	static IEMOPMEDIAOPTF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4699	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4700	# else
4701	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4702	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4703	# endif
4704	#else
4705	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4706	#endif
4707	/** @def IEMOPMEDIAOPTF3_INIT_VARS
4708	* Generate AVX function tables for the @a a_InstrNm instruction.
4709	* @sa IEMOPMEDIAOPTF3_INIT_VARS_EX */
4710	#define IEMOPMEDIAOPTF3_INIT_VARS(a_InstrNm) \
4711	IEMOPMEDIAOPTF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4712	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4713
4714	/**
4715	* Function table for media instruction taking one full sized media source
4716	* registers and one full sized destination register, but no additional state
4717	* (AVX).
4718	*/
4719	typedef struct IEMOPMEDIAOPTF2
4720	{
4721	PFNIEMAIMPLMEDIAOPTF2U128 pfnU128;
4722	PFNIEMAIMPLMEDIAOPTF2U256 pfnU256;
4723	} IEMOPMEDIAOPTF2;
4724	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
4725	typedef IEMOPMEDIAOPTF2 const *PCIEMOPMEDIAOPTF2;
4726
4727	/** @def IEMOPMEDIAOPTF2_INIT_VARS_EX
4728	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4729	* given functions as initializers. For use in AVX functions where a pair of
4730	* functions are only used once and the function table need not be public. */
4731	#ifndef TST_IEM_CHECK_MC
4732	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4733	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4734	static IEMOPMEDIAOPTF2 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4735	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4736	# else
4737	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4738	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4739	# endif
4740	#else
4741	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4742	#endif
4743	/** @def IEMOPMEDIAOPTF2_INIT_VARS
4744	* Generate AVX function tables for the @a a_InstrNm instruction.
4745	* @sa IEMOPMEDIAOPTF2_INIT_VARS_EX */
4746	#define IEMOPMEDIAOPTF2_INIT_VARS(a_InstrNm) \
4747	IEMOPMEDIAOPTF2_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4748	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4749
4750
4751	/**
4752	* Function table for media instruction taking one full sized media source
4753	* register and one full sized destination register and an 8-bit immediate (AVX).
4754	*/
4755	typedef struct IEMOPMEDIAF2IMM8
4756	{
4757	PFNIEMAIMPLMEDIAF2U128IMM8 pfnU128;
4758	PFNIEMAIMPLMEDIAF2U256IMM8 pfnU256;
4759	} IEMOPMEDIAF2IMM8;
4760	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
4761	typedef IEMOPMEDIAF2IMM8 const *PCIEMOPMEDIAF2IMM8;
4762
4763	/** @def IEMOPMEDIAF2IMM8_INIT_VARS_EX
4764	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4765	* given functions as initializers. For use in AVX functions where a pair of
4766	* functions are only used once and the function table need not be public. */
4767	#ifndef TST_IEM_CHECK_MC
4768	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4769	# define IEMOPMEDIAF2IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4770	static IEMOPMEDIAF2IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4771	static IEMOPMEDIAF2IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4772	# else
4773	# define IEMOPMEDIAF2IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4774	static IEMOPMEDIAF2IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4775	# endif
4776	#else
4777	# define IEMOPMEDIAF2IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4778	#endif
4779	/** @def IEMOPMEDIAF2IMM8_INIT_VARS
4780	* Generate AVX function tables for the @a a_InstrNm instruction.
4781	* @sa IEMOPMEDIAF2IMM8_INIT_VARS_EX */
4782	#define IEMOPMEDIAF2IMM8_INIT_VARS(a_InstrNm) \
4783	IEMOPMEDIAF2IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4784	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4785
4786
4787	/**
4788	* Function table for media instruction taking one full sized media source
4789	* register and one full sized destination register and an 8-bit immediate, but no additional state
4790	* (AVX).
4791	*/
4792	typedef struct IEMOPMEDIAOPTF2IMM8
4793	{
4794	PFNIEMAIMPLMEDIAOPTF2U128IMM8 pfnU128;
4795	PFNIEMAIMPLMEDIAOPTF2U256IMM8 pfnU256;
4796	} IEMOPMEDIAOPTF2IMM8;
4797	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
4798	typedef IEMOPMEDIAOPTF2IMM8 const *PCIEMOPMEDIAOPTF2IMM8;
4799
4800	/** @def IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX
4801	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4802	* given functions as initializers. For use in AVX functions where a pair of
4803	* functions are only used once and the function table need not be public. */
4804	#ifndef TST_IEM_CHECK_MC
4805	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4806	# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4807	static IEMOPMEDIAOPTF2IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4808	static IEMOPMEDIAOPTF2IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4809	# else
4810	# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4811	static IEMOPMEDIAOPTF2IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4812	# endif
4813	#else
4814	# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4815	#endif
4816	/** @def IEMOPMEDIAOPTF2IMM8_INIT_VARS
4817	* Generate AVX function tables for the @a a_InstrNm instruction.
4818	* @sa IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX */
4819	#define IEMOPMEDIAOPTF2IMM8_INIT_VARS(a_InstrNm) \
4820	IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u256),\
4821	RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u256_fallback))
4822
4823	/**
4824	* Function table for media instruction taking two full sized media source
4825	* registers and one full sized destination register and an 8-bit immediate, but no additional state
4826	* (AVX).
4827	*/
4828	typedef struct IEMOPMEDIAOPTF3IMM8
4829	{
4830	PFNIEMAIMPLMEDIAOPTF3U128IMM8 pfnU128;
4831	PFNIEMAIMPLMEDIAOPTF3U256IMM8 pfnU256;
4832	} IEMOPMEDIAOPTF3IMM8;
4833	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
4834	typedef IEMOPMEDIAOPTF3IMM8 const *PCIEMOPMEDIAOPTF3IMM8;
4835
4836	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX
4837	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4838	* given functions as initializers. For use in AVX functions where a pair of
4839	* functions are only used once and the function table need not be public. */
4840	#ifndef TST_IEM_CHECK_MC
4841	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4842	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4843	static IEMOPMEDIAOPTF3IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4844	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4845	# else
4846	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4847	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4848	# endif
4849	#else
4850	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4851	#endif
4852	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS
4853	* Generate AVX function tables for the @a a_InstrNm instruction.
4854	* @sa IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX */
4855	#define IEMOPMEDIAOPTF3IMM8_INIT_VARS(a_InstrNm) \
4856	IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4857	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4858	/** @} */
4859
4860
4861	/**
4862	* Function table for blend type instruction taking three full sized media source
4863	* registers and one full sized destination register, but no additional state
4864	* (AVX).
4865	*/
4866	typedef struct IEMOPBLENDOP
4867	{
4868	PFNIEMAIMPLAVXBLENDU128 pfnU128;
4869	PFNIEMAIMPLAVXBLENDU256 pfnU256;
4870	} IEMOPBLENDOP;
4871	/** Pointer to a media operation function table for 4 full sized ops (AVX). */
4872	typedef IEMOPBLENDOP const *PCIEMOPBLENDOP;
4873
4874	/** @def IEMOPBLENDOP_INIT_VARS_EX
4875	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4876	* given functions as initializers. For use in AVX functions where a pair of
4877	* functions are only used once and the function table need not be public. */
4878	#ifndef TST_IEM_CHECK_MC
4879	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4880	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4881	static IEMOPBLENDOP const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4882	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4883	# else
4884	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4885	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4886	# endif
4887	#else
4888	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4889	#endif
4890	/** @def IEMOPBLENDOP_INIT_VARS
4891	* Generate AVX function tables for the @a a_InstrNm instruction.
4892	* @sa IEMOPBLENDOP_INIT_VARS_EX */
4893	#define IEMOPBLENDOP_INIT_VARS(a_InstrNm) \
4894	IEMOPBLENDOP_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4895	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4896
4897
4898	/** @name SSE/AVX single/double precision floating point operations.
4899	* @{ */
4900	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
4901	typedef FNIEMAIMPLFPSSEF2U128 *PFNIEMAIMPLFPSSEF2U128;
4902	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128R32,(uint32_t uMxCsrIn, PX86XMMREG Result, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
4903	typedef FNIEMAIMPLFPSSEF2U128R32 *PFNIEMAIMPLFPSSEF2U128R32;
4904	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128R64,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
4905	typedef FNIEMAIMPLFPSSEF2U128R64 *PFNIEMAIMPLFPSSEF2U128R64;
4906
4907	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
4908	typedef FNIEMAIMPLFPAVXF3U128 *PFNIEMAIMPLFPAVXF3U128;
4909	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U128R32,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
4910	typedef FNIEMAIMPLFPAVXF3U128R32 *PFNIEMAIMPLFPAVXF3U128R32;
4911	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U128R64,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
4912	typedef FNIEMAIMPLFPAVXF3U128R64 *PFNIEMAIMPLFPAVXF3U128R64;
4913
4914	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U256,(uint32_t uMxCsrIn, PX86YMMREG pResult, PCX86YMMREG puSrc1, PCX86YMMREG puSrc2));
4915	typedef FNIEMAIMPLFPAVXF3U256 *PFNIEMAIMPLFPAVXF3U256;
4916
4917	FNIEMAIMPLFPSSEF2U128 iemAImpl_addps_u128;
4918	FNIEMAIMPLFPSSEF2U128 iemAImpl_addpd_u128;
4919	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulps_u128;
4920	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulpd_u128;
4921	FNIEMAIMPLFPSSEF2U128 iemAImpl_subps_u128;
4922	FNIEMAIMPLFPSSEF2U128 iemAImpl_subpd_u128;
4923	FNIEMAIMPLFPSSEF2U128 iemAImpl_minps_u128;
4924	FNIEMAIMPLFPSSEF2U128 iemAImpl_minpd_u128;
4925	FNIEMAIMPLFPSSEF2U128 iemAImpl_divps_u128;
4926	FNIEMAIMPLFPSSEF2U128 iemAImpl_divpd_u128;
4927	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxps_u128;
4928	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxpd_u128;
4929	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddps_u128;
4930	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddpd_u128;
4931	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubps_u128;
4932	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubpd_u128;
4933	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtps_u128;
4934	FNIEMAIMPLFPSSEF2U128 iemAImpl_rsqrtps_u128;
4935	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtpd_u128;
4936	FNIEMAIMPLFPSSEF2U128 iemAImpl_rcpps_u128;
4937	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubps_u128;
4938	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubpd_u128;
4939
4940	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2ps_u128;
4941	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_cvtps2pd_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, uint64_t const *pu64Src));
4942
4943	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2ps_u128;
4944	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2dq_u128;
4945	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttps2dq_u128;
4946	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttpd2dq_u128;
4947	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2pd_u128;
4948	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2dq_u128;
4949
4950	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_addss_u128_r32;
4951	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_addsd_u128_r64;
4952	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_mulss_u128_r32;
4953	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_mulsd_u128_r64;
4954	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_subss_u128_r32;
4955	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_subsd_u128_r64;
4956	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_minss_u128_r32;
4957	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_minsd_u128_r64;
4958	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_divss_u128_r32;
4959	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_divsd_u128_r64;
4960	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_maxss_u128_r32;
4961	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_maxsd_u128_r64;
4962	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_cvtss2sd_u128_r32;
4963	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_cvtsd2ss_u128_r64;
4964	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_sqrtss_u128_r32;
4965	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_sqrtsd_u128_r64;
4966	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_rsqrtss_u128_r32;
4967	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_rcpss_u128_r32;
4968
4969	FNIEMAIMPLMEDIAF3U128 iemAImpl_vaddps_u128, iemAImpl_vaddps_u128_fallback;
4970	FNIEMAIMPLMEDIAF3U128 iemAImpl_vaddpd_u128, iemAImpl_vaddpd_u128_fallback;
4971	FNIEMAIMPLMEDIAF3U128 iemAImpl_vmulps_u128, iemAImpl_vmulps_u128_fallback;
4972	FNIEMAIMPLMEDIAF3U128 iemAImpl_vmulpd_u128, iemAImpl_vmulpd_u128_fallback;
4973	FNIEMAIMPLMEDIAF3U128 iemAImpl_vsubps_u128, iemAImpl_vsubps_u128_fallback;
4974	FNIEMAIMPLMEDIAF3U128 iemAImpl_vsubpd_u128, iemAImpl_vsubpd_u128_fallback;
4975	FNIEMAIMPLMEDIAF3U128 iemAImpl_vminps_u128, iemAImpl_vminps_u128_fallback;
4976	FNIEMAIMPLMEDIAF3U128 iemAImpl_vminpd_u128, iemAImpl_vminpd_u128_fallback;
4977	FNIEMAIMPLMEDIAF3U128 iemAImpl_vdivps_u128, iemAImpl_vdivps_u128_fallback;
4978	FNIEMAIMPLMEDIAF3U128 iemAImpl_vdivpd_u128, iemAImpl_vdivpd_u128_fallback;
4979	FNIEMAIMPLMEDIAF3U128 iemAImpl_vmaxps_u128, iemAImpl_vmaxps_u128_fallback;
4980	FNIEMAIMPLMEDIAF3U128 iemAImpl_vmaxpd_u128, iemAImpl_vmaxpd_u128_fallback;
4981	FNIEMAIMPLMEDIAF3U128 iemAImpl_vhaddps_u128, iemAImpl_vhaddps_u128_fallback;
4982	FNIEMAIMPLMEDIAF3U128 iemAImpl_vhaddpd_u128, iemAImpl_vhaddpd_u128_fallback;
4983	FNIEMAIMPLMEDIAF3U128 iemAImpl_vhsubps_u128, iemAImpl_vhsubps_u128_fallback;
4984	FNIEMAIMPLMEDIAF3U128 iemAImpl_vhsubpd_u128, iemAImpl_vhsubpd_u128_fallback;
4985	FNIEMAIMPLMEDIAF2U128 iemAImpl_vsqrtps_u128, iemAImpl_vsqrtps_u128_fallback;
4986	FNIEMAIMPLMEDIAF2U128 iemAImpl_vsqrtpd_u128, iemAImpl_vsqrtpd_u128_fallback;
4987	FNIEMAIMPLMEDIAF2U128 iemAImpl_vrsqrtps_u128, iemAImpl_vrsqrtps_u128_fallback;
4988	FNIEMAIMPLMEDIAF2U128 iemAImpl_vrcpps_u128, iemAImpl_vrcpps_u128_fallback;
4989	FNIEMAIMPLMEDIAF3U128 iemAImpl_vaddsubps_u128, iemAImpl_vaddsubps_u128_fallback;
4990	FNIEMAIMPLMEDIAF3U128 iemAImpl_vaddsubpd_u128, iemAImpl_vaddsubpd_u128_fallback;
4991	FNIEMAIMPLMEDIAF2U128 iemAImpl_vcvtdq2ps_u128, iemAImpl_vcvtdq2ps_u128_fallback;
4992	FNIEMAIMPLMEDIAF2U128 iemAImpl_vcvtps2dq_u128, iemAImpl_vcvtps2dq_u128_fallback;
4993	FNIEMAIMPLMEDIAF2U128 iemAImpl_vcvttps2dq_u128, iemAImpl_vcvttps2dq_u128_fallback;
4994	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2ps_u128_u128,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
4995	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2ps_u128_u128_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
4996	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvttpd2dq_u128_u128,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
4997	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvttpd2dq_u128_u128_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
4998	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2dq_u128_u128,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
4999	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2dq_u128_u128_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
5000
5001
5002	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vaddss_u128_r32, iemAImpl_vaddss_u128_r32_fallback;
5003	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vaddsd_u128_r64, iemAImpl_vaddsd_u128_r64_fallback;
5004	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmulss_u128_r32, iemAImpl_vmulss_u128_r32_fallback;
5005	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmulsd_u128_r64, iemAImpl_vmulsd_u128_r64_fallback;
5006	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsubss_u128_r32, iemAImpl_vsubss_u128_r32_fallback;
5007	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsubsd_u128_r64, iemAImpl_vsubsd_u128_r64_fallback;
5008	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vminss_u128_r32, iemAImpl_vminss_u128_r32_fallback;
5009	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vminsd_u128_r64, iemAImpl_vminsd_u128_r64_fallback;
5010	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vdivss_u128_r32, iemAImpl_vdivss_u128_r32_fallback;
5011	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vdivsd_u128_r64, iemAImpl_vdivsd_u128_r64_fallback;
5012	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmaxss_u128_r32, iemAImpl_vmaxss_u128_r32_fallback;
5013	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmaxsd_u128_r64, iemAImpl_vmaxsd_u128_r64_fallback;
5014	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsqrtss_u128_r32, iemAImpl_vsqrtss_u128_r32_fallback;
5015	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsqrtsd_u128_r64, iemAImpl_vsqrtsd_u128_r64_fallback;
5016	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vrsqrtss_u128_r32, iemAImpl_vrsqrtss_u128_r32_fallback;
5017	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vrcpss_u128_r32, iemAImpl_vrcpss_u128_r32_fallback;
5018	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vcvtss2sd_u128_r32, iemAImpl_vcvtss2sd_u128_r32_fallback;
5019	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vcvtsd2ss_u128_r64, iemAImpl_vcvtsd2ss_u128_r64_fallback;
5020
5021
5022	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddps_u256, iemAImpl_vaddps_u256_fallback;
5023	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddpd_u256, iemAImpl_vaddpd_u256_fallback;
5024	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulps_u256, iemAImpl_vmulps_u256_fallback;
5025	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulpd_u256, iemAImpl_vmulpd_u256_fallback;
5026	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubps_u256, iemAImpl_vsubps_u256_fallback;
5027	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubpd_u256, iemAImpl_vsubpd_u256_fallback;
5028	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminps_u256, iemAImpl_vminps_u256_fallback;
5029	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminpd_u256, iemAImpl_vminpd_u256_fallback;
5030	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivps_u256, iemAImpl_vdivps_u256_fallback;
5031	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivpd_u256, iemAImpl_vdivpd_u256_fallback;
5032	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxps_u256, iemAImpl_vmaxps_u256_fallback;
5033	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxpd_u256, iemAImpl_vmaxpd_u256_fallback;
5034	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddps_u256, iemAImpl_vhaddps_u256_fallback;
5035	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddpd_u256, iemAImpl_vhaddpd_u256_fallback;
5036	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubps_u256, iemAImpl_vhsubps_u256_fallback;
5037	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubpd_u256, iemAImpl_vhsubpd_u256_fallback;
5038	FNIEMAIMPLMEDIAF3U256 iemAImpl_vaddsubps_u256, iemAImpl_vaddsubps_u256_fallback;
5039	FNIEMAIMPLMEDIAF3U256 iemAImpl_vaddsubpd_u256, iemAImpl_vaddsubpd_u256_fallback;
5040	FNIEMAIMPLMEDIAF2U256 iemAImpl_vsqrtps_u256, iemAImpl_vsqrtps_u256_fallback;
5041	FNIEMAIMPLMEDIAF2U256 iemAImpl_vsqrtpd_u256, iemAImpl_vsqrtpd_u256_fallback;
5042	FNIEMAIMPLMEDIAF2U256 iemAImpl_vrsqrtps_u256, iemAImpl_vrsqrtps_u256_fallback;
5043	FNIEMAIMPLMEDIAF2U256 iemAImpl_vrcpps_u256, iemAImpl_vrcpps_u256_fallback;
5044	FNIEMAIMPLMEDIAF2U256 iemAImpl_vcvtdq2ps_u256, iemAImpl_vcvtdq2ps_u256_fallback;
5045	FNIEMAIMPLMEDIAF2U256 iemAImpl_vcvtps2dq_u256, iemAImpl_vcvtps2dq_u256_fallback;
5046	FNIEMAIMPLMEDIAF2U256 iemAImpl_vcvttps2dq_u256, iemAImpl_vcvttps2dq_u256_fallback;
5047	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2ps_u128_u256,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86YMMREG puSrc));
5048	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2ps_u128_u256_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86YMMREG puSrc));
5049	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvttpd2dq_u128_u256,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86YMMREG puSrc));
5050	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvttpd2dq_u128_u256_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86YMMREG puSrc));
5051	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2dq_u128_u256,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86YMMREG puSrc));
5052	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2dq_u128_u256_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86YMMREG puSrc));
5053	/** @} */
5054
5055	/** @name C instruction implementations for anything slightly complicated.
5056	* @{ */
5057
5058	/**
5059	* For typedef'ing or declaring a C instruction implementation function taking
5060	* no extra arguments.
5061	*
5062	* @param a_Name The name of the type.
5063	*/
5064	# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
5065	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
5066	/**
5067	* For defining a C instruction implementation function taking no extra
5068	* arguments.
5069	*
5070	* @param a_Name The name of the function
5071	*/
5072	# define IEM_CIMPL_DEF_0(a_Name) \
5073	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
5074	/**
5075	* Prototype version of IEM_CIMPL_DEF_0.
5076	*/
5077	# define IEM_CIMPL_PROTO_0(a_Name) \
5078	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
5079	/**
5080	* For calling a C instruction implementation function taking no extra
5081	* arguments.
5082	*
5083	* This special call macro adds default arguments to the call and allow us to
5084	* change these later.
5085	*
5086	* @param a_fn The name of the function.
5087	*/
5088	# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
5089
5090	/** Type for a C instruction implementation function taking no extra
5091	* arguments. */
5092	typedef IEM_CIMPL_DECL_TYPE_0(FNIEMCIMPL0);
5093	/** Function pointer type for a C instruction implementation function taking
5094	* no extra arguments. */
5095	typedef FNIEMCIMPL0 *PFNIEMCIMPL0;
5096
5097	/**
5098	* For typedef'ing or declaring a C instruction implementation function taking
5099	* one extra argument.
5100	*
5101	* @param a_Name The name of the type.
5102	* @param a_Type0 The argument type.
5103	* @param a_Arg0 The argument name.
5104	*/
5105	# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
5106	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
5107	/**
5108	* For defining a C instruction implementation function taking one extra
5109	* argument.
5110	*
5111	* @param a_Name The name of the function
5112	* @param a_Type0 The argument type.
5113	* @param a_Arg0 The argument name.
5114	*/
5115	# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
5116	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
5117	/**
5118	* Prototype version of IEM_CIMPL_DEF_1.
5119	*/
5120	# define IEM_CIMPL_PROTO_1(a_Name, a_Type0, a_Arg0) \
5121	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
5122	/**
5123	* For calling a C instruction implementation function taking one extra
5124	* argument.
5125	*
5126	* This special call macro adds default arguments to the call and allow us to
5127	* change these later.
5128	*
5129	* @param a_fn The name of the function.
5130	* @param a0 The name of the 1st argument.
5131	*/
5132	# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
5133
5134	/**
5135	* For typedef'ing or declaring a C instruction implementation function taking
5136	* two extra arguments.
5137	*
5138	* @param a_Name The name of the type.
5139	* @param a_Type0 The type of the 1st argument
5140	* @param a_Arg0 The name of the 1st argument.
5141	* @param a_Type1 The type of the 2nd argument.
5142	* @param a_Arg1 The name of the 2nd argument.
5143	*/
5144	# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
5145	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
5146	/**
5147	* For defining a C instruction implementation function taking two extra
5148	* arguments.
5149	*
5150	* @param a_Name The name of the function.
5151	* @param a_Type0 The type of the 1st argument
5152	* @param a_Arg0 The name of the 1st argument.
5153	* @param a_Type1 The type of the 2nd argument.
5154	* @param a_Arg1 The name of the 2nd argument.
5155	*/
5156	# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
5157	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
5158	/**
5159	* Prototype version of IEM_CIMPL_DEF_2.
5160	*/
5161	# define IEM_CIMPL_PROTO_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
5162	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
5163	/**
5164	* For calling a C instruction implementation function taking two extra
5165	* arguments.
5166	*
5167	* This special call macro adds default arguments to the call and allow us to
5168	* change these later.
5169	*
5170	* @param a_fn The name of the function.
5171	* @param a0 The name of the 1st argument.
5172	* @param a1 The name of the 2nd argument.
5173	*/
5174	# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
5175
5176	/**
5177	* For typedef'ing or declaring a C instruction implementation function taking
5178	* three extra arguments.
5179	*
5180	* @param a_Name The name of the type.
5181	* @param a_Type0 The type of the 1st argument
5182	* @param a_Arg0 The name of the 1st argument.
5183	* @param a_Type1 The type of the 2nd argument.
5184	* @param a_Arg1 The name of the 2nd argument.
5185	* @param a_Type2 The type of the 3rd argument.
5186	* @param a_Arg2 The name of the 3rd argument.
5187	*/
5188	# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
5189	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
5190	/**
5191	* For defining a C instruction implementation function taking three extra
5192	* arguments.
5193	*
5194	* @param a_Name The name of the function.
5195	* @param a_Type0 The type of the 1st argument
5196	* @param a_Arg0 The name of the 1st argument.
5197	* @param a_Type1 The type of the 2nd argument.
5198	* @param a_Arg1 The name of the 2nd argument.
5199	* @param a_Type2 The type of the 3rd argument.
5200	* @param a_Arg2 The name of the 3rd argument.
5201	*/
5202	# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
5203	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
5204	/**
5205	* Prototype version of IEM_CIMPL_DEF_3.
5206	*/
5207	# define IEM_CIMPL_PROTO_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
5208	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
5209	/**
5210	* For calling a C instruction implementation function taking three extra
5211	* arguments.
5212	*
5213	* This special call macro adds default arguments to the call and allow us to
5214	* change these later.
5215	*
5216	* @param a_fn The name of the function.
5217	* @param a0 The name of the 1st argument.
5218	* @param a1 The name of the 2nd argument.
5219	* @param a2 The name of the 3rd argument.
5220	*/
5221	# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
5222
5223
5224	/**
5225	* For typedef'ing or declaring a C instruction implementation function taking
5226	* four extra arguments.
5227	*
5228	* @param a_Name The name of the type.
5229	* @param a_Type0 The type of the 1st argument
5230	* @param a_Arg0 The name of the 1st argument.
5231	* @param a_Type1 The type of the 2nd argument.
5232	* @param a_Arg1 The name of the 2nd argument.
5233	* @param a_Type2 The type of the 3rd argument.
5234	* @param a_Arg2 The name of the 3rd argument.
5235	* @param a_Type3 The type of the 4th argument.
5236	* @param a_Arg3 The name of the 4th argument.
5237	*/
5238	# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
5239	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
5240	/**
5241	* For defining a C instruction implementation function taking four extra
5242	* arguments.
5243	*
5244	* @param a_Name The name of the function.
5245	* @param a_Type0 The type of the 1st argument
5246	* @param a_Arg0 The name of the 1st argument.
5247	* @param a_Type1 The type of the 2nd argument.
5248	* @param a_Arg1 The name of the 2nd argument.
5249	* @param a_Type2 The type of the 3rd argument.
5250	* @param a_Arg2 The name of the 3rd argument.
5251	* @param a_Type3 The type of the 4th argument.
5252	* @param a_Arg3 The name of the 4th argument.
5253	*/
5254	# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
5255	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
5256	a_Type2 a_Arg2, a_Type3 a_Arg3))
5257	/**
5258	* Prototype version of IEM_CIMPL_DEF_4.
5259	*/
5260	# define IEM_CIMPL_PROTO_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
5261	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
5262	a_Type2 a_Arg2, a_Type3 a_Arg3))
5263	/**
5264	* For calling a C instruction implementation function taking four extra
5265	* arguments.
5266	*
5267	* This special call macro adds default arguments to the call and allow us to
5268	* change these later.
5269	*
5270	* @param a_fn The name of the function.
5271	* @param a0 The name of the 1st argument.
5272	* @param a1 The name of the 2nd argument.
5273	* @param a2 The name of the 3rd argument.
5274	* @param a3 The name of the 4th argument.
5275	*/
5276	# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
5277
5278
5279	/**
5280	* For typedef'ing or declaring a C instruction implementation function taking
5281	* five extra arguments.
5282	*
5283	* @param a_Name The name of the type.
5284	* @param a_Type0 The type of the 1st argument
5285	* @param a_Arg0 The name of the 1st argument.
5286	* @param a_Type1 The type of the 2nd argument.
5287	* @param a_Arg1 The name of the 2nd argument.
5288	* @param a_Type2 The type of the 3rd argument.
5289	* @param a_Arg2 The name of the 3rd argument.
5290	* @param a_Type3 The type of the 4th argument.
5291	* @param a_Arg3 The name of the 4th argument.
5292	* @param a_Type4 The type of the 5th argument.
5293	* @param a_Arg4 The name of the 5th argument.
5294	*/
5295	# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
5296	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, \
5297	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
5298	a_Type3 a_Arg3, a_Type4 a_Arg4))
5299	/**
5300	* For defining a C instruction implementation function taking five extra
5301	* arguments.
5302	*
5303	* @param a_Name The name of the function.
5304	* @param a_Type0 The type of the 1st argument
5305	* @param a_Arg0 The name of the 1st argument.
5306	* @param a_Type1 The type of the 2nd argument.
5307	* @param a_Arg1 The name of the 2nd argument.
5308	* @param a_Type2 The type of the 3rd argument.
5309	* @param a_Arg2 The name of the 3rd argument.
5310	* @param a_Type3 The type of the 4th argument.
5311	* @param a_Arg3 The name of the 4th argument.
5312	* @param a_Type4 The type of the 5th argument.
5313	* @param a_Arg4 The name of the 5th argument.
5314	*/
5315	# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
5316	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
5317	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
5318	/**
5319	* Prototype version of IEM_CIMPL_DEF_5.
5320	*/
5321	# define IEM_CIMPL_PROTO_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
5322	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
5323	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
5324	/**
5325	* For calling a C instruction implementation function taking five extra
5326	* arguments.
5327	*
5328	* This special call macro adds default arguments to the call and allow us to
5329	* change these later.
5330	*
5331	* @param a_fn The name of the function.
5332	* @param a0 The name of the 1st argument.
5333	* @param a1 The name of the 2nd argument.
5334	* @param a2 The name of the 3rd argument.
5335	* @param a3 The name of the 4th argument.
5336	* @param a4 The name of the 5th argument.
5337	*/
5338	# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
5339
5340	/** @} */
5341
5342
5343	/** @name Opcode Decoder Function Types.
5344	* @{ */
5345
5346	/** @typedef PFNIEMOP
5347	* Pointer to an opcode decoder function.
5348	*/
5349
5350	/** @def FNIEMOP_DEF
5351	* Define an opcode decoder function.
5352	*
5353	* We're using macors for this so that adding and removing parameters as well as
5354	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL
5355	*
5356	* @param a_Name The function name.
5357	*/
5358
5359	/** @typedef PFNIEMOPRM
5360	* Pointer to an opcode decoder function with RM byte.
5361	*/
5362
5363	/** @def FNIEMOPRM_DEF
5364	* Define an opcode decoder function with RM byte.
5365	*
5366	* We're using macors for this so that adding and removing parameters as well as
5367	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL_1
5368	*
5369	* @param a_Name The function name.
5370	*/
5371
5372	#if defined(__GNUC__) && defined(RT_ARCH_X86)
5373	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOP)(PVMCPUCC pVCpu);
5374	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
5375	# define FNIEMOP_DEF(a_Name) \
5376	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu)
5377	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
5378	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
5379	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
5380	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
5381
5382	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
5383	typedef VBOXSTRICTRC (__fastcall * PFNIEMOP)(PVMCPUCC pVCpu);
5384	typedef VBOXSTRICTRC (__fastcall * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
5385	# define FNIEMOP_DEF(a_Name) \
5386	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
5387	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
5388	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
5389	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
5390	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
5391
5392	#elif defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
5393	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
5394	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
5395	# define FNIEMOP_DEF(a_Name) \
5396	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu)
5397	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
5398	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
5399	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
5400	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
5401
5402	#else
5403	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
5404	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
5405	# define FNIEMOP_DEF(a_Name) \
5406	IEM_STATIC IEM_DECL_MSC_GUARD_IGNORE VBOXSTRICTRC a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
5407	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
5408	IEM_STATIC IEM_DECL_MSC_GUARD_IGNORE VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
5409	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
5410	IEM_STATIC IEM_DECL_MSC_GUARD_IGNORE VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
5411
5412	#endif
5413	#define FNIEMOPRM_DEF(a_Name) FNIEMOP_DEF_1(a_Name, uint8_t, bRm)
5414
5415	/**
5416	* Call an opcode decoder function.
5417	*
5418	* We're using macors for this so that adding and removing parameters can be
5419	* done as we please. See FNIEMOP_DEF.
5420	*/
5421	#define FNIEMOP_CALL(a_pfn) (a_pfn)(pVCpu)
5422
5423	/**
5424	* Call a common opcode decoder function taking one extra argument.
5425	*
5426	* We're using macors for this so that adding and removing parameters can be
5427	* done as we please. See FNIEMOP_DEF_1.
5428	*/
5429	#define FNIEMOP_CALL_1(a_pfn, a0) (a_pfn)(pVCpu, a0)
5430
5431	/**
5432	* Call a common opcode decoder function taking one extra argument.
5433	*
5434	* We're using macors for this so that adding and removing parameters can be
5435	* done as we please. See FNIEMOP_DEF_1.
5436	*/
5437	#define FNIEMOP_CALL_2(a_pfn, a0, a1) (a_pfn)(pVCpu, a0, a1)
5438	/** @} */
5439
5440
5441	/** @name Misc Helpers
5442	* @{ */
5443
5444	/** Used to shut up GCC warnings about variables that 'may be used uninitialized'
5445	* due to GCC lacking knowledge about the value range of a switch. */
5446	#if RT_CPLUSPLUS_PREREQ(202000)
5447	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: [[unlikely]] AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
5448	#else
5449	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
5450	#endif
5451
5452	/** Variant of IEM_NOT_REACHED_DEFAULT_CASE_RET that returns a custom value. */
5453	#if RT_CPLUSPLUS_PREREQ(202000)
5454	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: [[unlikely]] AssertFailedReturn(a_RetValue)
5455	#else
5456	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: AssertFailedReturn(a_RetValue)
5457	#endif
5458
5459	/**
5460	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
5461	* occation.
5462	*/
5463	#ifdef LOG_ENABLED
5464	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
5465	do { \
5466	/Log/ LogAlways(("%s: returning IEM_RETURN_ASPECT_NOT_IMPLEMENTED (line %d)\n", __FUNCTION__, __LINE__)); \
5467	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
5468	} while (0)
5469	#else
5470	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
5471	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
5472	#endif
5473
5474	/**
5475	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
5476	* occation using the supplied logger statement.
5477	*
5478	* @param a_LoggerArgs What to log on failure.
5479	*/
5480	#ifdef LOG_ENABLED
5481	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
5482	do { \
5483	LogAlways((LOG_FN_FMT ": ", __PRETTY_FUNCTION__)); LogAlways(a_LoggerArgs); \
5484	/LogFunc(a_LoggerArgs);/ \
5485	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
5486	} while (0)
5487	#else
5488	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
5489	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
5490	#endif
5491
5492	/**
5493	* Gets the CPU mode (from fExec) as a IEMMODE value.
5494	*
5495	* @returns IEMMODE
5496	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5497	*/
5498	#define IEM_GET_CPU_MODE(a_pVCpu) ((a_pVCpu)->iem.s.fExec & IEM_F_MODE_CPUMODE_MASK)
5499
5500	/**
5501	* Check if we're currently executing in real or virtual 8086 mode.
5502	*
5503	* @returns @c true if it is, @c false if not.
5504	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5505	*/
5506	#define IEM_IS_REAL_OR_V86_MODE(a_pVCpu) (( ((a_pVCpu)->iem.s.fExec ^ IEM_F_MODE_X86_PROT_MASK) \
5507	& (IEM_F_MODE_X86_V86_MASK \| IEM_F_MODE_X86_PROT_MASK)) != 0)
5508
5509	/**
5510	* Check if we're currently executing in virtual 8086 mode.
5511	*
5512	* @returns @c true if it is, @c false if not.
5513	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5514	*/
5515	#define IEM_IS_V86_MODE(a_pVCpu) (((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_V86_MASK) != 0)
5516
5517	/**
5518	* Check if we're currently executing in long mode.
5519	*
5520	* @returns @c true if it is, @c false if not.
5521	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5522	*/
5523	#define IEM_IS_LONG_MODE(a_pVCpu) (CPUMIsGuestInLongModeEx(IEM_GET_CTX(a_pVCpu)))
5524
5525	/**
5526	* Check if we're currently executing in a 16-bit code segment.
5527	*
5528	* @returns @c true if it is, @c false if not.
5529	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5530	*/
5531	#define IEM_IS_16BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_16BIT)
5532
5533	/**
5534	* Check if we're currently executing in a 32-bit code segment.
5535	*
5536	* @returns @c true if it is, @c false if not.
5537	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5538	*/
5539	#define IEM_IS_32BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_32BIT)
5540
5541	/**
5542	* Check if we're currently executing in a 64-bit code segment.
5543	*
5544	* @returns @c true if it is, @c false if not.
5545	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5546	*/
5547	#define IEM_IS_64BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_64BIT)
5548
5549	/**
5550	* Check if we're currently executing in real mode.
5551	*
5552	* @returns @c true if it is, @c false if not.
5553	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5554	*/
5555	#define IEM_IS_REAL_MODE(a_pVCpu) (!((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_PROT_MASK))
5556
5557	/**
5558	* Gets the current protection level (CPL).
5559	*
5560	* @returns 0..3
5561	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5562	*/
5563	#define IEM_GET_CPL(a_pVCpu) (((a_pVCpu)->iem.s.fExec >> IEM_F_X86_CPL_SHIFT) & IEM_F_X86_CPL_SMASK)
5564
5565	/**
5566	* Sets the current protection level (CPL).
5567	*
5568	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5569	*/
5570	#define IEM_SET_CPL(a_pVCpu, a_uCpl) \
5571	do { (a_pVCpu)->iem.s.fExec = ((a_pVCpu)->iem.s.fExec & ~IEM_F_X86_CPL_MASK) \| ((a_uCpl) << IEM_F_X86_CPL_SHIFT); } while (0)
5572
5573	/**
5574	* Returns a (const) pointer to the CPUMFEATURES for the guest CPU.
5575	* @returns PCCPUMFEATURES
5576	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5577	*/
5578	#define IEM_GET_GUEST_CPU_FEATURES(a_pVCpu) (&((a_pVCpu)->CTX_SUFF(pVM)->cpum.ro.GuestFeatures))
5579
5580	/**
5581	* Returns a (const) pointer to the CPUMFEATURES for the host CPU.
5582	* @returns PCCPUMFEATURES
5583	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5584	*/
5585	#define IEM_GET_HOST_CPU_FEATURES(a_pVCpu) (&g_CpumHostFeatures.s)
5586
5587	/**
5588	* Evaluates to true if we're presenting an Intel CPU to the guest.
5589	*/
5590	#define IEM_IS_GUEST_CPU_INTEL(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL )
5591
5592	/**
5593	* Evaluates to true if we're presenting an AMD CPU to the guest.
5594	*/
5595	#define IEM_IS_GUEST_CPU_AMD(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_AMD \|\| (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_HYGON )
5596
5597	/**
5598	* Check if the address is canonical.
5599	*/
5600	#define IEM_IS_CANONICAL(a_u64Addr) X86_IS_CANONICAL(a_u64Addr)
5601
5602	/** Checks if the ModR/M byte is in register mode or not. */
5603	#define IEM_IS_MODRM_REG_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT) )
5604	/** Checks if the ModR/M byte is in memory mode or not. */
5605	#define IEM_IS_MODRM_MEM_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT) )
5606
5607	/**
5608	* Gets the register (reg) part of a ModR/M encoding, with REX.R added in.
5609	*
5610	* For use during decoding.
5611	*/
5612	#define IEM_GET_MODRM_REG(a_pVCpu, a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| (a_pVCpu)->iem.s.uRexReg )
5613	/**
5614	* Gets the r/m part of a ModR/M encoding as a register index, with REX.B added in.
5615	*
5616	* For use during decoding.
5617	*/
5618	#define IEM_GET_MODRM_RM(a_pVCpu, a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) \| (a_pVCpu)->iem.s.uRexB )
5619
5620	/**
5621	* Gets the register (reg) part of a ModR/M encoding, without REX.R.
5622	*
5623	* For use during decoding.
5624	*/
5625	#define IEM_GET_MODRM_REG_8(a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) )
5626	/**
5627	* Gets the r/m part of a ModR/M encoding as a register index, without REX.B.
5628	*
5629	* For use during decoding.
5630	*/
5631	#define IEM_GET_MODRM_RM_8(a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) )
5632
5633	/**
5634	* Gets the register (reg) part of a ModR/M encoding as an extended 8-bit
5635	* register index, with REX.R added in.
5636	*
5637	* For use during decoding.
5638	*
5639	* @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
5640	*/
5641	#define IEM_GET_MODRM_REG_EX8(a_pVCpu, a_bRm) \
5642	( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
5643	\|\| !((a_bRm) & (4 << X86_MODRM_REG_SHIFT)) /* IEM_GET_MODRM_REG(pVCpu, a_bRm) < 4 */ \
5644	? IEM_GET_MODRM_REG(pVCpu, a_bRm) : (((a_bRm) >> X86_MODRM_REG_SHIFT) & 3) \| 16)
5645	/**
5646	* Gets the r/m part of a ModR/M encoding as an extended 8-bit register index,
5647	* with REX.B added in.
5648	*
5649	* For use during decoding.
5650	*
5651	* @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
5652	*/
5653	#define IEM_GET_MODRM_RM_EX8(a_pVCpu, a_bRm) \
5654	( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
5655	\|\| !((a_bRm) & 4) /* IEM_GET_MODRM_RM(pVCpu, a_bRm) < 4 */ \
5656	? IEM_GET_MODRM_RM(pVCpu, a_bRm) : ((a_bRm) & 3) \| 16)
5657
5658	/**
5659	* Combines the prefix REX and ModR/M byte for passing to
5660	* iemOpHlpCalcRmEffAddrThreadedAddr64().
5661	*
5662	* @returns The ModRM byte but with bit 3 set to REX.B and bit 4 to REX.X.
5663	* The two bits are part of the REG sub-field, which isn't needed in
5664	* iemOpHlpCalcRmEffAddrThreadedAddr64().
5665	*
5666	* For use during decoding/recompiling.
5667	*/
5668	#define IEM_GET_MODRM_EX(a_pVCpu, a_bRm) \
5669	( ((a_bRm) & ~X86_MODRM_REG_MASK) \
5670	\| (uint8_t)( (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X)) >> (25 - 3) ) )
5671	AssertCompile(IEM_OP_PRF_REX_B == RT_BIT_32(25));
5672	AssertCompile(IEM_OP_PRF_REX_X == RT_BIT_32(26));
5673
5674	/**
5675	* Gets the effective VEX.VVVV value.
5676	*
5677	* The 4th bit is ignored if not 64-bit code.
5678	* @returns effective V-register value.
5679	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5680	*/
5681	#define IEM_GET_EFFECTIVE_VVVV(a_pVCpu) \
5682	(IEM_IS_64BIT_CODE(a_pVCpu) ? (a_pVCpu)->iem.s.uVex3rdReg : (a_pVCpu)->iem.s.uVex3rdReg & 7)
5683
5684
5685	/**
5686	* Gets the register (reg) part of a the special 4th register byte used by
5687	* vblendvps and vblendvpd.
5688	*
5689	* For use during decoding.
5690	*/
5691	#define IEM_GET_IMM8_REG(a_pVCpu, a_bRegImm8) \
5692	(IEM_IS_64BIT_CODE(a_pVCpu) ? (a_bRegImm8) >> 4 : ((a_bRegImm8) >> 4) & 7)
5693
5694
5695	/**
5696	* Checks if we're executing inside an AMD-V or VT-x guest.
5697	*/
5698	#if defined(VBOX_WITH_NESTED_HWVIRT_VMX) \|\| defined(VBOX_WITH_NESTED_HWVIRT_SVM)
5699	# define IEM_IS_IN_GUEST(a_pVCpu) RT_BOOL((a_pVCpu)->iem.s.fExec & IEM_F_X86_CTX_IN_GUEST)
5700	#else
5701	# define IEM_IS_IN_GUEST(a_pVCpu) false
5702	#endif
5703
5704
5705	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5706
5707	/**
5708	* Check if the guest has entered VMX root operation.
5709	*/
5710	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxRootMode(IEM_GET_CTX(a_pVCpu)))
5711
5712	/**
5713	* Check if the guest has entered VMX non-root operation.
5714	*/
5715	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) ( ((a_pVCpu)->iem.s.fExec & (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST)) \
5716	== (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST) )
5717
5718	/**
5719	* Check if the nested-guest has the given Pin-based VM-execution control set.
5720	*/
5721	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_PinCtl) (CPUMIsGuestVmxPinCtlsSet(IEM_GET_CTX(a_pVCpu), (a_PinCtl)))
5722
5723	/**
5724	* Check if the nested-guest has the given Processor-based VM-execution control set.
5725	*/
5726	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_ProcCtl) (CPUMIsGuestVmxProcCtlsSet(IEM_GET_CTX(a_pVCpu), (a_ProcCtl)))
5727
5728	/**
5729	* Check if the nested-guest has the given Secondary Processor-based VM-execution
5730	* control set.
5731	*/
5732	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_ProcCtl2) (CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(a_pVCpu), (a_ProcCtl2)))
5733
5734	/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
5735	# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
5736
5737	/** Whether a shadow VMCS is present for the given VCPU. */
5738	# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
5739
5740	/** Gets the VMXON region pointer. */
5741	# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
5742
5743	/** Gets the guest-physical address of the current VMCS for the given VCPU. */
5744	# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
5745
5746	/** Whether a current VMCS is present for the given VCPU. */
5747	# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
5748
5749	/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
5750	# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
5751	do \
5752	{ \
5753	Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
5754	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
5755	} while (0)
5756
5757	/** Clears any current VMCS for the given VCPU. */
5758	# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
5759	do \
5760	{ \
5761	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
5762	} while (0)
5763
5764	/**
5765	* Invokes the VMX VM-exit handler for an instruction intercept.
5766	*/
5767	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) \
5768	do { return iemVmxVmexitInstr((a_pVCpu), (a_uExitReason), (a_cbInstr)); } while (0)
5769
5770	/**
5771	* Invokes the VMX VM-exit handler for an instruction intercept where the
5772	* instruction provides additional VM-exit information.
5773	*/
5774	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) \
5775	do { return iemVmxVmexitInstrNeedsInfo((a_pVCpu), (a_uExitReason), (a_uInstrId), (a_cbInstr)); } while (0)
5776
5777	/**
5778	* Invokes the VMX VM-exit handler for a task switch.
5779	*/
5780	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) \
5781	do { return iemVmxVmexitTaskSwitch((a_pVCpu), (a_enmTaskSwitch), (a_SelNewTss), (a_cbInstr)); } while (0)
5782
5783	/**
5784	* Invokes the VMX VM-exit handler for MWAIT.
5785	*/
5786	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) \
5787	do { return iemVmxVmexitInstrMwait((a_pVCpu), (a_fMonitorArmed), (a_cbInstr)); } while (0)
5788
5789	/**
5790	* Invokes the VMX VM-exit handler for EPT faults.
5791	*/
5792	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) \
5793	do { return iemVmxVmexitEpt(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr); } while (0)
5794
5795	/**
5796	* Invokes the VMX VM-exit handler.
5797	*/
5798	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) \
5799	do { return iemVmxVmexit((a_pVCpu), (a_uExitReason), (a_uExitQual)); } while (0)
5800
5801	#else
5802	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (false)
5803	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (false)
5804	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_cbInstr) (false)
5805	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_cbInstr) (false)
5806	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_cbInstr) (false)
5807	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5808	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5809	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5810	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5811	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5812	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) do { return VERR_VMX_IPE_1; } while (0)
5813
5814	#endif
5815
5816	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5817	/**
5818	* Checks if we're executing a guest using AMD-V.
5819	*/
5820	# define IEM_SVM_IS_IN_GUEST(a_pVCpu) ( (a_pVCpu->iem.s.fExec & (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST)) \
5821	== (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST))
5822	/**
5823	* Check if an SVM control/instruction intercept is set.
5824	*/
5825	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) \
5826	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmCtrlInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_Intercept)))
5827
5828	/**
5829	* Check if an SVM read CRx intercept is set.
5830	*/
5831	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
5832	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
5833
5834	/**
5835	* Check if an SVM write CRx intercept is set.
5836	*/
5837	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
5838	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
5839
5840	/**
5841	* Check if an SVM read DRx intercept is set.
5842	*/
5843	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
5844	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
5845
5846	/**
5847	* Check if an SVM write DRx intercept is set.
5848	*/
5849	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
5850	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
5851
5852	/**
5853	* Check if an SVM exception intercept is set.
5854	*/
5855	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) \
5856	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmXcptInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uVector)))
5857
5858	/**
5859	* Invokes the SVM \#VMEXIT handler for the nested-guest.
5860	*/
5861	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
5862	do { return iemSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2)); } while (0)
5863
5864	/**
5865	* Invokes the 'MOV CRx' SVM \#VMEXIT handler after constructing the
5866	* corresponding decode assist information.
5867	*/
5868	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) \
5869	do \
5870	{ \
5871	uint64_t uExitInfo1; \
5872	if ( IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmDecodeAssists \
5873	&& (a_enmAccessCrX) == IEMACCESSCRX_MOV_CRX) \
5874	uExitInfo1 = SVM_EXIT1_MOV_CRX_MASK \| ((a_iGReg) & 7); \
5875	else \
5876	uExitInfo1 = 0; \
5877	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, uExitInfo1, 0); \
5878	} while (0)
5879
5880	/** Check and handles SVM nested-guest instruction intercept and updates
5881	* NRIP if needed.
5882	*/
5883	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
5884	do \
5885	{ \
5886	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept)) \
5887	{ \
5888	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
5889	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2); \
5890	} \
5891	} while (0)
5892
5893	/** Checks and handles SVM nested-guest CR0 read intercept. */
5894	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
5895	do \
5896	{ \
5897	if (!IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, 0)) \
5898	{ /* probably likely */ } \
5899	else \
5900	{ \
5901	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
5902	IEM_SVM_VMEXIT_RET(a_pVCpu, SVM_EXIT_READ_CR0, a_uExitInfo1, a_uExitInfo2); \
5903	} \
5904	} while (0)
5905
5906	/**
5907	* Updates the NextRIP (NRI) field in the nested-guest VMCB.
5908	*/
5909	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) \
5910	do { \
5911	if (IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmNextRipSave) \
5912	CPUMGuestSvmUpdateNRip(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_cbInstr)); \
5913	} while (0)
5914
5915	#else
5916	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) (false)
5917	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
5918	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
5919	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
5920	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
5921	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) (false)
5922	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { return VERR_SVM_IPE_1; } while (0)
5923	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) do { return VERR_SVM_IPE_1; } while (0)
5924	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, \
5925	a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
5926	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
5927	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) do { } while (0)
5928
5929	#endif
5930
5931	/** @} */
5932
5933	uint32_t iemCalcExecDbgFlagsSlow(PVMCPUCC pVCpu);
5934	VBOXSTRICTRC iemExecInjectPendingTrap(PVMCPUCC pVCpu);
5935
5936
5937	/**
5938	* Selector descriptor table entry as fetched by iemMemFetchSelDesc.
5939	*/
5940	typedef union IEMSELDESC
5941	{
5942	/** The legacy view. */
5943	X86DESC Legacy;
5944	/** The long mode view. */
5945	X86DESC64 Long;
5946	} IEMSELDESC;
5947	/** Pointer to a selector descriptor table entry. */
5948	typedef IEMSELDESC *PIEMSELDESC;
5949
5950	/** @name Raising Exceptions.
5951	* @{ */
5952	VBOXSTRICTRC iemTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, uint32_t uNextEip, uint32_t fFlags,
5953	uint16_t uErr, uint64_t uCr2, RTSEL SelTSS, PIEMSELDESC pNewDescTSS) RT_NOEXCEPT;
5954
5955	VBOXSTRICTRC iemRaiseXcptOrInt(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags,
5956	uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
5957	#ifdef IEM_WITH_SETJMP
5958	DECL_NO_RETURN(void) iemRaiseXcptOrIntJmp(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector,
5959	uint32_t fFlags, uint16_t uErr, uint64_t uCr2) IEM_NOEXCEPT_MAY_LONGJMP;
5960	#endif
5961	VBOXSTRICTRC iemRaiseDivideError(PVMCPUCC pVCpu) RT_NOEXCEPT;
5962	#ifdef IEM_WITH_SETJMP
5963	DECL_NO_RETURN(void) iemRaiseDivideErrorJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5964	#endif
5965	VBOXSTRICTRC iemRaiseDebugException(PVMCPUCC pVCpu) RT_NOEXCEPT;
5966	VBOXSTRICTRC iemRaiseBoundRangeExceeded(PVMCPUCC pVCpu) RT_NOEXCEPT;
5967	VBOXSTRICTRC iemRaiseUndefinedOpcode(PVMCPUCC pVCpu) RT_NOEXCEPT;
5968	#ifdef IEM_WITH_SETJMP
5969	DECL_NO_RETURN(void) iemRaiseUndefinedOpcodeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5970	#endif
5971	VBOXSTRICTRC iemRaiseDeviceNotAvailable(PVMCPUCC pVCpu) RT_NOEXCEPT;
5972	#ifdef IEM_WITH_SETJMP
5973	DECL_NO_RETURN(void) iemRaiseDeviceNotAvailableJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5974	#endif
5975	VBOXSTRICTRC iemRaiseTaskSwitchFaultWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5976	VBOXSTRICTRC iemRaiseTaskSwitchFaultCurrentTSS(PVMCPUCC pVCpu) RT_NOEXCEPT;
5977	VBOXSTRICTRC iemRaiseTaskSwitchFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
5978	VBOXSTRICTRC iemRaiseTaskSwitchFaultBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5979	/VBOXSTRICTRC iemRaiseSelectorNotPresent(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;/
5980	VBOXSTRICTRC iemRaiseSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5981	VBOXSTRICTRC iemRaiseSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5982	VBOXSTRICTRC iemRaiseStackSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5983	VBOXSTRICTRC iemRaiseStackSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5984	VBOXSTRICTRC iemRaiseGeneralProtectionFault(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5985	VBOXSTRICTRC iemRaiseGeneralProtectionFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
5986	#ifdef IEM_WITH_SETJMP
5987	DECL_NO_RETURN(void) iemRaiseGeneralProtectionFault0Jmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5988	#endif
5989	VBOXSTRICTRC iemRaiseGeneralProtectionFaultBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
5990	VBOXSTRICTRC iemRaiseNotCanonical(PVMCPUCC pVCpu) RT_NOEXCEPT;
5991	VBOXSTRICTRC iemRaiseSelectorBounds(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
5992	#ifdef IEM_WITH_SETJMP
5993	DECL_NO_RETURN(void) iemRaiseSelectorBoundsJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
5994	#endif
5995	VBOXSTRICTRC iemRaiseSelectorBoundsBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
5996	#ifdef IEM_WITH_SETJMP
5997	DECL_NO_RETURN(void) iemRaiseSelectorBoundsBySelectorJmp(PVMCPUCC pVCpu, RTSEL Sel) IEM_NOEXCEPT_MAY_LONGJMP;
5998	#endif
5999	VBOXSTRICTRC iemRaiseSelectorInvalidAccess(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
6000	#ifdef IEM_WITH_SETJMP
6001	DECL_NO_RETURN(void) iemRaiseSelectorInvalidAccessJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
6002	#endif
6003	VBOXSTRICTRC iemRaisePageFault(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) RT_NOEXCEPT;
6004	#ifdef IEM_WITH_SETJMP
6005	DECL_NO_RETURN(void) iemRaisePageFaultJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) IEM_NOEXCEPT_MAY_LONGJMP;
6006	#endif
6007	VBOXSTRICTRC iemRaiseMathFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
6008	#ifdef IEM_WITH_SETJMP
6009	DECL_NO_RETURN(void) iemRaiseMathFaultJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6010	#endif
6011	VBOXSTRICTRC iemRaiseAlignmentCheckException(PVMCPUCC pVCpu) RT_NOEXCEPT;
6012	#ifdef IEM_WITH_SETJMP
6013	DECL_NO_RETURN(void) iemRaiseAlignmentCheckExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6014	#endif
6015	VBOXSTRICTRC iemRaiseSimdFpException(PVMCPUCC pVCpu) RT_NOEXCEPT;
6016	#ifdef IEM_WITH_SETJMP
6017	DECL_NO_RETURN(void) iemRaiseSimdFpExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6018	#endif
6019
6020	void iemLogSyscallRealModeInt(PVMCPUCC pVCpu, uint8_t u8Vector, uint8_t cbInstr);
6021	void iemLogSyscallProtModeInt(PVMCPUCC pVCpu, uint8_t u8Vector, uint8_t cbInstr);
6022
6023	IEM_CIMPL_DEF_0(iemCImplRaiseDivideError);
6024	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidLockPrefix);
6025	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidOpcode);
6026
6027	/**
6028	* Macro for calling iemCImplRaiseDivideError().
6029	*
6030	* This is for things that will _always_ decode to an \#DE, taking the
6031	* recompiler into consideration and everything.
6032	*
6033	* @return Strict VBox status code.
6034	*/
6035	#define IEMOP_RAISE_DIVIDE_ERROR_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseDivideError)
6036
6037	/**
6038	* Macro for calling iemCImplRaiseInvalidLockPrefix().
6039	*
6040	* This is for things that will _always_ decode to an \#UD, taking the
6041	* recompiler into consideration and everything.
6042	*
6043	* @return Strict VBox status code.
6044	*/
6045	#define IEMOP_RAISE_INVALID_LOCK_PREFIX_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidLockPrefix)
6046
6047	/**
6048	* Macro for calling iemCImplRaiseInvalidOpcode() for decode/static \#UDs.
6049	*
6050	* This is for things that will _always_ decode to an \#UD, taking the
6051	* recompiler into consideration and everything.
6052	*
6053	* @return Strict VBox status code.
6054	*/
6055	#define IEMOP_RAISE_INVALID_OPCODE_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidOpcode)
6056
6057	/**
6058	* Macro for calling iemCImplRaiseInvalidOpcode() for runtime-style \#UDs.
6059	*
6060	* Using this macro means you've got _buggy_ _code_ and are doing things that
6061	* belongs exclusively in IEMAllCImpl.cpp during decoding.
6062	*
6063	* @return Strict VBox status code.
6064	* @see IEMOP_RAISE_INVALID_OPCODE_RET
6065	*/
6066	#define IEMOP_RAISE_INVALID_OPCODE_RUNTIME_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidOpcode)
6067
6068	/** @} */
6069
6070	/** @name Register Access.
6071	* @{ */
6072	VBOXSTRICTRC iemRegRipRelativeJumpS8AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int8_t offNextInstr,
6073	IEMMODE enmEffOpSize) RT_NOEXCEPT;
6074	VBOXSTRICTRC iemRegRipRelativeJumpS16AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int16_t offNextInstr) RT_NOEXCEPT;
6075	VBOXSTRICTRC iemRegRipRelativeJumpS32AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int32_t offNextInstr,
6076	IEMMODE enmEffOpSize) RT_NOEXCEPT;
6077	/** @} */
6078
6079	/** @name FPU access and helpers.
6080	* @{ */
6081	void iemFpuPushResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
6082	void iemFpuPushResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
6083	void iemFpuPushResultTwo(PVMCPUCC pVCpu, PIEMFPURESULTTWO pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
6084	void iemFpuStoreResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
6085	void iemFpuStoreResultThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
6086	void iemFpuStoreResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
6087	uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
6088	void iemFpuStoreResultWithMemOpThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
6089	uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
6090	void iemFpuUpdateOpcodeAndIp(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
6091	void iemFpuUpdateFSW(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
6092	void iemFpuUpdateFSWThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
6093	void iemFpuUpdateFSWWithMemOp(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
6094	void iemFpuUpdateFSWThenPopPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
6095	void iemFpuUpdateFSWWithMemOpThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
6096	void iemFpuStackUnderflow(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
6097	void iemFpuStackUnderflowWithMemOp(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
6098	void iemFpuStackUnderflowThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
6099	void iemFpuStackUnderflowWithMemOpThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
6100	void iemFpuStackUnderflowThenPopPop(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
6101	void iemFpuStackPushUnderflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
6102	void iemFpuStackPushUnderflowTwo(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
6103	void iemFpuStackPushOverflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
6104	void iemFpuStackPushOverflowWithMemOp(PVMCPUCC pVCpu, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
6105	/** @} */
6106
6107	/** @name SSE+AVX SIMD access and helpers.
6108	* @{ */
6109	void iemSseUpdateMxcsr(PVMCPUCC pVCpu, uint32_t fMxcsr) RT_NOEXCEPT;
6110	/** @} */
6111
6112	/** @name Memory access.
6113	* @{ */
6114
6115	/** Report a \#GP instead of \#AC and do not restrict to ring-3 */
6116	#define IEM_MEMMAP_F_ALIGN_GP RT_BIT_32(16)
6117	/** SSE access that should report a \#GP instead of \#AC, unless MXCSR.MM=1
6118	* when it works like normal \#AC. Always used with IEM_MEMMAP_F_ALIGN_GP. */
6119	#define IEM_MEMMAP_F_ALIGN_SSE RT_BIT_32(17)
6120	/** If \#AC is applicable, raise it. Always used with IEM_MEMMAP_F_ALIGN_GP.
6121	* Users include FXSAVE & FXRSTOR. */
6122	#define IEM_MEMMAP_F_ALIGN_GP_OR_AC RT_BIT_32(18)
6123
6124	VBOXSTRICTRC iemMemMap(PVMCPUCC pVCpu, void *ppvMem, uint8_t pbUnmapInfo, size_t cbMem, uint8_t iSegReg, RTGCPTR GCPtrMem,
6125	uint32_t fAccess, uint32_t uAlignCtl) RT_NOEXCEPT;
6126	VBOXSTRICTRC iemMemCommitAndUnmap(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
6127	#ifndef IN_RING3
6128	VBOXSTRICTRC iemMemCommitAndUnmapPostponeTroubleToR3(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
6129	#endif
6130	void iemMemRollbackAndUnmap(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
6131	void iemMemRollback(PVMCPUCC pVCpu) RT_NOEXCEPT;
6132	VBOXSTRICTRC iemMemApplySegment(PVMCPUCC pVCpu, uint32_t fAccess, uint8_t iSegReg, size_t cbMem, PRTGCPTR pGCPtrMem) RT_NOEXCEPT;
6133	VBOXSTRICTRC iemMemMarkSelDescAccessed(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
6134	VBOXSTRICTRC iemMemPageTranslateAndCheckAccess(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t cbAccess, uint32_t fAccess, PRTGCPHYS pGCPhysMem) RT_NOEXCEPT;
6135
6136	void iemOpcodeFlushLight(PVMCPUCC pVCpu, uint8_t cbInstr);
6137	void iemOpcodeFlushHeavy(PVMCPUCC pVCpu, uint8_t cbInstr);
6138	#ifdef IEM_WITH_CODE_TLB
6139	void iemOpcodeFetchBytesJmp(PVMCPUCC pVCpu, size_t cbDst, void *pvDst) IEM_NOEXCEPT_MAY_LONGJMP;
6140	#else
6141	VBOXSTRICTRC iemOpcodeFetchMoreBytes(PVMCPUCC pVCpu, size_t cbMin) RT_NOEXCEPT;
6142	#endif
6143	#ifdef IEM_WITH_SETJMP
6144	uint8_t iemOpcodeGetNextU8SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6145	uint16_t iemOpcodeGetNextU16SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6146	uint32_t iemOpcodeGetNextU32SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6147	uint64_t iemOpcodeGetNextU64SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6148	#else
6149	VBOXSTRICTRC iemOpcodeGetNextU8Slow(PVMCPUCC pVCpu, uint8_t *pb) RT_NOEXCEPT;
6150	VBOXSTRICTRC iemOpcodeGetNextS8SxU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
6151	VBOXSTRICTRC iemOpcodeGetNextS8SxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
6152	VBOXSTRICTRC iemOpcodeGetNextS8SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
6153	VBOXSTRICTRC iemOpcodeGetNextU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
6154	VBOXSTRICTRC iemOpcodeGetNextU16ZxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
6155	VBOXSTRICTRC iemOpcodeGetNextU16ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
6156	VBOXSTRICTRC iemOpcodeGetNextU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
6157	VBOXSTRICTRC iemOpcodeGetNextU32ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
6158	VBOXSTRICTRC iemOpcodeGetNextS32SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
6159	VBOXSTRICTRC iemOpcodeGetNextU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
6160	#endif
6161
6162	VBOXSTRICTRC iemMemFetchDataU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6163	VBOXSTRICTRC iemMemFetchDataU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6164	VBOXSTRICTRC iemMemFetchDataU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6165	VBOXSTRICTRC iemMemFetchDataU32NoAc(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6166	VBOXSTRICTRC iemMemFetchDataU32_ZX_U64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6167	VBOXSTRICTRC iemMemFetchDataU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6168	VBOXSTRICTRC iemMemFetchDataU64NoAc(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6169	VBOXSTRICTRC iemMemFetchDataU64AlignedU128(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6170	VBOXSTRICTRC iemMemFetchDataR80(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6171	VBOXSTRICTRC iemMemFetchDataD80(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6172	VBOXSTRICTRC iemMemFetchDataU128(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6173	VBOXSTRICTRC iemMemFetchDataU128NoAc(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6174	VBOXSTRICTRC iemMemFetchDataU128AlignedSse(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6175	VBOXSTRICTRC iemMemFetchDataU256(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6176	VBOXSTRICTRC iemMemFetchDataU256NoAc(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6177	VBOXSTRICTRC iemMemFetchDataU256AlignedAvx(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6178	VBOXSTRICTRC iemMemFetchDataXdtr(PVMCPUCC pVCpu, uint16_t *pcbLimit, PRTGCPTR pGCPtrBase, uint8_t iSegReg,
6179	RTGCPTR GCPtrMem, IEMMODE enmOpSize) RT_NOEXCEPT;
6180	#ifdef IEM_WITH_SETJMP
6181	uint8_t iemMemFetchDataU8SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6182	uint16_t iemMemFetchDataU16SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6183	uint32_t iemMemFetchDataU32SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6184	uint32_t iemMemFetchDataU32NoAcSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6185	uint32_t iemMemFlatFetchDataU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6186	uint64_t iemMemFetchDataU64SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6187	uint64_t iemMemFetchDataU64NoAcSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6188	uint64_t iemMemFetchDataU64AlignedU128SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6189	void iemMemFetchDataR80SafeJmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6190	void iemMemFetchDataD80SafeJmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6191	void iemMemFetchDataU128SafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6192	void iemMemFetchDataU128NoAcSafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6193	void iemMemFetchDataU128AlignedSseSafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6194	void iemMemFetchDataU256SafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6195	void iemMemFetchDataU256NoAcSafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6196	void iemMemFetchDataU256AlignedAvxSafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6197	# if 0 /* these are inlined now */
6198	uint8_t iemMemFetchDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6199	uint16_t iemMemFetchDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6200	uint32_t iemMemFetchDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6201	uint32_t iemMemFlatFetchDataU32Jmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6202	uint64_t iemMemFetchDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6203	uint64_t iemMemFetchDataU64AlignedU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6204	void iemMemFetchDataR80Jmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6205	void iemMemFetchDataD80Jmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6206	void iemMemFetchDataU128Jmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6207	void iemMemFetchDataU128NoAcJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6208	void iemMemFetchDataU128AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6209	void iemMemFetchDataU256NoAcJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6210	void iemMemFetchDataU256AlignedAvxJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6211	# endif
6212	void iemMemFetchDataU256Jmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6213	#endif
6214
6215	VBOXSTRICTRC iemMemFetchSysU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6216	VBOXSTRICTRC iemMemFetchSysU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6217	VBOXSTRICTRC iemMemFetchSysU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6218	VBOXSTRICTRC iemMemFetchSysU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6219	VBOXSTRICTRC iemMemFetchSelDesc(PVMCPUCC pVCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt) RT_NOEXCEPT;
6220
6221	VBOXSTRICTRC iemMemStoreDataU8(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) RT_NOEXCEPT;
6222	VBOXSTRICTRC iemMemStoreDataU16(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) RT_NOEXCEPT;
6223	VBOXSTRICTRC iemMemStoreDataU32(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) RT_NOEXCEPT;
6224	VBOXSTRICTRC iemMemStoreDataU64(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) RT_NOEXCEPT;
6225	VBOXSTRICTRC iemMemStoreDataU128(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
6226	VBOXSTRICTRC iemMemStoreDataU128NoAc(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
6227	VBOXSTRICTRC iemMemStoreDataU128AlignedSse(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
6228	VBOXSTRICTRC iemMemStoreDataU256(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
6229	VBOXSTRICTRC iemMemStoreDataU256NoAc(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
6230	VBOXSTRICTRC iemMemStoreDataU256AlignedAvx(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
6231	VBOXSTRICTRC iemMemStoreDataXdtr(PVMCPUCC pVCpu, uint16_t cbLimit, RTGCPTR GCPtrBase, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6232	#ifdef IEM_WITH_SETJMP
6233	void iemMemStoreDataU8SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
6234	void iemMemStoreDataU16SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
6235	void iemMemStoreDataU32SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
6236	void iemMemStoreDataU64SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
6237	void iemMemStoreDataU128SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
6238	void iemMemStoreDataU128NoAcSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT128U pu128Value) IEM_NOEXCEPT_MAY_LONGJMP;
6239	void iemMemStoreDataU128AlignedSseSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT128U pu128Value) IEM_NOEXCEPT_MAY_LONGJMP;
6240	void iemMemStoreDataU256SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
6241	void iemMemStoreDataU256NoAcSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
6242	void iemMemStoreDataU256AlignedAvxSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
6243	void iemMemStoreDataR80SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTFLOAT80U pr80Value) IEM_NOEXCEPT_MAY_LONGJMP;
6244	void iemMemStoreDataD80SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTPBCD80U pd80Value) IEM_NOEXCEPT_MAY_LONGJMP;
6245	#if 0
6246	void iemMemStoreDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
6247	void iemMemStoreDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
6248	void iemMemStoreDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
6249	void iemMemStoreDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
6250	void iemMemStoreDataU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
6251	void iemMemStoreDataNoAcU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
6252	void iemMemStoreDataU256NoAcJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
6253	void iemMemStoreDataU256AlignedAvxJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
6254	#endif
6255	void iemMemStoreDataU128AlignedSseJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
6256	void iemMemStoreDataU256Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
6257	#endif
6258
6259	#ifdef IEM_WITH_SETJMP
6260	uint8_t iemMemMapDataU8RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6261	uint8_t iemMemMapDataU8AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6262	uint8_t iemMemMapDataU8WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6263	uint8_t const iemMemMapDataU8RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6264	uint16_t iemMemMapDataU16RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6265	uint16_t iemMemMapDataU16AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6266	uint16_t iemMemMapDataU16WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6267	uint16_t const iemMemMapDataU16RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6268	uint32_t iemMemMapDataU32RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6269	uint32_t iemMemMapDataU32AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6270	uint32_t iemMemMapDataU32WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6271	uint32_t const iemMemMapDataU32RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6272	uint64_t iemMemMapDataU64RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6273	uint64_t iemMemMapDataU64AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6274	uint64_t iemMemMapDataU64WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6275	uint64_t const iemMemMapDataU64RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6276	PRTFLOAT80U iemMemMapDataR80RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6277	PRTFLOAT80U iemMemMapDataR80WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6278	PCRTFLOAT80U iemMemMapDataR80RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6279	PRTPBCD80U iemMemMapDataD80RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6280	PRTPBCD80U iemMemMapDataD80WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6281	PCRTPBCD80U iemMemMapDataD80RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6282	PRTUINT128U iemMemMapDataU128RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6283	PRTUINT128U iemMemMapDataU128AtSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6284	PRTUINT128U iemMemMapDataU128WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6285	PCRTUINT128U iemMemMapDataU128RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6286
6287	void iemMemCommitAndUnmapJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
6288	void iemMemCommitAndUnmapRwSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
6289	void iemMemCommitAndUnmapAtSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
6290	void iemMemCommitAndUnmapWoSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
6291	void iemMemCommitAndUnmapRoSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
6292	void iemMemRollbackAndUnmapWoSafe(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
6293	#endif
6294
6295	VBOXSTRICTRC iemMemStackPushBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
6296	void *ppvMem, uint8_t pbUnmapInfo, uint64_t *puNewRsp) RT_NOEXCEPT;
6297	VBOXSTRICTRC iemMemStackPushCommitSpecial(PVMCPUCC pVCpu, uint8_t bUnmapInfo, uint64_t uNewRsp) RT_NOEXCEPT;
6298	VBOXSTRICTRC iemMemStackPushU16(PVMCPUCC pVCpu, uint16_t u16Value) RT_NOEXCEPT;
6299	VBOXSTRICTRC iemMemStackPushU32(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
6300	VBOXSTRICTRC iemMemStackPushU64(PVMCPUCC pVCpu, uint64_t u64Value) RT_NOEXCEPT;
6301	VBOXSTRICTRC iemMemStackPushU16Ex(PVMCPUCC pVCpu, uint16_t u16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
6302	VBOXSTRICTRC iemMemStackPushU32Ex(PVMCPUCC pVCpu, uint32_t u32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
6303	VBOXSTRICTRC iemMemStackPushU64Ex(PVMCPUCC pVCpu, uint64_t u64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
6304	VBOXSTRICTRC iemMemStackPushU32SReg(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
6305	VBOXSTRICTRC iemMemStackPopBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
6306	void const *ppvMem, uint8_t pbUnmapInfo, uint64_t *puNewRsp) RT_NOEXCEPT;
6307	VBOXSTRICTRC iemMemStackPopContinueSpecial(PVMCPUCC pVCpu, size_t off, size_t cbMem,
6308	void const *ppvMem, uint8_t pbUnmapInfo, uint64_t uCurNewRsp) RT_NOEXCEPT;
6309	VBOXSTRICTRC iemMemStackPopDoneSpecial(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
6310	VBOXSTRICTRC iemMemStackPopU16(PVMCPUCC pVCpu, uint16_t *pu16Value) RT_NOEXCEPT;
6311	VBOXSTRICTRC iemMemStackPopU32(PVMCPUCC pVCpu, uint32_t *pu32Value) RT_NOEXCEPT;
6312	VBOXSTRICTRC iemMemStackPopU64(PVMCPUCC pVCpu, uint64_t *pu64Value) RT_NOEXCEPT;
6313	VBOXSTRICTRC iemMemStackPopU16Ex(PVMCPUCC pVCpu, uint16_t *pu16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
6314	VBOXSTRICTRC iemMemStackPopU32Ex(PVMCPUCC pVCpu, uint32_t *pu32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
6315	VBOXSTRICTRC iemMemStackPopU64Ex(PVMCPUCC pVCpu, uint64_t *pu64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
6316
6317	#ifdef IEM_WITH_SETJMP
6318	void iemMemStackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6319	void iemMemStackPushU32SafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6320	void iemMemStackPushU32SRegSafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6321	void iemMemStackPushU64SafeJmp(PVMCPUCC pVCpu, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6322	void iemMemStackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
6323	void iemMemStackPopGRegU32SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
6324	void iemMemStackPopGRegU64SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
6325
6326	void iemMemFlat32StackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6327	void iemMemFlat32StackPushU32SafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6328	void iemMemFlat32StackPushU32SRegSafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6329	void iemMemFlat32StackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
6330	void iemMemFlat32StackPopGRegU32SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
6331
6332	void iemMemFlat64StackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6333	void iemMemFlat64StackPushU64SafeJmp(PVMCPUCC pVCpu, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6334	void iemMemFlat64StackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
6335	void iemMemFlat64StackPopGRegU64SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
6336
6337	void iemMemStoreStackU16SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6338	void iemMemStoreStackU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6339	void iemMemStoreStackU32SRegSafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6340	void iemMemStoreStackU64SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6341
6342	uint16_t iemMemFetchStackU16SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6343	uint32_t iemMemFetchStackU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6344	uint64_t iemMemFetchStackU64SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6345
6346	#endif
6347
6348	/** @} */
6349
6350	/** @name IEMAllCImpl.cpp
6351	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/'
6352	* @{ */
6353	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem16, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6354	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem32, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6355	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem64, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6356	IEM_CIMPL_PROTO_0(iemCImpl_popa_16);
6357	IEM_CIMPL_PROTO_0(iemCImpl_popa_32);
6358	IEM_CIMPL_PROTO_0(iemCImpl_pusha_16);
6359	IEM_CIMPL_PROTO_0(iemCImpl_pusha_32);
6360	IEM_CIMPL_PROTO_1(iemCImpl_pushf, IEMMODE, enmEffOpSize);
6361	IEM_CIMPL_PROTO_1(iemCImpl_popf, IEMMODE, enmEffOpSize);
6362	IEM_CIMPL_PROTO_3(iemCImpl_FarJmp, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
6363	IEM_CIMPL_PROTO_3(iemCImpl_callf, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
6364	typedef IEM_CIMPL_DECL_TYPE_3(FNIEMCIMPLFARBRANCH, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
6365	typedef FNIEMCIMPLFARBRANCH *PFNIEMCIMPLFARBRANCH;
6366	IEM_CIMPL_PROTO_2(iemCImpl_retf, IEMMODE, enmEffOpSize, uint16_t, cbPop);
6367	IEM_CIMPL_PROTO_3(iemCImpl_enter, IEMMODE, enmEffOpSize, uint16_t, cbFrame, uint8_t, cParameters);
6368	IEM_CIMPL_PROTO_1(iemCImpl_leave, IEMMODE, enmEffOpSize);
6369	IEM_CIMPL_PROTO_2(iemCImpl_int, uint8_t, u8Int, IEMINT, enmInt);
6370	IEM_CIMPL_PROTO_1(iemCImpl_iret_real_v8086, IEMMODE, enmEffOpSize);
6371	IEM_CIMPL_PROTO_4(iemCImpl_iret_prot_v8086, uint32_t, uNewEip, uint16_t, uNewCs, uint32_t, uNewFlags, uint64_t, uNewRsp);
6372	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot_NestedTask, IEMMODE, enmEffOpSize);
6373	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot, IEMMODE, enmEffOpSize);
6374	IEM_CIMPL_PROTO_1(iemCImpl_iret_64bit, IEMMODE, enmEffOpSize);
6375	IEM_CIMPL_PROTO_1(iemCImpl_iret, IEMMODE, enmEffOpSize);
6376	IEM_CIMPL_PROTO_0(iemCImpl_loadall286);
6377	IEM_CIMPL_PROTO_0(iemCImpl_syscall);
6378	IEM_CIMPL_PROTO_1(iemCImpl_sysret, IEMMODE, enmEffOpSize);
6379	IEM_CIMPL_PROTO_0(iemCImpl_sysenter);
6380	IEM_CIMPL_PROTO_1(iemCImpl_sysexit, IEMMODE, enmEffOpSize);
6381	IEM_CIMPL_PROTO_2(iemCImpl_LoadSReg, uint8_t, iSegReg, uint16_t, uSel);
6382	IEM_CIMPL_PROTO_2(iemCImpl_load_SReg, uint8_t, iSegReg, uint16_t, uSel);
6383	IEM_CIMPL_PROTO_2(iemCImpl_pop_Sreg, uint8_t, iSegReg, IEMMODE, enmEffOpSize);
6384	IEM_CIMPL_PROTO_5(iemCImpl_load_SReg_Greg, uint16_t, uSel, uint64_t, offSeg, uint8_t, iSegReg, uint8_t, iGReg, IEMMODE, enmEffOpSize);
6385	IEM_CIMPL_PROTO_2(iemCImpl_VerX, uint16_t, uSel, bool, fWrite);
6386	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u64, uint64_t *, pu64Dst, uint16_t, uSel, bool, fIsLar);
6387	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u16, uint16_t *, pu16Dst, uint16_t, uSel, bool, fIsLar);
6388	IEM_CIMPL_PROTO_3(iemCImpl_lgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
6389	IEM_CIMPL_PROTO_2(iemCImpl_sgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6390	IEM_CIMPL_PROTO_3(iemCImpl_lidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
6391	IEM_CIMPL_PROTO_2(iemCImpl_sidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6392	IEM_CIMPL_PROTO_1(iemCImpl_lldt, uint16_t, uNewLdt);
6393	IEM_CIMPL_PROTO_2(iemCImpl_sldt_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
6394	IEM_CIMPL_PROTO_2(iemCImpl_sldt_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6395	IEM_CIMPL_PROTO_1(iemCImpl_ltr, uint16_t, uNewTr);
6396	IEM_CIMPL_PROTO_2(iemCImpl_str_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
6397	IEM_CIMPL_PROTO_2(iemCImpl_str_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6398	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Cd, uint8_t, iGReg, uint8_t, iCrReg);
6399	IEM_CIMPL_PROTO_2(iemCImpl_smsw_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
6400	IEM_CIMPL_PROTO_2(iemCImpl_smsw_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6401	IEM_CIMPL_PROTO_4(iemCImpl_load_CrX, uint8_t, iCrReg, uint64_t, uNewCrX, IEMACCESSCRX, enmAccessCrX, uint8_t, iGReg);
6402	IEM_CIMPL_PROTO_2(iemCImpl_mov_Cd_Rd, uint8_t, iCrReg, uint8_t, iGReg);
6403	IEM_CIMPL_PROTO_2(iemCImpl_lmsw, uint16_t, u16NewMsw, RTGCPTR, GCPtrEffDst);
6404	IEM_CIMPL_PROTO_0(iemCImpl_clts);
6405	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Dd, uint8_t, iGReg, uint8_t, iDrReg);
6406	IEM_CIMPL_PROTO_2(iemCImpl_mov_Dd_Rd, uint8_t, iDrReg, uint8_t, iGReg);
6407	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Td, uint8_t, iGReg, uint8_t, iTrReg);
6408	IEM_CIMPL_PROTO_2(iemCImpl_mov_Td_Rd, uint8_t, iTrReg, uint8_t, iGReg);
6409	IEM_CIMPL_PROTO_1(iemCImpl_invlpg, RTGCPTR, GCPtrPage);
6410	IEM_CIMPL_PROTO_3(iemCImpl_invpcid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvpcidDesc, uint64_t, uInvpcidType);
6411	IEM_CIMPL_PROTO_0(iemCImpl_invd);
6412	IEM_CIMPL_PROTO_0(iemCImpl_wbinvd);
6413	IEM_CIMPL_PROTO_0(iemCImpl_rsm);
6414	IEM_CIMPL_PROTO_0(iemCImpl_rdtsc);
6415	IEM_CIMPL_PROTO_0(iemCImpl_rdtscp);
6416	IEM_CIMPL_PROTO_0(iemCImpl_rdpmc);
6417	IEM_CIMPL_PROTO_0(iemCImpl_rdmsr);
6418	IEM_CIMPL_PROTO_0(iemCImpl_wrmsr);
6419	IEM_CIMPL_PROTO_3(iemCImpl_in, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
6420	IEM_CIMPL_PROTO_2(iemCImpl_in_eAX_DX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
6421	IEM_CIMPL_PROTO_3(iemCImpl_out, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
6422	IEM_CIMPL_PROTO_2(iemCImpl_out_DX_eAX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
6423	IEM_CIMPL_PROTO_0(iemCImpl_cli);
6424	IEM_CIMPL_PROTO_0(iemCImpl_sti);
6425	IEM_CIMPL_PROTO_0(iemCImpl_hlt);
6426	IEM_CIMPL_PROTO_1(iemCImpl_monitor, uint8_t, iEffSeg);
6427	IEM_CIMPL_PROTO_0(iemCImpl_mwait);
6428	IEM_CIMPL_PROTO_0(iemCImpl_swapgs);
6429	IEM_CIMPL_PROTO_0(iemCImpl_cpuid);
6430	IEM_CIMPL_PROTO_1(iemCImpl_aad, uint8_t, bImm);
6431	IEM_CIMPL_PROTO_1(iemCImpl_aam, uint8_t, bImm);
6432	IEM_CIMPL_PROTO_0(iemCImpl_daa);
6433	IEM_CIMPL_PROTO_0(iemCImpl_das);
6434	IEM_CIMPL_PROTO_0(iemCImpl_aaa);
6435	IEM_CIMPL_PROTO_0(iemCImpl_aas);
6436	IEM_CIMPL_PROTO_3(iemCImpl_bound_16, int16_t, idxArray, int16_t, idxLowerBound, int16_t, idxUpperBound);
6437	IEM_CIMPL_PROTO_3(iemCImpl_bound_32, int32_t, idxArray, int32_t, idxLowerBound, int32_t, idxUpperBound);
6438	IEM_CIMPL_PROTO_0(iemCImpl_xgetbv);
6439	IEM_CIMPL_PROTO_0(iemCImpl_xsetbv);
6440	IEM_CIMPL_PROTO_5(iemCImpl_cmpxchg16b_fallback_rendezvous, PRTUINT128U, pu128Dst, PRTUINT128U, pu128RaxRdx,
6441	PRTUINT128U, pu128RbxRcx, uint32_t *, pEFlags, uint8_t, bUnmapInfo);
6442	IEM_CIMPL_PROTO_2(iemCImpl_clflush_clflushopt, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
6443	IEM_CIMPL_PROTO_1(iemCImpl_finit, bool, fCheckXcpts);
6444	IEM_CIMPL_PROTO_3(iemCImpl_fxsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
6445	IEM_CIMPL_PROTO_3(iemCImpl_fxrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
6446	IEM_CIMPL_PROTO_3(iemCImpl_xsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
6447	IEM_CIMPL_PROTO_3(iemCImpl_xrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
6448	IEM_CIMPL_PROTO_2(iemCImpl_stmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
6449	IEM_CIMPL_PROTO_2(iemCImpl_vstmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
6450	IEM_CIMPL_PROTO_2(iemCImpl_ldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
6451	IEM_CIMPL_PROTO_2(iemCImpl_vldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
6452	IEM_CIMPL_PROTO_3(iemCImpl_fnstenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6453	IEM_CIMPL_PROTO_3(iemCImpl_fnsave, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6454	IEM_CIMPL_PROTO_3(iemCImpl_fldenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6455	IEM_CIMPL_PROTO_3(iemCImpl_frstor, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6456	IEM_CIMPL_PROTO_1(iemCImpl_fldcw, uint16_t, u16Fcw);
6457	IEM_CIMPL_PROTO_2(iemCImpl_fxch_underflow, uint8_t, iStReg, uint16_t, uFpuOpcode);
6458	IEM_CIMPL_PROTO_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, bool, fUCmp, uint32_t, uPopAndFpuOpcode);
6459	IEM_CIMPL_PROTO_2(iemCImpl_rdseed, uint8_t, iReg, IEMMODE, enmEffOpSize);
6460	IEM_CIMPL_PROTO_2(iemCImpl_rdrand, uint8_t, iReg, IEMMODE, enmEffOpSize);
6461	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovps_load_u128, uint8_t, iXRegDst, uint8_t, iXRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6462	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovps_load_u256, uint8_t, iYRegDst, uint8_t, iYRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6463	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovps_store_u128, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iXRegMsk, uint8_t, iXRegSrc);
6464	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovps_store_u256, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iYRegMsk, uint8_t, iYRegSrc);
6465	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovd_load_u128, uint8_t, iXRegDst, uint8_t, iXRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6466	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovd_load_u256, uint8_t, iYRegDst, uint8_t, iYRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6467	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovd_store_u128, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iXRegMsk, uint8_t, iXRegSrc);
6468	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovd_store_u256, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iYRegMsk, uint8_t, iYRegSrc);
6469	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovpd_load_u128, uint8_t, iXRegDst, uint8_t, iXRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6470	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovpd_load_u256, uint8_t, iYRegDst, uint8_t, iYRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6471	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovpd_store_u128, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iXRegMsk, uint8_t, iXRegSrc);
6472	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovpd_store_u256, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iYRegMsk, uint8_t, iYRegSrc);
6473	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovq_load_u128, uint8_t, iXRegDst, uint8_t, iXRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6474	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovq_load_u256, uint8_t, iYRegDst, uint8_t, iYRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6475	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovq_store_u128, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iXRegMsk, uint8_t, iXRegSrc);
6476	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovq_store_u256, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iYRegMsk, uint8_t, iYRegSrc);
6477	IEM_CIMPL_PROTO_2(iemCImpl_vpgather_worker_xx, uint32_t, u32PackedArgs, uint32_t, u32Disp);
6478
6479	/** @} */
6480
6481	/** @name IEMAllCImplStrInstr.cpp.h
6482	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/' -e 's/RT_CONCAT4(//' \
6483	* -e 's/,ADDR_SIZE)/64/g' -e 's/,OP_SIZE,/64/g' -e 's/,OP_rAX,/rax/g' IEMAllCImplStrInstr.cpp.h
6484	* @{ */
6485	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr16, uint8_t, iEffSeg);
6486	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr16, uint8_t, iEffSeg);
6487	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m16);
6488	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m16);
6489	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr16, uint8_t, iEffSeg);
6490	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m16);
6491	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m16, int8_t, iEffSeg);
6492	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr16, bool, fIoChecked);
6493	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr16, bool, fIoChecked);
6494	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6495	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6496
6497	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr16, uint8_t, iEffSeg);
6498	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr16, uint8_t, iEffSeg);
6499	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m16);
6500	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m16);
6501	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr16, uint8_t, iEffSeg);
6502	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m16);
6503	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m16, int8_t, iEffSeg);
6504	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr16, bool, fIoChecked);
6505	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr16, bool, fIoChecked);
6506	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6507	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6508
6509	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr16, uint8_t, iEffSeg);
6510	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr16, uint8_t, iEffSeg);
6511	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m16);
6512	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m16);
6513	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr16, uint8_t, iEffSeg);
6514	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m16);
6515	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m16, int8_t, iEffSeg);
6516	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr16, bool, fIoChecked);
6517	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr16, bool, fIoChecked);
6518	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6519	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6520
6521
6522	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr32, uint8_t, iEffSeg);
6523	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr32, uint8_t, iEffSeg);
6524	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m32);
6525	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m32);
6526	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr32, uint8_t, iEffSeg);
6527	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m32);
6528	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m32, int8_t, iEffSeg);
6529	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr32, bool, fIoChecked);
6530	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr32, bool, fIoChecked);
6531	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6532	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6533
6534	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr32, uint8_t, iEffSeg);
6535	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr32, uint8_t, iEffSeg);
6536	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m32);
6537	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m32);
6538	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr32, uint8_t, iEffSeg);
6539	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m32);
6540	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m32, int8_t, iEffSeg);
6541	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr32, bool, fIoChecked);
6542	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr32, bool, fIoChecked);
6543	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6544	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6545
6546	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr32, uint8_t, iEffSeg);
6547	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr32, uint8_t, iEffSeg);
6548	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m32);
6549	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m32);
6550	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr32, uint8_t, iEffSeg);
6551	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m32);
6552	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m32, int8_t, iEffSeg);
6553	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr32, bool, fIoChecked);
6554	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr32, bool, fIoChecked);
6555	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6556	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6557
6558	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr32, uint8_t, iEffSeg);
6559	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr32, uint8_t, iEffSeg);
6560	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m32);
6561	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m32);
6562	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr32, uint8_t, iEffSeg);
6563	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m32);
6564	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m32, int8_t, iEffSeg);
6565	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr32, bool, fIoChecked);
6566	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr32, bool, fIoChecked);
6567	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6568	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6569
6570
6571	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr64, uint8_t, iEffSeg);
6572	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr64, uint8_t, iEffSeg);
6573	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m64);
6574	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m64);
6575	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr64, uint8_t, iEffSeg);
6576	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m64);
6577	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m64, int8_t, iEffSeg);
6578	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr64, bool, fIoChecked);
6579	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr64, bool, fIoChecked);
6580	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6581	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6582
6583	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr64, uint8_t, iEffSeg);
6584	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr64, uint8_t, iEffSeg);
6585	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m64);
6586	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m64);
6587	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr64, uint8_t, iEffSeg);
6588	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m64);
6589	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m64, int8_t, iEffSeg);
6590	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr64, bool, fIoChecked);
6591	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr64, bool, fIoChecked);
6592	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6593	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6594
6595	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr64, uint8_t, iEffSeg);
6596	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr64, uint8_t, iEffSeg);
6597	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m64);
6598	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m64);
6599	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr64, uint8_t, iEffSeg);
6600	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m64);
6601	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m64, int8_t, iEffSeg);
6602	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr64, bool, fIoChecked);
6603	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr64, bool, fIoChecked);
6604	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6605	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6606
6607	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr64, uint8_t, iEffSeg);
6608	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr64, uint8_t, iEffSeg);
6609	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m64);
6610	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m64);
6611	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr64, uint8_t, iEffSeg);
6612	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m64);
6613	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m64, int8_t, iEffSeg);
6614	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr64, bool, fIoChecked);
6615	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr64, bool, fIoChecked);
6616	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6617	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6618	/** @} */
6619
6620	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
6621	VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT;
6622	VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT;
6623	VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT;
6624	VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT;
6625	VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT;
6626	VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
6627	VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALKFAST pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT;
6628	VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT;
6629	VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT;
6630	VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
6631	bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT;
6632	VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
6633	bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT;
6634	VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6635	VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6636	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6637	VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6638	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6639	VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6640	VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT;
6641	VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
6642	RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT;
6643	VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT;
6644	VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT;
6645	VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT;
6646	uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT;
6647	void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT;
6648	VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
6649	uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT;
6650	bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT;
6651	IEM_CIMPL_PROTO_0(iemCImpl_vmxoff);
6652	IEM_CIMPL_PROTO_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon);
6653	IEM_CIMPL_PROTO_0(iemCImpl_vmlaunch);
6654	IEM_CIMPL_PROTO_0(iemCImpl_vmresume);
6655	IEM_CIMPL_PROTO_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
6656	IEM_CIMPL_PROTO_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
6657	IEM_CIMPL_PROTO_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
6658	IEM_CIMPL_PROTO_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField);
6659	IEM_CIMPL_PROTO_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField);
6660	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField);
6661	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg32, uint64_t *, pu32Dst, uint32_t, u32VmcsField);
6662	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField);
6663	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField);
6664	IEM_CIMPL_PROTO_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType);
6665	IEM_CIMPL_PROTO_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType);
6666	IEM_CIMPL_PROTO_0(iemCImpl_vmx_pause);
6667	#endif
6668
6669	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
6670	VBOXSTRICTRC iemSvmVmexit(PVMCPUCC pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2) RT_NOEXCEPT;
6671	VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr, uint64_t uCr2) RT_NOEXCEPT;
6672	VBOXSTRICTRC iemSvmHandleIOIntercept(PVMCPUCC pVCpu, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
6673	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, uint8_t cbInstr) RT_NOEXCEPT;
6674	VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPUCC pVCpu, uint32_t idMsr, bool fWrite, uint8_t cbInstr) RT_NOEXCEPT;
6675	IEM_CIMPL_PROTO_0(iemCImpl_vmrun);
6676	IEM_CIMPL_PROTO_0(iemCImpl_vmload);
6677	IEM_CIMPL_PROTO_0(iemCImpl_vmsave);
6678	IEM_CIMPL_PROTO_0(iemCImpl_clgi);
6679	IEM_CIMPL_PROTO_0(iemCImpl_stgi);
6680	IEM_CIMPL_PROTO_0(iemCImpl_invlpga);
6681	IEM_CIMPL_PROTO_0(iemCImpl_skinit);
6682	IEM_CIMPL_PROTO_0(iemCImpl_svm_pause);
6683	#endif
6684
6685	IEM_CIMPL_PROTO_0(iemCImpl_vmcall); /* vmx */
6686	IEM_CIMPL_PROTO_0(iemCImpl_vmmcall); /* svm */
6687	IEM_CIMPL_PROTO_1(iemCImpl_Hypercall, uint16_t, uDisOpcode); /* both */
6688
6689	extern const PFNIEMOP g_apfnIemInterpretOnlyOneByteMap[256];
6690	extern const PFNIEMOP g_apfnIemInterpretOnlyTwoByteMap[1024];
6691	extern const PFNIEMOP g_apfnIemInterpretOnlyThreeByte0f3a[1024];
6692	extern const PFNIEMOP g_apfnIemInterpretOnlyThreeByte0f38[1024];
6693	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap1[1024];
6694	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap2[1024];
6695	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap3[1024];
6696
6697	/*
6698	* Recompiler related stuff.
6699	*/
6700	extern const PFNIEMOP g_apfnIemThreadedRecompilerOneByteMap[256];
6701	extern const PFNIEMOP g_apfnIemThreadedRecompilerTwoByteMap[1024];
6702	extern const PFNIEMOP g_apfnIemThreadedRecompilerThreeByte0f3a[1024];
6703	extern const PFNIEMOP g_apfnIemThreadedRecompilerThreeByte0f38[1024];
6704	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap1[1024];
6705	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap2[1024];
6706	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap3[1024];
6707
6708	DECLHIDDEN(int) iemPollTimers(PVMCC pVM, PVMCPUCC pVCpu) RT_NOEXCEPT;
6709
6710	DECLCALLBACK(int) iemTbInit(PVMCC pVM, uint32_t cInitialTbs, uint32_t cMaxTbs,
6711	uint64_t cbInitialExec, uint64_t cbMaxExec, uint32_t cbChunkExec);
6712	void iemThreadedTbObsolete(PVMCPUCC pVCpu, PIEMTB pTb, bool fSafeToFree);
6713	DECLHIDDEN(void) iemTbAllocatorFree(PVMCPUCC pVCpu, PIEMTB pTb);
6714	void iemTbAllocatorProcessDelayedFrees(PVMCPUCC pVCpu, PIEMTBALLOCATOR pTbAllocator);
6715	void iemTbAllocatorFreeupNativeSpace(PVMCPUCC pVCpu, uint32_t cNeededInstrs);
6716	DECLHIDDEN(PIEMTBALLOCATOR) iemTbAllocatorFreeBulkStart(PVMCPUCC pVCpu);
6717	DECLHIDDEN(void) iemTbAllocatorFreeBulk(PVMCPUCC pVCpu, PIEMTBALLOCATOR pTbAllocator, PIEMTB pTb);
6718	DECLHIDDEN(const char ) iemTbFlagsToString(uint32_t fFlags, char pszBuf, size_t cbBuf) RT_NOEXCEPT;
6719	DECLHIDDEN(void) iemThreadedDisassembleTb(PCIEMTB pTb, PCDBGFINFOHLP pHlp) RT_NOEXCEPT;
6720	#if defined(VBOX_WITH_IEM_NATIVE_RECOMPILER) && defined(VBOX_WITH_SAVE_THREADED_TBS_FOR_PROFILING)
6721	DECLHIDDEN(void) iemThreadedSaveTbForProfilingCleanup(PVMCPU pVCpu);
6722	#endif
6723
6724
6725	/** @todo FNIEMTHREADEDFUNC and friends may need more work... */
6726	#if defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
6727	typedef VBOXSTRICTRC /__attribute__((__nothrow__))/ FNIEMTHREADEDFUNC(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
6728	typedef FNIEMTHREADEDFUNC *PFNIEMTHREADEDFUNC;
6729	# define IEM_DECL_IEMTHREADEDFUNC_DEF(a_Name) \
6730	VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2)
6731	# define IEM_DECL_IEMTHREADEDFUNC_PROTO(a_Name) \
6732	VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2)
6733
6734	#else
6735	typedef VBOXSTRICTRC (FNIEMTHREADEDFUNC)(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
6736	typedef FNIEMTHREADEDFUNC *PFNIEMTHREADEDFUNC;
6737	# define IEM_DECL_IEMTHREADEDFUNC_DEF(a_Name) \
6738	IEM_DECL_MSC_GUARD_IGNORE VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2) IEM_NOEXCEPT_MAY_LONGJMP
6739	# define IEM_DECL_IEMTHREADEDFUNC_PROTO(a_Name) \
6740	IEM_DECL_MSC_GUARD_IGNORE VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2) IEM_NOEXCEPT_MAY_LONGJMP
6741	#endif
6742
6743
6744	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_Nop);
6745	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_LogCpuState);
6746
6747	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_DeferToCImpl0);
6748
6749	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckIrq);
6750	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckTimers);
6751	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckTimersAndIrq);
6752	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckMode);
6753	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckHwInstrBps);
6754	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLim);
6755
6756	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodes);
6757	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodes);
6758	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesConsiderCsLim);
6759
6760	/* Branching: */
6761	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndPcAndOpcodes);
6762	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckPcAndOpcodes);
6763	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckPcAndOpcodesConsiderCsLim);
6764
6765	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesLoadingTlb);
6766	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesLoadingTlb);
6767	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesLoadingTlbConsiderCsLim);
6768
6769	/* Natural page crossing: */
6770	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesAcrossPageLoadingTlb);
6771	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesAcrossPageLoadingTlb);
6772	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesAcrossPageLoadingTlbConsiderCsLim);
6773
6774	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesOnNextPageLoadingTlb);
6775	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNextPageLoadingTlb);
6776	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNextPageLoadingTlbConsiderCsLim);
6777
6778	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesOnNewPageLoadingTlb);
6779	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNewPageLoadingTlb);
6780	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNewPageLoadingTlbConsiderCsLim);
6781
6782	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_Jump);
6783
6784	bool iemThreadedCompileEmitIrqCheckBefore(PVMCPUCC pVCpu, PIEMTB pTb);
6785	bool iemThreadedCompileBeginEmitCallsComplications(PVMCPUCC pVCpu, PIEMTB pTb);
6786	#ifdef IEM_WITH_INTRA_TB_JUMPS
6787	DECLHIDDEN(int) iemThreadedCompileBackAtFirstInstruction(PVMCPU pVCpu, PIEMTB pTb) RT_NOEXCEPT;
6788	#endif
6789
6790	/* Native recompiler public bits: */
6791
6792	DECLHIDDEN(PIEMTB) iemNativeRecompile(PVMCPUCC pVCpu, PIEMTB pTb) RT_NOEXCEPT;
6793	DECLHIDDEN(void) iemNativeDisassembleTb(PVMCPU pVCpu, PCIEMTB pTb, PCDBGFINFOHLP pHlp) RT_NOEXCEPT;
6794	int iemExecMemAllocatorInit(PVMCPU pVCpu, uint64_t cbMax, uint64_t cbInitial, uint32_t cbChunk) RT_NOEXCEPT;
6795	DECLHIDDEN(PIEMNATIVEINSTR) iemExecMemAllocatorAlloc(PVMCPU pVCpu, uint32_t cbReq, PIEMTB pTb, PIEMNATIVEINSTR *ppaExec,
6796	struct IEMNATIVEPERCHUNKCTX const **ppChunkCtx) RT_NOEXCEPT;
6797	DECLHIDDEN(PIEMNATIVEINSTR) iemExecMemAllocatorAllocFromChunk(PVMCPU pVCpu, uint32_t idxChunk, uint32_t cbReq,
6798	PIEMNATIVEINSTR *ppaExec);
6799	DECLHIDDEN(void) iemExecMemAllocatorReadyForUse(PVMCPUCC pVCpu, void *pv, size_t cb) RT_NOEXCEPT;
6800	void iemExecMemAllocatorFree(PVMCPU pVCpu, void *pv, size_t cb) RT_NOEXCEPT;
6801	DECLASM(DECL_NO_RETURN(void)) iemNativeTbLongJmp(void *pvFramePointer, int rc) RT_NOEXCEPT;
6802	DECLHIDDEN(struct IEMNATIVEPERCHUNKCTX const *) iemExecMemGetTbChunkCtx(PVMCPU pVCpu, PCIEMTB pTb);
6803	DECLHIDDEN(int) iemNativeRecompileAttachExecMemChunkCtx(PVMCPU pVCpu, uint32_t idxChunk, struct IEMNATIVEPERCHUNKCTX const **ppCtx);
6804
6805	/** Packed 32-bit argument for iemCImpl_vpgather_worker_xx. */
6806	typedef union IEMGATHERARGS
6807	{
6808	/** Integer view. */
6809	uint32_t u;
6810	/** Bitfield view. */
6811	struct
6812	{
6813	uint32_t iYRegDst : 4; /*< 0 - XMM or YMM register number (destination) /
6814	uint32_t iYRegIdc : 4; /*< 4 - XMM or YMM register number (indices) /
6815	uint32_t iYRegMsk : 4; /*< 8 - XMM or YMM register number (mask) /
6816	uint32_t iGRegBase : 4; /*< 12 - general register number (base ptr) /
6817	uint32_t iScale : 2; /*< 16 - scale factor (1/2/4/8) /
6818	uint32_t enmEffOpSize : 2; /*< 18 - operand size (16/32/64/--) /
6819	uint32_t enmEffAddrMode : 2; /*< 20 - addressing mode (16/32/64/--) /
6820	uint32_t iEffSeg : 3; /*< 22 - effective segment (ES/CS/SS/DS/FS/GS) /
6821	uint32_t fVex256 : 1; /*< 25 - overall instruction width (128/256 bits) /
6822	uint32_t fIdxQword : 1; /*< 26 - individual index width (4/8 bytes) /
6823	uint32_t fValQword : 1; /*< 27 - individual value width (4/8 bytes) /
6824	} s;
6825	} IEMGATHERARGS;
6826	AssertCompileSize(IEMGATHERARGS, sizeof(uint32_t));
6827
6828	#endif /* !RT_IN_ASSEMBLER - ASM-NOINC-END */
6829
6830
6831	/** @} */
6832
6833	RT_C_DECLS_END
6834
6835	/* ASM-INC: %include "IEMInternalStruct.mac" */
6836
6837	#endif /* !VMM_INCLUDED_SRC_include_IEMInternal_h */
6838

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source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h@ 108178

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