IEMInternal.h@ 62250

Last change on this file since 62250 was 62171, checked in by vboxsync, 9 years ago
IEM: Working on instruction fetching optimizations (incomplete and disabled).
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1	/* $Id: IEMInternal.h 62171 2016-07-11 18:30:07Z vboxsync $ */
2	/** @file
3	* IEM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2011-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef ___IEMInternal_h
19	#define ___IEMInternal_h
20
21	#include <VBox/vmm/cpum.h>
22	#include <VBox/vmm/iem.h>
23	#include <VBox/vmm/stam.h>
24	#include <VBox/param.h>
25
26	#include <setjmp.h>
27
28
29	RT_C_DECLS_BEGIN
30
31
32	/** @defgroup grp_iem_int Internals
33	* @ingroup grp_iem
34	* @internal
35	* @{
36	*/
37
38	/** For expanding symbol in slickedit and other products tagging and
39	* crossreferencing IEM symbols. */
40	#ifndef IEM_STATIC
41	# define IEM_STATIC static
42	#endif
43
44	/** @def IEM_VERIFICATION_MODE_FULL
45	* Shorthand for:
46	* defined(IEM_VERIFICATION_MODE) && !defined(IEM_VERIFICATION_MODE_MINIMAL)
47	*/
48	#if (defined(IEM_VERIFICATION_MODE) && !defined(IEM_VERIFICATION_MODE_MINIMAL) && !defined(IEM_VERIFICATION_MODE_FULL)) \
49	\|\| defined(DOXYGEN_RUNNING)
50	# define IEM_VERIFICATION_MODE_FULL
51	#endif
52
53
54	/** @def IEM_CFG_TARGET_CPU
55	* The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
56	*
57	* By default we allow this to be configured by the user via the
58	* CPUM/GuestCpuName config string, but this comes at a slight cost during
59	* decoding. So, for applications of this code where there is no need to
60	* be dynamic wrt target CPU, just modify this define.
61	*/
62	#if !defined(IEM_CFG_TARGET_CPU) \|\| defined(DOXYGEN_RUNNING)
63	# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
64	#endif
65
66
67
68	/** Finish and move to types.h */
69	typedef union
70	{
71	uint32_t u32;
72	} RTFLOAT32U;
73	typedef RTFLOAT32U *PRTFLOAT32U;
74	typedef RTFLOAT32U const *PCRTFLOAT32U;
75
76
77	/**
78	* Extended operand mode that includes a representation of 8-bit.
79	*
80	* This is used for packing down modes when invoking some C instruction
81	* implementations.
82	*/
83	typedef enum IEMMODEX
84	{
85	IEMMODEX_16BIT = IEMMODE_16BIT,
86	IEMMODEX_32BIT = IEMMODE_32BIT,
87	IEMMODEX_64BIT = IEMMODE_64BIT,
88	IEMMODEX_8BIT
89	} IEMMODEX;
90	AssertCompileSize(IEMMODEX, 4);
91
92
93	/**
94	* Branch types.
95	*/
96	typedef enum IEMBRANCH
97	{
98	IEMBRANCH_JUMP = 1,
99	IEMBRANCH_CALL,
100	IEMBRANCH_TRAP,
101	IEMBRANCH_SOFTWARE_INT,
102	IEMBRANCH_HARDWARE_INT
103	} IEMBRANCH;
104	AssertCompileSize(IEMBRANCH, 4);
105
106
107	/**
108	* A FPU result.
109	*/
110	typedef struct IEMFPURESULT
111	{
112	/** The output value. */
113	RTFLOAT80U r80Result;
114	/** The output status. */
115	uint16_t FSW;
116	} IEMFPURESULT;
117	AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
118	/** Pointer to a FPU result. */
119	typedef IEMFPURESULT *PIEMFPURESULT;
120	/** Pointer to a const FPU result. */
121	typedef IEMFPURESULT const *PCIEMFPURESULT;
122
123
124	/**
125	* A FPU result consisting of two output values and FSW.
126	*/
127	typedef struct IEMFPURESULTTWO
128	{
129	/** The first output value. */
130	RTFLOAT80U r80Result1;
131	/** The output status. */
132	uint16_t FSW;
133	/** The second output value. */
134	RTFLOAT80U r80Result2;
135	} IEMFPURESULTTWO;
136	AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
137	AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
138	/** Pointer to a FPU result consisting of two output values and FSW. */
139	typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
140	/** Pointer to a const FPU result consisting of two output values and FSW. */
141	typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
142
143
144
145	#ifdef IEM_VERIFICATION_MODE_FULL
146
147	/**
148	* Verification event type.
149	*/
150	typedef enum IEMVERIFYEVENT
151	{
152	IEMVERIFYEVENT_INVALID = 0,
153	IEMVERIFYEVENT_IOPORT_READ,
154	IEMVERIFYEVENT_IOPORT_WRITE,
155	IEMVERIFYEVENT_IOPORT_STR_READ,
156	IEMVERIFYEVENT_IOPORT_STR_WRITE,
157	IEMVERIFYEVENT_RAM_WRITE,
158	IEMVERIFYEVENT_RAM_READ
159	} IEMVERIFYEVENT;
160
161	/** Checks if the event type is a RAM read or write. */
162	# define IEMVERIFYEVENT_IS_RAM(a_enmType) ((a_enmType) == IEMVERIFYEVENT_RAM_WRITE \|\| (a_enmType) == IEMVERIFYEVENT_RAM_READ)
163
164	/**
165	* Verification event record.
166	*/
167	typedef struct IEMVERIFYEVTREC
168	{
169	/** Pointer to the next record in the list. */
170	struct IEMVERIFYEVTREC *pNext;
171	/** The event type. */
172	IEMVERIFYEVENT enmEvent;
173	/** The event data. */
174	union
175	{
176	/** IEMVERIFYEVENT_IOPORT_READ */
177	struct
178	{
179	RTIOPORT Port;
180	uint8_t cbValue;
181	} IOPortRead;
182
183	/** IEMVERIFYEVENT_IOPORT_WRITE */
184	struct
185	{
186	RTIOPORT Port;
187	uint8_t cbValue;
188	uint32_t u32Value;
189	} IOPortWrite;
190
191	/** IEMVERIFYEVENT_IOPORT_STR_READ */
192	struct
193	{
194	RTIOPORT Port;
195	uint8_t cbValue;
196	RTGCUINTREG cTransfers;
197	} IOPortStrRead;
198
199	/** IEMVERIFYEVENT_IOPORT_STR_WRITE */
200	struct
201	{
202	RTIOPORT Port;
203	uint8_t cbValue;
204	RTGCUINTREG cTransfers;
205	} IOPortStrWrite;
206
207	/** IEMVERIFYEVENT_RAM_READ */
208	struct
209	{
210	RTGCPHYS GCPhys;
211	uint32_t cb;
212	} RamRead;
213
214	/** IEMVERIFYEVENT_RAM_WRITE */
215	struct
216	{
217	RTGCPHYS GCPhys;
218	uint32_t cb;
219	uint8_t ab[512];
220	} RamWrite;
221	} u;
222	} IEMVERIFYEVTREC;
223	/** Pointer to an IEM event verification records. */
224	typedef IEMVERIFYEVTREC *PIEMVERIFYEVTREC;
225
226	#endif /* IEM_VERIFICATION_MODE_FULL */
227
228
229	/**
230	* IEM TLB entry.
231	*
232	* Lookup assembly:
233	* @code{.asm}
234	; Calculate tag.
235	mov rax, [VA]
236	shl rax, 16
237	shr rax, 16 + X86_PAGE_SHIFT
238	or rax, [uTlbRevision]
239
240	; Do indexing.
241	movzx ecx, al
242	lea rcx, [pTlbEntries + rcx]
243
244	; Check tag.
245	cmp [rcx + IEMTLBENTRY.uTag], rax
246	jne .TlbMiss
247
248	; Check access.
249	movsx rax, ACCESS_FLAGS \| MAPPING_R3_NOT_VALID \| 0xffffff00
250	and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
251	cmp rax, [uTlbPhysRev]
252	jne .TlbMiss
253
254	; Calc address and we're done.
255	mov eax, X86_PAGE_OFFSET_MASK
256	and eax, [VA]
257	or rax, [rcx + IEMTLBENTRY.pMappingR3]
258	%ifdef VBOX_WITH_STATISTICS
259	inc qword [cTlbHits]
260	%endif
261	jmp .Done
262
263	.TlbMiss:
264	mov r8d, ACCESS_FLAGS
265	mov rdx, [VA]
266	mov rcx, [pVCpu]
267	call iemTlbTypeMiss
268	.Done:
269
270	@endcode
271	*
272	*/
273	typedef struct IEMTLBENTRY
274	{
275	/** The TLB entry tag.
276	* Bits 35 thru 0 are made up of the virtual address shifted right 12 bits.
277	* Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
278	*
279	* The TLB lookup code uses the current TLB revision, which won't ever be zero,
280	* enabling an extremely cheap TLB invalidation most of the time. When the TLB
281	* revision wraps around though, the tags needs to be zeroed.
282	*
283	* @note Try use SHRD instruction? After seeing
284	* https://gmplib.org/~tege/x86-timing.pdf, maybe not.
285	*/
286	uint64_t uTag;
287	/** Access flags and physical TLB revision.
288	*
289	* - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
290	* - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
291	* - Bit 2 - page tables - not user (complemented X86_PTE_US).
292	* - Bit 3 - pgm phys/virt - not directly writable.
293	* - Bit 4 - pgm phys page - not directly readable.
294	* - Bit 5 - currently unused.
295	* - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
296	* - Bit 7 - tlb entry - pMappingR3 member not valid.
297	* - Bits 63 thru 8 are used for the physical TLB revision number.
298	*
299	* We're using complemented bit meanings here because it makes it easy to check
300	* whether special action is required. For instance a user mode write access
301	* would do a "TEST fFlags, (X86_PTE_RW \| X86_PTE_US \| X86_PTE_D)" and a
302	* non-zero result would mean special handling needed because either it wasn't
303	* writable, or it wasn't user, or the page wasn't dirty. A user mode read
304	* access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
305	* need to check any PTE flag.
306	*/
307	uint64_t fFlagsAndPhysRev;
308	/** The guest physical page address. */
309	uint64_t GCPhys;
310	/** Pointer to the ring-3 mapping (possibly also valid in ring-0). */
311	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
312	R3PTRTYPE(uint8_t *) pMappingR3;
313	#else
314	R3R0PTRTYPE(uint8_t *) pMappingR3;
315	#endif
316	#if HC_ARCH_BITS == 32
317	uint32_t u32Padding1;
318	#endif
319	} IEMTLBENTRY;
320	AssertCompileSize(IEMTLBENTRY, 32);
321	/** Pointer to an IEM TLB entry. */
322	typedef IEMTLBENTRY *PIEMTLBENTRY;
323
324	/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
325	* @{ */
326	#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /*< Page tables: Not executable. /
327	#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /*< Page tables: Not writable. /
328	#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /*< Page tables: Not user accessible (supervisor only). /
329	#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /*< Phys page: Not writable (access handler, ROM, whatever). /
330	#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /*< Phys page: Not readable (MMIO / access handler, ROM) /
331	#define IEMTLBE_F_UNUSED RT_BIT_64(5) /*< Currently unused. /
332	#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /*< Page tables: Not dirty (needs to be made dirty on write). /
333	#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(7) /*< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. /
334	/** @} */
335
336
337	/**
338	* An IEM TLB.
339	*
340	* We've got two of these, one for data and one for instructions.
341	*/
342	typedef struct IEMTLB
343	{
344	/** The TLB entries.
345	* We've choosen 256 because that way we can obtain the result directly from a
346	* 8-bit register without an additional AND instruction. */
347	IEMTLBENTRY aEntries[256];
348	/** The TLB revision.
349	* This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
350	* by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
351	* the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
352	* (The revision zero indicates an invalid TLB entry.)
353	*
354	* The initial value is choosen to cause an early wraparound. */
355	uint64_t uTlbRevision;
356	/** The TLB physical address revision - shadow of PGM variable.
357	*
358	* This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
359	* incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
360	* a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
361	* as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
362	*
363	* The initial value is choosen to cause an early wraparound. */
364	uint64_t volatile uTlbPhysRev;
365
366	/* Statistics: */
367
368	/** TLB hits (VBOX_WITH_STATISTICS only). */
369	uint64_t cTlbHits;
370	/** TLB misses. */
371	uint32_t cTlbMisses;
372	/** TLB misses because of tag mismatch. */
373	uint32_t cTlbMissesTag;
374	/** TLB misses because of virtual access violation. */
375	uint32_t cTlbMissesVirtAccess;
376	/** TLB misses because of dirty bit. */
377	uint32_t cTlbMissesDirty;
378	/** TLB misses because of MMIO */
379	uint32_t cTlbMissesMmio;
380	/** TLB misses because of write access handlers. */
381	uint32_t cTlbMissesWriteHandler;
382	/** TLB misses because no r3(/r0) mapping. */
383	uint32_t cTlbMissesMapping;
384	/** Alignment padding. */
385	uint32_t au32Padding[3];
386	} IEMTLB;
387	AssertCompileSizeAlignment(IEMTLB, 64);
388
389
390	/**
391	* The per-CPU IEM state.
392	*/
393	typedef struct IEMCPU
394	{
395	/** Info status code that needs to be propagated to the IEM caller.
396	* This cannot be passed internally, as it would complicate all success
397	* checks within the interpreter making the code larger and almost impossible
398	* to get right. Instead, we'll store status codes to pass on here. Each
399	* source of these codes will perform appropriate sanity checks. */
400	int32_t rcPassUp; /* 0x00 */
401
402	/** The current CPU execution mode (CS). */
403	IEMMODE enmCpuMode; /* 0x04 */
404	/** The CPL. */
405	uint8_t uCpl; /* 0x08 */
406
407	/** Whether to bypass access handlers or not. */
408	bool fBypassHandlers; /* 0x09 */
409	/** Indicates that we're interpreting patch code - RC only! */
410	bool fInPatchCode; /* 0x0a */
411
412	/** @name Decoder state.
413	* @{ */
414	#ifdef IEM_WITH_CODE_TLB
415	/** Unused. */
416	uint8_t bUnused0; /* 0x0b */
417	/** The offset of the next instruction byte. */
418	uint32_t offInstrNextByte; /* 0x0c */
419	/** Pointer to the page containing RIP, user specified buffer or abOpcode.
420	* This can be NULL if the page isn't mappable for some reason, in which
421	* case we'll do fallback stuff.
422	*
423	* If we're executing an instruction from a user specified buffer,
424	* IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
425	* aligned pointer but pointer to the user data.
426	*
427	* For instructions crossing pages, this will start on the first page and be
428	* advanced to the next page by the time we've decoded the instruction. This
429	* therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
430	*/
431	uint8_t const pbInstrBuf; / 0x10 */
432	# if defined(IN_RC) && HC_ARCH_BITS != 32
433	uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
434	# endif
435	/** The program counter corresponding to pbInstrBuf.
436	* This is set to a non-canonical address when we need to invalidate it. */
437	uint64_t uInstrBufPc; /* 0x18 */
438	/** The number of bytes available at pbInstrBuf for the current instruction.
439	* This takes the max opcode length into account so that doesn't need to be
440	* checked separately. */
441	uint32_t cbInstrBuf; /* 0x20 */
442	/** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
443	* This takes the CS segment limit into account. */
444	uint16_t cbInstrBufTotal; /* 0x24 */
445	/** Offset into pbInstrBuf of the first byte of the current instruction. */
446	uint16_t offCurInstrStart; /* 0x26 */
447
448	/** The prefix mask (IEM_OP_PRF_XXX). */
449	uint32_t fPrefixes; /* 0x28 */
450	/** The extra REX ModR/M register field bit (REX.R << 3). */
451	uint8_t uRexReg; /* 0x2c */
452	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
453	* (REX.B << 3). */
454	uint8_t uRexB; /* 0x2d */
455	/** The extra REX SIB index field bit (REX.X << 3). */
456	uint8_t uRexIndex; /* 0x2e */
457
458	/** The effective segment register (X86_SREG_XXX). */
459	uint8_t iEffSeg; /* 0x2f */
460
461	#else
462	/** The current offset into abOpcodes. */
463	uint8_t offOpcode; /* 0x0b */
464	/** The size of what has currently been fetched into abOpcodes. */
465	uint8_t cbOpcode; /* 0x0c */
466
467	/** The effective segment register (X86_SREG_XXX). */
468	uint8_t iEffSeg; /* 0x0d */
469
470	/** The extra REX ModR/M register field bit (REX.R << 3). */
471	uint8_t uRexReg; /* 0x0e */
472	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
473	* (REX.B << 3). */
474	uint8_t uRexB; /* 0x0f */
475	/** The prefix mask (IEM_OP_PRF_XXX). */
476	uint32_t fPrefixes; /* 0x10 */
477	/** The extra REX SIB index field bit (REX.X << 3). */
478	uint8_t uRexIndex; /* 0x14 */
479
480	/** Explicit alignment padding. */
481	uint8_t abAlignment1[3]; /* 0x15 */
482	#endif
483
484	/** The effective operand mode . */
485	IEMMODE enmEffOpSize; /* 0x30, 0x18 */
486	/** The default addressing mode . */
487	IEMMODE enmDefAddrMode; /* 0x34, 0x1c */
488	/** The effective addressing mode . */
489	IEMMODE enmEffAddrMode; /* 0x38, 0x20 */
490	/** The default operand mode . */
491	IEMMODE enmDefOpSize; /* 0x3c, 0x24 */
492
493	/** The FPU opcode (FOP). */
494	uint16_t uFpuOpcode; /* 0x40, 0x28 */
495	/** Align the opcode buffer on a dword boundrary. */
496	uint8_t abAlignment2a[2]; /* 0x42, 0x2a */
497
498	/** The opcode bytes. */
499	uint8_t abOpcode[15]; /* 0x44, 0x2c */
500	/** Explicit alignment padding. */
501	#ifdef IEM_WITH_CODE_TLB
502	uint8_t abAlignment2b[1+4]; /* 0x53 */
503	#else
504	uint8_t abAlignment2b[1+28]; /* 0x3b */
505	#endif
506	/** @} */
507
508
509	/** The flags of the current exception / interrupt. */
510	uint32_t fCurXcpt; /* 0x58, 0x58 */
511	/** The current exception / interrupt. */
512	uint8_t uCurXcpt;
513	/** Exception / interrupt recursion depth. */
514	int8_t cXcptRecursions;
515
516	/** The number of active guest memory mappings. */
517	uint8_t cActiveMappings;
518	/** The next unused mapping index. */
519	uint8_t iNextMapping;
520	/** Records for tracking guest memory mappings. */
521	struct
522	{
523	/** The address of the mapped bytes. */
524	void *pv;
525	#if defined(IN_RC) && HC_ARCH_BITS == 64
526	uint32_t u32Alignment3; /*< Alignment padding. /
527	#endif
528	/** The access flags (IEM_ACCESS_XXX).
529	* IEM_ACCESS_INVALID if the entry is unused. */
530	uint32_t fAccess;
531	#if HC_ARCH_BITS == 64
532	uint32_t u32Alignment4; /*< Alignment padding. /
533	#endif
534	} aMemMappings[3];
535
536	/** Locking records for the mapped memory. */
537	union
538	{
539	PGMPAGEMAPLOCK Lock;
540	uint64_t au64Padding[2];
541	} aMemMappingLocks[3];
542
543	/** Bounce buffer info.
544	* This runs in parallel to aMemMappings. */
545	struct
546	{
547	/** The physical address of the first byte. */
548	RTGCPHYS GCPhysFirst;
549	/** The physical address of the second page. */
550	RTGCPHYS GCPhysSecond;
551	/** The number of bytes in the first page. */
552	uint16_t cbFirst;
553	/** The number of bytes in the second page. */
554	uint16_t cbSecond;
555	/** Whether it's unassigned memory. */
556	bool fUnassigned;
557	/** Explicit alignment padding. */
558	bool afAlignment5[3];
559	} aMemBbMappings[3];
560
561	/** Bounce buffer storage.
562	* This runs in parallel to aMemMappings and aMemBbMappings. */
563	struct
564	{
565	uint8_t ab[512];
566	} aBounceBuffers[3];
567
568
569	/** Pointer set jump buffer - ring-3 context. */
570	R3PTRTYPE(jmp_buf *) pJmpBufR3;
571	/** Pointer set jump buffer - ring-0 context. */
572	R0PTRTYPE(jmp_buf *) pJmpBufR0;
573	/** Pointer set jump buffer - raw-mode context. */
574	RCPTRTYPE(jmp_buf *) pJmpBufRC;
575
576	/** @name Statistics
577	* @{ */
578	/** The number of instructions we've executed. */
579	uint32_t cInstructions;
580	/** The number of potential exits. */
581	uint32_t cPotentialExits;
582	/** The number of bytes data or stack written (mostly for IEMExecOneEx).
583	* This may contain uncommitted writes. */
584	uint32_t cbWritten;
585	/** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
586	uint32_t cRetInstrNotImplemented;
587	/** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
588	uint32_t cRetAspectNotImplemented;
589	/** Counts informational statuses returned (other than VINF_SUCCESS). */
590	uint32_t cRetInfStatuses;
591	/** Counts other error statuses returned. */
592	uint32_t cRetErrStatuses;
593	/** Number of times rcPassUp has been used. */
594	uint32_t cRetPassUpStatus;
595	/** Number of times RZ left with instruction commit pending for ring-3. */
596	uint32_t cPendingCommit;
597	/** Number of long jumps. */
598	uint32_t cLongJumps;
599	uint32_t uAlignment6; /*< Alignment padding. /
600	#ifdef IEM_VERIFICATION_MODE_FULL
601	/** The Number of I/O port reads that has been performed. */
602	uint32_t cIOReads;
603	/** The Number of I/O port writes that has been performed. */
604	uint32_t cIOWrites;
605	/** Set if no comparison to REM is currently performed.
606	* This is used to skip past really slow bits. */
607	bool fNoRem;
608	/** Saved fNoRem flag used by #iemInitExec and #iemUninitExec. */
609	bool fNoRemSavedByExec;
610	/** Indicates that RAX and RDX differences should be ignored since RDTSC
611	* and RDTSCP are timing sensitive. */
612	bool fIgnoreRaxRdx;
613	/** Indicates that a MOVS instruction with overlapping source and destination
614	* was executed, causing the memory write records to be incorrrect. */
615	bool fOverlappingMovs;
616	/** Set if there are problematic memory accesses (MMIO, write monitored, ++). */
617	bool fProblematicMemory;
618	/** This is used to communicate a CPL changed caused by IEMInjectTrap that
619	* CPUM doesn't yet reflect. */
620	uint8_t uInjectCpl;
621	/** To prevent EMR3HmSingleInstruction from triggering endless recursion via
622	* emR3ExecuteInstruction and iemExecVerificationModeCheck. */
623	uint8_t cVerifyDepth;
624	bool afAlignment7[2];
625	/** Mask of undefined eflags.
626	* The verifier will any difference in these flags. */
627	uint32_t fUndefinedEFlags;
628	/** The CS of the instruction being interpreted. */
629	RTSEL uOldCs;
630	/** The RIP of the instruction being interpreted. */
631	uint64_t uOldRip;
632	/** The physical address corresponding to abOpcodes[0]. */
633	RTGCPHYS GCPhysOpcodes;
634	#endif
635	/** @} */
636
637	/** @name Target CPU information.
638	* @{ */
639	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
640	/** The target CPU. */
641	uint32_t uTargetCpu;
642	#else
643	uint32_t u32TargetCpuPadding;
644	#endif
645	/** The CPU vendor. */
646	CPUMCPUVENDOR enmCpuVendor;
647	/** @} */
648
649	/** @name Host CPU information.
650	* @{ */
651	/** The CPU vendor. */
652	CPUMCPUVENDOR enmHostCpuVendor;
653	/** @} */
654
655	uint32_t au32Alignment8[HC_ARCH_BITS == 64 ? 1 + 2 + 8 : 1 + 2]; /*< Alignment padding. /
656
657	/** Data TLB.
658	* @remarks Must be 64-byte aligned. */
659	IEMTLB DataTlb;
660	/** Instruction TLB.
661	* @remarks Must be 64-byte aligned. */
662	IEMTLB CodeTlb;
663
664	/** Pointer to the CPU context - ring-3 context.
665	* @todo put inside IEM_VERIFICATION_MODE_FULL++. */
666	R3PTRTYPE(PCPUMCTX) pCtxR3;
667	/** Pointer to the CPU context - ring-0 context. */
668	R0PTRTYPE(PCPUMCTX) pCtxR0;
669	/** Pointer to the CPU context - raw-mode context. */
670	RCPTRTYPE(PCPUMCTX) pCtxRC;
671	/** Alignment padding. */
672	RTRCPTR uAlignment9;
673
674	#ifdef IEM_VERIFICATION_MODE_FULL
675	/** The event verification records for what IEM did (LIFO). */
676	R3PTRTYPE(PIEMVERIFYEVTREC) pIemEvtRecHead;
677	/** Insertion point for pIemEvtRecHead. */
678	R3PTRTYPE(PIEMVERIFYEVTREC *) ppIemEvtRecNext;
679	/** The event verification records for what the other party did (FIFO). */
680	R3PTRTYPE(PIEMVERIFYEVTREC) pOtherEvtRecHead;
681	/** Insertion point for pOtherEvtRecHead. */
682	R3PTRTYPE(PIEMVERIFYEVTREC *) ppOtherEvtRecNext;
683	/** List of free event records. */
684	R3PTRTYPE(PIEMVERIFYEVTREC) pFreeEvtRec;
685	#endif
686	} IEMCPU;
687	AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
688	AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
689	/** Pointer to the per-CPU IEM state. */
690	typedef IEMCPU *PIEMCPU;
691	/** Pointer to the const per-CPU IEM state. */
692	typedef IEMCPU const *PCIEMCPU;
693
694
695	/** @def IEM_GET_CTX
696	* Gets the guest CPU context for the calling EMT.
697	* @returns PCPUMCTX
698	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
699	*/
700	#if !defined(IEM_VERIFICATION_MODE_FULL) && !defined(IEM_VERIFICATION_MODE) \
701	&& !defined(IEM_VERIFICATION_MODE_MINIMAL) && defined(VMCPU_INCL_CPUM_GST_CTX)
702	# define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
703	#else
704	# define IEM_GET_CTX(a_pVCpu) ((a_pVCpu)->iem.s.CTX_SUFF(pCtx))
705	#endif
706
707	/** Gets the current IEMTARGETCPU value.
708	* @returns IEMTARGETCPU value.
709	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
710	*/
711	#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
712	# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
713	#else
714	# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
715	#endif
716
717	/** @def Gets the instruction length. */
718	#ifdef IEM_WITH_CODE_TLB
719	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(a_pVCpu)->iem.s.offCurInstrStart)
720	#else
721	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
722	#endif
723
724
725	/** @name IEM_ACCESS_XXX - Access details.
726	* @{ */
727	#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
728	#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
729	#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
730	#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
731	#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
732	#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
733	#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
734	#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
735	#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
736	#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
737	/** The writes are partial, so if initialize the bounce buffer with the
738	* orignal RAM content. */
739	#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
740	/** Used in aMemMappings to indicate that the entry is bounce buffered. */
741	#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
742	/** Bounce buffer with ring-3 write pending, first page. */
743	#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
744	/** Bounce buffer with ring-3 write pending, second page. */
745	#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
746	/** Valid bit mask. */
747	#define IEM_ACCESS_VALID_MASK UINT32_C(0x00000fff)
748	/** Read+write data alias. */
749	#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
750	/** Write data alias. */
751	#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
752	/** Read data alias. */
753	#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_DATA)
754	/** Instruction fetch alias. */
755	#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_WHAT_CODE)
756	/** Stack write alias. */
757	#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
758	/** Stack read alias. */
759	#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_STACK)
760	/** Stack read+write alias. */
761	#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
762	/** Read system table alias. */
763	#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_SYS)
764	/** Read+write system table alias. */
765	#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_SYS)
766	/** @} */
767
768	/** @name Prefix constants (IEMCPU::fPrefixes)
769	* @{ */
770	#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /*< CS segment prefix (0x2e). /
771	#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /*< SS segment prefix (0x36). /
772	#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /*< DS segment prefix (0x3e). /
773	#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /*< ES segment prefix (0x26). /
774	#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /*< FS segment prefix (0x64). /
775	#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /*< GS segment prefix (0x65). /
776	#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
777
778	#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /*< Operand size prefix (0x66). /
779	#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /*< REX.W prefix (0x48-0x4f). /
780	#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /*< Address size prefix (0x67). /
781
782	#define IEM_OP_PRF_LOCK RT_BIT_32(16) /*< Lock prefix (0xf0). /
783	#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /*< Repeat-not-zero prefix (0xf2). /
784	#define IEM_OP_PRF_REPZ RT_BIT_32(18) /*< Repeat-if-zero prefix (0xf3). /
785
786	#define IEM_OP_PRF_REX RT_BIT_32(24) /*< Any REX prefix (0x40-0x4f). /
787	#define IEM_OP_PRF_REX_R RT_BIT_32(25) /*< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). /
788	#define IEM_OP_PRF_REX_B RT_BIT_32(26) /*< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). /
789	#define IEM_OP_PRF_REX_X RT_BIT_32(27) /*< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). /
790	/** Mask with all the REX prefix flags.
791	* This is generally for use when needing to undo the REX prefixes when they
792	* are followed legacy prefixes and therefore does not immediately preceed
793	* the first opcode byte.
794	* For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
795	#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX \| IEM_OP_PRF_REX_R \| IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X \| IEM_OP_PRF_SIZE_REX_W )
796	/** @} */
797
798	/** @name Opcode forms
799	* @{ */
800	/** ModR/M: reg, r/m */
801	#define IEMOPFORM_RM 0
802	/** ModR/M: reg, r/m (register) */
803	#define IEMOPFORM_RM_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
804	/** ModR/M: reg, r/m (memory) */
805	#define IEMOPFORM_RM_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
806	/** ModR/M: r/m, reg */
807	#define IEMOPFORM_MR 1
808	/** ModR/M: r/m (register), reg */
809	#define IEMOPFORM_MR_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
810	/** ModR/M: r/m (memory), reg */
811	#define IEMOPFORM_MR_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
812	/** ModR/M: r/m only */
813	#define IEMOPFORM_M 2
814	/** ModR/M: r/m only (register). */
815	#define IEMOPFORM_M_REG (IEMOPFORM_M \| IEMOPFORM_MOD3)
816	/** ModR/M: r/m only (memory). */
817	#define IEMOPFORM_M_MEM (IEMOPFORM_M \| IEMOPFORM_NOT_MOD3)
818	/** ModR/M: reg only */
819	#define IEMOPFORM_R 3
820
821	/** Fixed register instruction, no R/M. */
822	#define IEMOPFORM_FIXED 4
823
824	/** The r/m is a register. */
825	#define IEMOPFORM_MOD3 RT_BIT_32(8)
826	/** The r/m is a memory access. */
827	#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
828	/** @} */
829
830	/**
831	* Possible hardware task switch sources.
832	*/
833	typedef enum IEMTASKSWITCH
834	{
835	/** Task switch caused by an interrupt/exception. */
836	IEMTASKSWITCH_INT_XCPT = 1,
837	/** Task switch caused by a far CALL. */
838	IEMTASKSWITCH_CALL,
839	/** Task switch caused by a far JMP. */
840	IEMTASKSWITCH_JUMP,
841	/** Task switch caused by an IRET. */
842	IEMTASKSWITCH_IRET
843	} IEMTASKSWITCH;
844	AssertCompileSize(IEMTASKSWITCH, 4);
845
846
847	/**
848	* Tests if verification mode is enabled.
849	*
850	* This expands to @c false when IEM_VERIFICATION_MODE is not defined and
851	* should therefore cause the compiler to eliminate the verification branch
852	* of an if statement. */
853	#ifdef IEM_VERIFICATION_MODE_FULL
854	# define IEM_VERIFICATION_ENABLED(a_pVCpu) (!(a_pVCpu)->iem.s.fNoRem)
855	#elif defined(IEM_VERIFICATION_MODE_MINIMAL)
856	# define IEM_VERIFICATION_ENABLED(a_pVCpu) (true)
857	#else
858	# define IEM_VERIFICATION_ENABLED(a_pVCpu) (false)
859	#endif
860
861	/**
862	* Tests if full verification mode is enabled.
863	*
864	* This expands to @c false when IEM_VERIFICATION_MODE_FULL is not defined and
865	* should therefore cause the compiler to eliminate the verification branch
866	* of an if statement. */
867	#ifdef IEM_VERIFICATION_MODE_FULL
868	# define IEM_FULL_VERIFICATION_ENABLED(a_pVCpu) (!(a_pVCpu)->iem.s.fNoRem)
869	#else
870	# define IEM_FULL_VERIFICATION_ENABLED(a_pVCpu) (false)
871	#endif
872
873	/**
874	* Tests if full verification mode is enabled again REM.
875	*
876	* This expands to @c false when IEM_VERIFICATION_MODE_FULL is not defined and
877	* should therefore cause the compiler to eliminate the verification branch
878	* of an if statement. */
879	#ifdef IEM_VERIFICATION_MODE_FULL
880	# ifdef IEM_VERIFICATION_MODE_FULL_HM
881	# define IEM_FULL_VERIFICATION_REM_ENABLED(a_pVCpu) (!(a_pVCpu)->iem.s.fNoRem && !HMIsEnabled((a_pVCpu)->CTX_SUFF(pVM)))
882	# else
883	# define IEM_FULL_VERIFICATION_REM_ENABLED(a_pVCpu) (!(a_pVCpu)->iem.s.fNoRem)
884	# endif
885	#else
886	# define IEM_FULL_VERIFICATION_REM_ENABLED(a_pVCpu) (false)
887	#endif
888
889	/** @def IEM_VERIFICATION_MODE
890	* Indicates that one of the verfication modes are enabled.
891	*/
892	#if (defined(IEM_VERIFICATION_MODE_FULL) \|\| defined(IEM_VERIFICATION_MODE_MINIMAL)) && !defined(IEM_VERIFICATION_MODE) \
893	\|\| defined(DOXYGEN_RUNNING)
894	# define IEM_VERIFICATION_MODE
895	#endif
896
897	/**
898	* Indicates to the verifier that the given flag set is undefined.
899	*
900	* Can be invoked again to add more flags.
901	*
902	* This is a NOOP if the verifier isn't compiled in.
903	*/
904	#ifdef IEM_VERIFICATION_MODE_FULL
905	# define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { pVCpu->iem.s.fUndefinedEFlags \|= (a_fEfl); } while (0)
906	#else
907	# define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
908	#endif
909
910
911	/** @def IEM_DECL_IMPL_TYPE
912	* For typedef'ing an instruction implementation function.
913	*
914	* @param a_RetType The return type.
915	* @param a_Name The name of the type.
916	* @param a_ArgList The argument list enclosed in parentheses.
917	*/
918
919	/** @def IEM_DECL_IMPL_DEF
920	* For defining an instruction implementation function.
921	*
922	* @param a_RetType The return type.
923	* @param a_Name The name of the type.
924	* @param a_ArgList The argument list enclosed in parentheses.
925	*/
926
927	#if defined(__GNUC__) && defined(RT_ARCH_X86)
928	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
929	__attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
930	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
931	__attribute__((__fastcall__, __nothrow__)) a_RetType a_Name a_ArgList
932
933	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
934	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
935	a_RetType (__fastcall a_Name) a_ArgList
936	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
937	a_RetType __fastcall a_Name a_ArgList
938
939	#else
940	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
941	a_RetType (VBOXCALL a_Name) a_ArgList
942	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
943	a_RetType VBOXCALL a_Name a_ArgList
944
945	#endif
946
947	/** @name Arithmetic assignment operations on bytes (binary).
948	* @{ */
949	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU8, (uint8_t pu8Dst, uint8_t u8Src, uint32_t pEFlags));
950	typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
951	FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
952	FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
953	FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
954	FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
955	FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
956	FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
957	FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
958	/** @} */
959
960	/** @name Arithmetic assignment operations on words (binary).
961	* @{ */
962	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU16, (uint16_t pu16Dst, uint16_t u16Src, uint32_t pEFlags));
963	typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
964	FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
965	FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
966	FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
967	FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
968	FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
969	FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
970	FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
971	/** @} */
972
973	/** @name Arithmetic assignment operations on double words (binary).
974	* @{ */
975	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU32, (uint32_t pu32Dst, uint32_t u32Src, uint32_t pEFlags));
976	typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
977	FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
978	FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
979	FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
980	FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
981	FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
982	FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
983	FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
984	/** @} */
985
986	/** @name Arithmetic assignment operations on quad words (binary).
987	* @{ */
988	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU64, (uint64_t pu64Dst, uint64_t u64Src, uint32_t pEFlags));
989	typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
990	FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
991	FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
992	FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
993	FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
994	FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
995	FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
996	FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
997	/** @} */
998
999	/** @name Compare operations (thrown in with the binary ops).
1000	* @{ */
1001	FNIEMAIMPLBINU8 iemAImpl_cmp_u8;
1002	FNIEMAIMPLBINU16 iemAImpl_cmp_u16;
1003	FNIEMAIMPLBINU32 iemAImpl_cmp_u32;
1004	FNIEMAIMPLBINU64 iemAImpl_cmp_u64;
1005	/** @} */
1006
1007	/** @name Test operations (thrown in with the binary ops).
1008	* @{ */
1009	FNIEMAIMPLBINU8 iemAImpl_test_u8;
1010	FNIEMAIMPLBINU16 iemAImpl_test_u16;
1011	FNIEMAIMPLBINU32 iemAImpl_test_u32;
1012	FNIEMAIMPLBINU64 iemAImpl_test_u64;
1013	/** @} */
1014
1015	/** @name Bit operations operations (thrown in with the binary ops).
1016	* @{ */
1017	FNIEMAIMPLBINU16 iemAImpl_bt_u16, iemAImpl_bt_u16_locked;
1018	FNIEMAIMPLBINU32 iemAImpl_bt_u32, iemAImpl_bt_u32_locked;
1019	FNIEMAIMPLBINU64 iemAImpl_bt_u64, iemAImpl_bt_u64_locked;
1020	FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
1021	FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
1022	FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
1023	FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
1024	FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
1025	FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
1026	FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
1027	FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
1028	FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
1029	/** @} */
1030
1031	/** @name Exchange memory with register operations.
1032	* @{ */
1033	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8, (uint8_t pu8Mem, uint8_t pu8Reg));
1034	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16,(uint16_t pu16Mem, uint16_t pu16Reg));
1035	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32,(uint32_t pu32Mem, uint32_t pu32Reg));
1036	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64,(uint64_t pu64Mem, uint64_t pu64Reg));
1037	/** @} */
1038
1039	/** @name Exchange and add operations.
1040	* @{ */
1041	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1042	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1043	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1044	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1045	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1046	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1047	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1048	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1049	/** @} */
1050
1051	/** @name Compare and exchange.
1052	* @{ */
1053	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1054	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1055	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1056	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1057	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1058	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1059	#ifdef RT_ARCH_X86
1060	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1061	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1062	#else
1063	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1064	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1065	#endif
1066	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1067	uint32_t *pEFlags));
1068	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1069	uint32_t *pEFlags));
1070	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U *pu128Dst, PRTUINT128U pu64RaxRdx, PRTUINT128U pu64RbxRcx,
1071	uint32_t *pEFlags));
1072	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U *pu128Dst, PRTUINT128U pu64RaxRdx, PRTUINT128U pu64RbxRcx,
1073	uint32_t *pEFlags));
1074	/** @} */
1075
1076	/** @name Memory ordering
1077	* @{ */
1078	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
1079	typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
1080	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
1081	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
1082	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
1083	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
1084	/** @} */
1085
1086	/** @name Double precision shifts
1087	* @{ */
1088	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t pEFlags));
1089	typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
1090	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t pEFlags));
1091	typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
1092	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t pEFlags));
1093	typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
1094	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16;
1095	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32;
1096	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64;
1097	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16;
1098	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32;
1099	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64;
1100	/** @} */
1101
1102
1103	/** @name Bit search operations (thrown in with the binary ops).
1104	* @{ */
1105	FNIEMAIMPLBINU16 iemAImpl_bsf_u16;
1106	FNIEMAIMPLBINU32 iemAImpl_bsf_u32;
1107	FNIEMAIMPLBINU64 iemAImpl_bsf_u64;
1108	FNIEMAIMPLBINU16 iemAImpl_bsr_u16;
1109	FNIEMAIMPLBINU32 iemAImpl_bsr_u32;
1110	FNIEMAIMPLBINU64 iemAImpl_bsr_u64;
1111	/** @} */
1112
1113	/** @name Signed multiplication operations (thrown in with the binary ops).
1114	* @{ */
1115	FNIEMAIMPLBINU16 iemAImpl_imul_two_u16;
1116	FNIEMAIMPLBINU32 iemAImpl_imul_two_u32;
1117	FNIEMAIMPLBINU64 iemAImpl_imul_two_u64;
1118	/** @} */
1119
1120	/** @name Arithmetic assignment operations on bytes (unary).
1121	* @{ */
1122	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t pu8Dst, uint32_t pEFlags));
1123	typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
1124	FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
1125	FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
1126	FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
1127	FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
1128	/** @} */
1129
1130	/** @name Arithmetic assignment operations on words (unary).
1131	* @{ */
1132	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t pu16Dst, uint32_t pEFlags));
1133	typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
1134	FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
1135	FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
1136	FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
1137	FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
1138	/** @} */
1139
1140	/** @name Arithmetic assignment operations on double words (unary).
1141	* @{ */
1142	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t pu32Dst, uint32_t pEFlags));
1143	typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
1144	FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
1145	FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
1146	FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
1147	FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
1148	/** @} */
1149
1150	/** @name Arithmetic assignment operations on quad words (unary).
1151	* @{ */
1152	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t pu64Dst, uint32_t pEFlags));
1153	typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
1154	FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
1155	FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
1156	FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
1157	FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
1158	/** @} */
1159
1160
1161	/** @name Shift operations on bytes (Group 2).
1162	* @{ */
1163	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU8,(uint8_t pu8Dst, uint8_t cShift, uint32_t pEFlags));
1164	typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
1165	FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8;
1166	FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8;
1167	FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8;
1168	FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8;
1169	FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8;
1170	FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8;
1171	FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8;
1172	/** @} */
1173
1174	/** @name Shift operations on words (Group 2).
1175	* @{ */
1176	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU16,(uint16_t pu16Dst, uint8_t cShift, uint32_t pEFlags));
1177	typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
1178	FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16;
1179	FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16;
1180	FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16;
1181	FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16;
1182	FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16;
1183	FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16;
1184	FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16;
1185	/** @} */
1186
1187	/** @name Shift operations on double words (Group 2).
1188	* @{ */
1189	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU32,(uint32_t pu32Dst, uint8_t cShift, uint32_t pEFlags));
1190	typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
1191	FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32;
1192	FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32;
1193	FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32;
1194	FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32;
1195	FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32;
1196	FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32;
1197	FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32;
1198	/** @} */
1199
1200	/** @name Shift operations on words (Group 2).
1201	* @{ */
1202	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU64,(uint64_t pu64Dst, uint8_t cShift, uint32_t pEFlags));
1203	typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
1204	FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64;
1205	FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64;
1206	FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64;
1207	FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64;
1208	FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64;
1209	FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64;
1210	FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64;
1211	/** @} */
1212
1213	/** @name Multiplication and division operations.
1214	* @{ */
1215	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t pu16AX, uint8_t u8FactorDivisor, uint32_t pEFlags));
1216	typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
1217	FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_imul_u8;
1218	FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_idiv_u8;
1219
1220	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t pu16AX, uint16_t pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
1221	typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
1222	FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_imul_u16;
1223	FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_idiv_u16;
1224
1225	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t pu32EAX, uint32_t pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
1226	typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
1227	FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_imul_u32;
1228	FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_idiv_u32;
1229
1230	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t pu64RAX, uint64_t pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
1231	typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
1232	FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_imul_u64;
1233	FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_idiv_u64;
1234	/** @} */
1235
1236	/** @name Byte Swap.
1237	* @{ */
1238	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t pu32Dst)); / Yes, 32-bit register access. */
1239	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
1240	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
1241	/** @} */
1242
1243	/** @name Misc.
1244	* @{ */
1245	FNIEMAIMPLBINU16 iemAImpl_arpl;
1246	/** @} */
1247
1248
1249	/** @name FPU operations taking a 32-bit float argument
1250	* @{ */
1251	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1252	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1253	typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
1254
1255	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1256	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1257	typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
1258
1259	FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
1260	FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
1261	FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
1262	FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
1263	FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
1264	FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
1265	FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
1266
1267	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r32_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
1268	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1269	PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
1270	/** @} */
1271
1272	/** @name FPU operations taking a 64-bit float argument
1273	* @{ */
1274	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1275	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1276	typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
1277
1278	FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
1279	FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
1280	FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
1281	FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
1282	FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
1283	FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
1284
1285	IEM_DECL_IMPL_DEF(void, iemAImpl_fcom_r80_by_r64,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1286	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1287	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r64_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
1288	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1289	PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
1290	/** @} */
1291
1292	/** @name FPU operations taking a 80-bit float argument
1293	* @{ */
1294	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1295	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1296	typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
1297	FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
1298	FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
1299	FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
1300	FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
1301	FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
1302	FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
1303	FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
1304	FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
1305	FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
1306
1307	FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80;
1308	FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80;
1309
1310	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1311	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1312	typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
1313	FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
1314	FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
1315
1316	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1317	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1318	typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
1319	FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
1320	FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
1321
1322	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
1323	typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
1324	FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
1325	FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
1326	FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80;
1327	FNIEMAIMPLFPUR80UNARY iemAImpl_fyl2x_r80;
1328	FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
1329	FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
1330	FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80;
1331	FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80;
1332
1333	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
1334	typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
1335	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
1336	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
1337
1338	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
1339	typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
1340	FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
1341	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
1342	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
1343	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
1344	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
1345	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
1346	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
1347
1348	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
1349	PCRTFLOAT80U pr80Val));
1350	typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
1351	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80;
1352	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
1353	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80;
1354
1355	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
1356	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1357	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
1358
1359	/** @} */
1360
1361	/** @name FPU operations taking a 16-bit signed integer argument
1362	* @{ */
1363	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1364	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
1365	typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
1366
1367	FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
1368	FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
1369	FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
1370	FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
1371	FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
1372	FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
1373
1374	IEM_DECL_IMPL_DEF(void, iemAImpl_ficom_r80_by_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1375	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
1376
1377	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i16_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
1378	IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1379	int16_t *pi16Val, PCRTFLOAT80U pr80Val));
1380	IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1381	int16_t *pi16Val, PCRTFLOAT80U pr80Val));
1382	/** @} */
1383
1384	/** @name FPU operations taking a 32-bit signed integer argument
1385	* @{ */
1386	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1387	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
1388	typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
1389
1390	FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
1391	FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
1392	FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
1393	FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
1394	FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
1395	FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
1396
1397	IEM_DECL_IMPL_DEF(void, iemAImpl_ficom_r80_by_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1398	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
1399
1400	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i32_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
1401	IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1402	int32_t *pi32Val, PCRTFLOAT80U pr80Val));
1403	IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1404	int32_t *pi32Val, PCRTFLOAT80U pr80Val));
1405	/** @} */
1406
1407	/** @name FPU operations taking a 64-bit signed integer argument
1408	* @{ */
1409	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1410	PCRTFLOAT80U pr80Val1, int64_t const *pi64Val2));
1411	typedef FNIEMAIMPLFPUI64 *PFNIEMAIMPLFPUI64;
1412
1413	FNIEMAIMPLFPUI64 iemAImpl_fiadd_r80_by_i64;
1414	FNIEMAIMPLFPUI64 iemAImpl_fimul_r80_by_i64;
1415	FNIEMAIMPLFPUI64 iemAImpl_fisub_r80_by_i64;
1416	FNIEMAIMPLFPUI64 iemAImpl_fisubr_r80_by_i64;
1417	FNIEMAIMPLFPUI64 iemAImpl_fidiv_r80_by_i64;
1418	FNIEMAIMPLFPUI64 iemAImpl_fidivr_r80_by_i64;
1419
1420	IEM_DECL_IMPL_DEF(void, iemAImpl_ficom_r80_by_i64,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1421	PCRTFLOAT80U pr80Val1, int64_t const *pi64Val2));
1422
1423	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i64_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
1424	IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1425	int64_t *pi64Val, PCRTFLOAT80U pr80Val));
1426	IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1427	int64_t *pi32Val, PCRTFLOAT80U pr80Val));
1428	/** @} */
1429
1430
1431	/** Temporary type representing a 256-bit vector register. */
1432	typedef struct {uint64_t au64[4]; } IEMVMM256;
1433	/** Temporary type pointing to a 256-bit vector register. */
1434	typedef IEMVMM256 *PIEMVMM256;
1435	/** Temporary type pointing to a const 256-bit vector register. */
1436	typedef IEMVMM256 *PCIEMVMM256;
1437
1438
1439	/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
1440	* @{ */
1441	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src));
1442	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
1443	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U128,(PCX86FXSTATE pFpuState, uint128_t pu128Dst, uint128_t const pu128Src));
1444	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
1445	FNIEMAIMPLMEDIAF2U64 iemAImpl_pxor_u64, iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
1446	FNIEMAIMPLMEDIAF2U128 iemAImpl_pxor_u128, iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
1447	/** @} */
1448
1449	/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
1450	* @{ */
1451	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1L1U64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint32_t const pu32Src));
1452	typedef FNIEMAIMPLMEDIAF1L1U64 *PFNIEMAIMPLMEDIAF1L1U64;
1453	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1L1U128,(PCX86FXSTATE pFpuState, uint128_t pu128Dst, uint64_t const pu64Src));
1454	typedef FNIEMAIMPLMEDIAF1L1U128 *PFNIEMAIMPLMEDIAF1L1U128;
1455	FNIEMAIMPLMEDIAF1L1U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
1456	FNIEMAIMPLMEDIAF1L1U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
1457	/** @} */
1458
1459	/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
1460	* @{ */
1461	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1H1U64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src));
1462	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF1H1U64;
1463	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1H1U128,(PCX86FXSTATE pFpuState, uint128_t pu128Dst, uint128_t const pu128Src));
1464	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF1H1U128;
1465	FNIEMAIMPLMEDIAF1H1U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
1466	FNIEMAIMPLMEDIAF1H1U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
1467	/** @} */
1468
1469	/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
1470	* @{ */
1471	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUF,(PCX86FXSTATE pFpuState, uint128_t *pu128Dst,
1472	uint128_t const *pu128Src, uint8_t bEvil));
1473	typedef FNIEMAIMPLMEDIAPSHUF *PFNIEMAIMPLMEDIAPSHUF;
1474	FNIEMAIMPLMEDIAPSHUF iemAImpl_pshufhw, iemAImpl_pshuflw, iemAImpl_pshufd;
1475	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src, uint8_t bEvil));
1476	/** @} */
1477
1478	/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
1479	* @{ */
1480	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src));
1481	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint128_t const pu128Src));
1482	/** @} */
1483
1484
1485
1486	/** @name Function tables.
1487	* @{
1488	*/
1489
1490	/**
1491	* Function table for a binary operator providing implementation based on
1492	* operand size.
1493	*/
1494	typedef struct IEMOPBINSIZES
1495	{
1496	PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
1497	PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
1498	PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
1499	PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
1500	} IEMOPBINSIZES;
1501	/** Pointer to a binary operator function table. */
1502	typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
1503
1504
1505	/**
1506	* Function table for a unary operator providing implementation based on
1507	* operand size.
1508	*/
1509	typedef struct IEMOPUNARYSIZES
1510	{
1511	PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
1512	PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
1513	PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
1514	PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
1515	} IEMOPUNARYSIZES;
1516	/** Pointer to a unary operator function table. */
1517	typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
1518
1519
1520	/**
1521	* Function table for a shift operator providing implementation based on
1522	* operand size.
1523	*/
1524	typedef struct IEMOPSHIFTSIZES
1525	{
1526	PFNIEMAIMPLSHIFTU8 pfnNormalU8;
1527	PFNIEMAIMPLSHIFTU16 pfnNormalU16;
1528	PFNIEMAIMPLSHIFTU32 pfnNormalU32;
1529	PFNIEMAIMPLSHIFTU64 pfnNormalU64;
1530	} IEMOPSHIFTSIZES;
1531	/** Pointer to a shift operator function table. */
1532	typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
1533
1534
1535	/**
1536	* Function table for a multiplication or division operation.
1537	*/
1538	typedef struct IEMOPMULDIVSIZES
1539	{
1540	PFNIEMAIMPLMULDIVU8 pfnU8;
1541	PFNIEMAIMPLMULDIVU16 pfnU16;
1542	PFNIEMAIMPLMULDIVU32 pfnU32;
1543	PFNIEMAIMPLMULDIVU64 pfnU64;
1544	} IEMOPMULDIVSIZES;
1545	/** Pointer to a multiplication or division operation function table. */
1546	typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
1547
1548
1549	/**
1550	* Function table for a double precision shift operator providing implementation
1551	* based on operand size.
1552	*/
1553	typedef struct IEMOPSHIFTDBLSIZES
1554	{
1555	PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
1556	PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
1557	PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
1558	} IEMOPSHIFTDBLSIZES;
1559	/** Pointer to a double precision shift function table. */
1560	typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
1561
1562
1563	/**
1564	* Function table for media instruction taking two full sized media registers,
1565	* optionally the 2nd being a memory reference (only modifying the first op.)
1566	*/
1567	typedef struct IEMOPMEDIAF2
1568	{
1569	PFNIEMAIMPLMEDIAF2U64 pfnU64;
1570	PFNIEMAIMPLMEDIAF2U128 pfnU128;
1571	} IEMOPMEDIAF2;
1572	/** Pointer to a media operation function table for full sized ops. */
1573	typedef IEMOPMEDIAF2 const *PCIEMOPMEDIAF2;
1574
1575	/**
1576	* Function table for media instruction taking taking one full and one lower
1577	* half media register.
1578	*/
1579	typedef struct IEMOPMEDIAF1L1
1580	{
1581	PFNIEMAIMPLMEDIAF1L1U64 pfnU64;
1582	PFNIEMAIMPLMEDIAF1L1U128 pfnU128;
1583	} IEMOPMEDIAF1L1;
1584	/** Pointer to a media operation function table for lowhalf+lowhalf -> full. */
1585	typedef IEMOPMEDIAF1L1 const *PCIEMOPMEDIAF1L1;
1586
1587	/**
1588	* Function table for media instruction taking taking one full and one high half
1589	* media register.
1590	*/
1591	typedef struct IEMOPMEDIAF1H1
1592	{
1593	PFNIEMAIMPLMEDIAF1H1U64 pfnU64;
1594	PFNIEMAIMPLMEDIAF1H1U128 pfnU128;
1595	} IEMOPMEDIAF1H1;
1596	/** Pointer to a media operation function table for hihalf+hihalf -> full. */
1597	typedef IEMOPMEDIAF1H1 const *PCIEMOPMEDIAF1H1;
1598
1599
1600	/** @} */
1601
1602
1603	/** @name C instruction implementations for anything slightly complicated.
1604	* @{ */
1605
1606	/**
1607	* For typedef'ing or declaring a C instruction implementation function taking
1608	* no extra arguments.
1609	*
1610	* @param a_Name The name of the type.
1611	*/
1612	# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
1613	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr))
1614	/**
1615	* For defining a C instruction implementation function taking no extra
1616	* arguments.
1617	*
1618	* @param a_Name The name of the function
1619	*/
1620	# define IEM_CIMPL_DEF_0(a_Name) \
1621	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr))
1622	/**
1623	* For calling a C instruction implementation function taking no extra
1624	* arguments.
1625	*
1626	* This special call macro adds default arguments to the call and allow us to
1627	* change these later.
1628	*
1629	* @param a_fn The name of the function.
1630	*/
1631	# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
1632
1633	/**
1634	* For typedef'ing or declaring a C instruction implementation function taking
1635	* one extra argument.
1636	*
1637	* @param a_Name The name of the type.
1638	* @param a_Type0 The argument type.
1639	* @param a_Arg0 The argument name.
1640	*/
1641	# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
1642	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
1643	/**
1644	* For defining a C instruction implementation function taking one extra
1645	* argument.
1646	*
1647	* @param a_Name The name of the function
1648	* @param a_Type0 The argument type.
1649	* @param a_Arg0 The argument name.
1650	*/
1651	# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
1652	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
1653	/**
1654	* For calling a C instruction implementation function taking one extra
1655	* argument.
1656	*
1657	* This special call macro adds default arguments to the call and allow us to
1658	* change these later.
1659	*
1660	* @param a_fn The name of the function.
1661	* @param a0 The name of the 1st argument.
1662	*/
1663	# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
1664
1665	/**
1666	* For typedef'ing or declaring a C instruction implementation function taking
1667	* two extra arguments.
1668	*
1669	* @param a_Name The name of the type.
1670	* @param a_Type0 The type of the 1st argument
1671	* @param a_Arg0 The name of the 1st argument.
1672	* @param a_Type1 The type of the 2nd argument.
1673	* @param a_Arg1 The name of the 2nd argument.
1674	*/
1675	# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
1676	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
1677	/**
1678	* For defining a C instruction implementation function taking two extra
1679	* arguments.
1680	*
1681	* @param a_Name The name of the function.
1682	* @param a_Type0 The type of the 1st argument
1683	* @param a_Arg0 The name of the 1st argument.
1684	* @param a_Type1 The type of the 2nd argument.
1685	* @param a_Arg1 The name of the 2nd argument.
1686	*/
1687	# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
1688	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
1689	/**
1690	* For calling a C instruction implementation function taking two extra
1691	* arguments.
1692	*
1693	* This special call macro adds default arguments to the call and allow us to
1694	* change these later.
1695	*
1696	* @param a_fn The name of the function.
1697	* @param a0 The name of the 1st argument.
1698	* @param a1 The name of the 2nd argument.
1699	*/
1700	# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
1701
1702	/**
1703	* For typedef'ing or declaring a C instruction implementation function taking
1704	* three extra arguments.
1705	*
1706	* @param a_Name The name of the type.
1707	* @param a_Type0 The type of the 1st argument
1708	* @param a_Arg0 The name of the 1st argument.
1709	* @param a_Type1 The type of the 2nd argument.
1710	* @param a_Arg1 The name of the 2nd argument.
1711	* @param a_Type2 The type of the 3rd argument.
1712	* @param a_Arg2 The name of the 3rd argument.
1713	*/
1714	# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
1715	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
1716	/**
1717	* For defining a C instruction implementation function taking three extra
1718	* arguments.
1719	*
1720	* @param a_Name The name of the function.
1721	* @param a_Type0 The type of the 1st argument
1722	* @param a_Arg0 The name of the 1st argument.
1723	* @param a_Type1 The type of the 2nd argument.
1724	* @param a_Arg1 The name of the 2nd argument.
1725	* @param a_Type2 The type of the 3rd argument.
1726	* @param a_Arg2 The name of the 3rd argument.
1727	*/
1728	# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
1729	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
1730	/**
1731	* For calling a C instruction implementation function taking three extra
1732	* arguments.
1733	*
1734	* This special call macro adds default arguments to the call and allow us to
1735	* change these later.
1736	*
1737	* @param a_fn The name of the function.
1738	* @param a0 The name of the 1st argument.
1739	* @param a1 The name of the 2nd argument.
1740	* @param a2 The name of the 3rd argument.
1741	*/
1742	# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
1743
1744
1745	/**
1746	* For typedef'ing or declaring a C instruction implementation function taking
1747	* four extra arguments.
1748	*
1749	* @param a_Name The name of the type.
1750	* @param a_Type0 The type of the 1st argument
1751	* @param a_Arg0 The name of the 1st argument.
1752	* @param a_Type1 The type of the 2nd argument.
1753	* @param a_Arg1 The name of the 2nd argument.
1754	* @param a_Type2 The type of the 3rd argument.
1755	* @param a_Arg2 The name of the 3rd argument.
1756	* @param a_Type3 The type of the 4th argument.
1757	* @param a_Arg3 The name of the 4th argument.
1758	*/
1759	# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
1760	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
1761	/**
1762	* For defining a C instruction implementation function taking four extra
1763	* arguments.
1764	*
1765	* @param a_Name The name of the function.
1766	* @param a_Type0 The type of the 1st argument
1767	* @param a_Arg0 The name of the 1st argument.
1768	* @param a_Type1 The type of the 2nd argument.
1769	* @param a_Arg1 The name of the 2nd argument.
1770	* @param a_Type2 The type of the 3rd argument.
1771	* @param a_Arg2 The name of the 3rd argument.
1772	* @param a_Type3 The type of the 4th argument.
1773	* @param a_Arg3 The name of the 4th argument.
1774	*/
1775	# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
1776	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
1777	a_Type2 a_Arg2, a_Type3 a_Arg3))
1778	/**
1779	* For calling a C instruction implementation function taking four extra
1780	* arguments.
1781	*
1782	* This special call macro adds default arguments to the call and allow us to
1783	* change these later.
1784	*
1785	* @param a_fn The name of the function.
1786	* @param a0 The name of the 1st argument.
1787	* @param a1 The name of the 2nd argument.
1788	* @param a2 The name of the 3rd argument.
1789	* @param a3 The name of the 4th argument.
1790	*/
1791	# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
1792
1793
1794	/**
1795	* For typedef'ing or declaring a C instruction implementation function taking
1796	* five extra arguments.
1797	*
1798	* @param a_Name The name of the type.
1799	* @param a_Type0 The type of the 1st argument
1800	* @param a_Arg0 The name of the 1st argument.
1801	* @param a_Type1 The type of the 2nd argument.
1802	* @param a_Arg1 The name of the 2nd argument.
1803	* @param a_Type2 The type of the 3rd argument.
1804	* @param a_Arg2 The name of the 3rd argument.
1805	* @param a_Type3 The type of the 4th argument.
1806	* @param a_Arg3 The name of the 4th argument.
1807	* @param a_Type4 The type of the 5th argument.
1808	* @param a_Arg4 The name of the 5th argument.
1809	*/
1810	# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
1811	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, \
1812	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
1813	a_Type3 a_Arg3, a_Type4 a_Arg4))
1814	/**
1815	* For defining a C instruction implementation function taking five extra
1816	* arguments.
1817	*
1818	* @param a_Name The name of the function.
1819	* @param a_Type0 The type of the 1st argument
1820	* @param a_Arg0 The name of the 1st argument.
1821	* @param a_Type1 The type of the 2nd argument.
1822	* @param a_Arg1 The name of the 2nd argument.
1823	* @param a_Type2 The type of the 3rd argument.
1824	* @param a_Arg2 The name of the 3rd argument.
1825	* @param a_Type3 The type of the 4th argument.
1826	* @param a_Arg3 The name of the 4th argument.
1827	* @param a_Type4 The type of the 5th argument.
1828	* @param a_Arg4 The name of the 5th argument.
1829	*/
1830	# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
1831	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, \
1832	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
1833	a_Type3 a_Arg3, a_Type4 a_Arg4))
1834	/**
1835	* For calling a C instruction implementation function taking five extra
1836	* arguments.
1837	*
1838	* This special call macro adds default arguments to the call and allow us to
1839	* change these later.
1840	*
1841	* @param a_fn The name of the function.
1842	* @param a0 The name of the 1st argument.
1843	* @param a1 The name of the 2nd argument.
1844	* @param a2 The name of the 3rd argument.
1845	* @param a3 The name of the 4th argument.
1846	* @param a4 The name of the 5th argument.
1847	*/
1848	# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
1849
1850	/** @} */
1851
1852
1853	/** @} */
1854
1855	RT_C_DECLS_END
1856
1857	#endif
1858

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source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h@ 62250

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