IEMInternal.h@ 96821

Last change on this file since 96821 was 96811, checked in by vboxsync, 2 years ago
VMM,IPRT,VBoxGuest,SUPDrv: Added a more efficient interface for guest logging using the CPUID instruction. This is mainly intended for development use and not enabled by default. Require updating host drivers.
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1	/* $Id: IEMInternal.h 96811 2022-09-21 13:23:31Z vboxsync $ */
2	/** @file
3	* IEM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2011-2022 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_IEMInternal_h
29	#define VMM_INCLUDED_SRC_include_IEMInternal_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#include <VBox/vmm/cpum.h>
35	#include <VBox/vmm/iem.h>
36	#include <VBox/vmm/pgm.h>
37	#include <VBox/vmm/stam.h>
38	#include <VBox/param.h>
39
40	#include <iprt/setjmp-without-sigmask.h>
41
42
43	RT_C_DECLS_BEGIN
44
45
46	/** @defgroup grp_iem_int Internals
47	* @ingroup grp_iem
48	* @internal
49	* @{
50	*/
51
52	/** For expanding symbol in slickedit and other products tagging and
53	* crossreferencing IEM symbols. */
54	#ifndef IEM_STATIC
55	# define IEM_STATIC static
56	#endif
57
58	/** @def IEM_WITH_SETJMP
59	* Enables alternative status code handling using setjmps.
60	*
61	* This adds a bit of expense via the setjmp() call since it saves all the
62	* non-volatile registers. However, it eliminates return code checks and allows
63	* for more optimal return value passing (return regs instead of stack buffer).
64	*/
65	#if defined(DOXYGEN_RUNNING) \|\| defined(RT_OS_WINDOWS) \|\| 1
66	# define IEM_WITH_SETJMP
67	#endif
68
69	#define IEM_IMPLEMENTS_TASKSWITCH
70
71	/** @def IEM_WITH_3DNOW
72	* Includes the 3DNow decoding. */
73	#define IEM_WITH_3DNOW
74
75	/** @def IEM_WITH_THREE_0F_38
76	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
77	#define IEM_WITH_THREE_0F_38
78
79	/** @def IEM_WITH_THREE_0F_3A
80	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
81	#define IEM_WITH_THREE_0F_3A
82
83	/** @def IEM_WITH_VEX
84	* Includes the VEX decoding. */
85	#define IEM_WITH_VEX
86
87	/** @def IEM_CFG_TARGET_CPU
88	* The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
89	*
90	* By default we allow this to be configured by the user via the
91	* CPUM/GuestCpuName config string, but this comes at a slight cost during
92	* decoding. So, for applications of this code where there is no need to
93	* be dynamic wrt target CPU, just modify this define.
94	*/
95	#if !defined(IEM_CFG_TARGET_CPU) \|\| defined(DOXYGEN_RUNNING)
96	# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
97	#endif
98
99	//#define IEM_WITH_CODE_TLB // - work in progress
100	//#define IEM_WITH_DATA_TLB // - work in progress
101
102
103	/** @def IEM_USE_UNALIGNED_DATA_ACCESS
104	* Use unaligned accesses instead of elaborate byte assembly. */
105	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86) \|\| defined(DOXYGEN_RUNNING)
106	# define IEM_USE_UNALIGNED_DATA_ACCESS
107	#endif
108
109	//#define IEM_LOG_MEMORY_WRITES
110
111	#if !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
112	/** Instruction statistics. */
113	typedef struct IEMINSTRSTATS
114	{
115	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
116	# include "IEMInstructionStatisticsTmpl.h"
117	# undef IEM_DO_INSTR_STAT
118	} IEMINSTRSTATS;
119	#else
120	struct IEMINSTRSTATS;
121	typedef struct IEMINSTRSTATS IEMINSTRSTATS;
122	#endif
123	/** Pointer to IEM instruction statistics. */
124	typedef IEMINSTRSTATS *PIEMINSTRSTATS;
125
126
127	/** @name IEMTARGETCPU_EFL_BEHAVIOR_XXX - IEMCPU::aidxTargetCpuEflFlavour
128	* @{ */
129	#define IEMTARGETCPU_EFL_BEHAVIOR_NATIVE 0 /*< Native x86 EFLAGS result; Intel EFLAGS when on non-x86 hosts. /
130	#define IEMTARGETCPU_EFL_BEHAVIOR_INTEL 1 /*< Intel EFLAGS result. /
131	#define IEMTARGETCPU_EFL_BEHAVIOR_AMD 2 /*< AMD EFLAGS result /
132	#define IEMTARGETCPU_EFL_BEHAVIOR_RESERVED 3 /*< Reserved/dummy entry slot that's the same as 0. /
133	#define IEMTARGETCPU_EFL_BEHAVIOR_MASK 3 /*< For masking the index before use. /
134	/** Selects the right variant from a_aArray.
135	* pVCpu is implicit in the caller context. */
136	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT(a_aArray) \
137	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[1] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
138	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for when no native worker can
139	* be used because the host CPU does not support the operation. */
140	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_NON_NATIVE(a_aArray) \
141	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
142	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for a two dimentional
143	* array paralleling IEMCPU::aidxTargetCpuEflFlavour and a single bit index
144	* into the two.
145	* @sa IEM_SELECT_NATIVE_OR_FALLBACK */
146	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
147	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
148	(a_aaArray[a_fNative][pVCpu->iem.s.aidxTargetCpuEflFlavour[a_fNative] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
149	#else
150	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
151	(a_aaArray[0][pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
152	#endif
153	/** @} */
154
155	/**
156	* Picks @a a_pfnNative or @a a_pfnFallback according to the host CPU feature
157	* indicator given by @a a_fCpumFeatureMember (CPUMFEATURES member).
158	*
159	* On non-x86 hosts, this will shortcut to the fallback w/o checking the
160	* indicator.
161	*
162	* @sa IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX
163	*/
164	#if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
165	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) \
166	(g_CpumHostFeatures.s.a_fCpumFeatureMember ? a_pfnNative : a_pfnFallback)
167	#else
168	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) (a_pfnFallback)
169	#endif
170
171
172	/**
173	* Extended operand mode that includes a representation of 8-bit.
174	*
175	* This is used for packing down modes when invoking some C instruction
176	* implementations.
177	*/
178	typedef enum IEMMODEX
179	{
180	IEMMODEX_16BIT = IEMMODE_16BIT,
181	IEMMODEX_32BIT = IEMMODE_32BIT,
182	IEMMODEX_64BIT = IEMMODE_64BIT,
183	IEMMODEX_8BIT
184	} IEMMODEX;
185	AssertCompileSize(IEMMODEX, 4);
186
187
188	/**
189	* Branch types.
190	*/
191	typedef enum IEMBRANCH
192	{
193	IEMBRANCH_JUMP = 1,
194	IEMBRANCH_CALL,
195	IEMBRANCH_TRAP,
196	IEMBRANCH_SOFTWARE_INT,
197	IEMBRANCH_HARDWARE_INT
198	} IEMBRANCH;
199	AssertCompileSize(IEMBRANCH, 4);
200
201
202	/**
203	* INT instruction types.
204	*/
205	typedef enum IEMINT
206	{
207	/** INT n instruction (opcode 0xcd imm). */
208	IEMINT_INTN = 0,
209	/** Single byte INT3 instruction (opcode 0xcc). */
210	IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
211	/** Single byte INTO instruction (opcode 0xce). */
212	IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
213	/** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
214	IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
215	} IEMINT;
216	AssertCompileSize(IEMINT, 4);
217
218
219	/**
220	* A FPU result.
221	*/
222	typedef struct IEMFPURESULT
223	{
224	/** The output value. */
225	RTFLOAT80U r80Result;
226	/** The output status. */
227	uint16_t FSW;
228	} IEMFPURESULT;
229	AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
230	/** Pointer to a FPU result. */
231	typedef IEMFPURESULT *PIEMFPURESULT;
232	/** Pointer to a const FPU result. */
233	typedef IEMFPURESULT const *PCIEMFPURESULT;
234
235
236	/**
237	* A FPU result consisting of two output values and FSW.
238	*/
239	typedef struct IEMFPURESULTTWO
240	{
241	/** The first output value. */
242	RTFLOAT80U r80Result1;
243	/** The output status. */
244	uint16_t FSW;
245	/** The second output value. */
246	RTFLOAT80U r80Result2;
247	} IEMFPURESULTTWO;
248	AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
249	AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
250	/** Pointer to a FPU result consisting of two output values and FSW. */
251	typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
252	/** Pointer to a const FPU result consisting of two output values and FSW. */
253	typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
254
255
256	/**
257	* IEM TLB entry.
258	*
259	* Lookup assembly:
260	* @code{.asm}
261	; Calculate tag.
262	mov rax, [VA]
263	shl rax, 16
264	shr rax, 16 + X86_PAGE_SHIFT
265	or rax, [uTlbRevision]
266
267	; Do indexing.
268	movzx ecx, al
269	lea rcx, [pTlbEntries + rcx]
270
271	; Check tag.
272	cmp [rcx + IEMTLBENTRY.uTag], rax
273	jne .TlbMiss
274
275	; Check access.
276	mov rax, ACCESS_FLAGS \| MAPPING_R3_NOT_VALID \| 0xffffff00
277	and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
278	cmp rax, [uTlbPhysRev]
279	jne .TlbMiss
280
281	; Calc address and we're done.
282	mov eax, X86_PAGE_OFFSET_MASK
283	and eax, [VA]
284	or rax, [rcx + IEMTLBENTRY.pMappingR3]
285	%ifdef VBOX_WITH_STATISTICS
286	inc qword [cTlbHits]
287	%endif
288	jmp .Done
289
290	.TlbMiss:
291	mov r8d, ACCESS_FLAGS
292	mov rdx, [VA]
293	mov rcx, [pVCpu]
294	call iemTlbTypeMiss
295	.Done:
296
297	@endcode
298	*
299	*/
300	typedef struct IEMTLBENTRY
301	{
302	/** The TLB entry tag.
303	* Bits 35 thru 0 are made up of the virtual address shifted right 12 bits, this
304	* is ASSUMING a virtual address width of 48 bits.
305	*
306	* Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
307	*
308	* The TLB lookup code uses the current TLB revision, which won't ever be zero,
309	* enabling an extremely cheap TLB invalidation most of the time. When the TLB
310	* revision wraps around though, the tags needs to be zeroed.
311	*
312	* @note Try use SHRD instruction? After seeing
313	* https://gmplib.org/~tege/x86-timing.pdf, maybe not.
314	*
315	* @todo This will need to be reorganized for 57-bit wide virtual address and
316	* PCID (currently 12 bits) and ASID (currently 6 bits) support. We'll
317	* have to move the TLB entry versioning entirely to the
318	* fFlagsAndPhysRev member then, 57 bit wide VAs means we'll only have
319	* 19 bits left (64 - 57 + 12 = 19) and they'll almost entire be
320	* consumed by PCID and ASID (12 + 6 = 18).
321	*/
322	uint64_t uTag;
323	/** Access flags and physical TLB revision.
324	*
325	* - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
326	* - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
327	* - Bit 2 - page tables - not user (complemented X86_PTE_US).
328	* - Bit 3 - pgm phys/virt - not directly writable.
329	* - Bit 4 - pgm phys page - not directly readable.
330	* - Bit 5 - page tables - not accessed (complemented X86_PTE_A).
331	* - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
332	* - Bit 7 - tlb entry - pMappingR3 member not valid.
333	* - Bits 63 thru 8 are used for the physical TLB revision number.
334	*
335	* We're using complemented bit meanings here because it makes it easy to check
336	* whether special action is required. For instance a user mode write access
337	* would do a "TEST fFlags, (X86_PTE_RW \| X86_PTE_US \| X86_PTE_D)" and a
338	* non-zero result would mean special handling needed because either it wasn't
339	* writable, or it wasn't user, or the page wasn't dirty. A user mode read
340	* access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
341	* need to check any PTE flag.
342	*/
343	uint64_t fFlagsAndPhysRev;
344	/** The guest physical page address. */
345	uint64_t GCPhys;
346	/** Pointer to the ring-3 mapping. */
347	R3PTRTYPE(uint8_t *) pbMappingR3;
348	#if HC_ARCH_BITS == 32
349	uint32_t u32Padding1;
350	#endif
351	} IEMTLBENTRY;
352	AssertCompileSize(IEMTLBENTRY, 32);
353	/** Pointer to an IEM TLB entry. */
354	typedef IEMTLBENTRY *PIEMTLBENTRY;
355
356	/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
357	* @{ */
358	#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /*< Page tables: Not executable. /
359	#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /*< Page tables: Not writable. /
360	#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /*< Page tables: Not user accessible (supervisor only). /
361	#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /*< Phys page: Not writable (access handler, ROM, whatever). /
362	#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /*< Phys page: Not readable (MMIO / access handler, ROM) /
363	#define IEMTLBE_F_PT_NO_ACCESSED RT_BIT_64(5) /*< Phys tables: Not accessed (need to be marked accessed). /
364	#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /*< Page tables: Not dirty (needs to be made dirty on write). /
365	#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(7) /*< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. /
366	#define IEMTLBE_F_PG_UNASSIGNED RT_BIT_64(8) /*< Phys page: Unassigned memory (not RAM, ROM, MMIO2 or MMIO). /
367	#define IEMTLBE_F_PHYS_REV UINT64_C(0xfffffffffffffe00) /*< Physical revision mask. @sa IEMTLB_PHYS_REV_INCR /
368	/** @} */
369
370
371	/**
372	* An IEM TLB.
373	*
374	* We've got two of these, one for data and one for instructions.
375	*/
376	typedef struct IEMTLB
377	{
378	/** The TLB entries.
379	* We've choosen 256 because that way we can obtain the result directly from a
380	* 8-bit register without an additional AND instruction. */
381	IEMTLBENTRY aEntries[256];
382	/** The TLB revision.
383	* This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
384	* by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
385	* the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
386	* (The revision zero indicates an invalid TLB entry.)
387	*
388	* The initial value is choosen to cause an early wraparound. */
389	uint64_t uTlbRevision;
390	/** The TLB physical address revision - shadow of PGM variable.
391	*
392	* This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
393	* incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
394	* a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
395	* as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
396	*
397	* The initial value is choosen to cause an early wraparound. */
398	uint64_t volatile uTlbPhysRev;
399
400	/* Statistics: */
401
402	/** TLB hits (VBOX_WITH_STATISTICS only). */
403	uint64_t cTlbHits;
404	/** TLB misses. */
405	uint32_t cTlbMisses;
406	/** Slow read path. */
407	uint32_t cTlbSlowReadPath;
408	#if 0
409	/** TLB misses because of tag mismatch. */
410	uint32_t cTlbMissesTag;
411	/** TLB misses because of virtual access violation. */
412	uint32_t cTlbMissesVirtAccess;
413	/** TLB misses because of dirty bit. */
414	uint32_t cTlbMissesDirty;
415	/** TLB misses because of MMIO */
416	uint32_t cTlbMissesMmio;
417	/** TLB misses because of write access handlers. */
418	uint32_t cTlbMissesWriteHandler;
419	/** TLB misses because no r3(/r0) mapping. */
420	uint32_t cTlbMissesMapping;
421	#endif
422	/** Alignment padding. */
423	uint32_t au32Padding[3+5];
424	} IEMTLB;
425	AssertCompileSizeAlignment(IEMTLB, 64);
426	/** IEMTLB::uTlbRevision increment. */
427	#define IEMTLB_REVISION_INCR RT_BIT_64(36)
428	/** IEMTLB::uTlbRevision mask. */
429	#define IEMTLB_REVISION_MASK (~(RT_BIT_64(36) - 1))
430	/** IEMTLB::uTlbPhysRev increment.
431	* @sa IEMTLBE_F_PHYS_REV */
432	#define IEMTLB_PHYS_REV_INCR RT_BIT_64(9)
433	/**
434	* Calculates the TLB tag for a virtual address.
435	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
436	* @param a_pTlb The TLB.
437	* @param a_GCPtr The virtual address.
438	*/
439	#define IEMTLB_CALC_TAG(a_pTlb, a_GCPtr) ( IEMTLB_CALC_TAG_NO_REV(a_GCPtr) \| (a_pTlb)->uTlbRevision )
440	/**
441	* Calculates the TLB tag for a virtual address but without TLB revision.
442	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
443	* @param a_GCPtr The virtual address.
444	*/
445	#define IEMTLB_CALC_TAG_NO_REV(a_GCPtr) ( (((a_GCPtr) << 16) >> (GUEST_PAGE_SHIFT + 16)) )
446	/**
447	* Converts a TLB tag value into a TLB index.
448	* @returns Index into IEMTLB::aEntries.
449	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
450	*/
451	#define IEMTLB_TAG_TO_INDEX(a_uTag) ( (uint8_t)(a_uTag) )
452	/**
453	* Converts a TLB tag value into a TLB index.
454	* @returns Index into IEMTLB::aEntries.
455	* @param a_pTlb The TLB.
456	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
457	*/
458	#define IEMTLB_TAG_TO_ENTRY(a_pTlb, a_uTag) ( &(a_pTlb)->aEntries[IEMTLB_TAG_TO_INDEX(a_uTag)] )
459
460
461	/**
462	* The per-CPU IEM state.
463	*/
464	typedef struct IEMCPU
465	{
466	/** Info status code that needs to be propagated to the IEM caller.
467	* This cannot be passed internally, as it would complicate all success
468	* checks within the interpreter making the code larger and almost impossible
469	* to get right. Instead, we'll store status codes to pass on here. Each
470	* source of these codes will perform appropriate sanity checks. */
471	int32_t rcPassUp; /* 0x00 */
472
473	/** The current CPU execution mode (CS). */
474	IEMMODE enmCpuMode; /* 0x04 */
475	/** The CPL. */
476	uint8_t uCpl; /* 0x05 */
477
478	/** Whether to bypass access handlers or not. */
479	bool fBypassHandlers; /* 0x06 */
480	/** Whether to disregard the lock prefix (implied or not). */
481	bool fDisregardLock; /* 0x07 */
482
483	/** @name Decoder state.
484	* @{ */
485	#ifdef IEM_WITH_CODE_TLB
486	/** The offset of the next instruction byte. */
487	uint32_t offInstrNextByte; /* 0x08 */
488	/** The number of bytes available at pbInstrBuf for the current instruction.
489	* This takes the max opcode length into account so that doesn't need to be
490	* checked separately. */
491	uint32_t cbInstrBuf; /* 0x0c */
492	/** Pointer to the page containing RIP, user specified buffer or abOpcode.
493	* This can be NULL if the page isn't mappable for some reason, in which
494	* case we'll do fallback stuff.
495	*
496	* If we're executing an instruction from a user specified buffer,
497	* IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
498	* aligned pointer but pointer to the user data.
499	*
500	* For instructions crossing pages, this will start on the first page and be
501	* advanced to the next page by the time we've decoded the instruction. This
502	* therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
503	*/
504	uint8_t const pbInstrBuf; / 0x10 */
505	# if ARCH_BITS == 32
506	uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
507	# endif
508	/** The program counter corresponding to pbInstrBuf.
509	* This is set to a non-canonical address when we need to invalidate it. */
510	uint64_t uInstrBufPc; /* 0x18 */
511	/** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
512	* This takes the CS segment limit into account. */
513	uint16_t cbInstrBufTotal; /* 0x20 */
514	/** Offset into pbInstrBuf of the first byte of the current instruction.
515	* Can be negative to efficiently handle cross page instructions. */
516	int16_t offCurInstrStart; /* 0x22 */
517
518	/** The prefix mask (IEM_OP_PRF_XXX). */
519	uint32_t fPrefixes; /* 0x24 */
520	/** The extra REX ModR/M register field bit (REX.R << 3). */
521	uint8_t uRexReg; /* 0x28 */
522	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
523	* (REX.B << 3). */
524	uint8_t uRexB; /* 0x29 */
525	/** The extra REX SIB index field bit (REX.X << 3). */
526	uint8_t uRexIndex; /* 0x2a */
527
528	/** The effective segment register (X86_SREG_XXX). */
529	uint8_t iEffSeg; /* 0x2b */
530
531	/** The offset of the ModR/M byte relative to the start of the instruction. */
532	uint8_t offModRm; /* 0x2c */
533	#else
534	/** The size of what has currently been fetched into abOpcode. */
535	uint8_t cbOpcode; /* 0x08 */
536	/** The current offset into abOpcode. */
537	uint8_t offOpcode; /* 0x09 */
538	/** The offset of the ModR/M byte relative to the start of the instruction. */
539	uint8_t offModRm; /* 0x0a */
540
541	/** The effective segment register (X86_SREG_XXX). */
542	uint8_t iEffSeg; /* 0x0b */
543
544	/** The prefix mask (IEM_OP_PRF_XXX). */
545	uint32_t fPrefixes; /* 0x0c */
546	/** The extra REX ModR/M register field bit (REX.R << 3). */
547	uint8_t uRexReg; /* 0x10 */
548	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
549	* (REX.B << 3). */
550	uint8_t uRexB; /* 0x11 */
551	/** The extra REX SIB index field bit (REX.X << 3). */
552	uint8_t uRexIndex; /* 0x12 */
553
554	#endif
555
556	/** The effective operand mode. */
557	IEMMODE enmEffOpSize; /* 0x2d, 0x13 */
558	/** The default addressing mode. */
559	IEMMODE enmDefAddrMode; /* 0x2e, 0x14 */
560	/** The effective addressing mode. */
561	IEMMODE enmEffAddrMode; /* 0x2f, 0x15 */
562	/** The default operand mode. */
563	IEMMODE enmDefOpSize; /* 0x30, 0x16 */
564
565	/** Prefix index (VEX.pp) for two byte and three byte tables. */
566	uint8_t idxPrefix; /* 0x31, 0x17 */
567	/** 3rd VEX/EVEX/XOP register.
568	* Please use IEM_GET_EFFECTIVE_VVVV to access. */
569	uint8_t uVex3rdReg; /* 0x32, 0x18 */
570	/** The VEX/EVEX/XOP length field. */
571	uint8_t uVexLength; /* 0x33, 0x19 */
572	/** Additional EVEX stuff. */
573	uint8_t fEvexStuff; /* 0x34, 0x1a */
574
575	/** Explicit alignment padding. */
576	uint8_t abAlignment2a[1]; /* 0x35, 0x1b */
577	/** The FPU opcode (FOP). */
578	uint16_t uFpuOpcode; /* 0x36, 0x1c */
579	#ifndef IEM_WITH_CODE_TLB
580	/** Explicit alignment padding. */
581	uint8_t abAlignment2b[2]; /* 0x1e */
582	#endif
583
584	/** The opcode bytes. */
585	uint8_t abOpcode[15]; /* 0x48, 0x20 */
586	/** Explicit alignment padding. */
587	#ifdef IEM_WITH_CODE_TLB
588	uint8_t abAlignment2c[0x48 - 0x47]; /* 0x37 */
589	#else
590	uint8_t abAlignment2c[0x48 - 0x2f]; /* 0x2f */
591	#endif
592	/** @} */
593
594
595	/** The flags of the current exception / interrupt. */
596	uint32_t fCurXcpt; /* 0x48, 0x48 */
597	/** The current exception / interrupt. */
598	uint8_t uCurXcpt;
599	/** Exception / interrupt recursion depth. */
600	int8_t cXcptRecursions;
601
602	/** The number of active guest memory mappings. */
603	uint8_t cActiveMappings;
604	/** The next unused mapping index. */
605	uint8_t iNextMapping;
606	/** Records for tracking guest memory mappings. */
607	struct
608	{
609	/** The address of the mapped bytes. */
610	void *pv;
611	/** The access flags (IEM_ACCESS_XXX).
612	* IEM_ACCESS_INVALID if the entry is unused. */
613	uint32_t fAccess;
614	#if HC_ARCH_BITS == 64
615	uint32_t u32Alignment4; /*< Alignment padding. /
616	#endif
617	} aMemMappings[3];
618
619	/** Locking records for the mapped memory. */
620	union
621	{
622	PGMPAGEMAPLOCK Lock;
623	uint64_t au64Padding[2];
624	} aMemMappingLocks[3];
625
626	/** Bounce buffer info.
627	* This runs in parallel to aMemMappings. */
628	struct
629	{
630	/** The physical address of the first byte. */
631	RTGCPHYS GCPhysFirst;
632	/** The physical address of the second page. */
633	RTGCPHYS GCPhysSecond;
634	/** The number of bytes in the first page. */
635	uint16_t cbFirst;
636	/** The number of bytes in the second page. */
637	uint16_t cbSecond;
638	/** Whether it's unassigned memory. */
639	bool fUnassigned;
640	/** Explicit alignment padding. */
641	bool afAlignment5[3];
642	} aMemBbMappings[3];
643
644	/* Ensure that aBounceBuffers are aligned at a 32 byte boundrary. */
645	uint64_t abAlignment7[1];
646
647	/** Bounce buffer storage.
648	* This runs in parallel to aMemMappings and aMemBbMappings. */
649	struct
650	{
651	uint8_t ab[512];
652	} aBounceBuffers[3];
653
654
655	/** Pointer set jump buffer - ring-3 context. */
656	R3PTRTYPE(jmp_buf *) pJmpBufR3;
657	/** Pointer set jump buffer - ring-0 context. */
658	R0PTRTYPE(jmp_buf *) pJmpBufR0;
659
660	/** @todo Should move this near @a fCurXcpt later. */
661	/** The CR2 for the current exception / interrupt. */
662	uint64_t uCurXcptCr2;
663	/** The error code for the current exception / interrupt. */
664	uint32_t uCurXcptErr;
665
666	/** @name Statistics
667	* @{ */
668	/** The number of instructions we've executed. */
669	uint32_t cInstructions;
670	/** The number of potential exits. */
671	uint32_t cPotentialExits;
672	/** The number of bytes data or stack written (mostly for IEMExecOneEx).
673	* This may contain uncommitted writes. */
674	uint32_t cbWritten;
675	/** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
676	uint32_t cRetInstrNotImplemented;
677	/** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
678	uint32_t cRetAspectNotImplemented;
679	/** Counts informational statuses returned (other than VINF_SUCCESS). */
680	uint32_t cRetInfStatuses;
681	/** Counts other error statuses returned. */
682	uint32_t cRetErrStatuses;
683	/** Number of times rcPassUp has been used. */
684	uint32_t cRetPassUpStatus;
685	/** Number of times RZ left with instruction commit pending for ring-3. */
686	uint32_t cPendingCommit;
687	/** Number of long jumps. */
688	uint32_t cLongJumps;
689	/** @} */
690
691	/** @name Target CPU information.
692	* @{ */
693	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
694	/** The target CPU. */
695	uint8_t uTargetCpu;
696	#else
697	uint8_t bTargetCpuPadding;
698	#endif
699	/** For selecting assembly works matching the target CPU EFLAGS behaviour, see
700	* IEMTARGETCPU_EFL_BEHAVIOR_XXX for values, with the 1st entry for when no
701	* native host support and the 2nd for when there is.
702	*
703	* The two values are typically indexed by a g_CpumHostFeatures bit.
704	*
705	* This is for instance used for the BSF & BSR instructions where AMD and
706	* Intel CPUs produce different EFLAGS. */
707	uint8_t aidxTargetCpuEflFlavour[2];
708
709	/** The CPU vendor. */
710	CPUMCPUVENDOR enmCpuVendor;
711	/** @} */
712
713	/** @name Host CPU information.
714	* @{ */
715	/** The CPU vendor. */
716	CPUMCPUVENDOR enmHostCpuVendor;
717	/** @} */
718
719	/** Counts RDMSR \#GP(0) LogRel(). */
720	uint8_t cLogRelRdMsr;
721	/** Counts WRMSR \#GP(0) LogRel(). */
722	uint8_t cLogRelWrMsr;
723	/** Alignment padding. */
724	uint8_t abAlignment8[42];
725
726	/** Data TLB.
727	* @remarks Must be 64-byte aligned. */
728	IEMTLB DataTlb;
729	/** Instruction TLB.
730	* @remarks Must be 64-byte aligned. */
731	IEMTLB CodeTlb;
732
733	/** Exception statistics. */
734	STAMCOUNTER aStatXcpts[32];
735	/** Interrupt statistics. */
736	uint32_t aStatInts[256];
737
738	#if defined(VBOX_WITH_STATISTICS) && !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
739	/** Instruction statistics for ring-0/raw-mode. */
740	IEMINSTRSTATS StatsRZ;
741	/** Instruction statistics for ring-3. */
742	IEMINSTRSTATS StatsR3;
743	#endif
744	} IEMCPU;
745	AssertCompileMemberOffset(IEMCPU, fCurXcpt, 0x48);
746	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 8);
747	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 16);
748	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 32);
749	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 64);
750	AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
751	AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
752
753	/** Pointer to the per-CPU IEM state. */
754	typedef IEMCPU *PIEMCPU;
755	/** Pointer to the const per-CPU IEM state. */
756	typedef IEMCPU const *PCIEMCPU;
757
758
759	/** @def IEM_GET_CTX
760	* Gets the guest CPU context for the calling EMT.
761	* @returns PCPUMCTX
762	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
763	*/
764	#define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
765
766	/** @def IEM_CTX_ASSERT
767	* Asserts that the @a a_fExtrnMbz is present in the CPU context.
768	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
769	* @param a_fExtrnMbz The mask of CPUMCTX_EXTRN_XXX flags that must be zero.
770	*/
771	#define IEM_CTX_ASSERT(a_pVCpu, a_fExtrnMbz) AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
772	("fExtrn=%#RX64 fExtrnMbz=%#RX64\n", (a_pVCpu)->cpum.GstCtx.fExtrn, \
773	(a_fExtrnMbz)))
774
775	/** @def IEM_CTX_IMPORT_RET
776	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
777	*
778	* Will call the keep to import the bits as needed.
779	*
780	* Returns on import failure.
781	*
782	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
783	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
784	*/
785	#define IEM_CTX_IMPORT_RET(a_pVCpu, a_fExtrnImport) \
786	do { \
787	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
788	{ /* likely */ } \
789	else \
790	{ \
791	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
792	AssertRCReturn(rcCtxImport, rcCtxImport); \
793	} \
794	} while (0)
795
796	/** @def IEM_CTX_IMPORT_NORET
797	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
798	*
799	* Will call the keep to import the bits as needed.
800	*
801	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
802	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
803	*/
804	#define IEM_CTX_IMPORT_NORET(a_pVCpu, a_fExtrnImport) \
805	do { \
806	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
807	{ /* likely */ } \
808	else \
809	{ \
810	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
811	AssertLogRelRC(rcCtxImport); \
812	} \
813	} while (0)
814
815	/** @def IEM_CTX_IMPORT_JMP
816	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
817	*
818	* Will call the keep to import the bits as needed.
819	*
820	* Jumps on import failure.
821	*
822	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
823	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
824	*/
825	#define IEM_CTX_IMPORT_JMP(a_pVCpu, a_fExtrnImport) \
826	do { \
827	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
828	{ /* likely */ } \
829	else \
830	{ \
831	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
832	AssertRCStmt(rcCtxImport, longjmp(*pVCpu->iem.s.CTX_SUFF(pJmpBuf), rcCtxImport)); \
833	} \
834	} while (0)
835
836
837
838	/** @def IEM_GET_TARGET_CPU
839	* Gets the current IEMTARGETCPU value.
840	* @returns IEMTARGETCPU value.
841	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
842	*/
843	#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
844	# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
845	#else
846	# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
847	#endif
848
849	/** @def IEM_GET_INSTR_LEN
850	* Gets the instruction length. */
851	#ifdef IEM_WITH_CODE_TLB
852	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
853	#else
854	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
855	#endif
856
857
858	/**
859	* Shared per-VM IEM data.
860	*/
861	typedef struct IEM
862	{
863	/** The VMX APIC-access page handler type. */
864	PGMPHYSHANDLERTYPE hVmxApicAccessPage;
865	#ifndef VBOX_WITHOUT_CPUID_HOST_CALL
866	/** Set if the CPUID host call functionality is enabled. */
867	bool fCpuIdHostCall;
868	#endif
869	} IEM;
870
871
872
873	/** @name IEM_ACCESS_XXX - Access details.
874	* @{ */
875	#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
876	#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
877	#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
878	#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
879	#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
880	#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
881	#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
882	#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
883	#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
884	#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
885	/** The writes are partial, so if initialize the bounce buffer with the
886	* orignal RAM content. */
887	#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
888	/** Used in aMemMappings to indicate that the entry is bounce buffered. */
889	#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
890	/** Bounce buffer with ring-3 write pending, first page. */
891	#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
892	/** Bounce buffer with ring-3 write pending, second page. */
893	#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
894	/** Not locked, accessed via the TLB. */
895	#define IEM_ACCESS_NOT_LOCKED UINT32_C(0x00001000)
896	/** Valid bit mask. */
897	#define IEM_ACCESS_VALID_MASK UINT32_C(0x00001fff)
898	/** Shift count for the TLB flags (upper word). */
899	#define IEM_ACCESS_SHIFT_TLB_FLAGS 16
900
901	/** Read+write data alias. */
902	#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
903	/** Write data alias. */
904	#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
905	/** Read data alias. */
906	#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_DATA)
907	/** Instruction fetch alias. */
908	#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_WHAT_CODE)
909	/** Stack write alias. */
910	#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
911	/** Stack read alias. */
912	#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_STACK)
913	/** Stack read+write alias. */
914	#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
915	/** Read system table alias. */
916	#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_SYS)
917	/** Read+write system table alias. */
918	#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_SYS)
919	/** @} */
920
921	/** @name Prefix constants (IEMCPU::fPrefixes)
922	* @{ */
923	#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /*< CS segment prefix (0x2e). /
924	#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /*< SS segment prefix (0x36). /
925	#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /*< DS segment prefix (0x3e). /
926	#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /*< ES segment prefix (0x26). /
927	#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /*< FS segment prefix (0x64). /
928	#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /*< GS segment prefix (0x65). /
929	#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
930
931	#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /*< Operand size prefix (0x66). /
932	#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /*< REX.W prefix (0x48-0x4f). /
933	#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /*< Address size prefix (0x67). /
934
935	#define IEM_OP_PRF_LOCK RT_BIT_32(16) /*< Lock prefix (0xf0). /
936	#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /*< Repeat-not-zero prefix (0xf2). /
937	#define IEM_OP_PRF_REPZ RT_BIT_32(18) /*< Repeat-if-zero prefix (0xf3). /
938
939	#define IEM_OP_PRF_REX RT_BIT_32(24) /*< Any REX prefix (0x40-0x4f). /
940	#define IEM_OP_PRF_REX_R RT_BIT_32(25) /*< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). /
941	#define IEM_OP_PRF_REX_B RT_BIT_32(26) /*< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). /
942	#define IEM_OP_PRF_REX_X RT_BIT_32(27) /*< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). /
943	/** Mask with all the REX prefix flags.
944	* This is generally for use when needing to undo the REX prefixes when they
945	* are followed legacy prefixes and therefore does not immediately preceed
946	* the first opcode byte.
947	* For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
948	#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX \| IEM_OP_PRF_REX_R \| IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X \| IEM_OP_PRF_SIZE_REX_W )
949
950	#define IEM_OP_PRF_VEX RT_BIT_32(28) /*< Indiciates VEX prefix. /
951	#define IEM_OP_PRF_EVEX RT_BIT_32(29) /*< Indiciates EVEX prefix. /
952	#define IEM_OP_PRF_XOP RT_BIT_32(30) /*< Indiciates XOP prefix. /
953	/** @} */
954
955	/** @name IEMOPFORM_XXX - Opcode forms
956	* @note These are ORed together with IEMOPHINT_XXX.
957	* @{ */
958	/** ModR/M: reg, r/m */
959	#define IEMOPFORM_RM 0
960	/** ModR/M: reg, r/m (register) */
961	#define IEMOPFORM_RM_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
962	/** ModR/M: reg, r/m (memory) */
963	#define IEMOPFORM_RM_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
964	/** ModR/M: reg, r/m */
965	#define IEMOPFORM_RMI 1
966	/** ModR/M: reg, r/m (register) */
967	#define IEMOPFORM_RMI_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
968	/** ModR/M: reg, r/m (memory) */
969	#define IEMOPFORM_RMI_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
970	/** ModR/M: r/m, reg */
971	#define IEMOPFORM_MR 2
972	/** ModR/M: r/m (register), reg */
973	#define IEMOPFORM_MR_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
974	/** ModR/M: r/m (memory), reg */
975	#define IEMOPFORM_MR_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
976	/** ModR/M: r/m only */
977	#define IEMOPFORM_M 3
978	/** ModR/M: r/m only (register). */
979	#define IEMOPFORM_M_REG (IEMOPFORM_M \| IEMOPFORM_MOD3)
980	/** ModR/M: r/m only (memory). */
981	#define IEMOPFORM_M_MEM (IEMOPFORM_M \| IEMOPFORM_NOT_MOD3)
982	/** ModR/M: reg only */
983	#define IEMOPFORM_R 4
984
985	/** VEX+ModR/M: reg, r/m */
986	#define IEMOPFORM_VEX_RM 8
987	/** VEX+ModR/M: reg, r/m (register) */
988	#define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM \| IEMOPFORM_MOD3)
989	/** VEX+ModR/M: reg, r/m (memory) */
990	#define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM \| IEMOPFORM_NOT_MOD3)
991	/** VEX+ModR/M: r/m, reg */
992	#define IEMOPFORM_VEX_MR 9
993	/** VEX+ModR/M: r/m (register), reg */
994	#define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR \| IEMOPFORM_MOD3)
995	/** VEX+ModR/M: r/m (memory), reg */
996	#define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR \| IEMOPFORM_NOT_MOD3)
997	/** VEX+ModR/M: r/m only */
998	#define IEMOPFORM_VEX_M 10
999	/** VEX+ModR/M: r/m only (register). */
1000	#define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M \| IEMOPFORM_MOD3)
1001	/** VEX+ModR/M: r/m only (memory). */
1002	#define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M \| IEMOPFORM_NOT_MOD3)
1003	/** VEX+ModR/M: reg only */
1004	#define IEMOPFORM_VEX_R 11
1005	/** VEX+ModR/M: reg, vvvv, r/m */
1006	#define IEMOPFORM_VEX_RVM 12
1007	/** VEX+ModR/M: reg, vvvv, r/m (register). */
1008	#define IEMOPFORM_VEX_RVM_REG (IEMOPFORM_VEX_RVM \| IEMOPFORM_MOD3)
1009	/** VEX+ModR/M: reg, vvvv, r/m (memory). */
1010	#define IEMOPFORM_VEX_RVM_MEM (IEMOPFORM_VEX_RVM \| IEMOPFORM_NOT_MOD3)
1011	/** VEX+ModR/M: reg, r/m, vvvv */
1012	#define IEMOPFORM_VEX_RMV 13
1013	/** VEX+ModR/M: reg, r/m, vvvv (register). */
1014	#define IEMOPFORM_VEX_RMV_REG (IEMOPFORM_VEX_RMV \| IEMOPFORM_MOD3)
1015	/** VEX+ModR/M: reg, r/m, vvvv (memory). */
1016	#define IEMOPFORM_VEX_RMV_MEM (IEMOPFORM_VEX_RMV \| IEMOPFORM_NOT_MOD3)
1017	/** VEX+ModR/M: reg, r/m, imm8 */
1018	#define IEMOPFORM_VEX_RMI 14
1019	/** VEX+ModR/M: reg, r/m, imm8 (register). */
1020	#define IEMOPFORM_VEX_RMI_REG (IEMOPFORM_VEX_RMI \| IEMOPFORM_MOD3)
1021	/** VEX+ModR/M: reg, r/m, imm8 (memory). */
1022	#define IEMOPFORM_VEX_RMI_MEM (IEMOPFORM_VEX_RMI \| IEMOPFORM_NOT_MOD3)
1023	/** VEX+ModR/M: r/m, vvvv, reg */
1024	#define IEMOPFORM_VEX_MVR 15
1025	/** VEX+ModR/M: r/m, vvvv, reg (register) */
1026	#define IEMOPFORM_VEX_MVR_REG (IEMOPFORM_VEX_MVR \| IEMOPFORM_MOD3)
1027	/** VEX+ModR/M: r/m, vvvv, reg (memory) */
1028	#define IEMOPFORM_VEX_MVR_MEM (IEMOPFORM_VEX_MVR \| IEMOPFORM_NOT_MOD3)
1029	/** VEX+ModR/M+/n: vvvv, r/m */
1030	#define IEMOPFORM_VEX_VM 16
1031	/** VEX+ModR/M+/n: vvvv, r/m (register) */
1032	#define IEMOPFORM_VEX_VM_REG (IEMOPFORM_VEX_VM \| IEMOPFORM_MOD3)
1033	/** VEX+ModR/M+/n: vvvv, r/m (memory) */
1034	#define IEMOPFORM_VEX_VM_MEM (IEMOPFORM_VEX_VM \| IEMOPFORM_NOT_MOD3)
1035
1036	/** Fixed register instruction, no R/M. */
1037	#define IEMOPFORM_FIXED 32
1038
1039	/** The r/m is a register. */
1040	#define IEMOPFORM_MOD3 RT_BIT_32(8)
1041	/** The r/m is a memory access. */
1042	#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
1043	/** @} */
1044
1045	/** @name IEMOPHINT_XXX - Additional Opcode Hints
1046	* @note These are ORed together with IEMOPFORM_XXX.
1047	* @{ */
1048	/** Ignores the operand size prefix (66h). */
1049	#define IEMOPHINT_IGNORES_OZ_PFX RT_BIT_32(10)
1050	/** Ignores REX.W (aka WIG). */
1051	#define IEMOPHINT_IGNORES_REXW RT_BIT_32(11)
1052	/** Both the operand size prefixes (66h + REX.W) are ignored. */
1053	#define IEMOPHINT_IGNORES_OP_SIZES (IEMOPHINT_IGNORES_OZ_PFX \| IEMOPHINT_IGNORES_REXW)
1054	/** Allowed with the lock prefix. */
1055	#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
1056	/** The VEX.L value is ignored (aka LIG). */
1057	#define IEMOPHINT_VEX_L_IGNORED RT_BIT_32(12)
1058	/** The VEX.L value must be zero (i.e. 128-bit width only). */
1059	#define IEMOPHINT_VEX_L_ZERO RT_BIT_32(13)
1060	/** The VEX.V value must be zero. */
1061	#define IEMOPHINT_VEX_V_ZERO RT_BIT_32(14)
1062
1063	/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
1064	#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
1065	/** @} */
1066
1067	/**
1068	* Possible hardware task switch sources.
1069	*/
1070	typedef enum IEMTASKSWITCH
1071	{
1072	/** Task switch caused by an interrupt/exception. */
1073	IEMTASKSWITCH_INT_XCPT = 1,
1074	/** Task switch caused by a far CALL. */
1075	IEMTASKSWITCH_CALL,
1076	/** Task switch caused by a far JMP. */
1077	IEMTASKSWITCH_JUMP,
1078	/** Task switch caused by an IRET. */
1079	IEMTASKSWITCH_IRET
1080	} IEMTASKSWITCH;
1081	AssertCompileSize(IEMTASKSWITCH, 4);
1082
1083	/**
1084	* Possible CrX load (write) sources.
1085	*/
1086	typedef enum IEMACCESSCRX
1087	{
1088	/** CrX access caused by 'mov crX' instruction. */
1089	IEMACCESSCRX_MOV_CRX,
1090	/** CrX (CR0) write caused by 'lmsw' instruction. */
1091	IEMACCESSCRX_LMSW,
1092	/** CrX (CR0) write caused by 'clts' instruction. */
1093	IEMACCESSCRX_CLTS,
1094	/** CrX (CR0) read caused by 'smsw' instruction. */
1095	IEMACCESSCRX_SMSW
1096	} IEMACCESSCRX;
1097
1098	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1099	/** @name IEM_SLAT_FAIL_XXX - Second-level address translation failure information.
1100	*
1101	* These flags provide further context to SLAT page-walk failures that could not be
1102	* determined by PGM (e.g, PGM is not privy to memory access permissions).
1103	*
1104	* @{
1105	*/
1106	/** Translating a nested-guest linear address failed accessing a nested-guest
1107	* physical address. */
1108	# define IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR RT_BIT_32(0)
1109	/** Translating a nested-guest linear address failed accessing a
1110	* paging-structure entry or updating accessed/dirty bits. */
1111	# define IEM_SLAT_FAIL_LINEAR_TO_PAGE_TABLE RT_BIT_32(1)
1112	/** @} */
1113
1114	DECLCALLBACK(FNPGMPHYSHANDLER) iemVmxApicAccessPageHandler;
1115	# ifndef IN_RING3
1116	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) iemVmxApicAccessPagePfHandler;
1117	# endif
1118	#endif
1119
1120	/**
1121	* Indicates to the verifier that the given flag set is undefined.
1122	*
1123	* Can be invoked again to add more flags.
1124	*
1125	* This is a NOOP if the verifier isn't compiled in.
1126	*
1127	* @note We're temporarily keeping this until code is converted to new
1128	* disassembler style opcode handling.
1129	*/
1130	#define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
1131
1132
1133	/** @def IEM_DECL_IMPL_TYPE
1134	* For typedef'ing an instruction implementation function.
1135	*
1136	* @param a_RetType The return type.
1137	* @param a_Name The name of the type.
1138	* @param a_ArgList The argument list enclosed in parentheses.
1139	*/
1140
1141	/** @def IEM_DECL_IMPL_DEF
1142	* For defining an instruction implementation function.
1143	*
1144	* @param a_RetType The return type.
1145	* @param a_Name The name of the type.
1146	* @param a_ArgList The argument list enclosed in parentheses.
1147	*/
1148
1149	#if defined(__GNUC__) && defined(RT_ARCH_X86)
1150	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1151	__attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
1152	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1153	__attribute__((__fastcall__, __nothrow__)) a_RetType a_Name a_ArgList
1154	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1155	__attribute__((__fastcall__, __nothrow__)) a_RetType a_Name a_ArgList
1156
1157	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
1158	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1159	a_RetType (__fastcall a_Name) a_ArgList
1160	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1161	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
1162	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1163	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
1164
1165	#elif __cplusplus >= 201700 /* P0012R1 support */
1166	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1167	a_RetType (VBOXCALL a_Name) a_ArgList RT_NOEXCEPT
1168	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1169	a_RetType VBOXCALL a_Name a_ArgList RT_NOEXCEPT
1170	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1171	a_RetType VBOXCALL a_Name a_ArgList RT_NOEXCEPT
1172
1173	#else
1174	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1175	a_RetType (VBOXCALL a_Name) a_ArgList
1176	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1177	a_RetType VBOXCALL a_Name a_ArgList
1178	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1179	a_RetType VBOXCALL a_Name a_ArgList
1180
1181	#endif
1182
1183	/** Defined in IEMAllAImplC.cpp but also used by IEMAllAImplA.asm. */
1184	RT_C_DECLS_BEGIN
1185	extern uint8_t const g_afParity[256];
1186	RT_C_DECLS_END
1187
1188
1189	/** @name Arithmetic assignment operations on bytes (binary).
1190	* @{ */
1191	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU8, (uint8_t pu8Dst, uint8_t u8Src, uint32_t pEFlags));
1192	typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
1193	FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
1194	FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
1195	FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
1196	FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
1197	FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
1198	FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
1199	FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
1200	/** @} */
1201
1202	/** @name Arithmetic assignment operations on words (binary).
1203	* @{ */
1204	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU16, (uint16_t pu16Dst, uint16_t u16Src, uint32_t pEFlags));
1205	typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
1206	FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
1207	FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
1208	FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
1209	FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
1210	FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
1211	FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
1212	FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
1213	/** @} */
1214
1215	/** @name Arithmetic assignment operations on double words (binary).
1216	* @{ */
1217	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU32, (uint32_t pu32Dst, uint32_t u32Src, uint32_t pEFlags));
1218	typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
1219	FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
1220	FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
1221	FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
1222	FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
1223	FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
1224	FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
1225	FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
1226	FNIEMAIMPLBINU32 iemAImpl_blsi_u32, iemAImpl_blsi_u32_fallback;
1227	FNIEMAIMPLBINU32 iemAImpl_blsr_u32, iemAImpl_blsr_u32_fallback;
1228	FNIEMAIMPLBINU32 iemAImpl_blsmsk_u32, iemAImpl_blsmsk_u32_fallback;
1229	/** @} */
1230
1231	/** @name Arithmetic assignment operations on quad words (binary).
1232	* @{ */
1233	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU64, (uint64_t pu64Dst, uint64_t u64Src, uint32_t pEFlags));
1234	typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
1235	FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
1236	FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
1237	FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
1238	FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
1239	FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
1240	FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
1241	FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
1242	FNIEMAIMPLBINU64 iemAImpl_blsi_u64, iemAImpl_blsi_u64_fallback;
1243	FNIEMAIMPLBINU64 iemAImpl_blsr_u64, iemAImpl_blsr_u64_fallback;
1244	FNIEMAIMPLBINU64 iemAImpl_blsmsk_u64, iemAImpl_blsmsk_u64_fallback;
1245	/** @} */
1246
1247	/** @name Compare operations (thrown in with the binary ops).
1248	* @{ */
1249	FNIEMAIMPLBINU8 iemAImpl_cmp_u8;
1250	FNIEMAIMPLBINU16 iemAImpl_cmp_u16;
1251	FNIEMAIMPLBINU32 iemAImpl_cmp_u32;
1252	FNIEMAIMPLBINU64 iemAImpl_cmp_u64;
1253	/** @} */
1254
1255	/** @name Test operations (thrown in with the binary ops).
1256	* @{ */
1257	FNIEMAIMPLBINU8 iemAImpl_test_u8;
1258	FNIEMAIMPLBINU16 iemAImpl_test_u16;
1259	FNIEMAIMPLBINU32 iemAImpl_test_u32;
1260	FNIEMAIMPLBINU64 iemAImpl_test_u64;
1261	/** @} */
1262
1263	/** @name Bit operations operations (thrown in with the binary ops).
1264	* @{ */
1265	FNIEMAIMPLBINU16 iemAImpl_bt_u16;
1266	FNIEMAIMPLBINU32 iemAImpl_bt_u32;
1267	FNIEMAIMPLBINU64 iemAImpl_bt_u64;
1268	FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
1269	FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
1270	FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
1271	FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
1272	FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
1273	FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
1274	FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
1275	FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
1276	FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
1277	/** @} */
1278
1279	/** @name Arithmetic three operand operations on double words (binary).
1280	* @{ */
1281	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32, (uint32_t pu32Dst, uint32_t u32Src1, uint32_t u32Src2, uint32_t pEFlags));
1282	typedef FNIEMAIMPLBINVEXU32 *PFNIEMAIMPLBINVEXU32;
1283	FNIEMAIMPLBINVEXU32 iemAImpl_andn_u32, iemAImpl_andn_u32_fallback;
1284	FNIEMAIMPLBINVEXU32 iemAImpl_bextr_u32, iemAImpl_bextr_u32_fallback;
1285	FNIEMAIMPLBINVEXU32 iemAImpl_bzhi_u32, iemAImpl_bzhi_u32_fallback;
1286	/** @} */
1287
1288	/** @name Arithmetic three operand operations on quad words (binary).
1289	* @{ */
1290	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64, (uint64_t pu64Dst, uint64_t u64Src1, uint64_t u64Src2, uint32_t pEFlags));
1291	typedef FNIEMAIMPLBINVEXU64 *PFNIEMAIMPLBINVEXU64;
1292	FNIEMAIMPLBINVEXU64 iemAImpl_andn_u64, iemAImpl_andn_u64_fallback;
1293	FNIEMAIMPLBINVEXU64 iemAImpl_bextr_u64, iemAImpl_bextr_u64_fallback;
1294	FNIEMAIMPLBINVEXU64 iemAImpl_bzhi_u64, iemAImpl_bzhi_u64_fallback;
1295	/** @} */
1296
1297	/** @name Arithmetic three operand operations on double words w/o EFLAGS (binary).
1298	* @{ */
1299	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32NOEFL, (uint32_t *pu32Dst, uint32_t u32Src1, uint32_t u32Src2));
1300	typedef FNIEMAIMPLBINVEXU32NOEFL *PFNIEMAIMPLBINVEXU32NOEFL;
1301	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pdep_u32, iemAImpl_pdep_u32_fallback;
1302	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pext_u32, iemAImpl_pext_u32_fallback;
1303	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_sarx_u32, iemAImpl_sarx_u32_fallback;
1304	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shlx_u32, iemAImpl_shlx_u32_fallback;
1305	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shrx_u32, iemAImpl_shrx_u32_fallback;
1306	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_rorx_u32;
1307	/** @} */
1308
1309	/** @name Arithmetic three operand operations on quad words w/o EFLAGS (binary).
1310	* @{ */
1311	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64NOEFL, (uint64_t *pu64Dst, uint64_t u64Src1, uint64_t u64Src2));
1312	typedef FNIEMAIMPLBINVEXU64NOEFL *PFNIEMAIMPLBINVEXU64NOEFL;
1313	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pdep_u64, iemAImpl_pdep_u64_fallback;
1314	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pext_u64, iemAImpl_pext_u64_fallback;
1315	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_sarx_u64, iemAImpl_sarx_u64_fallback;
1316	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shlx_u64, iemAImpl_shlx_u64_fallback;
1317	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shrx_u64, iemAImpl_shrx_u64_fallback;
1318	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_rorx_u64;
1319	/** @} */
1320
1321	/** @name MULX 32-bit and 64-bit.
1322	* @{ */
1323	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU32, (uint32_t puDst1, uint32_t puDst2, uint32_t uSrc1, uint32_t uSrc2));
1324	typedef FNIEMAIMPLMULXVEXU32 *PFNIEMAIMPLMULXVEXU32;
1325	FNIEMAIMPLMULXVEXU32 iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback;
1326
1327	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU64, (uint64_t puDst1, uint64_t puDst2, uint64_t uSrc1, uint64_t uSrc2));
1328	typedef FNIEMAIMPLMULXVEXU64 *PFNIEMAIMPLMULXVEXU64;
1329	FNIEMAIMPLMULXVEXU64 iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback;
1330	/** @} */
1331
1332
1333	/** @name Exchange memory with register operations.
1334	* @{ */
1335	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_locked, (uint8_t pu8Mem, uint8_t pu8Reg));
1336	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_locked,(uint16_t pu16Mem, uint16_t pu16Reg));
1337	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_locked,(uint32_t pu32Mem, uint32_t pu32Reg));
1338	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_locked,(uint64_t pu64Mem, uint64_t pu64Reg));
1339	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_unlocked, (uint8_t pu8Mem, uint8_t pu8Reg));
1340	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_unlocked,(uint16_t pu16Mem, uint16_t pu16Reg));
1341	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_unlocked,(uint32_t pu32Mem, uint32_t pu32Reg));
1342	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_unlocked,(uint64_t pu64Mem, uint64_t pu64Reg));
1343	/** @} */
1344
1345	/** @name Exchange and add operations.
1346	* @{ */
1347	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1348	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1349	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1350	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1351	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1352	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1353	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1354	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1355	/** @} */
1356
1357	/** @name Compare and exchange.
1358	* @{ */
1359	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1360	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1361	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1362	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1363	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1364	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1365	#if ARCH_BITS == 32
1366	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1367	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1368	#else
1369	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1370	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1371	#endif
1372	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1373	uint32_t *pEFlags));
1374	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1375	uint32_t *pEFlags));
1376	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1377	uint32_t *pEFlags));
1378	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1379	uint32_t *pEFlags));
1380	#ifndef RT_ARCH_ARM64
1381	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
1382	PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
1383	#endif
1384	/** @} */
1385
1386	/** @name Memory ordering
1387	* @{ */
1388	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
1389	typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
1390	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
1391	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
1392	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
1393	#ifndef RT_ARCH_ARM64
1394	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
1395	#endif
1396	/** @} */
1397
1398	/** @name Double precision shifts
1399	* @{ */
1400	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t pEFlags));
1401	typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
1402	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t pEFlags));
1403	typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
1404	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t pEFlags));
1405	typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
1406	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16, iemAImpl_shld_u16_amd, iemAImpl_shld_u16_intel;
1407	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32, iemAImpl_shld_u32_amd, iemAImpl_shld_u32_intel;
1408	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64, iemAImpl_shld_u64_amd, iemAImpl_shld_u64_intel;
1409	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16, iemAImpl_shrd_u16_amd, iemAImpl_shrd_u16_intel;
1410	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32, iemAImpl_shrd_u32_amd, iemAImpl_shrd_u32_intel;
1411	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64, iemAImpl_shrd_u64_amd, iemAImpl_shrd_u64_intel;
1412	/** @} */
1413
1414
1415	/** @name Bit search operations (thrown in with the binary ops).
1416	* @{ */
1417	FNIEMAIMPLBINU16 iemAImpl_bsf_u16, iemAImpl_bsf_u16_amd, iemAImpl_bsf_u16_intel;
1418	FNIEMAIMPLBINU32 iemAImpl_bsf_u32, iemAImpl_bsf_u32_amd, iemAImpl_bsf_u32_intel;
1419	FNIEMAIMPLBINU64 iemAImpl_bsf_u64, iemAImpl_bsf_u64_amd, iemAImpl_bsf_u64_intel;
1420	FNIEMAIMPLBINU16 iemAImpl_bsr_u16, iemAImpl_bsr_u16_amd, iemAImpl_bsr_u16_intel;
1421	FNIEMAIMPLBINU32 iemAImpl_bsr_u32, iemAImpl_bsr_u32_amd, iemAImpl_bsr_u32_intel;
1422	FNIEMAIMPLBINU64 iemAImpl_bsr_u64, iemAImpl_bsr_u64_amd, iemAImpl_bsr_u64_intel;
1423	FNIEMAIMPLBINU16 iemAImpl_lzcnt_u16, iemAImpl_lzcnt_u16_amd, iemAImpl_lzcnt_u16_intel;
1424	FNIEMAIMPLBINU32 iemAImpl_lzcnt_u32, iemAImpl_lzcnt_u32_amd, iemAImpl_lzcnt_u32_intel;
1425	FNIEMAIMPLBINU64 iemAImpl_lzcnt_u64, iemAImpl_lzcnt_u64_amd, iemAImpl_lzcnt_u64_intel;
1426	FNIEMAIMPLBINU16 iemAImpl_tzcnt_u16, iemAImpl_tzcnt_u16_amd, iemAImpl_tzcnt_u16_intel;
1427	FNIEMAIMPLBINU32 iemAImpl_tzcnt_u32, iemAImpl_tzcnt_u32_amd, iemAImpl_tzcnt_u32_intel;
1428	FNIEMAIMPLBINU64 iemAImpl_tzcnt_u64, iemAImpl_tzcnt_u64_amd, iemAImpl_tzcnt_u64_intel;
1429	FNIEMAIMPLBINU16 iemAImpl_popcnt_u16, iemAImpl_popcnt_u16_fallback;
1430	FNIEMAIMPLBINU32 iemAImpl_popcnt_u32, iemAImpl_popcnt_u32_fallback;
1431	FNIEMAIMPLBINU64 iemAImpl_popcnt_u64, iemAImpl_popcnt_u64_fallback;
1432	/** @} */
1433
1434	/** @name Signed multiplication operations (thrown in with the binary ops).
1435	* @{ */
1436	FNIEMAIMPLBINU16 iemAImpl_imul_two_u16, iemAImpl_imul_two_u16_amd, iemAImpl_imul_two_u16_intel;
1437	FNIEMAIMPLBINU32 iemAImpl_imul_two_u32, iemAImpl_imul_two_u32_amd, iemAImpl_imul_two_u32_intel;
1438	FNIEMAIMPLBINU64 iemAImpl_imul_two_u64, iemAImpl_imul_two_u64_amd, iemAImpl_imul_two_u64_intel;
1439	/** @} */
1440
1441	/** @name Arithmetic assignment operations on bytes (unary).
1442	* @{ */
1443	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t pu8Dst, uint32_t pEFlags));
1444	typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
1445	FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
1446	FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
1447	FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
1448	FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
1449	/** @} */
1450
1451	/** @name Arithmetic assignment operations on words (unary).
1452	* @{ */
1453	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t pu16Dst, uint32_t pEFlags));
1454	typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
1455	FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
1456	FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
1457	FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
1458	FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
1459	/** @} */
1460
1461	/** @name Arithmetic assignment operations on double words (unary).
1462	* @{ */
1463	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t pu32Dst, uint32_t pEFlags));
1464	typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
1465	FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
1466	FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
1467	FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
1468	FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
1469	/** @} */
1470
1471	/** @name Arithmetic assignment operations on quad words (unary).
1472	* @{ */
1473	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t pu64Dst, uint32_t pEFlags));
1474	typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
1475	FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
1476	FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
1477	FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
1478	FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
1479	/** @} */
1480
1481
1482	/** @name Shift operations on bytes (Group 2).
1483	* @{ */
1484	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU8,(uint8_t pu8Dst, uint8_t cShift, uint32_t pEFlags));
1485	typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
1486	FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8, iemAImpl_rol_u8_amd, iemAImpl_rol_u8_intel;
1487	FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8, iemAImpl_ror_u8_amd, iemAImpl_ror_u8_intel;
1488	FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8, iemAImpl_rcl_u8_amd, iemAImpl_rcl_u8_intel;
1489	FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8, iemAImpl_rcr_u8_amd, iemAImpl_rcr_u8_intel;
1490	FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8, iemAImpl_shl_u8_amd, iemAImpl_shl_u8_intel;
1491	FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8, iemAImpl_shr_u8_amd, iemAImpl_shr_u8_intel;
1492	FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8, iemAImpl_sar_u8_amd, iemAImpl_sar_u8_intel;
1493	/** @} */
1494
1495	/** @name Shift operations on words (Group 2).
1496	* @{ */
1497	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU16,(uint16_t pu16Dst, uint8_t cShift, uint32_t pEFlags));
1498	typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
1499	FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16, iemAImpl_rol_u16_amd, iemAImpl_rol_u16_intel;
1500	FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16, iemAImpl_ror_u16_amd, iemAImpl_ror_u16_intel;
1501	FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16, iemAImpl_rcl_u16_amd, iemAImpl_rcl_u16_intel;
1502	FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16, iemAImpl_rcr_u16_amd, iemAImpl_rcr_u16_intel;
1503	FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16, iemAImpl_shl_u16_amd, iemAImpl_shl_u16_intel;
1504	FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16, iemAImpl_shr_u16_amd, iemAImpl_shr_u16_intel;
1505	FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16, iemAImpl_sar_u16_amd, iemAImpl_sar_u16_intel;
1506	/** @} */
1507
1508	/** @name Shift operations on double words (Group 2).
1509	* @{ */
1510	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU32,(uint32_t pu32Dst, uint8_t cShift, uint32_t pEFlags));
1511	typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
1512	FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32, iemAImpl_rol_u32_amd, iemAImpl_rol_u32_intel;
1513	FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32, iemAImpl_ror_u32_amd, iemAImpl_ror_u32_intel;
1514	FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32, iemAImpl_rcl_u32_amd, iemAImpl_rcl_u32_intel;
1515	FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32, iemAImpl_rcr_u32_amd, iemAImpl_rcr_u32_intel;
1516	FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32, iemAImpl_shl_u32_amd, iemAImpl_shl_u32_intel;
1517	FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32, iemAImpl_shr_u32_amd, iemAImpl_shr_u32_intel;
1518	FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32, iemAImpl_sar_u32_amd, iemAImpl_sar_u32_intel;
1519	/** @} */
1520
1521	/** @name Shift operations on words (Group 2).
1522	* @{ */
1523	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU64,(uint64_t pu64Dst, uint8_t cShift, uint32_t pEFlags));
1524	typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
1525	FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64, iemAImpl_rol_u64_amd, iemAImpl_rol_u64_intel;
1526	FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64, iemAImpl_ror_u64_amd, iemAImpl_ror_u64_intel;
1527	FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64, iemAImpl_rcl_u64_amd, iemAImpl_rcl_u64_intel;
1528	FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64, iemAImpl_rcr_u64_amd, iemAImpl_rcr_u64_intel;
1529	FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64, iemAImpl_shl_u64_amd, iemAImpl_shl_u64_intel;
1530	FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64, iemAImpl_shr_u64_amd, iemAImpl_shr_u64_intel;
1531	FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64, iemAImpl_sar_u64_amd, iemAImpl_sar_u64_intel;
1532	/** @} */
1533
1534	/** @name Multiplication and division operations.
1535	* @{ */
1536	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t pu16AX, uint8_t u8FactorDivisor, uint32_t pEFlags));
1537	typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
1538	FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_mul_u8_amd, iemAImpl_mul_u8_intel;
1539	FNIEMAIMPLMULDIVU8 iemAImpl_imul_u8, iemAImpl_imul_u8_amd, iemAImpl_imul_u8_intel;
1540	FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_div_u8_amd, iemAImpl_div_u8_intel;
1541	FNIEMAIMPLMULDIVU8 iemAImpl_idiv_u8, iemAImpl_idiv_u8_amd, iemAImpl_idiv_u8_intel;
1542
1543	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t pu16AX, uint16_t pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
1544	typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
1545	FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_mul_u16_amd, iemAImpl_mul_u16_intel;
1546	FNIEMAIMPLMULDIVU16 iemAImpl_imul_u16, iemAImpl_imul_u16_amd, iemAImpl_imul_u16_intel;
1547	FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_div_u16_amd, iemAImpl_div_u16_intel;
1548	FNIEMAIMPLMULDIVU16 iemAImpl_idiv_u16, iemAImpl_idiv_u16_amd, iemAImpl_idiv_u16_intel;
1549
1550	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t pu32EAX, uint32_t pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
1551	typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
1552	FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_mul_u32_amd, iemAImpl_mul_u32_intel;
1553	FNIEMAIMPLMULDIVU32 iemAImpl_imul_u32, iemAImpl_imul_u32_amd, iemAImpl_imul_u32_intel;
1554	FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_div_u32_amd, iemAImpl_div_u32_intel;
1555	FNIEMAIMPLMULDIVU32 iemAImpl_idiv_u32, iemAImpl_idiv_u32_amd, iemAImpl_idiv_u32_intel;
1556
1557	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t pu64RAX, uint64_t pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
1558	typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
1559	FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_mul_u64_amd, iemAImpl_mul_u64_intel;
1560	FNIEMAIMPLMULDIVU64 iemAImpl_imul_u64, iemAImpl_imul_u64_amd, iemAImpl_imul_u64_intel;
1561	FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_div_u64_amd, iemAImpl_div_u64_intel;
1562	FNIEMAIMPLMULDIVU64 iemAImpl_idiv_u64, iemAImpl_idiv_u64_amd, iemAImpl_idiv_u64_intel;
1563	/** @} */
1564
1565	/** @name Byte Swap.
1566	* @{ */
1567	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t pu32Dst)); / Yes, 32-bit register access. */
1568	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
1569	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
1570	/** @} */
1571
1572	/** @name Misc.
1573	* @{ */
1574	FNIEMAIMPLBINU16 iemAImpl_arpl;
1575	/** @} */
1576
1577
1578	/** @name FPU operations taking a 32-bit float argument
1579	* @{ */
1580	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1581	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1582	typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
1583
1584	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1585	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1586	typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
1587
1588	FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
1589	FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
1590	FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
1591	FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
1592	FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
1593	FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
1594	FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
1595
1596	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
1597	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1598	PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
1599	/** @} */
1600
1601	/** @name FPU operations taking a 64-bit float argument
1602	* @{ */
1603	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1604	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1605	typedef FNIEMAIMPLFPUR64FSW *PFNIEMAIMPLFPUR64FSW;
1606
1607	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1608	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1609	typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
1610
1611	FNIEMAIMPLFPUR64FSW iemAImpl_fcom_r80_by_r64;
1612	FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
1613	FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
1614	FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
1615	FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
1616	FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
1617	FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
1618
1619	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
1620	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1621	PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
1622	/** @} */
1623
1624	/** @name FPU operations taking a 80-bit float argument
1625	* @{ */
1626	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1627	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1628	typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
1629	FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
1630	FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
1631	FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
1632	FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
1633	FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
1634	FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
1635	FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
1636	FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
1637	FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
1638
1639	FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80, iemAImpl_fpatan_r80_by_r80_amd, iemAImpl_fpatan_r80_by_r80_intel;
1640	FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80, iemAImpl_fyl2x_r80_by_r80_amd, iemAImpl_fyl2x_r80_by_r80_intel;
1641	FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80, iemAImpl_fyl2xp1_r80_by_r80_amd, iemAImpl_fyl2xp1_r80_by_r80_intel;
1642
1643	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1644	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1645	typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
1646	FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
1647	FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
1648
1649	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1650	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1651	typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
1652	FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
1653	FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
1654
1655	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
1656	typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
1657	FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
1658	FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
1659	FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80, iemAImpl_f2xm1_r80_amd, iemAImpl_f2xm1_r80_intel;
1660	FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
1661	FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
1662	FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80, iemAImpl_fsin_r80_amd, iemAImpl_fsin_r80_intel;
1663	FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80, iemAImpl_fcos_r80_amd, iemAImpl_fcos_r80_intel;
1664
1665	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
1666	typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
1667	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
1668	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
1669
1670	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
1671	typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
1672	FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
1673	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
1674	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
1675	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
1676	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
1677	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
1678	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
1679
1680	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
1681	PCRTFLOAT80U pr80Val));
1682	typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
1683	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80, iemAImpl_fptan_r80_r80_amd, iemAImpl_fptan_r80_r80_intel;
1684	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
1685	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80, iemAImpl_fsincos_r80_r80_amd, iemAImpl_fsincos_r80_r80_intel;
1686
1687	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
1688	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1689	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
1690
1691	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_d80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTPBCD80U pd80Val));
1692	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_d80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1693	PRTPBCD80U pd80Dst, PCRTFLOAT80U pr80Src));
1694
1695	/** @} */
1696
1697	/** @name FPU operations taking a 16-bit signed integer argument
1698	* @{ */
1699	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1700	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
1701	typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
1702	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI16,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
1703	int16_t *pi16Dst, PCRTFLOAT80U pr80Src));
1704	typedef FNIEMAIMPLFPUSTR80TOI16 *PFNIEMAIMPLFPUSTR80TOI16;
1705
1706	FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
1707	FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
1708	FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
1709	FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
1710	FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
1711	FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
1712
1713	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1714	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
1715	typedef FNIEMAIMPLFPUI16FSW *PFNIEMAIMPLFPUI16FSW;
1716	FNIEMAIMPLFPUI16FSW iemAImpl_ficom_r80_by_i16;
1717
1718	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
1719	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fist_r80_to_i16;
1720	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fistt_r80_to_i16, iemAImpl_fistt_r80_to_i16_amd, iemAImpl_fistt_r80_to_i16_intel;
1721	/** @} */
1722
1723	/** @name FPU operations taking a 32-bit signed integer argument
1724	* @{ */
1725	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1726	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
1727	typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
1728	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI32,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
1729	int32_t *pi32Dst, PCRTFLOAT80U pr80Src));
1730	typedef FNIEMAIMPLFPUSTR80TOI32 *PFNIEMAIMPLFPUSTR80TOI32;
1731
1732	FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
1733	FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
1734	FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
1735	FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
1736	FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
1737	FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
1738
1739	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1740	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
1741	typedef FNIEMAIMPLFPUI32FSW *PFNIEMAIMPLFPUI32FSW;
1742	FNIEMAIMPLFPUI32FSW iemAImpl_ficom_r80_by_i32;
1743
1744	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
1745	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fist_r80_to_i32;
1746	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fistt_r80_to_i32;
1747	/** @} */
1748
1749	/** @name FPU operations taking a 64-bit signed integer argument
1750	* @{ */
1751	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI64,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
1752	int64_t *pi64Dst, PCRTFLOAT80U pr80Src));
1753	typedef FNIEMAIMPLFPUSTR80TOI64 *PFNIEMAIMPLFPUSTR80TOI64;
1754
1755	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
1756	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fist_r80_to_i64;
1757	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fistt_r80_to_i64;
1758	/** @} */
1759
1760
1761	/** Temporary type representing a 256-bit vector register. */
1762	typedef struct { uint64_t au64[4]; } IEMVMM256;
1763	/** Temporary type pointing to a 256-bit vector register. */
1764	typedef IEMVMM256 *PIEMVMM256;
1765	/** Temporary type pointing to a const 256-bit vector register. */
1766	typedef IEMVMM256 *PCIEMVMM256;
1767
1768
1769	/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
1770	* @{ */
1771	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t puDst, uint64_t const puSrc));
1772	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
1773	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U128,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
1774	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
1775	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U128,(PX86XSAVEAREA pExtState, PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
1776	typedef FNIEMAIMPLMEDIAF3U128 *PFNIEMAIMPLMEDIAF3U128;
1777	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U256,(PX86XSAVEAREA pExtState, PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
1778	typedef FNIEMAIMPLMEDIAF3U256 *PFNIEMAIMPLMEDIAF3U256;
1779	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U64,(uint64_t puDst, uint64_t const puSrc));
1780	typedef FNIEMAIMPLMEDIAOPTF2U64 *PFNIEMAIMPLMEDIAOPTF2U64;
1781	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128,(PRTUINT128U puDst, PCRTUINT128U puSrc));
1782	typedef FNIEMAIMPLMEDIAOPTF2U128 *PFNIEMAIMPLMEDIAOPTF2U128;
1783	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
1784	typedef FNIEMAIMPLMEDIAOPTF3U128 *PFNIEMAIMPLMEDIAOPTF3U128;
1785	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
1786	typedef FNIEMAIMPLMEDIAOPTF3U256 *PFNIEMAIMPLMEDIAOPTF3U256;
1787	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256,(PRTUINT256U puDst, PCRTUINT256U puSrc));
1788	typedef FNIEMAIMPLMEDIAOPTF2U256 *PFNIEMAIMPLMEDIAOPTF2U256;
1789	FNIEMAIMPLMEDIAF2U64 iemAImpl_pshufb_u64, iemAImpl_pshufb_u64_fallback;
1790	FNIEMAIMPLMEDIAF2U64 iemAImpl_pand_u64, iemAImpl_pandn_u64, iemAImpl_por_u64, iemAImpl_pxor_u64;
1791	FNIEMAIMPLMEDIAF2U64 iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
1792	FNIEMAIMPLMEDIAF2U64 iemAImpl_pcmpgtb_u64, iemAImpl_pcmpgtw_u64, iemAImpl_pcmpgtd_u64;
1793	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddb_u64, iemAImpl_paddsb_u64, iemAImpl_paddusb_u64;
1794	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddw_u64, iemAImpl_paddsw_u64, iemAImpl_paddusw_u64;
1795	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddd_u64;
1796	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddq_u64;
1797	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubb_u64, iemAImpl_psubsb_u64, iemAImpl_psubusb_u64;
1798	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubw_u64, iemAImpl_psubsw_u64, iemAImpl_psubusw_u64;
1799	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubd_u64;
1800	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubq_u64;
1801	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmaddwd_u64;
1802	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmullw_u64, iemAImpl_pmulhw_u64;
1803	FNIEMAIMPLMEDIAF2U64 iemAImpl_pminub_u64, iemAImpl_pmaxub_u64;
1804	FNIEMAIMPLMEDIAF2U64 iemAImpl_pminsw_u64, iemAImpl_pmaxsw_u64;
1805	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsb_u64, iemAImpl_pabsb_u64_fallback;
1806	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsw_u64, iemAImpl_pabsw_u64_fallback;
1807	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsd_u64, iemAImpl_pabsd_u64_fallback;
1808	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignb_u64, iemAImpl_psignb_u64_fallback;
1809	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignw_u64, iemAImpl_psignw_u64_fallback;
1810	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignd_u64, iemAImpl_psignd_u64_fallback;
1811	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddw_u64, iemAImpl_phaddw_u64_fallback;
1812	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddd_u64, iemAImpl_phaddd_u64_fallback;
1813	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubw_u64, iemAImpl_phsubw_u64_fallback;
1814	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubd_u64, iemAImpl_phsubd_u64_fallback;
1815	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddsw_u64, iemAImpl_phaddsw_u64_fallback;
1816	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubsw_u64, iemAImpl_phsubsw_u64_fallback;
1817	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmaddubsw_u64, iemAImpl_pmaddubsw_u64_fallback;
1818	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmulhrsw_u64, iemAImpl_pmulhrsw_u64_fallback;
1819	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmuludq_u64;
1820	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllw_u64, iemAImpl_psrlw_u64, iemAImpl_psraw_u64;
1821	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pslld_u64, iemAImpl_psrld_u64, iemAImpl_psrad_u64;
1822	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllq_u64, iemAImpl_psrlq_u64;
1823	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packsswb_u64, iemAImpl_packuswb_u64;
1824	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packssdw_u64;
1825	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhuw_u64;
1826	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pavgb_u64, iemAImpl_pavgw_u64;
1827	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psadbw_u64;
1828
1829	FNIEMAIMPLMEDIAF2U128 iemAImpl_pshufb_u128, iemAImpl_pshufb_u128_fallback;
1830	FNIEMAIMPLMEDIAF2U128 iemAImpl_pand_u128, iemAImpl_pandn_u128, iemAImpl_por_u128, iemAImpl_pxor_u128;
1831	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
1832	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpeqq_u128, iemAImpl_pcmpeqq_u128_fallback;
1833	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpgtb_u128, iemAImpl_pcmpgtw_u128, iemAImpl_pcmpgtd_u128;
1834	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpgtq_u128, iemAImpl_pcmpgtq_u128_fallback;
1835	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddb_u128, iemAImpl_paddsb_u128, iemAImpl_paddusb_u128;
1836	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddw_u128, iemAImpl_paddsw_u128, iemAImpl_paddusw_u128;
1837	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddd_u128;
1838	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddq_u128;
1839	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubb_u128, iemAImpl_psubsb_u128, iemAImpl_psubusb_u128;
1840	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubw_u128, iemAImpl_psubsw_u128, iemAImpl_psubusw_u128;
1841	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubd_u128;
1842	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubq_u128;
1843	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmullw_u128, iemAImpl_pmullw_u128_fallback;
1844	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulhw_u128;
1845	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulld_u128, iemAImpl_pmulld_u128_fallback;
1846	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaddwd_u128;
1847	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminub_u128;
1848	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminud_u128, iemAImpl_pminud_u128_fallback;
1849	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminuw_u128, iemAImpl_pminuw_u128_fallback;
1850	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsb_u128, iemAImpl_pminsb_u128_fallback;
1851	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsd_u128, iemAImpl_pminsd_u128_fallback;
1852	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsw_u128, iemAImpl_pminsw_u128_fallback;
1853	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxub_u128;
1854	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxud_u128, iemAImpl_pmaxud_u128_fallback;
1855	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxuw_u128, iemAImpl_pmaxuw_u128_fallback;
1856	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsb_u128, iemAImpl_pmaxsb_u128_fallback;
1857	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsw_u128;
1858	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsd_u128, iemAImpl_pmaxsd_u128_fallback;
1859	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsb_u128, iemAImpl_pabsb_u128_fallback;
1860	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsw_u128, iemAImpl_pabsw_u128_fallback;
1861	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsd_u128, iemAImpl_pabsd_u128_fallback;
1862	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignb_u128, iemAImpl_psignb_u128_fallback;
1863	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignw_u128, iemAImpl_psignw_u128_fallback;
1864	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignd_u128, iemAImpl_psignd_u128_fallback;
1865	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddw_u128, iemAImpl_phaddw_u128_fallback;
1866	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddd_u128, iemAImpl_phaddd_u128_fallback;
1867	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubw_u128, iemAImpl_phsubw_u128_fallback;
1868	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubd_u128, iemAImpl_phsubd_u128_fallback;
1869	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddsw_u128, iemAImpl_phaddsw_u128_fallback;
1870	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubsw_u128, iemAImpl_phsubsw_u128_fallback;
1871	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaddubsw_u128, iemAImpl_pmaddubsw_u128_fallback;
1872	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulhrsw_u128, iemAImpl_pmulhrsw_u128_fallback;
1873	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmuludq_u128;
1874	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packsswb_u128, iemAImpl_packuswb_u128;
1875	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packssdw_u128, iemAImpl_packusdw_u128;
1876	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllw_u128, iemAImpl_psrlw_u128, iemAImpl_psraw_u128;
1877	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pslld_u128, iemAImpl_psrld_u128, iemAImpl_psrad_u128;
1878	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllq_u128, iemAImpl_psrlq_u128;
1879	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhuw_u128;
1880	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pavgb_u128, iemAImpl_pavgw_u128;
1881	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psadbw_u128;
1882	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuldq_u128, iemAImpl_pmuldq_u128_fallback;
1883	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpcklps_u128, iemAImpl_unpcklpd_u128;
1884	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpckhps_u128, iemAImpl_unpckhpd_u128;
1885	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phminposuw_u128, iemAImpl_phminposuw_u128_fallback;
1886
1887	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpshufb_u128, iemAImpl_vpshufb_u128_fallback;
1888	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpand_u128, iemAImpl_vpand_u128_fallback;
1889	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpandn_u128, iemAImpl_vpandn_u128_fallback;
1890	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpor_u128, iemAImpl_vpor_u128_fallback;
1891	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpxor_u128, iemAImpl_vpxor_u128_fallback;
1892	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqb_u128, iemAImpl_vpcmpeqb_u128_fallback;
1893	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqw_u128, iemAImpl_vpcmpeqw_u128_fallback;
1894	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqd_u128, iemAImpl_vpcmpeqd_u128_fallback;
1895	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqq_u128, iemAImpl_vpcmpeqq_u128_fallback;
1896	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtb_u128, iemAImpl_vpcmpgtb_u128_fallback;
1897	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtw_u128, iemAImpl_vpcmpgtw_u128_fallback;
1898	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtd_u128, iemAImpl_vpcmpgtd_u128_fallback;
1899	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtq_u128, iemAImpl_vpcmpgtq_u128_fallback;
1900	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddb_u128, iemAImpl_vpaddb_u128_fallback;
1901	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddw_u128, iemAImpl_vpaddw_u128_fallback;
1902	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddd_u128, iemAImpl_vpaddd_u128_fallback;
1903	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddq_u128, iemAImpl_vpaddq_u128_fallback;
1904	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubb_u128, iemAImpl_vpsubb_u128_fallback;
1905	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubw_u128, iemAImpl_vpsubw_u128_fallback;
1906	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubd_u128, iemAImpl_vpsubd_u128_fallback;
1907	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubq_u128, iemAImpl_vpsubq_u128_fallback;
1908	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminub_u128, iemAImpl_vpminub_u128_fallback;
1909	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminuw_u128, iemAImpl_vpminuw_u128_fallback;
1910	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminud_u128, iemAImpl_vpminud_u128_fallback;
1911	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsb_u128, iemAImpl_vpminsb_u128_fallback;
1912	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsw_u128, iemAImpl_vpminsw_u128_fallback;
1913	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsd_u128, iemAImpl_vpminsd_u128_fallback;
1914	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxub_u128, iemAImpl_vpmaxub_u128_fallback;
1915	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxuw_u128, iemAImpl_vpmaxuw_u128_fallback;
1916	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxud_u128, iemAImpl_vpmaxud_u128_fallback;
1917	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsb_u128, iemAImpl_vpmaxsb_u128_fallback;
1918	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsw_u128, iemAImpl_vpmaxsw_u128_fallback;
1919	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsd_u128, iemAImpl_vpmaxsd_u128_fallback;
1920	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpacksswb_u128, iemAImpl_vpacksswb_u128_fallback;
1921	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackssdw_u128, iemAImpl_vpackssdw_u128_fallback;
1922	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackuswb_u128, iemAImpl_vpackuswb_u128_fallback;
1923	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackusdw_u128, iemAImpl_vpackusdw_u128_fallback;
1924	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmullw_u128, iemAImpl_vpmullw_u128_fallback;
1925	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulld_u128, iemAImpl_vpmulld_u128_fallback;
1926	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhw_u128, iemAImpl_vpmulhw_u128_fallback;
1927	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhuw_u128, iemAImpl_vpmulhuw_u128_fallback;
1928	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgb_u128, iemAImpl_vpavgb_u128_fallback;
1929	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgw_u128, iemAImpl_vpavgw_u128_fallback;
1930	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignb_u128, iemAImpl_vpsignb_u128_fallback;
1931	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignw_u128, iemAImpl_vpsignw_u128_fallback;
1932	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignd_u128, iemAImpl_vpsignd_u128_fallback;
1933	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddw_u128, iemAImpl_vphaddw_u128_fallback;
1934	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddd_u128, iemAImpl_vphaddd_u128_fallback;
1935	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubw_u128, iemAImpl_vphsubw_u128_fallback;
1936	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubd_u128, iemAImpl_vphsubd_u128_fallback;
1937	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddsw_u128, iemAImpl_vphaddsw_u128_fallback;
1938	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubsw_u128, iemAImpl_vphsubsw_u128_fallback;
1939	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddubsw_u128, iemAImpl_vpmaddubsw_u128_fallback;
1940	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhrsw_u128, iemAImpl_vpmulhrsw_u128_fallback;
1941	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsadbw_u128, iemAImpl_vpsadbw_u128_fallback;
1942	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuldq_u128, iemAImpl_vpmuldq_u128_fallback;
1943	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuludq_u128, iemAImpl_vpmuludq_u128_fallback;
1944
1945	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsb_u128, iemAImpl_vpabsb_u128_fallback;
1946	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsw_u128, iemAImpl_vpabsd_u128_fallback;
1947	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsd_u128, iemAImpl_vpabsw_u128_fallback;
1948	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vphminposuw_u128, iemAImpl_vphminposuw_u128_fallback;
1949
1950	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpshufb_u256, iemAImpl_vpshufb_u256_fallback;
1951	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpand_u256, iemAImpl_vpand_u256_fallback;
1952	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpandn_u256, iemAImpl_vpandn_u256_fallback;
1953	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpor_u256, iemAImpl_vpor_u256_fallback;
1954	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpxor_u256, iemAImpl_vpxor_u256_fallback;
1955	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqb_u256, iemAImpl_vpcmpeqb_u256_fallback;
1956	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqw_u256, iemAImpl_vpcmpeqw_u256_fallback;
1957	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqd_u256, iemAImpl_vpcmpeqd_u256_fallback;
1958	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqq_u256, iemAImpl_vpcmpeqq_u256_fallback;
1959	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtb_u256, iemAImpl_vpcmpgtb_u256_fallback;
1960	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtw_u256, iemAImpl_vpcmpgtw_u256_fallback;
1961	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtd_u256, iemAImpl_vpcmpgtd_u256_fallback;
1962	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtq_u256, iemAImpl_vpcmpgtq_u256_fallback;
1963	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddb_u256, iemAImpl_vpaddb_u256_fallback;
1964	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddw_u256, iemAImpl_vpaddw_u256_fallback;
1965	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddd_u256, iemAImpl_vpaddd_u256_fallback;
1966	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddq_u256, iemAImpl_vpaddq_u256_fallback;
1967	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubb_u256, iemAImpl_vpsubb_u256_fallback;
1968	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubw_u256, iemAImpl_vpsubw_u256_fallback;
1969	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubd_u256, iemAImpl_vpsubd_u256_fallback;
1970	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubq_u256, iemAImpl_vpsubq_u256_fallback;
1971	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminub_u256, iemAImpl_vpminub_u256_fallback;
1972	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminuw_u256, iemAImpl_vpminuw_u256_fallback;
1973	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminud_u256, iemAImpl_vpminud_u256_fallback;
1974	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsb_u256, iemAImpl_vpminsb_u256_fallback;
1975	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsw_u256, iemAImpl_vpminsw_u256_fallback;
1976	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsd_u256, iemAImpl_vpminsd_u256_fallback;
1977	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxub_u256, iemAImpl_vpmaxub_u256_fallback;
1978	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxuw_u256, iemAImpl_vpmaxuw_u256_fallback;
1979	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxud_u256, iemAImpl_vpmaxud_u256_fallback;
1980	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsb_u256, iemAImpl_vpmaxsb_u256_fallback;
1981	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsw_u256, iemAImpl_vpmaxsw_u256_fallback;
1982	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsd_u256, iemAImpl_vpmaxsd_u256_fallback;
1983	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpacksswb_u256, iemAImpl_vpacksswb_u256_fallback;
1984	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackssdw_u256, iemAImpl_vpackssdw_u256_fallback;
1985	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackuswb_u256, iemAImpl_vpackuswb_u256_fallback;
1986	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackusdw_u256, iemAImpl_vpackusdw_u256_fallback;
1987	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmullw_u256, iemAImpl_vpmullw_u256_fallback;
1988	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulld_u256, iemAImpl_vpmulld_u256_fallback;
1989	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhw_u256, iemAImpl_vpmulhw_u256_fallback;
1990	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhuw_u256, iemAImpl_vpmulhuw_u256_fallback;
1991	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgb_u256, iemAImpl_vpavgb_u256_fallback;
1992	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgw_u256, iemAImpl_vpavgw_u256_fallback;
1993	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignb_u256, iemAImpl_vpsignb_u256_fallback;
1994	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignw_u256, iemAImpl_vpsignw_u256_fallback;
1995	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignd_u256, iemAImpl_vpsignd_u256_fallback;
1996	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddw_u256, iemAImpl_vphaddw_u256_fallback;
1997	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddd_u256, iemAImpl_vphaddd_u256_fallback;
1998	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubw_u256, iemAImpl_vphsubw_u256_fallback;
1999	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubd_u256, iemAImpl_vphsubd_u256_fallback;
2000	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddsw_u256, iemAImpl_vphaddsw_u256_fallback;
2001	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubsw_u256, iemAImpl_vphsubsw_u256_fallback;
2002	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddubsw_u256, iemAImpl_vpmaddubsw_u256_fallback;
2003	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhrsw_u256, iemAImpl_vpmulhrsw_u256_fallback;
2004	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsadbw_u256, iemAImpl_vpsadbw_u256_fallback;
2005	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuldq_u256, iemAImpl_vpmuldq_u256_fallback;
2006	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuludq_u256, iemAImpl_vpmuludq_u256_fallback;
2007
2008	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsb_u256, iemAImpl_vpabsb_u256_fallback;
2009	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsw_u256, iemAImpl_vpabsw_u256_fallback;
2010	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsd_u256, iemAImpl_vpabsd_u256_fallback;
2011	/** @} */
2012
2013	/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
2014	* @{ */
2015	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
2016	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
2017	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpcklbw_u128, iemAImpl_vpunpcklbw_u128_fallback,
2018	iemAImpl_vpunpcklwd_u128, iemAImpl_vpunpcklwd_u128_fallback,
2019	iemAImpl_vpunpckldq_u128, iemAImpl_vpunpckldq_u128_fallback,
2020	iemAImpl_vpunpcklqdq_u128, iemAImpl_vpunpcklqdq_u128_fallback,
2021	iemAImpl_vunpcklps_u128, iemAImpl_vunpcklps_u128_fallback,
2022	iemAImpl_vunpcklpd_u128, iemAImpl_vunpcklpd_u128_fallback,
2023	iemAImpl_vunpckhps_u128, iemAImpl_vunpckhps_u128_fallback,
2024	iemAImpl_vunpckhpd_u128, iemAImpl_vunpckhpd_u128_fallback;
2025
2026	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpcklbw_u256, iemAImpl_vpunpcklbw_u256_fallback,
2027	iemAImpl_vpunpcklwd_u256, iemAImpl_vpunpcklwd_u256_fallback,
2028	iemAImpl_vpunpckldq_u256, iemAImpl_vpunpckldq_u256_fallback,
2029	iemAImpl_vpunpcklqdq_u256, iemAImpl_vpunpcklqdq_u256_fallback,
2030	iemAImpl_vunpcklps_u256, iemAImpl_vunpcklps_u256_fallback,
2031	iemAImpl_vunpcklpd_u256, iemAImpl_vunpcklpd_u256_fallback,
2032	iemAImpl_vunpckhps_u256, iemAImpl_vunpckhps_u256_fallback,
2033	iemAImpl_vunpckhpd_u256, iemAImpl_vunpckhpd_u256_fallback;
2034	/** @} */
2035
2036	/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
2037	* @{ */
2038	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
2039	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
2040	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpckhbw_u128, iemAImpl_vpunpckhbw_u128_fallback,
2041	iemAImpl_vpunpckhwd_u128, iemAImpl_vpunpckhwd_u128_fallback,
2042	iemAImpl_vpunpckhdq_u128, iemAImpl_vpunpckhdq_u128_fallback,
2043	iemAImpl_vpunpckhqdq_u128, iemAImpl_vpunpckhqdq_u128_fallback;
2044	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpckhbw_u256, iemAImpl_vpunpckhbw_u256_fallback,
2045	iemAImpl_vpunpckhwd_u256, iemAImpl_vpunpckhwd_u256_fallback,
2046	iemAImpl_vpunpckhdq_u256, iemAImpl_vpunpckhdq_u256_fallback,
2047	iemAImpl_vpunpckhqdq_u256, iemAImpl_vpunpckhqdq_u256_fallback;
2048	/** @} */
2049
2050	/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
2051	* @{ */
2052	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2053	typedef FNIEMAIMPLMEDIAPSHUFU128 *PFNIEMAIMPLMEDIAPSHUFU128;
2054	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
2055	typedef FNIEMAIMPLMEDIAPSHUFU256 *PFNIEMAIMPLMEDIAPSHUFU256;
2056	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw_u64,(uint64_t puDst, uint64_t const puSrc, uint8_t bEvil));
2057	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_pshufhw_u128, iemAImpl_pshuflw_u128, iemAImpl_pshufd_u128;
2058	#ifndef IEM_WITHOUT_ASSEMBLY
2059	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256, iemAImpl_vpshuflw_u256, iemAImpl_vpshufd_u256;
2060	#endif
2061	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256_fallback, iemAImpl_vpshuflw_u256_fallback, iemAImpl_vpshufd_u256_fallback;
2062	/** @} */
2063
2064	/** @name Media (SSE/MMX/AVX) operation: Shift Immediate Stuff (evil)
2065	* @{ */
2066	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU64,(uint64_t *puDst, uint8_t bShift));
2067	typedef FNIEMAIMPLMEDIAPSHIFTU64 *PFNIEMAIMPLMEDIAPSHIFTU64;
2068	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU128,(PRTUINT128U puDst, uint8_t bShift));
2069	typedef FNIEMAIMPLMEDIAPSHIFTU128 *PFNIEMAIMPLMEDIAPSHIFTU128;
2070	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU256,(PRTUINT256U puDst, uint8_t bShift));
2071	typedef FNIEMAIMPLMEDIAPSHIFTU256 *PFNIEMAIMPLMEDIAPSHIFTU256;
2072	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psllw_imm_u64, iemAImpl_pslld_imm_u64, iemAImpl_psllq_imm_u64;
2073	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psrlw_imm_u64, iemAImpl_psrld_imm_u64, iemAImpl_psrlq_imm_u64;
2074	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psraw_imm_u64, iemAImpl_psrad_imm_u64;
2075	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psllw_imm_u128, iemAImpl_pslld_imm_u128, iemAImpl_psllq_imm_u128;
2076	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psrlw_imm_u128, iemAImpl_psrld_imm_u128, iemAImpl_psrlq_imm_u128;
2077	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psraw_imm_u128, iemAImpl_psrad_imm_u128;
2078	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_pslldq_imm_u128, iemAImpl_psrldq_imm_u128;
2079	/** @} */
2080
2081	/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
2082	* @{ */
2083	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(uint64_t pu64Dst, uint64_t const puSrc));
2084	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(uint64_t *pu64Dst, PCRTUINT128U puSrc));
2085	#ifndef IEM_WITHOUT_ASSEMBLY
2086	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
2087	#endif
2088	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256_fallback,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
2089	/** @} */
2090
2091	/** @name Media (SSE/MMX/AVX) operations: Variable Blend Packed Bytes/R32/R64.
2092	* @{ */
2093	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puMask));
2094	typedef FNIEMAIMPLBLENDU128 *PFNIEMAIMPLBLENDU128;
2095	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, PCRTUINT128U puMask));
2096	typedef FNIEMAIMPLAVXBLENDU128 *PFNIEMAIMPLAVXBLENDU128;
2097	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, PCRTUINT256U puMask));
2098	typedef FNIEMAIMPLAVXBLENDU256 *PFNIEMAIMPLAVXBLENDU256;
2099
2100	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128;
2101	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128_fallback;
2102	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128;
2103	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128_fallback;
2104	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256;
2105	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256_fallback;
2106
2107	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128;
2108	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128_fallback;
2109	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128;
2110	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128_fallback;
2111	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256;
2112	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256_fallback;
2113
2114	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128;
2115	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128_fallback;
2116	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128;
2117	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128_fallback;
2118	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256;
2119	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256_fallback;
2120	/** @} */
2121
2122
2123	/** @name Media (SSE/MMX/AVX) operation: Sort this later
2124	* @{ */
2125	IEM_DECL_IMPL_DEF(void, iemAImpl_movsldup,(PRTUINT128U puDst, PCRTUINT128U puSrc));
2126	IEM_DECL_IMPL_DEF(void, iemAImpl_movshdup,(PRTUINT128U puDst, PCRTUINT128U puSrc));
2127	IEM_DECL_IMPL_DEF(void, iemAImpl_movddup,(PRTUINT128U puDst, uint64_t uSrc));
2128
2129	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
2130	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
2131	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovshdup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
2132	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovshdup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
2133	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
2134	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
2135
2136	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2137	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2138	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2139	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2140	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2141
2142	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2143	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2144	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2145	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2146	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2147
2148	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2149	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2150	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
2151	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2152	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2153
2154	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2155	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2156	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2157	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2158	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2159
2160	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2161	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2162	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2163	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2164	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2165
2166	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2167	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2168	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2169	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2170	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2171
2172	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2173	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2174	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2175	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2176	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2177
2178	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2179	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2180	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2181	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2182	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2183
2184	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2185	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2186	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
2187	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2188	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2189
2190	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2191	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2192	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2193	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2194	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2195
2196	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2197	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2198	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2199	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2200	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2201
2202	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2203	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2204	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2205	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2206	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2207
2208	IEM_DECL_IMPL_DEF(void, iemAImpl_shufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2209	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2210	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2211	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2212	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2213
2214	IEM_DECL_IMPL_DEF(void, iemAImpl_shufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2215	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2216	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2217	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2218	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2219
2220	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
2221	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64_fallback,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
2222
2223	IEM_DECL_IMPL_DEF(void, iemAImpl_pinsrw_u64,(uint64_t *pu64Dst, uint16_t u16Src, uint8_t bEvil));
2224	IEM_DECL_IMPL_DEF(void, iemAImpl_pinsrw_u128,(PRTUINT128U puDst, uint16_t u16Src, uint8_t bEvil));
2225	IEM_DECL_IMPL_DEF(void, iemAImpl_vpinsrw_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint16_t u16Src, uint8_t bEvil));
2226	IEM_DECL_IMPL_DEF(void, iemAImpl_vpinsrw_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint16_t u16Src, uint8_t bEvil));
2227
2228	IEM_DECL_IMPL_DEF(void, iemAImpl_pextrw_u64,(uint16_t *pu16Dst, uint64_t u64Src, uint8_t bEvil));
2229	IEM_DECL_IMPL_DEF(void, iemAImpl_pextrw_u128,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
2230	IEM_DECL_IMPL_DEF(void, iemAImpl_vpextrw_u128,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
2231	IEM_DECL_IMPL_DEF(void, iemAImpl_vpextrw_u128_fallback,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
2232
2233	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2234	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2235	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2236	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
2237	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
2238
2239	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2240	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2241	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2242	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
2243	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
2244
2245
2246	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2247	typedef FNIEMAIMPLMEDIAOPTF2U128IMM8 *PFNIEMAIMPLMEDIAOPTF2U128IMM8;
2248	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2249	typedef FNIEMAIMPLMEDIAOPTF3U128IMM8 *PFNIEMAIMPLMEDIAOPTF3U128IMM8;
2250	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2251	typedef FNIEMAIMPLMEDIAOPTF3U256IMM8 *PFNIEMAIMPLMEDIAOPTF3U256IMM8;
2252
2253	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_palignr_u128, iemAImpl_palignr_u128_fallback;
2254	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pblendw_u128, iemAImpl_pblendw_u128_fallback;
2255	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendps_u128, iemAImpl_blendps_u128_fallback;
2256	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendpd_u128, iemAImpl_blendpd_u128_fallback;
2257
2258	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpalignr_u128, iemAImpl_vpalignr_u128_fallback;
2259	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendw_u128, iemAImpl_vpblendw_u128_fallback;
2260	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendps_u128, iemAImpl_vblendps_u128_fallback;
2261	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendpd_u128, iemAImpl_vblendpd_u128_fallback;
2262
2263	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpalignr_u256, iemAImpl_vpalignr_u256_fallback;
2264	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendw_u256, iemAImpl_vpblendw_u256_fallback;
2265	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendps_u256, iemAImpl_vblendps_u256_fallback;
2266	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendpd_u256, iemAImpl_vblendpd_u256_fallback;
2267
2268
2269	typedef struct IEMPCMPISTRISRC
2270	{
2271	RTUINT128U uSrc1;
2272	RTUINT128U uSrc2;
2273	} IEMPCMPISTRISRC;
2274	typedef IEMPCMPISTRISRC *PIEMPCMPISTRISRC;
2275	typedef const IEMPCMPISTRISRC *PCIEMPCMPISTRISRC;
2276
2277	IEM_DECL_IMPL_DEF(void, iemAImpl_pcmpistri_u128,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPISTRISRC pSrc, uint8_t bEvil));
2278	IEM_DECL_IMPL_DEF(void, iemAImpl_pcmpistri_u128_fallback,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPISTRISRC pSrc, uint8_t bEvil));
2279
2280	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pclmulqdq_u128, iemAImpl_pclmulqdq_u128_fallback;
2281	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpclmulqdq_u128, iemAImpl_vpclmulqdq_u128_fallback;
2282	/** @} */
2283
2284	/** @name Media Odds and Ends
2285	* @{ */
2286	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U8,(uint32_t *puDst, uint8_t uSrc));
2287	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U16,(uint32_t *puDst, uint16_t uSrc));
2288	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U32,(uint32_t *puDst, uint32_t uSrc));
2289	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U64,(uint32_t *puDst, uint64_t uSrc));
2290	FNIEMAIMPLCR32U8 iemAImpl_crc32_u8, iemAImpl_crc32_u8_fallback;
2291	FNIEMAIMPLCR32U16 iemAImpl_crc32_u16, iemAImpl_crc32_u16_fallback;
2292	FNIEMAIMPLCR32U32 iemAImpl_crc32_u32, iemAImpl_crc32_u32_fallback;
2293	FNIEMAIMPLCR32U64 iemAImpl_crc32_u64, iemAImpl_crc32_u64_fallback;
2294
2295	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL128,(PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint32_t *pEFlags));
2296	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL256,(PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint32_t *pEFlags));
2297	FNIEMAIMPLF2EFL128 iemAImpl_ptest_u128;
2298	FNIEMAIMPLF2EFL256 iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback;
2299
2300	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I32U64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int32_t pi32Dst, const uint64_t pu64Src)); / pu64Src is a double precision floating point. */
2301	typedef FNIEMAIMPLSSEF2I32U64 *PFNIEMAIMPLSSEF2I32U64;
2302	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I64U64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int64_t pi64Dst, const uint64_t pu64Src)); / pu64Src is a double precision floating point. */
2303	typedef FNIEMAIMPLSSEF2I64U64 *PFNIEMAIMPLSSEF2I64U64;
2304	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I32U32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int32_t pi32Dst, const uint32_t pu32Src)); / pu32Src is a single precision floating point. */
2305	typedef FNIEMAIMPLSSEF2I32U32 *PFNIEMAIMPLSSEF2I32U32;
2306	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I64U32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int64_t pi64Dst, const uint32_t pu32Src)); / pu32Src is a single precision floating point. */
2307	typedef FNIEMAIMPLSSEF2I64U32 *PFNIEMAIMPLSSEF2I64U32;
2308
2309	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvttsd2si_i32_r64;
2310	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvtsd2si_i32_r64;
2311
2312	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvttsd2si_i64_r64;
2313	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvtsd2si_i64_r64;
2314
2315	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvttss2si_i32_r32;
2316	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvtss2si_i32_r32;
2317
2318	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvttss2si_i64_r32;
2319	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvtss2si_i64_r32;
2320
2321	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R32I32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT32U pr32Dst, const int32_t pi32Src));
2322	typedef FNIEMAIMPLSSEF2R32I32 *PFNIEMAIMPLSSEF2R32I32;
2323	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R32I64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT32U pr32Dst, const int64_t pi64Src));
2324	typedef FNIEMAIMPLSSEF2R32I64 *PFNIEMAIMPLSSEF2R32I64;
2325
2326	FNIEMAIMPLSSEF2R32I32 iemAImpl_cvtsi2ss_r32_i32;
2327	FNIEMAIMPLSSEF2R32I64 iemAImpl_cvtsi2ss_r32_i64;
2328
2329	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R64I32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT64U pr64Dst, const int32_t pi32Src));
2330	typedef FNIEMAIMPLSSEF2R64I32 *PFNIEMAIMPLSSEF2R64I32;
2331	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R64I64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT64U pr64Dst, const int64_t pi64Src));
2332	typedef FNIEMAIMPLSSEF2R64I64 *PFNIEMAIMPLSSEF2R64I64;
2333
2334	FNIEMAIMPLSSEF2R64I32 iemAImpl_cvtsi2sd_r64_i32;
2335	FNIEMAIMPLSSEF2R64I64 iemAImpl_cvtsi2sd_r64_i64;
2336
2337
2338	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFLMXCSR128,(uint32_t pfMxcsr, uint32_t pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
2339	typedef FNIEMAIMPLF2EFLMXCSR128 *PFNIEMAIMPLF2EFLMXCSR128;
2340
2341	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_ucomiss_u128;
2342	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback;
2343
2344	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_ucomisd_u128;
2345	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback;
2346
2347	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_comiss_u128;
2348	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback;
2349
2350	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_comisd_u128;
2351	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback;
2352
2353
2354	typedef struct IEMMEDIAF2XMMSRC
2355	{
2356	X86XMMREG uSrc1;
2357	X86XMMREG uSrc2;
2358	} IEMMEDIAF2XMMSRC;
2359	typedef IEMMEDIAF2XMMSRC *PIEMMEDIAF2XMMSRC;
2360	typedef const IEMMEDIAF2XMMSRC *PCIEMMEDIAF2XMMSRC;
2361
2362	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRF2XMMIMM8,(uint32_t *pfMxcsr, PX86XMMREG puDst, PCIEMMEDIAF2XMMSRC puSrc, uint8_t bEvil));
2363	typedef FNIEMAIMPLMXCSRF2XMMIMM8 *PFNIEMAIMPLMXCSRF2XMMIMM8;
2364
2365	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpps_u128;
2366	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmppd_u128;
2367	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpss_u128;
2368	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpsd_u128;
2369
2370	/** @} */
2371
2372
2373	/** @name Function tables.
2374	* @{
2375	*/
2376
2377	/**
2378	* Function table for a binary operator providing implementation based on
2379	* operand size.
2380	*/
2381	typedef struct IEMOPBINSIZES
2382	{
2383	PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
2384	PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
2385	PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
2386	PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
2387	} IEMOPBINSIZES;
2388	/** Pointer to a binary operator function table. */
2389	typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
2390
2391
2392	/**
2393	* Function table for a unary operator providing implementation based on
2394	* operand size.
2395	*/
2396	typedef struct IEMOPUNARYSIZES
2397	{
2398	PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
2399	PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
2400	PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
2401	PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
2402	} IEMOPUNARYSIZES;
2403	/** Pointer to a unary operator function table. */
2404	typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
2405
2406
2407	/**
2408	* Function table for a shift operator providing implementation based on
2409	* operand size.
2410	*/
2411	typedef struct IEMOPSHIFTSIZES
2412	{
2413	PFNIEMAIMPLSHIFTU8 pfnNormalU8;
2414	PFNIEMAIMPLSHIFTU16 pfnNormalU16;
2415	PFNIEMAIMPLSHIFTU32 pfnNormalU32;
2416	PFNIEMAIMPLSHIFTU64 pfnNormalU64;
2417	} IEMOPSHIFTSIZES;
2418	/** Pointer to a shift operator function table. */
2419	typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
2420
2421
2422	/**
2423	* Function table for a multiplication or division operation.
2424	*/
2425	typedef struct IEMOPMULDIVSIZES
2426	{
2427	PFNIEMAIMPLMULDIVU8 pfnU8;
2428	PFNIEMAIMPLMULDIVU16 pfnU16;
2429	PFNIEMAIMPLMULDIVU32 pfnU32;
2430	PFNIEMAIMPLMULDIVU64 pfnU64;
2431	} IEMOPMULDIVSIZES;
2432	/** Pointer to a multiplication or division operation function table. */
2433	typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
2434
2435
2436	/**
2437	* Function table for a double precision shift operator providing implementation
2438	* based on operand size.
2439	*/
2440	typedef struct IEMOPSHIFTDBLSIZES
2441	{
2442	PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
2443	PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
2444	PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
2445	} IEMOPSHIFTDBLSIZES;
2446	/** Pointer to a double precision shift function table. */
2447	typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
2448
2449
2450	/**
2451	* Function table for media instruction taking two full sized media source
2452	* registers and one full sized destination register (AVX).
2453	*/
2454	typedef struct IEMOPMEDIAF3
2455	{
2456	PFNIEMAIMPLMEDIAF3U128 pfnU128;
2457	PFNIEMAIMPLMEDIAF3U256 pfnU256;
2458	} IEMOPMEDIAF3;
2459	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
2460	typedef IEMOPMEDIAF3 const *PCIEMOPMEDIAF3;
2461
2462	/** @def IEMOPMEDIAF3_INIT_VARS_EX
2463	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2464	* given functions as initializers. For use in AVX functions where a pair of
2465	* functions are only used once and the function table need not be public. */
2466	#ifndef TST_IEM_CHECK_MC
2467	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2468	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2469	static IEMOPMEDIAF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2470	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2471	# else
2472	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2473	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2474	# endif
2475	#else
2476	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2477	#endif
2478	/** @def IEMOPMEDIAF3_INIT_VARS
2479	* Generate AVX function tables for the @a a_InstrNm instruction.
2480	* @sa IEMOPMEDIAF3_INIT_VARS_EX */
2481	#define IEMOPMEDIAF3_INIT_VARS(a_InstrNm) \
2482	IEMOPMEDIAF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2483	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2484
2485	/**
2486	* Function table for media instruction taking two full sized media source
2487	* registers and one full sized destination register, but no additional state
2488	* (AVX).
2489	*/
2490	typedef struct IEMOPMEDIAOPTF3
2491	{
2492	PFNIEMAIMPLMEDIAOPTF3U128 pfnU128;
2493	PFNIEMAIMPLMEDIAOPTF3U256 pfnU256;
2494	} IEMOPMEDIAOPTF3;
2495	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
2496	typedef IEMOPMEDIAOPTF3 const *PCIEMOPMEDIAOPTF3;
2497
2498	/** @def IEMOPMEDIAOPTF3_INIT_VARS_EX
2499	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2500	* given functions as initializers. For use in AVX functions where a pair of
2501	* functions are only used once and the function table need not be public. */
2502	#ifndef TST_IEM_CHECK_MC
2503	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2504	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2505	static IEMOPMEDIAOPTF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2506	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2507	# else
2508	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2509	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2510	# endif
2511	#else
2512	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2513	#endif
2514	/** @def IEMOPMEDIAOPTF3_INIT_VARS
2515	* Generate AVX function tables for the @a a_InstrNm instruction.
2516	* @sa IEMOPMEDIAOPTF3_INIT_VARS_EX */
2517	#define IEMOPMEDIAOPTF3_INIT_VARS(a_InstrNm) \
2518	IEMOPMEDIAOPTF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2519	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2520
2521	/**
2522	* Function table for media instruction taking one full sized media source
2523	* registers and one full sized destination register, but no additional state
2524	* (AVX).
2525	*/
2526	typedef struct IEMOPMEDIAOPTF2
2527	{
2528	PFNIEMAIMPLMEDIAOPTF2U128 pfnU128;
2529	PFNIEMAIMPLMEDIAOPTF2U256 pfnU256;
2530	} IEMOPMEDIAOPTF2;
2531	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
2532	typedef IEMOPMEDIAOPTF2 const *PCIEMOPMEDIAOPTF2;
2533
2534	/** @def IEMOPMEDIAOPTF2_INIT_VARS_EX
2535	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2536	* given functions as initializers. For use in AVX functions where a pair of
2537	* functions are only used once and the function table need not be public. */
2538	#ifndef TST_IEM_CHECK_MC
2539	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2540	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2541	static IEMOPMEDIAOPTF2 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2542	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2543	# else
2544	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2545	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2546	# endif
2547	#else
2548	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2549	#endif
2550	/** @def IEMOPMEDIAOPTF2_INIT_VARS
2551	* Generate AVX function tables for the @a a_InstrNm instruction.
2552	* @sa IEMOPMEDIAOPTF2_INIT_VARS_EX */
2553	#define IEMOPMEDIAOPTF2_INIT_VARS(a_InstrNm) \
2554	IEMOPMEDIAOPTF2_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2555	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2556
2557	/**
2558	* Function table for media instruction taking two full sized media source
2559	* registers and one full sized destination register and an 8-bit immediate, but no additional state
2560	* (AVX).
2561	*/
2562	typedef struct IEMOPMEDIAOPTF3IMM8
2563	{
2564	PFNIEMAIMPLMEDIAOPTF3U128IMM8 pfnU128;
2565	PFNIEMAIMPLMEDIAOPTF3U256IMM8 pfnU256;
2566	} IEMOPMEDIAOPTF3IMM8;
2567	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
2568	typedef IEMOPMEDIAOPTF3IMM8 const *PCIEMOPMEDIAOPTF3IMM8;
2569
2570	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX
2571	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2572	* given functions as initializers. For use in AVX functions where a pair of
2573	* functions are only used once and the function table need not be public. */
2574	#ifndef TST_IEM_CHECK_MC
2575	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2576	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2577	static IEMOPMEDIAOPTF3IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2578	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2579	# else
2580	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2581	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2582	# endif
2583	#else
2584	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2585	#endif
2586	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS
2587	* Generate AVX function tables for the @a a_InstrNm instruction.
2588	* @sa IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX */
2589	#define IEMOPMEDIAOPTF3IMM8_INIT_VARS(a_InstrNm) \
2590	IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2591	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2592	/** @} */
2593
2594
2595	/**
2596	* Function table for blend type instruction taking three full sized media source
2597	* registers and one full sized destination register, but no additional state
2598	* (AVX).
2599	*/
2600	typedef struct IEMOPBLENDOP
2601	{
2602	PFNIEMAIMPLAVXBLENDU128 pfnU128;
2603	PFNIEMAIMPLAVXBLENDU256 pfnU256;
2604	} IEMOPBLENDOP;
2605	/** Pointer to a media operation function table for 4 full sized ops (AVX). */
2606	typedef IEMOPBLENDOP const *PCIEMOPBLENDOP;
2607
2608	/** @def IEMOPBLENDOP_INIT_VARS_EX
2609	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2610	* given functions as initializers. For use in AVX functions where a pair of
2611	* functions are only used once and the function table need not be public. */
2612	#ifndef TST_IEM_CHECK_MC
2613	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2614	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2615	static IEMOPBLENDOP const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2616	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2617	# else
2618	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2619	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2620	# endif
2621	#else
2622	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2623	#endif
2624	/** @def IEMOPBLENDOP_INIT_VARS
2625	* Generate AVX function tables for the @a a_InstrNm instruction.
2626	* @sa IEMOPBLENDOP_INIT_VARS_EX */
2627	#define IEMOPBLENDOP_INIT_VARS(a_InstrNm) \
2628	IEMOPBLENDOP_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2629	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2630
2631
2632	/** @name SSE/AVX single/double precision floating point operations.
2633	* @{ */
2634	/**
2635	* A SSE result.
2636	*/
2637	typedef struct IEMSSERESULT
2638	{
2639	/** The output value. */
2640	X86XMMREG uResult;
2641	/** The output status. */
2642	uint32_t MXCSR;
2643	} IEMSSERESULT;
2644	AssertCompileMemberOffset(IEMSSERESULT, MXCSR, 128 / 8);
2645	/** Pointer to a SSE result. */
2646	typedef IEMSSERESULT *PIEMSSERESULT;
2647	/** Pointer to a const SSE result. */
2648	typedef IEMSSERESULT const *PCIEMSSERESULT;
2649
2650
2651	/**
2652	* A AVX128 result.
2653	*/
2654	typedef struct IEMAVX128RESULT
2655	{
2656	/** The output value. */
2657	X86XMMREG uResult;
2658	/** The output status. */
2659	uint32_t MXCSR;
2660	} IEMAVX128RESULT;
2661	AssertCompileMemberOffset(IEMAVX128RESULT, MXCSR, 128 / 8);
2662	/** Pointer to a AVX128 result. */
2663	typedef IEMAVX128RESULT *PIEMAVX128RESULT;
2664	/** Pointer to a const AVX128 result. */
2665	typedef IEMAVX128RESULT const *PCIEMAVX128RESULT;
2666
2667
2668	/**
2669	* A AVX256 result.
2670	*/
2671	typedef struct IEMAVX256RESULT
2672	{
2673	/** The output value. */
2674	X86YMMREG uResult;
2675	/** The output status. */
2676	uint32_t MXCSR;
2677	} IEMAVX256RESULT;
2678	AssertCompileMemberOffset(IEMAVX256RESULT, MXCSR, 256 / 8);
2679	/** Pointer to a AVX256 result. */
2680	typedef IEMAVX256RESULT *PIEMAVX256RESULT;
2681	/** Pointer to a const AVX256 result. */
2682	typedef IEMAVX256RESULT const *PCIEMAVX256RESULT;
2683
2684
2685	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
2686	typedef FNIEMAIMPLFPSSEF2U128 *PFNIEMAIMPLFPSSEF2U128;
2687	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128R32,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
2688	typedef FNIEMAIMPLFPSSEF2U128R32 *PFNIEMAIMPLFPSSEF2U128R32;
2689	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128R64,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
2690	typedef FNIEMAIMPLFPSSEF2U128R64 *PFNIEMAIMPLFPSSEF2U128R64;
2691
2692	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
2693	typedef FNIEMAIMPLFPAVXF3U128 *PFNIEMAIMPLFPAVXF3U128;
2694	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128R32,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
2695	typedef FNIEMAIMPLFPAVXF3U128R32 *PFNIEMAIMPLFPAVXF3U128R32;
2696	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128R64,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
2697	typedef FNIEMAIMPLFPAVXF3U128R64 *PFNIEMAIMPLFPAVXF3U128R64;
2698
2699	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U256,(PX86XSAVEAREA pExtState, PIEMAVX256RESULT pResult, PCX86YMMREG puSrc1, PCX86YMMREG puSrc2));
2700	typedef FNIEMAIMPLFPAVXF3U256 *PFNIEMAIMPLFPAVXF3U256;
2701
2702	FNIEMAIMPLFPSSEF2U128 iemAImpl_addps_u128;
2703	FNIEMAIMPLFPSSEF2U128 iemAImpl_addpd_u128;
2704	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulps_u128;
2705	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulpd_u128;
2706	FNIEMAIMPLFPSSEF2U128 iemAImpl_subps_u128;
2707	FNIEMAIMPLFPSSEF2U128 iemAImpl_subpd_u128;
2708	FNIEMAIMPLFPSSEF2U128 iemAImpl_minps_u128;
2709	FNIEMAIMPLFPSSEF2U128 iemAImpl_minpd_u128;
2710	FNIEMAIMPLFPSSEF2U128 iemAImpl_divps_u128;
2711	FNIEMAIMPLFPSSEF2U128 iemAImpl_divpd_u128;
2712	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxps_u128;
2713	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxpd_u128;
2714	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddps_u128;
2715	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddpd_u128;
2716	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubps_u128;
2717	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubpd_u128;
2718	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtps_u128;
2719	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtpd_u128;
2720	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubps_u128;
2721	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubpd_u128;
2722	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2ps_u128;
2723	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2pd_u128;
2724
2725	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2ps_u128;
2726	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2dq_u128;
2727	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttps2dq_u128;
2728	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttpd2dq_u128;
2729	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2pd_u128;
2730	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2dq_u128;
2731
2732	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_addss_u128_r32;
2733	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_addsd_u128_r64;
2734	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_mulss_u128_r32;
2735	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_mulsd_u128_r64;
2736	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_subss_u128_r32;
2737	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_subsd_u128_r64;
2738	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_minss_u128_r32;
2739	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_minsd_u128_r64;
2740	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_divss_u128_r32;
2741	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_divsd_u128_r64;
2742	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_maxss_u128_r32;
2743	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_maxsd_u128_r64;
2744	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_cvtss2sd_u128_r32;
2745	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_cvtsd2ss_u128_r64;
2746	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_sqrtss_u128_r32;
2747	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_sqrtsd_u128_r64;
2748
2749	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddps_u128, iemAImpl_vaddps_u128_fallback;
2750	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddpd_u128, iemAImpl_vaddpd_u128_fallback;
2751	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulps_u128, iemAImpl_vmulps_u128_fallback;
2752	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulpd_u128, iemAImpl_vmulpd_u128_fallback;
2753	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubps_u128, iemAImpl_vsubps_u128_fallback;
2754	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubpd_u128, iemAImpl_vsubpd_u128_fallback;
2755	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminps_u128, iemAImpl_vminps_u128_fallback;
2756	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminpd_u128, iemAImpl_vminpd_u128_fallback;
2757	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivps_u128, iemAImpl_vdivps_u128_fallback;
2758	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivpd_u128, iemAImpl_vdivpd_u128_fallback;
2759	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxps_u128, iemAImpl_vmaxps_u128_fallback;
2760	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxpd_u128, iemAImpl_vmaxpd_u128_fallback;
2761	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddps_u128, iemAImpl_vhaddps_u128_fallback;
2762	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddpd_u128, iemAImpl_vhaddpd_u128_fallback;
2763	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubps_u128, iemAImpl_vhsubps_u128_fallback;
2764	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubpd_u128, iemAImpl_vhsubpd_u128_fallback;
2765	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtps_u128, iemAImpl_vsqrtps_u128_fallback;
2766	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtpd_u128, iemAImpl_vsqrtpd_u128_fallback;
2767	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubps_u128, iemAImpl_vaddsubps_u128_fallback;
2768	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubpd_u128, iemAImpl_vaddsubpd_u128_fallback;
2769	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtpd2ps_u128, iemAImpl_vcvtpd2ps_u128_fallback;
2770	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtps2pd_u128, iemAImpl_vcvtps2pd_u128_fallback;
2771
2772	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vaddss_u128_r32, iemAImpl_vaddss_u128_r32_fallback;
2773	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vaddsd_u128_r64, iemAImpl_vaddsd_u128_r64_fallback;
2774	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmulss_u128_r32, iemAImpl_vmulss_u128_r32_fallback;
2775	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmulsd_u128_r64, iemAImpl_vmulsd_u128_r64_fallback;
2776	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsubss_u128_r32, iemAImpl_vsubss_u128_r32_fallback;
2777	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsubsd_u128_r64, iemAImpl_vsubsd_u128_r64_fallback;
2778	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vminss_u128_r32, iemAImpl_vminss_u128_r32_fallback;
2779	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vminsd_u128_r64, iemAImpl_vminsd_u128_r64_fallback;
2780	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vdivss_u128_r32, iemAImpl_vdivss_u128_r32_fallback;
2781	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vdivsd_u128_r64, iemAImpl_vdivsd_u128_r64_fallback;
2782	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmaxss_u128_r32, iemAImpl_vmaxss_u128_r32_fallback;
2783	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmaxsd_u128_r64, iemAImpl_vmaxsd_u128_r64_fallback;
2784	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsqrtss_u128_r32, iemAImpl_vsqrtss_u128_r32_fallback;
2785	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsqrtsd_u128_r64, iemAImpl_vsqrtsd_u128_r64_fallback;
2786
2787	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddps_u256, iemAImpl_vaddps_u256_fallback;
2788	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddpd_u256, iemAImpl_vaddpd_u256_fallback;
2789	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulps_u256, iemAImpl_vmulps_u256_fallback;
2790	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulpd_u256, iemAImpl_vmulpd_u256_fallback;
2791	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubps_u256, iemAImpl_vsubps_u256_fallback;
2792	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubpd_u256, iemAImpl_vsubpd_u256_fallback;
2793	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminps_u256, iemAImpl_vminps_u256_fallback;
2794	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminpd_u256, iemAImpl_vminpd_u256_fallback;
2795	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivps_u256, iemAImpl_vdivps_u256_fallback;
2796	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivpd_u256, iemAImpl_vdivpd_u256_fallback;
2797	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxps_u256, iemAImpl_vmaxps_u256_fallback;
2798	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxpd_u256, iemAImpl_vmaxpd_u256_fallback;
2799	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddps_u256, iemAImpl_vhaddps_u256_fallback;
2800	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddpd_u256, iemAImpl_vhaddpd_u256_fallback;
2801	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubps_u256, iemAImpl_vhsubps_u256_fallback;
2802	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubpd_u256, iemAImpl_vhsubpd_u256_fallback;
2803	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubps_u256, iemAImpl_vhaddsubps_u256_fallback;
2804	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubpd_u256, iemAImpl_vhaddsubpd_u256_fallback;
2805	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtpd2ps_u256, iemAImpl_vcvtpd2ps_u256_fallback;
2806	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtps2pd_u256, iemAImpl_vcvtps2pd_u256_fallback;
2807	/** @} */
2808
2809	/** @name C instruction implementations for anything slightly complicated.
2810	* @{ */
2811
2812	/**
2813	* For typedef'ing or declaring a C instruction implementation function taking
2814	* no extra arguments.
2815	*
2816	* @param a_Name The name of the type.
2817	*/
2818	# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
2819	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
2820	/**
2821	* For defining a C instruction implementation function taking no extra
2822	* arguments.
2823	*
2824	* @param a_Name The name of the function
2825	*/
2826	# define IEM_CIMPL_DEF_0(a_Name) \
2827	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
2828	/**
2829	* Prototype version of IEM_CIMPL_DEF_0.
2830	*/
2831	# define IEM_CIMPL_PROTO_0(a_Name) \
2832	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
2833	/**
2834	* For calling a C instruction implementation function taking no extra
2835	* arguments.
2836	*
2837	* This special call macro adds default arguments to the call and allow us to
2838	* change these later.
2839	*
2840	* @param a_fn The name of the function.
2841	*/
2842	# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
2843
2844	/**
2845	* For typedef'ing or declaring a C instruction implementation function taking
2846	* one extra argument.
2847	*
2848	* @param a_Name The name of the type.
2849	* @param a_Type0 The argument type.
2850	* @param a_Arg0 The argument name.
2851	*/
2852	# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
2853	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
2854	/**
2855	* For defining a C instruction implementation function taking one extra
2856	* argument.
2857	*
2858	* @param a_Name The name of the function
2859	* @param a_Type0 The argument type.
2860	* @param a_Arg0 The argument name.
2861	*/
2862	# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
2863	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
2864	/**
2865	* Prototype version of IEM_CIMPL_DEF_1.
2866	*/
2867	# define IEM_CIMPL_PROTO_1(a_Name, a_Type0, a_Arg0) \
2868	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
2869	/**
2870	* For calling a C instruction implementation function taking one extra
2871	* argument.
2872	*
2873	* This special call macro adds default arguments to the call and allow us to
2874	* change these later.
2875	*
2876	* @param a_fn The name of the function.
2877	* @param a0 The name of the 1st argument.
2878	*/
2879	# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
2880
2881	/**
2882	* For typedef'ing or declaring a C instruction implementation function taking
2883	* two extra arguments.
2884	*
2885	* @param a_Name The name of the type.
2886	* @param a_Type0 The type of the 1st argument
2887	* @param a_Arg0 The name of the 1st argument.
2888	* @param a_Type1 The type of the 2nd argument.
2889	* @param a_Arg1 The name of the 2nd argument.
2890	*/
2891	# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
2892	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
2893	/**
2894	* For defining a C instruction implementation function taking two extra
2895	* arguments.
2896	*
2897	* @param a_Name The name of the function.
2898	* @param a_Type0 The type of the 1st argument
2899	* @param a_Arg0 The name of the 1st argument.
2900	* @param a_Type1 The type of the 2nd argument.
2901	* @param a_Arg1 The name of the 2nd argument.
2902	*/
2903	# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
2904	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
2905	/**
2906	* Prototype version of IEM_CIMPL_DEF_2.
2907	*/
2908	# define IEM_CIMPL_PROTO_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
2909	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
2910	/**
2911	* For calling a C instruction implementation function taking two extra
2912	* arguments.
2913	*
2914	* This special call macro adds default arguments to the call and allow us to
2915	* change these later.
2916	*
2917	* @param a_fn The name of the function.
2918	* @param a0 The name of the 1st argument.
2919	* @param a1 The name of the 2nd argument.
2920	*/
2921	# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
2922
2923	/**
2924	* For typedef'ing or declaring a C instruction implementation function taking
2925	* three extra arguments.
2926	*
2927	* @param a_Name The name of the type.
2928	* @param a_Type0 The type of the 1st argument
2929	* @param a_Arg0 The name of the 1st argument.
2930	* @param a_Type1 The type of the 2nd argument.
2931	* @param a_Arg1 The name of the 2nd argument.
2932	* @param a_Type2 The type of the 3rd argument.
2933	* @param a_Arg2 The name of the 3rd argument.
2934	*/
2935	# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
2936	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
2937	/**
2938	* For defining a C instruction implementation function taking three extra
2939	* arguments.
2940	*
2941	* @param a_Name The name of the function.
2942	* @param a_Type0 The type of the 1st argument
2943	* @param a_Arg0 The name of the 1st argument.
2944	* @param a_Type1 The type of the 2nd argument.
2945	* @param a_Arg1 The name of the 2nd argument.
2946	* @param a_Type2 The type of the 3rd argument.
2947	* @param a_Arg2 The name of the 3rd argument.
2948	*/
2949	# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
2950	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
2951	/**
2952	* Prototype version of IEM_CIMPL_DEF_3.
2953	*/
2954	# define IEM_CIMPL_PROTO_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
2955	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
2956	/**
2957	* For calling a C instruction implementation function taking three extra
2958	* arguments.
2959	*
2960	* This special call macro adds default arguments to the call and allow us to
2961	* change these later.
2962	*
2963	* @param a_fn The name of the function.
2964	* @param a0 The name of the 1st argument.
2965	* @param a1 The name of the 2nd argument.
2966	* @param a2 The name of the 3rd argument.
2967	*/
2968	# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
2969
2970
2971	/**
2972	* For typedef'ing or declaring a C instruction implementation function taking
2973	* four extra arguments.
2974	*
2975	* @param a_Name The name of the type.
2976	* @param a_Type0 The type of the 1st argument
2977	* @param a_Arg0 The name of the 1st argument.
2978	* @param a_Type1 The type of the 2nd argument.
2979	* @param a_Arg1 The name of the 2nd argument.
2980	* @param a_Type2 The type of the 3rd argument.
2981	* @param a_Arg2 The name of the 3rd argument.
2982	* @param a_Type3 The type of the 4th argument.
2983	* @param a_Arg3 The name of the 4th argument.
2984	*/
2985	# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
2986	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
2987	/**
2988	* For defining a C instruction implementation function taking four extra
2989	* arguments.
2990	*
2991	* @param a_Name The name of the function.
2992	* @param a_Type0 The type of the 1st argument
2993	* @param a_Arg0 The name of the 1st argument.
2994	* @param a_Type1 The type of the 2nd argument.
2995	* @param a_Arg1 The name of the 2nd argument.
2996	* @param a_Type2 The type of the 3rd argument.
2997	* @param a_Arg2 The name of the 3rd argument.
2998	* @param a_Type3 The type of the 4th argument.
2999	* @param a_Arg3 The name of the 4th argument.
3000	*/
3001	# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
3002	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3003	a_Type2 a_Arg2, a_Type3 a_Arg3))
3004	/**
3005	* Prototype version of IEM_CIMPL_DEF_4.
3006	*/
3007	# define IEM_CIMPL_PROTO_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
3008	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3009	a_Type2 a_Arg2, a_Type3 a_Arg3))
3010	/**
3011	* For calling a C instruction implementation function taking four extra
3012	* arguments.
3013	*
3014	* This special call macro adds default arguments to the call and allow us to
3015	* change these later.
3016	*
3017	* @param a_fn The name of the function.
3018	* @param a0 The name of the 1st argument.
3019	* @param a1 The name of the 2nd argument.
3020	* @param a2 The name of the 3rd argument.
3021	* @param a3 The name of the 4th argument.
3022	*/
3023	# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
3024
3025
3026	/**
3027	* For typedef'ing or declaring a C instruction implementation function taking
3028	* five extra arguments.
3029	*
3030	* @param a_Name The name of the type.
3031	* @param a_Type0 The type of the 1st argument
3032	* @param a_Arg0 The name of the 1st argument.
3033	* @param a_Type1 The type of the 2nd argument.
3034	* @param a_Arg1 The name of the 2nd argument.
3035	* @param a_Type2 The type of the 3rd argument.
3036	* @param a_Arg2 The name of the 3rd argument.
3037	* @param a_Type3 The type of the 4th argument.
3038	* @param a_Arg3 The name of the 4th argument.
3039	* @param a_Type4 The type of the 5th argument.
3040	* @param a_Arg4 The name of the 5th argument.
3041	*/
3042	# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
3043	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, \
3044	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
3045	a_Type3 a_Arg3, a_Type4 a_Arg4))
3046	/**
3047	* For defining a C instruction implementation function taking five extra
3048	* arguments.
3049	*
3050	* @param a_Name The name of the function.
3051	* @param a_Type0 The type of the 1st argument
3052	* @param a_Arg0 The name of the 1st argument.
3053	* @param a_Type1 The type of the 2nd argument.
3054	* @param a_Arg1 The name of the 2nd argument.
3055	* @param a_Type2 The type of the 3rd argument.
3056	* @param a_Arg2 The name of the 3rd argument.
3057	* @param a_Type3 The type of the 4th argument.
3058	* @param a_Arg3 The name of the 4th argument.
3059	* @param a_Type4 The type of the 5th argument.
3060	* @param a_Arg4 The name of the 5th argument.
3061	*/
3062	# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
3063	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3064	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
3065	/**
3066	* Prototype version of IEM_CIMPL_DEF_5.
3067	*/
3068	# define IEM_CIMPL_PROTO_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
3069	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3070	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
3071	/**
3072	* For calling a C instruction implementation function taking five extra
3073	* arguments.
3074	*
3075	* This special call macro adds default arguments to the call and allow us to
3076	* change these later.
3077	*
3078	* @param a_fn The name of the function.
3079	* @param a0 The name of the 1st argument.
3080	* @param a1 The name of the 2nd argument.
3081	* @param a2 The name of the 3rd argument.
3082	* @param a3 The name of the 4th argument.
3083	* @param a4 The name of the 5th argument.
3084	*/
3085	# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
3086
3087	/** @} */
3088
3089
3090	/** @name Opcode Decoder Function Types.
3091	* @{ */
3092
3093	/** @typedef PFNIEMOP
3094	* Pointer to an opcode decoder function.
3095	*/
3096
3097	/** @def FNIEMOP_DEF
3098	* Define an opcode decoder function.
3099	*
3100	* We're using macors for this so that adding and removing parameters as well as
3101	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL
3102	*
3103	* @param a_Name The function name.
3104	*/
3105
3106	/** @typedef PFNIEMOPRM
3107	* Pointer to an opcode decoder function with RM byte.
3108	*/
3109
3110	/** @def FNIEMOPRM_DEF
3111	* Define an opcode decoder function with RM byte.
3112	*
3113	* We're using macors for this so that adding and removing parameters as well as
3114	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL_1
3115	*
3116	* @param a_Name The function name.
3117	*/
3118
3119	#if defined(__GNUC__) && defined(RT_ARCH_X86)
3120	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOP)(PVMCPUCC pVCpu);
3121	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3122	# define FNIEMOP_DEF(a_Name) \
3123	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu)
3124	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3125	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
3126	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3127	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
3128
3129	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
3130	typedef VBOXSTRICTRC (__fastcall * PFNIEMOP)(PVMCPUCC pVCpu);
3131	typedef VBOXSTRICTRC (__fastcall * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3132	# define FNIEMOP_DEF(a_Name) \
3133	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu) RT_NO_THROW_DEF
3134	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3135	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) RT_NO_THROW_DEF
3136	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3137	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) RT_NO_THROW_DEF
3138
3139	#elif defined(__GNUC__)
3140	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
3141	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3142	# define FNIEMOP_DEF(a_Name) \
3143	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu)
3144	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3145	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
3146	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3147	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
3148
3149	#else
3150	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
3151	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3152	# define FNIEMOP_DEF(a_Name) \
3153	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu) RT_NO_THROW_DEF
3154	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3155	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) RT_NO_THROW_DEF
3156	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3157	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) RT_NO_THROW_DEF
3158
3159	#endif
3160	#define FNIEMOPRM_DEF(a_Name) FNIEMOP_DEF_1(a_Name, uint8_t, bRm)
3161
3162	/**
3163	* Call an opcode decoder function.
3164	*
3165	* We're using macors for this so that adding and removing parameters can be
3166	* done as we please. See FNIEMOP_DEF.
3167	*/
3168	#define FNIEMOP_CALL(a_pfn) (a_pfn)(pVCpu)
3169
3170	/**
3171	* Call a common opcode decoder function taking one extra argument.
3172	*
3173	* We're using macors for this so that adding and removing parameters can be
3174	* done as we please. See FNIEMOP_DEF_1.
3175	*/
3176	#define FNIEMOP_CALL_1(a_pfn, a0) (a_pfn)(pVCpu, a0)
3177
3178	/**
3179	* Call a common opcode decoder function taking one extra argument.
3180	*
3181	* We're using macors for this so that adding and removing parameters can be
3182	* done as we please. See FNIEMOP_DEF_1.
3183	*/
3184	#define FNIEMOP_CALL_2(a_pfn, a0, a1) (a_pfn)(pVCpu, a0, a1)
3185	/** @} */
3186
3187
3188	/** @name Misc Helpers
3189	* @{ */
3190
3191	/** Used to shut up GCC warnings about variables that 'may be used uninitialized'
3192	* due to GCC lacking knowledge about the value range of a switch. */
3193	#define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
3194
3195	/** Variant of IEM_NOT_REACHED_DEFAULT_CASE_RET that returns a custom value. */
3196	#define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: AssertFailedReturn(a_RetValue)
3197
3198	/**
3199	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
3200	* occation.
3201	*/
3202	#ifdef LOG_ENABLED
3203	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
3204	do { \
3205	/Log/ LogAlways(("%s: returning IEM_RETURN_ASPECT_NOT_IMPLEMENTED (line %d)\n", __FUNCTION__, __LINE__)); \
3206	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
3207	} while (0)
3208	#else
3209	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
3210	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
3211	#endif
3212
3213	/**
3214	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
3215	* occation using the supplied logger statement.
3216	*
3217	* @param a_LoggerArgs What to log on failure.
3218	*/
3219	#ifdef LOG_ENABLED
3220	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
3221	do { \
3222	LogAlways((LOG_FN_FMT ": ", __PRETTY_FUNCTION__)); LogAlways(a_LoggerArgs); \
3223	/LogFunc(a_LoggerArgs);/ \
3224	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
3225	} while (0)
3226	#else
3227	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
3228	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
3229	#endif
3230
3231	/**
3232	* Check if we're currently executing in real or virtual 8086 mode.
3233	*
3234	* @returns @c true if it is, @c false if not.
3235	* @param a_pVCpu The IEM state of the current CPU.
3236	*/
3237	#define IEM_IS_REAL_OR_V86_MODE(a_pVCpu) (CPUMIsGuestInRealOrV86ModeEx(IEM_GET_CTX(a_pVCpu)))
3238
3239	/**
3240	* Check if we're currently executing in virtual 8086 mode.
3241	*
3242	* @returns @c true if it is, @c false if not.
3243	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3244	*/
3245	#define IEM_IS_V86_MODE(a_pVCpu) (CPUMIsGuestInV86ModeEx(IEM_GET_CTX(a_pVCpu)))
3246
3247	/**
3248	* Check if we're currently executing in long mode.
3249	*
3250	* @returns @c true if it is, @c false if not.
3251	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3252	*/
3253	#define IEM_IS_LONG_MODE(a_pVCpu) (CPUMIsGuestInLongModeEx(IEM_GET_CTX(a_pVCpu)))
3254
3255	/**
3256	* Check if we're currently executing in a 64-bit code segment.
3257	*
3258	* @returns @c true if it is, @c false if not.
3259	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3260	*/
3261	#define IEM_IS_64BIT_CODE(a_pVCpu) (CPUMIsGuestIn64BitCodeEx(IEM_GET_CTX(a_pVCpu)))
3262
3263	/**
3264	* Check if we're currently executing in real mode.
3265	*
3266	* @returns @c true if it is, @c false if not.
3267	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3268	*/
3269	#define IEM_IS_REAL_MODE(a_pVCpu) (CPUMIsGuestInRealModeEx(IEM_GET_CTX(a_pVCpu)))
3270
3271	/**
3272	* Returns a (const) pointer to the CPUMFEATURES for the guest CPU.
3273	* @returns PCCPUMFEATURES
3274	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3275	*/
3276	#define IEM_GET_GUEST_CPU_FEATURES(a_pVCpu) (&((a_pVCpu)->CTX_SUFF(pVM)->cpum.ro.GuestFeatures))
3277
3278	/**
3279	* Returns a (const) pointer to the CPUMFEATURES for the host CPU.
3280	* @returns PCCPUMFEATURES
3281	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3282	*/
3283	#define IEM_GET_HOST_CPU_FEATURES(a_pVCpu) (&g_CpumHostFeatures.s)
3284
3285	/**
3286	* Evaluates to true if we're presenting an Intel CPU to the guest.
3287	*/
3288	#define IEM_IS_GUEST_CPU_INTEL(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL )
3289
3290	/**
3291	* Evaluates to true if we're presenting an AMD CPU to the guest.
3292	*/
3293	#define IEM_IS_GUEST_CPU_AMD(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_AMD \|\| (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_HYGON )
3294
3295	/**
3296	* Check if the address is canonical.
3297	*/
3298	#define IEM_IS_CANONICAL(a_u64Addr) X86_IS_CANONICAL(a_u64Addr)
3299
3300	/** Checks if the ModR/M byte is in register mode or not. */
3301	#define IEM_IS_MODRM_REG_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT) )
3302	/** Checks if the ModR/M byte is in memory mode or not. */
3303	#define IEM_IS_MODRM_MEM_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT) )
3304
3305	/**
3306	* Gets the register (reg) part of a ModR/M encoding, with REX.R added in.
3307	*
3308	* For use during decoding.
3309	*/
3310	#define IEM_GET_MODRM_REG(a_pVCpu, a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| (a_pVCpu)->iem.s.uRexReg )
3311	/**
3312	* Gets the r/m part of a ModR/M encoding as a register index, with REX.B added in.
3313	*
3314	* For use during decoding.
3315	*/
3316	#define IEM_GET_MODRM_RM(a_pVCpu, a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) \| (a_pVCpu)->iem.s.uRexB )
3317
3318	/**
3319	* Gets the register (reg) part of a ModR/M encoding, without REX.R.
3320	*
3321	* For use during decoding.
3322	*/
3323	#define IEM_GET_MODRM_REG_8(a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) )
3324	/**
3325	* Gets the r/m part of a ModR/M encoding as a register index, without REX.B.
3326	*
3327	* For use during decoding.
3328	*/
3329	#define IEM_GET_MODRM_RM_8(a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) )
3330
3331	/**
3332	* Gets the effective VEX.VVVV value.
3333	*
3334	* The 4th bit is ignored if not 64-bit code.
3335	* @returns effective V-register value.
3336	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3337	*/
3338	#define IEM_GET_EFFECTIVE_VVVV(a_pVCpu) \
3339	((a_pVCpu)->iem.s.enmCpuMode == IEMMODE_64BIT ? (a_pVCpu)->iem.s.uVex3rdReg : (a_pVCpu)->iem.s.uVex3rdReg & 7)
3340
3341
3342	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
3343
3344	/**
3345	* Check if the guest has entered VMX root operation.
3346	*/
3347	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxRootMode(IEM_GET_CTX(a_pVCpu)))
3348
3349	/**
3350	* Check if the guest has entered VMX non-root operation.
3351	*/
3352	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxNonRootMode(IEM_GET_CTX(a_pVCpu)))
3353
3354	/**
3355	* Check if the nested-guest has the given Pin-based VM-execution control set.
3356	*/
3357	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_PinCtl) \
3358	(CPUMIsGuestVmxPinCtlsSet(IEM_GET_CTX(a_pVCpu), (a_PinCtl)))
3359
3360	/**
3361	* Check if the nested-guest has the given Processor-based VM-execution control set.
3362	*/
3363	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_ProcCtl) \
3364	(CPUMIsGuestVmxProcCtlsSet(IEM_GET_CTX(a_pVCpu), (a_ProcCtl)))
3365
3366	/**
3367	* Check if the nested-guest has the given Secondary Processor-based VM-execution
3368	* control set.
3369	*/
3370	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_ProcCtl2) \
3371	(CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(a_pVCpu), (a_ProcCtl2)))
3372
3373	/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
3374	# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
3375
3376	/** Whether a shadow VMCS is present for the given VCPU. */
3377	# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
3378
3379	/** Gets the VMXON region pointer. */
3380	# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
3381
3382	/** Gets the guest-physical address of the current VMCS for the given VCPU. */
3383	# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
3384
3385	/** Whether a current VMCS is present for the given VCPU. */
3386	# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
3387
3388	/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
3389	# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
3390	do \
3391	{ \
3392	Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
3393	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
3394	} while (0)
3395
3396	/** Clears any current VMCS for the given VCPU. */
3397	# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
3398	do \
3399	{ \
3400	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
3401	} while (0)
3402
3403	/**
3404	* Invokes the VMX VM-exit handler for an instruction intercept.
3405	*/
3406	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) \
3407	do { return iemVmxVmexitInstr((a_pVCpu), (a_uExitReason), (a_cbInstr)); } while (0)
3408
3409	/**
3410	* Invokes the VMX VM-exit handler for an instruction intercept where the
3411	* instruction provides additional VM-exit information.
3412	*/
3413	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) \
3414	do { return iemVmxVmexitInstrNeedsInfo((a_pVCpu), (a_uExitReason), (a_uInstrId), (a_cbInstr)); } while (0)
3415
3416	/**
3417	* Invokes the VMX VM-exit handler for a task switch.
3418	*/
3419	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) \
3420	do { return iemVmxVmexitTaskSwitch((a_pVCpu), (a_enmTaskSwitch), (a_SelNewTss), (a_cbInstr)); } while (0)
3421
3422	/**
3423	* Invokes the VMX VM-exit handler for MWAIT.
3424	*/
3425	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) \
3426	do { return iemVmxVmexitInstrMwait((a_pVCpu), (a_fMonitorArmed), (a_cbInstr)); } while (0)
3427
3428	/**
3429	* Invokes the VMX VM-exit handler for EPT faults.
3430	*/
3431	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) \
3432	do { return iemVmxVmexitEpt(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr); } while (0)
3433
3434	/**
3435	* Invokes the VMX VM-exit handler.
3436	*/
3437	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) \
3438	do { return iemVmxVmexit((a_pVCpu), (a_uExitReason), (a_uExitQual)); } while (0)
3439
3440	#else
3441	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (false)
3442	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (false)
3443	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_cbInstr) (false)
3444	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_cbInstr) (false)
3445	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_cbInstr) (false)
3446	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3447	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3448	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3449	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3450	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3451	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) do { return VERR_VMX_IPE_1; } while (0)
3452
3453	#endif
3454
3455	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
3456	/**
3457	* Check if an SVM control/instruction intercept is set.
3458	*/
3459	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) \
3460	(CPUMIsGuestSvmCtrlInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_Intercept)))
3461
3462	/**
3463	* Check if an SVM read CRx intercept is set.
3464	*/
3465	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
3466	(CPUMIsGuestSvmReadCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
3467
3468	/**
3469	* Check if an SVM write CRx intercept is set.
3470	*/
3471	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
3472	(CPUMIsGuestSvmWriteCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
3473
3474	/**
3475	* Check if an SVM read DRx intercept is set.
3476	*/
3477	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
3478	(CPUMIsGuestSvmReadDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
3479
3480	/**
3481	* Check if an SVM write DRx intercept is set.
3482	*/
3483	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
3484	(CPUMIsGuestSvmWriteDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
3485
3486	/**
3487	* Check if an SVM exception intercept is set.
3488	*/
3489	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) \
3490	(CPUMIsGuestSvmXcptInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uVector)))
3491
3492	/**
3493	* Invokes the SVM \#VMEXIT handler for the nested-guest.
3494	*/
3495	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
3496	do { return iemSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2)); } while (0)
3497
3498	/**
3499	* Invokes the 'MOV CRx' SVM \#VMEXIT handler after constructing the
3500	* corresponding decode assist information.
3501	*/
3502	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) \
3503	do \
3504	{ \
3505	uint64_t uExitInfo1; \
3506	if ( IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmDecodeAssists \
3507	&& (a_enmAccessCrX) == IEMACCESSCRX_MOV_CRX) \
3508	uExitInfo1 = SVM_EXIT1_MOV_CRX_MASK \| ((a_iGReg) & 7); \
3509	else \
3510	uExitInfo1 = 0; \
3511	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, uExitInfo1, 0); \
3512	} while (0)
3513
3514	/** Check and handles SVM nested-guest instruction intercept and updates
3515	* NRIP if needed.
3516	*/
3517	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
3518	do \
3519	{ \
3520	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept)) \
3521	{ \
3522	IEM_SVM_UPDATE_NRIP(a_pVCpu); \
3523	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2); \
3524	} \
3525	} while (0)
3526
3527	/** Checks and handles SVM nested-guest CR0 read intercept. */
3528	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2) \
3529	do \
3530	{ \
3531	if (!IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, 0)) \
3532	{ /* probably likely */ } \
3533	else \
3534	{ \
3535	IEM_SVM_UPDATE_NRIP(a_pVCpu); \
3536	IEM_SVM_VMEXIT_RET(a_pVCpu, SVM_EXIT_READ_CR0, a_uExitInfo1, a_uExitInfo2); \
3537	} \
3538	} while (0)
3539
3540	/**
3541	* Updates the NextRIP (NRI) field in the nested-guest VMCB.
3542	*/
3543	# define IEM_SVM_UPDATE_NRIP(a_pVCpu) \
3544	do { \
3545	if (IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmNextRipSave) \
3546	CPUMGuestSvmUpdateNRip(a_pVCpu, IEM_GET_CTX(a_pVCpu), IEM_GET_INSTR_LEN(a_pVCpu)); \
3547	} while (0)
3548
3549	#else
3550	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) (false)
3551	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
3552	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
3553	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
3554	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
3555	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) (false)
3556	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { return VERR_SVM_IPE_1; } while (0)
3557	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) do { return VERR_SVM_IPE_1; } while (0)
3558	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { } while (0)
3559	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2) do { } while (0)
3560	# define IEM_SVM_UPDATE_NRIP(a_pVCpu) do { } while (0)
3561
3562	#endif
3563
3564	/** @} */
3565
3566
3567
3568	/**
3569	* Selector descriptor table entry as fetched by iemMemFetchSelDesc.
3570	*/
3571	typedef union IEMSELDESC
3572	{
3573	/** The legacy view. */
3574	X86DESC Legacy;
3575	/** The long mode view. */
3576	X86DESC64 Long;
3577	} IEMSELDESC;
3578	/** Pointer to a selector descriptor table entry. */
3579	typedef IEMSELDESC *PIEMSELDESC;
3580
3581	/** @name Raising Exceptions.
3582	* @{ */
3583	VBOXSTRICTRC iemTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, uint32_t uNextEip, uint32_t fFlags,
3584	uint16_t uErr, uint64_t uCr2, RTSEL SelTSS, PIEMSELDESC pNewDescTSS) RT_NOEXCEPT;
3585
3586	VBOXSTRICTRC iemRaiseXcptOrInt(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags,
3587	uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
3588	#ifdef IEM_WITH_SETJMP
3589	DECL_NO_RETURN(void) iemRaiseXcptOrIntJmp(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector,
3590	uint32_t fFlags, uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
3591	#endif
3592	VBOXSTRICTRC iemRaiseDivideError(PVMCPUCC pVCpu) RT_NOEXCEPT;
3593	VBOXSTRICTRC iemRaiseDebugException(PVMCPUCC pVCpu) RT_NOEXCEPT;
3594	VBOXSTRICTRC iemRaiseBoundRangeExceeded(PVMCPUCC pVCpu) RT_NOEXCEPT;
3595	VBOXSTRICTRC iemRaiseUndefinedOpcode(PVMCPUCC pVCpu) RT_NOEXCEPT;
3596	VBOXSTRICTRC iemRaiseDeviceNotAvailable(PVMCPUCC pVCpu) RT_NOEXCEPT;
3597	VBOXSTRICTRC iemRaiseTaskSwitchFaultWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
3598	VBOXSTRICTRC iemRaiseTaskSwitchFaultCurrentTSS(PVMCPUCC pVCpu) RT_NOEXCEPT;
3599	VBOXSTRICTRC iemRaiseTaskSwitchFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
3600	VBOXSTRICTRC iemRaiseTaskSwitchFaultBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
3601	/VBOXSTRICTRC iemRaiseSelectorNotPresent(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;/
3602	VBOXSTRICTRC iemRaiseSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
3603	VBOXSTRICTRC iemRaiseSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
3604	VBOXSTRICTRC iemRaiseStackSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
3605	VBOXSTRICTRC iemRaiseStackSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
3606	VBOXSTRICTRC iemRaiseGeneralProtectionFault(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
3607	VBOXSTRICTRC iemRaiseGeneralProtectionFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
3608	#ifdef IEM_WITH_SETJMP
3609	DECL_NO_RETURN(void) iemRaiseGeneralProtectionFault0Jmp(PVMCPUCC pVCpu) RT_NOEXCEPT;
3610	#endif
3611	VBOXSTRICTRC iemRaiseGeneralProtectionFaultBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
3612	VBOXSTRICTRC iemRaiseNotCanonical(PVMCPUCC pVCpu) RT_NOEXCEPT;
3613	VBOXSTRICTRC iemRaiseSelectorBounds(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
3614	#ifdef IEM_WITH_SETJMP
3615	DECL_NO_RETURN(void) iemRaiseSelectorBoundsJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
3616	#endif
3617	VBOXSTRICTRC iemRaiseSelectorBoundsBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
3618	#ifdef IEM_WITH_SETJMP
3619	DECL_NO_RETURN(void) iemRaiseSelectorBoundsBySelectorJmp(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
3620	#endif
3621	VBOXSTRICTRC iemRaiseSelectorInvalidAccess(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
3622	#ifdef IEM_WITH_SETJMP
3623	DECL_NO_RETURN(void) iemRaiseSelectorInvalidAccessJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
3624	#endif
3625	VBOXSTRICTRC iemRaisePageFault(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t fAccess, int rc) RT_NOEXCEPT;
3626	#ifdef IEM_WITH_SETJMP
3627	DECL_NO_RETURN(void) iemRaisePageFaultJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t fAccess, int rc) RT_NOEXCEPT;
3628	#endif
3629	VBOXSTRICTRC iemRaiseMathFault(PVMCPUCC pVCpu);
3630	VBOXSTRICTRC iemRaiseAlignmentCheckException(PVMCPUCC pVCpu);
3631	#ifdef IEM_WITH_SETJMP
3632	DECL_NO_RETURN(void) iemRaiseAlignmentCheckExceptionJmp(PVMCPUCC pVCpu) RT_NOEXCEPT;
3633	#endif
3634	VBOXSTRICTRC iemRaiseSimdFpException(PVMCPUCC pVCpu) RT_NOEXCEPT;
3635
3636	IEM_CIMPL_DEF_0(iemCImplRaiseDivideError);
3637	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidLockPrefix);
3638	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidOpcode);
3639
3640	/**
3641	* Macro for calling iemCImplRaiseDivideError().
3642	*
3643	* This enables us to add/remove arguments and force different levels of
3644	* inlining as we wish.
3645	*
3646	* @return Strict VBox status code.
3647	*/
3648	#define IEMOP_RAISE_DIVIDE_ERROR() IEM_MC_DEFER_TO_CIMPL_0(iemCImplRaiseDivideError)
3649
3650	/**
3651	* Macro for calling iemCImplRaiseInvalidLockPrefix().
3652	*
3653	* This enables us to add/remove arguments and force different levels of
3654	* inlining as we wish.
3655	*
3656	* @return Strict VBox status code.
3657	*/
3658	#define IEMOP_RAISE_INVALID_LOCK_PREFIX() IEM_MC_DEFER_TO_CIMPL_0(iemCImplRaiseInvalidLockPrefix)
3659
3660	/**
3661	* Macro for calling iemCImplRaiseInvalidOpcode().
3662	*
3663	* This enables us to add/remove arguments and force different levels of
3664	* inlining as we wish.
3665	*
3666	* @return Strict VBox status code.
3667	*/
3668	#define IEMOP_RAISE_INVALID_OPCODE() IEM_MC_DEFER_TO_CIMPL_0(iemCImplRaiseInvalidOpcode)
3669	/** @} */
3670
3671	/** @name Register Access.
3672	* @{ */
3673	VBOXSTRICTRC iemRegRipRelativeJumpS8(PVMCPUCC pVCpu, int8_t offNextInstr) RT_NOEXCEPT;
3674	VBOXSTRICTRC iemRegRipRelativeJumpS16(PVMCPUCC pVCpu, int16_t offNextInstr) RT_NOEXCEPT;
3675	VBOXSTRICTRC iemRegRipRelativeJumpS32(PVMCPUCC pVCpu, int32_t offNextInstr) RT_NOEXCEPT;
3676	VBOXSTRICTRC iemRegRipJump(PVMCPUCC pVCpu, uint64_t uNewRip) RT_NOEXCEPT;
3677	/** @} */
3678
3679	/** @name FPU access and helpers.
3680	* @{ */
3681	void iemFpuPushResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult) RT_NOEXCEPT;
3682	void iemFpuPushResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3683	void iemFpuPushResultTwo(PVMCPUCC pVCpu, PIEMFPURESULTTWO pResult) RT_NOEXCEPT;
3684	void iemFpuStoreResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg) RT_NOEXCEPT;
3685	void iemFpuStoreResultThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg) RT_NOEXCEPT;
3686	void iemFpuStoreResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
3687	uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3688	void iemFpuStoreResultWithMemOpThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
3689	uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3690	void iemFpuUpdateOpcodeAndIp(PVMCPUCC pVCpu) RT_NOEXCEPT;
3691	void iemFpuUpdateFSW(PVMCPUCC pVCpu, uint16_t u16FSW) RT_NOEXCEPT;
3692	void iemFpuUpdateFSWThenPop(PVMCPUCC pVCpu, uint16_t u16FSW) RT_NOEXCEPT;
3693	void iemFpuUpdateFSWWithMemOp(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3694	void iemFpuUpdateFSWThenPopPop(PVMCPUCC pVCpu, uint16_t u16FSW) RT_NOEXCEPT;
3695	void iemFpuUpdateFSWWithMemOpThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3696	void iemFpuStackUnderflow(PVMCPUCC pVCpu, uint8_t iStReg) RT_NOEXCEPT;
3697	void iemFpuStackUnderflowWithMemOp(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3698	void iemFpuStackUnderflowThenPop(PVMCPUCC pVCpu, uint8_t iStReg) RT_NOEXCEPT;
3699	void iemFpuStackUnderflowWithMemOpThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3700	void iemFpuStackUnderflowThenPopPop(PVMCPUCC pVCpu) RT_NOEXCEPT;
3701	void iemFpuStackPushUnderflow(PVMCPUCC pVCpu) RT_NOEXCEPT;
3702	void iemFpuStackPushUnderflowTwo(PVMCPUCC pVCpu) RT_NOEXCEPT;
3703	void iemFpuStackPushOverflow(PVMCPUCC pVCpu) RT_NOEXCEPT;
3704	void iemFpuStackPushOverflowWithMemOp(PVMCPUCC pVCpu, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3705	/** @} */
3706
3707	/** @name SSE+AVX SIMD access and helpers.
3708	* @{ */
3709	void iemSseStoreResult(PVMCPUCC pVCpu, PCIEMSSERESULT pResult, uint8_t iXmmReg) RT_NOEXCEPT;
3710	void iemSseUpdateMxcsr(PVMCPUCC pVCpu, uint32_t fMxcsr) RT_NOEXCEPT;
3711	/** @} */
3712
3713	/** @name Memory access.
3714	* @{ */
3715
3716	/** Report a \#GP instead of \#AC and do not restrict to ring-3 */
3717	#define IEM_MEMMAP_F_ALIGN_GP RT_BIT_32(16)
3718	/** SSE access that should report a \#GP instead of \#AC, unless MXCSR.MM=1
3719	* when it works like normal \#AC. Always used with IEM_MEMMAP_F_ALIGN_GP. */
3720	#define IEM_MEMMAP_F_ALIGN_SSE RT_BIT_32(17)
3721	/** If \#AC is applicable, raise it. Always used with IEM_MEMMAP_F_ALIGN_GP.
3722	* Users include FXSAVE & FXRSTOR. */
3723	#define IEM_MEMMAP_F_ALIGN_GP_OR_AC RT_BIT_32(18)
3724
3725	VBOXSTRICTRC iemMemMap(PVMCPUCC pVCpu, void **ppvMem, size_t cbMem, uint8_t iSegReg, RTGCPTR GCPtrMem,
3726	uint32_t fAccess, uint32_t uAlignCtl) RT_NOEXCEPT;
3727	VBOXSTRICTRC iemMemCommitAndUnmap(PVMCPUCC pVCpu, void *pvMem, uint32_t fAccess) RT_NOEXCEPT;
3728	#ifndef IN_RING3
3729	VBOXSTRICTRC iemMemCommitAndUnmapPostponeTroubleToR3(PVMCPUCC pVCpu, void *pvMem, uint32_t fAccess) RT_NOEXCEPT;
3730	#endif
3731	void iemMemRollback(PVMCPUCC pVCpu) RT_NOEXCEPT;
3732	VBOXSTRICTRC iemMemApplySegment(PVMCPUCC pVCpu, uint32_t fAccess, uint8_t iSegReg, size_t cbMem, PRTGCPTR pGCPtrMem) RT_NOEXCEPT;
3733	VBOXSTRICTRC iemMemMarkSelDescAccessed(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
3734	VBOXSTRICTRC iemMemPageTranslateAndCheckAccess(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t fAccess, PRTGCPHYS pGCPhysMem) RT_NOEXCEPT;
3735
3736	#ifdef IEM_WITH_CODE_TLB
3737	void iemOpcodeFetchBytesJmp(PVMCPUCC pVCpu, size_t cbDst, void *pvDst) RT_NOEXCEPT;
3738	#else
3739	VBOXSTRICTRC iemOpcodeFetchMoreBytes(PVMCPUCC pVCpu, size_t cbMin) RT_NOEXCEPT;
3740	#endif
3741	#ifdef IEM_WITH_SETJMP
3742	uint8_t iemOpcodeGetNextU8SlowJmp(PVMCPUCC pVCpu) RT_NOEXCEPT;
3743	uint16_t iemOpcodeGetNextU16SlowJmp(PVMCPUCC pVCpu) RT_NOEXCEPT;
3744	uint32_t iemOpcodeGetNextU32SlowJmp(PVMCPUCC pVCpu) RT_NOEXCEPT;
3745	uint64_t iemOpcodeGetNextU64SlowJmp(PVMCPUCC pVCpu) RT_NOEXCEPT;
3746	#else
3747	VBOXSTRICTRC iemOpcodeGetNextU8Slow(PVMCPUCC pVCpu, uint8_t *pb) RT_NOEXCEPT;
3748	VBOXSTRICTRC iemOpcodeGetNextS8SxU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
3749	VBOXSTRICTRC iemOpcodeGetNextS8SxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
3750	VBOXSTRICTRC iemOpcodeGetNextS8SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
3751	VBOXSTRICTRC iemOpcodeGetNextU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
3752	VBOXSTRICTRC iemOpcodeGetNextU16ZxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
3753	VBOXSTRICTRC iemOpcodeGetNextU16ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
3754	VBOXSTRICTRC iemOpcodeGetNextU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
3755	VBOXSTRICTRC iemOpcodeGetNextU32ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
3756	VBOXSTRICTRC iemOpcodeGetNextS32SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
3757	VBOXSTRICTRC iemOpcodeGetNextU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
3758	#endif
3759
3760	VBOXSTRICTRC iemMemFetchDataU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3761	VBOXSTRICTRC iemMemFetchDataU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3762	VBOXSTRICTRC iemMemFetchDataU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3763	VBOXSTRICTRC iemMemFetchDataU32_ZX_U64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3764	VBOXSTRICTRC iemMemFetchDataU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3765	VBOXSTRICTRC iemMemFetchDataU64AlignedU128(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3766	VBOXSTRICTRC iemMemFetchDataR80(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3767	VBOXSTRICTRC iemMemFetchDataD80(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3768	VBOXSTRICTRC iemMemFetchDataU128(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3769	VBOXSTRICTRC iemMemFetchDataU128AlignedSse(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3770	VBOXSTRICTRC iemMemFetchDataU256(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3771	VBOXSTRICTRC iemMemFetchDataU256AlignedSse(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3772	VBOXSTRICTRC iemMemFetchDataXdtr(PVMCPUCC pVCpu, uint16_t *pcbLimit, PRTGCPTR pGCPtrBase, uint8_t iSegReg,
3773	RTGCPTR GCPtrMem, IEMMODE enmOpSize) RT_NOEXCEPT;
3774	#ifdef IEM_WITH_SETJMP
3775	uint8_t iemMemFetchDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3776	uint16_t iemMemFetchDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3777	uint32_t iemMemFetchDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3778	uint64_t iemMemFetchDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3779	uint64_t iemMemFetchDataU64AlignedU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3780	void iemMemFetchDataR80Jmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3781	void iemMemFetchDataD80Jmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3782	void iemMemFetchDataU128Jmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3783	void iemMemFetchDataU128AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3784	void iemMemFetchDataU256Jmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3785	void iemMemFetchDataU256AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3786	#endif
3787
3788	VBOXSTRICTRC iemMemFetchSysU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3789	VBOXSTRICTRC iemMemFetchSysU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3790	VBOXSTRICTRC iemMemFetchSysU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3791	VBOXSTRICTRC iemMemFetchSysU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3792	VBOXSTRICTRC iemMemFetchSelDesc(PVMCPUCC pVCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt) RT_NOEXCEPT;
3793
3794	VBOXSTRICTRC iemMemStoreDataU8(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) RT_NOEXCEPT;
3795	VBOXSTRICTRC iemMemStoreDataU16(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) RT_NOEXCEPT;
3796	VBOXSTRICTRC iemMemStoreDataU32(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) RT_NOEXCEPT;
3797	VBOXSTRICTRC iemMemStoreDataU64(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) RT_NOEXCEPT;
3798	VBOXSTRICTRC iemMemStoreDataU128(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
3799	VBOXSTRICTRC iemMemStoreDataU128AlignedSse(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
3800	VBOXSTRICTRC iemMemStoreDataU256(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
3801	VBOXSTRICTRC iemMemStoreDataU256AlignedAvx(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
3802	VBOXSTRICTRC iemMemStoreDataXdtr(PVMCPUCC pVCpu, uint16_t cbLimit, RTGCPTR GCPtrBase, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3803	#ifdef IEM_WITH_SETJMP
3804	void iemMemStoreDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) RT_NOEXCEPT;
3805	void iemMemStoreDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) RT_NOEXCEPT;
3806	void iemMemStoreDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) RT_NOEXCEPT;
3807	void iemMemStoreDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) RT_NOEXCEPT;
3808	void iemMemStoreDataU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
3809	void iemMemStoreDataU128AlignedSseJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
3810	void iemMemStoreDataU256Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
3811	void iemMemStoreDataU256AlignedAvxJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
3812	#endif
3813
3814	VBOXSTRICTRC iemMemStackPushBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
3815	void *ppvMem, uint64_t puNewRsp) RT_NOEXCEPT;
3816	VBOXSTRICTRC iemMemStackPushCommitSpecial(PVMCPUCC pVCpu, void *pvMem, uint64_t uNewRsp) RT_NOEXCEPT;
3817	VBOXSTRICTRC iemMemStackPushU16(PVMCPUCC pVCpu, uint16_t u16Value) RT_NOEXCEPT;
3818	VBOXSTRICTRC iemMemStackPushU32(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
3819	VBOXSTRICTRC iemMemStackPushU64(PVMCPUCC pVCpu, uint64_t u64Value) RT_NOEXCEPT;
3820	VBOXSTRICTRC iemMemStackPushU16Ex(PVMCPUCC pVCpu, uint16_t u16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
3821	VBOXSTRICTRC iemMemStackPushU32Ex(PVMCPUCC pVCpu, uint32_t u32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
3822	VBOXSTRICTRC iemMemStackPushU64Ex(PVMCPUCC pVCpu, uint64_t u64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
3823	VBOXSTRICTRC iemMemStackPushU32SReg(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
3824	VBOXSTRICTRC iemMemStackPopBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
3825	void const *ppvMem, uint64_t puNewRsp) RT_NOEXCEPT;
3826	VBOXSTRICTRC iemMemStackPopContinueSpecial(PVMCPUCC pVCpu, size_t off, size_t cbMem,
3827	void const **ppvMem, uint64_t uCurNewRsp) RT_NOEXCEPT;
3828	VBOXSTRICTRC iemMemStackPopDoneSpecial(PVMCPUCC pVCpu, void const *pvMem) RT_NOEXCEPT;
3829	VBOXSTRICTRC iemMemStackPopU16(PVMCPUCC pVCpu, uint16_t *pu16Value) RT_NOEXCEPT;
3830	VBOXSTRICTRC iemMemStackPopU32(PVMCPUCC pVCpu, uint32_t *pu32Value) RT_NOEXCEPT;
3831	VBOXSTRICTRC iemMemStackPopU64(PVMCPUCC pVCpu, uint64_t *pu64Value) RT_NOEXCEPT;
3832	VBOXSTRICTRC iemMemStackPopU16Ex(PVMCPUCC pVCpu, uint16_t *pu16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
3833	VBOXSTRICTRC iemMemStackPopU32Ex(PVMCPUCC pVCpu, uint32_t *pu32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
3834	VBOXSTRICTRC iemMemStackPopU64Ex(PVMCPUCC pVCpu, uint64_t *pu64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
3835	/** @} */
3836
3837	/** @name IEMAllCImpl.cpp
3838	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/'
3839	* @{ */
3840	IEM_CIMPL_PROTO_0(iemCImpl_popa_16);
3841	IEM_CIMPL_PROTO_0(iemCImpl_popa_32);
3842	IEM_CIMPL_PROTO_0(iemCImpl_pusha_16);
3843	IEM_CIMPL_PROTO_0(iemCImpl_pusha_32);
3844	IEM_CIMPL_PROTO_1(iemCImpl_pushf, IEMMODE, enmEffOpSize);
3845	IEM_CIMPL_PROTO_1(iemCImpl_popf, IEMMODE, enmEffOpSize);
3846	IEM_CIMPL_PROTO_1(iemCImpl_call_16, uint16_t, uNewPC);
3847	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_16, int16_t, offDisp);
3848	IEM_CIMPL_PROTO_1(iemCImpl_call_32, uint32_t, uNewPC);
3849	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_32, int32_t, offDisp);
3850	IEM_CIMPL_PROTO_1(iemCImpl_call_64, uint64_t, uNewPC);
3851	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_64, int64_t, offDisp);
3852	IEM_CIMPL_PROTO_4(iemCImpl_BranchTaskSegment, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc);
3853	IEM_CIMPL_PROTO_4(iemCImpl_BranchTaskGate, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc);
3854	IEM_CIMPL_PROTO_4(iemCImpl_BranchCallGate, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc);
3855	IEM_CIMPL_PROTO_4(iemCImpl_BranchSysSel, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc);
3856	IEM_CIMPL_PROTO_3(iemCImpl_FarJmp, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
3857	IEM_CIMPL_PROTO_3(iemCImpl_callf, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
3858	IEM_CIMPL_PROTO_2(iemCImpl_retf, IEMMODE, enmEffOpSize, uint16_t, cbPop);
3859	IEM_CIMPL_PROTO_2(iemCImpl_retn, IEMMODE, enmEffOpSize, uint16_t, cbPop);
3860	IEM_CIMPL_PROTO_3(iemCImpl_enter, IEMMODE, enmEffOpSize, uint16_t, cbFrame, uint8_t, cParameters);
3861	IEM_CIMPL_PROTO_1(iemCImpl_leave, IEMMODE, enmEffOpSize);
3862	IEM_CIMPL_PROTO_2(iemCImpl_int, uint8_t, u8Int, IEMINT, enmInt);
3863	IEM_CIMPL_PROTO_1(iemCImpl_iret_real_v8086, IEMMODE, enmEffOpSize);
3864	IEM_CIMPL_PROTO_4(iemCImpl_iret_prot_v8086, uint32_t, uNewEip, uint16_t, uNewCs, uint32_t, uNewFlags, uint64_t, uNewRsp);
3865	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot_NestedTask, IEMMODE, enmEffOpSize);
3866	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot, IEMMODE, enmEffOpSize);
3867	IEM_CIMPL_PROTO_1(iemCImpl_iret_64bit, IEMMODE, enmEffOpSize);
3868	IEM_CIMPL_PROTO_1(iemCImpl_iret, IEMMODE, enmEffOpSize);
3869	IEM_CIMPL_PROTO_0(iemCImpl_loadall286);
3870	IEM_CIMPL_PROTO_0(iemCImpl_syscall);
3871	IEM_CIMPL_PROTO_0(iemCImpl_sysret);
3872	IEM_CIMPL_PROTO_0(iemCImpl_sysenter);
3873	IEM_CIMPL_PROTO_1(iemCImpl_sysexit, IEMMODE, enmEffOpSize);
3874	IEM_CIMPL_PROTO_2(iemCImpl_LoadSReg, uint8_t, iSegReg, uint16_t, uSel);
3875	IEM_CIMPL_PROTO_2(iemCImpl_load_SReg, uint8_t, iSegReg, uint16_t, uSel);
3876	IEM_CIMPL_PROTO_2(iemCImpl_pop_Sreg, uint8_t, iSegReg, IEMMODE, enmEffOpSize);
3877	IEM_CIMPL_PROTO_5(iemCImpl_load_SReg_Greg, uint16_t, uSel, uint64_t, offSeg, uint8_t, iSegReg, uint8_t, iGReg, IEMMODE, enmEffOpSize);
3878	IEM_CIMPL_PROTO_2(iemCImpl_VerX, uint16_t, uSel, bool, fWrite);
3879	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u64, uint64_t *, pu64Dst, uint16_t, uSel, bool, fIsLar);
3880	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u16, uint16_t *, pu16Dst, uint16_t, uSel, bool, fIsLar);
3881	IEM_CIMPL_PROTO_3(iemCImpl_lgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
3882	IEM_CIMPL_PROTO_2(iemCImpl_sgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
3883	IEM_CIMPL_PROTO_3(iemCImpl_lidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
3884	IEM_CIMPL_PROTO_2(iemCImpl_sidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
3885	IEM_CIMPL_PROTO_1(iemCImpl_lldt, uint16_t, uNewLdt);
3886	IEM_CIMPL_PROTO_2(iemCImpl_sldt_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
3887	IEM_CIMPL_PROTO_2(iemCImpl_sldt_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
3888	IEM_CIMPL_PROTO_1(iemCImpl_ltr, uint16_t, uNewTr);
3889	IEM_CIMPL_PROTO_2(iemCImpl_str_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
3890	IEM_CIMPL_PROTO_2(iemCImpl_str_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
3891	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Cd, uint8_t, iGReg, uint8_t, iCrReg);
3892	IEM_CIMPL_PROTO_2(iemCImpl_smsw_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
3893	IEM_CIMPL_PROTO_2(iemCImpl_smsw_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
3894	IEM_CIMPL_PROTO_4(iemCImpl_load_CrX, uint8_t, iCrReg, uint64_t, uNewCrX, IEMACCESSCRX, enmAccessCrX, uint8_t, iGReg);
3895	IEM_CIMPL_PROTO_2(iemCImpl_mov_Cd_Rd, uint8_t, iCrReg, uint8_t, iGReg);
3896	IEM_CIMPL_PROTO_2(iemCImpl_lmsw, uint16_t, u16NewMsw, RTGCPTR, GCPtrEffDst);
3897	IEM_CIMPL_PROTO_0(iemCImpl_clts);
3898	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Dd, uint8_t, iGReg, uint8_t, iDrReg);
3899	IEM_CIMPL_PROTO_2(iemCImpl_mov_Dd_Rd, uint8_t, iDrReg, uint8_t, iGReg);
3900	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Td, uint8_t, iGReg, uint8_t, iTrReg);
3901	IEM_CIMPL_PROTO_2(iemCImpl_mov_Td_Rd, uint8_t, iTrReg, uint8_t, iGReg);
3902	IEM_CIMPL_PROTO_1(iemCImpl_invlpg, RTGCPTR, GCPtrPage);
3903	IEM_CIMPL_PROTO_3(iemCImpl_invpcid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvpcidDesc, uint64_t, uInvpcidType);
3904	IEM_CIMPL_PROTO_0(iemCImpl_invd);
3905	IEM_CIMPL_PROTO_0(iemCImpl_wbinvd);
3906	IEM_CIMPL_PROTO_0(iemCImpl_rsm);
3907	IEM_CIMPL_PROTO_0(iemCImpl_rdtsc);
3908	IEM_CIMPL_PROTO_0(iemCImpl_rdtscp);
3909	IEM_CIMPL_PROTO_0(iemCImpl_rdpmc);
3910	IEM_CIMPL_PROTO_0(iemCImpl_rdmsr);
3911	IEM_CIMPL_PROTO_0(iemCImpl_wrmsr);
3912	IEM_CIMPL_PROTO_3(iemCImpl_in, uint16_t, u16Port, bool, fImm, uint8_t, cbReg);
3913	IEM_CIMPL_PROTO_1(iemCImpl_in_eAX_DX, uint8_t, cbReg);
3914	IEM_CIMPL_PROTO_3(iemCImpl_out, uint16_t, u16Port, bool, fImm, uint8_t, cbReg);
3915	IEM_CIMPL_PROTO_1(iemCImpl_out_DX_eAX, uint8_t, cbReg);
3916	IEM_CIMPL_PROTO_0(iemCImpl_cli);
3917	IEM_CIMPL_PROTO_0(iemCImpl_sti);
3918	IEM_CIMPL_PROTO_0(iemCImpl_hlt);
3919	IEM_CIMPL_PROTO_1(iemCImpl_monitor, uint8_t, iEffSeg);
3920	IEM_CIMPL_PROTO_0(iemCImpl_mwait);
3921	IEM_CIMPL_PROTO_0(iemCImpl_swapgs);
3922	IEM_CIMPL_PROTO_0(iemCImpl_cpuid);
3923	IEM_CIMPL_PROTO_1(iemCImpl_aad, uint8_t, bImm);
3924	IEM_CIMPL_PROTO_1(iemCImpl_aam, uint8_t, bImm);
3925	IEM_CIMPL_PROTO_0(iemCImpl_daa);
3926	IEM_CIMPL_PROTO_0(iemCImpl_das);
3927	IEM_CIMPL_PROTO_0(iemCImpl_aaa);
3928	IEM_CIMPL_PROTO_0(iemCImpl_aas);
3929	IEM_CIMPL_PROTO_3(iemCImpl_bound_16, int16_t, idxArray, int16_t, idxLowerBound, int16_t, idxUpperBound);
3930	IEM_CIMPL_PROTO_3(iemCImpl_bound_32, int32_t, idxArray, int32_t, idxLowerBound, int32_t, idxUpperBound);
3931	IEM_CIMPL_PROTO_0(iemCImpl_xgetbv);
3932	IEM_CIMPL_PROTO_0(iemCImpl_xsetbv);
3933	IEM_CIMPL_PROTO_4(iemCImpl_cmpxchg16b_fallback_rendezvous, PRTUINT128U, pu128Dst, PRTUINT128U, pu128RaxRdx,
3934	PRTUINT128U, pu128RbxRcx, uint32_t *, pEFlags);
3935	IEM_CIMPL_PROTO_2(iemCImpl_clflush_clflushopt, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
3936	IEM_CIMPL_PROTO_1(iemCImpl_finit, bool, fCheckXcpts);
3937	IEM_CIMPL_PROTO_3(iemCImpl_fxsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
3938	IEM_CIMPL_PROTO_3(iemCImpl_fxrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
3939	IEM_CIMPL_PROTO_3(iemCImpl_xsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
3940	IEM_CIMPL_PROTO_3(iemCImpl_xrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
3941	IEM_CIMPL_PROTO_2(iemCImpl_stmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
3942	IEM_CIMPL_PROTO_2(iemCImpl_vstmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
3943	IEM_CIMPL_PROTO_2(iemCImpl_ldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
3944	IEM_CIMPL_PROTO_3(iemCImpl_fnstenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
3945	IEM_CIMPL_PROTO_3(iemCImpl_fnsave, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
3946	IEM_CIMPL_PROTO_3(iemCImpl_fldenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
3947	IEM_CIMPL_PROTO_3(iemCImpl_frstor, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
3948	IEM_CIMPL_PROTO_1(iemCImpl_fldcw, uint16_t, u16Fcw);
3949	IEM_CIMPL_PROTO_1(iemCImpl_fxch_underflow, uint8_t, iStReg);
3950	IEM_CIMPL_PROTO_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, PFNIEMAIMPLFPUR80EFL, pfnAImpl, bool, fPop);
3951	/** @} */
3952
3953	/** @name IEMAllCImplStrInstr.cpp.h
3954	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/' -e 's/RT_CONCAT4(//' \
3955	* -e 's/,ADDR_SIZE)/64/g' -e 's/,OP_SIZE,/64/g' -e 's/,OP_rAX,/rax/g' IEMAllCImplStrInstr.cpp.h
3956	* @{ */
3957	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr16, uint8_t, iEffSeg);
3958	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr16, uint8_t, iEffSeg);
3959	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m16);
3960	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m16);
3961	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr16, uint8_t, iEffSeg);
3962	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m16);
3963	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m16, int8_t, iEffSeg);
3964	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr16, bool, fIoChecked);
3965	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr16, bool, fIoChecked);
3966	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
3967	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
3968
3969	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr16, uint8_t, iEffSeg);
3970	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr16, uint8_t, iEffSeg);
3971	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m16);
3972	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m16);
3973	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr16, uint8_t, iEffSeg);
3974	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m16);
3975	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m16, int8_t, iEffSeg);
3976	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr16, bool, fIoChecked);
3977	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr16, bool, fIoChecked);
3978	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
3979	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
3980
3981	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr16, uint8_t, iEffSeg);
3982	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr16, uint8_t, iEffSeg);
3983	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m16);
3984	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m16);
3985	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr16, uint8_t, iEffSeg);
3986	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m16);
3987	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m16, int8_t, iEffSeg);
3988	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr16, bool, fIoChecked);
3989	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr16, bool, fIoChecked);
3990	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
3991	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
3992
3993
3994	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr32, uint8_t, iEffSeg);
3995	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr32, uint8_t, iEffSeg);
3996	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m32);
3997	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m32);
3998	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr32, uint8_t, iEffSeg);
3999	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m32);
4000	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m32, int8_t, iEffSeg);
4001	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr32, bool, fIoChecked);
4002	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr32, bool, fIoChecked);
4003	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4004	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4005
4006	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr32, uint8_t, iEffSeg);
4007	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr32, uint8_t, iEffSeg);
4008	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m32);
4009	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m32);
4010	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr32, uint8_t, iEffSeg);
4011	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m32);
4012	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m32, int8_t, iEffSeg);
4013	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr32, bool, fIoChecked);
4014	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr32, bool, fIoChecked);
4015	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4016	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4017
4018	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr32, uint8_t, iEffSeg);
4019	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr32, uint8_t, iEffSeg);
4020	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m32);
4021	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m32);
4022	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr32, uint8_t, iEffSeg);
4023	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m32);
4024	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m32, int8_t, iEffSeg);
4025	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr32, bool, fIoChecked);
4026	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr32, bool, fIoChecked);
4027	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4028	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4029
4030	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr32, uint8_t, iEffSeg);
4031	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr32, uint8_t, iEffSeg);
4032	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m32);
4033	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m32);
4034	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr32, uint8_t, iEffSeg);
4035	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m32);
4036	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m32, int8_t, iEffSeg);
4037	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr32, bool, fIoChecked);
4038	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr32, bool, fIoChecked);
4039	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4040	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4041
4042
4043	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr64, uint8_t, iEffSeg);
4044	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr64, uint8_t, iEffSeg);
4045	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m64);
4046	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m64);
4047	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr64, uint8_t, iEffSeg);
4048	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m64);
4049	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m64, int8_t, iEffSeg);
4050	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr64, bool, fIoChecked);
4051	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr64, bool, fIoChecked);
4052	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4053	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4054
4055	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr64, uint8_t, iEffSeg);
4056	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr64, uint8_t, iEffSeg);
4057	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m64);
4058	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m64);
4059	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr64, uint8_t, iEffSeg);
4060	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m64);
4061	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m64, int8_t, iEffSeg);
4062	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr64, bool, fIoChecked);
4063	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr64, bool, fIoChecked);
4064	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4065	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4066
4067	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr64, uint8_t, iEffSeg);
4068	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr64, uint8_t, iEffSeg);
4069	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m64);
4070	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m64);
4071	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr64, uint8_t, iEffSeg);
4072	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m64);
4073	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m64, int8_t, iEffSeg);
4074	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr64, bool, fIoChecked);
4075	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr64, bool, fIoChecked);
4076	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4077	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4078
4079	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr64, uint8_t, iEffSeg);
4080	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr64, uint8_t, iEffSeg);
4081	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m64);
4082	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m64);
4083	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr64, uint8_t, iEffSeg);
4084	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m64);
4085	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m64, int8_t, iEffSeg);
4086	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr64, bool, fIoChecked);
4087	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr64, bool, fIoChecked);
4088	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4089	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4090	/** @} */
4091
4092	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
4093	VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT;
4094	VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT;
4095	VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT;
4096	VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT;
4097	VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT;
4098	VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
4099	VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALK pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT;
4100	VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT;
4101	VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT;
4102	VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
4103	bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT;
4104	VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
4105	bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT;
4106	VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4107	VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4108	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4109	VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4110	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4111	VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4112	VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT;
4113	VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
4114	RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT;
4115	VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT;
4116	VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT;
4117	VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT;
4118	uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT;
4119	void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT;
4120	VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
4121	uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT;
4122	bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT;
4123	IEM_CIMPL_PROTO_0(iemCImpl_vmxoff);
4124	IEM_CIMPL_PROTO_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon);
4125	IEM_CIMPL_PROTO_0(iemCImpl_vmlaunch);
4126	IEM_CIMPL_PROTO_0(iemCImpl_vmresume);
4127	IEM_CIMPL_PROTO_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
4128	IEM_CIMPL_PROTO_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
4129	IEM_CIMPL_PROTO_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
4130	IEM_CIMPL_PROTO_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField);
4131	IEM_CIMPL_PROTO_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField);
4132	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField);
4133	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg32, uint32_t *, pu32Dst, uint32_t, u32VmcsField);
4134	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField);
4135	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField);
4136	IEM_CIMPL_PROTO_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType);
4137	IEM_CIMPL_PROTO_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType);
4138	IEM_CIMPL_PROTO_0(iemCImpl_vmx_pause);
4139	#endif
4140
4141	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4142	VBOXSTRICTRC iemSvmVmexit(PVMCPUCC pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2) RT_NOEXCEPT;
4143	VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPUCC pVCpu, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr, uint64_t uCr2) RT_NOEXCEPT;
4144	VBOXSTRICTRC iemSvmHandleIOIntercept(PVMCPUCC pVCpu, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
4145	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, uint8_t cbInstr) RT_NOEXCEPT;
4146	VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPUCC pVCpu, uint32_t idMsr, bool fWrite) RT_NOEXCEPT;
4147	IEM_CIMPL_PROTO_0(iemCImpl_vmrun);
4148	IEM_CIMPL_PROTO_0(iemCImpl_vmload);
4149	IEM_CIMPL_PROTO_0(iemCImpl_vmsave);
4150	IEM_CIMPL_PROTO_0(iemCImpl_clgi);
4151	IEM_CIMPL_PROTO_0(iemCImpl_stgi);
4152	IEM_CIMPL_PROTO_0(iemCImpl_invlpga);
4153	IEM_CIMPL_PROTO_0(iemCImpl_skinit);
4154	IEM_CIMPL_PROTO_0(iemCImpl_svm_pause);
4155	#endif
4156
4157	IEM_CIMPL_PROTO_0(iemCImpl_vmcall); /* vmx */
4158	IEM_CIMPL_PROTO_0(iemCImpl_vmmcall); /* svm */
4159	IEM_CIMPL_PROTO_1(iemCImpl_Hypercall, uint16_t, uDisOpcode); /* both */
4160
4161
4162	extern const PFNIEMOP g_apfnOneByteMap[256];
4163
4164	/** @} */
4165
4166	RT_C_DECLS_END
4167
4168	#endif /* !VMM_INCLUDED_SRC_include_IEMInternal_h */
4169

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source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h@ 96821

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