IEMInternal.h@ 99949

Last change on this file since 99949 was 99930, checked in by vboxsync, 21 months ago
VMM/IEM: More recompiler work. bugref:10369
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1	/* $Id: IEMInternal.h 99930 2023-05-23 09:53:04Z vboxsync $ */
2	/** @file
3	* IEM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2011-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_IEMInternal_h
29	#define VMM_INCLUDED_SRC_include_IEMInternal_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#include <VBox/vmm/cpum.h>
35	#include <VBox/vmm/iem.h>
36	#include <VBox/vmm/pgm.h>
37	#include <VBox/vmm/stam.h>
38	#include <VBox/param.h>
39
40	#include <iprt/setjmp-without-sigmask.h>
41
42
43	RT_C_DECLS_BEGIN
44
45
46	/** @defgroup grp_iem_int Internals
47	* @ingroup grp_iem
48	* @internal
49	* @{
50	*/
51
52	/** For expanding symbol in slickedit and other products tagging and
53	* crossreferencing IEM symbols. */
54	#ifndef IEM_STATIC
55	# define IEM_STATIC static
56	#endif
57
58	/** @def IEM_WITH_SETJMP
59	* Enables alternative status code handling using setjmps.
60	*
61	* This adds a bit of expense via the setjmp() call since it saves all the
62	* non-volatile registers. However, it eliminates return code checks and allows
63	* for more optimal return value passing (return regs instead of stack buffer).
64	*/
65	#if defined(DOXYGEN_RUNNING) \|\| defined(RT_OS_WINDOWS) \|\| 1
66	# define IEM_WITH_SETJMP
67	#endif
68
69	/** @def IEM_WITH_THROW_CATCH
70	* Enables using C++ throw/catch as an alternative to setjmp/longjmp in user
71	* mode code when IEM_WITH_SETJMP is in effect.
72	*
73	* With GCC 11.3.1 and code TLB on linux, using throw/catch instead of
74	* setjmp/long resulted in bs2-test-1 running 3.00% faster and all but on test
75	* result value improving by more than 1%. (Best out of three.)
76	*
77	* With Visual C++ 2019 and code TLB on windows, using throw/catch instead of
78	* setjmp/long resulted in bs2-test-1 running 3.68% faster and all but some of
79	* the MMIO and CPUID tests ran noticeably faster. Variation is greater than on
80	* Linux, but it should be quite a bit faster for normal code.
81	*/
82	#if (defined(IEM_WITH_SETJMP) && defined(IN_RING3) && (defined(__GNUC__) \|\| defined(_MSC_VER))) \
83	\|\| defined(DOXYGEN_RUNNING)
84	# define IEM_WITH_THROW_CATCH
85	#endif
86
87	/** @def IEM_DO_LONGJMP
88	*
89	* Wrapper around longjmp / throw.
90	*
91	* @param a_pVCpu The CPU handle.
92	* @param a_rc The status code jump back with / throw.
93	*/
94	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
95	# ifdef IEM_WITH_THROW_CATCH
96	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) throw int(a_rc)
97	# else
98	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) longjmp(*(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf), (a_rc))
99	# endif
100	#endif
101
102	/** For use with IEM function that may do a longjmp (when enabled).
103	*
104	* Visual C++ has trouble longjmp'ing from/over functions with the noexcept
105	* attribute. So, we indicate that function that may be part of a longjmp may
106	* throw "exceptions" and that the compiler should definitely not generate and
107	* std::terminate calling unwind code.
108	*
109	* Here is one example of this ending in std::terminate:
110	* @code{.txt}
111	00 00000041`cadfda10 00007ffc`5d5a1f9f ucrtbase!abort+0x4e
112	01 00000041`cadfda40 00007ffc`57af229a ucrtbase!terminate+0x1f
113	02 00000041`cadfda70 00007ffb`eec91030 VCRUNTIME140!__std_terminate+0xa [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\ehhelpers.cpp @ 192]
114	03 00000041`cadfdaa0 00007ffb`eec92c6d VCRUNTIME140_1!_CallSettingFrame+0x20 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\handlers.asm @ 50]
115	04 00000041`cadfdad0 00007ffb`eec93ae5 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToState+0x241 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 1085]
116	05 00000041`cadfdc00 00007ffb`eec92258 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToEmptyState+0x2d [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 218]
117	06 00000041`cadfdc30 00007ffb`eec940e9 VCRUNTIME140_1!__InternalCxxFrameHandler<__FrameHandler4>+0x194 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 304]
118	07 00000041`cadfdcd0 00007ffc`5f9f249f VCRUNTIME140_1!__CxxFrameHandler4+0xa9 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 290]
119	08 00000041`cadfdd40 00007ffc`5f980939 ntdll!RtlpExecuteHandlerForUnwind+0xf
120	09 00000041`cadfdd70 00007ffc`5f9a0edd ntdll!RtlUnwindEx+0x339
121	0a 00000041`cadfe490 00007ffc`57aff976 ntdll!RtlUnwind+0xcd
122	0b 00000041`cadfea00 00007ffb`e1b5de01 VCRUNTIME140!__longjmp_internal+0xe6 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\longjmp.asm @ 140]
123	0c (Inline Function) --------`-------- VBoxVMM!iemOpcodeGetNextU8SlowJmp+0x95 [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 1155]
124	0d 00000041`cadfea50 00007ffb`e1b60f6b VBoxVMM!iemOpcodeGetNextU8Jmp+0xc1 [L:\vbox-intern\src\VBox\VMM\include\IEMInline.h @ 402]
125	0e 00000041`cadfea90 00007ffb`e1cc6201 VBoxVMM!IEMExecForExits+0xdb [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 10185]
126	0f 00000041`cadfec70 00007ffb`e1d0df8d VBoxVMM!EMHistoryExec+0x4f1 [L:\vbox-intern\src\VBox\VMM\VMMAll\EMAll.cpp @ 452]
127	10 00000041`cadfed60 00007ffb`e1d0d4c0 VBoxVMM!nemR3WinHandleExitCpuId+0x79d [L:\vbox-intern\src\VBox\VMM\VMMAll\NEMAllNativeTemplate-win.cpp.h @ 1829] @encode
128	@endcode
129	*
130	* @see https://developercommunity.visualstudio.com/t/fragile-behavior-of-longjmp-called-from-noexcept-f/1532859
131	*/
132	#if defined(IEM_WITH_SETJMP) && (defined(_MSC_VER) \|\| defined(IEM_WITH_THROW_CATCH))
133	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT_EX(false)
134	#else
135	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT
136	#endif
137
138	#define IEM_IMPLEMENTS_TASKSWITCH
139
140	/** @def IEM_WITH_3DNOW
141	* Includes the 3DNow decoding. */
142	#if (!defined(IEM_WITH_3DNOW) && !defined(IEM_WITHOUT_3DNOW)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
143	# define IEM_WITH_3DNOW
144	#endif
145
146	/** @def IEM_WITH_THREE_0F_38
147	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
148	#if (!defined(IEM_WITH_THREE_0F_38) && !defined(IEM_WITHOUT_THREE_0F_38)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
149	# define IEM_WITH_THREE_0F_38
150	#endif
151
152	/** @def IEM_WITH_THREE_0F_3A
153	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
154	#if (!defined(IEM_WITH_THREE_0F_3A) && !defined(IEM_WITHOUT_THREE_0F_3A)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
155	# define IEM_WITH_THREE_0F_3A
156	#endif
157
158	/** @def IEM_WITH_VEX
159	* Includes the VEX decoding. */
160	#if (!defined(IEM_WITH_VEX) && !defined(IEM_WITHOUT_VEX)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
161	# define IEM_WITH_VEX
162	#endif
163
164	/** @def IEM_CFG_TARGET_CPU
165	* The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
166	*
167	* By default we allow this to be configured by the user via the
168	* CPUM/GuestCpuName config string, but this comes at a slight cost during
169	* decoding. So, for applications of this code where there is no need to
170	* be dynamic wrt target CPU, just modify this define.
171	*/
172	#if !defined(IEM_CFG_TARGET_CPU) \|\| defined(DOXYGEN_RUNNING)
173	# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
174	#endif
175
176	//#define IEM_WITH_CODE_TLB // - work in progress
177	//#define IEM_WITH_DATA_TLB // - work in progress
178
179
180	/** @def IEM_USE_UNALIGNED_DATA_ACCESS
181	* Use unaligned accesses instead of elaborate byte assembly. */
182	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86) \|\| defined(DOXYGEN_RUNNING)
183	# define IEM_USE_UNALIGNED_DATA_ACCESS
184	#endif
185
186	//#define IEM_LOG_MEMORY_WRITES
187
188	#if !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
189	/** Instruction statistics. */
190	typedef struct IEMINSTRSTATS
191	{
192	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
193	# include "IEMInstructionStatisticsTmpl.h"
194	# undef IEM_DO_INSTR_STAT
195	} IEMINSTRSTATS;
196	#else
197	struct IEMINSTRSTATS;
198	typedef struct IEMINSTRSTATS IEMINSTRSTATS;
199	#endif
200	/** Pointer to IEM instruction statistics. */
201	typedef IEMINSTRSTATS *PIEMINSTRSTATS;
202
203
204	/** @name IEMTARGETCPU_EFL_BEHAVIOR_XXX - IEMCPU::aidxTargetCpuEflFlavour
205	* @{ */
206	#define IEMTARGETCPU_EFL_BEHAVIOR_NATIVE 0 /*< Native x86 EFLAGS result; Intel EFLAGS when on non-x86 hosts. /
207	#define IEMTARGETCPU_EFL_BEHAVIOR_INTEL 1 /*< Intel EFLAGS result. /
208	#define IEMTARGETCPU_EFL_BEHAVIOR_AMD 2 /*< AMD EFLAGS result /
209	#define IEMTARGETCPU_EFL_BEHAVIOR_RESERVED 3 /*< Reserved/dummy entry slot that's the same as 0. /
210	#define IEMTARGETCPU_EFL_BEHAVIOR_MASK 3 /*< For masking the index before use. /
211	/** Selects the right variant from a_aArray.
212	* pVCpu is implicit in the caller context. */
213	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT(a_aArray) \
214	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[1] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
215	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for when no native worker can
216	* be used because the host CPU does not support the operation. */
217	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_NON_NATIVE(a_aArray) \
218	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
219	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for a two dimentional
220	* array paralleling IEMCPU::aidxTargetCpuEflFlavour and a single bit index
221	* into the two.
222	* @sa IEM_SELECT_NATIVE_OR_FALLBACK */
223	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
224	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
225	(a_aaArray[a_fNative][pVCpu->iem.s.aidxTargetCpuEflFlavour[a_fNative] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
226	#else
227	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
228	(a_aaArray[0][pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
229	#endif
230	/** @} */
231
232	/**
233	* Picks @a a_pfnNative or @a a_pfnFallback according to the host CPU feature
234	* indicator given by @a a_fCpumFeatureMember (CPUMFEATURES member).
235	*
236	* On non-x86 hosts, this will shortcut to the fallback w/o checking the
237	* indicator.
238	*
239	* @sa IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX
240	*/
241	#if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
242	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) \
243	(g_CpumHostFeatures.s.a_fCpumFeatureMember ? a_pfnNative : a_pfnFallback)
244	#else
245	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) (a_pfnFallback)
246	#endif
247
248
249	/**
250	* Extended operand mode that includes a representation of 8-bit.
251	*
252	* This is used for packing down modes when invoking some C instruction
253	* implementations.
254	*/
255	typedef enum IEMMODEX
256	{
257	IEMMODEX_16BIT = IEMMODE_16BIT,
258	IEMMODEX_32BIT = IEMMODE_32BIT,
259	IEMMODEX_64BIT = IEMMODE_64BIT,
260	IEMMODEX_8BIT
261	} IEMMODEX;
262	AssertCompileSize(IEMMODEX, 4);
263
264
265	/**
266	* Branch types.
267	*/
268	typedef enum IEMBRANCH
269	{
270	IEMBRANCH_JUMP = 1,
271	IEMBRANCH_CALL,
272	IEMBRANCH_TRAP,
273	IEMBRANCH_SOFTWARE_INT,
274	IEMBRANCH_HARDWARE_INT
275	} IEMBRANCH;
276	AssertCompileSize(IEMBRANCH, 4);
277
278
279	/**
280	* INT instruction types.
281	*/
282	typedef enum IEMINT
283	{
284	/** INT n instruction (opcode 0xcd imm). */
285	IEMINT_INTN = 0,
286	/** Single byte INT3 instruction (opcode 0xcc). */
287	IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
288	/** Single byte INTO instruction (opcode 0xce). */
289	IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
290	/** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
291	IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
292	} IEMINT;
293	AssertCompileSize(IEMINT, 4);
294
295
296	/**
297	* A FPU result.
298	*/
299	typedef struct IEMFPURESULT
300	{
301	/** The output value. */
302	RTFLOAT80U r80Result;
303	/** The output status. */
304	uint16_t FSW;
305	} IEMFPURESULT;
306	AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
307	/** Pointer to a FPU result. */
308	typedef IEMFPURESULT *PIEMFPURESULT;
309	/** Pointer to a const FPU result. */
310	typedef IEMFPURESULT const *PCIEMFPURESULT;
311
312
313	/**
314	* A FPU result consisting of two output values and FSW.
315	*/
316	typedef struct IEMFPURESULTTWO
317	{
318	/** The first output value. */
319	RTFLOAT80U r80Result1;
320	/** The output status. */
321	uint16_t FSW;
322	/** The second output value. */
323	RTFLOAT80U r80Result2;
324	} IEMFPURESULTTWO;
325	AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
326	AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
327	/** Pointer to a FPU result consisting of two output values and FSW. */
328	typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
329	/** Pointer to a const FPU result consisting of two output values and FSW. */
330	typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
331
332
333	/**
334	* IEM TLB entry.
335	*
336	* Lookup assembly:
337	* @code{.asm}
338	; Calculate tag.
339	mov rax, [VA]
340	shl rax, 16
341	shr rax, 16 + X86_PAGE_SHIFT
342	or rax, [uTlbRevision]
343
344	; Do indexing.
345	movzx ecx, al
346	lea rcx, [pTlbEntries + rcx]
347
348	; Check tag.
349	cmp [rcx + IEMTLBENTRY.uTag], rax
350	jne .TlbMiss
351
352	; Check access.
353	mov rax, ACCESS_FLAGS \| MAPPING_R3_NOT_VALID \| 0xffffff00
354	and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
355	cmp rax, [uTlbPhysRev]
356	jne .TlbMiss
357
358	; Calc address and we're done.
359	mov eax, X86_PAGE_OFFSET_MASK
360	and eax, [VA]
361	or rax, [rcx + IEMTLBENTRY.pMappingR3]
362	%ifdef VBOX_WITH_STATISTICS
363	inc qword [cTlbHits]
364	%endif
365	jmp .Done
366
367	.TlbMiss:
368	mov r8d, ACCESS_FLAGS
369	mov rdx, [VA]
370	mov rcx, [pVCpu]
371	call iemTlbTypeMiss
372	.Done:
373
374	@endcode
375	*
376	*/
377	typedef struct IEMTLBENTRY
378	{
379	/** The TLB entry tag.
380	* Bits 35 thru 0 are made up of the virtual address shifted right 12 bits, this
381	* is ASSUMING a virtual address width of 48 bits.
382	*
383	* Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
384	*
385	* The TLB lookup code uses the current TLB revision, which won't ever be zero,
386	* enabling an extremely cheap TLB invalidation most of the time. When the TLB
387	* revision wraps around though, the tags needs to be zeroed.
388	*
389	* @note Try use SHRD instruction? After seeing
390	* https://gmplib.org/~tege/x86-timing.pdf, maybe not.
391	*
392	* @todo This will need to be reorganized for 57-bit wide virtual address and
393	* PCID (currently 12 bits) and ASID (currently 6 bits) support. We'll
394	* have to move the TLB entry versioning entirely to the
395	* fFlagsAndPhysRev member then, 57 bit wide VAs means we'll only have
396	* 19 bits left (64 - 57 + 12 = 19) and they'll almost entire be
397	* consumed by PCID and ASID (12 + 6 = 18).
398	*/
399	uint64_t uTag;
400	/** Access flags and physical TLB revision.
401	*
402	* - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
403	* - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
404	* - Bit 2 - page tables - not user (complemented X86_PTE_US).
405	* - Bit 3 - pgm phys/virt - not directly writable.
406	* - Bit 4 - pgm phys page - not directly readable.
407	* - Bit 5 - page tables - not accessed (complemented X86_PTE_A).
408	* - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
409	* - Bit 7 - tlb entry - pMappingR3 member not valid.
410	* - Bits 63 thru 8 are used for the physical TLB revision number.
411	*
412	* We're using complemented bit meanings here because it makes it easy to check
413	* whether special action is required. For instance a user mode write access
414	* would do a "TEST fFlags, (X86_PTE_RW \| X86_PTE_US \| X86_PTE_D)" and a
415	* non-zero result would mean special handling needed because either it wasn't
416	* writable, or it wasn't user, or the page wasn't dirty. A user mode read
417	* access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
418	* need to check any PTE flag.
419	*/
420	uint64_t fFlagsAndPhysRev;
421	/** The guest physical page address. */
422	uint64_t GCPhys;
423	/** Pointer to the ring-3 mapping. */
424	R3PTRTYPE(uint8_t *) pbMappingR3;
425	#if HC_ARCH_BITS == 32
426	uint32_t u32Padding1;
427	#endif
428	} IEMTLBENTRY;
429	AssertCompileSize(IEMTLBENTRY, 32);
430	/** Pointer to an IEM TLB entry. */
431	typedef IEMTLBENTRY *PIEMTLBENTRY;
432
433	/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
434	* @{ */
435	#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /*< Page tables: Not executable. /
436	#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /*< Page tables: Not writable. /
437	#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /*< Page tables: Not user accessible (supervisor only). /
438	#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /*< Phys page: Not writable (access handler, ROM, whatever). /
439	#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /*< Phys page: Not readable (MMIO / access handler, ROM) /
440	#define IEMTLBE_F_PT_NO_ACCESSED RT_BIT_64(5) /*< Phys tables: Not accessed (need to be marked accessed). /
441	#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /*< Page tables: Not dirty (needs to be made dirty on write). /
442	#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(7) /*< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. /
443	#define IEMTLBE_F_PG_UNASSIGNED RT_BIT_64(8) /*< Phys page: Unassigned memory (not RAM, ROM, MMIO2 or MMIO). /
444	#define IEMTLBE_F_PHYS_REV UINT64_C(0xfffffffffffffe00) /*< Physical revision mask. @sa IEMTLB_PHYS_REV_INCR /
445	/** @} */
446
447
448	/**
449	* An IEM TLB.
450	*
451	* We've got two of these, one for data and one for instructions.
452	*/
453	typedef struct IEMTLB
454	{
455	/** The TLB entries.
456	* We've choosen 256 because that way we can obtain the result directly from a
457	* 8-bit register without an additional AND instruction. */
458	IEMTLBENTRY aEntries[256];
459	/** The TLB revision.
460	* This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
461	* by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
462	* the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
463	* (The revision zero indicates an invalid TLB entry.)
464	*
465	* The initial value is choosen to cause an early wraparound. */
466	uint64_t uTlbRevision;
467	/** The TLB physical address revision - shadow of PGM variable.
468	*
469	* This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
470	* incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
471	* a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
472	* as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
473	*
474	* The initial value is choosen to cause an early wraparound. */
475	uint64_t volatile uTlbPhysRev;
476
477	/* Statistics: */
478
479	/** TLB hits (VBOX_WITH_STATISTICS only). */
480	uint64_t cTlbHits;
481	/** TLB misses. */
482	uint32_t cTlbMisses;
483	/** Slow read path. */
484	uint32_t cTlbSlowReadPath;
485	#if 0
486	/** TLB misses because of tag mismatch. */
487	uint32_t cTlbMissesTag;
488	/** TLB misses because of virtual access violation. */
489	uint32_t cTlbMissesVirtAccess;
490	/** TLB misses because of dirty bit. */
491	uint32_t cTlbMissesDirty;
492	/** TLB misses because of MMIO */
493	uint32_t cTlbMissesMmio;
494	/** TLB misses because of write access handlers. */
495	uint32_t cTlbMissesWriteHandler;
496	/** TLB misses because no r3(/r0) mapping. */
497	uint32_t cTlbMissesMapping;
498	#endif
499	/** Alignment padding. */
500	uint32_t au32Padding[3+5];
501	} IEMTLB;
502	AssertCompileSizeAlignment(IEMTLB, 64);
503	/** IEMTLB::uTlbRevision increment. */
504	#define IEMTLB_REVISION_INCR RT_BIT_64(36)
505	/** IEMTLB::uTlbRevision mask. */
506	#define IEMTLB_REVISION_MASK (~(RT_BIT_64(36) - 1))
507	/** IEMTLB::uTlbPhysRev increment.
508	* @sa IEMTLBE_F_PHYS_REV */
509	#define IEMTLB_PHYS_REV_INCR RT_BIT_64(9)
510	/**
511	* Calculates the TLB tag for a virtual address.
512	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
513	* @param a_pTlb The TLB.
514	* @param a_GCPtr The virtual address.
515	*/
516	#define IEMTLB_CALC_TAG(a_pTlb, a_GCPtr) ( IEMTLB_CALC_TAG_NO_REV(a_GCPtr) \| (a_pTlb)->uTlbRevision )
517	/**
518	* Calculates the TLB tag for a virtual address but without TLB revision.
519	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
520	* @param a_GCPtr The virtual address.
521	*/
522	#define IEMTLB_CALC_TAG_NO_REV(a_GCPtr) ( (((a_GCPtr) << 16) >> (GUEST_PAGE_SHIFT + 16)) )
523	/**
524	* Converts a TLB tag value into a TLB index.
525	* @returns Index into IEMTLB::aEntries.
526	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
527	*/
528	#define IEMTLB_TAG_TO_INDEX(a_uTag) ( (uint8_t)(a_uTag) )
529	/**
530	* Converts a TLB tag value into a TLB index.
531	* @returns Index into IEMTLB::aEntries.
532	* @param a_pTlb The TLB.
533	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
534	*/
535	#define IEMTLB_TAG_TO_ENTRY(a_pTlb, a_uTag) ( &(a_pTlb)->aEntries[IEMTLB_TAG_TO_INDEX(a_uTag)] )
536
537
538	/** Pointer to a translation block. */
539	typedef struct IEMTB *PIEMTB;
540
541
542	/**
543	* The per-CPU IEM state.
544	*/
545	typedef struct IEMCPU
546	{
547	/** Info status code that needs to be propagated to the IEM caller.
548	* This cannot be passed internally, as it would complicate all success
549	* checks within the interpreter making the code larger and almost impossible
550	* to get right. Instead, we'll store status codes to pass on here. Each
551	* source of these codes will perform appropriate sanity checks. */
552	int32_t rcPassUp; /* 0x00 */
553
554	/** The current CPU execution mode (CS). */
555	IEMMODE enmCpuMode; /* 0x04 */
556	/** The CPL. */
557	uint8_t uCpl; /* 0x05 */
558
559	/** Whether to bypass access handlers or not. */
560	bool fBypassHandlers : 1; /* 0x06.0 */
561	/** Whether to disregard the lock prefix (implied or not). */
562	bool fDisregardLock : 1; /* 0x06.1 */
563	/** Whether there are pending hardware instruction breakpoints. */
564	bool fPendingInstructionBreakpoints : 1; /* 0x06.2 */
565	/** Whether there are pending hardware data breakpoints. */
566	bool fPendingDataBreakpoints : 1; /* 0x06.3 */
567	/** Whether there are pending hardware I/O breakpoints. */
568	bool fPendingIoBreakpoints : 1; /* 0x06.4 */
569
570	/* Unused/padding */
571	bool fUnused; /* 0x07 */
572
573	/** @name Decoder state.
574	* @{ */
575	#ifndef IEM_WITH_OPAQUE_DECODER_STATE
576	# ifdef IEM_WITH_CODE_TLB
577	/** The offset of the next instruction byte. */
578	uint32_t offInstrNextByte; /* 0x08 */
579	/** The number of bytes available at pbInstrBuf for the current instruction.
580	* This takes the max opcode length into account so that doesn't need to be
581	* checked separately. */
582	uint32_t cbInstrBuf; /* 0x0c */
583	/** Pointer to the page containing RIP, user specified buffer or abOpcode.
584	* This can be NULL if the page isn't mappable for some reason, in which
585	* case we'll do fallback stuff.
586	*
587	* If we're executing an instruction from a user specified buffer,
588	* IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
589	* aligned pointer but pointer to the user data.
590	*
591	* For instructions crossing pages, this will start on the first page and be
592	* advanced to the next page by the time we've decoded the instruction. This
593	* therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
594	*/
595	uint8_t const pbInstrBuf; / 0x10 */
596	# if ARCH_BITS == 32
597	uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
598	# endif
599	/** The program counter corresponding to pbInstrBuf.
600	* This is set to a non-canonical address when we need to invalidate it. */
601	uint64_t uInstrBufPc; /* 0x18 */
602	/** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
603	* This takes the CS segment limit into account. */
604	uint16_t cbInstrBufTotal; /* 0x20 */
605	/** Offset into pbInstrBuf of the first byte of the current instruction.
606	* Can be negative to efficiently handle cross page instructions. */
607	int16_t offCurInstrStart; /* 0x22 */
608
609	/** The prefix mask (IEM_OP_PRF_XXX). */
610	uint32_t fPrefixes; /* 0x24 */
611	/** The extra REX ModR/M register field bit (REX.R << 3). */
612	uint8_t uRexReg; /* 0x28 */
613	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
614	* (REX.B << 3). */
615	uint8_t uRexB; /* 0x29 */
616	/** The extra REX SIB index field bit (REX.X << 3). */
617	uint8_t uRexIndex; /* 0x2a */
618
619	/** The effective segment register (X86_SREG_XXX). */
620	uint8_t iEffSeg; /* 0x2b */
621
622	/** The offset of the ModR/M byte relative to the start of the instruction. */
623	uint8_t offModRm; /* 0x2c */
624	# else /* !IEM_WITH_CODE_TLB */
625	/** The size of what has currently been fetched into abOpcode. */
626	uint8_t cbOpcode; /* 0x08 */
627	/** The current offset into abOpcode. */
628	uint8_t offOpcode; /* 0x09 */
629	/** The offset of the ModR/M byte relative to the start of the instruction. */
630	uint8_t offModRm; /* 0x0a */
631
632	/** The effective segment register (X86_SREG_XXX). */
633	uint8_t iEffSeg; /* 0x0b */
634
635	/** The prefix mask (IEM_OP_PRF_XXX). */
636	uint32_t fPrefixes; /* 0x0c */
637	/** The extra REX ModR/M register field bit (REX.R << 3). */
638	uint8_t uRexReg; /* 0x10 */
639	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
640	* (REX.B << 3). */
641	uint8_t uRexB; /* 0x11 */
642	/** The extra REX SIB index field bit (REX.X << 3). */
643	uint8_t uRexIndex; /* 0x12 */
644
645	# endif /* !IEM_WITH_CODE_TLB */
646
647	/** The effective operand mode. */
648	IEMMODE enmEffOpSize; /* 0x2d, 0x13 */
649	/** The default addressing mode. */
650	IEMMODE enmDefAddrMode; /* 0x2e, 0x14 */
651	/** The effective addressing mode. */
652	IEMMODE enmEffAddrMode; /* 0x2f, 0x15 */
653	/** The default operand mode. */
654	IEMMODE enmDefOpSize; /* 0x30, 0x16 */
655
656	/** Prefix index (VEX.pp) for two byte and three byte tables. */
657	uint8_t idxPrefix; /* 0x31, 0x17 */
658	/** 3rd VEX/EVEX/XOP register.
659	* Please use IEM_GET_EFFECTIVE_VVVV to access. */
660	uint8_t uVex3rdReg; /* 0x32, 0x18 */
661	/** The VEX/EVEX/XOP length field. */
662	uint8_t uVexLength; /* 0x33, 0x19 */
663	/** Additional EVEX stuff. */
664	uint8_t fEvexStuff; /* 0x34, 0x1a */
665
666	/** Explicit alignment padding. */
667	uint8_t abAlignment2a[1]; /* 0x35, 0x1b */
668	/** The FPU opcode (FOP). */
669	uint16_t uFpuOpcode; /* 0x36, 0x1c */
670	# ifndef IEM_WITH_CODE_TLB
671	/** Explicit alignment padding. */
672	uint8_t abAlignment2b[2]; /* 0x1e */
673	# endif
674
675	/** The opcode bytes. */
676	uint8_t abOpcode[15]; /* 0x48, 0x20 */
677	/** Explicit alignment padding. */
678	# ifdef IEM_WITH_CODE_TLB
679	uint8_t abAlignment2c[0x48 - 0x47]; /* 0x37 */
680	# else
681	uint8_t abAlignment2c[0x48 - 0x2f]; /* 0x2f */
682	# endif
683	#else /* IEM_WITH_OPAQUE_DECODER_STATE */
684	uint8_t abOpaqueDecoder[0x48 - 0x8];
685	#endif /* IEM_WITH_OPAQUE_DECODER_STATE */
686	/** @} */
687
688
689	/** The flags of the current exception / interrupt. */
690	uint32_t fCurXcpt; /* 0x48, 0x48 */
691	/** The current exception / interrupt. */
692	uint8_t uCurXcpt;
693	/** Exception / interrupt recursion depth. */
694	int8_t cXcptRecursions;
695
696	/** The number of active guest memory mappings. */
697	uint8_t cActiveMappings;
698	/** The next unused mapping index. */
699	uint8_t iNextMapping;
700	/** Records for tracking guest memory mappings. */
701	struct
702	{
703	/** The address of the mapped bytes. */
704	void *pv;
705	/** The access flags (IEM_ACCESS_XXX).
706	* IEM_ACCESS_INVALID if the entry is unused. */
707	uint32_t fAccess;
708	#if HC_ARCH_BITS == 64
709	uint32_t u32Alignment4; /*< Alignment padding. /
710	#endif
711	} aMemMappings[3];
712
713	/** Locking records for the mapped memory. */
714	union
715	{
716	PGMPAGEMAPLOCK Lock;
717	uint64_t au64Padding[2];
718	} aMemMappingLocks[3];
719
720	/** Bounce buffer info.
721	* This runs in parallel to aMemMappings. */
722	struct
723	{
724	/** The physical address of the first byte. */
725	RTGCPHYS GCPhysFirst;
726	/** The physical address of the second page. */
727	RTGCPHYS GCPhysSecond;
728	/** The number of bytes in the first page. */
729	uint16_t cbFirst;
730	/** The number of bytes in the second page. */
731	uint16_t cbSecond;
732	/** Whether it's unassigned memory. */
733	bool fUnassigned;
734	/** Explicit alignment padding. */
735	bool afAlignment5[3];
736	} aMemBbMappings[3];
737
738	/* Ensure that aBounceBuffers are aligned at a 32 byte boundrary. */
739	uint64_t abAlignment7[1];
740
741	/** Bounce buffer storage.
742	* This runs in parallel to aMemMappings and aMemBbMappings. */
743	struct
744	{
745	uint8_t ab[512];
746	} aBounceBuffers[3];
747
748
749	/** Pointer set jump buffer - ring-3 context. */
750	R3PTRTYPE(jmp_buf *) pJmpBufR3;
751	/** Pointer set jump buffer - ring-0 context. */
752	R0PTRTYPE(jmp_buf *) pJmpBufR0;
753
754	/** @todo Should move this near @a fCurXcpt later. */
755	/** The CR2 for the current exception / interrupt. */
756	uint64_t uCurXcptCr2;
757	/** The error code for the current exception / interrupt. */
758	uint32_t uCurXcptErr;
759
760	/** @name Statistics
761	* @{ */
762	/** The number of instructions we've executed. */
763	uint32_t cInstructions;
764	/** The number of potential exits. */
765	uint32_t cPotentialExits;
766	/** The number of bytes data or stack written (mostly for IEMExecOneEx).
767	* This may contain uncommitted writes. */
768	uint32_t cbWritten;
769	/** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
770	uint32_t cRetInstrNotImplemented;
771	/** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
772	uint32_t cRetAspectNotImplemented;
773	/** Counts informational statuses returned (other than VINF_SUCCESS). */
774	uint32_t cRetInfStatuses;
775	/** Counts other error statuses returned. */
776	uint32_t cRetErrStatuses;
777	/** Number of times rcPassUp has been used. */
778	uint32_t cRetPassUpStatus;
779	/** Number of times RZ left with instruction commit pending for ring-3. */
780	uint32_t cPendingCommit;
781	/** Number of long jumps. */
782	uint32_t cLongJumps;
783	/** @} */
784
785	/** @name Target CPU information.
786	* @{ */
787	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
788	/** The target CPU. */
789	uint8_t uTargetCpu;
790	#else
791	uint8_t bTargetCpuPadding;
792	#endif
793	/** For selecting assembly works matching the target CPU EFLAGS behaviour, see
794	* IEMTARGETCPU_EFL_BEHAVIOR_XXX for values, with the 1st entry for when no
795	* native host support and the 2nd for when there is.
796	*
797	* The two values are typically indexed by a g_CpumHostFeatures bit.
798	*
799	* This is for instance used for the BSF & BSR instructions where AMD and
800	* Intel CPUs produce different EFLAGS. */
801	uint8_t aidxTargetCpuEflFlavour[2];
802
803	/** The CPU vendor. */
804	CPUMCPUVENDOR enmCpuVendor;
805	/** @} */
806
807	/** @name Host CPU information.
808	* @{ */
809	/** The CPU vendor. */
810	CPUMCPUVENDOR enmHostCpuVendor;
811	/** @} */
812
813	/** Counts RDMSR \#GP(0) LogRel(). */
814	uint8_t cLogRelRdMsr;
815	/** Counts WRMSR \#GP(0) LogRel(). */
816	uint8_t cLogRelWrMsr;
817	/** Alignment padding. */
818	uint8_t abAlignment8[42];
819
820	/** @name Recompilation
821	* @{ */
822	/** Pointer to the current translation block.
823	* This can either be one being executed or one being compiled. */
824	R3PTRTYPE(PIEMTB) pCurTbR3;
825	/** Spaced reserved for recompiler data / alignment. */
826	uint64_t auRecompilerStuff[7];
827	/** @} */
828
829	/** Data TLB.
830	* @remarks Must be 64-byte aligned. */
831	IEMTLB DataTlb;
832	/** Instruction TLB.
833	* @remarks Must be 64-byte aligned. */
834	IEMTLB CodeTlb;
835
836	/** Exception statistics. */
837	STAMCOUNTER aStatXcpts[32];
838	/** Interrupt statistics. */
839	uint32_t aStatInts[256];
840
841	#if defined(VBOX_WITH_STATISTICS) && !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
842	/** Instruction statistics for ring-0/raw-mode. */
843	IEMINSTRSTATS StatsRZ;
844	/** Instruction statistics for ring-3. */
845	IEMINSTRSTATS StatsR3;
846	#endif
847	} IEMCPU;
848	AssertCompileMemberOffset(IEMCPU, fCurXcpt, 0x48);
849	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 8);
850	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 16);
851	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 32);
852	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 64);
853	AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
854	AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
855
856	/** Pointer to the per-CPU IEM state. */
857	typedef IEMCPU *PIEMCPU;
858	/** Pointer to the const per-CPU IEM state. */
859	typedef IEMCPU const *PCIEMCPU;
860
861
862	/** @def IEM_GET_CTX
863	* Gets the guest CPU context for the calling EMT.
864	* @returns PCPUMCTX
865	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
866	*/
867	#define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
868
869	/** @def IEM_CTX_ASSERT
870	* Asserts that the @a a_fExtrnMbz is present in the CPU context.
871	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
872	* @param a_fExtrnMbz The mask of CPUMCTX_EXTRN_XXX flags that must be zero.
873	*/
874	#define IEM_CTX_ASSERT(a_pVCpu, a_fExtrnMbz) AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
875	("fExtrn=%#RX64 fExtrnMbz=%#RX64\n", (a_pVCpu)->cpum.GstCtx.fExtrn, \
876	(a_fExtrnMbz)))
877
878	/** @def IEM_CTX_IMPORT_RET
879	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
880	*
881	* Will call the keep to import the bits as needed.
882	*
883	* Returns on import failure.
884	*
885	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
886	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
887	*/
888	#define IEM_CTX_IMPORT_RET(a_pVCpu, a_fExtrnImport) \
889	do { \
890	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
891	{ /* likely */ } \
892	else \
893	{ \
894	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
895	AssertRCReturn(rcCtxImport, rcCtxImport); \
896	} \
897	} while (0)
898
899	/** @def IEM_CTX_IMPORT_NORET
900	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
901	*
902	* Will call the keep to import the bits as needed.
903	*
904	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
905	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
906	*/
907	#define IEM_CTX_IMPORT_NORET(a_pVCpu, a_fExtrnImport) \
908	do { \
909	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
910	{ /* likely */ } \
911	else \
912	{ \
913	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
914	AssertLogRelRC(rcCtxImport); \
915	} \
916	} while (0)
917
918	/** @def IEM_CTX_IMPORT_JMP
919	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
920	*
921	* Will call the keep to import the bits as needed.
922	*
923	* Jumps on import failure.
924	*
925	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
926	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
927	*/
928	#define IEM_CTX_IMPORT_JMP(a_pVCpu, a_fExtrnImport) \
929	do { \
930	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
931	{ /* likely */ } \
932	else \
933	{ \
934	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
935	AssertRCStmt(rcCtxImport, IEM_DO_LONGJMP(pVCpu, rcCtxImport)); \
936	} \
937	} while (0)
938
939
940
941	/** @def IEM_GET_TARGET_CPU
942	* Gets the current IEMTARGETCPU value.
943	* @returns IEMTARGETCPU value.
944	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
945	*/
946	#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
947	# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
948	#else
949	# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
950	#endif
951
952	/** @def IEM_GET_INSTR_LEN
953	* Gets the instruction length. */
954	#ifdef IEM_WITH_CODE_TLB
955	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
956	#else
957	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
958	#endif
959
960	/** @def IEM_TRY_SETJMP
961	* Wrapper around setjmp / try, hiding all the ugly differences.
962	*
963	* @note Use with extreme care as this is a fragile macro.
964	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
965	* @param a_rcTarget The variable that should receive the status code in case
966	* of a longjmp/throw.
967	*/
968	/** @def IEM_TRY_SETJMP_AGAIN
969	* For when setjmp / try is used again in the same variable scope as a previous
970	* IEM_TRY_SETJMP invocation.
971	*/
972	/** @def IEM_CATCH_LONGJMP_BEGIN
973	* Start wrapper for catch / setjmp-else.
974	*
975	* This will set up a scope.
976	*
977	* @note Use with extreme care as this is a fragile macro.
978	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
979	* @param a_rcTarget The variable that should receive the status code in case
980	* of a longjmp/throw.
981	*/
982	/** @def IEM_CATCH_LONGJMP_END
983	* End wrapper for catch / setjmp-else.
984	*
985	* This will close the scope set up by IEM_CATCH_LONGJMP_BEGIN and clean up the
986	* state.
987	*
988	* @note Use with extreme care as this is a fragile macro.
989	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
990	*/
991	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
992	# ifdef IEM_WITH_THROW_CATCH
993	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
994	a_rcTarget = VINF_SUCCESS; \
995	try
996	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
997	IEM_TRY_SETJMP(a_pVCpu, a_rcTarget)
998	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
999	catch (int rcThrown) \
1000	{ \
1001	a_rcTarget = rcThrown
1002	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
1003	} \
1004	((void)0)
1005	# else /* !IEM_WITH_THROW_CATCH */
1006	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
1007	jmp_buf JmpBuf; \
1008	jmp_buf * volatile pSavedJmpBuf = pVCpu->iem.s.CTX_SUFF(pJmpBuf); \
1009	pVCpu->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
1010	if ((rcStrict = setjmp(JmpBuf)) == 0)
1011	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
1012	pSavedJmpBuf = pVCpu->iem.s.CTX_SUFF(pJmpBuf); \
1013	pVCpu->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
1014	if ((rcStrict = setjmp(JmpBuf)) == 0)
1015	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
1016	else \
1017	{ \
1018	((void)0)
1019	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
1020	} \
1021	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = pSavedJmpBuf
1022	# endif /* !IEM_WITH_THROW_CATCH */
1023	#endif /* IEM_WITH_SETJMP */
1024
1025
1026	/**
1027	* Shared per-VM IEM data.
1028	*/
1029	typedef struct IEM
1030	{
1031	/** The VMX APIC-access page handler type. */
1032	PGMPHYSHANDLERTYPE hVmxApicAccessPage;
1033	#ifndef VBOX_WITHOUT_CPUID_HOST_CALL
1034	/** Set if the CPUID host call functionality is enabled. */
1035	bool fCpuIdHostCall;
1036	#endif
1037	} IEM;
1038
1039
1040
1041	/** @name IEM_ACCESS_XXX - Access details.
1042	* @{ */
1043	#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
1044	#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
1045	#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
1046	#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
1047	#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
1048	#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
1049	#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
1050	#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
1051	#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
1052	#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
1053	/** The writes are partial, so if initialize the bounce buffer with the
1054	* orignal RAM content. */
1055	#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
1056	/** Used in aMemMappings to indicate that the entry is bounce buffered. */
1057	#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
1058	/** Bounce buffer with ring-3 write pending, first page. */
1059	#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
1060	/** Bounce buffer with ring-3 write pending, second page. */
1061	#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
1062	/** Not locked, accessed via the TLB. */
1063	#define IEM_ACCESS_NOT_LOCKED UINT32_C(0x00001000)
1064	/** Valid bit mask. */
1065	#define IEM_ACCESS_VALID_MASK UINT32_C(0x00001fff)
1066	/** Shift count for the TLB flags (upper word). */
1067	#define IEM_ACCESS_SHIFT_TLB_FLAGS 16
1068
1069	/** Read+write data alias. */
1070	#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
1071	/** Write data alias. */
1072	#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
1073	/** Read data alias. */
1074	#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_DATA)
1075	/** Instruction fetch alias. */
1076	#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_WHAT_CODE)
1077	/** Stack write alias. */
1078	#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
1079	/** Stack read alias. */
1080	#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_STACK)
1081	/** Stack read+write alias. */
1082	#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
1083	/** Read system table alias. */
1084	#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_SYS)
1085	/** Read+write system table alias. */
1086	#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_SYS)
1087	/** @} */
1088
1089	/** @name Prefix constants (IEMCPU::fPrefixes)
1090	* @{ */
1091	#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /*< CS segment prefix (0x2e). /
1092	#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /*< SS segment prefix (0x36). /
1093	#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /*< DS segment prefix (0x3e). /
1094	#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /*< ES segment prefix (0x26). /
1095	#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /*< FS segment prefix (0x64). /
1096	#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /*< GS segment prefix (0x65). /
1097	#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
1098
1099	#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /*< Operand size prefix (0x66). /
1100	#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /*< REX.W prefix (0x48-0x4f). /
1101	#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /*< Address size prefix (0x67). /
1102
1103	#define IEM_OP_PRF_LOCK RT_BIT_32(16) /*< Lock prefix (0xf0). /
1104	#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /*< Repeat-not-zero prefix (0xf2). /
1105	#define IEM_OP_PRF_REPZ RT_BIT_32(18) /*< Repeat-if-zero prefix (0xf3). /
1106
1107	#define IEM_OP_PRF_REX RT_BIT_32(24) /*< Any REX prefix (0x40-0x4f). /
1108	#define IEM_OP_PRF_REX_R RT_BIT_32(25) /*< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). /
1109	#define IEM_OP_PRF_REX_B RT_BIT_32(26) /*< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). /
1110	#define IEM_OP_PRF_REX_X RT_BIT_32(27) /*< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). /
1111	/** Mask with all the REX prefix flags.
1112	* This is generally for use when needing to undo the REX prefixes when they
1113	* are followed legacy prefixes and therefore does not immediately preceed
1114	* the first opcode byte.
1115	* For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
1116	#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX \| IEM_OP_PRF_REX_R \| IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X \| IEM_OP_PRF_SIZE_REX_W )
1117
1118	#define IEM_OP_PRF_VEX RT_BIT_32(28) /*< Indiciates VEX prefix. /
1119	#define IEM_OP_PRF_EVEX RT_BIT_32(29) /*< Indiciates EVEX prefix. /
1120	#define IEM_OP_PRF_XOP RT_BIT_32(30) /*< Indiciates XOP prefix. /
1121	/** @} */
1122
1123	/** @name IEMOPFORM_XXX - Opcode forms
1124	* @note These are ORed together with IEMOPHINT_XXX.
1125	* @{ */
1126	/** ModR/M: reg, r/m */
1127	#define IEMOPFORM_RM 0
1128	/** ModR/M: reg, r/m (register) */
1129	#define IEMOPFORM_RM_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
1130	/** ModR/M: reg, r/m (memory) */
1131	#define IEMOPFORM_RM_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
1132	/** ModR/M: reg, r/m */
1133	#define IEMOPFORM_RMI 1
1134	/** ModR/M: reg, r/m (register) */
1135	#define IEMOPFORM_RMI_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
1136	/** ModR/M: reg, r/m (memory) */
1137	#define IEMOPFORM_RMI_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
1138	/** ModR/M: r/m, reg */
1139	#define IEMOPFORM_MR 2
1140	/** ModR/M: r/m (register), reg */
1141	#define IEMOPFORM_MR_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
1142	/** ModR/M: r/m (memory), reg */
1143	#define IEMOPFORM_MR_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
1144	/** ModR/M: r/m, reg */
1145	#define IEMOPFORM_MRI 3
1146	/** ModR/M: r/m (register), reg */
1147	#define IEMOPFORM_MRI_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
1148	/** ModR/M: r/m (memory), reg */
1149	#define IEMOPFORM_MRI_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
1150	/** ModR/M: r/m only */
1151	#define IEMOPFORM_M 4
1152	/** ModR/M: r/m only (register). */
1153	#define IEMOPFORM_M_REG (IEMOPFORM_M \| IEMOPFORM_MOD3)
1154	/** ModR/M: r/m only (memory). */
1155	#define IEMOPFORM_M_MEM (IEMOPFORM_M \| IEMOPFORM_NOT_MOD3)
1156	/** ModR/M: reg only */
1157	#define IEMOPFORM_R 5
1158
1159	/** VEX+ModR/M: reg, r/m */
1160	#define IEMOPFORM_VEX_RM 8
1161	/** VEX+ModR/M: reg, r/m (register) */
1162	#define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM \| IEMOPFORM_MOD3)
1163	/** VEX+ModR/M: reg, r/m (memory) */
1164	#define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM \| IEMOPFORM_NOT_MOD3)
1165	/** VEX+ModR/M: r/m, reg */
1166	#define IEMOPFORM_VEX_MR 9
1167	/** VEX+ModR/M: r/m (register), reg */
1168	#define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR \| IEMOPFORM_MOD3)
1169	/** VEX+ModR/M: r/m (memory), reg */
1170	#define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR \| IEMOPFORM_NOT_MOD3)
1171	/** VEX+ModR/M: r/m only */
1172	#define IEMOPFORM_VEX_M 10
1173	/** VEX+ModR/M: r/m only (register). */
1174	#define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M \| IEMOPFORM_MOD3)
1175	/** VEX+ModR/M: r/m only (memory). */
1176	#define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M \| IEMOPFORM_NOT_MOD3)
1177	/** VEX+ModR/M: reg only */
1178	#define IEMOPFORM_VEX_R 11
1179	/** VEX+ModR/M: reg, vvvv, r/m */
1180	#define IEMOPFORM_VEX_RVM 12
1181	/** VEX+ModR/M: reg, vvvv, r/m (register). */
1182	#define IEMOPFORM_VEX_RVM_REG (IEMOPFORM_VEX_RVM \| IEMOPFORM_MOD3)
1183	/** VEX+ModR/M: reg, vvvv, r/m (memory). */
1184	#define IEMOPFORM_VEX_RVM_MEM (IEMOPFORM_VEX_RVM \| IEMOPFORM_NOT_MOD3)
1185	/** VEX+ModR/M: reg, r/m, vvvv */
1186	#define IEMOPFORM_VEX_RMV 13
1187	/** VEX+ModR/M: reg, r/m, vvvv (register). */
1188	#define IEMOPFORM_VEX_RMV_REG (IEMOPFORM_VEX_RMV \| IEMOPFORM_MOD3)
1189	/** VEX+ModR/M: reg, r/m, vvvv (memory). */
1190	#define IEMOPFORM_VEX_RMV_MEM (IEMOPFORM_VEX_RMV \| IEMOPFORM_NOT_MOD3)
1191	/** VEX+ModR/M: reg, r/m, imm8 */
1192	#define IEMOPFORM_VEX_RMI 14
1193	/** VEX+ModR/M: reg, r/m, imm8 (register). */
1194	#define IEMOPFORM_VEX_RMI_REG (IEMOPFORM_VEX_RMI \| IEMOPFORM_MOD3)
1195	/** VEX+ModR/M: reg, r/m, imm8 (memory). */
1196	#define IEMOPFORM_VEX_RMI_MEM (IEMOPFORM_VEX_RMI \| IEMOPFORM_NOT_MOD3)
1197	/** VEX+ModR/M: r/m, vvvv, reg */
1198	#define IEMOPFORM_VEX_MVR 15
1199	/** VEX+ModR/M: r/m, vvvv, reg (register) */
1200	#define IEMOPFORM_VEX_MVR_REG (IEMOPFORM_VEX_MVR \| IEMOPFORM_MOD3)
1201	/** VEX+ModR/M: r/m, vvvv, reg (memory) */
1202	#define IEMOPFORM_VEX_MVR_MEM (IEMOPFORM_VEX_MVR \| IEMOPFORM_NOT_MOD3)
1203	/** VEX+ModR/M+/n: vvvv, r/m */
1204	#define IEMOPFORM_VEX_VM 16
1205	/** VEX+ModR/M+/n: vvvv, r/m (register) */
1206	#define IEMOPFORM_VEX_VM_REG (IEMOPFORM_VEX_VM \| IEMOPFORM_MOD3)
1207	/** VEX+ModR/M+/n: vvvv, r/m (memory) */
1208	#define IEMOPFORM_VEX_VM_MEM (IEMOPFORM_VEX_VM \| IEMOPFORM_NOT_MOD3)
1209
1210	/** Fixed register instruction, no R/M. */
1211	#define IEMOPFORM_FIXED 32
1212
1213	/** The r/m is a register. */
1214	#define IEMOPFORM_MOD3 RT_BIT_32(8)
1215	/** The r/m is a memory access. */
1216	#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
1217	/** @} */
1218
1219	/** @name IEMOPHINT_XXX - Additional Opcode Hints
1220	* @note These are ORed together with IEMOPFORM_XXX.
1221	* @{ */
1222	/** Ignores the operand size prefix (66h). */
1223	#define IEMOPHINT_IGNORES_OZ_PFX RT_BIT_32(10)
1224	/** Ignores REX.W (aka WIG). */
1225	#define IEMOPHINT_IGNORES_REXW RT_BIT_32(11)
1226	/** Both the operand size prefixes (66h + REX.W) are ignored. */
1227	#define IEMOPHINT_IGNORES_OP_SIZES (IEMOPHINT_IGNORES_OZ_PFX \| IEMOPHINT_IGNORES_REXW)
1228	/** Allowed with the lock prefix. */
1229	#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
1230	/** The VEX.L value is ignored (aka LIG). */
1231	#define IEMOPHINT_VEX_L_IGNORED RT_BIT_32(12)
1232	/** The VEX.L value must be zero (i.e. 128-bit width only). */
1233	#define IEMOPHINT_VEX_L_ZERO RT_BIT_32(13)
1234	/** The VEX.V value must be zero. */
1235	#define IEMOPHINT_VEX_V_ZERO RT_BIT_32(14)
1236
1237	/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
1238	#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
1239	/** @} */
1240
1241	/**
1242	* Possible hardware task switch sources.
1243	*/
1244	typedef enum IEMTASKSWITCH
1245	{
1246	/** Task switch caused by an interrupt/exception. */
1247	IEMTASKSWITCH_INT_XCPT = 1,
1248	/** Task switch caused by a far CALL. */
1249	IEMTASKSWITCH_CALL,
1250	/** Task switch caused by a far JMP. */
1251	IEMTASKSWITCH_JUMP,
1252	/** Task switch caused by an IRET. */
1253	IEMTASKSWITCH_IRET
1254	} IEMTASKSWITCH;
1255	AssertCompileSize(IEMTASKSWITCH, 4);
1256
1257	/**
1258	* Possible CrX load (write) sources.
1259	*/
1260	typedef enum IEMACCESSCRX
1261	{
1262	/** CrX access caused by 'mov crX' instruction. */
1263	IEMACCESSCRX_MOV_CRX,
1264	/** CrX (CR0) write caused by 'lmsw' instruction. */
1265	IEMACCESSCRX_LMSW,
1266	/** CrX (CR0) write caused by 'clts' instruction. */
1267	IEMACCESSCRX_CLTS,
1268	/** CrX (CR0) read caused by 'smsw' instruction. */
1269	IEMACCESSCRX_SMSW
1270	} IEMACCESSCRX;
1271
1272	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1273	/** @name IEM_SLAT_FAIL_XXX - Second-level address translation failure information.
1274	*
1275	* These flags provide further context to SLAT page-walk failures that could not be
1276	* determined by PGM (e.g, PGM is not privy to memory access permissions).
1277	*
1278	* @{
1279	*/
1280	/** Translating a nested-guest linear address failed accessing a nested-guest
1281	* physical address. */
1282	# define IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR RT_BIT_32(0)
1283	/** Translating a nested-guest linear address failed accessing a
1284	* paging-structure entry or updating accessed/dirty bits. */
1285	# define IEM_SLAT_FAIL_LINEAR_TO_PAGE_TABLE RT_BIT_32(1)
1286	/** @} */
1287
1288	DECLCALLBACK(FNPGMPHYSHANDLER) iemVmxApicAccessPageHandler;
1289	# ifndef IN_RING3
1290	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) iemVmxApicAccessPagePfHandler;
1291	# endif
1292	#endif
1293
1294	/**
1295	* Indicates to the verifier that the given flag set is undefined.
1296	*
1297	* Can be invoked again to add more flags.
1298	*
1299	* This is a NOOP if the verifier isn't compiled in.
1300	*
1301	* @note We're temporarily keeping this until code is converted to new
1302	* disassembler style opcode handling.
1303	*/
1304	#define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
1305
1306
1307	/** @def IEM_DECL_IMPL_TYPE
1308	* For typedef'ing an instruction implementation function.
1309	*
1310	* @param a_RetType The return type.
1311	* @param a_Name The name of the type.
1312	* @param a_ArgList The argument list enclosed in parentheses.
1313	*/
1314
1315	/** @def IEM_DECL_IMPL_DEF
1316	* For defining an instruction implementation function.
1317	*
1318	* @param a_RetType The return type.
1319	* @param a_Name The name of the type.
1320	* @param a_ArgList The argument list enclosed in parentheses.
1321	*/
1322
1323	#if defined(__GNUC__) && defined(RT_ARCH_X86)
1324	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1325	__attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
1326	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1327	__attribute__((__fastcall__, __nothrow__)) a_RetType a_Name a_ArgList
1328	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1329	__attribute__((__fastcall__, __nothrow__)) a_RetType a_Name a_ArgList
1330
1331	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
1332	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1333	a_RetType (__fastcall a_Name) a_ArgList
1334	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1335	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
1336	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1337	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
1338
1339	#elif __cplusplus >= 201700 /* P0012R1 support */
1340	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1341	a_RetType (VBOXCALL a_Name) a_ArgList RT_NOEXCEPT
1342	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1343	a_RetType VBOXCALL a_Name a_ArgList RT_NOEXCEPT
1344	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1345	a_RetType VBOXCALL a_Name a_ArgList RT_NOEXCEPT
1346
1347	#else
1348	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1349	a_RetType (VBOXCALL a_Name) a_ArgList
1350	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1351	a_RetType VBOXCALL a_Name a_ArgList
1352	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1353	a_RetType VBOXCALL a_Name a_ArgList
1354
1355	#endif
1356
1357	/** Defined in IEMAllAImplC.cpp but also used by IEMAllAImplA.asm. */
1358	RT_C_DECLS_BEGIN
1359	extern uint8_t const g_afParity[256];
1360	RT_C_DECLS_END
1361
1362
1363	/** @name Arithmetic assignment operations on bytes (binary).
1364	* @{ */
1365	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU8, (uint8_t pu8Dst, uint8_t u8Src, uint32_t pEFlags));
1366	typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
1367	FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
1368	FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
1369	FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
1370	FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
1371	FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
1372	FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
1373	FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
1374	/** @} */
1375
1376	/** @name Arithmetic assignment operations on words (binary).
1377	* @{ */
1378	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU16, (uint16_t pu16Dst, uint16_t u16Src, uint32_t pEFlags));
1379	typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
1380	FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
1381	FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
1382	FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
1383	FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
1384	FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
1385	FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
1386	FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
1387	/** @} */
1388
1389	/** @name Arithmetic assignment operations on double words (binary).
1390	* @{ */
1391	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU32, (uint32_t pu32Dst, uint32_t u32Src, uint32_t pEFlags));
1392	typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
1393	FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
1394	FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
1395	FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
1396	FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
1397	FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
1398	FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
1399	FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
1400	FNIEMAIMPLBINU32 iemAImpl_blsi_u32, iemAImpl_blsi_u32_fallback;
1401	FNIEMAIMPLBINU32 iemAImpl_blsr_u32, iemAImpl_blsr_u32_fallback;
1402	FNIEMAIMPLBINU32 iemAImpl_blsmsk_u32, iemAImpl_blsmsk_u32_fallback;
1403	/** @} */
1404
1405	/** @name Arithmetic assignment operations on quad words (binary).
1406	* @{ */
1407	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU64, (uint64_t pu64Dst, uint64_t u64Src, uint32_t pEFlags));
1408	typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
1409	FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
1410	FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
1411	FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
1412	FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
1413	FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
1414	FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
1415	FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
1416	FNIEMAIMPLBINU64 iemAImpl_blsi_u64, iemAImpl_blsi_u64_fallback;
1417	FNIEMAIMPLBINU64 iemAImpl_blsr_u64, iemAImpl_blsr_u64_fallback;
1418	FNIEMAIMPLBINU64 iemAImpl_blsmsk_u64, iemAImpl_blsmsk_u64_fallback;
1419	/** @} */
1420
1421	/** @name Compare operations (thrown in with the binary ops).
1422	* @{ */
1423	FNIEMAIMPLBINU8 iemAImpl_cmp_u8;
1424	FNIEMAIMPLBINU16 iemAImpl_cmp_u16;
1425	FNIEMAIMPLBINU32 iemAImpl_cmp_u32;
1426	FNIEMAIMPLBINU64 iemAImpl_cmp_u64;
1427	/** @} */
1428
1429	/** @name Test operations (thrown in with the binary ops).
1430	* @{ */
1431	FNIEMAIMPLBINU8 iemAImpl_test_u8;
1432	FNIEMAIMPLBINU16 iemAImpl_test_u16;
1433	FNIEMAIMPLBINU32 iemAImpl_test_u32;
1434	FNIEMAIMPLBINU64 iemAImpl_test_u64;
1435	/** @} */
1436
1437	/** @name Bit operations operations (thrown in with the binary ops).
1438	* @{ */
1439	FNIEMAIMPLBINU16 iemAImpl_bt_u16;
1440	FNIEMAIMPLBINU32 iemAImpl_bt_u32;
1441	FNIEMAIMPLBINU64 iemAImpl_bt_u64;
1442	FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
1443	FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
1444	FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
1445	FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
1446	FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
1447	FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
1448	FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
1449	FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
1450	FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
1451	/** @} */
1452
1453	/** @name Arithmetic three operand operations on double words (binary).
1454	* @{ */
1455	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32, (uint32_t pu32Dst, uint32_t u32Src1, uint32_t u32Src2, uint32_t pEFlags));
1456	typedef FNIEMAIMPLBINVEXU32 *PFNIEMAIMPLBINVEXU32;
1457	FNIEMAIMPLBINVEXU32 iemAImpl_andn_u32, iemAImpl_andn_u32_fallback;
1458	FNIEMAIMPLBINVEXU32 iemAImpl_bextr_u32, iemAImpl_bextr_u32_fallback;
1459	FNIEMAIMPLBINVEXU32 iemAImpl_bzhi_u32, iemAImpl_bzhi_u32_fallback;
1460	/** @} */
1461
1462	/** @name Arithmetic three operand operations on quad words (binary).
1463	* @{ */
1464	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64, (uint64_t pu64Dst, uint64_t u64Src1, uint64_t u64Src2, uint32_t pEFlags));
1465	typedef FNIEMAIMPLBINVEXU64 *PFNIEMAIMPLBINVEXU64;
1466	FNIEMAIMPLBINVEXU64 iemAImpl_andn_u64, iemAImpl_andn_u64_fallback;
1467	FNIEMAIMPLBINVEXU64 iemAImpl_bextr_u64, iemAImpl_bextr_u64_fallback;
1468	FNIEMAIMPLBINVEXU64 iemAImpl_bzhi_u64, iemAImpl_bzhi_u64_fallback;
1469	/** @} */
1470
1471	/** @name Arithmetic three operand operations on double words w/o EFLAGS (binary).
1472	* @{ */
1473	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32NOEFL, (uint32_t *pu32Dst, uint32_t u32Src1, uint32_t u32Src2));
1474	typedef FNIEMAIMPLBINVEXU32NOEFL *PFNIEMAIMPLBINVEXU32NOEFL;
1475	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pdep_u32, iemAImpl_pdep_u32_fallback;
1476	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pext_u32, iemAImpl_pext_u32_fallback;
1477	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_sarx_u32, iemAImpl_sarx_u32_fallback;
1478	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shlx_u32, iemAImpl_shlx_u32_fallback;
1479	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shrx_u32, iemAImpl_shrx_u32_fallback;
1480	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_rorx_u32;
1481	/** @} */
1482
1483	/** @name Arithmetic three operand operations on quad words w/o EFLAGS (binary).
1484	* @{ */
1485	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64NOEFL, (uint64_t *pu64Dst, uint64_t u64Src1, uint64_t u64Src2));
1486	typedef FNIEMAIMPLBINVEXU64NOEFL *PFNIEMAIMPLBINVEXU64NOEFL;
1487	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pdep_u64, iemAImpl_pdep_u64_fallback;
1488	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pext_u64, iemAImpl_pext_u64_fallback;
1489	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_sarx_u64, iemAImpl_sarx_u64_fallback;
1490	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shlx_u64, iemAImpl_shlx_u64_fallback;
1491	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shrx_u64, iemAImpl_shrx_u64_fallback;
1492	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_rorx_u64;
1493	/** @} */
1494
1495	/** @name MULX 32-bit and 64-bit.
1496	* @{ */
1497	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU32, (uint32_t puDst1, uint32_t puDst2, uint32_t uSrc1, uint32_t uSrc2));
1498	typedef FNIEMAIMPLMULXVEXU32 *PFNIEMAIMPLMULXVEXU32;
1499	FNIEMAIMPLMULXVEXU32 iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback;
1500
1501	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU64, (uint64_t puDst1, uint64_t puDst2, uint64_t uSrc1, uint64_t uSrc2));
1502	typedef FNIEMAIMPLMULXVEXU64 *PFNIEMAIMPLMULXVEXU64;
1503	FNIEMAIMPLMULXVEXU64 iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback;
1504	/** @} */
1505
1506
1507	/** @name Exchange memory with register operations.
1508	* @{ */
1509	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_locked, (uint8_t pu8Mem, uint8_t pu8Reg));
1510	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_locked,(uint16_t pu16Mem, uint16_t pu16Reg));
1511	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_locked,(uint32_t pu32Mem, uint32_t pu32Reg));
1512	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_locked,(uint64_t pu64Mem, uint64_t pu64Reg));
1513	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_unlocked, (uint8_t pu8Mem, uint8_t pu8Reg));
1514	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_unlocked,(uint16_t pu16Mem, uint16_t pu16Reg));
1515	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_unlocked,(uint32_t pu32Mem, uint32_t pu32Reg));
1516	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_unlocked,(uint64_t pu64Mem, uint64_t pu64Reg));
1517	/** @} */
1518
1519	/** @name Exchange and add operations.
1520	* @{ */
1521	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1522	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1523	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1524	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1525	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1526	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1527	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1528	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1529	/** @} */
1530
1531	/** @name Compare and exchange.
1532	* @{ */
1533	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1534	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1535	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1536	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1537	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1538	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1539	#if ARCH_BITS == 32
1540	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1541	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1542	#else
1543	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1544	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1545	#endif
1546	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1547	uint32_t *pEFlags));
1548	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1549	uint32_t *pEFlags));
1550	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1551	uint32_t *pEFlags));
1552	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1553	uint32_t *pEFlags));
1554	#ifndef RT_ARCH_ARM64
1555	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
1556	PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
1557	#endif
1558	/** @} */
1559
1560	/** @name Memory ordering
1561	* @{ */
1562	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
1563	typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
1564	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
1565	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
1566	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
1567	#ifndef RT_ARCH_ARM64
1568	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
1569	#endif
1570	/** @} */
1571
1572	/** @name Double precision shifts
1573	* @{ */
1574	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t pEFlags));
1575	typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
1576	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t pEFlags));
1577	typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
1578	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t pEFlags));
1579	typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
1580	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16, iemAImpl_shld_u16_amd, iemAImpl_shld_u16_intel;
1581	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32, iemAImpl_shld_u32_amd, iemAImpl_shld_u32_intel;
1582	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64, iemAImpl_shld_u64_amd, iemAImpl_shld_u64_intel;
1583	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16, iemAImpl_shrd_u16_amd, iemAImpl_shrd_u16_intel;
1584	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32, iemAImpl_shrd_u32_amd, iemAImpl_shrd_u32_intel;
1585	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64, iemAImpl_shrd_u64_amd, iemAImpl_shrd_u64_intel;
1586	/** @} */
1587
1588
1589	/** @name Bit search operations (thrown in with the binary ops).
1590	* @{ */
1591	FNIEMAIMPLBINU16 iemAImpl_bsf_u16, iemAImpl_bsf_u16_amd, iemAImpl_bsf_u16_intel;
1592	FNIEMAIMPLBINU32 iemAImpl_bsf_u32, iemAImpl_bsf_u32_amd, iemAImpl_bsf_u32_intel;
1593	FNIEMAIMPLBINU64 iemAImpl_bsf_u64, iemAImpl_bsf_u64_amd, iemAImpl_bsf_u64_intel;
1594	FNIEMAIMPLBINU16 iemAImpl_bsr_u16, iemAImpl_bsr_u16_amd, iemAImpl_bsr_u16_intel;
1595	FNIEMAIMPLBINU32 iemAImpl_bsr_u32, iemAImpl_bsr_u32_amd, iemAImpl_bsr_u32_intel;
1596	FNIEMAIMPLBINU64 iemAImpl_bsr_u64, iemAImpl_bsr_u64_amd, iemAImpl_bsr_u64_intel;
1597	FNIEMAIMPLBINU16 iemAImpl_lzcnt_u16, iemAImpl_lzcnt_u16_amd, iemAImpl_lzcnt_u16_intel;
1598	FNIEMAIMPLBINU32 iemAImpl_lzcnt_u32, iemAImpl_lzcnt_u32_amd, iemAImpl_lzcnt_u32_intel;
1599	FNIEMAIMPLBINU64 iemAImpl_lzcnt_u64, iemAImpl_lzcnt_u64_amd, iemAImpl_lzcnt_u64_intel;
1600	FNIEMAIMPLBINU16 iemAImpl_tzcnt_u16, iemAImpl_tzcnt_u16_amd, iemAImpl_tzcnt_u16_intel;
1601	FNIEMAIMPLBINU32 iemAImpl_tzcnt_u32, iemAImpl_tzcnt_u32_amd, iemAImpl_tzcnt_u32_intel;
1602	FNIEMAIMPLBINU64 iemAImpl_tzcnt_u64, iemAImpl_tzcnt_u64_amd, iemAImpl_tzcnt_u64_intel;
1603	FNIEMAIMPLBINU16 iemAImpl_popcnt_u16, iemAImpl_popcnt_u16_fallback;
1604	FNIEMAIMPLBINU32 iemAImpl_popcnt_u32, iemAImpl_popcnt_u32_fallback;
1605	FNIEMAIMPLBINU64 iemAImpl_popcnt_u64, iemAImpl_popcnt_u64_fallback;
1606	/** @} */
1607
1608	/** @name Signed multiplication operations (thrown in with the binary ops).
1609	* @{ */
1610	FNIEMAIMPLBINU16 iemAImpl_imul_two_u16, iemAImpl_imul_two_u16_amd, iemAImpl_imul_two_u16_intel;
1611	FNIEMAIMPLBINU32 iemAImpl_imul_two_u32, iemAImpl_imul_two_u32_amd, iemAImpl_imul_two_u32_intel;
1612	FNIEMAIMPLBINU64 iemAImpl_imul_two_u64, iemAImpl_imul_two_u64_amd, iemAImpl_imul_two_u64_intel;
1613	/** @} */
1614
1615	/** @name Arithmetic assignment operations on bytes (unary).
1616	* @{ */
1617	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t pu8Dst, uint32_t pEFlags));
1618	typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
1619	FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
1620	FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
1621	FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
1622	FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
1623	/** @} */
1624
1625	/** @name Arithmetic assignment operations on words (unary).
1626	* @{ */
1627	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t pu16Dst, uint32_t pEFlags));
1628	typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
1629	FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
1630	FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
1631	FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
1632	FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
1633	/** @} */
1634
1635	/** @name Arithmetic assignment operations on double words (unary).
1636	* @{ */
1637	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t pu32Dst, uint32_t pEFlags));
1638	typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
1639	FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
1640	FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
1641	FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
1642	FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
1643	/** @} */
1644
1645	/** @name Arithmetic assignment operations on quad words (unary).
1646	* @{ */
1647	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t pu64Dst, uint32_t pEFlags));
1648	typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
1649	FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
1650	FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
1651	FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
1652	FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
1653	/** @} */
1654
1655
1656	/** @name Shift operations on bytes (Group 2).
1657	* @{ */
1658	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU8,(uint8_t pu8Dst, uint8_t cShift, uint32_t pEFlags));
1659	typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
1660	FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8, iemAImpl_rol_u8_amd, iemAImpl_rol_u8_intel;
1661	FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8, iemAImpl_ror_u8_amd, iemAImpl_ror_u8_intel;
1662	FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8, iemAImpl_rcl_u8_amd, iemAImpl_rcl_u8_intel;
1663	FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8, iemAImpl_rcr_u8_amd, iemAImpl_rcr_u8_intel;
1664	FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8, iemAImpl_shl_u8_amd, iemAImpl_shl_u8_intel;
1665	FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8, iemAImpl_shr_u8_amd, iemAImpl_shr_u8_intel;
1666	FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8, iemAImpl_sar_u8_amd, iemAImpl_sar_u8_intel;
1667	/** @} */
1668
1669	/** @name Shift operations on words (Group 2).
1670	* @{ */
1671	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU16,(uint16_t pu16Dst, uint8_t cShift, uint32_t pEFlags));
1672	typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
1673	FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16, iemAImpl_rol_u16_amd, iemAImpl_rol_u16_intel;
1674	FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16, iemAImpl_ror_u16_amd, iemAImpl_ror_u16_intel;
1675	FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16, iemAImpl_rcl_u16_amd, iemAImpl_rcl_u16_intel;
1676	FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16, iemAImpl_rcr_u16_amd, iemAImpl_rcr_u16_intel;
1677	FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16, iemAImpl_shl_u16_amd, iemAImpl_shl_u16_intel;
1678	FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16, iemAImpl_shr_u16_amd, iemAImpl_shr_u16_intel;
1679	FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16, iemAImpl_sar_u16_amd, iemAImpl_sar_u16_intel;
1680	/** @} */
1681
1682	/** @name Shift operations on double words (Group 2).
1683	* @{ */
1684	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU32,(uint32_t pu32Dst, uint8_t cShift, uint32_t pEFlags));
1685	typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
1686	FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32, iemAImpl_rol_u32_amd, iemAImpl_rol_u32_intel;
1687	FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32, iemAImpl_ror_u32_amd, iemAImpl_ror_u32_intel;
1688	FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32, iemAImpl_rcl_u32_amd, iemAImpl_rcl_u32_intel;
1689	FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32, iemAImpl_rcr_u32_amd, iemAImpl_rcr_u32_intel;
1690	FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32, iemAImpl_shl_u32_amd, iemAImpl_shl_u32_intel;
1691	FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32, iemAImpl_shr_u32_amd, iemAImpl_shr_u32_intel;
1692	FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32, iemAImpl_sar_u32_amd, iemAImpl_sar_u32_intel;
1693	/** @} */
1694
1695	/** @name Shift operations on words (Group 2).
1696	* @{ */
1697	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU64,(uint64_t pu64Dst, uint8_t cShift, uint32_t pEFlags));
1698	typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
1699	FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64, iemAImpl_rol_u64_amd, iemAImpl_rol_u64_intel;
1700	FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64, iemAImpl_ror_u64_amd, iemAImpl_ror_u64_intel;
1701	FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64, iemAImpl_rcl_u64_amd, iemAImpl_rcl_u64_intel;
1702	FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64, iemAImpl_rcr_u64_amd, iemAImpl_rcr_u64_intel;
1703	FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64, iemAImpl_shl_u64_amd, iemAImpl_shl_u64_intel;
1704	FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64, iemAImpl_shr_u64_amd, iemAImpl_shr_u64_intel;
1705	FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64, iemAImpl_sar_u64_amd, iemAImpl_sar_u64_intel;
1706	/** @} */
1707
1708	/** @name Multiplication and division operations.
1709	* @{ */
1710	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t pu16AX, uint8_t u8FactorDivisor, uint32_t pEFlags));
1711	typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
1712	FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_mul_u8_amd, iemAImpl_mul_u8_intel;
1713	FNIEMAIMPLMULDIVU8 iemAImpl_imul_u8, iemAImpl_imul_u8_amd, iemAImpl_imul_u8_intel;
1714	FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_div_u8_amd, iemAImpl_div_u8_intel;
1715	FNIEMAIMPLMULDIVU8 iemAImpl_idiv_u8, iemAImpl_idiv_u8_amd, iemAImpl_idiv_u8_intel;
1716
1717	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t pu16AX, uint16_t pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
1718	typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
1719	FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_mul_u16_amd, iemAImpl_mul_u16_intel;
1720	FNIEMAIMPLMULDIVU16 iemAImpl_imul_u16, iemAImpl_imul_u16_amd, iemAImpl_imul_u16_intel;
1721	FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_div_u16_amd, iemAImpl_div_u16_intel;
1722	FNIEMAIMPLMULDIVU16 iemAImpl_idiv_u16, iemAImpl_idiv_u16_amd, iemAImpl_idiv_u16_intel;
1723
1724	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t pu32EAX, uint32_t pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
1725	typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
1726	FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_mul_u32_amd, iemAImpl_mul_u32_intel;
1727	FNIEMAIMPLMULDIVU32 iemAImpl_imul_u32, iemAImpl_imul_u32_amd, iemAImpl_imul_u32_intel;
1728	FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_div_u32_amd, iemAImpl_div_u32_intel;
1729	FNIEMAIMPLMULDIVU32 iemAImpl_idiv_u32, iemAImpl_idiv_u32_amd, iemAImpl_idiv_u32_intel;
1730
1731	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t pu64RAX, uint64_t pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
1732	typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
1733	FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_mul_u64_amd, iemAImpl_mul_u64_intel;
1734	FNIEMAIMPLMULDIVU64 iemAImpl_imul_u64, iemAImpl_imul_u64_amd, iemAImpl_imul_u64_intel;
1735	FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_div_u64_amd, iemAImpl_div_u64_intel;
1736	FNIEMAIMPLMULDIVU64 iemAImpl_idiv_u64, iemAImpl_idiv_u64_amd, iemAImpl_idiv_u64_intel;
1737	/** @} */
1738
1739	/** @name Byte Swap.
1740	* @{ */
1741	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t pu32Dst)); / Yes, 32-bit register access. */
1742	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
1743	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
1744	/** @} */
1745
1746	/** @name Misc.
1747	* @{ */
1748	FNIEMAIMPLBINU16 iemAImpl_arpl;
1749	/** @} */
1750
1751	/** @name RDRAND and RDSEED
1752	* @{ */
1753	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU16,(uint16_t puDst, uint32_t pEFlags));
1754	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU32,(uint32_t puDst, uint32_t pEFlags));
1755	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU64,(uint64_t puDst, uint32_t pEFlags));
1756	typedef FNIEMAIMPLRDRANDSEEDU16 *FNIEMAIMPLPRDRANDSEEDU16;
1757	typedef FNIEMAIMPLRDRANDSEEDU32 *FNIEMAIMPLPRDRANDSEEDU32;
1758	typedef FNIEMAIMPLRDRANDSEEDU64 *FNIEMAIMPLPRDRANDSEEDU64;
1759
1760	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdrand_u16, iemAImpl_rdrand_u16_fallback;
1761	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdrand_u32, iemAImpl_rdrand_u32_fallback;
1762	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdrand_u64, iemAImpl_rdrand_u64_fallback;
1763	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdseed_u16, iemAImpl_rdseed_u16_fallback;
1764	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdseed_u32, iemAImpl_rdseed_u32_fallback;
1765	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdseed_u64, iemAImpl_rdseed_u64_fallback;
1766	/** @} */
1767
1768	/** @name ADOX and ADCX
1769	* @{ */
1770	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLADXU32,(uint32_t puDst, uint32_t pfEFlags, uint32_t uSrc));
1771	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLADXU64,(uint64_t puDst, uint32_t pfEFlags, uint64_t uSrc));
1772	typedef FNIEMAIMPLADXU32 *PFNIEMAIMPLADXU32;
1773	typedef FNIEMAIMPLADXU64 *PFNIEMAIMPLADXU64;
1774
1775	FNIEMAIMPLADXU32 iemAImpl_adcx_u32, iemAImpl_adcx_u32_fallback;
1776	FNIEMAIMPLADXU64 iemAImpl_adcx_u64, iemAImpl_adcx_u64_fallback;
1777	FNIEMAIMPLADXU32 iemAImpl_adox_u32, iemAImpl_adox_u32_fallback;
1778	FNIEMAIMPLADXU64 iemAImpl_adox_u64, iemAImpl_adox_u64_fallback;
1779	/** @} */
1780
1781	/** @name FPU operations taking a 32-bit float argument
1782	* @{ */
1783	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1784	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1785	typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
1786
1787	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1788	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1789	typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
1790
1791	FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
1792	FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
1793	FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
1794	FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
1795	FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
1796	FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
1797	FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
1798
1799	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
1800	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1801	PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
1802	/** @} */
1803
1804	/** @name FPU operations taking a 64-bit float argument
1805	* @{ */
1806	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1807	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1808	typedef FNIEMAIMPLFPUR64FSW *PFNIEMAIMPLFPUR64FSW;
1809
1810	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1811	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1812	typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
1813
1814	FNIEMAIMPLFPUR64FSW iemAImpl_fcom_r80_by_r64;
1815	FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
1816	FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
1817	FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
1818	FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
1819	FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
1820	FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
1821
1822	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
1823	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1824	PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
1825	/** @} */
1826
1827	/** @name FPU operations taking a 80-bit float argument
1828	* @{ */
1829	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1830	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1831	typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
1832	FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
1833	FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
1834	FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
1835	FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
1836	FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
1837	FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
1838	FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
1839	FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
1840	FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
1841
1842	FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80, iemAImpl_fpatan_r80_by_r80_amd, iemAImpl_fpatan_r80_by_r80_intel;
1843	FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80, iemAImpl_fyl2x_r80_by_r80_amd, iemAImpl_fyl2x_r80_by_r80_intel;
1844	FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80, iemAImpl_fyl2xp1_r80_by_r80_amd, iemAImpl_fyl2xp1_r80_by_r80_intel;
1845
1846	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1847	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1848	typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
1849	FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
1850	FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
1851
1852	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1853	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1854	typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
1855	FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
1856	FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
1857
1858	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
1859	typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
1860	FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
1861	FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
1862	FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80, iemAImpl_f2xm1_r80_amd, iemAImpl_f2xm1_r80_intel;
1863	FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
1864	FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
1865	FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80, iemAImpl_fsin_r80_amd, iemAImpl_fsin_r80_intel;
1866	FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80, iemAImpl_fcos_r80_amd, iemAImpl_fcos_r80_intel;
1867
1868	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
1869	typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
1870	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
1871	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
1872
1873	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
1874	typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
1875	FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
1876	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
1877	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
1878	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
1879	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
1880	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
1881	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
1882
1883	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
1884	PCRTFLOAT80U pr80Val));
1885	typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
1886	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80, iemAImpl_fptan_r80_r80_amd, iemAImpl_fptan_r80_r80_intel;
1887	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
1888	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80, iemAImpl_fsincos_r80_r80_amd, iemAImpl_fsincos_r80_r80_intel;
1889
1890	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
1891	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1892	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
1893
1894	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_d80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTPBCD80U pd80Val));
1895	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_d80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1896	PRTPBCD80U pd80Dst, PCRTFLOAT80U pr80Src));
1897
1898	/** @} */
1899
1900	/** @name FPU operations taking a 16-bit signed integer argument
1901	* @{ */
1902	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1903	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
1904	typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
1905	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI16,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
1906	int16_t *pi16Dst, PCRTFLOAT80U pr80Src));
1907	typedef FNIEMAIMPLFPUSTR80TOI16 *PFNIEMAIMPLFPUSTR80TOI16;
1908
1909	FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
1910	FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
1911	FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
1912	FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
1913	FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
1914	FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
1915
1916	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1917	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
1918	typedef FNIEMAIMPLFPUI16FSW *PFNIEMAIMPLFPUI16FSW;
1919	FNIEMAIMPLFPUI16FSW iemAImpl_ficom_r80_by_i16;
1920
1921	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
1922	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fist_r80_to_i16;
1923	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fistt_r80_to_i16, iemAImpl_fistt_r80_to_i16_amd, iemAImpl_fistt_r80_to_i16_intel;
1924	/** @} */
1925
1926	/** @name FPU operations taking a 32-bit signed integer argument
1927	* @{ */
1928	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1929	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
1930	typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
1931	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI32,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
1932	int32_t *pi32Dst, PCRTFLOAT80U pr80Src));
1933	typedef FNIEMAIMPLFPUSTR80TOI32 *PFNIEMAIMPLFPUSTR80TOI32;
1934
1935	FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
1936	FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
1937	FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
1938	FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
1939	FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
1940	FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
1941
1942	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1943	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
1944	typedef FNIEMAIMPLFPUI32FSW *PFNIEMAIMPLFPUI32FSW;
1945	FNIEMAIMPLFPUI32FSW iemAImpl_ficom_r80_by_i32;
1946
1947	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
1948	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fist_r80_to_i32;
1949	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fistt_r80_to_i32;
1950	/** @} */
1951
1952	/** @name FPU operations taking a 64-bit signed integer argument
1953	* @{ */
1954	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI64,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
1955	int64_t *pi64Dst, PCRTFLOAT80U pr80Src));
1956	typedef FNIEMAIMPLFPUSTR80TOI64 *PFNIEMAIMPLFPUSTR80TOI64;
1957
1958	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
1959	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fist_r80_to_i64;
1960	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fistt_r80_to_i64;
1961	/** @} */
1962
1963
1964	/** Temporary type representing a 256-bit vector register. */
1965	typedef struct { uint64_t au64[4]; } IEMVMM256;
1966	/** Temporary type pointing to a 256-bit vector register. */
1967	typedef IEMVMM256 *PIEMVMM256;
1968	/** Temporary type pointing to a const 256-bit vector register. */
1969	typedef IEMVMM256 *PCIEMVMM256;
1970
1971
1972	/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
1973	* @{ */
1974	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t puDst, uint64_t const puSrc));
1975	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
1976	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U128,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
1977	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
1978	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U128,(PX86XSAVEAREA pExtState, PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
1979	typedef FNIEMAIMPLMEDIAF3U128 *PFNIEMAIMPLMEDIAF3U128;
1980	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U256,(PX86XSAVEAREA pExtState, PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
1981	typedef FNIEMAIMPLMEDIAF3U256 *PFNIEMAIMPLMEDIAF3U256;
1982	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U64,(uint64_t puDst, uint64_t const puSrc));
1983	typedef FNIEMAIMPLMEDIAOPTF2U64 *PFNIEMAIMPLMEDIAOPTF2U64;
1984	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128,(PRTUINT128U puDst, PCRTUINT128U puSrc));
1985	typedef FNIEMAIMPLMEDIAOPTF2U128 *PFNIEMAIMPLMEDIAOPTF2U128;
1986	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
1987	typedef FNIEMAIMPLMEDIAOPTF3U128 *PFNIEMAIMPLMEDIAOPTF3U128;
1988	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
1989	typedef FNIEMAIMPLMEDIAOPTF3U256 *PFNIEMAIMPLMEDIAOPTF3U256;
1990	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256,(PRTUINT256U puDst, PCRTUINT256U puSrc));
1991	typedef FNIEMAIMPLMEDIAOPTF2U256 *PFNIEMAIMPLMEDIAOPTF2U256;
1992	FNIEMAIMPLMEDIAF2U64 iemAImpl_pshufb_u64, iemAImpl_pshufb_u64_fallback;
1993	FNIEMAIMPLMEDIAF2U64 iemAImpl_pand_u64, iemAImpl_pandn_u64, iemAImpl_por_u64, iemAImpl_pxor_u64;
1994	FNIEMAIMPLMEDIAF2U64 iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
1995	FNIEMAIMPLMEDIAF2U64 iemAImpl_pcmpgtb_u64, iemAImpl_pcmpgtw_u64, iemAImpl_pcmpgtd_u64;
1996	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddb_u64, iemAImpl_paddsb_u64, iemAImpl_paddusb_u64;
1997	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddw_u64, iemAImpl_paddsw_u64, iemAImpl_paddusw_u64;
1998	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddd_u64;
1999	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddq_u64;
2000	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubb_u64, iemAImpl_psubsb_u64, iemAImpl_psubusb_u64;
2001	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubw_u64, iemAImpl_psubsw_u64, iemAImpl_psubusw_u64;
2002	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubd_u64;
2003	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubq_u64;
2004	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmaddwd_u64;
2005	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmullw_u64, iemAImpl_pmulhw_u64;
2006	FNIEMAIMPLMEDIAF2U64 iemAImpl_pminub_u64, iemAImpl_pmaxub_u64;
2007	FNIEMAIMPLMEDIAF2U64 iemAImpl_pminsw_u64, iemAImpl_pmaxsw_u64;
2008	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsb_u64, iemAImpl_pabsb_u64_fallback;
2009	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsw_u64, iemAImpl_pabsw_u64_fallback;
2010	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsd_u64, iemAImpl_pabsd_u64_fallback;
2011	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignb_u64, iemAImpl_psignb_u64_fallback;
2012	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignw_u64, iemAImpl_psignw_u64_fallback;
2013	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignd_u64, iemAImpl_psignd_u64_fallback;
2014	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddw_u64, iemAImpl_phaddw_u64_fallback;
2015	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddd_u64, iemAImpl_phaddd_u64_fallback;
2016	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubw_u64, iemAImpl_phsubw_u64_fallback;
2017	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubd_u64, iemAImpl_phsubd_u64_fallback;
2018	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddsw_u64, iemAImpl_phaddsw_u64_fallback;
2019	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubsw_u64, iemAImpl_phsubsw_u64_fallback;
2020	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmaddubsw_u64, iemAImpl_pmaddubsw_u64_fallback;
2021	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmulhrsw_u64, iemAImpl_pmulhrsw_u64_fallback;
2022	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmuludq_u64;
2023	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllw_u64, iemAImpl_psrlw_u64, iemAImpl_psraw_u64;
2024	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pslld_u64, iemAImpl_psrld_u64, iemAImpl_psrad_u64;
2025	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllq_u64, iemAImpl_psrlq_u64;
2026	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packsswb_u64, iemAImpl_packuswb_u64;
2027	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packssdw_u64;
2028	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhuw_u64;
2029	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pavgb_u64, iemAImpl_pavgw_u64;
2030	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psadbw_u64;
2031
2032	FNIEMAIMPLMEDIAF2U128 iemAImpl_pshufb_u128, iemAImpl_pshufb_u128_fallback;
2033	FNIEMAIMPLMEDIAF2U128 iemAImpl_pand_u128, iemAImpl_pandn_u128, iemAImpl_por_u128, iemAImpl_pxor_u128;
2034	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
2035	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpeqq_u128, iemAImpl_pcmpeqq_u128_fallback;
2036	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpgtb_u128, iemAImpl_pcmpgtw_u128, iemAImpl_pcmpgtd_u128;
2037	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpgtq_u128, iemAImpl_pcmpgtq_u128_fallback;
2038	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddb_u128, iemAImpl_paddsb_u128, iemAImpl_paddusb_u128;
2039	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddw_u128, iemAImpl_paddsw_u128, iemAImpl_paddusw_u128;
2040	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddd_u128;
2041	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddq_u128;
2042	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubb_u128, iemAImpl_psubsb_u128, iemAImpl_psubusb_u128;
2043	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubw_u128, iemAImpl_psubsw_u128, iemAImpl_psubusw_u128;
2044	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubd_u128;
2045	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubq_u128;
2046	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmullw_u128, iemAImpl_pmullw_u128_fallback;
2047	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulhw_u128;
2048	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulld_u128, iemAImpl_pmulld_u128_fallback;
2049	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaddwd_u128;
2050	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminub_u128;
2051	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminud_u128, iemAImpl_pminud_u128_fallback;
2052	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminuw_u128, iemAImpl_pminuw_u128_fallback;
2053	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsb_u128, iemAImpl_pminsb_u128_fallback;
2054	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsd_u128, iemAImpl_pminsd_u128_fallback;
2055	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsw_u128, iemAImpl_pminsw_u128_fallback;
2056	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxub_u128;
2057	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxud_u128, iemAImpl_pmaxud_u128_fallback;
2058	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxuw_u128, iemAImpl_pmaxuw_u128_fallback;
2059	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsb_u128, iemAImpl_pmaxsb_u128_fallback;
2060	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsw_u128;
2061	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsd_u128, iemAImpl_pmaxsd_u128_fallback;
2062	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsb_u128, iemAImpl_pabsb_u128_fallback;
2063	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsw_u128, iemAImpl_pabsw_u128_fallback;
2064	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsd_u128, iemAImpl_pabsd_u128_fallback;
2065	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignb_u128, iemAImpl_psignb_u128_fallback;
2066	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignw_u128, iemAImpl_psignw_u128_fallback;
2067	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignd_u128, iemAImpl_psignd_u128_fallback;
2068	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddw_u128, iemAImpl_phaddw_u128_fallback;
2069	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddd_u128, iemAImpl_phaddd_u128_fallback;
2070	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubw_u128, iemAImpl_phsubw_u128_fallback;
2071	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubd_u128, iemAImpl_phsubd_u128_fallback;
2072	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddsw_u128, iemAImpl_phaddsw_u128_fallback;
2073	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubsw_u128, iemAImpl_phsubsw_u128_fallback;
2074	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaddubsw_u128, iemAImpl_pmaddubsw_u128_fallback;
2075	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulhrsw_u128, iemAImpl_pmulhrsw_u128_fallback;
2076	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmuludq_u128;
2077	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packsswb_u128, iemAImpl_packuswb_u128;
2078	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packssdw_u128, iemAImpl_packusdw_u128;
2079	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllw_u128, iemAImpl_psrlw_u128, iemAImpl_psraw_u128;
2080	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pslld_u128, iemAImpl_psrld_u128, iemAImpl_psrad_u128;
2081	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllq_u128, iemAImpl_psrlq_u128;
2082	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhuw_u128;
2083	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pavgb_u128, iemAImpl_pavgw_u128;
2084	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psadbw_u128;
2085	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuldq_u128, iemAImpl_pmuldq_u128_fallback;
2086	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpcklps_u128, iemAImpl_unpcklpd_u128;
2087	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpckhps_u128, iemAImpl_unpckhpd_u128;
2088	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phminposuw_u128, iemAImpl_phminposuw_u128_fallback;
2089
2090	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpshufb_u128, iemAImpl_vpshufb_u128_fallback;
2091	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpand_u128, iemAImpl_vpand_u128_fallback;
2092	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpandn_u128, iemAImpl_vpandn_u128_fallback;
2093	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpor_u128, iemAImpl_vpor_u128_fallback;
2094	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpxor_u128, iemAImpl_vpxor_u128_fallback;
2095	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqb_u128, iemAImpl_vpcmpeqb_u128_fallback;
2096	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqw_u128, iemAImpl_vpcmpeqw_u128_fallback;
2097	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqd_u128, iemAImpl_vpcmpeqd_u128_fallback;
2098	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqq_u128, iemAImpl_vpcmpeqq_u128_fallback;
2099	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtb_u128, iemAImpl_vpcmpgtb_u128_fallback;
2100	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtw_u128, iemAImpl_vpcmpgtw_u128_fallback;
2101	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtd_u128, iemAImpl_vpcmpgtd_u128_fallback;
2102	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtq_u128, iemAImpl_vpcmpgtq_u128_fallback;
2103	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddb_u128, iemAImpl_vpaddb_u128_fallback;
2104	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddw_u128, iemAImpl_vpaddw_u128_fallback;
2105	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddd_u128, iemAImpl_vpaddd_u128_fallback;
2106	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddq_u128, iemAImpl_vpaddq_u128_fallback;
2107	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubb_u128, iemAImpl_vpsubb_u128_fallback;
2108	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubw_u128, iemAImpl_vpsubw_u128_fallback;
2109	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubd_u128, iemAImpl_vpsubd_u128_fallback;
2110	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubq_u128, iemAImpl_vpsubq_u128_fallback;
2111	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminub_u128, iemAImpl_vpminub_u128_fallback;
2112	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminuw_u128, iemAImpl_vpminuw_u128_fallback;
2113	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminud_u128, iemAImpl_vpminud_u128_fallback;
2114	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsb_u128, iemAImpl_vpminsb_u128_fallback;
2115	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsw_u128, iemAImpl_vpminsw_u128_fallback;
2116	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsd_u128, iemAImpl_vpminsd_u128_fallback;
2117	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxub_u128, iemAImpl_vpmaxub_u128_fallback;
2118	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxuw_u128, iemAImpl_vpmaxuw_u128_fallback;
2119	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxud_u128, iemAImpl_vpmaxud_u128_fallback;
2120	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsb_u128, iemAImpl_vpmaxsb_u128_fallback;
2121	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsw_u128, iemAImpl_vpmaxsw_u128_fallback;
2122	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsd_u128, iemAImpl_vpmaxsd_u128_fallback;
2123	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpacksswb_u128, iemAImpl_vpacksswb_u128_fallback;
2124	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackssdw_u128, iemAImpl_vpackssdw_u128_fallback;
2125	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackuswb_u128, iemAImpl_vpackuswb_u128_fallback;
2126	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackusdw_u128, iemAImpl_vpackusdw_u128_fallback;
2127	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmullw_u128, iemAImpl_vpmullw_u128_fallback;
2128	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulld_u128, iemAImpl_vpmulld_u128_fallback;
2129	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhw_u128, iemAImpl_vpmulhw_u128_fallback;
2130	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhuw_u128, iemAImpl_vpmulhuw_u128_fallback;
2131	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgb_u128, iemAImpl_vpavgb_u128_fallback;
2132	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgw_u128, iemAImpl_vpavgw_u128_fallback;
2133	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignb_u128, iemAImpl_vpsignb_u128_fallback;
2134	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignw_u128, iemAImpl_vpsignw_u128_fallback;
2135	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignd_u128, iemAImpl_vpsignd_u128_fallback;
2136	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddw_u128, iemAImpl_vphaddw_u128_fallback;
2137	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddd_u128, iemAImpl_vphaddd_u128_fallback;
2138	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubw_u128, iemAImpl_vphsubw_u128_fallback;
2139	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubd_u128, iemAImpl_vphsubd_u128_fallback;
2140	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddsw_u128, iemAImpl_vphaddsw_u128_fallback;
2141	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubsw_u128, iemAImpl_vphsubsw_u128_fallback;
2142	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddubsw_u128, iemAImpl_vpmaddubsw_u128_fallback;
2143	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhrsw_u128, iemAImpl_vpmulhrsw_u128_fallback;
2144	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsadbw_u128, iemAImpl_vpsadbw_u128_fallback;
2145	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuldq_u128, iemAImpl_vpmuldq_u128_fallback;
2146	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuludq_u128, iemAImpl_vpmuludq_u128_fallback;
2147
2148	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsb_u128, iemAImpl_vpabsb_u128_fallback;
2149	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsw_u128, iemAImpl_vpabsd_u128_fallback;
2150	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsd_u128, iemAImpl_vpabsw_u128_fallback;
2151	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vphminposuw_u128, iemAImpl_vphminposuw_u128_fallback;
2152
2153	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpshufb_u256, iemAImpl_vpshufb_u256_fallback;
2154	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpand_u256, iemAImpl_vpand_u256_fallback;
2155	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpandn_u256, iemAImpl_vpandn_u256_fallback;
2156	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpor_u256, iemAImpl_vpor_u256_fallback;
2157	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpxor_u256, iemAImpl_vpxor_u256_fallback;
2158	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqb_u256, iemAImpl_vpcmpeqb_u256_fallback;
2159	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqw_u256, iemAImpl_vpcmpeqw_u256_fallback;
2160	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqd_u256, iemAImpl_vpcmpeqd_u256_fallback;
2161	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqq_u256, iemAImpl_vpcmpeqq_u256_fallback;
2162	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtb_u256, iemAImpl_vpcmpgtb_u256_fallback;
2163	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtw_u256, iemAImpl_vpcmpgtw_u256_fallback;
2164	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtd_u256, iemAImpl_vpcmpgtd_u256_fallback;
2165	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtq_u256, iemAImpl_vpcmpgtq_u256_fallback;
2166	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddb_u256, iemAImpl_vpaddb_u256_fallback;
2167	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddw_u256, iemAImpl_vpaddw_u256_fallback;
2168	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddd_u256, iemAImpl_vpaddd_u256_fallback;
2169	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddq_u256, iemAImpl_vpaddq_u256_fallback;
2170	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubb_u256, iemAImpl_vpsubb_u256_fallback;
2171	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubw_u256, iemAImpl_vpsubw_u256_fallback;
2172	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubd_u256, iemAImpl_vpsubd_u256_fallback;
2173	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubq_u256, iemAImpl_vpsubq_u256_fallback;
2174	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminub_u256, iemAImpl_vpminub_u256_fallback;
2175	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminuw_u256, iemAImpl_vpminuw_u256_fallback;
2176	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminud_u256, iemAImpl_vpminud_u256_fallback;
2177	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsb_u256, iemAImpl_vpminsb_u256_fallback;
2178	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsw_u256, iemAImpl_vpminsw_u256_fallback;
2179	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsd_u256, iemAImpl_vpminsd_u256_fallback;
2180	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxub_u256, iemAImpl_vpmaxub_u256_fallback;
2181	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxuw_u256, iemAImpl_vpmaxuw_u256_fallback;
2182	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxud_u256, iemAImpl_vpmaxud_u256_fallback;
2183	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsb_u256, iemAImpl_vpmaxsb_u256_fallback;
2184	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsw_u256, iemAImpl_vpmaxsw_u256_fallback;
2185	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsd_u256, iemAImpl_vpmaxsd_u256_fallback;
2186	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpacksswb_u256, iemAImpl_vpacksswb_u256_fallback;
2187	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackssdw_u256, iemAImpl_vpackssdw_u256_fallback;
2188	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackuswb_u256, iemAImpl_vpackuswb_u256_fallback;
2189	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackusdw_u256, iemAImpl_vpackusdw_u256_fallback;
2190	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmullw_u256, iemAImpl_vpmullw_u256_fallback;
2191	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulld_u256, iemAImpl_vpmulld_u256_fallback;
2192	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhw_u256, iemAImpl_vpmulhw_u256_fallback;
2193	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhuw_u256, iemAImpl_vpmulhuw_u256_fallback;
2194	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgb_u256, iemAImpl_vpavgb_u256_fallback;
2195	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgw_u256, iemAImpl_vpavgw_u256_fallback;
2196	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignb_u256, iemAImpl_vpsignb_u256_fallback;
2197	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignw_u256, iemAImpl_vpsignw_u256_fallback;
2198	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignd_u256, iemAImpl_vpsignd_u256_fallback;
2199	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddw_u256, iemAImpl_vphaddw_u256_fallback;
2200	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddd_u256, iemAImpl_vphaddd_u256_fallback;
2201	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubw_u256, iemAImpl_vphsubw_u256_fallback;
2202	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubd_u256, iemAImpl_vphsubd_u256_fallback;
2203	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddsw_u256, iemAImpl_vphaddsw_u256_fallback;
2204	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubsw_u256, iemAImpl_vphsubsw_u256_fallback;
2205	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddubsw_u256, iemAImpl_vpmaddubsw_u256_fallback;
2206	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhrsw_u256, iemAImpl_vpmulhrsw_u256_fallback;
2207	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsadbw_u256, iemAImpl_vpsadbw_u256_fallback;
2208	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuldq_u256, iemAImpl_vpmuldq_u256_fallback;
2209	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuludq_u256, iemAImpl_vpmuludq_u256_fallback;
2210
2211	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsb_u256, iemAImpl_vpabsb_u256_fallback;
2212	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsw_u256, iemAImpl_vpabsw_u256_fallback;
2213	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsd_u256, iemAImpl_vpabsd_u256_fallback;
2214	/** @} */
2215
2216	/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
2217	* @{ */
2218	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
2219	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
2220	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpcklbw_u128, iemAImpl_vpunpcklbw_u128_fallback,
2221	iemAImpl_vpunpcklwd_u128, iemAImpl_vpunpcklwd_u128_fallback,
2222	iemAImpl_vpunpckldq_u128, iemAImpl_vpunpckldq_u128_fallback,
2223	iemAImpl_vpunpcklqdq_u128, iemAImpl_vpunpcklqdq_u128_fallback,
2224	iemAImpl_vunpcklps_u128, iemAImpl_vunpcklps_u128_fallback,
2225	iemAImpl_vunpcklpd_u128, iemAImpl_vunpcklpd_u128_fallback,
2226	iemAImpl_vunpckhps_u128, iemAImpl_vunpckhps_u128_fallback,
2227	iemAImpl_vunpckhpd_u128, iemAImpl_vunpckhpd_u128_fallback;
2228
2229	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpcklbw_u256, iemAImpl_vpunpcklbw_u256_fallback,
2230	iemAImpl_vpunpcklwd_u256, iemAImpl_vpunpcklwd_u256_fallback,
2231	iemAImpl_vpunpckldq_u256, iemAImpl_vpunpckldq_u256_fallback,
2232	iemAImpl_vpunpcklqdq_u256, iemAImpl_vpunpcklqdq_u256_fallback,
2233	iemAImpl_vunpcklps_u256, iemAImpl_vunpcklps_u256_fallback,
2234	iemAImpl_vunpcklpd_u256, iemAImpl_vunpcklpd_u256_fallback,
2235	iemAImpl_vunpckhps_u256, iemAImpl_vunpckhps_u256_fallback,
2236	iemAImpl_vunpckhpd_u256, iemAImpl_vunpckhpd_u256_fallback;
2237	/** @} */
2238
2239	/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
2240	* @{ */
2241	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
2242	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
2243	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpckhbw_u128, iemAImpl_vpunpckhbw_u128_fallback,
2244	iemAImpl_vpunpckhwd_u128, iemAImpl_vpunpckhwd_u128_fallback,
2245	iemAImpl_vpunpckhdq_u128, iemAImpl_vpunpckhdq_u128_fallback,
2246	iemAImpl_vpunpckhqdq_u128, iemAImpl_vpunpckhqdq_u128_fallback;
2247	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpckhbw_u256, iemAImpl_vpunpckhbw_u256_fallback,
2248	iemAImpl_vpunpckhwd_u256, iemAImpl_vpunpckhwd_u256_fallback,
2249	iemAImpl_vpunpckhdq_u256, iemAImpl_vpunpckhdq_u256_fallback,
2250	iemAImpl_vpunpckhqdq_u256, iemAImpl_vpunpckhqdq_u256_fallback;
2251	/** @} */
2252
2253	/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
2254	* @{ */
2255	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2256	typedef FNIEMAIMPLMEDIAPSHUFU128 *PFNIEMAIMPLMEDIAPSHUFU128;
2257	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
2258	typedef FNIEMAIMPLMEDIAPSHUFU256 *PFNIEMAIMPLMEDIAPSHUFU256;
2259	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw_u64,(uint64_t puDst, uint64_t const puSrc, uint8_t bEvil));
2260	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_pshufhw_u128, iemAImpl_pshuflw_u128, iemAImpl_pshufd_u128;
2261	#ifndef IEM_WITHOUT_ASSEMBLY
2262	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256, iemAImpl_vpshuflw_u256, iemAImpl_vpshufd_u256;
2263	#endif
2264	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256_fallback, iemAImpl_vpshuflw_u256_fallback, iemAImpl_vpshufd_u256_fallback;
2265	/** @} */
2266
2267	/** @name Media (SSE/MMX/AVX) operation: Shift Immediate Stuff (evil)
2268	* @{ */
2269	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU64,(uint64_t *puDst, uint8_t bShift));
2270	typedef FNIEMAIMPLMEDIAPSHIFTU64 *PFNIEMAIMPLMEDIAPSHIFTU64;
2271	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU128,(PRTUINT128U puDst, uint8_t bShift));
2272	typedef FNIEMAIMPLMEDIAPSHIFTU128 *PFNIEMAIMPLMEDIAPSHIFTU128;
2273	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU256,(PRTUINT256U puDst, uint8_t bShift));
2274	typedef FNIEMAIMPLMEDIAPSHIFTU256 *PFNIEMAIMPLMEDIAPSHIFTU256;
2275	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psllw_imm_u64, iemAImpl_pslld_imm_u64, iemAImpl_psllq_imm_u64;
2276	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psrlw_imm_u64, iemAImpl_psrld_imm_u64, iemAImpl_psrlq_imm_u64;
2277	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psraw_imm_u64, iemAImpl_psrad_imm_u64;
2278	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psllw_imm_u128, iemAImpl_pslld_imm_u128, iemAImpl_psllq_imm_u128;
2279	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psrlw_imm_u128, iemAImpl_psrld_imm_u128, iemAImpl_psrlq_imm_u128;
2280	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psraw_imm_u128, iemAImpl_psrad_imm_u128;
2281	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_pslldq_imm_u128, iemAImpl_psrldq_imm_u128;
2282	/** @} */
2283
2284	/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
2285	* @{ */
2286	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(uint64_t pu64Dst, uint64_t const puSrc));
2287	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(uint64_t *pu64Dst, PCRTUINT128U puSrc));
2288	#ifndef IEM_WITHOUT_ASSEMBLY
2289	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
2290	#endif
2291	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256_fallback,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
2292	/** @} */
2293
2294	/** @name Media (SSE/MMX/AVX) operations: Variable Blend Packed Bytes/R32/R64.
2295	* @{ */
2296	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puMask));
2297	typedef FNIEMAIMPLBLENDU128 *PFNIEMAIMPLBLENDU128;
2298	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, PCRTUINT128U puMask));
2299	typedef FNIEMAIMPLAVXBLENDU128 *PFNIEMAIMPLAVXBLENDU128;
2300	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, PCRTUINT256U puMask));
2301	typedef FNIEMAIMPLAVXBLENDU256 *PFNIEMAIMPLAVXBLENDU256;
2302
2303	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128;
2304	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128_fallback;
2305	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128;
2306	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128_fallback;
2307	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256;
2308	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256_fallback;
2309
2310	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128;
2311	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128_fallback;
2312	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128;
2313	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128_fallback;
2314	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256;
2315	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256_fallback;
2316
2317	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128;
2318	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128_fallback;
2319	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128;
2320	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128_fallback;
2321	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256;
2322	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256_fallback;
2323	/** @} */
2324
2325
2326	/** @name Media (SSE/MMX/AVX) operation: Sort this later
2327	* @{ */
2328	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
2329	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
2330	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovshdup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
2331	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovshdup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
2332	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
2333	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
2334
2335	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2336	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2337	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2338	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2339	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2340
2341	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2342	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2343	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2344	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2345	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2346
2347	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2348	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2349	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
2350	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2351	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2352
2353	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2354	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2355	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2356	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2357	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2358
2359	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2360	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2361	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2362	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2363	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2364
2365	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2366	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2367	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2368	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2369	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2370
2371	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2372	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2373	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2374	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2375	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2376
2377	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2378	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2379	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2380	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2381	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2382
2383	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2384	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2385	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
2386	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2387	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2388
2389	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2390	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2391	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2392	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2393	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2394
2395	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2396	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2397	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2398	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2399	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2400
2401	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2402	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2403	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2404	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2405	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2406
2407	IEM_DECL_IMPL_DEF(void, iemAImpl_shufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2408	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2409	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2410	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2411	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2412
2413	IEM_DECL_IMPL_DEF(void, iemAImpl_shufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2414	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2415	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2416	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2417	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2418
2419	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
2420	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64_fallback,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
2421
2422	IEM_DECL_IMPL_DEF(void, iemAImpl_pinsrw_u64,(uint64_t *pu64Dst, uint16_t u16Src, uint8_t bEvil));
2423	IEM_DECL_IMPL_DEF(void, iemAImpl_pinsrw_u128,(PRTUINT128U puDst, uint16_t u16Src, uint8_t bEvil));
2424	IEM_DECL_IMPL_DEF(void, iemAImpl_vpinsrw_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint16_t u16Src, uint8_t bEvil));
2425	IEM_DECL_IMPL_DEF(void, iemAImpl_vpinsrw_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint16_t u16Src, uint8_t bEvil));
2426
2427	IEM_DECL_IMPL_DEF(void, iemAImpl_pextrw_u64,(uint16_t *pu16Dst, uint64_t u64Src, uint8_t bEvil));
2428	IEM_DECL_IMPL_DEF(void, iemAImpl_pextrw_u128,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
2429	IEM_DECL_IMPL_DEF(void, iemAImpl_vpextrw_u128,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
2430	IEM_DECL_IMPL_DEF(void, iemAImpl_vpextrw_u128_fallback,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
2431
2432	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2433	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2434	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2435	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
2436	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
2437
2438	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2439	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2440	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2441	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
2442	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
2443
2444
2445	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2446	typedef FNIEMAIMPLMEDIAOPTF2U128IMM8 *PFNIEMAIMPLMEDIAOPTF2U128IMM8;
2447	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2448	typedef FNIEMAIMPLMEDIAOPTF3U128IMM8 *PFNIEMAIMPLMEDIAOPTF3U128IMM8;
2449	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2450	typedef FNIEMAIMPLMEDIAOPTF3U256IMM8 *PFNIEMAIMPLMEDIAOPTF3U256IMM8;
2451
2452	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_palignr_u128, iemAImpl_palignr_u128_fallback;
2453	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pblendw_u128, iemAImpl_pblendw_u128_fallback;
2454	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendps_u128, iemAImpl_blendps_u128_fallback;
2455	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendpd_u128, iemAImpl_blendpd_u128_fallback;
2456
2457	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpalignr_u128, iemAImpl_vpalignr_u128_fallback;
2458	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendw_u128, iemAImpl_vpblendw_u128_fallback;
2459	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendps_u128, iemAImpl_vblendps_u128_fallback;
2460	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendpd_u128, iemAImpl_vblendpd_u128_fallback;
2461
2462	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpalignr_u256, iemAImpl_vpalignr_u256_fallback;
2463	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendw_u256, iemAImpl_vpblendw_u256_fallback;
2464	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendps_u256, iemAImpl_vblendps_u256_fallback;
2465	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendpd_u256, iemAImpl_vblendpd_u256_fallback;
2466
2467	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesimc_u128, iemAImpl_aesimc_u128_fallback;
2468	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenc_u128, iemAImpl_aesenc_u128_fallback;
2469	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenclast_u128, iemAImpl_aesenclast_u128_fallback;
2470	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdec_u128, iemAImpl_aesdec_u128_fallback;
2471	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdeclast_u128, iemAImpl_aesdeclast_u128_fallback;
2472
2473	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesimc_u128, iemAImpl_vaesimc_u128_fallback;
2474	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenc_u128, iemAImpl_vaesenc_u128_fallback;
2475	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenclast_u128, iemAImpl_vaesenclast_u128_fallback;
2476	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdec_u128, iemAImpl_vaesdec_u128_fallback;
2477	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdeclast_u128, iemAImpl_vaesdeclast_u128_fallback;
2478
2479	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_aeskeygenassist_u128, iemAImpl_aeskeygenassist_u128_fallback;
2480
2481	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vaeskeygenassist_u128, iemAImpl_vaeskeygenassist_u128_fallback;
2482
2483	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1nexte_u128, iemAImpl_sha1nexte_u128_fallback;
2484	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg1_u128, iemAImpl_sha1msg1_u128_fallback;
2485	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg2_u128, iemAImpl_sha1msg2_u128_fallback;
2486	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg1_u128, iemAImpl_sha256msg1_u128_fallback;
2487	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg2_u128, iemAImpl_sha256msg2_u128_fallback;
2488	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_sha1rnds4_u128, iemAImpl_sha1rnds4_u128_fallback;
2489	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
2490	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
2491
2492	typedef struct IEMPCMPISTRXSRC
2493	{
2494	RTUINT128U uSrc1;
2495	RTUINT128U uSrc2;
2496	} IEMPCMPISTRXSRC;
2497	typedef IEMPCMPISTRXSRC *PIEMPCMPISTRXSRC;
2498	typedef const IEMPCMPISTRXSRC *PCIEMPCMPISTRXSRC;
2499
2500	typedef struct IEMPCMPESTRXSRC
2501	{
2502	RTUINT128U uSrc1;
2503	RTUINT128U uSrc2;
2504	uint64_t u64Rax;
2505	uint64_t u64Rdx;
2506	} IEMPCMPESTRXSRC;
2507	typedef IEMPCMPESTRXSRC *PIEMPCMPESTRXSRC;
2508	typedef const IEMPCMPESTRXSRC *PCIEMPCMPESTRXSRC;
2509
2510	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPISTRIU128IMM8,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
2511	typedef FNIEMAIMPLPCMPISTRIU128IMM8 *PFNIEMAIMPLPCMPISTRIU128IMM8;
2512	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRIU128IMM8,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
2513	typedef FNIEMAIMPLPCMPESTRIU128IMM8 *PFNIEMAIMPLPCMPESTRIU128IMM8;
2514
2515	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPISTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
2516	typedef FNIEMAIMPLPCMPISTRMU128IMM8 *PFNIEMAIMPLPCMPISTRMU128IMM8;
2517	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
2518	typedef FNIEMAIMPLPCMPESTRMU128IMM8 *PFNIEMAIMPLPCMPESTRMU128IMM8;
2519
2520	FNIEMAIMPLPCMPISTRIU128IMM8 iemAImpl_pcmpistri_u128, iemAImpl_pcmpistri_u128_fallback;
2521	FNIEMAIMPLPCMPESTRIU128IMM8 iemAImpl_pcmpestri_u128, iemAImpl_pcmpestri_u128_fallback;
2522	FNIEMAIMPLPCMPISTRMU128IMM8 iemAImpl_pcmpistrm_u128, iemAImpl_pcmpistrm_u128_fallback;
2523	FNIEMAIMPLPCMPESTRMU128IMM8 iemAImpl_pcmpestrm_u128, iemAImpl_pcmpestrm_u128_fallback;
2524
2525	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pclmulqdq_u128, iemAImpl_pclmulqdq_u128_fallback;
2526	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpclmulqdq_u128, iemAImpl_vpclmulqdq_u128_fallback;
2527
2528	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_mpsadbw_u128, iemAImpl_mpsadbw_u128_fallback;
2529	/** @} */
2530
2531	/** @name Media Odds and Ends
2532	* @{ */
2533	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U8,(uint32_t *puDst, uint8_t uSrc));
2534	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U16,(uint32_t *puDst, uint16_t uSrc));
2535	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U32,(uint32_t *puDst, uint32_t uSrc));
2536	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U64,(uint32_t *puDst, uint64_t uSrc));
2537	FNIEMAIMPLCR32U8 iemAImpl_crc32_u8, iemAImpl_crc32_u8_fallback;
2538	FNIEMAIMPLCR32U16 iemAImpl_crc32_u16, iemAImpl_crc32_u16_fallback;
2539	FNIEMAIMPLCR32U32 iemAImpl_crc32_u32, iemAImpl_crc32_u32_fallback;
2540	FNIEMAIMPLCR32U64 iemAImpl_crc32_u64, iemAImpl_crc32_u64_fallback;
2541
2542	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL128,(PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint32_t *pEFlags));
2543	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL256,(PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint32_t *pEFlags));
2544	FNIEMAIMPLF2EFL128 iemAImpl_ptest_u128;
2545	FNIEMAIMPLF2EFL256 iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback;
2546
2547	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I32U64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int32_t pi32Dst, const uint64_t pu64Src)); / pu64Src is a double precision floating point. */
2548	typedef FNIEMAIMPLSSEF2I32U64 *PFNIEMAIMPLSSEF2I32U64;
2549	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I64U64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int64_t pi64Dst, const uint64_t pu64Src)); / pu64Src is a double precision floating point. */
2550	typedef FNIEMAIMPLSSEF2I64U64 *PFNIEMAIMPLSSEF2I64U64;
2551	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I32U32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int32_t pi32Dst, const uint32_t pu32Src)); / pu32Src is a single precision floating point. */
2552	typedef FNIEMAIMPLSSEF2I32U32 *PFNIEMAIMPLSSEF2I32U32;
2553	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I64U32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int64_t pi64Dst, const uint32_t pu32Src)); / pu32Src is a single precision floating point. */
2554	typedef FNIEMAIMPLSSEF2I64U32 *PFNIEMAIMPLSSEF2I64U32;
2555
2556	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvttsd2si_i32_r64;
2557	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvtsd2si_i32_r64;
2558
2559	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvttsd2si_i64_r64;
2560	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvtsd2si_i64_r64;
2561
2562	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvttss2si_i32_r32;
2563	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvtss2si_i32_r32;
2564
2565	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvttss2si_i64_r32;
2566	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvtss2si_i64_r32;
2567
2568	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R32I32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT32U pr32Dst, const int32_t pi32Src));
2569	typedef FNIEMAIMPLSSEF2R32I32 *PFNIEMAIMPLSSEF2R32I32;
2570	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R32I64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT32U pr32Dst, const int64_t pi64Src));
2571	typedef FNIEMAIMPLSSEF2R32I64 *PFNIEMAIMPLSSEF2R32I64;
2572
2573	FNIEMAIMPLSSEF2R32I32 iemAImpl_cvtsi2ss_r32_i32;
2574	FNIEMAIMPLSSEF2R32I64 iemAImpl_cvtsi2ss_r32_i64;
2575
2576	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R64I32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT64U pr64Dst, const int32_t pi32Src));
2577	typedef FNIEMAIMPLSSEF2R64I32 *PFNIEMAIMPLSSEF2R64I32;
2578	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R64I64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT64U pr64Dst, const int64_t pi64Src));
2579	typedef FNIEMAIMPLSSEF2R64I64 *PFNIEMAIMPLSSEF2R64I64;
2580
2581	FNIEMAIMPLSSEF2R64I32 iemAImpl_cvtsi2sd_r64_i32;
2582	FNIEMAIMPLSSEF2R64I64 iemAImpl_cvtsi2sd_r64_i64;
2583
2584
2585	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFLMXCSR128,(uint32_t pfMxcsr, uint32_t pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
2586	typedef FNIEMAIMPLF2EFLMXCSR128 *PFNIEMAIMPLF2EFLMXCSR128;
2587
2588	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_ucomiss_u128;
2589	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback;
2590
2591	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_ucomisd_u128;
2592	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback;
2593
2594	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_comiss_u128;
2595	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback;
2596
2597	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_comisd_u128;
2598	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback;
2599
2600
2601	typedef struct IEMMEDIAF2XMMSRC
2602	{
2603	X86XMMREG uSrc1;
2604	X86XMMREG uSrc2;
2605	} IEMMEDIAF2XMMSRC;
2606	typedef IEMMEDIAF2XMMSRC *PIEMMEDIAF2XMMSRC;
2607	typedef const IEMMEDIAF2XMMSRC *PCIEMMEDIAF2XMMSRC;
2608
2609	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRF2XMMIMM8,(uint32_t *pfMxcsr, PX86XMMREG puDst, PCIEMMEDIAF2XMMSRC puSrc, uint8_t bEvil));
2610	typedef FNIEMAIMPLMXCSRF2XMMIMM8 *PFNIEMAIMPLMXCSRF2XMMIMM8;
2611
2612	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpps_u128;
2613	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmppd_u128;
2614	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpss_u128;
2615	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpsd_u128;
2616	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundss_u128;
2617	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundsd_u128;
2618
2619	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundps_u128, iemAImpl_roundps_u128_fallback;
2620	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundpd_u128, iemAImpl_roundpd_u128_fallback;
2621
2622	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_dpps_u128, iemAImpl_dpps_u128_fallback;
2623	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_dppd_u128, iemAImpl_dppd_u128_fallback;
2624
2625	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU64U128,(uint32_t pfMxcsr, uint64_t pu64Dst, PCX86XMMREG pSrc));
2626	typedef FNIEMAIMPLMXCSRU64U128 *PFNIEMAIMPLMXCSRU64U128;
2627
2628	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvtpd2pi_u128;
2629	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvttpd2pi_u128;
2630
2631	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU128U64,(uint32_t *pfMxcsr, PX86XMMREG pDst, uint64_t u64Src));
2632	typedef FNIEMAIMPLMXCSRU128U64 *PFNIEMAIMPLMXCSRU128U64;
2633
2634	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2ps_u128;
2635	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2pd_u128;
2636
2637	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU64U64,(uint32_t pfMxcsr, uint64_t pu64Dst, uint64_t u64Src));
2638	typedef FNIEMAIMPLMXCSRU64U64 *PFNIEMAIMPLMXCSRU64U64;
2639
2640	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvtps2pi_u128;
2641	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvttps2pi_u128;
2642
2643	/** @} */
2644
2645
2646	/** @name Function tables.
2647	* @{
2648	*/
2649
2650	/**
2651	* Function table for a binary operator providing implementation based on
2652	* operand size.
2653	*/
2654	typedef struct IEMOPBINSIZES
2655	{
2656	PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
2657	PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
2658	PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
2659	PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
2660	} IEMOPBINSIZES;
2661	/** Pointer to a binary operator function table. */
2662	typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
2663
2664
2665	/**
2666	* Function table for a unary operator providing implementation based on
2667	* operand size.
2668	*/
2669	typedef struct IEMOPUNARYSIZES
2670	{
2671	PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
2672	PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
2673	PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
2674	PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
2675	} IEMOPUNARYSIZES;
2676	/** Pointer to a unary operator function table. */
2677	typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
2678
2679
2680	/**
2681	* Function table for a shift operator providing implementation based on
2682	* operand size.
2683	*/
2684	typedef struct IEMOPSHIFTSIZES
2685	{
2686	PFNIEMAIMPLSHIFTU8 pfnNormalU8;
2687	PFNIEMAIMPLSHIFTU16 pfnNormalU16;
2688	PFNIEMAIMPLSHIFTU32 pfnNormalU32;
2689	PFNIEMAIMPLSHIFTU64 pfnNormalU64;
2690	} IEMOPSHIFTSIZES;
2691	/** Pointer to a shift operator function table. */
2692	typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
2693
2694
2695	/**
2696	* Function table for a multiplication or division operation.
2697	*/
2698	typedef struct IEMOPMULDIVSIZES
2699	{
2700	PFNIEMAIMPLMULDIVU8 pfnU8;
2701	PFNIEMAIMPLMULDIVU16 pfnU16;
2702	PFNIEMAIMPLMULDIVU32 pfnU32;
2703	PFNIEMAIMPLMULDIVU64 pfnU64;
2704	} IEMOPMULDIVSIZES;
2705	/** Pointer to a multiplication or division operation function table. */
2706	typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
2707
2708
2709	/**
2710	* Function table for a double precision shift operator providing implementation
2711	* based on operand size.
2712	*/
2713	typedef struct IEMOPSHIFTDBLSIZES
2714	{
2715	PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
2716	PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
2717	PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
2718	} IEMOPSHIFTDBLSIZES;
2719	/** Pointer to a double precision shift function table. */
2720	typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
2721
2722
2723	/**
2724	* Function table for media instruction taking two full sized media source
2725	* registers and one full sized destination register (AVX).
2726	*/
2727	typedef struct IEMOPMEDIAF3
2728	{
2729	PFNIEMAIMPLMEDIAF3U128 pfnU128;
2730	PFNIEMAIMPLMEDIAF3U256 pfnU256;
2731	} IEMOPMEDIAF3;
2732	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
2733	typedef IEMOPMEDIAF3 const *PCIEMOPMEDIAF3;
2734
2735	/** @def IEMOPMEDIAF3_INIT_VARS_EX
2736	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2737	* given functions as initializers. For use in AVX functions where a pair of
2738	* functions are only used once and the function table need not be public. */
2739	#ifndef TST_IEM_CHECK_MC
2740	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2741	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2742	static IEMOPMEDIAF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2743	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2744	# else
2745	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2746	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2747	# endif
2748	#else
2749	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2750	#endif
2751	/** @def IEMOPMEDIAF3_INIT_VARS
2752	* Generate AVX function tables for the @a a_InstrNm instruction.
2753	* @sa IEMOPMEDIAF3_INIT_VARS_EX */
2754	#define IEMOPMEDIAF3_INIT_VARS(a_InstrNm) \
2755	IEMOPMEDIAF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2756	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2757
2758	/**
2759	* Function table for media instruction taking two full sized media source
2760	* registers and one full sized destination register, but no additional state
2761	* (AVX).
2762	*/
2763	typedef struct IEMOPMEDIAOPTF3
2764	{
2765	PFNIEMAIMPLMEDIAOPTF3U128 pfnU128;
2766	PFNIEMAIMPLMEDIAOPTF3U256 pfnU256;
2767	} IEMOPMEDIAOPTF3;
2768	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
2769	typedef IEMOPMEDIAOPTF3 const *PCIEMOPMEDIAOPTF3;
2770
2771	/** @def IEMOPMEDIAOPTF3_INIT_VARS_EX
2772	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2773	* given functions as initializers. For use in AVX functions where a pair of
2774	* functions are only used once and the function table need not be public. */
2775	#ifndef TST_IEM_CHECK_MC
2776	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2777	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2778	static IEMOPMEDIAOPTF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2779	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2780	# else
2781	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2782	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2783	# endif
2784	#else
2785	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2786	#endif
2787	/** @def IEMOPMEDIAOPTF3_INIT_VARS
2788	* Generate AVX function tables for the @a a_InstrNm instruction.
2789	* @sa IEMOPMEDIAOPTF3_INIT_VARS_EX */
2790	#define IEMOPMEDIAOPTF3_INIT_VARS(a_InstrNm) \
2791	IEMOPMEDIAOPTF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2792	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2793
2794	/**
2795	* Function table for media instruction taking one full sized media source
2796	* registers and one full sized destination register, but no additional state
2797	* (AVX).
2798	*/
2799	typedef struct IEMOPMEDIAOPTF2
2800	{
2801	PFNIEMAIMPLMEDIAOPTF2U128 pfnU128;
2802	PFNIEMAIMPLMEDIAOPTF2U256 pfnU256;
2803	} IEMOPMEDIAOPTF2;
2804	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
2805	typedef IEMOPMEDIAOPTF2 const *PCIEMOPMEDIAOPTF2;
2806
2807	/** @def IEMOPMEDIAOPTF2_INIT_VARS_EX
2808	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2809	* given functions as initializers. For use in AVX functions where a pair of
2810	* functions are only used once and the function table need not be public. */
2811	#ifndef TST_IEM_CHECK_MC
2812	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2813	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2814	static IEMOPMEDIAOPTF2 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2815	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2816	# else
2817	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2818	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2819	# endif
2820	#else
2821	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2822	#endif
2823	/** @def IEMOPMEDIAOPTF2_INIT_VARS
2824	* Generate AVX function tables for the @a a_InstrNm instruction.
2825	* @sa IEMOPMEDIAOPTF2_INIT_VARS_EX */
2826	#define IEMOPMEDIAOPTF2_INIT_VARS(a_InstrNm) \
2827	IEMOPMEDIAOPTF2_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2828	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2829
2830	/**
2831	* Function table for media instruction taking two full sized media source
2832	* registers and one full sized destination register and an 8-bit immediate, but no additional state
2833	* (AVX).
2834	*/
2835	typedef struct IEMOPMEDIAOPTF3IMM8
2836	{
2837	PFNIEMAIMPLMEDIAOPTF3U128IMM8 pfnU128;
2838	PFNIEMAIMPLMEDIAOPTF3U256IMM8 pfnU256;
2839	} IEMOPMEDIAOPTF3IMM8;
2840	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
2841	typedef IEMOPMEDIAOPTF3IMM8 const *PCIEMOPMEDIAOPTF3IMM8;
2842
2843	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX
2844	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2845	* given functions as initializers. For use in AVX functions where a pair of
2846	* functions are only used once and the function table need not be public. */
2847	#ifndef TST_IEM_CHECK_MC
2848	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2849	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2850	static IEMOPMEDIAOPTF3IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2851	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2852	# else
2853	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2854	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2855	# endif
2856	#else
2857	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2858	#endif
2859	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS
2860	* Generate AVX function tables for the @a a_InstrNm instruction.
2861	* @sa IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX */
2862	#define IEMOPMEDIAOPTF3IMM8_INIT_VARS(a_InstrNm) \
2863	IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2864	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2865	/** @} */
2866
2867
2868	/**
2869	* Function table for blend type instruction taking three full sized media source
2870	* registers and one full sized destination register, but no additional state
2871	* (AVX).
2872	*/
2873	typedef struct IEMOPBLENDOP
2874	{
2875	PFNIEMAIMPLAVXBLENDU128 pfnU128;
2876	PFNIEMAIMPLAVXBLENDU256 pfnU256;
2877	} IEMOPBLENDOP;
2878	/** Pointer to a media operation function table for 4 full sized ops (AVX). */
2879	typedef IEMOPBLENDOP const *PCIEMOPBLENDOP;
2880
2881	/** @def IEMOPBLENDOP_INIT_VARS_EX
2882	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2883	* given functions as initializers. For use in AVX functions where a pair of
2884	* functions are only used once and the function table need not be public. */
2885	#ifndef TST_IEM_CHECK_MC
2886	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2887	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2888	static IEMOPBLENDOP const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2889	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2890	# else
2891	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2892	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2893	# endif
2894	#else
2895	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2896	#endif
2897	/** @def IEMOPBLENDOP_INIT_VARS
2898	* Generate AVX function tables for the @a a_InstrNm instruction.
2899	* @sa IEMOPBLENDOP_INIT_VARS_EX */
2900	#define IEMOPBLENDOP_INIT_VARS(a_InstrNm) \
2901	IEMOPBLENDOP_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2902	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2903
2904
2905	/** @name SSE/AVX single/double precision floating point operations.
2906	* @{ */
2907	/**
2908	* A SSE result.
2909	*/
2910	typedef struct IEMSSERESULT
2911	{
2912	/** The output value. */
2913	X86XMMREG uResult;
2914	/** The output status. */
2915	uint32_t MXCSR;
2916	} IEMSSERESULT;
2917	AssertCompileMemberOffset(IEMSSERESULT, MXCSR, 128 / 8);
2918	/** Pointer to a SSE result. */
2919	typedef IEMSSERESULT *PIEMSSERESULT;
2920	/** Pointer to a const SSE result. */
2921	typedef IEMSSERESULT const *PCIEMSSERESULT;
2922
2923
2924	/**
2925	* A AVX128 result.
2926	*/
2927	typedef struct IEMAVX128RESULT
2928	{
2929	/** The output value. */
2930	X86XMMREG uResult;
2931	/** The output status. */
2932	uint32_t MXCSR;
2933	} IEMAVX128RESULT;
2934	AssertCompileMemberOffset(IEMAVX128RESULT, MXCSR, 128 / 8);
2935	/** Pointer to a AVX128 result. */
2936	typedef IEMAVX128RESULT *PIEMAVX128RESULT;
2937	/** Pointer to a const AVX128 result. */
2938	typedef IEMAVX128RESULT const *PCIEMAVX128RESULT;
2939
2940
2941	/**
2942	* A AVX256 result.
2943	*/
2944	typedef struct IEMAVX256RESULT
2945	{
2946	/** The output value. */
2947	X86YMMREG uResult;
2948	/** The output status. */
2949	uint32_t MXCSR;
2950	} IEMAVX256RESULT;
2951	AssertCompileMemberOffset(IEMAVX256RESULT, MXCSR, 256 / 8);
2952	/** Pointer to a AVX256 result. */
2953	typedef IEMAVX256RESULT *PIEMAVX256RESULT;
2954	/** Pointer to a const AVX256 result. */
2955	typedef IEMAVX256RESULT const *PCIEMAVX256RESULT;
2956
2957
2958	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
2959	typedef FNIEMAIMPLFPSSEF2U128 *PFNIEMAIMPLFPSSEF2U128;
2960	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128R32,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
2961	typedef FNIEMAIMPLFPSSEF2U128R32 *PFNIEMAIMPLFPSSEF2U128R32;
2962	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128R64,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
2963	typedef FNIEMAIMPLFPSSEF2U128R64 *PFNIEMAIMPLFPSSEF2U128R64;
2964
2965	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
2966	typedef FNIEMAIMPLFPAVXF3U128 *PFNIEMAIMPLFPAVXF3U128;
2967	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128R32,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
2968	typedef FNIEMAIMPLFPAVXF3U128R32 *PFNIEMAIMPLFPAVXF3U128R32;
2969	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128R64,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
2970	typedef FNIEMAIMPLFPAVXF3U128R64 *PFNIEMAIMPLFPAVXF3U128R64;
2971
2972	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U256,(PX86XSAVEAREA pExtState, PIEMAVX256RESULT pResult, PCX86YMMREG puSrc1, PCX86YMMREG puSrc2));
2973	typedef FNIEMAIMPLFPAVXF3U256 *PFNIEMAIMPLFPAVXF3U256;
2974
2975	FNIEMAIMPLFPSSEF2U128 iemAImpl_addps_u128;
2976	FNIEMAIMPLFPSSEF2U128 iemAImpl_addpd_u128;
2977	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulps_u128;
2978	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulpd_u128;
2979	FNIEMAIMPLFPSSEF2U128 iemAImpl_subps_u128;
2980	FNIEMAIMPLFPSSEF2U128 iemAImpl_subpd_u128;
2981	FNIEMAIMPLFPSSEF2U128 iemAImpl_minps_u128;
2982	FNIEMAIMPLFPSSEF2U128 iemAImpl_minpd_u128;
2983	FNIEMAIMPLFPSSEF2U128 iemAImpl_divps_u128;
2984	FNIEMAIMPLFPSSEF2U128 iemAImpl_divpd_u128;
2985	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxps_u128;
2986	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxpd_u128;
2987	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddps_u128;
2988	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddpd_u128;
2989	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubps_u128;
2990	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubpd_u128;
2991	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtps_u128;
2992	FNIEMAIMPLFPSSEF2U128 iemAImpl_rsqrtps_u128;
2993	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtpd_u128;
2994	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubps_u128;
2995	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubpd_u128;
2996	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2ps_u128;
2997	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2pd_u128;
2998
2999	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2ps_u128;
3000	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2dq_u128;
3001	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttps2dq_u128;
3002	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttpd2dq_u128;
3003	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2pd_u128;
3004	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2dq_u128;
3005
3006	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_addss_u128_r32;
3007	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_addsd_u128_r64;
3008	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_mulss_u128_r32;
3009	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_mulsd_u128_r64;
3010	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_subss_u128_r32;
3011	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_subsd_u128_r64;
3012	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_minss_u128_r32;
3013	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_minsd_u128_r64;
3014	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_divss_u128_r32;
3015	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_divsd_u128_r64;
3016	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_maxss_u128_r32;
3017	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_maxsd_u128_r64;
3018	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_cvtss2sd_u128_r32;
3019	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_cvtsd2ss_u128_r64;
3020	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_sqrtss_u128_r32;
3021	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_sqrtsd_u128_r64;
3022	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_rsqrtss_u128_r32;
3023
3024	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddps_u128, iemAImpl_vaddps_u128_fallback;
3025	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddpd_u128, iemAImpl_vaddpd_u128_fallback;
3026	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulps_u128, iemAImpl_vmulps_u128_fallback;
3027	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulpd_u128, iemAImpl_vmulpd_u128_fallback;
3028	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubps_u128, iemAImpl_vsubps_u128_fallback;
3029	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubpd_u128, iemAImpl_vsubpd_u128_fallback;
3030	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminps_u128, iemAImpl_vminps_u128_fallback;
3031	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminpd_u128, iemAImpl_vminpd_u128_fallback;
3032	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivps_u128, iemAImpl_vdivps_u128_fallback;
3033	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivpd_u128, iemAImpl_vdivpd_u128_fallback;
3034	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxps_u128, iemAImpl_vmaxps_u128_fallback;
3035	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxpd_u128, iemAImpl_vmaxpd_u128_fallback;
3036	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddps_u128, iemAImpl_vhaddps_u128_fallback;
3037	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddpd_u128, iemAImpl_vhaddpd_u128_fallback;
3038	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubps_u128, iemAImpl_vhsubps_u128_fallback;
3039	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubpd_u128, iemAImpl_vhsubpd_u128_fallback;
3040	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtps_u128, iemAImpl_vsqrtps_u128_fallback;
3041	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtpd_u128, iemAImpl_vsqrtpd_u128_fallback;
3042	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubps_u128, iemAImpl_vaddsubps_u128_fallback;
3043	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubpd_u128, iemAImpl_vaddsubpd_u128_fallback;
3044	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtpd2ps_u128, iemAImpl_vcvtpd2ps_u128_fallback;
3045	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtps2pd_u128, iemAImpl_vcvtps2pd_u128_fallback;
3046
3047	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vaddss_u128_r32, iemAImpl_vaddss_u128_r32_fallback;
3048	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vaddsd_u128_r64, iemAImpl_vaddsd_u128_r64_fallback;
3049	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmulss_u128_r32, iemAImpl_vmulss_u128_r32_fallback;
3050	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmulsd_u128_r64, iemAImpl_vmulsd_u128_r64_fallback;
3051	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsubss_u128_r32, iemAImpl_vsubss_u128_r32_fallback;
3052	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsubsd_u128_r64, iemAImpl_vsubsd_u128_r64_fallback;
3053	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vminss_u128_r32, iemAImpl_vminss_u128_r32_fallback;
3054	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vminsd_u128_r64, iemAImpl_vminsd_u128_r64_fallback;
3055	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vdivss_u128_r32, iemAImpl_vdivss_u128_r32_fallback;
3056	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vdivsd_u128_r64, iemAImpl_vdivsd_u128_r64_fallback;
3057	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmaxss_u128_r32, iemAImpl_vmaxss_u128_r32_fallback;
3058	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmaxsd_u128_r64, iemAImpl_vmaxsd_u128_r64_fallback;
3059	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsqrtss_u128_r32, iemAImpl_vsqrtss_u128_r32_fallback;
3060	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsqrtsd_u128_r64, iemAImpl_vsqrtsd_u128_r64_fallback;
3061
3062	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddps_u256, iemAImpl_vaddps_u256_fallback;
3063	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddpd_u256, iemAImpl_vaddpd_u256_fallback;
3064	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulps_u256, iemAImpl_vmulps_u256_fallback;
3065	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulpd_u256, iemAImpl_vmulpd_u256_fallback;
3066	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubps_u256, iemAImpl_vsubps_u256_fallback;
3067	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubpd_u256, iemAImpl_vsubpd_u256_fallback;
3068	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminps_u256, iemAImpl_vminps_u256_fallback;
3069	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminpd_u256, iemAImpl_vminpd_u256_fallback;
3070	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivps_u256, iemAImpl_vdivps_u256_fallback;
3071	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivpd_u256, iemAImpl_vdivpd_u256_fallback;
3072	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxps_u256, iemAImpl_vmaxps_u256_fallback;
3073	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxpd_u256, iemAImpl_vmaxpd_u256_fallback;
3074	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddps_u256, iemAImpl_vhaddps_u256_fallback;
3075	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddpd_u256, iemAImpl_vhaddpd_u256_fallback;
3076	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubps_u256, iemAImpl_vhsubps_u256_fallback;
3077	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubpd_u256, iemAImpl_vhsubpd_u256_fallback;
3078	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubps_u256, iemAImpl_vhaddsubps_u256_fallback;
3079	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubpd_u256, iemAImpl_vhaddsubpd_u256_fallback;
3080	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtpd2ps_u256, iemAImpl_vcvtpd2ps_u256_fallback;
3081	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtps2pd_u256, iemAImpl_vcvtps2pd_u256_fallback;
3082	/** @} */
3083
3084	/** @name C instruction implementations for anything slightly complicated.
3085	* @{ */
3086
3087	/**
3088	* For typedef'ing or declaring a C instruction implementation function taking
3089	* no extra arguments.
3090	*
3091	* @param a_Name The name of the type.
3092	*/
3093	# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
3094	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
3095	/**
3096	* For defining a C instruction implementation function taking no extra
3097	* arguments.
3098	*
3099	* @param a_Name The name of the function
3100	*/
3101	# define IEM_CIMPL_DEF_0(a_Name) \
3102	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
3103	/**
3104	* Prototype version of IEM_CIMPL_DEF_0.
3105	*/
3106	# define IEM_CIMPL_PROTO_0(a_Name) \
3107	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
3108	/**
3109	* For calling a C instruction implementation function taking no extra
3110	* arguments.
3111	*
3112	* This special call macro adds default arguments to the call and allow us to
3113	* change these later.
3114	*
3115	* @param a_fn The name of the function.
3116	*/
3117	# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
3118
3119	/**
3120	* For typedef'ing or declaring a C instruction implementation function taking
3121	* one extra argument.
3122	*
3123	* @param a_Name The name of the type.
3124	* @param a_Type0 The argument type.
3125	* @param a_Arg0 The argument name.
3126	*/
3127	# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
3128	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
3129	/**
3130	* For defining a C instruction implementation function taking one extra
3131	* argument.
3132	*
3133	* @param a_Name The name of the function
3134	* @param a_Type0 The argument type.
3135	* @param a_Arg0 The argument name.
3136	*/
3137	# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
3138	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
3139	/**
3140	* Prototype version of IEM_CIMPL_DEF_1.
3141	*/
3142	# define IEM_CIMPL_PROTO_1(a_Name, a_Type0, a_Arg0) \
3143	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
3144	/**
3145	* For calling a C instruction implementation function taking one extra
3146	* argument.
3147	*
3148	* This special call macro adds default arguments to the call and allow us to
3149	* change these later.
3150	*
3151	* @param a_fn The name of the function.
3152	* @param a0 The name of the 1st argument.
3153	*/
3154	# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
3155
3156	/**
3157	* For typedef'ing or declaring a C instruction implementation function taking
3158	* two extra arguments.
3159	*
3160	* @param a_Name The name of the type.
3161	* @param a_Type0 The type of the 1st argument
3162	* @param a_Arg0 The name of the 1st argument.
3163	* @param a_Type1 The type of the 2nd argument.
3164	* @param a_Arg1 The name of the 2nd argument.
3165	*/
3166	# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
3167	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
3168	/**
3169	* For defining a C instruction implementation function taking two extra
3170	* arguments.
3171	*
3172	* @param a_Name The name of the function.
3173	* @param a_Type0 The type of the 1st argument
3174	* @param a_Arg0 The name of the 1st argument.
3175	* @param a_Type1 The type of the 2nd argument.
3176	* @param a_Arg1 The name of the 2nd argument.
3177	*/
3178	# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
3179	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
3180	/**
3181	* Prototype version of IEM_CIMPL_DEF_2.
3182	*/
3183	# define IEM_CIMPL_PROTO_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
3184	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
3185	/**
3186	* For calling a C instruction implementation function taking two extra
3187	* arguments.
3188	*
3189	* This special call macro adds default arguments to the call and allow us to
3190	* change these later.
3191	*
3192	* @param a_fn The name of the function.
3193	* @param a0 The name of the 1st argument.
3194	* @param a1 The name of the 2nd argument.
3195	*/
3196	# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
3197
3198	/**
3199	* For typedef'ing or declaring a C instruction implementation function taking
3200	* three extra arguments.
3201	*
3202	* @param a_Name The name of the type.
3203	* @param a_Type0 The type of the 1st argument
3204	* @param a_Arg0 The name of the 1st argument.
3205	* @param a_Type1 The type of the 2nd argument.
3206	* @param a_Arg1 The name of the 2nd argument.
3207	* @param a_Type2 The type of the 3rd argument.
3208	* @param a_Arg2 The name of the 3rd argument.
3209	*/
3210	# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
3211	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
3212	/**
3213	* For defining a C instruction implementation function taking three extra
3214	* arguments.
3215	*
3216	* @param a_Name The name of the function.
3217	* @param a_Type0 The type of the 1st argument
3218	* @param a_Arg0 The name of the 1st argument.
3219	* @param a_Type1 The type of the 2nd argument.
3220	* @param a_Arg1 The name of the 2nd argument.
3221	* @param a_Type2 The type of the 3rd argument.
3222	* @param a_Arg2 The name of the 3rd argument.
3223	*/
3224	# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
3225	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
3226	/**
3227	* Prototype version of IEM_CIMPL_DEF_3.
3228	*/
3229	# define IEM_CIMPL_PROTO_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
3230	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
3231	/**
3232	* For calling a C instruction implementation function taking three extra
3233	* arguments.
3234	*
3235	* This special call macro adds default arguments to the call and allow us to
3236	* change these later.
3237	*
3238	* @param a_fn The name of the function.
3239	* @param a0 The name of the 1st argument.
3240	* @param a1 The name of the 2nd argument.
3241	* @param a2 The name of the 3rd argument.
3242	*/
3243	# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
3244
3245
3246	/**
3247	* For typedef'ing or declaring a C instruction implementation function taking
3248	* four extra arguments.
3249	*
3250	* @param a_Name The name of the type.
3251	* @param a_Type0 The type of the 1st argument
3252	* @param a_Arg0 The name of the 1st argument.
3253	* @param a_Type1 The type of the 2nd argument.
3254	* @param a_Arg1 The name of the 2nd argument.
3255	* @param a_Type2 The type of the 3rd argument.
3256	* @param a_Arg2 The name of the 3rd argument.
3257	* @param a_Type3 The type of the 4th argument.
3258	* @param a_Arg3 The name of the 4th argument.
3259	*/
3260	# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
3261	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
3262	/**
3263	* For defining a C instruction implementation function taking four extra
3264	* arguments.
3265	*
3266	* @param a_Name The name of the function.
3267	* @param a_Type0 The type of the 1st argument
3268	* @param a_Arg0 The name of the 1st argument.
3269	* @param a_Type1 The type of the 2nd argument.
3270	* @param a_Arg1 The name of the 2nd argument.
3271	* @param a_Type2 The type of the 3rd argument.
3272	* @param a_Arg2 The name of the 3rd argument.
3273	* @param a_Type3 The type of the 4th argument.
3274	* @param a_Arg3 The name of the 4th argument.
3275	*/
3276	# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
3277	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3278	a_Type2 a_Arg2, a_Type3 a_Arg3))
3279	/**
3280	* Prototype version of IEM_CIMPL_DEF_4.
3281	*/
3282	# define IEM_CIMPL_PROTO_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
3283	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3284	a_Type2 a_Arg2, a_Type3 a_Arg3))
3285	/**
3286	* For calling a C instruction implementation function taking four extra
3287	* arguments.
3288	*
3289	* This special call macro adds default arguments to the call and allow us to
3290	* change these later.
3291	*
3292	* @param a_fn The name of the function.
3293	* @param a0 The name of the 1st argument.
3294	* @param a1 The name of the 2nd argument.
3295	* @param a2 The name of the 3rd argument.
3296	* @param a3 The name of the 4th argument.
3297	*/
3298	# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
3299
3300
3301	/**
3302	* For typedef'ing or declaring a C instruction implementation function taking
3303	* five extra arguments.
3304	*
3305	* @param a_Name The name of the type.
3306	* @param a_Type0 The type of the 1st argument
3307	* @param a_Arg0 The name of the 1st argument.
3308	* @param a_Type1 The type of the 2nd argument.
3309	* @param a_Arg1 The name of the 2nd argument.
3310	* @param a_Type2 The type of the 3rd argument.
3311	* @param a_Arg2 The name of the 3rd argument.
3312	* @param a_Type3 The type of the 4th argument.
3313	* @param a_Arg3 The name of the 4th argument.
3314	* @param a_Type4 The type of the 5th argument.
3315	* @param a_Arg4 The name of the 5th argument.
3316	*/
3317	# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
3318	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, \
3319	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
3320	a_Type3 a_Arg3, a_Type4 a_Arg4))
3321	/**
3322	* For defining a C instruction implementation function taking five extra
3323	* arguments.
3324	*
3325	* @param a_Name The name of the function.
3326	* @param a_Type0 The type of the 1st argument
3327	* @param a_Arg0 The name of the 1st argument.
3328	* @param a_Type1 The type of the 2nd argument.
3329	* @param a_Arg1 The name of the 2nd argument.
3330	* @param a_Type2 The type of the 3rd argument.
3331	* @param a_Arg2 The name of the 3rd argument.
3332	* @param a_Type3 The type of the 4th argument.
3333	* @param a_Arg3 The name of the 4th argument.
3334	* @param a_Type4 The type of the 5th argument.
3335	* @param a_Arg4 The name of the 5th argument.
3336	*/
3337	# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
3338	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3339	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
3340	/**
3341	* Prototype version of IEM_CIMPL_DEF_5.
3342	*/
3343	# define IEM_CIMPL_PROTO_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
3344	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3345	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
3346	/**
3347	* For calling a C instruction implementation function taking five extra
3348	* arguments.
3349	*
3350	* This special call macro adds default arguments to the call and allow us to
3351	* change these later.
3352	*
3353	* @param a_fn The name of the function.
3354	* @param a0 The name of the 1st argument.
3355	* @param a1 The name of the 2nd argument.
3356	* @param a2 The name of the 3rd argument.
3357	* @param a3 The name of the 4th argument.
3358	* @param a4 The name of the 5th argument.
3359	*/
3360	# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
3361
3362	/** @} */
3363
3364
3365	/** @name Opcode Decoder Function Types.
3366	* @{ */
3367
3368	/** @typedef PFNIEMOP
3369	* Pointer to an opcode decoder function.
3370	*/
3371
3372	/** @def FNIEMOP_DEF
3373	* Define an opcode decoder function.
3374	*
3375	* We're using macors for this so that adding and removing parameters as well as
3376	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL
3377	*
3378	* @param a_Name The function name.
3379	*/
3380
3381	/** @typedef PFNIEMOPRM
3382	* Pointer to an opcode decoder function with RM byte.
3383	*/
3384
3385	/** @def FNIEMOPRM_DEF
3386	* Define an opcode decoder function with RM byte.
3387	*
3388	* We're using macors for this so that adding and removing parameters as well as
3389	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL_1
3390	*
3391	* @param a_Name The function name.
3392	*/
3393
3394	#if defined(__GNUC__) && defined(RT_ARCH_X86)
3395	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOP)(PVMCPUCC pVCpu);
3396	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3397	# define FNIEMOP_DEF(a_Name) \
3398	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu)
3399	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3400	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
3401	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3402	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
3403
3404	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
3405	typedef VBOXSTRICTRC (__fastcall * PFNIEMOP)(PVMCPUCC pVCpu);
3406	typedef VBOXSTRICTRC (__fastcall * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3407	# define FNIEMOP_DEF(a_Name) \
3408	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
3409	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3410	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
3411	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3412	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
3413
3414	#elif defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
3415	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
3416	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3417	# define FNIEMOP_DEF(a_Name) \
3418	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu)
3419	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3420	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
3421	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3422	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
3423
3424	#else
3425	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
3426	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3427	# define FNIEMOP_DEF(a_Name) \
3428	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
3429	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3430	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
3431	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3432	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
3433
3434	#endif
3435	#define FNIEMOPRM_DEF(a_Name) FNIEMOP_DEF_1(a_Name, uint8_t, bRm)
3436
3437	/**
3438	* Call an opcode decoder function.
3439	*
3440	* We're using macors for this so that adding and removing parameters can be
3441	* done as we please. See FNIEMOP_DEF.
3442	*/
3443	#define FNIEMOP_CALL(a_pfn) (a_pfn)(pVCpu)
3444
3445	/**
3446	* Call a common opcode decoder function taking one extra argument.
3447	*
3448	* We're using macors for this so that adding and removing parameters can be
3449	* done as we please. See FNIEMOP_DEF_1.
3450	*/
3451	#define FNIEMOP_CALL_1(a_pfn, a0) (a_pfn)(pVCpu, a0)
3452
3453	/**
3454	* Call a common opcode decoder function taking one extra argument.
3455	*
3456	* We're using macors for this so that adding and removing parameters can be
3457	* done as we please. See FNIEMOP_DEF_1.
3458	*/
3459	#define FNIEMOP_CALL_2(a_pfn, a0, a1) (a_pfn)(pVCpu, a0, a1)
3460	/** @} */
3461
3462
3463	/** @name Misc Helpers
3464	* @{ */
3465
3466	/** Used to shut up GCC warnings about variables that 'may be used uninitialized'
3467	* due to GCC lacking knowledge about the value range of a switch. */
3468	#if RT_CPLUSPLUS_PREREQ(202000)
3469	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: [[unlikely]] AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
3470	#else
3471	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
3472	#endif
3473
3474	/** Variant of IEM_NOT_REACHED_DEFAULT_CASE_RET that returns a custom value. */
3475	#if RT_CPLUSPLUS_PREREQ(202000)
3476	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: [[unlikely]] AssertFailedReturn(a_RetValue)
3477	#else
3478	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: AssertFailedReturn(a_RetValue)
3479	#endif
3480
3481	/**
3482	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
3483	* occation.
3484	*/
3485	#ifdef LOG_ENABLED
3486	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
3487	do { \
3488	/Log/ LogAlways(("%s: returning IEM_RETURN_ASPECT_NOT_IMPLEMENTED (line %d)\n", __FUNCTION__, __LINE__)); \
3489	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
3490	} while (0)
3491	#else
3492	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
3493	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
3494	#endif
3495
3496	/**
3497	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
3498	* occation using the supplied logger statement.
3499	*
3500	* @param a_LoggerArgs What to log on failure.
3501	*/
3502	#ifdef LOG_ENABLED
3503	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
3504	do { \
3505	LogAlways((LOG_FN_FMT ": ", __PRETTY_FUNCTION__)); LogAlways(a_LoggerArgs); \
3506	/LogFunc(a_LoggerArgs);/ \
3507	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
3508	} while (0)
3509	#else
3510	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
3511	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
3512	#endif
3513
3514	/**
3515	* Check if we're currently executing in real or virtual 8086 mode.
3516	*
3517	* @returns @c true if it is, @c false if not.
3518	* @param a_pVCpu The IEM state of the current CPU.
3519	*/
3520	#define IEM_IS_REAL_OR_V86_MODE(a_pVCpu) (CPUMIsGuestInRealOrV86ModeEx(IEM_GET_CTX(a_pVCpu)))
3521
3522	/**
3523	* Check if we're currently executing in virtual 8086 mode.
3524	*
3525	* @returns @c true if it is, @c false if not.
3526	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3527	*/
3528	#define IEM_IS_V86_MODE(a_pVCpu) (CPUMIsGuestInV86ModeEx(IEM_GET_CTX(a_pVCpu)))
3529
3530	/**
3531	* Check if we're currently executing in long mode.
3532	*
3533	* @returns @c true if it is, @c false if not.
3534	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3535	*/
3536	#define IEM_IS_LONG_MODE(a_pVCpu) (CPUMIsGuestInLongModeEx(IEM_GET_CTX(a_pVCpu)))
3537
3538	/**
3539	* Check if we're currently executing in a 64-bit code segment.
3540	*
3541	* @returns @c true if it is, @c false if not.
3542	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3543	*/
3544	#define IEM_IS_64BIT_CODE(a_pVCpu) (CPUMIsGuestIn64BitCodeEx(IEM_GET_CTX(a_pVCpu)))
3545
3546	/**
3547	* Check if we're currently executing in real mode.
3548	*
3549	* @returns @c true if it is, @c false if not.
3550	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3551	*/
3552	#define IEM_IS_REAL_MODE(a_pVCpu) (CPUMIsGuestInRealModeEx(IEM_GET_CTX(a_pVCpu)))
3553
3554	/**
3555	* Returns a (const) pointer to the CPUMFEATURES for the guest CPU.
3556	* @returns PCCPUMFEATURES
3557	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3558	*/
3559	#define IEM_GET_GUEST_CPU_FEATURES(a_pVCpu) (&((a_pVCpu)->CTX_SUFF(pVM)->cpum.ro.GuestFeatures))
3560
3561	/**
3562	* Returns a (const) pointer to the CPUMFEATURES for the host CPU.
3563	* @returns PCCPUMFEATURES
3564	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3565	*/
3566	#define IEM_GET_HOST_CPU_FEATURES(a_pVCpu) (&g_CpumHostFeatures.s)
3567
3568	/**
3569	* Evaluates to true if we're presenting an Intel CPU to the guest.
3570	*/
3571	#define IEM_IS_GUEST_CPU_INTEL(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL )
3572
3573	/**
3574	* Evaluates to true if we're presenting an AMD CPU to the guest.
3575	*/
3576	#define IEM_IS_GUEST_CPU_AMD(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_AMD \|\| (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_HYGON )
3577
3578	/**
3579	* Check if the address is canonical.
3580	*/
3581	#define IEM_IS_CANONICAL(a_u64Addr) X86_IS_CANONICAL(a_u64Addr)
3582
3583	/** Checks if the ModR/M byte is in register mode or not. */
3584	#define IEM_IS_MODRM_REG_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT) )
3585	/** Checks if the ModR/M byte is in memory mode or not. */
3586	#define IEM_IS_MODRM_MEM_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT) )
3587
3588	/**
3589	* Gets the register (reg) part of a ModR/M encoding, with REX.R added in.
3590	*
3591	* For use during decoding.
3592	*/
3593	#define IEM_GET_MODRM_REG(a_pVCpu, a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| (a_pVCpu)->iem.s.uRexReg )
3594	/**
3595	* Gets the r/m part of a ModR/M encoding as a register index, with REX.B added in.
3596	*
3597	* For use during decoding.
3598	*/
3599	#define IEM_GET_MODRM_RM(a_pVCpu, a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) \| (a_pVCpu)->iem.s.uRexB )
3600
3601	/**
3602	* Gets the register (reg) part of a ModR/M encoding, without REX.R.
3603	*
3604	* For use during decoding.
3605	*/
3606	#define IEM_GET_MODRM_REG_8(a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) )
3607	/**
3608	* Gets the r/m part of a ModR/M encoding as a register index, without REX.B.
3609	*
3610	* For use during decoding.
3611	*/
3612	#define IEM_GET_MODRM_RM_8(a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) )
3613
3614	/**
3615	* Combines the prefix REX and ModR/M byte for passing to
3616	* iemOpHlpCalcRmEffAddrThreadedAddr64().
3617	*
3618	* @returns The ModRM byte but with bit 3 set to REX.B and bit 4 to REX.X.
3619	* The two bits are part of the REG sub-field, which isn't needed in
3620	* iemOpHlpCalcRmEffAddrThreadedAddr64().
3621	*
3622	* For use during decoding/recompiling.
3623	*/
3624	#define IEM_GET_MODRM_EX(a_pVCpu, a_bRm) \
3625	( ((a_bRm) & ~X86_MODRM_REG_MASK) \
3626	\| (uint8_t)( (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X)) >> (26 - 3) ) )
3627	AssertCompile(IEM_OP_PRF_REX_B == RT_BIT_32(26));
3628	AssertCompile(IEM_OP_PRF_REX_X == RT_BIT_32(27));
3629
3630	/**
3631	* Gets the effective VEX.VVVV value.
3632	*
3633	* The 4th bit is ignored if not 64-bit code.
3634	* @returns effective V-register value.
3635	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3636	*/
3637	#define IEM_GET_EFFECTIVE_VVVV(a_pVCpu) \
3638	((a_pVCpu)->iem.s.enmCpuMode == IEMMODE_64BIT ? (a_pVCpu)->iem.s.uVex3rdReg : (a_pVCpu)->iem.s.uVex3rdReg & 7)
3639
3640
3641	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
3642
3643	/**
3644	* Check if the guest has entered VMX root operation.
3645	*/
3646	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxRootMode(IEM_GET_CTX(a_pVCpu)))
3647
3648	/**
3649	* Check if the guest has entered VMX non-root operation.
3650	*/
3651	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxNonRootMode(IEM_GET_CTX(a_pVCpu)))
3652
3653	/**
3654	* Check if the nested-guest has the given Pin-based VM-execution control set.
3655	*/
3656	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_PinCtl) \
3657	(CPUMIsGuestVmxPinCtlsSet(IEM_GET_CTX(a_pVCpu), (a_PinCtl)))
3658
3659	/**
3660	* Check if the nested-guest has the given Processor-based VM-execution control set.
3661	*/
3662	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_ProcCtl) \
3663	(CPUMIsGuestVmxProcCtlsSet(IEM_GET_CTX(a_pVCpu), (a_ProcCtl)))
3664
3665	/**
3666	* Check if the nested-guest has the given Secondary Processor-based VM-execution
3667	* control set.
3668	*/
3669	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_ProcCtl2) \
3670	(CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(a_pVCpu), (a_ProcCtl2)))
3671
3672	/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
3673	# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
3674
3675	/** Whether a shadow VMCS is present for the given VCPU. */
3676	# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
3677
3678	/** Gets the VMXON region pointer. */
3679	# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
3680
3681	/** Gets the guest-physical address of the current VMCS for the given VCPU. */
3682	# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
3683
3684	/** Whether a current VMCS is present for the given VCPU. */
3685	# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
3686
3687	/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
3688	# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
3689	do \
3690	{ \
3691	Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
3692	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
3693	} while (0)
3694
3695	/** Clears any current VMCS for the given VCPU. */
3696	# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
3697	do \
3698	{ \
3699	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
3700	} while (0)
3701
3702	/**
3703	* Invokes the VMX VM-exit handler for an instruction intercept.
3704	*/
3705	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) \
3706	do { return iemVmxVmexitInstr((a_pVCpu), (a_uExitReason), (a_cbInstr)); } while (0)
3707
3708	/**
3709	* Invokes the VMX VM-exit handler for an instruction intercept where the
3710	* instruction provides additional VM-exit information.
3711	*/
3712	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) \
3713	do { return iemVmxVmexitInstrNeedsInfo((a_pVCpu), (a_uExitReason), (a_uInstrId), (a_cbInstr)); } while (0)
3714
3715	/**
3716	* Invokes the VMX VM-exit handler for a task switch.
3717	*/
3718	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) \
3719	do { return iemVmxVmexitTaskSwitch((a_pVCpu), (a_enmTaskSwitch), (a_SelNewTss), (a_cbInstr)); } while (0)
3720
3721	/**
3722	* Invokes the VMX VM-exit handler for MWAIT.
3723	*/
3724	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) \
3725	do { return iemVmxVmexitInstrMwait((a_pVCpu), (a_fMonitorArmed), (a_cbInstr)); } while (0)
3726
3727	/**
3728	* Invokes the VMX VM-exit handler for EPT faults.
3729	*/
3730	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) \
3731	do { return iemVmxVmexitEpt(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr); } while (0)
3732
3733	/**
3734	* Invokes the VMX VM-exit handler.
3735	*/
3736	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) \
3737	do { return iemVmxVmexit((a_pVCpu), (a_uExitReason), (a_uExitQual)); } while (0)
3738
3739	#else
3740	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (false)
3741	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (false)
3742	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_cbInstr) (false)
3743	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_cbInstr) (false)
3744	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_cbInstr) (false)
3745	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3746	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3747	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3748	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3749	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3750	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) do { return VERR_VMX_IPE_1; } while (0)
3751
3752	#endif
3753
3754	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
3755	/**
3756	* Check if an SVM control/instruction intercept is set.
3757	*/
3758	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) \
3759	(CPUMIsGuestSvmCtrlInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_Intercept)))
3760
3761	/**
3762	* Check if an SVM read CRx intercept is set.
3763	*/
3764	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
3765	(CPUMIsGuestSvmReadCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
3766
3767	/**
3768	* Check if an SVM write CRx intercept is set.
3769	*/
3770	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
3771	(CPUMIsGuestSvmWriteCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
3772
3773	/**
3774	* Check if an SVM read DRx intercept is set.
3775	*/
3776	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
3777	(CPUMIsGuestSvmReadDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
3778
3779	/**
3780	* Check if an SVM write DRx intercept is set.
3781	*/
3782	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
3783	(CPUMIsGuestSvmWriteDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
3784
3785	/**
3786	* Check if an SVM exception intercept is set.
3787	*/
3788	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) \
3789	(CPUMIsGuestSvmXcptInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uVector)))
3790
3791	/**
3792	* Invokes the SVM \#VMEXIT handler for the nested-guest.
3793	*/
3794	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
3795	do { return iemSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2)); } while (0)
3796
3797	/**
3798	* Invokes the 'MOV CRx' SVM \#VMEXIT handler after constructing the
3799	* corresponding decode assist information.
3800	*/
3801	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) \
3802	do \
3803	{ \
3804	uint64_t uExitInfo1; \
3805	if ( IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmDecodeAssists \
3806	&& (a_enmAccessCrX) == IEMACCESSCRX_MOV_CRX) \
3807	uExitInfo1 = SVM_EXIT1_MOV_CRX_MASK \| ((a_iGReg) & 7); \
3808	else \
3809	uExitInfo1 = 0; \
3810	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, uExitInfo1, 0); \
3811	} while (0)
3812
3813	/** Check and handles SVM nested-guest instruction intercept and updates
3814	* NRIP if needed.
3815	*/
3816	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
3817	do \
3818	{ \
3819	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept)) \
3820	{ \
3821	IEM_SVM_UPDATE_NRIP(a_pVCpu); \
3822	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2); \
3823	} \
3824	} while (0)
3825
3826	/** Checks and handles SVM nested-guest CR0 read intercept. */
3827	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2) \
3828	do \
3829	{ \
3830	if (!IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, 0)) \
3831	{ /* probably likely */ } \
3832	else \
3833	{ \
3834	IEM_SVM_UPDATE_NRIP(a_pVCpu); \
3835	IEM_SVM_VMEXIT_RET(a_pVCpu, SVM_EXIT_READ_CR0, a_uExitInfo1, a_uExitInfo2); \
3836	} \
3837	} while (0)
3838
3839	/**
3840	* Updates the NextRIP (NRI) field in the nested-guest VMCB.
3841	*/
3842	# define IEM_SVM_UPDATE_NRIP(a_pVCpu) \
3843	do { \
3844	if (IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmNextRipSave) \
3845	CPUMGuestSvmUpdateNRip(a_pVCpu, IEM_GET_CTX(a_pVCpu), IEM_GET_INSTR_LEN(a_pVCpu)); \
3846	} while (0)
3847
3848	#else
3849	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) (false)
3850	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
3851	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
3852	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
3853	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
3854	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) (false)
3855	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { return VERR_SVM_IPE_1; } while (0)
3856	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) do { return VERR_SVM_IPE_1; } while (0)
3857	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { } while (0)
3858	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2) do { } while (0)
3859	# define IEM_SVM_UPDATE_NRIP(a_pVCpu) do { } while (0)
3860
3861	#endif
3862
3863	/** @} */
3864
3865	void iemInitPendingBreakpointsSlow(PVMCPUCC pVCpu);
3866
3867
3868	/**
3869	* Selector descriptor table entry as fetched by iemMemFetchSelDesc.
3870	*/
3871	typedef union IEMSELDESC
3872	{
3873	/** The legacy view. */
3874	X86DESC Legacy;
3875	/** The long mode view. */
3876	X86DESC64 Long;
3877	} IEMSELDESC;
3878	/** Pointer to a selector descriptor table entry. */
3879	typedef IEMSELDESC *PIEMSELDESC;
3880
3881	/** @name Raising Exceptions.
3882	* @{ */
3883	VBOXSTRICTRC iemTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, uint32_t uNextEip, uint32_t fFlags,
3884	uint16_t uErr, uint64_t uCr2, RTSEL SelTSS, PIEMSELDESC pNewDescTSS) RT_NOEXCEPT;
3885
3886	VBOXSTRICTRC iemRaiseXcptOrInt(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags,
3887	uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
3888	#ifdef IEM_WITH_SETJMP
3889	DECL_NO_RETURN(void) iemRaiseXcptOrIntJmp(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector,
3890	uint32_t fFlags, uint16_t uErr, uint64_t uCr2) IEM_NOEXCEPT_MAY_LONGJMP;
3891	#endif
3892	VBOXSTRICTRC iemRaiseDivideError(PVMCPUCC pVCpu) RT_NOEXCEPT;
3893	VBOXSTRICTRC iemRaiseDebugException(PVMCPUCC pVCpu) RT_NOEXCEPT;
3894	VBOXSTRICTRC iemRaiseBoundRangeExceeded(PVMCPUCC pVCpu) RT_NOEXCEPT;
3895	VBOXSTRICTRC iemRaiseUndefinedOpcode(PVMCPUCC pVCpu) RT_NOEXCEPT;
3896	VBOXSTRICTRC iemRaiseDeviceNotAvailable(PVMCPUCC pVCpu) RT_NOEXCEPT;
3897	VBOXSTRICTRC iemRaiseTaskSwitchFaultWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
3898	VBOXSTRICTRC iemRaiseTaskSwitchFaultCurrentTSS(PVMCPUCC pVCpu) RT_NOEXCEPT;
3899	VBOXSTRICTRC iemRaiseTaskSwitchFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
3900	VBOXSTRICTRC iemRaiseTaskSwitchFaultBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
3901	/VBOXSTRICTRC iemRaiseSelectorNotPresent(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;/
3902	VBOXSTRICTRC iemRaiseSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
3903	VBOXSTRICTRC iemRaiseSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
3904	VBOXSTRICTRC iemRaiseStackSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
3905	VBOXSTRICTRC iemRaiseStackSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
3906	VBOXSTRICTRC iemRaiseGeneralProtectionFault(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
3907	VBOXSTRICTRC iemRaiseGeneralProtectionFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
3908	#ifdef IEM_WITH_SETJMP
3909	DECL_NO_RETURN(void) iemRaiseGeneralProtectionFault0Jmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
3910	#endif
3911	VBOXSTRICTRC iemRaiseGeneralProtectionFaultBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
3912	VBOXSTRICTRC iemRaiseNotCanonical(PVMCPUCC pVCpu) RT_NOEXCEPT;
3913	VBOXSTRICTRC iemRaiseSelectorBounds(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
3914	#ifdef IEM_WITH_SETJMP
3915	DECL_NO_RETURN(void) iemRaiseSelectorBoundsJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
3916	#endif
3917	VBOXSTRICTRC iemRaiseSelectorBoundsBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
3918	#ifdef IEM_WITH_SETJMP
3919	DECL_NO_RETURN(void) iemRaiseSelectorBoundsBySelectorJmp(PVMCPUCC pVCpu, RTSEL Sel) IEM_NOEXCEPT_MAY_LONGJMP;
3920	#endif
3921	VBOXSTRICTRC iemRaiseSelectorInvalidAccess(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
3922	#ifdef IEM_WITH_SETJMP
3923	DECL_NO_RETURN(void) iemRaiseSelectorInvalidAccessJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
3924	#endif
3925	VBOXSTRICTRC iemRaisePageFault(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) RT_NOEXCEPT;
3926	#ifdef IEM_WITH_SETJMP
3927	DECL_NO_RETURN(void) iemRaisePageFaultJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) IEM_NOEXCEPT_MAY_LONGJMP;
3928	#endif
3929	VBOXSTRICTRC iemRaiseMathFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
3930	VBOXSTRICTRC iemRaiseAlignmentCheckException(PVMCPUCC pVCpu) RT_NOEXCEPT;
3931	#ifdef IEM_WITH_SETJMP
3932	DECL_NO_RETURN(void) iemRaiseAlignmentCheckExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
3933	#endif
3934	VBOXSTRICTRC iemRaiseSimdFpException(PVMCPUCC pVCpu) RT_NOEXCEPT;
3935
3936	IEM_CIMPL_DEF_0(iemCImplRaiseDivideError);
3937	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidLockPrefix);
3938	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidOpcode);
3939
3940	/**
3941	* Macro for calling iemCImplRaiseDivideError().
3942	*
3943	* This enables us to add/remove arguments and force different levels of
3944	* inlining as we wish.
3945	*
3946	* @return Strict VBox status code.
3947	*/
3948	#define IEMOP_RAISE_DIVIDE_ERROR() IEM_MC_DEFER_TO_CIMPL_0(iemCImplRaiseDivideError)
3949
3950	/**
3951	* Macro for calling iemCImplRaiseInvalidLockPrefix().
3952	*
3953	* This enables us to add/remove arguments and force different levels of
3954	* inlining as we wish.
3955	*
3956	* @return Strict VBox status code.
3957	*/
3958	#define IEMOP_RAISE_INVALID_LOCK_PREFIX() IEM_MC_DEFER_TO_CIMPL_0(iemCImplRaiseInvalidLockPrefix)
3959
3960	/**
3961	* Macro for calling iemCImplRaiseInvalidOpcode().
3962	*
3963	* This enables us to add/remove arguments and force different levels of
3964	* inlining as we wish.
3965	*
3966	* @return Strict VBox status code.
3967	*/
3968	#define IEMOP_RAISE_INVALID_OPCODE() IEM_MC_DEFER_TO_CIMPL_0(iemCImplRaiseInvalidOpcode)
3969	/** @} */
3970
3971	/** @name Register Access.
3972	* @{ */
3973	VBOXSTRICTRC iemRegRipRelativeJumpS8AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int8_t offNextInstr,
3974	IEMMODE enmEffOpSize) RT_NOEXCEPT;
3975	VBOXSTRICTRC iemRegRipRelativeJumpS16AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int16_t offNextInstr) RT_NOEXCEPT;
3976	VBOXSTRICTRC iemRegRipRelativeJumpS32AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int32_t offNextInstr,
3977	IEMMODE enmEffOpSize) RT_NOEXCEPT;
3978	VBOXSTRICTRC iemRegRipJumpU16AndFinishClearningRF(PVMCPUCC pVCpu, uint16_t uNewRip) RT_NOEXCEPT;
3979	VBOXSTRICTRC iemRegRipJumpU32AndFinishClearningRF(PVMCPUCC pVCpu, uint32_t uNewRip) RT_NOEXCEPT;
3980	VBOXSTRICTRC iemRegRipJumpU64AndFinishClearningRF(PVMCPUCC pVCpu, uint64_t uNewRip) RT_NOEXCEPT;
3981	/** @} */
3982
3983	/** @name FPU access and helpers.
3984	* @{ */
3985	void iemFpuPushResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult) RT_NOEXCEPT;
3986	void iemFpuPushResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3987	void iemFpuPushResultTwo(PVMCPUCC pVCpu, PIEMFPURESULTTWO pResult) RT_NOEXCEPT;
3988	void iemFpuStoreResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg) RT_NOEXCEPT;
3989	void iemFpuStoreResultThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg) RT_NOEXCEPT;
3990	void iemFpuStoreResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
3991	uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3992	void iemFpuStoreResultWithMemOpThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
3993	uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3994	void iemFpuUpdateOpcodeAndIp(PVMCPUCC pVCpu) RT_NOEXCEPT;
3995	void iemFpuUpdateFSW(PVMCPUCC pVCpu, uint16_t u16FSW) RT_NOEXCEPT;
3996	void iemFpuUpdateFSWThenPop(PVMCPUCC pVCpu, uint16_t u16FSW) RT_NOEXCEPT;
3997	void iemFpuUpdateFSWWithMemOp(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3998	void iemFpuUpdateFSWThenPopPop(PVMCPUCC pVCpu, uint16_t u16FSW) RT_NOEXCEPT;
3999	void iemFpuUpdateFSWWithMemOpThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
4000	void iemFpuStackUnderflow(PVMCPUCC pVCpu, uint8_t iStReg) RT_NOEXCEPT;
4001	void iemFpuStackUnderflowWithMemOp(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
4002	void iemFpuStackUnderflowThenPop(PVMCPUCC pVCpu, uint8_t iStReg) RT_NOEXCEPT;
4003	void iemFpuStackUnderflowWithMemOpThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
4004	void iemFpuStackUnderflowThenPopPop(PVMCPUCC pVCpu) RT_NOEXCEPT;
4005	void iemFpuStackPushUnderflow(PVMCPUCC pVCpu) RT_NOEXCEPT;
4006	void iemFpuStackPushUnderflowTwo(PVMCPUCC pVCpu) RT_NOEXCEPT;
4007	void iemFpuStackPushOverflow(PVMCPUCC pVCpu) RT_NOEXCEPT;
4008	void iemFpuStackPushOverflowWithMemOp(PVMCPUCC pVCpu, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
4009	/** @} */
4010
4011	/** @name SSE+AVX SIMD access and helpers.
4012	* @{ */
4013	void iemSseStoreResult(PVMCPUCC pVCpu, PCIEMSSERESULT pResult, uint8_t iXmmReg) RT_NOEXCEPT;
4014	void iemSseUpdateMxcsr(PVMCPUCC pVCpu, uint32_t fMxcsr) RT_NOEXCEPT;
4015	/** @} */
4016
4017	/** @name Memory access.
4018	* @{ */
4019
4020	/** Report a \#GP instead of \#AC and do not restrict to ring-3 */
4021	#define IEM_MEMMAP_F_ALIGN_GP RT_BIT_32(16)
4022	/** SSE access that should report a \#GP instead of \#AC, unless MXCSR.MM=1
4023	* when it works like normal \#AC. Always used with IEM_MEMMAP_F_ALIGN_GP. */
4024	#define IEM_MEMMAP_F_ALIGN_SSE RT_BIT_32(17)
4025	/** If \#AC is applicable, raise it. Always used with IEM_MEMMAP_F_ALIGN_GP.
4026	* Users include FXSAVE & FXRSTOR. */
4027	#define IEM_MEMMAP_F_ALIGN_GP_OR_AC RT_BIT_32(18)
4028
4029	VBOXSTRICTRC iemMemMap(PVMCPUCC pVCpu, void **ppvMem, size_t cbMem, uint8_t iSegReg, RTGCPTR GCPtrMem,
4030	uint32_t fAccess, uint32_t uAlignCtl) RT_NOEXCEPT;
4031	VBOXSTRICTRC iemMemCommitAndUnmap(PVMCPUCC pVCpu, void *pvMem, uint32_t fAccess) RT_NOEXCEPT;
4032	#ifndef IN_RING3
4033	VBOXSTRICTRC iemMemCommitAndUnmapPostponeTroubleToR3(PVMCPUCC pVCpu, void *pvMem, uint32_t fAccess) RT_NOEXCEPT;
4034	#endif
4035	void iemMemRollback(PVMCPUCC pVCpu) RT_NOEXCEPT;
4036	VBOXSTRICTRC iemMemApplySegment(PVMCPUCC pVCpu, uint32_t fAccess, uint8_t iSegReg, size_t cbMem, PRTGCPTR pGCPtrMem) RT_NOEXCEPT;
4037	VBOXSTRICTRC iemMemMarkSelDescAccessed(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
4038	VBOXSTRICTRC iemMemPageTranslateAndCheckAccess(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t cbAccess, uint32_t fAccess, PRTGCPHYS pGCPhysMem) RT_NOEXCEPT;
4039
4040	#ifdef IEM_WITH_CODE_TLB
4041	void iemOpcodeFetchBytesJmp(PVMCPUCC pVCpu, size_t cbDst, void *pvDst) IEM_NOEXCEPT_MAY_LONGJMP;
4042	#else
4043	VBOXSTRICTRC iemOpcodeFetchMoreBytes(PVMCPUCC pVCpu, size_t cbMin) RT_NOEXCEPT;
4044	#endif
4045	#ifdef IEM_WITH_SETJMP
4046	uint8_t iemOpcodeGetNextU8SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4047	uint16_t iemOpcodeGetNextU16SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4048	uint32_t iemOpcodeGetNextU32SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4049	uint64_t iemOpcodeGetNextU64SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4050	#else
4051	VBOXSTRICTRC iemOpcodeGetNextU8Slow(PVMCPUCC pVCpu, uint8_t *pb) RT_NOEXCEPT;
4052	VBOXSTRICTRC iemOpcodeGetNextS8SxU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
4053	VBOXSTRICTRC iemOpcodeGetNextS8SxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
4054	VBOXSTRICTRC iemOpcodeGetNextS8SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
4055	VBOXSTRICTRC iemOpcodeGetNextU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
4056	VBOXSTRICTRC iemOpcodeGetNextU16ZxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
4057	VBOXSTRICTRC iemOpcodeGetNextU16ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
4058	VBOXSTRICTRC iemOpcodeGetNextU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
4059	VBOXSTRICTRC iemOpcodeGetNextU32ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
4060	VBOXSTRICTRC iemOpcodeGetNextS32SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
4061	VBOXSTRICTRC iemOpcodeGetNextU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
4062	#endif
4063
4064	VBOXSTRICTRC iemMemFetchDataU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4065	VBOXSTRICTRC iemMemFetchDataU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4066	VBOXSTRICTRC iemMemFetchDataU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4067	VBOXSTRICTRC iemMemFetchDataU32_ZX_U64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4068	VBOXSTRICTRC iemMemFetchDataU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4069	VBOXSTRICTRC iemMemFetchDataU64AlignedU128(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4070	VBOXSTRICTRC iemMemFetchDataR80(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4071	VBOXSTRICTRC iemMemFetchDataD80(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4072	VBOXSTRICTRC iemMemFetchDataU128(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4073	VBOXSTRICTRC iemMemFetchDataU128AlignedSse(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4074	VBOXSTRICTRC iemMemFetchDataU256(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4075	VBOXSTRICTRC iemMemFetchDataU256AlignedSse(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4076	VBOXSTRICTRC iemMemFetchDataXdtr(PVMCPUCC pVCpu, uint16_t *pcbLimit, PRTGCPTR pGCPtrBase, uint8_t iSegReg,
4077	RTGCPTR GCPtrMem, IEMMODE enmOpSize) RT_NOEXCEPT;
4078	#ifdef IEM_WITH_SETJMP
4079	uint8_t iemMemFetchDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4080	uint16_t iemMemFetchDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4081	uint32_t iemMemFetchDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4082	uint64_t iemMemFetchDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4083	uint64_t iemMemFetchDataU64AlignedU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4084	void iemMemFetchDataR80Jmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4085	void iemMemFetchDataD80Jmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4086	void iemMemFetchDataU128Jmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4087	void iemMemFetchDataU128AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4088	void iemMemFetchDataU256Jmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4089	void iemMemFetchDataU256AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4090	#endif
4091
4092	VBOXSTRICTRC iemMemFetchSysU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4093	VBOXSTRICTRC iemMemFetchSysU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4094	VBOXSTRICTRC iemMemFetchSysU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4095	VBOXSTRICTRC iemMemFetchSysU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4096	VBOXSTRICTRC iemMemFetchSelDesc(PVMCPUCC pVCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt) RT_NOEXCEPT;
4097
4098	VBOXSTRICTRC iemMemStoreDataU8(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) RT_NOEXCEPT;
4099	VBOXSTRICTRC iemMemStoreDataU16(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) RT_NOEXCEPT;
4100	VBOXSTRICTRC iemMemStoreDataU32(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) RT_NOEXCEPT;
4101	VBOXSTRICTRC iemMemStoreDataU64(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) RT_NOEXCEPT;
4102	VBOXSTRICTRC iemMemStoreDataU128(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
4103	VBOXSTRICTRC iemMemStoreDataU128AlignedSse(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
4104	VBOXSTRICTRC iemMemStoreDataU256(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
4105	VBOXSTRICTRC iemMemStoreDataU256AlignedAvx(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
4106	VBOXSTRICTRC iemMemStoreDataXdtr(PVMCPUCC pVCpu, uint16_t cbLimit, RTGCPTR GCPtrBase, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4107	#ifdef IEM_WITH_SETJMP
4108	void iemMemStoreDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
4109	void iemMemStoreDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
4110	void iemMemStoreDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
4111	void iemMemStoreDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
4112	void iemMemStoreDataU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
4113	void iemMemStoreDataU128AlignedSseJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
4114	void iemMemStoreDataU256Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
4115	void iemMemStoreDataU256AlignedAvxJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
4116	#endif
4117
4118	VBOXSTRICTRC iemMemStackPushBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
4119	void *ppvMem, uint64_t puNewRsp) RT_NOEXCEPT;
4120	VBOXSTRICTRC iemMemStackPushCommitSpecial(PVMCPUCC pVCpu, void *pvMem, uint64_t uNewRsp) RT_NOEXCEPT;
4121	VBOXSTRICTRC iemMemStackPushU16(PVMCPUCC pVCpu, uint16_t u16Value) RT_NOEXCEPT;
4122	VBOXSTRICTRC iemMemStackPushU32(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
4123	VBOXSTRICTRC iemMemStackPushU64(PVMCPUCC pVCpu, uint64_t u64Value) RT_NOEXCEPT;
4124	VBOXSTRICTRC iemMemStackPushU16Ex(PVMCPUCC pVCpu, uint16_t u16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4125	VBOXSTRICTRC iemMemStackPushU32Ex(PVMCPUCC pVCpu, uint32_t u32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4126	VBOXSTRICTRC iemMemStackPushU64Ex(PVMCPUCC pVCpu, uint64_t u64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4127	VBOXSTRICTRC iemMemStackPushU32SReg(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
4128	VBOXSTRICTRC iemMemStackPopBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
4129	void const *ppvMem, uint64_t puNewRsp) RT_NOEXCEPT;
4130	VBOXSTRICTRC iemMemStackPopContinueSpecial(PVMCPUCC pVCpu, size_t off, size_t cbMem,
4131	void const **ppvMem, uint64_t uCurNewRsp) RT_NOEXCEPT;
4132	VBOXSTRICTRC iemMemStackPopDoneSpecial(PVMCPUCC pVCpu, void const *pvMem) RT_NOEXCEPT;
4133	VBOXSTRICTRC iemMemStackPopU16(PVMCPUCC pVCpu, uint16_t *pu16Value) RT_NOEXCEPT;
4134	VBOXSTRICTRC iemMemStackPopU32(PVMCPUCC pVCpu, uint32_t *pu32Value) RT_NOEXCEPT;
4135	VBOXSTRICTRC iemMemStackPopU64(PVMCPUCC pVCpu, uint64_t *pu64Value) RT_NOEXCEPT;
4136	VBOXSTRICTRC iemMemStackPopU16Ex(PVMCPUCC pVCpu, uint16_t *pu16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4137	VBOXSTRICTRC iemMemStackPopU32Ex(PVMCPUCC pVCpu, uint32_t *pu32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4138	VBOXSTRICTRC iemMemStackPopU64Ex(PVMCPUCC pVCpu, uint64_t *pu64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4139	/** @} */
4140
4141	/** @name IEMAllCImpl.cpp
4142	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/'
4143	* @{ */
4144	IEM_CIMPL_PROTO_0(iemCImpl_popa_16);
4145	IEM_CIMPL_PROTO_0(iemCImpl_popa_32);
4146	IEM_CIMPL_PROTO_0(iemCImpl_pusha_16);
4147	IEM_CIMPL_PROTO_0(iemCImpl_pusha_32);
4148	IEM_CIMPL_PROTO_1(iemCImpl_pushf, IEMMODE, enmEffOpSize);
4149	IEM_CIMPL_PROTO_1(iemCImpl_popf, IEMMODE, enmEffOpSize);
4150	IEM_CIMPL_PROTO_1(iemCImpl_call_16, uint16_t, uNewPC);
4151	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_16, int16_t, offDisp);
4152	IEM_CIMPL_PROTO_1(iemCImpl_call_32, uint32_t, uNewPC);
4153	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_32, int32_t, offDisp);
4154	IEM_CIMPL_PROTO_1(iemCImpl_call_64, uint64_t, uNewPC);
4155	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_64, int64_t, offDisp);
4156	IEM_CIMPL_PROTO_3(iemCImpl_FarJmp, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
4157	IEM_CIMPL_PROTO_3(iemCImpl_callf, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
4158	typedef IEM_CIMPL_DECL_TYPE_3(FNIEMCIMPLFARBRANCH, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
4159	typedef FNIEMCIMPLFARBRANCH *PFNIEMCIMPLFARBRANCH;
4160	IEM_CIMPL_PROTO_2(iemCImpl_retf, IEMMODE, enmEffOpSize, uint16_t, cbPop);
4161	IEM_CIMPL_PROTO_0(iemCImpl_retn_16);
4162	IEM_CIMPL_PROTO_0(iemCImpl_retn_32);
4163	IEM_CIMPL_PROTO_0(iemCImpl_retn_64);
4164	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_16, uint16_t, cbPop);
4165	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_32, uint16_t, cbPop);
4166	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_64, uint16_t, cbPop);
4167	IEM_CIMPL_PROTO_3(iemCImpl_enter, IEMMODE, enmEffOpSize, uint16_t, cbFrame, uint8_t, cParameters);
4168	IEM_CIMPL_PROTO_1(iemCImpl_leave, IEMMODE, enmEffOpSize);
4169	IEM_CIMPL_PROTO_2(iemCImpl_int, uint8_t, u8Int, IEMINT, enmInt);
4170	IEM_CIMPL_PROTO_1(iemCImpl_iret_real_v8086, IEMMODE, enmEffOpSize);
4171	IEM_CIMPL_PROTO_4(iemCImpl_iret_prot_v8086, uint32_t, uNewEip, uint16_t, uNewCs, uint32_t, uNewFlags, uint64_t, uNewRsp);
4172	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot_NestedTask, IEMMODE, enmEffOpSize);
4173	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot, IEMMODE, enmEffOpSize);
4174	IEM_CIMPL_PROTO_1(iemCImpl_iret_64bit, IEMMODE, enmEffOpSize);
4175	IEM_CIMPL_PROTO_1(iemCImpl_iret, IEMMODE, enmEffOpSize);
4176	IEM_CIMPL_PROTO_0(iemCImpl_loadall286);
4177	IEM_CIMPL_PROTO_0(iemCImpl_syscall);
4178	IEM_CIMPL_PROTO_0(iemCImpl_sysret);
4179	IEM_CIMPL_PROTO_0(iemCImpl_sysenter);
4180	IEM_CIMPL_PROTO_1(iemCImpl_sysexit, IEMMODE, enmEffOpSize);
4181	IEM_CIMPL_PROTO_2(iemCImpl_LoadSReg, uint8_t, iSegReg, uint16_t, uSel);
4182	IEM_CIMPL_PROTO_2(iemCImpl_load_SReg, uint8_t, iSegReg, uint16_t, uSel);
4183	IEM_CIMPL_PROTO_2(iemCImpl_pop_Sreg, uint8_t, iSegReg, IEMMODE, enmEffOpSize);
4184	IEM_CIMPL_PROTO_5(iemCImpl_load_SReg_Greg, uint16_t, uSel, uint64_t, offSeg, uint8_t, iSegReg, uint8_t, iGReg, IEMMODE, enmEffOpSize);
4185	IEM_CIMPL_PROTO_2(iemCImpl_VerX, uint16_t, uSel, bool, fWrite);
4186	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u64, uint64_t *, pu64Dst, uint16_t, uSel, bool, fIsLar);
4187	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u16, uint16_t *, pu16Dst, uint16_t, uSel, bool, fIsLar);
4188	IEM_CIMPL_PROTO_3(iemCImpl_lgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
4189	IEM_CIMPL_PROTO_2(iemCImpl_sgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4190	IEM_CIMPL_PROTO_3(iemCImpl_lidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
4191	IEM_CIMPL_PROTO_2(iemCImpl_sidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4192	IEM_CIMPL_PROTO_1(iemCImpl_lldt, uint16_t, uNewLdt);
4193	IEM_CIMPL_PROTO_2(iemCImpl_sldt_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
4194	IEM_CIMPL_PROTO_2(iemCImpl_sldt_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4195	IEM_CIMPL_PROTO_1(iemCImpl_ltr, uint16_t, uNewTr);
4196	IEM_CIMPL_PROTO_2(iemCImpl_str_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
4197	IEM_CIMPL_PROTO_2(iemCImpl_str_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4198	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Cd, uint8_t, iGReg, uint8_t, iCrReg);
4199	IEM_CIMPL_PROTO_2(iemCImpl_smsw_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
4200	IEM_CIMPL_PROTO_2(iemCImpl_smsw_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4201	IEM_CIMPL_PROTO_4(iemCImpl_load_CrX, uint8_t, iCrReg, uint64_t, uNewCrX, IEMACCESSCRX, enmAccessCrX, uint8_t, iGReg);
4202	IEM_CIMPL_PROTO_2(iemCImpl_mov_Cd_Rd, uint8_t, iCrReg, uint8_t, iGReg);
4203	IEM_CIMPL_PROTO_2(iemCImpl_lmsw, uint16_t, u16NewMsw, RTGCPTR, GCPtrEffDst);
4204	IEM_CIMPL_PROTO_0(iemCImpl_clts);
4205	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Dd, uint8_t, iGReg, uint8_t, iDrReg);
4206	IEM_CIMPL_PROTO_2(iemCImpl_mov_Dd_Rd, uint8_t, iDrReg, uint8_t, iGReg);
4207	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Td, uint8_t, iGReg, uint8_t, iTrReg);
4208	IEM_CIMPL_PROTO_2(iemCImpl_mov_Td_Rd, uint8_t, iTrReg, uint8_t, iGReg);
4209	IEM_CIMPL_PROTO_1(iemCImpl_invlpg, RTGCPTR, GCPtrPage);
4210	IEM_CIMPL_PROTO_3(iemCImpl_invpcid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvpcidDesc, uint64_t, uInvpcidType);
4211	IEM_CIMPL_PROTO_0(iemCImpl_invd);
4212	IEM_CIMPL_PROTO_0(iemCImpl_wbinvd);
4213	IEM_CIMPL_PROTO_0(iemCImpl_rsm);
4214	IEM_CIMPL_PROTO_0(iemCImpl_rdtsc);
4215	IEM_CIMPL_PROTO_0(iemCImpl_rdtscp);
4216	IEM_CIMPL_PROTO_0(iemCImpl_rdpmc);
4217	IEM_CIMPL_PROTO_0(iemCImpl_rdmsr);
4218	IEM_CIMPL_PROTO_0(iemCImpl_wrmsr);
4219	IEM_CIMPL_PROTO_3(iemCImpl_in, uint16_t, u16Port, bool, fImm, uint8_t, cbReg);
4220	IEM_CIMPL_PROTO_1(iemCImpl_in_eAX_DX, uint8_t, cbReg);
4221	IEM_CIMPL_PROTO_3(iemCImpl_out, uint16_t, u16Port, bool, fImm, uint8_t, cbReg);
4222	IEM_CIMPL_PROTO_1(iemCImpl_out_DX_eAX, uint8_t, cbReg);
4223	IEM_CIMPL_PROTO_0(iemCImpl_cli);
4224	IEM_CIMPL_PROTO_0(iemCImpl_sti);
4225	IEM_CIMPL_PROTO_0(iemCImpl_hlt);
4226	IEM_CIMPL_PROTO_1(iemCImpl_monitor, uint8_t, iEffSeg);
4227	IEM_CIMPL_PROTO_0(iemCImpl_mwait);
4228	IEM_CIMPL_PROTO_0(iemCImpl_swapgs);
4229	IEM_CIMPL_PROTO_0(iemCImpl_cpuid);
4230	IEM_CIMPL_PROTO_1(iemCImpl_aad, uint8_t, bImm);
4231	IEM_CIMPL_PROTO_1(iemCImpl_aam, uint8_t, bImm);
4232	IEM_CIMPL_PROTO_0(iemCImpl_daa);
4233	IEM_CIMPL_PROTO_0(iemCImpl_das);
4234	IEM_CIMPL_PROTO_0(iemCImpl_aaa);
4235	IEM_CIMPL_PROTO_0(iemCImpl_aas);
4236	IEM_CIMPL_PROTO_3(iemCImpl_bound_16, int16_t, idxArray, int16_t, idxLowerBound, int16_t, idxUpperBound);
4237	IEM_CIMPL_PROTO_3(iemCImpl_bound_32, int32_t, idxArray, int32_t, idxLowerBound, int32_t, idxUpperBound);
4238	IEM_CIMPL_PROTO_0(iemCImpl_xgetbv);
4239	IEM_CIMPL_PROTO_0(iemCImpl_xsetbv);
4240	IEM_CIMPL_PROTO_4(iemCImpl_cmpxchg16b_fallback_rendezvous, PRTUINT128U, pu128Dst, PRTUINT128U, pu128RaxRdx,
4241	PRTUINT128U, pu128RbxRcx, uint32_t *, pEFlags);
4242	IEM_CIMPL_PROTO_2(iemCImpl_clflush_clflushopt, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
4243	IEM_CIMPL_PROTO_1(iemCImpl_finit, bool, fCheckXcpts);
4244	IEM_CIMPL_PROTO_3(iemCImpl_fxsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
4245	IEM_CIMPL_PROTO_3(iemCImpl_fxrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
4246	IEM_CIMPL_PROTO_3(iemCImpl_xsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
4247	IEM_CIMPL_PROTO_3(iemCImpl_xrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
4248	IEM_CIMPL_PROTO_2(iemCImpl_stmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
4249	IEM_CIMPL_PROTO_2(iemCImpl_vstmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
4250	IEM_CIMPL_PROTO_2(iemCImpl_ldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
4251	IEM_CIMPL_PROTO_3(iemCImpl_fnstenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4252	IEM_CIMPL_PROTO_3(iemCImpl_fnsave, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4253	IEM_CIMPL_PROTO_3(iemCImpl_fldenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
4254	IEM_CIMPL_PROTO_3(iemCImpl_frstor, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
4255	IEM_CIMPL_PROTO_1(iemCImpl_fldcw, uint16_t, u16Fcw);
4256	IEM_CIMPL_PROTO_1(iemCImpl_fxch_underflow, uint8_t, iStReg);
4257	IEM_CIMPL_PROTO_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, PFNIEMAIMPLFPUR80EFL, pfnAImpl, bool, fPop);
4258	/** @} */
4259
4260	/** @name IEMAllCImplStrInstr.cpp.h
4261	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/' -e 's/RT_CONCAT4(//' \
4262	* -e 's/,ADDR_SIZE)/64/g' -e 's/,OP_SIZE,/64/g' -e 's/,OP_rAX,/rax/g' IEMAllCImplStrInstr.cpp.h
4263	* @{ */
4264	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr16, uint8_t, iEffSeg);
4265	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr16, uint8_t, iEffSeg);
4266	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m16);
4267	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m16);
4268	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr16, uint8_t, iEffSeg);
4269	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m16);
4270	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m16, int8_t, iEffSeg);
4271	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr16, bool, fIoChecked);
4272	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr16, bool, fIoChecked);
4273	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4274	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4275
4276	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr16, uint8_t, iEffSeg);
4277	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr16, uint8_t, iEffSeg);
4278	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m16);
4279	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m16);
4280	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr16, uint8_t, iEffSeg);
4281	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m16);
4282	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m16, int8_t, iEffSeg);
4283	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr16, bool, fIoChecked);
4284	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr16, bool, fIoChecked);
4285	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4286	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4287
4288	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr16, uint8_t, iEffSeg);
4289	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr16, uint8_t, iEffSeg);
4290	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m16);
4291	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m16);
4292	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr16, uint8_t, iEffSeg);
4293	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m16);
4294	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m16, int8_t, iEffSeg);
4295	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr16, bool, fIoChecked);
4296	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr16, bool, fIoChecked);
4297	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4298	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4299
4300
4301	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr32, uint8_t, iEffSeg);
4302	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr32, uint8_t, iEffSeg);
4303	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m32);
4304	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m32);
4305	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr32, uint8_t, iEffSeg);
4306	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m32);
4307	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m32, int8_t, iEffSeg);
4308	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr32, bool, fIoChecked);
4309	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr32, bool, fIoChecked);
4310	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4311	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4312
4313	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr32, uint8_t, iEffSeg);
4314	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr32, uint8_t, iEffSeg);
4315	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m32);
4316	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m32);
4317	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr32, uint8_t, iEffSeg);
4318	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m32);
4319	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m32, int8_t, iEffSeg);
4320	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr32, bool, fIoChecked);
4321	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr32, bool, fIoChecked);
4322	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4323	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4324
4325	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr32, uint8_t, iEffSeg);
4326	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr32, uint8_t, iEffSeg);
4327	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m32);
4328	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m32);
4329	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr32, uint8_t, iEffSeg);
4330	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m32);
4331	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m32, int8_t, iEffSeg);
4332	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr32, bool, fIoChecked);
4333	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr32, bool, fIoChecked);
4334	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4335	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4336
4337	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr32, uint8_t, iEffSeg);
4338	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr32, uint8_t, iEffSeg);
4339	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m32);
4340	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m32);
4341	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr32, uint8_t, iEffSeg);
4342	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m32);
4343	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m32, int8_t, iEffSeg);
4344	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr32, bool, fIoChecked);
4345	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr32, bool, fIoChecked);
4346	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4347	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4348
4349
4350	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr64, uint8_t, iEffSeg);
4351	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr64, uint8_t, iEffSeg);
4352	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m64);
4353	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m64);
4354	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr64, uint8_t, iEffSeg);
4355	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m64);
4356	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m64, int8_t, iEffSeg);
4357	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr64, bool, fIoChecked);
4358	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr64, bool, fIoChecked);
4359	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4360	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4361
4362	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr64, uint8_t, iEffSeg);
4363	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr64, uint8_t, iEffSeg);
4364	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m64);
4365	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m64);
4366	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr64, uint8_t, iEffSeg);
4367	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m64);
4368	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m64, int8_t, iEffSeg);
4369	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr64, bool, fIoChecked);
4370	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr64, bool, fIoChecked);
4371	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4372	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4373
4374	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr64, uint8_t, iEffSeg);
4375	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr64, uint8_t, iEffSeg);
4376	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m64);
4377	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m64);
4378	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr64, uint8_t, iEffSeg);
4379	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m64);
4380	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m64, int8_t, iEffSeg);
4381	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr64, bool, fIoChecked);
4382	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr64, bool, fIoChecked);
4383	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4384	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4385
4386	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr64, uint8_t, iEffSeg);
4387	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr64, uint8_t, iEffSeg);
4388	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m64);
4389	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m64);
4390	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr64, uint8_t, iEffSeg);
4391	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m64);
4392	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m64, int8_t, iEffSeg);
4393	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr64, bool, fIoChecked);
4394	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr64, bool, fIoChecked);
4395	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4396	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4397	/** @} */
4398
4399	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
4400	VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT;
4401	VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT;
4402	VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT;
4403	VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT;
4404	VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT;
4405	VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
4406	VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALK pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT;
4407	VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT;
4408	VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT;
4409	VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
4410	bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT;
4411	VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
4412	bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT;
4413	VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4414	VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4415	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4416	VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4417	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4418	VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4419	VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT;
4420	VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
4421	RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT;
4422	VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT;
4423	VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT;
4424	VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT;
4425	uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT;
4426	void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT;
4427	VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
4428	uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT;
4429	bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT;
4430	IEM_CIMPL_PROTO_0(iemCImpl_vmxoff);
4431	IEM_CIMPL_PROTO_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon);
4432	IEM_CIMPL_PROTO_0(iemCImpl_vmlaunch);
4433	IEM_CIMPL_PROTO_0(iemCImpl_vmresume);
4434	IEM_CIMPL_PROTO_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
4435	IEM_CIMPL_PROTO_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
4436	IEM_CIMPL_PROTO_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
4437	IEM_CIMPL_PROTO_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField);
4438	IEM_CIMPL_PROTO_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField);
4439	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField);
4440	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg32, uint64_t *, pu32Dst, uint32_t, u32VmcsField);
4441	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField);
4442	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField);
4443	IEM_CIMPL_PROTO_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType);
4444	IEM_CIMPL_PROTO_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType);
4445	IEM_CIMPL_PROTO_0(iemCImpl_vmx_pause);
4446	#endif
4447
4448	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4449	VBOXSTRICTRC iemSvmVmexit(PVMCPUCC pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2) RT_NOEXCEPT;
4450	VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPUCC pVCpu, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr, uint64_t uCr2) RT_NOEXCEPT;
4451	VBOXSTRICTRC iemSvmHandleIOIntercept(PVMCPUCC pVCpu, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
4452	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, uint8_t cbInstr) RT_NOEXCEPT;
4453	VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPUCC pVCpu, uint32_t idMsr, bool fWrite) RT_NOEXCEPT;
4454	IEM_CIMPL_PROTO_0(iemCImpl_vmrun);
4455	IEM_CIMPL_PROTO_0(iemCImpl_vmload);
4456	IEM_CIMPL_PROTO_0(iemCImpl_vmsave);
4457	IEM_CIMPL_PROTO_0(iemCImpl_clgi);
4458	IEM_CIMPL_PROTO_0(iemCImpl_stgi);
4459	IEM_CIMPL_PROTO_0(iemCImpl_invlpga);
4460	IEM_CIMPL_PROTO_0(iemCImpl_skinit);
4461	IEM_CIMPL_PROTO_0(iemCImpl_svm_pause);
4462	#endif
4463
4464	IEM_CIMPL_PROTO_0(iemCImpl_vmcall); /* vmx */
4465	IEM_CIMPL_PROTO_0(iemCImpl_vmmcall); /* svm */
4466	IEM_CIMPL_PROTO_1(iemCImpl_Hypercall, uint16_t, uDisOpcode); /* both */
4467
4468
4469	extern const PFNIEMOP g_apfnIemInterpretOnlyOneByteMap[256];
4470
4471	/** @} */
4472
4473	RT_C_DECLS_END
4474
4475	#endif /* !VMM_INCLUDED_SRC_include_IEMInternal_h */
4476

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source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h@ 99949

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