IEMInternal.h@ 98915

Last change on this file since 98915 was 98887, checked in by vboxsync, 2 years ago
VMM/IEM: Implement mpsadbw instruction emulation ,bugref:9898
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1	/* $Id: IEMInternal.h 98887 2023-03-09 11:18:21Z vboxsync $ */
2	/** @file
3	* IEM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2011-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_IEMInternal_h
29	#define VMM_INCLUDED_SRC_include_IEMInternal_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#include <VBox/vmm/cpum.h>
35	#include <VBox/vmm/iem.h>
36	#include <VBox/vmm/pgm.h>
37	#include <VBox/vmm/stam.h>
38	#include <VBox/param.h>
39
40	#include <iprt/setjmp-without-sigmask.h>
41
42
43	RT_C_DECLS_BEGIN
44
45
46	/** @defgroup grp_iem_int Internals
47	* @ingroup grp_iem
48	* @internal
49	* @{
50	*/
51
52	/** For expanding symbol in slickedit and other products tagging and
53	* crossreferencing IEM symbols. */
54	#ifndef IEM_STATIC
55	# define IEM_STATIC static
56	#endif
57
58	/** @def IEM_WITH_SETJMP
59	* Enables alternative status code handling using setjmps.
60	*
61	* This adds a bit of expense via the setjmp() call since it saves all the
62	* non-volatile registers. However, it eliminates return code checks and allows
63	* for more optimal return value passing (return regs instead of stack buffer).
64	*/
65	#if defined(DOXYGEN_RUNNING) \|\| defined(RT_OS_WINDOWS) \|\| 1
66	# define IEM_WITH_SETJMP
67	#endif
68
69	/** @def IEM_WITH_THROW_CATCH
70	* Enables using C++ throw/catch as an alternative to setjmp/longjmp in user
71	* mode code when IEM_WITH_SETJMP is in effect.
72	*
73	* With GCC 11.3.1 and code TLB on linux, using throw/catch instead of
74	* setjmp/long resulted in bs2-test-1 running 3.00% faster and all but on test
75	* result value improving by more than 1%. (Best out of three.)
76	*
77	* With Visual C++ 2019 and code TLB on windows, using throw/catch instead of
78	* setjmp/long resulted in bs2-test-1 running 3.68% faster and all but some of
79	* the MMIO and CPUID tests ran noticeably faster. Variation is greater than on
80	* Linux, but it should be quite a bit faster for normal code.
81	*/
82	#if (defined(IEM_WITH_SETJMP) && defined(IN_RING3) && (defined(__GNUC__) \|\| defined(_MSC_VER))) \
83	\|\| defined(DOXYGEN_RUNNING)
84	# define IEM_WITH_THROW_CATCH
85	#endif
86
87	/** @def IEM_DO_LONGJMP
88	*
89	* Wrapper around longjmp / throw.
90	*
91	* @param a_pVCpu The CPU handle.
92	* @param a_rc The status code jump back with / throw.
93	*/
94	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
95	# ifdef IEM_WITH_THROW_CATCH
96	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) throw int(a_rc)
97	# else
98	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) longjmp(*(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf), (a_rc))
99	# endif
100	#endif
101
102	/** For use with IEM function that may do a longjmp (when enabled).
103	*
104	* Visual C++ has trouble longjmp'ing from/over functions with the noexcept
105	* attribute. So, we indicate that function that may be part of a longjmp may
106	* throw "exceptions" and that the compiler should definitely not generate and
107	* std::terminate calling unwind code.
108	*
109	* Here is one example of this ending in std::terminate:
110	* @code{.txt}
111	00 00000041`cadfda10 00007ffc`5d5a1f9f ucrtbase!abort+0x4e
112	01 00000041`cadfda40 00007ffc`57af229a ucrtbase!terminate+0x1f
113	02 00000041`cadfda70 00007ffb`eec91030 VCRUNTIME140!__std_terminate+0xa [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\ehhelpers.cpp @ 192]
114	03 00000041`cadfdaa0 00007ffb`eec92c6d VCRUNTIME140_1!_CallSettingFrame+0x20 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\handlers.asm @ 50]
115	04 00000041`cadfdad0 00007ffb`eec93ae5 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToState+0x241 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 1085]
116	05 00000041`cadfdc00 00007ffb`eec92258 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToEmptyState+0x2d [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 218]
117	06 00000041`cadfdc30 00007ffb`eec940e9 VCRUNTIME140_1!__InternalCxxFrameHandler<__FrameHandler4>+0x194 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 304]
118	07 00000041`cadfdcd0 00007ffc`5f9f249f VCRUNTIME140_1!__CxxFrameHandler4+0xa9 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 290]
119	08 00000041`cadfdd40 00007ffc`5f980939 ntdll!RtlpExecuteHandlerForUnwind+0xf
120	09 00000041`cadfdd70 00007ffc`5f9a0edd ntdll!RtlUnwindEx+0x339
121	0a 00000041`cadfe490 00007ffc`57aff976 ntdll!RtlUnwind+0xcd
122	0b 00000041`cadfea00 00007ffb`e1b5de01 VCRUNTIME140!__longjmp_internal+0xe6 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\longjmp.asm @ 140]
123	0c (Inline Function) --------`-------- VBoxVMM!iemOpcodeGetNextU8SlowJmp+0x95 [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 1155]
124	0d 00000041`cadfea50 00007ffb`e1b60f6b VBoxVMM!iemOpcodeGetNextU8Jmp+0xc1 [L:\vbox-intern\src\VBox\VMM\include\IEMInline.h @ 402]
125	0e 00000041`cadfea90 00007ffb`e1cc6201 VBoxVMM!IEMExecForExits+0xdb [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 10185]
126	0f 00000041`cadfec70 00007ffb`e1d0df8d VBoxVMM!EMHistoryExec+0x4f1 [L:\vbox-intern\src\VBox\VMM\VMMAll\EMAll.cpp @ 452]
127	10 00000041`cadfed60 00007ffb`e1d0d4c0 VBoxVMM!nemR3WinHandleExitCpuId+0x79d [L:\vbox-intern\src\VBox\VMM\VMMAll\NEMAllNativeTemplate-win.cpp.h @ 1829] @encode
128	@endcode
129	*
130	* @see https://developercommunity.visualstudio.com/t/fragile-behavior-of-longjmp-called-from-noexcept-f/1532859
131	*/
132	#if defined(IEM_WITH_SETJMP) && (defined(_MSC_VER) \|\| defined(IEM_WITH_THROW_CATCH))
133	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT_EX(false)
134	#else
135	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT
136	#endif
137
138	#define IEM_IMPLEMENTS_TASKSWITCH
139
140	/** @def IEM_WITH_3DNOW
141	* Includes the 3DNow decoding. */
142	#if (!defined(IEM_WITH_3DNOW) && !defined(IEM_WITHOUT_3DNOW)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
143	# define IEM_WITH_3DNOW
144	#endif
145
146	/** @def IEM_WITH_THREE_0F_38
147	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
148	#if (!defined(IEM_WITH_THREE_0F_38) && !defined(IEM_WITHOUT_THREE_0F_38)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
149	# define IEM_WITH_THREE_0F_38
150	#endif
151
152	/** @def IEM_WITH_THREE_0F_3A
153	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
154	#if (!defined(IEM_WITH_THREE_0F_3A) && !defined(IEM_WITHOUT_THREE_0F_3A)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
155	# define IEM_WITH_THREE_0F_3A
156	#endif
157
158	/** @def IEM_WITH_VEX
159	* Includes the VEX decoding. */
160	#if (!defined(IEM_WITH_VEX) && !defined(IEM_WITHOUT_VEX)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
161	# define IEM_WITH_VEX
162	#endif
163
164	/** @def IEM_CFG_TARGET_CPU
165	* The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
166	*
167	* By default we allow this to be configured by the user via the
168	* CPUM/GuestCpuName config string, but this comes at a slight cost during
169	* decoding. So, for applications of this code where there is no need to
170	* be dynamic wrt target CPU, just modify this define.
171	*/
172	#if !defined(IEM_CFG_TARGET_CPU) \|\| defined(DOXYGEN_RUNNING)
173	# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
174	#endif
175
176	//#define IEM_WITH_CODE_TLB // - work in progress
177	//#define IEM_WITH_DATA_TLB // - work in progress
178
179
180	/** @def IEM_USE_UNALIGNED_DATA_ACCESS
181	* Use unaligned accesses instead of elaborate byte assembly. */
182	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86) \|\| defined(DOXYGEN_RUNNING)
183	# define IEM_USE_UNALIGNED_DATA_ACCESS
184	#endif
185
186	//#define IEM_LOG_MEMORY_WRITES
187
188	#if !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
189	/** Instruction statistics. */
190	typedef struct IEMINSTRSTATS
191	{
192	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
193	# include "IEMInstructionStatisticsTmpl.h"
194	# undef IEM_DO_INSTR_STAT
195	} IEMINSTRSTATS;
196	#else
197	struct IEMINSTRSTATS;
198	typedef struct IEMINSTRSTATS IEMINSTRSTATS;
199	#endif
200	/** Pointer to IEM instruction statistics. */
201	typedef IEMINSTRSTATS *PIEMINSTRSTATS;
202
203
204	/** @name IEMTARGETCPU_EFL_BEHAVIOR_XXX - IEMCPU::aidxTargetCpuEflFlavour
205	* @{ */
206	#define IEMTARGETCPU_EFL_BEHAVIOR_NATIVE 0 /*< Native x86 EFLAGS result; Intel EFLAGS when on non-x86 hosts. /
207	#define IEMTARGETCPU_EFL_BEHAVIOR_INTEL 1 /*< Intel EFLAGS result. /
208	#define IEMTARGETCPU_EFL_BEHAVIOR_AMD 2 /*< AMD EFLAGS result /
209	#define IEMTARGETCPU_EFL_BEHAVIOR_RESERVED 3 /*< Reserved/dummy entry slot that's the same as 0. /
210	#define IEMTARGETCPU_EFL_BEHAVIOR_MASK 3 /*< For masking the index before use. /
211	/** Selects the right variant from a_aArray.
212	* pVCpu is implicit in the caller context. */
213	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT(a_aArray) \
214	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[1] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
215	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for when no native worker can
216	* be used because the host CPU does not support the operation. */
217	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_NON_NATIVE(a_aArray) \
218	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
219	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for a two dimentional
220	* array paralleling IEMCPU::aidxTargetCpuEflFlavour and a single bit index
221	* into the two.
222	* @sa IEM_SELECT_NATIVE_OR_FALLBACK */
223	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
224	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
225	(a_aaArray[a_fNative][pVCpu->iem.s.aidxTargetCpuEflFlavour[a_fNative] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
226	#else
227	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
228	(a_aaArray[0][pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
229	#endif
230	/** @} */
231
232	/**
233	* Picks @a a_pfnNative or @a a_pfnFallback according to the host CPU feature
234	* indicator given by @a a_fCpumFeatureMember (CPUMFEATURES member).
235	*
236	* On non-x86 hosts, this will shortcut to the fallback w/o checking the
237	* indicator.
238	*
239	* @sa IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX
240	*/
241	#if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
242	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) \
243	(g_CpumHostFeatures.s.a_fCpumFeatureMember ? a_pfnNative : a_pfnFallback)
244	#else
245	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) (a_pfnFallback)
246	#endif
247
248
249	/**
250	* Extended operand mode that includes a representation of 8-bit.
251	*
252	* This is used for packing down modes when invoking some C instruction
253	* implementations.
254	*/
255	typedef enum IEMMODEX
256	{
257	IEMMODEX_16BIT = IEMMODE_16BIT,
258	IEMMODEX_32BIT = IEMMODE_32BIT,
259	IEMMODEX_64BIT = IEMMODE_64BIT,
260	IEMMODEX_8BIT
261	} IEMMODEX;
262	AssertCompileSize(IEMMODEX, 4);
263
264
265	/**
266	* Branch types.
267	*/
268	typedef enum IEMBRANCH
269	{
270	IEMBRANCH_JUMP = 1,
271	IEMBRANCH_CALL,
272	IEMBRANCH_TRAP,
273	IEMBRANCH_SOFTWARE_INT,
274	IEMBRANCH_HARDWARE_INT
275	} IEMBRANCH;
276	AssertCompileSize(IEMBRANCH, 4);
277
278
279	/**
280	* INT instruction types.
281	*/
282	typedef enum IEMINT
283	{
284	/** INT n instruction (opcode 0xcd imm). */
285	IEMINT_INTN = 0,
286	/** Single byte INT3 instruction (opcode 0xcc). */
287	IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
288	/** Single byte INTO instruction (opcode 0xce). */
289	IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
290	/** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
291	IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
292	} IEMINT;
293	AssertCompileSize(IEMINT, 4);
294
295
296	/**
297	* A FPU result.
298	*/
299	typedef struct IEMFPURESULT
300	{
301	/** The output value. */
302	RTFLOAT80U r80Result;
303	/** The output status. */
304	uint16_t FSW;
305	} IEMFPURESULT;
306	AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
307	/** Pointer to a FPU result. */
308	typedef IEMFPURESULT *PIEMFPURESULT;
309	/** Pointer to a const FPU result. */
310	typedef IEMFPURESULT const *PCIEMFPURESULT;
311
312
313	/**
314	* A FPU result consisting of two output values and FSW.
315	*/
316	typedef struct IEMFPURESULTTWO
317	{
318	/** The first output value. */
319	RTFLOAT80U r80Result1;
320	/** The output status. */
321	uint16_t FSW;
322	/** The second output value. */
323	RTFLOAT80U r80Result2;
324	} IEMFPURESULTTWO;
325	AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
326	AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
327	/** Pointer to a FPU result consisting of two output values and FSW. */
328	typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
329	/** Pointer to a const FPU result consisting of two output values and FSW. */
330	typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
331
332
333	/**
334	* IEM TLB entry.
335	*
336	* Lookup assembly:
337	* @code{.asm}
338	; Calculate tag.
339	mov rax, [VA]
340	shl rax, 16
341	shr rax, 16 + X86_PAGE_SHIFT
342	or rax, [uTlbRevision]
343
344	; Do indexing.
345	movzx ecx, al
346	lea rcx, [pTlbEntries + rcx]
347
348	; Check tag.
349	cmp [rcx + IEMTLBENTRY.uTag], rax
350	jne .TlbMiss
351
352	; Check access.
353	mov rax, ACCESS_FLAGS \| MAPPING_R3_NOT_VALID \| 0xffffff00
354	and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
355	cmp rax, [uTlbPhysRev]
356	jne .TlbMiss
357
358	; Calc address and we're done.
359	mov eax, X86_PAGE_OFFSET_MASK
360	and eax, [VA]
361	or rax, [rcx + IEMTLBENTRY.pMappingR3]
362	%ifdef VBOX_WITH_STATISTICS
363	inc qword [cTlbHits]
364	%endif
365	jmp .Done
366
367	.TlbMiss:
368	mov r8d, ACCESS_FLAGS
369	mov rdx, [VA]
370	mov rcx, [pVCpu]
371	call iemTlbTypeMiss
372	.Done:
373
374	@endcode
375	*
376	*/
377	typedef struct IEMTLBENTRY
378	{
379	/** The TLB entry tag.
380	* Bits 35 thru 0 are made up of the virtual address shifted right 12 bits, this
381	* is ASSUMING a virtual address width of 48 bits.
382	*
383	* Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
384	*
385	* The TLB lookup code uses the current TLB revision, which won't ever be zero,
386	* enabling an extremely cheap TLB invalidation most of the time. When the TLB
387	* revision wraps around though, the tags needs to be zeroed.
388	*
389	* @note Try use SHRD instruction? After seeing
390	* https://gmplib.org/~tege/x86-timing.pdf, maybe not.
391	*
392	* @todo This will need to be reorganized for 57-bit wide virtual address and
393	* PCID (currently 12 bits) and ASID (currently 6 bits) support. We'll
394	* have to move the TLB entry versioning entirely to the
395	* fFlagsAndPhysRev member then, 57 bit wide VAs means we'll only have
396	* 19 bits left (64 - 57 + 12 = 19) and they'll almost entire be
397	* consumed by PCID and ASID (12 + 6 = 18).
398	*/
399	uint64_t uTag;
400	/** Access flags and physical TLB revision.
401	*
402	* - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
403	* - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
404	* - Bit 2 - page tables - not user (complemented X86_PTE_US).
405	* - Bit 3 - pgm phys/virt - not directly writable.
406	* - Bit 4 - pgm phys page - not directly readable.
407	* - Bit 5 - page tables - not accessed (complemented X86_PTE_A).
408	* - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
409	* - Bit 7 - tlb entry - pMappingR3 member not valid.
410	* - Bits 63 thru 8 are used for the physical TLB revision number.
411	*
412	* We're using complemented bit meanings here because it makes it easy to check
413	* whether special action is required. For instance a user mode write access
414	* would do a "TEST fFlags, (X86_PTE_RW \| X86_PTE_US \| X86_PTE_D)" and a
415	* non-zero result would mean special handling needed because either it wasn't
416	* writable, or it wasn't user, or the page wasn't dirty. A user mode read
417	* access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
418	* need to check any PTE flag.
419	*/
420	uint64_t fFlagsAndPhysRev;
421	/** The guest physical page address. */
422	uint64_t GCPhys;
423	/** Pointer to the ring-3 mapping. */
424	R3PTRTYPE(uint8_t *) pbMappingR3;
425	#if HC_ARCH_BITS == 32
426	uint32_t u32Padding1;
427	#endif
428	} IEMTLBENTRY;
429	AssertCompileSize(IEMTLBENTRY, 32);
430	/** Pointer to an IEM TLB entry. */
431	typedef IEMTLBENTRY *PIEMTLBENTRY;
432
433	/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
434	* @{ */
435	#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /*< Page tables: Not executable. /
436	#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /*< Page tables: Not writable. /
437	#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /*< Page tables: Not user accessible (supervisor only). /
438	#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /*< Phys page: Not writable (access handler, ROM, whatever). /
439	#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /*< Phys page: Not readable (MMIO / access handler, ROM) /
440	#define IEMTLBE_F_PT_NO_ACCESSED RT_BIT_64(5) /*< Phys tables: Not accessed (need to be marked accessed). /
441	#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /*< Page tables: Not dirty (needs to be made dirty on write). /
442	#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(7) /*< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. /
443	#define IEMTLBE_F_PG_UNASSIGNED RT_BIT_64(8) /*< Phys page: Unassigned memory (not RAM, ROM, MMIO2 or MMIO). /
444	#define IEMTLBE_F_PHYS_REV UINT64_C(0xfffffffffffffe00) /*< Physical revision mask. @sa IEMTLB_PHYS_REV_INCR /
445	/** @} */
446
447
448	/**
449	* An IEM TLB.
450	*
451	* We've got two of these, one for data and one for instructions.
452	*/
453	typedef struct IEMTLB
454	{
455	/** The TLB entries.
456	* We've choosen 256 because that way we can obtain the result directly from a
457	* 8-bit register without an additional AND instruction. */
458	IEMTLBENTRY aEntries[256];
459	/** The TLB revision.
460	* This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
461	* by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
462	* the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
463	* (The revision zero indicates an invalid TLB entry.)
464	*
465	* The initial value is choosen to cause an early wraparound. */
466	uint64_t uTlbRevision;
467	/** The TLB physical address revision - shadow of PGM variable.
468	*
469	* This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
470	* incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
471	* a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
472	* as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
473	*
474	* The initial value is choosen to cause an early wraparound. */
475	uint64_t volatile uTlbPhysRev;
476
477	/* Statistics: */
478
479	/** TLB hits (VBOX_WITH_STATISTICS only). */
480	uint64_t cTlbHits;
481	/** TLB misses. */
482	uint32_t cTlbMisses;
483	/** Slow read path. */
484	uint32_t cTlbSlowReadPath;
485	#if 0
486	/** TLB misses because of tag mismatch. */
487	uint32_t cTlbMissesTag;
488	/** TLB misses because of virtual access violation. */
489	uint32_t cTlbMissesVirtAccess;
490	/** TLB misses because of dirty bit. */
491	uint32_t cTlbMissesDirty;
492	/** TLB misses because of MMIO */
493	uint32_t cTlbMissesMmio;
494	/** TLB misses because of write access handlers. */
495	uint32_t cTlbMissesWriteHandler;
496	/** TLB misses because no r3(/r0) mapping. */
497	uint32_t cTlbMissesMapping;
498	#endif
499	/** Alignment padding. */
500	uint32_t au32Padding[3+5];
501	} IEMTLB;
502	AssertCompileSizeAlignment(IEMTLB, 64);
503	/** IEMTLB::uTlbRevision increment. */
504	#define IEMTLB_REVISION_INCR RT_BIT_64(36)
505	/** IEMTLB::uTlbRevision mask. */
506	#define IEMTLB_REVISION_MASK (~(RT_BIT_64(36) - 1))
507	/** IEMTLB::uTlbPhysRev increment.
508	* @sa IEMTLBE_F_PHYS_REV */
509	#define IEMTLB_PHYS_REV_INCR RT_BIT_64(9)
510	/**
511	* Calculates the TLB tag for a virtual address.
512	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
513	* @param a_pTlb The TLB.
514	* @param a_GCPtr The virtual address.
515	*/
516	#define IEMTLB_CALC_TAG(a_pTlb, a_GCPtr) ( IEMTLB_CALC_TAG_NO_REV(a_GCPtr) \| (a_pTlb)->uTlbRevision )
517	/**
518	* Calculates the TLB tag for a virtual address but without TLB revision.
519	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
520	* @param a_GCPtr The virtual address.
521	*/
522	#define IEMTLB_CALC_TAG_NO_REV(a_GCPtr) ( (((a_GCPtr) << 16) >> (GUEST_PAGE_SHIFT + 16)) )
523	/**
524	* Converts a TLB tag value into a TLB index.
525	* @returns Index into IEMTLB::aEntries.
526	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
527	*/
528	#define IEMTLB_TAG_TO_INDEX(a_uTag) ( (uint8_t)(a_uTag) )
529	/**
530	* Converts a TLB tag value into a TLB index.
531	* @returns Index into IEMTLB::aEntries.
532	* @param a_pTlb The TLB.
533	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
534	*/
535	#define IEMTLB_TAG_TO_ENTRY(a_pTlb, a_uTag) ( &(a_pTlb)->aEntries[IEMTLB_TAG_TO_INDEX(a_uTag)] )
536
537
538	/**
539	* The per-CPU IEM state.
540	*/
541	typedef struct IEMCPU
542	{
543	/** Info status code that needs to be propagated to the IEM caller.
544	* This cannot be passed internally, as it would complicate all success
545	* checks within the interpreter making the code larger and almost impossible
546	* to get right. Instead, we'll store status codes to pass on here. Each
547	* source of these codes will perform appropriate sanity checks. */
548	int32_t rcPassUp; /* 0x00 */
549
550	/** The current CPU execution mode (CS). */
551	IEMMODE enmCpuMode; /* 0x04 */
552	/** The CPL. */
553	uint8_t uCpl; /* 0x05 */
554
555	/** Whether to bypass access handlers or not. */
556	bool fBypassHandlers : 1; /* 0x06.0 */
557	/** Whether to disregard the lock prefix (implied or not). */
558	bool fDisregardLock : 1; /* 0x06.1 */
559	/** Whether there are pending hardware instruction breakpoints. */
560	bool fPendingInstructionBreakpoints : 1; /* 0x06.2 */
561	/** Whether there are pending hardware data breakpoints. */
562	bool fPendingDataBreakpoints : 1; /* 0x06.3 */
563	/** Whether there are pending hardware I/O breakpoints. */
564	bool fPendingIoBreakpoints : 1; /* 0x06.4 */
565
566	/* Unused/padding */
567	bool fUnused; /* 0x07 */
568
569	/** @name Decoder state.
570	* @{ */
571	#ifdef IEM_WITH_CODE_TLB
572	/** The offset of the next instruction byte. */
573	uint32_t offInstrNextByte; /* 0x08 */
574	/** The number of bytes available at pbInstrBuf for the current instruction.
575	* This takes the max opcode length into account so that doesn't need to be
576	* checked separately. */
577	uint32_t cbInstrBuf; /* 0x0c */
578	/** Pointer to the page containing RIP, user specified buffer or abOpcode.
579	* This can be NULL if the page isn't mappable for some reason, in which
580	* case we'll do fallback stuff.
581	*
582	* If we're executing an instruction from a user specified buffer,
583	* IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
584	* aligned pointer but pointer to the user data.
585	*
586	* For instructions crossing pages, this will start on the first page and be
587	* advanced to the next page by the time we've decoded the instruction. This
588	* therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
589	*/
590	uint8_t const pbInstrBuf; / 0x10 */
591	# if ARCH_BITS == 32
592	uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
593	# endif
594	/** The program counter corresponding to pbInstrBuf.
595	* This is set to a non-canonical address when we need to invalidate it. */
596	uint64_t uInstrBufPc; /* 0x18 */
597	/** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
598	* This takes the CS segment limit into account. */
599	uint16_t cbInstrBufTotal; /* 0x20 */
600	/** Offset into pbInstrBuf of the first byte of the current instruction.
601	* Can be negative to efficiently handle cross page instructions. */
602	int16_t offCurInstrStart; /* 0x22 */
603
604	/** The prefix mask (IEM_OP_PRF_XXX). */
605	uint32_t fPrefixes; /* 0x24 */
606	/** The extra REX ModR/M register field bit (REX.R << 3). */
607	uint8_t uRexReg; /* 0x28 */
608	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
609	* (REX.B << 3). */
610	uint8_t uRexB; /* 0x29 */
611	/** The extra REX SIB index field bit (REX.X << 3). */
612	uint8_t uRexIndex; /* 0x2a */
613
614	/** The effective segment register (X86_SREG_XXX). */
615	uint8_t iEffSeg; /* 0x2b */
616
617	/** The offset of the ModR/M byte relative to the start of the instruction. */
618	uint8_t offModRm; /* 0x2c */
619	#else /* !IEM_WITH_CODE_TLB */
620	/** The size of what has currently been fetched into abOpcode. */
621	uint8_t cbOpcode; /* 0x08 */
622	/** The current offset into abOpcode. */
623	uint8_t offOpcode; /* 0x09 */
624	/** The offset of the ModR/M byte relative to the start of the instruction. */
625	uint8_t offModRm; /* 0x0a */
626
627	/** The effective segment register (X86_SREG_XXX). */
628	uint8_t iEffSeg; /* 0x0b */
629
630	/** The prefix mask (IEM_OP_PRF_XXX). */
631	uint32_t fPrefixes; /* 0x0c */
632	/** The extra REX ModR/M register field bit (REX.R << 3). */
633	uint8_t uRexReg; /* 0x10 */
634	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
635	* (REX.B << 3). */
636	uint8_t uRexB; /* 0x11 */
637	/** The extra REX SIB index field bit (REX.X << 3). */
638	uint8_t uRexIndex; /* 0x12 */
639
640	#endif /* !IEM_WITH_CODE_TLB */
641
642	/** The effective operand mode. */
643	IEMMODE enmEffOpSize; /* 0x2d, 0x13 */
644	/** The default addressing mode. */
645	IEMMODE enmDefAddrMode; /* 0x2e, 0x14 */
646	/** The effective addressing mode. */
647	IEMMODE enmEffAddrMode; /* 0x2f, 0x15 */
648	/** The default operand mode. */
649	IEMMODE enmDefOpSize; /* 0x30, 0x16 */
650
651	/** Prefix index (VEX.pp) for two byte and three byte tables. */
652	uint8_t idxPrefix; /* 0x31, 0x17 */
653	/** 3rd VEX/EVEX/XOP register.
654	* Please use IEM_GET_EFFECTIVE_VVVV to access. */
655	uint8_t uVex3rdReg; /* 0x32, 0x18 */
656	/** The VEX/EVEX/XOP length field. */
657	uint8_t uVexLength; /* 0x33, 0x19 */
658	/** Additional EVEX stuff. */
659	uint8_t fEvexStuff; /* 0x34, 0x1a */
660
661	/** Explicit alignment padding. */
662	uint8_t abAlignment2a[1]; /* 0x35, 0x1b */
663	/** The FPU opcode (FOP). */
664	uint16_t uFpuOpcode; /* 0x36, 0x1c */
665	#ifndef IEM_WITH_CODE_TLB
666	/** Explicit alignment padding. */
667	uint8_t abAlignment2b[2]; /* 0x1e */
668	#endif
669
670	/** The opcode bytes. */
671	uint8_t abOpcode[15]; /* 0x48, 0x20 */
672	/** Explicit alignment padding. */
673	#ifdef IEM_WITH_CODE_TLB
674	uint8_t abAlignment2c[0x48 - 0x47]; /* 0x37 */
675	#else
676	uint8_t abAlignment2c[0x48 - 0x2f]; /* 0x2f */
677	#endif
678	/** @} */
679
680
681	/** The flags of the current exception / interrupt. */
682	uint32_t fCurXcpt; /* 0x48, 0x48 */
683	/** The current exception / interrupt. */
684	uint8_t uCurXcpt;
685	/** Exception / interrupt recursion depth. */
686	int8_t cXcptRecursions;
687
688	/** The number of active guest memory mappings. */
689	uint8_t cActiveMappings;
690	/** The next unused mapping index. */
691	uint8_t iNextMapping;
692	/** Records for tracking guest memory mappings. */
693	struct
694	{
695	/** The address of the mapped bytes. */
696	void *pv;
697	/** The access flags (IEM_ACCESS_XXX).
698	* IEM_ACCESS_INVALID if the entry is unused. */
699	uint32_t fAccess;
700	#if HC_ARCH_BITS == 64
701	uint32_t u32Alignment4; /*< Alignment padding. /
702	#endif
703	} aMemMappings[3];
704
705	/** Locking records for the mapped memory. */
706	union
707	{
708	PGMPAGEMAPLOCK Lock;
709	uint64_t au64Padding[2];
710	} aMemMappingLocks[3];
711
712	/** Bounce buffer info.
713	* This runs in parallel to aMemMappings. */
714	struct
715	{
716	/** The physical address of the first byte. */
717	RTGCPHYS GCPhysFirst;
718	/** The physical address of the second page. */
719	RTGCPHYS GCPhysSecond;
720	/** The number of bytes in the first page. */
721	uint16_t cbFirst;
722	/** The number of bytes in the second page. */
723	uint16_t cbSecond;
724	/** Whether it's unassigned memory. */
725	bool fUnassigned;
726	/** Explicit alignment padding. */
727	bool afAlignment5[3];
728	} aMemBbMappings[3];
729
730	/* Ensure that aBounceBuffers are aligned at a 32 byte boundrary. */
731	uint64_t abAlignment7[1];
732
733	/** Bounce buffer storage.
734	* This runs in parallel to aMemMappings and aMemBbMappings. */
735	struct
736	{
737	uint8_t ab[512];
738	} aBounceBuffers[3];
739
740
741	/** Pointer set jump buffer - ring-3 context. */
742	R3PTRTYPE(jmp_buf *) pJmpBufR3;
743	/** Pointer set jump buffer - ring-0 context. */
744	R0PTRTYPE(jmp_buf *) pJmpBufR0;
745
746	/** @todo Should move this near @a fCurXcpt later. */
747	/** The CR2 for the current exception / interrupt. */
748	uint64_t uCurXcptCr2;
749	/** The error code for the current exception / interrupt. */
750	uint32_t uCurXcptErr;
751
752	/** @name Statistics
753	* @{ */
754	/** The number of instructions we've executed. */
755	uint32_t cInstructions;
756	/** The number of potential exits. */
757	uint32_t cPotentialExits;
758	/** The number of bytes data or stack written (mostly for IEMExecOneEx).
759	* This may contain uncommitted writes. */
760	uint32_t cbWritten;
761	/** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
762	uint32_t cRetInstrNotImplemented;
763	/** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
764	uint32_t cRetAspectNotImplemented;
765	/** Counts informational statuses returned (other than VINF_SUCCESS). */
766	uint32_t cRetInfStatuses;
767	/** Counts other error statuses returned. */
768	uint32_t cRetErrStatuses;
769	/** Number of times rcPassUp has been used. */
770	uint32_t cRetPassUpStatus;
771	/** Number of times RZ left with instruction commit pending for ring-3. */
772	uint32_t cPendingCommit;
773	/** Number of long jumps. */
774	uint32_t cLongJumps;
775	/** @} */
776
777	/** @name Target CPU information.
778	* @{ */
779	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
780	/** The target CPU. */
781	uint8_t uTargetCpu;
782	#else
783	uint8_t bTargetCpuPadding;
784	#endif
785	/** For selecting assembly works matching the target CPU EFLAGS behaviour, see
786	* IEMTARGETCPU_EFL_BEHAVIOR_XXX for values, with the 1st entry for when no
787	* native host support and the 2nd for when there is.
788	*
789	* The two values are typically indexed by a g_CpumHostFeatures bit.
790	*
791	* This is for instance used for the BSF & BSR instructions where AMD and
792	* Intel CPUs produce different EFLAGS. */
793	uint8_t aidxTargetCpuEflFlavour[2];
794
795	/** The CPU vendor. */
796	CPUMCPUVENDOR enmCpuVendor;
797	/** @} */
798
799	/** @name Host CPU information.
800	* @{ */
801	/** The CPU vendor. */
802	CPUMCPUVENDOR enmHostCpuVendor;
803	/** @} */
804
805	/** Counts RDMSR \#GP(0) LogRel(). */
806	uint8_t cLogRelRdMsr;
807	/** Counts WRMSR \#GP(0) LogRel(). */
808	uint8_t cLogRelWrMsr;
809	/** Alignment padding. */
810	uint8_t abAlignment8[42];
811
812	/** Data TLB.
813	* @remarks Must be 64-byte aligned. */
814	IEMTLB DataTlb;
815	/** Instruction TLB.
816	* @remarks Must be 64-byte aligned. */
817	IEMTLB CodeTlb;
818
819	/** Exception statistics. */
820	STAMCOUNTER aStatXcpts[32];
821	/** Interrupt statistics. */
822	uint32_t aStatInts[256];
823
824	#if defined(VBOX_WITH_STATISTICS) && !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
825	/** Instruction statistics for ring-0/raw-mode. */
826	IEMINSTRSTATS StatsRZ;
827	/** Instruction statistics for ring-3. */
828	IEMINSTRSTATS StatsR3;
829	#endif
830	} IEMCPU;
831	AssertCompileMemberOffset(IEMCPU, fCurXcpt, 0x48);
832	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 8);
833	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 16);
834	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 32);
835	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 64);
836	AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
837	AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
838
839	/** Pointer to the per-CPU IEM state. */
840	typedef IEMCPU *PIEMCPU;
841	/** Pointer to the const per-CPU IEM state. */
842	typedef IEMCPU const *PCIEMCPU;
843
844
845	/** @def IEM_GET_CTX
846	* Gets the guest CPU context for the calling EMT.
847	* @returns PCPUMCTX
848	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
849	*/
850	#define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
851
852	/** @def IEM_CTX_ASSERT
853	* Asserts that the @a a_fExtrnMbz is present in the CPU context.
854	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
855	* @param a_fExtrnMbz The mask of CPUMCTX_EXTRN_XXX flags that must be zero.
856	*/
857	#define IEM_CTX_ASSERT(a_pVCpu, a_fExtrnMbz) AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
858	("fExtrn=%#RX64 fExtrnMbz=%#RX64\n", (a_pVCpu)->cpum.GstCtx.fExtrn, \
859	(a_fExtrnMbz)))
860
861	/** @def IEM_CTX_IMPORT_RET
862	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
863	*
864	* Will call the keep to import the bits as needed.
865	*
866	* Returns on import failure.
867	*
868	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
869	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
870	*/
871	#define IEM_CTX_IMPORT_RET(a_pVCpu, a_fExtrnImport) \
872	do { \
873	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
874	{ /* likely */ } \
875	else \
876	{ \
877	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
878	AssertRCReturn(rcCtxImport, rcCtxImport); \
879	} \
880	} while (0)
881
882	/** @def IEM_CTX_IMPORT_NORET
883	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
884	*
885	* Will call the keep to import the bits as needed.
886	*
887	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
888	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
889	*/
890	#define IEM_CTX_IMPORT_NORET(a_pVCpu, a_fExtrnImport) \
891	do { \
892	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
893	{ /* likely */ } \
894	else \
895	{ \
896	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
897	AssertLogRelRC(rcCtxImport); \
898	} \
899	} while (0)
900
901	/** @def IEM_CTX_IMPORT_JMP
902	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
903	*
904	* Will call the keep to import the bits as needed.
905	*
906	* Jumps on import failure.
907	*
908	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
909	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
910	*/
911	#define IEM_CTX_IMPORT_JMP(a_pVCpu, a_fExtrnImport) \
912	do { \
913	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
914	{ /* likely */ } \
915	else \
916	{ \
917	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
918	AssertRCStmt(rcCtxImport, IEM_DO_LONGJMP(pVCpu, rcCtxImport)); \
919	} \
920	} while (0)
921
922
923
924	/** @def IEM_GET_TARGET_CPU
925	* Gets the current IEMTARGETCPU value.
926	* @returns IEMTARGETCPU value.
927	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
928	*/
929	#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
930	# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
931	#else
932	# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
933	#endif
934
935	/** @def IEM_GET_INSTR_LEN
936	* Gets the instruction length. */
937	#ifdef IEM_WITH_CODE_TLB
938	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
939	#else
940	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
941	#endif
942
943
944	/**
945	* Shared per-VM IEM data.
946	*/
947	typedef struct IEM
948	{
949	/** The VMX APIC-access page handler type. */
950	PGMPHYSHANDLERTYPE hVmxApicAccessPage;
951	#ifndef VBOX_WITHOUT_CPUID_HOST_CALL
952	/** Set if the CPUID host call functionality is enabled. */
953	bool fCpuIdHostCall;
954	#endif
955	} IEM;
956
957
958
959	/** @name IEM_ACCESS_XXX - Access details.
960	* @{ */
961	#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
962	#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
963	#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
964	#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
965	#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
966	#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
967	#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
968	#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
969	#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
970	#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
971	/** The writes are partial, so if initialize the bounce buffer with the
972	* orignal RAM content. */
973	#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
974	/** Used in aMemMappings to indicate that the entry is bounce buffered. */
975	#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
976	/** Bounce buffer with ring-3 write pending, first page. */
977	#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
978	/** Bounce buffer with ring-3 write pending, second page. */
979	#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
980	/** Not locked, accessed via the TLB. */
981	#define IEM_ACCESS_NOT_LOCKED UINT32_C(0x00001000)
982	/** Valid bit mask. */
983	#define IEM_ACCESS_VALID_MASK UINT32_C(0x00001fff)
984	/** Shift count for the TLB flags (upper word). */
985	#define IEM_ACCESS_SHIFT_TLB_FLAGS 16
986
987	/** Read+write data alias. */
988	#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
989	/** Write data alias. */
990	#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
991	/** Read data alias. */
992	#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_DATA)
993	/** Instruction fetch alias. */
994	#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_WHAT_CODE)
995	/** Stack write alias. */
996	#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
997	/** Stack read alias. */
998	#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_STACK)
999	/** Stack read+write alias. */
1000	#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
1001	/** Read system table alias. */
1002	#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_SYS)
1003	/** Read+write system table alias. */
1004	#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_SYS)
1005	/** @} */
1006
1007	/** @name Prefix constants (IEMCPU::fPrefixes)
1008	* @{ */
1009	#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /*< CS segment prefix (0x2e). /
1010	#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /*< SS segment prefix (0x36). /
1011	#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /*< DS segment prefix (0x3e). /
1012	#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /*< ES segment prefix (0x26). /
1013	#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /*< FS segment prefix (0x64). /
1014	#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /*< GS segment prefix (0x65). /
1015	#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
1016
1017	#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /*< Operand size prefix (0x66). /
1018	#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /*< REX.W prefix (0x48-0x4f). /
1019	#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /*< Address size prefix (0x67). /
1020
1021	#define IEM_OP_PRF_LOCK RT_BIT_32(16) /*< Lock prefix (0xf0). /
1022	#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /*< Repeat-not-zero prefix (0xf2). /
1023	#define IEM_OP_PRF_REPZ RT_BIT_32(18) /*< Repeat-if-zero prefix (0xf3). /
1024
1025	#define IEM_OP_PRF_REX RT_BIT_32(24) /*< Any REX prefix (0x40-0x4f). /
1026	#define IEM_OP_PRF_REX_R RT_BIT_32(25) /*< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). /
1027	#define IEM_OP_PRF_REX_B RT_BIT_32(26) /*< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). /
1028	#define IEM_OP_PRF_REX_X RT_BIT_32(27) /*< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). /
1029	/** Mask with all the REX prefix flags.
1030	* This is generally for use when needing to undo the REX prefixes when they
1031	* are followed legacy prefixes and therefore does not immediately preceed
1032	* the first opcode byte.
1033	* For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
1034	#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX \| IEM_OP_PRF_REX_R \| IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X \| IEM_OP_PRF_SIZE_REX_W )
1035
1036	#define IEM_OP_PRF_VEX RT_BIT_32(28) /*< Indiciates VEX prefix. /
1037	#define IEM_OP_PRF_EVEX RT_BIT_32(29) /*< Indiciates EVEX prefix. /
1038	#define IEM_OP_PRF_XOP RT_BIT_32(30) /*< Indiciates XOP prefix. /
1039	/** @} */
1040
1041	/** @name IEMOPFORM_XXX - Opcode forms
1042	* @note These are ORed together with IEMOPHINT_XXX.
1043	* @{ */
1044	/** ModR/M: reg, r/m */
1045	#define IEMOPFORM_RM 0
1046	/** ModR/M: reg, r/m (register) */
1047	#define IEMOPFORM_RM_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
1048	/** ModR/M: reg, r/m (memory) */
1049	#define IEMOPFORM_RM_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
1050	/** ModR/M: reg, r/m */
1051	#define IEMOPFORM_RMI 1
1052	/** ModR/M: reg, r/m (register) */
1053	#define IEMOPFORM_RMI_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
1054	/** ModR/M: reg, r/m (memory) */
1055	#define IEMOPFORM_RMI_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
1056	/** ModR/M: r/m, reg */
1057	#define IEMOPFORM_MR 2
1058	/** ModR/M: r/m (register), reg */
1059	#define IEMOPFORM_MR_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
1060	/** ModR/M: r/m (memory), reg */
1061	#define IEMOPFORM_MR_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
1062	/** ModR/M: r/m, reg */
1063	#define IEMOPFORM_MRI 3
1064	/** ModR/M: r/m (register), reg */
1065	#define IEMOPFORM_MRI_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
1066	/** ModR/M: r/m (memory), reg */
1067	#define IEMOPFORM_MRI_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
1068	/** ModR/M: r/m only */
1069	#define IEMOPFORM_M 4
1070	/** ModR/M: r/m only (register). */
1071	#define IEMOPFORM_M_REG (IEMOPFORM_M \| IEMOPFORM_MOD3)
1072	/** ModR/M: r/m only (memory). */
1073	#define IEMOPFORM_M_MEM (IEMOPFORM_M \| IEMOPFORM_NOT_MOD3)
1074	/** ModR/M: reg only */
1075	#define IEMOPFORM_R 5
1076
1077	/** VEX+ModR/M: reg, r/m */
1078	#define IEMOPFORM_VEX_RM 8
1079	/** VEX+ModR/M: reg, r/m (register) */
1080	#define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM \| IEMOPFORM_MOD3)
1081	/** VEX+ModR/M: reg, r/m (memory) */
1082	#define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM \| IEMOPFORM_NOT_MOD3)
1083	/** VEX+ModR/M: r/m, reg */
1084	#define IEMOPFORM_VEX_MR 9
1085	/** VEX+ModR/M: r/m (register), reg */
1086	#define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR \| IEMOPFORM_MOD3)
1087	/** VEX+ModR/M: r/m (memory), reg */
1088	#define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR \| IEMOPFORM_NOT_MOD3)
1089	/** VEX+ModR/M: r/m only */
1090	#define IEMOPFORM_VEX_M 10
1091	/** VEX+ModR/M: r/m only (register). */
1092	#define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M \| IEMOPFORM_MOD3)
1093	/** VEX+ModR/M: r/m only (memory). */
1094	#define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M \| IEMOPFORM_NOT_MOD3)
1095	/** VEX+ModR/M: reg only */
1096	#define IEMOPFORM_VEX_R 11
1097	/** VEX+ModR/M: reg, vvvv, r/m */
1098	#define IEMOPFORM_VEX_RVM 12
1099	/** VEX+ModR/M: reg, vvvv, r/m (register). */
1100	#define IEMOPFORM_VEX_RVM_REG (IEMOPFORM_VEX_RVM \| IEMOPFORM_MOD3)
1101	/** VEX+ModR/M: reg, vvvv, r/m (memory). */
1102	#define IEMOPFORM_VEX_RVM_MEM (IEMOPFORM_VEX_RVM \| IEMOPFORM_NOT_MOD3)
1103	/** VEX+ModR/M: reg, r/m, vvvv */
1104	#define IEMOPFORM_VEX_RMV 13
1105	/** VEX+ModR/M: reg, r/m, vvvv (register). */
1106	#define IEMOPFORM_VEX_RMV_REG (IEMOPFORM_VEX_RMV \| IEMOPFORM_MOD3)
1107	/** VEX+ModR/M: reg, r/m, vvvv (memory). */
1108	#define IEMOPFORM_VEX_RMV_MEM (IEMOPFORM_VEX_RMV \| IEMOPFORM_NOT_MOD3)
1109	/** VEX+ModR/M: reg, r/m, imm8 */
1110	#define IEMOPFORM_VEX_RMI 14
1111	/** VEX+ModR/M: reg, r/m, imm8 (register). */
1112	#define IEMOPFORM_VEX_RMI_REG (IEMOPFORM_VEX_RMI \| IEMOPFORM_MOD3)
1113	/** VEX+ModR/M: reg, r/m, imm8 (memory). */
1114	#define IEMOPFORM_VEX_RMI_MEM (IEMOPFORM_VEX_RMI \| IEMOPFORM_NOT_MOD3)
1115	/** VEX+ModR/M: r/m, vvvv, reg */
1116	#define IEMOPFORM_VEX_MVR 15
1117	/** VEX+ModR/M: r/m, vvvv, reg (register) */
1118	#define IEMOPFORM_VEX_MVR_REG (IEMOPFORM_VEX_MVR \| IEMOPFORM_MOD3)
1119	/** VEX+ModR/M: r/m, vvvv, reg (memory) */
1120	#define IEMOPFORM_VEX_MVR_MEM (IEMOPFORM_VEX_MVR \| IEMOPFORM_NOT_MOD3)
1121	/** VEX+ModR/M+/n: vvvv, r/m */
1122	#define IEMOPFORM_VEX_VM 16
1123	/** VEX+ModR/M+/n: vvvv, r/m (register) */
1124	#define IEMOPFORM_VEX_VM_REG (IEMOPFORM_VEX_VM \| IEMOPFORM_MOD3)
1125	/** VEX+ModR/M+/n: vvvv, r/m (memory) */
1126	#define IEMOPFORM_VEX_VM_MEM (IEMOPFORM_VEX_VM \| IEMOPFORM_NOT_MOD3)
1127
1128	/** Fixed register instruction, no R/M. */
1129	#define IEMOPFORM_FIXED 32
1130
1131	/** The r/m is a register. */
1132	#define IEMOPFORM_MOD3 RT_BIT_32(8)
1133	/** The r/m is a memory access. */
1134	#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
1135	/** @} */
1136
1137	/** @name IEMOPHINT_XXX - Additional Opcode Hints
1138	* @note These are ORed together with IEMOPFORM_XXX.
1139	* @{ */
1140	/** Ignores the operand size prefix (66h). */
1141	#define IEMOPHINT_IGNORES_OZ_PFX RT_BIT_32(10)
1142	/** Ignores REX.W (aka WIG). */
1143	#define IEMOPHINT_IGNORES_REXW RT_BIT_32(11)
1144	/** Both the operand size prefixes (66h + REX.W) are ignored. */
1145	#define IEMOPHINT_IGNORES_OP_SIZES (IEMOPHINT_IGNORES_OZ_PFX \| IEMOPHINT_IGNORES_REXW)
1146	/** Allowed with the lock prefix. */
1147	#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
1148	/** The VEX.L value is ignored (aka LIG). */
1149	#define IEMOPHINT_VEX_L_IGNORED RT_BIT_32(12)
1150	/** The VEX.L value must be zero (i.e. 128-bit width only). */
1151	#define IEMOPHINT_VEX_L_ZERO RT_BIT_32(13)
1152	/** The VEX.V value must be zero. */
1153	#define IEMOPHINT_VEX_V_ZERO RT_BIT_32(14)
1154
1155	/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
1156	#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
1157	/** @} */
1158
1159	/**
1160	* Possible hardware task switch sources.
1161	*/
1162	typedef enum IEMTASKSWITCH
1163	{
1164	/** Task switch caused by an interrupt/exception. */
1165	IEMTASKSWITCH_INT_XCPT = 1,
1166	/** Task switch caused by a far CALL. */
1167	IEMTASKSWITCH_CALL,
1168	/** Task switch caused by a far JMP. */
1169	IEMTASKSWITCH_JUMP,
1170	/** Task switch caused by an IRET. */
1171	IEMTASKSWITCH_IRET
1172	} IEMTASKSWITCH;
1173	AssertCompileSize(IEMTASKSWITCH, 4);
1174
1175	/**
1176	* Possible CrX load (write) sources.
1177	*/
1178	typedef enum IEMACCESSCRX
1179	{
1180	/** CrX access caused by 'mov crX' instruction. */
1181	IEMACCESSCRX_MOV_CRX,
1182	/** CrX (CR0) write caused by 'lmsw' instruction. */
1183	IEMACCESSCRX_LMSW,
1184	/** CrX (CR0) write caused by 'clts' instruction. */
1185	IEMACCESSCRX_CLTS,
1186	/** CrX (CR0) read caused by 'smsw' instruction. */
1187	IEMACCESSCRX_SMSW
1188	} IEMACCESSCRX;
1189
1190	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1191	/** @name IEM_SLAT_FAIL_XXX - Second-level address translation failure information.
1192	*
1193	* These flags provide further context to SLAT page-walk failures that could not be
1194	* determined by PGM (e.g, PGM is not privy to memory access permissions).
1195	*
1196	* @{
1197	*/
1198	/** Translating a nested-guest linear address failed accessing a nested-guest
1199	* physical address. */
1200	# define IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR RT_BIT_32(0)
1201	/** Translating a nested-guest linear address failed accessing a
1202	* paging-structure entry or updating accessed/dirty bits. */
1203	# define IEM_SLAT_FAIL_LINEAR_TO_PAGE_TABLE RT_BIT_32(1)
1204	/** @} */
1205
1206	DECLCALLBACK(FNPGMPHYSHANDLER) iemVmxApicAccessPageHandler;
1207	# ifndef IN_RING3
1208	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) iemVmxApicAccessPagePfHandler;
1209	# endif
1210	#endif
1211
1212	/**
1213	* Indicates to the verifier that the given flag set is undefined.
1214	*
1215	* Can be invoked again to add more flags.
1216	*
1217	* This is a NOOP if the verifier isn't compiled in.
1218	*
1219	* @note We're temporarily keeping this until code is converted to new
1220	* disassembler style opcode handling.
1221	*/
1222	#define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
1223
1224
1225	/** @def IEM_DECL_IMPL_TYPE
1226	* For typedef'ing an instruction implementation function.
1227	*
1228	* @param a_RetType The return type.
1229	* @param a_Name The name of the type.
1230	* @param a_ArgList The argument list enclosed in parentheses.
1231	*/
1232
1233	/** @def IEM_DECL_IMPL_DEF
1234	* For defining an instruction implementation function.
1235	*
1236	* @param a_RetType The return type.
1237	* @param a_Name The name of the type.
1238	* @param a_ArgList The argument list enclosed in parentheses.
1239	*/
1240
1241	#if defined(__GNUC__) && defined(RT_ARCH_X86)
1242	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1243	__attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
1244	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1245	__attribute__((__fastcall__, __nothrow__)) a_RetType a_Name a_ArgList
1246	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1247	__attribute__((__fastcall__, __nothrow__)) a_RetType a_Name a_ArgList
1248
1249	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
1250	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1251	a_RetType (__fastcall a_Name) a_ArgList
1252	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1253	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
1254	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1255	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
1256
1257	#elif __cplusplus >= 201700 /* P0012R1 support */
1258	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1259	a_RetType (VBOXCALL a_Name) a_ArgList RT_NOEXCEPT
1260	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1261	a_RetType VBOXCALL a_Name a_ArgList RT_NOEXCEPT
1262	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1263	a_RetType VBOXCALL a_Name a_ArgList RT_NOEXCEPT
1264
1265	#else
1266	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1267	a_RetType (VBOXCALL a_Name) a_ArgList
1268	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1269	a_RetType VBOXCALL a_Name a_ArgList
1270	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1271	a_RetType VBOXCALL a_Name a_ArgList
1272
1273	#endif
1274
1275	/** Defined in IEMAllAImplC.cpp but also used by IEMAllAImplA.asm. */
1276	RT_C_DECLS_BEGIN
1277	extern uint8_t const g_afParity[256];
1278	RT_C_DECLS_END
1279
1280
1281	/** @name Arithmetic assignment operations on bytes (binary).
1282	* @{ */
1283	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU8, (uint8_t pu8Dst, uint8_t u8Src, uint32_t pEFlags));
1284	typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
1285	FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
1286	FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
1287	FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
1288	FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
1289	FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
1290	FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
1291	FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
1292	/** @} */
1293
1294	/** @name Arithmetic assignment operations on words (binary).
1295	* @{ */
1296	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU16, (uint16_t pu16Dst, uint16_t u16Src, uint32_t pEFlags));
1297	typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
1298	FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
1299	FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
1300	FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
1301	FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
1302	FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
1303	FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
1304	FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
1305	/** @} */
1306
1307	/** @name Arithmetic assignment operations on double words (binary).
1308	* @{ */
1309	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU32, (uint32_t pu32Dst, uint32_t u32Src, uint32_t pEFlags));
1310	typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
1311	FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
1312	FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
1313	FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
1314	FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
1315	FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
1316	FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
1317	FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
1318	FNIEMAIMPLBINU32 iemAImpl_blsi_u32, iemAImpl_blsi_u32_fallback;
1319	FNIEMAIMPLBINU32 iemAImpl_blsr_u32, iemAImpl_blsr_u32_fallback;
1320	FNIEMAIMPLBINU32 iemAImpl_blsmsk_u32, iemAImpl_blsmsk_u32_fallback;
1321	/** @} */
1322
1323	/** @name Arithmetic assignment operations on quad words (binary).
1324	* @{ */
1325	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU64, (uint64_t pu64Dst, uint64_t u64Src, uint32_t pEFlags));
1326	typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
1327	FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
1328	FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
1329	FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
1330	FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
1331	FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
1332	FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
1333	FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
1334	FNIEMAIMPLBINU64 iemAImpl_blsi_u64, iemAImpl_blsi_u64_fallback;
1335	FNIEMAIMPLBINU64 iemAImpl_blsr_u64, iemAImpl_blsr_u64_fallback;
1336	FNIEMAIMPLBINU64 iemAImpl_blsmsk_u64, iemAImpl_blsmsk_u64_fallback;
1337	/** @} */
1338
1339	/** @name Compare operations (thrown in with the binary ops).
1340	* @{ */
1341	FNIEMAIMPLBINU8 iemAImpl_cmp_u8;
1342	FNIEMAIMPLBINU16 iemAImpl_cmp_u16;
1343	FNIEMAIMPLBINU32 iemAImpl_cmp_u32;
1344	FNIEMAIMPLBINU64 iemAImpl_cmp_u64;
1345	/** @} */
1346
1347	/** @name Test operations (thrown in with the binary ops).
1348	* @{ */
1349	FNIEMAIMPLBINU8 iemAImpl_test_u8;
1350	FNIEMAIMPLBINU16 iemAImpl_test_u16;
1351	FNIEMAIMPLBINU32 iemAImpl_test_u32;
1352	FNIEMAIMPLBINU64 iemAImpl_test_u64;
1353	/** @} */
1354
1355	/** @name Bit operations operations (thrown in with the binary ops).
1356	* @{ */
1357	FNIEMAIMPLBINU16 iemAImpl_bt_u16;
1358	FNIEMAIMPLBINU32 iemAImpl_bt_u32;
1359	FNIEMAIMPLBINU64 iemAImpl_bt_u64;
1360	FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
1361	FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
1362	FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
1363	FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
1364	FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
1365	FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
1366	FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
1367	FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
1368	FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
1369	/** @} */
1370
1371	/** @name Arithmetic three operand operations on double words (binary).
1372	* @{ */
1373	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32, (uint32_t pu32Dst, uint32_t u32Src1, uint32_t u32Src2, uint32_t pEFlags));
1374	typedef FNIEMAIMPLBINVEXU32 *PFNIEMAIMPLBINVEXU32;
1375	FNIEMAIMPLBINVEXU32 iemAImpl_andn_u32, iemAImpl_andn_u32_fallback;
1376	FNIEMAIMPLBINVEXU32 iemAImpl_bextr_u32, iemAImpl_bextr_u32_fallback;
1377	FNIEMAIMPLBINVEXU32 iemAImpl_bzhi_u32, iemAImpl_bzhi_u32_fallback;
1378	/** @} */
1379
1380	/** @name Arithmetic three operand operations on quad words (binary).
1381	* @{ */
1382	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64, (uint64_t pu64Dst, uint64_t u64Src1, uint64_t u64Src2, uint32_t pEFlags));
1383	typedef FNIEMAIMPLBINVEXU64 *PFNIEMAIMPLBINVEXU64;
1384	FNIEMAIMPLBINVEXU64 iemAImpl_andn_u64, iemAImpl_andn_u64_fallback;
1385	FNIEMAIMPLBINVEXU64 iemAImpl_bextr_u64, iemAImpl_bextr_u64_fallback;
1386	FNIEMAIMPLBINVEXU64 iemAImpl_bzhi_u64, iemAImpl_bzhi_u64_fallback;
1387	/** @} */
1388
1389	/** @name Arithmetic three operand operations on double words w/o EFLAGS (binary).
1390	* @{ */
1391	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32NOEFL, (uint32_t *pu32Dst, uint32_t u32Src1, uint32_t u32Src2));
1392	typedef FNIEMAIMPLBINVEXU32NOEFL *PFNIEMAIMPLBINVEXU32NOEFL;
1393	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pdep_u32, iemAImpl_pdep_u32_fallback;
1394	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pext_u32, iemAImpl_pext_u32_fallback;
1395	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_sarx_u32, iemAImpl_sarx_u32_fallback;
1396	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shlx_u32, iemAImpl_shlx_u32_fallback;
1397	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shrx_u32, iemAImpl_shrx_u32_fallback;
1398	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_rorx_u32;
1399	/** @} */
1400
1401	/** @name Arithmetic three operand operations on quad words w/o EFLAGS (binary).
1402	* @{ */
1403	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64NOEFL, (uint64_t *pu64Dst, uint64_t u64Src1, uint64_t u64Src2));
1404	typedef FNIEMAIMPLBINVEXU64NOEFL *PFNIEMAIMPLBINVEXU64NOEFL;
1405	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pdep_u64, iemAImpl_pdep_u64_fallback;
1406	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pext_u64, iemAImpl_pext_u64_fallback;
1407	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_sarx_u64, iemAImpl_sarx_u64_fallback;
1408	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shlx_u64, iemAImpl_shlx_u64_fallback;
1409	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shrx_u64, iemAImpl_shrx_u64_fallback;
1410	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_rorx_u64;
1411	/** @} */
1412
1413	/** @name MULX 32-bit and 64-bit.
1414	* @{ */
1415	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU32, (uint32_t puDst1, uint32_t puDst2, uint32_t uSrc1, uint32_t uSrc2));
1416	typedef FNIEMAIMPLMULXVEXU32 *PFNIEMAIMPLMULXVEXU32;
1417	FNIEMAIMPLMULXVEXU32 iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback;
1418
1419	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU64, (uint64_t puDst1, uint64_t puDst2, uint64_t uSrc1, uint64_t uSrc2));
1420	typedef FNIEMAIMPLMULXVEXU64 *PFNIEMAIMPLMULXVEXU64;
1421	FNIEMAIMPLMULXVEXU64 iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback;
1422	/** @} */
1423
1424
1425	/** @name Exchange memory with register operations.
1426	* @{ */
1427	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_locked, (uint8_t pu8Mem, uint8_t pu8Reg));
1428	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_locked,(uint16_t pu16Mem, uint16_t pu16Reg));
1429	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_locked,(uint32_t pu32Mem, uint32_t pu32Reg));
1430	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_locked,(uint64_t pu64Mem, uint64_t pu64Reg));
1431	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_unlocked, (uint8_t pu8Mem, uint8_t pu8Reg));
1432	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_unlocked,(uint16_t pu16Mem, uint16_t pu16Reg));
1433	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_unlocked,(uint32_t pu32Mem, uint32_t pu32Reg));
1434	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_unlocked,(uint64_t pu64Mem, uint64_t pu64Reg));
1435	/** @} */
1436
1437	/** @name Exchange and add operations.
1438	* @{ */
1439	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1440	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1441	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1442	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1443	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1444	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1445	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1446	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1447	/** @} */
1448
1449	/** @name Compare and exchange.
1450	* @{ */
1451	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1452	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1453	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1454	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1455	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1456	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1457	#if ARCH_BITS == 32
1458	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1459	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1460	#else
1461	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1462	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1463	#endif
1464	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1465	uint32_t *pEFlags));
1466	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1467	uint32_t *pEFlags));
1468	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1469	uint32_t *pEFlags));
1470	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1471	uint32_t *pEFlags));
1472	#ifndef RT_ARCH_ARM64
1473	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
1474	PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
1475	#endif
1476	/** @} */
1477
1478	/** @name Memory ordering
1479	* @{ */
1480	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
1481	typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
1482	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
1483	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
1484	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
1485	#ifndef RT_ARCH_ARM64
1486	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
1487	#endif
1488	/** @} */
1489
1490	/** @name Double precision shifts
1491	* @{ */
1492	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t pEFlags));
1493	typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
1494	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t pEFlags));
1495	typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
1496	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t pEFlags));
1497	typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
1498	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16, iemAImpl_shld_u16_amd, iemAImpl_shld_u16_intel;
1499	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32, iemAImpl_shld_u32_amd, iemAImpl_shld_u32_intel;
1500	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64, iemAImpl_shld_u64_amd, iemAImpl_shld_u64_intel;
1501	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16, iemAImpl_shrd_u16_amd, iemAImpl_shrd_u16_intel;
1502	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32, iemAImpl_shrd_u32_amd, iemAImpl_shrd_u32_intel;
1503	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64, iemAImpl_shrd_u64_amd, iemAImpl_shrd_u64_intel;
1504	/** @} */
1505
1506
1507	/** @name Bit search operations (thrown in with the binary ops).
1508	* @{ */
1509	FNIEMAIMPLBINU16 iemAImpl_bsf_u16, iemAImpl_bsf_u16_amd, iemAImpl_bsf_u16_intel;
1510	FNIEMAIMPLBINU32 iemAImpl_bsf_u32, iemAImpl_bsf_u32_amd, iemAImpl_bsf_u32_intel;
1511	FNIEMAIMPLBINU64 iemAImpl_bsf_u64, iemAImpl_bsf_u64_amd, iemAImpl_bsf_u64_intel;
1512	FNIEMAIMPLBINU16 iemAImpl_bsr_u16, iemAImpl_bsr_u16_amd, iemAImpl_bsr_u16_intel;
1513	FNIEMAIMPLBINU32 iemAImpl_bsr_u32, iemAImpl_bsr_u32_amd, iemAImpl_bsr_u32_intel;
1514	FNIEMAIMPLBINU64 iemAImpl_bsr_u64, iemAImpl_bsr_u64_amd, iemAImpl_bsr_u64_intel;
1515	FNIEMAIMPLBINU16 iemAImpl_lzcnt_u16, iemAImpl_lzcnt_u16_amd, iemAImpl_lzcnt_u16_intel;
1516	FNIEMAIMPLBINU32 iemAImpl_lzcnt_u32, iemAImpl_lzcnt_u32_amd, iemAImpl_lzcnt_u32_intel;
1517	FNIEMAIMPLBINU64 iemAImpl_lzcnt_u64, iemAImpl_lzcnt_u64_amd, iemAImpl_lzcnt_u64_intel;
1518	FNIEMAIMPLBINU16 iemAImpl_tzcnt_u16, iemAImpl_tzcnt_u16_amd, iemAImpl_tzcnt_u16_intel;
1519	FNIEMAIMPLBINU32 iemAImpl_tzcnt_u32, iemAImpl_tzcnt_u32_amd, iemAImpl_tzcnt_u32_intel;
1520	FNIEMAIMPLBINU64 iemAImpl_tzcnt_u64, iemAImpl_tzcnt_u64_amd, iemAImpl_tzcnt_u64_intel;
1521	FNIEMAIMPLBINU16 iemAImpl_popcnt_u16, iemAImpl_popcnt_u16_fallback;
1522	FNIEMAIMPLBINU32 iemAImpl_popcnt_u32, iemAImpl_popcnt_u32_fallback;
1523	FNIEMAIMPLBINU64 iemAImpl_popcnt_u64, iemAImpl_popcnt_u64_fallback;
1524	/** @} */
1525
1526	/** @name Signed multiplication operations (thrown in with the binary ops).
1527	* @{ */
1528	FNIEMAIMPLBINU16 iemAImpl_imul_two_u16, iemAImpl_imul_two_u16_amd, iemAImpl_imul_two_u16_intel;
1529	FNIEMAIMPLBINU32 iemAImpl_imul_two_u32, iemAImpl_imul_two_u32_amd, iemAImpl_imul_two_u32_intel;
1530	FNIEMAIMPLBINU64 iemAImpl_imul_two_u64, iemAImpl_imul_two_u64_amd, iemAImpl_imul_two_u64_intel;
1531	/** @} */
1532
1533	/** @name Arithmetic assignment operations on bytes (unary).
1534	* @{ */
1535	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t pu8Dst, uint32_t pEFlags));
1536	typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
1537	FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
1538	FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
1539	FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
1540	FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
1541	/** @} */
1542
1543	/** @name Arithmetic assignment operations on words (unary).
1544	* @{ */
1545	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t pu16Dst, uint32_t pEFlags));
1546	typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
1547	FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
1548	FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
1549	FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
1550	FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
1551	/** @} */
1552
1553	/** @name Arithmetic assignment operations on double words (unary).
1554	* @{ */
1555	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t pu32Dst, uint32_t pEFlags));
1556	typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
1557	FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
1558	FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
1559	FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
1560	FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
1561	/** @} */
1562
1563	/** @name Arithmetic assignment operations on quad words (unary).
1564	* @{ */
1565	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t pu64Dst, uint32_t pEFlags));
1566	typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
1567	FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
1568	FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
1569	FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
1570	FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
1571	/** @} */
1572
1573
1574	/** @name Shift operations on bytes (Group 2).
1575	* @{ */
1576	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU8,(uint8_t pu8Dst, uint8_t cShift, uint32_t pEFlags));
1577	typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
1578	FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8, iemAImpl_rol_u8_amd, iemAImpl_rol_u8_intel;
1579	FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8, iemAImpl_ror_u8_amd, iemAImpl_ror_u8_intel;
1580	FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8, iemAImpl_rcl_u8_amd, iemAImpl_rcl_u8_intel;
1581	FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8, iemAImpl_rcr_u8_amd, iemAImpl_rcr_u8_intel;
1582	FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8, iemAImpl_shl_u8_amd, iemAImpl_shl_u8_intel;
1583	FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8, iemAImpl_shr_u8_amd, iemAImpl_shr_u8_intel;
1584	FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8, iemAImpl_sar_u8_amd, iemAImpl_sar_u8_intel;
1585	/** @} */
1586
1587	/** @name Shift operations on words (Group 2).
1588	* @{ */
1589	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU16,(uint16_t pu16Dst, uint8_t cShift, uint32_t pEFlags));
1590	typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
1591	FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16, iemAImpl_rol_u16_amd, iemAImpl_rol_u16_intel;
1592	FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16, iemAImpl_ror_u16_amd, iemAImpl_ror_u16_intel;
1593	FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16, iemAImpl_rcl_u16_amd, iemAImpl_rcl_u16_intel;
1594	FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16, iemAImpl_rcr_u16_amd, iemAImpl_rcr_u16_intel;
1595	FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16, iemAImpl_shl_u16_amd, iemAImpl_shl_u16_intel;
1596	FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16, iemAImpl_shr_u16_amd, iemAImpl_shr_u16_intel;
1597	FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16, iemAImpl_sar_u16_amd, iemAImpl_sar_u16_intel;
1598	/** @} */
1599
1600	/** @name Shift operations on double words (Group 2).
1601	* @{ */
1602	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU32,(uint32_t pu32Dst, uint8_t cShift, uint32_t pEFlags));
1603	typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
1604	FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32, iemAImpl_rol_u32_amd, iemAImpl_rol_u32_intel;
1605	FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32, iemAImpl_ror_u32_amd, iemAImpl_ror_u32_intel;
1606	FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32, iemAImpl_rcl_u32_amd, iemAImpl_rcl_u32_intel;
1607	FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32, iemAImpl_rcr_u32_amd, iemAImpl_rcr_u32_intel;
1608	FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32, iemAImpl_shl_u32_amd, iemAImpl_shl_u32_intel;
1609	FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32, iemAImpl_shr_u32_amd, iemAImpl_shr_u32_intel;
1610	FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32, iemAImpl_sar_u32_amd, iemAImpl_sar_u32_intel;
1611	/** @} */
1612
1613	/** @name Shift operations on words (Group 2).
1614	* @{ */
1615	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU64,(uint64_t pu64Dst, uint8_t cShift, uint32_t pEFlags));
1616	typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
1617	FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64, iemAImpl_rol_u64_amd, iemAImpl_rol_u64_intel;
1618	FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64, iemAImpl_ror_u64_amd, iemAImpl_ror_u64_intel;
1619	FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64, iemAImpl_rcl_u64_amd, iemAImpl_rcl_u64_intel;
1620	FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64, iemAImpl_rcr_u64_amd, iemAImpl_rcr_u64_intel;
1621	FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64, iemAImpl_shl_u64_amd, iemAImpl_shl_u64_intel;
1622	FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64, iemAImpl_shr_u64_amd, iemAImpl_shr_u64_intel;
1623	FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64, iemAImpl_sar_u64_amd, iemAImpl_sar_u64_intel;
1624	/** @} */
1625
1626	/** @name Multiplication and division operations.
1627	* @{ */
1628	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t pu16AX, uint8_t u8FactorDivisor, uint32_t pEFlags));
1629	typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
1630	FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_mul_u8_amd, iemAImpl_mul_u8_intel;
1631	FNIEMAIMPLMULDIVU8 iemAImpl_imul_u8, iemAImpl_imul_u8_amd, iemAImpl_imul_u8_intel;
1632	FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_div_u8_amd, iemAImpl_div_u8_intel;
1633	FNIEMAIMPLMULDIVU8 iemAImpl_idiv_u8, iemAImpl_idiv_u8_amd, iemAImpl_idiv_u8_intel;
1634
1635	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t pu16AX, uint16_t pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
1636	typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
1637	FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_mul_u16_amd, iemAImpl_mul_u16_intel;
1638	FNIEMAIMPLMULDIVU16 iemAImpl_imul_u16, iemAImpl_imul_u16_amd, iemAImpl_imul_u16_intel;
1639	FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_div_u16_amd, iemAImpl_div_u16_intel;
1640	FNIEMAIMPLMULDIVU16 iemAImpl_idiv_u16, iemAImpl_idiv_u16_amd, iemAImpl_idiv_u16_intel;
1641
1642	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t pu32EAX, uint32_t pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
1643	typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
1644	FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_mul_u32_amd, iemAImpl_mul_u32_intel;
1645	FNIEMAIMPLMULDIVU32 iemAImpl_imul_u32, iemAImpl_imul_u32_amd, iemAImpl_imul_u32_intel;
1646	FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_div_u32_amd, iemAImpl_div_u32_intel;
1647	FNIEMAIMPLMULDIVU32 iemAImpl_idiv_u32, iemAImpl_idiv_u32_amd, iemAImpl_idiv_u32_intel;
1648
1649	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t pu64RAX, uint64_t pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
1650	typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
1651	FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_mul_u64_amd, iemAImpl_mul_u64_intel;
1652	FNIEMAIMPLMULDIVU64 iemAImpl_imul_u64, iemAImpl_imul_u64_amd, iemAImpl_imul_u64_intel;
1653	FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_div_u64_amd, iemAImpl_div_u64_intel;
1654	FNIEMAIMPLMULDIVU64 iemAImpl_idiv_u64, iemAImpl_idiv_u64_amd, iemAImpl_idiv_u64_intel;
1655	/** @} */
1656
1657	/** @name Byte Swap.
1658	* @{ */
1659	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t pu32Dst)); / Yes, 32-bit register access. */
1660	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
1661	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
1662	/** @} */
1663
1664	/** @name Misc.
1665	* @{ */
1666	FNIEMAIMPLBINU16 iemAImpl_arpl;
1667	/** @} */
1668
1669	/** @name RDRAND and RDSEED
1670	* @{ */
1671	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU16,(uint16_t puDst, uint32_t pEFlags));
1672	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU32,(uint32_t puDst, uint32_t pEFlags));
1673	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU64,(uint64_t puDst, uint32_t pEFlags));
1674	typedef FNIEMAIMPLRDRANDSEEDU16 *FNIEMAIMPLPRDRANDSEEDU16;
1675	typedef FNIEMAIMPLRDRANDSEEDU32 *FNIEMAIMPLPRDRANDSEEDU32;
1676	typedef FNIEMAIMPLRDRANDSEEDU64 *FNIEMAIMPLPRDRANDSEEDU64;
1677
1678	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdrand_u16, iemAImpl_rdrand_u16_fallback;
1679	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdrand_u32, iemAImpl_rdrand_u32_fallback;
1680	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdrand_u64, iemAImpl_rdrand_u64_fallback;
1681	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdseed_u16, iemAImpl_rdseed_u16_fallback;
1682	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdseed_u32, iemAImpl_rdseed_u32_fallback;
1683	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdseed_u64, iemAImpl_rdseed_u64_fallback;
1684	/** @} */
1685
1686	/** @name ADOX and ADCX
1687	* @{ */
1688	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLADXU32,(uint32_t puDst, uint32_t pfEFlags, uint32_t uSrc));
1689	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLADXU64,(uint64_t puDst, uint32_t pfEFlags, uint64_t uSrc));
1690	typedef FNIEMAIMPLADXU32 *PFNIEMAIMPLADXU32;
1691	typedef FNIEMAIMPLADXU64 *PFNIEMAIMPLADXU64;
1692
1693	FNIEMAIMPLADXU32 iemAImpl_adcx_u32, iemAImpl_adcx_u32_fallback;
1694	FNIEMAIMPLADXU64 iemAImpl_adcx_u64, iemAImpl_adcx_u64_fallback;
1695	FNIEMAIMPLADXU32 iemAImpl_adox_u32, iemAImpl_adox_u32_fallback;
1696	FNIEMAIMPLADXU64 iemAImpl_adox_u64, iemAImpl_adox_u64_fallback;
1697	/** @} */
1698
1699	/** @name FPU operations taking a 32-bit float argument
1700	* @{ */
1701	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1702	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1703	typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
1704
1705	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1706	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1707	typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
1708
1709	FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
1710	FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
1711	FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
1712	FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
1713	FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
1714	FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
1715	FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
1716
1717	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
1718	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1719	PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
1720	/** @} */
1721
1722	/** @name FPU operations taking a 64-bit float argument
1723	* @{ */
1724	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1725	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1726	typedef FNIEMAIMPLFPUR64FSW *PFNIEMAIMPLFPUR64FSW;
1727
1728	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1729	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1730	typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
1731
1732	FNIEMAIMPLFPUR64FSW iemAImpl_fcom_r80_by_r64;
1733	FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
1734	FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
1735	FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
1736	FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
1737	FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
1738	FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
1739
1740	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
1741	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1742	PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
1743	/** @} */
1744
1745	/** @name FPU operations taking a 80-bit float argument
1746	* @{ */
1747	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1748	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1749	typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
1750	FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
1751	FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
1752	FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
1753	FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
1754	FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
1755	FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
1756	FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
1757	FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
1758	FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
1759
1760	FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80, iemAImpl_fpatan_r80_by_r80_amd, iemAImpl_fpatan_r80_by_r80_intel;
1761	FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80, iemAImpl_fyl2x_r80_by_r80_amd, iemAImpl_fyl2x_r80_by_r80_intel;
1762	FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80, iemAImpl_fyl2xp1_r80_by_r80_amd, iemAImpl_fyl2xp1_r80_by_r80_intel;
1763
1764	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1765	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1766	typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
1767	FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
1768	FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
1769
1770	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1771	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1772	typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
1773	FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
1774	FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
1775
1776	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
1777	typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
1778	FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
1779	FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
1780	FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80, iemAImpl_f2xm1_r80_amd, iemAImpl_f2xm1_r80_intel;
1781	FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
1782	FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
1783	FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80, iemAImpl_fsin_r80_amd, iemAImpl_fsin_r80_intel;
1784	FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80, iemAImpl_fcos_r80_amd, iemAImpl_fcos_r80_intel;
1785
1786	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
1787	typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
1788	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
1789	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
1790
1791	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
1792	typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
1793	FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
1794	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
1795	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
1796	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
1797	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
1798	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
1799	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
1800
1801	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
1802	PCRTFLOAT80U pr80Val));
1803	typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
1804	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80, iemAImpl_fptan_r80_r80_amd, iemAImpl_fptan_r80_r80_intel;
1805	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
1806	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80, iemAImpl_fsincos_r80_r80_amd, iemAImpl_fsincos_r80_r80_intel;
1807
1808	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
1809	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1810	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
1811
1812	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_d80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTPBCD80U pd80Val));
1813	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_d80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1814	PRTPBCD80U pd80Dst, PCRTFLOAT80U pr80Src));
1815
1816	/** @} */
1817
1818	/** @name FPU operations taking a 16-bit signed integer argument
1819	* @{ */
1820	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1821	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
1822	typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
1823	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI16,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
1824	int16_t *pi16Dst, PCRTFLOAT80U pr80Src));
1825	typedef FNIEMAIMPLFPUSTR80TOI16 *PFNIEMAIMPLFPUSTR80TOI16;
1826
1827	FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
1828	FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
1829	FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
1830	FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
1831	FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
1832	FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
1833
1834	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1835	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
1836	typedef FNIEMAIMPLFPUI16FSW *PFNIEMAIMPLFPUI16FSW;
1837	FNIEMAIMPLFPUI16FSW iemAImpl_ficom_r80_by_i16;
1838
1839	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
1840	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fist_r80_to_i16;
1841	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fistt_r80_to_i16, iemAImpl_fistt_r80_to_i16_amd, iemAImpl_fistt_r80_to_i16_intel;
1842	/** @} */
1843
1844	/** @name FPU operations taking a 32-bit signed integer argument
1845	* @{ */
1846	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1847	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
1848	typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
1849	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI32,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
1850	int32_t *pi32Dst, PCRTFLOAT80U pr80Src));
1851	typedef FNIEMAIMPLFPUSTR80TOI32 *PFNIEMAIMPLFPUSTR80TOI32;
1852
1853	FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
1854	FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
1855	FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
1856	FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
1857	FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
1858	FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
1859
1860	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1861	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
1862	typedef FNIEMAIMPLFPUI32FSW *PFNIEMAIMPLFPUI32FSW;
1863	FNIEMAIMPLFPUI32FSW iemAImpl_ficom_r80_by_i32;
1864
1865	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
1866	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fist_r80_to_i32;
1867	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fistt_r80_to_i32;
1868	/** @} */
1869
1870	/** @name FPU operations taking a 64-bit signed integer argument
1871	* @{ */
1872	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI64,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
1873	int64_t *pi64Dst, PCRTFLOAT80U pr80Src));
1874	typedef FNIEMAIMPLFPUSTR80TOI64 *PFNIEMAIMPLFPUSTR80TOI64;
1875
1876	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
1877	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fist_r80_to_i64;
1878	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fistt_r80_to_i64;
1879	/** @} */
1880
1881
1882	/** Temporary type representing a 256-bit vector register. */
1883	typedef struct { uint64_t au64[4]; } IEMVMM256;
1884	/** Temporary type pointing to a 256-bit vector register. */
1885	typedef IEMVMM256 *PIEMVMM256;
1886	/** Temporary type pointing to a const 256-bit vector register. */
1887	typedef IEMVMM256 *PCIEMVMM256;
1888
1889
1890	/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
1891	* @{ */
1892	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t puDst, uint64_t const puSrc));
1893	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
1894	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U128,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
1895	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
1896	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U128,(PX86XSAVEAREA pExtState, PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
1897	typedef FNIEMAIMPLMEDIAF3U128 *PFNIEMAIMPLMEDIAF3U128;
1898	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U256,(PX86XSAVEAREA pExtState, PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
1899	typedef FNIEMAIMPLMEDIAF3U256 *PFNIEMAIMPLMEDIAF3U256;
1900	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U64,(uint64_t puDst, uint64_t const puSrc));
1901	typedef FNIEMAIMPLMEDIAOPTF2U64 *PFNIEMAIMPLMEDIAOPTF2U64;
1902	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128,(PRTUINT128U puDst, PCRTUINT128U puSrc));
1903	typedef FNIEMAIMPLMEDIAOPTF2U128 *PFNIEMAIMPLMEDIAOPTF2U128;
1904	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
1905	typedef FNIEMAIMPLMEDIAOPTF3U128 *PFNIEMAIMPLMEDIAOPTF3U128;
1906	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
1907	typedef FNIEMAIMPLMEDIAOPTF3U256 *PFNIEMAIMPLMEDIAOPTF3U256;
1908	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256,(PRTUINT256U puDst, PCRTUINT256U puSrc));
1909	typedef FNIEMAIMPLMEDIAOPTF2U256 *PFNIEMAIMPLMEDIAOPTF2U256;
1910	FNIEMAIMPLMEDIAF2U64 iemAImpl_pshufb_u64, iemAImpl_pshufb_u64_fallback;
1911	FNIEMAIMPLMEDIAF2U64 iemAImpl_pand_u64, iemAImpl_pandn_u64, iemAImpl_por_u64, iemAImpl_pxor_u64;
1912	FNIEMAIMPLMEDIAF2U64 iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
1913	FNIEMAIMPLMEDIAF2U64 iemAImpl_pcmpgtb_u64, iemAImpl_pcmpgtw_u64, iemAImpl_pcmpgtd_u64;
1914	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddb_u64, iemAImpl_paddsb_u64, iemAImpl_paddusb_u64;
1915	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddw_u64, iemAImpl_paddsw_u64, iemAImpl_paddusw_u64;
1916	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddd_u64;
1917	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddq_u64;
1918	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubb_u64, iemAImpl_psubsb_u64, iemAImpl_psubusb_u64;
1919	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubw_u64, iemAImpl_psubsw_u64, iemAImpl_psubusw_u64;
1920	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubd_u64;
1921	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubq_u64;
1922	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmaddwd_u64;
1923	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmullw_u64, iemAImpl_pmulhw_u64;
1924	FNIEMAIMPLMEDIAF2U64 iemAImpl_pminub_u64, iemAImpl_pmaxub_u64;
1925	FNIEMAIMPLMEDIAF2U64 iemAImpl_pminsw_u64, iemAImpl_pmaxsw_u64;
1926	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsb_u64, iemAImpl_pabsb_u64_fallback;
1927	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsw_u64, iemAImpl_pabsw_u64_fallback;
1928	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsd_u64, iemAImpl_pabsd_u64_fallback;
1929	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignb_u64, iemAImpl_psignb_u64_fallback;
1930	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignw_u64, iemAImpl_psignw_u64_fallback;
1931	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignd_u64, iemAImpl_psignd_u64_fallback;
1932	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddw_u64, iemAImpl_phaddw_u64_fallback;
1933	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddd_u64, iemAImpl_phaddd_u64_fallback;
1934	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubw_u64, iemAImpl_phsubw_u64_fallback;
1935	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubd_u64, iemAImpl_phsubd_u64_fallback;
1936	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddsw_u64, iemAImpl_phaddsw_u64_fallback;
1937	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubsw_u64, iemAImpl_phsubsw_u64_fallback;
1938	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmaddubsw_u64, iemAImpl_pmaddubsw_u64_fallback;
1939	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmulhrsw_u64, iemAImpl_pmulhrsw_u64_fallback;
1940	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmuludq_u64;
1941	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllw_u64, iemAImpl_psrlw_u64, iemAImpl_psraw_u64;
1942	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pslld_u64, iemAImpl_psrld_u64, iemAImpl_psrad_u64;
1943	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllq_u64, iemAImpl_psrlq_u64;
1944	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packsswb_u64, iemAImpl_packuswb_u64;
1945	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packssdw_u64;
1946	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhuw_u64;
1947	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pavgb_u64, iemAImpl_pavgw_u64;
1948	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psadbw_u64;
1949
1950	FNIEMAIMPLMEDIAF2U128 iemAImpl_pshufb_u128, iemAImpl_pshufb_u128_fallback;
1951	FNIEMAIMPLMEDIAF2U128 iemAImpl_pand_u128, iemAImpl_pandn_u128, iemAImpl_por_u128, iemAImpl_pxor_u128;
1952	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
1953	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpeqq_u128, iemAImpl_pcmpeqq_u128_fallback;
1954	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpgtb_u128, iemAImpl_pcmpgtw_u128, iemAImpl_pcmpgtd_u128;
1955	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpgtq_u128, iemAImpl_pcmpgtq_u128_fallback;
1956	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddb_u128, iemAImpl_paddsb_u128, iemAImpl_paddusb_u128;
1957	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddw_u128, iemAImpl_paddsw_u128, iemAImpl_paddusw_u128;
1958	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddd_u128;
1959	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddq_u128;
1960	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubb_u128, iemAImpl_psubsb_u128, iemAImpl_psubusb_u128;
1961	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubw_u128, iemAImpl_psubsw_u128, iemAImpl_psubusw_u128;
1962	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubd_u128;
1963	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubq_u128;
1964	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmullw_u128, iemAImpl_pmullw_u128_fallback;
1965	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulhw_u128;
1966	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulld_u128, iemAImpl_pmulld_u128_fallback;
1967	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaddwd_u128;
1968	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminub_u128;
1969	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminud_u128, iemAImpl_pminud_u128_fallback;
1970	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminuw_u128, iemAImpl_pminuw_u128_fallback;
1971	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsb_u128, iemAImpl_pminsb_u128_fallback;
1972	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsd_u128, iemAImpl_pminsd_u128_fallback;
1973	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsw_u128, iemAImpl_pminsw_u128_fallback;
1974	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxub_u128;
1975	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxud_u128, iemAImpl_pmaxud_u128_fallback;
1976	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxuw_u128, iemAImpl_pmaxuw_u128_fallback;
1977	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsb_u128, iemAImpl_pmaxsb_u128_fallback;
1978	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsw_u128;
1979	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsd_u128, iemAImpl_pmaxsd_u128_fallback;
1980	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsb_u128, iemAImpl_pabsb_u128_fallback;
1981	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsw_u128, iemAImpl_pabsw_u128_fallback;
1982	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsd_u128, iemAImpl_pabsd_u128_fallback;
1983	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignb_u128, iemAImpl_psignb_u128_fallback;
1984	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignw_u128, iemAImpl_psignw_u128_fallback;
1985	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignd_u128, iemAImpl_psignd_u128_fallback;
1986	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddw_u128, iemAImpl_phaddw_u128_fallback;
1987	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddd_u128, iemAImpl_phaddd_u128_fallback;
1988	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubw_u128, iemAImpl_phsubw_u128_fallback;
1989	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubd_u128, iemAImpl_phsubd_u128_fallback;
1990	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddsw_u128, iemAImpl_phaddsw_u128_fallback;
1991	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubsw_u128, iemAImpl_phsubsw_u128_fallback;
1992	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaddubsw_u128, iemAImpl_pmaddubsw_u128_fallback;
1993	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulhrsw_u128, iemAImpl_pmulhrsw_u128_fallback;
1994	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmuludq_u128;
1995	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packsswb_u128, iemAImpl_packuswb_u128;
1996	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packssdw_u128, iemAImpl_packusdw_u128;
1997	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllw_u128, iemAImpl_psrlw_u128, iemAImpl_psraw_u128;
1998	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pslld_u128, iemAImpl_psrld_u128, iemAImpl_psrad_u128;
1999	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllq_u128, iemAImpl_psrlq_u128;
2000	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhuw_u128;
2001	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pavgb_u128, iemAImpl_pavgw_u128;
2002	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psadbw_u128;
2003	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuldq_u128, iemAImpl_pmuldq_u128_fallback;
2004	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpcklps_u128, iemAImpl_unpcklpd_u128;
2005	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpckhps_u128, iemAImpl_unpckhpd_u128;
2006	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phminposuw_u128, iemAImpl_phminposuw_u128_fallback;
2007
2008	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpshufb_u128, iemAImpl_vpshufb_u128_fallback;
2009	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpand_u128, iemAImpl_vpand_u128_fallback;
2010	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpandn_u128, iemAImpl_vpandn_u128_fallback;
2011	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpor_u128, iemAImpl_vpor_u128_fallback;
2012	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpxor_u128, iemAImpl_vpxor_u128_fallback;
2013	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqb_u128, iemAImpl_vpcmpeqb_u128_fallback;
2014	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqw_u128, iemAImpl_vpcmpeqw_u128_fallback;
2015	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqd_u128, iemAImpl_vpcmpeqd_u128_fallback;
2016	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqq_u128, iemAImpl_vpcmpeqq_u128_fallback;
2017	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtb_u128, iemAImpl_vpcmpgtb_u128_fallback;
2018	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtw_u128, iemAImpl_vpcmpgtw_u128_fallback;
2019	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtd_u128, iemAImpl_vpcmpgtd_u128_fallback;
2020	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtq_u128, iemAImpl_vpcmpgtq_u128_fallback;
2021	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddb_u128, iemAImpl_vpaddb_u128_fallback;
2022	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddw_u128, iemAImpl_vpaddw_u128_fallback;
2023	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddd_u128, iemAImpl_vpaddd_u128_fallback;
2024	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddq_u128, iemAImpl_vpaddq_u128_fallback;
2025	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubb_u128, iemAImpl_vpsubb_u128_fallback;
2026	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubw_u128, iemAImpl_vpsubw_u128_fallback;
2027	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubd_u128, iemAImpl_vpsubd_u128_fallback;
2028	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubq_u128, iemAImpl_vpsubq_u128_fallback;
2029	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminub_u128, iemAImpl_vpminub_u128_fallback;
2030	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminuw_u128, iemAImpl_vpminuw_u128_fallback;
2031	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminud_u128, iemAImpl_vpminud_u128_fallback;
2032	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsb_u128, iemAImpl_vpminsb_u128_fallback;
2033	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsw_u128, iemAImpl_vpminsw_u128_fallback;
2034	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsd_u128, iemAImpl_vpminsd_u128_fallback;
2035	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxub_u128, iemAImpl_vpmaxub_u128_fallback;
2036	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxuw_u128, iemAImpl_vpmaxuw_u128_fallback;
2037	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxud_u128, iemAImpl_vpmaxud_u128_fallback;
2038	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsb_u128, iemAImpl_vpmaxsb_u128_fallback;
2039	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsw_u128, iemAImpl_vpmaxsw_u128_fallback;
2040	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsd_u128, iemAImpl_vpmaxsd_u128_fallback;
2041	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpacksswb_u128, iemAImpl_vpacksswb_u128_fallback;
2042	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackssdw_u128, iemAImpl_vpackssdw_u128_fallback;
2043	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackuswb_u128, iemAImpl_vpackuswb_u128_fallback;
2044	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackusdw_u128, iemAImpl_vpackusdw_u128_fallback;
2045	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmullw_u128, iemAImpl_vpmullw_u128_fallback;
2046	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulld_u128, iemAImpl_vpmulld_u128_fallback;
2047	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhw_u128, iemAImpl_vpmulhw_u128_fallback;
2048	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhuw_u128, iemAImpl_vpmulhuw_u128_fallback;
2049	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgb_u128, iemAImpl_vpavgb_u128_fallback;
2050	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgw_u128, iemAImpl_vpavgw_u128_fallback;
2051	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignb_u128, iemAImpl_vpsignb_u128_fallback;
2052	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignw_u128, iemAImpl_vpsignw_u128_fallback;
2053	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignd_u128, iemAImpl_vpsignd_u128_fallback;
2054	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddw_u128, iemAImpl_vphaddw_u128_fallback;
2055	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddd_u128, iemAImpl_vphaddd_u128_fallback;
2056	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubw_u128, iemAImpl_vphsubw_u128_fallback;
2057	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubd_u128, iemAImpl_vphsubd_u128_fallback;
2058	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddsw_u128, iemAImpl_vphaddsw_u128_fallback;
2059	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubsw_u128, iemAImpl_vphsubsw_u128_fallback;
2060	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddubsw_u128, iemAImpl_vpmaddubsw_u128_fallback;
2061	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhrsw_u128, iemAImpl_vpmulhrsw_u128_fallback;
2062	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsadbw_u128, iemAImpl_vpsadbw_u128_fallback;
2063	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuldq_u128, iemAImpl_vpmuldq_u128_fallback;
2064	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuludq_u128, iemAImpl_vpmuludq_u128_fallback;
2065
2066	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsb_u128, iemAImpl_vpabsb_u128_fallback;
2067	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsw_u128, iemAImpl_vpabsd_u128_fallback;
2068	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsd_u128, iemAImpl_vpabsw_u128_fallback;
2069	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vphminposuw_u128, iemAImpl_vphminposuw_u128_fallback;
2070
2071	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpshufb_u256, iemAImpl_vpshufb_u256_fallback;
2072	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpand_u256, iemAImpl_vpand_u256_fallback;
2073	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpandn_u256, iemAImpl_vpandn_u256_fallback;
2074	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpor_u256, iemAImpl_vpor_u256_fallback;
2075	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpxor_u256, iemAImpl_vpxor_u256_fallback;
2076	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqb_u256, iemAImpl_vpcmpeqb_u256_fallback;
2077	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqw_u256, iemAImpl_vpcmpeqw_u256_fallback;
2078	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqd_u256, iemAImpl_vpcmpeqd_u256_fallback;
2079	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqq_u256, iemAImpl_vpcmpeqq_u256_fallback;
2080	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtb_u256, iemAImpl_vpcmpgtb_u256_fallback;
2081	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtw_u256, iemAImpl_vpcmpgtw_u256_fallback;
2082	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtd_u256, iemAImpl_vpcmpgtd_u256_fallback;
2083	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtq_u256, iemAImpl_vpcmpgtq_u256_fallback;
2084	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddb_u256, iemAImpl_vpaddb_u256_fallback;
2085	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddw_u256, iemAImpl_vpaddw_u256_fallback;
2086	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddd_u256, iemAImpl_vpaddd_u256_fallback;
2087	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddq_u256, iemAImpl_vpaddq_u256_fallback;
2088	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubb_u256, iemAImpl_vpsubb_u256_fallback;
2089	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubw_u256, iemAImpl_vpsubw_u256_fallback;
2090	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubd_u256, iemAImpl_vpsubd_u256_fallback;
2091	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubq_u256, iemAImpl_vpsubq_u256_fallback;
2092	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminub_u256, iemAImpl_vpminub_u256_fallback;
2093	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminuw_u256, iemAImpl_vpminuw_u256_fallback;
2094	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminud_u256, iemAImpl_vpminud_u256_fallback;
2095	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsb_u256, iemAImpl_vpminsb_u256_fallback;
2096	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsw_u256, iemAImpl_vpminsw_u256_fallback;
2097	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsd_u256, iemAImpl_vpminsd_u256_fallback;
2098	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxub_u256, iemAImpl_vpmaxub_u256_fallback;
2099	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxuw_u256, iemAImpl_vpmaxuw_u256_fallback;
2100	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxud_u256, iemAImpl_vpmaxud_u256_fallback;
2101	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsb_u256, iemAImpl_vpmaxsb_u256_fallback;
2102	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsw_u256, iemAImpl_vpmaxsw_u256_fallback;
2103	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsd_u256, iemAImpl_vpmaxsd_u256_fallback;
2104	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpacksswb_u256, iemAImpl_vpacksswb_u256_fallback;
2105	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackssdw_u256, iemAImpl_vpackssdw_u256_fallback;
2106	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackuswb_u256, iemAImpl_vpackuswb_u256_fallback;
2107	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackusdw_u256, iemAImpl_vpackusdw_u256_fallback;
2108	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmullw_u256, iemAImpl_vpmullw_u256_fallback;
2109	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulld_u256, iemAImpl_vpmulld_u256_fallback;
2110	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhw_u256, iemAImpl_vpmulhw_u256_fallback;
2111	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhuw_u256, iemAImpl_vpmulhuw_u256_fallback;
2112	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgb_u256, iemAImpl_vpavgb_u256_fallback;
2113	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgw_u256, iemAImpl_vpavgw_u256_fallback;
2114	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignb_u256, iemAImpl_vpsignb_u256_fallback;
2115	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignw_u256, iemAImpl_vpsignw_u256_fallback;
2116	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignd_u256, iemAImpl_vpsignd_u256_fallback;
2117	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddw_u256, iemAImpl_vphaddw_u256_fallback;
2118	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddd_u256, iemAImpl_vphaddd_u256_fallback;
2119	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubw_u256, iemAImpl_vphsubw_u256_fallback;
2120	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubd_u256, iemAImpl_vphsubd_u256_fallback;
2121	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddsw_u256, iemAImpl_vphaddsw_u256_fallback;
2122	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubsw_u256, iemAImpl_vphsubsw_u256_fallback;
2123	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddubsw_u256, iemAImpl_vpmaddubsw_u256_fallback;
2124	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhrsw_u256, iemAImpl_vpmulhrsw_u256_fallback;
2125	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsadbw_u256, iemAImpl_vpsadbw_u256_fallback;
2126	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuldq_u256, iemAImpl_vpmuldq_u256_fallback;
2127	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuludq_u256, iemAImpl_vpmuludq_u256_fallback;
2128
2129	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsb_u256, iemAImpl_vpabsb_u256_fallback;
2130	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsw_u256, iemAImpl_vpabsw_u256_fallback;
2131	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsd_u256, iemAImpl_vpabsd_u256_fallback;
2132	/** @} */
2133
2134	/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
2135	* @{ */
2136	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
2137	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
2138	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpcklbw_u128, iemAImpl_vpunpcklbw_u128_fallback,
2139	iemAImpl_vpunpcklwd_u128, iemAImpl_vpunpcklwd_u128_fallback,
2140	iemAImpl_vpunpckldq_u128, iemAImpl_vpunpckldq_u128_fallback,
2141	iemAImpl_vpunpcklqdq_u128, iemAImpl_vpunpcklqdq_u128_fallback,
2142	iemAImpl_vunpcklps_u128, iemAImpl_vunpcklps_u128_fallback,
2143	iemAImpl_vunpcklpd_u128, iemAImpl_vunpcklpd_u128_fallback,
2144	iemAImpl_vunpckhps_u128, iemAImpl_vunpckhps_u128_fallback,
2145	iemAImpl_vunpckhpd_u128, iemAImpl_vunpckhpd_u128_fallback;
2146
2147	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpcklbw_u256, iemAImpl_vpunpcklbw_u256_fallback,
2148	iemAImpl_vpunpcklwd_u256, iemAImpl_vpunpcklwd_u256_fallback,
2149	iemAImpl_vpunpckldq_u256, iemAImpl_vpunpckldq_u256_fallback,
2150	iemAImpl_vpunpcklqdq_u256, iemAImpl_vpunpcklqdq_u256_fallback,
2151	iemAImpl_vunpcklps_u256, iemAImpl_vunpcklps_u256_fallback,
2152	iemAImpl_vunpcklpd_u256, iemAImpl_vunpcklpd_u256_fallback,
2153	iemAImpl_vunpckhps_u256, iemAImpl_vunpckhps_u256_fallback,
2154	iemAImpl_vunpckhpd_u256, iemAImpl_vunpckhpd_u256_fallback;
2155	/** @} */
2156
2157	/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
2158	* @{ */
2159	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
2160	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
2161	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpckhbw_u128, iemAImpl_vpunpckhbw_u128_fallback,
2162	iemAImpl_vpunpckhwd_u128, iemAImpl_vpunpckhwd_u128_fallback,
2163	iemAImpl_vpunpckhdq_u128, iemAImpl_vpunpckhdq_u128_fallback,
2164	iemAImpl_vpunpckhqdq_u128, iemAImpl_vpunpckhqdq_u128_fallback;
2165	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpckhbw_u256, iemAImpl_vpunpckhbw_u256_fallback,
2166	iemAImpl_vpunpckhwd_u256, iemAImpl_vpunpckhwd_u256_fallback,
2167	iemAImpl_vpunpckhdq_u256, iemAImpl_vpunpckhdq_u256_fallback,
2168	iemAImpl_vpunpckhqdq_u256, iemAImpl_vpunpckhqdq_u256_fallback;
2169	/** @} */
2170
2171	/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
2172	* @{ */
2173	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2174	typedef FNIEMAIMPLMEDIAPSHUFU128 *PFNIEMAIMPLMEDIAPSHUFU128;
2175	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
2176	typedef FNIEMAIMPLMEDIAPSHUFU256 *PFNIEMAIMPLMEDIAPSHUFU256;
2177	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw_u64,(uint64_t puDst, uint64_t const puSrc, uint8_t bEvil));
2178	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_pshufhw_u128, iemAImpl_pshuflw_u128, iemAImpl_pshufd_u128;
2179	#ifndef IEM_WITHOUT_ASSEMBLY
2180	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256, iemAImpl_vpshuflw_u256, iemAImpl_vpshufd_u256;
2181	#endif
2182	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256_fallback, iemAImpl_vpshuflw_u256_fallback, iemAImpl_vpshufd_u256_fallback;
2183	/** @} */
2184
2185	/** @name Media (SSE/MMX/AVX) operation: Shift Immediate Stuff (evil)
2186	* @{ */
2187	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU64,(uint64_t *puDst, uint8_t bShift));
2188	typedef FNIEMAIMPLMEDIAPSHIFTU64 *PFNIEMAIMPLMEDIAPSHIFTU64;
2189	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU128,(PRTUINT128U puDst, uint8_t bShift));
2190	typedef FNIEMAIMPLMEDIAPSHIFTU128 *PFNIEMAIMPLMEDIAPSHIFTU128;
2191	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU256,(PRTUINT256U puDst, uint8_t bShift));
2192	typedef FNIEMAIMPLMEDIAPSHIFTU256 *PFNIEMAIMPLMEDIAPSHIFTU256;
2193	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psllw_imm_u64, iemAImpl_pslld_imm_u64, iemAImpl_psllq_imm_u64;
2194	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psrlw_imm_u64, iemAImpl_psrld_imm_u64, iemAImpl_psrlq_imm_u64;
2195	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psraw_imm_u64, iemAImpl_psrad_imm_u64;
2196	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psllw_imm_u128, iemAImpl_pslld_imm_u128, iemAImpl_psllq_imm_u128;
2197	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psrlw_imm_u128, iemAImpl_psrld_imm_u128, iemAImpl_psrlq_imm_u128;
2198	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psraw_imm_u128, iemAImpl_psrad_imm_u128;
2199	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_pslldq_imm_u128, iemAImpl_psrldq_imm_u128;
2200	/** @} */
2201
2202	/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
2203	* @{ */
2204	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(uint64_t pu64Dst, uint64_t const puSrc));
2205	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(uint64_t *pu64Dst, PCRTUINT128U puSrc));
2206	#ifndef IEM_WITHOUT_ASSEMBLY
2207	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
2208	#endif
2209	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256_fallback,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
2210	/** @} */
2211
2212	/** @name Media (SSE/MMX/AVX) operations: Variable Blend Packed Bytes/R32/R64.
2213	* @{ */
2214	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puMask));
2215	typedef FNIEMAIMPLBLENDU128 *PFNIEMAIMPLBLENDU128;
2216	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, PCRTUINT128U puMask));
2217	typedef FNIEMAIMPLAVXBLENDU128 *PFNIEMAIMPLAVXBLENDU128;
2218	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, PCRTUINT256U puMask));
2219	typedef FNIEMAIMPLAVXBLENDU256 *PFNIEMAIMPLAVXBLENDU256;
2220
2221	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128;
2222	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128_fallback;
2223	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128;
2224	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128_fallback;
2225	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256;
2226	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256_fallback;
2227
2228	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128;
2229	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128_fallback;
2230	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128;
2231	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128_fallback;
2232	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256;
2233	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256_fallback;
2234
2235	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128;
2236	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128_fallback;
2237	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128;
2238	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128_fallback;
2239	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256;
2240	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256_fallback;
2241	/** @} */
2242
2243
2244	/** @name Media (SSE/MMX/AVX) operation: Sort this later
2245	* @{ */
2246	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
2247	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
2248	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovshdup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
2249	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovshdup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
2250	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
2251	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
2252
2253	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2254	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2255	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2256	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2257	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2258
2259	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2260	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2261	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2262	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2263	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2264
2265	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2266	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2267	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
2268	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2269	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2270
2271	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2272	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2273	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2274	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2275	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2276
2277	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2278	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2279	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2280	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2281	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2282
2283	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2284	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2285	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2286	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2287	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2288
2289	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2290	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2291	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2292	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2293	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2294
2295	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2296	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2297	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2298	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2299	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2300
2301	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2302	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2303	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
2304	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2305	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2306
2307	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2308	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2309	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2310	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2311	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2312
2313	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2314	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2315	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2316	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2317	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2318
2319	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2320	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2321	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2322	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2323	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2324
2325	IEM_DECL_IMPL_DEF(void, iemAImpl_shufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2326	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2327	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2328	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2329	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2330
2331	IEM_DECL_IMPL_DEF(void, iemAImpl_shufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2332	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2333	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2334	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2335	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2336
2337	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
2338	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64_fallback,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
2339
2340	IEM_DECL_IMPL_DEF(void, iemAImpl_pinsrw_u64,(uint64_t *pu64Dst, uint16_t u16Src, uint8_t bEvil));
2341	IEM_DECL_IMPL_DEF(void, iemAImpl_pinsrw_u128,(PRTUINT128U puDst, uint16_t u16Src, uint8_t bEvil));
2342	IEM_DECL_IMPL_DEF(void, iemAImpl_vpinsrw_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint16_t u16Src, uint8_t bEvil));
2343	IEM_DECL_IMPL_DEF(void, iemAImpl_vpinsrw_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint16_t u16Src, uint8_t bEvil));
2344
2345	IEM_DECL_IMPL_DEF(void, iemAImpl_pextrw_u64,(uint16_t *pu16Dst, uint64_t u64Src, uint8_t bEvil));
2346	IEM_DECL_IMPL_DEF(void, iemAImpl_pextrw_u128,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
2347	IEM_DECL_IMPL_DEF(void, iemAImpl_vpextrw_u128,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
2348	IEM_DECL_IMPL_DEF(void, iemAImpl_vpextrw_u128_fallback,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
2349
2350	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2351	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2352	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2353	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
2354	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
2355
2356	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2357	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2358	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2359	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
2360	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
2361
2362
2363	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2364	typedef FNIEMAIMPLMEDIAOPTF2U128IMM8 *PFNIEMAIMPLMEDIAOPTF2U128IMM8;
2365	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2366	typedef FNIEMAIMPLMEDIAOPTF3U128IMM8 *PFNIEMAIMPLMEDIAOPTF3U128IMM8;
2367	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2368	typedef FNIEMAIMPLMEDIAOPTF3U256IMM8 *PFNIEMAIMPLMEDIAOPTF3U256IMM8;
2369
2370	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_palignr_u128, iemAImpl_palignr_u128_fallback;
2371	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pblendw_u128, iemAImpl_pblendw_u128_fallback;
2372	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendps_u128, iemAImpl_blendps_u128_fallback;
2373	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendpd_u128, iemAImpl_blendpd_u128_fallback;
2374
2375	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpalignr_u128, iemAImpl_vpalignr_u128_fallback;
2376	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendw_u128, iemAImpl_vpblendw_u128_fallback;
2377	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendps_u128, iemAImpl_vblendps_u128_fallback;
2378	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendpd_u128, iemAImpl_vblendpd_u128_fallback;
2379
2380	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpalignr_u256, iemAImpl_vpalignr_u256_fallback;
2381	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendw_u256, iemAImpl_vpblendw_u256_fallback;
2382	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendps_u256, iemAImpl_vblendps_u256_fallback;
2383	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendpd_u256, iemAImpl_vblendpd_u256_fallback;
2384
2385	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesimc_u128, iemAImpl_aesimc_u128_fallback;
2386	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenc_u128, iemAImpl_aesenc_u128_fallback;
2387	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenclast_u128, iemAImpl_aesenclast_u128_fallback;
2388	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdec_u128, iemAImpl_aesdec_u128_fallback;
2389	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdeclast_u128, iemAImpl_aesdeclast_u128_fallback;
2390
2391	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesimc_u128, iemAImpl_vaesimc_u128_fallback;
2392	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenc_u128, iemAImpl_vaesenc_u128_fallback;
2393	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenclast_u128, iemAImpl_vaesenclast_u128_fallback;
2394	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdec_u128, iemAImpl_vaesdec_u128_fallback;
2395	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdeclast_u128, iemAImpl_vaesdeclast_u128_fallback;
2396
2397	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_aeskeygenassist_u128, iemAImpl_aeskeygenassist_u128_fallback;
2398
2399	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vaeskeygenassist_u128, iemAImpl_vaeskeygenassist_u128_fallback;
2400
2401	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1nexte_u128, iemAImpl_sha1nexte_u128_fallback;
2402	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg1_u128, iemAImpl_sha1msg1_u128_fallback;
2403	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg2_u128, iemAImpl_sha1msg2_u128_fallback;
2404	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg1_u128, iemAImpl_sha256msg1_u128_fallback;
2405	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg2_u128, iemAImpl_sha256msg2_u128_fallback;
2406	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_sha1rnds4_u128, iemAImpl_sha1rnds4_u128_fallback;
2407	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
2408	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
2409
2410	typedef struct IEMPCMPISTRXSRC
2411	{
2412	RTUINT128U uSrc1;
2413	RTUINT128U uSrc2;
2414	} IEMPCMPISTRXSRC;
2415	typedef IEMPCMPISTRXSRC *PIEMPCMPISTRXSRC;
2416	typedef const IEMPCMPISTRXSRC *PCIEMPCMPISTRXSRC;
2417
2418	typedef struct IEMPCMPESTRXSRC
2419	{
2420	RTUINT128U uSrc1;
2421	RTUINT128U uSrc2;
2422	uint64_t u64Rax;
2423	uint64_t u64Rdx;
2424	} IEMPCMPESTRXSRC;
2425	typedef IEMPCMPESTRXSRC *PIEMPCMPESTRXSRC;
2426	typedef const IEMPCMPESTRXSRC *PCIEMPCMPESTRXSRC;
2427
2428	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPISTRIU128IMM8,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
2429	typedef FNIEMAIMPLPCMPISTRIU128IMM8 *PFNIEMAIMPLPCMPISTRIU128IMM8;
2430	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRIU128IMM8,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
2431	typedef FNIEMAIMPLPCMPESTRIU128IMM8 *PFNIEMAIMPLPCMPESTRIU128IMM8;
2432
2433	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPISTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
2434	typedef FNIEMAIMPLPCMPISTRMU128IMM8 *PFNIEMAIMPLPCMPISTRMU128IMM8;
2435	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
2436	typedef FNIEMAIMPLPCMPESTRMU128IMM8 *PFNIEMAIMPLPCMPESTRMU128IMM8;
2437
2438	FNIEMAIMPLPCMPISTRIU128IMM8 iemAImpl_pcmpistri_u128, iemAImpl_pcmpistri_u128_fallback;
2439	FNIEMAIMPLPCMPESTRIU128IMM8 iemAImpl_pcmpestri_u128, iemAImpl_pcmpestri_u128_fallback;
2440	FNIEMAIMPLPCMPISTRMU128IMM8 iemAImpl_pcmpistrm_u128, iemAImpl_pcmpistrm_u128_fallback;
2441	FNIEMAIMPLPCMPESTRMU128IMM8 iemAImpl_pcmpestrm_u128, iemAImpl_pcmpestrm_u128_fallback;
2442
2443	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pclmulqdq_u128, iemAImpl_pclmulqdq_u128_fallback;
2444	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpclmulqdq_u128, iemAImpl_vpclmulqdq_u128_fallback;
2445
2446	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_mpsadbw_u128, iemAImpl_mpsadbw_u128_fallback;
2447	/** @} */
2448
2449	/** @name Media Odds and Ends
2450	* @{ */
2451	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U8,(uint32_t *puDst, uint8_t uSrc));
2452	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U16,(uint32_t *puDst, uint16_t uSrc));
2453	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U32,(uint32_t *puDst, uint32_t uSrc));
2454	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U64,(uint32_t *puDst, uint64_t uSrc));
2455	FNIEMAIMPLCR32U8 iemAImpl_crc32_u8, iemAImpl_crc32_u8_fallback;
2456	FNIEMAIMPLCR32U16 iemAImpl_crc32_u16, iemAImpl_crc32_u16_fallback;
2457	FNIEMAIMPLCR32U32 iemAImpl_crc32_u32, iemAImpl_crc32_u32_fallback;
2458	FNIEMAIMPLCR32U64 iemAImpl_crc32_u64, iemAImpl_crc32_u64_fallback;
2459
2460	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL128,(PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint32_t *pEFlags));
2461	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL256,(PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint32_t *pEFlags));
2462	FNIEMAIMPLF2EFL128 iemAImpl_ptest_u128;
2463	FNIEMAIMPLF2EFL256 iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback;
2464
2465	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I32U64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int32_t pi32Dst, const uint64_t pu64Src)); / pu64Src is a double precision floating point. */
2466	typedef FNIEMAIMPLSSEF2I32U64 *PFNIEMAIMPLSSEF2I32U64;
2467	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I64U64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int64_t pi64Dst, const uint64_t pu64Src)); / pu64Src is a double precision floating point. */
2468	typedef FNIEMAIMPLSSEF2I64U64 *PFNIEMAIMPLSSEF2I64U64;
2469	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I32U32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int32_t pi32Dst, const uint32_t pu32Src)); / pu32Src is a single precision floating point. */
2470	typedef FNIEMAIMPLSSEF2I32U32 *PFNIEMAIMPLSSEF2I32U32;
2471	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I64U32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int64_t pi64Dst, const uint32_t pu32Src)); / pu32Src is a single precision floating point. */
2472	typedef FNIEMAIMPLSSEF2I64U32 *PFNIEMAIMPLSSEF2I64U32;
2473
2474	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvttsd2si_i32_r64;
2475	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvtsd2si_i32_r64;
2476
2477	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvttsd2si_i64_r64;
2478	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvtsd2si_i64_r64;
2479
2480	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvttss2si_i32_r32;
2481	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvtss2si_i32_r32;
2482
2483	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvttss2si_i64_r32;
2484	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvtss2si_i64_r32;
2485
2486	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R32I32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT32U pr32Dst, const int32_t pi32Src));
2487	typedef FNIEMAIMPLSSEF2R32I32 *PFNIEMAIMPLSSEF2R32I32;
2488	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R32I64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT32U pr32Dst, const int64_t pi64Src));
2489	typedef FNIEMAIMPLSSEF2R32I64 *PFNIEMAIMPLSSEF2R32I64;
2490
2491	FNIEMAIMPLSSEF2R32I32 iemAImpl_cvtsi2ss_r32_i32;
2492	FNIEMAIMPLSSEF2R32I64 iemAImpl_cvtsi2ss_r32_i64;
2493
2494	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R64I32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT64U pr64Dst, const int32_t pi32Src));
2495	typedef FNIEMAIMPLSSEF2R64I32 *PFNIEMAIMPLSSEF2R64I32;
2496	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R64I64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT64U pr64Dst, const int64_t pi64Src));
2497	typedef FNIEMAIMPLSSEF2R64I64 *PFNIEMAIMPLSSEF2R64I64;
2498
2499	FNIEMAIMPLSSEF2R64I32 iemAImpl_cvtsi2sd_r64_i32;
2500	FNIEMAIMPLSSEF2R64I64 iemAImpl_cvtsi2sd_r64_i64;
2501
2502
2503	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFLMXCSR128,(uint32_t pfMxcsr, uint32_t pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
2504	typedef FNIEMAIMPLF2EFLMXCSR128 *PFNIEMAIMPLF2EFLMXCSR128;
2505
2506	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_ucomiss_u128;
2507	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback;
2508
2509	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_ucomisd_u128;
2510	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback;
2511
2512	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_comiss_u128;
2513	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback;
2514
2515	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_comisd_u128;
2516	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback;
2517
2518
2519	typedef struct IEMMEDIAF2XMMSRC
2520	{
2521	X86XMMREG uSrc1;
2522	X86XMMREG uSrc2;
2523	} IEMMEDIAF2XMMSRC;
2524	typedef IEMMEDIAF2XMMSRC *PIEMMEDIAF2XMMSRC;
2525	typedef const IEMMEDIAF2XMMSRC *PCIEMMEDIAF2XMMSRC;
2526
2527	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRF2XMMIMM8,(uint32_t *pfMxcsr, PX86XMMREG puDst, PCIEMMEDIAF2XMMSRC puSrc, uint8_t bEvil));
2528	typedef FNIEMAIMPLMXCSRF2XMMIMM8 *PFNIEMAIMPLMXCSRF2XMMIMM8;
2529
2530	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpps_u128;
2531	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmppd_u128;
2532	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpss_u128;
2533	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpsd_u128;
2534	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundss_u128;
2535	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundsd_u128;
2536
2537	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundps_u128, iemAImpl_roundps_u128_fallback;
2538	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundpd_u128, iemAImpl_roundpd_u128_fallback;
2539
2540	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU64U128,(uint32_t pfMxcsr, uint64_t pu64Dst, PCX86XMMREG pSrc));
2541	typedef FNIEMAIMPLMXCSRU64U128 *PFNIEMAIMPLMXCSRU64U128;
2542
2543	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvtpd2pi_u128;
2544	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvttpd2pi_u128;
2545
2546	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU128U64,(uint32_t *pfMxcsr, PX86XMMREG pDst, uint64_t u64Src));
2547	typedef FNIEMAIMPLMXCSRU128U64 *PFNIEMAIMPLMXCSRU128U64;
2548
2549	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2ps_u128;
2550	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2pd_u128;
2551
2552	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU64U64,(uint32_t pfMxcsr, uint64_t pu64Dst, uint64_t u64Src));
2553	typedef FNIEMAIMPLMXCSRU64U64 *PFNIEMAIMPLMXCSRU64U64;
2554
2555	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvtps2pi_u128;
2556	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvttps2pi_u128;
2557
2558	/** @} */
2559
2560
2561	/** @name Function tables.
2562	* @{
2563	*/
2564
2565	/**
2566	* Function table for a binary operator providing implementation based on
2567	* operand size.
2568	*/
2569	typedef struct IEMOPBINSIZES
2570	{
2571	PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
2572	PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
2573	PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
2574	PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
2575	} IEMOPBINSIZES;
2576	/** Pointer to a binary operator function table. */
2577	typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
2578
2579
2580	/**
2581	* Function table for a unary operator providing implementation based on
2582	* operand size.
2583	*/
2584	typedef struct IEMOPUNARYSIZES
2585	{
2586	PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
2587	PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
2588	PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
2589	PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
2590	} IEMOPUNARYSIZES;
2591	/** Pointer to a unary operator function table. */
2592	typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
2593
2594
2595	/**
2596	* Function table for a shift operator providing implementation based on
2597	* operand size.
2598	*/
2599	typedef struct IEMOPSHIFTSIZES
2600	{
2601	PFNIEMAIMPLSHIFTU8 pfnNormalU8;
2602	PFNIEMAIMPLSHIFTU16 pfnNormalU16;
2603	PFNIEMAIMPLSHIFTU32 pfnNormalU32;
2604	PFNIEMAIMPLSHIFTU64 pfnNormalU64;
2605	} IEMOPSHIFTSIZES;
2606	/** Pointer to a shift operator function table. */
2607	typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
2608
2609
2610	/**
2611	* Function table for a multiplication or division operation.
2612	*/
2613	typedef struct IEMOPMULDIVSIZES
2614	{
2615	PFNIEMAIMPLMULDIVU8 pfnU8;
2616	PFNIEMAIMPLMULDIVU16 pfnU16;
2617	PFNIEMAIMPLMULDIVU32 pfnU32;
2618	PFNIEMAIMPLMULDIVU64 pfnU64;
2619	} IEMOPMULDIVSIZES;
2620	/** Pointer to a multiplication or division operation function table. */
2621	typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
2622
2623
2624	/**
2625	* Function table for a double precision shift operator providing implementation
2626	* based on operand size.
2627	*/
2628	typedef struct IEMOPSHIFTDBLSIZES
2629	{
2630	PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
2631	PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
2632	PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
2633	} IEMOPSHIFTDBLSIZES;
2634	/** Pointer to a double precision shift function table. */
2635	typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
2636
2637
2638	/**
2639	* Function table for media instruction taking two full sized media source
2640	* registers and one full sized destination register (AVX).
2641	*/
2642	typedef struct IEMOPMEDIAF3
2643	{
2644	PFNIEMAIMPLMEDIAF3U128 pfnU128;
2645	PFNIEMAIMPLMEDIAF3U256 pfnU256;
2646	} IEMOPMEDIAF3;
2647	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
2648	typedef IEMOPMEDIAF3 const *PCIEMOPMEDIAF3;
2649
2650	/** @def IEMOPMEDIAF3_INIT_VARS_EX
2651	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2652	* given functions as initializers. For use in AVX functions where a pair of
2653	* functions are only used once and the function table need not be public. */
2654	#ifndef TST_IEM_CHECK_MC
2655	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2656	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2657	static IEMOPMEDIAF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2658	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2659	# else
2660	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2661	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2662	# endif
2663	#else
2664	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2665	#endif
2666	/** @def IEMOPMEDIAF3_INIT_VARS
2667	* Generate AVX function tables for the @a a_InstrNm instruction.
2668	* @sa IEMOPMEDIAF3_INIT_VARS_EX */
2669	#define IEMOPMEDIAF3_INIT_VARS(a_InstrNm) \
2670	IEMOPMEDIAF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2671	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2672
2673	/**
2674	* Function table for media instruction taking two full sized media source
2675	* registers and one full sized destination register, but no additional state
2676	* (AVX).
2677	*/
2678	typedef struct IEMOPMEDIAOPTF3
2679	{
2680	PFNIEMAIMPLMEDIAOPTF3U128 pfnU128;
2681	PFNIEMAIMPLMEDIAOPTF3U256 pfnU256;
2682	} IEMOPMEDIAOPTF3;
2683	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
2684	typedef IEMOPMEDIAOPTF3 const *PCIEMOPMEDIAOPTF3;
2685
2686	/** @def IEMOPMEDIAOPTF3_INIT_VARS_EX
2687	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2688	* given functions as initializers. For use in AVX functions where a pair of
2689	* functions are only used once and the function table need not be public. */
2690	#ifndef TST_IEM_CHECK_MC
2691	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2692	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2693	static IEMOPMEDIAOPTF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2694	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2695	# else
2696	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2697	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2698	# endif
2699	#else
2700	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2701	#endif
2702	/** @def IEMOPMEDIAOPTF3_INIT_VARS
2703	* Generate AVX function tables for the @a a_InstrNm instruction.
2704	* @sa IEMOPMEDIAOPTF3_INIT_VARS_EX */
2705	#define IEMOPMEDIAOPTF3_INIT_VARS(a_InstrNm) \
2706	IEMOPMEDIAOPTF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2707	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2708
2709	/**
2710	* Function table for media instruction taking one full sized media source
2711	* registers and one full sized destination register, but no additional state
2712	* (AVX).
2713	*/
2714	typedef struct IEMOPMEDIAOPTF2
2715	{
2716	PFNIEMAIMPLMEDIAOPTF2U128 pfnU128;
2717	PFNIEMAIMPLMEDIAOPTF2U256 pfnU256;
2718	} IEMOPMEDIAOPTF2;
2719	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
2720	typedef IEMOPMEDIAOPTF2 const *PCIEMOPMEDIAOPTF2;
2721
2722	/** @def IEMOPMEDIAOPTF2_INIT_VARS_EX
2723	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2724	* given functions as initializers. For use in AVX functions where a pair of
2725	* functions are only used once and the function table need not be public. */
2726	#ifndef TST_IEM_CHECK_MC
2727	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2728	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2729	static IEMOPMEDIAOPTF2 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2730	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2731	# else
2732	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2733	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2734	# endif
2735	#else
2736	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2737	#endif
2738	/** @def IEMOPMEDIAOPTF2_INIT_VARS
2739	* Generate AVX function tables for the @a a_InstrNm instruction.
2740	* @sa IEMOPMEDIAOPTF2_INIT_VARS_EX */
2741	#define IEMOPMEDIAOPTF2_INIT_VARS(a_InstrNm) \
2742	IEMOPMEDIAOPTF2_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2743	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2744
2745	/**
2746	* Function table for media instruction taking two full sized media source
2747	* registers and one full sized destination register and an 8-bit immediate, but no additional state
2748	* (AVX).
2749	*/
2750	typedef struct IEMOPMEDIAOPTF3IMM8
2751	{
2752	PFNIEMAIMPLMEDIAOPTF3U128IMM8 pfnU128;
2753	PFNIEMAIMPLMEDIAOPTF3U256IMM8 pfnU256;
2754	} IEMOPMEDIAOPTF3IMM8;
2755	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
2756	typedef IEMOPMEDIAOPTF3IMM8 const *PCIEMOPMEDIAOPTF3IMM8;
2757
2758	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX
2759	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2760	* given functions as initializers. For use in AVX functions where a pair of
2761	* functions are only used once and the function table need not be public. */
2762	#ifndef TST_IEM_CHECK_MC
2763	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2764	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2765	static IEMOPMEDIAOPTF3IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2766	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2767	# else
2768	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2769	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2770	# endif
2771	#else
2772	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2773	#endif
2774	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS
2775	* Generate AVX function tables for the @a a_InstrNm instruction.
2776	* @sa IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX */
2777	#define IEMOPMEDIAOPTF3IMM8_INIT_VARS(a_InstrNm) \
2778	IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2779	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2780	/** @} */
2781
2782
2783	/**
2784	* Function table for blend type instruction taking three full sized media source
2785	* registers and one full sized destination register, but no additional state
2786	* (AVX).
2787	*/
2788	typedef struct IEMOPBLENDOP
2789	{
2790	PFNIEMAIMPLAVXBLENDU128 pfnU128;
2791	PFNIEMAIMPLAVXBLENDU256 pfnU256;
2792	} IEMOPBLENDOP;
2793	/** Pointer to a media operation function table for 4 full sized ops (AVX). */
2794	typedef IEMOPBLENDOP const *PCIEMOPBLENDOP;
2795
2796	/** @def IEMOPBLENDOP_INIT_VARS_EX
2797	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2798	* given functions as initializers. For use in AVX functions where a pair of
2799	* functions are only used once and the function table need not be public. */
2800	#ifndef TST_IEM_CHECK_MC
2801	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2802	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2803	static IEMOPBLENDOP const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2804	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2805	# else
2806	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2807	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2808	# endif
2809	#else
2810	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2811	#endif
2812	/** @def IEMOPBLENDOP_INIT_VARS
2813	* Generate AVX function tables for the @a a_InstrNm instruction.
2814	* @sa IEMOPBLENDOP_INIT_VARS_EX */
2815	#define IEMOPBLENDOP_INIT_VARS(a_InstrNm) \
2816	IEMOPBLENDOP_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2817	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2818
2819
2820	/** @name SSE/AVX single/double precision floating point operations.
2821	* @{ */
2822	/**
2823	* A SSE result.
2824	*/
2825	typedef struct IEMSSERESULT
2826	{
2827	/** The output value. */
2828	X86XMMREG uResult;
2829	/** The output status. */
2830	uint32_t MXCSR;
2831	} IEMSSERESULT;
2832	AssertCompileMemberOffset(IEMSSERESULT, MXCSR, 128 / 8);
2833	/** Pointer to a SSE result. */
2834	typedef IEMSSERESULT *PIEMSSERESULT;
2835	/** Pointer to a const SSE result. */
2836	typedef IEMSSERESULT const *PCIEMSSERESULT;
2837
2838
2839	/**
2840	* A AVX128 result.
2841	*/
2842	typedef struct IEMAVX128RESULT
2843	{
2844	/** The output value. */
2845	X86XMMREG uResult;
2846	/** The output status. */
2847	uint32_t MXCSR;
2848	} IEMAVX128RESULT;
2849	AssertCompileMemberOffset(IEMAVX128RESULT, MXCSR, 128 / 8);
2850	/** Pointer to a AVX128 result. */
2851	typedef IEMAVX128RESULT *PIEMAVX128RESULT;
2852	/** Pointer to a const AVX128 result. */
2853	typedef IEMAVX128RESULT const *PCIEMAVX128RESULT;
2854
2855
2856	/**
2857	* A AVX256 result.
2858	*/
2859	typedef struct IEMAVX256RESULT
2860	{
2861	/** The output value. */
2862	X86YMMREG uResult;
2863	/** The output status. */
2864	uint32_t MXCSR;
2865	} IEMAVX256RESULT;
2866	AssertCompileMemberOffset(IEMAVX256RESULT, MXCSR, 256 / 8);
2867	/** Pointer to a AVX256 result. */
2868	typedef IEMAVX256RESULT *PIEMAVX256RESULT;
2869	/** Pointer to a const AVX256 result. */
2870	typedef IEMAVX256RESULT const *PCIEMAVX256RESULT;
2871
2872
2873	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
2874	typedef FNIEMAIMPLFPSSEF2U128 *PFNIEMAIMPLFPSSEF2U128;
2875	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128R32,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
2876	typedef FNIEMAIMPLFPSSEF2U128R32 *PFNIEMAIMPLFPSSEF2U128R32;
2877	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128R64,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
2878	typedef FNIEMAIMPLFPSSEF2U128R64 *PFNIEMAIMPLFPSSEF2U128R64;
2879
2880	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
2881	typedef FNIEMAIMPLFPAVXF3U128 *PFNIEMAIMPLFPAVXF3U128;
2882	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128R32,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
2883	typedef FNIEMAIMPLFPAVXF3U128R32 *PFNIEMAIMPLFPAVXF3U128R32;
2884	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128R64,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
2885	typedef FNIEMAIMPLFPAVXF3U128R64 *PFNIEMAIMPLFPAVXF3U128R64;
2886
2887	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U256,(PX86XSAVEAREA pExtState, PIEMAVX256RESULT pResult, PCX86YMMREG puSrc1, PCX86YMMREG puSrc2));
2888	typedef FNIEMAIMPLFPAVXF3U256 *PFNIEMAIMPLFPAVXF3U256;
2889
2890	FNIEMAIMPLFPSSEF2U128 iemAImpl_addps_u128;
2891	FNIEMAIMPLFPSSEF2U128 iemAImpl_addpd_u128;
2892	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulps_u128;
2893	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulpd_u128;
2894	FNIEMAIMPLFPSSEF2U128 iemAImpl_subps_u128;
2895	FNIEMAIMPLFPSSEF2U128 iemAImpl_subpd_u128;
2896	FNIEMAIMPLFPSSEF2U128 iemAImpl_minps_u128;
2897	FNIEMAIMPLFPSSEF2U128 iemAImpl_minpd_u128;
2898	FNIEMAIMPLFPSSEF2U128 iemAImpl_divps_u128;
2899	FNIEMAIMPLFPSSEF2U128 iemAImpl_divpd_u128;
2900	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxps_u128;
2901	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxpd_u128;
2902	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddps_u128;
2903	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddpd_u128;
2904	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubps_u128;
2905	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubpd_u128;
2906	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtps_u128;
2907	FNIEMAIMPLFPSSEF2U128 iemAImpl_rsqrtps_u128;
2908	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtpd_u128;
2909	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubps_u128;
2910	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubpd_u128;
2911	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2ps_u128;
2912	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2pd_u128;
2913
2914	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2ps_u128;
2915	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2dq_u128;
2916	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttps2dq_u128;
2917	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttpd2dq_u128;
2918	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2pd_u128;
2919	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2dq_u128;
2920
2921	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_addss_u128_r32;
2922	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_addsd_u128_r64;
2923	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_mulss_u128_r32;
2924	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_mulsd_u128_r64;
2925	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_subss_u128_r32;
2926	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_subsd_u128_r64;
2927	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_minss_u128_r32;
2928	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_minsd_u128_r64;
2929	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_divss_u128_r32;
2930	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_divsd_u128_r64;
2931	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_maxss_u128_r32;
2932	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_maxsd_u128_r64;
2933	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_cvtss2sd_u128_r32;
2934	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_cvtsd2ss_u128_r64;
2935	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_sqrtss_u128_r32;
2936	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_sqrtsd_u128_r64;
2937	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_rsqrtss_u128_r32;
2938
2939	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddps_u128, iemAImpl_vaddps_u128_fallback;
2940	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddpd_u128, iemAImpl_vaddpd_u128_fallback;
2941	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulps_u128, iemAImpl_vmulps_u128_fallback;
2942	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulpd_u128, iemAImpl_vmulpd_u128_fallback;
2943	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubps_u128, iemAImpl_vsubps_u128_fallback;
2944	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubpd_u128, iemAImpl_vsubpd_u128_fallback;
2945	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminps_u128, iemAImpl_vminps_u128_fallback;
2946	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminpd_u128, iemAImpl_vminpd_u128_fallback;
2947	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivps_u128, iemAImpl_vdivps_u128_fallback;
2948	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivpd_u128, iemAImpl_vdivpd_u128_fallback;
2949	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxps_u128, iemAImpl_vmaxps_u128_fallback;
2950	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxpd_u128, iemAImpl_vmaxpd_u128_fallback;
2951	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddps_u128, iemAImpl_vhaddps_u128_fallback;
2952	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddpd_u128, iemAImpl_vhaddpd_u128_fallback;
2953	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubps_u128, iemAImpl_vhsubps_u128_fallback;
2954	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubpd_u128, iemAImpl_vhsubpd_u128_fallback;
2955	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtps_u128, iemAImpl_vsqrtps_u128_fallback;
2956	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtpd_u128, iemAImpl_vsqrtpd_u128_fallback;
2957	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubps_u128, iemAImpl_vaddsubps_u128_fallback;
2958	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubpd_u128, iemAImpl_vaddsubpd_u128_fallback;
2959	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtpd2ps_u128, iemAImpl_vcvtpd2ps_u128_fallback;
2960	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtps2pd_u128, iemAImpl_vcvtps2pd_u128_fallback;
2961
2962	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vaddss_u128_r32, iemAImpl_vaddss_u128_r32_fallback;
2963	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vaddsd_u128_r64, iemAImpl_vaddsd_u128_r64_fallback;
2964	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmulss_u128_r32, iemAImpl_vmulss_u128_r32_fallback;
2965	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmulsd_u128_r64, iemAImpl_vmulsd_u128_r64_fallback;
2966	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsubss_u128_r32, iemAImpl_vsubss_u128_r32_fallback;
2967	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsubsd_u128_r64, iemAImpl_vsubsd_u128_r64_fallback;
2968	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vminss_u128_r32, iemAImpl_vminss_u128_r32_fallback;
2969	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vminsd_u128_r64, iemAImpl_vminsd_u128_r64_fallback;
2970	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vdivss_u128_r32, iemAImpl_vdivss_u128_r32_fallback;
2971	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vdivsd_u128_r64, iemAImpl_vdivsd_u128_r64_fallback;
2972	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmaxss_u128_r32, iemAImpl_vmaxss_u128_r32_fallback;
2973	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmaxsd_u128_r64, iemAImpl_vmaxsd_u128_r64_fallback;
2974	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsqrtss_u128_r32, iemAImpl_vsqrtss_u128_r32_fallback;
2975	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsqrtsd_u128_r64, iemAImpl_vsqrtsd_u128_r64_fallback;
2976
2977	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddps_u256, iemAImpl_vaddps_u256_fallback;
2978	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddpd_u256, iemAImpl_vaddpd_u256_fallback;
2979	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulps_u256, iemAImpl_vmulps_u256_fallback;
2980	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulpd_u256, iemAImpl_vmulpd_u256_fallback;
2981	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubps_u256, iemAImpl_vsubps_u256_fallback;
2982	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubpd_u256, iemAImpl_vsubpd_u256_fallback;
2983	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminps_u256, iemAImpl_vminps_u256_fallback;
2984	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminpd_u256, iemAImpl_vminpd_u256_fallback;
2985	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivps_u256, iemAImpl_vdivps_u256_fallback;
2986	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivpd_u256, iemAImpl_vdivpd_u256_fallback;
2987	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxps_u256, iemAImpl_vmaxps_u256_fallback;
2988	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxpd_u256, iemAImpl_vmaxpd_u256_fallback;
2989	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddps_u256, iemAImpl_vhaddps_u256_fallback;
2990	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddpd_u256, iemAImpl_vhaddpd_u256_fallback;
2991	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubps_u256, iemAImpl_vhsubps_u256_fallback;
2992	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubpd_u256, iemAImpl_vhsubpd_u256_fallback;
2993	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubps_u256, iemAImpl_vhaddsubps_u256_fallback;
2994	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubpd_u256, iemAImpl_vhaddsubpd_u256_fallback;
2995	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtpd2ps_u256, iemAImpl_vcvtpd2ps_u256_fallback;
2996	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtps2pd_u256, iemAImpl_vcvtps2pd_u256_fallback;
2997	/** @} */
2998
2999	/** @name C instruction implementations for anything slightly complicated.
3000	* @{ */
3001
3002	/**
3003	* For typedef'ing or declaring a C instruction implementation function taking
3004	* no extra arguments.
3005	*
3006	* @param a_Name The name of the type.
3007	*/
3008	# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
3009	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
3010	/**
3011	* For defining a C instruction implementation function taking no extra
3012	* arguments.
3013	*
3014	* @param a_Name The name of the function
3015	*/
3016	# define IEM_CIMPL_DEF_0(a_Name) \
3017	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
3018	/**
3019	* Prototype version of IEM_CIMPL_DEF_0.
3020	*/
3021	# define IEM_CIMPL_PROTO_0(a_Name) \
3022	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
3023	/**
3024	* For calling a C instruction implementation function taking no extra
3025	* arguments.
3026	*
3027	* This special call macro adds default arguments to the call and allow us to
3028	* change these later.
3029	*
3030	* @param a_fn The name of the function.
3031	*/
3032	# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
3033
3034	/**
3035	* For typedef'ing or declaring a C instruction implementation function taking
3036	* one extra argument.
3037	*
3038	* @param a_Name The name of the type.
3039	* @param a_Type0 The argument type.
3040	* @param a_Arg0 The argument name.
3041	*/
3042	# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
3043	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
3044	/**
3045	* For defining a C instruction implementation function taking one extra
3046	* argument.
3047	*
3048	* @param a_Name The name of the function
3049	* @param a_Type0 The argument type.
3050	* @param a_Arg0 The argument name.
3051	*/
3052	# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
3053	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
3054	/**
3055	* Prototype version of IEM_CIMPL_DEF_1.
3056	*/
3057	# define IEM_CIMPL_PROTO_1(a_Name, a_Type0, a_Arg0) \
3058	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
3059	/**
3060	* For calling a C instruction implementation function taking one extra
3061	* argument.
3062	*
3063	* This special call macro adds default arguments to the call and allow us to
3064	* change these later.
3065	*
3066	* @param a_fn The name of the function.
3067	* @param a0 The name of the 1st argument.
3068	*/
3069	# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
3070
3071	/**
3072	* For typedef'ing or declaring a C instruction implementation function taking
3073	* two extra arguments.
3074	*
3075	* @param a_Name The name of the type.
3076	* @param a_Type0 The type of the 1st argument
3077	* @param a_Arg0 The name of the 1st argument.
3078	* @param a_Type1 The type of the 2nd argument.
3079	* @param a_Arg1 The name of the 2nd argument.
3080	*/
3081	# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
3082	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
3083	/**
3084	* For defining a C instruction implementation function taking two extra
3085	* arguments.
3086	*
3087	* @param a_Name The name of the function.
3088	* @param a_Type0 The type of the 1st argument
3089	* @param a_Arg0 The name of the 1st argument.
3090	* @param a_Type1 The type of the 2nd argument.
3091	* @param a_Arg1 The name of the 2nd argument.
3092	*/
3093	# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
3094	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
3095	/**
3096	* Prototype version of IEM_CIMPL_DEF_2.
3097	*/
3098	# define IEM_CIMPL_PROTO_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
3099	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
3100	/**
3101	* For calling a C instruction implementation function taking two extra
3102	* arguments.
3103	*
3104	* This special call macro adds default arguments to the call and allow us to
3105	* change these later.
3106	*
3107	* @param a_fn The name of the function.
3108	* @param a0 The name of the 1st argument.
3109	* @param a1 The name of the 2nd argument.
3110	*/
3111	# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
3112
3113	/**
3114	* For typedef'ing or declaring a C instruction implementation function taking
3115	* three extra arguments.
3116	*
3117	* @param a_Name The name of the type.
3118	* @param a_Type0 The type of the 1st argument
3119	* @param a_Arg0 The name of the 1st argument.
3120	* @param a_Type1 The type of the 2nd argument.
3121	* @param a_Arg1 The name of the 2nd argument.
3122	* @param a_Type2 The type of the 3rd argument.
3123	* @param a_Arg2 The name of the 3rd argument.
3124	*/
3125	# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
3126	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
3127	/**
3128	* For defining a C instruction implementation function taking three extra
3129	* arguments.
3130	*
3131	* @param a_Name The name of the function.
3132	* @param a_Type0 The type of the 1st argument
3133	* @param a_Arg0 The name of the 1st argument.
3134	* @param a_Type1 The type of the 2nd argument.
3135	* @param a_Arg1 The name of the 2nd argument.
3136	* @param a_Type2 The type of the 3rd argument.
3137	* @param a_Arg2 The name of the 3rd argument.
3138	*/
3139	# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
3140	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
3141	/**
3142	* Prototype version of IEM_CIMPL_DEF_3.
3143	*/
3144	# define IEM_CIMPL_PROTO_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
3145	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
3146	/**
3147	* For calling a C instruction implementation function taking three extra
3148	* arguments.
3149	*
3150	* This special call macro adds default arguments to the call and allow us to
3151	* change these later.
3152	*
3153	* @param a_fn The name of the function.
3154	* @param a0 The name of the 1st argument.
3155	* @param a1 The name of the 2nd argument.
3156	* @param a2 The name of the 3rd argument.
3157	*/
3158	# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
3159
3160
3161	/**
3162	* For typedef'ing or declaring a C instruction implementation function taking
3163	* four extra arguments.
3164	*
3165	* @param a_Name The name of the type.
3166	* @param a_Type0 The type of the 1st argument
3167	* @param a_Arg0 The name of the 1st argument.
3168	* @param a_Type1 The type of the 2nd argument.
3169	* @param a_Arg1 The name of the 2nd argument.
3170	* @param a_Type2 The type of the 3rd argument.
3171	* @param a_Arg2 The name of the 3rd argument.
3172	* @param a_Type3 The type of the 4th argument.
3173	* @param a_Arg3 The name of the 4th argument.
3174	*/
3175	# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
3176	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
3177	/**
3178	* For defining a C instruction implementation function taking four extra
3179	* arguments.
3180	*
3181	* @param a_Name The name of the function.
3182	* @param a_Type0 The type of the 1st argument
3183	* @param a_Arg0 The name of the 1st argument.
3184	* @param a_Type1 The type of the 2nd argument.
3185	* @param a_Arg1 The name of the 2nd argument.
3186	* @param a_Type2 The type of the 3rd argument.
3187	* @param a_Arg2 The name of the 3rd argument.
3188	* @param a_Type3 The type of the 4th argument.
3189	* @param a_Arg3 The name of the 4th argument.
3190	*/
3191	# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
3192	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3193	a_Type2 a_Arg2, a_Type3 a_Arg3))
3194	/**
3195	* Prototype version of IEM_CIMPL_DEF_4.
3196	*/
3197	# define IEM_CIMPL_PROTO_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
3198	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3199	a_Type2 a_Arg2, a_Type3 a_Arg3))
3200	/**
3201	* For calling a C instruction implementation function taking four extra
3202	* arguments.
3203	*
3204	* This special call macro adds default arguments to the call and allow us to
3205	* change these later.
3206	*
3207	* @param a_fn The name of the function.
3208	* @param a0 The name of the 1st argument.
3209	* @param a1 The name of the 2nd argument.
3210	* @param a2 The name of the 3rd argument.
3211	* @param a3 The name of the 4th argument.
3212	*/
3213	# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
3214
3215
3216	/**
3217	* For typedef'ing or declaring a C instruction implementation function taking
3218	* five extra arguments.
3219	*
3220	* @param a_Name The name of the type.
3221	* @param a_Type0 The type of the 1st argument
3222	* @param a_Arg0 The name of the 1st argument.
3223	* @param a_Type1 The type of the 2nd argument.
3224	* @param a_Arg1 The name of the 2nd argument.
3225	* @param a_Type2 The type of the 3rd argument.
3226	* @param a_Arg2 The name of the 3rd argument.
3227	* @param a_Type3 The type of the 4th argument.
3228	* @param a_Arg3 The name of the 4th argument.
3229	* @param a_Type4 The type of the 5th argument.
3230	* @param a_Arg4 The name of the 5th argument.
3231	*/
3232	# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
3233	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, \
3234	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
3235	a_Type3 a_Arg3, a_Type4 a_Arg4))
3236	/**
3237	* For defining a C instruction implementation function taking five extra
3238	* arguments.
3239	*
3240	* @param a_Name The name of the function.
3241	* @param a_Type0 The type of the 1st argument
3242	* @param a_Arg0 The name of the 1st argument.
3243	* @param a_Type1 The type of the 2nd argument.
3244	* @param a_Arg1 The name of the 2nd argument.
3245	* @param a_Type2 The type of the 3rd argument.
3246	* @param a_Arg2 The name of the 3rd argument.
3247	* @param a_Type3 The type of the 4th argument.
3248	* @param a_Arg3 The name of the 4th argument.
3249	* @param a_Type4 The type of the 5th argument.
3250	* @param a_Arg4 The name of the 5th argument.
3251	*/
3252	# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
3253	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3254	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
3255	/**
3256	* Prototype version of IEM_CIMPL_DEF_5.
3257	*/
3258	# define IEM_CIMPL_PROTO_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
3259	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3260	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
3261	/**
3262	* For calling a C instruction implementation function taking five extra
3263	* arguments.
3264	*
3265	* This special call macro adds default arguments to the call and allow us to
3266	* change these later.
3267	*
3268	* @param a_fn The name of the function.
3269	* @param a0 The name of the 1st argument.
3270	* @param a1 The name of the 2nd argument.
3271	* @param a2 The name of the 3rd argument.
3272	* @param a3 The name of the 4th argument.
3273	* @param a4 The name of the 5th argument.
3274	*/
3275	# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
3276
3277	/** @} */
3278
3279
3280	/** @name Opcode Decoder Function Types.
3281	* @{ */
3282
3283	/** @typedef PFNIEMOP
3284	* Pointer to an opcode decoder function.
3285	*/
3286
3287	/** @def FNIEMOP_DEF
3288	* Define an opcode decoder function.
3289	*
3290	* We're using macors for this so that adding and removing parameters as well as
3291	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL
3292	*
3293	* @param a_Name The function name.
3294	*/
3295
3296	/** @typedef PFNIEMOPRM
3297	* Pointer to an opcode decoder function with RM byte.
3298	*/
3299
3300	/** @def FNIEMOPRM_DEF
3301	* Define an opcode decoder function with RM byte.
3302	*
3303	* We're using macors for this so that adding and removing parameters as well as
3304	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL_1
3305	*
3306	* @param a_Name The function name.
3307	*/
3308
3309	#if defined(__GNUC__) && defined(RT_ARCH_X86)
3310	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOP)(PVMCPUCC pVCpu);
3311	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3312	# define FNIEMOP_DEF(a_Name) \
3313	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu)
3314	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3315	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
3316	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3317	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
3318
3319	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
3320	typedef VBOXSTRICTRC (__fastcall * PFNIEMOP)(PVMCPUCC pVCpu);
3321	typedef VBOXSTRICTRC (__fastcall * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3322	# define FNIEMOP_DEF(a_Name) \
3323	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
3324	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3325	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
3326	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3327	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
3328
3329	#elif defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
3330	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
3331	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3332	# define FNIEMOP_DEF(a_Name) \
3333	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu)
3334	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3335	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
3336	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3337	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
3338
3339	#else
3340	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
3341	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3342	# define FNIEMOP_DEF(a_Name) \
3343	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
3344	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3345	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
3346	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3347	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
3348
3349	#endif
3350	#define FNIEMOPRM_DEF(a_Name) FNIEMOP_DEF_1(a_Name, uint8_t, bRm)
3351
3352	/**
3353	* Call an opcode decoder function.
3354	*
3355	* We're using macors for this so that adding and removing parameters can be
3356	* done as we please. See FNIEMOP_DEF.
3357	*/
3358	#define FNIEMOP_CALL(a_pfn) (a_pfn)(pVCpu)
3359
3360	/**
3361	* Call a common opcode decoder function taking one extra argument.
3362	*
3363	* We're using macors for this so that adding and removing parameters can be
3364	* done as we please. See FNIEMOP_DEF_1.
3365	*/
3366	#define FNIEMOP_CALL_1(a_pfn, a0) (a_pfn)(pVCpu, a0)
3367
3368	/**
3369	* Call a common opcode decoder function taking one extra argument.
3370	*
3371	* We're using macors for this so that adding and removing parameters can be
3372	* done as we please. See FNIEMOP_DEF_1.
3373	*/
3374	#define FNIEMOP_CALL_2(a_pfn, a0, a1) (a_pfn)(pVCpu, a0, a1)
3375	/** @} */
3376
3377
3378	/** @name Misc Helpers
3379	* @{ */
3380
3381	/** Used to shut up GCC warnings about variables that 'may be used uninitialized'
3382	* due to GCC lacking knowledge about the value range of a switch. */
3383	#if RT_CPLUSPLUS_PREREQ(202000)
3384	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: [[unlikely]] AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
3385	#else
3386	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
3387	#endif
3388
3389	/** Variant of IEM_NOT_REACHED_DEFAULT_CASE_RET that returns a custom value. */
3390	#if RT_CPLUSPLUS_PREREQ(202000)
3391	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: [[unlikely]] AssertFailedReturn(a_RetValue)
3392	#else
3393	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: AssertFailedReturn(a_RetValue)
3394	#endif
3395
3396	/**
3397	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
3398	* occation.
3399	*/
3400	#ifdef LOG_ENABLED
3401	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
3402	do { \
3403	/Log/ LogAlways(("%s: returning IEM_RETURN_ASPECT_NOT_IMPLEMENTED (line %d)\n", __FUNCTION__, __LINE__)); \
3404	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
3405	} while (0)
3406	#else
3407	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
3408	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
3409	#endif
3410
3411	/**
3412	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
3413	* occation using the supplied logger statement.
3414	*
3415	* @param a_LoggerArgs What to log on failure.
3416	*/
3417	#ifdef LOG_ENABLED
3418	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
3419	do { \
3420	LogAlways((LOG_FN_FMT ": ", __PRETTY_FUNCTION__)); LogAlways(a_LoggerArgs); \
3421	/LogFunc(a_LoggerArgs);/ \
3422	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
3423	} while (0)
3424	#else
3425	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
3426	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
3427	#endif
3428
3429	/**
3430	* Check if we're currently executing in real or virtual 8086 mode.
3431	*
3432	* @returns @c true if it is, @c false if not.
3433	* @param a_pVCpu The IEM state of the current CPU.
3434	*/
3435	#define IEM_IS_REAL_OR_V86_MODE(a_pVCpu) (CPUMIsGuestInRealOrV86ModeEx(IEM_GET_CTX(a_pVCpu)))
3436
3437	/**
3438	* Check if we're currently executing in virtual 8086 mode.
3439	*
3440	* @returns @c true if it is, @c false if not.
3441	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3442	*/
3443	#define IEM_IS_V86_MODE(a_pVCpu) (CPUMIsGuestInV86ModeEx(IEM_GET_CTX(a_pVCpu)))
3444
3445	/**
3446	* Check if we're currently executing in long mode.
3447	*
3448	* @returns @c true if it is, @c false if not.
3449	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3450	*/
3451	#define IEM_IS_LONG_MODE(a_pVCpu) (CPUMIsGuestInLongModeEx(IEM_GET_CTX(a_pVCpu)))
3452
3453	/**
3454	* Check if we're currently executing in a 64-bit code segment.
3455	*
3456	* @returns @c true if it is, @c false if not.
3457	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3458	*/
3459	#define IEM_IS_64BIT_CODE(a_pVCpu) (CPUMIsGuestIn64BitCodeEx(IEM_GET_CTX(a_pVCpu)))
3460
3461	/**
3462	* Check if we're currently executing in real mode.
3463	*
3464	* @returns @c true if it is, @c false if not.
3465	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3466	*/
3467	#define IEM_IS_REAL_MODE(a_pVCpu) (CPUMIsGuestInRealModeEx(IEM_GET_CTX(a_pVCpu)))
3468
3469	/**
3470	* Returns a (const) pointer to the CPUMFEATURES for the guest CPU.
3471	* @returns PCCPUMFEATURES
3472	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3473	*/
3474	#define IEM_GET_GUEST_CPU_FEATURES(a_pVCpu) (&((a_pVCpu)->CTX_SUFF(pVM)->cpum.ro.GuestFeatures))
3475
3476	/**
3477	* Returns a (const) pointer to the CPUMFEATURES for the host CPU.
3478	* @returns PCCPUMFEATURES
3479	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3480	*/
3481	#define IEM_GET_HOST_CPU_FEATURES(a_pVCpu) (&g_CpumHostFeatures.s)
3482
3483	/**
3484	* Evaluates to true if we're presenting an Intel CPU to the guest.
3485	*/
3486	#define IEM_IS_GUEST_CPU_INTEL(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL )
3487
3488	/**
3489	* Evaluates to true if we're presenting an AMD CPU to the guest.
3490	*/
3491	#define IEM_IS_GUEST_CPU_AMD(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_AMD \|\| (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_HYGON )
3492
3493	/**
3494	* Check if the address is canonical.
3495	*/
3496	#define IEM_IS_CANONICAL(a_u64Addr) X86_IS_CANONICAL(a_u64Addr)
3497
3498	/** Checks if the ModR/M byte is in register mode or not. */
3499	#define IEM_IS_MODRM_REG_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT) )
3500	/** Checks if the ModR/M byte is in memory mode or not. */
3501	#define IEM_IS_MODRM_MEM_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT) )
3502
3503	/**
3504	* Gets the register (reg) part of a ModR/M encoding, with REX.R added in.
3505	*
3506	* For use during decoding.
3507	*/
3508	#define IEM_GET_MODRM_REG(a_pVCpu, a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| (a_pVCpu)->iem.s.uRexReg )
3509	/**
3510	* Gets the r/m part of a ModR/M encoding as a register index, with REX.B added in.
3511	*
3512	* For use during decoding.
3513	*/
3514	#define IEM_GET_MODRM_RM(a_pVCpu, a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) \| (a_pVCpu)->iem.s.uRexB )
3515
3516	/**
3517	* Gets the register (reg) part of a ModR/M encoding, without REX.R.
3518	*
3519	* For use during decoding.
3520	*/
3521	#define IEM_GET_MODRM_REG_8(a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) )
3522	/**
3523	* Gets the r/m part of a ModR/M encoding as a register index, without REX.B.
3524	*
3525	* For use during decoding.
3526	*/
3527	#define IEM_GET_MODRM_RM_8(a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) )
3528
3529	/**
3530	* Gets the effective VEX.VVVV value.
3531	*
3532	* The 4th bit is ignored if not 64-bit code.
3533	* @returns effective V-register value.
3534	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3535	*/
3536	#define IEM_GET_EFFECTIVE_VVVV(a_pVCpu) \
3537	((a_pVCpu)->iem.s.enmCpuMode == IEMMODE_64BIT ? (a_pVCpu)->iem.s.uVex3rdReg : (a_pVCpu)->iem.s.uVex3rdReg & 7)
3538
3539
3540	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
3541
3542	/**
3543	* Check if the guest has entered VMX root operation.
3544	*/
3545	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxRootMode(IEM_GET_CTX(a_pVCpu)))
3546
3547	/**
3548	* Check if the guest has entered VMX non-root operation.
3549	*/
3550	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxNonRootMode(IEM_GET_CTX(a_pVCpu)))
3551
3552	/**
3553	* Check if the nested-guest has the given Pin-based VM-execution control set.
3554	*/
3555	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_PinCtl) \
3556	(CPUMIsGuestVmxPinCtlsSet(IEM_GET_CTX(a_pVCpu), (a_PinCtl)))
3557
3558	/**
3559	* Check if the nested-guest has the given Processor-based VM-execution control set.
3560	*/
3561	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_ProcCtl) \
3562	(CPUMIsGuestVmxProcCtlsSet(IEM_GET_CTX(a_pVCpu), (a_ProcCtl)))
3563
3564	/**
3565	* Check if the nested-guest has the given Secondary Processor-based VM-execution
3566	* control set.
3567	*/
3568	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_ProcCtl2) \
3569	(CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(a_pVCpu), (a_ProcCtl2)))
3570
3571	/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
3572	# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
3573
3574	/** Whether a shadow VMCS is present for the given VCPU. */
3575	# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
3576
3577	/** Gets the VMXON region pointer. */
3578	# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
3579
3580	/** Gets the guest-physical address of the current VMCS for the given VCPU. */
3581	# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
3582
3583	/** Whether a current VMCS is present for the given VCPU. */
3584	# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
3585
3586	/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
3587	# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
3588	do \
3589	{ \
3590	Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
3591	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
3592	} while (0)
3593
3594	/** Clears any current VMCS for the given VCPU. */
3595	# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
3596	do \
3597	{ \
3598	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
3599	} while (0)
3600
3601	/**
3602	* Invokes the VMX VM-exit handler for an instruction intercept.
3603	*/
3604	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) \
3605	do { return iemVmxVmexitInstr((a_pVCpu), (a_uExitReason), (a_cbInstr)); } while (0)
3606
3607	/**
3608	* Invokes the VMX VM-exit handler for an instruction intercept where the
3609	* instruction provides additional VM-exit information.
3610	*/
3611	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) \
3612	do { return iemVmxVmexitInstrNeedsInfo((a_pVCpu), (a_uExitReason), (a_uInstrId), (a_cbInstr)); } while (0)
3613
3614	/**
3615	* Invokes the VMX VM-exit handler for a task switch.
3616	*/
3617	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) \
3618	do { return iemVmxVmexitTaskSwitch((a_pVCpu), (a_enmTaskSwitch), (a_SelNewTss), (a_cbInstr)); } while (0)
3619
3620	/**
3621	* Invokes the VMX VM-exit handler for MWAIT.
3622	*/
3623	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) \
3624	do { return iemVmxVmexitInstrMwait((a_pVCpu), (a_fMonitorArmed), (a_cbInstr)); } while (0)
3625
3626	/**
3627	* Invokes the VMX VM-exit handler for EPT faults.
3628	*/
3629	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) \
3630	do { return iemVmxVmexitEpt(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr); } while (0)
3631
3632	/**
3633	* Invokes the VMX VM-exit handler.
3634	*/
3635	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) \
3636	do { return iemVmxVmexit((a_pVCpu), (a_uExitReason), (a_uExitQual)); } while (0)
3637
3638	#else
3639	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (false)
3640	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (false)
3641	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_cbInstr) (false)
3642	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_cbInstr) (false)
3643	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_cbInstr) (false)
3644	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3645	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3646	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3647	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3648	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3649	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) do { return VERR_VMX_IPE_1; } while (0)
3650
3651	#endif
3652
3653	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
3654	/**
3655	* Check if an SVM control/instruction intercept is set.
3656	*/
3657	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) \
3658	(CPUMIsGuestSvmCtrlInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_Intercept)))
3659
3660	/**
3661	* Check if an SVM read CRx intercept is set.
3662	*/
3663	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
3664	(CPUMIsGuestSvmReadCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
3665
3666	/**
3667	* Check if an SVM write CRx intercept is set.
3668	*/
3669	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
3670	(CPUMIsGuestSvmWriteCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
3671
3672	/**
3673	* Check if an SVM read DRx intercept is set.
3674	*/
3675	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
3676	(CPUMIsGuestSvmReadDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
3677
3678	/**
3679	* Check if an SVM write DRx intercept is set.
3680	*/
3681	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
3682	(CPUMIsGuestSvmWriteDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
3683
3684	/**
3685	* Check if an SVM exception intercept is set.
3686	*/
3687	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) \
3688	(CPUMIsGuestSvmXcptInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uVector)))
3689
3690	/**
3691	* Invokes the SVM \#VMEXIT handler for the nested-guest.
3692	*/
3693	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
3694	do { return iemSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2)); } while (0)
3695
3696	/**
3697	* Invokes the 'MOV CRx' SVM \#VMEXIT handler after constructing the
3698	* corresponding decode assist information.
3699	*/
3700	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) \
3701	do \
3702	{ \
3703	uint64_t uExitInfo1; \
3704	if ( IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmDecodeAssists \
3705	&& (a_enmAccessCrX) == IEMACCESSCRX_MOV_CRX) \
3706	uExitInfo1 = SVM_EXIT1_MOV_CRX_MASK \| ((a_iGReg) & 7); \
3707	else \
3708	uExitInfo1 = 0; \
3709	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, uExitInfo1, 0); \
3710	} while (0)
3711
3712	/** Check and handles SVM nested-guest instruction intercept and updates
3713	* NRIP if needed.
3714	*/
3715	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
3716	do \
3717	{ \
3718	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept)) \
3719	{ \
3720	IEM_SVM_UPDATE_NRIP(a_pVCpu); \
3721	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2); \
3722	} \
3723	} while (0)
3724
3725	/** Checks and handles SVM nested-guest CR0 read intercept. */
3726	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2) \
3727	do \
3728	{ \
3729	if (!IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, 0)) \
3730	{ /* probably likely */ } \
3731	else \
3732	{ \
3733	IEM_SVM_UPDATE_NRIP(a_pVCpu); \
3734	IEM_SVM_VMEXIT_RET(a_pVCpu, SVM_EXIT_READ_CR0, a_uExitInfo1, a_uExitInfo2); \
3735	} \
3736	} while (0)
3737
3738	/**
3739	* Updates the NextRIP (NRI) field in the nested-guest VMCB.
3740	*/
3741	# define IEM_SVM_UPDATE_NRIP(a_pVCpu) \
3742	do { \
3743	if (IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmNextRipSave) \
3744	CPUMGuestSvmUpdateNRip(a_pVCpu, IEM_GET_CTX(a_pVCpu), IEM_GET_INSTR_LEN(a_pVCpu)); \
3745	} while (0)
3746
3747	#else
3748	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) (false)
3749	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
3750	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
3751	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
3752	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
3753	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) (false)
3754	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { return VERR_SVM_IPE_1; } while (0)
3755	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) do { return VERR_SVM_IPE_1; } while (0)
3756	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { } while (0)
3757	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2) do { } while (0)
3758	# define IEM_SVM_UPDATE_NRIP(a_pVCpu) do { } while (0)
3759
3760	#endif
3761
3762	/** @} */
3763
3764	void iemInitPendingBreakpointsSlow(PVMCPUCC pVCpu);
3765
3766
3767	/**
3768	* Selector descriptor table entry as fetched by iemMemFetchSelDesc.
3769	*/
3770	typedef union IEMSELDESC
3771	{
3772	/** The legacy view. */
3773	X86DESC Legacy;
3774	/** The long mode view. */
3775	X86DESC64 Long;
3776	} IEMSELDESC;
3777	/** Pointer to a selector descriptor table entry. */
3778	typedef IEMSELDESC *PIEMSELDESC;
3779
3780	/** @name Raising Exceptions.
3781	* @{ */
3782	VBOXSTRICTRC iemTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, uint32_t uNextEip, uint32_t fFlags,
3783	uint16_t uErr, uint64_t uCr2, RTSEL SelTSS, PIEMSELDESC pNewDescTSS) RT_NOEXCEPT;
3784
3785	VBOXSTRICTRC iemRaiseXcptOrInt(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags,
3786	uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
3787	#ifdef IEM_WITH_SETJMP
3788	DECL_NO_RETURN(void) iemRaiseXcptOrIntJmp(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector,
3789	uint32_t fFlags, uint16_t uErr, uint64_t uCr2) IEM_NOEXCEPT_MAY_LONGJMP;
3790	#endif
3791	VBOXSTRICTRC iemRaiseDivideError(PVMCPUCC pVCpu) RT_NOEXCEPT;
3792	VBOXSTRICTRC iemRaiseDebugException(PVMCPUCC pVCpu) RT_NOEXCEPT;
3793	VBOXSTRICTRC iemRaiseBoundRangeExceeded(PVMCPUCC pVCpu) RT_NOEXCEPT;
3794	VBOXSTRICTRC iemRaiseUndefinedOpcode(PVMCPUCC pVCpu) RT_NOEXCEPT;
3795	VBOXSTRICTRC iemRaiseDeviceNotAvailable(PVMCPUCC pVCpu) RT_NOEXCEPT;
3796	VBOXSTRICTRC iemRaiseTaskSwitchFaultWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
3797	VBOXSTRICTRC iemRaiseTaskSwitchFaultCurrentTSS(PVMCPUCC pVCpu) RT_NOEXCEPT;
3798	VBOXSTRICTRC iemRaiseTaskSwitchFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
3799	VBOXSTRICTRC iemRaiseTaskSwitchFaultBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
3800	/VBOXSTRICTRC iemRaiseSelectorNotPresent(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;/
3801	VBOXSTRICTRC iemRaiseSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
3802	VBOXSTRICTRC iemRaiseSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
3803	VBOXSTRICTRC iemRaiseStackSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
3804	VBOXSTRICTRC iemRaiseStackSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
3805	VBOXSTRICTRC iemRaiseGeneralProtectionFault(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
3806	VBOXSTRICTRC iemRaiseGeneralProtectionFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
3807	#ifdef IEM_WITH_SETJMP
3808	DECL_NO_RETURN(void) iemRaiseGeneralProtectionFault0Jmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
3809	#endif
3810	VBOXSTRICTRC iemRaiseGeneralProtectionFaultBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
3811	VBOXSTRICTRC iemRaiseNotCanonical(PVMCPUCC pVCpu) RT_NOEXCEPT;
3812	VBOXSTRICTRC iemRaiseSelectorBounds(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
3813	#ifdef IEM_WITH_SETJMP
3814	DECL_NO_RETURN(void) iemRaiseSelectorBoundsJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
3815	#endif
3816	VBOXSTRICTRC iemRaiseSelectorBoundsBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
3817	#ifdef IEM_WITH_SETJMP
3818	DECL_NO_RETURN(void) iemRaiseSelectorBoundsBySelectorJmp(PVMCPUCC pVCpu, RTSEL Sel) IEM_NOEXCEPT_MAY_LONGJMP;
3819	#endif
3820	VBOXSTRICTRC iemRaiseSelectorInvalidAccess(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
3821	#ifdef IEM_WITH_SETJMP
3822	DECL_NO_RETURN(void) iemRaiseSelectorInvalidAccessJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
3823	#endif
3824	VBOXSTRICTRC iemRaisePageFault(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) RT_NOEXCEPT;
3825	#ifdef IEM_WITH_SETJMP
3826	DECL_NO_RETURN(void) iemRaisePageFaultJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) IEM_NOEXCEPT_MAY_LONGJMP;
3827	#endif
3828	VBOXSTRICTRC iemRaiseMathFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
3829	VBOXSTRICTRC iemRaiseAlignmentCheckException(PVMCPUCC pVCpu) RT_NOEXCEPT;
3830	#ifdef IEM_WITH_SETJMP
3831	DECL_NO_RETURN(void) iemRaiseAlignmentCheckExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
3832	#endif
3833	VBOXSTRICTRC iemRaiseSimdFpException(PVMCPUCC pVCpu) RT_NOEXCEPT;
3834
3835	IEM_CIMPL_DEF_0(iemCImplRaiseDivideError);
3836	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidLockPrefix);
3837	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidOpcode);
3838
3839	/**
3840	* Macro for calling iemCImplRaiseDivideError().
3841	*
3842	* This enables us to add/remove arguments and force different levels of
3843	* inlining as we wish.
3844	*
3845	* @return Strict VBox status code.
3846	*/
3847	#define IEMOP_RAISE_DIVIDE_ERROR() IEM_MC_DEFER_TO_CIMPL_0(iemCImplRaiseDivideError)
3848
3849	/**
3850	* Macro for calling iemCImplRaiseInvalidLockPrefix().
3851	*
3852	* This enables us to add/remove arguments and force different levels of
3853	* inlining as we wish.
3854	*
3855	* @return Strict VBox status code.
3856	*/
3857	#define IEMOP_RAISE_INVALID_LOCK_PREFIX() IEM_MC_DEFER_TO_CIMPL_0(iemCImplRaiseInvalidLockPrefix)
3858
3859	/**
3860	* Macro for calling iemCImplRaiseInvalidOpcode().
3861	*
3862	* This enables us to add/remove arguments and force different levels of
3863	* inlining as we wish.
3864	*
3865	* @return Strict VBox status code.
3866	*/
3867	#define IEMOP_RAISE_INVALID_OPCODE() IEM_MC_DEFER_TO_CIMPL_0(iemCImplRaiseInvalidOpcode)
3868	/** @} */
3869
3870	/** @name Register Access.
3871	* @{ */
3872	VBOXSTRICTRC iemRegRipRelativeJumpS8AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int8_t offNextInstr,
3873	IEMMODE enmEffOpSize) RT_NOEXCEPT;
3874	VBOXSTRICTRC iemRegRipRelativeJumpS16AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int16_t offNextInstr) RT_NOEXCEPT;
3875	VBOXSTRICTRC iemRegRipRelativeJumpS32AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int32_t offNextInstr,
3876	IEMMODE enmEffOpSize) RT_NOEXCEPT;
3877	VBOXSTRICTRC iemRegRipJumpU16AndFinishClearningRF(PVMCPUCC pVCpu, uint16_t uNewRip) RT_NOEXCEPT;
3878	VBOXSTRICTRC iemRegRipJumpU32AndFinishClearningRF(PVMCPUCC pVCpu, uint32_t uNewRip) RT_NOEXCEPT;
3879	VBOXSTRICTRC iemRegRipJumpU64AndFinishClearningRF(PVMCPUCC pVCpu, uint64_t uNewRip) RT_NOEXCEPT;
3880	/** @} */
3881
3882	/** @name FPU access and helpers.
3883	* @{ */
3884	void iemFpuPushResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult) RT_NOEXCEPT;
3885	void iemFpuPushResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3886	void iemFpuPushResultTwo(PVMCPUCC pVCpu, PIEMFPURESULTTWO pResult) RT_NOEXCEPT;
3887	void iemFpuStoreResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg) RT_NOEXCEPT;
3888	void iemFpuStoreResultThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg) RT_NOEXCEPT;
3889	void iemFpuStoreResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
3890	uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3891	void iemFpuStoreResultWithMemOpThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
3892	uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3893	void iemFpuUpdateOpcodeAndIp(PVMCPUCC pVCpu) RT_NOEXCEPT;
3894	void iemFpuUpdateFSW(PVMCPUCC pVCpu, uint16_t u16FSW) RT_NOEXCEPT;
3895	void iemFpuUpdateFSWThenPop(PVMCPUCC pVCpu, uint16_t u16FSW) RT_NOEXCEPT;
3896	void iemFpuUpdateFSWWithMemOp(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3897	void iemFpuUpdateFSWThenPopPop(PVMCPUCC pVCpu, uint16_t u16FSW) RT_NOEXCEPT;
3898	void iemFpuUpdateFSWWithMemOpThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3899	void iemFpuStackUnderflow(PVMCPUCC pVCpu, uint8_t iStReg) RT_NOEXCEPT;
3900	void iemFpuStackUnderflowWithMemOp(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3901	void iemFpuStackUnderflowThenPop(PVMCPUCC pVCpu, uint8_t iStReg) RT_NOEXCEPT;
3902	void iemFpuStackUnderflowWithMemOpThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3903	void iemFpuStackUnderflowThenPopPop(PVMCPUCC pVCpu) RT_NOEXCEPT;
3904	void iemFpuStackPushUnderflow(PVMCPUCC pVCpu) RT_NOEXCEPT;
3905	void iemFpuStackPushUnderflowTwo(PVMCPUCC pVCpu) RT_NOEXCEPT;
3906	void iemFpuStackPushOverflow(PVMCPUCC pVCpu) RT_NOEXCEPT;
3907	void iemFpuStackPushOverflowWithMemOp(PVMCPUCC pVCpu, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3908	/** @} */
3909
3910	/** @name SSE+AVX SIMD access and helpers.
3911	* @{ */
3912	void iemSseStoreResult(PVMCPUCC pVCpu, PCIEMSSERESULT pResult, uint8_t iXmmReg) RT_NOEXCEPT;
3913	void iemSseUpdateMxcsr(PVMCPUCC pVCpu, uint32_t fMxcsr) RT_NOEXCEPT;
3914	/** @} */
3915
3916	/** @name Memory access.
3917	* @{ */
3918
3919	/** Report a \#GP instead of \#AC and do not restrict to ring-3 */
3920	#define IEM_MEMMAP_F_ALIGN_GP RT_BIT_32(16)
3921	/** SSE access that should report a \#GP instead of \#AC, unless MXCSR.MM=1
3922	* when it works like normal \#AC. Always used with IEM_MEMMAP_F_ALIGN_GP. */
3923	#define IEM_MEMMAP_F_ALIGN_SSE RT_BIT_32(17)
3924	/** If \#AC is applicable, raise it. Always used with IEM_MEMMAP_F_ALIGN_GP.
3925	* Users include FXSAVE & FXRSTOR. */
3926	#define IEM_MEMMAP_F_ALIGN_GP_OR_AC RT_BIT_32(18)
3927
3928	VBOXSTRICTRC iemMemMap(PVMCPUCC pVCpu, void **ppvMem, size_t cbMem, uint8_t iSegReg, RTGCPTR GCPtrMem,
3929	uint32_t fAccess, uint32_t uAlignCtl) RT_NOEXCEPT;
3930	VBOXSTRICTRC iemMemCommitAndUnmap(PVMCPUCC pVCpu, void *pvMem, uint32_t fAccess) RT_NOEXCEPT;
3931	#ifndef IN_RING3
3932	VBOXSTRICTRC iemMemCommitAndUnmapPostponeTroubleToR3(PVMCPUCC pVCpu, void *pvMem, uint32_t fAccess) RT_NOEXCEPT;
3933	#endif
3934	void iemMemRollback(PVMCPUCC pVCpu) RT_NOEXCEPT;
3935	VBOXSTRICTRC iemMemApplySegment(PVMCPUCC pVCpu, uint32_t fAccess, uint8_t iSegReg, size_t cbMem, PRTGCPTR pGCPtrMem) RT_NOEXCEPT;
3936	VBOXSTRICTRC iemMemMarkSelDescAccessed(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
3937	VBOXSTRICTRC iemMemPageTranslateAndCheckAccess(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t cbAccess, uint32_t fAccess, PRTGCPHYS pGCPhysMem) RT_NOEXCEPT;
3938
3939	#ifdef IEM_WITH_CODE_TLB
3940	void iemOpcodeFetchBytesJmp(PVMCPUCC pVCpu, size_t cbDst, void *pvDst) IEM_NOEXCEPT_MAY_LONGJMP;
3941	#else
3942	VBOXSTRICTRC iemOpcodeFetchMoreBytes(PVMCPUCC pVCpu, size_t cbMin) RT_NOEXCEPT;
3943	#endif
3944	#ifdef IEM_WITH_SETJMP
3945	uint8_t iemOpcodeGetNextU8SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
3946	uint16_t iemOpcodeGetNextU16SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
3947	uint32_t iemOpcodeGetNextU32SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
3948	uint64_t iemOpcodeGetNextU64SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
3949	#else
3950	VBOXSTRICTRC iemOpcodeGetNextU8Slow(PVMCPUCC pVCpu, uint8_t *pb) RT_NOEXCEPT;
3951	VBOXSTRICTRC iemOpcodeGetNextS8SxU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
3952	VBOXSTRICTRC iemOpcodeGetNextS8SxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
3953	VBOXSTRICTRC iemOpcodeGetNextS8SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
3954	VBOXSTRICTRC iemOpcodeGetNextU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
3955	VBOXSTRICTRC iemOpcodeGetNextU16ZxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
3956	VBOXSTRICTRC iemOpcodeGetNextU16ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
3957	VBOXSTRICTRC iemOpcodeGetNextU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
3958	VBOXSTRICTRC iemOpcodeGetNextU32ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
3959	VBOXSTRICTRC iemOpcodeGetNextS32SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
3960	VBOXSTRICTRC iemOpcodeGetNextU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
3961	#endif
3962
3963	VBOXSTRICTRC iemMemFetchDataU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3964	VBOXSTRICTRC iemMemFetchDataU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3965	VBOXSTRICTRC iemMemFetchDataU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3966	VBOXSTRICTRC iemMemFetchDataU32_ZX_U64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3967	VBOXSTRICTRC iemMemFetchDataU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3968	VBOXSTRICTRC iemMemFetchDataU64AlignedU128(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3969	VBOXSTRICTRC iemMemFetchDataR80(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3970	VBOXSTRICTRC iemMemFetchDataD80(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3971	VBOXSTRICTRC iemMemFetchDataU128(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3972	VBOXSTRICTRC iemMemFetchDataU128AlignedSse(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3973	VBOXSTRICTRC iemMemFetchDataU256(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3974	VBOXSTRICTRC iemMemFetchDataU256AlignedSse(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3975	VBOXSTRICTRC iemMemFetchDataXdtr(PVMCPUCC pVCpu, uint16_t *pcbLimit, PRTGCPTR pGCPtrBase, uint8_t iSegReg,
3976	RTGCPTR GCPtrMem, IEMMODE enmOpSize) RT_NOEXCEPT;
3977	#ifdef IEM_WITH_SETJMP
3978	uint8_t iemMemFetchDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
3979	uint16_t iemMemFetchDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
3980	uint32_t iemMemFetchDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
3981	uint64_t iemMemFetchDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
3982	uint64_t iemMemFetchDataU64AlignedU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
3983	void iemMemFetchDataR80Jmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
3984	void iemMemFetchDataD80Jmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
3985	void iemMemFetchDataU128Jmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
3986	void iemMemFetchDataU128AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
3987	void iemMemFetchDataU256Jmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
3988	void iemMemFetchDataU256AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
3989	#endif
3990
3991	VBOXSTRICTRC iemMemFetchSysU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3992	VBOXSTRICTRC iemMemFetchSysU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3993	VBOXSTRICTRC iemMemFetchSysU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3994	VBOXSTRICTRC iemMemFetchSysU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3995	VBOXSTRICTRC iemMemFetchSelDesc(PVMCPUCC pVCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt) RT_NOEXCEPT;
3996
3997	VBOXSTRICTRC iemMemStoreDataU8(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) RT_NOEXCEPT;
3998	VBOXSTRICTRC iemMemStoreDataU16(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) RT_NOEXCEPT;
3999	VBOXSTRICTRC iemMemStoreDataU32(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) RT_NOEXCEPT;
4000	VBOXSTRICTRC iemMemStoreDataU64(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) RT_NOEXCEPT;
4001	VBOXSTRICTRC iemMemStoreDataU128(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
4002	VBOXSTRICTRC iemMemStoreDataU128AlignedSse(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
4003	VBOXSTRICTRC iemMemStoreDataU256(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
4004	VBOXSTRICTRC iemMemStoreDataU256AlignedAvx(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
4005	VBOXSTRICTRC iemMemStoreDataXdtr(PVMCPUCC pVCpu, uint16_t cbLimit, RTGCPTR GCPtrBase, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4006	#ifdef IEM_WITH_SETJMP
4007	void iemMemStoreDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
4008	void iemMemStoreDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
4009	void iemMemStoreDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
4010	void iemMemStoreDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
4011	void iemMemStoreDataU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
4012	void iemMemStoreDataU128AlignedSseJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
4013	void iemMemStoreDataU256Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
4014	void iemMemStoreDataU256AlignedAvxJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
4015	#endif
4016
4017	VBOXSTRICTRC iemMemStackPushBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
4018	void *ppvMem, uint64_t puNewRsp) RT_NOEXCEPT;
4019	VBOXSTRICTRC iemMemStackPushCommitSpecial(PVMCPUCC pVCpu, void *pvMem, uint64_t uNewRsp) RT_NOEXCEPT;
4020	VBOXSTRICTRC iemMemStackPushU16(PVMCPUCC pVCpu, uint16_t u16Value) RT_NOEXCEPT;
4021	VBOXSTRICTRC iemMemStackPushU32(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
4022	VBOXSTRICTRC iemMemStackPushU64(PVMCPUCC pVCpu, uint64_t u64Value) RT_NOEXCEPT;
4023	VBOXSTRICTRC iemMemStackPushU16Ex(PVMCPUCC pVCpu, uint16_t u16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4024	VBOXSTRICTRC iemMemStackPushU32Ex(PVMCPUCC pVCpu, uint32_t u32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4025	VBOXSTRICTRC iemMemStackPushU64Ex(PVMCPUCC pVCpu, uint64_t u64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4026	VBOXSTRICTRC iemMemStackPushU32SReg(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
4027	VBOXSTRICTRC iemMemStackPopBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
4028	void const *ppvMem, uint64_t puNewRsp) RT_NOEXCEPT;
4029	VBOXSTRICTRC iemMemStackPopContinueSpecial(PVMCPUCC pVCpu, size_t off, size_t cbMem,
4030	void const **ppvMem, uint64_t uCurNewRsp) RT_NOEXCEPT;
4031	VBOXSTRICTRC iemMemStackPopDoneSpecial(PVMCPUCC pVCpu, void const *pvMem) RT_NOEXCEPT;
4032	VBOXSTRICTRC iemMemStackPopU16(PVMCPUCC pVCpu, uint16_t *pu16Value) RT_NOEXCEPT;
4033	VBOXSTRICTRC iemMemStackPopU32(PVMCPUCC pVCpu, uint32_t *pu32Value) RT_NOEXCEPT;
4034	VBOXSTRICTRC iemMemStackPopU64(PVMCPUCC pVCpu, uint64_t *pu64Value) RT_NOEXCEPT;
4035	VBOXSTRICTRC iemMemStackPopU16Ex(PVMCPUCC pVCpu, uint16_t *pu16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4036	VBOXSTRICTRC iemMemStackPopU32Ex(PVMCPUCC pVCpu, uint32_t *pu32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4037	VBOXSTRICTRC iemMemStackPopU64Ex(PVMCPUCC pVCpu, uint64_t *pu64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4038	/** @} */
4039
4040	/** @name IEMAllCImpl.cpp
4041	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/'
4042	* @{ */
4043	IEM_CIMPL_PROTO_0(iemCImpl_popa_16);
4044	IEM_CIMPL_PROTO_0(iemCImpl_popa_32);
4045	IEM_CIMPL_PROTO_0(iemCImpl_pusha_16);
4046	IEM_CIMPL_PROTO_0(iemCImpl_pusha_32);
4047	IEM_CIMPL_PROTO_1(iemCImpl_pushf, IEMMODE, enmEffOpSize);
4048	IEM_CIMPL_PROTO_1(iemCImpl_popf, IEMMODE, enmEffOpSize);
4049	IEM_CIMPL_PROTO_1(iemCImpl_call_16, uint16_t, uNewPC);
4050	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_16, int16_t, offDisp);
4051	IEM_CIMPL_PROTO_1(iemCImpl_call_32, uint32_t, uNewPC);
4052	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_32, int32_t, offDisp);
4053	IEM_CIMPL_PROTO_1(iemCImpl_call_64, uint64_t, uNewPC);
4054	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_64, int64_t, offDisp);
4055	IEM_CIMPL_PROTO_3(iemCImpl_FarJmp, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
4056	IEM_CIMPL_PROTO_3(iemCImpl_callf, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
4057	IEM_CIMPL_PROTO_2(iemCImpl_retf, IEMMODE, enmEffOpSize, uint16_t, cbPop);
4058	IEM_CIMPL_PROTO_0(iemCImpl_retn_16);
4059	IEM_CIMPL_PROTO_0(iemCImpl_retn_32);
4060	IEM_CIMPL_PROTO_0(iemCImpl_retn_64);
4061	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_16, uint16_t, cbPop);
4062	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_32, uint16_t, cbPop);
4063	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_64, uint16_t, cbPop);
4064	IEM_CIMPL_PROTO_3(iemCImpl_enter, IEMMODE, enmEffOpSize, uint16_t, cbFrame, uint8_t, cParameters);
4065	IEM_CIMPL_PROTO_1(iemCImpl_leave, IEMMODE, enmEffOpSize);
4066	IEM_CIMPL_PROTO_2(iemCImpl_int, uint8_t, u8Int, IEMINT, enmInt);
4067	IEM_CIMPL_PROTO_1(iemCImpl_iret_real_v8086, IEMMODE, enmEffOpSize);
4068	IEM_CIMPL_PROTO_4(iemCImpl_iret_prot_v8086, uint32_t, uNewEip, uint16_t, uNewCs, uint32_t, uNewFlags, uint64_t, uNewRsp);
4069	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot_NestedTask, IEMMODE, enmEffOpSize);
4070	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot, IEMMODE, enmEffOpSize);
4071	IEM_CIMPL_PROTO_1(iemCImpl_iret_64bit, IEMMODE, enmEffOpSize);
4072	IEM_CIMPL_PROTO_1(iemCImpl_iret, IEMMODE, enmEffOpSize);
4073	IEM_CIMPL_PROTO_0(iemCImpl_loadall286);
4074	IEM_CIMPL_PROTO_0(iemCImpl_syscall);
4075	IEM_CIMPL_PROTO_0(iemCImpl_sysret);
4076	IEM_CIMPL_PROTO_0(iemCImpl_sysenter);
4077	IEM_CIMPL_PROTO_1(iemCImpl_sysexit, IEMMODE, enmEffOpSize);
4078	IEM_CIMPL_PROTO_2(iemCImpl_LoadSReg, uint8_t, iSegReg, uint16_t, uSel);
4079	IEM_CIMPL_PROTO_2(iemCImpl_load_SReg, uint8_t, iSegReg, uint16_t, uSel);
4080	IEM_CIMPL_PROTO_2(iemCImpl_pop_Sreg, uint8_t, iSegReg, IEMMODE, enmEffOpSize);
4081	IEM_CIMPL_PROTO_5(iemCImpl_load_SReg_Greg, uint16_t, uSel, uint64_t, offSeg, uint8_t, iSegReg, uint8_t, iGReg, IEMMODE, enmEffOpSize);
4082	IEM_CIMPL_PROTO_2(iemCImpl_VerX, uint16_t, uSel, bool, fWrite);
4083	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u64, uint64_t *, pu64Dst, uint16_t, uSel, bool, fIsLar);
4084	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u16, uint16_t *, pu16Dst, uint16_t, uSel, bool, fIsLar);
4085	IEM_CIMPL_PROTO_3(iemCImpl_lgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
4086	IEM_CIMPL_PROTO_2(iemCImpl_sgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4087	IEM_CIMPL_PROTO_3(iemCImpl_lidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
4088	IEM_CIMPL_PROTO_2(iemCImpl_sidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4089	IEM_CIMPL_PROTO_1(iemCImpl_lldt, uint16_t, uNewLdt);
4090	IEM_CIMPL_PROTO_2(iemCImpl_sldt_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
4091	IEM_CIMPL_PROTO_2(iemCImpl_sldt_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4092	IEM_CIMPL_PROTO_1(iemCImpl_ltr, uint16_t, uNewTr);
4093	IEM_CIMPL_PROTO_2(iemCImpl_str_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
4094	IEM_CIMPL_PROTO_2(iemCImpl_str_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4095	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Cd, uint8_t, iGReg, uint8_t, iCrReg);
4096	IEM_CIMPL_PROTO_2(iemCImpl_smsw_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
4097	IEM_CIMPL_PROTO_2(iemCImpl_smsw_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4098	IEM_CIMPL_PROTO_4(iemCImpl_load_CrX, uint8_t, iCrReg, uint64_t, uNewCrX, IEMACCESSCRX, enmAccessCrX, uint8_t, iGReg);
4099	IEM_CIMPL_PROTO_2(iemCImpl_mov_Cd_Rd, uint8_t, iCrReg, uint8_t, iGReg);
4100	IEM_CIMPL_PROTO_2(iemCImpl_lmsw, uint16_t, u16NewMsw, RTGCPTR, GCPtrEffDst);
4101	IEM_CIMPL_PROTO_0(iemCImpl_clts);
4102	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Dd, uint8_t, iGReg, uint8_t, iDrReg);
4103	IEM_CIMPL_PROTO_2(iemCImpl_mov_Dd_Rd, uint8_t, iDrReg, uint8_t, iGReg);
4104	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Td, uint8_t, iGReg, uint8_t, iTrReg);
4105	IEM_CIMPL_PROTO_2(iemCImpl_mov_Td_Rd, uint8_t, iTrReg, uint8_t, iGReg);
4106	IEM_CIMPL_PROTO_1(iemCImpl_invlpg, RTGCPTR, GCPtrPage);
4107	IEM_CIMPL_PROTO_3(iemCImpl_invpcid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvpcidDesc, uint64_t, uInvpcidType);
4108	IEM_CIMPL_PROTO_0(iemCImpl_invd);
4109	IEM_CIMPL_PROTO_0(iemCImpl_wbinvd);
4110	IEM_CIMPL_PROTO_0(iemCImpl_rsm);
4111	IEM_CIMPL_PROTO_0(iemCImpl_rdtsc);
4112	IEM_CIMPL_PROTO_0(iemCImpl_rdtscp);
4113	IEM_CIMPL_PROTO_0(iemCImpl_rdpmc);
4114	IEM_CIMPL_PROTO_0(iemCImpl_rdmsr);
4115	IEM_CIMPL_PROTO_0(iemCImpl_wrmsr);
4116	IEM_CIMPL_PROTO_3(iemCImpl_in, uint16_t, u16Port, bool, fImm, uint8_t, cbReg);
4117	IEM_CIMPL_PROTO_1(iemCImpl_in_eAX_DX, uint8_t, cbReg);
4118	IEM_CIMPL_PROTO_3(iemCImpl_out, uint16_t, u16Port, bool, fImm, uint8_t, cbReg);
4119	IEM_CIMPL_PROTO_1(iemCImpl_out_DX_eAX, uint8_t, cbReg);
4120	IEM_CIMPL_PROTO_0(iemCImpl_cli);
4121	IEM_CIMPL_PROTO_0(iemCImpl_sti);
4122	IEM_CIMPL_PROTO_0(iemCImpl_hlt);
4123	IEM_CIMPL_PROTO_1(iemCImpl_monitor, uint8_t, iEffSeg);
4124	IEM_CIMPL_PROTO_0(iemCImpl_mwait);
4125	IEM_CIMPL_PROTO_0(iemCImpl_swapgs);
4126	IEM_CIMPL_PROTO_0(iemCImpl_cpuid);
4127	IEM_CIMPL_PROTO_1(iemCImpl_aad, uint8_t, bImm);
4128	IEM_CIMPL_PROTO_1(iemCImpl_aam, uint8_t, bImm);
4129	IEM_CIMPL_PROTO_0(iemCImpl_daa);
4130	IEM_CIMPL_PROTO_0(iemCImpl_das);
4131	IEM_CIMPL_PROTO_0(iemCImpl_aaa);
4132	IEM_CIMPL_PROTO_0(iemCImpl_aas);
4133	IEM_CIMPL_PROTO_3(iemCImpl_bound_16, int16_t, idxArray, int16_t, idxLowerBound, int16_t, idxUpperBound);
4134	IEM_CIMPL_PROTO_3(iemCImpl_bound_32, int32_t, idxArray, int32_t, idxLowerBound, int32_t, idxUpperBound);
4135	IEM_CIMPL_PROTO_0(iemCImpl_xgetbv);
4136	IEM_CIMPL_PROTO_0(iemCImpl_xsetbv);
4137	IEM_CIMPL_PROTO_4(iemCImpl_cmpxchg16b_fallback_rendezvous, PRTUINT128U, pu128Dst, PRTUINT128U, pu128RaxRdx,
4138	PRTUINT128U, pu128RbxRcx, uint32_t *, pEFlags);
4139	IEM_CIMPL_PROTO_2(iemCImpl_clflush_clflushopt, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
4140	IEM_CIMPL_PROTO_1(iemCImpl_finit, bool, fCheckXcpts);
4141	IEM_CIMPL_PROTO_3(iemCImpl_fxsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
4142	IEM_CIMPL_PROTO_3(iemCImpl_fxrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
4143	IEM_CIMPL_PROTO_3(iemCImpl_xsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
4144	IEM_CIMPL_PROTO_3(iemCImpl_xrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
4145	IEM_CIMPL_PROTO_2(iemCImpl_stmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
4146	IEM_CIMPL_PROTO_2(iemCImpl_vstmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
4147	IEM_CIMPL_PROTO_2(iemCImpl_ldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
4148	IEM_CIMPL_PROTO_3(iemCImpl_fnstenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4149	IEM_CIMPL_PROTO_3(iemCImpl_fnsave, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4150	IEM_CIMPL_PROTO_3(iemCImpl_fldenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
4151	IEM_CIMPL_PROTO_3(iemCImpl_frstor, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
4152	IEM_CIMPL_PROTO_1(iemCImpl_fldcw, uint16_t, u16Fcw);
4153	IEM_CIMPL_PROTO_1(iemCImpl_fxch_underflow, uint8_t, iStReg);
4154	IEM_CIMPL_PROTO_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, PFNIEMAIMPLFPUR80EFL, pfnAImpl, bool, fPop);
4155	/** @} */
4156
4157	/** @name IEMAllCImplStrInstr.cpp.h
4158	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/' -e 's/RT_CONCAT4(//' \
4159	* -e 's/,ADDR_SIZE)/64/g' -e 's/,OP_SIZE,/64/g' -e 's/,OP_rAX,/rax/g' IEMAllCImplStrInstr.cpp.h
4160	* @{ */
4161	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr16, uint8_t, iEffSeg);
4162	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr16, uint8_t, iEffSeg);
4163	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m16);
4164	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m16);
4165	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr16, uint8_t, iEffSeg);
4166	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m16);
4167	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m16, int8_t, iEffSeg);
4168	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr16, bool, fIoChecked);
4169	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr16, bool, fIoChecked);
4170	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4171	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4172
4173	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr16, uint8_t, iEffSeg);
4174	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr16, uint8_t, iEffSeg);
4175	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m16);
4176	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m16);
4177	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr16, uint8_t, iEffSeg);
4178	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m16);
4179	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m16, int8_t, iEffSeg);
4180	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr16, bool, fIoChecked);
4181	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr16, bool, fIoChecked);
4182	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4183	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4184
4185	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr16, uint8_t, iEffSeg);
4186	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr16, uint8_t, iEffSeg);
4187	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m16);
4188	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m16);
4189	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr16, uint8_t, iEffSeg);
4190	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m16);
4191	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m16, int8_t, iEffSeg);
4192	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr16, bool, fIoChecked);
4193	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr16, bool, fIoChecked);
4194	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4195	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4196
4197
4198	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr32, uint8_t, iEffSeg);
4199	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr32, uint8_t, iEffSeg);
4200	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m32);
4201	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m32);
4202	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr32, uint8_t, iEffSeg);
4203	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m32);
4204	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m32, int8_t, iEffSeg);
4205	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr32, bool, fIoChecked);
4206	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr32, bool, fIoChecked);
4207	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4208	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4209
4210	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr32, uint8_t, iEffSeg);
4211	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr32, uint8_t, iEffSeg);
4212	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m32);
4213	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m32);
4214	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr32, uint8_t, iEffSeg);
4215	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m32);
4216	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m32, int8_t, iEffSeg);
4217	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr32, bool, fIoChecked);
4218	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr32, bool, fIoChecked);
4219	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4220	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4221
4222	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr32, uint8_t, iEffSeg);
4223	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr32, uint8_t, iEffSeg);
4224	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m32);
4225	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m32);
4226	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr32, uint8_t, iEffSeg);
4227	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m32);
4228	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m32, int8_t, iEffSeg);
4229	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr32, bool, fIoChecked);
4230	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr32, bool, fIoChecked);
4231	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4232	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4233
4234	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr32, uint8_t, iEffSeg);
4235	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr32, uint8_t, iEffSeg);
4236	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m32);
4237	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m32);
4238	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr32, uint8_t, iEffSeg);
4239	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m32);
4240	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m32, int8_t, iEffSeg);
4241	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr32, bool, fIoChecked);
4242	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr32, bool, fIoChecked);
4243	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4244	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4245
4246
4247	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr64, uint8_t, iEffSeg);
4248	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr64, uint8_t, iEffSeg);
4249	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m64);
4250	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m64);
4251	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr64, uint8_t, iEffSeg);
4252	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m64);
4253	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m64, int8_t, iEffSeg);
4254	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr64, bool, fIoChecked);
4255	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr64, bool, fIoChecked);
4256	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4257	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4258
4259	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr64, uint8_t, iEffSeg);
4260	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr64, uint8_t, iEffSeg);
4261	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m64);
4262	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m64);
4263	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr64, uint8_t, iEffSeg);
4264	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m64);
4265	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m64, int8_t, iEffSeg);
4266	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr64, bool, fIoChecked);
4267	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr64, bool, fIoChecked);
4268	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4269	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4270
4271	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr64, uint8_t, iEffSeg);
4272	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr64, uint8_t, iEffSeg);
4273	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m64);
4274	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m64);
4275	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr64, uint8_t, iEffSeg);
4276	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m64);
4277	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m64, int8_t, iEffSeg);
4278	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr64, bool, fIoChecked);
4279	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr64, bool, fIoChecked);
4280	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4281	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4282
4283	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr64, uint8_t, iEffSeg);
4284	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr64, uint8_t, iEffSeg);
4285	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m64);
4286	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m64);
4287	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr64, uint8_t, iEffSeg);
4288	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m64);
4289	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m64, int8_t, iEffSeg);
4290	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr64, bool, fIoChecked);
4291	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr64, bool, fIoChecked);
4292	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4293	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4294	/** @} */
4295
4296	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
4297	VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT;
4298	VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT;
4299	VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT;
4300	VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT;
4301	VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT;
4302	VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
4303	VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALK pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT;
4304	VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT;
4305	VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT;
4306	VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
4307	bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT;
4308	VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
4309	bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT;
4310	VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4311	VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4312	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4313	VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4314	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4315	VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4316	VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT;
4317	VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
4318	RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT;
4319	VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT;
4320	VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT;
4321	VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT;
4322	uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT;
4323	void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT;
4324	VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
4325	uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT;
4326	bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT;
4327	IEM_CIMPL_PROTO_0(iemCImpl_vmxoff);
4328	IEM_CIMPL_PROTO_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon);
4329	IEM_CIMPL_PROTO_0(iemCImpl_vmlaunch);
4330	IEM_CIMPL_PROTO_0(iemCImpl_vmresume);
4331	IEM_CIMPL_PROTO_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
4332	IEM_CIMPL_PROTO_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
4333	IEM_CIMPL_PROTO_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
4334	IEM_CIMPL_PROTO_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField);
4335	IEM_CIMPL_PROTO_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField);
4336	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField);
4337	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg32, uint64_t *, pu32Dst, uint32_t, u32VmcsField);
4338	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField);
4339	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField);
4340	IEM_CIMPL_PROTO_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType);
4341	IEM_CIMPL_PROTO_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType);
4342	IEM_CIMPL_PROTO_0(iemCImpl_vmx_pause);
4343	#endif
4344
4345	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4346	VBOXSTRICTRC iemSvmVmexit(PVMCPUCC pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2) RT_NOEXCEPT;
4347	VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPUCC pVCpu, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr, uint64_t uCr2) RT_NOEXCEPT;
4348	VBOXSTRICTRC iemSvmHandleIOIntercept(PVMCPUCC pVCpu, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
4349	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, uint8_t cbInstr) RT_NOEXCEPT;
4350	VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPUCC pVCpu, uint32_t idMsr, bool fWrite) RT_NOEXCEPT;
4351	IEM_CIMPL_PROTO_0(iemCImpl_vmrun);
4352	IEM_CIMPL_PROTO_0(iemCImpl_vmload);
4353	IEM_CIMPL_PROTO_0(iemCImpl_vmsave);
4354	IEM_CIMPL_PROTO_0(iemCImpl_clgi);
4355	IEM_CIMPL_PROTO_0(iemCImpl_stgi);
4356	IEM_CIMPL_PROTO_0(iemCImpl_invlpga);
4357	IEM_CIMPL_PROTO_0(iemCImpl_skinit);
4358	IEM_CIMPL_PROTO_0(iemCImpl_svm_pause);
4359	#endif
4360
4361	IEM_CIMPL_PROTO_0(iemCImpl_vmcall); /* vmx */
4362	IEM_CIMPL_PROTO_0(iemCImpl_vmmcall); /* svm */
4363	IEM_CIMPL_PROTO_1(iemCImpl_Hypercall, uint16_t, uDisOpcode); /* both */
4364
4365
4366	extern const PFNIEMOP g_apfnIemInterpretOnlyOneByteMap[256];
4367
4368	/** @} */
4369
4370	RT_C_DECLS_END
4371
4372	#endif /* !VMM_INCLUDED_SRC_include_IEMInternal_h */
4373

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source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h@ 98915

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