IEMInternal.h@ 100231

Last change on this file since 100231 was 100231, checked in by vboxsync, 21 months ago
VMM/IEM: Recompiler fixes. Gets thru the bios now. bugref:10369
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1	/* $Id: IEMInternal.h 100231 2023-06-20 23:10:27Z vboxsync $ */
2	/** @file
3	* IEM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2011-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_IEMInternal_h
29	#define VMM_INCLUDED_SRC_include_IEMInternal_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#include <VBox/vmm/cpum.h>
35	#include <VBox/vmm/iem.h>
36	#include <VBox/vmm/pgm.h>
37	#include <VBox/vmm/stam.h>
38	#include <VBox/param.h>
39
40	#include <iprt/setjmp-without-sigmask.h>
41
42
43	RT_C_DECLS_BEGIN
44
45
46	/** @defgroup grp_iem_int Internals
47	* @ingroup grp_iem
48	* @internal
49	* @{
50	*/
51
52	/** For expanding symbol in slickedit and other products tagging and
53	* crossreferencing IEM symbols. */
54	#ifndef IEM_STATIC
55	# define IEM_STATIC static
56	#endif
57
58	/** @def IEM_WITH_SETJMP
59	* Enables alternative status code handling using setjmps.
60	*
61	* This adds a bit of expense via the setjmp() call since it saves all the
62	* non-volatile registers. However, it eliminates return code checks and allows
63	* for more optimal return value passing (return regs instead of stack buffer).
64	*/
65	#if defined(DOXYGEN_RUNNING) \|\| defined(RT_OS_WINDOWS) \|\| 1
66	# define IEM_WITH_SETJMP
67	#endif
68
69	/** @def IEM_WITH_THROW_CATCH
70	* Enables using C++ throw/catch as an alternative to setjmp/longjmp in user
71	* mode code when IEM_WITH_SETJMP is in effect.
72	*
73	* With GCC 11.3.1 and code TLB on linux, using throw/catch instead of
74	* setjmp/long resulted in bs2-test-1 running 3.00% faster and all but on test
75	* result value improving by more than 1%. (Best out of three.)
76	*
77	* With Visual C++ 2019 and code TLB on windows, using throw/catch instead of
78	* setjmp/long resulted in bs2-test-1 running 3.68% faster and all but some of
79	* the MMIO and CPUID tests ran noticeably faster. Variation is greater than on
80	* Linux, but it should be quite a bit faster for normal code.
81	*/
82	#if (defined(IEM_WITH_SETJMP) && defined(IN_RING3) && (defined(__GNUC__) \|\| defined(_MSC_VER))) \
83	\|\| defined(DOXYGEN_RUNNING)
84	# define IEM_WITH_THROW_CATCH
85	#endif
86
87	/** @def IEM_DO_LONGJMP
88	*
89	* Wrapper around longjmp / throw.
90	*
91	* @param a_pVCpu The CPU handle.
92	* @param a_rc The status code jump back with / throw.
93	*/
94	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
95	# ifdef IEM_WITH_THROW_CATCH
96	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) throw int(a_rc)
97	# else
98	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) longjmp(*(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf), (a_rc))
99	# endif
100	#endif
101
102	/** For use with IEM function that may do a longjmp (when enabled).
103	*
104	* Visual C++ has trouble longjmp'ing from/over functions with the noexcept
105	* attribute. So, we indicate that function that may be part of a longjmp may
106	* throw "exceptions" and that the compiler should definitely not generate and
107	* std::terminate calling unwind code.
108	*
109	* Here is one example of this ending in std::terminate:
110	* @code{.txt}
111	00 00000041`cadfda10 00007ffc`5d5a1f9f ucrtbase!abort+0x4e
112	01 00000041`cadfda40 00007ffc`57af229a ucrtbase!terminate+0x1f
113	02 00000041`cadfda70 00007ffb`eec91030 VCRUNTIME140!__std_terminate+0xa [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\ehhelpers.cpp @ 192]
114	03 00000041`cadfdaa0 00007ffb`eec92c6d VCRUNTIME140_1!_CallSettingFrame+0x20 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\handlers.asm @ 50]
115	04 00000041`cadfdad0 00007ffb`eec93ae5 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToState+0x241 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 1085]
116	05 00000041`cadfdc00 00007ffb`eec92258 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToEmptyState+0x2d [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 218]
117	06 00000041`cadfdc30 00007ffb`eec940e9 VCRUNTIME140_1!__InternalCxxFrameHandler<__FrameHandler4>+0x194 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 304]
118	07 00000041`cadfdcd0 00007ffc`5f9f249f VCRUNTIME140_1!__CxxFrameHandler4+0xa9 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 290]
119	08 00000041`cadfdd40 00007ffc`5f980939 ntdll!RtlpExecuteHandlerForUnwind+0xf
120	09 00000041`cadfdd70 00007ffc`5f9a0edd ntdll!RtlUnwindEx+0x339
121	0a 00000041`cadfe490 00007ffc`57aff976 ntdll!RtlUnwind+0xcd
122	0b 00000041`cadfea00 00007ffb`e1b5de01 VCRUNTIME140!__longjmp_internal+0xe6 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\longjmp.asm @ 140]
123	0c (Inline Function) --------`-------- VBoxVMM!iemOpcodeGetNextU8SlowJmp+0x95 [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 1155]
124	0d 00000041`cadfea50 00007ffb`e1b60f6b VBoxVMM!iemOpcodeGetNextU8Jmp+0xc1 [L:\vbox-intern\src\VBox\VMM\include\IEMInline.h @ 402]
125	0e 00000041`cadfea90 00007ffb`e1cc6201 VBoxVMM!IEMExecForExits+0xdb [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 10185]
126	0f 00000041`cadfec70 00007ffb`e1d0df8d VBoxVMM!EMHistoryExec+0x4f1 [L:\vbox-intern\src\VBox\VMM\VMMAll\EMAll.cpp @ 452]
127	10 00000041`cadfed60 00007ffb`e1d0d4c0 VBoxVMM!nemR3WinHandleExitCpuId+0x79d [L:\vbox-intern\src\VBox\VMM\VMMAll\NEMAllNativeTemplate-win.cpp.h @ 1829] @encode
128	@endcode
129	*
130	* @see https://developercommunity.visualstudio.com/t/fragile-behavior-of-longjmp-called-from-noexcept-f/1532859
131	*/
132	#if defined(IEM_WITH_SETJMP) && (defined(_MSC_VER) \|\| defined(IEM_WITH_THROW_CATCH))
133	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT_EX(false)
134	#else
135	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT
136	#endif
137
138	#define IEM_IMPLEMENTS_TASKSWITCH
139
140	/** @def IEM_WITH_3DNOW
141	* Includes the 3DNow decoding. */
142	#if (!defined(IEM_WITH_3DNOW) && !defined(IEM_WITHOUT_3DNOW)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
143	# define IEM_WITH_3DNOW
144	#endif
145
146	/** @def IEM_WITH_THREE_0F_38
147	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
148	#if (!defined(IEM_WITH_THREE_0F_38) && !defined(IEM_WITHOUT_THREE_0F_38)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
149	# define IEM_WITH_THREE_0F_38
150	#endif
151
152	/** @def IEM_WITH_THREE_0F_3A
153	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
154	#if (!defined(IEM_WITH_THREE_0F_3A) && !defined(IEM_WITHOUT_THREE_0F_3A)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
155	# define IEM_WITH_THREE_0F_3A
156	#endif
157
158	/** @def IEM_WITH_VEX
159	* Includes the VEX decoding. */
160	#if (!defined(IEM_WITH_VEX) && !defined(IEM_WITHOUT_VEX)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
161	# define IEM_WITH_VEX
162	#endif
163
164	/** @def IEM_CFG_TARGET_CPU
165	* The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
166	*
167	* By default we allow this to be configured by the user via the
168	* CPUM/GuestCpuName config string, but this comes at a slight cost during
169	* decoding. So, for applications of this code where there is no need to
170	* be dynamic wrt target CPU, just modify this define.
171	*/
172	#if !defined(IEM_CFG_TARGET_CPU) \|\| defined(DOXYGEN_RUNNING)
173	# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
174	#endif
175
176	//#define IEM_WITH_CODE_TLB // - work in progress
177	//#define IEM_WITH_DATA_TLB // - work in progress
178
179
180	/** @def IEM_USE_UNALIGNED_DATA_ACCESS
181	* Use unaligned accesses instead of elaborate byte assembly. */
182	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86) \|\| defined(DOXYGEN_RUNNING)
183	# define IEM_USE_UNALIGNED_DATA_ACCESS
184	#endif
185
186	//#define IEM_LOG_MEMORY_WRITES
187
188	#if !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
189	/** Instruction statistics. */
190	typedef struct IEMINSTRSTATS
191	{
192	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
193	# include "IEMInstructionStatisticsTmpl.h"
194	# undef IEM_DO_INSTR_STAT
195	} IEMINSTRSTATS;
196	#else
197	struct IEMINSTRSTATS;
198	typedef struct IEMINSTRSTATS IEMINSTRSTATS;
199	#endif
200	/** Pointer to IEM instruction statistics. */
201	typedef IEMINSTRSTATS *PIEMINSTRSTATS;
202
203
204	/** @name IEMTARGETCPU_EFL_BEHAVIOR_XXX - IEMCPU::aidxTargetCpuEflFlavour
205	* @{ */
206	#define IEMTARGETCPU_EFL_BEHAVIOR_NATIVE 0 /*< Native x86 EFLAGS result; Intel EFLAGS when on non-x86 hosts. /
207	#define IEMTARGETCPU_EFL_BEHAVIOR_INTEL 1 /*< Intel EFLAGS result. /
208	#define IEMTARGETCPU_EFL_BEHAVIOR_AMD 2 /*< AMD EFLAGS result /
209	#define IEMTARGETCPU_EFL_BEHAVIOR_RESERVED 3 /*< Reserved/dummy entry slot that's the same as 0. /
210	#define IEMTARGETCPU_EFL_BEHAVIOR_MASK 3 /*< For masking the index before use. /
211	/** Selects the right variant from a_aArray.
212	* pVCpu is implicit in the caller context. */
213	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT(a_aArray) \
214	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[1] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
215	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for when no native worker can
216	* be used because the host CPU does not support the operation. */
217	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_NON_NATIVE(a_aArray) \
218	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
219	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for a two dimentional
220	* array paralleling IEMCPU::aidxTargetCpuEflFlavour and a single bit index
221	* into the two.
222	* @sa IEM_SELECT_NATIVE_OR_FALLBACK */
223	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
224	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
225	(a_aaArray[a_fNative][pVCpu->iem.s.aidxTargetCpuEflFlavour[a_fNative] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
226	#else
227	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
228	(a_aaArray[0][pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
229	#endif
230	/** @} */
231
232	/**
233	* Picks @a a_pfnNative or @a a_pfnFallback according to the host CPU feature
234	* indicator given by @a a_fCpumFeatureMember (CPUMFEATURES member).
235	*
236	* On non-x86 hosts, this will shortcut to the fallback w/o checking the
237	* indicator.
238	*
239	* @sa IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX
240	*/
241	#if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
242	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) \
243	(g_CpumHostFeatures.s.a_fCpumFeatureMember ? a_pfnNative : a_pfnFallback)
244	#else
245	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) (a_pfnFallback)
246	#endif
247
248
249	/**
250	* Extended operand mode that includes a representation of 8-bit.
251	*
252	* This is used for packing down modes when invoking some C instruction
253	* implementations.
254	*/
255	typedef enum IEMMODEX
256	{
257	IEMMODEX_16BIT = IEMMODE_16BIT,
258	IEMMODEX_32BIT = IEMMODE_32BIT,
259	IEMMODEX_64BIT = IEMMODE_64BIT,
260	IEMMODEX_8BIT
261	} IEMMODEX;
262	AssertCompileSize(IEMMODEX, 4);
263
264
265	/**
266	* Branch types.
267	*/
268	typedef enum IEMBRANCH
269	{
270	IEMBRANCH_JUMP = 1,
271	IEMBRANCH_CALL,
272	IEMBRANCH_TRAP,
273	IEMBRANCH_SOFTWARE_INT,
274	IEMBRANCH_HARDWARE_INT
275	} IEMBRANCH;
276	AssertCompileSize(IEMBRANCH, 4);
277
278
279	/**
280	* INT instruction types.
281	*/
282	typedef enum IEMINT
283	{
284	/** INT n instruction (opcode 0xcd imm). */
285	IEMINT_INTN = 0,
286	/** Single byte INT3 instruction (opcode 0xcc). */
287	IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
288	/** Single byte INTO instruction (opcode 0xce). */
289	IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
290	/** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
291	IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
292	} IEMINT;
293	AssertCompileSize(IEMINT, 4);
294
295
296	/**
297	* A FPU result.
298	*/
299	typedef struct IEMFPURESULT
300	{
301	/** The output value. */
302	RTFLOAT80U r80Result;
303	/** The output status. */
304	uint16_t FSW;
305	} IEMFPURESULT;
306	AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
307	/** Pointer to a FPU result. */
308	typedef IEMFPURESULT *PIEMFPURESULT;
309	/** Pointer to a const FPU result. */
310	typedef IEMFPURESULT const *PCIEMFPURESULT;
311
312
313	/**
314	* A FPU result consisting of two output values and FSW.
315	*/
316	typedef struct IEMFPURESULTTWO
317	{
318	/** The first output value. */
319	RTFLOAT80U r80Result1;
320	/** The output status. */
321	uint16_t FSW;
322	/** The second output value. */
323	RTFLOAT80U r80Result2;
324	} IEMFPURESULTTWO;
325	AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
326	AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
327	/** Pointer to a FPU result consisting of two output values and FSW. */
328	typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
329	/** Pointer to a const FPU result consisting of two output values and FSW. */
330	typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
331
332
333	/**
334	* IEM TLB entry.
335	*
336	* Lookup assembly:
337	* @code{.asm}
338	; Calculate tag.
339	mov rax, [VA]
340	shl rax, 16
341	shr rax, 16 + X86_PAGE_SHIFT
342	or rax, [uTlbRevision]
343
344	; Do indexing.
345	movzx ecx, al
346	lea rcx, [pTlbEntries + rcx]
347
348	; Check tag.
349	cmp [rcx + IEMTLBENTRY.uTag], rax
350	jne .TlbMiss
351
352	; Check access.
353	mov rax, ACCESS_FLAGS \| MAPPING_R3_NOT_VALID \| 0xffffff00
354	and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
355	cmp rax, [uTlbPhysRev]
356	jne .TlbMiss
357
358	; Calc address and we're done.
359	mov eax, X86_PAGE_OFFSET_MASK
360	and eax, [VA]
361	or rax, [rcx + IEMTLBENTRY.pMappingR3]
362	%ifdef VBOX_WITH_STATISTICS
363	inc qword [cTlbHits]
364	%endif
365	jmp .Done
366
367	.TlbMiss:
368	mov r8d, ACCESS_FLAGS
369	mov rdx, [VA]
370	mov rcx, [pVCpu]
371	call iemTlbTypeMiss
372	.Done:
373
374	@endcode
375	*
376	*/
377	typedef struct IEMTLBENTRY
378	{
379	/** The TLB entry tag.
380	* Bits 35 thru 0 are made up of the virtual address shifted right 12 bits, this
381	* is ASSUMING a virtual address width of 48 bits.
382	*
383	* Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
384	*
385	* The TLB lookup code uses the current TLB revision, which won't ever be zero,
386	* enabling an extremely cheap TLB invalidation most of the time. When the TLB
387	* revision wraps around though, the tags needs to be zeroed.
388	*
389	* @note Try use SHRD instruction? After seeing
390	* https://gmplib.org/~tege/x86-timing.pdf, maybe not.
391	*
392	* @todo This will need to be reorganized for 57-bit wide virtual address and
393	* PCID (currently 12 bits) and ASID (currently 6 bits) support. We'll
394	* have to move the TLB entry versioning entirely to the
395	* fFlagsAndPhysRev member then, 57 bit wide VAs means we'll only have
396	* 19 bits left (64 - 57 + 12 = 19) and they'll almost entire be
397	* consumed by PCID and ASID (12 + 6 = 18).
398	*/
399	uint64_t uTag;
400	/** Access flags and physical TLB revision.
401	*
402	* - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
403	* - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
404	* - Bit 2 - page tables - not user (complemented X86_PTE_US).
405	* - Bit 3 - pgm phys/virt - not directly writable.
406	* - Bit 4 - pgm phys page - not directly readable.
407	* - Bit 5 - page tables - not accessed (complemented X86_PTE_A).
408	* - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
409	* - Bit 7 - tlb entry - pMappingR3 member not valid.
410	* - Bits 63 thru 8 are used for the physical TLB revision number.
411	*
412	* We're using complemented bit meanings here because it makes it easy to check
413	* whether special action is required. For instance a user mode write access
414	* would do a "TEST fFlags, (X86_PTE_RW \| X86_PTE_US \| X86_PTE_D)" and a
415	* non-zero result would mean special handling needed because either it wasn't
416	* writable, or it wasn't user, or the page wasn't dirty. A user mode read
417	* access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
418	* need to check any PTE flag.
419	*/
420	uint64_t fFlagsAndPhysRev;
421	/** The guest physical page address. */
422	uint64_t GCPhys;
423	/** Pointer to the ring-3 mapping. */
424	R3PTRTYPE(uint8_t *) pbMappingR3;
425	#if HC_ARCH_BITS == 32
426	uint32_t u32Padding1;
427	#endif
428	} IEMTLBENTRY;
429	AssertCompileSize(IEMTLBENTRY, 32);
430	/** Pointer to an IEM TLB entry. */
431	typedef IEMTLBENTRY *PIEMTLBENTRY;
432
433	/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
434	* @{ */
435	#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /*< Page tables: Not executable. /
436	#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /*< Page tables: Not writable. /
437	#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /*< Page tables: Not user accessible (supervisor only). /
438	#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /*< Phys page: Not writable (access handler, ROM, whatever). /
439	#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /*< Phys page: Not readable (MMIO / access handler, ROM) /
440	#define IEMTLBE_F_PT_NO_ACCESSED RT_BIT_64(5) /*< Phys tables: Not accessed (need to be marked accessed). /
441	#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /*< Page tables: Not dirty (needs to be made dirty on write). /
442	#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(7) /*< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. /
443	#define IEMTLBE_F_PG_UNASSIGNED RT_BIT_64(8) /*< Phys page: Unassigned memory (not RAM, ROM, MMIO2 or MMIO). /
444	#define IEMTLBE_F_PHYS_REV UINT64_C(0xfffffffffffffe00) /*< Physical revision mask. @sa IEMTLB_PHYS_REV_INCR /
445	/** @} */
446
447
448	/**
449	* An IEM TLB.
450	*
451	* We've got two of these, one for data and one for instructions.
452	*/
453	typedef struct IEMTLB
454	{
455	/** The TLB entries.
456	* We've choosen 256 because that way we can obtain the result directly from a
457	* 8-bit register without an additional AND instruction. */
458	IEMTLBENTRY aEntries[256];
459	/** The TLB revision.
460	* This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
461	* by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
462	* the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
463	* (The revision zero indicates an invalid TLB entry.)
464	*
465	* The initial value is choosen to cause an early wraparound. */
466	uint64_t uTlbRevision;
467	/** The TLB physical address revision - shadow of PGM variable.
468	*
469	* This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
470	* incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
471	* a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
472	* as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
473	*
474	* The initial value is choosen to cause an early wraparound. */
475	uint64_t volatile uTlbPhysRev;
476
477	/* Statistics: */
478
479	/** TLB hits (VBOX_WITH_STATISTICS only). */
480	uint64_t cTlbHits;
481	/** TLB misses. */
482	uint32_t cTlbMisses;
483	/** Slow read path. */
484	uint32_t cTlbSlowReadPath;
485	#if 0
486	/** TLB misses because of tag mismatch. */
487	uint32_t cTlbMissesTag;
488	/** TLB misses because of virtual access violation. */
489	uint32_t cTlbMissesVirtAccess;
490	/** TLB misses because of dirty bit. */
491	uint32_t cTlbMissesDirty;
492	/** TLB misses because of MMIO */
493	uint32_t cTlbMissesMmio;
494	/** TLB misses because of write access handlers. */
495	uint32_t cTlbMissesWriteHandler;
496	/** TLB misses because no r3(/r0) mapping. */
497	uint32_t cTlbMissesMapping;
498	#endif
499	/** Alignment padding. */
500	uint32_t au32Padding[3+5];
501	} IEMTLB;
502	AssertCompileSizeAlignment(IEMTLB, 64);
503	/** IEMTLB::uTlbRevision increment. */
504	#define IEMTLB_REVISION_INCR RT_BIT_64(36)
505	/** IEMTLB::uTlbRevision mask. */
506	#define IEMTLB_REVISION_MASK (~(RT_BIT_64(36) - 1))
507	/** IEMTLB::uTlbPhysRev increment.
508	* @sa IEMTLBE_F_PHYS_REV */
509	#define IEMTLB_PHYS_REV_INCR RT_BIT_64(9)
510	/**
511	* Calculates the TLB tag for a virtual address.
512	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
513	* @param a_pTlb The TLB.
514	* @param a_GCPtr The virtual address.
515	*/
516	#define IEMTLB_CALC_TAG(a_pTlb, a_GCPtr) ( IEMTLB_CALC_TAG_NO_REV(a_GCPtr) \| (a_pTlb)->uTlbRevision )
517	/**
518	* Calculates the TLB tag for a virtual address but without TLB revision.
519	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
520	* @param a_GCPtr The virtual address.
521	*/
522	#define IEMTLB_CALC_TAG_NO_REV(a_GCPtr) ( (((a_GCPtr) << 16) >> (GUEST_PAGE_SHIFT + 16)) )
523	/**
524	* Converts a TLB tag value into a TLB index.
525	* @returns Index into IEMTLB::aEntries.
526	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
527	*/
528	#define IEMTLB_TAG_TO_INDEX(a_uTag) ( (uint8_t)(a_uTag) )
529	/**
530	* Converts a TLB tag value into a TLB index.
531	* @returns Index into IEMTLB::aEntries.
532	* @param a_pTlb The TLB.
533	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
534	*/
535	#define IEMTLB_TAG_TO_ENTRY(a_pTlb, a_uTag) ( &(a_pTlb)->aEntries[IEMTLB_TAG_TO_INDEX(a_uTag)] )
536
537
538	/** Pointer to a translation block. */
539	typedef struct IEMTB *PIEMTB;
540
541	/** @name IEM_F_XXX - Execution mode flags (IEMCPU::fExec, IEMTB::fFlags).
542	*
543	* These flags are set when entering IEM and adjusted as code is executed, such
544	* that they will always contain the current values as instructions are
545	* finished.
546	*
547	* In recompiled execution mode, (most of) these flags are included in the
548	* translation block selection key and stored in IEMTB::fFlags alongside the
549	* IEMTB_F_XXX flags. The latter flags uses bits 31 thru 24, which are all zero
550	* in IEMCPU::fExec.
551	*
552	* @{ */
553	/** Mode: The block target mode mask. */
554	#define IEM_F_MODE_MASK UINT32_C(0x0000001f)
555	/** Mode: The IEMMODE part of the IEMTB_F_MODE_MASK value. */
556	#define IEM_F_MODE_CPUMODE_MASK UINT32_C(0x00000003)
557	/** X86 Mode: Bit used to indicating pre-386 CPU in 16-bit mode (for eliminating
558	* conditional in EIP/IP updating), and flat wide open CS, SS DS, and ES in
559	* 32-bit mode (for simplifying most memory accesses). */
560	#define IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK UINT32_C(0x00000004)
561	/** X86 Mode: Bit indicating protected mode, real mode (or SMM) when not set. */
562	#define IEM_F_MODE_X86_PROT_MASK UINT32_C(0x00000008)
563	/** X86 Mode: Bit used to indicate virtual 8086 mode (only 16-bit). */
564	#define IEM_F_MODE_X86_V86_MASK UINT32_C(0x00000010)
565
566	/** X86 Mode: 16-bit on 386 or later. */
567	#define IEM_F_MODE_X86_16BIT UINT32_C(0x00000000)
568	/** X86 Mode: 80286, 80186 and 8086/88 targetting blocks (EIP update opt). */
569	#define IEM_F_MODE_X86_16BIT_PRE_386 UINT32_C(0x00000004)
570	/** X86 Mode: 16-bit protected mode on 386 or later. */
571	#define IEM_F_MODE_X86_16BIT_PROT UINT32_C(0x00000008)
572	/** X86 Mode: 16-bit protected mode on 386 or later. */
573	#define IEM_F_MODE_X86_16BIT_PROT_PRE_386 UINT32_C(0x0000000c)
574	/** X86 Mode: 16-bit virtual 8086 protected mode (on 386 or later). */
575	#define IEM_F_MODE_X86_16BIT_PROT_V86 UINT32_C(0x00000018)
576
577	/** X86 Mode: 32-bit on 386 or later. */
578	#define IEM_F_MODE_X86_32BIT UINT32_C(0x00000001)
579	/** X86 Mode: 32-bit mode with wide open flat CS, SS, DS and ES. */
580	#define IEM_F_MODE_X86_32BIT_FLAT UINT32_C(0x00000005)
581	/** X86 Mode: 32-bit protected mode. */
582	#define IEM_F_MODE_X86_32BIT_PROT UINT32_C(0x00000009)
583	/** X86 Mode: 32-bit protected mode with wide open flat CS, SS, DS and ES. */
584	#define IEM_F_MODE_X86_32BIT_PROT_FLAT UINT32_C(0x0000000d)
585
586	/** X86 Mode: 64-bit (includes protected, but not the flat bit). */
587	#define IEM_F_MODE_X86_64BIT UINT32_C(0x0000000a)
588
589
590	/** Bypass access handlers when set. */
591	#define IEM_F_BYPASS_HANDLERS UINT32_C(0x00010000)
592	/** Have pending hardware instruction breakpoints. */
593	#define IEM_F_PENDING_BRK_INSTR UINT32_C(0x00020000)
594	/** Have pending hardware data breakpoints. */
595	#define IEM_F_PENDING_BRK_DATA UINT32_C(0x00040000)
596
597	/** X86: Have pending hardware I/O breakpoints. */
598	#define IEM_F_PENDING_BRK_X86_IO UINT32_C(0x00000400)
599	/** X86: Disregard the lock prefix (implied or not) when set. */
600	#define IEM_F_X86_DISREGARD_LOCK UINT32_C(0x00000800)
601
602	/** Pending breakpoint mask (what iemCalcExecDbgFlags works out). */
603	#define IEM_F_PENDING_BRK_MASK (IEM_F_PENDING_BRK_INSTR \| IEM_F_PENDING_BRK_DATA \| IEM_F_PENDING_BRK_X86_IO)
604
605	/** Caller configurable options. */
606	#define IEM_F_USER_OPTS (IEM_F_BYPASS_HANDLERS \| IEM_F_X86_DISREGARD_LOCK)
607
608	/** X86: The current protection level (CPL) shift factor. */
609	#define IEM_F_X86_CPL_SHIFT 8
610	/** X86: The current protection level (CPL) mask. */
611	#define IEM_F_X86_CPL_MASK UINT32_C(0x00000300)
612	/** X86: The current protection level (CPL) shifted mask. */
613	#define IEM_F_X86_CPL_SMASK UINT32_C(0x00000003)
614
615	/** X86 execution context.
616	* The IEM_F_X86_CTX_XXX values are individual flags that can be combined (with
617	* the exception of IEM_F_X86_CTX_NORMAL). This allows running VMs from SMM
618	* mode. */
619	#define IEM_F_X86_CTX_MASK UINT32_C(0x0000f000)
620	/** X86 context: Plain regular execution context. */
621	#define IEM_F_X86_CTX_NORMAL UINT32_C(0x00000000)
622	/** X86 context: VT-x enabled. */
623	#define IEM_F_X86_CTX_VMX UINT32_C(0x00001000)
624	/** X86 context: AMD-V enabled. */
625	#define IEM_F_X86_CTX_SVM UINT32_C(0x00002000)
626	/** X86 context: In AMD-V or VT-x guest mode. */
627	#define IEM_F_X86_CTX_IN_GUEST UINT32_C(0x00004000)
628	/** X86 context: System management mode (SMM). */
629	#define IEM_F_X86_CTX_SMM UINT32_C(0x00008000)
630
631	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
632	* iemRegFinishClearingRF() most for most situations (CPUMCTX_DBG_HIT_DRX_MASK
633	* and CPUMCTX_DBG_DBGF_MASK are covered by the IEM_F_PENDING_BRK_XXX bits
634	* alread). */
635
636	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
637	* iemRegFinishClearingRF() most for most situations
638	* (CPUMCTX_DBG_HIT_DRX_MASK and CPUMCTX_DBG_DBGF_MASK are covered by
639	* the IEM_F_PENDING_BRK_XXX bits alread). */
640
641	/** @} */
642
643
644	/** @name IEMTB_F_XXX - Translation block flags (IEMTB::fFlags).
645	*
646	* Extends the IEM_F_XXX flags (subject to IEMTB_F_IEM_F_MASK) to make up the
647	* translation block flags. The combined flag mask (subject to
648	* IEMTB_F_KEY_MASK) is used as part of the lookup key for translation blocks.
649	*
650	* @{ */
651	/** Mask of IEM_F_XXX flags included in IEMTB_F_XXX. */
652	#define IEMTB_F_IEM_F_MASK UINT32_C(0x00ffffff)
653
654	/** Type: The block type mask. */
655	#define IEMTB_F_TYPE_MASK UINT32_C(0x03000000)
656	/** Type: Purly threaded recompiler (via tables). */
657	#define IEMTB_F_TYPE_THREADED UINT32_C(0x01000000)
658	/** Type: Native recompilation. */
659	#define IEMTB_F_TYPE_NATIVE UINT32_C(0x02000000)
660
661	/** State mask. */
662	#define IEMTB_F_STATE_MASK UINT32_C(0x0c000000)
663	/** State shift count. */
664	#define IEMTB_F_STATE_SHIFT 26
665	/** State: Compiling. */
666	#define IEMTB_F_STATE_COMPILING UINT32_C(0x04000000)
667	/** State: Ready. */
668	#define IEMTB_F_STATE_READY UINT32_C(0x08000000)
669	/** State: Obsolete, can be deleted when we're sure it's not used any longer. */
670	#define IEMTB_F_STATE_OBSOLETE UINT32_C(0x0c000000)
671
672	/** Checks that EIP/IP is wihin CS.LIM and that RIP is canonical before each
673	* instruction. Used when we're close the limit before starting a TB, as
674	* determined by iemGetTbFlagsForCurrentPc(). */
675	#define IEMTB_F_RIP_CHECKS UINT32_C(0x0c000000)
676
677	/** Mask of the IEMTB_F_XXX flags that are part of the TB lookup key.
678	* @note We skip the CPL as we don't currently generate ring-specific code,
679	* that's all handled in CIMPL functions.
680	*
681	* For the same reasons, we skip all of IEM_F_X86_CTX_MASK, with the
682	* exception of SMM (which we don't implement). */
683	#define IEMTB_F_KEY_MASK ((UINT32_C(0xffffffff) & ~(IEM_F_X86_CTX_MASK \| IEM_F_X86_CPL_MASK)) \| IEM_F_X86_CTX_SMM)
684	/** @} */
685
686	AssertCompile( (IEM_F_MODE_X86_16BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
687	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
688	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_PROT_MASK));
689	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_V86_MASK));
690	AssertCompile( (IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
691	AssertCompile( IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
692	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_PROT_MASK));
693	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
694	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
695	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
696	AssertCompile( IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
697	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_V86_MASK));
698	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
699	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
700	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_PROT_MASK);
701	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
702	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_PROT_MASK);
703	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
704	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_V86_MASK);
705
706	AssertCompile( (IEM_F_MODE_X86_32BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
707	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
708	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_PROT_MASK));
709	AssertCompile( (IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
710	AssertCompile( IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
711	AssertCompile(!(IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_PROT_MASK));
712	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
713	AssertCompile(!(IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
714	AssertCompile( IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
715	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
716	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
717	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_PROT_MASK);
718
719	AssertCompile( (IEM_F_MODE_X86_64BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_64BIT);
720	AssertCompile( IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_PROT_MASK);
721	AssertCompile(!(IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
722
723
724	/**
725	* The per-CPU IEM state.
726	*/
727	typedef struct IEMCPU
728	{
729	/** Info status code that needs to be propagated to the IEM caller.
730	* This cannot be passed internally, as it would complicate all success
731	* checks within the interpreter making the code larger and almost impossible
732	* to get right. Instead, we'll store status codes to pass on here. Each
733	* source of these codes will perform appropriate sanity checks. */
734	int32_t rcPassUp; /* 0x00 */
735	/** Execution flag, IEM_F_XXX. */
736	uint32_t fExec; /* 0x04 */
737
738	/** @name Decoder state.
739	* @{ */
740	#ifndef IEM_WITH_OPAQUE_DECODER_STATE
741	# ifdef IEM_WITH_CODE_TLB
742	/** The offset of the next instruction byte. */
743	uint32_t offInstrNextByte; /* 0x08 */
744	/** The number of bytes available at pbInstrBuf for the current instruction.
745	* This takes the max opcode length into account so that doesn't need to be
746	* checked separately. */
747	uint32_t cbInstrBuf; /* 0x0c */
748	/** Pointer to the page containing RIP, user specified buffer or abOpcode.
749	* This can be NULL if the page isn't mappable for some reason, in which
750	* case we'll do fallback stuff.
751	*
752	* If we're executing an instruction from a user specified buffer,
753	* IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
754	* aligned pointer but pointer to the user data.
755	*
756	* For instructions crossing pages, this will start on the first page and be
757	* advanced to the next page by the time we've decoded the instruction. This
758	* therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
759	*/
760	uint8_t const pbInstrBuf; / 0x10 */
761	# if ARCH_BITS == 32
762	uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
763	# endif
764	/** The program counter corresponding to pbInstrBuf.
765	* This is set to a non-canonical address when we need to invalidate it. */
766	uint64_t uInstrBufPc; /* 0x18 */
767	/** The guest physical address corresponding to pbInstrBuf. */
768	RTGCPHYS GCPhysInstrBuf; /* 0x20 */
769	/** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
770	* This takes the CS segment limit into account. */
771	uint16_t cbInstrBufTotal; /* 0x28 */
772	/** Offset into pbInstrBuf of the first byte of the current instruction.
773	* Can be negative to efficiently handle cross page instructions. */
774	int16_t offCurInstrStart; /* 0x2a */
775
776	/** The prefix mask (IEM_OP_PRF_XXX). */
777	uint32_t fPrefixes; /* 0x2c */
778	/** The extra REX ModR/M register field bit (REX.R << 3). */
779	uint8_t uRexReg; /* 0x30 */
780	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
781	* (REX.B << 3). */
782	uint8_t uRexB; /* 0x31 */
783	/** The extra REX SIB index field bit (REX.X << 3). */
784	uint8_t uRexIndex; /* 0x32 */
785
786	/** The effective segment register (X86_SREG_XXX). */
787	uint8_t iEffSeg; /* 0x33 */
788
789	/** The offset of the ModR/M byte relative to the start of the instruction. */
790	uint8_t offModRm; /* 0x34 */
791	# else /* !IEM_WITH_CODE_TLB */
792	/** The size of what has currently been fetched into abOpcode. */
793	uint8_t cbOpcode; /* 0x08 */
794	/** The current offset into abOpcode. */
795	uint8_t offOpcode; /* 0x09 */
796	/** The offset of the ModR/M byte relative to the start of the instruction. */
797	uint8_t offModRm; /* 0x0a */
798
799	/** The effective segment register (X86_SREG_XXX). */
800	uint8_t iEffSeg; /* 0x0b */
801
802	/** The prefix mask (IEM_OP_PRF_XXX). */
803	uint32_t fPrefixes; /* 0x0c */
804	/** The extra REX ModR/M register field bit (REX.R << 3). */
805	uint8_t uRexReg; /* 0x10 */
806	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
807	* (REX.B << 3). */
808	uint8_t uRexB; /* 0x11 */
809	/** The extra REX SIB index field bit (REX.X << 3). */
810	uint8_t uRexIndex; /* 0x12 */
811
812	# endif /* !IEM_WITH_CODE_TLB */
813
814	/** The effective operand mode. */
815	IEMMODE enmEffOpSize; /* 0x35, 0x13 */
816	/** The default addressing mode. */
817	IEMMODE enmDefAddrMode; /* 0x36, 0x14 */
818	/** The effective addressing mode. */
819	IEMMODE enmEffAddrMode; /* 0x37, 0x15 */
820	/** The default operand mode. */
821	IEMMODE enmDefOpSize; /* 0x38, 0x16 */
822
823	/** Prefix index (VEX.pp) for two byte and three byte tables. */
824	uint8_t idxPrefix; /* 0x39, 0x17 */
825	/** 3rd VEX/EVEX/XOP register.
826	* Please use IEM_GET_EFFECTIVE_VVVV to access. */
827	uint8_t uVex3rdReg; /* 0x3a, 0x18 */
828	/** The VEX/EVEX/XOP length field. */
829	uint8_t uVexLength; /* 0x3b, 0x19 */
830	/** Additional EVEX stuff. */
831	uint8_t fEvexStuff; /* 0x3c, 0x1a */
832
833	/** Explicit alignment padding. */
834	uint8_t abAlignment2a[1]; /* 0x3d, 0x1b */
835	/** The FPU opcode (FOP). */
836	uint16_t uFpuOpcode; /* 0x3e, 0x1c */
837	# ifndef IEM_WITH_CODE_TLB
838	/** Explicit alignment padding. */
839	uint8_t abAlignment2b[2]; /* 0x1e */
840	# endif
841
842	/** The opcode bytes. */
843	uint8_t abOpcode[15]; /* 0x40, 0x20 */
844	/** Explicit alignment padding. */
845	# ifdef IEM_WITH_CODE_TLB
846	//uint8_t abAlignment2c[0x4f - 0x4f]; /* 0x4f */
847	# else
848	uint8_t abAlignment2c[0x4f - 0x2f]; /* 0x2f */
849	# endif
850	#else /* IEM_WITH_OPAQUE_DECODER_STATE */
851	uint8_t abOpaqueDecoder[0x4f - 0x8];
852	#endif /* IEM_WITH_OPAQUE_DECODER_STATE */
853	/** @} */
854
855
856	/** The number of active guest memory mappings. */
857	uint8_t cActiveMappings; /* 0x4f, 0x4f */
858
859	/** Records for tracking guest memory mappings. */
860	struct
861	{
862	/** The address of the mapped bytes. */
863	R3R0PTRTYPE(void *) pv;
864	/** The access flags (IEM_ACCESS_XXX).
865	* IEM_ACCESS_INVALID if the entry is unused. */
866	uint32_t fAccess;
867	#if HC_ARCH_BITS == 64
868	uint32_t u32Alignment4; /*< Alignment padding. /
869	#endif
870	} aMemMappings[3]; /* 0x50 LB 0x30 */
871
872	/** Locking records for the mapped memory. */
873	union
874	{
875	PGMPAGEMAPLOCK Lock;
876	uint64_t au64Padding[2];
877	} aMemMappingLocks[3]; /* 0x80 LB 0x30 */
878
879	/** Bounce buffer info.
880	* This runs in parallel to aMemMappings. */
881	struct
882	{
883	/** The physical address of the first byte. */
884	RTGCPHYS GCPhysFirst;
885	/** The physical address of the second page. */
886	RTGCPHYS GCPhysSecond;
887	/** The number of bytes in the first page. */
888	uint16_t cbFirst;
889	/** The number of bytes in the second page. */
890	uint16_t cbSecond;
891	/** Whether it's unassigned memory. */
892	bool fUnassigned;
893	/** Explicit alignment padding. */
894	bool afAlignment5[3];
895	} aMemBbMappings[3]; /* 0xb0 LB 0x48 */
896
897	/** The flags of the current exception / interrupt. */
898	uint32_t fCurXcpt; /* 0xf8 */
899	/** The current exception / interrupt. */
900	uint8_t uCurXcpt; /* 0xfc */
901	/** Exception / interrupt recursion depth. */
902	int8_t cXcptRecursions; /* 0xfb */
903
904	/** The next unused mapping index.
905	* @todo try find room for this up with cActiveMappings. */
906	uint8_t iNextMapping; /* 0xfd */
907	uint8_t abAlignment7[1];
908
909	/** Bounce buffer storage.
910	* This runs in parallel to aMemMappings and aMemBbMappings. */
911	struct
912	{
913	uint8_t ab[512];
914	} aBounceBuffers[3]; /* 0x100 LB 0x600 */
915
916
917	/** Pointer set jump buffer - ring-3 context. */
918	R3PTRTYPE(jmp_buf *) pJmpBufR3;
919	/** Pointer set jump buffer - ring-0 context. */
920	R0PTRTYPE(jmp_buf *) pJmpBufR0;
921
922	/** @todo Should move this near @a fCurXcpt later. */
923	/** The CR2 for the current exception / interrupt. */
924	uint64_t uCurXcptCr2;
925	/** The error code for the current exception / interrupt. */
926	uint32_t uCurXcptErr;
927
928	/** @name Statistics
929	* @{ */
930	/** The number of instructions we've executed. */
931	uint32_t cInstructions;
932	/** The number of potential exits. */
933	uint32_t cPotentialExits;
934	/** The number of bytes data or stack written (mostly for IEMExecOneEx).
935	* This may contain uncommitted writes. */
936	uint32_t cbWritten;
937	/** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
938	uint32_t cRetInstrNotImplemented;
939	/** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
940	uint32_t cRetAspectNotImplemented;
941	/** Counts informational statuses returned (other than VINF_SUCCESS). */
942	uint32_t cRetInfStatuses;
943	/** Counts other error statuses returned. */
944	uint32_t cRetErrStatuses;
945	/** Number of times rcPassUp has been used. */
946	uint32_t cRetPassUpStatus;
947	/** Number of times RZ left with instruction commit pending for ring-3. */
948	uint32_t cPendingCommit;
949	/** Number of long jumps. */
950	uint32_t cLongJumps;
951	/** @} */
952
953	/** @name Target CPU information.
954	* @{ */
955	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
956	/** The target CPU. */
957	uint8_t uTargetCpu;
958	#else
959	uint8_t bTargetCpuPadding;
960	#endif
961	/** For selecting assembly works matching the target CPU EFLAGS behaviour, see
962	* IEMTARGETCPU_EFL_BEHAVIOR_XXX for values, with the 1st entry for when no
963	* native host support and the 2nd for when there is.
964	*
965	* The two values are typically indexed by a g_CpumHostFeatures bit.
966	*
967	* This is for instance used for the BSF & BSR instructions where AMD and
968	* Intel CPUs produce different EFLAGS. */
969	uint8_t aidxTargetCpuEflFlavour[2];
970
971	/** The CPU vendor. */
972	CPUMCPUVENDOR enmCpuVendor;
973	/** @} */
974
975	/** @name Host CPU information.
976	* @{ */
977	/** The CPU vendor. */
978	CPUMCPUVENDOR enmHostCpuVendor;
979	/** @} */
980
981	/** Counts RDMSR \#GP(0) LogRel(). */
982	uint8_t cLogRelRdMsr;
983	/** Counts WRMSR \#GP(0) LogRel(). */
984	uint8_t cLogRelWrMsr;
985	/** Alignment padding. */
986	uint8_t abAlignment9[46];
987
988	/** @name Recompilation
989	* @{ */
990	/** Pointer to the current translation block.
991	* This can either be one being executed or one being compiled. */
992	R3PTRTYPE(PIEMTB) pCurTbR3;
993	/** The PC (RIP) at the start of pCurTbR3/pCurTbR0.
994	* The TBs are based on physical addresses, so this is needed to correleated
995	* RIP to opcode bytes stored in the TB (AMD-V / VT-x). */
996	uint64_t uCurTbStartPc;
997	/** Statistics: Number of TB allocation calls. */
998	uint64_t cTbAllocs;
999	/** Statistics: Number of TB free calls. */
1000	uint64_t cTbFrees;
1001	/** Statistics: Number of TB lookup misses. */
1002	uint64_t cTbLookupMisses;
1003	/** Statistics: Number of TB lookup hits (debug only). */
1004	uint64_t cTbLookupHits;
1005	/** Whether to end the current TB. */
1006	bool fEndTb;
1007	/** Spaced reserved for recompiler data / alignment. */
1008	bool afRecompilerStuff1[7];
1009	/** Spaced reserved for recompiler data / alignment. */
1010	uint64_t auRecompilerStuff2[1];
1011	/** @} */
1012
1013	/** Data TLB.
1014	* @remarks Must be 64-byte aligned. */
1015	IEMTLB DataTlb;
1016	/** Instruction TLB.
1017	* @remarks Must be 64-byte aligned. */
1018	IEMTLB CodeTlb;
1019
1020	/** Exception statistics. */
1021	STAMCOUNTER aStatXcpts[32];
1022	/** Interrupt statistics. */
1023	uint32_t aStatInts[256];
1024
1025	#if defined(VBOX_WITH_STATISTICS) && !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
1026	/** Instruction statistics for ring-0/raw-mode. */
1027	IEMINSTRSTATS StatsRZ;
1028	/** Instruction statistics for ring-3. */
1029	IEMINSTRSTATS StatsR3;
1030	#endif
1031	} IEMCPU;
1032	AssertCompileMemberOffset(IEMCPU, cActiveMappings, 0x4f);
1033	AssertCompileMemberAlignment(IEMCPU, aMemMappings, 16);
1034	AssertCompileMemberAlignment(IEMCPU, aMemMappingLocks, 16);
1035	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 64);
1036	AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
1037	AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
1038
1039	/** Pointer to the per-CPU IEM state. */
1040	typedef IEMCPU *PIEMCPU;
1041	/** Pointer to the const per-CPU IEM state. */
1042	typedef IEMCPU const *PCIEMCPU;
1043
1044
1045	/** @def IEM_GET_CTX
1046	* Gets the guest CPU context for the calling EMT.
1047	* @returns PCPUMCTX
1048	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1049	*/
1050	#define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
1051
1052	/** @def IEM_CTX_ASSERT
1053	* Asserts that the @a a_fExtrnMbz is present in the CPU context.
1054	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1055	* @param a_fExtrnMbz The mask of CPUMCTX_EXTRN_XXX flags that must be zero.
1056	*/
1057	#define IEM_CTX_ASSERT(a_pVCpu, a_fExtrnMbz) AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
1058	("fExtrn=%#RX64 fExtrnMbz=%#RX64\n", (a_pVCpu)->cpum.GstCtx.fExtrn, \
1059	(a_fExtrnMbz)))
1060
1061	/** @def IEM_CTX_IMPORT_RET
1062	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
1063	*
1064	* Will call the keep to import the bits as needed.
1065	*
1066	* Returns on import failure.
1067	*
1068	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1069	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
1070	*/
1071	#define IEM_CTX_IMPORT_RET(a_pVCpu, a_fExtrnImport) \
1072	do { \
1073	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
1074	{ /* likely */ } \
1075	else \
1076	{ \
1077	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
1078	AssertRCReturn(rcCtxImport, rcCtxImport); \
1079	} \
1080	} while (0)
1081
1082	/** @def IEM_CTX_IMPORT_NORET
1083	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
1084	*
1085	* Will call the keep to import the bits as needed.
1086	*
1087	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1088	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
1089	*/
1090	#define IEM_CTX_IMPORT_NORET(a_pVCpu, a_fExtrnImport) \
1091	do { \
1092	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
1093	{ /* likely */ } \
1094	else \
1095	{ \
1096	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
1097	AssertLogRelRC(rcCtxImport); \
1098	} \
1099	} while (0)
1100
1101	/** @def IEM_CTX_IMPORT_JMP
1102	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
1103	*
1104	* Will call the keep to import the bits as needed.
1105	*
1106	* Jumps on import failure.
1107	*
1108	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1109	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
1110	*/
1111	#define IEM_CTX_IMPORT_JMP(a_pVCpu, a_fExtrnImport) \
1112	do { \
1113	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
1114	{ /* likely */ } \
1115	else \
1116	{ \
1117	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
1118	AssertRCStmt(rcCtxImport, IEM_DO_LONGJMP(pVCpu, rcCtxImport)); \
1119	} \
1120	} while (0)
1121
1122
1123
1124	/** @def IEM_GET_TARGET_CPU
1125	* Gets the current IEMTARGETCPU value.
1126	* @returns IEMTARGETCPU value.
1127	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1128	*/
1129	#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
1130	# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
1131	#else
1132	# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
1133	#endif
1134
1135	/** @def IEM_GET_INSTR_LEN
1136	* Gets the instruction length. */
1137	#ifdef IEM_WITH_CODE_TLB
1138	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
1139	#else
1140	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
1141	#endif
1142
1143	/** @def IEM_TRY_SETJMP
1144	* Wrapper around setjmp / try, hiding all the ugly differences.
1145	*
1146	* @note Use with extreme care as this is a fragile macro.
1147	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
1148	* @param a_rcTarget The variable that should receive the status code in case
1149	* of a longjmp/throw.
1150	*/
1151	/** @def IEM_TRY_SETJMP_AGAIN
1152	* For when setjmp / try is used again in the same variable scope as a previous
1153	* IEM_TRY_SETJMP invocation.
1154	*/
1155	/** @def IEM_CATCH_LONGJMP_BEGIN
1156	* Start wrapper for catch / setjmp-else.
1157	*
1158	* This will set up a scope.
1159	*
1160	* @note Use with extreme care as this is a fragile macro.
1161	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
1162	* @param a_rcTarget The variable that should receive the status code in case
1163	* of a longjmp/throw.
1164	*/
1165	/** @def IEM_CATCH_LONGJMP_END
1166	* End wrapper for catch / setjmp-else.
1167	*
1168	* This will close the scope set up by IEM_CATCH_LONGJMP_BEGIN and clean up the
1169	* state.
1170	*
1171	* @note Use with extreme care as this is a fragile macro.
1172	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
1173	*/
1174	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
1175	# ifdef IEM_WITH_THROW_CATCH
1176	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
1177	a_rcTarget = VINF_SUCCESS; \
1178	try
1179	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
1180	IEM_TRY_SETJMP(a_pVCpu, a_rcTarget)
1181	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
1182	catch (int rcThrown) \
1183	{ \
1184	a_rcTarget = rcThrown
1185	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
1186	} \
1187	((void)0)
1188	# else /* !IEM_WITH_THROW_CATCH */
1189	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
1190	jmp_buf JmpBuf; \
1191	jmp_buf * volatile pSavedJmpBuf = pVCpu->iem.s.CTX_SUFF(pJmpBuf); \
1192	pVCpu->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
1193	if ((rcStrict = setjmp(JmpBuf)) == 0)
1194	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
1195	pSavedJmpBuf = pVCpu->iem.s.CTX_SUFF(pJmpBuf); \
1196	pVCpu->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
1197	if ((rcStrict = setjmp(JmpBuf)) == 0)
1198	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
1199	else \
1200	{ \
1201	((void)0)
1202	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
1203	} \
1204	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = pSavedJmpBuf
1205	# endif /* !IEM_WITH_THROW_CATCH */
1206	#endif /* IEM_WITH_SETJMP */
1207
1208
1209	/**
1210	* Shared per-VM IEM data.
1211	*/
1212	typedef struct IEM
1213	{
1214	/** The VMX APIC-access page handler type. */
1215	PGMPHYSHANDLERTYPE hVmxApicAccessPage;
1216	#ifndef VBOX_WITHOUT_CPUID_HOST_CALL
1217	/** Set if the CPUID host call functionality is enabled. */
1218	bool fCpuIdHostCall;
1219	#endif
1220	} IEM;
1221
1222
1223
1224	/** @name IEM_ACCESS_XXX - Access details.
1225	* @{ */
1226	#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
1227	#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
1228	#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
1229	#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
1230	#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
1231	#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
1232	#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
1233	#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
1234	#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
1235	#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
1236	/** The writes are partial, so if initialize the bounce buffer with the
1237	* orignal RAM content. */
1238	#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
1239	/** Used in aMemMappings to indicate that the entry is bounce buffered. */
1240	#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
1241	/** Bounce buffer with ring-3 write pending, first page. */
1242	#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
1243	/** Bounce buffer with ring-3 write pending, second page. */
1244	#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
1245	/** Not locked, accessed via the TLB. */
1246	#define IEM_ACCESS_NOT_LOCKED UINT32_C(0x00001000)
1247	/** Valid bit mask. */
1248	#define IEM_ACCESS_VALID_MASK UINT32_C(0x00001fff)
1249	/** Shift count for the TLB flags (upper word). */
1250	#define IEM_ACCESS_SHIFT_TLB_FLAGS 16
1251
1252	/** Read+write data alias. */
1253	#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
1254	/** Write data alias. */
1255	#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
1256	/** Read data alias. */
1257	#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_DATA)
1258	/** Instruction fetch alias. */
1259	#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_WHAT_CODE)
1260	/** Stack write alias. */
1261	#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
1262	/** Stack read alias. */
1263	#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_STACK)
1264	/** Stack read+write alias. */
1265	#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
1266	/** Read system table alias. */
1267	#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_SYS)
1268	/** Read+write system table alias. */
1269	#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_SYS)
1270	/** @} */
1271
1272	/** @name Prefix constants (IEMCPU::fPrefixes)
1273	* @{ */
1274	#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /*< CS segment prefix (0x2e). /
1275	#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /*< SS segment prefix (0x36). /
1276	#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /*< DS segment prefix (0x3e). /
1277	#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /*< ES segment prefix (0x26). /
1278	#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /*< FS segment prefix (0x64). /
1279	#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /*< GS segment prefix (0x65). /
1280	#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
1281
1282	#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /*< Operand size prefix (0x66). /
1283	#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /*< REX.W prefix (0x48-0x4f). /
1284	#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /*< Address size prefix (0x67). /
1285
1286	#define IEM_OP_PRF_LOCK RT_BIT_32(16) /*< Lock prefix (0xf0). /
1287	#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /*< Repeat-not-zero prefix (0xf2). /
1288	#define IEM_OP_PRF_REPZ RT_BIT_32(18) /*< Repeat-if-zero prefix (0xf3). /
1289
1290	#define IEM_OP_PRF_REX RT_BIT_32(24) /*< Any REX prefix (0x40-0x4f). /
1291	#define IEM_OP_PRF_REX_R RT_BIT_32(25) /*< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). /
1292	#define IEM_OP_PRF_REX_B RT_BIT_32(26) /*< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). /
1293	#define IEM_OP_PRF_REX_X RT_BIT_32(27) /*< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). /
1294	/** Mask with all the REX prefix flags.
1295	* This is generally for use when needing to undo the REX prefixes when they
1296	* are followed legacy prefixes and therefore does not immediately preceed
1297	* the first opcode byte.
1298	* For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
1299	#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX \| IEM_OP_PRF_REX_R \| IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X \| IEM_OP_PRF_SIZE_REX_W )
1300
1301	#define IEM_OP_PRF_VEX RT_BIT_32(28) /*< Indiciates VEX prefix. /
1302	#define IEM_OP_PRF_EVEX RT_BIT_32(29) /*< Indiciates EVEX prefix. /
1303	#define IEM_OP_PRF_XOP RT_BIT_32(30) /*< Indiciates XOP prefix. /
1304	/** @} */
1305
1306	/** @name IEMOPFORM_XXX - Opcode forms
1307	* @note These are ORed together with IEMOPHINT_XXX.
1308	* @{ */
1309	/** ModR/M: reg, r/m */
1310	#define IEMOPFORM_RM 0
1311	/** ModR/M: reg, r/m (register) */
1312	#define IEMOPFORM_RM_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
1313	/** ModR/M: reg, r/m (memory) */
1314	#define IEMOPFORM_RM_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
1315	/** ModR/M: reg, r/m */
1316	#define IEMOPFORM_RMI 1
1317	/** ModR/M: reg, r/m (register) */
1318	#define IEMOPFORM_RMI_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
1319	/** ModR/M: reg, r/m (memory) */
1320	#define IEMOPFORM_RMI_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
1321	/** ModR/M: r/m, reg */
1322	#define IEMOPFORM_MR 2
1323	/** ModR/M: r/m (register), reg */
1324	#define IEMOPFORM_MR_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
1325	/** ModR/M: r/m (memory), reg */
1326	#define IEMOPFORM_MR_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
1327	/** ModR/M: r/m, reg */
1328	#define IEMOPFORM_MRI 3
1329	/** ModR/M: r/m (register), reg */
1330	#define IEMOPFORM_MRI_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
1331	/** ModR/M: r/m (memory), reg */
1332	#define IEMOPFORM_MRI_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
1333	/** ModR/M: r/m only */
1334	#define IEMOPFORM_M 4
1335	/** ModR/M: r/m only (register). */
1336	#define IEMOPFORM_M_REG (IEMOPFORM_M \| IEMOPFORM_MOD3)
1337	/** ModR/M: r/m only (memory). */
1338	#define IEMOPFORM_M_MEM (IEMOPFORM_M \| IEMOPFORM_NOT_MOD3)
1339	/** ModR/M: reg only */
1340	#define IEMOPFORM_R 5
1341
1342	/** VEX+ModR/M: reg, r/m */
1343	#define IEMOPFORM_VEX_RM 8
1344	/** VEX+ModR/M: reg, r/m (register) */
1345	#define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM \| IEMOPFORM_MOD3)
1346	/** VEX+ModR/M: reg, r/m (memory) */
1347	#define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM \| IEMOPFORM_NOT_MOD3)
1348	/** VEX+ModR/M: r/m, reg */
1349	#define IEMOPFORM_VEX_MR 9
1350	/** VEX+ModR/M: r/m (register), reg */
1351	#define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR \| IEMOPFORM_MOD3)
1352	/** VEX+ModR/M: r/m (memory), reg */
1353	#define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR \| IEMOPFORM_NOT_MOD3)
1354	/** VEX+ModR/M: r/m only */
1355	#define IEMOPFORM_VEX_M 10
1356	/** VEX+ModR/M: r/m only (register). */
1357	#define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M \| IEMOPFORM_MOD3)
1358	/** VEX+ModR/M: r/m only (memory). */
1359	#define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M \| IEMOPFORM_NOT_MOD3)
1360	/** VEX+ModR/M: reg only */
1361	#define IEMOPFORM_VEX_R 11
1362	/** VEX+ModR/M: reg, vvvv, r/m */
1363	#define IEMOPFORM_VEX_RVM 12
1364	/** VEX+ModR/M: reg, vvvv, r/m (register). */
1365	#define IEMOPFORM_VEX_RVM_REG (IEMOPFORM_VEX_RVM \| IEMOPFORM_MOD3)
1366	/** VEX+ModR/M: reg, vvvv, r/m (memory). */
1367	#define IEMOPFORM_VEX_RVM_MEM (IEMOPFORM_VEX_RVM \| IEMOPFORM_NOT_MOD3)
1368	/** VEX+ModR/M: reg, r/m, vvvv */
1369	#define IEMOPFORM_VEX_RMV 13
1370	/** VEX+ModR/M: reg, r/m, vvvv (register). */
1371	#define IEMOPFORM_VEX_RMV_REG (IEMOPFORM_VEX_RMV \| IEMOPFORM_MOD3)
1372	/** VEX+ModR/M: reg, r/m, vvvv (memory). */
1373	#define IEMOPFORM_VEX_RMV_MEM (IEMOPFORM_VEX_RMV \| IEMOPFORM_NOT_MOD3)
1374	/** VEX+ModR/M: reg, r/m, imm8 */
1375	#define IEMOPFORM_VEX_RMI 14
1376	/** VEX+ModR/M: reg, r/m, imm8 (register). */
1377	#define IEMOPFORM_VEX_RMI_REG (IEMOPFORM_VEX_RMI \| IEMOPFORM_MOD3)
1378	/** VEX+ModR/M: reg, r/m, imm8 (memory). */
1379	#define IEMOPFORM_VEX_RMI_MEM (IEMOPFORM_VEX_RMI \| IEMOPFORM_NOT_MOD3)
1380	/** VEX+ModR/M: r/m, vvvv, reg */
1381	#define IEMOPFORM_VEX_MVR 15
1382	/** VEX+ModR/M: r/m, vvvv, reg (register) */
1383	#define IEMOPFORM_VEX_MVR_REG (IEMOPFORM_VEX_MVR \| IEMOPFORM_MOD3)
1384	/** VEX+ModR/M: r/m, vvvv, reg (memory) */
1385	#define IEMOPFORM_VEX_MVR_MEM (IEMOPFORM_VEX_MVR \| IEMOPFORM_NOT_MOD3)
1386	/** VEX+ModR/M+/n: vvvv, r/m */
1387	#define IEMOPFORM_VEX_VM 16
1388	/** VEX+ModR/M+/n: vvvv, r/m (register) */
1389	#define IEMOPFORM_VEX_VM_REG (IEMOPFORM_VEX_VM \| IEMOPFORM_MOD3)
1390	/** VEX+ModR/M+/n: vvvv, r/m (memory) */
1391	#define IEMOPFORM_VEX_VM_MEM (IEMOPFORM_VEX_VM \| IEMOPFORM_NOT_MOD3)
1392
1393	/** Fixed register instruction, no R/M. */
1394	#define IEMOPFORM_FIXED 32
1395
1396	/** The r/m is a register. */
1397	#define IEMOPFORM_MOD3 RT_BIT_32(8)
1398	/** The r/m is a memory access. */
1399	#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
1400	/** @} */
1401
1402	/** @name IEMOPHINT_XXX - Additional Opcode Hints
1403	* @note These are ORed together with IEMOPFORM_XXX.
1404	* @{ */
1405	/** Ignores the operand size prefix (66h). */
1406	#define IEMOPHINT_IGNORES_OZ_PFX RT_BIT_32(10)
1407	/** Ignores REX.W (aka WIG). */
1408	#define IEMOPHINT_IGNORES_REXW RT_BIT_32(11)
1409	/** Both the operand size prefixes (66h + REX.W) are ignored. */
1410	#define IEMOPHINT_IGNORES_OP_SIZES (IEMOPHINT_IGNORES_OZ_PFX \| IEMOPHINT_IGNORES_REXW)
1411	/** Allowed with the lock prefix. */
1412	#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
1413	/** The VEX.L value is ignored (aka LIG). */
1414	#define IEMOPHINT_VEX_L_IGNORED RT_BIT_32(12)
1415	/** The VEX.L value must be zero (i.e. 128-bit width only). */
1416	#define IEMOPHINT_VEX_L_ZERO RT_BIT_32(13)
1417	/** The VEX.V value must be zero. */
1418	#define IEMOPHINT_VEX_V_ZERO RT_BIT_32(14)
1419
1420	/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
1421	#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
1422	/** @} */
1423
1424	/**
1425	* Possible hardware task switch sources.
1426	*/
1427	typedef enum IEMTASKSWITCH
1428	{
1429	/** Task switch caused by an interrupt/exception. */
1430	IEMTASKSWITCH_INT_XCPT = 1,
1431	/** Task switch caused by a far CALL. */
1432	IEMTASKSWITCH_CALL,
1433	/** Task switch caused by a far JMP. */
1434	IEMTASKSWITCH_JUMP,
1435	/** Task switch caused by an IRET. */
1436	IEMTASKSWITCH_IRET
1437	} IEMTASKSWITCH;
1438	AssertCompileSize(IEMTASKSWITCH, 4);
1439
1440	/**
1441	* Possible CrX load (write) sources.
1442	*/
1443	typedef enum IEMACCESSCRX
1444	{
1445	/** CrX access caused by 'mov crX' instruction. */
1446	IEMACCESSCRX_MOV_CRX,
1447	/** CrX (CR0) write caused by 'lmsw' instruction. */
1448	IEMACCESSCRX_LMSW,
1449	/** CrX (CR0) write caused by 'clts' instruction. */
1450	IEMACCESSCRX_CLTS,
1451	/** CrX (CR0) read caused by 'smsw' instruction. */
1452	IEMACCESSCRX_SMSW
1453	} IEMACCESSCRX;
1454
1455	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1456	/** @name IEM_SLAT_FAIL_XXX - Second-level address translation failure information.
1457	*
1458	* These flags provide further context to SLAT page-walk failures that could not be
1459	* determined by PGM (e.g, PGM is not privy to memory access permissions).
1460	*
1461	* @{
1462	*/
1463	/** Translating a nested-guest linear address failed accessing a nested-guest
1464	* physical address. */
1465	# define IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR RT_BIT_32(0)
1466	/** Translating a nested-guest linear address failed accessing a
1467	* paging-structure entry or updating accessed/dirty bits. */
1468	# define IEM_SLAT_FAIL_LINEAR_TO_PAGE_TABLE RT_BIT_32(1)
1469	/** @} */
1470
1471	DECLCALLBACK(FNPGMPHYSHANDLER) iemVmxApicAccessPageHandler;
1472	# ifndef IN_RING3
1473	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) iemVmxApicAccessPagePfHandler;
1474	# endif
1475	#endif
1476
1477	/**
1478	* Indicates to the verifier that the given flag set is undefined.
1479	*
1480	* Can be invoked again to add more flags.
1481	*
1482	* This is a NOOP if the verifier isn't compiled in.
1483	*
1484	* @note We're temporarily keeping this until code is converted to new
1485	* disassembler style opcode handling.
1486	*/
1487	#define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
1488
1489
1490	/** @def IEM_DECL_IMPL_TYPE
1491	* For typedef'ing an instruction implementation function.
1492	*
1493	* @param a_RetType The return type.
1494	* @param a_Name The name of the type.
1495	* @param a_ArgList The argument list enclosed in parentheses.
1496	*/
1497
1498	/** @def IEM_DECL_IMPL_DEF
1499	* For defining an instruction implementation function.
1500	*
1501	* @param a_RetType The return type.
1502	* @param a_Name The name of the type.
1503	* @param a_ArgList The argument list enclosed in parentheses.
1504	*/
1505
1506	#if defined(__GNUC__) && defined(RT_ARCH_X86)
1507	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1508	__attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
1509	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1510	__attribute__((__fastcall__, __nothrow__)) a_RetType a_Name a_ArgList
1511	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1512	__attribute__((__fastcall__, __nothrow__)) a_RetType a_Name a_ArgList
1513
1514	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
1515	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1516	a_RetType (__fastcall a_Name) a_ArgList
1517	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1518	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
1519	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1520	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
1521
1522	#elif __cplusplus >= 201700 /* P0012R1 support */
1523	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1524	a_RetType (VBOXCALL a_Name) a_ArgList RT_NOEXCEPT
1525	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1526	a_RetType VBOXCALL a_Name a_ArgList RT_NOEXCEPT
1527	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1528	a_RetType VBOXCALL a_Name a_ArgList RT_NOEXCEPT
1529
1530	#else
1531	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1532	a_RetType (VBOXCALL a_Name) a_ArgList
1533	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1534	a_RetType VBOXCALL a_Name a_ArgList
1535	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1536	a_RetType VBOXCALL a_Name a_ArgList
1537
1538	#endif
1539
1540	/** Defined in IEMAllAImplC.cpp but also used by IEMAllAImplA.asm. */
1541	RT_C_DECLS_BEGIN
1542	extern uint8_t const g_afParity[256];
1543	RT_C_DECLS_END
1544
1545
1546	/** @name Arithmetic assignment operations on bytes (binary).
1547	* @{ */
1548	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU8, (uint8_t pu8Dst, uint8_t u8Src, uint32_t pEFlags));
1549	typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
1550	FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
1551	FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
1552	FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
1553	FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
1554	FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
1555	FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
1556	FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
1557	/** @} */
1558
1559	/** @name Arithmetic assignment operations on words (binary).
1560	* @{ */
1561	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU16, (uint16_t pu16Dst, uint16_t u16Src, uint32_t pEFlags));
1562	typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
1563	FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
1564	FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
1565	FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
1566	FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
1567	FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
1568	FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
1569	FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
1570	/** @} */
1571
1572	/** @name Arithmetic assignment operations on double words (binary).
1573	* @{ */
1574	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU32, (uint32_t pu32Dst, uint32_t u32Src, uint32_t pEFlags));
1575	typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
1576	FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
1577	FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
1578	FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
1579	FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
1580	FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
1581	FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
1582	FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
1583	FNIEMAIMPLBINU32 iemAImpl_blsi_u32, iemAImpl_blsi_u32_fallback;
1584	FNIEMAIMPLBINU32 iemAImpl_blsr_u32, iemAImpl_blsr_u32_fallback;
1585	FNIEMAIMPLBINU32 iemAImpl_blsmsk_u32, iemAImpl_blsmsk_u32_fallback;
1586	/** @} */
1587
1588	/** @name Arithmetic assignment operations on quad words (binary).
1589	* @{ */
1590	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU64, (uint64_t pu64Dst, uint64_t u64Src, uint32_t pEFlags));
1591	typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
1592	FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
1593	FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
1594	FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
1595	FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
1596	FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
1597	FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
1598	FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
1599	FNIEMAIMPLBINU64 iemAImpl_blsi_u64, iemAImpl_blsi_u64_fallback;
1600	FNIEMAIMPLBINU64 iemAImpl_blsr_u64, iemAImpl_blsr_u64_fallback;
1601	FNIEMAIMPLBINU64 iemAImpl_blsmsk_u64, iemAImpl_blsmsk_u64_fallback;
1602	/** @} */
1603
1604	/** @name Compare operations (thrown in with the binary ops).
1605	* @{ */
1606	FNIEMAIMPLBINU8 iemAImpl_cmp_u8;
1607	FNIEMAIMPLBINU16 iemAImpl_cmp_u16;
1608	FNIEMAIMPLBINU32 iemAImpl_cmp_u32;
1609	FNIEMAIMPLBINU64 iemAImpl_cmp_u64;
1610	/** @} */
1611
1612	/** @name Test operations (thrown in with the binary ops).
1613	* @{ */
1614	FNIEMAIMPLBINU8 iemAImpl_test_u8;
1615	FNIEMAIMPLBINU16 iemAImpl_test_u16;
1616	FNIEMAIMPLBINU32 iemAImpl_test_u32;
1617	FNIEMAIMPLBINU64 iemAImpl_test_u64;
1618	/** @} */
1619
1620	/** @name Bit operations operations (thrown in with the binary ops).
1621	* @{ */
1622	FNIEMAIMPLBINU16 iemAImpl_bt_u16;
1623	FNIEMAIMPLBINU32 iemAImpl_bt_u32;
1624	FNIEMAIMPLBINU64 iemAImpl_bt_u64;
1625	FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
1626	FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
1627	FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
1628	FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
1629	FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
1630	FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
1631	FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
1632	FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
1633	FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
1634	/** @} */
1635
1636	/** @name Arithmetic three operand operations on double words (binary).
1637	* @{ */
1638	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32, (uint32_t pu32Dst, uint32_t u32Src1, uint32_t u32Src2, uint32_t pEFlags));
1639	typedef FNIEMAIMPLBINVEXU32 *PFNIEMAIMPLBINVEXU32;
1640	FNIEMAIMPLBINVEXU32 iemAImpl_andn_u32, iemAImpl_andn_u32_fallback;
1641	FNIEMAIMPLBINVEXU32 iemAImpl_bextr_u32, iemAImpl_bextr_u32_fallback;
1642	FNIEMAIMPLBINVEXU32 iemAImpl_bzhi_u32, iemAImpl_bzhi_u32_fallback;
1643	/** @} */
1644
1645	/** @name Arithmetic three operand operations on quad words (binary).
1646	* @{ */
1647	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64, (uint64_t pu64Dst, uint64_t u64Src1, uint64_t u64Src2, uint32_t pEFlags));
1648	typedef FNIEMAIMPLBINVEXU64 *PFNIEMAIMPLBINVEXU64;
1649	FNIEMAIMPLBINVEXU64 iemAImpl_andn_u64, iemAImpl_andn_u64_fallback;
1650	FNIEMAIMPLBINVEXU64 iemAImpl_bextr_u64, iemAImpl_bextr_u64_fallback;
1651	FNIEMAIMPLBINVEXU64 iemAImpl_bzhi_u64, iemAImpl_bzhi_u64_fallback;
1652	/** @} */
1653
1654	/** @name Arithmetic three operand operations on double words w/o EFLAGS (binary).
1655	* @{ */
1656	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32NOEFL, (uint32_t *pu32Dst, uint32_t u32Src1, uint32_t u32Src2));
1657	typedef FNIEMAIMPLBINVEXU32NOEFL *PFNIEMAIMPLBINVEXU32NOEFL;
1658	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pdep_u32, iemAImpl_pdep_u32_fallback;
1659	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pext_u32, iemAImpl_pext_u32_fallback;
1660	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_sarx_u32, iemAImpl_sarx_u32_fallback;
1661	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shlx_u32, iemAImpl_shlx_u32_fallback;
1662	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shrx_u32, iemAImpl_shrx_u32_fallback;
1663	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_rorx_u32;
1664	/** @} */
1665
1666	/** @name Arithmetic three operand operations on quad words w/o EFLAGS (binary).
1667	* @{ */
1668	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64NOEFL, (uint64_t *pu64Dst, uint64_t u64Src1, uint64_t u64Src2));
1669	typedef FNIEMAIMPLBINVEXU64NOEFL *PFNIEMAIMPLBINVEXU64NOEFL;
1670	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pdep_u64, iemAImpl_pdep_u64_fallback;
1671	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pext_u64, iemAImpl_pext_u64_fallback;
1672	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_sarx_u64, iemAImpl_sarx_u64_fallback;
1673	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shlx_u64, iemAImpl_shlx_u64_fallback;
1674	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shrx_u64, iemAImpl_shrx_u64_fallback;
1675	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_rorx_u64;
1676	/** @} */
1677
1678	/** @name MULX 32-bit and 64-bit.
1679	* @{ */
1680	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU32, (uint32_t puDst1, uint32_t puDst2, uint32_t uSrc1, uint32_t uSrc2));
1681	typedef FNIEMAIMPLMULXVEXU32 *PFNIEMAIMPLMULXVEXU32;
1682	FNIEMAIMPLMULXVEXU32 iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback;
1683
1684	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU64, (uint64_t puDst1, uint64_t puDst2, uint64_t uSrc1, uint64_t uSrc2));
1685	typedef FNIEMAIMPLMULXVEXU64 *PFNIEMAIMPLMULXVEXU64;
1686	FNIEMAIMPLMULXVEXU64 iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback;
1687	/** @} */
1688
1689
1690	/** @name Exchange memory with register operations.
1691	* @{ */
1692	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_locked, (uint8_t pu8Mem, uint8_t pu8Reg));
1693	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_locked,(uint16_t pu16Mem, uint16_t pu16Reg));
1694	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_locked,(uint32_t pu32Mem, uint32_t pu32Reg));
1695	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_locked,(uint64_t pu64Mem, uint64_t pu64Reg));
1696	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_unlocked, (uint8_t pu8Mem, uint8_t pu8Reg));
1697	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_unlocked,(uint16_t pu16Mem, uint16_t pu16Reg));
1698	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_unlocked,(uint32_t pu32Mem, uint32_t pu32Reg));
1699	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_unlocked,(uint64_t pu64Mem, uint64_t pu64Reg));
1700	/** @} */
1701
1702	/** @name Exchange and add operations.
1703	* @{ */
1704	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1705	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1706	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1707	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1708	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1709	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1710	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1711	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1712	/** @} */
1713
1714	/** @name Compare and exchange.
1715	* @{ */
1716	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1717	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1718	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1719	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1720	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1721	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1722	#if ARCH_BITS == 32
1723	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1724	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1725	#else
1726	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1727	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1728	#endif
1729	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1730	uint32_t *pEFlags));
1731	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1732	uint32_t *pEFlags));
1733	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1734	uint32_t *pEFlags));
1735	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1736	uint32_t *pEFlags));
1737	#ifndef RT_ARCH_ARM64
1738	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
1739	PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
1740	#endif
1741	/** @} */
1742
1743	/** @name Memory ordering
1744	* @{ */
1745	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
1746	typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
1747	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
1748	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
1749	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
1750	#ifndef RT_ARCH_ARM64
1751	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
1752	#endif
1753	/** @} */
1754
1755	/** @name Double precision shifts
1756	* @{ */
1757	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t pEFlags));
1758	typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
1759	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t pEFlags));
1760	typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
1761	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t pEFlags));
1762	typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
1763	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16, iemAImpl_shld_u16_amd, iemAImpl_shld_u16_intel;
1764	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32, iemAImpl_shld_u32_amd, iemAImpl_shld_u32_intel;
1765	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64, iemAImpl_shld_u64_amd, iemAImpl_shld_u64_intel;
1766	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16, iemAImpl_shrd_u16_amd, iemAImpl_shrd_u16_intel;
1767	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32, iemAImpl_shrd_u32_amd, iemAImpl_shrd_u32_intel;
1768	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64, iemAImpl_shrd_u64_amd, iemAImpl_shrd_u64_intel;
1769	/** @} */
1770
1771
1772	/** @name Bit search operations (thrown in with the binary ops).
1773	* @{ */
1774	FNIEMAIMPLBINU16 iemAImpl_bsf_u16, iemAImpl_bsf_u16_amd, iemAImpl_bsf_u16_intel;
1775	FNIEMAIMPLBINU32 iemAImpl_bsf_u32, iemAImpl_bsf_u32_amd, iemAImpl_bsf_u32_intel;
1776	FNIEMAIMPLBINU64 iemAImpl_bsf_u64, iemAImpl_bsf_u64_amd, iemAImpl_bsf_u64_intel;
1777	FNIEMAIMPLBINU16 iemAImpl_bsr_u16, iemAImpl_bsr_u16_amd, iemAImpl_bsr_u16_intel;
1778	FNIEMAIMPLBINU32 iemAImpl_bsr_u32, iemAImpl_bsr_u32_amd, iemAImpl_bsr_u32_intel;
1779	FNIEMAIMPLBINU64 iemAImpl_bsr_u64, iemAImpl_bsr_u64_amd, iemAImpl_bsr_u64_intel;
1780	FNIEMAIMPLBINU16 iemAImpl_lzcnt_u16, iemAImpl_lzcnt_u16_amd, iemAImpl_lzcnt_u16_intel;
1781	FNIEMAIMPLBINU32 iemAImpl_lzcnt_u32, iemAImpl_lzcnt_u32_amd, iemAImpl_lzcnt_u32_intel;
1782	FNIEMAIMPLBINU64 iemAImpl_lzcnt_u64, iemAImpl_lzcnt_u64_amd, iemAImpl_lzcnt_u64_intel;
1783	FNIEMAIMPLBINU16 iemAImpl_tzcnt_u16, iemAImpl_tzcnt_u16_amd, iemAImpl_tzcnt_u16_intel;
1784	FNIEMAIMPLBINU32 iemAImpl_tzcnt_u32, iemAImpl_tzcnt_u32_amd, iemAImpl_tzcnt_u32_intel;
1785	FNIEMAIMPLBINU64 iemAImpl_tzcnt_u64, iemAImpl_tzcnt_u64_amd, iemAImpl_tzcnt_u64_intel;
1786	FNIEMAIMPLBINU16 iemAImpl_popcnt_u16, iemAImpl_popcnt_u16_fallback;
1787	FNIEMAIMPLBINU32 iemAImpl_popcnt_u32, iemAImpl_popcnt_u32_fallback;
1788	FNIEMAIMPLBINU64 iemAImpl_popcnt_u64, iemAImpl_popcnt_u64_fallback;
1789	/** @} */
1790
1791	/** @name Signed multiplication operations (thrown in with the binary ops).
1792	* @{ */
1793	FNIEMAIMPLBINU16 iemAImpl_imul_two_u16, iemAImpl_imul_two_u16_amd, iemAImpl_imul_two_u16_intel;
1794	FNIEMAIMPLBINU32 iemAImpl_imul_two_u32, iemAImpl_imul_two_u32_amd, iemAImpl_imul_two_u32_intel;
1795	FNIEMAIMPLBINU64 iemAImpl_imul_two_u64, iemAImpl_imul_two_u64_amd, iemAImpl_imul_two_u64_intel;
1796	/** @} */
1797
1798	/** @name Arithmetic assignment operations on bytes (unary).
1799	* @{ */
1800	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t pu8Dst, uint32_t pEFlags));
1801	typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
1802	FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
1803	FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
1804	FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
1805	FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
1806	/** @} */
1807
1808	/** @name Arithmetic assignment operations on words (unary).
1809	* @{ */
1810	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t pu16Dst, uint32_t pEFlags));
1811	typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
1812	FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
1813	FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
1814	FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
1815	FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
1816	/** @} */
1817
1818	/** @name Arithmetic assignment operations on double words (unary).
1819	* @{ */
1820	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t pu32Dst, uint32_t pEFlags));
1821	typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
1822	FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
1823	FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
1824	FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
1825	FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
1826	/** @} */
1827
1828	/** @name Arithmetic assignment operations on quad words (unary).
1829	* @{ */
1830	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t pu64Dst, uint32_t pEFlags));
1831	typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
1832	FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
1833	FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
1834	FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
1835	FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
1836	/** @} */
1837
1838
1839	/** @name Shift operations on bytes (Group 2).
1840	* @{ */
1841	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU8,(uint8_t pu8Dst, uint8_t cShift, uint32_t pEFlags));
1842	typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
1843	FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8, iemAImpl_rol_u8_amd, iemAImpl_rol_u8_intel;
1844	FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8, iemAImpl_ror_u8_amd, iemAImpl_ror_u8_intel;
1845	FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8, iemAImpl_rcl_u8_amd, iemAImpl_rcl_u8_intel;
1846	FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8, iemAImpl_rcr_u8_amd, iemAImpl_rcr_u8_intel;
1847	FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8, iemAImpl_shl_u8_amd, iemAImpl_shl_u8_intel;
1848	FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8, iemAImpl_shr_u8_amd, iemAImpl_shr_u8_intel;
1849	FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8, iemAImpl_sar_u8_amd, iemAImpl_sar_u8_intel;
1850	/** @} */
1851
1852	/** @name Shift operations on words (Group 2).
1853	* @{ */
1854	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU16,(uint16_t pu16Dst, uint8_t cShift, uint32_t pEFlags));
1855	typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
1856	FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16, iemAImpl_rol_u16_amd, iemAImpl_rol_u16_intel;
1857	FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16, iemAImpl_ror_u16_amd, iemAImpl_ror_u16_intel;
1858	FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16, iemAImpl_rcl_u16_amd, iemAImpl_rcl_u16_intel;
1859	FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16, iemAImpl_rcr_u16_amd, iemAImpl_rcr_u16_intel;
1860	FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16, iemAImpl_shl_u16_amd, iemAImpl_shl_u16_intel;
1861	FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16, iemAImpl_shr_u16_amd, iemAImpl_shr_u16_intel;
1862	FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16, iemAImpl_sar_u16_amd, iemAImpl_sar_u16_intel;
1863	/** @} */
1864
1865	/** @name Shift operations on double words (Group 2).
1866	* @{ */
1867	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU32,(uint32_t pu32Dst, uint8_t cShift, uint32_t pEFlags));
1868	typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
1869	FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32, iemAImpl_rol_u32_amd, iemAImpl_rol_u32_intel;
1870	FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32, iemAImpl_ror_u32_amd, iemAImpl_ror_u32_intel;
1871	FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32, iemAImpl_rcl_u32_amd, iemAImpl_rcl_u32_intel;
1872	FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32, iemAImpl_rcr_u32_amd, iemAImpl_rcr_u32_intel;
1873	FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32, iemAImpl_shl_u32_amd, iemAImpl_shl_u32_intel;
1874	FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32, iemAImpl_shr_u32_amd, iemAImpl_shr_u32_intel;
1875	FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32, iemAImpl_sar_u32_amd, iemAImpl_sar_u32_intel;
1876	/** @} */
1877
1878	/** @name Shift operations on words (Group 2).
1879	* @{ */
1880	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU64,(uint64_t pu64Dst, uint8_t cShift, uint32_t pEFlags));
1881	typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
1882	FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64, iemAImpl_rol_u64_amd, iemAImpl_rol_u64_intel;
1883	FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64, iemAImpl_ror_u64_amd, iemAImpl_ror_u64_intel;
1884	FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64, iemAImpl_rcl_u64_amd, iemAImpl_rcl_u64_intel;
1885	FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64, iemAImpl_rcr_u64_amd, iemAImpl_rcr_u64_intel;
1886	FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64, iemAImpl_shl_u64_amd, iemAImpl_shl_u64_intel;
1887	FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64, iemAImpl_shr_u64_amd, iemAImpl_shr_u64_intel;
1888	FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64, iemAImpl_sar_u64_amd, iemAImpl_sar_u64_intel;
1889	/** @} */
1890
1891	/** @name Multiplication and division operations.
1892	* @{ */
1893	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t pu16AX, uint8_t u8FactorDivisor, uint32_t pEFlags));
1894	typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
1895	FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_mul_u8_amd, iemAImpl_mul_u8_intel;
1896	FNIEMAIMPLMULDIVU8 iemAImpl_imul_u8, iemAImpl_imul_u8_amd, iemAImpl_imul_u8_intel;
1897	FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_div_u8_amd, iemAImpl_div_u8_intel;
1898	FNIEMAIMPLMULDIVU8 iemAImpl_idiv_u8, iemAImpl_idiv_u8_amd, iemAImpl_idiv_u8_intel;
1899
1900	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t pu16AX, uint16_t pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
1901	typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
1902	FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_mul_u16_amd, iemAImpl_mul_u16_intel;
1903	FNIEMAIMPLMULDIVU16 iemAImpl_imul_u16, iemAImpl_imul_u16_amd, iemAImpl_imul_u16_intel;
1904	FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_div_u16_amd, iemAImpl_div_u16_intel;
1905	FNIEMAIMPLMULDIVU16 iemAImpl_idiv_u16, iemAImpl_idiv_u16_amd, iemAImpl_idiv_u16_intel;
1906
1907	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t pu32EAX, uint32_t pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
1908	typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
1909	FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_mul_u32_amd, iemAImpl_mul_u32_intel;
1910	FNIEMAIMPLMULDIVU32 iemAImpl_imul_u32, iemAImpl_imul_u32_amd, iemAImpl_imul_u32_intel;
1911	FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_div_u32_amd, iemAImpl_div_u32_intel;
1912	FNIEMAIMPLMULDIVU32 iemAImpl_idiv_u32, iemAImpl_idiv_u32_amd, iemAImpl_idiv_u32_intel;
1913
1914	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t pu64RAX, uint64_t pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
1915	typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
1916	FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_mul_u64_amd, iemAImpl_mul_u64_intel;
1917	FNIEMAIMPLMULDIVU64 iemAImpl_imul_u64, iemAImpl_imul_u64_amd, iemAImpl_imul_u64_intel;
1918	FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_div_u64_amd, iemAImpl_div_u64_intel;
1919	FNIEMAIMPLMULDIVU64 iemAImpl_idiv_u64, iemAImpl_idiv_u64_amd, iemAImpl_idiv_u64_intel;
1920	/** @} */
1921
1922	/** @name Byte Swap.
1923	* @{ */
1924	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t pu32Dst)); / Yes, 32-bit register access. */
1925	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
1926	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
1927	/** @} */
1928
1929	/** @name Misc.
1930	* @{ */
1931	FNIEMAIMPLBINU16 iemAImpl_arpl;
1932	/** @} */
1933
1934	/** @name RDRAND and RDSEED
1935	* @{ */
1936	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU16,(uint16_t puDst, uint32_t pEFlags));
1937	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU32,(uint32_t puDst, uint32_t pEFlags));
1938	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU64,(uint64_t puDst, uint32_t pEFlags));
1939	typedef FNIEMAIMPLRDRANDSEEDU16 *FNIEMAIMPLPRDRANDSEEDU16;
1940	typedef FNIEMAIMPLRDRANDSEEDU32 *FNIEMAIMPLPRDRANDSEEDU32;
1941	typedef FNIEMAIMPLRDRANDSEEDU64 *FNIEMAIMPLPRDRANDSEEDU64;
1942
1943	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdrand_u16, iemAImpl_rdrand_u16_fallback;
1944	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdrand_u32, iemAImpl_rdrand_u32_fallback;
1945	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdrand_u64, iemAImpl_rdrand_u64_fallback;
1946	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdseed_u16, iemAImpl_rdseed_u16_fallback;
1947	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdseed_u32, iemAImpl_rdseed_u32_fallback;
1948	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdseed_u64, iemAImpl_rdseed_u64_fallback;
1949	/** @} */
1950
1951	/** @name ADOX and ADCX
1952	* @{ */
1953	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLADXU32,(uint32_t puDst, uint32_t pfEFlags, uint32_t uSrc));
1954	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLADXU64,(uint64_t puDst, uint32_t pfEFlags, uint64_t uSrc));
1955	typedef FNIEMAIMPLADXU32 *PFNIEMAIMPLADXU32;
1956	typedef FNIEMAIMPLADXU64 *PFNIEMAIMPLADXU64;
1957
1958	FNIEMAIMPLADXU32 iemAImpl_adcx_u32, iemAImpl_adcx_u32_fallback;
1959	FNIEMAIMPLADXU64 iemAImpl_adcx_u64, iemAImpl_adcx_u64_fallback;
1960	FNIEMAIMPLADXU32 iemAImpl_adox_u32, iemAImpl_adox_u32_fallback;
1961	FNIEMAIMPLADXU64 iemAImpl_adox_u64, iemAImpl_adox_u64_fallback;
1962	/** @} */
1963
1964	/** @name FPU operations taking a 32-bit float argument
1965	* @{ */
1966	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1967	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1968	typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
1969
1970	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1971	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1972	typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
1973
1974	FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
1975	FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
1976	FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
1977	FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
1978	FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
1979	FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
1980	FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
1981
1982	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
1983	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1984	PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
1985	/** @} */
1986
1987	/** @name FPU operations taking a 64-bit float argument
1988	* @{ */
1989	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1990	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1991	typedef FNIEMAIMPLFPUR64FSW *PFNIEMAIMPLFPUR64FSW;
1992
1993	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1994	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1995	typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
1996
1997	FNIEMAIMPLFPUR64FSW iemAImpl_fcom_r80_by_r64;
1998	FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
1999	FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
2000	FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
2001	FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
2002	FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
2003	FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
2004
2005	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
2006	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2007	PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
2008	/** @} */
2009
2010	/** @name FPU operations taking a 80-bit float argument
2011	* @{ */
2012	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2013	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
2014	typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
2015	FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
2016	FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
2017	FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
2018	FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
2019	FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
2020	FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
2021	FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
2022	FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
2023	FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
2024
2025	FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80, iemAImpl_fpatan_r80_by_r80_amd, iemAImpl_fpatan_r80_by_r80_intel;
2026	FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80, iemAImpl_fyl2x_r80_by_r80_amd, iemAImpl_fyl2x_r80_by_r80_intel;
2027	FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80, iemAImpl_fyl2xp1_r80_by_r80_amd, iemAImpl_fyl2xp1_r80_by_r80_intel;
2028
2029	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2030	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
2031	typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
2032	FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
2033	FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
2034
2035	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
2036	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
2037	typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
2038	FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
2039	FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
2040
2041	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
2042	typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
2043	FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
2044	FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
2045	FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80, iemAImpl_f2xm1_r80_amd, iemAImpl_f2xm1_r80_intel;
2046	FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
2047	FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
2048	FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80, iemAImpl_fsin_r80_amd, iemAImpl_fsin_r80_intel;
2049	FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80, iemAImpl_fcos_r80_amd, iemAImpl_fcos_r80_intel;
2050
2051	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
2052	typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
2053	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
2054	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
2055
2056	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
2057	typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
2058	FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
2059	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
2060	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
2061	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
2062	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
2063	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
2064	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
2065
2066	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
2067	PCRTFLOAT80U pr80Val));
2068	typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
2069	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80, iemAImpl_fptan_r80_r80_amd, iemAImpl_fptan_r80_r80_intel;
2070	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
2071	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80, iemAImpl_fsincos_r80_r80_amd, iemAImpl_fsincos_r80_r80_intel;
2072
2073	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
2074	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2075	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
2076
2077	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_d80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTPBCD80U pd80Val));
2078	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_d80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2079	PRTPBCD80U pd80Dst, PCRTFLOAT80U pr80Src));
2080
2081	/** @} */
2082
2083	/** @name FPU operations taking a 16-bit signed integer argument
2084	* @{ */
2085	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2086	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
2087	typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
2088	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI16,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
2089	int16_t *pi16Dst, PCRTFLOAT80U pr80Src));
2090	typedef FNIEMAIMPLFPUSTR80TOI16 *PFNIEMAIMPLFPUSTR80TOI16;
2091
2092	FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
2093	FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
2094	FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
2095	FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
2096	FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
2097	FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
2098
2099	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2100	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
2101	typedef FNIEMAIMPLFPUI16FSW *PFNIEMAIMPLFPUI16FSW;
2102	FNIEMAIMPLFPUI16FSW iemAImpl_ficom_r80_by_i16;
2103
2104	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
2105	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fist_r80_to_i16;
2106	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fistt_r80_to_i16, iemAImpl_fistt_r80_to_i16_amd, iemAImpl_fistt_r80_to_i16_intel;
2107	/** @} */
2108
2109	/** @name FPU operations taking a 32-bit signed integer argument
2110	* @{ */
2111	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2112	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
2113	typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
2114	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI32,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
2115	int32_t *pi32Dst, PCRTFLOAT80U pr80Src));
2116	typedef FNIEMAIMPLFPUSTR80TOI32 *PFNIEMAIMPLFPUSTR80TOI32;
2117
2118	FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
2119	FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
2120	FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
2121	FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
2122	FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
2123	FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
2124
2125	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2126	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
2127	typedef FNIEMAIMPLFPUI32FSW *PFNIEMAIMPLFPUI32FSW;
2128	FNIEMAIMPLFPUI32FSW iemAImpl_ficom_r80_by_i32;
2129
2130	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
2131	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fist_r80_to_i32;
2132	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fistt_r80_to_i32;
2133	/** @} */
2134
2135	/** @name FPU operations taking a 64-bit signed integer argument
2136	* @{ */
2137	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI64,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
2138	int64_t *pi64Dst, PCRTFLOAT80U pr80Src));
2139	typedef FNIEMAIMPLFPUSTR80TOI64 *PFNIEMAIMPLFPUSTR80TOI64;
2140
2141	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
2142	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fist_r80_to_i64;
2143	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fistt_r80_to_i64;
2144	/** @} */
2145
2146
2147	/** Temporary type representing a 256-bit vector register. */
2148	typedef struct { uint64_t au64[4]; } IEMVMM256;
2149	/** Temporary type pointing to a 256-bit vector register. */
2150	typedef IEMVMM256 *PIEMVMM256;
2151	/** Temporary type pointing to a const 256-bit vector register. */
2152	typedef IEMVMM256 *PCIEMVMM256;
2153
2154
2155	/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
2156	* @{ */
2157	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t puDst, uint64_t const puSrc));
2158	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
2159	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U128,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
2160	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
2161	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U128,(PX86XSAVEAREA pExtState, PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
2162	typedef FNIEMAIMPLMEDIAF3U128 *PFNIEMAIMPLMEDIAF3U128;
2163	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U256,(PX86XSAVEAREA pExtState, PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
2164	typedef FNIEMAIMPLMEDIAF3U256 *PFNIEMAIMPLMEDIAF3U256;
2165	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U64,(uint64_t puDst, uint64_t const puSrc));
2166	typedef FNIEMAIMPLMEDIAOPTF2U64 *PFNIEMAIMPLMEDIAOPTF2U64;
2167	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128,(PRTUINT128U puDst, PCRTUINT128U puSrc));
2168	typedef FNIEMAIMPLMEDIAOPTF2U128 *PFNIEMAIMPLMEDIAOPTF2U128;
2169	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
2170	typedef FNIEMAIMPLMEDIAOPTF3U128 *PFNIEMAIMPLMEDIAOPTF3U128;
2171	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
2172	typedef FNIEMAIMPLMEDIAOPTF3U256 *PFNIEMAIMPLMEDIAOPTF3U256;
2173	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256,(PRTUINT256U puDst, PCRTUINT256U puSrc));
2174	typedef FNIEMAIMPLMEDIAOPTF2U256 *PFNIEMAIMPLMEDIAOPTF2U256;
2175	FNIEMAIMPLMEDIAF2U64 iemAImpl_pshufb_u64, iemAImpl_pshufb_u64_fallback;
2176	FNIEMAIMPLMEDIAF2U64 iemAImpl_pand_u64, iemAImpl_pandn_u64, iemAImpl_por_u64, iemAImpl_pxor_u64;
2177	FNIEMAIMPLMEDIAF2U64 iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
2178	FNIEMAIMPLMEDIAF2U64 iemAImpl_pcmpgtb_u64, iemAImpl_pcmpgtw_u64, iemAImpl_pcmpgtd_u64;
2179	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddb_u64, iemAImpl_paddsb_u64, iemAImpl_paddusb_u64;
2180	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddw_u64, iemAImpl_paddsw_u64, iemAImpl_paddusw_u64;
2181	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddd_u64;
2182	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddq_u64;
2183	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubb_u64, iemAImpl_psubsb_u64, iemAImpl_psubusb_u64;
2184	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubw_u64, iemAImpl_psubsw_u64, iemAImpl_psubusw_u64;
2185	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubd_u64;
2186	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubq_u64;
2187	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmaddwd_u64;
2188	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmullw_u64, iemAImpl_pmulhw_u64;
2189	FNIEMAIMPLMEDIAF2U64 iemAImpl_pminub_u64, iemAImpl_pmaxub_u64;
2190	FNIEMAIMPLMEDIAF2U64 iemAImpl_pminsw_u64, iemAImpl_pmaxsw_u64;
2191	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsb_u64, iemAImpl_pabsb_u64_fallback;
2192	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsw_u64, iemAImpl_pabsw_u64_fallback;
2193	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsd_u64, iemAImpl_pabsd_u64_fallback;
2194	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignb_u64, iemAImpl_psignb_u64_fallback;
2195	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignw_u64, iemAImpl_psignw_u64_fallback;
2196	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignd_u64, iemAImpl_psignd_u64_fallback;
2197	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddw_u64, iemAImpl_phaddw_u64_fallback;
2198	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddd_u64, iemAImpl_phaddd_u64_fallback;
2199	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubw_u64, iemAImpl_phsubw_u64_fallback;
2200	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubd_u64, iemAImpl_phsubd_u64_fallback;
2201	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddsw_u64, iemAImpl_phaddsw_u64_fallback;
2202	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubsw_u64, iemAImpl_phsubsw_u64_fallback;
2203	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmaddubsw_u64, iemAImpl_pmaddubsw_u64_fallback;
2204	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmulhrsw_u64, iemAImpl_pmulhrsw_u64_fallback;
2205	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmuludq_u64;
2206	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllw_u64, iemAImpl_psrlw_u64, iemAImpl_psraw_u64;
2207	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pslld_u64, iemAImpl_psrld_u64, iemAImpl_psrad_u64;
2208	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllq_u64, iemAImpl_psrlq_u64;
2209	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packsswb_u64, iemAImpl_packuswb_u64;
2210	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packssdw_u64;
2211	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhuw_u64;
2212	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pavgb_u64, iemAImpl_pavgw_u64;
2213	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psadbw_u64;
2214
2215	FNIEMAIMPLMEDIAF2U128 iemAImpl_pshufb_u128, iemAImpl_pshufb_u128_fallback;
2216	FNIEMAIMPLMEDIAF2U128 iemAImpl_pand_u128, iemAImpl_pandn_u128, iemAImpl_por_u128, iemAImpl_pxor_u128;
2217	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
2218	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpeqq_u128, iemAImpl_pcmpeqq_u128_fallback;
2219	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpgtb_u128, iemAImpl_pcmpgtw_u128, iemAImpl_pcmpgtd_u128;
2220	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpgtq_u128, iemAImpl_pcmpgtq_u128_fallback;
2221	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddb_u128, iemAImpl_paddsb_u128, iemAImpl_paddusb_u128;
2222	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddw_u128, iemAImpl_paddsw_u128, iemAImpl_paddusw_u128;
2223	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddd_u128;
2224	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddq_u128;
2225	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubb_u128, iemAImpl_psubsb_u128, iemAImpl_psubusb_u128;
2226	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubw_u128, iemAImpl_psubsw_u128, iemAImpl_psubusw_u128;
2227	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubd_u128;
2228	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubq_u128;
2229	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmullw_u128, iemAImpl_pmullw_u128_fallback;
2230	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulhw_u128;
2231	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulld_u128, iemAImpl_pmulld_u128_fallback;
2232	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaddwd_u128;
2233	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminub_u128;
2234	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminud_u128, iemAImpl_pminud_u128_fallback;
2235	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminuw_u128, iemAImpl_pminuw_u128_fallback;
2236	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsb_u128, iemAImpl_pminsb_u128_fallback;
2237	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsd_u128, iemAImpl_pminsd_u128_fallback;
2238	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsw_u128, iemAImpl_pminsw_u128_fallback;
2239	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxub_u128;
2240	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxud_u128, iemAImpl_pmaxud_u128_fallback;
2241	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxuw_u128, iemAImpl_pmaxuw_u128_fallback;
2242	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsb_u128, iemAImpl_pmaxsb_u128_fallback;
2243	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsw_u128;
2244	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsd_u128, iemAImpl_pmaxsd_u128_fallback;
2245	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsb_u128, iemAImpl_pabsb_u128_fallback;
2246	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsw_u128, iemAImpl_pabsw_u128_fallback;
2247	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsd_u128, iemAImpl_pabsd_u128_fallback;
2248	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignb_u128, iemAImpl_psignb_u128_fallback;
2249	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignw_u128, iemAImpl_psignw_u128_fallback;
2250	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignd_u128, iemAImpl_psignd_u128_fallback;
2251	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddw_u128, iemAImpl_phaddw_u128_fallback;
2252	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddd_u128, iemAImpl_phaddd_u128_fallback;
2253	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubw_u128, iemAImpl_phsubw_u128_fallback;
2254	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubd_u128, iemAImpl_phsubd_u128_fallback;
2255	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddsw_u128, iemAImpl_phaddsw_u128_fallback;
2256	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubsw_u128, iemAImpl_phsubsw_u128_fallback;
2257	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaddubsw_u128, iemAImpl_pmaddubsw_u128_fallback;
2258	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulhrsw_u128, iemAImpl_pmulhrsw_u128_fallback;
2259	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmuludq_u128;
2260	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packsswb_u128, iemAImpl_packuswb_u128;
2261	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packssdw_u128, iemAImpl_packusdw_u128;
2262	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllw_u128, iemAImpl_psrlw_u128, iemAImpl_psraw_u128;
2263	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pslld_u128, iemAImpl_psrld_u128, iemAImpl_psrad_u128;
2264	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllq_u128, iemAImpl_psrlq_u128;
2265	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhuw_u128;
2266	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pavgb_u128, iemAImpl_pavgw_u128;
2267	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psadbw_u128;
2268	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuldq_u128, iemAImpl_pmuldq_u128_fallback;
2269	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpcklps_u128, iemAImpl_unpcklpd_u128;
2270	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpckhps_u128, iemAImpl_unpckhpd_u128;
2271	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phminposuw_u128, iemAImpl_phminposuw_u128_fallback;
2272
2273	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpshufb_u128, iemAImpl_vpshufb_u128_fallback;
2274	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpand_u128, iemAImpl_vpand_u128_fallback;
2275	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpandn_u128, iemAImpl_vpandn_u128_fallback;
2276	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpor_u128, iemAImpl_vpor_u128_fallback;
2277	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpxor_u128, iemAImpl_vpxor_u128_fallback;
2278	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqb_u128, iemAImpl_vpcmpeqb_u128_fallback;
2279	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqw_u128, iemAImpl_vpcmpeqw_u128_fallback;
2280	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqd_u128, iemAImpl_vpcmpeqd_u128_fallback;
2281	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqq_u128, iemAImpl_vpcmpeqq_u128_fallback;
2282	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtb_u128, iemAImpl_vpcmpgtb_u128_fallback;
2283	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtw_u128, iemAImpl_vpcmpgtw_u128_fallback;
2284	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtd_u128, iemAImpl_vpcmpgtd_u128_fallback;
2285	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtq_u128, iemAImpl_vpcmpgtq_u128_fallback;
2286	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddb_u128, iemAImpl_vpaddb_u128_fallback;
2287	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddw_u128, iemAImpl_vpaddw_u128_fallback;
2288	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddd_u128, iemAImpl_vpaddd_u128_fallback;
2289	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddq_u128, iemAImpl_vpaddq_u128_fallback;
2290	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubb_u128, iemAImpl_vpsubb_u128_fallback;
2291	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubw_u128, iemAImpl_vpsubw_u128_fallback;
2292	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubd_u128, iemAImpl_vpsubd_u128_fallback;
2293	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubq_u128, iemAImpl_vpsubq_u128_fallback;
2294	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminub_u128, iemAImpl_vpminub_u128_fallback;
2295	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminuw_u128, iemAImpl_vpminuw_u128_fallback;
2296	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminud_u128, iemAImpl_vpminud_u128_fallback;
2297	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsb_u128, iemAImpl_vpminsb_u128_fallback;
2298	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsw_u128, iemAImpl_vpminsw_u128_fallback;
2299	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsd_u128, iemAImpl_vpminsd_u128_fallback;
2300	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxub_u128, iemAImpl_vpmaxub_u128_fallback;
2301	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxuw_u128, iemAImpl_vpmaxuw_u128_fallback;
2302	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxud_u128, iemAImpl_vpmaxud_u128_fallback;
2303	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsb_u128, iemAImpl_vpmaxsb_u128_fallback;
2304	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsw_u128, iemAImpl_vpmaxsw_u128_fallback;
2305	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsd_u128, iemAImpl_vpmaxsd_u128_fallback;
2306	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpacksswb_u128, iemAImpl_vpacksswb_u128_fallback;
2307	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackssdw_u128, iemAImpl_vpackssdw_u128_fallback;
2308	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackuswb_u128, iemAImpl_vpackuswb_u128_fallback;
2309	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackusdw_u128, iemAImpl_vpackusdw_u128_fallback;
2310	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmullw_u128, iemAImpl_vpmullw_u128_fallback;
2311	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulld_u128, iemAImpl_vpmulld_u128_fallback;
2312	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhw_u128, iemAImpl_vpmulhw_u128_fallback;
2313	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhuw_u128, iemAImpl_vpmulhuw_u128_fallback;
2314	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgb_u128, iemAImpl_vpavgb_u128_fallback;
2315	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgw_u128, iemAImpl_vpavgw_u128_fallback;
2316	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignb_u128, iemAImpl_vpsignb_u128_fallback;
2317	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignw_u128, iemAImpl_vpsignw_u128_fallback;
2318	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignd_u128, iemAImpl_vpsignd_u128_fallback;
2319	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddw_u128, iemAImpl_vphaddw_u128_fallback;
2320	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddd_u128, iemAImpl_vphaddd_u128_fallback;
2321	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubw_u128, iemAImpl_vphsubw_u128_fallback;
2322	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubd_u128, iemAImpl_vphsubd_u128_fallback;
2323	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddsw_u128, iemAImpl_vphaddsw_u128_fallback;
2324	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubsw_u128, iemAImpl_vphsubsw_u128_fallback;
2325	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddubsw_u128, iemAImpl_vpmaddubsw_u128_fallback;
2326	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhrsw_u128, iemAImpl_vpmulhrsw_u128_fallback;
2327	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsadbw_u128, iemAImpl_vpsadbw_u128_fallback;
2328	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuldq_u128, iemAImpl_vpmuldq_u128_fallback;
2329	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuludq_u128, iemAImpl_vpmuludq_u128_fallback;
2330
2331	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsb_u128, iemAImpl_vpabsb_u128_fallback;
2332	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsw_u128, iemAImpl_vpabsd_u128_fallback;
2333	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsd_u128, iemAImpl_vpabsw_u128_fallback;
2334	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vphminposuw_u128, iemAImpl_vphminposuw_u128_fallback;
2335
2336	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpshufb_u256, iemAImpl_vpshufb_u256_fallback;
2337	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpand_u256, iemAImpl_vpand_u256_fallback;
2338	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpandn_u256, iemAImpl_vpandn_u256_fallback;
2339	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpor_u256, iemAImpl_vpor_u256_fallback;
2340	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpxor_u256, iemAImpl_vpxor_u256_fallback;
2341	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqb_u256, iemAImpl_vpcmpeqb_u256_fallback;
2342	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqw_u256, iemAImpl_vpcmpeqw_u256_fallback;
2343	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqd_u256, iemAImpl_vpcmpeqd_u256_fallback;
2344	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqq_u256, iemAImpl_vpcmpeqq_u256_fallback;
2345	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtb_u256, iemAImpl_vpcmpgtb_u256_fallback;
2346	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtw_u256, iemAImpl_vpcmpgtw_u256_fallback;
2347	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtd_u256, iemAImpl_vpcmpgtd_u256_fallback;
2348	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtq_u256, iemAImpl_vpcmpgtq_u256_fallback;
2349	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddb_u256, iemAImpl_vpaddb_u256_fallback;
2350	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddw_u256, iemAImpl_vpaddw_u256_fallback;
2351	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddd_u256, iemAImpl_vpaddd_u256_fallback;
2352	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddq_u256, iemAImpl_vpaddq_u256_fallback;
2353	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubb_u256, iemAImpl_vpsubb_u256_fallback;
2354	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubw_u256, iemAImpl_vpsubw_u256_fallback;
2355	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubd_u256, iemAImpl_vpsubd_u256_fallback;
2356	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubq_u256, iemAImpl_vpsubq_u256_fallback;
2357	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminub_u256, iemAImpl_vpminub_u256_fallback;
2358	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminuw_u256, iemAImpl_vpminuw_u256_fallback;
2359	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminud_u256, iemAImpl_vpminud_u256_fallback;
2360	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsb_u256, iemAImpl_vpminsb_u256_fallback;
2361	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsw_u256, iemAImpl_vpminsw_u256_fallback;
2362	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsd_u256, iemAImpl_vpminsd_u256_fallback;
2363	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxub_u256, iemAImpl_vpmaxub_u256_fallback;
2364	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxuw_u256, iemAImpl_vpmaxuw_u256_fallback;
2365	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxud_u256, iemAImpl_vpmaxud_u256_fallback;
2366	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsb_u256, iemAImpl_vpmaxsb_u256_fallback;
2367	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsw_u256, iemAImpl_vpmaxsw_u256_fallback;
2368	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsd_u256, iemAImpl_vpmaxsd_u256_fallback;
2369	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpacksswb_u256, iemAImpl_vpacksswb_u256_fallback;
2370	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackssdw_u256, iemAImpl_vpackssdw_u256_fallback;
2371	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackuswb_u256, iemAImpl_vpackuswb_u256_fallback;
2372	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackusdw_u256, iemAImpl_vpackusdw_u256_fallback;
2373	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmullw_u256, iemAImpl_vpmullw_u256_fallback;
2374	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulld_u256, iemAImpl_vpmulld_u256_fallback;
2375	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhw_u256, iemAImpl_vpmulhw_u256_fallback;
2376	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhuw_u256, iemAImpl_vpmulhuw_u256_fallback;
2377	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgb_u256, iemAImpl_vpavgb_u256_fallback;
2378	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgw_u256, iemAImpl_vpavgw_u256_fallback;
2379	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignb_u256, iemAImpl_vpsignb_u256_fallback;
2380	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignw_u256, iemAImpl_vpsignw_u256_fallback;
2381	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignd_u256, iemAImpl_vpsignd_u256_fallback;
2382	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddw_u256, iemAImpl_vphaddw_u256_fallback;
2383	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddd_u256, iemAImpl_vphaddd_u256_fallback;
2384	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubw_u256, iemAImpl_vphsubw_u256_fallback;
2385	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubd_u256, iemAImpl_vphsubd_u256_fallback;
2386	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddsw_u256, iemAImpl_vphaddsw_u256_fallback;
2387	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubsw_u256, iemAImpl_vphsubsw_u256_fallback;
2388	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddubsw_u256, iemAImpl_vpmaddubsw_u256_fallback;
2389	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhrsw_u256, iemAImpl_vpmulhrsw_u256_fallback;
2390	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsadbw_u256, iemAImpl_vpsadbw_u256_fallback;
2391	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuldq_u256, iemAImpl_vpmuldq_u256_fallback;
2392	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuludq_u256, iemAImpl_vpmuludq_u256_fallback;
2393
2394	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsb_u256, iemAImpl_vpabsb_u256_fallback;
2395	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsw_u256, iemAImpl_vpabsw_u256_fallback;
2396	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsd_u256, iemAImpl_vpabsd_u256_fallback;
2397	/** @} */
2398
2399	/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
2400	* @{ */
2401	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
2402	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
2403	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpcklbw_u128, iemAImpl_vpunpcklbw_u128_fallback,
2404	iemAImpl_vpunpcklwd_u128, iemAImpl_vpunpcklwd_u128_fallback,
2405	iemAImpl_vpunpckldq_u128, iemAImpl_vpunpckldq_u128_fallback,
2406	iemAImpl_vpunpcklqdq_u128, iemAImpl_vpunpcklqdq_u128_fallback,
2407	iemAImpl_vunpcklps_u128, iemAImpl_vunpcklps_u128_fallback,
2408	iemAImpl_vunpcklpd_u128, iemAImpl_vunpcklpd_u128_fallback,
2409	iemAImpl_vunpckhps_u128, iemAImpl_vunpckhps_u128_fallback,
2410	iemAImpl_vunpckhpd_u128, iemAImpl_vunpckhpd_u128_fallback;
2411
2412	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpcklbw_u256, iemAImpl_vpunpcklbw_u256_fallback,
2413	iemAImpl_vpunpcklwd_u256, iemAImpl_vpunpcklwd_u256_fallback,
2414	iemAImpl_vpunpckldq_u256, iemAImpl_vpunpckldq_u256_fallback,
2415	iemAImpl_vpunpcklqdq_u256, iemAImpl_vpunpcklqdq_u256_fallback,
2416	iemAImpl_vunpcklps_u256, iemAImpl_vunpcklps_u256_fallback,
2417	iemAImpl_vunpcklpd_u256, iemAImpl_vunpcklpd_u256_fallback,
2418	iemAImpl_vunpckhps_u256, iemAImpl_vunpckhps_u256_fallback,
2419	iemAImpl_vunpckhpd_u256, iemAImpl_vunpckhpd_u256_fallback;
2420	/** @} */
2421
2422	/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
2423	* @{ */
2424	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
2425	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
2426	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpckhbw_u128, iemAImpl_vpunpckhbw_u128_fallback,
2427	iemAImpl_vpunpckhwd_u128, iemAImpl_vpunpckhwd_u128_fallback,
2428	iemAImpl_vpunpckhdq_u128, iemAImpl_vpunpckhdq_u128_fallback,
2429	iemAImpl_vpunpckhqdq_u128, iemAImpl_vpunpckhqdq_u128_fallback;
2430	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpckhbw_u256, iemAImpl_vpunpckhbw_u256_fallback,
2431	iemAImpl_vpunpckhwd_u256, iemAImpl_vpunpckhwd_u256_fallback,
2432	iemAImpl_vpunpckhdq_u256, iemAImpl_vpunpckhdq_u256_fallback,
2433	iemAImpl_vpunpckhqdq_u256, iemAImpl_vpunpckhqdq_u256_fallback;
2434	/** @} */
2435
2436	/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
2437	* @{ */
2438	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2439	typedef FNIEMAIMPLMEDIAPSHUFU128 *PFNIEMAIMPLMEDIAPSHUFU128;
2440	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
2441	typedef FNIEMAIMPLMEDIAPSHUFU256 *PFNIEMAIMPLMEDIAPSHUFU256;
2442	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw_u64,(uint64_t puDst, uint64_t const puSrc, uint8_t bEvil));
2443	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_pshufhw_u128, iemAImpl_pshuflw_u128, iemAImpl_pshufd_u128;
2444	#ifndef IEM_WITHOUT_ASSEMBLY
2445	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256, iemAImpl_vpshuflw_u256, iemAImpl_vpshufd_u256;
2446	#endif
2447	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256_fallback, iemAImpl_vpshuflw_u256_fallback, iemAImpl_vpshufd_u256_fallback;
2448	/** @} */
2449
2450	/** @name Media (SSE/MMX/AVX) operation: Shift Immediate Stuff (evil)
2451	* @{ */
2452	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU64,(uint64_t *puDst, uint8_t bShift));
2453	typedef FNIEMAIMPLMEDIAPSHIFTU64 *PFNIEMAIMPLMEDIAPSHIFTU64;
2454	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU128,(PRTUINT128U puDst, uint8_t bShift));
2455	typedef FNIEMAIMPLMEDIAPSHIFTU128 *PFNIEMAIMPLMEDIAPSHIFTU128;
2456	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU256,(PRTUINT256U puDst, uint8_t bShift));
2457	typedef FNIEMAIMPLMEDIAPSHIFTU256 *PFNIEMAIMPLMEDIAPSHIFTU256;
2458	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psllw_imm_u64, iemAImpl_pslld_imm_u64, iemAImpl_psllq_imm_u64;
2459	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psrlw_imm_u64, iemAImpl_psrld_imm_u64, iemAImpl_psrlq_imm_u64;
2460	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psraw_imm_u64, iemAImpl_psrad_imm_u64;
2461	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psllw_imm_u128, iemAImpl_pslld_imm_u128, iemAImpl_psllq_imm_u128;
2462	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psrlw_imm_u128, iemAImpl_psrld_imm_u128, iemAImpl_psrlq_imm_u128;
2463	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psraw_imm_u128, iemAImpl_psrad_imm_u128;
2464	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_pslldq_imm_u128, iemAImpl_psrldq_imm_u128;
2465	/** @} */
2466
2467	/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
2468	* @{ */
2469	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(uint64_t pu64Dst, uint64_t const puSrc));
2470	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(uint64_t *pu64Dst, PCRTUINT128U puSrc));
2471	#ifndef IEM_WITHOUT_ASSEMBLY
2472	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
2473	#endif
2474	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256_fallback,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
2475	/** @} */
2476
2477	/** @name Media (SSE/MMX/AVX) operations: Variable Blend Packed Bytes/R32/R64.
2478	* @{ */
2479	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puMask));
2480	typedef FNIEMAIMPLBLENDU128 *PFNIEMAIMPLBLENDU128;
2481	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, PCRTUINT128U puMask));
2482	typedef FNIEMAIMPLAVXBLENDU128 *PFNIEMAIMPLAVXBLENDU128;
2483	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, PCRTUINT256U puMask));
2484	typedef FNIEMAIMPLAVXBLENDU256 *PFNIEMAIMPLAVXBLENDU256;
2485
2486	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128;
2487	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128_fallback;
2488	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128;
2489	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128_fallback;
2490	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256;
2491	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256_fallback;
2492
2493	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128;
2494	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128_fallback;
2495	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128;
2496	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128_fallback;
2497	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256;
2498	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256_fallback;
2499
2500	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128;
2501	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128_fallback;
2502	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128;
2503	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128_fallback;
2504	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256;
2505	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256_fallback;
2506	/** @} */
2507
2508
2509	/** @name Media (SSE/MMX/AVX) operation: Sort this later
2510	* @{ */
2511	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
2512	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
2513	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovshdup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
2514	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovshdup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
2515	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
2516	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
2517
2518	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2519	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2520	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2521	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2522	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2523
2524	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2525	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2526	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2527	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2528	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2529
2530	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2531	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2532	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
2533	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2534	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2535
2536	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2537	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2538	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2539	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2540	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2541
2542	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2543	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2544	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2545	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2546	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2547
2548	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2549	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2550	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2551	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2552	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2553
2554	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2555	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2556	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2557	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2558	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2559
2560	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2561	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2562	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2563	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2564	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2565
2566	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2567	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2568	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
2569	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2570	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2571
2572	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2573	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2574	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2575	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2576	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2577
2578	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2579	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2580	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2581	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2582	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2583
2584	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2585	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2586	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2587	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2588	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2589
2590	IEM_DECL_IMPL_DEF(void, iemAImpl_shufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2591	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2592	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2593	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2594	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2595
2596	IEM_DECL_IMPL_DEF(void, iemAImpl_shufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2597	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2598	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2599	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2600	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2601
2602	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
2603	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64_fallback,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
2604
2605	IEM_DECL_IMPL_DEF(void, iemAImpl_pinsrw_u64,(uint64_t *pu64Dst, uint16_t u16Src, uint8_t bEvil));
2606	IEM_DECL_IMPL_DEF(void, iemAImpl_pinsrw_u128,(PRTUINT128U puDst, uint16_t u16Src, uint8_t bEvil));
2607	IEM_DECL_IMPL_DEF(void, iemAImpl_vpinsrw_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint16_t u16Src, uint8_t bEvil));
2608	IEM_DECL_IMPL_DEF(void, iemAImpl_vpinsrw_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint16_t u16Src, uint8_t bEvil));
2609
2610	IEM_DECL_IMPL_DEF(void, iemAImpl_pextrw_u64,(uint16_t *pu16Dst, uint64_t u64Src, uint8_t bEvil));
2611	IEM_DECL_IMPL_DEF(void, iemAImpl_pextrw_u128,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
2612	IEM_DECL_IMPL_DEF(void, iemAImpl_vpextrw_u128,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
2613	IEM_DECL_IMPL_DEF(void, iemAImpl_vpextrw_u128_fallback,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
2614
2615	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2616	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2617	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2618	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
2619	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
2620
2621	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2622	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2623	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2624	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
2625	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
2626
2627
2628	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2629	typedef FNIEMAIMPLMEDIAOPTF2U128IMM8 *PFNIEMAIMPLMEDIAOPTF2U128IMM8;
2630	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2631	typedef FNIEMAIMPLMEDIAOPTF3U128IMM8 *PFNIEMAIMPLMEDIAOPTF3U128IMM8;
2632	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2633	typedef FNIEMAIMPLMEDIAOPTF3U256IMM8 *PFNIEMAIMPLMEDIAOPTF3U256IMM8;
2634
2635	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_palignr_u128, iemAImpl_palignr_u128_fallback;
2636	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pblendw_u128, iemAImpl_pblendw_u128_fallback;
2637	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendps_u128, iemAImpl_blendps_u128_fallback;
2638	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendpd_u128, iemAImpl_blendpd_u128_fallback;
2639
2640	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpalignr_u128, iemAImpl_vpalignr_u128_fallback;
2641	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendw_u128, iemAImpl_vpblendw_u128_fallback;
2642	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendps_u128, iemAImpl_vblendps_u128_fallback;
2643	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendpd_u128, iemAImpl_vblendpd_u128_fallback;
2644
2645	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpalignr_u256, iemAImpl_vpalignr_u256_fallback;
2646	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendw_u256, iemAImpl_vpblendw_u256_fallback;
2647	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendps_u256, iemAImpl_vblendps_u256_fallback;
2648	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendpd_u256, iemAImpl_vblendpd_u256_fallback;
2649
2650	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesimc_u128, iemAImpl_aesimc_u128_fallback;
2651	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenc_u128, iemAImpl_aesenc_u128_fallback;
2652	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenclast_u128, iemAImpl_aesenclast_u128_fallback;
2653	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdec_u128, iemAImpl_aesdec_u128_fallback;
2654	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdeclast_u128, iemAImpl_aesdeclast_u128_fallback;
2655
2656	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesimc_u128, iemAImpl_vaesimc_u128_fallback;
2657	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenc_u128, iemAImpl_vaesenc_u128_fallback;
2658	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenclast_u128, iemAImpl_vaesenclast_u128_fallback;
2659	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdec_u128, iemAImpl_vaesdec_u128_fallback;
2660	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdeclast_u128, iemAImpl_vaesdeclast_u128_fallback;
2661
2662	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_aeskeygenassist_u128, iemAImpl_aeskeygenassist_u128_fallback;
2663
2664	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vaeskeygenassist_u128, iemAImpl_vaeskeygenassist_u128_fallback;
2665
2666	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1nexte_u128, iemAImpl_sha1nexte_u128_fallback;
2667	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg1_u128, iemAImpl_sha1msg1_u128_fallback;
2668	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg2_u128, iemAImpl_sha1msg2_u128_fallback;
2669	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg1_u128, iemAImpl_sha256msg1_u128_fallback;
2670	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg2_u128, iemAImpl_sha256msg2_u128_fallback;
2671	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_sha1rnds4_u128, iemAImpl_sha1rnds4_u128_fallback;
2672	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
2673	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
2674
2675	typedef struct IEMPCMPISTRXSRC
2676	{
2677	RTUINT128U uSrc1;
2678	RTUINT128U uSrc2;
2679	} IEMPCMPISTRXSRC;
2680	typedef IEMPCMPISTRXSRC *PIEMPCMPISTRXSRC;
2681	typedef const IEMPCMPISTRXSRC *PCIEMPCMPISTRXSRC;
2682
2683	typedef struct IEMPCMPESTRXSRC
2684	{
2685	RTUINT128U uSrc1;
2686	RTUINT128U uSrc2;
2687	uint64_t u64Rax;
2688	uint64_t u64Rdx;
2689	} IEMPCMPESTRXSRC;
2690	typedef IEMPCMPESTRXSRC *PIEMPCMPESTRXSRC;
2691	typedef const IEMPCMPESTRXSRC *PCIEMPCMPESTRXSRC;
2692
2693	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPISTRIU128IMM8,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
2694	typedef FNIEMAIMPLPCMPISTRIU128IMM8 *PFNIEMAIMPLPCMPISTRIU128IMM8;
2695	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRIU128IMM8,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
2696	typedef FNIEMAIMPLPCMPESTRIU128IMM8 *PFNIEMAIMPLPCMPESTRIU128IMM8;
2697
2698	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPISTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
2699	typedef FNIEMAIMPLPCMPISTRMU128IMM8 *PFNIEMAIMPLPCMPISTRMU128IMM8;
2700	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
2701	typedef FNIEMAIMPLPCMPESTRMU128IMM8 *PFNIEMAIMPLPCMPESTRMU128IMM8;
2702
2703	FNIEMAIMPLPCMPISTRIU128IMM8 iemAImpl_pcmpistri_u128, iemAImpl_pcmpistri_u128_fallback;
2704	FNIEMAIMPLPCMPESTRIU128IMM8 iemAImpl_pcmpestri_u128, iemAImpl_pcmpestri_u128_fallback;
2705	FNIEMAIMPLPCMPISTRMU128IMM8 iemAImpl_pcmpistrm_u128, iemAImpl_pcmpistrm_u128_fallback;
2706	FNIEMAIMPLPCMPESTRMU128IMM8 iemAImpl_pcmpestrm_u128, iemAImpl_pcmpestrm_u128_fallback;
2707
2708	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pclmulqdq_u128, iemAImpl_pclmulqdq_u128_fallback;
2709	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpclmulqdq_u128, iemAImpl_vpclmulqdq_u128_fallback;
2710
2711	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_mpsadbw_u128, iemAImpl_mpsadbw_u128_fallback;
2712	/** @} */
2713
2714	/** @name Media Odds and Ends
2715	* @{ */
2716	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U8,(uint32_t *puDst, uint8_t uSrc));
2717	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U16,(uint32_t *puDst, uint16_t uSrc));
2718	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U32,(uint32_t *puDst, uint32_t uSrc));
2719	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U64,(uint32_t *puDst, uint64_t uSrc));
2720	FNIEMAIMPLCR32U8 iemAImpl_crc32_u8, iemAImpl_crc32_u8_fallback;
2721	FNIEMAIMPLCR32U16 iemAImpl_crc32_u16, iemAImpl_crc32_u16_fallback;
2722	FNIEMAIMPLCR32U32 iemAImpl_crc32_u32, iemAImpl_crc32_u32_fallback;
2723	FNIEMAIMPLCR32U64 iemAImpl_crc32_u64, iemAImpl_crc32_u64_fallback;
2724
2725	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL128,(PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint32_t *pEFlags));
2726	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL256,(PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint32_t *pEFlags));
2727	FNIEMAIMPLF2EFL128 iemAImpl_ptest_u128;
2728	FNIEMAIMPLF2EFL256 iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback;
2729
2730	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I32U64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int32_t pi32Dst, const uint64_t pu64Src)); / pu64Src is a double precision floating point. */
2731	typedef FNIEMAIMPLSSEF2I32U64 *PFNIEMAIMPLSSEF2I32U64;
2732	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I64U64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int64_t pi64Dst, const uint64_t pu64Src)); / pu64Src is a double precision floating point. */
2733	typedef FNIEMAIMPLSSEF2I64U64 *PFNIEMAIMPLSSEF2I64U64;
2734	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I32U32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int32_t pi32Dst, const uint32_t pu32Src)); / pu32Src is a single precision floating point. */
2735	typedef FNIEMAIMPLSSEF2I32U32 *PFNIEMAIMPLSSEF2I32U32;
2736	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I64U32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int64_t pi64Dst, const uint32_t pu32Src)); / pu32Src is a single precision floating point. */
2737	typedef FNIEMAIMPLSSEF2I64U32 *PFNIEMAIMPLSSEF2I64U32;
2738
2739	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvttsd2si_i32_r64;
2740	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvtsd2si_i32_r64;
2741
2742	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvttsd2si_i64_r64;
2743	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvtsd2si_i64_r64;
2744
2745	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvttss2si_i32_r32;
2746	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvtss2si_i32_r32;
2747
2748	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvttss2si_i64_r32;
2749	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvtss2si_i64_r32;
2750
2751	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R32I32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT32U pr32Dst, const int32_t pi32Src));
2752	typedef FNIEMAIMPLSSEF2R32I32 *PFNIEMAIMPLSSEF2R32I32;
2753	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R32I64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT32U pr32Dst, const int64_t pi64Src));
2754	typedef FNIEMAIMPLSSEF2R32I64 *PFNIEMAIMPLSSEF2R32I64;
2755
2756	FNIEMAIMPLSSEF2R32I32 iemAImpl_cvtsi2ss_r32_i32;
2757	FNIEMAIMPLSSEF2R32I64 iemAImpl_cvtsi2ss_r32_i64;
2758
2759	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R64I32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT64U pr64Dst, const int32_t pi32Src));
2760	typedef FNIEMAIMPLSSEF2R64I32 *PFNIEMAIMPLSSEF2R64I32;
2761	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R64I64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT64U pr64Dst, const int64_t pi64Src));
2762	typedef FNIEMAIMPLSSEF2R64I64 *PFNIEMAIMPLSSEF2R64I64;
2763
2764	FNIEMAIMPLSSEF2R64I32 iemAImpl_cvtsi2sd_r64_i32;
2765	FNIEMAIMPLSSEF2R64I64 iemAImpl_cvtsi2sd_r64_i64;
2766
2767
2768	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFLMXCSR128,(uint32_t pfMxcsr, uint32_t pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
2769	typedef FNIEMAIMPLF2EFLMXCSR128 *PFNIEMAIMPLF2EFLMXCSR128;
2770
2771	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_ucomiss_u128;
2772	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback;
2773
2774	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_ucomisd_u128;
2775	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback;
2776
2777	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_comiss_u128;
2778	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback;
2779
2780	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_comisd_u128;
2781	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback;
2782
2783
2784	typedef struct IEMMEDIAF2XMMSRC
2785	{
2786	X86XMMREG uSrc1;
2787	X86XMMREG uSrc2;
2788	} IEMMEDIAF2XMMSRC;
2789	typedef IEMMEDIAF2XMMSRC *PIEMMEDIAF2XMMSRC;
2790	typedef const IEMMEDIAF2XMMSRC *PCIEMMEDIAF2XMMSRC;
2791
2792	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRF2XMMIMM8,(uint32_t *pfMxcsr, PX86XMMREG puDst, PCIEMMEDIAF2XMMSRC puSrc, uint8_t bEvil));
2793	typedef FNIEMAIMPLMXCSRF2XMMIMM8 *PFNIEMAIMPLMXCSRF2XMMIMM8;
2794
2795	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpps_u128;
2796	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmppd_u128;
2797	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpss_u128;
2798	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpsd_u128;
2799	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundss_u128;
2800	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundsd_u128;
2801
2802	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundps_u128, iemAImpl_roundps_u128_fallback;
2803	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundpd_u128, iemAImpl_roundpd_u128_fallback;
2804
2805	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_dpps_u128, iemAImpl_dpps_u128_fallback;
2806	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_dppd_u128, iemAImpl_dppd_u128_fallback;
2807
2808	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU64U128,(uint32_t pfMxcsr, uint64_t pu64Dst, PCX86XMMREG pSrc));
2809	typedef FNIEMAIMPLMXCSRU64U128 *PFNIEMAIMPLMXCSRU64U128;
2810
2811	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvtpd2pi_u128;
2812	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvttpd2pi_u128;
2813
2814	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU128U64,(uint32_t *pfMxcsr, PX86XMMREG pDst, uint64_t u64Src));
2815	typedef FNIEMAIMPLMXCSRU128U64 *PFNIEMAIMPLMXCSRU128U64;
2816
2817	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2ps_u128;
2818	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2pd_u128;
2819
2820	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU64U64,(uint32_t pfMxcsr, uint64_t pu64Dst, uint64_t u64Src));
2821	typedef FNIEMAIMPLMXCSRU64U64 *PFNIEMAIMPLMXCSRU64U64;
2822
2823	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvtps2pi_u128;
2824	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvttps2pi_u128;
2825
2826	/** @} */
2827
2828
2829	/** @name Function tables.
2830	* @{
2831	*/
2832
2833	/**
2834	* Function table for a binary operator providing implementation based on
2835	* operand size.
2836	*/
2837	typedef struct IEMOPBINSIZES
2838	{
2839	PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
2840	PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
2841	PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
2842	PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
2843	} IEMOPBINSIZES;
2844	/** Pointer to a binary operator function table. */
2845	typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
2846
2847
2848	/**
2849	* Function table for a unary operator providing implementation based on
2850	* operand size.
2851	*/
2852	typedef struct IEMOPUNARYSIZES
2853	{
2854	PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
2855	PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
2856	PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
2857	PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
2858	} IEMOPUNARYSIZES;
2859	/** Pointer to a unary operator function table. */
2860	typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
2861
2862
2863	/**
2864	* Function table for a shift operator providing implementation based on
2865	* operand size.
2866	*/
2867	typedef struct IEMOPSHIFTSIZES
2868	{
2869	PFNIEMAIMPLSHIFTU8 pfnNormalU8;
2870	PFNIEMAIMPLSHIFTU16 pfnNormalU16;
2871	PFNIEMAIMPLSHIFTU32 pfnNormalU32;
2872	PFNIEMAIMPLSHIFTU64 pfnNormalU64;
2873	} IEMOPSHIFTSIZES;
2874	/** Pointer to a shift operator function table. */
2875	typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
2876
2877
2878	/**
2879	* Function table for a multiplication or division operation.
2880	*/
2881	typedef struct IEMOPMULDIVSIZES
2882	{
2883	PFNIEMAIMPLMULDIVU8 pfnU8;
2884	PFNIEMAIMPLMULDIVU16 pfnU16;
2885	PFNIEMAIMPLMULDIVU32 pfnU32;
2886	PFNIEMAIMPLMULDIVU64 pfnU64;
2887	} IEMOPMULDIVSIZES;
2888	/** Pointer to a multiplication or division operation function table. */
2889	typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
2890
2891
2892	/**
2893	* Function table for a double precision shift operator providing implementation
2894	* based on operand size.
2895	*/
2896	typedef struct IEMOPSHIFTDBLSIZES
2897	{
2898	PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
2899	PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
2900	PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
2901	} IEMOPSHIFTDBLSIZES;
2902	/** Pointer to a double precision shift function table. */
2903	typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
2904
2905
2906	/**
2907	* Function table for media instruction taking two full sized media source
2908	* registers and one full sized destination register (AVX).
2909	*/
2910	typedef struct IEMOPMEDIAF3
2911	{
2912	PFNIEMAIMPLMEDIAF3U128 pfnU128;
2913	PFNIEMAIMPLMEDIAF3U256 pfnU256;
2914	} IEMOPMEDIAF3;
2915	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
2916	typedef IEMOPMEDIAF3 const *PCIEMOPMEDIAF3;
2917
2918	/** @def IEMOPMEDIAF3_INIT_VARS_EX
2919	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2920	* given functions as initializers. For use in AVX functions where a pair of
2921	* functions are only used once and the function table need not be public. */
2922	#ifndef TST_IEM_CHECK_MC
2923	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2924	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2925	static IEMOPMEDIAF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2926	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2927	# else
2928	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2929	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2930	# endif
2931	#else
2932	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2933	#endif
2934	/** @def IEMOPMEDIAF3_INIT_VARS
2935	* Generate AVX function tables for the @a a_InstrNm instruction.
2936	* @sa IEMOPMEDIAF3_INIT_VARS_EX */
2937	#define IEMOPMEDIAF3_INIT_VARS(a_InstrNm) \
2938	IEMOPMEDIAF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2939	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2940
2941	/**
2942	* Function table for media instruction taking two full sized media source
2943	* registers and one full sized destination register, but no additional state
2944	* (AVX).
2945	*/
2946	typedef struct IEMOPMEDIAOPTF3
2947	{
2948	PFNIEMAIMPLMEDIAOPTF3U128 pfnU128;
2949	PFNIEMAIMPLMEDIAOPTF3U256 pfnU256;
2950	} IEMOPMEDIAOPTF3;
2951	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
2952	typedef IEMOPMEDIAOPTF3 const *PCIEMOPMEDIAOPTF3;
2953
2954	/** @def IEMOPMEDIAOPTF3_INIT_VARS_EX
2955	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2956	* given functions as initializers. For use in AVX functions where a pair of
2957	* functions are only used once and the function table need not be public. */
2958	#ifndef TST_IEM_CHECK_MC
2959	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2960	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2961	static IEMOPMEDIAOPTF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2962	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2963	# else
2964	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2965	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2966	# endif
2967	#else
2968	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2969	#endif
2970	/** @def IEMOPMEDIAOPTF3_INIT_VARS
2971	* Generate AVX function tables for the @a a_InstrNm instruction.
2972	* @sa IEMOPMEDIAOPTF3_INIT_VARS_EX */
2973	#define IEMOPMEDIAOPTF3_INIT_VARS(a_InstrNm) \
2974	IEMOPMEDIAOPTF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2975	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2976
2977	/**
2978	* Function table for media instruction taking one full sized media source
2979	* registers and one full sized destination register, but no additional state
2980	* (AVX).
2981	*/
2982	typedef struct IEMOPMEDIAOPTF2
2983	{
2984	PFNIEMAIMPLMEDIAOPTF2U128 pfnU128;
2985	PFNIEMAIMPLMEDIAOPTF2U256 pfnU256;
2986	} IEMOPMEDIAOPTF2;
2987	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
2988	typedef IEMOPMEDIAOPTF2 const *PCIEMOPMEDIAOPTF2;
2989
2990	/** @def IEMOPMEDIAOPTF2_INIT_VARS_EX
2991	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2992	* given functions as initializers. For use in AVX functions where a pair of
2993	* functions are only used once and the function table need not be public. */
2994	#ifndef TST_IEM_CHECK_MC
2995	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2996	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2997	static IEMOPMEDIAOPTF2 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2998	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2999	# else
3000	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3001	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3002	# endif
3003	#else
3004	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3005	#endif
3006	/** @def IEMOPMEDIAOPTF2_INIT_VARS
3007	* Generate AVX function tables for the @a a_InstrNm instruction.
3008	* @sa IEMOPMEDIAOPTF2_INIT_VARS_EX */
3009	#define IEMOPMEDIAOPTF2_INIT_VARS(a_InstrNm) \
3010	IEMOPMEDIAOPTF2_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3011	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3012
3013	/**
3014	* Function table for media instruction taking two full sized media source
3015	* registers and one full sized destination register and an 8-bit immediate, but no additional state
3016	* (AVX).
3017	*/
3018	typedef struct IEMOPMEDIAOPTF3IMM8
3019	{
3020	PFNIEMAIMPLMEDIAOPTF3U128IMM8 pfnU128;
3021	PFNIEMAIMPLMEDIAOPTF3U256IMM8 pfnU256;
3022	} IEMOPMEDIAOPTF3IMM8;
3023	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
3024	typedef IEMOPMEDIAOPTF3IMM8 const *PCIEMOPMEDIAOPTF3IMM8;
3025
3026	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX
3027	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3028	* given functions as initializers. For use in AVX functions where a pair of
3029	* functions are only used once and the function table need not be public. */
3030	#ifndef TST_IEM_CHECK_MC
3031	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3032	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3033	static IEMOPMEDIAOPTF3IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3034	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3035	# else
3036	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3037	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3038	# endif
3039	#else
3040	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3041	#endif
3042	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS
3043	* Generate AVX function tables for the @a a_InstrNm instruction.
3044	* @sa IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX */
3045	#define IEMOPMEDIAOPTF3IMM8_INIT_VARS(a_InstrNm) \
3046	IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3047	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3048	/** @} */
3049
3050
3051	/**
3052	* Function table for blend type instruction taking three full sized media source
3053	* registers and one full sized destination register, but no additional state
3054	* (AVX).
3055	*/
3056	typedef struct IEMOPBLENDOP
3057	{
3058	PFNIEMAIMPLAVXBLENDU128 pfnU128;
3059	PFNIEMAIMPLAVXBLENDU256 pfnU256;
3060	} IEMOPBLENDOP;
3061	/** Pointer to a media operation function table for 4 full sized ops (AVX). */
3062	typedef IEMOPBLENDOP const *PCIEMOPBLENDOP;
3063
3064	/** @def IEMOPBLENDOP_INIT_VARS_EX
3065	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3066	* given functions as initializers. For use in AVX functions where a pair of
3067	* functions are only used once and the function table need not be public. */
3068	#ifndef TST_IEM_CHECK_MC
3069	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3070	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3071	static IEMOPBLENDOP const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3072	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3073	# else
3074	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3075	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3076	# endif
3077	#else
3078	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3079	#endif
3080	/** @def IEMOPBLENDOP_INIT_VARS
3081	* Generate AVX function tables for the @a a_InstrNm instruction.
3082	* @sa IEMOPBLENDOP_INIT_VARS_EX */
3083	#define IEMOPBLENDOP_INIT_VARS(a_InstrNm) \
3084	IEMOPBLENDOP_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3085	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3086
3087
3088	/** @name SSE/AVX single/double precision floating point operations.
3089	* @{ */
3090	/**
3091	* A SSE result.
3092	*/
3093	typedef struct IEMSSERESULT
3094	{
3095	/** The output value. */
3096	X86XMMREG uResult;
3097	/** The output status. */
3098	uint32_t MXCSR;
3099	} IEMSSERESULT;
3100	AssertCompileMemberOffset(IEMSSERESULT, MXCSR, 128 / 8);
3101	/** Pointer to a SSE result. */
3102	typedef IEMSSERESULT *PIEMSSERESULT;
3103	/** Pointer to a const SSE result. */
3104	typedef IEMSSERESULT const *PCIEMSSERESULT;
3105
3106
3107	/**
3108	* A AVX128 result.
3109	*/
3110	typedef struct IEMAVX128RESULT
3111	{
3112	/** The output value. */
3113	X86XMMREG uResult;
3114	/** The output status. */
3115	uint32_t MXCSR;
3116	} IEMAVX128RESULT;
3117	AssertCompileMemberOffset(IEMAVX128RESULT, MXCSR, 128 / 8);
3118	/** Pointer to a AVX128 result. */
3119	typedef IEMAVX128RESULT *PIEMAVX128RESULT;
3120	/** Pointer to a const AVX128 result. */
3121	typedef IEMAVX128RESULT const *PCIEMAVX128RESULT;
3122
3123
3124	/**
3125	* A AVX256 result.
3126	*/
3127	typedef struct IEMAVX256RESULT
3128	{
3129	/** The output value. */
3130	X86YMMREG uResult;
3131	/** The output status. */
3132	uint32_t MXCSR;
3133	} IEMAVX256RESULT;
3134	AssertCompileMemberOffset(IEMAVX256RESULT, MXCSR, 256 / 8);
3135	/** Pointer to a AVX256 result. */
3136	typedef IEMAVX256RESULT *PIEMAVX256RESULT;
3137	/** Pointer to a const AVX256 result. */
3138	typedef IEMAVX256RESULT const *PCIEMAVX256RESULT;
3139
3140
3141	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
3142	typedef FNIEMAIMPLFPSSEF2U128 *PFNIEMAIMPLFPSSEF2U128;
3143	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128R32,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
3144	typedef FNIEMAIMPLFPSSEF2U128R32 *PFNIEMAIMPLFPSSEF2U128R32;
3145	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128R64,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
3146	typedef FNIEMAIMPLFPSSEF2U128R64 *PFNIEMAIMPLFPSSEF2U128R64;
3147
3148	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
3149	typedef FNIEMAIMPLFPAVXF3U128 *PFNIEMAIMPLFPAVXF3U128;
3150	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128R32,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
3151	typedef FNIEMAIMPLFPAVXF3U128R32 *PFNIEMAIMPLFPAVXF3U128R32;
3152	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128R64,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
3153	typedef FNIEMAIMPLFPAVXF3U128R64 *PFNIEMAIMPLFPAVXF3U128R64;
3154
3155	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U256,(PX86XSAVEAREA pExtState, PIEMAVX256RESULT pResult, PCX86YMMREG puSrc1, PCX86YMMREG puSrc2));
3156	typedef FNIEMAIMPLFPAVXF3U256 *PFNIEMAIMPLFPAVXF3U256;
3157
3158	FNIEMAIMPLFPSSEF2U128 iemAImpl_addps_u128;
3159	FNIEMAIMPLFPSSEF2U128 iemAImpl_addpd_u128;
3160	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulps_u128;
3161	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulpd_u128;
3162	FNIEMAIMPLFPSSEF2U128 iemAImpl_subps_u128;
3163	FNIEMAIMPLFPSSEF2U128 iemAImpl_subpd_u128;
3164	FNIEMAIMPLFPSSEF2U128 iemAImpl_minps_u128;
3165	FNIEMAIMPLFPSSEF2U128 iemAImpl_minpd_u128;
3166	FNIEMAIMPLFPSSEF2U128 iemAImpl_divps_u128;
3167	FNIEMAIMPLFPSSEF2U128 iemAImpl_divpd_u128;
3168	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxps_u128;
3169	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxpd_u128;
3170	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddps_u128;
3171	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddpd_u128;
3172	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubps_u128;
3173	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubpd_u128;
3174	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtps_u128;
3175	FNIEMAIMPLFPSSEF2U128 iemAImpl_rsqrtps_u128;
3176	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtpd_u128;
3177	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubps_u128;
3178	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubpd_u128;
3179	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2ps_u128;
3180	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2pd_u128;
3181
3182	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2ps_u128;
3183	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2dq_u128;
3184	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttps2dq_u128;
3185	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttpd2dq_u128;
3186	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2pd_u128;
3187	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2dq_u128;
3188
3189	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_addss_u128_r32;
3190	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_addsd_u128_r64;
3191	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_mulss_u128_r32;
3192	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_mulsd_u128_r64;
3193	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_subss_u128_r32;
3194	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_subsd_u128_r64;
3195	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_minss_u128_r32;
3196	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_minsd_u128_r64;
3197	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_divss_u128_r32;
3198	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_divsd_u128_r64;
3199	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_maxss_u128_r32;
3200	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_maxsd_u128_r64;
3201	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_cvtss2sd_u128_r32;
3202	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_cvtsd2ss_u128_r64;
3203	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_sqrtss_u128_r32;
3204	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_sqrtsd_u128_r64;
3205	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_rsqrtss_u128_r32;
3206
3207	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddps_u128, iemAImpl_vaddps_u128_fallback;
3208	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddpd_u128, iemAImpl_vaddpd_u128_fallback;
3209	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulps_u128, iemAImpl_vmulps_u128_fallback;
3210	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulpd_u128, iemAImpl_vmulpd_u128_fallback;
3211	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubps_u128, iemAImpl_vsubps_u128_fallback;
3212	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubpd_u128, iemAImpl_vsubpd_u128_fallback;
3213	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminps_u128, iemAImpl_vminps_u128_fallback;
3214	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminpd_u128, iemAImpl_vminpd_u128_fallback;
3215	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivps_u128, iemAImpl_vdivps_u128_fallback;
3216	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivpd_u128, iemAImpl_vdivpd_u128_fallback;
3217	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxps_u128, iemAImpl_vmaxps_u128_fallback;
3218	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxpd_u128, iemAImpl_vmaxpd_u128_fallback;
3219	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddps_u128, iemAImpl_vhaddps_u128_fallback;
3220	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddpd_u128, iemAImpl_vhaddpd_u128_fallback;
3221	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubps_u128, iemAImpl_vhsubps_u128_fallback;
3222	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubpd_u128, iemAImpl_vhsubpd_u128_fallback;
3223	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtps_u128, iemAImpl_vsqrtps_u128_fallback;
3224	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtpd_u128, iemAImpl_vsqrtpd_u128_fallback;
3225	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubps_u128, iemAImpl_vaddsubps_u128_fallback;
3226	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubpd_u128, iemAImpl_vaddsubpd_u128_fallback;
3227	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtpd2ps_u128, iemAImpl_vcvtpd2ps_u128_fallback;
3228	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtps2pd_u128, iemAImpl_vcvtps2pd_u128_fallback;
3229
3230	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vaddss_u128_r32, iemAImpl_vaddss_u128_r32_fallback;
3231	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vaddsd_u128_r64, iemAImpl_vaddsd_u128_r64_fallback;
3232	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmulss_u128_r32, iemAImpl_vmulss_u128_r32_fallback;
3233	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmulsd_u128_r64, iemAImpl_vmulsd_u128_r64_fallback;
3234	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsubss_u128_r32, iemAImpl_vsubss_u128_r32_fallback;
3235	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsubsd_u128_r64, iemAImpl_vsubsd_u128_r64_fallback;
3236	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vminss_u128_r32, iemAImpl_vminss_u128_r32_fallback;
3237	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vminsd_u128_r64, iemAImpl_vminsd_u128_r64_fallback;
3238	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vdivss_u128_r32, iemAImpl_vdivss_u128_r32_fallback;
3239	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vdivsd_u128_r64, iemAImpl_vdivsd_u128_r64_fallback;
3240	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmaxss_u128_r32, iemAImpl_vmaxss_u128_r32_fallback;
3241	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmaxsd_u128_r64, iemAImpl_vmaxsd_u128_r64_fallback;
3242	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsqrtss_u128_r32, iemAImpl_vsqrtss_u128_r32_fallback;
3243	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsqrtsd_u128_r64, iemAImpl_vsqrtsd_u128_r64_fallback;
3244
3245	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddps_u256, iemAImpl_vaddps_u256_fallback;
3246	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddpd_u256, iemAImpl_vaddpd_u256_fallback;
3247	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulps_u256, iemAImpl_vmulps_u256_fallback;
3248	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulpd_u256, iemAImpl_vmulpd_u256_fallback;
3249	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubps_u256, iemAImpl_vsubps_u256_fallback;
3250	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubpd_u256, iemAImpl_vsubpd_u256_fallback;
3251	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminps_u256, iemAImpl_vminps_u256_fallback;
3252	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminpd_u256, iemAImpl_vminpd_u256_fallback;
3253	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivps_u256, iemAImpl_vdivps_u256_fallback;
3254	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivpd_u256, iemAImpl_vdivpd_u256_fallback;
3255	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxps_u256, iemAImpl_vmaxps_u256_fallback;
3256	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxpd_u256, iemAImpl_vmaxpd_u256_fallback;
3257	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddps_u256, iemAImpl_vhaddps_u256_fallback;
3258	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddpd_u256, iemAImpl_vhaddpd_u256_fallback;
3259	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubps_u256, iemAImpl_vhsubps_u256_fallback;
3260	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubpd_u256, iemAImpl_vhsubpd_u256_fallback;
3261	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubps_u256, iemAImpl_vhaddsubps_u256_fallback;
3262	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubpd_u256, iemAImpl_vhaddsubpd_u256_fallback;
3263	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtpd2ps_u256, iemAImpl_vcvtpd2ps_u256_fallback;
3264	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtps2pd_u256, iemAImpl_vcvtps2pd_u256_fallback;
3265	/** @} */
3266
3267	/** @name C instruction implementations for anything slightly complicated.
3268	* @{ */
3269
3270	/**
3271	* For typedef'ing or declaring a C instruction implementation function taking
3272	* no extra arguments.
3273	*
3274	* @param a_Name The name of the type.
3275	*/
3276	# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
3277	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
3278	/**
3279	* For defining a C instruction implementation function taking no extra
3280	* arguments.
3281	*
3282	* @param a_Name The name of the function
3283	*/
3284	# define IEM_CIMPL_DEF_0(a_Name) \
3285	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
3286	/**
3287	* Prototype version of IEM_CIMPL_DEF_0.
3288	*/
3289	# define IEM_CIMPL_PROTO_0(a_Name) \
3290	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
3291	/**
3292	* For calling a C instruction implementation function taking no extra
3293	* arguments.
3294	*
3295	* This special call macro adds default arguments to the call and allow us to
3296	* change these later.
3297	*
3298	* @param a_fn The name of the function.
3299	*/
3300	# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
3301
3302	/**
3303	* For typedef'ing or declaring a C instruction implementation function taking
3304	* one extra argument.
3305	*
3306	* @param a_Name The name of the type.
3307	* @param a_Type0 The argument type.
3308	* @param a_Arg0 The argument name.
3309	*/
3310	# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
3311	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
3312	/**
3313	* For defining a C instruction implementation function taking one extra
3314	* argument.
3315	*
3316	* @param a_Name The name of the function
3317	* @param a_Type0 The argument type.
3318	* @param a_Arg0 The argument name.
3319	*/
3320	# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
3321	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
3322	/**
3323	* Prototype version of IEM_CIMPL_DEF_1.
3324	*/
3325	# define IEM_CIMPL_PROTO_1(a_Name, a_Type0, a_Arg0) \
3326	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
3327	/**
3328	* For calling a C instruction implementation function taking one extra
3329	* argument.
3330	*
3331	* This special call macro adds default arguments to the call and allow us to
3332	* change these later.
3333	*
3334	* @param a_fn The name of the function.
3335	* @param a0 The name of the 1st argument.
3336	*/
3337	# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
3338
3339	/**
3340	* For typedef'ing or declaring a C instruction implementation function taking
3341	* two extra arguments.
3342	*
3343	* @param a_Name The name of the type.
3344	* @param a_Type0 The type of the 1st argument
3345	* @param a_Arg0 The name of the 1st argument.
3346	* @param a_Type1 The type of the 2nd argument.
3347	* @param a_Arg1 The name of the 2nd argument.
3348	*/
3349	# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
3350	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
3351	/**
3352	* For defining a C instruction implementation function taking two extra
3353	* arguments.
3354	*
3355	* @param a_Name The name of the function.
3356	* @param a_Type0 The type of the 1st argument
3357	* @param a_Arg0 The name of the 1st argument.
3358	* @param a_Type1 The type of the 2nd argument.
3359	* @param a_Arg1 The name of the 2nd argument.
3360	*/
3361	# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
3362	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
3363	/**
3364	* Prototype version of IEM_CIMPL_DEF_2.
3365	*/
3366	# define IEM_CIMPL_PROTO_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
3367	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
3368	/**
3369	* For calling a C instruction implementation function taking two extra
3370	* arguments.
3371	*
3372	* This special call macro adds default arguments to the call and allow us to
3373	* change these later.
3374	*
3375	* @param a_fn The name of the function.
3376	* @param a0 The name of the 1st argument.
3377	* @param a1 The name of the 2nd argument.
3378	*/
3379	# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
3380
3381	/**
3382	* For typedef'ing or declaring a C instruction implementation function taking
3383	* three extra arguments.
3384	*
3385	* @param a_Name The name of the type.
3386	* @param a_Type0 The type of the 1st argument
3387	* @param a_Arg0 The name of the 1st argument.
3388	* @param a_Type1 The type of the 2nd argument.
3389	* @param a_Arg1 The name of the 2nd argument.
3390	* @param a_Type2 The type of the 3rd argument.
3391	* @param a_Arg2 The name of the 3rd argument.
3392	*/
3393	# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
3394	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
3395	/**
3396	* For defining a C instruction implementation function taking three extra
3397	* arguments.
3398	*
3399	* @param a_Name The name of the function.
3400	* @param a_Type0 The type of the 1st argument
3401	* @param a_Arg0 The name of the 1st argument.
3402	* @param a_Type1 The type of the 2nd argument.
3403	* @param a_Arg1 The name of the 2nd argument.
3404	* @param a_Type2 The type of the 3rd argument.
3405	* @param a_Arg2 The name of the 3rd argument.
3406	*/
3407	# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
3408	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
3409	/**
3410	* Prototype version of IEM_CIMPL_DEF_3.
3411	*/
3412	# define IEM_CIMPL_PROTO_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
3413	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
3414	/**
3415	* For calling a C instruction implementation function taking three extra
3416	* arguments.
3417	*
3418	* This special call macro adds default arguments to the call and allow us to
3419	* change these later.
3420	*
3421	* @param a_fn The name of the function.
3422	* @param a0 The name of the 1st argument.
3423	* @param a1 The name of the 2nd argument.
3424	* @param a2 The name of the 3rd argument.
3425	*/
3426	# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
3427
3428
3429	/**
3430	* For typedef'ing or declaring a C instruction implementation function taking
3431	* four extra arguments.
3432	*
3433	* @param a_Name The name of the type.
3434	* @param a_Type0 The type of the 1st argument
3435	* @param a_Arg0 The name of the 1st argument.
3436	* @param a_Type1 The type of the 2nd argument.
3437	* @param a_Arg1 The name of the 2nd argument.
3438	* @param a_Type2 The type of the 3rd argument.
3439	* @param a_Arg2 The name of the 3rd argument.
3440	* @param a_Type3 The type of the 4th argument.
3441	* @param a_Arg3 The name of the 4th argument.
3442	*/
3443	# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
3444	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
3445	/**
3446	* For defining a C instruction implementation function taking four extra
3447	* arguments.
3448	*
3449	* @param a_Name The name of the function.
3450	* @param a_Type0 The type of the 1st argument
3451	* @param a_Arg0 The name of the 1st argument.
3452	* @param a_Type1 The type of the 2nd argument.
3453	* @param a_Arg1 The name of the 2nd argument.
3454	* @param a_Type2 The type of the 3rd argument.
3455	* @param a_Arg2 The name of the 3rd argument.
3456	* @param a_Type3 The type of the 4th argument.
3457	* @param a_Arg3 The name of the 4th argument.
3458	*/
3459	# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
3460	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3461	a_Type2 a_Arg2, a_Type3 a_Arg3))
3462	/**
3463	* Prototype version of IEM_CIMPL_DEF_4.
3464	*/
3465	# define IEM_CIMPL_PROTO_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
3466	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3467	a_Type2 a_Arg2, a_Type3 a_Arg3))
3468	/**
3469	* For calling a C instruction implementation function taking four extra
3470	* arguments.
3471	*
3472	* This special call macro adds default arguments to the call and allow us to
3473	* change these later.
3474	*
3475	* @param a_fn The name of the function.
3476	* @param a0 The name of the 1st argument.
3477	* @param a1 The name of the 2nd argument.
3478	* @param a2 The name of the 3rd argument.
3479	* @param a3 The name of the 4th argument.
3480	*/
3481	# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
3482
3483
3484	/**
3485	* For typedef'ing or declaring a C instruction implementation function taking
3486	* five extra arguments.
3487	*
3488	* @param a_Name The name of the type.
3489	* @param a_Type0 The type of the 1st argument
3490	* @param a_Arg0 The name of the 1st argument.
3491	* @param a_Type1 The type of the 2nd argument.
3492	* @param a_Arg1 The name of the 2nd argument.
3493	* @param a_Type2 The type of the 3rd argument.
3494	* @param a_Arg2 The name of the 3rd argument.
3495	* @param a_Type3 The type of the 4th argument.
3496	* @param a_Arg3 The name of the 4th argument.
3497	* @param a_Type4 The type of the 5th argument.
3498	* @param a_Arg4 The name of the 5th argument.
3499	*/
3500	# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
3501	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, \
3502	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
3503	a_Type3 a_Arg3, a_Type4 a_Arg4))
3504	/**
3505	* For defining a C instruction implementation function taking five extra
3506	* arguments.
3507	*
3508	* @param a_Name The name of the function.
3509	* @param a_Type0 The type of the 1st argument
3510	* @param a_Arg0 The name of the 1st argument.
3511	* @param a_Type1 The type of the 2nd argument.
3512	* @param a_Arg1 The name of the 2nd argument.
3513	* @param a_Type2 The type of the 3rd argument.
3514	* @param a_Arg2 The name of the 3rd argument.
3515	* @param a_Type3 The type of the 4th argument.
3516	* @param a_Arg3 The name of the 4th argument.
3517	* @param a_Type4 The type of the 5th argument.
3518	* @param a_Arg4 The name of the 5th argument.
3519	*/
3520	# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
3521	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3522	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
3523	/**
3524	* Prototype version of IEM_CIMPL_DEF_5.
3525	*/
3526	# define IEM_CIMPL_PROTO_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
3527	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3528	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
3529	/**
3530	* For calling a C instruction implementation function taking five extra
3531	* arguments.
3532	*
3533	* This special call macro adds default arguments to the call and allow us to
3534	* change these later.
3535	*
3536	* @param a_fn The name of the function.
3537	* @param a0 The name of the 1st argument.
3538	* @param a1 The name of the 2nd argument.
3539	* @param a2 The name of the 3rd argument.
3540	* @param a3 The name of the 4th argument.
3541	* @param a4 The name of the 5th argument.
3542	*/
3543	# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
3544
3545	/** @} */
3546
3547
3548	/** @name Opcode Decoder Function Types.
3549	* @{ */
3550
3551	/** @typedef PFNIEMOP
3552	* Pointer to an opcode decoder function.
3553	*/
3554
3555	/** @def FNIEMOP_DEF
3556	* Define an opcode decoder function.
3557	*
3558	* We're using macors for this so that adding and removing parameters as well as
3559	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL
3560	*
3561	* @param a_Name The function name.
3562	*/
3563
3564	/** @typedef PFNIEMOPRM
3565	* Pointer to an opcode decoder function with RM byte.
3566	*/
3567
3568	/** @def FNIEMOPRM_DEF
3569	* Define an opcode decoder function with RM byte.
3570	*
3571	* We're using macors for this so that adding and removing parameters as well as
3572	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL_1
3573	*
3574	* @param a_Name The function name.
3575	*/
3576
3577	#if defined(__GNUC__) && defined(RT_ARCH_X86)
3578	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOP)(PVMCPUCC pVCpu);
3579	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3580	# define FNIEMOP_DEF(a_Name) \
3581	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu)
3582	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3583	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
3584	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3585	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
3586
3587	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
3588	typedef VBOXSTRICTRC (__fastcall * PFNIEMOP)(PVMCPUCC pVCpu);
3589	typedef VBOXSTRICTRC (__fastcall * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3590	# define FNIEMOP_DEF(a_Name) \
3591	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
3592	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3593	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
3594	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3595	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
3596
3597	#elif defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
3598	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
3599	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3600	# define FNIEMOP_DEF(a_Name) \
3601	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu)
3602	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3603	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
3604	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3605	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
3606
3607	#else
3608	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
3609	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3610	# define FNIEMOP_DEF(a_Name) \
3611	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
3612	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3613	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
3614	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3615	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
3616
3617	#endif
3618	#define FNIEMOPRM_DEF(a_Name) FNIEMOP_DEF_1(a_Name, uint8_t, bRm)
3619
3620	/**
3621	* Call an opcode decoder function.
3622	*
3623	* We're using macors for this so that adding and removing parameters can be
3624	* done as we please. See FNIEMOP_DEF.
3625	*/
3626	#define FNIEMOP_CALL(a_pfn) (a_pfn)(pVCpu)
3627
3628	/**
3629	* Call a common opcode decoder function taking one extra argument.
3630	*
3631	* We're using macors for this so that adding and removing parameters can be
3632	* done as we please. See FNIEMOP_DEF_1.
3633	*/
3634	#define FNIEMOP_CALL_1(a_pfn, a0) (a_pfn)(pVCpu, a0)
3635
3636	/**
3637	* Call a common opcode decoder function taking one extra argument.
3638	*
3639	* We're using macors for this so that adding and removing parameters can be
3640	* done as we please. See FNIEMOP_DEF_1.
3641	*/
3642	#define FNIEMOP_CALL_2(a_pfn, a0, a1) (a_pfn)(pVCpu, a0, a1)
3643	/** @} */
3644
3645
3646	/** @name Misc Helpers
3647	* @{ */
3648
3649	/** Used to shut up GCC warnings about variables that 'may be used uninitialized'
3650	* due to GCC lacking knowledge about the value range of a switch. */
3651	#if RT_CPLUSPLUS_PREREQ(202000)
3652	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: [[unlikely]] AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
3653	#else
3654	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
3655	#endif
3656
3657	/** Variant of IEM_NOT_REACHED_DEFAULT_CASE_RET that returns a custom value. */
3658	#if RT_CPLUSPLUS_PREREQ(202000)
3659	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: [[unlikely]] AssertFailedReturn(a_RetValue)
3660	#else
3661	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: AssertFailedReturn(a_RetValue)
3662	#endif
3663
3664	/**
3665	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
3666	* occation.
3667	*/
3668	#ifdef LOG_ENABLED
3669	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
3670	do { \
3671	/Log/ LogAlways(("%s: returning IEM_RETURN_ASPECT_NOT_IMPLEMENTED (line %d)\n", __FUNCTION__, __LINE__)); \
3672	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
3673	} while (0)
3674	#else
3675	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
3676	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
3677	#endif
3678
3679	/**
3680	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
3681	* occation using the supplied logger statement.
3682	*
3683	* @param a_LoggerArgs What to log on failure.
3684	*/
3685	#ifdef LOG_ENABLED
3686	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
3687	do { \
3688	LogAlways((LOG_FN_FMT ": ", __PRETTY_FUNCTION__)); LogAlways(a_LoggerArgs); \
3689	/LogFunc(a_LoggerArgs);/ \
3690	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
3691	} while (0)
3692	#else
3693	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
3694	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
3695	#endif
3696
3697	/**
3698	* Gets the CPU mode (from fExec) as a IEMMODE value.
3699	*
3700	* @returns IEMMODE
3701	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3702	*/
3703	#define IEM_GET_CPU_MODE(a_pVCpu) ((a_pVCpu)->iem.s.fExec & IEM_F_MODE_CPUMODE_MASK)
3704
3705	/**
3706	* Check if we're currently executing in real or virtual 8086 mode.
3707	*
3708	* @returns @c true if it is, @c false if not.
3709	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3710	*/
3711	#define IEM_IS_REAL_OR_V86_MODE(a_pVCpu) (( ((a_pVCpu)->iem.s.fExec ^ IEM_F_MODE_X86_PROT_MASK) \
3712	& (IEM_F_MODE_X86_V86_MASK \| IEM_F_MODE_X86_PROT_MASK)) != 0)
3713
3714	/**
3715	* Check if we're currently executing in virtual 8086 mode.
3716	*
3717	* @returns @c true if it is, @c false if not.
3718	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3719	*/
3720	#define IEM_IS_V86_MODE(a_pVCpu) (((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_V86_MASK) != 0)
3721
3722	/**
3723	* Check if we're currently executing in long mode.
3724	*
3725	* @returns @c true if it is, @c false if not.
3726	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3727	*/
3728	#define IEM_IS_LONG_MODE(a_pVCpu) (CPUMIsGuestInLongModeEx(IEM_GET_CTX(a_pVCpu)))
3729
3730	/**
3731	* Check if we're currently executing in a 16-bit code segment.
3732	*
3733	* @returns @c true if it is, @c false if not.
3734	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3735	*/
3736	#define IEM_IS_16BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_16BIT)
3737
3738	/**
3739	* Check if we're currently executing in a 32-bit code segment.
3740	*
3741	* @returns @c true if it is, @c false if not.
3742	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3743	*/
3744	#define IEM_IS_32BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_32BIT)
3745
3746	/**
3747	* Check if we're currently executing in a 64-bit code segment.
3748	*
3749	* @returns @c true if it is, @c false if not.
3750	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3751	*/
3752	#define IEM_IS_64BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_64BIT)
3753
3754	/**
3755	* Check if we're currently executing in real mode.
3756	*
3757	* @returns @c true if it is, @c false if not.
3758	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3759	*/
3760	#define IEM_IS_REAL_MODE(a_pVCpu) (!((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_PROT_MASK))
3761
3762	/**
3763	* Gets the current protection level (CPL).
3764	*
3765	* @returns 0..3
3766	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3767	*/
3768	#define IEM_GET_CPL(a_pVCpu) (((a_pVCpu)->iem.s.fExec >> IEM_F_X86_CPL_SHIFT) & IEM_F_X86_CPL_SMASK)
3769
3770	/**
3771	* Sets the current protection level (CPL).
3772	*
3773	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3774	*/
3775	#define IEM_SET_CPL(a_pVCpu, a_uCpl) \
3776	do { (a_pVCpu)->iem.s.fExec = ((a_pVCpu)->iem.s.fExec & ~IEM_F_X86_CPL_MASK) \| ((a_uCpl) << IEM_F_X86_CPL_SHIFT); } while (0)
3777
3778	/**
3779	* Returns a (const) pointer to the CPUMFEATURES for the guest CPU.
3780	* @returns PCCPUMFEATURES
3781	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3782	*/
3783	#define IEM_GET_GUEST_CPU_FEATURES(a_pVCpu) (&((a_pVCpu)->CTX_SUFF(pVM)->cpum.ro.GuestFeatures))
3784
3785	/**
3786	* Returns a (const) pointer to the CPUMFEATURES for the host CPU.
3787	* @returns PCCPUMFEATURES
3788	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3789	*/
3790	#define IEM_GET_HOST_CPU_FEATURES(a_pVCpu) (&g_CpumHostFeatures.s)
3791
3792	/**
3793	* Evaluates to true if we're presenting an Intel CPU to the guest.
3794	*/
3795	#define IEM_IS_GUEST_CPU_INTEL(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL )
3796
3797	/**
3798	* Evaluates to true if we're presenting an AMD CPU to the guest.
3799	*/
3800	#define IEM_IS_GUEST_CPU_AMD(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_AMD \|\| (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_HYGON )
3801
3802	/**
3803	* Check if the address is canonical.
3804	*/
3805	#define IEM_IS_CANONICAL(a_u64Addr) X86_IS_CANONICAL(a_u64Addr)
3806
3807	/** Checks if the ModR/M byte is in register mode or not. */
3808	#define IEM_IS_MODRM_REG_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT) )
3809	/** Checks if the ModR/M byte is in memory mode or not. */
3810	#define IEM_IS_MODRM_MEM_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT) )
3811
3812	/**
3813	* Gets the register (reg) part of a ModR/M encoding, with REX.R added in.
3814	*
3815	* For use during decoding.
3816	*/
3817	#define IEM_GET_MODRM_REG(a_pVCpu, a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| (a_pVCpu)->iem.s.uRexReg )
3818	/**
3819	* Gets the r/m part of a ModR/M encoding as a register index, with REX.B added in.
3820	*
3821	* For use during decoding.
3822	*/
3823	#define IEM_GET_MODRM_RM(a_pVCpu, a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) \| (a_pVCpu)->iem.s.uRexB )
3824
3825	/**
3826	* Gets the register (reg) part of a ModR/M encoding, without REX.R.
3827	*
3828	* For use during decoding.
3829	*/
3830	#define IEM_GET_MODRM_REG_8(a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) )
3831	/**
3832	* Gets the r/m part of a ModR/M encoding as a register index, without REX.B.
3833	*
3834	* For use during decoding.
3835	*/
3836	#define IEM_GET_MODRM_RM_8(a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) )
3837
3838	/**
3839	* Gets the register (reg) part of a ModR/M encoding as an extended 8-bit
3840	* register index, with REX.R added in.
3841	*
3842	* For use during decoding.
3843	*
3844	* @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
3845	*/
3846	#define IEM_GET_MODRM_REG_EX8(a_pVCpu, a_bRm) \
3847	( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
3848	\|\| !((a_bRm) & (4 << X86_MODRM_REG_SHIFT)) /* IEM_GET_MODRM_REG(pVCpu, a_bRm) < 4 */ \
3849	? IEM_GET_MODRM_REG(pVCpu, a_bRm) : (((a_bRm) >> X86_MODRM_REG_SHIFT) & 3) \| 16)
3850	/**
3851	* Gets the r/m part of a ModR/M encoding as an extended 8-bit register index,
3852	* with REX.B added in.
3853	*
3854	* For use during decoding.
3855	*
3856	* @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
3857	*/
3858	#define IEM_GET_MODRM_RM_EX8(a_pVCpu, a_bRm) \
3859	( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
3860	\|\| !((a_bRm) & 4) /* IEM_GET_MODRM_RM(pVCpu, a_bRm) < 4 */ \
3861	? IEM_GET_MODRM_RM(pVCpu, a_bRm) : ((a_bRm) & 3) \| 16)
3862
3863	/**
3864	* Combines the prefix REX and ModR/M byte for passing to
3865	* iemOpHlpCalcRmEffAddrThreadedAddr64().
3866	*
3867	* @returns The ModRM byte but with bit 3 set to REX.B and bit 4 to REX.X.
3868	* The two bits are part of the REG sub-field, which isn't needed in
3869	* iemOpHlpCalcRmEffAddrThreadedAddr64().
3870	*
3871	* For use during decoding/recompiling.
3872	*/
3873	#define IEM_GET_MODRM_EX(a_pVCpu, a_bRm) \
3874	( ((a_bRm) & ~X86_MODRM_REG_MASK) \
3875	\| (uint8_t)( (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X)) >> (26 - 3) ) )
3876	AssertCompile(IEM_OP_PRF_REX_B == RT_BIT_32(26));
3877	AssertCompile(IEM_OP_PRF_REX_X == RT_BIT_32(27));
3878
3879	/**
3880	* Gets the effective VEX.VVVV value.
3881	*
3882	* The 4th bit is ignored if not 64-bit code.
3883	* @returns effective V-register value.
3884	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3885	*/
3886	#define IEM_GET_EFFECTIVE_VVVV(a_pVCpu) \
3887	(IEM_IS_64BIT_CODE(a_pVCpu) ? (a_pVCpu)->iem.s.uVex3rdReg : (a_pVCpu)->iem.s.uVex3rdReg & 7)
3888
3889
3890	/**
3891	* Checks if we're executing inside an AMD-V or VT-x guest.
3892	*/
3893	#if defined(VBOX_WITH_NESTED_HWVIRT_VMX) \|\| defined(VBOX_WITH_NESTED_HWVIRT_SVM)
3894	# define IEM_IS_IN_GUEST(a_pVCpu) RT_BOOL((a_pVCpu)->iem.s.fExec & IEM_F_X86_CTX_IN_GUEST)
3895	#else
3896	# define IEM_IS_IN_GUEST(a_pVCpu) false
3897	#endif
3898
3899
3900	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
3901
3902	/**
3903	* Check if the guest has entered VMX root operation.
3904	*/
3905	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxRootMode(IEM_GET_CTX(a_pVCpu)))
3906
3907	/**
3908	* Check if the guest has entered VMX non-root operation.
3909	*/
3910	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) ( ((a_pVCpu)->iem.s.fExec & (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST)) \
3911	== (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST) )
3912
3913	/**
3914	* Check if the nested-guest has the given Pin-based VM-execution control set.
3915	*/
3916	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_PinCtl) (CPUMIsGuestVmxPinCtlsSet(IEM_GET_CTX(a_pVCpu), (a_PinCtl)))
3917
3918	/**
3919	* Check if the nested-guest has the given Processor-based VM-execution control set.
3920	*/
3921	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_ProcCtl) (CPUMIsGuestVmxProcCtlsSet(IEM_GET_CTX(a_pVCpu), (a_ProcCtl)))
3922
3923	/**
3924	* Check if the nested-guest has the given Secondary Processor-based VM-execution
3925	* control set.
3926	*/
3927	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_ProcCtl2) (CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(a_pVCpu), (a_ProcCtl2)))
3928
3929	/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
3930	# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
3931
3932	/** Whether a shadow VMCS is present for the given VCPU. */
3933	# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
3934
3935	/** Gets the VMXON region pointer. */
3936	# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
3937
3938	/** Gets the guest-physical address of the current VMCS for the given VCPU. */
3939	# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
3940
3941	/** Whether a current VMCS is present for the given VCPU. */
3942	# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
3943
3944	/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
3945	# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
3946	do \
3947	{ \
3948	Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
3949	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
3950	} while (0)
3951
3952	/** Clears any current VMCS for the given VCPU. */
3953	# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
3954	do \
3955	{ \
3956	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
3957	} while (0)
3958
3959	/**
3960	* Invokes the VMX VM-exit handler for an instruction intercept.
3961	*/
3962	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) \
3963	do { return iemVmxVmexitInstr((a_pVCpu), (a_uExitReason), (a_cbInstr)); } while (0)
3964
3965	/**
3966	* Invokes the VMX VM-exit handler for an instruction intercept where the
3967	* instruction provides additional VM-exit information.
3968	*/
3969	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) \
3970	do { return iemVmxVmexitInstrNeedsInfo((a_pVCpu), (a_uExitReason), (a_uInstrId), (a_cbInstr)); } while (0)
3971
3972	/**
3973	* Invokes the VMX VM-exit handler for a task switch.
3974	*/
3975	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) \
3976	do { return iemVmxVmexitTaskSwitch((a_pVCpu), (a_enmTaskSwitch), (a_SelNewTss), (a_cbInstr)); } while (0)
3977
3978	/**
3979	* Invokes the VMX VM-exit handler for MWAIT.
3980	*/
3981	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) \
3982	do { return iemVmxVmexitInstrMwait((a_pVCpu), (a_fMonitorArmed), (a_cbInstr)); } while (0)
3983
3984	/**
3985	* Invokes the VMX VM-exit handler for EPT faults.
3986	*/
3987	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) \
3988	do { return iemVmxVmexitEpt(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr); } while (0)
3989
3990	/**
3991	* Invokes the VMX VM-exit handler.
3992	*/
3993	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) \
3994	do { return iemVmxVmexit((a_pVCpu), (a_uExitReason), (a_uExitQual)); } while (0)
3995
3996	#else
3997	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (false)
3998	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (false)
3999	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_cbInstr) (false)
4000	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_cbInstr) (false)
4001	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_cbInstr) (false)
4002	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4003	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4004	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4005	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4006	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4007	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) do { return VERR_VMX_IPE_1; } while (0)
4008
4009	#endif
4010
4011	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4012	/**
4013	* Checks if we're executing a guest using AMD-V.
4014	*/
4015	# define IEM_SVM_IS_IN_GUEST(a_pVCpu) ( (a_pVCpu->iem.s.fExec & (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST)) \
4016	== (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST))
4017	/**
4018	* Check if an SVM control/instruction intercept is set.
4019	*/
4020	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) \
4021	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmCtrlInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_Intercept)))
4022
4023	/**
4024	* Check if an SVM read CRx intercept is set.
4025	*/
4026	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
4027	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
4028
4029	/**
4030	* Check if an SVM write CRx intercept is set.
4031	*/
4032	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
4033	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
4034
4035	/**
4036	* Check if an SVM read DRx intercept is set.
4037	*/
4038	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
4039	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
4040
4041	/**
4042	* Check if an SVM write DRx intercept is set.
4043	*/
4044	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
4045	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
4046
4047	/**
4048	* Check if an SVM exception intercept is set.
4049	*/
4050	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) \
4051	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmXcptInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uVector)))
4052
4053	/**
4054	* Invokes the SVM \#VMEXIT handler for the nested-guest.
4055	*/
4056	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
4057	do { return iemSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2)); } while (0)
4058
4059	/**
4060	* Invokes the 'MOV CRx' SVM \#VMEXIT handler after constructing the
4061	* corresponding decode assist information.
4062	*/
4063	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) \
4064	do \
4065	{ \
4066	uint64_t uExitInfo1; \
4067	if ( IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmDecodeAssists \
4068	&& (a_enmAccessCrX) == IEMACCESSCRX_MOV_CRX) \
4069	uExitInfo1 = SVM_EXIT1_MOV_CRX_MASK \| ((a_iGReg) & 7); \
4070	else \
4071	uExitInfo1 = 0; \
4072	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, uExitInfo1, 0); \
4073	} while (0)
4074
4075	/** Check and handles SVM nested-guest instruction intercept and updates
4076	* NRIP if needed.
4077	*/
4078	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
4079	do \
4080	{ \
4081	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept)) \
4082	{ \
4083	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
4084	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2); \
4085	} \
4086	} while (0)
4087
4088	/** Checks and handles SVM nested-guest CR0 read intercept. */
4089	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
4090	do \
4091	{ \
4092	if (!IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, 0)) \
4093	{ /* probably likely */ } \
4094	else \
4095	{ \
4096	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
4097	IEM_SVM_VMEXIT_RET(a_pVCpu, SVM_EXIT_READ_CR0, a_uExitInfo1, a_uExitInfo2); \
4098	} \
4099	} while (0)
4100
4101	/**
4102	* Updates the NextRIP (NRI) field in the nested-guest VMCB.
4103	*/
4104	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) \
4105	do { \
4106	if (IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmNextRipSave) \
4107	CPUMGuestSvmUpdateNRip(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_cbInstr)); \
4108	} while (0)
4109
4110	#else
4111	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) (false)
4112	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
4113	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
4114	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
4115	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
4116	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) (false)
4117	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { return VERR_SVM_IPE_1; } while (0)
4118	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) do { return VERR_SVM_IPE_1; } while (0)
4119	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, \
4120	a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
4121	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
4122	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) do { } while (0)
4123
4124	#endif
4125
4126	/** @} */
4127
4128	uint32_t iemCalcExecDbgFlagsSlow(PVMCPUCC pVCpu);
4129	VBOXSTRICTRC iemExecInjectPendingTrap(PVMCPUCC pVCpu);
4130
4131
4132	/**
4133	* Selector descriptor table entry as fetched by iemMemFetchSelDesc.
4134	*/
4135	typedef union IEMSELDESC
4136	{
4137	/** The legacy view. */
4138	X86DESC Legacy;
4139	/** The long mode view. */
4140	X86DESC64 Long;
4141	} IEMSELDESC;
4142	/** Pointer to a selector descriptor table entry. */
4143	typedef IEMSELDESC *PIEMSELDESC;
4144
4145	/** @name Raising Exceptions.
4146	* @{ */
4147	VBOXSTRICTRC iemTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, uint32_t uNextEip, uint32_t fFlags,
4148	uint16_t uErr, uint64_t uCr2, RTSEL SelTSS, PIEMSELDESC pNewDescTSS) RT_NOEXCEPT;
4149
4150	VBOXSTRICTRC iemRaiseXcptOrInt(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags,
4151	uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
4152	#ifdef IEM_WITH_SETJMP
4153	DECL_NO_RETURN(void) iemRaiseXcptOrIntJmp(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector,
4154	uint32_t fFlags, uint16_t uErr, uint64_t uCr2) IEM_NOEXCEPT_MAY_LONGJMP;
4155	#endif
4156	VBOXSTRICTRC iemRaiseDivideError(PVMCPUCC pVCpu) RT_NOEXCEPT;
4157	VBOXSTRICTRC iemRaiseDebugException(PVMCPUCC pVCpu) RT_NOEXCEPT;
4158	VBOXSTRICTRC iemRaiseBoundRangeExceeded(PVMCPUCC pVCpu) RT_NOEXCEPT;
4159	VBOXSTRICTRC iemRaiseUndefinedOpcode(PVMCPUCC pVCpu) RT_NOEXCEPT;
4160	VBOXSTRICTRC iemRaiseDeviceNotAvailable(PVMCPUCC pVCpu) RT_NOEXCEPT;
4161	VBOXSTRICTRC iemRaiseTaskSwitchFaultWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
4162	VBOXSTRICTRC iemRaiseTaskSwitchFaultCurrentTSS(PVMCPUCC pVCpu) RT_NOEXCEPT;
4163	VBOXSTRICTRC iemRaiseTaskSwitchFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
4164	VBOXSTRICTRC iemRaiseTaskSwitchFaultBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
4165	/VBOXSTRICTRC iemRaiseSelectorNotPresent(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;/
4166	VBOXSTRICTRC iemRaiseSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
4167	VBOXSTRICTRC iemRaiseSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
4168	VBOXSTRICTRC iemRaiseStackSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
4169	VBOXSTRICTRC iemRaiseStackSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
4170	VBOXSTRICTRC iemRaiseGeneralProtectionFault(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
4171	VBOXSTRICTRC iemRaiseGeneralProtectionFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
4172	#ifdef IEM_WITH_SETJMP
4173	DECL_NO_RETURN(void) iemRaiseGeneralProtectionFault0Jmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4174	#endif
4175	VBOXSTRICTRC iemRaiseGeneralProtectionFaultBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
4176	VBOXSTRICTRC iemRaiseNotCanonical(PVMCPUCC pVCpu) RT_NOEXCEPT;
4177	VBOXSTRICTRC iemRaiseSelectorBounds(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
4178	#ifdef IEM_WITH_SETJMP
4179	DECL_NO_RETURN(void) iemRaiseSelectorBoundsJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
4180	#endif
4181	VBOXSTRICTRC iemRaiseSelectorBoundsBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
4182	#ifdef IEM_WITH_SETJMP
4183	DECL_NO_RETURN(void) iemRaiseSelectorBoundsBySelectorJmp(PVMCPUCC pVCpu, RTSEL Sel) IEM_NOEXCEPT_MAY_LONGJMP;
4184	#endif
4185	VBOXSTRICTRC iemRaiseSelectorInvalidAccess(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
4186	#ifdef IEM_WITH_SETJMP
4187	DECL_NO_RETURN(void) iemRaiseSelectorInvalidAccessJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
4188	#endif
4189	VBOXSTRICTRC iemRaisePageFault(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) RT_NOEXCEPT;
4190	#ifdef IEM_WITH_SETJMP
4191	DECL_NO_RETURN(void) iemRaisePageFaultJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) IEM_NOEXCEPT_MAY_LONGJMP;
4192	#endif
4193	VBOXSTRICTRC iemRaiseMathFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
4194	VBOXSTRICTRC iemRaiseAlignmentCheckException(PVMCPUCC pVCpu) RT_NOEXCEPT;
4195	#ifdef IEM_WITH_SETJMP
4196	DECL_NO_RETURN(void) iemRaiseAlignmentCheckExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4197	#endif
4198	VBOXSTRICTRC iemRaiseSimdFpException(PVMCPUCC pVCpu) RT_NOEXCEPT;
4199
4200	IEM_CIMPL_DEF_0(iemCImplRaiseDivideError);
4201	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidLockPrefix);
4202	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidOpcode);
4203
4204	/**
4205	* Macro for calling iemCImplRaiseDivideError().
4206	*
4207	* This enables us to add/remove arguments and force different levels of
4208	* inlining as we wish.
4209	*
4210	* @return Strict VBox status code.
4211	*/
4212	#define IEMOP_RAISE_DIVIDE_ERROR_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, iemCImplRaiseDivideError)
4213
4214	/**
4215	* Macro for calling iemCImplRaiseInvalidLockPrefix().
4216	*
4217	* This enables us to add/remove arguments and force different levels of
4218	* inlining as we wish.
4219	*
4220	* @return Strict VBox status code.
4221	*/
4222	#define IEMOP_RAISE_INVALID_LOCK_PREFIX_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, iemCImplRaiseInvalidLockPrefix)
4223
4224	/**
4225	* Macro for calling iemCImplRaiseInvalidOpcode().
4226	*
4227	* This enables us to add/remove arguments and force different levels of
4228	* inlining as we wish.
4229	*
4230	* @return Strict VBox status code.
4231	*/
4232	#define IEMOP_RAISE_INVALID_OPCODE_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, iemCImplRaiseInvalidOpcode)
4233	/** @} */
4234
4235	/** @name Register Access.
4236	* @{ */
4237	VBOXSTRICTRC iemRegRipRelativeJumpS8AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int8_t offNextInstr,
4238	IEMMODE enmEffOpSize) RT_NOEXCEPT;
4239	VBOXSTRICTRC iemRegRipRelativeJumpS16AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int16_t offNextInstr) RT_NOEXCEPT;
4240	VBOXSTRICTRC iemRegRipRelativeJumpS32AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int32_t offNextInstr,
4241	IEMMODE enmEffOpSize) RT_NOEXCEPT;
4242	VBOXSTRICTRC iemRegRipJumpU16AndFinishClearningRF(PVMCPUCC pVCpu, uint16_t uNewRip) RT_NOEXCEPT;
4243	VBOXSTRICTRC iemRegRipJumpU32AndFinishClearningRF(PVMCPUCC pVCpu, uint32_t uNewRip) RT_NOEXCEPT;
4244	VBOXSTRICTRC iemRegRipJumpU64AndFinishClearningRF(PVMCPUCC pVCpu, uint64_t uNewRip) RT_NOEXCEPT;
4245	/** @} */
4246
4247	/** @name FPU access and helpers.
4248	* @{ */
4249	void iemFpuPushResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult) RT_NOEXCEPT;
4250	void iemFpuPushResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
4251	void iemFpuPushResultTwo(PVMCPUCC pVCpu, PIEMFPURESULTTWO pResult) RT_NOEXCEPT;
4252	void iemFpuStoreResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg) RT_NOEXCEPT;
4253	void iemFpuStoreResultThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg) RT_NOEXCEPT;
4254	void iemFpuStoreResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
4255	uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
4256	void iemFpuStoreResultWithMemOpThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
4257	uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
4258	void iemFpuUpdateOpcodeAndIp(PVMCPUCC pVCpu) RT_NOEXCEPT;
4259	void iemFpuUpdateFSW(PVMCPUCC pVCpu, uint16_t u16FSW) RT_NOEXCEPT;
4260	void iemFpuUpdateFSWThenPop(PVMCPUCC pVCpu, uint16_t u16FSW) RT_NOEXCEPT;
4261	void iemFpuUpdateFSWWithMemOp(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
4262	void iemFpuUpdateFSWThenPopPop(PVMCPUCC pVCpu, uint16_t u16FSW) RT_NOEXCEPT;
4263	void iemFpuUpdateFSWWithMemOpThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
4264	void iemFpuStackUnderflow(PVMCPUCC pVCpu, uint8_t iStReg) RT_NOEXCEPT;
4265	void iemFpuStackUnderflowWithMemOp(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
4266	void iemFpuStackUnderflowThenPop(PVMCPUCC pVCpu, uint8_t iStReg) RT_NOEXCEPT;
4267	void iemFpuStackUnderflowWithMemOpThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
4268	void iemFpuStackUnderflowThenPopPop(PVMCPUCC pVCpu) RT_NOEXCEPT;
4269	void iemFpuStackPushUnderflow(PVMCPUCC pVCpu) RT_NOEXCEPT;
4270	void iemFpuStackPushUnderflowTwo(PVMCPUCC pVCpu) RT_NOEXCEPT;
4271	void iemFpuStackPushOverflow(PVMCPUCC pVCpu) RT_NOEXCEPT;
4272	void iemFpuStackPushOverflowWithMemOp(PVMCPUCC pVCpu, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
4273	/** @} */
4274
4275	/** @name SSE+AVX SIMD access and helpers.
4276	* @{ */
4277	void iemSseStoreResult(PVMCPUCC pVCpu, PCIEMSSERESULT pResult, uint8_t iXmmReg) RT_NOEXCEPT;
4278	void iemSseUpdateMxcsr(PVMCPUCC pVCpu, uint32_t fMxcsr) RT_NOEXCEPT;
4279	/** @} */
4280
4281	/** @name Memory access.
4282	* @{ */
4283
4284	/** Report a \#GP instead of \#AC and do not restrict to ring-3 */
4285	#define IEM_MEMMAP_F_ALIGN_GP RT_BIT_32(16)
4286	/** SSE access that should report a \#GP instead of \#AC, unless MXCSR.MM=1
4287	* when it works like normal \#AC. Always used with IEM_MEMMAP_F_ALIGN_GP. */
4288	#define IEM_MEMMAP_F_ALIGN_SSE RT_BIT_32(17)
4289	/** If \#AC is applicable, raise it. Always used with IEM_MEMMAP_F_ALIGN_GP.
4290	* Users include FXSAVE & FXRSTOR. */
4291	#define IEM_MEMMAP_F_ALIGN_GP_OR_AC RT_BIT_32(18)
4292
4293	VBOXSTRICTRC iemMemMap(PVMCPUCC pVCpu, void **ppvMem, size_t cbMem, uint8_t iSegReg, RTGCPTR GCPtrMem,
4294	uint32_t fAccess, uint32_t uAlignCtl) RT_NOEXCEPT;
4295	VBOXSTRICTRC iemMemCommitAndUnmap(PVMCPUCC pVCpu, void *pvMem, uint32_t fAccess) RT_NOEXCEPT;
4296	#ifndef IN_RING3
4297	VBOXSTRICTRC iemMemCommitAndUnmapPostponeTroubleToR3(PVMCPUCC pVCpu, void *pvMem, uint32_t fAccess) RT_NOEXCEPT;
4298	#endif
4299	void iemMemRollback(PVMCPUCC pVCpu) RT_NOEXCEPT;
4300	VBOXSTRICTRC iemMemApplySegment(PVMCPUCC pVCpu, uint32_t fAccess, uint8_t iSegReg, size_t cbMem, PRTGCPTR pGCPtrMem) RT_NOEXCEPT;
4301	VBOXSTRICTRC iemMemMarkSelDescAccessed(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
4302	VBOXSTRICTRC iemMemPageTranslateAndCheckAccess(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t cbAccess, uint32_t fAccess, PRTGCPHYS pGCPhysMem) RT_NOEXCEPT;
4303
4304	void iemOpcodeFlushLight(PVMCPUCC pVCpu, uint8_t cbInstr);
4305	void iemOpcodeFlushHeavy(PVMCPUCC pVCpu, uint8_t cbInstr);
4306	#ifdef IEM_WITH_CODE_TLB
4307	void iemOpcodeFetchBytesJmp(PVMCPUCC pVCpu, size_t cbDst, void *pvDst) IEM_NOEXCEPT_MAY_LONGJMP;
4308	#else
4309	VBOXSTRICTRC iemOpcodeFetchMoreBytes(PVMCPUCC pVCpu, size_t cbMin) RT_NOEXCEPT;
4310	#endif
4311	#ifdef IEM_WITH_SETJMP
4312	uint8_t iemOpcodeGetNextU8SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4313	uint16_t iemOpcodeGetNextU16SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4314	uint32_t iemOpcodeGetNextU32SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4315	uint64_t iemOpcodeGetNextU64SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4316	#else
4317	VBOXSTRICTRC iemOpcodeGetNextU8Slow(PVMCPUCC pVCpu, uint8_t *pb) RT_NOEXCEPT;
4318	VBOXSTRICTRC iemOpcodeGetNextS8SxU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
4319	VBOXSTRICTRC iemOpcodeGetNextS8SxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
4320	VBOXSTRICTRC iemOpcodeGetNextS8SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
4321	VBOXSTRICTRC iemOpcodeGetNextU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
4322	VBOXSTRICTRC iemOpcodeGetNextU16ZxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
4323	VBOXSTRICTRC iemOpcodeGetNextU16ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
4324	VBOXSTRICTRC iemOpcodeGetNextU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
4325	VBOXSTRICTRC iemOpcodeGetNextU32ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
4326	VBOXSTRICTRC iemOpcodeGetNextS32SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
4327	VBOXSTRICTRC iemOpcodeGetNextU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
4328	#endif
4329
4330	VBOXSTRICTRC iemMemFetchDataU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4331	VBOXSTRICTRC iemMemFetchDataU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4332	VBOXSTRICTRC iemMemFetchDataU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4333	VBOXSTRICTRC iemMemFetchDataU32_ZX_U64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4334	VBOXSTRICTRC iemMemFetchDataU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4335	VBOXSTRICTRC iemMemFetchDataU64AlignedU128(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4336	VBOXSTRICTRC iemMemFetchDataR80(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4337	VBOXSTRICTRC iemMemFetchDataD80(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4338	VBOXSTRICTRC iemMemFetchDataU128(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4339	VBOXSTRICTRC iemMemFetchDataU128AlignedSse(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4340	VBOXSTRICTRC iemMemFetchDataU256(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4341	VBOXSTRICTRC iemMemFetchDataU256AlignedSse(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4342	VBOXSTRICTRC iemMemFetchDataXdtr(PVMCPUCC pVCpu, uint16_t *pcbLimit, PRTGCPTR pGCPtrBase, uint8_t iSegReg,
4343	RTGCPTR GCPtrMem, IEMMODE enmOpSize) RT_NOEXCEPT;
4344	#ifdef IEM_WITH_SETJMP
4345	uint8_t iemMemFetchDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4346	uint16_t iemMemFetchDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4347	uint32_t iemMemFetchDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4348	uint64_t iemMemFetchDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4349	uint64_t iemMemFetchDataU64AlignedU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4350	void iemMemFetchDataR80Jmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4351	void iemMemFetchDataD80Jmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4352	void iemMemFetchDataU128Jmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4353	void iemMemFetchDataU128AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4354	void iemMemFetchDataU256Jmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4355	void iemMemFetchDataU256AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4356	#endif
4357
4358	VBOXSTRICTRC iemMemFetchSysU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4359	VBOXSTRICTRC iemMemFetchSysU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4360	VBOXSTRICTRC iemMemFetchSysU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4361	VBOXSTRICTRC iemMemFetchSysU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4362	VBOXSTRICTRC iemMemFetchSelDesc(PVMCPUCC pVCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt) RT_NOEXCEPT;
4363
4364	VBOXSTRICTRC iemMemStoreDataU8(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) RT_NOEXCEPT;
4365	VBOXSTRICTRC iemMemStoreDataU16(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) RT_NOEXCEPT;
4366	VBOXSTRICTRC iemMemStoreDataU32(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) RT_NOEXCEPT;
4367	VBOXSTRICTRC iemMemStoreDataU64(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) RT_NOEXCEPT;
4368	VBOXSTRICTRC iemMemStoreDataU128(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
4369	VBOXSTRICTRC iemMemStoreDataU128AlignedSse(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
4370	VBOXSTRICTRC iemMemStoreDataU256(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
4371	VBOXSTRICTRC iemMemStoreDataU256AlignedAvx(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
4372	VBOXSTRICTRC iemMemStoreDataXdtr(PVMCPUCC pVCpu, uint16_t cbLimit, RTGCPTR GCPtrBase, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4373	#ifdef IEM_WITH_SETJMP
4374	void iemMemStoreDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
4375	void iemMemStoreDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
4376	void iemMemStoreDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
4377	void iemMemStoreDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
4378	void iemMemStoreDataU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
4379	void iemMemStoreDataU128AlignedSseJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
4380	void iemMemStoreDataU256Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
4381	void iemMemStoreDataU256AlignedAvxJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
4382	#endif
4383
4384	VBOXSTRICTRC iemMemStackPushBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
4385	void *ppvMem, uint64_t puNewRsp) RT_NOEXCEPT;
4386	VBOXSTRICTRC iemMemStackPushCommitSpecial(PVMCPUCC pVCpu, void *pvMem, uint64_t uNewRsp) RT_NOEXCEPT;
4387	VBOXSTRICTRC iemMemStackPushU16(PVMCPUCC pVCpu, uint16_t u16Value) RT_NOEXCEPT;
4388	VBOXSTRICTRC iemMemStackPushU32(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
4389	VBOXSTRICTRC iemMemStackPushU64(PVMCPUCC pVCpu, uint64_t u64Value) RT_NOEXCEPT;
4390	VBOXSTRICTRC iemMemStackPushU16Ex(PVMCPUCC pVCpu, uint16_t u16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4391	VBOXSTRICTRC iemMemStackPushU32Ex(PVMCPUCC pVCpu, uint32_t u32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4392	VBOXSTRICTRC iemMemStackPushU64Ex(PVMCPUCC pVCpu, uint64_t u64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4393	VBOXSTRICTRC iemMemStackPushU32SReg(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
4394	VBOXSTRICTRC iemMemStackPopBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
4395	void const *ppvMem, uint64_t puNewRsp) RT_NOEXCEPT;
4396	VBOXSTRICTRC iemMemStackPopContinueSpecial(PVMCPUCC pVCpu, size_t off, size_t cbMem,
4397	void const **ppvMem, uint64_t uCurNewRsp) RT_NOEXCEPT;
4398	VBOXSTRICTRC iemMemStackPopDoneSpecial(PVMCPUCC pVCpu, void const *pvMem) RT_NOEXCEPT;
4399	VBOXSTRICTRC iemMemStackPopU16(PVMCPUCC pVCpu, uint16_t *pu16Value) RT_NOEXCEPT;
4400	VBOXSTRICTRC iemMemStackPopU32(PVMCPUCC pVCpu, uint32_t *pu32Value) RT_NOEXCEPT;
4401	VBOXSTRICTRC iemMemStackPopU64(PVMCPUCC pVCpu, uint64_t *pu64Value) RT_NOEXCEPT;
4402	VBOXSTRICTRC iemMemStackPopU16Ex(PVMCPUCC pVCpu, uint16_t *pu16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4403	VBOXSTRICTRC iemMemStackPopU32Ex(PVMCPUCC pVCpu, uint32_t *pu32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4404	VBOXSTRICTRC iemMemStackPopU64Ex(PVMCPUCC pVCpu, uint64_t *pu64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4405	/** @} */
4406
4407	/** @name IEMAllCImpl.cpp
4408	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/'
4409	* @{ */
4410	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem16, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4411	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem32, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4412	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem64, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4413	IEM_CIMPL_PROTO_0(iemCImpl_popa_16);
4414	IEM_CIMPL_PROTO_0(iemCImpl_popa_32);
4415	IEM_CIMPL_PROTO_0(iemCImpl_pusha_16);
4416	IEM_CIMPL_PROTO_0(iemCImpl_pusha_32);
4417	IEM_CIMPL_PROTO_1(iemCImpl_pushf, IEMMODE, enmEffOpSize);
4418	IEM_CIMPL_PROTO_1(iemCImpl_popf, IEMMODE, enmEffOpSize);
4419	IEM_CIMPL_PROTO_1(iemCImpl_call_16, uint16_t, uNewPC);
4420	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_16, int16_t, offDisp);
4421	IEM_CIMPL_PROTO_1(iemCImpl_call_32, uint32_t, uNewPC);
4422	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_32, int32_t, offDisp);
4423	IEM_CIMPL_PROTO_1(iemCImpl_call_64, uint64_t, uNewPC);
4424	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_64, int64_t, offDisp);
4425	IEM_CIMPL_PROTO_3(iemCImpl_FarJmp, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
4426	IEM_CIMPL_PROTO_3(iemCImpl_callf, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
4427	typedef IEM_CIMPL_DECL_TYPE_3(FNIEMCIMPLFARBRANCH, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
4428	typedef FNIEMCIMPLFARBRANCH *PFNIEMCIMPLFARBRANCH;
4429	IEM_CIMPL_PROTO_2(iemCImpl_retf, IEMMODE, enmEffOpSize, uint16_t, cbPop);
4430	IEM_CIMPL_PROTO_0(iemCImpl_retn_16);
4431	IEM_CIMPL_PROTO_0(iemCImpl_retn_32);
4432	IEM_CIMPL_PROTO_0(iemCImpl_retn_64);
4433	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_16, uint16_t, cbPop);
4434	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_32, uint16_t, cbPop);
4435	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_64, uint16_t, cbPop);
4436	IEM_CIMPL_PROTO_3(iemCImpl_enter, IEMMODE, enmEffOpSize, uint16_t, cbFrame, uint8_t, cParameters);
4437	IEM_CIMPL_PROTO_1(iemCImpl_leave, IEMMODE, enmEffOpSize);
4438	IEM_CIMPL_PROTO_2(iemCImpl_int, uint8_t, u8Int, IEMINT, enmInt);
4439	IEM_CIMPL_PROTO_1(iemCImpl_iret_real_v8086, IEMMODE, enmEffOpSize);
4440	IEM_CIMPL_PROTO_4(iemCImpl_iret_prot_v8086, uint32_t, uNewEip, uint16_t, uNewCs, uint32_t, uNewFlags, uint64_t, uNewRsp);
4441	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot_NestedTask, IEMMODE, enmEffOpSize);
4442	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot, IEMMODE, enmEffOpSize);
4443	IEM_CIMPL_PROTO_1(iemCImpl_iret_64bit, IEMMODE, enmEffOpSize);
4444	IEM_CIMPL_PROTO_1(iemCImpl_iret, IEMMODE, enmEffOpSize);
4445	IEM_CIMPL_PROTO_0(iemCImpl_loadall286);
4446	IEM_CIMPL_PROTO_0(iemCImpl_syscall);
4447	IEM_CIMPL_PROTO_1(iemCImpl_sysret, IEMMODE, enmEffOpSize);
4448	IEM_CIMPL_PROTO_0(iemCImpl_sysenter);
4449	IEM_CIMPL_PROTO_1(iemCImpl_sysexit, IEMMODE, enmEffOpSize);
4450	IEM_CIMPL_PROTO_2(iemCImpl_LoadSReg, uint8_t, iSegReg, uint16_t, uSel);
4451	IEM_CIMPL_PROTO_2(iemCImpl_load_SReg, uint8_t, iSegReg, uint16_t, uSel);
4452	IEM_CIMPL_PROTO_2(iemCImpl_pop_Sreg, uint8_t, iSegReg, IEMMODE, enmEffOpSize);
4453	IEM_CIMPL_PROTO_5(iemCImpl_load_SReg_Greg, uint16_t, uSel, uint64_t, offSeg, uint8_t, iSegReg, uint8_t, iGReg, IEMMODE, enmEffOpSize);
4454	IEM_CIMPL_PROTO_2(iemCImpl_VerX, uint16_t, uSel, bool, fWrite);
4455	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u64, uint64_t *, pu64Dst, uint16_t, uSel, bool, fIsLar);
4456	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u16, uint16_t *, pu16Dst, uint16_t, uSel, bool, fIsLar);
4457	IEM_CIMPL_PROTO_3(iemCImpl_lgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
4458	IEM_CIMPL_PROTO_2(iemCImpl_sgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4459	IEM_CIMPL_PROTO_3(iemCImpl_lidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
4460	IEM_CIMPL_PROTO_2(iemCImpl_sidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4461	IEM_CIMPL_PROTO_1(iemCImpl_lldt, uint16_t, uNewLdt);
4462	IEM_CIMPL_PROTO_2(iemCImpl_sldt_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
4463	IEM_CIMPL_PROTO_2(iemCImpl_sldt_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4464	IEM_CIMPL_PROTO_1(iemCImpl_ltr, uint16_t, uNewTr);
4465	IEM_CIMPL_PROTO_2(iemCImpl_str_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
4466	IEM_CIMPL_PROTO_2(iemCImpl_str_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4467	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Cd, uint8_t, iGReg, uint8_t, iCrReg);
4468	IEM_CIMPL_PROTO_2(iemCImpl_smsw_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
4469	IEM_CIMPL_PROTO_2(iemCImpl_smsw_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4470	IEM_CIMPL_PROTO_4(iemCImpl_load_CrX, uint8_t, iCrReg, uint64_t, uNewCrX, IEMACCESSCRX, enmAccessCrX, uint8_t, iGReg);
4471	IEM_CIMPL_PROTO_2(iemCImpl_mov_Cd_Rd, uint8_t, iCrReg, uint8_t, iGReg);
4472	IEM_CIMPL_PROTO_2(iemCImpl_lmsw, uint16_t, u16NewMsw, RTGCPTR, GCPtrEffDst);
4473	IEM_CIMPL_PROTO_0(iemCImpl_clts);
4474	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Dd, uint8_t, iGReg, uint8_t, iDrReg);
4475	IEM_CIMPL_PROTO_2(iemCImpl_mov_Dd_Rd, uint8_t, iDrReg, uint8_t, iGReg);
4476	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Td, uint8_t, iGReg, uint8_t, iTrReg);
4477	IEM_CIMPL_PROTO_2(iemCImpl_mov_Td_Rd, uint8_t, iTrReg, uint8_t, iGReg);
4478	IEM_CIMPL_PROTO_1(iemCImpl_invlpg, RTGCPTR, GCPtrPage);
4479	IEM_CIMPL_PROTO_3(iemCImpl_invpcid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvpcidDesc, uint64_t, uInvpcidType);
4480	IEM_CIMPL_PROTO_0(iemCImpl_invd);
4481	IEM_CIMPL_PROTO_0(iemCImpl_wbinvd);
4482	IEM_CIMPL_PROTO_0(iemCImpl_rsm);
4483	IEM_CIMPL_PROTO_0(iemCImpl_rdtsc);
4484	IEM_CIMPL_PROTO_0(iemCImpl_rdtscp);
4485	IEM_CIMPL_PROTO_0(iemCImpl_rdpmc);
4486	IEM_CIMPL_PROTO_0(iemCImpl_rdmsr);
4487	IEM_CIMPL_PROTO_0(iemCImpl_wrmsr);
4488	IEM_CIMPL_PROTO_3(iemCImpl_in, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
4489	IEM_CIMPL_PROTO_2(iemCImpl_in_eAX_DX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
4490	IEM_CIMPL_PROTO_3(iemCImpl_out, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
4491	IEM_CIMPL_PROTO_2(iemCImpl_out_DX_eAX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
4492	IEM_CIMPL_PROTO_0(iemCImpl_cli);
4493	IEM_CIMPL_PROTO_0(iemCImpl_sti);
4494	IEM_CIMPL_PROTO_0(iemCImpl_hlt);
4495	IEM_CIMPL_PROTO_1(iemCImpl_monitor, uint8_t, iEffSeg);
4496	IEM_CIMPL_PROTO_0(iemCImpl_mwait);
4497	IEM_CIMPL_PROTO_0(iemCImpl_swapgs);
4498	IEM_CIMPL_PROTO_0(iemCImpl_cpuid);
4499	IEM_CIMPL_PROTO_1(iemCImpl_aad, uint8_t, bImm);
4500	IEM_CIMPL_PROTO_1(iemCImpl_aam, uint8_t, bImm);
4501	IEM_CIMPL_PROTO_0(iemCImpl_daa);
4502	IEM_CIMPL_PROTO_0(iemCImpl_das);
4503	IEM_CIMPL_PROTO_0(iemCImpl_aaa);
4504	IEM_CIMPL_PROTO_0(iemCImpl_aas);
4505	IEM_CIMPL_PROTO_3(iemCImpl_bound_16, int16_t, idxArray, int16_t, idxLowerBound, int16_t, idxUpperBound);
4506	IEM_CIMPL_PROTO_3(iemCImpl_bound_32, int32_t, idxArray, int32_t, idxLowerBound, int32_t, idxUpperBound);
4507	IEM_CIMPL_PROTO_0(iemCImpl_xgetbv);
4508	IEM_CIMPL_PROTO_0(iemCImpl_xsetbv);
4509	IEM_CIMPL_PROTO_4(iemCImpl_cmpxchg16b_fallback_rendezvous, PRTUINT128U, pu128Dst, PRTUINT128U, pu128RaxRdx,
4510	PRTUINT128U, pu128RbxRcx, uint32_t *, pEFlags);
4511	IEM_CIMPL_PROTO_2(iemCImpl_clflush_clflushopt, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
4512	IEM_CIMPL_PROTO_1(iemCImpl_finit, bool, fCheckXcpts);
4513	IEM_CIMPL_PROTO_3(iemCImpl_fxsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
4514	IEM_CIMPL_PROTO_3(iemCImpl_fxrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
4515	IEM_CIMPL_PROTO_3(iemCImpl_xsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
4516	IEM_CIMPL_PROTO_3(iemCImpl_xrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
4517	IEM_CIMPL_PROTO_2(iemCImpl_stmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
4518	IEM_CIMPL_PROTO_2(iemCImpl_vstmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
4519	IEM_CIMPL_PROTO_2(iemCImpl_ldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
4520	IEM_CIMPL_PROTO_3(iemCImpl_fnstenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4521	IEM_CIMPL_PROTO_3(iemCImpl_fnsave, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4522	IEM_CIMPL_PROTO_3(iemCImpl_fldenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
4523	IEM_CIMPL_PROTO_3(iemCImpl_frstor, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
4524	IEM_CIMPL_PROTO_1(iemCImpl_fldcw, uint16_t, u16Fcw);
4525	IEM_CIMPL_PROTO_2(iemCImpl_fxch_underflow, uint8_t, iStReg, uint16_t, uFpuOpcode);
4526	IEM_CIMPL_PROTO_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, PFNIEMAIMPLFPUR80EFL, pfnAImpl, uint32_t, uPopAndFpuOpcode);
4527	/** @} */
4528
4529	/** @name IEMAllCImplStrInstr.cpp.h
4530	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/' -e 's/RT_CONCAT4(//' \
4531	* -e 's/,ADDR_SIZE)/64/g' -e 's/,OP_SIZE,/64/g' -e 's/,OP_rAX,/rax/g' IEMAllCImplStrInstr.cpp.h
4532	* @{ */
4533	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr16, uint8_t, iEffSeg);
4534	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr16, uint8_t, iEffSeg);
4535	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m16);
4536	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m16);
4537	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr16, uint8_t, iEffSeg);
4538	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m16);
4539	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m16, int8_t, iEffSeg);
4540	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr16, bool, fIoChecked);
4541	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr16, bool, fIoChecked);
4542	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4543	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4544
4545	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr16, uint8_t, iEffSeg);
4546	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr16, uint8_t, iEffSeg);
4547	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m16);
4548	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m16);
4549	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr16, uint8_t, iEffSeg);
4550	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m16);
4551	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m16, int8_t, iEffSeg);
4552	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr16, bool, fIoChecked);
4553	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr16, bool, fIoChecked);
4554	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4555	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4556
4557	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr16, uint8_t, iEffSeg);
4558	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr16, uint8_t, iEffSeg);
4559	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m16);
4560	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m16);
4561	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr16, uint8_t, iEffSeg);
4562	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m16);
4563	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m16, int8_t, iEffSeg);
4564	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr16, bool, fIoChecked);
4565	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr16, bool, fIoChecked);
4566	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4567	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4568
4569
4570	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr32, uint8_t, iEffSeg);
4571	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr32, uint8_t, iEffSeg);
4572	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m32);
4573	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m32);
4574	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr32, uint8_t, iEffSeg);
4575	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m32);
4576	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m32, int8_t, iEffSeg);
4577	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr32, bool, fIoChecked);
4578	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr32, bool, fIoChecked);
4579	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4580	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4581
4582	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr32, uint8_t, iEffSeg);
4583	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr32, uint8_t, iEffSeg);
4584	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m32);
4585	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m32);
4586	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr32, uint8_t, iEffSeg);
4587	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m32);
4588	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m32, int8_t, iEffSeg);
4589	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr32, bool, fIoChecked);
4590	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr32, bool, fIoChecked);
4591	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4592	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4593
4594	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr32, uint8_t, iEffSeg);
4595	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr32, uint8_t, iEffSeg);
4596	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m32);
4597	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m32);
4598	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr32, uint8_t, iEffSeg);
4599	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m32);
4600	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m32, int8_t, iEffSeg);
4601	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr32, bool, fIoChecked);
4602	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr32, bool, fIoChecked);
4603	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4604	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4605
4606	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr32, uint8_t, iEffSeg);
4607	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr32, uint8_t, iEffSeg);
4608	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m32);
4609	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m32);
4610	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr32, uint8_t, iEffSeg);
4611	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m32);
4612	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m32, int8_t, iEffSeg);
4613	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr32, bool, fIoChecked);
4614	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr32, bool, fIoChecked);
4615	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4616	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4617
4618
4619	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr64, uint8_t, iEffSeg);
4620	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr64, uint8_t, iEffSeg);
4621	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m64);
4622	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m64);
4623	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr64, uint8_t, iEffSeg);
4624	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m64);
4625	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m64, int8_t, iEffSeg);
4626	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr64, bool, fIoChecked);
4627	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr64, bool, fIoChecked);
4628	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4629	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4630
4631	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr64, uint8_t, iEffSeg);
4632	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr64, uint8_t, iEffSeg);
4633	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m64);
4634	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m64);
4635	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr64, uint8_t, iEffSeg);
4636	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m64);
4637	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m64, int8_t, iEffSeg);
4638	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr64, bool, fIoChecked);
4639	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr64, bool, fIoChecked);
4640	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4641	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4642
4643	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr64, uint8_t, iEffSeg);
4644	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr64, uint8_t, iEffSeg);
4645	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m64);
4646	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m64);
4647	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr64, uint8_t, iEffSeg);
4648	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m64);
4649	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m64, int8_t, iEffSeg);
4650	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr64, bool, fIoChecked);
4651	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr64, bool, fIoChecked);
4652	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4653	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4654
4655	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr64, uint8_t, iEffSeg);
4656	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr64, uint8_t, iEffSeg);
4657	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m64);
4658	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m64);
4659	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr64, uint8_t, iEffSeg);
4660	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m64);
4661	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m64, int8_t, iEffSeg);
4662	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr64, bool, fIoChecked);
4663	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr64, bool, fIoChecked);
4664	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4665	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4666	/** @} */
4667
4668	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
4669	VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT;
4670	VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT;
4671	VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT;
4672	VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT;
4673	VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT;
4674	VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
4675	VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALK pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT;
4676	VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT;
4677	VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT;
4678	VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
4679	bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT;
4680	VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
4681	bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT;
4682	VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4683	VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4684	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4685	VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4686	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4687	VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4688	VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT;
4689	VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
4690	RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT;
4691	VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT;
4692	VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT;
4693	VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT;
4694	uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT;
4695	void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT;
4696	VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
4697	uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT;
4698	bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT;
4699	IEM_CIMPL_PROTO_0(iemCImpl_vmxoff);
4700	IEM_CIMPL_PROTO_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon);
4701	IEM_CIMPL_PROTO_0(iemCImpl_vmlaunch);
4702	IEM_CIMPL_PROTO_0(iemCImpl_vmresume);
4703	IEM_CIMPL_PROTO_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
4704	IEM_CIMPL_PROTO_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
4705	IEM_CIMPL_PROTO_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
4706	IEM_CIMPL_PROTO_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField);
4707	IEM_CIMPL_PROTO_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField);
4708	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField);
4709	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg32, uint64_t *, pu32Dst, uint32_t, u32VmcsField);
4710	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField);
4711	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField);
4712	IEM_CIMPL_PROTO_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType);
4713	IEM_CIMPL_PROTO_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType);
4714	IEM_CIMPL_PROTO_0(iemCImpl_vmx_pause);
4715	#endif
4716
4717	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4718	VBOXSTRICTRC iemSvmVmexit(PVMCPUCC pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2) RT_NOEXCEPT;
4719	VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr, uint64_t uCr2) RT_NOEXCEPT;
4720	VBOXSTRICTRC iemSvmHandleIOIntercept(PVMCPUCC pVCpu, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
4721	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, uint8_t cbInstr) RT_NOEXCEPT;
4722	VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPUCC pVCpu, uint32_t idMsr, bool fWrite, uint8_t cbInstr) RT_NOEXCEPT;
4723	IEM_CIMPL_PROTO_0(iemCImpl_vmrun);
4724	IEM_CIMPL_PROTO_0(iemCImpl_vmload);
4725	IEM_CIMPL_PROTO_0(iemCImpl_vmsave);
4726	IEM_CIMPL_PROTO_0(iemCImpl_clgi);
4727	IEM_CIMPL_PROTO_0(iemCImpl_stgi);
4728	IEM_CIMPL_PROTO_0(iemCImpl_invlpga);
4729	IEM_CIMPL_PROTO_0(iemCImpl_skinit);
4730	IEM_CIMPL_PROTO_0(iemCImpl_svm_pause);
4731	#endif
4732
4733	IEM_CIMPL_PROTO_0(iemCImpl_vmcall); /* vmx */
4734	IEM_CIMPL_PROTO_0(iemCImpl_vmmcall); /* svm */
4735	IEM_CIMPL_PROTO_1(iemCImpl_Hypercall, uint16_t, uDisOpcode); /* both */
4736
4737
4738	extern const PFNIEMOP g_apfnIemInterpretOnlyOneByteMap[256];
4739
4740	/** @} */
4741
4742	RT_C_DECLS_END
4743
4744	#endif /* !VMM_INCLUDED_SRC_include_IEMInternal_h */
4745

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source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h@ 100231

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