IEMInternal.h@ 100694

Last change on this file since 100694 was 100694, checked in by vboxsync, 17 months ago
IEM/VMM: Deal with opcode checking cross page boundraries and tentativiely for branches. bugref:10369
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1	/* $Id: IEMInternal.h 100694 2023-07-25 10:34:22Z vboxsync $ */
2	/** @file
3	* IEM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2011-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_IEMInternal_h
29	#define VMM_INCLUDED_SRC_include_IEMInternal_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#include <VBox/vmm/cpum.h>
35	#include <VBox/vmm/iem.h>
36	#include <VBox/vmm/pgm.h>
37	#include <VBox/vmm/stam.h>
38	#include <VBox/param.h>
39
40	#include <iprt/setjmp-without-sigmask.h>
41	#include <iprt/list.h>
42
43
44	RT_C_DECLS_BEGIN
45
46
47	/** @defgroup grp_iem_int Internals
48	* @ingroup grp_iem
49	* @internal
50	* @{
51	*/
52
53	/** For expanding symbol in slickedit and other products tagging and
54	* crossreferencing IEM symbols. */
55	#ifndef IEM_STATIC
56	# define IEM_STATIC static
57	#endif
58
59	/** @def IEM_WITH_SETJMP
60	* Enables alternative status code handling using setjmps.
61	*
62	* This adds a bit of expense via the setjmp() call since it saves all the
63	* non-volatile registers. However, it eliminates return code checks and allows
64	* for more optimal return value passing (return regs instead of stack buffer).
65	*/
66	#if defined(DOXYGEN_RUNNING) \|\| defined(RT_OS_WINDOWS) \|\| 1
67	# define IEM_WITH_SETJMP
68	#endif
69
70	/** @def IEM_WITH_THROW_CATCH
71	* Enables using C++ throw/catch as an alternative to setjmp/longjmp in user
72	* mode code when IEM_WITH_SETJMP is in effect.
73	*
74	* With GCC 11.3.1 and code TLB on linux, using throw/catch instead of
75	* setjmp/long resulted in bs2-test-1 running 3.00% faster and all but on test
76	* result value improving by more than 1%. (Best out of three.)
77	*
78	* With Visual C++ 2019 and code TLB on windows, using throw/catch instead of
79	* setjmp/long resulted in bs2-test-1 running 3.68% faster and all but some of
80	* the MMIO and CPUID tests ran noticeably faster. Variation is greater than on
81	* Linux, but it should be quite a bit faster for normal code.
82	*/
83	#if (defined(IEM_WITH_SETJMP) && defined(IN_RING3) && (defined(__GNUC__) \|\| defined(_MSC_VER))) \
84	\|\| defined(DOXYGEN_RUNNING)
85	# define IEM_WITH_THROW_CATCH
86	#endif
87
88	/** @def IEM_DO_LONGJMP
89	*
90	* Wrapper around longjmp / throw.
91	*
92	* @param a_pVCpu The CPU handle.
93	* @param a_rc The status code jump back with / throw.
94	*/
95	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
96	# ifdef IEM_WITH_THROW_CATCH
97	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) throw int(a_rc)
98	# else
99	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) longjmp(*(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf), (a_rc))
100	# endif
101	#endif
102
103	/** For use with IEM function that may do a longjmp (when enabled).
104	*
105	* Visual C++ has trouble longjmp'ing from/over functions with the noexcept
106	* attribute. So, we indicate that function that may be part of a longjmp may
107	* throw "exceptions" and that the compiler should definitely not generate and
108	* std::terminate calling unwind code.
109	*
110	* Here is one example of this ending in std::terminate:
111	* @code{.txt}
112	00 00000041`cadfda10 00007ffc`5d5a1f9f ucrtbase!abort+0x4e
113	01 00000041`cadfda40 00007ffc`57af229a ucrtbase!terminate+0x1f
114	02 00000041`cadfda70 00007ffb`eec91030 VCRUNTIME140!__std_terminate+0xa [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\ehhelpers.cpp @ 192]
115	03 00000041`cadfdaa0 00007ffb`eec92c6d VCRUNTIME140_1!_CallSettingFrame+0x20 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\handlers.asm @ 50]
116	04 00000041`cadfdad0 00007ffb`eec93ae5 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToState+0x241 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 1085]
117	05 00000041`cadfdc00 00007ffb`eec92258 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToEmptyState+0x2d [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 218]
118	06 00000041`cadfdc30 00007ffb`eec940e9 VCRUNTIME140_1!__InternalCxxFrameHandler<__FrameHandler4>+0x194 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 304]
119	07 00000041`cadfdcd0 00007ffc`5f9f249f VCRUNTIME140_1!__CxxFrameHandler4+0xa9 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 290]
120	08 00000041`cadfdd40 00007ffc`5f980939 ntdll!RtlpExecuteHandlerForUnwind+0xf
121	09 00000041`cadfdd70 00007ffc`5f9a0edd ntdll!RtlUnwindEx+0x339
122	0a 00000041`cadfe490 00007ffc`57aff976 ntdll!RtlUnwind+0xcd
123	0b 00000041`cadfea00 00007ffb`e1b5de01 VCRUNTIME140!__longjmp_internal+0xe6 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\longjmp.asm @ 140]
124	0c (Inline Function) --------`-------- VBoxVMM!iemOpcodeGetNextU8SlowJmp+0x95 [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 1155]
125	0d 00000041`cadfea50 00007ffb`e1b60f6b VBoxVMM!iemOpcodeGetNextU8Jmp+0xc1 [L:\vbox-intern\src\VBox\VMM\include\IEMInline.h @ 402]
126	0e 00000041`cadfea90 00007ffb`e1cc6201 VBoxVMM!IEMExecForExits+0xdb [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 10185]
127	0f 00000041`cadfec70 00007ffb`e1d0df8d VBoxVMM!EMHistoryExec+0x4f1 [L:\vbox-intern\src\VBox\VMM\VMMAll\EMAll.cpp @ 452]
128	10 00000041`cadfed60 00007ffb`e1d0d4c0 VBoxVMM!nemR3WinHandleExitCpuId+0x79d [L:\vbox-intern\src\VBox\VMM\VMMAll\NEMAllNativeTemplate-win.cpp.h @ 1829] @encode
129	@endcode
130	*
131	* @see https://developercommunity.visualstudio.com/t/fragile-behavior-of-longjmp-called-from-noexcept-f/1532859
132	*/
133	#if defined(IEM_WITH_SETJMP) && (defined(_MSC_VER) \|\| defined(IEM_WITH_THROW_CATCH))
134	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT_EX(false)
135	#else
136	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT
137	#endif
138
139	#define IEM_IMPLEMENTS_TASKSWITCH
140
141	/** @def IEM_WITH_3DNOW
142	* Includes the 3DNow decoding. */
143	#if (!defined(IEM_WITH_3DNOW) && !defined(IEM_WITHOUT_3DNOW)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
144	# define IEM_WITH_3DNOW
145	#endif
146
147	/** @def IEM_WITH_THREE_0F_38
148	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
149	#if (!defined(IEM_WITH_THREE_0F_38) && !defined(IEM_WITHOUT_THREE_0F_38)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
150	# define IEM_WITH_THREE_0F_38
151	#endif
152
153	/** @def IEM_WITH_THREE_0F_3A
154	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
155	#if (!defined(IEM_WITH_THREE_0F_3A) && !defined(IEM_WITHOUT_THREE_0F_3A)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
156	# define IEM_WITH_THREE_0F_3A
157	#endif
158
159	/** @def IEM_WITH_VEX
160	* Includes the VEX decoding. */
161	#if (!defined(IEM_WITH_VEX) && !defined(IEM_WITHOUT_VEX)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
162	# define IEM_WITH_VEX
163	#endif
164
165	/** @def IEM_CFG_TARGET_CPU
166	* The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
167	*
168	* By default we allow this to be configured by the user via the
169	* CPUM/GuestCpuName config string, but this comes at a slight cost during
170	* decoding. So, for applications of this code where there is no need to
171	* be dynamic wrt target CPU, just modify this define.
172	*/
173	#if !defined(IEM_CFG_TARGET_CPU) \|\| defined(DOXYGEN_RUNNING)
174	# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
175	#endif
176
177	//#define IEM_WITH_CODE_TLB // - work in progress
178	//#define IEM_WITH_DATA_TLB // - work in progress
179
180
181	/** @def IEM_USE_UNALIGNED_DATA_ACCESS
182	* Use unaligned accesses instead of elaborate byte assembly. */
183	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86) \|\| defined(DOXYGEN_RUNNING)
184	# define IEM_USE_UNALIGNED_DATA_ACCESS
185	#endif
186
187	//#define IEM_LOG_MEMORY_WRITES
188
189	#if !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
190	/** Instruction statistics. */
191	typedef struct IEMINSTRSTATS
192	{
193	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
194	# include "IEMInstructionStatisticsTmpl.h"
195	# undef IEM_DO_INSTR_STAT
196	} IEMINSTRSTATS;
197	#else
198	struct IEMINSTRSTATS;
199	typedef struct IEMINSTRSTATS IEMINSTRSTATS;
200	#endif
201	/** Pointer to IEM instruction statistics. */
202	typedef IEMINSTRSTATS *PIEMINSTRSTATS;
203
204
205	/** @name IEMTARGETCPU_EFL_BEHAVIOR_XXX - IEMCPU::aidxTargetCpuEflFlavour
206	* @{ */
207	#define IEMTARGETCPU_EFL_BEHAVIOR_NATIVE 0 /*< Native x86 EFLAGS result; Intel EFLAGS when on non-x86 hosts. /
208	#define IEMTARGETCPU_EFL_BEHAVIOR_INTEL 1 /*< Intel EFLAGS result. /
209	#define IEMTARGETCPU_EFL_BEHAVIOR_AMD 2 /*< AMD EFLAGS result /
210	#define IEMTARGETCPU_EFL_BEHAVIOR_RESERVED 3 /*< Reserved/dummy entry slot that's the same as 0. /
211	#define IEMTARGETCPU_EFL_BEHAVIOR_MASK 3 /*< For masking the index before use. /
212	/** Selects the right variant from a_aArray.
213	* pVCpu is implicit in the caller context. */
214	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT(a_aArray) \
215	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[1] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
216	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for when no native worker can
217	* be used because the host CPU does not support the operation. */
218	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_NON_NATIVE(a_aArray) \
219	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
220	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for a two dimentional
221	* array paralleling IEMCPU::aidxTargetCpuEflFlavour and a single bit index
222	* into the two.
223	* @sa IEM_SELECT_NATIVE_OR_FALLBACK */
224	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
225	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
226	(a_aaArray[a_fNative][pVCpu->iem.s.aidxTargetCpuEflFlavour[a_fNative] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
227	#else
228	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
229	(a_aaArray[0][pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
230	#endif
231	/** @} */
232
233	/**
234	* Picks @a a_pfnNative or @a a_pfnFallback according to the host CPU feature
235	* indicator given by @a a_fCpumFeatureMember (CPUMFEATURES member).
236	*
237	* On non-x86 hosts, this will shortcut to the fallback w/o checking the
238	* indicator.
239	*
240	* @sa IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX
241	*/
242	#if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
243	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) \
244	(g_CpumHostFeatures.s.a_fCpumFeatureMember ? a_pfnNative : a_pfnFallback)
245	#else
246	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) (a_pfnFallback)
247	#endif
248
249
250	/**
251	* Extended operand mode that includes a representation of 8-bit.
252	*
253	* This is used for packing down modes when invoking some C instruction
254	* implementations.
255	*/
256	typedef enum IEMMODEX
257	{
258	IEMMODEX_16BIT = IEMMODE_16BIT,
259	IEMMODEX_32BIT = IEMMODE_32BIT,
260	IEMMODEX_64BIT = IEMMODE_64BIT,
261	IEMMODEX_8BIT
262	} IEMMODEX;
263	AssertCompileSize(IEMMODEX, 4);
264
265
266	/**
267	* Branch types.
268	*/
269	typedef enum IEMBRANCH
270	{
271	IEMBRANCH_JUMP = 1,
272	IEMBRANCH_CALL,
273	IEMBRANCH_TRAP,
274	IEMBRANCH_SOFTWARE_INT,
275	IEMBRANCH_HARDWARE_INT
276	} IEMBRANCH;
277	AssertCompileSize(IEMBRANCH, 4);
278
279
280	/**
281	* INT instruction types.
282	*/
283	typedef enum IEMINT
284	{
285	/** INT n instruction (opcode 0xcd imm). */
286	IEMINT_INTN = 0,
287	/** Single byte INT3 instruction (opcode 0xcc). */
288	IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
289	/** Single byte INTO instruction (opcode 0xce). */
290	IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
291	/** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
292	IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
293	} IEMINT;
294	AssertCompileSize(IEMINT, 4);
295
296
297	/**
298	* A FPU result.
299	*/
300	typedef struct IEMFPURESULT
301	{
302	/** The output value. */
303	RTFLOAT80U r80Result;
304	/** The output status. */
305	uint16_t FSW;
306	} IEMFPURESULT;
307	AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
308	/** Pointer to a FPU result. */
309	typedef IEMFPURESULT *PIEMFPURESULT;
310	/** Pointer to a const FPU result. */
311	typedef IEMFPURESULT const *PCIEMFPURESULT;
312
313
314	/**
315	* A FPU result consisting of two output values and FSW.
316	*/
317	typedef struct IEMFPURESULTTWO
318	{
319	/** The first output value. */
320	RTFLOAT80U r80Result1;
321	/** The output status. */
322	uint16_t FSW;
323	/** The second output value. */
324	RTFLOAT80U r80Result2;
325	} IEMFPURESULTTWO;
326	AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
327	AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
328	/** Pointer to a FPU result consisting of two output values and FSW. */
329	typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
330	/** Pointer to a const FPU result consisting of two output values and FSW. */
331	typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
332
333
334	/**
335	* IEM TLB entry.
336	*
337	* Lookup assembly:
338	* @code{.asm}
339	; Calculate tag.
340	mov rax, [VA]
341	shl rax, 16
342	shr rax, 16 + X86_PAGE_SHIFT
343	or rax, [uTlbRevision]
344
345	; Do indexing.
346	movzx ecx, al
347	lea rcx, [pTlbEntries + rcx]
348
349	; Check tag.
350	cmp [rcx + IEMTLBENTRY.uTag], rax
351	jne .TlbMiss
352
353	; Check access.
354	mov rax, ACCESS_FLAGS \| MAPPING_R3_NOT_VALID \| 0xffffff00
355	and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
356	cmp rax, [uTlbPhysRev]
357	jne .TlbMiss
358
359	; Calc address and we're done.
360	mov eax, X86_PAGE_OFFSET_MASK
361	and eax, [VA]
362	or rax, [rcx + IEMTLBENTRY.pMappingR3]
363	%ifdef VBOX_WITH_STATISTICS
364	inc qword [cTlbHits]
365	%endif
366	jmp .Done
367
368	.TlbMiss:
369	mov r8d, ACCESS_FLAGS
370	mov rdx, [VA]
371	mov rcx, [pVCpu]
372	call iemTlbTypeMiss
373	.Done:
374
375	@endcode
376	*
377	*/
378	typedef struct IEMTLBENTRY
379	{
380	/** The TLB entry tag.
381	* Bits 35 thru 0 are made up of the virtual address shifted right 12 bits, this
382	* is ASSUMING a virtual address width of 48 bits.
383	*
384	* Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
385	*
386	* The TLB lookup code uses the current TLB revision, which won't ever be zero,
387	* enabling an extremely cheap TLB invalidation most of the time. When the TLB
388	* revision wraps around though, the tags needs to be zeroed.
389	*
390	* @note Try use SHRD instruction? After seeing
391	* https://gmplib.org/~tege/x86-timing.pdf, maybe not.
392	*
393	* @todo This will need to be reorganized for 57-bit wide virtual address and
394	* PCID (currently 12 bits) and ASID (currently 6 bits) support. We'll
395	* have to move the TLB entry versioning entirely to the
396	* fFlagsAndPhysRev member then, 57 bit wide VAs means we'll only have
397	* 19 bits left (64 - 57 + 12 = 19) and they'll almost entire be
398	* consumed by PCID and ASID (12 + 6 = 18).
399	*/
400	uint64_t uTag;
401	/** Access flags and physical TLB revision.
402	*
403	* - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
404	* - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
405	* - Bit 2 - page tables - not user (complemented X86_PTE_US).
406	* - Bit 3 - pgm phys/virt - not directly writable.
407	* - Bit 4 - pgm phys page - not directly readable.
408	* - Bit 5 - page tables - not accessed (complemented X86_PTE_A).
409	* - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
410	* - Bit 7 - tlb entry - pMappingR3 member not valid.
411	* - Bits 63 thru 8 are used for the physical TLB revision number.
412	*
413	* We're using complemented bit meanings here because it makes it easy to check
414	* whether special action is required. For instance a user mode write access
415	* would do a "TEST fFlags, (X86_PTE_RW \| X86_PTE_US \| X86_PTE_D)" and a
416	* non-zero result would mean special handling needed because either it wasn't
417	* writable, or it wasn't user, or the page wasn't dirty. A user mode read
418	* access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
419	* need to check any PTE flag.
420	*/
421	uint64_t fFlagsAndPhysRev;
422	/** The guest physical page address. */
423	uint64_t GCPhys;
424	/** Pointer to the ring-3 mapping. */
425	R3PTRTYPE(uint8_t *) pbMappingR3;
426	#if HC_ARCH_BITS == 32
427	uint32_t u32Padding1;
428	#endif
429	} IEMTLBENTRY;
430	AssertCompileSize(IEMTLBENTRY, 32);
431	/** Pointer to an IEM TLB entry. */
432	typedef IEMTLBENTRY *PIEMTLBENTRY;
433
434	/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
435	* @{ */
436	#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /*< Page tables: Not executable. /
437	#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /*< Page tables: Not writable. /
438	#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /*< Page tables: Not user accessible (supervisor only). /
439	#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /*< Phys page: Not writable (access handler, ROM, whatever). /
440	#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /*< Phys page: Not readable (MMIO / access handler, ROM) /
441	#define IEMTLBE_F_PT_NO_ACCESSED RT_BIT_64(5) /*< Phys tables: Not accessed (need to be marked accessed). /
442	#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /*< Page tables: Not dirty (needs to be made dirty on write). /
443	#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(7) /*< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. /
444	#define IEMTLBE_F_PG_UNASSIGNED RT_BIT_64(8) /*< Phys page: Unassigned memory (not RAM, ROM, MMIO2 or MMIO). /
445	#define IEMTLBE_F_PHYS_REV UINT64_C(0xfffffffffffffe00) /*< Physical revision mask. @sa IEMTLB_PHYS_REV_INCR /
446	/** @} */
447
448
449	/**
450	* An IEM TLB.
451	*
452	* We've got two of these, one for data and one for instructions.
453	*/
454	typedef struct IEMTLB
455	{
456	/** The TLB entries.
457	* We've choosen 256 because that way we can obtain the result directly from a
458	* 8-bit register without an additional AND instruction. */
459	IEMTLBENTRY aEntries[256];
460	/** The TLB revision.
461	* This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
462	* by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
463	* the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
464	* (The revision zero indicates an invalid TLB entry.)
465	*
466	* The initial value is choosen to cause an early wraparound. */
467	uint64_t uTlbRevision;
468	/** The TLB physical address revision - shadow of PGM variable.
469	*
470	* This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
471	* incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
472	* a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
473	* as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
474	*
475	* The initial value is choosen to cause an early wraparound. */
476	uint64_t volatile uTlbPhysRev;
477
478	/* Statistics: */
479
480	/** TLB hits (VBOX_WITH_STATISTICS only). */
481	uint64_t cTlbHits;
482	/** TLB misses. */
483	uint32_t cTlbMisses;
484	/** Slow read path. */
485	uint32_t cTlbSlowReadPath;
486	#if 0
487	/** TLB misses because of tag mismatch. */
488	uint32_t cTlbMissesTag;
489	/** TLB misses because of virtual access violation. */
490	uint32_t cTlbMissesVirtAccess;
491	/** TLB misses because of dirty bit. */
492	uint32_t cTlbMissesDirty;
493	/** TLB misses because of MMIO */
494	uint32_t cTlbMissesMmio;
495	/** TLB misses because of write access handlers. */
496	uint32_t cTlbMissesWriteHandler;
497	/** TLB misses because no r3(/r0) mapping. */
498	uint32_t cTlbMissesMapping;
499	#endif
500	/** Alignment padding. */
501	uint32_t au32Padding[3+5];
502	} IEMTLB;
503	AssertCompileSizeAlignment(IEMTLB, 64);
504	/** IEMTLB::uTlbRevision increment. */
505	#define IEMTLB_REVISION_INCR RT_BIT_64(36)
506	/** IEMTLB::uTlbRevision mask. */
507	#define IEMTLB_REVISION_MASK (~(RT_BIT_64(36) - 1))
508	/** IEMTLB::uTlbPhysRev increment.
509	* @sa IEMTLBE_F_PHYS_REV */
510	#define IEMTLB_PHYS_REV_INCR RT_BIT_64(9)
511	/**
512	* Calculates the TLB tag for a virtual address.
513	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
514	* @param a_pTlb The TLB.
515	* @param a_GCPtr The virtual address.
516	*/
517	#define IEMTLB_CALC_TAG(a_pTlb, a_GCPtr) ( IEMTLB_CALC_TAG_NO_REV(a_GCPtr) \| (a_pTlb)->uTlbRevision )
518	/**
519	* Calculates the TLB tag for a virtual address but without TLB revision.
520	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
521	* @param a_GCPtr The virtual address.
522	*/
523	#define IEMTLB_CALC_TAG_NO_REV(a_GCPtr) ( (((a_GCPtr) << 16) >> (GUEST_PAGE_SHIFT + 16)) )
524	/**
525	* Converts a TLB tag value into a TLB index.
526	* @returns Index into IEMTLB::aEntries.
527	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
528	*/
529	#define IEMTLB_TAG_TO_INDEX(a_uTag) ( (uint8_t)(a_uTag) )
530	/**
531	* Converts a TLB tag value into a TLB index.
532	* @returns Index into IEMTLB::aEntries.
533	* @param a_pTlb The TLB.
534	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
535	*/
536	#define IEMTLB_TAG_TO_ENTRY(a_pTlb, a_uTag) ( &(a_pTlb)->aEntries[IEMTLB_TAG_TO_INDEX(a_uTag)] )
537
538
539	/** @name IEM_F_XXX - Execution mode flags (IEMCPU::fExec, IEMTB::fFlags).
540	*
541	* These flags are set when entering IEM and adjusted as code is executed, such
542	* that they will always contain the current values as instructions are
543	* finished.
544	*
545	* In recompiled execution mode, (most of) these flags are included in the
546	* translation block selection key and stored in IEMTB::fFlags alongside the
547	* IEMTB_F_XXX flags. The latter flags uses bits 31 thru 24, which are all zero
548	* in IEMCPU::fExec.
549	*
550	* @{ */
551	/** Mode: The block target mode mask. */
552	#define IEM_F_MODE_MASK UINT32_C(0x0000001f)
553	/** Mode: The IEMMODE part of the IEMTB_F_MODE_MASK value. */
554	#define IEM_F_MODE_CPUMODE_MASK UINT32_C(0x00000003)
555	/** X86 Mode: Bit used to indicating pre-386 CPU in 16-bit mode (for eliminating
556	* conditional in EIP/IP updating), and flat wide open CS, SS DS, and ES in
557	* 32-bit mode (for simplifying most memory accesses). */
558	#define IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK UINT32_C(0x00000004)
559	/** X86 Mode: Bit indicating protected mode, real mode (or SMM) when not set. */
560	#define IEM_F_MODE_X86_PROT_MASK UINT32_C(0x00000008)
561	/** X86 Mode: Bit used to indicate virtual 8086 mode (only 16-bit). */
562	#define IEM_F_MODE_X86_V86_MASK UINT32_C(0x00000010)
563
564	/** X86 Mode: 16-bit on 386 or later. */
565	#define IEM_F_MODE_X86_16BIT UINT32_C(0x00000000)
566	/** X86 Mode: 80286, 80186 and 8086/88 targetting blocks (EIP update opt). */
567	#define IEM_F_MODE_X86_16BIT_PRE_386 UINT32_C(0x00000004)
568	/** X86 Mode: 16-bit protected mode on 386 or later. */
569	#define IEM_F_MODE_X86_16BIT_PROT UINT32_C(0x00000008)
570	/** X86 Mode: 16-bit protected mode on 386 or later. */
571	#define IEM_F_MODE_X86_16BIT_PROT_PRE_386 UINT32_C(0x0000000c)
572	/** X86 Mode: 16-bit virtual 8086 protected mode (on 386 or later). */
573	#define IEM_F_MODE_X86_16BIT_PROT_V86 UINT32_C(0x00000018)
574
575	/** X86 Mode: 32-bit on 386 or later. */
576	#define IEM_F_MODE_X86_32BIT UINT32_C(0x00000001)
577	/** X86 Mode: 32-bit mode with wide open flat CS, SS, DS and ES. */
578	#define IEM_F_MODE_X86_32BIT_FLAT UINT32_C(0x00000005)
579	/** X86 Mode: 32-bit protected mode. */
580	#define IEM_F_MODE_X86_32BIT_PROT UINT32_C(0x00000009)
581	/** X86 Mode: 32-bit protected mode with wide open flat CS, SS, DS and ES. */
582	#define IEM_F_MODE_X86_32BIT_PROT_FLAT UINT32_C(0x0000000d)
583
584	/** X86 Mode: 64-bit (includes protected, but not the flat bit). */
585	#define IEM_F_MODE_X86_64BIT UINT32_C(0x0000000a)
586
587
588	/** Bypass access handlers when set. */
589	#define IEM_F_BYPASS_HANDLERS UINT32_C(0x00010000)
590	/** Have pending hardware instruction breakpoints. */
591	#define IEM_F_PENDING_BRK_INSTR UINT32_C(0x00020000)
592	/** Have pending hardware data breakpoints. */
593	#define IEM_F_PENDING_BRK_DATA UINT32_C(0x00040000)
594
595	/** X86: Have pending hardware I/O breakpoints. */
596	#define IEM_F_PENDING_BRK_X86_IO UINT32_C(0x00000400)
597	/** X86: Disregard the lock prefix (implied or not) when set. */
598	#define IEM_F_X86_DISREGARD_LOCK UINT32_C(0x00000800)
599
600	/** Pending breakpoint mask (what iemCalcExecDbgFlags works out). */
601	#define IEM_F_PENDING_BRK_MASK (IEM_F_PENDING_BRK_INSTR \| IEM_F_PENDING_BRK_DATA \| IEM_F_PENDING_BRK_X86_IO)
602
603	/** Caller configurable options. */
604	#define IEM_F_USER_OPTS (IEM_F_BYPASS_HANDLERS \| IEM_F_X86_DISREGARD_LOCK)
605
606	/** X86: The current protection level (CPL) shift factor. */
607	#define IEM_F_X86_CPL_SHIFT 8
608	/** X86: The current protection level (CPL) mask. */
609	#define IEM_F_X86_CPL_MASK UINT32_C(0x00000300)
610	/** X86: The current protection level (CPL) shifted mask. */
611	#define IEM_F_X86_CPL_SMASK UINT32_C(0x00000003)
612
613	/** X86 execution context.
614	* The IEM_F_X86_CTX_XXX values are individual flags that can be combined (with
615	* the exception of IEM_F_X86_CTX_NORMAL). This allows running VMs from SMM
616	* mode. */
617	#define IEM_F_X86_CTX_MASK UINT32_C(0x0000f000)
618	/** X86 context: Plain regular execution context. */
619	#define IEM_F_X86_CTX_NORMAL UINT32_C(0x00000000)
620	/** X86 context: VT-x enabled. */
621	#define IEM_F_X86_CTX_VMX UINT32_C(0x00001000)
622	/** X86 context: AMD-V enabled. */
623	#define IEM_F_X86_CTX_SVM UINT32_C(0x00002000)
624	/** X86 context: In AMD-V or VT-x guest mode. */
625	#define IEM_F_X86_CTX_IN_GUEST UINT32_C(0x00004000)
626	/** X86 context: System management mode (SMM). */
627	#define IEM_F_X86_CTX_SMM UINT32_C(0x00008000)
628
629	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
630	* iemRegFinishClearingRF() most for most situations (CPUMCTX_DBG_HIT_DRX_MASK
631	* and CPUMCTX_DBG_DBGF_MASK are covered by the IEM_F_PENDING_BRK_XXX bits
632	* alread). */
633
634	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
635	* iemRegFinishClearingRF() most for most situations
636	* (CPUMCTX_DBG_HIT_DRX_MASK and CPUMCTX_DBG_DBGF_MASK are covered by
637	* the IEM_F_PENDING_BRK_XXX bits alread). */
638
639	/** @} */
640
641
642	/** @name IEMTB_F_XXX - Translation block flags (IEMTB::fFlags).
643	*
644	* Extends the IEM_F_XXX flags (subject to IEMTB_F_IEM_F_MASK) to make up the
645	* translation block flags. The combined flag mask (subject to
646	* IEMTB_F_KEY_MASK) is used as part of the lookup key for translation blocks.
647	*
648	* @{ */
649	/** Mask of IEM_F_XXX flags included in IEMTB_F_XXX. */
650	#define IEMTB_F_IEM_F_MASK UINT32_C(0x00ffffff)
651
652	/** Type: The block type mask. */
653	#define IEMTB_F_TYPE_MASK UINT32_C(0x03000000)
654	/** Type: Purly threaded recompiler (via tables). */
655	#define IEMTB_F_TYPE_THREADED UINT32_C(0x01000000)
656	/** Type: Native recompilation. */
657	#define IEMTB_F_TYPE_NATIVE UINT32_C(0x02000000)
658
659	/** State mask. */
660	#define IEMTB_F_STATE_MASK UINT32_C(0x0c000000)
661	/** State shift count. */
662	#define IEMTB_F_STATE_SHIFT 26
663	/** State: Compiling. */
664	#define IEMTB_F_STATE_COMPILING UINT32_C(0x04000000)
665	/** State: Ready. */
666	#define IEMTB_F_STATE_READY UINT32_C(0x08000000)
667	/** State: Obsolete, can be deleted when we're sure it's not used any longer. */
668	#define IEMTB_F_STATE_OBSOLETE UINT32_C(0x0c000000)
669
670	/** Checks that EIP/IP is wihin CS.LIM before each instruction. Used when
671	* we're close the limit before starting a TB, as determined by
672	* iemGetTbFlagsForCurrentPc(). */
673	#define IEMTB_F_CS_LIM_CHECKS UINT32_C(0x0c000000)
674
675	/** Mask of the IEMTB_F_XXX flags that are part of the TB lookup key.
676	* @note We skip the CPL as we don't currently generate ring-specific code,
677	* that's all handled in CIMPL functions.
678	*
679	* For the same reasons, we skip all of IEM_F_X86_CTX_MASK, with the
680	* exception of SMM (which we don't implement). */
681	#define IEMTB_F_KEY_MASK ((UINT32_C(0xffffffff) & ~(IEM_F_X86_CTX_MASK \| IEM_F_X86_CPL_MASK)) \| IEM_F_X86_CTX_SMM)
682	/** @} */
683
684	AssertCompile( (IEM_F_MODE_X86_16BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
685	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
686	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_PROT_MASK));
687	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_V86_MASK));
688	AssertCompile( (IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
689	AssertCompile( IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
690	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_PROT_MASK));
691	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
692	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
693	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
694	AssertCompile( IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
695	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_V86_MASK));
696	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
697	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
698	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_PROT_MASK);
699	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
700	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_PROT_MASK);
701	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
702	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_V86_MASK);
703
704	AssertCompile( (IEM_F_MODE_X86_32BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
705	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
706	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_PROT_MASK));
707	AssertCompile( (IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
708	AssertCompile( IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
709	AssertCompile(!(IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_PROT_MASK));
710	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
711	AssertCompile(!(IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
712	AssertCompile( IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
713	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
714	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
715	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_PROT_MASK);
716
717	AssertCompile( (IEM_F_MODE_X86_64BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_64BIT);
718	AssertCompile( IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_PROT_MASK);
719	AssertCompile(!(IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
720
721	/**
722	* A call for the threaded call table.
723	*/
724	typedef struct IEMTHRDEDCALLENTRY
725	{
726	/** The function to call (IEMTHREADEDFUNCS). */
727	uint16_t enmFunction;
728	uint16_t uUnused0;
729
730	/** Offset into IEMTB::pabOpcodes. */
731	uint16_t offOpcode;
732	/** The opcode length. */
733	uint8_t cbOpcode;
734	/** Index in to IEMTB::aRanges. */
735	uint8_t idxRange;
736
737	/** Generic parameters. */
738	uint64_t auParams[3];
739	} IEMTHRDEDCALLENTRY;
740	AssertCompileSize(IEMTHRDEDCALLENTRY, sizeof(uint64_t) * 4);
741	/** Pointer to a threaded call entry. */
742	typedef struct IEMTHRDEDCALLENTRY *PIEMTHRDEDCALLENTRY;
743	/** Pointer to a const threaded call entry. */
744	typedef IEMTHRDEDCALLENTRY const *PCIEMTHRDEDCALLENTRY;
745
746	/**
747	* Translation block.
748	*/
749	#pragma pack(2) /* to prevent the Thrd structure from being padded unnecessarily */
750	typedef struct IEMTB
751	{
752	/** Next block with the same hash table entry. */
753	struct IEMTB * volatile pNext;
754	/** List on the local VCPU for blocks. */
755	RTLISTNODE LocalList;
756
757	/** @name What uniquely identifies the block.
758	* @{ */
759	RTGCPHYS GCPhysPc;
760	/** IEMTB_F_XXX (i.e. IEM_F_XXX ++). */
761	uint32_t fFlags;
762	union
763	{
764	struct
765	{
766	/*< Relevant CS X86DESCATTR_XXX bits. /
767	uint16_t fAttr;
768	} x86;
769	};
770	/** @} */
771
772	/** Number of opcode ranges. */
773	uint8_t cRanges;
774	/** Statistics: Number of instructions in the block. */
775	uint8_t cInstructions;
776
777	/** Type specific info. */
778	union
779	{
780	struct
781	{
782	/** The call sequence table. */
783	PIEMTHRDEDCALLENTRY paCalls;
784	/** Number of calls in paCalls. */
785	uint16_t cCalls;
786	/** Number of calls allocated. */
787	uint16_t cAllocated;
788	} Thrd;
789	};
790
791	/** Number of bytes of opcodes stored in pabOpcodes. */
792	uint16_t cbOpcodes;
793	/** The max storage available in the pabOpcodes block. */
794	uint16_t cbOpcodesAllocated;
795	/** Pointer to the opcode bytes this block was recompiled from. */
796	uint8_t *pabOpcodes;
797
798	/* --- 64 byte cache line end --- */
799
800	/** Opcode ranges.
801	*
802	* The opcode checkers and maybe TLB loading functions will use this to figure
803	* out what to do. The parameter will specify an entry and the opcode offset to
804	* start at and the minimum number of bytes to verify (instruction length).
805	*
806	* When VT-x and AMD-V looks up the opcode bytes for an exitting instruction,
807	* they'll first translate RIP (+ cbInstr - 1) to a physical address using the
808	* code TLB (must have a valid entry for that address) and scan the ranges to
809	* locate the corresponding opcodes. Probably.
810	*/
811	struct IEMTBOPCODERANGE
812	{
813	/** Offset within pabOpcodes. */
814	uint16_t offOpcodes;
815	/** Number of bytes. */
816	uint16_t cbOpcodes;
817	/** The page offset. */
818	RT_GCC_EXTENSION
819	uint16_t offPhysPage : 12;
820	/** Unused bits. */
821	RT_GCC_EXTENSION
822	uint16_t u2Unused : 2;
823	/** Index into GCPhysPc + aGCPhysPages for the physical page address. */
824	RT_GCC_EXTENSION
825	uint16_t idxPhysPage : 2;
826	} aRanges[8];
827
828	/** Physical pages that this TB covers.
829	* The GCPhysPc w/o page offset is element zero, so starting here with 1. */
830	RTGCPHYS aGCPhysPages[2];
831	} IEMTB;
832	#pragma pack()
833	AssertCompileMemberOffset(IEMTB, x86, 36);
834	AssertCompileMemberOffset(IEMTB, cRanges, 38);
835	AssertCompileMemberOffset(IEMTB, Thrd, 40);
836	AssertCompileMemberOffset(IEMTB, Thrd.cCalls, 48);
837	AssertCompileMemberOffset(IEMTB, cbOpcodes, 52);
838	AssertCompileMemberSize(IEMTB, aRanges[0], 6);
839	AssertCompileSize(IEMTB, 128);
840	/** Pointer to a translation block. */
841	typedef IEMTB *PIEMTB;
842	/** Pointer to a const translation block. */
843	typedef IEMTB const *PCIEMTB;
844
845
846	/**
847	* The per-CPU IEM state.
848	*/
849	typedef struct IEMCPU
850	{
851	/** Info status code that needs to be propagated to the IEM caller.
852	* This cannot be passed internally, as it would complicate all success
853	* checks within the interpreter making the code larger and almost impossible
854	* to get right. Instead, we'll store status codes to pass on here. Each
855	* source of these codes will perform appropriate sanity checks. */
856	int32_t rcPassUp; /* 0x00 */
857	/** Execution flag, IEM_F_XXX. */
858	uint32_t fExec; /* 0x04 */
859
860	/** @name Decoder state.
861	* @{ */
862	#ifndef IEM_WITH_OPAQUE_DECODER_STATE
863	# ifdef IEM_WITH_CODE_TLB
864	/** The offset of the next instruction byte. */
865	uint32_t offInstrNextByte; /* 0x08 */
866	/** The number of bytes available at pbInstrBuf for the current instruction.
867	* This takes the max opcode length into account so that doesn't need to be
868	* checked separately. */
869	uint32_t cbInstrBuf; /* 0x0c */
870	/** Pointer to the page containing RIP, user specified buffer or abOpcode.
871	* This can be NULL if the page isn't mappable for some reason, in which
872	* case we'll do fallback stuff.
873	*
874	* If we're executing an instruction from a user specified buffer,
875	* IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
876	* aligned pointer but pointer to the user data.
877	*
878	* For instructions crossing pages, this will start on the first page and be
879	* advanced to the next page by the time we've decoded the instruction. This
880	* therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
881	*/
882	uint8_t const pbInstrBuf; / 0x10 */
883	# if ARCH_BITS == 32
884	uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
885	# endif
886	/** The program counter corresponding to pbInstrBuf.
887	* This is set to a non-canonical address when we need to invalidate it. */
888	uint64_t uInstrBufPc; /* 0x18 */
889	/** The guest physical address corresponding to pbInstrBuf. */
890	RTGCPHYS GCPhysInstrBuf; /* 0x20 */
891	/** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
892	* This takes the CS segment limit into account. */
893	uint16_t cbInstrBufTotal; /* 0x28 */
894	/** Offset into pbInstrBuf of the first byte of the current instruction.
895	* Can be negative to efficiently handle cross page instructions. */
896	int16_t offCurInstrStart; /* 0x2a */
897
898	/** The prefix mask (IEM_OP_PRF_XXX). */
899	uint32_t fPrefixes; /* 0x2c */
900	/** The extra REX ModR/M register field bit (REX.R << 3). */
901	uint8_t uRexReg; /* 0x30 */
902	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
903	* (REX.B << 3). */
904	uint8_t uRexB; /* 0x31 */
905	/** The extra REX SIB index field bit (REX.X << 3). */
906	uint8_t uRexIndex; /* 0x32 */
907
908	/** The effective segment register (X86_SREG_XXX). */
909	uint8_t iEffSeg; /* 0x33 */
910
911	/** The offset of the ModR/M byte relative to the start of the instruction. */
912	uint8_t offModRm; /* 0x34 */
913
914	# ifdef IEM_WITH_CODE_TLB_AND_OPCODE_BUF
915	/** The current offset into abOpcode. */
916	uint8_t offOpcode; /* 0x35 */
917	# else
918	uint8_t bUnused; /* 0x35 */
919	# endif
920	# else /* !IEM_WITH_CODE_TLB */
921	/** The size of what has currently been fetched into abOpcode. */
922	uint8_t cbOpcode; /* 0x08 */
923	/** The current offset into abOpcode. */
924	uint8_t offOpcode; /* 0x09 */
925	/** The offset of the ModR/M byte relative to the start of the instruction. */
926	uint8_t offModRm; /* 0x0a */
927
928	/** The effective segment register (X86_SREG_XXX). */
929	uint8_t iEffSeg; /* 0x0b */
930
931	/** The prefix mask (IEM_OP_PRF_XXX). */
932	uint32_t fPrefixes; /* 0x0c */
933	/** The extra REX ModR/M register field bit (REX.R << 3). */
934	uint8_t uRexReg; /* 0x10 */
935	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
936	* (REX.B << 3). */
937	uint8_t uRexB; /* 0x11 */
938	/** The extra REX SIB index field bit (REX.X << 3). */
939	uint8_t uRexIndex; /* 0x12 */
940
941	# endif /* !IEM_WITH_CODE_TLB */
942
943	/** The effective operand mode. */
944	IEMMODE enmEffOpSize; /* 0x36, 0x13 */
945	/** The default addressing mode. */
946	IEMMODE enmDefAddrMode; /* 0x37, 0x14 */
947	/** The effective addressing mode. */
948	IEMMODE enmEffAddrMode; /* 0x38, 0x15 */
949	/** The default operand mode. */
950	IEMMODE enmDefOpSize; /* 0x39, 0x16 */
951
952	/** Prefix index (VEX.pp) for two byte and three byte tables. */
953	uint8_t idxPrefix; /* 0x3a, 0x17 */
954	/** 3rd VEX/EVEX/XOP register.
955	* Please use IEM_GET_EFFECTIVE_VVVV to access. */
956	uint8_t uVex3rdReg; /* 0x3b, 0x18 */
957	/** The VEX/EVEX/XOP length field. */
958	uint8_t uVexLength; /* 0x3c, 0x19 */
959	/** Additional EVEX stuff. */
960	uint8_t fEvexStuff; /* 0x3d, 0x1a */
961
962	# ifndef IEM_WITH_CODE_TLB
963	/** Explicit alignment padding. */
964	uint8_t abAlignment2a[1]; /* 0x1b */
965	# endif
966	/** The FPU opcode (FOP). */
967	uint16_t uFpuOpcode; /* 0x3e, 0x1c */
968	# ifndef IEM_WITH_CODE_TLB
969	/** Explicit alignment padding. */
970	uint8_t abAlignment2b[2]; /* 0x1e */
971	# endif
972
973	/** The opcode bytes. */
974	uint8_t abOpcode[15]; /* 0x40, 0x20 */
975	/** Explicit alignment padding. */
976	# ifdef IEM_WITH_CODE_TLB
977	//uint8_t abAlignment2c[0x4f - 0x4f]; /* 0x4f */
978	# else
979	uint8_t abAlignment2c[0x4f - 0x2f]; /* 0x2f */
980	# endif
981	#else /* IEM_WITH_OPAQUE_DECODER_STATE */
982	uint8_t abOpaqueDecoder[0x4f - 0x8];
983	#endif /* IEM_WITH_OPAQUE_DECODER_STATE */
984	/** @} */
985
986
987	/** The number of active guest memory mappings. */
988	uint8_t cActiveMappings; /* 0x4f, 0x4f */
989
990	/** Records for tracking guest memory mappings. */
991	struct
992	{
993	/** The address of the mapped bytes. */
994	R3R0PTRTYPE(void *) pv;
995	/** The access flags (IEM_ACCESS_XXX).
996	* IEM_ACCESS_INVALID if the entry is unused. */
997	uint32_t fAccess;
998	#if HC_ARCH_BITS == 64
999	uint32_t u32Alignment4; /*< Alignment padding. /
1000	#endif
1001	} aMemMappings[3]; /* 0x50 LB 0x30 */
1002
1003	/** Locking records for the mapped memory. */
1004	union
1005	{
1006	PGMPAGEMAPLOCK Lock;
1007	uint64_t au64Padding[2];
1008	} aMemMappingLocks[3]; /* 0x80 LB 0x30 */
1009
1010	/** Bounce buffer info.
1011	* This runs in parallel to aMemMappings. */
1012	struct
1013	{
1014	/** The physical address of the first byte. */
1015	RTGCPHYS GCPhysFirst;
1016	/** The physical address of the second page. */
1017	RTGCPHYS GCPhysSecond;
1018	/** The number of bytes in the first page. */
1019	uint16_t cbFirst;
1020	/** The number of bytes in the second page. */
1021	uint16_t cbSecond;
1022	/** Whether it's unassigned memory. */
1023	bool fUnassigned;
1024	/** Explicit alignment padding. */
1025	bool afAlignment5[3];
1026	} aMemBbMappings[3]; /* 0xb0 LB 0x48 */
1027
1028	/** The flags of the current exception / interrupt. */
1029	uint32_t fCurXcpt; /* 0xf8 */
1030	/** The current exception / interrupt. */
1031	uint8_t uCurXcpt; /* 0xfc */
1032	/** Exception / interrupt recursion depth. */
1033	int8_t cXcptRecursions; /* 0xfb */
1034
1035	/** The next unused mapping index.
1036	* @todo try find room for this up with cActiveMappings. */
1037	uint8_t iNextMapping; /* 0xfd */
1038	uint8_t abAlignment7[1];
1039
1040	/** Bounce buffer storage.
1041	* This runs in parallel to aMemMappings and aMemBbMappings. */
1042	struct
1043	{
1044	uint8_t ab[512];
1045	} aBounceBuffers[3]; /* 0x100 LB 0x600 */
1046
1047
1048	/** Pointer set jump buffer - ring-3 context. */
1049	R3PTRTYPE(jmp_buf *) pJmpBufR3;
1050	/** Pointer set jump buffer - ring-0 context. */
1051	R0PTRTYPE(jmp_buf *) pJmpBufR0;
1052
1053	/** @todo Should move this near @a fCurXcpt later. */
1054	/** The CR2 for the current exception / interrupt. */
1055	uint64_t uCurXcptCr2;
1056	/** The error code for the current exception / interrupt. */
1057	uint32_t uCurXcptErr;
1058
1059	/** @name Statistics
1060	* @{ */
1061	/** The number of instructions we've executed. */
1062	uint32_t cInstructions;
1063	/** The number of potential exits. */
1064	uint32_t cPotentialExits;
1065	/** The number of bytes data or stack written (mostly for IEMExecOneEx).
1066	* This may contain uncommitted writes. */
1067	uint32_t cbWritten;
1068	/** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
1069	uint32_t cRetInstrNotImplemented;
1070	/** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
1071	uint32_t cRetAspectNotImplemented;
1072	/** Counts informational statuses returned (other than VINF_SUCCESS). */
1073	uint32_t cRetInfStatuses;
1074	/** Counts other error statuses returned. */
1075	uint32_t cRetErrStatuses;
1076	/** Number of times rcPassUp has been used. */
1077	uint32_t cRetPassUpStatus;
1078	/** Number of times RZ left with instruction commit pending for ring-3. */
1079	uint32_t cPendingCommit;
1080	/** Number of long jumps. */
1081	uint32_t cLongJumps;
1082	/** @} */
1083
1084	/** @name Target CPU information.
1085	* @{ */
1086	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
1087	/** The target CPU. */
1088	uint8_t uTargetCpu;
1089	#else
1090	uint8_t bTargetCpuPadding;
1091	#endif
1092	/** For selecting assembly works matching the target CPU EFLAGS behaviour, see
1093	* IEMTARGETCPU_EFL_BEHAVIOR_XXX for values, with the 1st entry for when no
1094	* native host support and the 2nd for when there is.
1095	*
1096	* The two values are typically indexed by a g_CpumHostFeatures bit.
1097	*
1098	* This is for instance used for the BSF & BSR instructions where AMD and
1099	* Intel CPUs produce different EFLAGS. */
1100	uint8_t aidxTargetCpuEflFlavour[2];
1101
1102	/** The CPU vendor. */
1103	CPUMCPUVENDOR enmCpuVendor;
1104	/** @} */
1105
1106	/** @name Host CPU information.
1107	* @{ */
1108	/** The CPU vendor. */
1109	CPUMCPUVENDOR enmHostCpuVendor;
1110	/** @} */
1111
1112	/** Counts RDMSR \#GP(0) LogRel(). */
1113	uint8_t cLogRelRdMsr;
1114	/** Counts WRMSR \#GP(0) LogRel(). */
1115	uint8_t cLogRelWrMsr;
1116	/** Alignment padding. */
1117	uint8_t abAlignment9[46];
1118
1119	/** @name Recompilation
1120	* @{ */
1121	/** Pointer to the current translation block.
1122	* This can either be one being executed or one being compiled. */
1123	R3PTRTYPE(PIEMTB) pCurTbR3;
1124	/** The PC (RIP) at the start of pCurTbR3/pCurTbR0.
1125	* The TBs are based on physical addresses, so this is needed to correleated
1126	* RIP to opcode bytes stored in the TB (AMD-V / VT-x). */
1127	uint64_t uCurTbStartPc;
1128	/** Statistics: Number of TB allocation calls. */
1129	uint64_t cTbAllocs;
1130	/** Statistics: Number of TB free calls. */
1131	uint64_t cTbFrees;
1132	/** Statistics: Number of TB lookup misses. */
1133	uint64_t cTbLookupMisses;
1134	/** Statistics: Number of TB lookup hits (debug only). */
1135	uint64_t cTbLookupHits;
1136	/** Number of TBs executed. */
1137	uint64_t cTbExec;
1138	/** Whether we need to check the opcode bytes for the current instruction.
1139	* This is set by a previous instruction if it modified memory or similar. */
1140	bool fTbCheckOpcodes;
1141	/** Whether we just branched and need to start a new opcode range and emit code
1142	* to do a TLB load and check them again. */
1143	bool fTbBranched;
1144	/** Set when GCPhysInstrBuf is updated because of a page crossing. */
1145	bool fTbCrossedPage;
1146	/** Whether to end the current TB. */
1147	bool fEndTb;
1148	/** Spaced reserved for recompiler data / alignment. */
1149	bool afRecompilerStuff1[4];
1150	/** @} */
1151
1152	/** Data TLB.
1153	* @remarks Must be 64-byte aligned. */
1154	IEMTLB DataTlb;
1155	/** Instruction TLB.
1156	* @remarks Must be 64-byte aligned. */
1157	IEMTLB CodeTlb;
1158
1159	/** Exception statistics. */
1160	STAMCOUNTER aStatXcpts[32];
1161	/** Interrupt statistics. */
1162	uint32_t aStatInts[256];
1163
1164	#if defined(VBOX_WITH_STATISTICS) && !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
1165	/** Instruction statistics for ring-0/raw-mode. */
1166	IEMINSTRSTATS StatsRZ;
1167	/** Instruction statistics for ring-3. */
1168	IEMINSTRSTATS StatsR3;
1169	#endif
1170	} IEMCPU;
1171	AssertCompileMemberOffset(IEMCPU, cActiveMappings, 0x4f);
1172	AssertCompileMemberAlignment(IEMCPU, aMemMappings, 16);
1173	AssertCompileMemberAlignment(IEMCPU, aMemMappingLocks, 16);
1174	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 64);
1175	AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
1176	AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
1177
1178	/** Pointer to the per-CPU IEM state. */
1179	typedef IEMCPU *PIEMCPU;
1180	/** Pointer to the const per-CPU IEM state. */
1181	typedef IEMCPU const *PCIEMCPU;
1182
1183
1184	/** @def IEM_GET_CTX
1185	* Gets the guest CPU context for the calling EMT.
1186	* @returns PCPUMCTX
1187	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1188	*/
1189	#define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
1190
1191	/** @def IEM_CTX_ASSERT
1192	* Asserts that the @a a_fExtrnMbz is present in the CPU context.
1193	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1194	* @param a_fExtrnMbz The mask of CPUMCTX_EXTRN_XXX flags that must be zero.
1195	*/
1196	#define IEM_CTX_ASSERT(a_pVCpu, a_fExtrnMbz) AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
1197	("fExtrn=%#RX64 fExtrnMbz=%#RX64\n", (a_pVCpu)->cpum.GstCtx.fExtrn, \
1198	(a_fExtrnMbz)))
1199
1200	/** @def IEM_CTX_IMPORT_RET
1201	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
1202	*
1203	* Will call the keep to import the bits as needed.
1204	*
1205	* Returns on import failure.
1206	*
1207	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1208	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
1209	*/
1210	#define IEM_CTX_IMPORT_RET(a_pVCpu, a_fExtrnImport) \
1211	do { \
1212	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
1213	{ /* likely */ } \
1214	else \
1215	{ \
1216	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
1217	AssertRCReturn(rcCtxImport, rcCtxImport); \
1218	} \
1219	} while (0)
1220
1221	/** @def IEM_CTX_IMPORT_NORET
1222	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
1223	*
1224	* Will call the keep to import the bits as needed.
1225	*
1226	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1227	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
1228	*/
1229	#define IEM_CTX_IMPORT_NORET(a_pVCpu, a_fExtrnImport) \
1230	do { \
1231	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
1232	{ /* likely */ } \
1233	else \
1234	{ \
1235	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
1236	AssertLogRelRC(rcCtxImport); \
1237	} \
1238	} while (0)
1239
1240	/** @def IEM_CTX_IMPORT_JMP
1241	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
1242	*
1243	* Will call the keep to import the bits as needed.
1244	*
1245	* Jumps on import failure.
1246	*
1247	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1248	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
1249	*/
1250	#define IEM_CTX_IMPORT_JMP(a_pVCpu, a_fExtrnImport) \
1251	do { \
1252	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
1253	{ /* likely */ } \
1254	else \
1255	{ \
1256	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
1257	AssertRCStmt(rcCtxImport, IEM_DO_LONGJMP(pVCpu, rcCtxImport)); \
1258	} \
1259	} while (0)
1260
1261
1262
1263	/** @def IEM_GET_TARGET_CPU
1264	* Gets the current IEMTARGETCPU value.
1265	* @returns IEMTARGETCPU value.
1266	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1267	*/
1268	#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
1269	# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
1270	#else
1271	# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
1272	#endif
1273
1274	/** @def IEM_GET_INSTR_LEN
1275	* Gets the instruction length. */
1276	#ifdef IEM_WITH_CODE_TLB
1277	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
1278	#else
1279	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
1280	#endif
1281
1282	/** @def IEM_TRY_SETJMP
1283	* Wrapper around setjmp / try, hiding all the ugly differences.
1284	*
1285	* @note Use with extreme care as this is a fragile macro.
1286	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
1287	* @param a_rcTarget The variable that should receive the status code in case
1288	* of a longjmp/throw.
1289	*/
1290	/** @def IEM_TRY_SETJMP_AGAIN
1291	* For when setjmp / try is used again in the same variable scope as a previous
1292	* IEM_TRY_SETJMP invocation.
1293	*/
1294	/** @def IEM_CATCH_LONGJMP_BEGIN
1295	* Start wrapper for catch / setjmp-else.
1296	*
1297	* This will set up a scope.
1298	*
1299	* @note Use with extreme care as this is a fragile macro.
1300	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
1301	* @param a_rcTarget The variable that should receive the status code in case
1302	* of a longjmp/throw.
1303	*/
1304	/** @def IEM_CATCH_LONGJMP_END
1305	* End wrapper for catch / setjmp-else.
1306	*
1307	* This will close the scope set up by IEM_CATCH_LONGJMP_BEGIN and clean up the
1308	* state.
1309	*
1310	* @note Use with extreme care as this is a fragile macro.
1311	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
1312	*/
1313	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
1314	# ifdef IEM_WITH_THROW_CATCH
1315	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
1316	a_rcTarget = VINF_SUCCESS; \
1317	try
1318	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
1319	IEM_TRY_SETJMP(a_pVCpu, a_rcTarget)
1320	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
1321	catch (int rcThrown) \
1322	{ \
1323	a_rcTarget = rcThrown
1324	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
1325	} \
1326	((void)0)
1327	# else /* !IEM_WITH_THROW_CATCH */
1328	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
1329	jmp_buf JmpBuf; \
1330	jmp_buf * volatile pSavedJmpBuf = pVCpu->iem.s.CTX_SUFF(pJmpBuf); \
1331	pVCpu->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
1332	if ((rcStrict = setjmp(JmpBuf)) == 0)
1333	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
1334	pSavedJmpBuf = pVCpu->iem.s.CTX_SUFF(pJmpBuf); \
1335	pVCpu->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
1336	if ((rcStrict = setjmp(JmpBuf)) == 0)
1337	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
1338	else \
1339	{ \
1340	((void)0)
1341	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
1342	} \
1343	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = pSavedJmpBuf
1344	# endif /* !IEM_WITH_THROW_CATCH */
1345	#endif /* IEM_WITH_SETJMP */
1346
1347
1348	/**
1349	* Shared per-VM IEM data.
1350	*/
1351	typedef struct IEM
1352	{
1353	/** The VMX APIC-access page handler type. */
1354	PGMPHYSHANDLERTYPE hVmxApicAccessPage;
1355	#ifndef VBOX_WITHOUT_CPUID_HOST_CALL
1356	/** Set if the CPUID host call functionality is enabled. */
1357	bool fCpuIdHostCall;
1358	#endif
1359	} IEM;
1360
1361
1362
1363	/** @name IEM_ACCESS_XXX - Access details.
1364	* @{ */
1365	#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
1366	#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
1367	#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
1368	#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
1369	#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
1370	#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
1371	#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
1372	#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
1373	#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
1374	#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
1375	/** The writes are partial, so if initialize the bounce buffer with the
1376	* orignal RAM content. */
1377	#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
1378	/** Used in aMemMappings to indicate that the entry is bounce buffered. */
1379	#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
1380	/** Bounce buffer with ring-3 write pending, first page. */
1381	#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
1382	/** Bounce buffer with ring-3 write pending, second page. */
1383	#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
1384	/** Not locked, accessed via the TLB. */
1385	#define IEM_ACCESS_NOT_LOCKED UINT32_C(0x00001000)
1386	/** Valid bit mask. */
1387	#define IEM_ACCESS_VALID_MASK UINT32_C(0x00001fff)
1388	/** Shift count for the TLB flags (upper word). */
1389	#define IEM_ACCESS_SHIFT_TLB_FLAGS 16
1390
1391	/** Read+write data alias. */
1392	#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
1393	/** Write data alias. */
1394	#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
1395	/** Read data alias. */
1396	#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_DATA)
1397	/** Instruction fetch alias. */
1398	#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_WHAT_CODE)
1399	/** Stack write alias. */
1400	#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
1401	/** Stack read alias. */
1402	#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_STACK)
1403	/** Stack read+write alias. */
1404	#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
1405	/** Read system table alias. */
1406	#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_SYS)
1407	/** Read+write system table alias. */
1408	#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_SYS)
1409	/** @} */
1410
1411	/** @name Prefix constants (IEMCPU::fPrefixes)
1412	* @{ */
1413	#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /*< CS segment prefix (0x2e). /
1414	#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /*< SS segment prefix (0x36). /
1415	#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /*< DS segment prefix (0x3e). /
1416	#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /*< ES segment prefix (0x26). /
1417	#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /*< FS segment prefix (0x64). /
1418	#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /*< GS segment prefix (0x65). /
1419	#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
1420
1421	#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /*< Operand size prefix (0x66). /
1422	#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /*< REX.W prefix (0x48-0x4f). /
1423	#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /*< Address size prefix (0x67). /
1424
1425	#define IEM_OP_PRF_LOCK RT_BIT_32(16) /*< Lock prefix (0xf0). /
1426	#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /*< Repeat-not-zero prefix (0xf2). /
1427	#define IEM_OP_PRF_REPZ RT_BIT_32(18) /*< Repeat-if-zero prefix (0xf3). /
1428
1429	#define IEM_OP_PRF_REX RT_BIT_32(24) /*< Any REX prefix (0x40-0x4f). /
1430	#define IEM_OP_PRF_REX_R RT_BIT_32(25) /*< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). /
1431	#define IEM_OP_PRF_REX_B RT_BIT_32(26) /*< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). /
1432	#define IEM_OP_PRF_REX_X RT_BIT_32(27) /*< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). /
1433	/** Mask with all the REX prefix flags.
1434	* This is generally for use when needing to undo the REX prefixes when they
1435	* are followed legacy prefixes and therefore does not immediately preceed
1436	* the first opcode byte.
1437	* For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
1438	#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX \| IEM_OP_PRF_REX_R \| IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X \| IEM_OP_PRF_SIZE_REX_W )
1439
1440	#define IEM_OP_PRF_VEX RT_BIT_32(28) /*< Indiciates VEX prefix. /
1441	#define IEM_OP_PRF_EVEX RT_BIT_32(29) /*< Indiciates EVEX prefix. /
1442	#define IEM_OP_PRF_XOP RT_BIT_32(30) /*< Indiciates XOP prefix. /
1443	/** @} */
1444
1445	/** @name IEMOPFORM_XXX - Opcode forms
1446	* @note These are ORed together with IEMOPHINT_XXX.
1447	* @{ */
1448	/** ModR/M: reg, r/m */
1449	#define IEMOPFORM_RM 0
1450	/** ModR/M: reg, r/m (register) */
1451	#define IEMOPFORM_RM_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
1452	/** ModR/M: reg, r/m (memory) */
1453	#define IEMOPFORM_RM_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
1454	/** ModR/M: reg, r/m */
1455	#define IEMOPFORM_RMI 1
1456	/** ModR/M: reg, r/m (register) */
1457	#define IEMOPFORM_RMI_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
1458	/** ModR/M: reg, r/m (memory) */
1459	#define IEMOPFORM_RMI_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
1460	/** ModR/M: r/m, reg */
1461	#define IEMOPFORM_MR 2
1462	/** ModR/M: r/m (register), reg */
1463	#define IEMOPFORM_MR_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
1464	/** ModR/M: r/m (memory), reg */
1465	#define IEMOPFORM_MR_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
1466	/** ModR/M: r/m, reg */
1467	#define IEMOPFORM_MRI 3
1468	/** ModR/M: r/m (register), reg */
1469	#define IEMOPFORM_MRI_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
1470	/** ModR/M: r/m (memory), reg */
1471	#define IEMOPFORM_MRI_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
1472	/** ModR/M: r/m only */
1473	#define IEMOPFORM_M 4
1474	/** ModR/M: r/m only (register). */
1475	#define IEMOPFORM_M_REG (IEMOPFORM_M \| IEMOPFORM_MOD3)
1476	/** ModR/M: r/m only (memory). */
1477	#define IEMOPFORM_M_MEM (IEMOPFORM_M \| IEMOPFORM_NOT_MOD3)
1478	/** ModR/M: reg only */
1479	#define IEMOPFORM_R 5
1480
1481	/** VEX+ModR/M: reg, r/m */
1482	#define IEMOPFORM_VEX_RM 8
1483	/** VEX+ModR/M: reg, r/m (register) */
1484	#define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM \| IEMOPFORM_MOD3)
1485	/** VEX+ModR/M: reg, r/m (memory) */
1486	#define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM \| IEMOPFORM_NOT_MOD3)
1487	/** VEX+ModR/M: r/m, reg */
1488	#define IEMOPFORM_VEX_MR 9
1489	/** VEX+ModR/M: r/m (register), reg */
1490	#define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR \| IEMOPFORM_MOD3)
1491	/** VEX+ModR/M: r/m (memory), reg */
1492	#define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR \| IEMOPFORM_NOT_MOD3)
1493	/** VEX+ModR/M: r/m only */
1494	#define IEMOPFORM_VEX_M 10
1495	/** VEX+ModR/M: r/m only (register). */
1496	#define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M \| IEMOPFORM_MOD3)
1497	/** VEX+ModR/M: r/m only (memory). */
1498	#define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M \| IEMOPFORM_NOT_MOD3)
1499	/** VEX+ModR/M: reg only */
1500	#define IEMOPFORM_VEX_R 11
1501	/** VEX+ModR/M: reg, vvvv, r/m */
1502	#define IEMOPFORM_VEX_RVM 12
1503	/** VEX+ModR/M: reg, vvvv, r/m (register). */
1504	#define IEMOPFORM_VEX_RVM_REG (IEMOPFORM_VEX_RVM \| IEMOPFORM_MOD3)
1505	/** VEX+ModR/M: reg, vvvv, r/m (memory). */
1506	#define IEMOPFORM_VEX_RVM_MEM (IEMOPFORM_VEX_RVM \| IEMOPFORM_NOT_MOD3)
1507	/** VEX+ModR/M: reg, r/m, vvvv */
1508	#define IEMOPFORM_VEX_RMV 13
1509	/** VEX+ModR/M: reg, r/m, vvvv (register). */
1510	#define IEMOPFORM_VEX_RMV_REG (IEMOPFORM_VEX_RMV \| IEMOPFORM_MOD3)
1511	/** VEX+ModR/M: reg, r/m, vvvv (memory). */
1512	#define IEMOPFORM_VEX_RMV_MEM (IEMOPFORM_VEX_RMV \| IEMOPFORM_NOT_MOD3)
1513	/** VEX+ModR/M: reg, r/m, imm8 */
1514	#define IEMOPFORM_VEX_RMI 14
1515	/** VEX+ModR/M: reg, r/m, imm8 (register). */
1516	#define IEMOPFORM_VEX_RMI_REG (IEMOPFORM_VEX_RMI \| IEMOPFORM_MOD3)
1517	/** VEX+ModR/M: reg, r/m, imm8 (memory). */
1518	#define IEMOPFORM_VEX_RMI_MEM (IEMOPFORM_VEX_RMI \| IEMOPFORM_NOT_MOD3)
1519	/** VEX+ModR/M: r/m, vvvv, reg */
1520	#define IEMOPFORM_VEX_MVR 15
1521	/** VEX+ModR/M: r/m, vvvv, reg (register) */
1522	#define IEMOPFORM_VEX_MVR_REG (IEMOPFORM_VEX_MVR \| IEMOPFORM_MOD3)
1523	/** VEX+ModR/M: r/m, vvvv, reg (memory) */
1524	#define IEMOPFORM_VEX_MVR_MEM (IEMOPFORM_VEX_MVR \| IEMOPFORM_NOT_MOD3)
1525	/** VEX+ModR/M+/n: vvvv, r/m */
1526	#define IEMOPFORM_VEX_VM 16
1527	/** VEX+ModR/M+/n: vvvv, r/m (register) */
1528	#define IEMOPFORM_VEX_VM_REG (IEMOPFORM_VEX_VM \| IEMOPFORM_MOD3)
1529	/** VEX+ModR/M+/n: vvvv, r/m (memory) */
1530	#define IEMOPFORM_VEX_VM_MEM (IEMOPFORM_VEX_VM \| IEMOPFORM_NOT_MOD3)
1531
1532	/** Fixed register instruction, no R/M. */
1533	#define IEMOPFORM_FIXED 32
1534
1535	/** The r/m is a register. */
1536	#define IEMOPFORM_MOD3 RT_BIT_32(8)
1537	/** The r/m is a memory access. */
1538	#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
1539	/** @} */
1540
1541	/** @name IEMOPHINT_XXX - Additional Opcode Hints
1542	* @note These are ORed together with IEMOPFORM_XXX.
1543	* @{ */
1544	/** Ignores the operand size prefix (66h). */
1545	#define IEMOPHINT_IGNORES_OZ_PFX RT_BIT_32(10)
1546	/** Ignores REX.W (aka WIG). */
1547	#define IEMOPHINT_IGNORES_REXW RT_BIT_32(11)
1548	/** Both the operand size prefixes (66h + REX.W) are ignored. */
1549	#define IEMOPHINT_IGNORES_OP_SIZES (IEMOPHINT_IGNORES_OZ_PFX \| IEMOPHINT_IGNORES_REXW)
1550	/** Allowed with the lock prefix. */
1551	#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
1552	/** The VEX.L value is ignored (aka LIG). */
1553	#define IEMOPHINT_VEX_L_IGNORED RT_BIT_32(12)
1554	/** The VEX.L value must be zero (i.e. 128-bit width only). */
1555	#define IEMOPHINT_VEX_L_ZERO RT_BIT_32(13)
1556	/** The VEX.V value must be zero. */
1557	#define IEMOPHINT_VEX_V_ZERO RT_BIT_32(14)
1558
1559	/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
1560	#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
1561	/** @} */
1562
1563	/**
1564	* Possible hardware task switch sources.
1565	*/
1566	typedef enum IEMTASKSWITCH
1567	{
1568	/** Task switch caused by an interrupt/exception. */
1569	IEMTASKSWITCH_INT_XCPT = 1,
1570	/** Task switch caused by a far CALL. */
1571	IEMTASKSWITCH_CALL,
1572	/** Task switch caused by a far JMP. */
1573	IEMTASKSWITCH_JUMP,
1574	/** Task switch caused by an IRET. */
1575	IEMTASKSWITCH_IRET
1576	} IEMTASKSWITCH;
1577	AssertCompileSize(IEMTASKSWITCH, 4);
1578
1579	/**
1580	* Possible CrX load (write) sources.
1581	*/
1582	typedef enum IEMACCESSCRX
1583	{
1584	/** CrX access caused by 'mov crX' instruction. */
1585	IEMACCESSCRX_MOV_CRX,
1586	/** CrX (CR0) write caused by 'lmsw' instruction. */
1587	IEMACCESSCRX_LMSW,
1588	/** CrX (CR0) write caused by 'clts' instruction. */
1589	IEMACCESSCRX_CLTS,
1590	/** CrX (CR0) read caused by 'smsw' instruction. */
1591	IEMACCESSCRX_SMSW
1592	} IEMACCESSCRX;
1593
1594	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1595	/** @name IEM_SLAT_FAIL_XXX - Second-level address translation failure information.
1596	*
1597	* These flags provide further context to SLAT page-walk failures that could not be
1598	* determined by PGM (e.g, PGM is not privy to memory access permissions).
1599	*
1600	* @{
1601	*/
1602	/** Translating a nested-guest linear address failed accessing a nested-guest
1603	* physical address. */
1604	# define IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR RT_BIT_32(0)
1605	/** Translating a nested-guest linear address failed accessing a
1606	* paging-structure entry or updating accessed/dirty bits. */
1607	# define IEM_SLAT_FAIL_LINEAR_TO_PAGE_TABLE RT_BIT_32(1)
1608	/** @} */
1609
1610	DECLCALLBACK(FNPGMPHYSHANDLER) iemVmxApicAccessPageHandler;
1611	# ifndef IN_RING3
1612	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) iemVmxApicAccessPagePfHandler;
1613	# endif
1614	#endif
1615
1616	/**
1617	* Indicates to the verifier that the given flag set is undefined.
1618	*
1619	* Can be invoked again to add more flags.
1620	*
1621	* This is a NOOP if the verifier isn't compiled in.
1622	*
1623	* @note We're temporarily keeping this until code is converted to new
1624	* disassembler style opcode handling.
1625	*/
1626	#define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
1627
1628
1629	/** @def IEM_DECL_IMPL_TYPE
1630	* For typedef'ing an instruction implementation function.
1631	*
1632	* @param a_RetType The return type.
1633	* @param a_Name The name of the type.
1634	* @param a_ArgList The argument list enclosed in parentheses.
1635	*/
1636
1637	/** @def IEM_DECL_IMPL_DEF
1638	* For defining an instruction implementation function.
1639	*
1640	* @param a_RetType The return type.
1641	* @param a_Name The name of the type.
1642	* @param a_ArgList The argument list enclosed in parentheses.
1643	*/
1644
1645	#if defined(__GNUC__) && defined(RT_ARCH_X86)
1646	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1647	__attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
1648	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1649	__attribute__((__fastcall__, __nothrow__)) a_RetType a_Name a_ArgList
1650	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1651	__attribute__((__fastcall__, __nothrow__)) a_RetType a_Name a_ArgList
1652
1653	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
1654	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1655	a_RetType (__fastcall a_Name) a_ArgList
1656	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1657	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
1658	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1659	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
1660
1661	#elif __cplusplus >= 201700 /* P0012R1 support */
1662	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1663	a_RetType (VBOXCALL a_Name) a_ArgList RT_NOEXCEPT
1664	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1665	a_RetType VBOXCALL a_Name a_ArgList RT_NOEXCEPT
1666	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1667	a_RetType VBOXCALL a_Name a_ArgList RT_NOEXCEPT
1668
1669	#else
1670	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1671	a_RetType (VBOXCALL a_Name) a_ArgList
1672	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1673	a_RetType VBOXCALL a_Name a_ArgList
1674	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1675	a_RetType VBOXCALL a_Name a_ArgList
1676
1677	#endif
1678
1679	/** Defined in IEMAllAImplC.cpp but also used by IEMAllAImplA.asm. */
1680	RT_C_DECLS_BEGIN
1681	extern uint8_t const g_afParity[256];
1682	RT_C_DECLS_END
1683
1684
1685	/** @name Arithmetic assignment operations on bytes (binary).
1686	* @{ */
1687	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU8, (uint8_t pu8Dst, uint8_t u8Src, uint32_t pEFlags));
1688	typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
1689	FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
1690	FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
1691	FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
1692	FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
1693	FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
1694	FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
1695	FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
1696	/** @} */
1697
1698	/** @name Arithmetic assignment operations on words (binary).
1699	* @{ */
1700	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU16, (uint16_t pu16Dst, uint16_t u16Src, uint32_t pEFlags));
1701	typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
1702	FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
1703	FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
1704	FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
1705	FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
1706	FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
1707	FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
1708	FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
1709	/** @} */
1710
1711	/** @name Arithmetic assignment operations on double words (binary).
1712	* @{ */
1713	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU32, (uint32_t pu32Dst, uint32_t u32Src, uint32_t pEFlags));
1714	typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
1715	FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
1716	FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
1717	FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
1718	FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
1719	FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
1720	FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
1721	FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
1722	FNIEMAIMPLBINU32 iemAImpl_blsi_u32, iemAImpl_blsi_u32_fallback;
1723	FNIEMAIMPLBINU32 iemAImpl_blsr_u32, iemAImpl_blsr_u32_fallback;
1724	FNIEMAIMPLBINU32 iemAImpl_blsmsk_u32, iemAImpl_blsmsk_u32_fallback;
1725	/** @} */
1726
1727	/** @name Arithmetic assignment operations on quad words (binary).
1728	* @{ */
1729	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU64, (uint64_t pu64Dst, uint64_t u64Src, uint32_t pEFlags));
1730	typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
1731	FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
1732	FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
1733	FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
1734	FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
1735	FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
1736	FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
1737	FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
1738	FNIEMAIMPLBINU64 iemAImpl_blsi_u64, iemAImpl_blsi_u64_fallback;
1739	FNIEMAIMPLBINU64 iemAImpl_blsr_u64, iemAImpl_blsr_u64_fallback;
1740	FNIEMAIMPLBINU64 iemAImpl_blsmsk_u64, iemAImpl_blsmsk_u64_fallback;
1741	/** @} */
1742
1743	/** @name Compare operations (thrown in with the binary ops).
1744	* @{ */
1745	FNIEMAIMPLBINU8 iemAImpl_cmp_u8;
1746	FNIEMAIMPLBINU16 iemAImpl_cmp_u16;
1747	FNIEMAIMPLBINU32 iemAImpl_cmp_u32;
1748	FNIEMAIMPLBINU64 iemAImpl_cmp_u64;
1749	/** @} */
1750
1751	/** @name Test operations (thrown in with the binary ops).
1752	* @{ */
1753	FNIEMAIMPLBINU8 iemAImpl_test_u8;
1754	FNIEMAIMPLBINU16 iemAImpl_test_u16;
1755	FNIEMAIMPLBINU32 iemAImpl_test_u32;
1756	FNIEMAIMPLBINU64 iemAImpl_test_u64;
1757	/** @} */
1758
1759	/** @name Bit operations operations (thrown in with the binary ops).
1760	* @{ */
1761	FNIEMAIMPLBINU16 iemAImpl_bt_u16;
1762	FNIEMAIMPLBINU32 iemAImpl_bt_u32;
1763	FNIEMAIMPLBINU64 iemAImpl_bt_u64;
1764	FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
1765	FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
1766	FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
1767	FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
1768	FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
1769	FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
1770	FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
1771	FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
1772	FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
1773	/** @} */
1774
1775	/** @name Arithmetic three operand operations on double words (binary).
1776	* @{ */
1777	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32, (uint32_t pu32Dst, uint32_t u32Src1, uint32_t u32Src2, uint32_t pEFlags));
1778	typedef FNIEMAIMPLBINVEXU32 *PFNIEMAIMPLBINVEXU32;
1779	FNIEMAIMPLBINVEXU32 iemAImpl_andn_u32, iemAImpl_andn_u32_fallback;
1780	FNIEMAIMPLBINVEXU32 iemAImpl_bextr_u32, iemAImpl_bextr_u32_fallback;
1781	FNIEMAIMPLBINVEXU32 iemAImpl_bzhi_u32, iemAImpl_bzhi_u32_fallback;
1782	/** @} */
1783
1784	/** @name Arithmetic three operand operations on quad words (binary).
1785	* @{ */
1786	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64, (uint64_t pu64Dst, uint64_t u64Src1, uint64_t u64Src2, uint32_t pEFlags));
1787	typedef FNIEMAIMPLBINVEXU64 *PFNIEMAIMPLBINVEXU64;
1788	FNIEMAIMPLBINVEXU64 iemAImpl_andn_u64, iemAImpl_andn_u64_fallback;
1789	FNIEMAIMPLBINVEXU64 iemAImpl_bextr_u64, iemAImpl_bextr_u64_fallback;
1790	FNIEMAIMPLBINVEXU64 iemAImpl_bzhi_u64, iemAImpl_bzhi_u64_fallback;
1791	/** @} */
1792
1793	/** @name Arithmetic three operand operations on double words w/o EFLAGS (binary).
1794	* @{ */
1795	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32NOEFL, (uint32_t *pu32Dst, uint32_t u32Src1, uint32_t u32Src2));
1796	typedef FNIEMAIMPLBINVEXU32NOEFL *PFNIEMAIMPLBINVEXU32NOEFL;
1797	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pdep_u32, iemAImpl_pdep_u32_fallback;
1798	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pext_u32, iemAImpl_pext_u32_fallback;
1799	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_sarx_u32, iemAImpl_sarx_u32_fallback;
1800	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shlx_u32, iemAImpl_shlx_u32_fallback;
1801	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shrx_u32, iemAImpl_shrx_u32_fallback;
1802	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_rorx_u32;
1803	/** @} */
1804
1805	/** @name Arithmetic three operand operations on quad words w/o EFLAGS (binary).
1806	* @{ */
1807	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64NOEFL, (uint64_t *pu64Dst, uint64_t u64Src1, uint64_t u64Src2));
1808	typedef FNIEMAIMPLBINVEXU64NOEFL *PFNIEMAIMPLBINVEXU64NOEFL;
1809	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pdep_u64, iemAImpl_pdep_u64_fallback;
1810	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pext_u64, iemAImpl_pext_u64_fallback;
1811	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_sarx_u64, iemAImpl_sarx_u64_fallback;
1812	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shlx_u64, iemAImpl_shlx_u64_fallback;
1813	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shrx_u64, iemAImpl_shrx_u64_fallback;
1814	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_rorx_u64;
1815	/** @} */
1816
1817	/** @name MULX 32-bit and 64-bit.
1818	* @{ */
1819	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU32, (uint32_t puDst1, uint32_t puDst2, uint32_t uSrc1, uint32_t uSrc2));
1820	typedef FNIEMAIMPLMULXVEXU32 *PFNIEMAIMPLMULXVEXU32;
1821	FNIEMAIMPLMULXVEXU32 iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback;
1822
1823	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU64, (uint64_t puDst1, uint64_t puDst2, uint64_t uSrc1, uint64_t uSrc2));
1824	typedef FNIEMAIMPLMULXVEXU64 *PFNIEMAIMPLMULXVEXU64;
1825	FNIEMAIMPLMULXVEXU64 iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback;
1826	/** @} */
1827
1828
1829	/** @name Exchange memory with register operations.
1830	* @{ */
1831	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_locked, (uint8_t pu8Mem, uint8_t pu8Reg));
1832	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_locked,(uint16_t pu16Mem, uint16_t pu16Reg));
1833	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_locked,(uint32_t pu32Mem, uint32_t pu32Reg));
1834	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_locked,(uint64_t pu64Mem, uint64_t pu64Reg));
1835	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_unlocked, (uint8_t pu8Mem, uint8_t pu8Reg));
1836	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_unlocked,(uint16_t pu16Mem, uint16_t pu16Reg));
1837	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_unlocked,(uint32_t pu32Mem, uint32_t pu32Reg));
1838	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_unlocked,(uint64_t pu64Mem, uint64_t pu64Reg));
1839	/** @} */
1840
1841	/** @name Exchange and add operations.
1842	* @{ */
1843	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1844	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1845	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1846	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1847	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1848	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1849	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1850	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1851	/** @} */
1852
1853	/** @name Compare and exchange.
1854	* @{ */
1855	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1856	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1857	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1858	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1859	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1860	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1861	#if ARCH_BITS == 32
1862	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1863	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1864	#else
1865	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1866	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1867	#endif
1868	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1869	uint32_t *pEFlags));
1870	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1871	uint32_t *pEFlags));
1872	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1873	uint32_t *pEFlags));
1874	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1875	uint32_t *pEFlags));
1876	#ifndef RT_ARCH_ARM64
1877	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
1878	PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
1879	#endif
1880	/** @} */
1881
1882	/** @name Memory ordering
1883	* @{ */
1884	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
1885	typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
1886	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
1887	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
1888	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
1889	#ifndef RT_ARCH_ARM64
1890	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
1891	#endif
1892	/** @} */
1893
1894	/** @name Double precision shifts
1895	* @{ */
1896	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t pEFlags));
1897	typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
1898	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t pEFlags));
1899	typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
1900	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t pEFlags));
1901	typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
1902	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16, iemAImpl_shld_u16_amd, iemAImpl_shld_u16_intel;
1903	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32, iemAImpl_shld_u32_amd, iemAImpl_shld_u32_intel;
1904	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64, iemAImpl_shld_u64_amd, iemAImpl_shld_u64_intel;
1905	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16, iemAImpl_shrd_u16_amd, iemAImpl_shrd_u16_intel;
1906	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32, iemAImpl_shrd_u32_amd, iemAImpl_shrd_u32_intel;
1907	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64, iemAImpl_shrd_u64_amd, iemAImpl_shrd_u64_intel;
1908	/** @} */
1909
1910
1911	/** @name Bit search operations (thrown in with the binary ops).
1912	* @{ */
1913	FNIEMAIMPLBINU16 iemAImpl_bsf_u16, iemAImpl_bsf_u16_amd, iemAImpl_bsf_u16_intel;
1914	FNIEMAIMPLBINU32 iemAImpl_bsf_u32, iemAImpl_bsf_u32_amd, iemAImpl_bsf_u32_intel;
1915	FNIEMAIMPLBINU64 iemAImpl_bsf_u64, iemAImpl_bsf_u64_amd, iemAImpl_bsf_u64_intel;
1916	FNIEMAIMPLBINU16 iemAImpl_bsr_u16, iemAImpl_bsr_u16_amd, iemAImpl_bsr_u16_intel;
1917	FNIEMAIMPLBINU32 iemAImpl_bsr_u32, iemAImpl_bsr_u32_amd, iemAImpl_bsr_u32_intel;
1918	FNIEMAIMPLBINU64 iemAImpl_bsr_u64, iemAImpl_bsr_u64_amd, iemAImpl_bsr_u64_intel;
1919	FNIEMAIMPLBINU16 iemAImpl_lzcnt_u16, iemAImpl_lzcnt_u16_amd, iemAImpl_lzcnt_u16_intel;
1920	FNIEMAIMPLBINU32 iemAImpl_lzcnt_u32, iemAImpl_lzcnt_u32_amd, iemAImpl_lzcnt_u32_intel;
1921	FNIEMAIMPLBINU64 iemAImpl_lzcnt_u64, iemAImpl_lzcnt_u64_amd, iemAImpl_lzcnt_u64_intel;
1922	FNIEMAIMPLBINU16 iemAImpl_tzcnt_u16, iemAImpl_tzcnt_u16_amd, iemAImpl_tzcnt_u16_intel;
1923	FNIEMAIMPLBINU32 iemAImpl_tzcnt_u32, iemAImpl_tzcnt_u32_amd, iemAImpl_tzcnt_u32_intel;
1924	FNIEMAIMPLBINU64 iemAImpl_tzcnt_u64, iemAImpl_tzcnt_u64_amd, iemAImpl_tzcnt_u64_intel;
1925	FNIEMAIMPLBINU16 iemAImpl_popcnt_u16, iemAImpl_popcnt_u16_fallback;
1926	FNIEMAIMPLBINU32 iemAImpl_popcnt_u32, iemAImpl_popcnt_u32_fallback;
1927	FNIEMAIMPLBINU64 iemAImpl_popcnt_u64, iemAImpl_popcnt_u64_fallback;
1928	/** @} */
1929
1930	/** @name Signed multiplication operations (thrown in with the binary ops).
1931	* @{ */
1932	FNIEMAIMPLBINU16 iemAImpl_imul_two_u16, iemAImpl_imul_two_u16_amd, iemAImpl_imul_two_u16_intel;
1933	FNIEMAIMPLBINU32 iemAImpl_imul_two_u32, iemAImpl_imul_two_u32_amd, iemAImpl_imul_two_u32_intel;
1934	FNIEMAIMPLBINU64 iemAImpl_imul_two_u64, iemAImpl_imul_two_u64_amd, iemAImpl_imul_two_u64_intel;
1935	/** @} */
1936
1937	/** @name Arithmetic assignment operations on bytes (unary).
1938	* @{ */
1939	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t pu8Dst, uint32_t pEFlags));
1940	typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
1941	FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
1942	FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
1943	FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
1944	FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
1945	/** @} */
1946
1947	/** @name Arithmetic assignment operations on words (unary).
1948	* @{ */
1949	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t pu16Dst, uint32_t pEFlags));
1950	typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
1951	FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
1952	FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
1953	FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
1954	FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
1955	/** @} */
1956
1957	/** @name Arithmetic assignment operations on double words (unary).
1958	* @{ */
1959	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t pu32Dst, uint32_t pEFlags));
1960	typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
1961	FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
1962	FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
1963	FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
1964	FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
1965	/** @} */
1966
1967	/** @name Arithmetic assignment operations on quad words (unary).
1968	* @{ */
1969	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t pu64Dst, uint32_t pEFlags));
1970	typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
1971	FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
1972	FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
1973	FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
1974	FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
1975	/** @} */
1976
1977
1978	/** @name Shift operations on bytes (Group 2).
1979	* @{ */
1980	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU8,(uint8_t pu8Dst, uint8_t cShift, uint32_t pEFlags));
1981	typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
1982	FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8, iemAImpl_rol_u8_amd, iemAImpl_rol_u8_intel;
1983	FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8, iemAImpl_ror_u8_amd, iemAImpl_ror_u8_intel;
1984	FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8, iemAImpl_rcl_u8_amd, iemAImpl_rcl_u8_intel;
1985	FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8, iemAImpl_rcr_u8_amd, iemAImpl_rcr_u8_intel;
1986	FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8, iemAImpl_shl_u8_amd, iemAImpl_shl_u8_intel;
1987	FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8, iemAImpl_shr_u8_amd, iemAImpl_shr_u8_intel;
1988	FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8, iemAImpl_sar_u8_amd, iemAImpl_sar_u8_intel;
1989	/** @} */
1990
1991	/** @name Shift operations on words (Group 2).
1992	* @{ */
1993	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU16,(uint16_t pu16Dst, uint8_t cShift, uint32_t pEFlags));
1994	typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
1995	FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16, iemAImpl_rol_u16_amd, iemAImpl_rol_u16_intel;
1996	FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16, iemAImpl_ror_u16_amd, iemAImpl_ror_u16_intel;
1997	FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16, iemAImpl_rcl_u16_amd, iemAImpl_rcl_u16_intel;
1998	FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16, iemAImpl_rcr_u16_amd, iemAImpl_rcr_u16_intel;
1999	FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16, iemAImpl_shl_u16_amd, iemAImpl_shl_u16_intel;
2000	FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16, iemAImpl_shr_u16_amd, iemAImpl_shr_u16_intel;
2001	FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16, iemAImpl_sar_u16_amd, iemAImpl_sar_u16_intel;
2002	/** @} */
2003
2004	/** @name Shift operations on double words (Group 2).
2005	* @{ */
2006	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU32,(uint32_t pu32Dst, uint8_t cShift, uint32_t pEFlags));
2007	typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
2008	FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32, iemAImpl_rol_u32_amd, iemAImpl_rol_u32_intel;
2009	FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32, iemAImpl_ror_u32_amd, iemAImpl_ror_u32_intel;
2010	FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32, iemAImpl_rcl_u32_amd, iemAImpl_rcl_u32_intel;
2011	FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32, iemAImpl_rcr_u32_amd, iemAImpl_rcr_u32_intel;
2012	FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32, iemAImpl_shl_u32_amd, iemAImpl_shl_u32_intel;
2013	FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32, iemAImpl_shr_u32_amd, iemAImpl_shr_u32_intel;
2014	FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32, iemAImpl_sar_u32_amd, iemAImpl_sar_u32_intel;
2015	/** @} */
2016
2017	/** @name Shift operations on words (Group 2).
2018	* @{ */
2019	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU64,(uint64_t pu64Dst, uint8_t cShift, uint32_t pEFlags));
2020	typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
2021	FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64, iemAImpl_rol_u64_amd, iemAImpl_rol_u64_intel;
2022	FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64, iemAImpl_ror_u64_amd, iemAImpl_ror_u64_intel;
2023	FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64, iemAImpl_rcl_u64_amd, iemAImpl_rcl_u64_intel;
2024	FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64, iemAImpl_rcr_u64_amd, iemAImpl_rcr_u64_intel;
2025	FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64, iemAImpl_shl_u64_amd, iemAImpl_shl_u64_intel;
2026	FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64, iemAImpl_shr_u64_amd, iemAImpl_shr_u64_intel;
2027	FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64, iemAImpl_sar_u64_amd, iemAImpl_sar_u64_intel;
2028	/** @} */
2029
2030	/** @name Multiplication and division operations.
2031	* @{ */
2032	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t pu16AX, uint8_t u8FactorDivisor, uint32_t pEFlags));
2033	typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
2034	FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_mul_u8_amd, iemAImpl_mul_u8_intel;
2035	FNIEMAIMPLMULDIVU8 iemAImpl_imul_u8, iemAImpl_imul_u8_amd, iemAImpl_imul_u8_intel;
2036	FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_div_u8_amd, iemAImpl_div_u8_intel;
2037	FNIEMAIMPLMULDIVU8 iemAImpl_idiv_u8, iemAImpl_idiv_u8_amd, iemAImpl_idiv_u8_intel;
2038
2039	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t pu16AX, uint16_t pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
2040	typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
2041	FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_mul_u16_amd, iemAImpl_mul_u16_intel;
2042	FNIEMAIMPLMULDIVU16 iemAImpl_imul_u16, iemAImpl_imul_u16_amd, iemAImpl_imul_u16_intel;
2043	FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_div_u16_amd, iemAImpl_div_u16_intel;
2044	FNIEMAIMPLMULDIVU16 iemAImpl_idiv_u16, iemAImpl_idiv_u16_amd, iemAImpl_idiv_u16_intel;
2045
2046	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t pu32EAX, uint32_t pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
2047	typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
2048	FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_mul_u32_amd, iemAImpl_mul_u32_intel;
2049	FNIEMAIMPLMULDIVU32 iemAImpl_imul_u32, iemAImpl_imul_u32_amd, iemAImpl_imul_u32_intel;
2050	FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_div_u32_amd, iemAImpl_div_u32_intel;
2051	FNIEMAIMPLMULDIVU32 iemAImpl_idiv_u32, iemAImpl_idiv_u32_amd, iemAImpl_idiv_u32_intel;
2052
2053	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t pu64RAX, uint64_t pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
2054	typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
2055	FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_mul_u64_amd, iemAImpl_mul_u64_intel;
2056	FNIEMAIMPLMULDIVU64 iemAImpl_imul_u64, iemAImpl_imul_u64_amd, iemAImpl_imul_u64_intel;
2057	FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_div_u64_amd, iemAImpl_div_u64_intel;
2058	FNIEMAIMPLMULDIVU64 iemAImpl_idiv_u64, iemAImpl_idiv_u64_amd, iemAImpl_idiv_u64_intel;
2059	/** @} */
2060
2061	/** @name Byte Swap.
2062	* @{ */
2063	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t pu32Dst)); / Yes, 32-bit register access. */
2064	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
2065	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
2066	/** @} */
2067
2068	/** @name Misc.
2069	* @{ */
2070	FNIEMAIMPLBINU16 iemAImpl_arpl;
2071	/** @} */
2072
2073	/** @name RDRAND and RDSEED
2074	* @{ */
2075	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU16,(uint16_t puDst, uint32_t pEFlags));
2076	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU32,(uint32_t puDst, uint32_t pEFlags));
2077	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU64,(uint64_t puDst, uint32_t pEFlags));
2078	typedef FNIEMAIMPLRDRANDSEEDU16 *FNIEMAIMPLPRDRANDSEEDU16;
2079	typedef FNIEMAIMPLRDRANDSEEDU32 *FNIEMAIMPLPRDRANDSEEDU32;
2080	typedef FNIEMAIMPLRDRANDSEEDU64 *FNIEMAIMPLPRDRANDSEEDU64;
2081
2082	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdrand_u16, iemAImpl_rdrand_u16_fallback;
2083	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdrand_u32, iemAImpl_rdrand_u32_fallback;
2084	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdrand_u64, iemAImpl_rdrand_u64_fallback;
2085	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdseed_u16, iemAImpl_rdseed_u16_fallback;
2086	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdseed_u32, iemAImpl_rdseed_u32_fallback;
2087	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdseed_u64, iemAImpl_rdseed_u64_fallback;
2088	/** @} */
2089
2090	/** @name ADOX and ADCX
2091	* @{ */
2092	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLADXU32,(uint32_t puDst, uint32_t pfEFlags, uint32_t uSrc));
2093	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLADXU64,(uint64_t puDst, uint32_t pfEFlags, uint64_t uSrc));
2094	typedef FNIEMAIMPLADXU32 *PFNIEMAIMPLADXU32;
2095	typedef FNIEMAIMPLADXU64 *PFNIEMAIMPLADXU64;
2096
2097	FNIEMAIMPLADXU32 iemAImpl_adcx_u32, iemAImpl_adcx_u32_fallback;
2098	FNIEMAIMPLADXU64 iemAImpl_adcx_u64, iemAImpl_adcx_u64_fallback;
2099	FNIEMAIMPLADXU32 iemAImpl_adox_u32, iemAImpl_adox_u32_fallback;
2100	FNIEMAIMPLADXU64 iemAImpl_adox_u64, iemAImpl_adox_u64_fallback;
2101	/** @} */
2102
2103	/** @name FPU operations taking a 32-bit float argument
2104	* @{ */
2105	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2106	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
2107	typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
2108
2109	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2110	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
2111	typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
2112
2113	FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
2114	FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
2115	FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
2116	FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
2117	FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
2118	FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
2119	FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
2120
2121	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
2122	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2123	PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
2124	/** @} */
2125
2126	/** @name FPU operations taking a 64-bit float argument
2127	* @{ */
2128	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2129	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
2130	typedef FNIEMAIMPLFPUR64FSW *PFNIEMAIMPLFPUR64FSW;
2131
2132	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2133	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
2134	typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
2135
2136	FNIEMAIMPLFPUR64FSW iemAImpl_fcom_r80_by_r64;
2137	FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
2138	FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
2139	FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
2140	FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
2141	FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
2142	FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
2143
2144	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
2145	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2146	PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
2147	/** @} */
2148
2149	/** @name FPU operations taking a 80-bit float argument
2150	* @{ */
2151	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2152	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
2153	typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
2154	FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
2155	FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
2156	FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
2157	FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
2158	FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
2159	FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
2160	FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
2161	FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
2162	FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
2163
2164	FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80, iemAImpl_fpatan_r80_by_r80_amd, iemAImpl_fpatan_r80_by_r80_intel;
2165	FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80, iemAImpl_fyl2x_r80_by_r80_amd, iemAImpl_fyl2x_r80_by_r80_intel;
2166	FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80, iemAImpl_fyl2xp1_r80_by_r80_amd, iemAImpl_fyl2xp1_r80_by_r80_intel;
2167
2168	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2169	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
2170	typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
2171	FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
2172	FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
2173
2174	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
2175	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
2176	typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
2177	FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
2178	FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
2179
2180	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
2181	typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
2182	FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
2183	FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
2184	FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80, iemAImpl_f2xm1_r80_amd, iemAImpl_f2xm1_r80_intel;
2185	FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
2186	FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
2187	FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80, iemAImpl_fsin_r80_amd, iemAImpl_fsin_r80_intel;
2188	FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80, iemAImpl_fcos_r80_amd, iemAImpl_fcos_r80_intel;
2189
2190	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
2191	typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
2192	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
2193	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
2194
2195	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
2196	typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
2197	FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
2198	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
2199	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
2200	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
2201	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
2202	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
2203	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
2204
2205	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
2206	PCRTFLOAT80U pr80Val));
2207	typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
2208	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80, iemAImpl_fptan_r80_r80_amd, iemAImpl_fptan_r80_r80_intel;
2209	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
2210	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80, iemAImpl_fsincos_r80_r80_amd, iemAImpl_fsincos_r80_r80_intel;
2211
2212	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
2213	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2214	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
2215
2216	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_d80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTPBCD80U pd80Val));
2217	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_d80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2218	PRTPBCD80U pd80Dst, PCRTFLOAT80U pr80Src));
2219
2220	/** @} */
2221
2222	/** @name FPU operations taking a 16-bit signed integer argument
2223	* @{ */
2224	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2225	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
2226	typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
2227	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI16,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
2228	int16_t *pi16Dst, PCRTFLOAT80U pr80Src));
2229	typedef FNIEMAIMPLFPUSTR80TOI16 *PFNIEMAIMPLFPUSTR80TOI16;
2230
2231	FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
2232	FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
2233	FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
2234	FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
2235	FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
2236	FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
2237
2238	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2239	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
2240	typedef FNIEMAIMPLFPUI16FSW *PFNIEMAIMPLFPUI16FSW;
2241	FNIEMAIMPLFPUI16FSW iemAImpl_ficom_r80_by_i16;
2242
2243	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
2244	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fist_r80_to_i16;
2245	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fistt_r80_to_i16, iemAImpl_fistt_r80_to_i16_amd, iemAImpl_fistt_r80_to_i16_intel;
2246	/** @} */
2247
2248	/** @name FPU operations taking a 32-bit signed integer argument
2249	* @{ */
2250	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2251	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
2252	typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
2253	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI32,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
2254	int32_t *pi32Dst, PCRTFLOAT80U pr80Src));
2255	typedef FNIEMAIMPLFPUSTR80TOI32 *PFNIEMAIMPLFPUSTR80TOI32;
2256
2257	FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
2258	FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
2259	FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
2260	FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
2261	FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
2262	FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
2263
2264	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2265	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
2266	typedef FNIEMAIMPLFPUI32FSW *PFNIEMAIMPLFPUI32FSW;
2267	FNIEMAIMPLFPUI32FSW iemAImpl_ficom_r80_by_i32;
2268
2269	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
2270	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fist_r80_to_i32;
2271	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fistt_r80_to_i32;
2272	/** @} */
2273
2274	/** @name FPU operations taking a 64-bit signed integer argument
2275	* @{ */
2276	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI64,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
2277	int64_t *pi64Dst, PCRTFLOAT80U pr80Src));
2278	typedef FNIEMAIMPLFPUSTR80TOI64 *PFNIEMAIMPLFPUSTR80TOI64;
2279
2280	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
2281	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fist_r80_to_i64;
2282	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fistt_r80_to_i64;
2283	/** @} */
2284
2285
2286	/** Temporary type representing a 256-bit vector register. */
2287	typedef struct { uint64_t au64[4]; } IEMVMM256;
2288	/** Temporary type pointing to a 256-bit vector register. */
2289	typedef IEMVMM256 *PIEMVMM256;
2290	/** Temporary type pointing to a const 256-bit vector register. */
2291	typedef IEMVMM256 *PCIEMVMM256;
2292
2293
2294	/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
2295	* @{ */
2296	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t puDst, uint64_t const puSrc));
2297	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
2298	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U128,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
2299	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
2300	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U128,(PX86XSAVEAREA pExtState, PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
2301	typedef FNIEMAIMPLMEDIAF3U128 *PFNIEMAIMPLMEDIAF3U128;
2302	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U256,(PX86XSAVEAREA pExtState, PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
2303	typedef FNIEMAIMPLMEDIAF3U256 *PFNIEMAIMPLMEDIAF3U256;
2304	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U64,(uint64_t puDst, uint64_t const puSrc));
2305	typedef FNIEMAIMPLMEDIAOPTF2U64 *PFNIEMAIMPLMEDIAOPTF2U64;
2306	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128,(PRTUINT128U puDst, PCRTUINT128U puSrc));
2307	typedef FNIEMAIMPLMEDIAOPTF2U128 *PFNIEMAIMPLMEDIAOPTF2U128;
2308	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
2309	typedef FNIEMAIMPLMEDIAOPTF3U128 *PFNIEMAIMPLMEDIAOPTF3U128;
2310	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
2311	typedef FNIEMAIMPLMEDIAOPTF3U256 *PFNIEMAIMPLMEDIAOPTF3U256;
2312	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256,(PRTUINT256U puDst, PCRTUINT256U puSrc));
2313	typedef FNIEMAIMPLMEDIAOPTF2U256 *PFNIEMAIMPLMEDIAOPTF2U256;
2314	FNIEMAIMPLMEDIAF2U64 iemAImpl_pshufb_u64, iemAImpl_pshufb_u64_fallback;
2315	FNIEMAIMPLMEDIAF2U64 iemAImpl_pand_u64, iemAImpl_pandn_u64, iemAImpl_por_u64, iemAImpl_pxor_u64;
2316	FNIEMAIMPLMEDIAF2U64 iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
2317	FNIEMAIMPLMEDIAF2U64 iemAImpl_pcmpgtb_u64, iemAImpl_pcmpgtw_u64, iemAImpl_pcmpgtd_u64;
2318	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddb_u64, iemAImpl_paddsb_u64, iemAImpl_paddusb_u64;
2319	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddw_u64, iemAImpl_paddsw_u64, iemAImpl_paddusw_u64;
2320	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddd_u64;
2321	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddq_u64;
2322	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubb_u64, iemAImpl_psubsb_u64, iemAImpl_psubusb_u64;
2323	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubw_u64, iemAImpl_psubsw_u64, iemAImpl_psubusw_u64;
2324	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubd_u64;
2325	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubq_u64;
2326	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmaddwd_u64;
2327	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmullw_u64, iemAImpl_pmulhw_u64;
2328	FNIEMAIMPLMEDIAF2U64 iemAImpl_pminub_u64, iemAImpl_pmaxub_u64;
2329	FNIEMAIMPLMEDIAF2U64 iemAImpl_pminsw_u64, iemAImpl_pmaxsw_u64;
2330	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsb_u64, iemAImpl_pabsb_u64_fallback;
2331	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsw_u64, iemAImpl_pabsw_u64_fallback;
2332	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsd_u64, iemAImpl_pabsd_u64_fallback;
2333	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignb_u64, iemAImpl_psignb_u64_fallback;
2334	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignw_u64, iemAImpl_psignw_u64_fallback;
2335	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignd_u64, iemAImpl_psignd_u64_fallback;
2336	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddw_u64, iemAImpl_phaddw_u64_fallback;
2337	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddd_u64, iemAImpl_phaddd_u64_fallback;
2338	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubw_u64, iemAImpl_phsubw_u64_fallback;
2339	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubd_u64, iemAImpl_phsubd_u64_fallback;
2340	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddsw_u64, iemAImpl_phaddsw_u64_fallback;
2341	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubsw_u64, iemAImpl_phsubsw_u64_fallback;
2342	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmaddubsw_u64, iemAImpl_pmaddubsw_u64_fallback;
2343	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmulhrsw_u64, iemAImpl_pmulhrsw_u64_fallback;
2344	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmuludq_u64;
2345	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllw_u64, iemAImpl_psrlw_u64, iemAImpl_psraw_u64;
2346	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pslld_u64, iemAImpl_psrld_u64, iemAImpl_psrad_u64;
2347	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllq_u64, iemAImpl_psrlq_u64;
2348	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packsswb_u64, iemAImpl_packuswb_u64;
2349	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packssdw_u64;
2350	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhuw_u64;
2351	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pavgb_u64, iemAImpl_pavgw_u64;
2352	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psadbw_u64;
2353
2354	FNIEMAIMPLMEDIAF2U128 iemAImpl_pshufb_u128, iemAImpl_pshufb_u128_fallback;
2355	FNIEMAIMPLMEDIAF2U128 iemAImpl_pand_u128, iemAImpl_pandn_u128, iemAImpl_por_u128, iemAImpl_pxor_u128;
2356	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
2357	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpeqq_u128, iemAImpl_pcmpeqq_u128_fallback;
2358	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpgtb_u128, iemAImpl_pcmpgtw_u128, iemAImpl_pcmpgtd_u128;
2359	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpgtq_u128, iemAImpl_pcmpgtq_u128_fallback;
2360	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddb_u128, iemAImpl_paddsb_u128, iemAImpl_paddusb_u128;
2361	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddw_u128, iemAImpl_paddsw_u128, iemAImpl_paddusw_u128;
2362	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddd_u128;
2363	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddq_u128;
2364	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubb_u128, iemAImpl_psubsb_u128, iemAImpl_psubusb_u128;
2365	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubw_u128, iemAImpl_psubsw_u128, iemAImpl_psubusw_u128;
2366	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubd_u128;
2367	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubq_u128;
2368	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmullw_u128, iemAImpl_pmullw_u128_fallback;
2369	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulhw_u128;
2370	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulld_u128, iemAImpl_pmulld_u128_fallback;
2371	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaddwd_u128;
2372	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminub_u128;
2373	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminud_u128, iemAImpl_pminud_u128_fallback;
2374	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminuw_u128, iemAImpl_pminuw_u128_fallback;
2375	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsb_u128, iemAImpl_pminsb_u128_fallback;
2376	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsd_u128, iemAImpl_pminsd_u128_fallback;
2377	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsw_u128, iemAImpl_pminsw_u128_fallback;
2378	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxub_u128;
2379	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxud_u128, iemAImpl_pmaxud_u128_fallback;
2380	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxuw_u128, iemAImpl_pmaxuw_u128_fallback;
2381	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsb_u128, iemAImpl_pmaxsb_u128_fallback;
2382	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsw_u128;
2383	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsd_u128, iemAImpl_pmaxsd_u128_fallback;
2384	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsb_u128, iemAImpl_pabsb_u128_fallback;
2385	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsw_u128, iemAImpl_pabsw_u128_fallback;
2386	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsd_u128, iemAImpl_pabsd_u128_fallback;
2387	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignb_u128, iemAImpl_psignb_u128_fallback;
2388	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignw_u128, iemAImpl_psignw_u128_fallback;
2389	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignd_u128, iemAImpl_psignd_u128_fallback;
2390	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddw_u128, iemAImpl_phaddw_u128_fallback;
2391	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddd_u128, iemAImpl_phaddd_u128_fallback;
2392	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubw_u128, iemAImpl_phsubw_u128_fallback;
2393	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubd_u128, iemAImpl_phsubd_u128_fallback;
2394	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddsw_u128, iemAImpl_phaddsw_u128_fallback;
2395	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubsw_u128, iemAImpl_phsubsw_u128_fallback;
2396	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaddubsw_u128, iemAImpl_pmaddubsw_u128_fallback;
2397	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulhrsw_u128, iemAImpl_pmulhrsw_u128_fallback;
2398	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmuludq_u128;
2399	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packsswb_u128, iemAImpl_packuswb_u128;
2400	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packssdw_u128, iemAImpl_packusdw_u128;
2401	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllw_u128, iemAImpl_psrlw_u128, iemAImpl_psraw_u128;
2402	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pslld_u128, iemAImpl_psrld_u128, iemAImpl_psrad_u128;
2403	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllq_u128, iemAImpl_psrlq_u128;
2404	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhuw_u128;
2405	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pavgb_u128, iemAImpl_pavgw_u128;
2406	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psadbw_u128;
2407	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuldq_u128, iemAImpl_pmuldq_u128_fallback;
2408	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpcklps_u128, iemAImpl_unpcklpd_u128;
2409	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpckhps_u128, iemAImpl_unpckhpd_u128;
2410	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phminposuw_u128, iemAImpl_phminposuw_u128_fallback;
2411
2412	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpshufb_u128, iemAImpl_vpshufb_u128_fallback;
2413	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpand_u128, iemAImpl_vpand_u128_fallback;
2414	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpandn_u128, iemAImpl_vpandn_u128_fallback;
2415	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpor_u128, iemAImpl_vpor_u128_fallback;
2416	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpxor_u128, iemAImpl_vpxor_u128_fallback;
2417	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqb_u128, iemAImpl_vpcmpeqb_u128_fallback;
2418	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqw_u128, iemAImpl_vpcmpeqw_u128_fallback;
2419	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqd_u128, iemAImpl_vpcmpeqd_u128_fallback;
2420	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqq_u128, iemAImpl_vpcmpeqq_u128_fallback;
2421	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtb_u128, iemAImpl_vpcmpgtb_u128_fallback;
2422	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtw_u128, iemAImpl_vpcmpgtw_u128_fallback;
2423	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtd_u128, iemAImpl_vpcmpgtd_u128_fallback;
2424	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtq_u128, iemAImpl_vpcmpgtq_u128_fallback;
2425	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddb_u128, iemAImpl_vpaddb_u128_fallback;
2426	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddw_u128, iemAImpl_vpaddw_u128_fallback;
2427	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddd_u128, iemAImpl_vpaddd_u128_fallback;
2428	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddq_u128, iemAImpl_vpaddq_u128_fallback;
2429	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubb_u128, iemAImpl_vpsubb_u128_fallback;
2430	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubw_u128, iemAImpl_vpsubw_u128_fallback;
2431	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubd_u128, iemAImpl_vpsubd_u128_fallback;
2432	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubq_u128, iemAImpl_vpsubq_u128_fallback;
2433	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminub_u128, iemAImpl_vpminub_u128_fallback;
2434	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminuw_u128, iemAImpl_vpminuw_u128_fallback;
2435	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminud_u128, iemAImpl_vpminud_u128_fallback;
2436	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsb_u128, iemAImpl_vpminsb_u128_fallback;
2437	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsw_u128, iemAImpl_vpminsw_u128_fallback;
2438	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsd_u128, iemAImpl_vpminsd_u128_fallback;
2439	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxub_u128, iemAImpl_vpmaxub_u128_fallback;
2440	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxuw_u128, iemAImpl_vpmaxuw_u128_fallback;
2441	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxud_u128, iemAImpl_vpmaxud_u128_fallback;
2442	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsb_u128, iemAImpl_vpmaxsb_u128_fallback;
2443	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsw_u128, iemAImpl_vpmaxsw_u128_fallback;
2444	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsd_u128, iemAImpl_vpmaxsd_u128_fallback;
2445	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpacksswb_u128, iemAImpl_vpacksswb_u128_fallback;
2446	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackssdw_u128, iemAImpl_vpackssdw_u128_fallback;
2447	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackuswb_u128, iemAImpl_vpackuswb_u128_fallback;
2448	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackusdw_u128, iemAImpl_vpackusdw_u128_fallback;
2449	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmullw_u128, iemAImpl_vpmullw_u128_fallback;
2450	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulld_u128, iemAImpl_vpmulld_u128_fallback;
2451	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhw_u128, iemAImpl_vpmulhw_u128_fallback;
2452	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhuw_u128, iemAImpl_vpmulhuw_u128_fallback;
2453	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgb_u128, iemAImpl_vpavgb_u128_fallback;
2454	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgw_u128, iemAImpl_vpavgw_u128_fallback;
2455	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignb_u128, iemAImpl_vpsignb_u128_fallback;
2456	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignw_u128, iemAImpl_vpsignw_u128_fallback;
2457	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignd_u128, iemAImpl_vpsignd_u128_fallback;
2458	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddw_u128, iemAImpl_vphaddw_u128_fallback;
2459	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddd_u128, iemAImpl_vphaddd_u128_fallback;
2460	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubw_u128, iemAImpl_vphsubw_u128_fallback;
2461	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubd_u128, iemAImpl_vphsubd_u128_fallback;
2462	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddsw_u128, iemAImpl_vphaddsw_u128_fallback;
2463	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubsw_u128, iemAImpl_vphsubsw_u128_fallback;
2464	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddubsw_u128, iemAImpl_vpmaddubsw_u128_fallback;
2465	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhrsw_u128, iemAImpl_vpmulhrsw_u128_fallback;
2466	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsadbw_u128, iemAImpl_vpsadbw_u128_fallback;
2467	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuldq_u128, iemAImpl_vpmuldq_u128_fallback;
2468	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuludq_u128, iemAImpl_vpmuludq_u128_fallback;
2469	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsb_u128, iemAImpl_vpsubsb_u128_fallback;
2470	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsw_u128, iemAImpl_vpsubsw_u128_fallback;
2471	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusb_u128, iemAImpl_vpsubusb_u128_fallback;
2472	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusw_u128, iemAImpl_vpsubusw_u128_fallback;
2473	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusb_u128, iemAImpl_vpaddusb_u128_fallback;
2474	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusw_u128, iemAImpl_vpaddusw_u128_fallback;
2475	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsb_u128, iemAImpl_vpaddsb_u128_fallback;
2476	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsw_u128, iemAImpl_vpaddsw_u128_fallback;
2477
2478	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsb_u128, iemAImpl_vpabsb_u128_fallback;
2479	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsw_u128, iemAImpl_vpabsd_u128_fallback;
2480	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsd_u128, iemAImpl_vpabsw_u128_fallback;
2481	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vphminposuw_u128, iemAImpl_vphminposuw_u128_fallback;
2482
2483	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpshufb_u256, iemAImpl_vpshufb_u256_fallback;
2484	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpand_u256, iemAImpl_vpand_u256_fallback;
2485	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpandn_u256, iemAImpl_vpandn_u256_fallback;
2486	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpor_u256, iemAImpl_vpor_u256_fallback;
2487	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpxor_u256, iemAImpl_vpxor_u256_fallback;
2488	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqb_u256, iemAImpl_vpcmpeqb_u256_fallback;
2489	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqw_u256, iemAImpl_vpcmpeqw_u256_fallback;
2490	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqd_u256, iemAImpl_vpcmpeqd_u256_fallback;
2491	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqq_u256, iemAImpl_vpcmpeqq_u256_fallback;
2492	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtb_u256, iemAImpl_vpcmpgtb_u256_fallback;
2493	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtw_u256, iemAImpl_vpcmpgtw_u256_fallback;
2494	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtd_u256, iemAImpl_vpcmpgtd_u256_fallback;
2495	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtq_u256, iemAImpl_vpcmpgtq_u256_fallback;
2496	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddb_u256, iemAImpl_vpaddb_u256_fallback;
2497	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddw_u256, iemAImpl_vpaddw_u256_fallback;
2498	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddd_u256, iemAImpl_vpaddd_u256_fallback;
2499	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddq_u256, iemAImpl_vpaddq_u256_fallback;
2500	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubb_u256, iemAImpl_vpsubb_u256_fallback;
2501	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubw_u256, iemAImpl_vpsubw_u256_fallback;
2502	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubd_u256, iemAImpl_vpsubd_u256_fallback;
2503	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubq_u256, iemAImpl_vpsubq_u256_fallback;
2504	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminub_u256, iemAImpl_vpminub_u256_fallback;
2505	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminuw_u256, iemAImpl_vpminuw_u256_fallback;
2506	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminud_u256, iemAImpl_vpminud_u256_fallback;
2507	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsb_u256, iemAImpl_vpminsb_u256_fallback;
2508	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsw_u256, iemAImpl_vpminsw_u256_fallback;
2509	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsd_u256, iemAImpl_vpminsd_u256_fallback;
2510	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxub_u256, iemAImpl_vpmaxub_u256_fallback;
2511	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxuw_u256, iemAImpl_vpmaxuw_u256_fallback;
2512	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxud_u256, iemAImpl_vpmaxud_u256_fallback;
2513	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsb_u256, iemAImpl_vpmaxsb_u256_fallback;
2514	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsw_u256, iemAImpl_vpmaxsw_u256_fallback;
2515	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsd_u256, iemAImpl_vpmaxsd_u256_fallback;
2516	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpacksswb_u256, iemAImpl_vpacksswb_u256_fallback;
2517	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackssdw_u256, iemAImpl_vpackssdw_u256_fallback;
2518	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackuswb_u256, iemAImpl_vpackuswb_u256_fallback;
2519	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackusdw_u256, iemAImpl_vpackusdw_u256_fallback;
2520	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmullw_u256, iemAImpl_vpmullw_u256_fallback;
2521	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulld_u256, iemAImpl_vpmulld_u256_fallback;
2522	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhw_u256, iemAImpl_vpmulhw_u256_fallback;
2523	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhuw_u256, iemAImpl_vpmulhuw_u256_fallback;
2524	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgb_u256, iemAImpl_vpavgb_u256_fallback;
2525	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgw_u256, iemAImpl_vpavgw_u256_fallback;
2526	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignb_u256, iemAImpl_vpsignb_u256_fallback;
2527	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignw_u256, iemAImpl_vpsignw_u256_fallback;
2528	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignd_u256, iemAImpl_vpsignd_u256_fallback;
2529	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddw_u256, iemAImpl_vphaddw_u256_fallback;
2530	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddd_u256, iemAImpl_vphaddd_u256_fallback;
2531	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubw_u256, iemAImpl_vphsubw_u256_fallback;
2532	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubd_u256, iemAImpl_vphsubd_u256_fallback;
2533	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddsw_u256, iemAImpl_vphaddsw_u256_fallback;
2534	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubsw_u256, iemAImpl_vphsubsw_u256_fallback;
2535	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddubsw_u256, iemAImpl_vpmaddubsw_u256_fallback;
2536	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhrsw_u256, iemAImpl_vpmulhrsw_u256_fallback;
2537	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsadbw_u256, iemAImpl_vpsadbw_u256_fallback;
2538	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuldq_u256, iemAImpl_vpmuldq_u256_fallback;
2539	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuludq_u256, iemAImpl_vpmuludq_u256_fallback;
2540	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsb_u256, iemAImpl_vpsubsb_u256_fallback;
2541	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsw_u256, iemAImpl_vpsubsw_u256_fallback;
2542	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusb_u256, iemAImpl_vpsubusb_u256_fallback;
2543	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusw_u256, iemAImpl_vpsubusw_u256_fallback;
2544	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusb_u256, iemAImpl_vpaddusb_u256_fallback;
2545	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusw_u256, iemAImpl_vpaddusw_u256_fallback;
2546	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsb_u256, iemAImpl_vpaddsb_u256_fallback;
2547	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsw_u256, iemAImpl_vpaddsw_u256_fallback;
2548
2549	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsb_u256, iemAImpl_vpabsb_u256_fallback;
2550	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsw_u256, iemAImpl_vpabsw_u256_fallback;
2551	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsd_u256, iemAImpl_vpabsd_u256_fallback;
2552	/** @} */
2553
2554	/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
2555	* @{ */
2556	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
2557	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
2558	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpcklbw_u128, iemAImpl_vpunpcklbw_u128_fallback,
2559	iemAImpl_vpunpcklwd_u128, iemAImpl_vpunpcklwd_u128_fallback,
2560	iemAImpl_vpunpckldq_u128, iemAImpl_vpunpckldq_u128_fallback,
2561	iemAImpl_vpunpcklqdq_u128, iemAImpl_vpunpcklqdq_u128_fallback,
2562	iemAImpl_vunpcklps_u128, iemAImpl_vunpcklps_u128_fallback,
2563	iemAImpl_vunpcklpd_u128, iemAImpl_vunpcklpd_u128_fallback,
2564	iemAImpl_vunpckhps_u128, iemAImpl_vunpckhps_u128_fallback,
2565	iemAImpl_vunpckhpd_u128, iemAImpl_vunpckhpd_u128_fallback;
2566
2567	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpcklbw_u256, iemAImpl_vpunpcklbw_u256_fallback,
2568	iemAImpl_vpunpcklwd_u256, iemAImpl_vpunpcklwd_u256_fallback,
2569	iemAImpl_vpunpckldq_u256, iemAImpl_vpunpckldq_u256_fallback,
2570	iemAImpl_vpunpcklqdq_u256, iemAImpl_vpunpcklqdq_u256_fallback,
2571	iemAImpl_vunpcklps_u256, iemAImpl_vunpcklps_u256_fallback,
2572	iemAImpl_vunpcklpd_u256, iemAImpl_vunpcklpd_u256_fallback,
2573	iemAImpl_vunpckhps_u256, iemAImpl_vunpckhps_u256_fallback,
2574	iemAImpl_vunpckhpd_u256, iemAImpl_vunpckhpd_u256_fallback;
2575	/** @} */
2576
2577	/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
2578	* @{ */
2579	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
2580	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
2581	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpckhbw_u128, iemAImpl_vpunpckhbw_u128_fallback,
2582	iemAImpl_vpunpckhwd_u128, iemAImpl_vpunpckhwd_u128_fallback,
2583	iemAImpl_vpunpckhdq_u128, iemAImpl_vpunpckhdq_u128_fallback,
2584	iemAImpl_vpunpckhqdq_u128, iemAImpl_vpunpckhqdq_u128_fallback;
2585	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpckhbw_u256, iemAImpl_vpunpckhbw_u256_fallback,
2586	iemAImpl_vpunpckhwd_u256, iemAImpl_vpunpckhwd_u256_fallback,
2587	iemAImpl_vpunpckhdq_u256, iemAImpl_vpunpckhdq_u256_fallback,
2588	iemAImpl_vpunpckhqdq_u256, iemAImpl_vpunpckhqdq_u256_fallback;
2589	/** @} */
2590
2591	/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
2592	* @{ */
2593	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2594	typedef FNIEMAIMPLMEDIAPSHUFU128 *PFNIEMAIMPLMEDIAPSHUFU128;
2595	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
2596	typedef FNIEMAIMPLMEDIAPSHUFU256 *PFNIEMAIMPLMEDIAPSHUFU256;
2597	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw_u64,(uint64_t puDst, uint64_t const puSrc, uint8_t bEvil));
2598	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_pshufhw_u128, iemAImpl_pshuflw_u128, iemAImpl_pshufd_u128;
2599	#ifndef IEM_WITHOUT_ASSEMBLY
2600	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256, iemAImpl_vpshuflw_u256, iemAImpl_vpshufd_u256;
2601	#endif
2602	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256_fallback, iemAImpl_vpshuflw_u256_fallback, iemAImpl_vpshufd_u256_fallback;
2603	/** @} */
2604
2605	/** @name Media (SSE/MMX/AVX) operation: Shift Immediate Stuff (evil)
2606	* @{ */
2607	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU64,(uint64_t *puDst, uint8_t bShift));
2608	typedef FNIEMAIMPLMEDIAPSHIFTU64 *PFNIEMAIMPLMEDIAPSHIFTU64;
2609	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU128,(PRTUINT128U puDst, uint8_t bShift));
2610	typedef FNIEMAIMPLMEDIAPSHIFTU128 *PFNIEMAIMPLMEDIAPSHIFTU128;
2611	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU256,(PRTUINT256U puDst, uint8_t bShift));
2612	typedef FNIEMAIMPLMEDIAPSHIFTU256 *PFNIEMAIMPLMEDIAPSHIFTU256;
2613	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psllw_imm_u64, iemAImpl_pslld_imm_u64, iemAImpl_psllq_imm_u64;
2614	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psrlw_imm_u64, iemAImpl_psrld_imm_u64, iemAImpl_psrlq_imm_u64;
2615	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psraw_imm_u64, iemAImpl_psrad_imm_u64;
2616	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psllw_imm_u128, iemAImpl_pslld_imm_u128, iemAImpl_psllq_imm_u128;
2617	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psrlw_imm_u128, iemAImpl_psrld_imm_u128, iemAImpl_psrlq_imm_u128;
2618	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psraw_imm_u128, iemAImpl_psrad_imm_u128;
2619	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_pslldq_imm_u128, iemAImpl_psrldq_imm_u128;
2620	/** @} */
2621
2622	/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
2623	* @{ */
2624	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(uint64_t pu64Dst, uint64_t const puSrc));
2625	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(uint64_t *pu64Dst, PCRTUINT128U puSrc));
2626	#ifndef IEM_WITHOUT_ASSEMBLY
2627	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
2628	#endif
2629	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256_fallback,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
2630	/** @} */
2631
2632	/** @name Media (SSE/MMX/AVX) operations: Variable Blend Packed Bytes/R32/R64.
2633	* @{ */
2634	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puMask));
2635	typedef FNIEMAIMPLBLENDU128 *PFNIEMAIMPLBLENDU128;
2636	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, PCRTUINT128U puMask));
2637	typedef FNIEMAIMPLAVXBLENDU128 *PFNIEMAIMPLAVXBLENDU128;
2638	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, PCRTUINT256U puMask));
2639	typedef FNIEMAIMPLAVXBLENDU256 *PFNIEMAIMPLAVXBLENDU256;
2640
2641	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128;
2642	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128_fallback;
2643	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128;
2644	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128_fallback;
2645	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256;
2646	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256_fallback;
2647
2648	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128;
2649	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128_fallback;
2650	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128;
2651	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128_fallback;
2652	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256;
2653	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256_fallback;
2654
2655	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128;
2656	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128_fallback;
2657	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128;
2658	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128_fallback;
2659	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256;
2660	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256_fallback;
2661	/** @} */
2662
2663
2664	/** @name Media (SSE/MMX/AVX) operation: Sort this later
2665	* @{ */
2666	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
2667	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
2668	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovshdup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
2669	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovshdup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
2670	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
2671	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
2672
2673	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2674	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2675	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2676	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2677	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2678
2679	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2680	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2681	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2682	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2683	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2684
2685	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2686	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2687	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
2688	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2689	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2690
2691	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2692	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2693	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2694	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2695	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2696
2697	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2698	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2699	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2700	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2701	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2702
2703	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2704	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2705	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2706	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2707	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2708
2709	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2710	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2711	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2712	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2713	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2714
2715	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2716	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2717	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2718	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2719	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2720
2721	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2722	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2723	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
2724	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2725	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2726
2727	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2728	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2729	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2730	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2731	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2732
2733	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2734	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2735	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2736	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2737	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2738
2739	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2740	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2741	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2742	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2743	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2744
2745	IEM_DECL_IMPL_DEF(void, iemAImpl_shufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2746	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2747	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2748	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2749	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2750
2751	IEM_DECL_IMPL_DEF(void, iemAImpl_shufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2752	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2753	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2754	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2755	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2756
2757	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
2758	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64_fallback,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
2759
2760	IEM_DECL_IMPL_DEF(void, iemAImpl_pinsrw_u64,(uint64_t *pu64Dst, uint16_t u16Src, uint8_t bEvil));
2761	IEM_DECL_IMPL_DEF(void, iemAImpl_pinsrw_u128,(PRTUINT128U puDst, uint16_t u16Src, uint8_t bEvil));
2762	IEM_DECL_IMPL_DEF(void, iemAImpl_vpinsrw_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint16_t u16Src, uint8_t bEvil));
2763	IEM_DECL_IMPL_DEF(void, iemAImpl_vpinsrw_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint16_t u16Src, uint8_t bEvil));
2764
2765	IEM_DECL_IMPL_DEF(void, iemAImpl_pextrw_u64,(uint16_t *pu16Dst, uint64_t u64Src, uint8_t bEvil));
2766	IEM_DECL_IMPL_DEF(void, iemAImpl_pextrw_u128,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
2767	IEM_DECL_IMPL_DEF(void, iemAImpl_vpextrw_u128,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
2768	IEM_DECL_IMPL_DEF(void, iemAImpl_vpextrw_u128_fallback,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
2769
2770	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2771	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2772	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2773	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
2774	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
2775
2776	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2777	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2778	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2779	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
2780	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
2781
2782
2783	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2784	typedef FNIEMAIMPLMEDIAOPTF2U128IMM8 *PFNIEMAIMPLMEDIAOPTF2U128IMM8;
2785	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2786	typedef FNIEMAIMPLMEDIAOPTF3U128IMM8 *PFNIEMAIMPLMEDIAOPTF3U128IMM8;
2787	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2788	typedef FNIEMAIMPLMEDIAOPTF3U256IMM8 *PFNIEMAIMPLMEDIAOPTF3U256IMM8;
2789
2790	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_palignr_u128, iemAImpl_palignr_u128_fallback;
2791	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pblendw_u128, iemAImpl_pblendw_u128_fallback;
2792	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendps_u128, iemAImpl_blendps_u128_fallback;
2793	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendpd_u128, iemAImpl_blendpd_u128_fallback;
2794
2795	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpalignr_u128, iemAImpl_vpalignr_u128_fallback;
2796	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendw_u128, iemAImpl_vpblendw_u128_fallback;
2797	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendps_u128, iemAImpl_vblendps_u128_fallback;
2798	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendpd_u128, iemAImpl_vblendpd_u128_fallback;
2799
2800	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpalignr_u256, iemAImpl_vpalignr_u256_fallback;
2801	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendw_u256, iemAImpl_vpblendw_u256_fallback;
2802	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendps_u256, iemAImpl_vblendps_u256_fallback;
2803	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendpd_u256, iemAImpl_vblendpd_u256_fallback;
2804	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2i128_u256, iemAImpl_vperm2i128_u256_fallback;
2805	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2f128_u256, iemAImpl_vperm2f128_u256_fallback;
2806
2807	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesimc_u128, iemAImpl_aesimc_u128_fallback;
2808	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenc_u128, iemAImpl_aesenc_u128_fallback;
2809	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenclast_u128, iemAImpl_aesenclast_u128_fallback;
2810	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdec_u128, iemAImpl_aesdec_u128_fallback;
2811	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdeclast_u128, iemAImpl_aesdeclast_u128_fallback;
2812
2813	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesimc_u128, iemAImpl_vaesimc_u128_fallback;
2814	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenc_u128, iemAImpl_vaesenc_u128_fallback;
2815	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenclast_u128, iemAImpl_vaesenclast_u128_fallback;
2816	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdec_u128, iemAImpl_vaesdec_u128_fallback;
2817	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdeclast_u128, iemAImpl_vaesdeclast_u128_fallback;
2818
2819	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_aeskeygenassist_u128, iemAImpl_aeskeygenassist_u128_fallback;
2820
2821	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vaeskeygenassist_u128, iemAImpl_vaeskeygenassist_u128_fallback;
2822
2823	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1nexte_u128, iemAImpl_sha1nexte_u128_fallback;
2824	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg1_u128, iemAImpl_sha1msg1_u128_fallback;
2825	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg2_u128, iemAImpl_sha1msg2_u128_fallback;
2826	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg1_u128, iemAImpl_sha256msg1_u128_fallback;
2827	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg2_u128, iemAImpl_sha256msg2_u128_fallback;
2828	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_sha1rnds4_u128, iemAImpl_sha1rnds4_u128_fallback;
2829	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
2830	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
2831
2832	typedef struct IEMPCMPISTRXSRC
2833	{
2834	RTUINT128U uSrc1;
2835	RTUINT128U uSrc2;
2836	} IEMPCMPISTRXSRC;
2837	typedef IEMPCMPISTRXSRC *PIEMPCMPISTRXSRC;
2838	typedef const IEMPCMPISTRXSRC *PCIEMPCMPISTRXSRC;
2839
2840	typedef struct IEMPCMPESTRXSRC
2841	{
2842	RTUINT128U uSrc1;
2843	RTUINT128U uSrc2;
2844	uint64_t u64Rax;
2845	uint64_t u64Rdx;
2846	} IEMPCMPESTRXSRC;
2847	typedef IEMPCMPESTRXSRC *PIEMPCMPESTRXSRC;
2848	typedef const IEMPCMPESTRXSRC *PCIEMPCMPESTRXSRC;
2849
2850	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPISTRIU128IMM8,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
2851	typedef FNIEMAIMPLPCMPISTRIU128IMM8 *PFNIEMAIMPLPCMPISTRIU128IMM8;
2852	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRIU128IMM8,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
2853	typedef FNIEMAIMPLPCMPESTRIU128IMM8 *PFNIEMAIMPLPCMPESTRIU128IMM8;
2854
2855	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPISTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
2856	typedef FNIEMAIMPLPCMPISTRMU128IMM8 *PFNIEMAIMPLPCMPISTRMU128IMM8;
2857	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
2858	typedef FNIEMAIMPLPCMPESTRMU128IMM8 *PFNIEMAIMPLPCMPESTRMU128IMM8;
2859
2860	FNIEMAIMPLPCMPISTRIU128IMM8 iemAImpl_pcmpistri_u128, iemAImpl_pcmpistri_u128_fallback;
2861	FNIEMAIMPLPCMPESTRIU128IMM8 iemAImpl_pcmpestri_u128, iemAImpl_pcmpestri_u128_fallback;
2862	FNIEMAIMPLPCMPISTRMU128IMM8 iemAImpl_pcmpistrm_u128, iemAImpl_pcmpistrm_u128_fallback;
2863	FNIEMAIMPLPCMPESTRMU128IMM8 iemAImpl_pcmpestrm_u128, iemAImpl_pcmpestrm_u128_fallback;
2864
2865	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pclmulqdq_u128, iemAImpl_pclmulqdq_u128_fallback;
2866	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpclmulqdq_u128, iemAImpl_vpclmulqdq_u128_fallback;
2867
2868	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_mpsadbw_u128, iemAImpl_mpsadbw_u128_fallback;
2869	/** @} */
2870
2871	/** @name Media Odds and Ends
2872	* @{ */
2873	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U8,(uint32_t *puDst, uint8_t uSrc));
2874	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U16,(uint32_t *puDst, uint16_t uSrc));
2875	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U32,(uint32_t *puDst, uint32_t uSrc));
2876	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U64,(uint32_t *puDst, uint64_t uSrc));
2877	FNIEMAIMPLCR32U8 iemAImpl_crc32_u8, iemAImpl_crc32_u8_fallback;
2878	FNIEMAIMPLCR32U16 iemAImpl_crc32_u16, iemAImpl_crc32_u16_fallback;
2879	FNIEMAIMPLCR32U32 iemAImpl_crc32_u32, iemAImpl_crc32_u32_fallback;
2880	FNIEMAIMPLCR32U64 iemAImpl_crc32_u64, iemAImpl_crc32_u64_fallback;
2881
2882	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL128,(PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint32_t *pEFlags));
2883	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL256,(PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint32_t *pEFlags));
2884	FNIEMAIMPLF2EFL128 iemAImpl_ptest_u128;
2885	FNIEMAIMPLF2EFL256 iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback;
2886
2887	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I32U64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int32_t pi32Dst, const uint64_t pu64Src)); / pu64Src is a double precision floating point. */
2888	typedef FNIEMAIMPLSSEF2I32U64 *PFNIEMAIMPLSSEF2I32U64;
2889	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I64U64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int64_t pi64Dst, const uint64_t pu64Src)); / pu64Src is a double precision floating point. */
2890	typedef FNIEMAIMPLSSEF2I64U64 *PFNIEMAIMPLSSEF2I64U64;
2891	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I32U32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int32_t pi32Dst, const uint32_t pu32Src)); / pu32Src is a single precision floating point. */
2892	typedef FNIEMAIMPLSSEF2I32U32 *PFNIEMAIMPLSSEF2I32U32;
2893	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I64U32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int64_t pi64Dst, const uint32_t pu32Src)); / pu32Src is a single precision floating point. */
2894	typedef FNIEMAIMPLSSEF2I64U32 *PFNIEMAIMPLSSEF2I64U32;
2895
2896	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvttsd2si_i32_r64;
2897	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvtsd2si_i32_r64;
2898
2899	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvttsd2si_i64_r64;
2900	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvtsd2si_i64_r64;
2901
2902	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvttss2si_i32_r32;
2903	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvtss2si_i32_r32;
2904
2905	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvttss2si_i64_r32;
2906	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvtss2si_i64_r32;
2907
2908	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R32I32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT32U pr32Dst, const int32_t pi32Src));
2909	typedef FNIEMAIMPLSSEF2R32I32 *PFNIEMAIMPLSSEF2R32I32;
2910	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R32I64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT32U pr32Dst, const int64_t pi64Src));
2911	typedef FNIEMAIMPLSSEF2R32I64 *PFNIEMAIMPLSSEF2R32I64;
2912
2913	FNIEMAIMPLSSEF2R32I32 iemAImpl_cvtsi2ss_r32_i32;
2914	FNIEMAIMPLSSEF2R32I64 iemAImpl_cvtsi2ss_r32_i64;
2915
2916	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R64I32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT64U pr64Dst, const int32_t pi32Src));
2917	typedef FNIEMAIMPLSSEF2R64I32 *PFNIEMAIMPLSSEF2R64I32;
2918	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R64I64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT64U pr64Dst, const int64_t pi64Src));
2919	typedef FNIEMAIMPLSSEF2R64I64 *PFNIEMAIMPLSSEF2R64I64;
2920
2921	FNIEMAIMPLSSEF2R64I32 iemAImpl_cvtsi2sd_r64_i32;
2922	FNIEMAIMPLSSEF2R64I64 iemAImpl_cvtsi2sd_r64_i64;
2923
2924
2925	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFLMXCSR128,(uint32_t pfMxcsr, uint32_t pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
2926	typedef FNIEMAIMPLF2EFLMXCSR128 *PFNIEMAIMPLF2EFLMXCSR128;
2927
2928	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_ucomiss_u128;
2929	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback;
2930
2931	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_ucomisd_u128;
2932	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback;
2933
2934	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_comiss_u128;
2935	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback;
2936
2937	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_comisd_u128;
2938	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback;
2939
2940
2941	typedef struct IEMMEDIAF2XMMSRC
2942	{
2943	X86XMMREG uSrc1;
2944	X86XMMREG uSrc2;
2945	} IEMMEDIAF2XMMSRC;
2946	typedef IEMMEDIAF2XMMSRC *PIEMMEDIAF2XMMSRC;
2947	typedef const IEMMEDIAF2XMMSRC *PCIEMMEDIAF2XMMSRC;
2948
2949	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRF2XMMIMM8,(uint32_t *pfMxcsr, PX86XMMREG puDst, PCIEMMEDIAF2XMMSRC puSrc, uint8_t bEvil));
2950	typedef FNIEMAIMPLMXCSRF2XMMIMM8 *PFNIEMAIMPLMXCSRF2XMMIMM8;
2951
2952	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpps_u128;
2953	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmppd_u128;
2954	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpss_u128;
2955	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpsd_u128;
2956	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundss_u128;
2957	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundsd_u128;
2958
2959	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundps_u128, iemAImpl_roundps_u128_fallback;
2960	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundpd_u128, iemAImpl_roundpd_u128_fallback;
2961
2962	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_dpps_u128, iemAImpl_dpps_u128_fallback;
2963	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_dppd_u128, iemAImpl_dppd_u128_fallback;
2964
2965	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU64U128,(uint32_t pfMxcsr, uint64_t pu64Dst, PCX86XMMREG pSrc));
2966	typedef FNIEMAIMPLMXCSRU64U128 *PFNIEMAIMPLMXCSRU64U128;
2967
2968	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvtpd2pi_u128;
2969	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvttpd2pi_u128;
2970
2971	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU128U64,(uint32_t *pfMxcsr, PX86XMMREG pDst, uint64_t u64Src));
2972	typedef FNIEMAIMPLMXCSRU128U64 *PFNIEMAIMPLMXCSRU128U64;
2973
2974	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2ps_u128;
2975	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2pd_u128;
2976
2977	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU64U64,(uint32_t pfMxcsr, uint64_t pu64Dst, uint64_t u64Src));
2978	typedef FNIEMAIMPLMXCSRU64U64 *PFNIEMAIMPLMXCSRU64U64;
2979
2980	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvtps2pi_u128;
2981	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvttps2pi_u128;
2982
2983	/** @} */
2984
2985
2986	/** @name Function tables.
2987	* @{
2988	*/
2989
2990	/**
2991	* Function table for a binary operator providing implementation based on
2992	* operand size.
2993	*/
2994	typedef struct IEMOPBINSIZES
2995	{
2996	PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
2997	PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
2998	PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
2999	PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
3000	} IEMOPBINSIZES;
3001	/** Pointer to a binary operator function table. */
3002	typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
3003
3004
3005	/**
3006	* Function table for a unary operator providing implementation based on
3007	* operand size.
3008	*/
3009	typedef struct IEMOPUNARYSIZES
3010	{
3011	PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
3012	PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
3013	PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
3014	PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
3015	} IEMOPUNARYSIZES;
3016	/** Pointer to a unary operator function table. */
3017	typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
3018
3019
3020	/**
3021	* Function table for a shift operator providing implementation based on
3022	* operand size.
3023	*/
3024	typedef struct IEMOPSHIFTSIZES
3025	{
3026	PFNIEMAIMPLSHIFTU8 pfnNormalU8;
3027	PFNIEMAIMPLSHIFTU16 pfnNormalU16;
3028	PFNIEMAIMPLSHIFTU32 pfnNormalU32;
3029	PFNIEMAIMPLSHIFTU64 pfnNormalU64;
3030	} IEMOPSHIFTSIZES;
3031	/** Pointer to a shift operator function table. */
3032	typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
3033
3034
3035	/**
3036	* Function table for a multiplication or division operation.
3037	*/
3038	typedef struct IEMOPMULDIVSIZES
3039	{
3040	PFNIEMAIMPLMULDIVU8 pfnU8;
3041	PFNIEMAIMPLMULDIVU16 pfnU16;
3042	PFNIEMAIMPLMULDIVU32 pfnU32;
3043	PFNIEMAIMPLMULDIVU64 pfnU64;
3044	} IEMOPMULDIVSIZES;
3045	/** Pointer to a multiplication or division operation function table. */
3046	typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
3047
3048
3049	/**
3050	* Function table for a double precision shift operator providing implementation
3051	* based on operand size.
3052	*/
3053	typedef struct IEMOPSHIFTDBLSIZES
3054	{
3055	PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
3056	PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
3057	PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
3058	} IEMOPSHIFTDBLSIZES;
3059	/** Pointer to a double precision shift function table. */
3060	typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
3061
3062
3063	/**
3064	* Function table for media instruction taking two full sized media source
3065	* registers and one full sized destination register (AVX).
3066	*/
3067	typedef struct IEMOPMEDIAF3
3068	{
3069	PFNIEMAIMPLMEDIAF3U128 pfnU128;
3070	PFNIEMAIMPLMEDIAF3U256 pfnU256;
3071	} IEMOPMEDIAF3;
3072	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
3073	typedef IEMOPMEDIAF3 const *PCIEMOPMEDIAF3;
3074
3075	/** @def IEMOPMEDIAF3_INIT_VARS_EX
3076	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3077	* given functions as initializers. For use in AVX functions where a pair of
3078	* functions are only used once and the function table need not be public. */
3079	#ifndef TST_IEM_CHECK_MC
3080	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3081	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3082	static IEMOPMEDIAF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3083	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3084	# else
3085	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3086	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3087	# endif
3088	#else
3089	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3090	#endif
3091	/** @def IEMOPMEDIAF3_INIT_VARS
3092	* Generate AVX function tables for the @a a_InstrNm instruction.
3093	* @sa IEMOPMEDIAF3_INIT_VARS_EX */
3094	#define IEMOPMEDIAF3_INIT_VARS(a_InstrNm) \
3095	IEMOPMEDIAF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3096	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3097
3098	/**
3099	* Function table for media instruction taking two full sized media source
3100	* registers and one full sized destination register, but no additional state
3101	* (AVX).
3102	*/
3103	typedef struct IEMOPMEDIAOPTF3
3104	{
3105	PFNIEMAIMPLMEDIAOPTF3U128 pfnU128;
3106	PFNIEMAIMPLMEDIAOPTF3U256 pfnU256;
3107	} IEMOPMEDIAOPTF3;
3108	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
3109	typedef IEMOPMEDIAOPTF3 const *PCIEMOPMEDIAOPTF3;
3110
3111	/** @def IEMOPMEDIAOPTF3_INIT_VARS_EX
3112	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3113	* given functions as initializers. For use in AVX functions where a pair of
3114	* functions are only used once and the function table need not be public. */
3115	#ifndef TST_IEM_CHECK_MC
3116	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3117	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3118	static IEMOPMEDIAOPTF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3119	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3120	# else
3121	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3122	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3123	# endif
3124	#else
3125	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3126	#endif
3127	/** @def IEMOPMEDIAOPTF3_INIT_VARS
3128	* Generate AVX function tables for the @a a_InstrNm instruction.
3129	* @sa IEMOPMEDIAOPTF3_INIT_VARS_EX */
3130	#define IEMOPMEDIAOPTF3_INIT_VARS(a_InstrNm) \
3131	IEMOPMEDIAOPTF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3132	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3133
3134	/**
3135	* Function table for media instruction taking one full sized media source
3136	* registers and one full sized destination register, but no additional state
3137	* (AVX).
3138	*/
3139	typedef struct IEMOPMEDIAOPTF2
3140	{
3141	PFNIEMAIMPLMEDIAOPTF2U128 pfnU128;
3142	PFNIEMAIMPLMEDIAOPTF2U256 pfnU256;
3143	} IEMOPMEDIAOPTF2;
3144	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
3145	typedef IEMOPMEDIAOPTF2 const *PCIEMOPMEDIAOPTF2;
3146
3147	/** @def IEMOPMEDIAOPTF2_INIT_VARS_EX
3148	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3149	* given functions as initializers. For use in AVX functions where a pair of
3150	* functions are only used once and the function table need not be public. */
3151	#ifndef TST_IEM_CHECK_MC
3152	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3153	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3154	static IEMOPMEDIAOPTF2 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3155	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3156	# else
3157	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3158	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3159	# endif
3160	#else
3161	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3162	#endif
3163	/** @def IEMOPMEDIAOPTF2_INIT_VARS
3164	* Generate AVX function tables for the @a a_InstrNm instruction.
3165	* @sa IEMOPMEDIAOPTF2_INIT_VARS_EX */
3166	#define IEMOPMEDIAOPTF2_INIT_VARS(a_InstrNm) \
3167	IEMOPMEDIAOPTF2_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3168	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3169
3170	/**
3171	* Function table for media instruction taking two full sized media source
3172	* registers and one full sized destination register and an 8-bit immediate, but no additional state
3173	* (AVX).
3174	*/
3175	typedef struct IEMOPMEDIAOPTF3IMM8
3176	{
3177	PFNIEMAIMPLMEDIAOPTF3U128IMM8 pfnU128;
3178	PFNIEMAIMPLMEDIAOPTF3U256IMM8 pfnU256;
3179	} IEMOPMEDIAOPTF3IMM8;
3180	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
3181	typedef IEMOPMEDIAOPTF3IMM8 const *PCIEMOPMEDIAOPTF3IMM8;
3182
3183	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX
3184	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3185	* given functions as initializers. For use in AVX functions where a pair of
3186	* functions are only used once and the function table need not be public. */
3187	#ifndef TST_IEM_CHECK_MC
3188	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3189	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3190	static IEMOPMEDIAOPTF3IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3191	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3192	# else
3193	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3194	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3195	# endif
3196	#else
3197	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3198	#endif
3199	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS
3200	* Generate AVX function tables for the @a a_InstrNm instruction.
3201	* @sa IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX */
3202	#define IEMOPMEDIAOPTF3IMM8_INIT_VARS(a_InstrNm) \
3203	IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3204	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3205	/** @} */
3206
3207
3208	/**
3209	* Function table for blend type instruction taking three full sized media source
3210	* registers and one full sized destination register, but no additional state
3211	* (AVX).
3212	*/
3213	typedef struct IEMOPBLENDOP
3214	{
3215	PFNIEMAIMPLAVXBLENDU128 pfnU128;
3216	PFNIEMAIMPLAVXBLENDU256 pfnU256;
3217	} IEMOPBLENDOP;
3218	/** Pointer to a media operation function table for 4 full sized ops (AVX). */
3219	typedef IEMOPBLENDOP const *PCIEMOPBLENDOP;
3220
3221	/** @def IEMOPBLENDOP_INIT_VARS_EX
3222	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3223	* given functions as initializers. For use in AVX functions where a pair of
3224	* functions are only used once and the function table need not be public. */
3225	#ifndef TST_IEM_CHECK_MC
3226	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3227	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3228	static IEMOPBLENDOP const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3229	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3230	# else
3231	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3232	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3233	# endif
3234	#else
3235	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3236	#endif
3237	/** @def IEMOPBLENDOP_INIT_VARS
3238	* Generate AVX function tables for the @a a_InstrNm instruction.
3239	* @sa IEMOPBLENDOP_INIT_VARS_EX */
3240	#define IEMOPBLENDOP_INIT_VARS(a_InstrNm) \
3241	IEMOPBLENDOP_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3242	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3243
3244
3245	/** @name SSE/AVX single/double precision floating point operations.
3246	* @{ */
3247	/**
3248	* A SSE result.
3249	*/
3250	typedef struct IEMSSERESULT
3251	{
3252	/** The output value. */
3253	X86XMMREG uResult;
3254	/** The output status. */
3255	uint32_t MXCSR;
3256	} IEMSSERESULT;
3257	AssertCompileMemberOffset(IEMSSERESULT, MXCSR, 128 / 8);
3258	/** Pointer to a SSE result. */
3259	typedef IEMSSERESULT *PIEMSSERESULT;
3260	/** Pointer to a const SSE result. */
3261	typedef IEMSSERESULT const *PCIEMSSERESULT;
3262
3263
3264	/**
3265	* A AVX128 result.
3266	*/
3267	typedef struct IEMAVX128RESULT
3268	{
3269	/** The output value. */
3270	X86XMMREG uResult;
3271	/** The output status. */
3272	uint32_t MXCSR;
3273	} IEMAVX128RESULT;
3274	AssertCompileMemberOffset(IEMAVX128RESULT, MXCSR, 128 / 8);
3275	/** Pointer to a AVX128 result. */
3276	typedef IEMAVX128RESULT *PIEMAVX128RESULT;
3277	/** Pointer to a const AVX128 result. */
3278	typedef IEMAVX128RESULT const *PCIEMAVX128RESULT;
3279
3280
3281	/**
3282	* A AVX256 result.
3283	*/
3284	typedef struct IEMAVX256RESULT
3285	{
3286	/** The output value. */
3287	X86YMMREG uResult;
3288	/** The output status. */
3289	uint32_t MXCSR;
3290	} IEMAVX256RESULT;
3291	AssertCompileMemberOffset(IEMAVX256RESULT, MXCSR, 256 / 8);
3292	/** Pointer to a AVX256 result. */
3293	typedef IEMAVX256RESULT *PIEMAVX256RESULT;
3294	/** Pointer to a const AVX256 result. */
3295	typedef IEMAVX256RESULT const *PCIEMAVX256RESULT;
3296
3297
3298	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
3299	typedef FNIEMAIMPLFPSSEF2U128 *PFNIEMAIMPLFPSSEF2U128;
3300	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128R32,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
3301	typedef FNIEMAIMPLFPSSEF2U128R32 *PFNIEMAIMPLFPSSEF2U128R32;
3302	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128R64,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
3303	typedef FNIEMAIMPLFPSSEF2U128R64 *PFNIEMAIMPLFPSSEF2U128R64;
3304
3305	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
3306	typedef FNIEMAIMPLFPAVXF3U128 *PFNIEMAIMPLFPAVXF3U128;
3307	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128R32,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
3308	typedef FNIEMAIMPLFPAVXF3U128R32 *PFNIEMAIMPLFPAVXF3U128R32;
3309	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128R64,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
3310	typedef FNIEMAIMPLFPAVXF3U128R64 *PFNIEMAIMPLFPAVXF3U128R64;
3311
3312	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U256,(PX86XSAVEAREA pExtState, PIEMAVX256RESULT pResult, PCX86YMMREG puSrc1, PCX86YMMREG puSrc2));
3313	typedef FNIEMAIMPLFPAVXF3U256 *PFNIEMAIMPLFPAVXF3U256;
3314
3315	FNIEMAIMPLFPSSEF2U128 iemAImpl_addps_u128;
3316	FNIEMAIMPLFPSSEF2U128 iemAImpl_addpd_u128;
3317	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulps_u128;
3318	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulpd_u128;
3319	FNIEMAIMPLFPSSEF2U128 iemAImpl_subps_u128;
3320	FNIEMAIMPLFPSSEF2U128 iemAImpl_subpd_u128;
3321	FNIEMAIMPLFPSSEF2U128 iemAImpl_minps_u128;
3322	FNIEMAIMPLFPSSEF2U128 iemAImpl_minpd_u128;
3323	FNIEMAIMPLFPSSEF2U128 iemAImpl_divps_u128;
3324	FNIEMAIMPLFPSSEF2U128 iemAImpl_divpd_u128;
3325	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxps_u128;
3326	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxpd_u128;
3327	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddps_u128;
3328	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddpd_u128;
3329	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubps_u128;
3330	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubpd_u128;
3331	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtps_u128;
3332	FNIEMAIMPLFPSSEF2U128 iemAImpl_rsqrtps_u128;
3333	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtpd_u128;
3334	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubps_u128;
3335	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubpd_u128;
3336	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2ps_u128;
3337	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2pd_u128;
3338
3339	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2ps_u128;
3340	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2dq_u128;
3341	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttps2dq_u128;
3342	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttpd2dq_u128;
3343	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2pd_u128;
3344	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2dq_u128;
3345
3346	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_addss_u128_r32;
3347	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_addsd_u128_r64;
3348	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_mulss_u128_r32;
3349	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_mulsd_u128_r64;
3350	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_subss_u128_r32;
3351	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_subsd_u128_r64;
3352	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_minss_u128_r32;
3353	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_minsd_u128_r64;
3354	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_divss_u128_r32;
3355	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_divsd_u128_r64;
3356	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_maxss_u128_r32;
3357	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_maxsd_u128_r64;
3358	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_cvtss2sd_u128_r32;
3359	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_cvtsd2ss_u128_r64;
3360	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_sqrtss_u128_r32;
3361	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_sqrtsd_u128_r64;
3362	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_rsqrtss_u128_r32;
3363
3364	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddps_u128, iemAImpl_vaddps_u128_fallback;
3365	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddpd_u128, iemAImpl_vaddpd_u128_fallback;
3366	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulps_u128, iemAImpl_vmulps_u128_fallback;
3367	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulpd_u128, iemAImpl_vmulpd_u128_fallback;
3368	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubps_u128, iemAImpl_vsubps_u128_fallback;
3369	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubpd_u128, iemAImpl_vsubpd_u128_fallback;
3370	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminps_u128, iemAImpl_vminps_u128_fallback;
3371	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminpd_u128, iemAImpl_vminpd_u128_fallback;
3372	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivps_u128, iemAImpl_vdivps_u128_fallback;
3373	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivpd_u128, iemAImpl_vdivpd_u128_fallback;
3374	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxps_u128, iemAImpl_vmaxps_u128_fallback;
3375	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxpd_u128, iemAImpl_vmaxpd_u128_fallback;
3376	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddps_u128, iemAImpl_vhaddps_u128_fallback;
3377	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddpd_u128, iemAImpl_vhaddpd_u128_fallback;
3378	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubps_u128, iemAImpl_vhsubps_u128_fallback;
3379	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubpd_u128, iemAImpl_vhsubpd_u128_fallback;
3380	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtps_u128, iemAImpl_vsqrtps_u128_fallback;
3381	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtpd_u128, iemAImpl_vsqrtpd_u128_fallback;
3382	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubps_u128, iemAImpl_vaddsubps_u128_fallback;
3383	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubpd_u128, iemAImpl_vaddsubpd_u128_fallback;
3384	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtpd2ps_u128, iemAImpl_vcvtpd2ps_u128_fallback;
3385	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtps2pd_u128, iemAImpl_vcvtps2pd_u128_fallback;
3386
3387	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vaddss_u128_r32, iemAImpl_vaddss_u128_r32_fallback;
3388	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vaddsd_u128_r64, iemAImpl_vaddsd_u128_r64_fallback;
3389	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmulss_u128_r32, iemAImpl_vmulss_u128_r32_fallback;
3390	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmulsd_u128_r64, iemAImpl_vmulsd_u128_r64_fallback;
3391	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsubss_u128_r32, iemAImpl_vsubss_u128_r32_fallback;
3392	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsubsd_u128_r64, iemAImpl_vsubsd_u128_r64_fallback;
3393	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vminss_u128_r32, iemAImpl_vminss_u128_r32_fallback;
3394	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vminsd_u128_r64, iemAImpl_vminsd_u128_r64_fallback;
3395	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vdivss_u128_r32, iemAImpl_vdivss_u128_r32_fallback;
3396	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vdivsd_u128_r64, iemAImpl_vdivsd_u128_r64_fallback;
3397	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmaxss_u128_r32, iemAImpl_vmaxss_u128_r32_fallback;
3398	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmaxsd_u128_r64, iemAImpl_vmaxsd_u128_r64_fallback;
3399	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsqrtss_u128_r32, iemAImpl_vsqrtss_u128_r32_fallback;
3400	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsqrtsd_u128_r64, iemAImpl_vsqrtsd_u128_r64_fallback;
3401
3402	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddps_u256, iemAImpl_vaddps_u256_fallback;
3403	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddpd_u256, iemAImpl_vaddpd_u256_fallback;
3404	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulps_u256, iemAImpl_vmulps_u256_fallback;
3405	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulpd_u256, iemAImpl_vmulpd_u256_fallback;
3406	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubps_u256, iemAImpl_vsubps_u256_fallback;
3407	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubpd_u256, iemAImpl_vsubpd_u256_fallback;
3408	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminps_u256, iemAImpl_vminps_u256_fallback;
3409	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminpd_u256, iemAImpl_vminpd_u256_fallback;
3410	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivps_u256, iemAImpl_vdivps_u256_fallback;
3411	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivpd_u256, iemAImpl_vdivpd_u256_fallback;
3412	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxps_u256, iemAImpl_vmaxps_u256_fallback;
3413	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxpd_u256, iemAImpl_vmaxpd_u256_fallback;
3414	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddps_u256, iemAImpl_vhaddps_u256_fallback;
3415	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddpd_u256, iemAImpl_vhaddpd_u256_fallback;
3416	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubps_u256, iemAImpl_vhsubps_u256_fallback;
3417	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubpd_u256, iemAImpl_vhsubpd_u256_fallback;
3418	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubps_u256, iemAImpl_vhaddsubps_u256_fallback;
3419	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubpd_u256, iemAImpl_vhaddsubpd_u256_fallback;
3420	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtpd2ps_u256, iemAImpl_vcvtpd2ps_u256_fallback;
3421	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtps2pd_u256, iemAImpl_vcvtps2pd_u256_fallback;
3422	/** @} */
3423
3424	/** @name C instruction implementations for anything slightly complicated.
3425	* @{ */
3426
3427	/**
3428	* For typedef'ing or declaring a C instruction implementation function taking
3429	* no extra arguments.
3430	*
3431	* @param a_Name The name of the type.
3432	*/
3433	# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
3434	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
3435	/**
3436	* For defining a C instruction implementation function taking no extra
3437	* arguments.
3438	*
3439	* @param a_Name The name of the function
3440	*/
3441	# define IEM_CIMPL_DEF_0(a_Name) \
3442	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
3443	/**
3444	* Prototype version of IEM_CIMPL_DEF_0.
3445	*/
3446	# define IEM_CIMPL_PROTO_0(a_Name) \
3447	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
3448	/**
3449	* For calling a C instruction implementation function taking no extra
3450	* arguments.
3451	*
3452	* This special call macro adds default arguments to the call and allow us to
3453	* change these later.
3454	*
3455	* @param a_fn The name of the function.
3456	*/
3457	# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
3458
3459	/**
3460	* For typedef'ing or declaring a C instruction implementation function taking
3461	* one extra argument.
3462	*
3463	* @param a_Name The name of the type.
3464	* @param a_Type0 The argument type.
3465	* @param a_Arg0 The argument name.
3466	*/
3467	# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
3468	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
3469	/**
3470	* For defining a C instruction implementation function taking one extra
3471	* argument.
3472	*
3473	* @param a_Name The name of the function
3474	* @param a_Type0 The argument type.
3475	* @param a_Arg0 The argument name.
3476	*/
3477	# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
3478	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
3479	/**
3480	* Prototype version of IEM_CIMPL_DEF_1.
3481	*/
3482	# define IEM_CIMPL_PROTO_1(a_Name, a_Type0, a_Arg0) \
3483	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
3484	/**
3485	* For calling a C instruction implementation function taking one extra
3486	* argument.
3487	*
3488	* This special call macro adds default arguments to the call and allow us to
3489	* change these later.
3490	*
3491	* @param a_fn The name of the function.
3492	* @param a0 The name of the 1st argument.
3493	*/
3494	# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
3495
3496	/**
3497	* For typedef'ing or declaring a C instruction implementation function taking
3498	* two extra arguments.
3499	*
3500	* @param a_Name The name of the type.
3501	* @param a_Type0 The type of the 1st argument
3502	* @param a_Arg0 The name of the 1st argument.
3503	* @param a_Type1 The type of the 2nd argument.
3504	* @param a_Arg1 The name of the 2nd argument.
3505	*/
3506	# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
3507	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
3508	/**
3509	* For defining a C instruction implementation function taking two extra
3510	* arguments.
3511	*
3512	* @param a_Name The name of the function.
3513	* @param a_Type0 The type of the 1st argument
3514	* @param a_Arg0 The name of the 1st argument.
3515	* @param a_Type1 The type of the 2nd argument.
3516	* @param a_Arg1 The name of the 2nd argument.
3517	*/
3518	# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
3519	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
3520	/**
3521	* Prototype version of IEM_CIMPL_DEF_2.
3522	*/
3523	# define IEM_CIMPL_PROTO_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
3524	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
3525	/**
3526	* For calling a C instruction implementation function taking two extra
3527	* arguments.
3528	*
3529	* This special call macro adds default arguments to the call and allow us to
3530	* change these later.
3531	*
3532	* @param a_fn The name of the function.
3533	* @param a0 The name of the 1st argument.
3534	* @param a1 The name of the 2nd argument.
3535	*/
3536	# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
3537
3538	/**
3539	* For typedef'ing or declaring a C instruction implementation function taking
3540	* three extra arguments.
3541	*
3542	* @param a_Name The name of the type.
3543	* @param a_Type0 The type of the 1st argument
3544	* @param a_Arg0 The name of the 1st argument.
3545	* @param a_Type1 The type of the 2nd argument.
3546	* @param a_Arg1 The name of the 2nd argument.
3547	* @param a_Type2 The type of the 3rd argument.
3548	* @param a_Arg2 The name of the 3rd argument.
3549	*/
3550	# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
3551	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
3552	/**
3553	* For defining a C instruction implementation function taking three extra
3554	* arguments.
3555	*
3556	* @param a_Name The name of the function.
3557	* @param a_Type0 The type of the 1st argument
3558	* @param a_Arg0 The name of the 1st argument.
3559	* @param a_Type1 The type of the 2nd argument.
3560	* @param a_Arg1 The name of the 2nd argument.
3561	* @param a_Type2 The type of the 3rd argument.
3562	* @param a_Arg2 The name of the 3rd argument.
3563	*/
3564	# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
3565	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
3566	/**
3567	* Prototype version of IEM_CIMPL_DEF_3.
3568	*/
3569	# define IEM_CIMPL_PROTO_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
3570	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
3571	/**
3572	* For calling a C instruction implementation function taking three extra
3573	* arguments.
3574	*
3575	* This special call macro adds default arguments to the call and allow us to
3576	* change these later.
3577	*
3578	* @param a_fn The name of the function.
3579	* @param a0 The name of the 1st argument.
3580	* @param a1 The name of the 2nd argument.
3581	* @param a2 The name of the 3rd argument.
3582	*/
3583	# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
3584
3585
3586	/**
3587	* For typedef'ing or declaring a C instruction implementation function taking
3588	* four extra arguments.
3589	*
3590	* @param a_Name The name of the type.
3591	* @param a_Type0 The type of the 1st argument
3592	* @param a_Arg0 The name of the 1st argument.
3593	* @param a_Type1 The type of the 2nd argument.
3594	* @param a_Arg1 The name of the 2nd argument.
3595	* @param a_Type2 The type of the 3rd argument.
3596	* @param a_Arg2 The name of the 3rd argument.
3597	* @param a_Type3 The type of the 4th argument.
3598	* @param a_Arg3 The name of the 4th argument.
3599	*/
3600	# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
3601	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
3602	/**
3603	* For defining a C instruction implementation function taking four extra
3604	* arguments.
3605	*
3606	* @param a_Name The name of the function.
3607	* @param a_Type0 The type of the 1st argument
3608	* @param a_Arg0 The name of the 1st argument.
3609	* @param a_Type1 The type of the 2nd argument.
3610	* @param a_Arg1 The name of the 2nd argument.
3611	* @param a_Type2 The type of the 3rd argument.
3612	* @param a_Arg2 The name of the 3rd argument.
3613	* @param a_Type3 The type of the 4th argument.
3614	* @param a_Arg3 The name of the 4th argument.
3615	*/
3616	# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
3617	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3618	a_Type2 a_Arg2, a_Type3 a_Arg3))
3619	/**
3620	* Prototype version of IEM_CIMPL_DEF_4.
3621	*/
3622	# define IEM_CIMPL_PROTO_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
3623	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3624	a_Type2 a_Arg2, a_Type3 a_Arg3))
3625	/**
3626	* For calling a C instruction implementation function taking four extra
3627	* arguments.
3628	*
3629	* This special call macro adds default arguments to the call and allow us to
3630	* change these later.
3631	*
3632	* @param a_fn The name of the function.
3633	* @param a0 The name of the 1st argument.
3634	* @param a1 The name of the 2nd argument.
3635	* @param a2 The name of the 3rd argument.
3636	* @param a3 The name of the 4th argument.
3637	*/
3638	# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
3639
3640
3641	/**
3642	* For typedef'ing or declaring a C instruction implementation function taking
3643	* five extra arguments.
3644	*
3645	* @param a_Name The name of the type.
3646	* @param a_Type0 The type of the 1st argument
3647	* @param a_Arg0 The name of the 1st argument.
3648	* @param a_Type1 The type of the 2nd argument.
3649	* @param a_Arg1 The name of the 2nd argument.
3650	* @param a_Type2 The type of the 3rd argument.
3651	* @param a_Arg2 The name of the 3rd argument.
3652	* @param a_Type3 The type of the 4th argument.
3653	* @param a_Arg3 The name of the 4th argument.
3654	* @param a_Type4 The type of the 5th argument.
3655	* @param a_Arg4 The name of the 5th argument.
3656	*/
3657	# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
3658	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, \
3659	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
3660	a_Type3 a_Arg3, a_Type4 a_Arg4))
3661	/**
3662	* For defining a C instruction implementation function taking five extra
3663	* arguments.
3664	*
3665	* @param a_Name The name of the function.
3666	* @param a_Type0 The type of the 1st argument
3667	* @param a_Arg0 The name of the 1st argument.
3668	* @param a_Type1 The type of the 2nd argument.
3669	* @param a_Arg1 The name of the 2nd argument.
3670	* @param a_Type2 The type of the 3rd argument.
3671	* @param a_Arg2 The name of the 3rd argument.
3672	* @param a_Type3 The type of the 4th argument.
3673	* @param a_Arg3 The name of the 4th argument.
3674	* @param a_Type4 The type of the 5th argument.
3675	* @param a_Arg4 The name of the 5th argument.
3676	*/
3677	# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
3678	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3679	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
3680	/**
3681	* Prototype version of IEM_CIMPL_DEF_5.
3682	*/
3683	# define IEM_CIMPL_PROTO_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
3684	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3685	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
3686	/**
3687	* For calling a C instruction implementation function taking five extra
3688	* arguments.
3689	*
3690	* This special call macro adds default arguments to the call and allow us to
3691	* change these later.
3692	*
3693	* @param a_fn The name of the function.
3694	* @param a0 The name of the 1st argument.
3695	* @param a1 The name of the 2nd argument.
3696	* @param a2 The name of the 3rd argument.
3697	* @param a3 The name of the 4th argument.
3698	* @param a4 The name of the 5th argument.
3699	*/
3700	# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
3701
3702	/** @} */
3703
3704
3705	/** @name Opcode Decoder Function Types.
3706	* @{ */
3707
3708	/** @typedef PFNIEMOP
3709	* Pointer to an opcode decoder function.
3710	*/
3711
3712	/** @def FNIEMOP_DEF
3713	* Define an opcode decoder function.
3714	*
3715	* We're using macors for this so that adding and removing parameters as well as
3716	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL
3717	*
3718	* @param a_Name The function name.
3719	*/
3720
3721	/** @typedef PFNIEMOPRM
3722	* Pointer to an opcode decoder function with RM byte.
3723	*/
3724
3725	/** @def FNIEMOPRM_DEF
3726	* Define an opcode decoder function with RM byte.
3727	*
3728	* We're using macors for this so that adding and removing parameters as well as
3729	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL_1
3730	*
3731	* @param a_Name The function name.
3732	*/
3733
3734	#if defined(__GNUC__) && defined(RT_ARCH_X86)
3735	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOP)(PVMCPUCC pVCpu);
3736	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3737	# define FNIEMOP_DEF(a_Name) \
3738	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu)
3739	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3740	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
3741	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3742	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
3743
3744	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
3745	typedef VBOXSTRICTRC (__fastcall * PFNIEMOP)(PVMCPUCC pVCpu);
3746	typedef VBOXSTRICTRC (__fastcall * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3747	# define FNIEMOP_DEF(a_Name) \
3748	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
3749	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3750	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
3751	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3752	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
3753
3754	#elif defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
3755	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
3756	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3757	# define FNIEMOP_DEF(a_Name) \
3758	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu)
3759	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3760	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
3761	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3762	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
3763
3764	#else
3765	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
3766	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3767	# define FNIEMOP_DEF(a_Name) \
3768	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
3769	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3770	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
3771	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3772	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
3773
3774	#endif
3775	#define FNIEMOPRM_DEF(a_Name) FNIEMOP_DEF_1(a_Name, uint8_t, bRm)
3776
3777	/**
3778	* Call an opcode decoder function.
3779	*
3780	* We're using macors for this so that adding and removing parameters can be
3781	* done as we please. See FNIEMOP_DEF.
3782	*/
3783	#define FNIEMOP_CALL(a_pfn) (a_pfn)(pVCpu)
3784
3785	/**
3786	* Call a common opcode decoder function taking one extra argument.
3787	*
3788	* We're using macors for this so that adding and removing parameters can be
3789	* done as we please. See FNIEMOP_DEF_1.
3790	*/
3791	#define FNIEMOP_CALL_1(a_pfn, a0) (a_pfn)(pVCpu, a0)
3792
3793	/**
3794	* Call a common opcode decoder function taking one extra argument.
3795	*
3796	* We're using macors for this so that adding and removing parameters can be
3797	* done as we please. See FNIEMOP_DEF_1.
3798	*/
3799	#define FNIEMOP_CALL_2(a_pfn, a0, a1) (a_pfn)(pVCpu, a0, a1)
3800	/** @} */
3801
3802
3803	/** @name Misc Helpers
3804	* @{ */
3805
3806	/** Used to shut up GCC warnings about variables that 'may be used uninitialized'
3807	* due to GCC lacking knowledge about the value range of a switch. */
3808	#if RT_CPLUSPLUS_PREREQ(202000)
3809	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: [[unlikely]] AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
3810	#else
3811	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
3812	#endif
3813
3814	/** Variant of IEM_NOT_REACHED_DEFAULT_CASE_RET that returns a custom value. */
3815	#if RT_CPLUSPLUS_PREREQ(202000)
3816	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: [[unlikely]] AssertFailedReturn(a_RetValue)
3817	#else
3818	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: AssertFailedReturn(a_RetValue)
3819	#endif
3820
3821	/**
3822	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
3823	* occation.
3824	*/
3825	#ifdef LOG_ENABLED
3826	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
3827	do { \
3828	/Log/ LogAlways(("%s: returning IEM_RETURN_ASPECT_NOT_IMPLEMENTED (line %d)\n", __FUNCTION__, __LINE__)); \
3829	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
3830	} while (0)
3831	#else
3832	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
3833	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
3834	#endif
3835
3836	/**
3837	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
3838	* occation using the supplied logger statement.
3839	*
3840	* @param a_LoggerArgs What to log on failure.
3841	*/
3842	#ifdef LOG_ENABLED
3843	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
3844	do { \
3845	LogAlways((LOG_FN_FMT ": ", __PRETTY_FUNCTION__)); LogAlways(a_LoggerArgs); \
3846	/LogFunc(a_LoggerArgs);/ \
3847	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
3848	} while (0)
3849	#else
3850	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
3851	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
3852	#endif
3853
3854	/**
3855	* Gets the CPU mode (from fExec) as a IEMMODE value.
3856	*
3857	* @returns IEMMODE
3858	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3859	*/
3860	#define IEM_GET_CPU_MODE(a_pVCpu) ((a_pVCpu)->iem.s.fExec & IEM_F_MODE_CPUMODE_MASK)
3861
3862	/**
3863	* Check if we're currently executing in real or virtual 8086 mode.
3864	*
3865	* @returns @c true if it is, @c false if not.
3866	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3867	*/
3868	#define IEM_IS_REAL_OR_V86_MODE(a_pVCpu) (( ((a_pVCpu)->iem.s.fExec ^ IEM_F_MODE_X86_PROT_MASK) \
3869	& (IEM_F_MODE_X86_V86_MASK \| IEM_F_MODE_X86_PROT_MASK)) != 0)
3870
3871	/**
3872	* Check if we're currently executing in virtual 8086 mode.
3873	*
3874	* @returns @c true if it is, @c false if not.
3875	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3876	*/
3877	#define IEM_IS_V86_MODE(a_pVCpu) (((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_V86_MASK) != 0)
3878
3879	/**
3880	* Check if we're currently executing in long mode.
3881	*
3882	* @returns @c true if it is, @c false if not.
3883	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3884	*/
3885	#define IEM_IS_LONG_MODE(a_pVCpu) (CPUMIsGuestInLongModeEx(IEM_GET_CTX(a_pVCpu)))
3886
3887	/**
3888	* Check if we're currently executing in a 16-bit code segment.
3889	*
3890	* @returns @c true if it is, @c false if not.
3891	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3892	*/
3893	#define IEM_IS_16BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_16BIT)
3894
3895	/**
3896	* Check if we're currently executing in a 32-bit code segment.
3897	*
3898	* @returns @c true if it is, @c false if not.
3899	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3900	*/
3901	#define IEM_IS_32BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_32BIT)
3902
3903	/**
3904	* Check if we're currently executing in a 64-bit code segment.
3905	*
3906	* @returns @c true if it is, @c false if not.
3907	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3908	*/
3909	#define IEM_IS_64BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_64BIT)
3910
3911	/**
3912	* Check if we're currently executing in real mode.
3913	*
3914	* @returns @c true if it is, @c false if not.
3915	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3916	*/
3917	#define IEM_IS_REAL_MODE(a_pVCpu) (!((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_PROT_MASK))
3918
3919	/**
3920	* Gets the current protection level (CPL).
3921	*
3922	* @returns 0..3
3923	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3924	*/
3925	#define IEM_GET_CPL(a_pVCpu) (((a_pVCpu)->iem.s.fExec >> IEM_F_X86_CPL_SHIFT) & IEM_F_X86_CPL_SMASK)
3926
3927	/**
3928	* Sets the current protection level (CPL).
3929	*
3930	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3931	*/
3932	#define IEM_SET_CPL(a_pVCpu, a_uCpl) \
3933	do { (a_pVCpu)->iem.s.fExec = ((a_pVCpu)->iem.s.fExec & ~IEM_F_X86_CPL_MASK) \| ((a_uCpl) << IEM_F_X86_CPL_SHIFT); } while (0)
3934
3935	/**
3936	* Returns a (const) pointer to the CPUMFEATURES for the guest CPU.
3937	* @returns PCCPUMFEATURES
3938	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3939	*/
3940	#define IEM_GET_GUEST_CPU_FEATURES(a_pVCpu) (&((a_pVCpu)->CTX_SUFF(pVM)->cpum.ro.GuestFeatures))
3941
3942	/**
3943	* Returns a (const) pointer to the CPUMFEATURES for the host CPU.
3944	* @returns PCCPUMFEATURES
3945	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3946	*/
3947	#define IEM_GET_HOST_CPU_FEATURES(a_pVCpu) (&g_CpumHostFeatures.s)
3948
3949	/**
3950	* Evaluates to true if we're presenting an Intel CPU to the guest.
3951	*/
3952	#define IEM_IS_GUEST_CPU_INTEL(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL )
3953
3954	/**
3955	* Evaluates to true if we're presenting an AMD CPU to the guest.
3956	*/
3957	#define IEM_IS_GUEST_CPU_AMD(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_AMD \|\| (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_HYGON )
3958
3959	/**
3960	* Check if the address is canonical.
3961	*/
3962	#define IEM_IS_CANONICAL(a_u64Addr) X86_IS_CANONICAL(a_u64Addr)
3963
3964	/** Checks if the ModR/M byte is in register mode or not. */
3965	#define IEM_IS_MODRM_REG_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT) )
3966	/** Checks if the ModR/M byte is in memory mode or not. */
3967	#define IEM_IS_MODRM_MEM_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT) )
3968
3969	/**
3970	* Gets the register (reg) part of a ModR/M encoding, with REX.R added in.
3971	*
3972	* For use during decoding.
3973	*/
3974	#define IEM_GET_MODRM_REG(a_pVCpu, a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| (a_pVCpu)->iem.s.uRexReg )
3975	/**
3976	* Gets the r/m part of a ModR/M encoding as a register index, with REX.B added in.
3977	*
3978	* For use during decoding.
3979	*/
3980	#define IEM_GET_MODRM_RM(a_pVCpu, a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) \| (a_pVCpu)->iem.s.uRexB )
3981
3982	/**
3983	* Gets the register (reg) part of a ModR/M encoding, without REX.R.
3984	*
3985	* For use during decoding.
3986	*/
3987	#define IEM_GET_MODRM_REG_8(a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) )
3988	/**
3989	* Gets the r/m part of a ModR/M encoding as a register index, without REX.B.
3990	*
3991	* For use during decoding.
3992	*/
3993	#define IEM_GET_MODRM_RM_8(a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) )
3994
3995	/**
3996	* Gets the register (reg) part of a ModR/M encoding as an extended 8-bit
3997	* register index, with REX.R added in.
3998	*
3999	* For use during decoding.
4000	*
4001	* @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
4002	*/
4003	#define IEM_GET_MODRM_REG_EX8(a_pVCpu, a_bRm) \
4004	( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
4005	\|\| !((a_bRm) & (4 << X86_MODRM_REG_SHIFT)) /* IEM_GET_MODRM_REG(pVCpu, a_bRm) < 4 */ \
4006	? IEM_GET_MODRM_REG(pVCpu, a_bRm) : (((a_bRm) >> X86_MODRM_REG_SHIFT) & 3) \| 16)
4007	/**
4008	* Gets the r/m part of a ModR/M encoding as an extended 8-bit register index,
4009	* with REX.B added in.
4010	*
4011	* For use during decoding.
4012	*
4013	* @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
4014	*/
4015	#define IEM_GET_MODRM_RM_EX8(a_pVCpu, a_bRm) \
4016	( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
4017	\|\| !((a_bRm) & 4) /* IEM_GET_MODRM_RM(pVCpu, a_bRm) < 4 */ \
4018	? IEM_GET_MODRM_RM(pVCpu, a_bRm) : ((a_bRm) & 3) \| 16)
4019
4020	/**
4021	* Combines the prefix REX and ModR/M byte for passing to
4022	* iemOpHlpCalcRmEffAddrThreadedAddr64().
4023	*
4024	* @returns The ModRM byte but with bit 3 set to REX.B and bit 4 to REX.X.
4025	* The two bits are part of the REG sub-field, which isn't needed in
4026	* iemOpHlpCalcRmEffAddrThreadedAddr64().
4027	*
4028	* For use during decoding/recompiling.
4029	*/
4030	#define IEM_GET_MODRM_EX(a_pVCpu, a_bRm) \
4031	( ((a_bRm) & ~X86_MODRM_REG_MASK) \
4032	\| (uint8_t)( (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X)) >> (26 - 3) ) )
4033	AssertCompile(IEM_OP_PRF_REX_B == RT_BIT_32(26));
4034	AssertCompile(IEM_OP_PRF_REX_X == RT_BIT_32(27));
4035
4036	/**
4037	* Gets the effective VEX.VVVV value.
4038	*
4039	* The 4th bit is ignored if not 64-bit code.
4040	* @returns effective V-register value.
4041	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4042	*/
4043	#define IEM_GET_EFFECTIVE_VVVV(a_pVCpu) \
4044	(IEM_IS_64BIT_CODE(a_pVCpu) ? (a_pVCpu)->iem.s.uVex3rdReg : (a_pVCpu)->iem.s.uVex3rdReg & 7)
4045
4046
4047	/**
4048	* Checks if we're executing inside an AMD-V or VT-x guest.
4049	*/
4050	#if defined(VBOX_WITH_NESTED_HWVIRT_VMX) \|\| defined(VBOX_WITH_NESTED_HWVIRT_SVM)
4051	# define IEM_IS_IN_GUEST(a_pVCpu) RT_BOOL((a_pVCpu)->iem.s.fExec & IEM_F_X86_CTX_IN_GUEST)
4052	#else
4053	# define IEM_IS_IN_GUEST(a_pVCpu) false
4054	#endif
4055
4056
4057	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
4058
4059	/**
4060	* Check if the guest has entered VMX root operation.
4061	*/
4062	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxRootMode(IEM_GET_CTX(a_pVCpu)))
4063
4064	/**
4065	* Check if the guest has entered VMX non-root operation.
4066	*/
4067	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) ( ((a_pVCpu)->iem.s.fExec & (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST)) \
4068	== (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST) )
4069
4070	/**
4071	* Check if the nested-guest has the given Pin-based VM-execution control set.
4072	*/
4073	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_PinCtl) (CPUMIsGuestVmxPinCtlsSet(IEM_GET_CTX(a_pVCpu), (a_PinCtl)))
4074
4075	/**
4076	* Check if the nested-guest has the given Processor-based VM-execution control set.
4077	*/
4078	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_ProcCtl) (CPUMIsGuestVmxProcCtlsSet(IEM_GET_CTX(a_pVCpu), (a_ProcCtl)))
4079
4080	/**
4081	* Check if the nested-guest has the given Secondary Processor-based VM-execution
4082	* control set.
4083	*/
4084	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_ProcCtl2) (CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(a_pVCpu), (a_ProcCtl2)))
4085
4086	/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
4087	# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
4088
4089	/** Whether a shadow VMCS is present for the given VCPU. */
4090	# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
4091
4092	/** Gets the VMXON region pointer. */
4093	# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
4094
4095	/** Gets the guest-physical address of the current VMCS for the given VCPU. */
4096	# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
4097
4098	/** Whether a current VMCS is present for the given VCPU. */
4099	# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
4100
4101	/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
4102	# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
4103	do \
4104	{ \
4105	Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
4106	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
4107	} while (0)
4108
4109	/** Clears any current VMCS for the given VCPU. */
4110	# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
4111	do \
4112	{ \
4113	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
4114	} while (0)
4115
4116	/**
4117	* Invokes the VMX VM-exit handler for an instruction intercept.
4118	*/
4119	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) \
4120	do { return iemVmxVmexitInstr((a_pVCpu), (a_uExitReason), (a_cbInstr)); } while (0)
4121
4122	/**
4123	* Invokes the VMX VM-exit handler for an instruction intercept where the
4124	* instruction provides additional VM-exit information.
4125	*/
4126	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) \
4127	do { return iemVmxVmexitInstrNeedsInfo((a_pVCpu), (a_uExitReason), (a_uInstrId), (a_cbInstr)); } while (0)
4128
4129	/**
4130	* Invokes the VMX VM-exit handler for a task switch.
4131	*/
4132	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) \
4133	do { return iemVmxVmexitTaskSwitch((a_pVCpu), (a_enmTaskSwitch), (a_SelNewTss), (a_cbInstr)); } while (0)
4134
4135	/**
4136	* Invokes the VMX VM-exit handler for MWAIT.
4137	*/
4138	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) \
4139	do { return iemVmxVmexitInstrMwait((a_pVCpu), (a_fMonitorArmed), (a_cbInstr)); } while (0)
4140
4141	/**
4142	* Invokes the VMX VM-exit handler for EPT faults.
4143	*/
4144	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) \
4145	do { return iemVmxVmexitEpt(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr); } while (0)
4146
4147	/**
4148	* Invokes the VMX VM-exit handler.
4149	*/
4150	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) \
4151	do { return iemVmxVmexit((a_pVCpu), (a_uExitReason), (a_uExitQual)); } while (0)
4152
4153	#else
4154	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (false)
4155	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (false)
4156	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_cbInstr) (false)
4157	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_cbInstr) (false)
4158	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_cbInstr) (false)
4159	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4160	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4161	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4162	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4163	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4164	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) do { return VERR_VMX_IPE_1; } while (0)
4165
4166	#endif
4167
4168	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4169	/**
4170	* Checks if we're executing a guest using AMD-V.
4171	*/
4172	# define IEM_SVM_IS_IN_GUEST(a_pVCpu) ( (a_pVCpu->iem.s.fExec & (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST)) \
4173	== (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST))
4174	/**
4175	* Check if an SVM control/instruction intercept is set.
4176	*/
4177	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) \
4178	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmCtrlInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_Intercept)))
4179
4180	/**
4181	* Check if an SVM read CRx intercept is set.
4182	*/
4183	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
4184	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
4185
4186	/**
4187	* Check if an SVM write CRx intercept is set.
4188	*/
4189	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
4190	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
4191
4192	/**
4193	* Check if an SVM read DRx intercept is set.
4194	*/
4195	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
4196	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
4197
4198	/**
4199	* Check if an SVM write DRx intercept is set.
4200	*/
4201	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
4202	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
4203
4204	/**
4205	* Check if an SVM exception intercept is set.
4206	*/
4207	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) \
4208	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmXcptInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uVector)))
4209
4210	/**
4211	* Invokes the SVM \#VMEXIT handler for the nested-guest.
4212	*/
4213	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
4214	do { return iemSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2)); } while (0)
4215
4216	/**
4217	* Invokes the 'MOV CRx' SVM \#VMEXIT handler after constructing the
4218	* corresponding decode assist information.
4219	*/
4220	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) \
4221	do \
4222	{ \
4223	uint64_t uExitInfo1; \
4224	if ( IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmDecodeAssists \
4225	&& (a_enmAccessCrX) == IEMACCESSCRX_MOV_CRX) \
4226	uExitInfo1 = SVM_EXIT1_MOV_CRX_MASK \| ((a_iGReg) & 7); \
4227	else \
4228	uExitInfo1 = 0; \
4229	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, uExitInfo1, 0); \
4230	} while (0)
4231
4232	/** Check and handles SVM nested-guest instruction intercept and updates
4233	* NRIP if needed.
4234	*/
4235	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
4236	do \
4237	{ \
4238	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept)) \
4239	{ \
4240	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
4241	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2); \
4242	} \
4243	} while (0)
4244
4245	/** Checks and handles SVM nested-guest CR0 read intercept. */
4246	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
4247	do \
4248	{ \
4249	if (!IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, 0)) \
4250	{ /* probably likely */ } \
4251	else \
4252	{ \
4253	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
4254	IEM_SVM_VMEXIT_RET(a_pVCpu, SVM_EXIT_READ_CR0, a_uExitInfo1, a_uExitInfo2); \
4255	} \
4256	} while (0)
4257
4258	/**
4259	* Updates the NextRIP (NRI) field in the nested-guest VMCB.
4260	*/
4261	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) \
4262	do { \
4263	if (IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmNextRipSave) \
4264	CPUMGuestSvmUpdateNRip(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_cbInstr)); \
4265	} while (0)
4266
4267	#else
4268	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) (false)
4269	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
4270	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
4271	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
4272	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
4273	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) (false)
4274	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { return VERR_SVM_IPE_1; } while (0)
4275	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) do { return VERR_SVM_IPE_1; } while (0)
4276	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, \
4277	a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
4278	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
4279	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) do { } while (0)
4280
4281	#endif
4282
4283	/** @} */
4284
4285	uint32_t iemCalcExecDbgFlagsSlow(PVMCPUCC pVCpu);
4286	VBOXSTRICTRC iemExecInjectPendingTrap(PVMCPUCC pVCpu);
4287
4288
4289	/**
4290	* Selector descriptor table entry as fetched by iemMemFetchSelDesc.
4291	*/
4292	typedef union IEMSELDESC
4293	{
4294	/** The legacy view. */
4295	X86DESC Legacy;
4296	/** The long mode view. */
4297	X86DESC64 Long;
4298	} IEMSELDESC;
4299	/** Pointer to a selector descriptor table entry. */
4300	typedef IEMSELDESC *PIEMSELDESC;
4301
4302	/** @name Raising Exceptions.
4303	* @{ */
4304	VBOXSTRICTRC iemTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, uint32_t uNextEip, uint32_t fFlags,
4305	uint16_t uErr, uint64_t uCr2, RTSEL SelTSS, PIEMSELDESC pNewDescTSS) RT_NOEXCEPT;
4306
4307	VBOXSTRICTRC iemRaiseXcptOrInt(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags,
4308	uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
4309	#ifdef IEM_WITH_SETJMP
4310	DECL_NO_RETURN(void) iemRaiseXcptOrIntJmp(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector,
4311	uint32_t fFlags, uint16_t uErr, uint64_t uCr2) IEM_NOEXCEPT_MAY_LONGJMP;
4312	#endif
4313	VBOXSTRICTRC iemRaiseDivideError(PVMCPUCC pVCpu) RT_NOEXCEPT;
4314	VBOXSTRICTRC iemRaiseDebugException(PVMCPUCC pVCpu) RT_NOEXCEPT;
4315	VBOXSTRICTRC iemRaiseBoundRangeExceeded(PVMCPUCC pVCpu) RT_NOEXCEPT;
4316	VBOXSTRICTRC iemRaiseUndefinedOpcode(PVMCPUCC pVCpu) RT_NOEXCEPT;
4317	VBOXSTRICTRC iemRaiseDeviceNotAvailable(PVMCPUCC pVCpu) RT_NOEXCEPT;
4318	VBOXSTRICTRC iemRaiseTaskSwitchFaultWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
4319	VBOXSTRICTRC iemRaiseTaskSwitchFaultCurrentTSS(PVMCPUCC pVCpu) RT_NOEXCEPT;
4320	VBOXSTRICTRC iemRaiseTaskSwitchFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
4321	VBOXSTRICTRC iemRaiseTaskSwitchFaultBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
4322	/VBOXSTRICTRC iemRaiseSelectorNotPresent(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;/
4323	VBOXSTRICTRC iemRaiseSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
4324	VBOXSTRICTRC iemRaiseSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
4325	VBOXSTRICTRC iemRaiseStackSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
4326	VBOXSTRICTRC iemRaiseStackSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
4327	VBOXSTRICTRC iemRaiseGeneralProtectionFault(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
4328	VBOXSTRICTRC iemRaiseGeneralProtectionFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
4329	#ifdef IEM_WITH_SETJMP
4330	DECL_NO_RETURN(void) iemRaiseGeneralProtectionFault0Jmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4331	#endif
4332	VBOXSTRICTRC iemRaiseGeneralProtectionFaultBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
4333	VBOXSTRICTRC iemRaiseNotCanonical(PVMCPUCC pVCpu) RT_NOEXCEPT;
4334	VBOXSTRICTRC iemRaiseSelectorBounds(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
4335	#ifdef IEM_WITH_SETJMP
4336	DECL_NO_RETURN(void) iemRaiseSelectorBoundsJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
4337	#endif
4338	VBOXSTRICTRC iemRaiseSelectorBoundsBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
4339	#ifdef IEM_WITH_SETJMP
4340	DECL_NO_RETURN(void) iemRaiseSelectorBoundsBySelectorJmp(PVMCPUCC pVCpu, RTSEL Sel) IEM_NOEXCEPT_MAY_LONGJMP;
4341	#endif
4342	VBOXSTRICTRC iemRaiseSelectorInvalidAccess(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
4343	#ifdef IEM_WITH_SETJMP
4344	DECL_NO_RETURN(void) iemRaiseSelectorInvalidAccessJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
4345	#endif
4346	VBOXSTRICTRC iemRaisePageFault(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) RT_NOEXCEPT;
4347	#ifdef IEM_WITH_SETJMP
4348	DECL_NO_RETURN(void) iemRaisePageFaultJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) IEM_NOEXCEPT_MAY_LONGJMP;
4349	#endif
4350	VBOXSTRICTRC iemRaiseMathFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
4351	VBOXSTRICTRC iemRaiseAlignmentCheckException(PVMCPUCC pVCpu) RT_NOEXCEPT;
4352	#ifdef IEM_WITH_SETJMP
4353	DECL_NO_RETURN(void) iemRaiseAlignmentCheckExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4354	#endif
4355	VBOXSTRICTRC iemRaiseSimdFpException(PVMCPUCC pVCpu) RT_NOEXCEPT;
4356
4357	void iemLogSyscallProtModeInt(PVMCPUCC pVCpu, uint8_t u8Vector, uint8_t cbInstr);
4358
4359	IEM_CIMPL_DEF_0(iemCImplRaiseDivideError);
4360	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidLockPrefix);
4361	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidOpcode);
4362
4363	/**
4364	* Macro for calling iemCImplRaiseDivideError().
4365	*
4366	* This enables us to add/remove arguments and force different levels of
4367	* inlining as we wish.
4368	*
4369	* @return Strict VBox status code.
4370	*/
4371	#define IEMOP_RAISE_DIVIDE_ERROR_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, iemCImplRaiseDivideError)
4372
4373	/**
4374	* Macro for calling iemCImplRaiseInvalidLockPrefix().
4375	*
4376	* This enables us to add/remove arguments and force different levels of
4377	* inlining as we wish.
4378	*
4379	* @return Strict VBox status code.
4380	*/
4381	#define IEMOP_RAISE_INVALID_LOCK_PREFIX_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, iemCImplRaiseInvalidLockPrefix)
4382
4383	/**
4384	* Macro for calling iemCImplRaiseInvalidOpcode().
4385	*
4386	* This enables us to add/remove arguments and force different levels of
4387	* inlining as we wish.
4388	*
4389	* @return Strict VBox status code.
4390	*/
4391	#define IEMOP_RAISE_INVALID_OPCODE_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, iemCImplRaiseInvalidOpcode)
4392	/** @} */
4393
4394	/** @name Register Access.
4395	* @{ */
4396	VBOXSTRICTRC iemRegRipRelativeJumpS8AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int8_t offNextInstr,
4397	IEMMODE enmEffOpSize) RT_NOEXCEPT;
4398	VBOXSTRICTRC iemRegRipRelativeJumpS16AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int16_t offNextInstr) RT_NOEXCEPT;
4399	VBOXSTRICTRC iemRegRipRelativeJumpS32AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int32_t offNextInstr,
4400	IEMMODE enmEffOpSize) RT_NOEXCEPT;
4401	VBOXSTRICTRC iemRegRipJumpU16AndFinishClearningRF(PVMCPUCC pVCpu, uint16_t uNewRip) RT_NOEXCEPT;
4402	VBOXSTRICTRC iemRegRipJumpU32AndFinishClearningRF(PVMCPUCC pVCpu, uint32_t uNewRip) RT_NOEXCEPT;
4403	VBOXSTRICTRC iemRegRipJumpU64AndFinishClearningRF(PVMCPUCC pVCpu, uint64_t uNewRip) RT_NOEXCEPT;
4404	/** @} */
4405
4406	/** @name FPU access and helpers.
4407	* @{ */
4408	void iemFpuPushResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
4409	void iemFpuPushResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4410	void iemFpuPushResultTwo(PVMCPUCC pVCpu, PIEMFPURESULTTWO pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
4411	void iemFpuStoreResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
4412	void iemFpuStoreResultThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
4413	void iemFpuStoreResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
4414	uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4415	void iemFpuStoreResultWithMemOpThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
4416	uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4417	void iemFpuUpdateOpcodeAndIp(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
4418	void iemFpuUpdateFSW(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
4419	void iemFpuUpdateFSWThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
4420	void iemFpuUpdateFSWWithMemOp(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4421	void iemFpuUpdateFSWThenPopPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
4422	void iemFpuUpdateFSWWithMemOpThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4423	void iemFpuStackUnderflow(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
4424	void iemFpuStackUnderflowWithMemOp(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4425	void iemFpuStackUnderflowThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
4426	void iemFpuStackUnderflowWithMemOpThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4427	void iemFpuStackUnderflowThenPopPop(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
4428	void iemFpuStackPushUnderflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
4429	void iemFpuStackPushUnderflowTwo(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
4430	void iemFpuStackPushOverflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
4431	void iemFpuStackPushOverflowWithMemOp(PVMCPUCC pVCpu, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4432	/** @} */
4433
4434	/** @name SSE+AVX SIMD access and helpers.
4435	* @{ */
4436	void iemSseStoreResult(PVMCPUCC pVCpu, PCIEMSSERESULT pResult, uint8_t iXmmReg) RT_NOEXCEPT;
4437	void iemSseUpdateMxcsr(PVMCPUCC pVCpu, uint32_t fMxcsr) RT_NOEXCEPT;
4438	/** @} */
4439
4440	/** @name Memory access.
4441	* @{ */
4442
4443	/** Report a \#GP instead of \#AC and do not restrict to ring-3 */
4444	#define IEM_MEMMAP_F_ALIGN_GP RT_BIT_32(16)
4445	/** SSE access that should report a \#GP instead of \#AC, unless MXCSR.MM=1
4446	* when it works like normal \#AC. Always used with IEM_MEMMAP_F_ALIGN_GP. */
4447	#define IEM_MEMMAP_F_ALIGN_SSE RT_BIT_32(17)
4448	/** If \#AC is applicable, raise it. Always used with IEM_MEMMAP_F_ALIGN_GP.
4449	* Users include FXSAVE & FXRSTOR. */
4450	#define IEM_MEMMAP_F_ALIGN_GP_OR_AC RT_BIT_32(18)
4451
4452	VBOXSTRICTRC iemMemMap(PVMCPUCC pVCpu, void **ppvMem, size_t cbMem, uint8_t iSegReg, RTGCPTR GCPtrMem,
4453	uint32_t fAccess, uint32_t uAlignCtl) RT_NOEXCEPT;
4454	VBOXSTRICTRC iemMemCommitAndUnmap(PVMCPUCC pVCpu, void *pvMem, uint32_t fAccess) RT_NOEXCEPT;
4455	#ifndef IN_RING3
4456	VBOXSTRICTRC iemMemCommitAndUnmapPostponeTroubleToR3(PVMCPUCC pVCpu, void *pvMem, uint32_t fAccess) RT_NOEXCEPT;
4457	#endif
4458	void iemMemRollback(PVMCPUCC pVCpu) RT_NOEXCEPT;
4459	VBOXSTRICTRC iemMemApplySegment(PVMCPUCC pVCpu, uint32_t fAccess, uint8_t iSegReg, size_t cbMem, PRTGCPTR pGCPtrMem) RT_NOEXCEPT;
4460	VBOXSTRICTRC iemMemMarkSelDescAccessed(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
4461	VBOXSTRICTRC iemMemPageTranslateAndCheckAccess(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t cbAccess, uint32_t fAccess, PRTGCPHYS pGCPhysMem) RT_NOEXCEPT;
4462
4463	void iemOpcodeFlushLight(PVMCPUCC pVCpu, uint8_t cbInstr);
4464	void iemOpcodeFlushHeavy(PVMCPUCC pVCpu, uint8_t cbInstr);
4465	#ifdef IEM_WITH_CODE_TLB
4466	void iemOpcodeFetchBytesJmp(PVMCPUCC pVCpu, size_t cbDst, void *pvDst) IEM_NOEXCEPT_MAY_LONGJMP;
4467	#else
4468	VBOXSTRICTRC iemOpcodeFetchMoreBytes(PVMCPUCC pVCpu, size_t cbMin) RT_NOEXCEPT;
4469	#endif
4470	#ifdef IEM_WITH_SETJMP
4471	uint8_t iemOpcodeGetNextU8SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4472	uint16_t iemOpcodeGetNextU16SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4473	uint32_t iemOpcodeGetNextU32SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4474	uint64_t iemOpcodeGetNextU64SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4475	#else
4476	VBOXSTRICTRC iemOpcodeGetNextU8Slow(PVMCPUCC pVCpu, uint8_t *pb) RT_NOEXCEPT;
4477	VBOXSTRICTRC iemOpcodeGetNextS8SxU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
4478	VBOXSTRICTRC iemOpcodeGetNextS8SxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
4479	VBOXSTRICTRC iemOpcodeGetNextS8SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
4480	VBOXSTRICTRC iemOpcodeGetNextU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
4481	VBOXSTRICTRC iemOpcodeGetNextU16ZxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
4482	VBOXSTRICTRC iemOpcodeGetNextU16ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
4483	VBOXSTRICTRC iemOpcodeGetNextU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
4484	VBOXSTRICTRC iemOpcodeGetNextU32ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
4485	VBOXSTRICTRC iemOpcodeGetNextS32SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
4486	VBOXSTRICTRC iemOpcodeGetNextU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
4487	#endif
4488
4489	VBOXSTRICTRC iemMemFetchDataU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4490	VBOXSTRICTRC iemMemFetchDataU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4491	VBOXSTRICTRC iemMemFetchDataU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4492	VBOXSTRICTRC iemMemFetchDataU32_ZX_U64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4493	VBOXSTRICTRC iemMemFetchDataU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4494	VBOXSTRICTRC iemMemFetchDataU64AlignedU128(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4495	VBOXSTRICTRC iemMemFetchDataR80(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4496	VBOXSTRICTRC iemMemFetchDataD80(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4497	VBOXSTRICTRC iemMemFetchDataU128(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4498	VBOXSTRICTRC iemMemFetchDataU128AlignedSse(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4499	VBOXSTRICTRC iemMemFetchDataU256(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4500	VBOXSTRICTRC iemMemFetchDataU256AlignedSse(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4501	VBOXSTRICTRC iemMemFetchDataXdtr(PVMCPUCC pVCpu, uint16_t *pcbLimit, PRTGCPTR pGCPtrBase, uint8_t iSegReg,
4502	RTGCPTR GCPtrMem, IEMMODE enmOpSize) RT_NOEXCEPT;
4503	#ifdef IEM_WITH_SETJMP
4504	uint8_t iemMemFetchDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4505	uint16_t iemMemFetchDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4506	uint32_t iemMemFetchDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4507	uint64_t iemMemFetchDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4508	uint64_t iemMemFetchDataU64AlignedU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4509	void iemMemFetchDataR80Jmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4510	void iemMemFetchDataD80Jmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4511	void iemMemFetchDataU128Jmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4512	void iemMemFetchDataU128AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4513	void iemMemFetchDataU256Jmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4514	void iemMemFetchDataU256AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4515	#endif
4516
4517	VBOXSTRICTRC iemMemFetchSysU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4518	VBOXSTRICTRC iemMemFetchSysU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4519	VBOXSTRICTRC iemMemFetchSysU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4520	VBOXSTRICTRC iemMemFetchSysU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4521	VBOXSTRICTRC iemMemFetchSelDesc(PVMCPUCC pVCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt) RT_NOEXCEPT;
4522
4523	VBOXSTRICTRC iemMemStoreDataU8(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) RT_NOEXCEPT;
4524	VBOXSTRICTRC iemMemStoreDataU16(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) RT_NOEXCEPT;
4525	VBOXSTRICTRC iemMemStoreDataU32(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) RT_NOEXCEPT;
4526	VBOXSTRICTRC iemMemStoreDataU64(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) RT_NOEXCEPT;
4527	VBOXSTRICTRC iemMemStoreDataU128(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
4528	VBOXSTRICTRC iemMemStoreDataU128AlignedSse(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
4529	VBOXSTRICTRC iemMemStoreDataU256(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
4530	VBOXSTRICTRC iemMemStoreDataU256AlignedAvx(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
4531	VBOXSTRICTRC iemMemStoreDataXdtr(PVMCPUCC pVCpu, uint16_t cbLimit, RTGCPTR GCPtrBase, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4532	#ifdef IEM_WITH_SETJMP
4533	void iemMemStoreDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
4534	void iemMemStoreDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
4535	void iemMemStoreDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
4536	void iemMemStoreDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
4537	void iemMemStoreDataU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
4538	void iemMemStoreDataU128AlignedSseJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
4539	void iemMemStoreDataU256Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
4540	void iemMemStoreDataU256AlignedAvxJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
4541	#endif
4542
4543	VBOXSTRICTRC iemMemStackPushBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
4544	void *ppvMem, uint64_t puNewRsp) RT_NOEXCEPT;
4545	VBOXSTRICTRC iemMemStackPushCommitSpecial(PVMCPUCC pVCpu, void *pvMem, uint64_t uNewRsp) RT_NOEXCEPT;
4546	VBOXSTRICTRC iemMemStackPushU16(PVMCPUCC pVCpu, uint16_t u16Value) RT_NOEXCEPT;
4547	VBOXSTRICTRC iemMemStackPushU32(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
4548	VBOXSTRICTRC iemMemStackPushU64(PVMCPUCC pVCpu, uint64_t u64Value) RT_NOEXCEPT;
4549	VBOXSTRICTRC iemMemStackPushU16Ex(PVMCPUCC pVCpu, uint16_t u16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4550	VBOXSTRICTRC iemMemStackPushU32Ex(PVMCPUCC pVCpu, uint32_t u32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4551	VBOXSTRICTRC iemMemStackPushU64Ex(PVMCPUCC pVCpu, uint64_t u64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4552	VBOXSTRICTRC iemMemStackPushU32SReg(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
4553	VBOXSTRICTRC iemMemStackPopBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
4554	void const *ppvMem, uint64_t puNewRsp) RT_NOEXCEPT;
4555	VBOXSTRICTRC iemMemStackPopContinueSpecial(PVMCPUCC pVCpu, size_t off, size_t cbMem,
4556	void const **ppvMem, uint64_t uCurNewRsp) RT_NOEXCEPT;
4557	VBOXSTRICTRC iemMemStackPopDoneSpecial(PVMCPUCC pVCpu, void const *pvMem) RT_NOEXCEPT;
4558	VBOXSTRICTRC iemMemStackPopU16(PVMCPUCC pVCpu, uint16_t *pu16Value) RT_NOEXCEPT;
4559	VBOXSTRICTRC iemMemStackPopU32(PVMCPUCC pVCpu, uint32_t *pu32Value) RT_NOEXCEPT;
4560	VBOXSTRICTRC iemMemStackPopU64(PVMCPUCC pVCpu, uint64_t *pu64Value) RT_NOEXCEPT;
4561	VBOXSTRICTRC iemMemStackPopU16Ex(PVMCPUCC pVCpu, uint16_t *pu16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4562	VBOXSTRICTRC iemMemStackPopU32Ex(PVMCPUCC pVCpu, uint32_t *pu32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4563	VBOXSTRICTRC iemMemStackPopU64Ex(PVMCPUCC pVCpu, uint64_t *pu64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4564	/** @} */
4565
4566	/** @name IEMAllCImpl.cpp
4567	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/'
4568	* @{ */
4569	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem16, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4570	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem32, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4571	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem64, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4572	IEM_CIMPL_PROTO_0(iemCImpl_popa_16);
4573	IEM_CIMPL_PROTO_0(iemCImpl_popa_32);
4574	IEM_CIMPL_PROTO_0(iemCImpl_pusha_16);
4575	IEM_CIMPL_PROTO_0(iemCImpl_pusha_32);
4576	IEM_CIMPL_PROTO_1(iemCImpl_pushf, IEMMODE, enmEffOpSize);
4577	IEM_CIMPL_PROTO_1(iemCImpl_popf, IEMMODE, enmEffOpSize);
4578	IEM_CIMPL_PROTO_1(iemCImpl_call_16, uint16_t, uNewPC);
4579	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_16, int16_t, offDisp);
4580	IEM_CIMPL_PROTO_1(iemCImpl_call_32, uint32_t, uNewPC);
4581	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_32, int32_t, offDisp);
4582	IEM_CIMPL_PROTO_1(iemCImpl_call_64, uint64_t, uNewPC);
4583	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_64, int64_t, offDisp);
4584	IEM_CIMPL_PROTO_3(iemCImpl_FarJmp, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
4585	IEM_CIMPL_PROTO_3(iemCImpl_callf, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
4586	typedef IEM_CIMPL_DECL_TYPE_3(FNIEMCIMPLFARBRANCH, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
4587	typedef FNIEMCIMPLFARBRANCH *PFNIEMCIMPLFARBRANCH;
4588	IEM_CIMPL_PROTO_2(iemCImpl_retf, IEMMODE, enmEffOpSize, uint16_t, cbPop);
4589	IEM_CIMPL_PROTO_0(iemCImpl_retn_16);
4590	IEM_CIMPL_PROTO_0(iemCImpl_retn_32);
4591	IEM_CIMPL_PROTO_0(iemCImpl_retn_64);
4592	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_16, uint16_t, cbPop);
4593	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_32, uint16_t, cbPop);
4594	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_64, uint16_t, cbPop);
4595	IEM_CIMPL_PROTO_3(iemCImpl_enter, IEMMODE, enmEffOpSize, uint16_t, cbFrame, uint8_t, cParameters);
4596	IEM_CIMPL_PROTO_1(iemCImpl_leave, IEMMODE, enmEffOpSize);
4597	IEM_CIMPL_PROTO_2(iemCImpl_int, uint8_t, u8Int, IEMINT, enmInt);
4598	IEM_CIMPL_PROTO_1(iemCImpl_iret_real_v8086, IEMMODE, enmEffOpSize);
4599	IEM_CIMPL_PROTO_4(iemCImpl_iret_prot_v8086, uint32_t, uNewEip, uint16_t, uNewCs, uint32_t, uNewFlags, uint64_t, uNewRsp);
4600	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot_NestedTask, IEMMODE, enmEffOpSize);
4601	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot, IEMMODE, enmEffOpSize);
4602	IEM_CIMPL_PROTO_1(iemCImpl_iret_64bit, IEMMODE, enmEffOpSize);
4603	IEM_CIMPL_PROTO_1(iemCImpl_iret, IEMMODE, enmEffOpSize);
4604	IEM_CIMPL_PROTO_0(iemCImpl_loadall286);
4605	IEM_CIMPL_PROTO_0(iemCImpl_syscall);
4606	IEM_CIMPL_PROTO_1(iemCImpl_sysret, IEMMODE, enmEffOpSize);
4607	IEM_CIMPL_PROTO_0(iemCImpl_sysenter);
4608	IEM_CIMPL_PROTO_1(iemCImpl_sysexit, IEMMODE, enmEffOpSize);
4609	IEM_CIMPL_PROTO_2(iemCImpl_LoadSReg, uint8_t, iSegReg, uint16_t, uSel);
4610	IEM_CIMPL_PROTO_2(iemCImpl_load_SReg, uint8_t, iSegReg, uint16_t, uSel);
4611	IEM_CIMPL_PROTO_2(iemCImpl_pop_Sreg, uint8_t, iSegReg, IEMMODE, enmEffOpSize);
4612	IEM_CIMPL_PROTO_5(iemCImpl_load_SReg_Greg, uint16_t, uSel, uint64_t, offSeg, uint8_t, iSegReg, uint8_t, iGReg, IEMMODE, enmEffOpSize);
4613	IEM_CIMPL_PROTO_2(iemCImpl_VerX, uint16_t, uSel, bool, fWrite);
4614	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u64, uint64_t *, pu64Dst, uint16_t, uSel, bool, fIsLar);
4615	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u16, uint16_t *, pu16Dst, uint16_t, uSel, bool, fIsLar);
4616	IEM_CIMPL_PROTO_3(iemCImpl_lgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
4617	IEM_CIMPL_PROTO_2(iemCImpl_sgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4618	IEM_CIMPL_PROTO_3(iemCImpl_lidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
4619	IEM_CIMPL_PROTO_2(iemCImpl_sidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4620	IEM_CIMPL_PROTO_1(iemCImpl_lldt, uint16_t, uNewLdt);
4621	IEM_CIMPL_PROTO_2(iemCImpl_sldt_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
4622	IEM_CIMPL_PROTO_2(iemCImpl_sldt_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4623	IEM_CIMPL_PROTO_1(iemCImpl_ltr, uint16_t, uNewTr);
4624	IEM_CIMPL_PROTO_2(iemCImpl_str_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
4625	IEM_CIMPL_PROTO_2(iemCImpl_str_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4626	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Cd, uint8_t, iGReg, uint8_t, iCrReg);
4627	IEM_CIMPL_PROTO_2(iemCImpl_smsw_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
4628	IEM_CIMPL_PROTO_2(iemCImpl_smsw_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4629	IEM_CIMPL_PROTO_4(iemCImpl_load_CrX, uint8_t, iCrReg, uint64_t, uNewCrX, IEMACCESSCRX, enmAccessCrX, uint8_t, iGReg);
4630	IEM_CIMPL_PROTO_2(iemCImpl_mov_Cd_Rd, uint8_t, iCrReg, uint8_t, iGReg);
4631	IEM_CIMPL_PROTO_2(iemCImpl_lmsw, uint16_t, u16NewMsw, RTGCPTR, GCPtrEffDst);
4632	IEM_CIMPL_PROTO_0(iemCImpl_clts);
4633	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Dd, uint8_t, iGReg, uint8_t, iDrReg);
4634	IEM_CIMPL_PROTO_2(iemCImpl_mov_Dd_Rd, uint8_t, iDrReg, uint8_t, iGReg);
4635	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Td, uint8_t, iGReg, uint8_t, iTrReg);
4636	IEM_CIMPL_PROTO_2(iemCImpl_mov_Td_Rd, uint8_t, iTrReg, uint8_t, iGReg);
4637	IEM_CIMPL_PROTO_1(iemCImpl_invlpg, RTGCPTR, GCPtrPage);
4638	IEM_CIMPL_PROTO_3(iemCImpl_invpcid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvpcidDesc, uint64_t, uInvpcidType);
4639	IEM_CIMPL_PROTO_0(iemCImpl_invd);
4640	IEM_CIMPL_PROTO_0(iemCImpl_wbinvd);
4641	IEM_CIMPL_PROTO_0(iemCImpl_rsm);
4642	IEM_CIMPL_PROTO_0(iemCImpl_rdtsc);
4643	IEM_CIMPL_PROTO_0(iemCImpl_rdtscp);
4644	IEM_CIMPL_PROTO_0(iemCImpl_rdpmc);
4645	IEM_CIMPL_PROTO_0(iemCImpl_rdmsr);
4646	IEM_CIMPL_PROTO_0(iemCImpl_wrmsr);
4647	IEM_CIMPL_PROTO_3(iemCImpl_in, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
4648	IEM_CIMPL_PROTO_2(iemCImpl_in_eAX_DX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
4649	IEM_CIMPL_PROTO_3(iemCImpl_out, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
4650	IEM_CIMPL_PROTO_2(iemCImpl_out_DX_eAX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
4651	IEM_CIMPL_PROTO_0(iemCImpl_cli);
4652	IEM_CIMPL_PROTO_0(iemCImpl_sti);
4653	IEM_CIMPL_PROTO_0(iemCImpl_hlt);
4654	IEM_CIMPL_PROTO_1(iemCImpl_monitor, uint8_t, iEffSeg);
4655	IEM_CIMPL_PROTO_0(iemCImpl_mwait);
4656	IEM_CIMPL_PROTO_0(iemCImpl_swapgs);
4657	IEM_CIMPL_PROTO_0(iemCImpl_cpuid);
4658	IEM_CIMPL_PROTO_1(iemCImpl_aad, uint8_t, bImm);
4659	IEM_CIMPL_PROTO_1(iemCImpl_aam, uint8_t, bImm);
4660	IEM_CIMPL_PROTO_0(iemCImpl_daa);
4661	IEM_CIMPL_PROTO_0(iemCImpl_das);
4662	IEM_CIMPL_PROTO_0(iemCImpl_aaa);
4663	IEM_CIMPL_PROTO_0(iemCImpl_aas);
4664	IEM_CIMPL_PROTO_3(iemCImpl_bound_16, int16_t, idxArray, int16_t, idxLowerBound, int16_t, idxUpperBound);
4665	IEM_CIMPL_PROTO_3(iemCImpl_bound_32, int32_t, idxArray, int32_t, idxLowerBound, int32_t, idxUpperBound);
4666	IEM_CIMPL_PROTO_0(iemCImpl_xgetbv);
4667	IEM_CIMPL_PROTO_0(iemCImpl_xsetbv);
4668	IEM_CIMPL_PROTO_4(iemCImpl_cmpxchg16b_fallback_rendezvous, PRTUINT128U, pu128Dst, PRTUINT128U, pu128RaxRdx,
4669	PRTUINT128U, pu128RbxRcx, uint32_t *, pEFlags);
4670	IEM_CIMPL_PROTO_2(iemCImpl_clflush_clflushopt, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
4671	IEM_CIMPL_PROTO_1(iemCImpl_finit, bool, fCheckXcpts);
4672	IEM_CIMPL_PROTO_3(iemCImpl_fxsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
4673	IEM_CIMPL_PROTO_3(iemCImpl_fxrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
4674	IEM_CIMPL_PROTO_3(iemCImpl_xsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
4675	IEM_CIMPL_PROTO_3(iemCImpl_xrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
4676	IEM_CIMPL_PROTO_2(iemCImpl_stmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
4677	IEM_CIMPL_PROTO_2(iemCImpl_vstmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
4678	IEM_CIMPL_PROTO_2(iemCImpl_ldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
4679	IEM_CIMPL_PROTO_3(iemCImpl_fnstenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4680	IEM_CIMPL_PROTO_3(iemCImpl_fnsave, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4681	IEM_CIMPL_PROTO_3(iemCImpl_fldenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
4682	IEM_CIMPL_PROTO_3(iemCImpl_frstor, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
4683	IEM_CIMPL_PROTO_1(iemCImpl_fldcw, uint16_t, u16Fcw);
4684	IEM_CIMPL_PROTO_2(iemCImpl_fxch_underflow, uint8_t, iStReg, uint16_t, uFpuOpcode);
4685	IEM_CIMPL_PROTO_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, PFNIEMAIMPLFPUR80EFL, pfnAImpl, uint32_t, uPopAndFpuOpcode);
4686	/** @} */
4687
4688	/** @name IEMAllCImplStrInstr.cpp.h
4689	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/' -e 's/RT_CONCAT4(//' \
4690	* -e 's/,ADDR_SIZE)/64/g' -e 's/,OP_SIZE,/64/g' -e 's/,OP_rAX,/rax/g' IEMAllCImplStrInstr.cpp.h
4691	* @{ */
4692	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr16, uint8_t, iEffSeg);
4693	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr16, uint8_t, iEffSeg);
4694	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m16);
4695	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m16);
4696	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr16, uint8_t, iEffSeg);
4697	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m16);
4698	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m16, int8_t, iEffSeg);
4699	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr16, bool, fIoChecked);
4700	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr16, bool, fIoChecked);
4701	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4702	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4703
4704	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr16, uint8_t, iEffSeg);
4705	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr16, uint8_t, iEffSeg);
4706	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m16);
4707	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m16);
4708	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr16, uint8_t, iEffSeg);
4709	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m16);
4710	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m16, int8_t, iEffSeg);
4711	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr16, bool, fIoChecked);
4712	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr16, bool, fIoChecked);
4713	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4714	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4715
4716	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr16, uint8_t, iEffSeg);
4717	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr16, uint8_t, iEffSeg);
4718	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m16);
4719	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m16);
4720	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr16, uint8_t, iEffSeg);
4721	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m16);
4722	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m16, int8_t, iEffSeg);
4723	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr16, bool, fIoChecked);
4724	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr16, bool, fIoChecked);
4725	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4726	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4727
4728
4729	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr32, uint8_t, iEffSeg);
4730	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr32, uint8_t, iEffSeg);
4731	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m32);
4732	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m32);
4733	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr32, uint8_t, iEffSeg);
4734	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m32);
4735	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m32, int8_t, iEffSeg);
4736	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr32, bool, fIoChecked);
4737	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr32, bool, fIoChecked);
4738	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4739	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4740
4741	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr32, uint8_t, iEffSeg);
4742	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr32, uint8_t, iEffSeg);
4743	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m32);
4744	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m32);
4745	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr32, uint8_t, iEffSeg);
4746	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m32);
4747	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m32, int8_t, iEffSeg);
4748	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr32, bool, fIoChecked);
4749	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr32, bool, fIoChecked);
4750	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4751	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4752
4753	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr32, uint8_t, iEffSeg);
4754	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr32, uint8_t, iEffSeg);
4755	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m32);
4756	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m32);
4757	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr32, uint8_t, iEffSeg);
4758	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m32);
4759	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m32, int8_t, iEffSeg);
4760	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr32, bool, fIoChecked);
4761	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr32, bool, fIoChecked);
4762	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4763	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4764
4765	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr32, uint8_t, iEffSeg);
4766	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr32, uint8_t, iEffSeg);
4767	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m32);
4768	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m32);
4769	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr32, uint8_t, iEffSeg);
4770	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m32);
4771	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m32, int8_t, iEffSeg);
4772	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr32, bool, fIoChecked);
4773	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr32, bool, fIoChecked);
4774	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4775	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4776
4777
4778	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr64, uint8_t, iEffSeg);
4779	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr64, uint8_t, iEffSeg);
4780	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m64);
4781	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m64);
4782	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr64, uint8_t, iEffSeg);
4783	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m64);
4784	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m64, int8_t, iEffSeg);
4785	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr64, bool, fIoChecked);
4786	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr64, bool, fIoChecked);
4787	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4788	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4789
4790	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr64, uint8_t, iEffSeg);
4791	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr64, uint8_t, iEffSeg);
4792	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m64);
4793	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m64);
4794	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr64, uint8_t, iEffSeg);
4795	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m64);
4796	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m64, int8_t, iEffSeg);
4797	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr64, bool, fIoChecked);
4798	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr64, bool, fIoChecked);
4799	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4800	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4801
4802	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr64, uint8_t, iEffSeg);
4803	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr64, uint8_t, iEffSeg);
4804	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m64);
4805	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m64);
4806	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr64, uint8_t, iEffSeg);
4807	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m64);
4808	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m64, int8_t, iEffSeg);
4809	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr64, bool, fIoChecked);
4810	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr64, bool, fIoChecked);
4811	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4812	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4813
4814	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr64, uint8_t, iEffSeg);
4815	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr64, uint8_t, iEffSeg);
4816	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m64);
4817	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m64);
4818	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr64, uint8_t, iEffSeg);
4819	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m64);
4820	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m64, int8_t, iEffSeg);
4821	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr64, bool, fIoChecked);
4822	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr64, bool, fIoChecked);
4823	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4824	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4825	/** @} */
4826
4827	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
4828	VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT;
4829	VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT;
4830	VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT;
4831	VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT;
4832	VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT;
4833	VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
4834	VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALK pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT;
4835	VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT;
4836	VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT;
4837	VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
4838	bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT;
4839	VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
4840	bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT;
4841	VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4842	VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4843	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4844	VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4845	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4846	VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4847	VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT;
4848	VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
4849	RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT;
4850	VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT;
4851	VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT;
4852	VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT;
4853	uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT;
4854	void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT;
4855	VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
4856	uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT;
4857	bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT;
4858	IEM_CIMPL_PROTO_0(iemCImpl_vmxoff);
4859	IEM_CIMPL_PROTO_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon);
4860	IEM_CIMPL_PROTO_0(iemCImpl_vmlaunch);
4861	IEM_CIMPL_PROTO_0(iemCImpl_vmresume);
4862	IEM_CIMPL_PROTO_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
4863	IEM_CIMPL_PROTO_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
4864	IEM_CIMPL_PROTO_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
4865	IEM_CIMPL_PROTO_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField);
4866	IEM_CIMPL_PROTO_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField);
4867	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField);
4868	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg32, uint64_t *, pu32Dst, uint32_t, u32VmcsField);
4869	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField);
4870	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField);
4871	IEM_CIMPL_PROTO_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType);
4872	IEM_CIMPL_PROTO_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType);
4873	IEM_CIMPL_PROTO_0(iemCImpl_vmx_pause);
4874	#endif
4875
4876	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4877	VBOXSTRICTRC iemSvmVmexit(PVMCPUCC pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2) RT_NOEXCEPT;
4878	VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr, uint64_t uCr2) RT_NOEXCEPT;
4879	VBOXSTRICTRC iemSvmHandleIOIntercept(PVMCPUCC pVCpu, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
4880	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, uint8_t cbInstr) RT_NOEXCEPT;
4881	VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPUCC pVCpu, uint32_t idMsr, bool fWrite, uint8_t cbInstr) RT_NOEXCEPT;
4882	IEM_CIMPL_PROTO_0(iemCImpl_vmrun);
4883	IEM_CIMPL_PROTO_0(iemCImpl_vmload);
4884	IEM_CIMPL_PROTO_0(iemCImpl_vmsave);
4885	IEM_CIMPL_PROTO_0(iemCImpl_clgi);
4886	IEM_CIMPL_PROTO_0(iemCImpl_stgi);
4887	IEM_CIMPL_PROTO_0(iemCImpl_invlpga);
4888	IEM_CIMPL_PROTO_0(iemCImpl_skinit);
4889	IEM_CIMPL_PROTO_0(iemCImpl_svm_pause);
4890	#endif
4891
4892	IEM_CIMPL_PROTO_0(iemCImpl_vmcall); /* vmx */
4893	IEM_CIMPL_PROTO_0(iemCImpl_vmmcall); /* svm */
4894	IEM_CIMPL_PROTO_1(iemCImpl_Hypercall, uint16_t, uDisOpcode); /* both */
4895
4896	void iemThreadedTbObsolete(PVMCPUCC pVCpu, PIEMTB pTb);
4897	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, iemThreadedFunc_BltIn_CheckMode,
4898	(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2));
4899	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, iemThreadedFunc_BltIn_CheckCsLim,
4900	(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2));
4901	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, iemThreadedFunc_BltIn_CheckCsLimAndOpcodes,
4902	(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2));
4903	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, iemThreadedFunc_BltIn_CheckCsLimAndOpcodesAcrossPageLoadingTlb,
4904	(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2));
4905	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, iemThreadedFunc_BltIn_CheckCsLimAndOpcodesLoadingTlb,
4906	(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2));
4907	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, iemThreadedFunc_BltIn_CheckCsLimAndOpcodesOnNextPageLoadingTlb,
4908	(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2));
4909	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, iemThreadedFunc_BltIn_CheckOpcodes,
4910	(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2));
4911	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, iemThreadedFunc_BltIn_CheckOpcodesAcrossPageLoadingTlb,
4912	(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2));
4913	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, iemThreadedFunc_BltIn_CheckOpcodesLoadingTlb,
4914	(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2));
4915	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, iemThreadedFunc_BltIn_CheckOpcodesOnNextPageLoadingTlb,
4916	(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2));
4917
4918
4919	extern const PFNIEMOP g_apfnIemInterpretOnlyOneByteMap[256];
4920
4921	/** @} */
4922
4923	RT_C_DECLS_END
4924
4925	#endif /* !VMM_INCLUDED_SRC_include_IEMInternal_h */
4926

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source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h@ 100694

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