IEMInternal.h@ 100851

Last change on this file since 100851 was 100851, checked in by vboxsync, 20 months ago
VMM/IEM: Make the assembly helpers hidden to avoid calling via the plt or stubs. bugref:10369
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File size: 263.5 KB

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1	/* $Id: IEMInternal.h 100851 2023-08-10 14:34:07Z vboxsync $ */
2	/** @file
3	* IEM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2011-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_IEMInternal_h
29	#define VMM_INCLUDED_SRC_include_IEMInternal_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#include <VBox/vmm/cpum.h>
35	#include <VBox/vmm/iem.h>
36	#include <VBox/vmm/pgm.h>
37	#include <VBox/vmm/stam.h>
38	#include <VBox/param.h>
39
40	#include <iprt/setjmp-without-sigmask.h>
41	#include <iprt/list.h>
42
43
44	RT_C_DECLS_BEGIN
45
46
47	/** @defgroup grp_iem_int Internals
48	* @ingroup grp_iem
49	* @internal
50	* @{
51	*/
52
53	/** For expanding symbol in slickedit and other products tagging and
54	* crossreferencing IEM symbols. */
55	#ifndef IEM_STATIC
56	# define IEM_STATIC static
57	#endif
58
59	/** @def IEM_WITH_SETJMP
60	* Enables alternative status code handling using setjmps.
61	*
62	* This adds a bit of expense via the setjmp() call since it saves all the
63	* non-volatile registers. However, it eliminates return code checks and allows
64	* for more optimal return value passing (return regs instead of stack buffer).
65	*/
66	#if defined(DOXYGEN_RUNNING) \|\| defined(RT_OS_WINDOWS) \|\| 1
67	# define IEM_WITH_SETJMP
68	#endif
69
70	/** @def IEM_WITH_THROW_CATCH
71	* Enables using C++ throw/catch as an alternative to setjmp/longjmp in user
72	* mode code when IEM_WITH_SETJMP is in effect.
73	*
74	* With GCC 11.3.1 and code TLB on linux, using throw/catch instead of
75	* setjmp/long resulted in bs2-test-1 running 3.00% faster and all but on test
76	* result value improving by more than 1%. (Best out of three.)
77	*
78	* With Visual C++ 2019 and code TLB on windows, using throw/catch instead of
79	* setjmp/long resulted in bs2-test-1 running 3.68% faster and all but some of
80	* the MMIO and CPUID tests ran noticeably faster. Variation is greater than on
81	* Linux, but it should be quite a bit faster for normal code.
82	*/
83	#if (defined(__cplusplus) && defined(IEM_WITH_SETJMP) && defined(IN_RING3) && (defined(__GNUC__) \|\| defined(_MSC_VER))) \
84	\|\| defined(DOXYGEN_RUNNING)
85	# define IEM_WITH_THROW_CATCH
86	#endif
87
88	/** @def IEM_DO_LONGJMP
89	*
90	* Wrapper around longjmp / throw.
91	*
92	* @param a_pVCpu The CPU handle.
93	* @param a_rc The status code jump back with / throw.
94	*/
95	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
96	# ifdef IEM_WITH_THROW_CATCH
97	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) throw int(a_rc)
98	# else
99	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) longjmp(*(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf), (a_rc))
100	# endif
101	#endif
102
103	/** For use with IEM function that may do a longjmp (when enabled).
104	*
105	* Visual C++ has trouble longjmp'ing from/over functions with the noexcept
106	* attribute. So, we indicate that function that may be part of a longjmp may
107	* throw "exceptions" and that the compiler should definitely not generate and
108	* std::terminate calling unwind code.
109	*
110	* Here is one example of this ending in std::terminate:
111	* @code{.txt}
112	00 00000041`cadfda10 00007ffc`5d5a1f9f ucrtbase!abort+0x4e
113	01 00000041`cadfda40 00007ffc`57af229a ucrtbase!terminate+0x1f
114	02 00000041`cadfda70 00007ffb`eec91030 VCRUNTIME140!__std_terminate+0xa [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\ehhelpers.cpp @ 192]
115	03 00000041`cadfdaa0 00007ffb`eec92c6d VCRUNTIME140_1!_CallSettingFrame+0x20 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\handlers.asm @ 50]
116	04 00000041`cadfdad0 00007ffb`eec93ae5 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToState+0x241 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 1085]
117	05 00000041`cadfdc00 00007ffb`eec92258 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToEmptyState+0x2d [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 218]
118	06 00000041`cadfdc30 00007ffb`eec940e9 VCRUNTIME140_1!__InternalCxxFrameHandler<__FrameHandler4>+0x194 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 304]
119	07 00000041`cadfdcd0 00007ffc`5f9f249f VCRUNTIME140_1!__CxxFrameHandler4+0xa9 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 290]
120	08 00000041`cadfdd40 00007ffc`5f980939 ntdll!RtlpExecuteHandlerForUnwind+0xf
121	09 00000041`cadfdd70 00007ffc`5f9a0edd ntdll!RtlUnwindEx+0x339
122	0a 00000041`cadfe490 00007ffc`57aff976 ntdll!RtlUnwind+0xcd
123	0b 00000041`cadfea00 00007ffb`e1b5de01 VCRUNTIME140!__longjmp_internal+0xe6 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\longjmp.asm @ 140]
124	0c (Inline Function) --------`-------- VBoxVMM!iemOpcodeGetNextU8SlowJmp+0x95 [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 1155]
125	0d 00000041`cadfea50 00007ffb`e1b60f6b VBoxVMM!iemOpcodeGetNextU8Jmp+0xc1 [L:\vbox-intern\src\VBox\VMM\include\IEMInline.h @ 402]
126	0e 00000041`cadfea90 00007ffb`e1cc6201 VBoxVMM!IEMExecForExits+0xdb [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 10185]
127	0f 00000041`cadfec70 00007ffb`e1d0df8d VBoxVMM!EMHistoryExec+0x4f1 [L:\vbox-intern\src\VBox\VMM\VMMAll\EMAll.cpp @ 452]
128	10 00000041`cadfed60 00007ffb`e1d0d4c0 VBoxVMM!nemR3WinHandleExitCpuId+0x79d [L:\vbox-intern\src\VBox\VMM\VMMAll\NEMAllNativeTemplate-win.cpp.h @ 1829] @encode
129	@endcode
130	*
131	* @see https://developercommunity.visualstudio.com/t/fragile-behavior-of-longjmp-called-from-noexcept-f/1532859
132	*/
133	#if defined(IEM_WITH_SETJMP) && (defined(_MSC_VER) \|\| defined(IEM_WITH_THROW_CATCH))
134	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT_EX(false)
135	#else
136	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT
137	#endif
138
139	#define IEM_IMPLEMENTS_TASKSWITCH
140
141	/** @def IEM_WITH_3DNOW
142	* Includes the 3DNow decoding. */
143	#if (!defined(IEM_WITH_3DNOW) && !defined(IEM_WITHOUT_3DNOW)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
144	# define IEM_WITH_3DNOW
145	#endif
146
147	/** @def IEM_WITH_THREE_0F_38
148	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
149	#if (!defined(IEM_WITH_THREE_0F_38) && !defined(IEM_WITHOUT_THREE_0F_38)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
150	# define IEM_WITH_THREE_0F_38
151	#endif
152
153	/** @def IEM_WITH_THREE_0F_3A
154	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
155	#if (!defined(IEM_WITH_THREE_0F_3A) && !defined(IEM_WITHOUT_THREE_0F_3A)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
156	# define IEM_WITH_THREE_0F_3A
157	#endif
158
159	/** @def IEM_WITH_VEX
160	* Includes the VEX decoding. */
161	#if (!defined(IEM_WITH_VEX) && !defined(IEM_WITHOUT_VEX)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
162	# define IEM_WITH_VEX
163	#endif
164
165	/** @def IEM_CFG_TARGET_CPU
166	* The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
167	*
168	* By default we allow this to be configured by the user via the
169	* CPUM/GuestCpuName config string, but this comes at a slight cost during
170	* decoding. So, for applications of this code where there is no need to
171	* be dynamic wrt target CPU, just modify this define.
172	*/
173	#if !defined(IEM_CFG_TARGET_CPU) \|\| defined(DOXYGEN_RUNNING)
174	# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
175	#endif
176
177	//#define IEM_WITH_CODE_TLB // - work in progress
178	//#define IEM_WITH_DATA_TLB // - work in progress
179
180
181	/** @def IEM_USE_UNALIGNED_DATA_ACCESS
182	* Use unaligned accesses instead of elaborate byte assembly. */
183	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86) \|\| defined(DOXYGEN_RUNNING)
184	# define IEM_USE_UNALIGNED_DATA_ACCESS
185	#endif
186
187	//#define IEM_LOG_MEMORY_WRITES
188
189	#if !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
190	/** Instruction statistics. */
191	typedef struct IEMINSTRSTATS
192	{
193	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
194	# include "IEMInstructionStatisticsTmpl.h"
195	# undef IEM_DO_INSTR_STAT
196	} IEMINSTRSTATS;
197	#else
198	struct IEMINSTRSTATS;
199	typedef struct IEMINSTRSTATS IEMINSTRSTATS;
200	#endif
201	/** Pointer to IEM instruction statistics. */
202	typedef IEMINSTRSTATS *PIEMINSTRSTATS;
203
204
205	/** @name IEMTARGETCPU_EFL_BEHAVIOR_XXX - IEMCPU::aidxTargetCpuEflFlavour
206	* @{ */
207	#define IEMTARGETCPU_EFL_BEHAVIOR_NATIVE 0 /*< Native x86 EFLAGS result; Intel EFLAGS when on non-x86 hosts. /
208	#define IEMTARGETCPU_EFL_BEHAVIOR_INTEL 1 /*< Intel EFLAGS result. /
209	#define IEMTARGETCPU_EFL_BEHAVIOR_AMD 2 /*< AMD EFLAGS result /
210	#define IEMTARGETCPU_EFL_BEHAVIOR_RESERVED 3 /*< Reserved/dummy entry slot that's the same as 0. /
211	#define IEMTARGETCPU_EFL_BEHAVIOR_MASK 3 /*< For masking the index before use. /
212	/** Selects the right variant from a_aArray.
213	* pVCpu is implicit in the caller context. */
214	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT(a_aArray) \
215	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[1] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
216	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for when no native worker can
217	* be used because the host CPU does not support the operation. */
218	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_NON_NATIVE(a_aArray) \
219	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
220	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for a two dimentional
221	* array paralleling IEMCPU::aidxTargetCpuEflFlavour and a single bit index
222	* into the two.
223	* @sa IEM_SELECT_NATIVE_OR_FALLBACK */
224	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
225	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
226	(a_aaArray[a_fNative][pVCpu->iem.s.aidxTargetCpuEflFlavour[a_fNative] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
227	#else
228	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
229	(a_aaArray[0][pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
230	#endif
231	/** @} */
232
233	/**
234	* Picks @a a_pfnNative or @a a_pfnFallback according to the host CPU feature
235	* indicator given by @a a_fCpumFeatureMember (CPUMFEATURES member).
236	*
237	* On non-x86 hosts, this will shortcut to the fallback w/o checking the
238	* indicator.
239	*
240	* @sa IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX
241	*/
242	#if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
243	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) \
244	(g_CpumHostFeatures.s.a_fCpumFeatureMember ? a_pfnNative : a_pfnFallback)
245	#else
246	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) (a_pfnFallback)
247	#endif
248
249
250	/**
251	* Extended operand mode that includes a representation of 8-bit.
252	*
253	* This is used for packing down modes when invoking some C instruction
254	* implementations.
255	*/
256	typedef enum IEMMODEX
257	{
258	IEMMODEX_16BIT = IEMMODE_16BIT,
259	IEMMODEX_32BIT = IEMMODE_32BIT,
260	IEMMODEX_64BIT = IEMMODE_64BIT,
261	IEMMODEX_8BIT
262	} IEMMODEX;
263	AssertCompileSize(IEMMODEX, 4);
264
265
266	/**
267	* Branch types.
268	*/
269	typedef enum IEMBRANCH
270	{
271	IEMBRANCH_JUMP = 1,
272	IEMBRANCH_CALL,
273	IEMBRANCH_TRAP,
274	IEMBRANCH_SOFTWARE_INT,
275	IEMBRANCH_HARDWARE_INT
276	} IEMBRANCH;
277	AssertCompileSize(IEMBRANCH, 4);
278
279
280	/**
281	* INT instruction types.
282	*/
283	typedef enum IEMINT
284	{
285	/** INT n instruction (opcode 0xcd imm). */
286	IEMINT_INTN = 0,
287	/** Single byte INT3 instruction (opcode 0xcc). */
288	IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
289	/** Single byte INTO instruction (opcode 0xce). */
290	IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
291	/** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
292	IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
293	} IEMINT;
294	AssertCompileSize(IEMINT, 4);
295
296
297	/**
298	* A FPU result.
299	*/
300	typedef struct IEMFPURESULT
301	{
302	/** The output value. */
303	RTFLOAT80U r80Result;
304	/** The output status. */
305	uint16_t FSW;
306	} IEMFPURESULT;
307	AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
308	/** Pointer to a FPU result. */
309	typedef IEMFPURESULT *PIEMFPURESULT;
310	/** Pointer to a const FPU result. */
311	typedef IEMFPURESULT const *PCIEMFPURESULT;
312
313
314	/**
315	* A FPU result consisting of two output values and FSW.
316	*/
317	typedef struct IEMFPURESULTTWO
318	{
319	/** The first output value. */
320	RTFLOAT80U r80Result1;
321	/** The output status. */
322	uint16_t FSW;
323	/** The second output value. */
324	RTFLOAT80U r80Result2;
325	} IEMFPURESULTTWO;
326	AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
327	AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
328	/** Pointer to a FPU result consisting of two output values and FSW. */
329	typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
330	/** Pointer to a const FPU result consisting of two output values and FSW. */
331	typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
332
333
334	/**
335	* IEM TLB entry.
336	*
337	* Lookup assembly:
338	* @code{.asm}
339	; Calculate tag.
340	mov rax, [VA]
341	shl rax, 16
342	shr rax, 16 + X86_PAGE_SHIFT
343	or rax, [uTlbRevision]
344
345	; Do indexing.
346	movzx ecx, al
347	lea rcx, [pTlbEntries + rcx]
348
349	; Check tag.
350	cmp [rcx + IEMTLBENTRY.uTag], rax
351	jne .TlbMiss
352
353	; Check access.
354	mov rax, ACCESS_FLAGS \| MAPPING_R3_NOT_VALID \| 0xffffff00
355	and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
356	cmp rax, [uTlbPhysRev]
357	jne .TlbMiss
358
359	; Calc address and we're done.
360	mov eax, X86_PAGE_OFFSET_MASK
361	and eax, [VA]
362	or rax, [rcx + IEMTLBENTRY.pMappingR3]
363	%ifdef VBOX_WITH_STATISTICS
364	inc qword [cTlbHits]
365	%endif
366	jmp .Done
367
368	.TlbMiss:
369	mov r8d, ACCESS_FLAGS
370	mov rdx, [VA]
371	mov rcx, [pVCpu]
372	call iemTlbTypeMiss
373	.Done:
374
375	@endcode
376	*
377	*/
378	typedef struct IEMTLBENTRY
379	{
380	/** The TLB entry tag.
381	* Bits 35 thru 0 are made up of the virtual address shifted right 12 bits, this
382	* is ASSUMING a virtual address width of 48 bits.
383	*
384	* Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
385	*
386	* The TLB lookup code uses the current TLB revision, which won't ever be zero,
387	* enabling an extremely cheap TLB invalidation most of the time. When the TLB
388	* revision wraps around though, the tags needs to be zeroed.
389	*
390	* @note Try use SHRD instruction? After seeing
391	* https://gmplib.org/~tege/x86-timing.pdf, maybe not.
392	*
393	* @todo This will need to be reorganized for 57-bit wide virtual address and
394	* PCID (currently 12 bits) and ASID (currently 6 bits) support. We'll
395	* have to move the TLB entry versioning entirely to the
396	* fFlagsAndPhysRev member then, 57 bit wide VAs means we'll only have
397	* 19 bits left (64 - 57 + 12 = 19) and they'll almost entire be
398	* consumed by PCID and ASID (12 + 6 = 18).
399	*/
400	uint64_t uTag;
401	/** Access flags and physical TLB revision.
402	*
403	* - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
404	* - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
405	* - Bit 2 - page tables - not user (complemented X86_PTE_US).
406	* - Bit 3 - pgm phys/virt - not directly writable.
407	* - Bit 4 - pgm phys page - not directly readable.
408	* - Bit 5 - page tables - not accessed (complemented X86_PTE_A).
409	* - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
410	* - Bit 7 - tlb entry - pMappingR3 member not valid.
411	* - Bits 63 thru 8 are used for the physical TLB revision number.
412	*
413	* We're using complemented bit meanings here because it makes it easy to check
414	* whether special action is required. For instance a user mode write access
415	* would do a "TEST fFlags, (X86_PTE_RW \| X86_PTE_US \| X86_PTE_D)" and a
416	* non-zero result would mean special handling needed because either it wasn't
417	* writable, or it wasn't user, or the page wasn't dirty. A user mode read
418	* access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
419	* need to check any PTE flag.
420	*/
421	uint64_t fFlagsAndPhysRev;
422	/** The guest physical page address. */
423	uint64_t GCPhys;
424	/** Pointer to the ring-3 mapping. */
425	R3PTRTYPE(uint8_t *) pbMappingR3;
426	#if HC_ARCH_BITS == 32
427	uint32_t u32Padding1;
428	#endif
429	} IEMTLBENTRY;
430	AssertCompileSize(IEMTLBENTRY, 32);
431	/** Pointer to an IEM TLB entry. */
432	typedef IEMTLBENTRY *PIEMTLBENTRY;
433
434	/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
435	* @{ */
436	#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /*< Page tables: Not executable. /
437	#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /*< Page tables: Not writable. /
438	#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /*< Page tables: Not user accessible (supervisor only). /
439	#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /*< Phys page: Not writable (access handler, ROM, whatever). /
440	#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /*< Phys page: Not readable (MMIO / access handler, ROM) /
441	#define IEMTLBE_F_PT_NO_ACCESSED RT_BIT_64(5) /*< Phys tables: Not accessed (need to be marked accessed). /
442	#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /*< Page tables: Not dirty (needs to be made dirty on write). /
443	#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(7) /*< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. /
444	#define IEMTLBE_F_PG_UNASSIGNED RT_BIT_64(8) /*< Phys page: Unassigned memory (not RAM, ROM, MMIO2 or MMIO). /
445	#define IEMTLBE_F_PHYS_REV UINT64_C(0xfffffffffffffe00) /*< Physical revision mask. @sa IEMTLB_PHYS_REV_INCR /
446	/** @} */
447
448
449	/**
450	* An IEM TLB.
451	*
452	* We've got two of these, one for data and one for instructions.
453	*/
454	typedef struct IEMTLB
455	{
456	/** The TLB entries.
457	* We've choosen 256 because that way we can obtain the result directly from a
458	* 8-bit register without an additional AND instruction. */
459	IEMTLBENTRY aEntries[256];
460	/** The TLB revision.
461	* This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
462	* by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
463	* the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
464	* (The revision zero indicates an invalid TLB entry.)
465	*
466	* The initial value is choosen to cause an early wraparound. */
467	uint64_t uTlbRevision;
468	/** The TLB physical address revision - shadow of PGM variable.
469	*
470	* This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
471	* incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
472	* a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
473	* as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
474	*
475	* The initial value is choosen to cause an early wraparound. */
476	uint64_t volatile uTlbPhysRev;
477
478	/* Statistics: */
479
480	/** TLB hits (VBOX_WITH_STATISTICS only). */
481	uint64_t cTlbHits;
482	/** TLB misses. */
483	uint32_t cTlbMisses;
484	/** Slow read path. */
485	uint32_t cTlbSlowReadPath;
486	/** Safe read path. */
487	uint32_t cTlbSafeReadPath;
488	/** Safe write path. */
489	uint32_t cTlbSafeWritePath;
490	#if 0
491	/** TLB misses because of tag mismatch. */
492	uint32_t cTlbMissesTag;
493	/** TLB misses because of virtual access violation. */
494	uint32_t cTlbMissesVirtAccess;
495	/** TLB misses because of dirty bit. */
496	uint32_t cTlbMissesDirty;
497	/** TLB misses because of MMIO */
498	uint32_t cTlbMissesMmio;
499	/** TLB misses because of write access handlers. */
500	uint32_t cTlbMissesWriteHandler;
501	/** TLB misses because no r3(/r0) mapping. */
502	uint32_t cTlbMissesMapping;
503	#endif
504	/** Alignment padding. */
505	uint32_t au32Padding[6];
506	} IEMTLB;
507	AssertCompileSizeAlignment(IEMTLB, 64);
508	/** IEMTLB::uTlbRevision increment. */
509	#define IEMTLB_REVISION_INCR RT_BIT_64(36)
510	/** IEMTLB::uTlbRevision mask. */
511	#define IEMTLB_REVISION_MASK (~(RT_BIT_64(36) - 1))
512	/** IEMTLB::uTlbPhysRev increment.
513	* @sa IEMTLBE_F_PHYS_REV */
514	#define IEMTLB_PHYS_REV_INCR RT_BIT_64(9)
515	/**
516	* Calculates the TLB tag for a virtual address.
517	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
518	* @param a_pTlb The TLB.
519	* @param a_GCPtr The virtual address.
520	*/
521	#define IEMTLB_CALC_TAG(a_pTlb, a_GCPtr) ( IEMTLB_CALC_TAG_NO_REV(a_GCPtr) \| (a_pTlb)->uTlbRevision )
522	/**
523	* Calculates the TLB tag for a virtual address but without TLB revision.
524	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
525	* @param a_GCPtr The virtual address.
526	*/
527	#define IEMTLB_CALC_TAG_NO_REV(a_GCPtr) ( (((a_GCPtr) << 16) >> (GUEST_PAGE_SHIFT + 16)) )
528	/**
529	* Converts a TLB tag value into a TLB index.
530	* @returns Index into IEMTLB::aEntries.
531	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
532	*/
533	#define IEMTLB_TAG_TO_INDEX(a_uTag) ( (uint8_t)(a_uTag) )
534	/**
535	* Converts a TLB tag value into a TLB index.
536	* @returns Index into IEMTLB::aEntries.
537	* @param a_pTlb The TLB.
538	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
539	*/
540	#define IEMTLB_TAG_TO_ENTRY(a_pTlb, a_uTag) ( &(a_pTlb)->aEntries[IEMTLB_TAG_TO_INDEX(a_uTag)] )
541
542
543	/** @name IEM_F_XXX - Execution mode flags (IEMCPU::fExec, IEMTB::fFlags).
544	*
545	* These flags are set when entering IEM and adjusted as code is executed, such
546	* that they will always contain the current values as instructions are
547	* finished.
548	*
549	* In recompiled execution mode, (most of) these flags are included in the
550	* translation block selection key and stored in IEMTB::fFlags alongside the
551	* IEMTB_F_XXX flags. The latter flags uses bits 31 thru 24, which are all zero
552	* in IEMCPU::fExec.
553	*
554	* @{ */
555	/** Mode: The block target mode mask. */
556	#define IEM_F_MODE_MASK UINT32_C(0x0000001f)
557	/** Mode: The IEMMODE part of the IEMTB_F_MODE_MASK value. */
558	#define IEM_F_MODE_CPUMODE_MASK UINT32_C(0x00000003)
559	/** X86 Mode: Bit used to indicating pre-386 CPU in 16-bit mode (for eliminating
560	* conditional in EIP/IP updating), and flat wide open CS, SS DS, and ES in
561	* 32-bit mode (for simplifying most memory accesses). */
562	#define IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK UINT32_C(0x00000004)
563	/** X86 Mode: Bit indicating protected mode, real mode (or SMM) when not set. */
564	#define IEM_F_MODE_X86_PROT_MASK UINT32_C(0x00000008)
565	/** X86 Mode: Bit used to indicate virtual 8086 mode (only 16-bit). */
566	#define IEM_F_MODE_X86_V86_MASK UINT32_C(0x00000010)
567
568	/** X86 Mode: 16-bit on 386 or later. */
569	#define IEM_F_MODE_X86_16BIT UINT32_C(0x00000000)
570	/** X86 Mode: 80286, 80186 and 8086/88 targetting blocks (EIP update opt). */
571	#define IEM_F_MODE_X86_16BIT_PRE_386 UINT32_C(0x00000004)
572	/** X86 Mode: 16-bit protected mode on 386 or later. */
573	#define IEM_F_MODE_X86_16BIT_PROT UINT32_C(0x00000008)
574	/** X86 Mode: 16-bit protected mode on 386 or later. */
575	#define IEM_F_MODE_X86_16BIT_PROT_PRE_386 UINT32_C(0x0000000c)
576	/** X86 Mode: 16-bit virtual 8086 protected mode (on 386 or later). */
577	#define IEM_F_MODE_X86_16BIT_PROT_V86 UINT32_C(0x00000018)
578
579	/** X86 Mode: 32-bit on 386 or later. */
580	#define IEM_F_MODE_X86_32BIT UINT32_C(0x00000001)
581	/** X86 Mode: 32-bit mode with wide open flat CS, SS, DS and ES. */
582	#define IEM_F_MODE_X86_32BIT_FLAT UINT32_C(0x00000005)
583	/** X86 Mode: 32-bit protected mode. */
584	#define IEM_F_MODE_X86_32BIT_PROT UINT32_C(0x00000009)
585	/** X86 Mode: 32-bit protected mode with wide open flat CS, SS, DS and ES. */
586	#define IEM_F_MODE_X86_32BIT_PROT_FLAT UINT32_C(0x0000000d)
587
588	/** X86 Mode: 64-bit (includes protected, but not the flat bit). */
589	#define IEM_F_MODE_X86_64BIT UINT32_C(0x0000000a)
590
591
592	/** Bypass access handlers when set. */
593	#define IEM_F_BYPASS_HANDLERS UINT32_C(0x00010000)
594	/** Have pending hardware instruction breakpoints. */
595	#define IEM_F_PENDING_BRK_INSTR UINT32_C(0x00020000)
596	/** Have pending hardware data breakpoints. */
597	#define IEM_F_PENDING_BRK_DATA UINT32_C(0x00040000)
598
599	/** X86: Have pending hardware I/O breakpoints. */
600	#define IEM_F_PENDING_BRK_X86_IO UINT32_C(0x00000400)
601	/** X86: Disregard the lock prefix (implied or not) when set. */
602	#define IEM_F_X86_DISREGARD_LOCK UINT32_C(0x00000800)
603
604	/** Pending breakpoint mask (what iemCalcExecDbgFlags works out). */
605	#define IEM_F_PENDING_BRK_MASK (IEM_F_PENDING_BRK_INSTR \| IEM_F_PENDING_BRK_DATA \| IEM_F_PENDING_BRK_X86_IO)
606
607	/** Caller configurable options. */
608	#define IEM_F_USER_OPTS (IEM_F_BYPASS_HANDLERS \| IEM_F_X86_DISREGARD_LOCK)
609
610	/** X86: The current protection level (CPL) shift factor. */
611	#define IEM_F_X86_CPL_SHIFT 8
612	/** X86: The current protection level (CPL) mask. */
613	#define IEM_F_X86_CPL_MASK UINT32_C(0x00000300)
614	/** X86: The current protection level (CPL) shifted mask. */
615	#define IEM_F_X86_CPL_SMASK UINT32_C(0x00000003)
616
617	/** X86 execution context.
618	* The IEM_F_X86_CTX_XXX values are individual flags that can be combined (with
619	* the exception of IEM_F_X86_CTX_NORMAL). This allows running VMs from SMM
620	* mode. */
621	#define IEM_F_X86_CTX_MASK UINT32_C(0x0000f000)
622	/** X86 context: Plain regular execution context. */
623	#define IEM_F_X86_CTX_NORMAL UINT32_C(0x00000000)
624	/** X86 context: VT-x enabled. */
625	#define IEM_F_X86_CTX_VMX UINT32_C(0x00001000)
626	/** X86 context: AMD-V enabled. */
627	#define IEM_F_X86_CTX_SVM UINT32_C(0x00002000)
628	/** X86 context: In AMD-V or VT-x guest mode. */
629	#define IEM_F_X86_CTX_IN_GUEST UINT32_C(0x00004000)
630	/** X86 context: System management mode (SMM). */
631	#define IEM_F_X86_CTX_SMM UINT32_C(0x00008000)
632
633	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
634	* iemRegFinishClearingRF() most for most situations (CPUMCTX_DBG_HIT_DRX_MASK
635	* and CPUMCTX_DBG_DBGF_MASK are covered by the IEM_F_PENDING_BRK_XXX bits
636	* alread). */
637
638	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
639	* iemRegFinishClearingRF() most for most situations
640	* (CPUMCTX_DBG_HIT_DRX_MASK and CPUMCTX_DBG_DBGF_MASK are covered by
641	* the IEM_F_PENDING_BRK_XXX bits alread). */
642
643	/** @} */
644
645
646	/** @name IEMTB_F_XXX - Translation block flags (IEMTB::fFlags).
647	*
648	* Extends the IEM_F_XXX flags (subject to IEMTB_F_IEM_F_MASK) to make up the
649	* translation block flags. The combined flag mask (subject to
650	* IEMTB_F_KEY_MASK) is used as part of the lookup key for translation blocks.
651	*
652	* @{ */
653	/** Mask of IEM_F_XXX flags included in IEMTB_F_XXX. */
654	#define IEMTB_F_IEM_F_MASK UINT32_C(0x00ffffff)
655
656	/** Type: The block type mask. */
657	#define IEMTB_F_TYPE_MASK UINT32_C(0x03000000)
658	/** Type: Purly threaded recompiler (via tables). */
659	#define IEMTB_F_TYPE_THREADED UINT32_C(0x01000000)
660	/** Type: Native recompilation. */
661	#define IEMTB_F_TYPE_NATIVE UINT32_C(0x02000000)
662
663	/** State mask. */
664	#define IEMTB_F_STATE_MASK UINT32_C(0x0c000000)
665	/** State shift count. */
666	#define IEMTB_F_STATE_SHIFT 26
667	/** State: Compiling. */
668	#define IEMTB_F_STATE_COMPILING UINT32_C(0x04000000)
669	/** State: Ready. */
670	#define IEMTB_F_STATE_READY UINT32_C(0x08000000)
671	/** State: Obsolete, can be deleted when we're sure it's not used any longer. */
672	#define IEMTB_F_STATE_OBSOLETE UINT32_C(0x0c000000)
673
674	/** Set when we're starting the block in an "interrupt shadow".
675	* We don't need to distingish between the two types of this mask, thus the one.
676	* @see CPUMCTX_INHIBIT_SHADOW, CPUMIsInInterruptShadow() */
677	#define IEMTB_F_INHIBIT_SHADOW UINT32_C(0x10000000)
678	/** Set when we're currently inhibiting NMIs
679	* @see CPUMCTX_INHIBIT_NMI, CPUMAreInterruptsInhibitedByNmi() */
680	#define IEMTB_F_INHIBIT_NMI UINT32_C(0x20000000)
681
682	/** Checks that EIP/IP is wihin CS.LIM before each instruction. Used when
683	* we're close the limit before starting a TB, as determined by
684	* iemGetTbFlagsForCurrentPc(). */
685	#define IEMTB_F_CS_LIM_CHECKS UINT32_C(0x40000000)
686
687	/** Mask of the IEMTB_F_XXX flags that are part of the TB lookup key.
688	* @note We skip the CPL as we don't currently generate ring-specific code,
689	* that's all handled in CIMPL functions.
690	*
691	* For the same reasons, we skip all of IEM_F_X86_CTX_MASK, with the
692	* exception of SMM (which we don't implement). */
693	#define IEMTB_F_KEY_MASK ((UINT32_C(0xffffffff) & ~(IEM_F_X86_CTX_MASK \| IEM_F_X86_CPL_MASK)) \| IEM_F_X86_CTX_SMM)
694	/** @} */
695
696	AssertCompile( (IEM_F_MODE_X86_16BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
697	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
698	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_PROT_MASK));
699	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_V86_MASK));
700	AssertCompile( (IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
701	AssertCompile( IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
702	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_PROT_MASK));
703	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
704	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
705	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
706	AssertCompile( IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
707	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_V86_MASK));
708	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
709	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
710	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_PROT_MASK);
711	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
712	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_PROT_MASK);
713	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
714	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_V86_MASK);
715
716	AssertCompile( (IEM_F_MODE_X86_32BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
717	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
718	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_PROT_MASK));
719	AssertCompile( (IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
720	AssertCompile( IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
721	AssertCompile(!(IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_PROT_MASK));
722	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
723	AssertCompile(!(IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
724	AssertCompile( IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
725	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
726	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
727	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_PROT_MASK);
728
729	AssertCompile( (IEM_F_MODE_X86_64BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_64BIT);
730	AssertCompile( IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_PROT_MASK);
731	AssertCompile(!(IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
732
733	/**
734	* A call for the threaded call table.
735	*/
736	typedef struct IEMTHRDEDCALLENTRY
737	{
738	/** The function to call (IEMTHREADEDFUNCS). */
739	uint16_t enmFunction;
740	/** Instruction number in the TB (for statistics). */
741	uint8_t idxInstr;
742	uint8_t uUnused0;
743
744	/** Offset into IEMTB::pabOpcodes. */
745	uint16_t offOpcode;
746	/** The opcode length. */
747	uint8_t cbOpcode;
748	/** Index in to IEMTB::aRanges. */
749	uint8_t idxRange;
750
751	/** Generic parameters. */
752	uint64_t auParams[3];
753	} IEMTHRDEDCALLENTRY;
754	AssertCompileSize(IEMTHRDEDCALLENTRY, sizeof(uint64_t) * 4);
755	/** Pointer to a threaded call entry. */
756	typedef struct IEMTHRDEDCALLENTRY *PIEMTHRDEDCALLENTRY;
757	/** Pointer to a const threaded call entry. */
758	typedef IEMTHRDEDCALLENTRY const *PCIEMTHRDEDCALLENTRY;
759
760	/**
761	* Translation block.
762	*/
763	#pragma pack(2) /* to prevent the Thrd structure from being padded unnecessarily */
764	typedef struct IEMTB
765	{
766	/** Next block with the same hash table entry. */
767	struct IEMTB * volatile pNext;
768	/** List on the local VCPU for blocks. */
769	RTLISTNODE LocalList;
770
771	/** @name What uniquely identifies the block.
772	* @{ */
773	RTGCPHYS GCPhysPc;
774	/** IEMTB_F_XXX (i.e. IEM_F_XXX ++). */
775	uint32_t fFlags;
776	union
777	{
778	struct
779	{
780	/*< Relevant CS X86DESCATTR_XXX bits. /
781	uint16_t fAttr;
782	} x86;
783	};
784	/** @} */
785
786	/** Number of opcode ranges. */
787	uint8_t cRanges;
788	/** Statistics: Number of instructions in the block. */
789	uint8_t cInstructions;
790
791	/** Type specific info. */
792	union
793	{
794	struct
795	{
796	/** The call sequence table. */
797	PIEMTHRDEDCALLENTRY paCalls;
798	/** Number of calls in paCalls. */
799	uint16_t cCalls;
800	/** Number of calls allocated. */
801	uint16_t cAllocated;
802	} Thrd;
803	};
804
805	/** Number of bytes of opcodes stored in pabOpcodes. */
806	uint16_t cbOpcodes;
807	/** The max storage available in the pabOpcodes block. */
808	uint16_t cbOpcodesAllocated;
809	/** Pointer to the opcode bytes this block was recompiled from. */
810	uint8_t *pabOpcodes;
811
812	/* --- 64 byte cache line end --- */
813
814	/** Opcode ranges.
815	*
816	* The opcode checkers and maybe TLB loading functions will use this to figure
817	* out what to do. The parameter will specify an entry and the opcode offset to
818	* start at and the minimum number of bytes to verify (instruction length).
819	*
820	* When VT-x and AMD-V looks up the opcode bytes for an exitting instruction,
821	* they'll first translate RIP (+ cbInstr - 1) to a physical address using the
822	* code TLB (must have a valid entry for that address) and scan the ranges to
823	* locate the corresponding opcodes. Probably.
824	*/
825	struct IEMTBOPCODERANGE
826	{
827	/** Offset within pabOpcodes. */
828	uint16_t offOpcodes;
829	/** Number of bytes. */
830	uint16_t cbOpcodes;
831	/** The page offset. */
832	RT_GCC_EXTENSION
833	uint16_t offPhysPage : 12;
834	/** Unused bits. */
835	RT_GCC_EXTENSION
836	uint16_t u2Unused : 2;
837	/** Index into GCPhysPc + aGCPhysPages for the physical page address. */
838	RT_GCC_EXTENSION
839	uint16_t idxPhysPage : 2;
840	} aRanges[8];
841
842	/** Physical pages that this TB covers.
843	* The GCPhysPc w/o page offset is element zero, so starting here with 1. */
844	RTGCPHYS aGCPhysPages[2];
845	} IEMTB;
846	#pragma pack()
847	AssertCompileMemberOffset(IEMTB, x86, 36);
848	AssertCompileMemberOffset(IEMTB, cRanges, 38);
849	AssertCompileMemberOffset(IEMTB, Thrd, 40);
850	AssertCompileMemberOffset(IEMTB, Thrd.cCalls, 48);
851	AssertCompileMemberOffset(IEMTB, cbOpcodes, 52);
852	AssertCompileMemberSize(IEMTB, aRanges[0], 6);
853	AssertCompileSize(IEMTB, 128);
854	/** Pointer to a translation block. */
855	typedef IEMTB *PIEMTB;
856	/** Pointer to a const translation block. */
857	typedef IEMTB const *PCIEMTB;
858
859	/** @name IEMBRANCHED_F_XXX - Branched indicator (IEMCPU::fTbBranched).
860	*
861	* These flags parallels IEM_CIMPL_F_BRANCH_XXX.
862	*
863	* @{ */
864	/** Value if no branching happened recently. */
865	#define IEMBRANCHED_F_NO UINT8_C(0x00)
866	/** Flag set if direct branch, clear if absolute or indirect. */
867	#define IEMBRANCHED_F_DIRECT UINT8_C(0x01)
868	/** Flag set if indirect branch, clear if direct or relative. */
869	#define IEMBRANCHED_F_INDIRECT UINT8_C(0x02)
870	/** Flag set if relative branch, clear if absolute or indirect. */
871	#define IEMBRANCHED_F_RELATIVE UINT8_C(0x04)
872	/** Flag set if conditional branch, clear if unconditional. */
873	#define IEMBRANCHED_F_CONDITIONAL UINT8_C(0x08)
874	/** Flag set if it's a far branch. */
875	#define IEMBRANCHED_F_FAR UINT8_C(0x10)
876	/** Flag set (by IEM_MC_REL_JMP_XXX) if it's a zero bytes relative jump. */
877	#define IEMBRANCHED_F_ZERO UINT8_C(0x20)
878	/** @} */
879
880
881	/**
882	* The per-CPU IEM state.
883	*/
884	typedef struct IEMCPU
885	{
886	/** Info status code that needs to be propagated to the IEM caller.
887	* This cannot be passed internally, as it would complicate all success
888	* checks within the interpreter making the code larger and almost impossible
889	* to get right. Instead, we'll store status codes to pass on here. Each
890	* source of these codes will perform appropriate sanity checks. */
891	int32_t rcPassUp; /* 0x00 */
892	/** Execution flag, IEM_F_XXX. */
893	uint32_t fExec; /* 0x04 */
894
895	/** @name Decoder state.
896	* @{ */
897	#ifndef IEM_WITH_OPAQUE_DECODER_STATE
898	# ifdef IEM_WITH_CODE_TLB
899	/** The offset of the next instruction byte. */
900	uint32_t offInstrNextByte; /* 0x08 */
901	/** The number of bytes available at pbInstrBuf for the current instruction.
902	* This takes the max opcode length into account so that doesn't need to be
903	* checked separately. */
904	uint32_t cbInstrBuf; /* 0x0c */
905	/** Pointer to the page containing RIP, user specified buffer or abOpcode.
906	* This can be NULL if the page isn't mappable for some reason, in which
907	* case we'll do fallback stuff.
908	*
909	* If we're executing an instruction from a user specified buffer,
910	* IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
911	* aligned pointer but pointer to the user data.
912	*
913	* For instructions crossing pages, this will start on the first page and be
914	* advanced to the next page by the time we've decoded the instruction. This
915	* therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
916	*/
917	uint8_t const pbInstrBuf; / 0x10 */
918	# if ARCH_BITS == 32
919	uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
920	# endif
921	/** The program counter corresponding to pbInstrBuf.
922	* This is set to a non-canonical address when we need to invalidate it. */
923	uint64_t uInstrBufPc; /* 0x18 */
924	/** The guest physical address corresponding to pbInstrBuf. */
925	RTGCPHYS GCPhysInstrBuf; /* 0x20 */
926	/** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
927	* This takes the CS segment limit into account. */
928	uint16_t cbInstrBufTotal; /* 0x28 */
929	/** Offset into pbInstrBuf of the first byte of the current instruction.
930	* Can be negative to efficiently handle cross page instructions. */
931	int16_t offCurInstrStart; /* 0x2a */
932
933	/** The prefix mask (IEM_OP_PRF_XXX). */
934	uint32_t fPrefixes; /* 0x2c */
935	/** The extra REX ModR/M register field bit (REX.R << 3). */
936	uint8_t uRexReg; /* 0x30 */
937	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
938	* (REX.B << 3). */
939	uint8_t uRexB; /* 0x31 */
940	/** The extra REX SIB index field bit (REX.X << 3). */
941	uint8_t uRexIndex; /* 0x32 */
942
943	/** The effective segment register (X86_SREG_XXX). */
944	uint8_t iEffSeg; /* 0x33 */
945
946	/** The offset of the ModR/M byte relative to the start of the instruction. */
947	uint8_t offModRm; /* 0x34 */
948
949	# ifdef IEM_WITH_CODE_TLB_AND_OPCODE_BUF
950	/** The current offset into abOpcode. */
951	uint8_t offOpcode; /* 0x35 */
952	# else
953	uint8_t bUnused; /* 0x35 */
954	# endif
955	# else /* !IEM_WITH_CODE_TLB */
956	/** The size of what has currently been fetched into abOpcode. */
957	uint8_t cbOpcode; /* 0x08 */
958	/** The current offset into abOpcode. */
959	uint8_t offOpcode; /* 0x09 */
960	/** The offset of the ModR/M byte relative to the start of the instruction. */
961	uint8_t offModRm; /* 0x0a */
962
963	/** The effective segment register (X86_SREG_XXX). */
964	uint8_t iEffSeg; /* 0x0b */
965
966	/** The prefix mask (IEM_OP_PRF_XXX). */
967	uint32_t fPrefixes; /* 0x0c */
968	/** The extra REX ModR/M register field bit (REX.R << 3). */
969	uint8_t uRexReg; /* 0x10 */
970	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
971	* (REX.B << 3). */
972	uint8_t uRexB; /* 0x11 */
973	/** The extra REX SIB index field bit (REX.X << 3). */
974	uint8_t uRexIndex; /* 0x12 */
975
976	# endif /* !IEM_WITH_CODE_TLB */
977
978	/** The effective operand mode. */
979	IEMMODE enmEffOpSize; /* 0x36, 0x13 */
980	/** The default addressing mode. */
981	IEMMODE enmDefAddrMode; /* 0x37, 0x14 */
982	/** The effective addressing mode. */
983	IEMMODE enmEffAddrMode; /* 0x38, 0x15 */
984	/** The default operand mode. */
985	IEMMODE enmDefOpSize; /* 0x39, 0x16 */
986
987	/** Prefix index (VEX.pp) for two byte and three byte tables. */
988	uint8_t idxPrefix; /* 0x3a, 0x17 */
989	/** 3rd VEX/EVEX/XOP register.
990	* Please use IEM_GET_EFFECTIVE_VVVV to access. */
991	uint8_t uVex3rdReg; /* 0x3b, 0x18 */
992	/** The VEX/EVEX/XOP length field. */
993	uint8_t uVexLength; /* 0x3c, 0x19 */
994	/** Additional EVEX stuff. */
995	uint8_t fEvexStuff; /* 0x3d, 0x1a */
996
997	# ifndef IEM_WITH_CODE_TLB
998	/** Explicit alignment padding. */
999	uint8_t abAlignment2a[1]; /* 0x1b */
1000	# endif
1001	/** The FPU opcode (FOP). */
1002	uint16_t uFpuOpcode; /* 0x3e, 0x1c */
1003	# ifndef IEM_WITH_CODE_TLB
1004	/** Explicit alignment padding. */
1005	uint8_t abAlignment2b[2]; /* 0x1e */
1006	# endif
1007
1008	/** The opcode bytes. */
1009	uint8_t abOpcode[15]; /* 0x40, 0x20 */
1010	/** Explicit alignment padding. */
1011	# ifdef IEM_WITH_CODE_TLB
1012	//uint8_t abAlignment2c[0x4f - 0x4f]; /* 0x4f */
1013	# else
1014	uint8_t abAlignment2c[0x4f - 0x2f]; /* 0x2f */
1015	# endif
1016	#else /* IEM_WITH_OPAQUE_DECODER_STATE */
1017	uint8_t abOpaqueDecoder[0x4f - 0x8];
1018	#endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1019	/** @} */
1020
1021
1022	/** The number of active guest memory mappings. */
1023	uint8_t cActiveMappings; /* 0x4f, 0x4f */
1024
1025	/** Records for tracking guest memory mappings. */
1026	struct
1027	{
1028	/** The address of the mapped bytes. */
1029	R3R0PTRTYPE(void *) pv;
1030	/** The access flags (IEM_ACCESS_XXX).
1031	* IEM_ACCESS_INVALID if the entry is unused. */
1032	uint32_t fAccess;
1033	#if HC_ARCH_BITS == 64
1034	uint32_t u32Alignment4; /*< Alignment padding. /
1035	#endif
1036	} aMemMappings[3]; /* 0x50 LB 0x30 */
1037
1038	/** Locking records for the mapped memory. */
1039	union
1040	{
1041	PGMPAGEMAPLOCK Lock;
1042	uint64_t au64Padding[2];
1043	} aMemMappingLocks[3]; /* 0x80 LB 0x30 */
1044
1045	/** Bounce buffer info.
1046	* This runs in parallel to aMemMappings. */
1047	struct
1048	{
1049	/** The physical address of the first byte. */
1050	RTGCPHYS GCPhysFirst;
1051	/** The physical address of the second page. */
1052	RTGCPHYS GCPhysSecond;
1053	/** The number of bytes in the first page. */
1054	uint16_t cbFirst;
1055	/** The number of bytes in the second page. */
1056	uint16_t cbSecond;
1057	/** Whether it's unassigned memory. */
1058	bool fUnassigned;
1059	/** Explicit alignment padding. */
1060	bool afAlignment5[3];
1061	} aMemBbMappings[3]; /* 0xb0 LB 0x48 */
1062
1063	/** The flags of the current exception / interrupt. */
1064	uint32_t fCurXcpt; /* 0xf8 */
1065	/** The current exception / interrupt. */
1066	uint8_t uCurXcpt; /* 0xfc */
1067	/** Exception / interrupt recursion depth. */
1068	int8_t cXcptRecursions; /* 0xfb */
1069
1070	/** The next unused mapping index.
1071	* @todo try find room for this up with cActiveMappings. */
1072	uint8_t iNextMapping; /* 0xfd */
1073	uint8_t abAlignment7[1];
1074
1075	/** Bounce buffer storage.
1076	* This runs in parallel to aMemMappings and aMemBbMappings. */
1077	struct
1078	{
1079	uint8_t ab[512];
1080	} aBounceBuffers[3]; /* 0x100 LB 0x600 */
1081
1082
1083	/** Pointer set jump buffer - ring-3 context. */
1084	R3PTRTYPE(jmp_buf *) pJmpBufR3;
1085	/** Pointer set jump buffer - ring-0 context. */
1086	R0PTRTYPE(jmp_buf *) pJmpBufR0;
1087
1088	/** @todo Should move this near @a fCurXcpt later. */
1089	/** The CR2 for the current exception / interrupt. */
1090	uint64_t uCurXcptCr2;
1091	/** The error code for the current exception / interrupt. */
1092	uint32_t uCurXcptErr;
1093
1094	/** @name Statistics
1095	* @{ */
1096	/** The number of instructions we've executed. */
1097	uint32_t cInstructions;
1098	/** The number of potential exits. */
1099	uint32_t cPotentialExits;
1100	/** The number of bytes data or stack written (mostly for IEMExecOneEx).
1101	* This may contain uncommitted writes. */
1102	uint32_t cbWritten;
1103	/** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
1104	uint32_t cRetInstrNotImplemented;
1105	/** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
1106	uint32_t cRetAspectNotImplemented;
1107	/** Counts informational statuses returned (other than VINF_SUCCESS). */
1108	uint32_t cRetInfStatuses;
1109	/** Counts other error statuses returned. */
1110	uint32_t cRetErrStatuses;
1111	/** Number of times rcPassUp has been used. */
1112	uint32_t cRetPassUpStatus;
1113	/** Number of times RZ left with instruction commit pending for ring-3. */
1114	uint32_t cPendingCommit;
1115	/** Number of long jumps. */
1116	uint32_t cLongJumps;
1117	/** @} */
1118
1119	/** @name Target CPU information.
1120	* @{ */
1121	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
1122	/** The target CPU. */
1123	uint8_t uTargetCpu;
1124	#else
1125	uint8_t bTargetCpuPadding;
1126	#endif
1127	/** For selecting assembly works matching the target CPU EFLAGS behaviour, see
1128	* IEMTARGETCPU_EFL_BEHAVIOR_XXX for values, with the 1st entry for when no
1129	* native host support and the 2nd for when there is.
1130	*
1131	* The two values are typically indexed by a g_CpumHostFeatures bit.
1132	*
1133	* This is for instance used for the BSF & BSR instructions where AMD and
1134	* Intel CPUs produce different EFLAGS. */
1135	uint8_t aidxTargetCpuEflFlavour[2];
1136
1137	/** The CPU vendor. */
1138	CPUMCPUVENDOR enmCpuVendor;
1139	/** @} */
1140
1141	/** @name Host CPU information.
1142	* @{ */
1143	/** The CPU vendor. */
1144	CPUMCPUVENDOR enmHostCpuVendor;
1145	/** @} */
1146
1147	/** Counts RDMSR \#GP(0) LogRel(). */
1148	uint8_t cLogRelRdMsr;
1149	/** Counts WRMSR \#GP(0) LogRel(). */
1150	uint8_t cLogRelWrMsr;
1151	/** Alignment padding. */
1152	uint8_t abAlignment9[46];
1153
1154	/** @name Recompilation
1155	* @{ */
1156	/** Pointer to the current translation block.
1157	* This can either be one being executed or one being compiled. */
1158	R3PTRTYPE(PIEMTB) pCurTbR3;
1159	/** The PC (RIP) at the start of pCurTbR3/pCurTbR0.
1160	* The TBs are based on physical addresses, so this is needed to correleated
1161	* RIP to opcode bytes stored in the TB (AMD-V / VT-x). */
1162	uint64_t uCurTbStartPc;
1163	/** Statistics: Number of TB allocation calls. */
1164	uint64_t cTbAllocs;
1165	/** Statistics: Number of TB free calls. */
1166	uint64_t cTbFrees;
1167	/** Statistics: Number of TB lookup misses. */
1168	uint64_t cTbLookupMisses;
1169	/** Statistics: Number of TB lookup hits (debug only). */
1170	uint64_t cTbLookupHits;
1171	/** Number of TBs executed. */
1172	uint64_t cTbExec;
1173	/** Whether we need to check the opcode bytes for the current instruction.
1174	* This is set by a previous instruction if it modified memory or similar. */
1175	bool fTbCheckOpcodes;
1176	/** Indicates whether and how we just branched - IEMBRANCHED_F_XXX. */
1177	uint8_t fTbBranched;
1178	/** Set when GCPhysInstrBuf is updated because of a page crossing. */
1179	bool fTbCrossedPage;
1180	/** Whether to end the current TB. */
1181	bool fEndTb;
1182	/** Number of instructions before we need emit an IRQ check call again.
1183	* This helps making sure we don't execute too long w/o checking for
1184	* interrupts and immediately following instructions that may enable
1185	* interrupts (e.g. POPF, IRET, STI). With STI an additional hack is
1186	* required to make sure we check following the next instruction as well, see
1187	* fTbCurInstrIsSti. */
1188	uint8_t cInstrTillIrqCheck;
1189	/** Indicates that the current instruction is an STI. This is set by the
1190	* iemCImpl_sti code and subsequently cleared by the recompiler. */
1191	bool fTbCurInstrIsSti;
1192	/** Spaced reserved for recompiler data / alignment. */
1193	bool afRecompilerStuff1[2];
1194	/** Previous GCPhysInstrBuf value - only valid if fTbCrossedPage is set. */
1195	RTGCPHYS GCPhysInstrBufPrev;
1196	/** Copy of IEMCPU::GCPhysInstrBuf after decoding a branch instruction.
1197	* This is used together with fTbBranched and GCVirtTbBranchSrcBuf to determin
1198	* whether a branch instruction jumps to a new page or stays within the
1199	* current one. */
1200	RTGCPHYS GCPhysTbBranchSrcBuf;
1201	/** Copy of IEMCPU::uInstrBufPc after decoding a branch instruction. */
1202	uint64_t GCVirtTbBranchSrcBuf;
1203	/* Alignment. */
1204	/** Statistics: Times TB execution was broken off before reaching the end. */
1205	STAMCOUNTER StatTbExecBreaks;
1206	/** Statistics: Times BltIn_CheckIrq breaks out of the TB. */
1207	STAMCOUNTER StatCheckIrqBreaks;
1208	/** Statistics: Times BltIn_CheckMode breaks out of the TB. */
1209	STAMCOUNTER StatCheckModeBreaks;
1210	/** Statistics: Times a post jump target check missed and had to find new TB. */
1211	STAMCOUNTER StatCheckBranchMisses;
1212	/** Statistics: Times a jump or page crossing required a TB with CS.LIM checking. */
1213	STAMCOUNTER StatCheckNeedCsLimChecking;
1214	/** Threaded TB statistics: Number of instructions per TB. */
1215	STAMPROFILE StatTbThreadedInstr;
1216	/** Threaded TB statistics: Number of calls per TB. */
1217	STAMPROFILE StatTbThreadedCalls;
1218	/** @} */
1219
1220	/** Data TLB.
1221	* @remarks Must be 64-byte aligned. */
1222	IEMTLB DataTlb;
1223	/** Instruction TLB.
1224	* @remarks Must be 64-byte aligned. */
1225	IEMTLB CodeTlb;
1226
1227	/** Exception statistics. */
1228	STAMCOUNTER aStatXcpts[32];
1229	/** Interrupt statistics. */
1230	uint32_t aStatInts[256];
1231
1232	#if defined(VBOX_WITH_STATISTICS) && !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
1233	/** Instruction statistics for ring-0/raw-mode. */
1234	IEMINSTRSTATS StatsRZ;
1235	/** Instruction statistics for ring-3. */
1236	IEMINSTRSTATS StatsR3;
1237	#endif
1238	} IEMCPU;
1239	AssertCompileMemberOffset(IEMCPU, cActiveMappings, 0x4f);
1240	AssertCompileMemberAlignment(IEMCPU, aMemMappings, 16);
1241	AssertCompileMemberAlignment(IEMCPU, aMemMappingLocks, 16);
1242	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 64);
1243	AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
1244	AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
1245
1246	/** Pointer to the per-CPU IEM state. */
1247	typedef IEMCPU *PIEMCPU;
1248	/** Pointer to the const per-CPU IEM state. */
1249	typedef IEMCPU const *PCIEMCPU;
1250
1251
1252	/** @def IEM_GET_CTX
1253	* Gets the guest CPU context for the calling EMT.
1254	* @returns PCPUMCTX
1255	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1256	*/
1257	#define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
1258
1259	/** @def IEM_CTX_ASSERT
1260	* Asserts that the @a a_fExtrnMbz is present in the CPU context.
1261	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1262	* @param a_fExtrnMbz The mask of CPUMCTX_EXTRN_XXX flags that must be zero.
1263	*/
1264	#define IEM_CTX_ASSERT(a_pVCpu, a_fExtrnMbz) AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
1265	("fExtrn=%#RX64 fExtrnMbz=%#RX64\n", (a_pVCpu)->cpum.GstCtx.fExtrn, \
1266	(a_fExtrnMbz)))
1267
1268	/** @def IEM_CTX_IMPORT_RET
1269	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
1270	*
1271	* Will call the keep to import the bits as needed.
1272	*
1273	* Returns on import failure.
1274	*
1275	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1276	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
1277	*/
1278	#define IEM_CTX_IMPORT_RET(a_pVCpu, a_fExtrnImport) \
1279	do { \
1280	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
1281	{ /* likely */ } \
1282	else \
1283	{ \
1284	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
1285	AssertRCReturn(rcCtxImport, rcCtxImport); \
1286	} \
1287	} while (0)
1288
1289	/** @def IEM_CTX_IMPORT_NORET
1290	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
1291	*
1292	* Will call the keep to import the bits as needed.
1293	*
1294	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1295	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
1296	*/
1297	#define IEM_CTX_IMPORT_NORET(a_pVCpu, a_fExtrnImport) \
1298	do { \
1299	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
1300	{ /* likely */ } \
1301	else \
1302	{ \
1303	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
1304	AssertLogRelRC(rcCtxImport); \
1305	} \
1306	} while (0)
1307
1308	/** @def IEM_CTX_IMPORT_JMP
1309	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
1310	*
1311	* Will call the keep to import the bits as needed.
1312	*
1313	* Jumps on import failure.
1314	*
1315	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1316	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
1317	*/
1318	#define IEM_CTX_IMPORT_JMP(a_pVCpu, a_fExtrnImport) \
1319	do { \
1320	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
1321	{ /* likely */ } \
1322	else \
1323	{ \
1324	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
1325	AssertRCStmt(rcCtxImport, IEM_DO_LONGJMP(pVCpu, rcCtxImport)); \
1326	} \
1327	} while (0)
1328
1329
1330
1331	/** @def IEM_GET_TARGET_CPU
1332	* Gets the current IEMTARGETCPU value.
1333	* @returns IEMTARGETCPU value.
1334	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1335	*/
1336	#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
1337	# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
1338	#else
1339	# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
1340	#endif
1341
1342	/** @def IEM_GET_INSTR_LEN
1343	* Gets the instruction length. */
1344	#ifdef IEM_WITH_CODE_TLB
1345	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
1346	#else
1347	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
1348	#endif
1349
1350	/** @def IEM_TRY_SETJMP
1351	* Wrapper around setjmp / try, hiding all the ugly differences.
1352	*
1353	* @note Use with extreme care as this is a fragile macro.
1354	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
1355	* @param a_rcTarget The variable that should receive the status code in case
1356	* of a longjmp/throw.
1357	*/
1358	/** @def IEM_TRY_SETJMP_AGAIN
1359	* For when setjmp / try is used again in the same variable scope as a previous
1360	* IEM_TRY_SETJMP invocation.
1361	*/
1362	/** @def IEM_CATCH_LONGJMP_BEGIN
1363	* Start wrapper for catch / setjmp-else.
1364	*
1365	* This will set up a scope.
1366	*
1367	* @note Use with extreme care as this is a fragile macro.
1368	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
1369	* @param a_rcTarget The variable that should receive the status code in case
1370	* of a longjmp/throw.
1371	*/
1372	/** @def IEM_CATCH_LONGJMP_END
1373	* End wrapper for catch / setjmp-else.
1374	*
1375	* This will close the scope set up by IEM_CATCH_LONGJMP_BEGIN and clean up the
1376	* state.
1377	*
1378	* @note Use with extreme care as this is a fragile macro.
1379	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
1380	*/
1381	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
1382	# ifdef IEM_WITH_THROW_CATCH
1383	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
1384	a_rcTarget = VINF_SUCCESS; \
1385	try
1386	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
1387	IEM_TRY_SETJMP(a_pVCpu, a_rcTarget)
1388	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
1389	catch (int rcThrown) \
1390	{ \
1391	a_rcTarget = rcThrown
1392	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
1393	} \
1394	((void)0)
1395	# else /* !IEM_WITH_THROW_CATCH */
1396	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
1397	jmp_buf JmpBuf; \
1398	jmp_buf * volatile pSavedJmpBuf = pVCpu->iem.s.CTX_SUFF(pJmpBuf); \
1399	pVCpu->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
1400	if ((rcStrict = setjmp(JmpBuf)) == 0)
1401	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
1402	pSavedJmpBuf = pVCpu->iem.s.CTX_SUFF(pJmpBuf); \
1403	pVCpu->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
1404	if ((rcStrict = setjmp(JmpBuf)) == 0)
1405	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
1406	else \
1407	{ \
1408	((void)0)
1409	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
1410	} \
1411	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = pSavedJmpBuf
1412	# endif /* !IEM_WITH_THROW_CATCH */
1413	#endif /* IEM_WITH_SETJMP */
1414
1415
1416	/**
1417	* Shared per-VM IEM data.
1418	*/
1419	typedef struct IEM
1420	{
1421	/** The VMX APIC-access page handler type. */
1422	PGMPHYSHANDLERTYPE hVmxApicAccessPage;
1423	#ifndef VBOX_WITHOUT_CPUID_HOST_CALL
1424	/** Set if the CPUID host call functionality is enabled. */
1425	bool fCpuIdHostCall;
1426	#endif
1427	} IEM;
1428
1429
1430
1431	/** @name IEM_ACCESS_XXX - Access details.
1432	* @{ */
1433	#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
1434	#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
1435	#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
1436	#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
1437	#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
1438	#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
1439	#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
1440	#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
1441	#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
1442	#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
1443	/** The writes are partial, so if initialize the bounce buffer with the
1444	* orignal RAM content. */
1445	#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
1446	/** Used in aMemMappings to indicate that the entry is bounce buffered. */
1447	#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
1448	/** Bounce buffer with ring-3 write pending, first page. */
1449	#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
1450	/** Bounce buffer with ring-3 write pending, second page. */
1451	#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
1452	/** Not locked, accessed via the TLB. */
1453	#define IEM_ACCESS_NOT_LOCKED UINT32_C(0x00001000)
1454	/** Valid bit mask. */
1455	#define IEM_ACCESS_VALID_MASK UINT32_C(0x00001fff)
1456	/** Shift count for the TLB flags (upper word). */
1457	#define IEM_ACCESS_SHIFT_TLB_FLAGS 16
1458
1459	/** Read+write data alias. */
1460	#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
1461	/** Write data alias. */
1462	#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
1463	/** Read data alias. */
1464	#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_DATA)
1465	/** Instruction fetch alias. */
1466	#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_WHAT_CODE)
1467	/** Stack write alias. */
1468	#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
1469	/** Stack read alias. */
1470	#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_STACK)
1471	/** Stack read+write alias. */
1472	#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
1473	/** Read system table alias. */
1474	#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_SYS)
1475	/** Read+write system table alias. */
1476	#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_SYS)
1477	/** @} */
1478
1479	/** @name Prefix constants (IEMCPU::fPrefixes)
1480	* @{ */
1481	#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /*< CS segment prefix (0x2e). /
1482	#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /*< SS segment prefix (0x36). /
1483	#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /*< DS segment prefix (0x3e). /
1484	#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /*< ES segment prefix (0x26). /
1485	#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /*< FS segment prefix (0x64). /
1486	#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /*< GS segment prefix (0x65). /
1487	#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
1488
1489	#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /*< Operand size prefix (0x66). /
1490	#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /*< REX.W prefix (0x48-0x4f). /
1491	#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /*< Address size prefix (0x67). /
1492
1493	#define IEM_OP_PRF_LOCK RT_BIT_32(16) /*< Lock prefix (0xf0). /
1494	#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /*< Repeat-not-zero prefix (0xf2). /
1495	#define IEM_OP_PRF_REPZ RT_BIT_32(18) /*< Repeat-if-zero prefix (0xf3). /
1496
1497	#define IEM_OP_PRF_REX RT_BIT_32(24) /*< Any REX prefix (0x40-0x4f). /
1498	#define IEM_OP_PRF_REX_R RT_BIT_32(25) /*< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). /
1499	#define IEM_OP_PRF_REX_B RT_BIT_32(26) /*< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). /
1500	#define IEM_OP_PRF_REX_X RT_BIT_32(27) /*< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). /
1501	/** Mask with all the REX prefix flags.
1502	* This is generally for use when needing to undo the REX prefixes when they
1503	* are followed legacy prefixes and therefore does not immediately preceed
1504	* the first opcode byte.
1505	* For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
1506	#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX \| IEM_OP_PRF_REX_R \| IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X \| IEM_OP_PRF_SIZE_REX_W )
1507
1508	#define IEM_OP_PRF_VEX RT_BIT_32(28) /*< Indiciates VEX prefix. /
1509	#define IEM_OP_PRF_EVEX RT_BIT_32(29) /*< Indiciates EVEX prefix. /
1510	#define IEM_OP_PRF_XOP RT_BIT_32(30) /*< Indiciates XOP prefix. /
1511	/** @} */
1512
1513	/** @name IEMOPFORM_XXX - Opcode forms
1514	* @note These are ORed together with IEMOPHINT_XXX.
1515	* @{ */
1516	/** ModR/M: reg, r/m */
1517	#define IEMOPFORM_RM 0
1518	/** ModR/M: reg, r/m (register) */
1519	#define IEMOPFORM_RM_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
1520	/** ModR/M: reg, r/m (memory) */
1521	#define IEMOPFORM_RM_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
1522	/** ModR/M: reg, r/m */
1523	#define IEMOPFORM_RMI 1
1524	/** ModR/M: reg, r/m (register) */
1525	#define IEMOPFORM_RMI_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
1526	/** ModR/M: reg, r/m (memory) */
1527	#define IEMOPFORM_RMI_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
1528	/** ModR/M: r/m, reg */
1529	#define IEMOPFORM_MR 2
1530	/** ModR/M: r/m (register), reg */
1531	#define IEMOPFORM_MR_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
1532	/** ModR/M: r/m (memory), reg */
1533	#define IEMOPFORM_MR_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
1534	/** ModR/M: r/m, reg */
1535	#define IEMOPFORM_MRI 3
1536	/** ModR/M: r/m (register), reg */
1537	#define IEMOPFORM_MRI_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
1538	/** ModR/M: r/m (memory), reg */
1539	#define IEMOPFORM_MRI_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
1540	/** ModR/M: r/m only */
1541	#define IEMOPFORM_M 4
1542	/** ModR/M: r/m only (register). */
1543	#define IEMOPFORM_M_REG (IEMOPFORM_M \| IEMOPFORM_MOD3)
1544	/** ModR/M: r/m only (memory). */
1545	#define IEMOPFORM_M_MEM (IEMOPFORM_M \| IEMOPFORM_NOT_MOD3)
1546	/** ModR/M: reg only */
1547	#define IEMOPFORM_R 5
1548
1549	/** VEX+ModR/M: reg, r/m */
1550	#define IEMOPFORM_VEX_RM 8
1551	/** VEX+ModR/M: reg, r/m (register) */
1552	#define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM \| IEMOPFORM_MOD3)
1553	/** VEX+ModR/M: reg, r/m (memory) */
1554	#define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM \| IEMOPFORM_NOT_MOD3)
1555	/** VEX+ModR/M: r/m, reg */
1556	#define IEMOPFORM_VEX_MR 9
1557	/** VEX+ModR/M: r/m (register), reg */
1558	#define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR \| IEMOPFORM_MOD3)
1559	/** VEX+ModR/M: r/m (memory), reg */
1560	#define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR \| IEMOPFORM_NOT_MOD3)
1561	/** VEX+ModR/M: r/m only */
1562	#define IEMOPFORM_VEX_M 10
1563	/** VEX+ModR/M: r/m only (register). */
1564	#define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M \| IEMOPFORM_MOD3)
1565	/** VEX+ModR/M: r/m only (memory). */
1566	#define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M \| IEMOPFORM_NOT_MOD3)
1567	/** VEX+ModR/M: reg only */
1568	#define IEMOPFORM_VEX_R 11
1569	/** VEX+ModR/M: reg, vvvv, r/m */
1570	#define IEMOPFORM_VEX_RVM 12
1571	/** VEX+ModR/M: reg, vvvv, r/m (register). */
1572	#define IEMOPFORM_VEX_RVM_REG (IEMOPFORM_VEX_RVM \| IEMOPFORM_MOD3)
1573	/** VEX+ModR/M: reg, vvvv, r/m (memory). */
1574	#define IEMOPFORM_VEX_RVM_MEM (IEMOPFORM_VEX_RVM \| IEMOPFORM_NOT_MOD3)
1575	/** VEX+ModR/M: reg, r/m, vvvv */
1576	#define IEMOPFORM_VEX_RMV 13
1577	/** VEX+ModR/M: reg, r/m, vvvv (register). */
1578	#define IEMOPFORM_VEX_RMV_REG (IEMOPFORM_VEX_RMV \| IEMOPFORM_MOD3)
1579	/** VEX+ModR/M: reg, r/m, vvvv (memory). */
1580	#define IEMOPFORM_VEX_RMV_MEM (IEMOPFORM_VEX_RMV \| IEMOPFORM_NOT_MOD3)
1581	/** VEX+ModR/M: reg, r/m, imm8 */
1582	#define IEMOPFORM_VEX_RMI 14
1583	/** VEX+ModR/M: reg, r/m, imm8 (register). */
1584	#define IEMOPFORM_VEX_RMI_REG (IEMOPFORM_VEX_RMI \| IEMOPFORM_MOD3)
1585	/** VEX+ModR/M: reg, r/m, imm8 (memory). */
1586	#define IEMOPFORM_VEX_RMI_MEM (IEMOPFORM_VEX_RMI \| IEMOPFORM_NOT_MOD3)
1587	/** VEX+ModR/M: r/m, vvvv, reg */
1588	#define IEMOPFORM_VEX_MVR 15
1589	/** VEX+ModR/M: r/m, vvvv, reg (register) */
1590	#define IEMOPFORM_VEX_MVR_REG (IEMOPFORM_VEX_MVR \| IEMOPFORM_MOD3)
1591	/** VEX+ModR/M: r/m, vvvv, reg (memory) */
1592	#define IEMOPFORM_VEX_MVR_MEM (IEMOPFORM_VEX_MVR \| IEMOPFORM_NOT_MOD3)
1593	/** VEX+ModR/M+/n: vvvv, r/m */
1594	#define IEMOPFORM_VEX_VM 16
1595	/** VEX+ModR/M+/n: vvvv, r/m (register) */
1596	#define IEMOPFORM_VEX_VM_REG (IEMOPFORM_VEX_VM \| IEMOPFORM_MOD3)
1597	/** VEX+ModR/M+/n: vvvv, r/m (memory) */
1598	#define IEMOPFORM_VEX_VM_MEM (IEMOPFORM_VEX_VM \| IEMOPFORM_NOT_MOD3)
1599
1600	/** Fixed register instruction, no R/M. */
1601	#define IEMOPFORM_FIXED 32
1602
1603	/** The r/m is a register. */
1604	#define IEMOPFORM_MOD3 RT_BIT_32(8)
1605	/** The r/m is a memory access. */
1606	#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
1607	/** @} */
1608
1609	/** @name IEMOPHINT_XXX - Additional Opcode Hints
1610	* @note These are ORed together with IEMOPFORM_XXX.
1611	* @{ */
1612	/** Ignores the operand size prefix (66h). */
1613	#define IEMOPHINT_IGNORES_OZ_PFX RT_BIT_32(10)
1614	/** Ignores REX.W (aka WIG). */
1615	#define IEMOPHINT_IGNORES_REXW RT_BIT_32(11)
1616	/** Both the operand size prefixes (66h + REX.W) are ignored. */
1617	#define IEMOPHINT_IGNORES_OP_SIZES (IEMOPHINT_IGNORES_OZ_PFX \| IEMOPHINT_IGNORES_REXW)
1618	/** Allowed with the lock prefix. */
1619	#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
1620	/** The VEX.L value is ignored (aka LIG). */
1621	#define IEMOPHINT_VEX_L_IGNORED RT_BIT_32(12)
1622	/** The VEX.L value must be zero (i.e. 128-bit width only). */
1623	#define IEMOPHINT_VEX_L_ZERO RT_BIT_32(13)
1624	/** The VEX.V value must be zero. */
1625	#define IEMOPHINT_VEX_V_ZERO RT_BIT_32(14)
1626
1627	/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
1628	#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
1629	/** @} */
1630
1631	/**
1632	* Possible hardware task switch sources.
1633	*/
1634	typedef enum IEMTASKSWITCH
1635	{
1636	/** Task switch caused by an interrupt/exception. */
1637	IEMTASKSWITCH_INT_XCPT = 1,
1638	/** Task switch caused by a far CALL. */
1639	IEMTASKSWITCH_CALL,
1640	/** Task switch caused by a far JMP. */
1641	IEMTASKSWITCH_JUMP,
1642	/** Task switch caused by an IRET. */
1643	IEMTASKSWITCH_IRET
1644	} IEMTASKSWITCH;
1645	AssertCompileSize(IEMTASKSWITCH, 4);
1646
1647	/**
1648	* Possible CrX load (write) sources.
1649	*/
1650	typedef enum IEMACCESSCRX
1651	{
1652	/** CrX access caused by 'mov crX' instruction. */
1653	IEMACCESSCRX_MOV_CRX,
1654	/** CrX (CR0) write caused by 'lmsw' instruction. */
1655	IEMACCESSCRX_LMSW,
1656	/** CrX (CR0) write caused by 'clts' instruction. */
1657	IEMACCESSCRX_CLTS,
1658	/** CrX (CR0) read caused by 'smsw' instruction. */
1659	IEMACCESSCRX_SMSW
1660	} IEMACCESSCRX;
1661
1662	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1663	/** @name IEM_SLAT_FAIL_XXX - Second-level address translation failure information.
1664	*
1665	* These flags provide further context to SLAT page-walk failures that could not be
1666	* determined by PGM (e.g, PGM is not privy to memory access permissions).
1667	*
1668	* @{
1669	*/
1670	/** Translating a nested-guest linear address failed accessing a nested-guest
1671	* physical address. */
1672	# define IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR RT_BIT_32(0)
1673	/** Translating a nested-guest linear address failed accessing a
1674	* paging-structure entry or updating accessed/dirty bits. */
1675	# define IEM_SLAT_FAIL_LINEAR_TO_PAGE_TABLE RT_BIT_32(1)
1676	/** @} */
1677
1678	DECLCALLBACK(FNPGMPHYSHANDLER) iemVmxApicAccessPageHandler;
1679	# ifndef IN_RING3
1680	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) iemVmxApicAccessPagePfHandler;
1681	# endif
1682	#endif
1683
1684	/**
1685	* Indicates to the verifier that the given flag set is undefined.
1686	*
1687	* Can be invoked again to add more flags.
1688	*
1689	* This is a NOOP if the verifier isn't compiled in.
1690	*
1691	* @note We're temporarily keeping this until code is converted to new
1692	* disassembler style opcode handling.
1693	*/
1694	#define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
1695
1696
1697	/** @def IEM_DECL_IMPL_TYPE
1698	* For typedef'ing an instruction implementation function.
1699	*
1700	* @param a_RetType The return type.
1701	* @param a_Name The name of the type.
1702	* @param a_ArgList The argument list enclosed in parentheses.
1703	*/
1704
1705	/** @def IEM_DECL_IMPL_DEF
1706	* For defining an instruction implementation function.
1707	*
1708	* @param a_RetType The return type.
1709	* @param a_Name The name of the type.
1710	* @param a_ArgList The argument list enclosed in parentheses.
1711	*/
1712
1713	#if defined(__GNUC__) && defined(RT_ARCH_X86)
1714	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1715	__attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
1716	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1717	__attribute__((__fastcall__, __nothrow__)) DECL_HIDDEN_ONLY(a_RetType) a_Name a_ArgList
1718	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1719	__attribute__((__fastcall__, __nothrow__)) DECL_HIDDEN_ONLY(a_RetType) a_Name a_ArgList
1720
1721	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
1722	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1723	a_RetType (__fastcall a_Name) a_ArgList
1724	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1725	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
1726	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1727	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
1728
1729	#elif __cplusplus >= 201700 /* P0012R1 support */
1730	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1731	a_RetType (VBOXCALL a_Name) a_ArgList RT_NOEXCEPT
1732	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1733	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList RT_NOEXCEPT
1734	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1735	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList RT_NOEXCEPT
1736
1737	#else
1738	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1739	a_RetType (VBOXCALL a_Name) a_ArgList
1740	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1741	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList
1742	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1743	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList
1744
1745	#endif
1746
1747	/** Defined in IEMAllAImplC.cpp but also used by IEMAllAImplA.asm. */
1748	RT_C_DECLS_BEGIN
1749	extern uint8_t const g_afParity[256];
1750	RT_C_DECLS_END
1751
1752
1753	/** @name Arithmetic assignment operations on bytes (binary).
1754	* @{ */
1755	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU8, (uint8_t pu8Dst, uint8_t u8Src, uint32_t pEFlags));
1756	typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
1757	FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
1758	FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
1759	FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
1760	FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
1761	FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
1762	FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
1763	FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
1764	/** @} */
1765
1766	/** @name Arithmetic assignment operations on words (binary).
1767	* @{ */
1768	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU16, (uint16_t pu16Dst, uint16_t u16Src, uint32_t pEFlags));
1769	typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
1770	FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
1771	FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
1772	FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
1773	FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
1774	FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
1775	FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
1776	FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
1777	/** @} */
1778
1779	/** @name Arithmetic assignment operations on double words (binary).
1780	* @{ */
1781	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU32, (uint32_t pu32Dst, uint32_t u32Src, uint32_t pEFlags));
1782	typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
1783	FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
1784	FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
1785	FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
1786	FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
1787	FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
1788	FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
1789	FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
1790	FNIEMAIMPLBINU32 iemAImpl_blsi_u32, iemAImpl_blsi_u32_fallback;
1791	FNIEMAIMPLBINU32 iemAImpl_blsr_u32, iemAImpl_blsr_u32_fallback;
1792	FNIEMAIMPLBINU32 iemAImpl_blsmsk_u32, iemAImpl_blsmsk_u32_fallback;
1793	/** @} */
1794
1795	/** @name Arithmetic assignment operations on quad words (binary).
1796	* @{ */
1797	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU64, (uint64_t pu64Dst, uint64_t u64Src, uint32_t pEFlags));
1798	typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
1799	FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
1800	FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
1801	FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
1802	FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
1803	FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
1804	FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
1805	FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
1806	FNIEMAIMPLBINU64 iemAImpl_blsi_u64, iemAImpl_blsi_u64_fallback;
1807	FNIEMAIMPLBINU64 iemAImpl_blsr_u64, iemAImpl_blsr_u64_fallback;
1808	FNIEMAIMPLBINU64 iemAImpl_blsmsk_u64, iemAImpl_blsmsk_u64_fallback;
1809	/** @} */
1810
1811	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINROU8,(uint8_t const pu8Dst, uint8_t u8Src, uint32_t pEFlags));
1812	typedef FNIEMAIMPLBINROU8 *PFNIEMAIMPLBINROU8;
1813	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINROU16,(uint16_t const pu16Dst, uint16_t u16Src, uint32_t pEFlags));
1814	typedef FNIEMAIMPLBINROU16 *PFNIEMAIMPLBINROU16;
1815	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINROU32,(uint32_t const pu32Dst, uint32_t u32Src, uint32_t pEFlags));
1816	typedef FNIEMAIMPLBINROU32 *PFNIEMAIMPLBINROU32;
1817	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINROU64,(uint64_t const pu64Dst, uint64_t u64Src, uint32_t pEFlags));
1818	typedef FNIEMAIMPLBINROU64 *PFNIEMAIMPLBINROU64;
1819
1820	/** @name Compare operations (thrown in with the binary ops).
1821	* @{ */
1822	FNIEMAIMPLBINROU8 iemAImpl_cmp_u8;
1823	FNIEMAIMPLBINROU16 iemAImpl_cmp_u16;
1824	FNIEMAIMPLBINROU32 iemAImpl_cmp_u32;
1825	FNIEMAIMPLBINROU64 iemAImpl_cmp_u64;
1826	/** @} */
1827
1828	/** @name Test operations (thrown in with the binary ops).
1829	* @{ */
1830	FNIEMAIMPLBINROU8 iemAImpl_test_u8;
1831	FNIEMAIMPLBINROU16 iemAImpl_test_u16;
1832	FNIEMAIMPLBINROU32 iemAImpl_test_u32;
1833	FNIEMAIMPLBINROU64 iemAImpl_test_u64;
1834	/** @} */
1835
1836	/** @name Bit operations operations (thrown in with the binary ops).
1837	* @{ */
1838	FNIEMAIMPLBINROU16 iemAImpl_bt_u16;
1839	FNIEMAIMPLBINROU32 iemAImpl_bt_u32;
1840	FNIEMAIMPLBINROU64 iemAImpl_bt_u64;
1841	FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
1842	FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
1843	FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
1844	FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
1845	FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
1846	FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
1847	FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
1848	FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
1849	FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
1850	/** @} */
1851
1852	/** @name Arithmetic three operand operations on double words (binary).
1853	* @{ */
1854	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32, (uint32_t pu32Dst, uint32_t u32Src1, uint32_t u32Src2, uint32_t pEFlags));
1855	typedef FNIEMAIMPLBINVEXU32 *PFNIEMAIMPLBINVEXU32;
1856	FNIEMAIMPLBINVEXU32 iemAImpl_andn_u32, iemAImpl_andn_u32_fallback;
1857	FNIEMAIMPLBINVEXU32 iemAImpl_bextr_u32, iemAImpl_bextr_u32_fallback;
1858	FNIEMAIMPLBINVEXU32 iemAImpl_bzhi_u32, iemAImpl_bzhi_u32_fallback;
1859	/** @} */
1860
1861	/** @name Arithmetic three operand operations on quad words (binary).
1862	* @{ */
1863	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64, (uint64_t pu64Dst, uint64_t u64Src1, uint64_t u64Src2, uint32_t pEFlags));
1864	typedef FNIEMAIMPLBINVEXU64 *PFNIEMAIMPLBINVEXU64;
1865	FNIEMAIMPLBINVEXU64 iemAImpl_andn_u64, iemAImpl_andn_u64_fallback;
1866	FNIEMAIMPLBINVEXU64 iemAImpl_bextr_u64, iemAImpl_bextr_u64_fallback;
1867	FNIEMAIMPLBINVEXU64 iemAImpl_bzhi_u64, iemAImpl_bzhi_u64_fallback;
1868	/** @} */
1869
1870	/** @name Arithmetic three operand operations on double words w/o EFLAGS (binary).
1871	* @{ */
1872	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32NOEFL, (uint32_t *pu32Dst, uint32_t u32Src1, uint32_t u32Src2));
1873	typedef FNIEMAIMPLBINVEXU32NOEFL *PFNIEMAIMPLBINVEXU32NOEFL;
1874	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pdep_u32, iemAImpl_pdep_u32_fallback;
1875	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pext_u32, iemAImpl_pext_u32_fallback;
1876	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_sarx_u32, iemAImpl_sarx_u32_fallback;
1877	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shlx_u32, iemAImpl_shlx_u32_fallback;
1878	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shrx_u32, iemAImpl_shrx_u32_fallback;
1879	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_rorx_u32;
1880	/** @} */
1881
1882	/** @name Arithmetic three operand operations on quad words w/o EFLAGS (binary).
1883	* @{ */
1884	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64NOEFL, (uint64_t *pu64Dst, uint64_t u64Src1, uint64_t u64Src2));
1885	typedef FNIEMAIMPLBINVEXU64NOEFL *PFNIEMAIMPLBINVEXU64NOEFL;
1886	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pdep_u64, iemAImpl_pdep_u64_fallback;
1887	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pext_u64, iemAImpl_pext_u64_fallback;
1888	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_sarx_u64, iemAImpl_sarx_u64_fallback;
1889	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shlx_u64, iemAImpl_shlx_u64_fallback;
1890	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shrx_u64, iemAImpl_shrx_u64_fallback;
1891	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_rorx_u64;
1892	/** @} */
1893
1894	/** @name MULX 32-bit and 64-bit.
1895	* @{ */
1896	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU32, (uint32_t puDst1, uint32_t puDst2, uint32_t uSrc1, uint32_t uSrc2));
1897	typedef FNIEMAIMPLMULXVEXU32 *PFNIEMAIMPLMULXVEXU32;
1898	FNIEMAIMPLMULXVEXU32 iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback;
1899
1900	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU64, (uint64_t puDst1, uint64_t puDst2, uint64_t uSrc1, uint64_t uSrc2));
1901	typedef FNIEMAIMPLMULXVEXU64 *PFNIEMAIMPLMULXVEXU64;
1902	FNIEMAIMPLMULXVEXU64 iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback;
1903	/** @} */
1904
1905
1906	/** @name Exchange memory with register operations.
1907	* @{ */
1908	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_locked, (uint8_t pu8Mem, uint8_t pu8Reg));
1909	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_locked,(uint16_t pu16Mem, uint16_t pu16Reg));
1910	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_locked,(uint32_t pu32Mem, uint32_t pu32Reg));
1911	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_locked,(uint64_t pu64Mem, uint64_t pu64Reg));
1912	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_unlocked, (uint8_t pu8Mem, uint8_t pu8Reg));
1913	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_unlocked,(uint16_t pu16Mem, uint16_t pu16Reg));
1914	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_unlocked,(uint32_t pu32Mem, uint32_t pu32Reg));
1915	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_unlocked,(uint64_t pu64Mem, uint64_t pu64Reg));
1916	/** @} */
1917
1918	/** @name Exchange and add operations.
1919	* @{ */
1920	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1921	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1922	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1923	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1924	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1925	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1926	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1927	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1928	/** @} */
1929
1930	/** @name Compare and exchange.
1931	* @{ */
1932	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1933	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1934	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1935	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1936	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1937	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1938	#if ARCH_BITS == 32
1939	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1940	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1941	#else
1942	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1943	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1944	#endif
1945	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1946	uint32_t *pEFlags));
1947	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1948	uint32_t *pEFlags));
1949	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1950	uint32_t *pEFlags));
1951	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1952	uint32_t *pEFlags));
1953	#ifndef RT_ARCH_ARM64
1954	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
1955	PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
1956	#endif
1957	/** @} */
1958
1959	/** @name Memory ordering
1960	* @{ */
1961	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
1962	typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
1963	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
1964	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
1965	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
1966	#ifndef RT_ARCH_ARM64
1967	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
1968	#endif
1969	/** @} */
1970
1971	/** @name Double precision shifts
1972	* @{ */
1973	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t pEFlags));
1974	typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
1975	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t pEFlags));
1976	typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
1977	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t pEFlags));
1978	typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
1979	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16, iemAImpl_shld_u16_amd, iemAImpl_shld_u16_intel;
1980	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32, iemAImpl_shld_u32_amd, iemAImpl_shld_u32_intel;
1981	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64, iemAImpl_shld_u64_amd, iemAImpl_shld_u64_intel;
1982	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16, iemAImpl_shrd_u16_amd, iemAImpl_shrd_u16_intel;
1983	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32, iemAImpl_shrd_u32_amd, iemAImpl_shrd_u32_intel;
1984	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64, iemAImpl_shrd_u64_amd, iemAImpl_shrd_u64_intel;
1985	/** @} */
1986
1987
1988	/** @name Bit search operations (thrown in with the binary ops).
1989	* @{ */
1990	FNIEMAIMPLBINU16 iemAImpl_bsf_u16, iemAImpl_bsf_u16_amd, iemAImpl_bsf_u16_intel;
1991	FNIEMAIMPLBINU32 iemAImpl_bsf_u32, iemAImpl_bsf_u32_amd, iemAImpl_bsf_u32_intel;
1992	FNIEMAIMPLBINU64 iemAImpl_bsf_u64, iemAImpl_bsf_u64_amd, iemAImpl_bsf_u64_intel;
1993	FNIEMAIMPLBINU16 iemAImpl_bsr_u16, iemAImpl_bsr_u16_amd, iemAImpl_bsr_u16_intel;
1994	FNIEMAIMPLBINU32 iemAImpl_bsr_u32, iemAImpl_bsr_u32_amd, iemAImpl_bsr_u32_intel;
1995	FNIEMAIMPLBINU64 iemAImpl_bsr_u64, iemAImpl_bsr_u64_amd, iemAImpl_bsr_u64_intel;
1996	FNIEMAIMPLBINU16 iemAImpl_lzcnt_u16, iemAImpl_lzcnt_u16_amd, iemAImpl_lzcnt_u16_intel;
1997	FNIEMAIMPLBINU32 iemAImpl_lzcnt_u32, iemAImpl_lzcnt_u32_amd, iemAImpl_lzcnt_u32_intel;
1998	FNIEMAIMPLBINU64 iemAImpl_lzcnt_u64, iemAImpl_lzcnt_u64_amd, iemAImpl_lzcnt_u64_intel;
1999	FNIEMAIMPLBINU16 iemAImpl_tzcnt_u16, iemAImpl_tzcnt_u16_amd, iemAImpl_tzcnt_u16_intel;
2000	FNIEMAIMPLBINU32 iemAImpl_tzcnt_u32, iemAImpl_tzcnt_u32_amd, iemAImpl_tzcnt_u32_intel;
2001	FNIEMAIMPLBINU64 iemAImpl_tzcnt_u64, iemAImpl_tzcnt_u64_amd, iemAImpl_tzcnt_u64_intel;
2002	FNIEMAIMPLBINU16 iemAImpl_popcnt_u16, iemAImpl_popcnt_u16_fallback;
2003	FNIEMAIMPLBINU32 iemAImpl_popcnt_u32, iemAImpl_popcnt_u32_fallback;
2004	FNIEMAIMPLBINU64 iemAImpl_popcnt_u64, iemAImpl_popcnt_u64_fallback;
2005	/** @} */
2006
2007	/** @name Signed multiplication operations (thrown in with the binary ops).
2008	* @{ */
2009	FNIEMAIMPLBINU16 iemAImpl_imul_two_u16, iemAImpl_imul_two_u16_amd, iemAImpl_imul_two_u16_intel;
2010	FNIEMAIMPLBINU32 iemAImpl_imul_two_u32, iemAImpl_imul_two_u32_amd, iemAImpl_imul_two_u32_intel;
2011	FNIEMAIMPLBINU64 iemAImpl_imul_two_u64, iemAImpl_imul_two_u64_amd, iemAImpl_imul_two_u64_intel;
2012	/** @} */
2013
2014	/** @name Arithmetic assignment operations on bytes (unary).
2015	* @{ */
2016	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t pu8Dst, uint32_t pEFlags));
2017	typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
2018	FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
2019	FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
2020	FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
2021	FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
2022	/** @} */
2023
2024	/** @name Arithmetic assignment operations on words (unary).
2025	* @{ */
2026	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t pu16Dst, uint32_t pEFlags));
2027	typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
2028	FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
2029	FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
2030	FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
2031	FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
2032	/** @} */
2033
2034	/** @name Arithmetic assignment operations on double words (unary).
2035	* @{ */
2036	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t pu32Dst, uint32_t pEFlags));
2037	typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
2038	FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
2039	FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
2040	FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
2041	FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
2042	/** @} */
2043
2044	/** @name Arithmetic assignment operations on quad words (unary).
2045	* @{ */
2046	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t pu64Dst, uint32_t pEFlags));
2047	typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
2048	FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
2049	FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
2050	FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
2051	FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
2052	/** @} */
2053
2054
2055	/** @name Shift operations on bytes (Group 2).
2056	* @{ */
2057	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU8,(uint8_t pu8Dst, uint8_t cShift, uint32_t pEFlags));
2058	typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
2059	FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8, iemAImpl_rol_u8_amd, iemAImpl_rol_u8_intel;
2060	FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8, iemAImpl_ror_u8_amd, iemAImpl_ror_u8_intel;
2061	FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8, iemAImpl_rcl_u8_amd, iemAImpl_rcl_u8_intel;
2062	FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8, iemAImpl_rcr_u8_amd, iemAImpl_rcr_u8_intel;
2063	FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8, iemAImpl_shl_u8_amd, iemAImpl_shl_u8_intel;
2064	FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8, iemAImpl_shr_u8_amd, iemAImpl_shr_u8_intel;
2065	FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8, iemAImpl_sar_u8_amd, iemAImpl_sar_u8_intel;
2066	/** @} */
2067
2068	/** @name Shift operations on words (Group 2).
2069	* @{ */
2070	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU16,(uint16_t pu16Dst, uint8_t cShift, uint32_t pEFlags));
2071	typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
2072	FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16, iemAImpl_rol_u16_amd, iemAImpl_rol_u16_intel;
2073	FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16, iemAImpl_ror_u16_amd, iemAImpl_ror_u16_intel;
2074	FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16, iemAImpl_rcl_u16_amd, iemAImpl_rcl_u16_intel;
2075	FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16, iemAImpl_rcr_u16_amd, iemAImpl_rcr_u16_intel;
2076	FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16, iemAImpl_shl_u16_amd, iemAImpl_shl_u16_intel;
2077	FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16, iemAImpl_shr_u16_amd, iemAImpl_shr_u16_intel;
2078	FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16, iemAImpl_sar_u16_amd, iemAImpl_sar_u16_intel;
2079	/** @} */
2080
2081	/** @name Shift operations on double words (Group 2).
2082	* @{ */
2083	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU32,(uint32_t pu32Dst, uint8_t cShift, uint32_t pEFlags));
2084	typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
2085	FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32, iemAImpl_rol_u32_amd, iemAImpl_rol_u32_intel;
2086	FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32, iemAImpl_ror_u32_amd, iemAImpl_ror_u32_intel;
2087	FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32, iemAImpl_rcl_u32_amd, iemAImpl_rcl_u32_intel;
2088	FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32, iemAImpl_rcr_u32_amd, iemAImpl_rcr_u32_intel;
2089	FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32, iemAImpl_shl_u32_amd, iemAImpl_shl_u32_intel;
2090	FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32, iemAImpl_shr_u32_amd, iemAImpl_shr_u32_intel;
2091	FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32, iemAImpl_sar_u32_amd, iemAImpl_sar_u32_intel;
2092	/** @} */
2093
2094	/** @name Shift operations on words (Group 2).
2095	* @{ */
2096	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU64,(uint64_t pu64Dst, uint8_t cShift, uint32_t pEFlags));
2097	typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
2098	FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64, iemAImpl_rol_u64_amd, iemAImpl_rol_u64_intel;
2099	FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64, iemAImpl_ror_u64_amd, iemAImpl_ror_u64_intel;
2100	FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64, iemAImpl_rcl_u64_amd, iemAImpl_rcl_u64_intel;
2101	FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64, iemAImpl_rcr_u64_amd, iemAImpl_rcr_u64_intel;
2102	FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64, iemAImpl_shl_u64_amd, iemAImpl_shl_u64_intel;
2103	FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64, iemAImpl_shr_u64_amd, iemAImpl_shr_u64_intel;
2104	FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64, iemAImpl_sar_u64_amd, iemAImpl_sar_u64_intel;
2105	/** @} */
2106
2107	/** @name Multiplication and division operations.
2108	* @{ */
2109	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t pu16AX, uint8_t u8FactorDivisor, uint32_t pEFlags));
2110	typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
2111	FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_mul_u8_amd, iemAImpl_mul_u8_intel;
2112	FNIEMAIMPLMULDIVU8 iemAImpl_imul_u8, iemAImpl_imul_u8_amd, iemAImpl_imul_u8_intel;
2113	FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_div_u8_amd, iemAImpl_div_u8_intel;
2114	FNIEMAIMPLMULDIVU8 iemAImpl_idiv_u8, iemAImpl_idiv_u8_amd, iemAImpl_idiv_u8_intel;
2115
2116	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t pu16AX, uint16_t pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
2117	typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
2118	FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_mul_u16_amd, iemAImpl_mul_u16_intel;
2119	FNIEMAIMPLMULDIVU16 iemAImpl_imul_u16, iemAImpl_imul_u16_amd, iemAImpl_imul_u16_intel;
2120	FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_div_u16_amd, iemAImpl_div_u16_intel;
2121	FNIEMAIMPLMULDIVU16 iemAImpl_idiv_u16, iemAImpl_idiv_u16_amd, iemAImpl_idiv_u16_intel;
2122
2123	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t pu32EAX, uint32_t pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
2124	typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
2125	FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_mul_u32_amd, iemAImpl_mul_u32_intel;
2126	FNIEMAIMPLMULDIVU32 iemAImpl_imul_u32, iemAImpl_imul_u32_amd, iemAImpl_imul_u32_intel;
2127	FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_div_u32_amd, iemAImpl_div_u32_intel;
2128	FNIEMAIMPLMULDIVU32 iemAImpl_idiv_u32, iemAImpl_idiv_u32_amd, iemAImpl_idiv_u32_intel;
2129
2130	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t pu64RAX, uint64_t pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
2131	typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
2132	FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_mul_u64_amd, iemAImpl_mul_u64_intel;
2133	FNIEMAIMPLMULDIVU64 iemAImpl_imul_u64, iemAImpl_imul_u64_amd, iemAImpl_imul_u64_intel;
2134	FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_div_u64_amd, iemAImpl_div_u64_intel;
2135	FNIEMAIMPLMULDIVU64 iemAImpl_idiv_u64, iemAImpl_idiv_u64_amd, iemAImpl_idiv_u64_intel;
2136	/** @} */
2137
2138	/** @name Byte Swap.
2139	* @{ */
2140	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t pu32Dst)); / Yes, 32-bit register access. */
2141	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
2142	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
2143	/** @} */
2144
2145	/** @name Misc.
2146	* @{ */
2147	FNIEMAIMPLBINU16 iemAImpl_arpl;
2148	/** @} */
2149
2150	/** @name RDRAND and RDSEED
2151	* @{ */
2152	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU16,(uint16_t puDst, uint32_t pEFlags));
2153	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU32,(uint32_t puDst, uint32_t pEFlags));
2154	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU64,(uint64_t puDst, uint32_t pEFlags));
2155	typedef FNIEMAIMPLRDRANDSEEDU16 *FNIEMAIMPLPRDRANDSEEDU16;
2156	typedef FNIEMAIMPLRDRANDSEEDU32 *FNIEMAIMPLPRDRANDSEEDU32;
2157	typedef FNIEMAIMPLRDRANDSEEDU64 *FNIEMAIMPLPRDRANDSEEDU64;
2158
2159	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdrand_u16, iemAImpl_rdrand_u16_fallback;
2160	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdrand_u32, iemAImpl_rdrand_u32_fallback;
2161	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdrand_u64, iemAImpl_rdrand_u64_fallback;
2162	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdseed_u16, iemAImpl_rdseed_u16_fallback;
2163	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdseed_u32, iemAImpl_rdseed_u32_fallback;
2164	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdseed_u64, iemAImpl_rdseed_u64_fallback;
2165	/** @} */
2166
2167	/** @name ADOX and ADCX
2168	* @{ */
2169	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLADXU32,(uint32_t puDst, uint32_t pfEFlags, uint32_t uSrc));
2170	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLADXU64,(uint64_t puDst, uint32_t pfEFlags, uint64_t uSrc));
2171	typedef FNIEMAIMPLADXU32 *PFNIEMAIMPLADXU32;
2172	typedef FNIEMAIMPLADXU64 *PFNIEMAIMPLADXU64;
2173
2174	FNIEMAIMPLADXU32 iemAImpl_adcx_u32, iemAImpl_adcx_u32_fallback;
2175	FNIEMAIMPLADXU64 iemAImpl_adcx_u64, iemAImpl_adcx_u64_fallback;
2176	FNIEMAIMPLADXU32 iemAImpl_adox_u32, iemAImpl_adox_u32_fallback;
2177	FNIEMAIMPLADXU64 iemAImpl_adox_u64, iemAImpl_adox_u64_fallback;
2178	/** @} */
2179
2180	/** @name FPU operations taking a 32-bit float argument
2181	* @{ */
2182	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2183	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
2184	typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
2185
2186	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2187	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
2188	typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
2189
2190	FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
2191	FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
2192	FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
2193	FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
2194	FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
2195	FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
2196	FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
2197
2198	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
2199	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2200	PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
2201	/** @} */
2202
2203	/** @name FPU operations taking a 64-bit float argument
2204	* @{ */
2205	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2206	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
2207	typedef FNIEMAIMPLFPUR64FSW *PFNIEMAIMPLFPUR64FSW;
2208
2209	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2210	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
2211	typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
2212
2213	FNIEMAIMPLFPUR64FSW iemAImpl_fcom_r80_by_r64;
2214	FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
2215	FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
2216	FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
2217	FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
2218	FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
2219	FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
2220
2221	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
2222	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2223	PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
2224	/** @} */
2225
2226	/** @name FPU operations taking a 80-bit float argument
2227	* @{ */
2228	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2229	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
2230	typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
2231	FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
2232	FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
2233	FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
2234	FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
2235	FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
2236	FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
2237	FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
2238	FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
2239	FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
2240
2241	FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80, iemAImpl_fpatan_r80_by_r80_amd, iemAImpl_fpatan_r80_by_r80_intel;
2242	FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80, iemAImpl_fyl2x_r80_by_r80_amd, iemAImpl_fyl2x_r80_by_r80_intel;
2243	FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80, iemAImpl_fyl2xp1_r80_by_r80_amd, iemAImpl_fyl2xp1_r80_by_r80_intel;
2244
2245	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2246	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
2247	typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
2248	FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
2249	FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
2250
2251	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
2252	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
2253	typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
2254	FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
2255	FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
2256
2257	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
2258	typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
2259	FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
2260	FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
2261	FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80, iemAImpl_f2xm1_r80_amd, iemAImpl_f2xm1_r80_intel;
2262	FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
2263	FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
2264	FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80, iemAImpl_fsin_r80_amd, iemAImpl_fsin_r80_intel;
2265	FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80, iemAImpl_fcos_r80_amd, iemAImpl_fcos_r80_intel;
2266
2267	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
2268	typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
2269	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
2270	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
2271
2272	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
2273	typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
2274	FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
2275	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
2276	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
2277	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
2278	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
2279	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
2280	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
2281
2282	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
2283	PCRTFLOAT80U pr80Val));
2284	typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
2285	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80, iemAImpl_fptan_r80_r80_amd, iemAImpl_fptan_r80_r80_intel;
2286	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
2287	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80, iemAImpl_fsincos_r80_r80_amd, iemAImpl_fsincos_r80_r80_intel;
2288
2289	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
2290	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2291	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
2292
2293	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_d80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTPBCD80U pd80Val));
2294	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_d80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2295	PRTPBCD80U pd80Dst, PCRTFLOAT80U pr80Src));
2296
2297	/** @} */
2298
2299	/** @name FPU operations taking a 16-bit signed integer argument
2300	* @{ */
2301	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2302	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
2303	typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
2304	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI16,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
2305	int16_t *pi16Dst, PCRTFLOAT80U pr80Src));
2306	typedef FNIEMAIMPLFPUSTR80TOI16 *PFNIEMAIMPLFPUSTR80TOI16;
2307
2308	FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
2309	FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
2310	FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
2311	FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
2312	FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
2313	FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
2314
2315	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2316	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
2317	typedef FNIEMAIMPLFPUI16FSW *PFNIEMAIMPLFPUI16FSW;
2318	FNIEMAIMPLFPUI16FSW iemAImpl_ficom_r80_by_i16;
2319
2320	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
2321	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fist_r80_to_i16;
2322	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fistt_r80_to_i16, iemAImpl_fistt_r80_to_i16_amd, iemAImpl_fistt_r80_to_i16_intel;
2323	/** @} */
2324
2325	/** @name FPU operations taking a 32-bit signed integer argument
2326	* @{ */
2327	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2328	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
2329	typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
2330	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI32,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
2331	int32_t *pi32Dst, PCRTFLOAT80U pr80Src));
2332	typedef FNIEMAIMPLFPUSTR80TOI32 *PFNIEMAIMPLFPUSTR80TOI32;
2333
2334	FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
2335	FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
2336	FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
2337	FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
2338	FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
2339	FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
2340
2341	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2342	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
2343	typedef FNIEMAIMPLFPUI32FSW *PFNIEMAIMPLFPUI32FSW;
2344	FNIEMAIMPLFPUI32FSW iemAImpl_ficom_r80_by_i32;
2345
2346	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
2347	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fist_r80_to_i32;
2348	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fistt_r80_to_i32;
2349	/** @} */
2350
2351	/** @name FPU operations taking a 64-bit signed integer argument
2352	* @{ */
2353	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI64,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
2354	int64_t *pi64Dst, PCRTFLOAT80U pr80Src));
2355	typedef FNIEMAIMPLFPUSTR80TOI64 *PFNIEMAIMPLFPUSTR80TOI64;
2356
2357	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
2358	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fist_r80_to_i64;
2359	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fistt_r80_to_i64;
2360	/** @} */
2361
2362
2363	/** Temporary type representing a 256-bit vector register. */
2364	typedef struct { uint64_t au64[4]; } IEMVMM256;
2365	/** Temporary type pointing to a 256-bit vector register. */
2366	typedef IEMVMM256 *PIEMVMM256;
2367	/** Temporary type pointing to a const 256-bit vector register. */
2368	typedef IEMVMM256 *PCIEMVMM256;
2369
2370
2371	/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
2372	* @{ */
2373	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t puDst, uint64_t const puSrc));
2374	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
2375	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U128,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
2376	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
2377	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U128,(PX86XSAVEAREA pExtState, PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
2378	typedef FNIEMAIMPLMEDIAF3U128 *PFNIEMAIMPLMEDIAF3U128;
2379	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U256,(PX86XSAVEAREA pExtState, PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
2380	typedef FNIEMAIMPLMEDIAF3U256 *PFNIEMAIMPLMEDIAF3U256;
2381	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U64,(uint64_t puDst, uint64_t const puSrc));
2382	typedef FNIEMAIMPLMEDIAOPTF2U64 *PFNIEMAIMPLMEDIAOPTF2U64;
2383	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128,(PRTUINT128U puDst, PCRTUINT128U puSrc));
2384	typedef FNIEMAIMPLMEDIAOPTF2U128 *PFNIEMAIMPLMEDIAOPTF2U128;
2385	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
2386	typedef FNIEMAIMPLMEDIAOPTF3U128 *PFNIEMAIMPLMEDIAOPTF3U128;
2387	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
2388	typedef FNIEMAIMPLMEDIAOPTF3U256 *PFNIEMAIMPLMEDIAOPTF3U256;
2389	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256,(PRTUINT256U puDst, PCRTUINT256U puSrc));
2390	typedef FNIEMAIMPLMEDIAOPTF2U256 *PFNIEMAIMPLMEDIAOPTF2U256;
2391	FNIEMAIMPLMEDIAF2U64 iemAImpl_pshufb_u64, iemAImpl_pshufb_u64_fallback;
2392	FNIEMAIMPLMEDIAF2U64 iemAImpl_pand_u64, iemAImpl_pandn_u64, iemAImpl_por_u64, iemAImpl_pxor_u64;
2393	FNIEMAIMPLMEDIAF2U64 iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
2394	FNIEMAIMPLMEDIAF2U64 iemAImpl_pcmpgtb_u64, iemAImpl_pcmpgtw_u64, iemAImpl_pcmpgtd_u64;
2395	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddb_u64, iemAImpl_paddsb_u64, iemAImpl_paddusb_u64;
2396	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddw_u64, iemAImpl_paddsw_u64, iemAImpl_paddusw_u64;
2397	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddd_u64;
2398	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddq_u64;
2399	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubb_u64, iemAImpl_psubsb_u64, iemAImpl_psubusb_u64;
2400	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubw_u64, iemAImpl_psubsw_u64, iemAImpl_psubusw_u64;
2401	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubd_u64;
2402	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubq_u64;
2403	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmaddwd_u64;
2404	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmullw_u64, iemAImpl_pmulhw_u64;
2405	FNIEMAIMPLMEDIAF2U64 iemAImpl_pminub_u64, iemAImpl_pmaxub_u64;
2406	FNIEMAIMPLMEDIAF2U64 iemAImpl_pminsw_u64, iemAImpl_pmaxsw_u64;
2407	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsb_u64, iemAImpl_pabsb_u64_fallback;
2408	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsw_u64, iemAImpl_pabsw_u64_fallback;
2409	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsd_u64, iemAImpl_pabsd_u64_fallback;
2410	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignb_u64, iemAImpl_psignb_u64_fallback;
2411	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignw_u64, iemAImpl_psignw_u64_fallback;
2412	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignd_u64, iemAImpl_psignd_u64_fallback;
2413	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddw_u64, iemAImpl_phaddw_u64_fallback;
2414	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddd_u64, iemAImpl_phaddd_u64_fallback;
2415	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubw_u64, iemAImpl_phsubw_u64_fallback;
2416	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubd_u64, iemAImpl_phsubd_u64_fallback;
2417	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddsw_u64, iemAImpl_phaddsw_u64_fallback;
2418	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubsw_u64, iemAImpl_phsubsw_u64_fallback;
2419	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmaddubsw_u64, iemAImpl_pmaddubsw_u64_fallback;
2420	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmulhrsw_u64, iemAImpl_pmulhrsw_u64_fallback;
2421	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmuludq_u64;
2422	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllw_u64, iemAImpl_psrlw_u64, iemAImpl_psraw_u64;
2423	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pslld_u64, iemAImpl_psrld_u64, iemAImpl_psrad_u64;
2424	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllq_u64, iemAImpl_psrlq_u64;
2425	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packsswb_u64, iemAImpl_packuswb_u64;
2426	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packssdw_u64;
2427	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhuw_u64;
2428	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pavgb_u64, iemAImpl_pavgw_u64;
2429	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psadbw_u64;
2430
2431	FNIEMAIMPLMEDIAF2U128 iemAImpl_pshufb_u128, iemAImpl_pshufb_u128_fallback;
2432	FNIEMAIMPLMEDIAF2U128 iemAImpl_pand_u128, iemAImpl_pandn_u128, iemAImpl_por_u128, iemAImpl_pxor_u128;
2433	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
2434	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpeqq_u128, iemAImpl_pcmpeqq_u128_fallback;
2435	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpgtb_u128, iemAImpl_pcmpgtw_u128, iemAImpl_pcmpgtd_u128;
2436	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpgtq_u128, iemAImpl_pcmpgtq_u128_fallback;
2437	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddb_u128, iemAImpl_paddsb_u128, iemAImpl_paddusb_u128;
2438	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddw_u128, iemAImpl_paddsw_u128, iemAImpl_paddusw_u128;
2439	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddd_u128;
2440	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddq_u128;
2441	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubb_u128, iemAImpl_psubsb_u128, iemAImpl_psubusb_u128;
2442	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubw_u128, iemAImpl_psubsw_u128, iemAImpl_psubusw_u128;
2443	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubd_u128;
2444	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubq_u128;
2445	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmullw_u128, iemAImpl_pmullw_u128_fallback;
2446	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulhw_u128;
2447	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulld_u128, iemAImpl_pmulld_u128_fallback;
2448	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaddwd_u128;
2449	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminub_u128;
2450	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminud_u128, iemAImpl_pminud_u128_fallback;
2451	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminuw_u128, iemAImpl_pminuw_u128_fallback;
2452	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsb_u128, iemAImpl_pminsb_u128_fallback;
2453	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsd_u128, iemAImpl_pminsd_u128_fallback;
2454	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsw_u128, iemAImpl_pminsw_u128_fallback;
2455	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxub_u128;
2456	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxud_u128, iemAImpl_pmaxud_u128_fallback;
2457	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxuw_u128, iemAImpl_pmaxuw_u128_fallback;
2458	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsb_u128, iemAImpl_pmaxsb_u128_fallback;
2459	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsw_u128;
2460	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsd_u128, iemAImpl_pmaxsd_u128_fallback;
2461	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsb_u128, iemAImpl_pabsb_u128_fallback;
2462	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsw_u128, iemAImpl_pabsw_u128_fallback;
2463	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsd_u128, iemAImpl_pabsd_u128_fallback;
2464	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignb_u128, iemAImpl_psignb_u128_fallback;
2465	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignw_u128, iemAImpl_psignw_u128_fallback;
2466	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignd_u128, iemAImpl_psignd_u128_fallback;
2467	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddw_u128, iemAImpl_phaddw_u128_fallback;
2468	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddd_u128, iemAImpl_phaddd_u128_fallback;
2469	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubw_u128, iemAImpl_phsubw_u128_fallback;
2470	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubd_u128, iemAImpl_phsubd_u128_fallback;
2471	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddsw_u128, iemAImpl_phaddsw_u128_fallback;
2472	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubsw_u128, iemAImpl_phsubsw_u128_fallback;
2473	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaddubsw_u128, iemAImpl_pmaddubsw_u128_fallback;
2474	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulhrsw_u128, iemAImpl_pmulhrsw_u128_fallback;
2475	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmuludq_u128;
2476	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packsswb_u128, iemAImpl_packuswb_u128;
2477	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packssdw_u128, iemAImpl_packusdw_u128;
2478	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllw_u128, iemAImpl_psrlw_u128, iemAImpl_psraw_u128;
2479	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pslld_u128, iemAImpl_psrld_u128, iemAImpl_psrad_u128;
2480	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllq_u128, iemAImpl_psrlq_u128;
2481	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhuw_u128;
2482	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pavgb_u128, iemAImpl_pavgw_u128;
2483	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psadbw_u128;
2484	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuldq_u128, iemAImpl_pmuldq_u128_fallback;
2485	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpcklps_u128, iemAImpl_unpcklpd_u128;
2486	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpckhps_u128, iemAImpl_unpckhpd_u128;
2487	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phminposuw_u128, iemAImpl_phminposuw_u128_fallback;
2488
2489	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpshufb_u128, iemAImpl_vpshufb_u128_fallback;
2490	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpand_u128, iemAImpl_vpand_u128_fallback;
2491	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpandn_u128, iemAImpl_vpandn_u128_fallback;
2492	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpor_u128, iemAImpl_vpor_u128_fallback;
2493	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpxor_u128, iemAImpl_vpxor_u128_fallback;
2494	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqb_u128, iemAImpl_vpcmpeqb_u128_fallback;
2495	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqw_u128, iemAImpl_vpcmpeqw_u128_fallback;
2496	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqd_u128, iemAImpl_vpcmpeqd_u128_fallback;
2497	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqq_u128, iemAImpl_vpcmpeqq_u128_fallback;
2498	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtb_u128, iemAImpl_vpcmpgtb_u128_fallback;
2499	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtw_u128, iemAImpl_vpcmpgtw_u128_fallback;
2500	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtd_u128, iemAImpl_vpcmpgtd_u128_fallback;
2501	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtq_u128, iemAImpl_vpcmpgtq_u128_fallback;
2502	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddb_u128, iemAImpl_vpaddb_u128_fallback;
2503	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddw_u128, iemAImpl_vpaddw_u128_fallback;
2504	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddd_u128, iemAImpl_vpaddd_u128_fallback;
2505	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddq_u128, iemAImpl_vpaddq_u128_fallback;
2506	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubb_u128, iemAImpl_vpsubb_u128_fallback;
2507	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubw_u128, iemAImpl_vpsubw_u128_fallback;
2508	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubd_u128, iemAImpl_vpsubd_u128_fallback;
2509	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubq_u128, iemAImpl_vpsubq_u128_fallback;
2510	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminub_u128, iemAImpl_vpminub_u128_fallback;
2511	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminuw_u128, iemAImpl_vpminuw_u128_fallback;
2512	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminud_u128, iemAImpl_vpminud_u128_fallback;
2513	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsb_u128, iemAImpl_vpminsb_u128_fallback;
2514	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsw_u128, iemAImpl_vpminsw_u128_fallback;
2515	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsd_u128, iemAImpl_vpminsd_u128_fallback;
2516	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxub_u128, iemAImpl_vpmaxub_u128_fallback;
2517	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxuw_u128, iemAImpl_vpmaxuw_u128_fallback;
2518	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxud_u128, iemAImpl_vpmaxud_u128_fallback;
2519	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsb_u128, iemAImpl_vpmaxsb_u128_fallback;
2520	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsw_u128, iemAImpl_vpmaxsw_u128_fallback;
2521	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsd_u128, iemAImpl_vpmaxsd_u128_fallback;
2522	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpacksswb_u128, iemAImpl_vpacksswb_u128_fallback;
2523	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackssdw_u128, iemAImpl_vpackssdw_u128_fallback;
2524	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackuswb_u128, iemAImpl_vpackuswb_u128_fallback;
2525	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackusdw_u128, iemAImpl_vpackusdw_u128_fallback;
2526	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmullw_u128, iemAImpl_vpmullw_u128_fallback;
2527	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulld_u128, iemAImpl_vpmulld_u128_fallback;
2528	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhw_u128, iemAImpl_vpmulhw_u128_fallback;
2529	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhuw_u128, iemAImpl_vpmulhuw_u128_fallback;
2530	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgb_u128, iemAImpl_vpavgb_u128_fallback;
2531	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgw_u128, iemAImpl_vpavgw_u128_fallback;
2532	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignb_u128, iemAImpl_vpsignb_u128_fallback;
2533	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignw_u128, iemAImpl_vpsignw_u128_fallback;
2534	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignd_u128, iemAImpl_vpsignd_u128_fallback;
2535	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddw_u128, iemAImpl_vphaddw_u128_fallback;
2536	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddd_u128, iemAImpl_vphaddd_u128_fallback;
2537	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubw_u128, iemAImpl_vphsubw_u128_fallback;
2538	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubd_u128, iemAImpl_vphsubd_u128_fallback;
2539	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddsw_u128, iemAImpl_vphaddsw_u128_fallback;
2540	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubsw_u128, iemAImpl_vphsubsw_u128_fallback;
2541	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddubsw_u128, iemAImpl_vpmaddubsw_u128_fallback;
2542	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhrsw_u128, iemAImpl_vpmulhrsw_u128_fallback;
2543	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsadbw_u128, iemAImpl_vpsadbw_u128_fallback;
2544	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuldq_u128, iemAImpl_vpmuldq_u128_fallback;
2545	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuludq_u128, iemAImpl_vpmuludq_u128_fallback;
2546	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsb_u128, iemAImpl_vpsubsb_u128_fallback;
2547	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsw_u128, iemAImpl_vpsubsw_u128_fallback;
2548	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusb_u128, iemAImpl_vpsubusb_u128_fallback;
2549	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusw_u128, iemAImpl_vpsubusw_u128_fallback;
2550	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusb_u128, iemAImpl_vpaddusb_u128_fallback;
2551	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusw_u128, iemAImpl_vpaddusw_u128_fallback;
2552	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsb_u128, iemAImpl_vpaddsb_u128_fallback;
2553	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsw_u128, iemAImpl_vpaddsw_u128_fallback;
2554
2555	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsb_u128, iemAImpl_vpabsb_u128_fallback;
2556	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsw_u128, iemAImpl_vpabsd_u128_fallback;
2557	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsd_u128, iemAImpl_vpabsw_u128_fallback;
2558	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vphminposuw_u128, iemAImpl_vphminposuw_u128_fallback;
2559
2560	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpshufb_u256, iemAImpl_vpshufb_u256_fallback;
2561	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpand_u256, iemAImpl_vpand_u256_fallback;
2562	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpandn_u256, iemAImpl_vpandn_u256_fallback;
2563	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpor_u256, iemAImpl_vpor_u256_fallback;
2564	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpxor_u256, iemAImpl_vpxor_u256_fallback;
2565	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqb_u256, iemAImpl_vpcmpeqb_u256_fallback;
2566	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqw_u256, iemAImpl_vpcmpeqw_u256_fallback;
2567	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqd_u256, iemAImpl_vpcmpeqd_u256_fallback;
2568	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqq_u256, iemAImpl_vpcmpeqq_u256_fallback;
2569	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtb_u256, iemAImpl_vpcmpgtb_u256_fallback;
2570	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtw_u256, iemAImpl_vpcmpgtw_u256_fallback;
2571	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtd_u256, iemAImpl_vpcmpgtd_u256_fallback;
2572	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtq_u256, iemAImpl_vpcmpgtq_u256_fallback;
2573	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddb_u256, iemAImpl_vpaddb_u256_fallback;
2574	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddw_u256, iemAImpl_vpaddw_u256_fallback;
2575	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddd_u256, iemAImpl_vpaddd_u256_fallback;
2576	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddq_u256, iemAImpl_vpaddq_u256_fallback;
2577	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubb_u256, iemAImpl_vpsubb_u256_fallback;
2578	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubw_u256, iemAImpl_vpsubw_u256_fallback;
2579	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubd_u256, iemAImpl_vpsubd_u256_fallback;
2580	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubq_u256, iemAImpl_vpsubq_u256_fallback;
2581	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminub_u256, iemAImpl_vpminub_u256_fallback;
2582	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminuw_u256, iemAImpl_vpminuw_u256_fallback;
2583	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminud_u256, iemAImpl_vpminud_u256_fallback;
2584	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsb_u256, iemAImpl_vpminsb_u256_fallback;
2585	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsw_u256, iemAImpl_vpminsw_u256_fallback;
2586	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsd_u256, iemAImpl_vpminsd_u256_fallback;
2587	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxub_u256, iemAImpl_vpmaxub_u256_fallback;
2588	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxuw_u256, iemAImpl_vpmaxuw_u256_fallback;
2589	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxud_u256, iemAImpl_vpmaxud_u256_fallback;
2590	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsb_u256, iemAImpl_vpmaxsb_u256_fallback;
2591	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsw_u256, iemAImpl_vpmaxsw_u256_fallback;
2592	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsd_u256, iemAImpl_vpmaxsd_u256_fallback;
2593	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpacksswb_u256, iemAImpl_vpacksswb_u256_fallback;
2594	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackssdw_u256, iemAImpl_vpackssdw_u256_fallback;
2595	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackuswb_u256, iemAImpl_vpackuswb_u256_fallback;
2596	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackusdw_u256, iemAImpl_vpackusdw_u256_fallback;
2597	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmullw_u256, iemAImpl_vpmullw_u256_fallback;
2598	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulld_u256, iemAImpl_vpmulld_u256_fallback;
2599	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhw_u256, iemAImpl_vpmulhw_u256_fallback;
2600	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhuw_u256, iemAImpl_vpmulhuw_u256_fallback;
2601	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgb_u256, iemAImpl_vpavgb_u256_fallback;
2602	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgw_u256, iemAImpl_vpavgw_u256_fallback;
2603	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignb_u256, iemAImpl_vpsignb_u256_fallback;
2604	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignw_u256, iemAImpl_vpsignw_u256_fallback;
2605	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignd_u256, iemAImpl_vpsignd_u256_fallback;
2606	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddw_u256, iemAImpl_vphaddw_u256_fallback;
2607	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddd_u256, iemAImpl_vphaddd_u256_fallback;
2608	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubw_u256, iemAImpl_vphsubw_u256_fallback;
2609	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubd_u256, iemAImpl_vphsubd_u256_fallback;
2610	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddsw_u256, iemAImpl_vphaddsw_u256_fallback;
2611	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubsw_u256, iemAImpl_vphsubsw_u256_fallback;
2612	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddubsw_u256, iemAImpl_vpmaddubsw_u256_fallback;
2613	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhrsw_u256, iemAImpl_vpmulhrsw_u256_fallback;
2614	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsadbw_u256, iemAImpl_vpsadbw_u256_fallback;
2615	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuldq_u256, iemAImpl_vpmuldq_u256_fallback;
2616	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuludq_u256, iemAImpl_vpmuludq_u256_fallback;
2617	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsb_u256, iemAImpl_vpsubsb_u256_fallback;
2618	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsw_u256, iemAImpl_vpsubsw_u256_fallback;
2619	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusb_u256, iemAImpl_vpsubusb_u256_fallback;
2620	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusw_u256, iemAImpl_vpsubusw_u256_fallback;
2621	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusb_u256, iemAImpl_vpaddusb_u256_fallback;
2622	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusw_u256, iemAImpl_vpaddusw_u256_fallback;
2623	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsb_u256, iemAImpl_vpaddsb_u256_fallback;
2624	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsw_u256, iemAImpl_vpaddsw_u256_fallback;
2625
2626	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsb_u256, iemAImpl_vpabsb_u256_fallback;
2627	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsw_u256, iemAImpl_vpabsw_u256_fallback;
2628	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsd_u256, iemAImpl_vpabsd_u256_fallback;
2629	/** @} */
2630
2631	/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
2632	* @{ */
2633	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
2634	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
2635	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpcklbw_u128, iemAImpl_vpunpcklbw_u128_fallback,
2636	iemAImpl_vpunpcklwd_u128, iemAImpl_vpunpcklwd_u128_fallback,
2637	iemAImpl_vpunpckldq_u128, iemAImpl_vpunpckldq_u128_fallback,
2638	iemAImpl_vpunpcklqdq_u128, iemAImpl_vpunpcklqdq_u128_fallback,
2639	iemAImpl_vunpcklps_u128, iemAImpl_vunpcklps_u128_fallback,
2640	iemAImpl_vunpcklpd_u128, iemAImpl_vunpcklpd_u128_fallback,
2641	iemAImpl_vunpckhps_u128, iemAImpl_vunpckhps_u128_fallback,
2642	iemAImpl_vunpckhpd_u128, iemAImpl_vunpckhpd_u128_fallback;
2643
2644	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpcklbw_u256, iemAImpl_vpunpcklbw_u256_fallback,
2645	iemAImpl_vpunpcklwd_u256, iemAImpl_vpunpcklwd_u256_fallback,
2646	iemAImpl_vpunpckldq_u256, iemAImpl_vpunpckldq_u256_fallback,
2647	iemAImpl_vpunpcklqdq_u256, iemAImpl_vpunpcklqdq_u256_fallback,
2648	iemAImpl_vunpcklps_u256, iemAImpl_vunpcklps_u256_fallback,
2649	iemAImpl_vunpcklpd_u256, iemAImpl_vunpcklpd_u256_fallback,
2650	iemAImpl_vunpckhps_u256, iemAImpl_vunpckhps_u256_fallback,
2651	iemAImpl_vunpckhpd_u256, iemAImpl_vunpckhpd_u256_fallback;
2652	/** @} */
2653
2654	/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
2655	* @{ */
2656	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
2657	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
2658	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpckhbw_u128, iemAImpl_vpunpckhbw_u128_fallback,
2659	iemAImpl_vpunpckhwd_u128, iemAImpl_vpunpckhwd_u128_fallback,
2660	iemAImpl_vpunpckhdq_u128, iemAImpl_vpunpckhdq_u128_fallback,
2661	iemAImpl_vpunpckhqdq_u128, iemAImpl_vpunpckhqdq_u128_fallback;
2662	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpckhbw_u256, iemAImpl_vpunpckhbw_u256_fallback,
2663	iemAImpl_vpunpckhwd_u256, iemAImpl_vpunpckhwd_u256_fallback,
2664	iemAImpl_vpunpckhdq_u256, iemAImpl_vpunpckhdq_u256_fallback,
2665	iemAImpl_vpunpckhqdq_u256, iemAImpl_vpunpckhqdq_u256_fallback;
2666	/** @} */
2667
2668	/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
2669	* @{ */
2670	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2671	typedef FNIEMAIMPLMEDIAPSHUFU128 *PFNIEMAIMPLMEDIAPSHUFU128;
2672	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
2673	typedef FNIEMAIMPLMEDIAPSHUFU256 *PFNIEMAIMPLMEDIAPSHUFU256;
2674	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw_u64,(uint64_t puDst, uint64_t const puSrc, uint8_t bEvil));
2675	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_pshufhw_u128, iemAImpl_pshuflw_u128, iemAImpl_pshufd_u128;
2676	#ifndef IEM_WITHOUT_ASSEMBLY
2677	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256, iemAImpl_vpshuflw_u256, iemAImpl_vpshufd_u256;
2678	#endif
2679	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256_fallback, iemAImpl_vpshuflw_u256_fallback, iemAImpl_vpshufd_u256_fallback;
2680	/** @} */
2681
2682	/** @name Media (SSE/MMX/AVX) operation: Shift Immediate Stuff (evil)
2683	* @{ */
2684	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU64,(uint64_t *puDst, uint8_t bShift));
2685	typedef FNIEMAIMPLMEDIAPSHIFTU64 *PFNIEMAIMPLMEDIAPSHIFTU64;
2686	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU128,(PRTUINT128U puDst, uint8_t bShift));
2687	typedef FNIEMAIMPLMEDIAPSHIFTU128 *PFNIEMAIMPLMEDIAPSHIFTU128;
2688	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU256,(PRTUINT256U puDst, uint8_t bShift));
2689	typedef FNIEMAIMPLMEDIAPSHIFTU256 *PFNIEMAIMPLMEDIAPSHIFTU256;
2690	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psllw_imm_u64, iemAImpl_pslld_imm_u64, iemAImpl_psllq_imm_u64;
2691	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psrlw_imm_u64, iemAImpl_psrld_imm_u64, iemAImpl_psrlq_imm_u64;
2692	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psraw_imm_u64, iemAImpl_psrad_imm_u64;
2693	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psllw_imm_u128, iemAImpl_pslld_imm_u128, iemAImpl_psllq_imm_u128;
2694	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psrlw_imm_u128, iemAImpl_psrld_imm_u128, iemAImpl_psrlq_imm_u128;
2695	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psraw_imm_u128, iemAImpl_psrad_imm_u128;
2696	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_pslldq_imm_u128, iemAImpl_psrldq_imm_u128;
2697	/** @} */
2698
2699	/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
2700	* @{ */
2701	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(uint64_t pu64Dst, uint64_t const puSrc));
2702	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(uint64_t *pu64Dst, PCRTUINT128U puSrc));
2703	#ifndef IEM_WITHOUT_ASSEMBLY
2704	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
2705	#endif
2706	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256_fallback,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
2707	/** @} */
2708
2709	/** @name Media (SSE/MMX/AVX) operations: Variable Blend Packed Bytes/R32/R64.
2710	* @{ */
2711	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puMask));
2712	typedef FNIEMAIMPLBLENDU128 *PFNIEMAIMPLBLENDU128;
2713	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, PCRTUINT128U puMask));
2714	typedef FNIEMAIMPLAVXBLENDU128 *PFNIEMAIMPLAVXBLENDU128;
2715	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, PCRTUINT256U puMask));
2716	typedef FNIEMAIMPLAVXBLENDU256 *PFNIEMAIMPLAVXBLENDU256;
2717
2718	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128;
2719	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128_fallback;
2720	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128;
2721	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128_fallback;
2722	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256;
2723	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256_fallback;
2724
2725	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128;
2726	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128_fallback;
2727	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128;
2728	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128_fallback;
2729	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256;
2730	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256_fallback;
2731
2732	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128;
2733	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128_fallback;
2734	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128;
2735	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128_fallback;
2736	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256;
2737	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256_fallback;
2738	/** @} */
2739
2740
2741	/** @name Media (SSE/MMX/AVX) operation: Sort this later
2742	* @{ */
2743	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
2744	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
2745	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovshdup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
2746	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovshdup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
2747	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
2748	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
2749
2750	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2751	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2752	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2753	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2754	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2755
2756	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2757	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2758	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2759	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2760	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2761
2762	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2763	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2764	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
2765	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2766	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2767
2768	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2769	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2770	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2771	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2772	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2773
2774	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2775	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2776	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2777	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2778	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2779
2780	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2781	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2782	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2783	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2784	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2785
2786	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2787	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2788	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2789	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2790	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2791
2792	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2793	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2794	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2795	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2796	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2797
2798	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2799	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2800	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
2801	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2802	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2803
2804	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2805	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2806	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2807	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2808	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2809
2810	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2811	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2812	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2813	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2814	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2815
2816	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2817	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2818	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2819	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2820	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2821
2822	IEM_DECL_IMPL_DEF(void, iemAImpl_shufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2823	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2824	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2825	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2826	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2827
2828	IEM_DECL_IMPL_DEF(void, iemAImpl_shufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2829	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2830	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2831	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2832	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2833
2834	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
2835	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64_fallback,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
2836
2837	IEM_DECL_IMPL_DEF(void, iemAImpl_pinsrw_u64,(uint64_t *pu64Dst, uint16_t u16Src, uint8_t bEvil));
2838	IEM_DECL_IMPL_DEF(void, iemAImpl_pinsrw_u128,(PRTUINT128U puDst, uint16_t u16Src, uint8_t bEvil));
2839	IEM_DECL_IMPL_DEF(void, iemAImpl_vpinsrw_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint16_t u16Src, uint8_t bEvil));
2840	IEM_DECL_IMPL_DEF(void, iemAImpl_vpinsrw_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint16_t u16Src, uint8_t bEvil));
2841
2842	IEM_DECL_IMPL_DEF(void, iemAImpl_pextrw_u64,(uint16_t *pu16Dst, uint64_t u64Src, uint8_t bEvil));
2843	IEM_DECL_IMPL_DEF(void, iemAImpl_pextrw_u128,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
2844	IEM_DECL_IMPL_DEF(void, iemAImpl_vpextrw_u128,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
2845	IEM_DECL_IMPL_DEF(void, iemAImpl_vpextrw_u128_fallback,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
2846
2847	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2848	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2849	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2850	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
2851	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
2852
2853	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2854	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2855	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2856	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
2857	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
2858
2859
2860	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2861	typedef FNIEMAIMPLMEDIAOPTF2U128IMM8 *PFNIEMAIMPLMEDIAOPTF2U128IMM8;
2862	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2863	typedef FNIEMAIMPLMEDIAOPTF3U128IMM8 *PFNIEMAIMPLMEDIAOPTF3U128IMM8;
2864	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2865	typedef FNIEMAIMPLMEDIAOPTF3U256IMM8 *PFNIEMAIMPLMEDIAOPTF3U256IMM8;
2866
2867	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_palignr_u128, iemAImpl_palignr_u128_fallback;
2868	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pblendw_u128, iemAImpl_pblendw_u128_fallback;
2869	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendps_u128, iemAImpl_blendps_u128_fallback;
2870	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendpd_u128, iemAImpl_blendpd_u128_fallback;
2871
2872	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpalignr_u128, iemAImpl_vpalignr_u128_fallback;
2873	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendw_u128, iemAImpl_vpblendw_u128_fallback;
2874	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendps_u128, iemAImpl_vblendps_u128_fallback;
2875	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendpd_u128, iemAImpl_vblendpd_u128_fallback;
2876
2877	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpalignr_u256, iemAImpl_vpalignr_u256_fallback;
2878	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendw_u256, iemAImpl_vpblendw_u256_fallback;
2879	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendps_u256, iemAImpl_vblendps_u256_fallback;
2880	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendpd_u256, iemAImpl_vblendpd_u256_fallback;
2881	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2i128_u256, iemAImpl_vperm2i128_u256_fallback;
2882	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2f128_u256, iemAImpl_vperm2f128_u256_fallback;
2883
2884	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesimc_u128, iemAImpl_aesimc_u128_fallback;
2885	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenc_u128, iemAImpl_aesenc_u128_fallback;
2886	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenclast_u128, iemAImpl_aesenclast_u128_fallback;
2887	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdec_u128, iemAImpl_aesdec_u128_fallback;
2888	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdeclast_u128, iemAImpl_aesdeclast_u128_fallback;
2889
2890	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesimc_u128, iemAImpl_vaesimc_u128_fallback;
2891	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenc_u128, iemAImpl_vaesenc_u128_fallback;
2892	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenclast_u128, iemAImpl_vaesenclast_u128_fallback;
2893	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdec_u128, iemAImpl_vaesdec_u128_fallback;
2894	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdeclast_u128, iemAImpl_vaesdeclast_u128_fallback;
2895
2896	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_aeskeygenassist_u128, iemAImpl_aeskeygenassist_u128_fallback;
2897
2898	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vaeskeygenassist_u128, iemAImpl_vaeskeygenassist_u128_fallback;
2899
2900	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1nexte_u128, iemAImpl_sha1nexte_u128_fallback;
2901	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg1_u128, iemAImpl_sha1msg1_u128_fallback;
2902	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg2_u128, iemAImpl_sha1msg2_u128_fallback;
2903	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg1_u128, iemAImpl_sha256msg1_u128_fallback;
2904	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg2_u128, iemAImpl_sha256msg2_u128_fallback;
2905	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_sha1rnds4_u128, iemAImpl_sha1rnds4_u128_fallback;
2906	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
2907	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
2908
2909	typedef struct IEMPCMPISTRXSRC
2910	{
2911	RTUINT128U uSrc1;
2912	RTUINT128U uSrc2;
2913	} IEMPCMPISTRXSRC;
2914	typedef IEMPCMPISTRXSRC *PIEMPCMPISTRXSRC;
2915	typedef const IEMPCMPISTRXSRC *PCIEMPCMPISTRXSRC;
2916
2917	typedef struct IEMPCMPESTRXSRC
2918	{
2919	RTUINT128U uSrc1;
2920	RTUINT128U uSrc2;
2921	uint64_t u64Rax;
2922	uint64_t u64Rdx;
2923	} IEMPCMPESTRXSRC;
2924	typedef IEMPCMPESTRXSRC *PIEMPCMPESTRXSRC;
2925	typedef const IEMPCMPESTRXSRC *PCIEMPCMPESTRXSRC;
2926
2927	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPISTRIU128IMM8,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
2928	typedef FNIEMAIMPLPCMPISTRIU128IMM8 *PFNIEMAIMPLPCMPISTRIU128IMM8;
2929	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRIU128IMM8,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
2930	typedef FNIEMAIMPLPCMPESTRIU128IMM8 *PFNIEMAIMPLPCMPESTRIU128IMM8;
2931
2932	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPISTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
2933	typedef FNIEMAIMPLPCMPISTRMU128IMM8 *PFNIEMAIMPLPCMPISTRMU128IMM8;
2934	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
2935	typedef FNIEMAIMPLPCMPESTRMU128IMM8 *PFNIEMAIMPLPCMPESTRMU128IMM8;
2936
2937	FNIEMAIMPLPCMPISTRIU128IMM8 iemAImpl_pcmpistri_u128, iemAImpl_pcmpistri_u128_fallback;
2938	FNIEMAIMPLPCMPESTRIU128IMM8 iemAImpl_pcmpestri_u128, iemAImpl_pcmpestri_u128_fallback;
2939	FNIEMAIMPLPCMPISTRMU128IMM8 iemAImpl_pcmpistrm_u128, iemAImpl_pcmpistrm_u128_fallback;
2940	FNIEMAIMPLPCMPESTRMU128IMM8 iemAImpl_pcmpestrm_u128, iemAImpl_pcmpestrm_u128_fallback;
2941
2942	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pclmulqdq_u128, iemAImpl_pclmulqdq_u128_fallback;
2943	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpclmulqdq_u128, iemAImpl_vpclmulqdq_u128_fallback;
2944
2945	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_mpsadbw_u128, iemAImpl_mpsadbw_u128_fallback;
2946	/** @} */
2947
2948	/** @name Media Odds and Ends
2949	* @{ */
2950	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U8,(uint32_t *puDst, uint8_t uSrc));
2951	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U16,(uint32_t *puDst, uint16_t uSrc));
2952	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U32,(uint32_t *puDst, uint32_t uSrc));
2953	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U64,(uint32_t *puDst, uint64_t uSrc));
2954	FNIEMAIMPLCR32U8 iemAImpl_crc32_u8, iemAImpl_crc32_u8_fallback;
2955	FNIEMAIMPLCR32U16 iemAImpl_crc32_u16, iemAImpl_crc32_u16_fallback;
2956	FNIEMAIMPLCR32U32 iemAImpl_crc32_u32, iemAImpl_crc32_u32_fallback;
2957	FNIEMAIMPLCR32U64 iemAImpl_crc32_u64, iemAImpl_crc32_u64_fallback;
2958
2959	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL128,(PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint32_t *pEFlags));
2960	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL256,(PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint32_t *pEFlags));
2961	FNIEMAIMPLF2EFL128 iemAImpl_ptest_u128;
2962	FNIEMAIMPLF2EFL256 iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback;
2963
2964	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I32U64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int32_t pi32Dst, const uint64_t pu64Src)); / pu64Src is a double precision floating point. */
2965	typedef FNIEMAIMPLSSEF2I32U64 *PFNIEMAIMPLSSEF2I32U64;
2966	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I64U64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int64_t pi64Dst, const uint64_t pu64Src)); / pu64Src is a double precision floating point. */
2967	typedef FNIEMAIMPLSSEF2I64U64 *PFNIEMAIMPLSSEF2I64U64;
2968	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I32U32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int32_t pi32Dst, const uint32_t pu32Src)); / pu32Src is a single precision floating point. */
2969	typedef FNIEMAIMPLSSEF2I32U32 *PFNIEMAIMPLSSEF2I32U32;
2970	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I64U32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int64_t pi64Dst, const uint32_t pu32Src)); / pu32Src is a single precision floating point. */
2971	typedef FNIEMAIMPLSSEF2I64U32 *PFNIEMAIMPLSSEF2I64U32;
2972
2973	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvttsd2si_i32_r64;
2974	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvtsd2si_i32_r64;
2975
2976	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvttsd2si_i64_r64;
2977	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvtsd2si_i64_r64;
2978
2979	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvttss2si_i32_r32;
2980	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvtss2si_i32_r32;
2981
2982	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvttss2si_i64_r32;
2983	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvtss2si_i64_r32;
2984
2985	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R32I32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT32U pr32Dst, const int32_t pi32Src));
2986	typedef FNIEMAIMPLSSEF2R32I32 *PFNIEMAIMPLSSEF2R32I32;
2987	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R32I64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT32U pr32Dst, const int64_t pi64Src));
2988	typedef FNIEMAIMPLSSEF2R32I64 *PFNIEMAIMPLSSEF2R32I64;
2989
2990	FNIEMAIMPLSSEF2R32I32 iemAImpl_cvtsi2ss_r32_i32;
2991	FNIEMAIMPLSSEF2R32I64 iemAImpl_cvtsi2ss_r32_i64;
2992
2993	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R64I32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT64U pr64Dst, const int32_t pi32Src));
2994	typedef FNIEMAIMPLSSEF2R64I32 *PFNIEMAIMPLSSEF2R64I32;
2995	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R64I64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT64U pr64Dst, const int64_t pi64Src));
2996	typedef FNIEMAIMPLSSEF2R64I64 *PFNIEMAIMPLSSEF2R64I64;
2997
2998	FNIEMAIMPLSSEF2R64I32 iemAImpl_cvtsi2sd_r64_i32;
2999	FNIEMAIMPLSSEF2R64I64 iemAImpl_cvtsi2sd_r64_i64;
3000
3001
3002	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFLMXCSR128,(uint32_t pfMxcsr, uint32_t pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
3003	typedef FNIEMAIMPLF2EFLMXCSR128 *PFNIEMAIMPLF2EFLMXCSR128;
3004
3005	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_ucomiss_u128;
3006	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback;
3007
3008	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_ucomisd_u128;
3009	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback;
3010
3011	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_comiss_u128;
3012	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback;
3013
3014	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_comisd_u128;
3015	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback;
3016
3017
3018	typedef struct IEMMEDIAF2XMMSRC
3019	{
3020	X86XMMREG uSrc1;
3021	X86XMMREG uSrc2;
3022	} IEMMEDIAF2XMMSRC;
3023	typedef IEMMEDIAF2XMMSRC *PIEMMEDIAF2XMMSRC;
3024	typedef const IEMMEDIAF2XMMSRC *PCIEMMEDIAF2XMMSRC;
3025
3026	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRF2XMMIMM8,(uint32_t *pfMxcsr, PX86XMMREG puDst, PCIEMMEDIAF2XMMSRC puSrc, uint8_t bEvil));
3027	typedef FNIEMAIMPLMXCSRF2XMMIMM8 *PFNIEMAIMPLMXCSRF2XMMIMM8;
3028
3029	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpps_u128;
3030	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmppd_u128;
3031	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpss_u128;
3032	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpsd_u128;
3033	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundss_u128;
3034	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundsd_u128;
3035
3036	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundps_u128, iemAImpl_roundps_u128_fallback;
3037	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundpd_u128, iemAImpl_roundpd_u128_fallback;
3038
3039	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_dpps_u128, iemAImpl_dpps_u128_fallback;
3040	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_dppd_u128, iemAImpl_dppd_u128_fallback;
3041
3042	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU64U128,(uint32_t pfMxcsr, uint64_t pu64Dst, PCX86XMMREG pSrc));
3043	typedef FNIEMAIMPLMXCSRU64U128 *PFNIEMAIMPLMXCSRU64U128;
3044
3045	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvtpd2pi_u128;
3046	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvttpd2pi_u128;
3047
3048	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU128U64,(uint32_t *pfMxcsr, PX86XMMREG pDst, uint64_t u64Src));
3049	typedef FNIEMAIMPLMXCSRU128U64 *PFNIEMAIMPLMXCSRU128U64;
3050
3051	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2ps_u128;
3052	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2pd_u128;
3053
3054	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU64U64,(uint32_t pfMxcsr, uint64_t pu64Dst, uint64_t u64Src));
3055	typedef FNIEMAIMPLMXCSRU64U64 *PFNIEMAIMPLMXCSRU64U64;
3056
3057	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvtps2pi_u128;
3058	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvttps2pi_u128;
3059
3060	/** @} */
3061
3062
3063	/** @name Function tables.
3064	* @{
3065	*/
3066
3067	/**
3068	* Function table for a binary operator providing implementation based on
3069	* operand size.
3070	*/
3071	typedef struct IEMOPBINSIZES
3072	{
3073	PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
3074	PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
3075	PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
3076	PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
3077	} IEMOPBINSIZES;
3078	/** Pointer to a binary operator function table. */
3079	typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
3080
3081
3082	/**
3083	* Function table for a unary operator providing implementation based on
3084	* operand size.
3085	*/
3086	typedef struct IEMOPUNARYSIZES
3087	{
3088	PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
3089	PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
3090	PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
3091	PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
3092	} IEMOPUNARYSIZES;
3093	/** Pointer to a unary operator function table. */
3094	typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
3095
3096
3097	/**
3098	* Function table for a shift operator providing implementation based on
3099	* operand size.
3100	*/
3101	typedef struct IEMOPSHIFTSIZES
3102	{
3103	PFNIEMAIMPLSHIFTU8 pfnNormalU8;
3104	PFNIEMAIMPLSHIFTU16 pfnNormalU16;
3105	PFNIEMAIMPLSHIFTU32 pfnNormalU32;
3106	PFNIEMAIMPLSHIFTU64 pfnNormalU64;
3107	} IEMOPSHIFTSIZES;
3108	/** Pointer to a shift operator function table. */
3109	typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
3110
3111
3112	/**
3113	* Function table for a multiplication or division operation.
3114	*/
3115	typedef struct IEMOPMULDIVSIZES
3116	{
3117	PFNIEMAIMPLMULDIVU8 pfnU8;
3118	PFNIEMAIMPLMULDIVU16 pfnU16;
3119	PFNIEMAIMPLMULDIVU32 pfnU32;
3120	PFNIEMAIMPLMULDIVU64 pfnU64;
3121	} IEMOPMULDIVSIZES;
3122	/** Pointer to a multiplication or division operation function table. */
3123	typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
3124
3125
3126	/**
3127	* Function table for a double precision shift operator providing implementation
3128	* based on operand size.
3129	*/
3130	typedef struct IEMOPSHIFTDBLSIZES
3131	{
3132	PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
3133	PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
3134	PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
3135	} IEMOPSHIFTDBLSIZES;
3136	/** Pointer to a double precision shift function table. */
3137	typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
3138
3139
3140	/**
3141	* Function table for media instruction taking two full sized media source
3142	* registers and one full sized destination register (AVX).
3143	*/
3144	typedef struct IEMOPMEDIAF3
3145	{
3146	PFNIEMAIMPLMEDIAF3U128 pfnU128;
3147	PFNIEMAIMPLMEDIAF3U256 pfnU256;
3148	} IEMOPMEDIAF3;
3149	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
3150	typedef IEMOPMEDIAF3 const *PCIEMOPMEDIAF3;
3151
3152	/** @def IEMOPMEDIAF3_INIT_VARS_EX
3153	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3154	* given functions as initializers. For use in AVX functions where a pair of
3155	* functions are only used once and the function table need not be public. */
3156	#ifndef TST_IEM_CHECK_MC
3157	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3158	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3159	static IEMOPMEDIAF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3160	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3161	# else
3162	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3163	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3164	# endif
3165	#else
3166	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3167	#endif
3168	/** @def IEMOPMEDIAF3_INIT_VARS
3169	* Generate AVX function tables for the @a a_InstrNm instruction.
3170	* @sa IEMOPMEDIAF3_INIT_VARS_EX */
3171	#define IEMOPMEDIAF3_INIT_VARS(a_InstrNm) \
3172	IEMOPMEDIAF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3173	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3174
3175	/**
3176	* Function table for media instruction taking two full sized media source
3177	* registers and one full sized destination register, but no additional state
3178	* (AVX).
3179	*/
3180	typedef struct IEMOPMEDIAOPTF3
3181	{
3182	PFNIEMAIMPLMEDIAOPTF3U128 pfnU128;
3183	PFNIEMAIMPLMEDIAOPTF3U256 pfnU256;
3184	} IEMOPMEDIAOPTF3;
3185	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
3186	typedef IEMOPMEDIAOPTF3 const *PCIEMOPMEDIAOPTF3;
3187
3188	/** @def IEMOPMEDIAOPTF3_INIT_VARS_EX
3189	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3190	* given functions as initializers. For use in AVX functions where a pair of
3191	* functions are only used once and the function table need not be public. */
3192	#ifndef TST_IEM_CHECK_MC
3193	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3194	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3195	static IEMOPMEDIAOPTF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3196	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3197	# else
3198	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3199	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3200	# endif
3201	#else
3202	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3203	#endif
3204	/** @def IEMOPMEDIAOPTF3_INIT_VARS
3205	* Generate AVX function tables for the @a a_InstrNm instruction.
3206	* @sa IEMOPMEDIAOPTF3_INIT_VARS_EX */
3207	#define IEMOPMEDIAOPTF3_INIT_VARS(a_InstrNm) \
3208	IEMOPMEDIAOPTF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3209	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3210
3211	/**
3212	* Function table for media instruction taking one full sized media source
3213	* registers and one full sized destination register, but no additional state
3214	* (AVX).
3215	*/
3216	typedef struct IEMOPMEDIAOPTF2
3217	{
3218	PFNIEMAIMPLMEDIAOPTF2U128 pfnU128;
3219	PFNIEMAIMPLMEDIAOPTF2U256 pfnU256;
3220	} IEMOPMEDIAOPTF2;
3221	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
3222	typedef IEMOPMEDIAOPTF2 const *PCIEMOPMEDIAOPTF2;
3223
3224	/** @def IEMOPMEDIAOPTF2_INIT_VARS_EX
3225	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3226	* given functions as initializers. For use in AVX functions where a pair of
3227	* functions are only used once and the function table need not be public. */
3228	#ifndef TST_IEM_CHECK_MC
3229	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3230	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3231	static IEMOPMEDIAOPTF2 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3232	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3233	# else
3234	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3235	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3236	# endif
3237	#else
3238	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3239	#endif
3240	/** @def IEMOPMEDIAOPTF2_INIT_VARS
3241	* Generate AVX function tables for the @a a_InstrNm instruction.
3242	* @sa IEMOPMEDIAOPTF2_INIT_VARS_EX */
3243	#define IEMOPMEDIAOPTF2_INIT_VARS(a_InstrNm) \
3244	IEMOPMEDIAOPTF2_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3245	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3246
3247	/**
3248	* Function table for media instruction taking two full sized media source
3249	* registers and one full sized destination register and an 8-bit immediate, but no additional state
3250	* (AVX).
3251	*/
3252	typedef struct IEMOPMEDIAOPTF3IMM8
3253	{
3254	PFNIEMAIMPLMEDIAOPTF3U128IMM8 pfnU128;
3255	PFNIEMAIMPLMEDIAOPTF3U256IMM8 pfnU256;
3256	} IEMOPMEDIAOPTF3IMM8;
3257	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
3258	typedef IEMOPMEDIAOPTF3IMM8 const *PCIEMOPMEDIAOPTF3IMM8;
3259
3260	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX
3261	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3262	* given functions as initializers. For use in AVX functions where a pair of
3263	* functions are only used once and the function table need not be public. */
3264	#ifndef TST_IEM_CHECK_MC
3265	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3266	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3267	static IEMOPMEDIAOPTF3IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3268	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3269	# else
3270	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3271	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3272	# endif
3273	#else
3274	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3275	#endif
3276	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS
3277	* Generate AVX function tables for the @a a_InstrNm instruction.
3278	* @sa IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX */
3279	#define IEMOPMEDIAOPTF3IMM8_INIT_VARS(a_InstrNm) \
3280	IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3281	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3282	/** @} */
3283
3284
3285	/**
3286	* Function table for blend type instruction taking three full sized media source
3287	* registers and one full sized destination register, but no additional state
3288	* (AVX).
3289	*/
3290	typedef struct IEMOPBLENDOP
3291	{
3292	PFNIEMAIMPLAVXBLENDU128 pfnU128;
3293	PFNIEMAIMPLAVXBLENDU256 pfnU256;
3294	} IEMOPBLENDOP;
3295	/** Pointer to a media operation function table for 4 full sized ops (AVX). */
3296	typedef IEMOPBLENDOP const *PCIEMOPBLENDOP;
3297
3298	/** @def IEMOPBLENDOP_INIT_VARS_EX
3299	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3300	* given functions as initializers. For use in AVX functions where a pair of
3301	* functions are only used once and the function table need not be public. */
3302	#ifndef TST_IEM_CHECK_MC
3303	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3304	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3305	static IEMOPBLENDOP const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3306	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3307	# else
3308	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3309	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3310	# endif
3311	#else
3312	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3313	#endif
3314	/** @def IEMOPBLENDOP_INIT_VARS
3315	* Generate AVX function tables for the @a a_InstrNm instruction.
3316	* @sa IEMOPBLENDOP_INIT_VARS_EX */
3317	#define IEMOPBLENDOP_INIT_VARS(a_InstrNm) \
3318	IEMOPBLENDOP_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3319	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3320
3321
3322	/** @name SSE/AVX single/double precision floating point operations.
3323	* @{ */
3324	/**
3325	* A SSE result.
3326	*/
3327	typedef struct IEMSSERESULT
3328	{
3329	/** The output value. */
3330	X86XMMREG uResult;
3331	/** The output status. */
3332	uint32_t MXCSR;
3333	} IEMSSERESULT;
3334	AssertCompileMemberOffset(IEMSSERESULT, MXCSR, 128 / 8);
3335	/** Pointer to a SSE result. */
3336	typedef IEMSSERESULT *PIEMSSERESULT;
3337	/** Pointer to a const SSE result. */
3338	typedef IEMSSERESULT const *PCIEMSSERESULT;
3339
3340
3341	/**
3342	* A AVX128 result.
3343	*/
3344	typedef struct IEMAVX128RESULT
3345	{
3346	/** The output value. */
3347	X86XMMREG uResult;
3348	/** The output status. */
3349	uint32_t MXCSR;
3350	} IEMAVX128RESULT;
3351	AssertCompileMemberOffset(IEMAVX128RESULT, MXCSR, 128 / 8);
3352	/** Pointer to a AVX128 result. */
3353	typedef IEMAVX128RESULT *PIEMAVX128RESULT;
3354	/** Pointer to a const AVX128 result. */
3355	typedef IEMAVX128RESULT const *PCIEMAVX128RESULT;
3356
3357
3358	/**
3359	* A AVX256 result.
3360	*/
3361	typedef struct IEMAVX256RESULT
3362	{
3363	/** The output value. */
3364	X86YMMREG uResult;
3365	/** The output status. */
3366	uint32_t MXCSR;
3367	} IEMAVX256RESULT;
3368	AssertCompileMemberOffset(IEMAVX256RESULT, MXCSR, 256 / 8);
3369	/** Pointer to a AVX256 result. */
3370	typedef IEMAVX256RESULT *PIEMAVX256RESULT;
3371	/** Pointer to a const AVX256 result. */
3372	typedef IEMAVX256RESULT const *PCIEMAVX256RESULT;
3373
3374
3375	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
3376	typedef FNIEMAIMPLFPSSEF2U128 *PFNIEMAIMPLFPSSEF2U128;
3377	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128R32,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
3378	typedef FNIEMAIMPLFPSSEF2U128R32 *PFNIEMAIMPLFPSSEF2U128R32;
3379	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128R64,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
3380	typedef FNIEMAIMPLFPSSEF2U128R64 *PFNIEMAIMPLFPSSEF2U128R64;
3381
3382	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
3383	typedef FNIEMAIMPLFPAVXF3U128 *PFNIEMAIMPLFPAVXF3U128;
3384	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128R32,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
3385	typedef FNIEMAIMPLFPAVXF3U128R32 *PFNIEMAIMPLFPAVXF3U128R32;
3386	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128R64,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
3387	typedef FNIEMAIMPLFPAVXF3U128R64 *PFNIEMAIMPLFPAVXF3U128R64;
3388
3389	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U256,(PX86XSAVEAREA pExtState, PIEMAVX256RESULT pResult, PCX86YMMREG puSrc1, PCX86YMMREG puSrc2));
3390	typedef FNIEMAIMPLFPAVXF3U256 *PFNIEMAIMPLFPAVXF3U256;
3391
3392	FNIEMAIMPLFPSSEF2U128 iemAImpl_addps_u128;
3393	FNIEMAIMPLFPSSEF2U128 iemAImpl_addpd_u128;
3394	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulps_u128;
3395	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulpd_u128;
3396	FNIEMAIMPLFPSSEF2U128 iemAImpl_subps_u128;
3397	FNIEMAIMPLFPSSEF2U128 iemAImpl_subpd_u128;
3398	FNIEMAIMPLFPSSEF2U128 iemAImpl_minps_u128;
3399	FNIEMAIMPLFPSSEF2U128 iemAImpl_minpd_u128;
3400	FNIEMAIMPLFPSSEF2U128 iemAImpl_divps_u128;
3401	FNIEMAIMPLFPSSEF2U128 iemAImpl_divpd_u128;
3402	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxps_u128;
3403	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxpd_u128;
3404	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddps_u128;
3405	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddpd_u128;
3406	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubps_u128;
3407	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubpd_u128;
3408	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtps_u128;
3409	FNIEMAIMPLFPSSEF2U128 iemAImpl_rsqrtps_u128;
3410	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtpd_u128;
3411	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubps_u128;
3412	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubpd_u128;
3413	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2ps_u128;
3414	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2pd_u128;
3415
3416	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2ps_u128;
3417	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2dq_u128;
3418	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttps2dq_u128;
3419	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttpd2dq_u128;
3420	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2pd_u128;
3421	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2dq_u128;
3422
3423	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_addss_u128_r32;
3424	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_addsd_u128_r64;
3425	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_mulss_u128_r32;
3426	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_mulsd_u128_r64;
3427	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_subss_u128_r32;
3428	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_subsd_u128_r64;
3429	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_minss_u128_r32;
3430	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_minsd_u128_r64;
3431	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_divss_u128_r32;
3432	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_divsd_u128_r64;
3433	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_maxss_u128_r32;
3434	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_maxsd_u128_r64;
3435	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_cvtss2sd_u128_r32;
3436	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_cvtsd2ss_u128_r64;
3437	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_sqrtss_u128_r32;
3438	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_sqrtsd_u128_r64;
3439	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_rsqrtss_u128_r32;
3440
3441	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddps_u128, iemAImpl_vaddps_u128_fallback;
3442	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddpd_u128, iemAImpl_vaddpd_u128_fallback;
3443	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulps_u128, iemAImpl_vmulps_u128_fallback;
3444	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulpd_u128, iemAImpl_vmulpd_u128_fallback;
3445	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubps_u128, iemAImpl_vsubps_u128_fallback;
3446	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubpd_u128, iemAImpl_vsubpd_u128_fallback;
3447	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminps_u128, iemAImpl_vminps_u128_fallback;
3448	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminpd_u128, iemAImpl_vminpd_u128_fallback;
3449	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivps_u128, iemAImpl_vdivps_u128_fallback;
3450	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivpd_u128, iemAImpl_vdivpd_u128_fallback;
3451	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxps_u128, iemAImpl_vmaxps_u128_fallback;
3452	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxpd_u128, iemAImpl_vmaxpd_u128_fallback;
3453	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddps_u128, iemAImpl_vhaddps_u128_fallback;
3454	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddpd_u128, iemAImpl_vhaddpd_u128_fallback;
3455	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubps_u128, iemAImpl_vhsubps_u128_fallback;
3456	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubpd_u128, iemAImpl_vhsubpd_u128_fallback;
3457	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtps_u128, iemAImpl_vsqrtps_u128_fallback;
3458	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtpd_u128, iemAImpl_vsqrtpd_u128_fallback;
3459	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubps_u128, iemAImpl_vaddsubps_u128_fallback;
3460	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubpd_u128, iemAImpl_vaddsubpd_u128_fallback;
3461	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtpd2ps_u128, iemAImpl_vcvtpd2ps_u128_fallback;
3462	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtps2pd_u128, iemAImpl_vcvtps2pd_u128_fallback;
3463
3464	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vaddss_u128_r32, iemAImpl_vaddss_u128_r32_fallback;
3465	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vaddsd_u128_r64, iemAImpl_vaddsd_u128_r64_fallback;
3466	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmulss_u128_r32, iemAImpl_vmulss_u128_r32_fallback;
3467	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmulsd_u128_r64, iemAImpl_vmulsd_u128_r64_fallback;
3468	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsubss_u128_r32, iemAImpl_vsubss_u128_r32_fallback;
3469	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsubsd_u128_r64, iemAImpl_vsubsd_u128_r64_fallback;
3470	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vminss_u128_r32, iemAImpl_vminss_u128_r32_fallback;
3471	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vminsd_u128_r64, iemAImpl_vminsd_u128_r64_fallback;
3472	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vdivss_u128_r32, iemAImpl_vdivss_u128_r32_fallback;
3473	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vdivsd_u128_r64, iemAImpl_vdivsd_u128_r64_fallback;
3474	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmaxss_u128_r32, iemAImpl_vmaxss_u128_r32_fallback;
3475	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmaxsd_u128_r64, iemAImpl_vmaxsd_u128_r64_fallback;
3476	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsqrtss_u128_r32, iemAImpl_vsqrtss_u128_r32_fallback;
3477	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsqrtsd_u128_r64, iemAImpl_vsqrtsd_u128_r64_fallback;
3478
3479	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddps_u256, iemAImpl_vaddps_u256_fallback;
3480	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddpd_u256, iemAImpl_vaddpd_u256_fallback;
3481	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulps_u256, iemAImpl_vmulps_u256_fallback;
3482	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulpd_u256, iemAImpl_vmulpd_u256_fallback;
3483	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubps_u256, iemAImpl_vsubps_u256_fallback;
3484	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubpd_u256, iemAImpl_vsubpd_u256_fallback;
3485	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminps_u256, iemAImpl_vminps_u256_fallback;
3486	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminpd_u256, iemAImpl_vminpd_u256_fallback;
3487	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivps_u256, iemAImpl_vdivps_u256_fallback;
3488	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivpd_u256, iemAImpl_vdivpd_u256_fallback;
3489	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxps_u256, iemAImpl_vmaxps_u256_fallback;
3490	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxpd_u256, iemAImpl_vmaxpd_u256_fallback;
3491	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddps_u256, iemAImpl_vhaddps_u256_fallback;
3492	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddpd_u256, iemAImpl_vhaddpd_u256_fallback;
3493	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubps_u256, iemAImpl_vhsubps_u256_fallback;
3494	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubpd_u256, iemAImpl_vhsubpd_u256_fallback;
3495	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubps_u256, iemAImpl_vhaddsubps_u256_fallback;
3496	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubpd_u256, iemAImpl_vhaddsubpd_u256_fallback;
3497	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtpd2ps_u256, iemAImpl_vcvtpd2ps_u256_fallback;
3498	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtps2pd_u256, iemAImpl_vcvtps2pd_u256_fallback;
3499	/** @} */
3500
3501	/** @name C instruction implementations for anything slightly complicated.
3502	* @{ */
3503
3504	/**
3505	* For typedef'ing or declaring a C instruction implementation function taking
3506	* no extra arguments.
3507	*
3508	* @param a_Name The name of the type.
3509	*/
3510	# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
3511	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
3512	/**
3513	* For defining a C instruction implementation function taking no extra
3514	* arguments.
3515	*
3516	* @param a_Name The name of the function
3517	*/
3518	# define IEM_CIMPL_DEF_0(a_Name) \
3519	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
3520	/**
3521	* Prototype version of IEM_CIMPL_DEF_0.
3522	*/
3523	# define IEM_CIMPL_PROTO_0(a_Name) \
3524	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
3525	/**
3526	* For calling a C instruction implementation function taking no extra
3527	* arguments.
3528	*
3529	* This special call macro adds default arguments to the call and allow us to
3530	* change these later.
3531	*
3532	* @param a_fn The name of the function.
3533	*/
3534	# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
3535
3536	/** Type for a C instruction implementation function taking no extra
3537	* arguments. */
3538	typedef IEM_CIMPL_DECL_TYPE_0(FNIEMCIMPL0);
3539	/** Function pointer type for a C instruction implementation function taking
3540	* no extra arguments. */
3541	typedef FNIEMCIMPL0 *PFNIEMCIMPL0;
3542
3543	/**
3544	* For typedef'ing or declaring a C instruction implementation function taking
3545	* one extra argument.
3546	*
3547	* @param a_Name The name of the type.
3548	* @param a_Type0 The argument type.
3549	* @param a_Arg0 The argument name.
3550	*/
3551	# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
3552	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
3553	/**
3554	* For defining a C instruction implementation function taking one extra
3555	* argument.
3556	*
3557	* @param a_Name The name of the function
3558	* @param a_Type0 The argument type.
3559	* @param a_Arg0 The argument name.
3560	*/
3561	# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
3562	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
3563	/**
3564	* Prototype version of IEM_CIMPL_DEF_1.
3565	*/
3566	# define IEM_CIMPL_PROTO_1(a_Name, a_Type0, a_Arg0) \
3567	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
3568	/**
3569	* For calling a C instruction implementation function taking one extra
3570	* argument.
3571	*
3572	* This special call macro adds default arguments to the call and allow us to
3573	* change these later.
3574	*
3575	* @param a_fn The name of the function.
3576	* @param a0 The name of the 1st argument.
3577	*/
3578	# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
3579
3580	/**
3581	* For typedef'ing or declaring a C instruction implementation function taking
3582	* two extra arguments.
3583	*
3584	* @param a_Name The name of the type.
3585	* @param a_Type0 The type of the 1st argument
3586	* @param a_Arg0 The name of the 1st argument.
3587	* @param a_Type1 The type of the 2nd argument.
3588	* @param a_Arg1 The name of the 2nd argument.
3589	*/
3590	# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
3591	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
3592	/**
3593	* For defining a C instruction implementation function taking two extra
3594	* arguments.
3595	*
3596	* @param a_Name The name of the function.
3597	* @param a_Type0 The type of the 1st argument
3598	* @param a_Arg0 The name of the 1st argument.
3599	* @param a_Type1 The type of the 2nd argument.
3600	* @param a_Arg1 The name of the 2nd argument.
3601	*/
3602	# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
3603	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
3604	/**
3605	* Prototype version of IEM_CIMPL_DEF_2.
3606	*/
3607	# define IEM_CIMPL_PROTO_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
3608	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
3609	/**
3610	* For calling a C instruction implementation function taking two extra
3611	* arguments.
3612	*
3613	* This special call macro adds default arguments to the call and allow us to
3614	* change these later.
3615	*
3616	* @param a_fn The name of the function.
3617	* @param a0 The name of the 1st argument.
3618	* @param a1 The name of the 2nd argument.
3619	*/
3620	# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
3621
3622	/**
3623	* For typedef'ing or declaring a C instruction implementation function taking
3624	* three extra arguments.
3625	*
3626	* @param a_Name The name of the type.
3627	* @param a_Type0 The type of the 1st argument
3628	* @param a_Arg0 The name of the 1st argument.
3629	* @param a_Type1 The type of the 2nd argument.
3630	* @param a_Arg1 The name of the 2nd argument.
3631	* @param a_Type2 The type of the 3rd argument.
3632	* @param a_Arg2 The name of the 3rd argument.
3633	*/
3634	# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
3635	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
3636	/**
3637	* For defining a C instruction implementation function taking three extra
3638	* arguments.
3639	*
3640	* @param a_Name The name of the function.
3641	* @param a_Type0 The type of the 1st argument
3642	* @param a_Arg0 The name of the 1st argument.
3643	* @param a_Type1 The type of the 2nd argument.
3644	* @param a_Arg1 The name of the 2nd argument.
3645	* @param a_Type2 The type of the 3rd argument.
3646	* @param a_Arg2 The name of the 3rd argument.
3647	*/
3648	# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
3649	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
3650	/**
3651	* Prototype version of IEM_CIMPL_DEF_3.
3652	*/
3653	# define IEM_CIMPL_PROTO_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
3654	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
3655	/**
3656	* For calling a C instruction implementation function taking three extra
3657	* arguments.
3658	*
3659	* This special call macro adds default arguments to the call and allow us to
3660	* change these later.
3661	*
3662	* @param a_fn The name of the function.
3663	* @param a0 The name of the 1st argument.
3664	* @param a1 The name of the 2nd argument.
3665	* @param a2 The name of the 3rd argument.
3666	*/
3667	# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
3668
3669
3670	/**
3671	* For typedef'ing or declaring a C instruction implementation function taking
3672	* four extra arguments.
3673	*
3674	* @param a_Name The name of the type.
3675	* @param a_Type0 The type of the 1st argument
3676	* @param a_Arg0 The name of the 1st argument.
3677	* @param a_Type1 The type of the 2nd argument.
3678	* @param a_Arg1 The name of the 2nd argument.
3679	* @param a_Type2 The type of the 3rd argument.
3680	* @param a_Arg2 The name of the 3rd argument.
3681	* @param a_Type3 The type of the 4th argument.
3682	* @param a_Arg3 The name of the 4th argument.
3683	*/
3684	# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
3685	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
3686	/**
3687	* For defining a C instruction implementation function taking four extra
3688	* arguments.
3689	*
3690	* @param a_Name The name of the function.
3691	* @param a_Type0 The type of the 1st argument
3692	* @param a_Arg0 The name of the 1st argument.
3693	* @param a_Type1 The type of the 2nd argument.
3694	* @param a_Arg1 The name of the 2nd argument.
3695	* @param a_Type2 The type of the 3rd argument.
3696	* @param a_Arg2 The name of the 3rd argument.
3697	* @param a_Type3 The type of the 4th argument.
3698	* @param a_Arg3 The name of the 4th argument.
3699	*/
3700	# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
3701	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3702	a_Type2 a_Arg2, a_Type3 a_Arg3))
3703	/**
3704	* Prototype version of IEM_CIMPL_DEF_4.
3705	*/
3706	# define IEM_CIMPL_PROTO_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
3707	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3708	a_Type2 a_Arg2, a_Type3 a_Arg3))
3709	/**
3710	* For calling a C instruction implementation function taking four extra
3711	* arguments.
3712	*
3713	* This special call macro adds default arguments to the call and allow us to
3714	* change these later.
3715	*
3716	* @param a_fn The name of the function.
3717	* @param a0 The name of the 1st argument.
3718	* @param a1 The name of the 2nd argument.
3719	* @param a2 The name of the 3rd argument.
3720	* @param a3 The name of the 4th argument.
3721	*/
3722	# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
3723
3724
3725	/**
3726	* For typedef'ing or declaring a C instruction implementation function taking
3727	* five extra arguments.
3728	*
3729	* @param a_Name The name of the type.
3730	* @param a_Type0 The type of the 1st argument
3731	* @param a_Arg0 The name of the 1st argument.
3732	* @param a_Type1 The type of the 2nd argument.
3733	* @param a_Arg1 The name of the 2nd argument.
3734	* @param a_Type2 The type of the 3rd argument.
3735	* @param a_Arg2 The name of the 3rd argument.
3736	* @param a_Type3 The type of the 4th argument.
3737	* @param a_Arg3 The name of the 4th argument.
3738	* @param a_Type4 The type of the 5th argument.
3739	* @param a_Arg4 The name of the 5th argument.
3740	*/
3741	# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
3742	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, \
3743	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
3744	a_Type3 a_Arg3, a_Type4 a_Arg4))
3745	/**
3746	* For defining a C instruction implementation function taking five extra
3747	* arguments.
3748	*
3749	* @param a_Name The name of the function.
3750	* @param a_Type0 The type of the 1st argument
3751	* @param a_Arg0 The name of the 1st argument.
3752	* @param a_Type1 The type of the 2nd argument.
3753	* @param a_Arg1 The name of the 2nd argument.
3754	* @param a_Type2 The type of the 3rd argument.
3755	* @param a_Arg2 The name of the 3rd argument.
3756	* @param a_Type3 The type of the 4th argument.
3757	* @param a_Arg3 The name of the 4th argument.
3758	* @param a_Type4 The type of the 5th argument.
3759	* @param a_Arg4 The name of the 5th argument.
3760	*/
3761	# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
3762	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3763	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
3764	/**
3765	* Prototype version of IEM_CIMPL_DEF_5.
3766	*/
3767	# define IEM_CIMPL_PROTO_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
3768	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3769	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
3770	/**
3771	* For calling a C instruction implementation function taking five extra
3772	* arguments.
3773	*
3774	* This special call macro adds default arguments to the call and allow us to
3775	* change these later.
3776	*
3777	* @param a_fn The name of the function.
3778	* @param a0 The name of the 1st argument.
3779	* @param a1 The name of the 2nd argument.
3780	* @param a2 The name of the 3rd argument.
3781	* @param a3 The name of the 4th argument.
3782	* @param a4 The name of the 5th argument.
3783	*/
3784	# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
3785
3786	/** @} */
3787
3788
3789	/** @name Opcode Decoder Function Types.
3790	* @{ */
3791
3792	/** @typedef PFNIEMOP
3793	* Pointer to an opcode decoder function.
3794	*/
3795
3796	/** @def FNIEMOP_DEF
3797	* Define an opcode decoder function.
3798	*
3799	* We're using macors for this so that adding and removing parameters as well as
3800	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL
3801	*
3802	* @param a_Name The function name.
3803	*/
3804
3805	/** @typedef PFNIEMOPRM
3806	* Pointer to an opcode decoder function with RM byte.
3807	*/
3808
3809	/** @def FNIEMOPRM_DEF
3810	* Define an opcode decoder function with RM byte.
3811	*
3812	* We're using macors for this so that adding and removing parameters as well as
3813	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL_1
3814	*
3815	* @param a_Name The function name.
3816	*/
3817
3818	#if defined(__GNUC__) && defined(RT_ARCH_X86)
3819	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOP)(PVMCPUCC pVCpu);
3820	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3821	# define FNIEMOP_DEF(a_Name) \
3822	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu)
3823	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3824	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
3825	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3826	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
3827
3828	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
3829	typedef VBOXSTRICTRC (__fastcall * PFNIEMOP)(PVMCPUCC pVCpu);
3830	typedef VBOXSTRICTRC (__fastcall * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3831	# define FNIEMOP_DEF(a_Name) \
3832	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
3833	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3834	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
3835	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3836	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
3837
3838	#elif defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
3839	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
3840	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3841	# define FNIEMOP_DEF(a_Name) \
3842	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu)
3843	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3844	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
3845	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3846	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
3847
3848	#else
3849	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
3850	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3851	# define FNIEMOP_DEF(a_Name) \
3852	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
3853	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3854	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
3855	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3856	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
3857
3858	#endif
3859	#define FNIEMOPRM_DEF(a_Name) FNIEMOP_DEF_1(a_Name, uint8_t, bRm)
3860
3861	/**
3862	* Call an opcode decoder function.
3863	*
3864	* We're using macors for this so that adding and removing parameters can be
3865	* done as we please. See FNIEMOP_DEF.
3866	*/
3867	#define FNIEMOP_CALL(a_pfn) (a_pfn)(pVCpu)
3868
3869	/**
3870	* Call a common opcode decoder function taking one extra argument.
3871	*
3872	* We're using macors for this so that adding and removing parameters can be
3873	* done as we please. See FNIEMOP_DEF_1.
3874	*/
3875	#define FNIEMOP_CALL_1(a_pfn, a0) (a_pfn)(pVCpu, a0)
3876
3877	/**
3878	* Call a common opcode decoder function taking one extra argument.
3879	*
3880	* We're using macors for this so that adding and removing parameters can be
3881	* done as we please. See FNIEMOP_DEF_1.
3882	*/
3883	#define FNIEMOP_CALL_2(a_pfn, a0, a1) (a_pfn)(pVCpu, a0, a1)
3884	/** @} */
3885
3886
3887	/** @name Misc Helpers
3888	* @{ */
3889
3890	/** Used to shut up GCC warnings about variables that 'may be used uninitialized'
3891	* due to GCC lacking knowledge about the value range of a switch. */
3892	#if RT_CPLUSPLUS_PREREQ(202000)
3893	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: [[unlikely]] AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
3894	#else
3895	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
3896	#endif
3897
3898	/** Variant of IEM_NOT_REACHED_DEFAULT_CASE_RET that returns a custom value. */
3899	#if RT_CPLUSPLUS_PREREQ(202000)
3900	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: [[unlikely]] AssertFailedReturn(a_RetValue)
3901	#else
3902	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: AssertFailedReturn(a_RetValue)
3903	#endif
3904
3905	/**
3906	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
3907	* occation.
3908	*/
3909	#ifdef LOG_ENABLED
3910	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
3911	do { \
3912	/Log/ LogAlways(("%s: returning IEM_RETURN_ASPECT_NOT_IMPLEMENTED (line %d)\n", __FUNCTION__, __LINE__)); \
3913	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
3914	} while (0)
3915	#else
3916	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
3917	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
3918	#endif
3919
3920	/**
3921	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
3922	* occation using the supplied logger statement.
3923	*
3924	* @param a_LoggerArgs What to log on failure.
3925	*/
3926	#ifdef LOG_ENABLED
3927	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
3928	do { \
3929	LogAlways((LOG_FN_FMT ": ", __PRETTY_FUNCTION__)); LogAlways(a_LoggerArgs); \
3930	/LogFunc(a_LoggerArgs);/ \
3931	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
3932	} while (0)
3933	#else
3934	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
3935	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
3936	#endif
3937
3938	/**
3939	* Gets the CPU mode (from fExec) as a IEMMODE value.
3940	*
3941	* @returns IEMMODE
3942	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3943	*/
3944	#define IEM_GET_CPU_MODE(a_pVCpu) ((a_pVCpu)->iem.s.fExec & IEM_F_MODE_CPUMODE_MASK)
3945
3946	/**
3947	* Check if we're currently executing in real or virtual 8086 mode.
3948	*
3949	* @returns @c true if it is, @c false if not.
3950	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3951	*/
3952	#define IEM_IS_REAL_OR_V86_MODE(a_pVCpu) (( ((a_pVCpu)->iem.s.fExec ^ IEM_F_MODE_X86_PROT_MASK) \
3953	& (IEM_F_MODE_X86_V86_MASK \| IEM_F_MODE_X86_PROT_MASK)) != 0)
3954
3955	/**
3956	* Check if we're currently executing in virtual 8086 mode.
3957	*
3958	* @returns @c true if it is, @c false if not.
3959	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3960	*/
3961	#define IEM_IS_V86_MODE(a_pVCpu) (((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_V86_MASK) != 0)
3962
3963	/**
3964	* Check if we're currently executing in long mode.
3965	*
3966	* @returns @c true if it is, @c false if not.
3967	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3968	*/
3969	#define IEM_IS_LONG_MODE(a_pVCpu) (CPUMIsGuestInLongModeEx(IEM_GET_CTX(a_pVCpu)))
3970
3971	/**
3972	* Check if we're currently executing in a 16-bit code segment.
3973	*
3974	* @returns @c true if it is, @c false if not.
3975	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3976	*/
3977	#define IEM_IS_16BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_16BIT)
3978
3979	/**
3980	* Check if we're currently executing in a 32-bit code segment.
3981	*
3982	* @returns @c true if it is, @c false if not.
3983	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3984	*/
3985	#define IEM_IS_32BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_32BIT)
3986
3987	/**
3988	* Check if we're currently executing in a 64-bit code segment.
3989	*
3990	* @returns @c true if it is, @c false if not.
3991	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3992	*/
3993	#define IEM_IS_64BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_64BIT)
3994
3995	/**
3996	* Check if we're currently executing in real mode.
3997	*
3998	* @returns @c true if it is, @c false if not.
3999	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4000	*/
4001	#define IEM_IS_REAL_MODE(a_pVCpu) (!((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_PROT_MASK))
4002
4003	/**
4004	* Gets the current protection level (CPL).
4005	*
4006	* @returns 0..3
4007	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4008	*/
4009	#define IEM_GET_CPL(a_pVCpu) (((a_pVCpu)->iem.s.fExec >> IEM_F_X86_CPL_SHIFT) & IEM_F_X86_CPL_SMASK)
4010
4011	/**
4012	* Sets the current protection level (CPL).
4013	*
4014	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4015	*/
4016	#define IEM_SET_CPL(a_pVCpu, a_uCpl) \
4017	do { (a_pVCpu)->iem.s.fExec = ((a_pVCpu)->iem.s.fExec & ~IEM_F_X86_CPL_MASK) \| ((a_uCpl) << IEM_F_X86_CPL_SHIFT); } while (0)
4018
4019	/**
4020	* Returns a (const) pointer to the CPUMFEATURES for the guest CPU.
4021	* @returns PCCPUMFEATURES
4022	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4023	*/
4024	#define IEM_GET_GUEST_CPU_FEATURES(a_pVCpu) (&((a_pVCpu)->CTX_SUFF(pVM)->cpum.ro.GuestFeatures))
4025
4026	/**
4027	* Returns a (const) pointer to the CPUMFEATURES for the host CPU.
4028	* @returns PCCPUMFEATURES
4029	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4030	*/
4031	#define IEM_GET_HOST_CPU_FEATURES(a_pVCpu) (&g_CpumHostFeatures.s)
4032
4033	/**
4034	* Evaluates to true if we're presenting an Intel CPU to the guest.
4035	*/
4036	#define IEM_IS_GUEST_CPU_INTEL(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL )
4037
4038	/**
4039	* Evaluates to true if we're presenting an AMD CPU to the guest.
4040	*/
4041	#define IEM_IS_GUEST_CPU_AMD(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_AMD \|\| (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_HYGON )
4042
4043	/**
4044	* Check if the address is canonical.
4045	*/
4046	#define IEM_IS_CANONICAL(a_u64Addr) X86_IS_CANONICAL(a_u64Addr)
4047
4048	/** Checks if the ModR/M byte is in register mode or not. */
4049	#define IEM_IS_MODRM_REG_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT) )
4050	/** Checks if the ModR/M byte is in memory mode or not. */
4051	#define IEM_IS_MODRM_MEM_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT) )
4052
4053	/**
4054	* Gets the register (reg) part of a ModR/M encoding, with REX.R added in.
4055	*
4056	* For use during decoding.
4057	*/
4058	#define IEM_GET_MODRM_REG(a_pVCpu, a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| (a_pVCpu)->iem.s.uRexReg )
4059	/**
4060	* Gets the r/m part of a ModR/M encoding as a register index, with REX.B added in.
4061	*
4062	* For use during decoding.
4063	*/
4064	#define IEM_GET_MODRM_RM(a_pVCpu, a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) \| (a_pVCpu)->iem.s.uRexB )
4065
4066	/**
4067	* Gets the register (reg) part of a ModR/M encoding, without REX.R.
4068	*
4069	* For use during decoding.
4070	*/
4071	#define IEM_GET_MODRM_REG_8(a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) )
4072	/**
4073	* Gets the r/m part of a ModR/M encoding as a register index, without REX.B.
4074	*
4075	* For use during decoding.
4076	*/
4077	#define IEM_GET_MODRM_RM_8(a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) )
4078
4079	/**
4080	* Gets the register (reg) part of a ModR/M encoding as an extended 8-bit
4081	* register index, with REX.R added in.
4082	*
4083	* For use during decoding.
4084	*
4085	* @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
4086	*/
4087	#define IEM_GET_MODRM_REG_EX8(a_pVCpu, a_bRm) \
4088	( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
4089	\|\| !((a_bRm) & (4 << X86_MODRM_REG_SHIFT)) /* IEM_GET_MODRM_REG(pVCpu, a_bRm) < 4 */ \
4090	? IEM_GET_MODRM_REG(pVCpu, a_bRm) : (((a_bRm) >> X86_MODRM_REG_SHIFT) & 3) \| 16)
4091	/**
4092	* Gets the r/m part of a ModR/M encoding as an extended 8-bit register index,
4093	* with REX.B added in.
4094	*
4095	* For use during decoding.
4096	*
4097	* @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
4098	*/
4099	#define IEM_GET_MODRM_RM_EX8(a_pVCpu, a_bRm) \
4100	( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
4101	\|\| !((a_bRm) & 4) /* IEM_GET_MODRM_RM(pVCpu, a_bRm) < 4 */ \
4102	? IEM_GET_MODRM_RM(pVCpu, a_bRm) : ((a_bRm) & 3) \| 16)
4103
4104	/**
4105	* Combines the prefix REX and ModR/M byte for passing to
4106	* iemOpHlpCalcRmEffAddrThreadedAddr64().
4107	*
4108	* @returns The ModRM byte but with bit 3 set to REX.B and bit 4 to REX.X.
4109	* The two bits are part of the REG sub-field, which isn't needed in
4110	* iemOpHlpCalcRmEffAddrThreadedAddr64().
4111	*
4112	* For use during decoding/recompiling.
4113	*/
4114	#define IEM_GET_MODRM_EX(a_pVCpu, a_bRm) \
4115	( ((a_bRm) & ~X86_MODRM_REG_MASK) \
4116	\| (uint8_t)( (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X)) >> (26 - 3) ) )
4117	AssertCompile(IEM_OP_PRF_REX_B == RT_BIT_32(26));
4118	AssertCompile(IEM_OP_PRF_REX_X == RT_BIT_32(27));
4119
4120	/**
4121	* Gets the effective VEX.VVVV value.
4122	*
4123	* The 4th bit is ignored if not 64-bit code.
4124	* @returns effective V-register value.
4125	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4126	*/
4127	#define IEM_GET_EFFECTIVE_VVVV(a_pVCpu) \
4128	(IEM_IS_64BIT_CODE(a_pVCpu) ? (a_pVCpu)->iem.s.uVex3rdReg : (a_pVCpu)->iem.s.uVex3rdReg & 7)
4129
4130
4131	/**
4132	* Checks if we're executing inside an AMD-V or VT-x guest.
4133	*/
4134	#if defined(VBOX_WITH_NESTED_HWVIRT_VMX) \|\| defined(VBOX_WITH_NESTED_HWVIRT_SVM)
4135	# define IEM_IS_IN_GUEST(a_pVCpu) RT_BOOL((a_pVCpu)->iem.s.fExec & IEM_F_X86_CTX_IN_GUEST)
4136	#else
4137	# define IEM_IS_IN_GUEST(a_pVCpu) false
4138	#endif
4139
4140
4141	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
4142
4143	/**
4144	* Check if the guest has entered VMX root operation.
4145	*/
4146	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxRootMode(IEM_GET_CTX(a_pVCpu)))
4147
4148	/**
4149	* Check if the guest has entered VMX non-root operation.
4150	*/
4151	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) ( ((a_pVCpu)->iem.s.fExec & (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST)) \
4152	== (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST) )
4153
4154	/**
4155	* Check if the nested-guest has the given Pin-based VM-execution control set.
4156	*/
4157	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_PinCtl) (CPUMIsGuestVmxPinCtlsSet(IEM_GET_CTX(a_pVCpu), (a_PinCtl)))
4158
4159	/**
4160	* Check if the nested-guest has the given Processor-based VM-execution control set.
4161	*/
4162	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_ProcCtl) (CPUMIsGuestVmxProcCtlsSet(IEM_GET_CTX(a_pVCpu), (a_ProcCtl)))
4163
4164	/**
4165	* Check if the nested-guest has the given Secondary Processor-based VM-execution
4166	* control set.
4167	*/
4168	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_ProcCtl2) (CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(a_pVCpu), (a_ProcCtl2)))
4169
4170	/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
4171	# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
4172
4173	/** Whether a shadow VMCS is present for the given VCPU. */
4174	# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
4175
4176	/** Gets the VMXON region pointer. */
4177	# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
4178
4179	/** Gets the guest-physical address of the current VMCS for the given VCPU. */
4180	# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
4181
4182	/** Whether a current VMCS is present for the given VCPU. */
4183	# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
4184
4185	/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
4186	# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
4187	do \
4188	{ \
4189	Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
4190	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
4191	} while (0)
4192
4193	/** Clears any current VMCS for the given VCPU. */
4194	# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
4195	do \
4196	{ \
4197	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
4198	} while (0)
4199
4200	/**
4201	* Invokes the VMX VM-exit handler for an instruction intercept.
4202	*/
4203	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) \
4204	do { return iemVmxVmexitInstr((a_pVCpu), (a_uExitReason), (a_cbInstr)); } while (0)
4205
4206	/**
4207	* Invokes the VMX VM-exit handler for an instruction intercept where the
4208	* instruction provides additional VM-exit information.
4209	*/
4210	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) \
4211	do { return iemVmxVmexitInstrNeedsInfo((a_pVCpu), (a_uExitReason), (a_uInstrId), (a_cbInstr)); } while (0)
4212
4213	/**
4214	* Invokes the VMX VM-exit handler for a task switch.
4215	*/
4216	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) \
4217	do { return iemVmxVmexitTaskSwitch((a_pVCpu), (a_enmTaskSwitch), (a_SelNewTss), (a_cbInstr)); } while (0)
4218
4219	/**
4220	* Invokes the VMX VM-exit handler for MWAIT.
4221	*/
4222	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) \
4223	do { return iemVmxVmexitInstrMwait((a_pVCpu), (a_fMonitorArmed), (a_cbInstr)); } while (0)
4224
4225	/**
4226	* Invokes the VMX VM-exit handler for EPT faults.
4227	*/
4228	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) \
4229	do { return iemVmxVmexitEpt(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr); } while (0)
4230
4231	/**
4232	* Invokes the VMX VM-exit handler.
4233	*/
4234	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) \
4235	do { return iemVmxVmexit((a_pVCpu), (a_uExitReason), (a_uExitQual)); } while (0)
4236
4237	#else
4238	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (false)
4239	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (false)
4240	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_cbInstr) (false)
4241	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_cbInstr) (false)
4242	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_cbInstr) (false)
4243	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4244	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4245	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4246	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4247	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4248	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) do { return VERR_VMX_IPE_1; } while (0)
4249
4250	#endif
4251
4252	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4253	/**
4254	* Checks if we're executing a guest using AMD-V.
4255	*/
4256	# define IEM_SVM_IS_IN_GUEST(a_pVCpu) ( (a_pVCpu->iem.s.fExec & (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST)) \
4257	== (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST))
4258	/**
4259	* Check if an SVM control/instruction intercept is set.
4260	*/
4261	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) \
4262	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmCtrlInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_Intercept)))
4263
4264	/**
4265	* Check if an SVM read CRx intercept is set.
4266	*/
4267	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
4268	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
4269
4270	/**
4271	* Check if an SVM write CRx intercept is set.
4272	*/
4273	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
4274	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
4275
4276	/**
4277	* Check if an SVM read DRx intercept is set.
4278	*/
4279	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
4280	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
4281
4282	/**
4283	* Check if an SVM write DRx intercept is set.
4284	*/
4285	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
4286	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
4287
4288	/**
4289	* Check if an SVM exception intercept is set.
4290	*/
4291	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) \
4292	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmXcptInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uVector)))
4293
4294	/**
4295	* Invokes the SVM \#VMEXIT handler for the nested-guest.
4296	*/
4297	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
4298	do { return iemSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2)); } while (0)
4299
4300	/**
4301	* Invokes the 'MOV CRx' SVM \#VMEXIT handler after constructing the
4302	* corresponding decode assist information.
4303	*/
4304	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) \
4305	do \
4306	{ \
4307	uint64_t uExitInfo1; \
4308	if ( IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmDecodeAssists \
4309	&& (a_enmAccessCrX) == IEMACCESSCRX_MOV_CRX) \
4310	uExitInfo1 = SVM_EXIT1_MOV_CRX_MASK \| ((a_iGReg) & 7); \
4311	else \
4312	uExitInfo1 = 0; \
4313	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, uExitInfo1, 0); \
4314	} while (0)
4315
4316	/** Check and handles SVM nested-guest instruction intercept and updates
4317	* NRIP if needed.
4318	*/
4319	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
4320	do \
4321	{ \
4322	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept)) \
4323	{ \
4324	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
4325	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2); \
4326	} \
4327	} while (0)
4328
4329	/** Checks and handles SVM nested-guest CR0 read intercept. */
4330	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
4331	do \
4332	{ \
4333	if (!IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, 0)) \
4334	{ /* probably likely */ } \
4335	else \
4336	{ \
4337	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
4338	IEM_SVM_VMEXIT_RET(a_pVCpu, SVM_EXIT_READ_CR0, a_uExitInfo1, a_uExitInfo2); \
4339	} \
4340	} while (0)
4341
4342	/**
4343	* Updates the NextRIP (NRI) field in the nested-guest VMCB.
4344	*/
4345	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) \
4346	do { \
4347	if (IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmNextRipSave) \
4348	CPUMGuestSvmUpdateNRip(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_cbInstr)); \
4349	} while (0)
4350
4351	#else
4352	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) (false)
4353	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
4354	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
4355	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
4356	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
4357	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) (false)
4358	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { return VERR_SVM_IPE_1; } while (0)
4359	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) do { return VERR_SVM_IPE_1; } while (0)
4360	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, \
4361	a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
4362	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
4363	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) do { } while (0)
4364
4365	#endif
4366
4367	/** @} */
4368
4369	uint32_t iemCalcExecDbgFlagsSlow(PVMCPUCC pVCpu);
4370	VBOXSTRICTRC iemExecInjectPendingTrap(PVMCPUCC pVCpu);
4371
4372
4373	/**
4374	* Selector descriptor table entry as fetched by iemMemFetchSelDesc.
4375	*/
4376	typedef union IEMSELDESC
4377	{
4378	/** The legacy view. */
4379	X86DESC Legacy;
4380	/** The long mode view. */
4381	X86DESC64 Long;
4382	} IEMSELDESC;
4383	/** Pointer to a selector descriptor table entry. */
4384	typedef IEMSELDESC *PIEMSELDESC;
4385
4386	/** @name Raising Exceptions.
4387	* @{ */
4388	VBOXSTRICTRC iemTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, uint32_t uNextEip, uint32_t fFlags,
4389	uint16_t uErr, uint64_t uCr2, RTSEL SelTSS, PIEMSELDESC pNewDescTSS) RT_NOEXCEPT;
4390
4391	VBOXSTRICTRC iemRaiseXcptOrInt(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags,
4392	uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
4393	#ifdef IEM_WITH_SETJMP
4394	DECL_NO_RETURN(void) iemRaiseXcptOrIntJmp(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector,
4395	uint32_t fFlags, uint16_t uErr, uint64_t uCr2) IEM_NOEXCEPT_MAY_LONGJMP;
4396	#endif
4397	VBOXSTRICTRC iemRaiseDivideError(PVMCPUCC pVCpu) RT_NOEXCEPT;
4398	VBOXSTRICTRC iemRaiseDebugException(PVMCPUCC pVCpu) RT_NOEXCEPT;
4399	VBOXSTRICTRC iemRaiseBoundRangeExceeded(PVMCPUCC pVCpu) RT_NOEXCEPT;
4400	VBOXSTRICTRC iemRaiseUndefinedOpcode(PVMCPUCC pVCpu) RT_NOEXCEPT;
4401	VBOXSTRICTRC iemRaiseDeviceNotAvailable(PVMCPUCC pVCpu) RT_NOEXCEPT;
4402	VBOXSTRICTRC iemRaiseTaskSwitchFaultWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
4403	VBOXSTRICTRC iemRaiseTaskSwitchFaultCurrentTSS(PVMCPUCC pVCpu) RT_NOEXCEPT;
4404	VBOXSTRICTRC iemRaiseTaskSwitchFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
4405	VBOXSTRICTRC iemRaiseTaskSwitchFaultBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
4406	/VBOXSTRICTRC iemRaiseSelectorNotPresent(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;/
4407	VBOXSTRICTRC iemRaiseSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
4408	VBOXSTRICTRC iemRaiseSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
4409	VBOXSTRICTRC iemRaiseStackSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
4410	VBOXSTRICTRC iemRaiseStackSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
4411	VBOXSTRICTRC iemRaiseGeneralProtectionFault(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
4412	VBOXSTRICTRC iemRaiseGeneralProtectionFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
4413	#ifdef IEM_WITH_SETJMP
4414	DECL_NO_RETURN(void) iemRaiseGeneralProtectionFault0Jmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4415	#endif
4416	VBOXSTRICTRC iemRaiseGeneralProtectionFaultBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
4417	VBOXSTRICTRC iemRaiseNotCanonical(PVMCPUCC pVCpu) RT_NOEXCEPT;
4418	VBOXSTRICTRC iemRaiseSelectorBounds(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
4419	#ifdef IEM_WITH_SETJMP
4420	DECL_NO_RETURN(void) iemRaiseSelectorBoundsJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
4421	#endif
4422	VBOXSTRICTRC iemRaiseSelectorBoundsBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
4423	#ifdef IEM_WITH_SETJMP
4424	DECL_NO_RETURN(void) iemRaiseSelectorBoundsBySelectorJmp(PVMCPUCC pVCpu, RTSEL Sel) IEM_NOEXCEPT_MAY_LONGJMP;
4425	#endif
4426	VBOXSTRICTRC iemRaiseSelectorInvalidAccess(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
4427	#ifdef IEM_WITH_SETJMP
4428	DECL_NO_RETURN(void) iemRaiseSelectorInvalidAccessJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
4429	#endif
4430	VBOXSTRICTRC iemRaisePageFault(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) RT_NOEXCEPT;
4431	#ifdef IEM_WITH_SETJMP
4432	DECL_NO_RETURN(void) iemRaisePageFaultJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) IEM_NOEXCEPT_MAY_LONGJMP;
4433	#endif
4434	VBOXSTRICTRC iemRaiseMathFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
4435	VBOXSTRICTRC iemRaiseAlignmentCheckException(PVMCPUCC pVCpu) RT_NOEXCEPT;
4436	#ifdef IEM_WITH_SETJMP
4437	DECL_NO_RETURN(void) iemRaiseAlignmentCheckExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4438	#endif
4439	VBOXSTRICTRC iemRaiseSimdFpException(PVMCPUCC pVCpu) RT_NOEXCEPT;
4440
4441	void iemLogSyscallProtModeInt(PVMCPUCC pVCpu, uint8_t u8Vector, uint8_t cbInstr);
4442
4443	IEM_CIMPL_DEF_0(iemCImplRaiseDivideError);
4444	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidLockPrefix);
4445	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidOpcode);
4446
4447	/**
4448	* Macro for calling iemCImplRaiseDivideError().
4449	*
4450	* This is for things that will _always_ decode to an \#DE, taking the
4451	* recompiler into consideration and everything.
4452	*
4453	* @return Strict VBox status code.
4454	*/
4455	#define IEMOP_RAISE_DIVIDE_ERROR_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, iemCImplRaiseDivideError)
4456
4457	/**
4458	* Macro for calling iemCImplRaiseInvalidLockPrefix().
4459	*
4460	* This is for things that will _always_ decode to an \#UD, taking the
4461	* recompiler into consideration and everything.
4462	*
4463	* @return Strict VBox status code.
4464	*/
4465	#define IEMOP_RAISE_INVALID_LOCK_PREFIX_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, iemCImplRaiseInvalidLockPrefix)
4466
4467	/**
4468	* Macro for calling iemCImplRaiseInvalidOpcode() for decode/static \#UDs.
4469	*
4470	* This is for things that will _always_ decode to an \#UD, taking the
4471	* recompiler into consideration and everything.
4472	*
4473	* @return Strict VBox status code.
4474	*/
4475	#define IEMOP_RAISE_INVALID_OPCODE_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, iemCImplRaiseInvalidOpcode)
4476
4477	/**
4478	* Macro for calling iemCImplRaiseInvalidOpcode() for runtime-style \#UDs.
4479	*
4480	* Using this macro means you've got _buggy_ _code_ and are doing things that
4481	* belongs exclusively in IEMAllCImpl.cpp during decoding.
4482	*
4483	* @return Strict VBox status code.
4484	* @see IEMOP_RAISE_INVALID_OPCODE_RET
4485	*/
4486	#define IEMOP_RAISE_INVALID_OPCODE_RUNTIME_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, iemCImplRaiseInvalidOpcode)
4487
4488	/** @} */
4489
4490	/** @name Register Access.
4491	* @{ */
4492	VBOXSTRICTRC iemRegRipRelativeJumpS8AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int8_t offNextInstr,
4493	IEMMODE enmEffOpSize) RT_NOEXCEPT;
4494	VBOXSTRICTRC iemRegRipRelativeJumpS16AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int16_t offNextInstr) RT_NOEXCEPT;
4495	VBOXSTRICTRC iemRegRipRelativeJumpS32AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int32_t offNextInstr,
4496	IEMMODE enmEffOpSize) RT_NOEXCEPT;
4497	VBOXSTRICTRC iemRegRipJumpU16AndFinishClearningRF(PVMCPUCC pVCpu, uint16_t uNewRip) RT_NOEXCEPT;
4498	VBOXSTRICTRC iemRegRipJumpU32AndFinishClearningRF(PVMCPUCC pVCpu, uint32_t uNewRip) RT_NOEXCEPT;
4499	VBOXSTRICTRC iemRegRipJumpU64AndFinishClearningRF(PVMCPUCC pVCpu, uint64_t uNewRip) RT_NOEXCEPT;
4500	/** @} */
4501
4502	/** @name FPU access and helpers.
4503	* @{ */
4504	void iemFpuPushResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
4505	void iemFpuPushResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4506	void iemFpuPushResultTwo(PVMCPUCC pVCpu, PIEMFPURESULTTWO pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
4507	void iemFpuStoreResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
4508	void iemFpuStoreResultThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
4509	void iemFpuStoreResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
4510	uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4511	void iemFpuStoreResultWithMemOpThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
4512	uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4513	void iemFpuUpdateOpcodeAndIp(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
4514	void iemFpuUpdateFSW(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
4515	void iemFpuUpdateFSWThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
4516	void iemFpuUpdateFSWWithMemOp(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4517	void iemFpuUpdateFSWThenPopPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
4518	void iemFpuUpdateFSWWithMemOpThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4519	void iemFpuStackUnderflow(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
4520	void iemFpuStackUnderflowWithMemOp(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4521	void iemFpuStackUnderflowThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
4522	void iemFpuStackUnderflowWithMemOpThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4523	void iemFpuStackUnderflowThenPopPop(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
4524	void iemFpuStackPushUnderflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
4525	void iemFpuStackPushUnderflowTwo(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
4526	void iemFpuStackPushOverflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
4527	void iemFpuStackPushOverflowWithMemOp(PVMCPUCC pVCpu, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4528	/** @} */
4529
4530	/** @name SSE+AVX SIMD access and helpers.
4531	* @{ */
4532	void iemSseStoreResult(PVMCPUCC pVCpu, PCIEMSSERESULT pResult, uint8_t iXmmReg) RT_NOEXCEPT;
4533	void iemSseUpdateMxcsr(PVMCPUCC pVCpu, uint32_t fMxcsr) RT_NOEXCEPT;
4534	/** @} */
4535
4536	/** @name Memory access.
4537	* @{ */
4538
4539	/** Report a \#GP instead of \#AC and do not restrict to ring-3 */
4540	#define IEM_MEMMAP_F_ALIGN_GP RT_BIT_32(16)
4541	/** SSE access that should report a \#GP instead of \#AC, unless MXCSR.MM=1
4542	* when it works like normal \#AC. Always used with IEM_MEMMAP_F_ALIGN_GP. */
4543	#define IEM_MEMMAP_F_ALIGN_SSE RT_BIT_32(17)
4544	/** If \#AC is applicable, raise it. Always used with IEM_MEMMAP_F_ALIGN_GP.
4545	* Users include FXSAVE & FXRSTOR. */
4546	#define IEM_MEMMAP_F_ALIGN_GP_OR_AC RT_BIT_32(18)
4547
4548	VBOXSTRICTRC iemMemMap(PVMCPUCC pVCpu, void **ppvMem, size_t cbMem, uint8_t iSegReg, RTGCPTR GCPtrMem,
4549	uint32_t fAccess, uint32_t uAlignCtl) RT_NOEXCEPT;
4550	VBOXSTRICTRC iemMemCommitAndUnmap(PVMCPUCC pVCpu, void *pvMem, uint32_t fAccess) RT_NOEXCEPT;
4551	#ifndef IN_RING3
4552	VBOXSTRICTRC iemMemCommitAndUnmapPostponeTroubleToR3(PVMCPUCC pVCpu, void *pvMem, uint32_t fAccess) RT_NOEXCEPT;
4553	#endif
4554	void iemMemRollback(PVMCPUCC pVCpu) RT_NOEXCEPT;
4555	VBOXSTRICTRC iemMemApplySegment(PVMCPUCC pVCpu, uint32_t fAccess, uint8_t iSegReg, size_t cbMem, PRTGCPTR pGCPtrMem) RT_NOEXCEPT;
4556	VBOXSTRICTRC iemMemMarkSelDescAccessed(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
4557	VBOXSTRICTRC iemMemPageTranslateAndCheckAccess(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t cbAccess, uint32_t fAccess, PRTGCPHYS pGCPhysMem) RT_NOEXCEPT;
4558
4559	void iemOpcodeFlushLight(PVMCPUCC pVCpu, uint8_t cbInstr);
4560	void iemOpcodeFlushHeavy(PVMCPUCC pVCpu, uint8_t cbInstr);
4561	#ifdef IEM_WITH_CODE_TLB
4562	void iemOpcodeFetchBytesJmp(PVMCPUCC pVCpu, size_t cbDst, void *pvDst) IEM_NOEXCEPT_MAY_LONGJMP;
4563	#else
4564	VBOXSTRICTRC iemOpcodeFetchMoreBytes(PVMCPUCC pVCpu, size_t cbMin) RT_NOEXCEPT;
4565	#endif
4566	#ifdef IEM_WITH_SETJMP
4567	uint8_t iemOpcodeGetNextU8SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4568	uint16_t iemOpcodeGetNextU16SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4569	uint32_t iemOpcodeGetNextU32SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4570	uint64_t iemOpcodeGetNextU64SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4571	#else
4572	VBOXSTRICTRC iemOpcodeGetNextU8Slow(PVMCPUCC pVCpu, uint8_t *pb) RT_NOEXCEPT;
4573	VBOXSTRICTRC iemOpcodeGetNextS8SxU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
4574	VBOXSTRICTRC iemOpcodeGetNextS8SxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
4575	VBOXSTRICTRC iemOpcodeGetNextS8SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
4576	VBOXSTRICTRC iemOpcodeGetNextU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
4577	VBOXSTRICTRC iemOpcodeGetNextU16ZxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
4578	VBOXSTRICTRC iemOpcodeGetNextU16ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
4579	VBOXSTRICTRC iemOpcodeGetNextU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
4580	VBOXSTRICTRC iemOpcodeGetNextU32ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
4581	VBOXSTRICTRC iemOpcodeGetNextS32SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
4582	VBOXSTRICTRC iemOpcodeGetNextU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
4583	#endif
4584
4585	VBOXSTRICTRC iemMemFetchDataU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4586	VBOXSTRICTRC iemMemFetchDataU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4587	VBOXSTRICTRC iemMemFetchDataU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4588	VBOXSTRICTRC iemMemFetchDataU32_ZX_U64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4589	VBOXSTRICTRC iemMemFetchDataU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4590	VBOXSTRICTRC iemMemFetchDataU64AlignedU128(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4591	VBOXSTRICTRC iemMemFetchDataR80(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4592	VBOXSTRICTRC iemMemFetchDataD80(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4593	VBOXSTRICTRC iemMemFetchDataU128(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4594	VBOXSTRICTRC iemMemFetchDataU128AlignedSse(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4595	VBOXSTRICTRC iemMemFetchDataU256(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4596	VBOXSTRICTRC iemMemFetchDataU256AlignedSse(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4597	VBOXSTRICTRC iemMemFetchDataXdtr(PVMCPUCC pVCpu, uint16_t *pcbLimit, PRTGCPTR pGCPtrBase, uint8_t iSegReg,
4598	RTGCPTR GCPtrMem, IEMMODE enmOpSize) RT_NOEXCEPT;
4599	#ifdef IEM_WITH_SETJMP
4600	uint8_t iemMemFetchDataU8SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4601	uint16_t iemMemFetchDataU16SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4602	uint32_t iemMemFetchDataU32SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4603	uint32_t iemMemFlatFetchDataU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4604	uint64_t iemMemFetchDataU64SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4605	uint64_t iemMemFetchDataU64AlignedU128SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4606	void iemMemFetchDataR80SafeJmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4607	void iemMemFetchDataD80SafeJmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4608	void iemMemFetchDataU128SafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4609	void iemMemFetchDataU128AlignedSseSafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4610	void iemMemFetchDataU256SafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4611	void iemMemFetchDataU256AlignedSseSafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4612	# if 0 /* these are inlined now */
4613	uint8_t iemMemFetchDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4614	uint16_t iemMemFetchDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4615	uint32_t iemMemFetchDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4616	uint32_t iemMemFlatFetchDataU32Jmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4617	uint64_t iemMemFetchDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4618	uint64_t iemMemFetchDataU64AlignedU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4619	# endif
4620	void iemMemFetchDataR80Jmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4621	void iemMemFetchDataD80Jmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4622	void iemMemFetchDataU128Jmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4623	void iemMemFetchDataU128AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4624	void iemMemFetchDataU256Jmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4625	void iemMemFetchDataU256AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4626	#endif
4627
4628	VBOXSTRICTRC iemMemFetchSysU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4629	VBOXSTRICTRC iemMemFetchSysU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4630	VBOXSTRICTRC iemMemFetchSysU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4631	VBOXSTRICTRC iemMemFetchSysU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4632	VBOXSTRICTRC iemMemFetchSelDesc(PVMCPUCC pVCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt) RT_NOEXCEPT;
4633
4634	VBOXSTRICTRC iemMemStoreDataU8(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) RT_NOEXCEPT;
4635	VBOXSTRICTRC iemMemStoreDataU16(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) RT_NOEXCEPT;
4636	VBOXSTRICTRC iemMemStoreDataU32(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) RT_NOEXCEPT;
4637	VBOXSTRICTRC iemMemStoreDataU64(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) RT_NOEXCEPT;
4638	VBOXSTRICTRC iemMemStoreDataU128(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
4639	VBOXSTRICTRC iemMemStoreDataU128AlignedSse(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
4640	VBOXSTRICTRC iemMemStoreDataU256(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
4641	VBOXSTRICTRC iemMemStoreDataU256AlignedAvx(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
4642	VBOXSTRICTRC iemMemStoreDataXdtr(PVMCPUCC pVCpu, uint16_t cbLimit, RTGCPTR GCPtrBase, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4643	#ifdef IEM_WITH_SETJMP
4644	void iemMemStoreDataU8SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
4645	void iemMemStoreDataU16SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
4646	void iemMemStoreDataU32SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
4647	void iemMemStoreDataU64SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
4648	void iemMemStoreDataU128SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
4649	void iemMemStoreDataU128AlignedSseSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
4650	void iemMemStoreDataU256SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
4651	void iemMemStoreDataU256AlignedAvxSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
4652	#if 0
4653	void iemMemStoreDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
4654	void iemMemStoreDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
4655	void iemMemStoreDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
4656	void iemMemStoreDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
4657	#endif
4658	void iemMemStoreDataU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
4659	void iemMemStoreDataU128AlignedSseJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
4660	void iemMemStoreDataU256Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
4661	void iemMemStoreDataU256AlignedAvxJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
4662	#endif
4663
4664	#ifdef IEM_WITH_SETJMP
4665	uint8_t iemMemMapDataU8RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4666	uint8_t iemMemMapDataU8WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4667	uint8_t const iemMemMapDataU8RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4668	uint16_t iemMemMapDataU16RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4669	uint16_t iemMemMapDataU16WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4670	uint16_t const iemMemMapDataU16RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4671	uint32_t iemMemMapDataU32RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4672	uint32_t iemMemMapDataU32WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4673	uint32_t const iemMemMapDataU32RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4674	uint64_t iemMemMapDataU64RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4675	uint64_t iemMemMapDataU64WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4676	uint64_t const iemMemMapDataU64RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4677
4678	void iemMemCommitAndUnmapRwSafeJmp(PVMCPUCC pVCpu, void *pvMem, uint8_t bMapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
4679	void iemMemCommitAndUnmapWoSafeJmp(PVMCPUCC pVCpu, void *pvMem, uint8_t bMapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
4680	void iemMemCommitAndUnmapRoSafeJmp(PVMCPUCC pVCpu, const void *pvMem, uint8_t bMapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
4681	#endif
4682
4683	VBOXSTRICTRC iemMemStackPushBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
4684	void *ppvMem, uint64_t puNewRsp) RT_NOEXCEPT;
4685	VBOXSTRICTRC iemMemStackPushCommitSpecial(PVMCPUCC pVCpu, void *pvMem, uint64_t uNewRsp) RT_NOEXCEPT;
4686	VBOXSTRICTRC iemMemStackPushU16(PVMCPUCC pVCpu, uint16_t u16Value) RT_NOEXCEPT;
4687	VBOXSTRICTRC iemMemStackPushU32(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
4688	VBOXSTRICTRC iemMemStackPushU64(PVMCPUCC pVCpu, uint64_t u64Value) RT_NOEXCEPT;
4689	VBOXSTRICTRC iemMemStackPushU16Ex(PVMCPUCC pVCpu, uint16_t u16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4690	VBOXSTRICTRC iemMemStackPushU32Ex(PVMCPUCC pVCpu, uint32_t u32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4691	VBOXSTRICTRC iemMemStackPushU64Ex(PVMCPUCC pVCpu, uint64_t u64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4692	VBOXSTRICTRC iemMemStackPushU32SReg(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
4693	VBOXSTRICTRC iemMemStackPopBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
4694	void const *ppvMem, uint64_t puNewRsp) RT_NOEXCEPT;
4695	VBOXSTRICTRC iemMemStackPopContinueSpecial(PVMCPUCC pVCpu, size_t off, size_t cbMem,
4696	void const **ppvMem, uint64_t uCurNewRsp) RT_NOEXCEPT;
4697	VBOXSTRICTRC iemMemStackPopDoneSpecial(PVMCPUCC pVCpu, void const *pvMem) RT_NOEXCEPT;
4698	VBOXSTRICTRC iemMemStackPopU16(PVMCPUCC pVCpu, uint16_t *pu16Value) RT_NOEXCEPT;
4699	VBOXSTRICTRC iemMemStackPopU32(PVMCPUCC pVCpu, uint32_t *pu32Value) RT_NOEXCEPT;
4700	VBOXSTRICTRC iemMemStackPopU64(PVMCPUCC pVCpu, uint64_t *pu64Value) RT_NOEXCEPT;
4701	VBOXSTRICTRC iemMemStackPopU16Ex(PVMCPUCC pVCpu, uint16_t *pu16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4702	VBOXSTRICTRC iemMemStackPopU32Ex(PVMCPUCC pVCpu, uint32_t *pu32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4703	VBOXSTRICTRC iemMemStackPopU64Ex(PVMCPUCC pVCpu, uint64_t *pu64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4704	/** @} */
4705
4706	/** @name IEMAllCImpl.cpp
4707	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/'
4708	* @{ */
4709	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem16, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4710	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem32, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4711	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem64, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4712	IEM_CIMPL_PROTO_0(iemCImpl_popa_16);
4713	IEM_CIMPL_PROTO_0(iemCImpl_popa_32);
4714	IEM_CIMPL_PROTO_0(iemCImpl_pusha_16);
4715	IEM_CIMPL_PROTO_0(iemCImpl_pusha_32);
4716	IEM_CIMPL_PROTO_1(iemCImpl_pushf, IEMMODE, enmEffOpSize);
4717	IEM_CIMPL_PROTO_1(iemCImpl_popf, IEMMODE, enmEffOpSize);
4718	IEM_CIMPL_PROTO_1(iemCImpl_call_16, uint16_t, uNewPC);
4719	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_16, int16_t, offDisp);
4720	IEM_CIMPL_PROTO_1(iemCImpl_call_32, uint32_t, uNewPC);
4721	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_32, int32_t, offDisp);
4722	IEM_CIMPL_PROTO_1(iemCImpl_call_64, uint64_t, uNewPC);
4723	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_64, int64_t, offDisp);
4724	IEM_CIMPL_PROTO_3(iemCImpl_FarJmp, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
4725	IEM_CIMPL_PROTO_3(iemCImpl_callf, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
4726	typedef IEM_CIMPL_DECL_TYPE_3(FNIEMCIMPLFARBRANCH, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
4727	typedef FNIEMCIMPLFARBRANCH *PFNIEMCIMPLFARBRANCH;
4728	IEM_CIMPL_PROTO_2(iemCImpl_retf, IEMMODE, enmEffOpSize, uint16_t, cbPop);
4729	IEM_CIMPL_PROTO_0(iemCImpl_retn_16);
4730	IEM_CIMPL_PROTO_0(iemCImpl_retn_32);
4731	IEM_CIMPL_PROTO_0(iemCImpl_retn_64);
4732	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_16, uint16_t, cbPop);
4733	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_32, uint16_t, cbPop);
4734	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_64, uint16_t, cbPop);
4735	IEM_CIMPL_PROTO_3(iemCImpl_enter, IEMMODE, enmEffOpSize, uint16_t, cbFrame, uint8_t, cParameters);
4736	IEM_CIMPL_PROTO_1(iemCImpl_leave, IEMMODE, enmEffOpSize);
4737	IEM_CIMPL_PROTO_2(iemCImpl_int, uint8_t, u8Int, IEMINT, enmInt);
4738	IEM_CIMPL_PROTO_1(iemCImpl_iret_real_v8086, IEMMODE, enmEffOpSize);
4739	IEM_CIMPL_PROTO_4(iemCImpl_iret_prot_v8086, uint32_t, uNewEip, uint16_t, uNewCs, uint32_t, uNewFlags, uint64_t, uNewRsp);
4740	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot_NestedTask, IEMMODE, enmEffOpSize);
4741	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot, IEMMODE, enmEffOpSize);
4742	IEM_CIMPL_PROTO_1(iemCImpl_iret_64bit, IEMMODE, enmEffOpSize);
4743	IEM_CIMPL_PROTO_1(iemCImpl_iret, IEMMODE, enmEffOpSize);
4744	IEM_CIMPL_PROTO_0(iemCImpl_loadall286);
4745	IEM_CIMPL_PROTO_0(iemCImpl_syscall);
4746	IEM_CIMPL_PROTO_1(iemCImpl_sysret, IEMMODE, enmEffOpSize);
4747	IEM_CIMPL_PROTO_0(iemCImpl_sysenter);
4748	IEM_CIMPL_PROTO_1(iemCImpl_sysexit, IEMMODE, enmEffOpSize);
4749	IEM_CIMPL_PROTO_2(iemCImpl_LoadSReg, uint8_t, iSegReg, uint16_t, uSel);
4750	IEM_CIMPL_PROTO_2(iemCImpl_load_SReg, uint8_t, iSegReg, uint16_t, uSel);
4751	IEM_CIMPL_PROTO_2(iemCImpl_pop_Sreg, uint8_t, iSegReg, IEMMODE, enmEffOpSize);
4752	IEM_CIMPL_PROTO_5(iemCImpl_load_SReg_Greg, uint16_t, uSel, uint64_t, offSeg, uint8_t, iSegReg, uint8_t, iGReg, IEMMODE, enmEffOpSize);
4753	IEM_CIMPL_PROTO_2(iemCImpl_VerX, uint16_t, uSel, bool, fWrite);
4754	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u64, uint64_t *, pu64Dst, uint16_t, uSel, bool, fIsLar);
4755	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u16, uint16_t *, pu16Dst, uint16_t, uSel, bool, fIsLar);
4756	IEM_CIMPL_PROTO_3(iemCImpl_lgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
4757	IEM_CIMPL_PROTO_2(iemCImpl_sgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4758	IEM_CIMPL_PROTO_3(iemCImpl_lidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
4759	IEM_CIMPL_PROTO_2(iemCImpl_sidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4760	IEM_CIMPL_PROTO_1(iemCImpl_lldt, uint16_t, uNewLdt);
4761	IEM_CIMPL_PROTO_2(iemCImpl_sldt_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
4762	IEM_CIMPL_PROTO_2(iemCImpl_sldt_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4763	IEM_CIMPL_PROTO_1(iemCImpl_ltr, uint16_t, uNewTr);
4764	IEM_CIMPL_PROTO_2(iemCImpl_str_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
4765	IEM_CIMPL_PROTO_2(iemCImpl_str_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4766	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Cd, uint8_t, iGReg, uint8_t, iCrReg);
4767	IEM_CIMPL_PROTO_2(iemCImpl_smsw_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
4768	IEM_CIMPL_PROTO_2(iemCImpl_smsw_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4769	IEM_CIMPL_PROTO_4(iemCImpl_load_CrX, uint8_t, iCrReg, uint64_t, uNewCrX, IEMACCESSCRX, enmAccessCrX, uint8_t, iGReg);
4770	IEM_CIMPL_PROTO_2(iemCImpl_mov_Cd_Rd, uint8_t, iCrReg, uint8_t, iGReg);
4771	IEM_CIMPL_PROTO_2(iemCImpl_lmsw, uint16_t, u16NewMsw, RTGCPTR, GCPtrEffDst);
4772	IEM_CIMPL_PROTO_0(iemCImpl_clts);
4773	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Dd, uint8_t, iGReg, uint8_t, iDrReg);
4774	IEM_CIMPL_PROTO_2(iemCImpl_mov_Dd_Rd, uint8_t, iDrReg, uint8_t, iGReg);
4775	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Td, uint8_t, iGReg, uint8_t, iTrReg);
4776	IEM_CIMPL_PROTO_2(iemCImpl_mov_Td_Rd, uint8_t, iTrReg, uint8_t, iGReg);
4777	IEM_CIMPL_PROTO_1(iemCImpl_invlpg, RTGCPTR, GCPtrPage);
4778	IEM_CIMPL_PROTO_3(iemCImpl_invpcid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvpcidDesc, uint64_t, uInvpcidType);
4779	IEM_CIMPL_PROTO_0(iemCImpl_invd);
4780	IEM_CIMPL_PROTO_0(iemCImpl_wbinvd);
4781	IEM_CIMPL_PROTO_0(iemCImpl_rsm);
4782	IEM_CIMPL_PROTO_0(iemCImpl_rdtsc);
4783	IEM_CIMPL_PROTO_0(iemCImpl_rdtscp);
4784	IEM_CIMPL_PROTO_0(iemCImpl_rdpmc);
4785	IEM_CIMPL_PROTO_0(iemCImpl_rdmsr);
4786	IEM_CIMPL_PROTO_0(iemCImpl_wrmsr);
4787	IEM_CIMPL_PROTO_3(iemCImpl_in, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
4788	IEM_CIMPL_PROTO_2(iemCImpl_in_eAX_DX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
4789	IEM_CIMPL_PROTO_3(iemCImpl_out, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
4790	IEM_CIMPL_PROTO_2(iemCImpl_out_DX_eAX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
4791	IEM_CIMPL_PROTO_0(iemCImpl_cli);
4792	IEM_CIMPL_PROTO_0(iemCImpl_sti);
4793	IEM_CIMPL_PROTO_0(iemCImpl_hlt);
4794	IEM_CIMPL_PROTO_1(iemCImpl_monitor, uint8_t, iEffSeg);
4795	IEM_CIMPL_PROTO_0(iemCImpl_mwait);
4796	IEM_CIMPL_PROTO_0(iemCImpl_swapgs);
4797	IEM_CIMPL_PROTO_0(iemCImpl_cpuid);
4798	IEM_CIMPL_PROTO_1(iemCImpl_aad, uint8_t, bImm);
4799	IEM_CIMPL_PROTO_1(iemCImpl_aam, uint8_t, bImm);
4800	IEM_CIMPL_PROTO_0(iemCImpl_daa);
4801	IEM_CIMPL_PROTO_0(iemCImpl_das);
4802	IEM_CIMPL_PROTO_0(iemCImpl_aaa);
4803	IEM_CIMPL_PROTO_0(iemCImpl_aas);
4804	IEM_CIMPL_PROTO_3(iemCImpl_bound_16, int16_t, idxArray, int16_t, idxLowerBound, int16_t, idxUpperBound);
4805	IEM_CIMPL_PROTO_3(iemCImpl_bound_32, int32_t, idxArray, int32_t, idxLowerBound, int32_t, idxUpperBound);
4806	IEM_CIMPL_PROTO_0(iemCImpl_xgetbv);
4807	IEM_CIMPL_PROTO_0(iemCImpl_xsetbv);
4808	IEM_CIMPL_PROTO_4(iemCImpl_cmpxchg16b_fallback_rendezvous, PRTUINT128U, pu128Dst, PRTUINT128U, pu128RaxRdx,
4809	PRTUINT128U, pu128RbxRcx, uint32_t *, pEFlags);
4810	IEM_CIMPL_PROTO_2(iemCImpl_clflush_clflushopt, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
4811	IEM_CIMPL_PROTO_1(iemCImpl_finit, bool, fCheckXcpts);
4812	IEM_CIMPL_PROTO_3(iemCImpl_fxsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
4813	IEM_CIMPL_PROTO_3(iemCImpl_fxrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
4814	IEM_CIMPL_PROTO_3(iemCImpl_xsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
4815	IEM_CIMPL_PROTO_3(iemCImpl_xrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
4816	IEM_CIMPL_PROTO_2(iemCImpl_stmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
4817	IEM_CIMPL_PROTO_2(iemCImpl_vstmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
4818	IEM_CIMPL_PROTO_2(iemCImpl_ldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
4819	IEM_CIMPL_PROTO_3(iemCImpl_fnstenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4820	IEM_CIMPL_PROTO_3(iemCImpl_fnsave, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4821	IEM_CIMPL_PROTO_3(iemCImpl_fldenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
4822	IEM_CIMPL_PROTO_3(iemCImpl_frstor, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
4823	IEM_CIMPL_PROTO_1(iemCImpl_fldcw, uint16_t, u16Fcw);
4824	IEM_CIMPL_PROTO_2(iemCImpl_fxch_underflow, uint8_t, iStReg, uint16_t, uFpuOpcode);
4825	IEM_CIMPL_PROTO_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, PFNIEMAIMPLFPUR80EFL, pfnAImpl, uint32_t, uPopAndFpuOpcode);
4826	/** @} */
4827
4828	/** @name IEMAllCImplStrInstr.cpp.h
4829	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/' -e 's/RT_CONCAT4(//' \
4830	* -e 's/,ADDR_SIZE)/64/g' -e 's/,OP_SIZE,/64/g' -e 's/,OP_rAX,/rax/g' IEMAllCImplStrInstr.cpp.h
4831	* @{ */
4832	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr16, uint8_t, iEffSeg);
4833	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr16, uint8_t, iEffSeg);
4834	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m16);
4835	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m16);
4836	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr16, uint8_t, iEffSeg);
4837	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m16);
4838	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m16, int8_t, iEffSeg);
4839	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr16, bool, fIoChecked);
4840	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr16, bool, fIoChecked);
4841	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4842	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4843
4844	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr16, uint8_t, iEffSeg);
4845	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr16, uint8_t, iEffSeg);
4846	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m16);
4847	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m16);
4848	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr16, uint8_t, iEffSeg);
4849	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m16);
4850	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m16, int8_t, iEffSeg);
4851	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr16, bool, fIoChecked);
4852	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr16, bool, fIoChecked);
4853	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4854	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4855
4856	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr16, uint8_t, iEffSeg);
4857	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr16, uint8_t, iEffSeg);
4858	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m16);
4859	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m16);
4860	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr16, uint8_t, iEffSeg);
4861	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m16);
4862	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m16, int8_t, iEffSeg);
4863	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr16, bool, fIoChecked);
4864	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr16, bool, fIoChecked);
4865	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4866	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4867
4868
4869	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr32, uint8_t, iEffSeg);
4870	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr32, uint8_t, iEffSeg);
4871	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m32);
4872	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m32);
4873	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr32, uint8_t, iEffSeg);
4874	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m32);
4875	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m32, int8_t, iEffSeg);
4876	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr32, bool, fIoChecked);
4877	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr32, bool, fIoChecked);
4878	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4879	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4880
4881	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr32, uint8_t, iEffSeg);
4882	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr32, uint8_t, iEffSeg);
4883	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m32);
4884	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m32);
4885	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr32, uint8_t, iEffSeg);
4886	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m32);
4887	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m32, int8_t, iEffSeg);
4888	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr32, bool, fIoChecked);
4889	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr32, bool, fIoChecked);
4890	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4891	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4892
4893	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr32, uint8_t, iEffSeg);
4894	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr32, uint8_t, iEffSeg);
4895	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m32);
4896	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m32);
4897	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr32, uint8_t, iEffSeg);
4898	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m32);
4899	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m32, int8_t, iEffSeg);
4900	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr32, bool, fIoChecked);
4901	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr32, bool, fIoChecked);
4902	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4903	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4904
4905	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr32, uint8_t, iEffSeg);
4906	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr32, uint8_t, iEffSeg);
4907	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m32);
4908	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m32);
4909	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr32, uint8_t, iEffSeg);
4910	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m32);
4911	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m32, int8_t, iEffSeg);
4912	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr32, bool, fIoChecked);
4913	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr32, bool, fIoChecked);
4914	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4915	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4916
4917
4918	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr64, uint8_t, iEffSeg);
4919	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr64, uint8_t, iEffSeg);
4920	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m64);
4921	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m64);
4922	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr64, uint8_t, iEffSeg);
4923	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m64);
4924	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m64, int8_t, iEffSeg);
4925	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr64, bool, fIoChecked);
4926	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr64, bool, fIoChecked);
4927	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4928	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4929
4930	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr64, uint8_t, iEffSeg);
4931	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr64, uint8_t, iEffSeg);
4932	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m64);
4933	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m64);
4934	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr64, uint8_t, iEffSeg);
4935	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m64);
4936	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m64, int8_t, iEffSeg);
4937	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr64, bool, fIoChecked);
4938	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr64, bool, fIoChecked);
4939	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4940	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4941
4942	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr64, uint8_t, iEffSeg);
4943	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr64, uint8_t, iEffSeg);
4944	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m64);
4945	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m64);
4946	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr64, uint8_t, iEffSeg);
4947	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m64);
4948	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m64, int8_t, iEffSeg);
4949	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr64, bool, fIoChecked);
4950	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr64, bool, fIoChecked);
4951	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4952	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4953
4954	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr64, uint8_t, iEffSeg);
4955	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr64, uint8_t, iEffSeg);
4956	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m64);
4957	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m64);
4958	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr64, uint8_t, iEffSeg);
4959	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m64);
4960	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m64, int8_t, iEffSeg);
4961	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr64, bool, fIoChecked);
4962	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr64, bool, fIoChecked);
4963	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4964	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4965	/** @} */
4966
4967	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
4968	VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT;
4969	VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT;
4970	VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT;
4971	VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT;
4972	VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT;
4973	VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
4974	VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALK pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT;
4975	VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT;
4976	VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT;
4977	VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
4978	bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT;
4979	VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
4980	bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT;
4981	VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4982	VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4983	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4984	VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4985	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4986	VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4987	VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT;
4988	VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
4989	RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT;
4990	VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT;
4991	VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT;
4992	VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT;
4993	uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT;
4994	void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT;
4995	VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
4996	uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT;
4997	bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT;
4998	IEM_CIMPL_PROTO_0(iemCImpl_vmxoff);
4999	IEM_CIMPL_PROTO_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon);
5000	IEM_CIMPL_PROTO_0(iemCImpl_vmlaunch);
5001	IEM_CIMPL_PROTO_0(iemCImpl_vmresume);
5002	IEM_CIMPL_PROTO_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
5003	IEM_CIMPL_PROTO_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
5004	IEM_CIMPL_PROTO_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
5005	IEM_CIMPL_PROTO_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField);
5006	IEM_CIMPL_PROTO_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField);
5007	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField);
5008	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg32, uint64_t *, pu32Dst, uint32_t, u32VmcsField);
5009	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField);
5010	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField);
5011	IEM_CIMPL_PROTO_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType);
5012	IEM_CIMPL_PROTO_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType);
5013	IEM_CIMPL_PROTO_0(iemCImpl_vmx_pause);
5014	#endif
5015
5016	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5017	VBOXSTRICTRC iemSvmVmexit(PVMCPUCC pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2) RT_NOEXCEPT;
5018	VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr, uint64_t uCr2) RT_NOEXCEPT;
5019	VBOXSTRICTRC iemSvmHandleIOIntercept(PVMCPUCC pVCpu, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
5020	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, uint8_t cbInstr) RT_NOEXCEPT;
5021	VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPUCC pVCpu, uint32_t idMsr, bool fWrite, uint8_t cbInstr) RT_NOEXCEPT;
5022	IEM_CIMPL_PROTO_0(iemCImpl_vmrun);
5023	IEM_CIMPL_PROTO_0(iemCImpl_vmload);
5024	IEM_CIMPL_PROTO_0(iemCImpl_vmsave);
5025	IEM_CIMPL_PROTO_0(iemCImpl_clgi);
5026	IEM_CIMPL_PROTO_0(iemCImpl_stgi);
5027	IEM_CIMPL_PROTO_0(iemCImpl_invlpga);
5028	IEM_CIMPL_PROTO_0(iemCImpl_skinit);
5029	IEM_CIMPL_PROTO_0(iemCImpl_svm_pause);
5030	#endif
5031
5032	IEM_CIMPL_PROTO_0(iemCImpl_vmcall); /* vmx */
5033	IEM_CIMPL_PROTO_0(iemCImpl_vmmcall); /* svm */
5034	IEM_CIMPL_PROTO_1(iemCImpl_Hypercall, uint16_t, uDisOpcode); /* both */
5035
5036	extern const PFNIEMOP g_apfnIemInterpretOnlyOneByteMap[256];
5037	extern const PFNIEMOP g_apfnIemInterpretOnlyTwoByteMap[1024];
5038	extern const PFNIEMOP g_apfnIemInterpretOnlyThreeByte0f3a[1024];
5039	extern const PFNIEMOP g_apfnIemInterpretOnlyThreeByte0f38[1024];
5040	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap1[1024];
5041	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap2[1024];
5042	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap3[1024];
5043
5044	/*
5045	* Recompiler related stuff.
5046	*/
5047	extern const PFNIEMOP g_apfnIemThreadedRecompilerOneByteMap[256];
5048	extern const PFNIEMOP g_apfnIemThreadedRecompilerTwoByteMap[1024];
5049	extern const PFNIEMOP g_apfnIemThreadedRecompilerThreeByte0f3a[1024];
5050	extern const PFNIEMOP g_apfnIemThreadedRecompilerThreeByte0f38[1024];
5051	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap1[1024];
5052	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap2[1024];
5053	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap3[1024];
5054
5055	void iemThreadedTbObsolete(PVMCPUCC pVCpu, PIEMTB pTb);
5056
5057	/** @todo FNIEMTHREADEDFUNC and friends may need more work... */
5058	#if defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
5059	typedef VBOXSTRICTRC /__attribute__((__nothrow__))/ FNIEMTHREADEDFUNC(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
5060	typedef FNIEMTHREADEDFUNC *PFNIEMTHREADEDFUNC;
5061	# define IEM_DECL_IEMTHREADEDFUNC_DEF(a_Name) \
5062	VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2)
5063	# define IEM_DECL_IEMTHREADEDFUNC_PROTO(a_Name) \
5064	VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2)
5065
5066	#else
5067	typedef VBOXSTRICTRC (FNIEMTHREADEDFUNC)(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
5068	typedef FNIEMTHREADEDFUNC *PFNIEMTHREADEDFUNC;
5069	# define IEM_DECL_IEMTHREADEDFUNC_DEF(a_Name) \
5070	VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2) IEM_NOEXCEPT_MAY_LONGJMP
5071	# define IEM_DECL_IEMTHREADEDFUNC_PROTO(a_Name) \
5072	VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2) IEM_NOEXCEPT_MAY_LONGJMP
5073	#endif
5074
5075
5076	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_DeferToCImpl0);
5077
5078	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckIrq);
5079	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckMode);
5080	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckHwInstrBps);
5081	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLim);
5082
5083	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodes);
5084	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodes);
5085	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesConsiderCsLim);
5086
5087	/* Branching: */
5088	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndPcAndOpcodes);
5089	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckPcAndOpcodes);
5090	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckPcAndOpcodesConsiderCsLim);
5091
5092	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesLoadingTlb);
5093	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesLoadingTlb);
5094	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesLoadingTlbConsiderCsLim);
5095
5096	/* Natural page crossing: */
5097	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesAcrossPageLoadingTlb);
5098	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesAcrossPageLoadingTlb);
5099	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesAcrossPageLoadingTlbConsiderCsLim);
5100
5101	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesOnNextPageLoadingTlb);
5102	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNextPageLoadingTlb);
5103	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNextPageLoadingTlbConsiderCsLim);
5104
5105	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesOnNewPageLoadingTlb);
5106	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNewPageLoadingTlb);
5107	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNewPageLoadingTlbConsiderCsLim);
5108
5109	bool iemThreadedCompileEmitIrqCheckBefore(PVMCPUCC pVCpu, PIEMTB pTb);
5110	bool iemThreadedCompileBeginEmitCallsComplications(PVMCPUCC pVCpu, PIEMTB pTb);
5111
5112
5113	/** @} */
5114
5115	RT_C_DECLS_END
5116
5117	#endif /* !VMM_INCLUDED_SRC_include_IEMInternal_h */
5118

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source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h@ 100851

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