IEMInternal.h@ 101330

Last change on this file since 101330 was 101304, checked in by vboxsync, 18 months ago
VMM/IEM: Emit native code for pure defer-CImpl instructions. Tested on linux.amd64 only and this doesn't cover cases with zero parameters. bugref:10371
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 274.9 KB

Line
1	/* $Id: IEMInternal.h 101304 2023-09-29 01:02:02Z vboxsync $ */
2	/** @file
3	* IEM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2011-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_IEMInternal_h
29	#define VMM_INCLUDED_SRC_include_IEMInternal_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#include <VBox/vmm/cpum.h>
35	#include <VBox/vmm/iem.h>
36	#include <VBox/vmm/pgm.h>
37	#include <VBox/vmm/stam.h>
38	#include <VBox/param.h>
39
40	#include <iprt/setjmp-without-sigmask.h>
41	#include <iprt/list.h>
42
43
44	RT_C_DECLS_BEGIN
45
46
47	/** @defgroup grp_iem_int Internals
48	* @ingroup grp_iem
49	* @internal
50	* @{
51	*/
52
53	/** For expanding symbol in slickedit and other products tagging and
54	* crossreferencing IEM symbols. */
55	#ifndef IEM_STATIC
56	# define IEM_STATIC static
57	#endif
58
59	/** @def IEM_WITH_SETJMP
60	* Enables alternative status code handling using setjmps.
61	*
62	* This adds a bit of expense via the setjmp() call since it saves all the
63	* non-volatile registers. However, it eliminates return code checks and allows
64	* for more optimal return value passing (return regs instead of stack buffer).
65	*/
66	#if defined(DOXYGEN_RUNNING) \|\| defined(RT_OS_WINDOWS) \|\| 1
67	# define IEM_WITH_SETJMP
68	#endif
69
70	/** @def IEM_WITH_THROW_CATCH
71	* Enables using C++ throw/catch as an alternative to setjmp/longjmp in user
72	* mode code when IEM_WITH_SETJMP is in effect.
73	*
74	* With GCC 11.3.1 and code TLB on linux, using throw/catch instead of
75	* setjmp/long resulted in bs2-test-1 running 3.00% faster and all but on test
76	* result value improving by more than 1%. (Best out of three.)
77	*
78	* With Visual C++ 2019 and code TLB on windows, using throw/catch instead of
79	* setjmp/long resulted in bs2-test-1 running 3.68% faster and all but some of
80	* the MMIO and CPUID tests ran noticeably faster. Variation is greater than on
81	* Linux, but it should be quite a bit faster for normal code.
82	*/
83	#if (defined(__cplusplus) && defined(IEM_WITH_SETJMP) && defined(IN_RING3) && (defined(__GNUC__) \|\| defined(_MSC_VER))) \
84	\|\| defined(DOXYGEN_RUNNING)
85	# define IEM_WITH_THROW_CATCH
86	#endif
87
88	/** @def IEM_DO_LONGJMP
89	*
90	* Wrapper around longjmp / throw.
91	*
92	* @param a_pVCpu The CPU handle.
93	* @param a_rc The status code jump back with / throw.
94	*/
95	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
96	# ifdef IEM_WITH_THROW_CATCH
97	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) throw int(a_rc)
98	# else
99	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) longjmp(*(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf), (a_rc))
100	# endif
101	#endif
102
103	/** For use with IEM function that may do a longjmp (when enabled).
104	*
105	* Visual C++ has trouble longjmp'ing from/over functions with the noexcept
106	* attribute. So, we indicate that function that may be part of a longjmp may
107	* throw "exceptions" and that the compiler should definitely not generate and
108	* std::terminate calling unwind code.
109	*
110	* Here is one example of this ending in std::terminate:
111	* @code{.txt}
112	00 00000041`cadfda10 00007ffc`5d5a1f9f ucrtbase!abort+0x4e
113	01 00000041`cadfda40 00007ffc`57af229a ucrtbase!terminate+0x1f
114	02 00000041`cadfda70 00007ffb`eec91030 VCRUNTIME140!__std_terminate+0xa [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\ehhelpers.cpp @ 192]
115	03 00000041`cadfdaa0 00007ffb`eec92c6d VCRUNTIME140_1!_CallSettingFrame+0x20 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\handlers.asm @ 50]
116	04 00000041`cadfdad0 00007ffb`eec93ae5 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToState+0x241 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 1085]
117	05 00000041`cadfdc00 00007ffb`eec92258 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToEmptyState+0x2d [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 218]
118	06 00000041`cadfdc30 00007ffb`eec940e9 VCRUNTIME140_1!__InternalCxxFrameHandler<__FrameHandler4>+0x194 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 304]
119	07 00000041`cadfdcd0 00007ffc`5f9f249f VCRUNTIME140_1!__CxxFrameHandler4+0xa9 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 290]
120	08 00000041`cadfdd40 00007ffc`5f980939 ntdll!RtlpExecuteHandlerForUnwind+0xf
121	09 00000041`cadfdd70 00007ffc`5f9a0edd ntdll!RtlUnwindEx+0x339
122	0a 00000041`cadfe490 00007ffc`57aff976 ntdll!RtlUnwind+0xcd
123	0b 00000041`cadfea00 00007ffb`e1b5de01 VCRUNTIME140!__longjmp_internal+0xe6 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\longjmp.asm @ 140]
124	0c (Inline Function) --------`-------- VBoxVMM!iemOpcodeGetNextU8SlowJmp+0x95 [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 1155]
125	0d 00000041`cadfea50 00007ffb`e1b60f6b VBoxVMM!iemOpcodeGetNextU8Jmp+0xc1 [L:\vbox-intern\src\VBox\VMM\include\IEMInline.h @ 402]
126	0e 00000041`cadfea90 00007ffb`e1cc6201 VBoxVMM!IEMExecForExits+0xdb [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 10185]
127	0f 00000041`cadfec70 00007ffb`e1d0df8d VBoxVMM!EMHistoryExec+0x4f1 [L:\vbox-intern\src\VBox\VMM\VMMAll\EMAll.cpp @ 452]
128	10 00000041`cadfed60 00007ffb`e1d0d4c0 VBoxVMM!nemR3WinHandleExitCpuId+0x79d [L:\vbox-intern\src\VBox\VMM\VMMAll\NEMAllNativeTemplate-win.cpp.h @ 1829] @encode
129	@endcode
130	*
131	* @see https://developercommunity.visualstudio.com/t/fragile-behavior-of-longjmp-called-from-noexcept-f/1532859
132	*/
133	#if defined(IEM_WITH_SETJMP) && (defined(_MSC_VER) \|\| defined(IEM_WITH_THROW_CATCH))
134	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT_EX(false)
135	#else
136	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT
137	#endif
138
139	#define IEM_IMPLEMENTS_TASKSWITCH
140
141	/** @def IEM_WITH_3DNOW
142	* Includes the 3DNow decoding. */
143	#if (!defined(IEM_WITH_3DNOW) && !defined(IEM_WITHOUT_3DNOW)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
144	# define IEM_WITH_3DNOW
145	#endif
146
147	/** @def IEM_WITH_THREE_0F_38
148	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
149	#if (!defined(IEM_WITH_THREE_0F_38) && !defined(IEM_WITHOUT_THREE_0F_38)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
150	# define IEM_WITH_THREE_0F_38
151	#endif
152
153	/** @def IEM_WITH_THREE_0F_3A
154	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
155	#if (!defined(IEM_WITH_THREE_0F_3A) && !defined(IEM_WITHOUT_THREE_0F_3A)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
156	# define IEM_WITH_THREE_0F_3A
157	#endif
158
159	/** @def IEM_WITH_VEX
160	* Includes the VEX decoding. */
161	#if (!defined(IEM_WITH_VEX) && !defined(IEM_WITHOUT_VEX)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
162	# define IEM_WITH_VEX
163	#endif
164
165	/** @def IEM_CFG_TARGET_CPU
166	* The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
167	*
168	* By default we allow this to be configured by the user via the
169	* CPUM/GuestCpuName config string, but this comes at a slight cost during
170	* decoding. So, for applications of this code where there is no need to
171	* be dynamic wrt target CPU, just modify this define.
172	*/
173	#if !defined(IEM_CFG_TARGET_CPU) \|\| defined(DOXYGEN_RUNNING)
174	# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
175	#endif
176
177	//#define IEM_WITH_CODE_TLB // - work in progress
178	//#define IEM_WITH_DATA_TLB // - work in progress
179
180
181	/** @def IEM_USE_UNALIGNED_DATA_ACCESS
182	* Use unaligned accesses instead of elaborate byte assembly. */
183	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86) \|\| defined(DOXYGEN_RUNNING)
184	# define IEM_USE_UNALIGNED_DATA_ACCESS
185	#endif
186
187	//#define IEM_LOG_MEMORY_WRITES
188
189	#if !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
190	/** Instruction statistics. */
191	typedef struct IEMINSTRSTATS
192	{
193	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
194	# include "IEMInstructionStatisticsTmpl.h"
195	# undef IEM_DO_INSTR_STAT
196	} IEMINSTRSTATS;
197	#else
198	struct IEMINSTRSTATS;
199	typedef struct IEMINSTRSTATS IEMINSTRSTATS;
200	#endif
201	/** Pointer to IEM instruction statistics. */
202	typedef IEMINSTRSTATS *PIEMINSTRSTATS;
203
204
205	/** @name IEMTARGETCPU_EFL_BEHAVIOR_XXX - IEMCPU::aidxTargetCpuEflFlavour
206	* @{ */
207	#define IEMTARGETCPU_EFL_BEHAVIOR_NATIVE 0 /*< Native x86 EFLAGS result; Intel EFLAGS when on non-x86 hosts. /
208	#define IEMTARGETCPU_EFL_BEHAVIOR_INTEL 1 /*< Intel EFLAGS result. /
209	#define IEMTARGETCPU_EFL_BEHAVIOR_AMD 2 /*< AMD EFLAGS result /
210	#define IEMTARGETCPU_EFL_BEHAVIOR_RESERVED 3 /*< Reserved/dummy entry slot that's the same as 0. /
211	#define IEMTARGETCPU_EFL_BEHAVIOR_MASK 3 /*< For masking the index before use. /
212	/** Selects the right variant from a_aArray.
213	* pVCpu is implicit in the caller context. */
214	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT(a_aArray) \
215	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[1] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
216	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for when no native worker can
217	* be used because the host CPU does not support the operation. */
218	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_NON_NATIVE(a_aArray) \
219	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
220	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for a two dimentional
221	* array paralleling IEMCPU::aidxTargetCpuEflFlavour and a single bit index
222	* into the two.
223	* @sa IEM_SELECT_NATIVE_OR_FALLBACK */
224	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
225	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
226	(a_aaArray[a_fNative][pVCpu->iem.s.aidxTargetCpuEflFlavour[a_fNative] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
227	#else
228	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
229	(a_aaArray[0][pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
230	#endif
231	/** @} */
232
233	/**
234	* Picks @a a_pfnNative or @a a_pfnFallback according to the host CPU feature
235	* indicator given by @a a_fCpumFeatureMember (CPUMFEATURES member).
236	*
237	* On non-x86 hosts, this will shortcut to the fallback w/o checking the
238	* indicator.
239	*
240	* @sa IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX
241	*/
242	#if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
243	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) \
244	(g_CpumHostFeatures.s.a_fCpumFeatureMember ? a_pfnNative : a_pfnFallback)
245	#else
246	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) (a_pfnFallback)
247	#endif
248
249
250	/**
251	* Extended operand mode that includes a representation of 8-bit.
252	*
253	* This is used for packing down modes when invoking some C instruction
254	* implementations.
255	*/
256	typedef enum IEMMODEX
257	{
258	IEMMODEX_16BIT = IEMMODE_16BIT,
259	IEMMODEX_32BIT = IEMMODE_32BIT,
260	IEMMODEX_64BIT = IEMMODE_64BIT,
261	IEMMODEX_8BIT
262	} IEMMODEX;
263	AssertCompileSize(IEMMODEX, 4);
264
265
266	/**
267	* Branch types.
268	*/
269	typedef enum IEMBRANCH
270	{
271	IEMBRANCH_JUMP = 1,
272	IEMBRANCH_CALL,
273	IEMBRANCH_TRAP,
274	IEMBRANCH_SOFTWARE_INT,
275	IEMBRANCH_HARDWARE_INT
276	} IEMBRANCH;
277	AssertCompileSize(IEMBRANCH, 4);
278
279
280	/**
281	* INT instruction types.
282	*/
283	typedef enum IEMINT
284	{
285	/** INT n instruction (opcode 0xcd imm). */
286	IEMINT_INTN = 0,
287	/** Single byte INT3 instruction (opcode 0xcc). */
288	IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
289	/** Single byte INTO instruction (opcode 0xce). */
290	IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
291	/** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
292	IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
293	} IEMINT;
294	AssertCompileSize(IEMINT, 4);
295
296
297	/**
298	* A FPU result.
299	*/
300	typedef struct IEMFPURESULT
301	{
302	/** The output value. */
303	RTFLOAT80U r80Result;
304	/** The output status. */
305	uint16_t FSW;
306	} IEMFPURESULT;
307	AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
308	/** Pointer to a FPU result. */
309	typedef IEMFPURESULT *PIEMFPURESULT;
310	/** Pointer to a const FPU result. */
311	typedef IEMFPURESULT const *PCIEMFPURESULT;
312
313
314	/**
315	* A FPU result consisting of two output values and FSW.
316	*/
317	typedef struct IEMFPURESULTTWO
318	{
319	/** The first output value. */
320	RTFLOAT80U r80Result1;
321	/** The output status. */
322	uint16_t FSW;
323	/** The second output value. */
324	RTFLOAT80U r80Result2;
325	} IEMFPURESULTTWO;
326	AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
327	AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
328	/** Pointer to a FPU result consisting of two output values and FSW. */
329	typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
330	/** Pointer to a const FPU result consisting of two output values and FSW. */
331	typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
332
333
334	/**
335	* IEM TLB entry.
336	*
337	* Lookup assembly:
338	* @code{.asm}
339	; Calculate tag.
340	mov rax, [VA]
341	shl rax, 16
342	shr rax, 16 + X86_PAGE_SHIFT
343	or rax, [uTlbRevision]
344
345	; Do indexing.
346	movzx ecx, al
347	lea rcx, [pTlbEntries + rcx]
348
349	; Check tag.
350	cmp [rcx + IEMTLBENTRY.uTag], rax
351	jne .TlbMiss
352
353	; Check access.
354	mov rax, ACCESS_FLAGS \| MAPPING_R3_NOT_VALID \| 0xffffff00
355	and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
356	cmp rax, [uTlbPhysRev]
357	jne .TlbMiss
358
359	; Calc address and we're done.
360	mov eax, X86_PAGE_OFFSET_MASK
361	and eax, [VA]
362	or rax, [rcx + IEMTLBENTRY.pMappingR3]
363	%ifdef VBOX_WITH_STATISTICS
364	inc qword [cTlbHits]
365	%endif
366	jmp .Done
367
368	.TlbMiss:
369	mov r8d, ACCESS_FLAGS
370	mov rdx, [VA]
371	mov rcx, [pVCpu]
372	call iemTlbTypeMiss
373	.Done:
374
375	@endcode
376	*
377	*/
378	typedef struct IEMTLBENTRY
379	{
380	/** The TLB entry tag.
381	* Bits 35 thru 0 are made up of the virtual address shifted right 12 bits, this
382	* is ASSUMING a virtual address width of 48 bits.
383	*
384	* Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
385	*
386	* The TLB lookup code uses the current TLB revision, which won't ever be zero,
387	* enabling an extremely cheap TLB invalidation most of the time. When the TLB
388	* revision wraps around though, the tags needs to be zeroed.
389	*
390	* @note Try use SHRD instruction? After seeing
391	* https://gmplib.org/~tege/x86-timing.pdf, maybe not.
392	*
393	* @todo This will need to be reorganized for 57-bit wide virtual address and
394	* PCID (currently 12 bits) and ASID (currently 6 bits) support. We'll
395	* have to move the TLB entry versioning entirely to the
396	* fFlagsAndPhysRev member then, 57 bit wide VAs means we'll only have
397	* 19 bits left (64 - 57 + 12 = 19) and they'll almost entire be
398	* consumed by PCID and ASID (12 + 6 = 18).
399	*/
400	uint64_t uTag;
401	/** Access flags and physical TLB revision.
402	*
403	* - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
404	* - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
405	* - Bit 2 - page tables - not user (complemented X86_PTE_US).
406	* - Bit 3 - pgm phys/virt - not directly writable.
407	* - Bit 4 - pgm phys page - not directly readable.
408	* - Bit 5 - page tables - not accessed (complemented X86_PTE_A).
409	* - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
410	* - Bit 7 - tlb entry - pMappingR3 member not valid.
411	* - Bits 63 thru 8 are used for the physical TLB revision number.
412	*
413	* We're using complemented bit meanings here because it makes it easy to check
414	* whether special action is required. For instance a user mode write access
415	* would do a "TEST fFlags, (X86_PTE_RW \| X86_PTE_US \| X86_PTE_D)" and a
416	* non-zero result would mean special handling needed because either it wasn't
417	* writable, or it wasn't user, or the page wasn't dirty. A user mode read
418	* access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
419	* need to check any PTE flag.
420	*/
421	uint64_t fFlagsAndPhysRev;
422	/** The guest physical page address. */
423	uint64_t GCPhys;
424	/** Pointer to the ring-3 mapping. */
425	R3PTRTYPE(uint8_t *) pbMappingR3;
426	#if HC_ARCH_BITS == 32
427	uint32_t u32Padding1;
428	#endif
429	} IEMTLBENTRY;
430	AssertCompileSize(IEMTLBENTRY, 32);
431	/** Pointer to an IEM TLB entry. */
432	typedef IEMTLBENTRY *PIEMTLBENTRY;
433
434	/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
435	* @{ */
436	#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /*< Page tables: Not executable. /
437	#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /*< Page tables: Not writable. /
438	#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /*< Page tables: Not user accessible (supervisor only). /
439	#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /*< Phys page: Not writable (access handler, ROM, whatever). /
440	#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /*< Phys page: Not readable (MMIO / access handler, ROM) /
441	#define IEMTLBE_F_PT_NO_ACCESSED RT_BIT_64(5) /*< Phys tables: Not accessed (need to be marked accessed). /
442	#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /*< Page tables: Not dirty (needs to be made dirty on write). /
443	#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(7) /*< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. /
444	#define IEMTLBE_F_PG_UNASSIGNED RT_BIT_64(8) /*< Phys page: Unassigned memory (not RAM, ROM, MMIO2 or MMIO). /
445	#define IEMTLBE_F_PG_CODE_PAGE RT_BIT_64(9) /*< Phys page: Code page. /
446	#define IEMTLBE_F_PHYS_REV UINT64_C(0xfffffffffffffc00) /*< Physical revision mask. @sa IEMTLB_PHYS_REV_INCR /
447	/** @} */
448
449
450	/**
451	* An IEM TLB.
452	*
453	* We've got two of these, one for data and one for instructions.
454	*/
455	typedef struct IEMTLB
456	{
457	/** The TLB entries.
458	* We've choosen 256 because that way we can obtain the result directly from a
459	* 8-bit register without an additional AND instruction. */
460	IEMTLBENTRY aEntries[256];
461	/** The TLB revision.
462	* This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
463	* by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
464	* the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
465	* (The revision zero indicates an invalid TLB entry.)
466	*
467	* The initial value is choosen to cause an early wraparound. */
468	uint64_t uTlbRevision;
469	/** The TLB physical address revision - shadow of PGM variable.
470	*
471	* This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
472	* incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
473	* a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
474	* as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
475	*
476	* The initial value is choosen to cause an early wraparound. */
477	uint64_t volatile uTlbPhysRev;
478
479	/* Statistics: */
480
481	/** TLB hits (VBOX_WITH_STATISTICS only). */
482	uint64_t cTlbHits;
483	/** TLB misses. */
484	uint32_t cTlbMisses;
485	/** Slow read path. */
486	uint32_t cTlbSlowReadPath;
487	/** Safe read path. */
488	uint32_t cTlbSafeReadPath;
489	/** Safe write path. */
490	uint32_t cTlbSafeWritePath;
491	#if 0
492	/** TLB misses because of tag mismatch. */
493	uint32_t cTlbMissesTag;
494	/** TLB misses because of virtual access violation. */
495	uint32_t cTlbMissesVirtAccess;
496	/** TLB misses because of dirty bit. */
497	uint32_t cTlbMissesDirty;
498	/** TLB misses because of MMIO */
499	uint32_t cTlbMissesMmio;
500	/** TLB misses because of write access handlers. */
501	uint32_t cTlbMissesWriteHandler;
502	/** TLB misses because no r3(/r0) mapping. */
503	uint32_t cTlbMissesMapping;
504	#endif
505	/** Alignment padding. */
506	uint32_t au32Padding[6];
507	} IEMTLB;
508	AssertCompileSizeAlignment(IEMTLB, 64);
509	/** IEMTLB::uTlbRevision increment. */
510	#define IEMTLB_REVISION_INCR RT_BIT_64(36)
511	/** IEMTLB::uTlbRevision mask. */
512	#define IEMTLB_REVISION_MASK (~(RT_BIT_64(36) - 1))
513	/** IEMTLB::uTlbPhysRev increment.
514	* @sa IEMTLBE_F_PHYS_REV */
515	#define IEMTLB_PHYS_REV_INCR RT_BIT_64(10)
516	/**
517	* Calculates the TLB tag for a virtual address.
518	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
519	* @param a_pTlb The TLB.
520	* @param a_GCPtr The virtual address. Must be RTGCPTR or same size or
521	* the clearing of the top 16 bits won't work (if 32-bit
522	* we'll end up with mostly zeros).
523	*/
524	#define IEMTLB_CALC_TAG(a_pTlb, a_GCPtr) ( IEMTLB_CALC_TAG_NO_REV(a_GCPtr) \| (a_pTlb)->uTlbRevision )
525	/**
526	* Calculates the TLB tag for a virtual address but without TLB revision.
527	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
528	* @param a_GCPtr The virtual address. Must be RTGCPTR or same size or
529	* the clearing of the top 16 bits won't work (if 32-bit
530	* we'll end up with mostly zeros).
531	*/
532	#define IEMTLB_CALC_TAG_NO_REV(a_GCPtr) ( (((a_GCPtr) << 16) >> (GUEST_PAGE_SHIFT + 16)) )
533	/**
534	* Converts a TLB tag value into a TLB index.
535	* @returns Index into IEMTLB::aEntries.
536	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
537	*/
538	#define IEMTLB_TAG_TO_INDEX(a_uTag) ( (uint8_t)(a_uTag) )
539	/**
540	* Converts a TLB tag value into a TLB index.
541	* @returns Index into IEMTLB::aEntries.
542	* @param a_pTlb The TLB.
543	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
544	*/
545	#define IEMTLB_TAG_TO_ENTRY(a_pTlb, a_uTag) ( &(a_pTlb)->aEntries[IEMTLB_TAG_TO_INDEX(a_uTag)] )
546
547
548	/** @name IEM_MC_F_XXX - MC block flags/clues.
549	* @{ */
550	#define IEM_MC_F_ONLY_8086 RT_BIT_32(0)
551	#define IEM_MC_F_MIN_186 RT_BIT_32(1)
552	#define IEM_MC_F_MIN_286 RT_BIT_32(2)
553	#define IEM_MC_F_NOT_286_OR_OLDER IEM_MC_F_MIN_386
554	#define IEM_MC_F_MIN_386 RT_BIT_32(3)
555	#define IEM_MC_F_MIN_486 RT_BIT_32(4)
556	#define IEM_MC_F_MIN_PENTIUM RT_BIT_32(5)
557	#define IEM_MC_F_MIN_PENTIUM_II IEM_MC_F_MIN_PENTIUM
558	#define IEM_MC_F_MIN_CORE IEM_MC_F_MIN_PENTIUM
559	#define IEM_MC_F_64BIT RT_BIT_32(6)
560	#define IEM_MC_F_NOT_64BIT RT_BIT_32(7)
561	/** @} */
562
563
564	/** @name IEM_F_XXX - Execution mode flags (IEMCPU::fExec, IEMTB::fFlags).
565	*
566	* These flags are set when entering IEM and adjusted as code is executed, such
567	* that they will always contain the current values as instructions are
568	* finished.
569	*
570	* In recompiled execution mode, (most of) these flags are included in the
571	* translation block selection key and stored in IEMTB::fFlags alongside the
572	* IEMTB_F_XXX flags. The latter flags uses bits 31 thru 24, which are all zero
573	* in IEMCPU::fExec.
574	*
575	* @{ */
576	/** Mode: The block target mode mask. */
577	#define IEM_F_MODE_MASK UINT32_C(0x0000001f)
578	/** Mode: The IEMMODE part of the IEMTB_F_MODE_MASK value. */
579	#define IEM_F_MODE_CPUMODE_MASK UINT32_C(0x00000003)
580	/** X86 Mode: Bit used to indicating pre-386 CPU in 16-bit mode (for eliminating
581	* conditional in EIP/IP updating), and flat wide open CS, SS DS, and ES in
582	* 32-bit mode (for simplifying most memory accesses). */
583	#define IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK UINT32_C(0x00000004)
584	/** X86 Mode: Bit indicating protected mode, real mode (or SMM) when not set. */
585	#define IEM_F_MODE_X86_PROT_MASK UINT32_C(0x00000008)
586	/** X86 Mode: Bit used to indicate virtual 8086 mode (only 16-bit). */
587	#define IEM_F_MODE_X86_V86_MASK UINT32_C(0x00000010)
588
589	/** X86 Mode: 16-bit on 386 or later. */
590	#define IEM_F_MODE_X86_16BIT UINT32_C(0x00000000)
591	/** X86 Mode: 80286, 80186 and 8086/88 targetting blocks (EIP update opt). */
592	#define IEM_F_MODE_X86_16BIT_PRE_386 UINT32_C(0x00000004)
593	/** X86 Mode: 16-bit protected mode on 386 or later. */
594	#define IEM_F_MODE_X86_16BIT_PROT UINT32_C(0x00000008)
595	/** X86 Mode: 16-bit protected mode on 386 or later. */
596	#define IEM_F_MODE_X86_16BIT_PROT_PRE_386 UINT32_C(0x0000000c)
597	/** X86 Mode: 16-bit virtual 8086 protected mode (on 386 or later). */
598	#define IEM_F_MODE_X86_16BIT_PROT_V86 UINT32_C(0x00000018)
599
600	/** X86 Mode: 32-bit on 386 or later. */
601	#define IEM_F_MODE_X86_32BIT UINT32_C(0x00000001)
602	/** X86 Mode: 32-bit mode with wide open flat CS, SS, DS and ES. */
603	#define IEM_F_MODE_X86_32BIT_FLAT UINT32_C(0x00000005)
604	/** X86 Mode: 32-bit protected mode. */
605	#define IEM_F_MODE_X86_32BIT_PROT UINT32_C(0x00000009)
606	/** X86 Mode: 32-bit protected mode with wide open flat CS, SS, DS and ES. */
607	#define IEM_F_MODE_X86_32BIT_PROT_FLAT UINT32_C(0x0000000d)
608
609	/** X86 Mode: 64-bit (includes protected, but not the flat bit). */
610	#define IEM_F_MODE_X86_64BIT UINT32_C(0x0000000a)
611
612
613	/** Bypass access handlers when set. */
614	#define IEM_F_BYPASS_HANDLERS UINT32_C(0x00010000)
615	/** Have pending hardware instruction breakpoints. */
616	#define IEM_F_PENDING_BRK_INSTR UINT32_C(0x00020000)
617	/** Have pending hardware data breakpoints. */
618	#define IEM_F_PENDING_BRK_DATA UINT32_C(0x00040000)
619
620	/** X86: Have pending hardware I/O breakpoints. */
621	#define IEM_F_PENDING_BRK_X86_IO UINT32_C(0x00000400)
622	/** X86: Disregard the lock prefix (implied or not) when set. */
623	#define IEM_F_X86_DISREGARD_LOCK UINT32_C(0x00000800)
624
625	/** Pending breakpoint mask (what iemCalcExecDbgFlags works out). */
626	#define IEM_F_PENDING_BRK_MASK (IEM_F_PENDING_BRK_INSTR \| IEM_F_PENDING_BRK_DATA \| IEM_F_PENDING_BRK_X86_IO)
627
628	/** Caller configurable options. */
629	#define IEM_F_USER_OPTS (IEM_F_BYPASS_HANDLERS \| IEM_F_X86_DISREGARD_LOCK)
630
631	/** X86: The current protection level (CPL) shift factor. */
632	#define IEM_F_X86_CPL_SHIFT 8
633	/** X86: The current protection level (CPL) mask. */
634	#define IEM_F_X86_CPL_MASK UINT32_C(0x00000300)
635	/** X86: The current protection level (CPL) shifted mask. */
636	#define IEM_F_X86_CPL_SMASK UINT32_C(0x00000003)
637
638	/** X86 execution context.
639	* The IEM_F_X86_CTX_XXX values are individual flags that can be combined (with
640	* the exception of IEM_F_X86_CTX_NORMAL). This allows running VMs from SMM
641	* mode. */
642	#define IEM_F_X86_CTX_MASK UINT32_C(0x0000f000)
643	/** X86 context: Plain regular execution context. */
644	#define IEM_F_X86_CTX_NORMAL UINT32_C(0x00000000)
645	/** X86 context: VT-x enabled. */
646	#define IEM_F_X86_CTX_VMX UINT32_C(0x00001000)
647	/** X86 context: AMD-V enabled. */
648	#define IEM_F_X86_CTX_SVM UINT32_C(0x00002000)
649	/** X86 context: In AMD-V or VT-x guest mode. */
650	#define IEM_F_X86_CTX_IN_GUEST UINT32_C(0x00004000)
651	/** X86 context: System management mode (SMM). */
652	#define IEM_F_X86_CTX_SMM UINT32_C(0x00008000)
653
654	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
655	* iemRegFinishClearingRF() most for most situations (CPUMCTX_DBG_HIT_DRX_MASK
656	* and CPUMCTX_DBG_DBGF_MASK are covered by the IEM_F_PENDING_BRK_XXX bits
657	* alread). */
658
659	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
660	* iemRegFinishClearingRF() most for most situations
661	* (CPUMCTX_DBG_HIT_DRX_MASK and CPUMCTX_DBG_DBGF_MASK are covered by
662	* the IEM_F_PENDING_BRK_XXX bits alread). */
663
664	/** @} */
665
666
667	/** @name IEMTB_F_XXX - Translation block flags (IEMTB::fFlags).
668	*
669	* Extends the IEM_F_XXX flags (subject to IEMTB_F_IEM_F_MASK) to make up the
670	* translation block flags. The combined flag mask (subject to
671	* IEMTB_F_KEY_MASK) is used as part of the lookup key for translation blocks.
672	*
673	* @{ */
674	/** Mask of IEM_F_XXX flags included in IEMTB_F_XXX. */
675	#define IEMTB_F_IEM_F_MASK UINT32_C(0x00ffffff)
676
677	/** Type: The block type mask. */
678	#define IEMTB_F_TYPE_MASK UINT32_C(0x03000000)
679	/** Type: Purly threaded recompiler (via tables). */
680	#define IEMTB_F_TYPE_THREADED UINT32_C(0x01000000)
681	/** Type: Native recompilation. */
682	#define IEMTB_F_TYPE_NATIVE UINT32_C(0x02000000)
683
684	/** Set when we're starting the block in an "interrupt shadow".
685	* We don't need to distingish between the two types of this mask, thus the one.
686	* @see CPUMCTX_INHIBIT_SHADOW, CPUMIsInInterruptShadow() */
687	#define IEMTB_F_INHIBIT_SHADOW UINT32_C(0x04000000)
688	/** Set when we're currently inhibiting NMIs
689	* @see CPUMCTX_INHIBIT_NMI, CPUMAreInterruptsInhibitedByNmi() */
690	#define IEMTB_F_INHIBIT_NMI UINT32_C(0x08000000)
691
692	/** Checks that EIP/IP is wihin CS.LIM before each instruction. Used when
693	* we're close the limit before starting a TB, as determined by
694	* iemGetTbFlagsForCurrentPc(). */
695	#define IEMTB_F_CS_LIM_CHECKS UINT32_C(0x10000000)
696
697	/** Mask of the IEMTB_F_XXX flags that are part of the TB lookup key.
698	* @note We skip the CPL as we don't currently generate ring-specific code,
699	* that's all handled in CIMPL functions.
700	*
701	* For the same reasons, we skip all of IEM_F_X86_CTX_MASK, with the
702	* exception of SMM (which we don't implement). */
703	#define IEMTB_F_KEY_MASK ( (UINT32_MAX & ~(IEM_F_X86_CTX_MASK \| IEM_F_X86_CPL_MASK \| IEMTB_F_TYPE_MASK)) \
704	\| IEM_F_X86_CTX_SMM)
705	/** @} */
706
707	AssertCompile( (IEM_F_MODE_X86_16BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
708	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
709	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_PROT_MASK));
710	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_V86_MASK));
711	AssertCompile( (IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
712	AssertCompile( IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
713	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_PROT_MASK));
714	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
715	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
716	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
717	AssertCompile( IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
718	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_V86_MASK));
719	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
720	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
721	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_PROT_MASK);
722	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
723	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_PROT_MASK);
724	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
725	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_V86_MASK);
726
727	AssertCompile( (IEM_F_MODE_X86_32BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
728	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
729	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_PROT_MASK));
730	AssertCompile( (IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
731	AssertCompile( IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
732	AssertCompile(!(IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_PROT_MASK));
733	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
734	AssertCompile(!(IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
735	AssertCompile( IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
736	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
737	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
738	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_PROT_MASK);
739
740	AssertCompile( (IEM_F_MODE_X86_64BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_64BIT);
741	AssertCompile( IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_PROT_MASK);
742	AssertCompile(!(IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
743
744	/** Native instruction type for use with the native code generator.
745	* This is a byte (uint8_t) for x86 and amd64 and uint32_t for the other(s). */
746	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
747	typedef uint8_t IEMNATIVEINSTR;
748	#else
749	typedef uint32_t IEMNATIVEINSTR;
750	#endif
751	/** Pointer to a native instruction unit. */
752	typedef IEMNATIVEINSTR *PIEMNATIVEINSTR;
753
754	/**
755	* A call for the threaded call table.
756	*/
757	typedef struct IEMTHRDEDCALLENTRY
758	{
759	/** The function to call (IEMTHREADEDFUNCS). */
760	uint16_t enmFunction;
761	/** Instruction number in the TB (for statistics). */
762	uint8_t idxInstr;
763	uint8_t uUnused0;
764
765	/** Offset into IEMTB::pabOpcodes. */
766	uint16_t offOpcode;
767	/** The opcode length. */
768	uint8_t cbOpcode;
769	/** Index in to IEMTB::aRanges. */
770	uint8_t idxRange;
771
772	/** Generic parameters. */
773	uint64_t auParams[3];
774	} IEMTHRDEDCALLENTRY;
775	AssertCompileSize(IEMTHRDEDCALLENTRY, sizeof(uint64_t) * 4);
776	/** Pointer to a threaded call entry. */
777	typedef struct IEMTHRDEDCALLENTRY *PIEMTHRDEDCALLENTRY;
778	/** Pointer to a const threaded call entry. */
779	typedef IEMTHRDEDCALLENTRY const *PCIEMTHRDEDCALLENTRY;
780
781	/** Native IEM TB 'function' typedef.
782	* This will throw/longjmp on occation. */
783	#if RT_CPLUSPLUS_PREREQ(201700)
784	typedef int FNIEMTBNATIVE(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
785	#else
786	typedef int FNIEMTBNATIVE(PVMCPUCC pVCpu);
787	#endif
788	/** Pointer to a native IEM TB entry point function.
789	* This will throw/longjmp on occation. */
790	typedef FNIEMTBNATIVE *PFNIEMTBNATIVE;
791
792
793	/**
794	* Translation block.
795	*
796	* The current plan is to just keep TBs and associated lookup hash table private
797	* to each VCpu as that simplifies TB removal greatly (no races) and generally
798	* avoids using expensive atomic primitives for updating lists and stuff.
799	*/
800	#pragma pack(2) /* to prevent the Thrd structure from being padded unnecessarily */
801	typedef struct IEMTB
802	{
803	/** Next block with the same hash table entry. */
804	struct IEMTB *pNext;
805	/** Usage counter. */
806	uint32_t cUsed;
807	/** The IEMCPU::msRecompilerPollNow last time it was used. */
808	uint32_t msLastUsed;
809	/** The allocation chunk this TB belongs to. */
810	uint8_t idxAllocChunk;
811
812	uint8_t abUnused[3];
813	uint32_t uUnused;
814
815
816	/** @name What uniquely identifies the block.
817	* @{ */
818	RTGCPHYS GCPhysPc;
819	/** IEMTB_F_XXX (i.e. IEM_F_XXX ++). */
820	uint32_t fFlags;
821	union
822	{
823	struct
824	{
825	/*< Relevant CS X86DESCATTR_XXX bits. /
826	uint16_t fAttr;
827	} x86;
828	};
829	/** @} */
830
831	/** Number of opcode ranges. */
832	uint8_t cRanges;
833	/** Statistics: Number of instructions in the block. */
834	uint8_t cInstructions;
835
836	/** Type specific info. */
837	union
838	{
839	struct
840	{
841	/** The call sequence table. */
842	PIEMTHRDEDCALLENTRY paCalls;
843	/** Number of calls in paCalls. */
844	uint16_t cCalls;
845	/** Number of calls allocated. */
846	uint16_t cAllocated;
847	} Thrd;
848	struct
849	{
850	/** The native instructions (PFNIEMTBNATIVE). */
851	PIEMNATIVEINSTR paInstructions;
852	/** Number of instructions pointed to by paInstructions. */
853	uint32_t cInstructions;
854	} Native;
855	/** Generic view for zeroing when freeing. */
856	struct
857	{
858	uintptr_t uPtr;
859	uint32_t uData;
860	} Gen;
861	};
862
863	/** Number of bytes of opcodes stored in pabOpcodes. */
864	uint16_t cbOpcodes;
865	/** The max storage available in the pabOpcodes block. */
866	uint16_t cbOpcodesAllocated;
867	/** Pointer to the opcode bytes this block was recompiled from. */
868	uint8_t *pabOpcodes;
869
870	/* --- 64 byte cache line end --- */
871
872	/** Opcode ranges.
873	*
874	* The opcode checkers and maybe TLB loading functions will use this to figure
875	* out what to do. The parameter will specify an entry and the opcode offset to
876	* start at and the minimum number of bytes to verify (instruction length).
877	*
878	* When VT-x and AMD-V looks up the opcode bytes for an exitting instruction,
879	* they'll first translate RIP (+ cbInstr - 1) to a physical address using the
880	* code TLB (must have a valid entry for that address) and scan the ranges to
881	* locate the corresponding opcodes. Probably.
882	*/
883	struct IEMTBOPCODERANGE
884	{
885	/** Offset within pabOpcodes. */
886	uint16_t offOpcodes;
887	/** Number of bytes. */
888	uint16_t cbOpcodes;
889	/** The page offset. */
890	RT_GCC_EXTENSION
891	uint16_t offPhysPage : 12;
892	/** Unused bits. */
893	RT_GCC_EXTENSION
894	uint16_t u2Unused : 2;
895	/** Index into GCPhysPc + aGCPhysPages for the physical page address. */
896	RT_GCC_EXTENSION
897	uint16_t idxPhysPage : 2;
898	} aRanges[8];
899
900	/** Physical pages that this TB covers.
901	* The GCPhysPc w/o page offset is element zero, so starting here with 1. */
902	RTGCPHYS aGCPhysPages[2];
903	} IEMTB;
904	#pragma pack()
905	AssertCompileMemberOffset(IEMTB, x86, 36);
906	AssertCompileMemberOffset(IEMTB, cRanges, 38);
907	AssertCompileMemberOffset(IEMTB, Thrd, 40);
908	AssertCompileMemberOffset(IEMTB, Thrd.cCalls, 48);
909	AssertCompileMemberOffset(IEMTB, cbOpcodes, 52);
910	AssertCompileMemberSize(IEMTB, aRanges[0], 6);
911	#if 1
912	AssertCompileSize(IEMTB, 128);
913	# define IEMTB_SIZE_IS_POWER_OF_TWO /*< The IEMTB size is a power of two. /
914	#else
915	AssertCompileSize(IEMTB, 168);
916	# undef IEMTB_SIZE_IS_POWER_OF_TWO
917	#endif
918
919	/** Pointer to a translation block. */
920	typedef IEMTB *PIEMTB;
921	/** Pointer to a const translation block. */
922	typedef IEMTB const *PCIEMTB;
923
924	/**
925	* A chunk of memory in the TB allocator.
926	*/
927	typedef struct IEMTBCHUNK
928	{
929	/** Pointer to the translation blocks in this chunk. */
930	PIEMTB paTbs;
931	#ifdef IN_RING0
932	/** Allocation handle. */
933	RTR0MEMOBJ hMemObj;
934	#endif
935	} IEMTBCHUNK;
936
937	/**
938	* A per-CPU translation block allocator.
939	*
940	* Because of how the IEMTBCACHE uses the lower 6 bits of the TB address to keep
941	* the length of the collision list, and of course also for cache line alignment
942	* reasons, the TBs must be allocated with at least 64-byte alignment.
943	* Memory is there therefore allocated using one of the page aligned allocators.
944	*
945	*
946	* To avoid wasting too much memory, it is allocated piecemeal as needed,
947	* in chunks (IEMTBCHUNK) of 2 MiB or more. The TB has an 8-bit chunk index
948	* that enables us to quickly calculate the allocation bitmap position when
949	* freeing the translation block.
950	*/
951	typedef struct IEMTBALLOCATOR
952	{
953	/** Magic value (IEMTBALLOCATOR_MAGIC). */
954	uint32_t uMagic;
955
956	#ifdef IEMTB_SIZE_IS_POWER_OF_TWO
957	/** Mask corresponding to cTbsPerChunk - 1. */
958	uint32_t fChunkMask;
959	/** Shift count corresponding to cTbsPerChunk. */
960	uint8_t cChunkShift;
961	#else
962	uint32_t uUnused;
963	uint8_t bUnused;
964	#endif
965	/** Number of chunks we're allowed to allocate. */
966	uint8_t cMaxChunks;
967	/** Number of chunks currently populated. */
968	uint16_t cAllocatedChunks;
969	/** Number of translation blocks per chunk. */
970	uint32_t cTbsPerChunk;
971	/** Chunk size. */
972	uint32_t cbPerChunk;
973
974	/** The maximum number of TBs. */
975	uint32_t cMaxTbs;
976	/** Total number of TBs in the populated chunks.
977	* (cAllocatedChunks * cTbsPerChunk) */
978	uint32_t cTotalTbs;
979	/** The current number of TBs in use.
980	* The number of free TBs: cAllocatedTbs - cInUseTbs; */
981	uint32_t cInUseTbs;
982	/** Statistics: Number of the cInUseTbs that are native ones. */
983	uint32_t cNativeTbs;
984	/** Statistics: Number of the cInUseTbs that are threaded ones. */
985	uint32_t cThreadedTbs;
986
987	/** Where to start pruning TBs from when we're out.
988	* See iemTbAllocatorAllocSlow for details. */
989	uint32_t iPruneFrom;
990	/** Hint about which bit to start scanning the bitmap from. */
991	uint32_t iStartHint;
992
993	/** Statistics: Number of TB allocation calls. */
994	STAMCOUNTER StatAllocs;
995	/** Statistics: Number of TB free calls. */
996	STAMCOUNTER StatFrees;
997	/** Statistics: Time spend pruning. */
998	STAMPROFILE StatPrune;
999
1000	/** The delayed free list (see iemTbAlloctorScheduleForFree). */
1001	PIEMTB pDelayedFreeHead;
1002
1003	/** Allocation chunks. */
1004	IEMTBCHUNK aChunks[256];
1005
1006	/** Allocation bitmap for all possible chunk chunks. */
1007	RT_FLEXIBLE_ARRAY_EXTENSION
1008	uint64_t bmAllocated[RT_FLEXIBLE_ARRAY];
1009	} IEMTBALLOCATOR;
1010	/** Pointer to a TB allocator. */
1011	typedef struct IEMTBALLOCATOR *PIEMTBALLOCATOR;
1012
1013	/** Magic value for the TB allocator (Emmet Harley Cohen). */
1014	#define IEMTBALLOCATOR_MAGIC UINT32_C(0x19900525)
1015
1016
1017	/**
1018	* A per-CPU translation block cache (hash table).
1019	*
1020	* The hash table is allocated once during IEM initialization and size double
1021	* the max TB count, rounded up to the nearest power of two (so we can use and
1022	* AND mask rather than a rest division when hashing).
1023	*/
1024	typedef struct IEMTBCACHE
1025	{
1026	/** Magic value (IEMTBCACHE_MAGIC). */
1027	uint32_t uMagic;
1028	/** Size of the hash table. This is a power of two. */
1029	uint32_t cHash;
1030	/** The mask corresponding to cHash. */
1031	uint32_t uHashMask;
1032	uint32_t uPadding;
1033
1034	/** @name Statistics
1035	* @{ */
1036	/** Number of collisions ever. */
1037	STAMCOUNTER cCollisions;
1038
1039	/** Statistics: Number of TB lookup misses. */
1040	STAMCOUNTER cLookupMisses;
1041	/** Statistics: Number of TB lookup hits (debug only). */
1042	STAMCOUNTER cLookupHits;
1043	STAMCOUNTER auPadding2[3];
1044	/** Statistics: Collision list length pruning. */
1045	STAMPROFILE StatPrune;
1046	/** @} */
1047
1048	/** The hash table itself.
1049	* @note The lower 6 bits of the pointer is used for keeping the collision
1050	* list length, so we can take action when it grows too long.
1051	* This works because TBs are allocated using a 64 byte (or
1052	* higher) alignment from page aligned chunks of memory, so the lower
1053	* 6 bits of the address will always be zero.
1054	* See IEMTBCACHE_PTR_COUNT_MASK, IEMTBCACHE_PTR_MAKE and friends.
1055	*/
1056	RT_FLEXIBLE_ARRAY_EXTENSION
1057	PIEMTB apHash[RT_FLEXIBLE_ARRAY];
1058	} IEMTBCACHE;
1059	/** Pointer to a per-CPU translation block cahce. */
1060	typedef IEMTBCACHE *PIEMTBCACHE;
1061
1062	/** Magic value for IEMTBCACHE (Johnny O'Neal). */
1063	#define IEMTBCACHE_MAGIC UINT32_C(0x19561010)
1064
1065	/** The collision count mask for IEMTBCACHE::apHash entries. */
1066	#define IEMTBCACHE_PTR_COUNT_MASK ((uintptr_t)0x3f)
1067	/** The max collision count for IEMTBCACHE::apHash entries before pruning. */
1068	#define IEMTBCACHE_PTR_MAX_COUNT ((uintptr_t)0x30)
1069	/** Combine a TB pointer and a collision list length into a value for an
1070	* IEMTBCACHE::apHash entry. */
1071	#define IEMTBCACHE_PTR_MAKE(a_pTb, a_cCount) (PIEMTB)((uintptr_t)(a_pTb) \| (a_cCount))
1072	/** Combine a TB pointer and a collision list length into a value for an
1073	* IEMTBCACHE::apHash entry. */
1074	#define IEMTBCACHE_PTR_GET_TB(a_pHashEntry) (PIEMTB)((uintptr_t)(a_pHashEntry) & ~IEMTBCACHE_PTR_COUNT_MASK)
1075	/** Combine a TB pointer and a collision list length into a value for an
1076	* IEMTBCACHE::apHash entry. */
1077	#define IEMTBCACHE_PTR_GET_COUNT(a_pHashEntry) ((uintptr_t)(a_pHashEntry) & IEMTBCACHE_PTR_COUNT_MASK)
1078
1079	/**
1080	* Calculates the hash table slot for a TB from physical PC address and TB flags.
1081	*/
1082	#define IEMTBCACHE_HASH(a_paCache, a_fTbFlags, a_GCPhysPc) \
1083	IEMTBCACHE_HASH_NO_KEY_MASK(a_paCache, (a_fTbFlags) & IEMTB_F_KEY_MASK, a_GCPhysPc)
1084
1085	/**
1086	* Calculates the hash table slot for a TB from physical PC address and TB
1087	* flags, ASSUMING the caller has applied IEMTB_F_KEY_MASK to @a a_fTbFlags.
1088	*/
1089	#define IEMTBCACHE_HASH_NO_KEY_MASK(a_paCache, a_fTbFlags, a_GCPhysPc) \
1090	(((uint32_t)(a_GCPhysPc) ^ (a_fTbFlags)) & (a_paCache)->uHashMask)
1091
1092
1093	/** @name IEMBRANCHED_F_XXX - Branched indicator (IEMCPU::fTbBranched).
1094	*
1095	* These flags parallels IEM_CIMPL_F_BRANCH_XXX.
1096	*
1097	* @{ */
1098	/** Value if no branching happened recently. */
1099	#define IEMBRANCHED_F_NO UINT8_C(0x00)
1100	/** Flag set if direct branch, clear if absolute or indirect. */
1101	#define IEMBRANCHED_F_DIRECT UINT8_C(0x01)
1102	/** Flag set if indirect branch, clear if direct or relative. */
1103	#define IEMBRANCHED_F_INDIRECT UINT8_C(0x02)
1104	/** Flag set if relative branch, clear if absolute or indirect. */
1105	#define IEMBRANCHED_F_RELATIVE UINT8_C(0x04)
1106	/** Flag set if conditional branch, clear if unconditional. */
1107	#define IEMBRANCHED_F_CONDITIONAL UINT8_C(0x08)
1108	/** Flag set if it's a far branch. */
1109	#define IEMBRANCHED_F_FAR UINT8_C(0x10)
1110	/** Flag set (by IEM_MC_REL_JMP_XXX) if it's a zero bytes relative jump. */
1111	#define IEMBRANCHED_F_ZERO UINT8_C(0x20)
1112	/** @} */
1113
1114
1115	/**
1116	* The per-CPU IEM state.
1117	*/
1118	typedef struct IEMCPU
1119	{
1120	/** Info status code that needs to be propagated to the IEM caller.
1121	* This cannot be passed internally, as it would complicate all success
1122	* checks within the interpreter making the code larger and almost impossible
1123	* to get right. Instead, we'll store status codes to pass on here. Each
1124	* source of these codes will perform appropriate sanity checks. */
1125	int32_t rcPassUp; /* 0x00 */
1126	/** Execution flag, IEM_F_XXX. */
1127	uint32_t fExec; /* 0x04 */
1128
1129	/** @name Decoder state.
1130	* @{ */
1131	#ifndef IEM_WITH_OPAQUE_DECODER_STATE
1132	# ifdef IEM_WITH_CODE_TLB
1133	/** The offset of the next instruction byte. */
1134	uint32_t offInstrNextByte; /* 0x08 */
1135	/** The number of bytes available at pbInstrBuf for the current instruction.
1136	* This takes the max opcode length into account so that doesn't need to be
1137	* checked separately. */
1138	uint32_t cbInstrBuf; /* 0x0c */
1139	/** Pointer to the page containing RIP, user specified buffer or abOpcode.
1140	* This can be NULL if the page isn't mappable for some reason, in which
1141	* case we'll do fallback stuff.
1142	*
1143	* If we're executing an instruction from a user specified buffer,
1144	* IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
1145	* aligned pointer but pointer to the user data.
1146	*
1147	* For instructions crossing pages, this will start on the first page and be
1148	* advanced to the next page by the time we've decoded the instruction. This
1149	* therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
1150	*/
1151	uint8_t const pbInstrBuf; / 0x10 */
1152	# if ARCH_BITS == 32
1153	uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
1154	# endif
1155	/** The program counter corresponding to pbInstrBuf.
1156	* This is set to a non-canonical address when we need to invalidate it. */
1157	uint64_t uInstrBufPc; /* 0x18 */
1158	/** The guest physical address corresponding to pbInstrBuf. */
1159	RTGCPHYS GCPhysInstrBuf; /* 0x20 */
1160	/** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
1161	* This takes the CS segment limit into account. */
1162	uint16_t cbInstrBufTotal; /* 0x28 */
1163	/** Offset into pbInstrBuf of the first byte of the current instruction.
1164	* Can be negative to efficiently handle cross page instructions. */
1165	int16_t offCurInstrStart; /* 0x2a */
1166
1167	/** The prefix mask (IEM_OP_PRF_XXX). */
1168	uint32_t fPrefixes; /* 0x2c */
1169	/** The extra REX ModR/M register field bit (REX.R << 3). */
1170	uint8_t uRexReg; /* 0x30 */
1171	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
1172	* (REX.B << 3). */
1173	uint8_t uRexB; /* 0x31 */
1174	/** The extra REX SIB index field bit (REX.X << 3). */
1175	uint8_t uRexIndex; /* 0x32 */
1176
1177	/** The effective segment register (X86_SREG_XXX). */
1178	uint8_t iEffSeg; /* 0x33 */
1179
1180	/** The offset of the ModR/M byte relative to the start of the instruction. */
1181	uint8_t offModRm; /* 0x34 */
1182
1183	# ifdef IEM_WITH_CODE_TLB_AND_OPCODE_BUF
1184	/** The current offset into abOpcode. */
1185	uint8_t offOpcode; /* 0x35 */
1186	# else
1187	uint8_t bUnused; /* 0x35 */
1188	# endif
1189	# else /* !IEM_WITH_CODE_TLB */
1190	/** The size of what has currently been fetched into abOpcode. */
1191	uint8_t cbOpcode; /* 0x08 */
1192	/** The current offset into abOpcode. */
1193	uint8_t offOpcode; /* 0x09 */
1194	/** The offset of the ModR/M byte relative to the start of the instruction. */
1195	uint8_t offModRm; /* 0x0a */
1196
1197	/** The effective segment register (X86_SREG_XXX). */
1198	uint8_t iEffSeg; /* 0x0b */
1199
1200	/** The prefix mask (IEM_OP_PRF_XXX). */
1201	uint32_t fPrefixes; /* 0x0c */
1202	/** The extra REX ModR/M register field bit (REX.R << 3). */
1203	uint8_t uRexReg; /* 0x10 */
1204	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
1205	* (REX.B << 3). */
1206	uint8_t uRexB; /* 0x11 */
1207	/** The extra REX SIB index field bit (REX.X << 3). */
1208	uint8_t uRexIndex; /* 0x12 */
1209
1210	# endif /* !IEM_WITH_CODE_TLB */
1211
1212	/** The effective operand mode. */
1213	IEMMODE enmEffOpSize; /* 0x36, 0x13 */
1214	/** The default addressing mode. */
1215	IEMMODE enmDefAddrMode; /* 0x37, 0x14 */
1216	/** The effective addressing mode. */
1217	IEMMODE enmEffAddrMode; /* 0x38, 0x15 */
1218	/** The default operand mode. */
1219	IEMMODE enmDefOpSize; /* 0x39, 0x16 */
1220
1221	/** Prefix index (VEX.pp) for two byte and three byte tables. */
1222	uint8_t idxPrefix; /* 0x3a, 0x17 */
1223	/** 3rd VEX/EVEX/XOP register.
1224	* Please use IEM_GET_EFFECTIVE_VVVV to access. */
1225	uint8_t uVex3rdReg; /* 0x3b, 0x18 */
1226	/** The VEX/EVEX/XOP length field. */
1227	uint8_t uVexLength; /* 0x3c, 0x19 */
1228	/** Additional EVEX stuff. */
1229	uint8_t fEvexStuff; /* 0x3d, 0x1a */
1230
1231	# ifndef IEM_WITH_CODE_TLB
1232	/** Explicit alignment padding. */
1233	uint8_t abAlignment2a[1]; /* 0x1b */
1234	# endif
1235	/** The FPU opcode (FOP). */
1236	uint16_t uFpuOpcode; /* 0x3e, 0x1c */
1237	# ifndef IEM_WITH_CODE_TLB
1238	/** Explicit alignment padding. */
1239	uint8_t abAlignment2b[2]; /* 0x1e */
1240	# endif
1241
1242	/** The opcode bytes. */
1243	uint8_t abOpcode[15]; /* 0x40, 0x20 */
1244	/** Explicit alignment padding. */
1245	# ifdef IEM_WITH_CODE_TLB
1246	//uint8_t abAlignment2c[0x4f - 0x4f]; /* 0x4f */
1247	# else
1248	uint8_t abAlignment2c[0x4f - 0x2f]; /* 0x2f */
1249	# endif
1250	#else /* IEM_WITH_OPAQUE_DECODER_STATE */
1251	uint8_t abOpaqueDecoder[0x4f - 0x8];
1252	#endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1253	/** @} */
1254
1255
1256	/** The number of active guest memory mappings. */
1257	uint8_t cActiveMappings; /* 0x4f, 0x4f */
1258
1259	/** Records for tracking guest memory mappings. */
1260	struct
1261	{
1262	/** The address of the mapped bytes. */
1263	R3R0PTRTYPE(void *) pv;
1264	/** The access flags (IEM_ACCESS_XXX).
1265	* IEM_ACCESS_INVALID if the entry is unused. */
1266	uint32_t fAccess;
1267	#if HC_ARCH_BITS == 64
1268	uint32_t u32Alignment4; /*< Alignment padding. /
1269	#endif
1270	} aMemMappings[3]; /* 0x50 LB 0x30 */
1271
1272	/** Locking records for the mapped memory. */
1273	union
1274	{
1275	PGMPAGEMAPLOCK Lock;
1276	uint64_t au64Padding[2];
1277	} aMemMappingLocks[3]; /* 0x80 LB 0x30 */
1278
1279	/** Bounce buffer info.
1280	* This runs in parallel to aMemMappings. */
1281	struct
1282	{
1283	/** The physical address of the first byte. */
1284	RTGCPHYS GCPhysFirst;
1285	/** The physical address of the second page. */
1286	RTGCPHYS GCPhysSecond;
1287	/** The number of bytes in the first page. */
1288	uint16_t cbFirst;
1289	/** The number of bytes in the second page. */
1290	uint16_t cbSecond;
1291	/** Whether it's unassigned memory. */
1292	bool fUnassigned;
1293	/** Explicit alignment padding. */
1294	bool afAlignment5[3];
1295	} aMemBbMappings[3]; /* 0xb0 LB 0x48 */
1296
1297	/** The flags of the current exception / interrupt. */
1298	uint32_t fCurXcpt; /* 0xf8 */
1299	/** The current exception / interrupt. */
1300	uint8_t uCurXcpt; /* 0xfc */
1301	/** Exception / interrupt recursion depth. */
1302	int8_t cXcptRecursions; /* 0xfb */
1303
1304	/** The next unused mapping index.
1305	* @todo try find room for this up with cActiveMappings. */
1306	uint8_t iNextMapping; /* 0xfd */
1307	uint8_t abAlignment7[1];
1308
1309	/** Bounce buffer storage.
1310	* This runs in parallel to aMemMappings and aMemBbMappings. */
1311	struct
1312	{
1313	uint8_t ab[512];
1314	} aBounceBuffers[3]; /* 0x100 LB 0x600 */
1315
1316
1317	/** Pointer set jump buffer - ring-3 context. */
1318	R3PTRTYPE(jmp_buf *) pJmpBufR3;
1319	/** Pointer set jump buffer - ring-0 context. */
1320	R0PTRTYPE(jmp_buf *) pJmpBufR0;
1321
1322	/** @todo Should move this near @a fCurXcpt later. */
1323	/** The CR2 for the current exception / interrupt. */
1324	uint64_t uCurXcptCr2;
1325	/** The error code for the current exception / interrupt. */
1326	uint32_t uCurXcptErr;
1327
1328	/** @name Statistics
1329	* @{ */
1330	/** The number of instructions we've executed. */
1331	uint32_t cInstructions;
1332	/** The number of potential exits. */
1333	uint32_t cPotentialExits;
1334	/** The number of bytes data or stack written (mostly for IEMExecOneEx).
1335	* This may contain uncommitted writes. */
1336	uint32_t cbWritten;
1337	/** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
1338	uint32_t cRetInstrNotImplemented;
1339	/** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
1340	uint32_t cRetAspectNotImplemented;
1341	/** Counts informational statuses returned (other than VINF_SUCCESS). */
1342	uint32_t cRetInfStatuses;
1343	/** Counts other error statuses returned. */
1344	uint32_t cRetErrStatuses;
1345	/** Number of times rcPassUp has been used. */
1346	uint32_t cRetPassUpStatus;
1347	/** Number of times RZ left with instruction commit pending for ring-3. */
1348	uint32_t cPendingCommit;
1349	/** Number of long jumps. */
1350	uint32_t cLongJumps;
1351	/** @} */
1352
1353	/** @name Target CPU information.
1354	* @{ */
1355	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
1356	/** The target CPU. */
1357	uint8_t uTargetCpu;
1358	#else
1359	uint8_t bTargetCpuPadding;
1360	#endif
1361	/** For selecting assembly works matching the target CPU EFLAGS behaviour, see
1362	* IEMTARGETCPU_EFL_BEHAVIOR_XXX for values, with the 1st entry for when no
1363	* native host support and the 2nd for when there is.
1364	*
1365	* The two values are typically indexed by a g_CpumHostFeatures bit.
1366	*
1367	* This is for instance used for the BSF & BSR instructions where AMD and
1368	* Intel CPUs produce different EFLAGS. */
1369	uint8_t aidxTargetCpuEflFlavour[2];
1370
1371	/** The CPU vendor. */
1372	CPUMCPUVENDOR enmCpuVendor;
1373	/** @} */
1374
1375	/** @name Host CPU information.
1376	* @{ */
1377	/** The CPU vendor. */
1378	CPUMCPUVENDOR enmHostCpuVendor;
1379	/** @} */
1380
1381	/** Counts RDMSR \#GP(0) LogRel(). */
1382	uint8_t cLogRelRdMsr;
1383	/** Counts WRMSR \#GP(0) LogRel(). */
1384	uint8_t cLogRelWrMsr;
1385	/** Alignment padding. */
1386	uint8_t abAlignment9[46];
1387
1388	/** @name Recompilation
1389	* @{ */
1390	/** Pointer to the current translation block.
1391	* This can either be one being executed or one being compiled. */
1392	R3PTRTYPE(PIEMTB) pCurTbR3;
1393	/** Fixed TB used for threaded recompilation.
1394	* This is allocated once with maxed-out sizes and re-used afterwards. */
1395	R3PTRTYPE(PIEMTB) pThrdCompileTbR3;
1396	/** Pointer to the ring-3 TB cache for this EMT. */
1397	R3PTRTYPE(PIEMTBCACHE) pTbCacheR3;
1398	/** The PC (RIP) at the start of pCurTbR3/pCurTbR0.
1399	* The TBs are based on physical addresses, so this is needed to correleated
1400	* RIP to opcode bytes stored in the TB (AMD-V / VT-x). */
1401	uint64_t uCurTbStartPc;
1402	/** Number of threaded TBs executed. */
1403	uint64_t cTbExecThreaded;
1404	/** Number of native TBs executed. */
1405	uint64_t cTbExecNative;
1406	/** Whether we need to check the opcode bytes for the current instruction.
1407	* This is set by a previous instruction if it modified memory or similar. */
1408	bool fTbCheckOpcodes;
1409	/** Indicates whether and how we just branched - IEMBRANCHED_F_XXX. */
1410	uint8_t fTbBranched;
1411	/** Set when GCPhysInstrBuf is updated because of a page crossing. */
1412	bool fTbCrossedPage;
1413	/** Whether to end the current TB. */
1414	bool fEndTb;
1415	/** Number of instructions before we need emit an IRQ check call again.
1416	* This helps making sure we don't execute too long w/o checking for
1417	* interrupts and immediately following instructions that may enable
1418	* interrupts (e.g. POPF, IRET, STI). With STI an additional hack is
1419	* required to make sure we check following the next instruction as well, see
1420	* fTbCurInstrIsSti. */
1421	uint8_t cInstrTillIrqCheck;
1422	/** Indicates that the current instruction is an STI. This is set by the
1423	* iemCImpl_sti code and subsequently cleared by the recompiler. */
1424	bool fTbCurInstrIsSti;
1425	/** Spaced reserved for recompiler data / alignment. */
1426	bool afRecompilerStuff1[2+4];
1427	/** The virtual sync time at the last timer poll call. */
1428	uint32_t msRecompilerPollNow;
1429	/** Previous GCPhysInstrBuf value - only valid if fTbCrossedPage is set. */
1430	RTGCPHYS GCPhysInstrBufPrev;
1431	/** Copy of IEMCPU::GCPhysInstrBuf after decoding a branch instruction.
1432	* This is used together with fTbBranched and GCVirtTbBranchSrcBuf to determin
1433	* whether a branch instruction jumps to a new page or stays within the
1434	* current one. */
1435	RTGCPHYS GCPhysTbBranchSrcBuf;
1436	/** Copy of IEMCPU::uInstrBufPc after decoding a branch instruction. */
1437	uint64_t GCVirtTbBranchSrcBuf;
1438	/** Pointer to the ring-3 TB allocator for this EMT. */
1439	R3PTRTYPE(PIEMTBALLOCATOR) pTbAllocatorR3;
1440	/** Pointer to the ring-3 executable memory allocator for this EMT. */
1441	R3PTRTYPE(struct IEMEXECMEMALLOCATOR *) pExecMemAllocatorR3;
1442	/** Pointer to the native recompiler state for ring-3. */
1443	R3PTRTYPE(struct IEMRECOMPILERSTATE *) pNativeRecompilerStateR3;
1444	/** Alignment padding. */
1445	uint64_t auAlignment10[5];
1446	/** Statistics: Times TB execution was broken off before reaching the end. */
1447	STAMCOUNTER StatTbExecBreaks;
1448	/** Statistics: Times BltIn_CheckIrq breaks out of the TB. */
1449	STAMCOUNTER StatCheckIrqBreaks;
1450	/** Statistics: Times BltIn_CheckMode breaks out of the TB. */
1451	STAMCOUNTER StatCheckModeBreaks;
1452	/** Statistics: Times a post jump target check missed and had to find new TB. */
1453	STAMCOUNTER StatCheckBranchMisses;
1454	/** Statistics: Times a jump or page crossing required a TB with CS.LIM checking. */
1455	STAMCOUNTER StatCheckNeedCsLimChecking;
1456	/** Threaded TB statistics: Number of instructions per TB. */
1457	STAMPROFILE StatTbThreadedInstr;
1458	/** Threaded TB statistics: Number of calls per TB. */
1459	STAMPROFILE StatTbThreadedCalls;
1460	/** Native TB statistics: Native code size per TB. */
1461	STAMPROFILE StatTbNativeCode;
1462	/** Native TB statistics: Profiling native recompilation. */
1463	STAMPROFILE StatNativeRecompilation;
1464	/** @} */
1465
1466	/** Data TLB.
1467	* @remarks Must be 64-byte aligned. */
1468	IEMTLB DataTlb;
1469	/** Instruction TLB.
1470	* @remarks Must be 64-byte aligned. */
1471	IEMTLB CodeTlb;
1472
1473	/** Exception statistics. */
1474	STAMCOUNTER aStatXcpts[32];
1475	/** Interrupt statistics. */
1476	uint32_t aStatInts[256];
1477
1478	#if defined(VBOX_WITH_STATISTICS) && !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
1479	/** Instruction statistics for ring-0/raw-mode. */
1480	IEMINSTRSTATS StatsRZ;
1481	/** Instruction statistics for ring-3. */
1482	IEMINSTRSTATS StatsR3;
1483	#endif
1484	} IEMCPU;
1485	AssertCompileMemberOffset(IEMCPU, cActiveMappings, 0x4f);
1486	AssertCompileMemberAlignment(IEMCPU, aMemMappings, 16);
1487	AssertCompileMemberAlignment(IEMCPU, aMemMappingLocks, 16);
1488	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 64);
1489	AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
1490	AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
1491
1492	/** Pointer to the per-CPU IEM state. */
1493	typedef IEMCPU *PIEMCPU;
1494	/** Pointer to the const per-CPU IEM state. */
1495	typedef IEMCPU const *PCIEMCPU;
1496
1497
1498	/** @def IEM_GET_CTX
1499	* Gets the guest CPU context for the calling EMT.
1500	* @returns PCPUMCTX
1501	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1502	*/
1503	#define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
1504
1505	/** @def IEM_CTX_ASSERT
1506	* Asserts that the @a a_fExtrnMbz is present in the CPU context.
1507	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1508	* @param a_fExtrnMbz The mask of CPUMCTX_EXTRN_XXX flags that must be zero.
1509	*/
1510	#define IEM_CTX_ASSERT(a_pVCpu, a_fExtrnMbz) \
1511	AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
1512	("fExtrn=%#RX64 & fExtrnMbz=%#RX64 -> %#RX64\n", \
1513	(a_pVCpu)->cpum.GstCtx.fExtrn, (a_fExtrnMbz), (a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz) ))
1514
1515	/** @def IEM_CTX_IMPORT_RET
1516	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
1517	*
1518	* Will call the keep to import the bits as needed.
1519	*
1520	* Returns on import failure.
1521	*
1522	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1523	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
1524	*/
1525	#define IEM_CTX_IMPORT_RET(a_pVCpu, a_fExtrnImport) \
1526	do { \
1527	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
1528	{ /* likely */ } \
1529	else \
1530	{ \
1531	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
1532	AssertRCReturn(rcCtxImport, rcCtxImport); \
1533	} \
1534	} while (0)
1535
1536	/** @def IEM_CTX_IMPORT_NORET
1537	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
1538	*
1539	* Will call the keep to import the bits as needed.
1540	*
1541	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1542	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
1543	*/
1544	#define IEM_CTX_IMPORT_NORET(a_pVCpu, a_fExtrnImport) \
1545	do { \
1546	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
1547	{ /* likely */ } \
1548	else \
1549	{ \
1550	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
1551	AssertLogRelRC(rcCtxImport); \
1552	} \
1553	} while (0)
1554
1555	/** @def IEM_CTX_IMPORT_JMP
1556	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
1557	*
1558	* Will call the keep to import the bits as needed.
1559	*
1560	* Jumps on import failure.
1561	*
1562	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1563	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
1564	*/
1565	#define IEM_CTX_IMPORT_JMP(a_pVCpu, a_fExtrnImport) \
1566	do { \
1567	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
1568	{ /* likely */ } \
1569	else \
1570	{ \
1571	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
1572	AssertRCStmt(rcCtxImport, IEM_DO_LONGJMP(pVCpu, rcCtxImport)); \
1573	} \
1574	} while (0)
1575
1576
1577
1578	/** @def IEM_GET_TARGET_CPU
1579	* Gets the current IEMTARGETCPU value.
1580	* @returns IEMTARGETCPU value.
1581	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1582	*/
1583	#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
1584	# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
1585	#else
1586	# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
1587	#endif
1588
1589	/** @def IEM_GET_INSTR_LEN
1590	* Gets the instruction length. */
1591	#ifdef IEM_WITH_CODE_TLB
1592	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
1593	#else
1594	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
1595	#endif
1596
1597	/** @def IEM_TRY_SETJMP
1598	* Wrapper around setjmp / try, hiding all the ugly differences.
1599	*
1600	* @note Use with extreme care as this is a fragile macro.
1601	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
1602	* @param a_rcTarget The variable that should receive the status code in case
1603	* of a longjmp/throw.
1604	*/
1605	/** @def IEM_TRY_SETJMP_AGAIN
1606	* For when setjmp / try is used again in the same variable scope as a previous
1607	* IEM_TRY_SETJMP invocation.
1608	*/
1609	/** @def IEM_CATCH_LONGJMP_BEGIN
1610	* Start wrapper for catch / setjmp-else.
1611	*
1612	* This will set up a scope.
1613	*
1614	* @note Use with extreme care as this is a fragile macro.
1615	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
1616	* @param a_rcTarget The variable that should receive the status code in case
1617	* of a longjmp/throw.
1618	*/
1619	/** @def IEM_CATCH_LONGJMP_END
1620	* End wrapper for catch / setjmp-else.
1621	*
1622	* This will close the scope set up by IEM_CATCH_LONGJMP_BEGIN and clean up the
1623	* state.
1624	*
1625	* @note Use with extreme care as this is a fragile macro.
1626	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
1627	*/
1628	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
1629	# ifdef IEM_WITH_THROW_CATCH
1630	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
1631	a_rcTarget = VINF_SUCCESS; \
1632	try
1633	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
1634	IEM_TRY_SETJMP(a_pVCpu, a_rcTarget)
1635	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
1636	catch (int rcThrown) \
1637	{ \
1638	a_rcTarget = rcThrown
1639	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
1640	} \
1641	((void)0)
1642	# else /* !IEM_WITH_THROW_CATCH */
1643	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
1644	jmp_buf JmpBuf; \
1645	jmp_buf * volatile pSavedJmpBuf = pVCpu->iem.s.CTX_SUFF(pJmpBuf); \
1646	pVCpu->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
1647	if ((rcStrict = setjmp(JmpBuf)) == 0)
1648	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
1649	pSavedJmpBuf = pVCpu->iem.s.CTX_SUFF(pJmpBuf); \
1650	pVCpu->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
1651	if ((rcStrict = setjmp(JmpBuf)) == 0)
1652	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
1653	else \
1654	{ \
1655	((void)0)
1656	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
1657	} \
1658	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = pSavedJmpBuf
1659	# endif /* !IEM_WITH_THROW_CATCH */
1660	#endif /* IEM_WITH_SETJMP */
1661
1662
1663	/**
1664	* Shared per-VM IEM data.
1665	*/
1666	typedef struct IEM
1667	{
1668	/** The VMX APIC-access page handler type. */
1669	PGMPHYSHANDLERTYPE hVmxApicAccessPage;
1670	#ifndef VBOX_WITHOUT_CPUID_HOST_CALL
1671	/** Set if the CPUID host call functionality is enabled. */
1672	bool fCpuIdHostCall;
1673	#endif
1674	} IEM;
1675
1676
1677
1678	/** @name IEM_ACCESS_XXX - Access details.
1679	* @{ */
1680	#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
1681	#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
1682	#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
1683	#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
1684	#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
1685	#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
1686	#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
1687	#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
1688	#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
1689	#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
1690	/** The writes are partial, so if initialize the bounce buffer with the
1691	* orignal RAM content. */
1692	#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
1693	/** Used in aMemMappings to indicate that the entry is bounce buffered. */
1694	#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
1695	/** Bounce buffer with ring-3 write pending, first page. */
1696	#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
1697	/** Bounce buffer with ring-3 write pending, second page. */
1698	#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
1699	/** Not locked, accessed via the TLB. */
1700	#define IEM_ACCESS_NOT_LOCKED UINT32_C(0x00001000)
1701	/** Valid bit mask. */
1702	#define IEM_ACCESS_VALID_MASK UINT32_C(0x00001fff)
1703	/** Shift count for the TLB flags (upper word). */
1704	#define IEM_ACCESS_SHIFT_TLB_FLAGS 16
1705
1706	/** Read+write data alias. */
1707	#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
1708	/** Write data alias. */
1709	#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
1710	/** Read data alias. */
1711	#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_DATA)
1712	/** Instruction fetch alias. */
1713	#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_WHAT_CODE)
1714	/** Stack write alias. */
1715	#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
1716	/** Stack read alias. */
1717	#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_STACK)
1718	/** Stack read+write alias. */
1719	#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
1720	/** Read system table alias. */
1721	#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_SYS)
1722	/** Read+write system table alias. */
1723	#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_SYS)
1724	/** @} */
1725
1726	/** @name Prefix constants (IEMCPU::fPrefixes)
1727	* @{ */
1728	#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /*< CS segment prefix (0x2e). /
1729	#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /*< SS segment prefix (0x36). /
1730	#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /*< DS segment prefix (0x3e). /
1731	#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /*< ES segment prefix (0x26). /
1732	#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /*< FS segment prefix (0x64). /
1733	#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /*< GS segment prefix (0x65). /
1734	#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
1735
1736	#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /*< Operand size prefix (0x66). /
1737	#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /*< REX.W prefix (0x48-0x4f). /
1738	#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /*< Address size prefix (0x67). /
1739
1740	#define IEM_OP_PRF_LOCK RT_BIT_32(16) /*< Lock prefix (0xf0). /
1741	#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /*< Repeat-not-zero prefix (0xf2). /
1742	#define IEM_OP_PRF_REPZ RT_BIT_32(18) /*< Repeat-if-zero prefix (0xf3). /
1743
1744	#define IEM_OP_PRF_REX RT_BIT_32(24) /*< Any REX prefix (0x40-0x4f). /
1745	#define IEM_OP_PRF_REX_R RT_BIT_32(25) /*< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). /
1746	#define IEM_OP_PRF_REX_B RT_BIT_32(26) /*< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). /
1747	#define IEM_OP_PRF_REX_X RT_BIT_32(27) /*< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). /
1748	/** Mask with all the REX prefix flags.
1749	* This is generally for use when needing to undo the REX prefixes when they
1750	* are followed legacy prefixes and therefore does not immediately preceed
1751	* the first opcode byte.
1752	* For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
1753	#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX \| IEM_OP_PRF_REX_R \| IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X \| IEM_OP_PRF_SIZE_REX_W )
1754
1755	#define IEM_OP_PRF_VEX RT_BIT_32(28) /*< Indiciates VEX prefix. /
1756	#define IEM_OP_PRF_EVEX RT_BIT_32(29) /*< Indiciates EVEX prefix. /
1757	#define IEM_OP_PRF_XOP RT_BIT_32(30) /*< Indiciates XOP prefix. /
1758	/** @} */
1759
1760	/** @name IEMOPFORM_XXX - Opcode forms
1761	* @note These are ORed together with IEMOPHINT_XXX.
1762	* @{ */
1763	/** ModR/M: reg, r/m */
1764	#define IEMOPFORM_RM 0
1765	/** ModR/M: reg, r/m (register) */
1766	#define IEMOPFORM_RM_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
1767	/** ModR/M: reg, r/m (memory) */
1768	#define IEMOPFORM_RM_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
1769	/** ModR/M: reg, r/m */
1770	#define IEMOPFORM_RMI 1
1771	/** ModR/M: reg, r/m (register) */
1772	#define IEMOPFORM_RMI_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
1773	/** ModR/M: reg, r/m (memory) */
1774	#define IEMOPFORM_RMI_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
1775	/** ModR/M: r/m, reg */
1776	#define IEMOPFORM_MR 2
1777	/** ModR/M: r/m (register), reg */
1778	#define IEMOPFORM_MR_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
1779	/** ModR/M: r/m (memory), reg */
1780	#define IEMOPFORM_MR_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
1781	/** ModR/M: r/m, reg */
1782	#define IEMOPFORM_MRI 3
1783	/** ModR/M: r/m (register), reg */
1784	#define IEMOPFORM_MRI_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
1785	/** ModR/M: r/m (memory), reg */
1786	#define IEMOPFORM_MRI_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
1787	/** ModR/M: r/m only */
1788	#define IEMOPFORM_M 4
1789	/** ModR/M: r/m only (register). */
1790	#define IEMOPFORM_M_REG (IEMOPFORM_M \| IEMOPFORM_MOD3)
1791	/** ModR/M: r/m only (memory). */
1792	#define IEMOPFORM_M_MEM (IEMOPFORM_M \| IEMOPFORM_NOT_MOD3)
1793	/** ModR/M: reg only */
1794	#define IEMOPFORM_R 5
1795
1796	/** VEX+ModR/M: reg, r/m */
1797	#define IEMOPFORM_VEX_RM 8
1798	/** VEX+ModR/M: reg, r/m (register) */
1799	#define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM \| IEMOPFORM_MOD3)
1800	/** VEX+ModR/M: reg, r/m (memory) */
1801	#define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM \| IEMOPFORM_NOT_MOD3)
1802	/** VEX+ModR/M: r/m, reg */
1803	#define IEMOPFORM_VEX_MR 9
1804	/** VEX+ModR/M: r/m (register), reg */
1805	#define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR \| IEMOPFORM_MOD3)
1806	/** VEX+ModR/M: r/m (memory), reg */
1807	#define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR \| IEMOPFORM_NOT_MOD3)
1808	/** VEX+ModR/M: r/m only */
1809	#define IEMOPFORM_VEX_M 10
1810	/** VEX+ModR/M: r/m only (register). */
1811	#define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M \| IEMOPFORM_MOD3)
1812	/** VEX+ModR/M: r/m only (memory). */
1813	#define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M \| IEMOPFORM_NOT_MOD3)
1814	/** VEX+ModR/M: reg only */
1815	#define IEMOPFORM_VEX_R 11
1816	/** VEX+ModR/M: reg, vvvv, r/m */
1817	#define IEMOPFORM_VEX_RVM 12
1818	/** VEX+ModR/M: reg, vvvv, r/m (register). */
1819	#define IEMOPFORM_VEX_RVM_REG (IEMOPFORM_VEX_RVM \| IEMOPFORM_MOD3)
1820	/** VEX+ModR/M: reg, vvvv, r/m (memory). */
1821	#define IEMOPFORM_VEX_RVM_MEM (IEMOPFORM_VEX_RVM \| IEMOPFORM_NOT_MOD3)
1822	/** VEX+ModR/M: reg, r/m, vvvv */
1823	#define IEMOPFORM_VEX_RMV 13
1824	/** VEX+ModR/M: reg, r/m, vvvv (register). */
1825	#define IEMOPFORM_VEX_RMV_REG (IEMOPFORM_VEX_RMV \| IEMOPFORM_MOD3)
1826	/** VEX+ModR/M: reg, r/m, vvvv (memory). */
1827	#define IEMOPFORM_VEX_RMV_MEM (IEMOPFORM_VEX_RMV \| IEMOPFORM_NOT_MOD3)
1828	/** VEX+ModR/M: reg, r/m, imm8 */
1829	#define IEMOPFORM_VEX_RMI 14
1830	/** VEX+ModR/M: reg, r/m, imm8 (register). */
1831	#define IEMOPFORM_VEX_RMI_REG (IEMOPFORM_VEX_RMI \| IEMOPFORM_MOD3)
1832	/** VEX+ModR/M: reg, r/m, imm8 (memory). */
1833	#define IEMOPFORM_VEX_RMI_MEM (IEMOPFORM_VEX_RMI \| IEMOPFORM_NOT_MOD3)
1834	/** VEX+ModR/M: r/m, vvvv, reg */
1835	#define IEMOPFORM_VEX_MVR 15
1836	/** VEX+ModR/M: r/m, vvvv, reg (register) */
1837	#define IEMOPFORM_VEX_MVR_REG (IEMOPFORM_VEX_MVR \| IEMOPFORM_MOD3)
1838	/** VEX+ModR/M: r/m, vvvv, reg (memory) */
1839	#define IEMOPFORM_VEX_MVR_MEM (IEMOPFORM_VEX_MVR \| IEMOPFORM_NOT_MOD3)
1840	/** VEX+ModR/M+/n: vvvv, r/m */
1841	#define IEMOPFORM_VEX_VM 16
1842	/** VEX+ModR/M+/n: vvvv, r/m (register) */
1843	#define IEMOPFORM_VEX_VM_REG (IEMOPFORM_VEX_VM \| IEMOPFORM_MOD3)
1844	/** VEX+ModR/M+/n: vvvv, r/m (memory) */
1845	#define IEMOPFORM_VEX_VM_MEM (IEMOPFORM_VEX_VM \| IEMOPFORM_NOT_MOD3)
1846
1847	/** Fixed register instruction, no R/M. */
1848	#define IEMOPFORM_FIXED 32
1849
1850	/** The r/m is a register. */
1851	#define IEMOPFORM_MOD3 RT_BIT_32(8)
1852	/** The r/m is a memory access. */
1853	#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
1854	/** @} */
1855
1856	/** @name IEMOPHINT_XXX - Additional Opcode Hints
1857	* @note These are ORed together with IEMOPFORM_XXX.
1858	* @{ */
1859	/** Ignores the operand size prefix (66h). */
1860	#define IEMOPHINT_IGNORES_OZ_PFX RT_BIT_32(10)
1861	/** Ignores REX.W (aka WIG). */
1862	#define IEMOPHINT_IGNORES_REXW RT_BIT_32(11)
1863	/** Both the operand size prefixes (66h + REX.W) are ignored. */
1864	#define IEMOPHINT_IGNORES_OP_SIZES (IEMOPHINT_IGNORES_OZ_PFX \| IEMOPHINT_IGNORES_REXW)
1865	/** Allowed with the lock prefix. */
1866	#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
1867	/** The VEX.L value is ignored (aka LIG). */
1868	#define IEMOPHINT_VEX_L_IGNORED RT_BIT_32(12)
1869	/** The VEX.L value must be zero (i.e. 128-bit width only). */
1870	#define IEMOPHINT_VEX_L_ZERO RT_BIT_32(13)
1871	/** The VEX.V value must be zero. */
1872	#define IEMOPHINT_VEX_V_ZERO RT_BIT_32(14)
1873
1874	/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
1875	#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
1876	/** @} */
1877
1878	/**
1879	* Possible hardware task switch sources.
1880	*/
1881	typedef enum IEMTASKSWITCH
1882	{
1883	/** Task switch caused by an interrupt/exception. */
1884	IEMTASKSWITCH_INT_XCPT = 1,
1885	/** Task switch caused by a far CALL. */
1886	IEMTASKSWITCH_CALL,
1887	/** Task switch caused by a far JMP. */
1888	IEMTASKSWITCH_JUMP,
1889	/** Task switch caused by an IRET. */
1890	IEMTASKSWITCH_IRET
1891	} IEMTASKSWITCH;
1892	AssertCompileSize(IEMTASKSWITCH, 4);
1893
1894	/**
1895	* Possible CrX load (write) sources.
1896	*/
1897	typedef enum IEMACCESSCRX
1898	{
1899	/** CrX access caused by 'mov crX' instruction. */
1900	IEMACCESSCRX_MOV_CRX,
1901	/** CrX (CR0) write caused by 'lmsw' instruction. */
1902	IEMACCESSCRX_LMSW,
1903	/** CrX (CR0) write caused by 'clts' instruction. */
1904	IEMACCESSCRX_CLTS,
1905	/** CrX (CR0) read caused by 'smsw' instruction. */
1906	IEMACCESSCRX_SMSW
1907	} IEMACCESSCRX;
1908
1909	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1910	/** @name IEM_SLAT_FAIL_XXX - Second-level address translation failure information.
1911	*
1912	* These flags provide further context to SLAT page-walk failures that could not be
1913	* determined by PGM (e.g, PGM is not privy to memory access permissions).
1914	*
1915	* @{
1916	*/
1917	/** Translating a nested-guest linear address failed accessing a nested-guest
1918	* physical address. */
1919	# define IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR RT_BIT_32(0)
1920	/** Translating a nested-guest linear address failed accessing a
1921	* paging-structure entry or updating accessed/dirty bits. */
1922	# define IEM_SLAT_FAIL_LINEAR_TO_PAGE_TABLE RT_BIT_32(1)
1923	/** @} */
1924
1925	DECLCALLBACK(FNPGMPHYSHANDLER) iemVmxApicAccessPageHandler;
1926	# ifndef IN_RING3
1927	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) iemVmxApicAccessPagePfHandler;
1928	# endif
1929	#endif
1930
1931	/**
1932	* Indicates to the verifier that the given flag set is undefined.
1933	*
1934	* Can be invoked again to add more flags.
1935	*
1936	* This is a NOOP if the verifier isn't compiled in.
1937	*
1938	* @note We're temporarily keeping this until code is converted to new
1939	* disassembler style opcode handling.
1940	*/
1941	#define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
1942
1943
1944	/** @def IEM_DECL_IMPL_TYPE
1945	* For typedef'ing an instruction implementation function.
1946	*
1947	* @param a_RetType The return type.
1948	* @param a_Name The name of the type.
1949	* @param a_ArgList The argument list enclosed in parentheses.
1950	*/
1951
1952	/** @def IEM_DECL_IMPL_DEF
1953	* For defining an instruction implementation function.
1954	*
1955	* @param a_RetType The return type.
1956	* @param a_Name The name of the type.
1957	* @param a_ArgList The argument list enclosed in parentheses.
1958	*/
1959
1960	#if defined(__GNUC__) && defined(RT_ARCH_X86)
1961	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1962	__attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
1963	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1964	__attribute__((__fastcall__, __nothrow__)) DECL_HIDDEN_ONLY(a_RetType) a_Name a_ArgList
1965	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1966	__attribute__((__fastcall__, __nothrow__)) DECL_HIDDEN_ONLY(a_RetType) a_Name a_ArgList
1967
1968	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
1969	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1970	a_RetType (__fastcall a_Name) a_ArgList
1971	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1972	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
1973	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1974	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
1975
1976	#elif __cplusplus >= 201700 /* P0012R1 support */
1977	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1978	a_RetType (VBOXCALL a_Name) a_ArgList RT_NOEXCEPT
1979	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1980	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList RT_NOEXCEPT
1981	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1982	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList RT_NOEXCEPT
1983
1984	#else
1985	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1986	a_RetType (VBOXCALL a_Name) a_ArgList
1987	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1988	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList
1989	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1990	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList
1991
1992	#endif
1993
1994	/** Defined in IEMAllAImplC.cpp but also used by IEMAllAImplA.asm. */
1995	RT_C_DECLS_BEGIN
1996	extern uint8_t const g_afParity[256];
1997	RT_C_DECLS_END
1998
1999
2000	/** @name Arithmetic assignment operations on bytes (binary).
2001	* @{ */
2002	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU8, (uint8_t pu8Dst, uint8_t u8Src, uint32_t pEFlags));
2003	typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
2004	FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
2005	FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
2006	FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
2007	FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
2008	FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
2009	FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
2010	FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
2011	/** @} */
2012
2013	/** @name Arithmetic assignment operations on words (binary).
2014	* @{ */
2015	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU16, (uint16_t pu16Dst, uint16_t u16Src, uint32_t pEFlags));
2016	typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
2017	FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
2018	FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
2019	FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
2020	FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
2021	FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
2022	FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
2023	FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
2024	/** @} */
2025
2026	/** @name Arithmetic assignment operations on double words (binary).
2027	* @{ */
2028	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU32, (uint32_t pu32Dst, uint32_t u32Src, uint32_t pEFlags));
2029	typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
2030	FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
2031	FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
2032	FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
2033	FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
2034	FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
2035	FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
2036	FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
2037	FNIEMAIMPLBINU32 iemAImpl_blsi_u32, iemAImpl_blsi_u32_fallback;
2038	FNIEMAIMPLBINU32 iemAImpl_blsr_u32, iemAImpl_blsr_u32_fallback;
2039	FNIEMAIMPLBINU32 iemAImpl_blsmsk_u32, iemAImpl_blsmsk_u32_fallback;
2040	/** @} */
2041
2042	/** @name Arithmetic assignment operations on quad words (binary).
2043	* @{ */
2044	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU64, (uint64_t pu64Dst, uint64_t u64Src, uint32_t pEFlags));
2045	typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
2046	FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
2047	FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
2048	FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
2049	FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
2050	FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
2051	FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
2052	FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
2053	FNIEMAIMPLBINU64 iemAImpl_blsi_u64, iemAImpl_blsi_u64_fallback;
2054	FNIEMAIMPLBINU64 iemAImpl_blsr_u64, iemAImpl_blsr_u64_fallback;
2055	FNIEMAIMPLBINU64 iemAImpl_blsmsk_u64, iemAImpl_blsmsk_u64_fallback;
2056	/** @} */
2057
2058	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINROU8,(uint8_t const pu8Dst, uint8_t u8Src, uint32_t pEFlags));
2059	typedef FNIEMAIMPLBINROU8 *PFNIEMAIMPLBINROU8;
2060	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINROU16,(uint16_t const pu16Dst, uint16_t u16Src, uint32_t pEFlags));
2061	typedef FNIEMAIMPLBINROU16 *PFNIEMAIMPLBINROU16;
2062	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINROU32,(uint32_t const pu32Dst, uint32_t u32Src, uint32_t pEFlags));
2063	typedef FNIEMAIMPLBINROU32 *PFNIEMAIMPLBINROU32;
2064	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINROU64,(uint64_t const pu64Dst, uint64_t u64Src, uint32_t pEFlags));
2065	typedef FNIEMAIMPLBINROU64 *PFNIEMAIMPLBINROU64;
2066
2067	/** @name Compare operations (thrown in with the binary ops).
2068	* @{ */
2069	FNIEMAIMPLBINROU8 iemAImpl_cmp_u8;
2070	FNIEMAIMPLBINROU16 iemAImpl_cmp_u16;
2071	FNIEMAIMPLBINROU32 iemAImpl_cmp_u32;
2072	FNIEMAIMPLBINROU64 iemAImpl_cmp_u64;
2073	/** @} */
2074
2075	/** @name Test operations (thrown in with the binary ops).
2076	* @{ */
2077	FNIEMAIMPLBINROU8 iemAImpl_test_u8;
2078	FNIEMAIMPLBINROU16 iemAImpl_test_u16;
2079	FNIEMAIMPLBINROU32 iemAImpl_test_u32;
2080	FNIEMAIMPLBINROU64 iemAImpl_test_u64;
2081	/** @} */
2082
2083	/** @name Bit operations operations (thrown in with the binary ops).
2084	* @{ */
2085	FNIEMAIMPLBINROU16 iemAImpl_bt_u16;
2086	FNIEMAIMPLBINROU32 iemAImpl_bt_u32;
2087	FNIEMAIMPLBINROU64 iemAImpl_bt_u64;
2088	FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
2089	FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
2090	FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
2091	FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
2092	FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
2093	FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
2094	FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
2095	FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
2096	FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
2097	/** @} */
2098
2099	/** @name Arithmetic three operand operations on double words (binary).
2100	* @{ */
2101	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32, (uint32_t pu32Dst, uint32_t u32Src1, uint32_t u32Src2, uint32_t pEFlags));
2102	typedef FNIEMAIMPLBINVEXU32 *PFNIEMAIMPLBINVEXU32;
2103	FNIEMAIMPLBINVEXU32 iemAImpl_andn_u32, iemAImpl_andn_u32_fallback;
2104	FNIEMAIMPLBINVEXU32 iemAImpl_bextr_u32, iemAImpl_bextr_u32_fallback;
2105	FNIEMAIMPLBINVEXU32 iemAImpl_bzhi_u32, iemAImpl_bzhi_u32_fallback;
2106	/** @} */
2107
2108	/** @name Arithmetic three operand operations on quad words (binary).
2109	* @{ */
2110	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64, (uint64_t pu64Dst, uint64_t u64Src1, uint64_t u64Src2, uint32_t pEFlags));
2111	typedef FNIEMAIMPLBINVEXU64 *PFNIEMAIMPLBINVEXU64;
2112	FNIEMAIMPLBINVEXU64 iemAImpl_andn_u64, iemAImpl_andn_u64_fallback;
2113	FNIEMAIMPLBINVEXU64 iemAImpl_bextr_u64, iemAImpl_bextr_u64_fallback;
2114	FNIEMAIMPLBINVEXU64 iemAImpl_bzhi_u64, iemAImpl_bzhi_u64_fallback;
2115	/** @} */
2116
2117	/** @name Arithmetic three operand operations on double words w/o EFLAGS (binary).
2118	* @{ */
2119	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32NOEFL, (uint32_t *pu32Dst, uint32_t u32Src1, uint32_t u32Src2));
2120	typedef FNIEMAIMPLBINVEXU32NOEFL *PFNIEMAIMPLBINVEXU32NOEFL;
2121	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pdep_u32, iemAImpl_pdep_u32_fallback;
2122	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pext_u32, iemAImpl_pext_u32_fallback;
2123	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_sarx_u32, iemAImpl_sarx_u32_fallback;
2124	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shlx_u32, iemAImpl_shlx_u32_fallback;
2125	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shrx_u32, iemAImpl_shrx_u32_fallback;
2126	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_rorx_u32;
2127	/** @} */
2128
2129	/** @name Arithmetic three operand operations on quad words w/o EFLAGS (binary).
2130	* @{ */
2131	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64NOEFL, (uint64_t *pu64Dst, uint64_t u64Src1, uint64_t u64Src2));
2132	typedef FNIEMAIMPLBINVEXU64NOEFL *PFNIEMAIMPLBINVEXU64NOEFL;
2133	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pdep_u64, iemAImpl_pdep_u64_fallback;
2134	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pext_u64, iemAImpl_pext_u64_fallback;
2135	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_sarx_u64, iemAImpl_sarx_u64_fallback;
2136	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shlx_u64, iemAImpl_shlx_u64_fallback;
2137	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shrx_u64, iemAImpl_shrx_u64_fallback;
2138	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_rorx_u64;
2139	/** @} */
2140
2141	/** @name MULX 32-bit and 64-bit.
2142	* @{ */
2143	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU32, (uint32_t puDst1, uint32_t puDst2, uint32_t uSrc1, uint32_t uSrc2));
2144	typedef FNIEMAIMPLMULXVEXU32 *PFNIEMAIMPLMULXVEXU32;
2145	FNIEMAIMPLMULXVEXU32 iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback;
2146
2147	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU64, (uint64_t puDst1, uint64_t puDst2, uint64_t uSrc1, uint64_t uSrc2));
2148	typedef FNIEMAIMPLMULXVEXU64 *PFNIEMAIMPLMULXVEXU64;
2149	FNIEMAIMPLMULXVEXU64 iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback;
2150	/** @} */
2151
2152
2153	/** @name Exchange memory with register operations.
2154	* @{ */
2155	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_locked, (uint8_t pu8Mem, uint8_t pu8Reg));
2156	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_locked,(uint16_t pu16Mem, uint16_t pu16Reg));
2157	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_locked,(uint32_t pu32Mem, uint32_t pu32Reg));
2158	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_locked,(uint64_t pu64Mem, uint64_t pu64Reg));
2159	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_unlocked, (uint8_t pu8Mem, uint8_t pu8Reg));
2160	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_unlocked,(uint16_t pu16Mem, uint16_t pu16Reg));
2161	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_unlocked,(uint32_t pu32Mem, uint32_t pu32Reg));
2162	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_unlocked,(uint64_t pu64Mem, uint64_t pu64Reg));
2163	/** @} */
2164
2165	/** @name Exchange and add operations.
2166	* @{ */
2167	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
2168	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
2169	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
2170	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
2171	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
2172	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
2173	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
2174	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
2175	/** @} */
2176
2177	/** @name Compare and exchange.
2178	* @{ */
2179	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
2180	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
2181	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
2182	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
2183	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
2184	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
2185	#if ARCH_BITS == 32
2186	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
2187	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
2188	#else
2189	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
2190	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
2191	#endif
2192	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
2193	uint32_t *pEFlags));
2194	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
2195	uint32_t *pEFlags));
2196	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
2197	uint32_t *pEFlags));
2198	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
2199	uint32_t *pEFlags));
2200	#ifndef RT_ARCH_ARM64
2201	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
2202	PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
2203	#endif
2204	/** @} */
2205
2206	/** @name Memory ordering
2207	* @{ */
2208	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
2209	typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
2210	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
2211	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
2212	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
2213	#ifndef RT_ARCH_ARM64
2214	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
2215	#endif
2216	/** @} */
2217
2218	/** @name Double precision shifts
2219	* @{ */
2220	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t pEFlags));
2221	typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
2222	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t pEFlags));
2223	typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
2224	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t pEFlags));
2225	typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
2226	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16, iemAImpl_shld_u16_amd, iemAImpl_shld_u16_intel;
2227	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32, iemAImpl_shld_u32_amd, iemAImpl_shld_u32_intel;
2228	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64, iemAImpl_shld_u64_amd, iemAImpl_shld_u64_intel;
2229	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16, iemAImpl_shrd_u16_amd, iemAImpl_shrd_u16_intel;
2230	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32, iemAImpl_shrd_u32_amd, iemAImpl_shrd_u32_intel;
2231	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64, iemAImpl_shrd_u64_amd, iemAImpl_shrd_u64_intel;
2232	/** @} */
2233
2234
2235	/** @name Bit search operations (thrown in with the binary ops).
2236	* @{ */
2237	FNIEMAIMPLBINU16 iemAImpl_bsf_u16, iemAImpl_bsf_u16_amd, iemAImpl_bsf_u16_intel;
2238	FNIEMAIMPLBINU32 iemAImpl_bsf_u32, iemAImpl_bsf_u32_amd, iemAImpl_bsf_u32_intel;
2239	FNIEMAIMPLBINU64 iemAImpl_bsf_u64, iemAImpl_bsf_u64_amd, iemAImpl_bsf_u64_intel;
2240	FNIEMAIMPLBINU16 iemAImpl_bsr_u16, iemAImpl_bsr_u16_amd, iemAImpl_bsr_u16_intel;
2241	FNIEMAIMPLBINU32 iemAImpl_bsr_u32, iemAImpl_bsr_u32_amd, iemAImpl_bsr_u32_intel;
2242	FNIEMAIMPLBINU64 iemAImpl_bsr_u64, iemAImpl_bsr_u64_amd, iemAImpl_bsr_u64_intel;
2243	FNIEMAIMPLBINU16 iemAImpl_lzcnt_u16, iemAImpl_lzcnt_u16_amd, iemAImpl_lzcnt_u16_intel;
2244	FNIEMAIMPLBINU32 iemAImpl_lzcnt_u32, iemAImpl_lzcnt_u32_amd, iemAImpl_lzcnt_u32_intel;
2245	FNIEMAIMPLBINU64 iemAImpl_lzcnt_u64, iemAImpl_lzcnt_u64_amd, iemAImpl_lzcnt_u64_intel;
2246	FNIEMAIMPLBINU16 iemAImpl_tzcnt_u16, iemAImpl_tzcnt_u16_amd, iemAImpl_tzcnt_u16_intel;
2247	FNIEMAIMPLBINU32 iemAImpl_tzcnt_u32, iemAImpl_tzcnt_u32_amd, iemAImpl_tzcnt_u32_intel;
2248	FNIEMAIMPLBINU64 iemAImpl_tzcnt_u64, iemAImpl_tzcnt_u64_amd, iemAImpl_tzcnt_u64_intel;
2249	FNIEMAIMPLBINU16 iemAImpl_popcnt_u16, iemAImpl_popcnt_u16_fallback;
2250	FNIEMAIMPLBINU32 iemAImpl_popcnt_u32, iemAImpl_popcnt_u32_fallback;
2251	FNIEMAIMPLBINU64 iemAImpl_popcnt_u64, iemAImpl_popcnt_u64_fallback;
2252	/** @} */
2253
2254	/** @name Signed multiplication operations (thrown in with the binary ops).
2255	* @{ */
2256	FNIEMAIMPLBINU16 iemAImpl_imul_two_u16, iemAImpl_imul_two_u16_amd, iemAImpl_imul_two_u16_intel;
2257	FNIEMAIMPLBINU32 iemAImpl_imul_two_u32, iemAImpl_imul_two_u32_amd, iemAImpl_imul_two_u32_intel;
2258	FNIEMAIMPLBINU64 iemAImpl_imul_two_u64, iemAImpl_imul_two_u64_amd, iemAImpl_imul_two_u64_intel;
2259	/** @} */
2260
2261	/** @name Arithmetic assignment operations on bytes (unary).
2262	* @{ */
2263	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t pu8Dst, uint32_t pEFlags));
2264	typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
2265	FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
2266	FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
2267	FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
2268	FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
2269	/** @} */
2270
2271	/** @name Arithmetic assignment operations on words (unary).
2272	* @{ */
2273	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t pu16Dst, uint32_t pEFlags));
2274	typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
2275	FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
2276	FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
2277	FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
2278	FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
2279	/** @} */
2280
2281	/** @name Arithmetic assignment operations on double words (unary).
2282	* @{ */
2283	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t pu32Dst, uint32_t pEFlags));
2284	typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
2285	FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
2286	FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
2287	FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
2288	FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
2289	/** @} */
2290
2291	/** @name Arithmetic assignment operations on quad words (unary).
2292	* @{ */
2293	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t pu64Dst, uint32_t pEFlags));
2294	typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
2295	FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
2296	FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
2297	FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
2298	FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
2299	/** @} */
2300
2301
2302	/** @name Shift operations on bytes (Group 2).
2303	* @{ */
2304	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU8,(uint8_t pu8Dst, uint8_t cShift, uint32_t pEFlags));
2305	typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
2306	FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8, iemAImpl_rol_u8_amd, iemAImpl_rol_u8_intel;
2307	FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8, iemAImpl_ror_u8_amd, iemAImpl_ror_u8_intel;
2308	FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8, iemAImpl_rcl_u8_amd, iemAImpl_rcl_u8_intel;
2309	FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8, iemAImpl_rcr_u8_amd, iemAImpl_rcr_u8_intel;
2310	FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8, iemAImpl_shl_u8_amd, iemAImpl_shl_u8_intel;
2311	FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8, iemAImpl_shr_u8_amd, iemAImpl_shr_u8_intel;
2312	FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8, iemAImpl_sar_u8_amd, iemAImpl_sar_u8_intel;
2313	/** @} */
2314
2315	/** @name Shift operations on words (Group 2).
2316	* @{ */
2317	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU16,(uint16_t pu16Dst, uint8_t cShift, uint32_t pEFlags));
2318	typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
2319	FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16, iemAImpl_rol_u16_amd, iemAImpl_rol_u16_intel;
2320	FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16, iemAImpl_ror_u16_amd, iemAImpl_ror_u16_intel;
2321	FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16, iemAImpl_rcl_u16_amd, iemAImpl_rcl_u16_intel;
2322	FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16, iemAImpl_rcr_u16_amd, iemAImpl_rcr_u16_intel;
2323	FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16, iemAImpl_shl_u16_amd, iemAImpl_shl_u16_intel;
2324	FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16, iemAImpl_shr_u16_amd, iemAImpl_shr_u16_intel;
2325	FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16, iemAImpl_sar_u16_amd, iemAImpl_sar_u16_intel;
2326	/** @} */
2327
2328	/** @name Shift operations on double words (Group 2).
2329	* @{ */
2330	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU32,(uint32_t pu32Dst, uint8_t cShift, uint32_t pEFlags));
2331	typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
2332	FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32, iemAImpl_rol_u32_amd, iemAImpl_rol_u32_intel;
2333	FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32, iemAImpl_ror_u32_amd, iemAImpl_ror_u32_intel;
2334	FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32, iemAImpl_rcl_u32_amd, iemAImpl_rcl_u32_intel;
2335	FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32, iemAImpl_rcr_u32_amd, iemAImpl_rcr_u32_intel;
2336	FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32, iemAImpl_shl_u32_amd, iemAImpl_shl_u32_intel;
2337	FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32, iemAImpl_shr_u32_amd, iemAImpl_shr_u32_intel;
2338	FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32, iemAImpl_sar_u32_amd, iemAImpl_sar_u32_intel;
2339	/** @} */
2340
2341	/** @name Shift operations on words (Group 2).
2342	* @{ */
2343	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU64,(uint64_t pu64Dst, uint8_t cShift, uint32_t pEFlags));
2344	typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
2345	FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64, iemAImpl_rol_u64_amd, iemAImpl_rol_u64_intel;
2346	FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64, iemAImpl_ror_u64_amd, iemAImpl_ror_u64_intel;
2347	FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64, iemAImpl_rcl_u64_amd, iemAImpl_rcl_u64_intel;
2348	FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64, iemAImpl_rcr_u64_amd, iemAImpl_rcr_u64_intel;
2349	FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64, iemAImpl_shl_u64_amd, iemAImpl_shl_u64_intel;
2350	FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64, iemAImpl_shr_u64_amd, iemAImpl_shr_u64_intel;
2351	FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64, iemAImpl_sar_u64_amd, iemAImpl_sar_u64_intel;
2352	/** @} */
2353
2354	/** @name Multiplication and division operations.
2355	* @{ */
2356	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t pu16AX, uint8_t u8FactorDivisor, uint32_t pEFlags));
2357	typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
2358	FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_mul_u8_amd, iemAImpl_mul_u8_intel;
2359	FNIEMAIMPLMULDIVU8 iemAImpl_imul_u8, iemAImpl_imul_u8_amd, iemAImpl_imul_u8_intel;
2360	FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_div_u8_amd, iemAImpl_div_u8_intel;
2361	FNIEMAIMPLMULDIVU8 iemAImpl_idiv_u8, iemAImpl_idiv_u8_amd, iemAImpl_idiv_u8_intel;
2362
2363	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t pu16AX, uint16_t pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
2364	typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
2365	FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_mul_u16_amd, iemAImpl_mul_u16_intel;
2366	FNIEMAIMPLMULDIVU16 iemAImpl_imul_u16, iemAImpl_imul_u16_amd, iemAImpl_imul_u16_intel;
2367	FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_div_u16_amd, iemAImpl_div_u16_intel;
2368	FNIEMAIMPLMULDIVU16 iemAImpl_idiv_u16, iemAImpl_idiv_u16_amd, iemAImpl_idiv_u16_intel;
2369
2370	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t pu32EAX, uint32_t pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
2371	typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
2372	FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_mul_u32_amd, iemAImpl_mul_u32_intel;
2373	FNIEMAIMPLMULDIVU32 iemAImpl_imul_u32, iemAImpl_imul_u32_amd, iemAImpl_imul_u32_intel;
2374	FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_div_u32_amd, iemAImpl_div_u32_intel;
2375	FNIEMAIMPLMULDIVU32 iemAImpl_idiv_u32, iemAImpl_idiv_u32_amd, iemAImpl_idiv_u32_intel;
2376
2377	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t pu64RAX, uint64_t pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
2378	typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
2379	FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_mul_u64_amd, iemAImpl_mul_u64_intel;
2380	FNIEMAIMPLMULDIVU64 iemAImpl_imul_u64, iemAImpl_imul_u64_amd, iemAImpl_imul_u64_intel;
2381	FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_div_u64_amd, iemAImpl_div_u64_intel;
2382	FNIEMAIMPLMULDIVU64 iemAImpl_idiv_u64, iemAImpl_idiv_u64_amd, iemAImpl_idiv_u64_intel;
2383	/** @} */
2384
2385	/** @name Byte Swap.
2386	* @{ */
2387	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t pu32Dst)); / Yes, 32-bit register access. */
2388	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
2389	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
2390	/** @} */
2391
2392	/** @name Misc.
2393	* @{ */
2394	FNIEMAIMPLBINU16 iemAImpl_arpl;
2395	/** @} */
2396
2397	/** @name RDRAND and RDSEED
2398	* @{ */
2399	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU16,(uint16_t puDst, uint32_t pEFlags));
2400	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU32,(uint32_t puDst, uint32_t pEFlags));
2401	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU64,(uint64_t puDst, uint32_t pEFlags));
2402	typedef FNIEMAIMPLRDRANDSEEDU16 *FNIEMAIMPLPRDRANDSEEDU16;
2403	typedef FNIEMAIMPLRDRANDSEEDU32 *FNIEMAIMPLPRDRANDSEEDU32;
2404	typedef FNIEMAIMPLRDRANDSEEDU64 *FNIEMAIMPLPRDRANDSEEDU64;
2405
2406	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdrand_u16, iemAImpl_rdrand_u16_fallback;
2407	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdrand_u32, iemAImpl_rdrand_u32_fallback;
2408	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdrand_u64, iemAImpl_rdrand_u64_fallback;
2409	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdseed_u16, iemAImpl_rdseed_u16_fallback;
2410	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdseed_u32, iemAImpl_rdseed_u32_fallback;
2411	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdseed_u64, iemAImpl_rdseed_u64_fallback;
2412	/** @} */
2413
2414	/** @name ADOX and ADCX
2415	* @{ */
2416	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLADXU32,(uint32_t puDst, uint32_t pfEFlags, uint32_t uSrc));
2417	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLADXU64,(uint64_t puDst, uint32_t pfEFlags, uint64_t uSrc));
2418	typedef FNIEMAIMPLADXU32 *PFNIEMAIMPLADXU32;
2419	typedef FNIEMAIMPLADXU64 *PFNIEMAIMPLADXU64;
2420
2421	FNIEMAIMPLADXU32 iemAImpl_adcx_u32, iemAImpl_adcx_u32_fallback;
2422	FNIEMAIMPLADXU64 iemAImpl_adcx_u64, iemAImpl_adcx_u64_fallback;
2423	FNIEMAIMPLADXU32 iemAImpl_adox_u32, iemAImpl_adox_u32_fallback;
2424	FNIEMAIMPLADXU64 iemAImpl_adox_u64, iemAImpl_adox_u64_fallback;
2425	/** @} */
2426
2427	/** @name FPU operations taking a 32-bit float argument
2428	* @{ */
2429	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2430	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
2431	typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
2432
2433	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2434	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
2435	typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
2436
2437	FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
2438	FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
2439	FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
2440	FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
2441	FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
2442	FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
2443	FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
2444
2445	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
2446	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2447	PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
2448	/** @} */
2449
2450	/** @name FPU operations taking a 64-bit float argument
2451	* @{ */
2452	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2453	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
2454	typedef FNIEMAIMPLFPUR64FSW *PFNIEMAIMPLFPUR64FSW;
2455
2456	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2457	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
2458	typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
2459
2460	FNIEMAIMPLFPUR64FSW iemAImpl_fcom_r80_by_r64;
2461	FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
2462	FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
2463	FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
2464	FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
2465	FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
2466	FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
2467
2468	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
2469	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2470	PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
2471	/** @} */
2472
2473	/** @name FPU operations taking a 80-bit float argument
2474	* @{ */
2475	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2476	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
2477	typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
2478	FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
2479	FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
2480	FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
2481	FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
2482	FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
2483	FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
2484	FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
2485	FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
2486	FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
2487
2488	FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80, iemAImpl_fpatan_r80_by_r80_amd, iemAImpl_fpatan_r80_by_r80_intel;
2489	FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80, iemAImpl_fyl2x_r80_by_r80_amd, iemAImpl_fyl2x_r80_by_r80_intel;
2490	FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80, iemAImpl_fyl2xp1_r80_by_r80_amd, iemAImpl_fyl2xp1_r80_by_r80_intel;
2491
2492	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2493	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
2494	typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
2495	FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
2496	FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
2497
2498	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
2499	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
2500	typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
2501	FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
2502	FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
2503
2504	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
2505	typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
2506	FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
2507	FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
2508	FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80, iemAImpl_f2xm1_r80_amd, iemAImpl_f2xm1_r80_intel;
2509	FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
2510	FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
2511	FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80, iemAImpl_fsin_r80_amd, iemAImpl_fsin_r80_intel;
2512	FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80, iemAImpl_fcos_r80_amd, iemAImpl_fcos_r80_intel;
2513
2514	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
2515	typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
2516	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
2517	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
2518
2519	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
2520	typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
2521	FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
2522	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
2523	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
2524	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
2525	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
2526	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
2527	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
2528
2529	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
2530	PCRTFLOAT80U pr80Val));
2531	typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
2532	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80, iemAImpl_fptan_r80_r80_amd, iemAImpl_fptan_r80_r80_intel;
2533	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
2534	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80, iemAImpl_fsincos_r80_r80_amd, iemAImpl_fsincos_r80_r80_intel;
2535
2536	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
2537	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2538	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
2539
2540	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_d80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTPBCD80U pd80Val));
2541	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_d80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2542	PRTPBCD80U pd80Dst, PCRTFLOAT80U pr80Src));
2543
2544	/** @} */
2545
2546	/** @name FPU operations taking a 16-bit signed integer argument
2547	* @{ */
2548	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2549	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
2550	typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
2551	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI16,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
2552	int16_t *pi16Dst, PCRTFLOAT80U pr80Src));
2553	typedef FNIEMAIMPLFPUSTR80TOI16 *PFNIEMAIMPLFPUSTR80TOI16;
2554
2555	FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
2556	FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
2557	FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
2558	FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
2559	FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
2560	FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
2561
2562	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2563	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
2564	typedef FNIEMAIMPLFPUI16FSW *PFNIEMAIMPLFPUI16FSW;
2565	FNIEMAIMPLFPUI16FSW iemAImpl_ficom_r80_by_i16;
2566
2567	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
2568	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fist_r80_to_i16;
2569	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fistt_r80_to_i16, iemAImpl_fistt_r80_to_i16_amd, iemAImpl_fistt_r80_to_i16_intel;
2570	/** @} */
2571
2572	/** @name FPU operations taking a 32-bit signed integer argument
2573	* @{ */
2574	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2575	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
2576	typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
2577	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI32,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
2578	int32_t *pi32Dst, PCRTFLOAT80U pr80Src));
2579	typedef FNIEMAIMPLFPUSTR80TOI32 *PFNIEMAIMPLFPUSTR80TOI32;
2580
2581	FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
2582	FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
2583	FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
2584	FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
2585	FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
2586	FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
2587
2588	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2589	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
2590	typedef FNIEMAIMPLFPUI32FSW *PFNIEMAIMPLFPUI32FSW;
2591	FNIEMAIMPLFPUI32FSW iemAImpl_ficom_r80_by_i32;
2592
2593	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
2594	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fist_r80_to_i32;
2595	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fistt_r80_to_i32;
2596	/** @} */
2597
2598	/** @name FPU operations taking a 64-bit signed integer argument
2599	* @{ */
2600	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI64,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
2601	int64_t *pi64Dst, PCRTFLOAT80U pr80Src));
2602	typedef FNIEMAIMPLFPUSTR80TOI64 *PFNIEMAIMPLFPUSTR80TOI64;
2603
2604	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
2605	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fist_r80_to_i64;
2606	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fistt_r80_to_i64;
2607	/** @} */
2608
2609
2610	/** Temporary type representing a 256-bit vector register. */
2611	typedef struct { uint64_t au64[4]; } IEMVMM256;
2612	/** Temporary type pointing to a 256-bit vector register. */
2613	typedef IEMVMM256 *PIEMVMM256;
2614	/** Temporary type pointing to a const 256-bit vector register. */
2615	typedef IEMVMM256 *PCIEMVMM256;
2616
2617
2618	/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
2619	* @{ */
2620	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t puDst, uint64_t const puSrc));
2621	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
2622	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U128,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
2623	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
2624	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U128,(PX86XSAVEAREA pExtState, PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
2625	typedef FNIEMAIMPLMEDIAF3U128 *PFNIEMAIMPLMEDIAF3U128;
2626	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U256,(PX86XSAVEAREA pExtState, PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
2627	typedef FNIEMAIMPLMEDIAF3U256 *PFNIEMAIMPLMEDIAF3U256;
2628	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U64,(uint64_t puDst, uint64_t const puSrc));
2629	typedef FNIEMAIMPLMEDIAOPTF2U64 *PFNIEMAIMPLMEDIAOPTF2U64;
2630	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128,(PRTUINT128U puDst, PCRTUINT128U puSrc));
2631	typedef FNIEMAIMPLMEDIAOPTF2U128 *PFNIEMAIMPLMEDIAOPTF2U128;
2632	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
2633	typedef FNIEMAIMPLMEDIAOPTF3U128 *PFNIEMAIMPLMEDIAOPTF3U128;
2634	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
2635	typedef FNIEMAIMPLMEDIAOPTF3U256 *PFNIEMAIMPLMEDIAOPTF3U256;
2636	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256,(PRTUINT256U puDst, PCRTUINT256U puSrc));
2637	typedef FNIEMAIMPLMEDIAOPTF2U256 *PFNIEMAIMPLMEDIAOPTF2U256;
2638	FNIEMAIMPLMEDIAF2U64 iemAImpl_pshufb_u64, iemAImpl_pshufb_u64_fallback;
2639	FNIEMAIMPLMEDIAF2U64 iemAImpl_pand_u64, iemAImpl_pandn_u64, iemAImpl_por_u64, iemAImpl_pxor_u64;
2640	FNIEMAIMPLMEDIAF2U64 iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
2641	FNIEMAIMPLMEDIAF2U64 iemAImpl_pcmpgtb_u64, iemAImpl_pcmpgtw_u64, iemAImpl_pcmpgtd_u64;
2642	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddb_u64, iemAImpl_paddsb_u64, iemAImpl_paddusb_u64;
2643	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddw_u64, iemAImpl_paddsw_u64, iemAImpl_paddusw_u64;
2644	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddd_u64;
2645	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddq_u64;
2646	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubb_u64, iemAImpl_psubsb_u64, iemAImpl_psubusb_u64;
2647	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubw_u64, iemAImpl_psubsw_u64, iemAImpl_psubusw_u64;
2648	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubd_u64;
2649	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubq_u64;
2650	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmaddwd_u64;
2651	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmullw_u64, iemAImpl_pmulhw_u64;
2652	FNIEMAIMPLMEDIAF2U64 iemAImpl_pminub_u64, iemAImpl_pmaxub_u64;
2653	FNIEMAIMPLMEDIAF2U64 iemAImpl_pminsw_u64, iemAImpl_pmaxsw_u64;
2654	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsb_u64, iemAImpl_pabsb_u64_fallback;
2655	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsw_u64, iemAImpl_pabsw_u64_fallback;
2656	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsd_u64, iemAImpl_pabsd_u64_fallback;
2657	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignb_u64, iemAImpl_psignb_u64_fallback;
2658	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignw_u64, iemAImpl_psignw_u64_fallback;
2659	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignd_u64, iemAImpl_psignd_u64_fallback;
2660	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddw_u64, iemAImpl_phaddw_u64_fallback;
2661	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddd_u64, iemAImpl_phaddd_u64_fallback;
2662	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubw_u64, iemAImpl_phsubw_u64_fallback;
2663	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubd_u64, iemAImpl_phsubd_u64_fallback;
2664	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddsw_u64, iemAImpl_phaddsw_u64_fallback;
2665	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubsw_u64, iemAImpl_phsubsw_u64_fallback;
2666	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmaddubsw_u64, iemAImpl_pmaddubsw_u64_fallback;
2667	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmulhrsw_u64, iemAImpl_pmulhrsw_u64_fallback;
2668	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmuludq_u64;
2669	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllw_u64, iemAImpl_psrlw_u64, iemAImpl_psraw_u64;
2670	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pslld_u64, iemAImpl_psrld_u64, iemAImpl_psrad_u64;
2671	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllq_u64, iemAImpl_psrlq_u64;
2672	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packsswb_u64, iemAImpl_packuswb_u64;
2673	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packssdw_u64;
2674	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhuw_u64;
2675	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pavgb_u64, iemAImpl_pavgw_u64;
2676	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psadbw_u64;
2677
2678	FNIEMAIMPLMEDIAF2U128 iemAImpl_pshufb_u128, iemAImpl_pshufb_u128_fallback;
2679	FNIEMAIMPLMEDIAF2U128 iemAImpl_pand_u128, iemAImpl_pandn_u128, iemAImpl_por_u128, iemAImpl_pxor_u128;
2680	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
2681	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpeqq_u128, iemAImpl_pcmpeqq_u128_fallback;
2682	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpgtb_u128, iemAImpl_pcmpgtw_u128, iemAImpl_pcmpgtd_u128;
2683	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpgtq_u128, iemAImpl_pcmpgtq_u128_fallback;
2684	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddb_u128, iemAImpl_paddsb_u128, iemAImpl_paddusb_u128;
2685	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddw_u128, iemAImpl_paddsw_u128, iemAImpl_paddusw_u128;
2686	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddd_u128;
2687	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddq_u128;
2688	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubb_u128, iemAImpl_psubsb_u128, iemAImpl_psubusb_u128;
2689	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubw_u128, iemAImpl_psubsw_u128, iemAImpl_psubusw_u128;
2690	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubd_u128;
2691	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubq_u128;
2692	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmullw_u128, iemAImpl_pmullw_u128_fallback;
2693	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulhw_u128;
2694	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulld_u128, iemAImpl_pmulld_u128_fallback;
2695	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaddwd_u128;
2696	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminub_u128;
2697	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminud_u128, iemAImpl_pminud_u128_fallback;
2698	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminuw_u128, iemAImpl_pminuw_u128_fallback;
2699	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsb_u128, iemAImpl_pminsb_u128_fallback;
2700	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsd_u128, iemAImpl_pminsd_u128_fallback;
2701	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsw_u128, iemAImpl_pminsw_u128_fallback;
2702	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxub_u128;
2703	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxud_u128, iemAImpl_pmaxud_u128_fallback;
2704	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxuw_u128, iemAImpl_pmaxuw_u128_fallback;
2705	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsb_u128, iemAImpl_pmaxsb_u128_fallback;
2706	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsw_u128;
2707	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsd_u128, iemAImpl_pmaxsd_u128_fallback;
2708	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsb_u128, iemAImpl_pabsb_u128_fallback;
2709	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsw_u128, iemAImpl_pabsw_u128_fallback;
2710	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsd_u128, iemAImpl_pabsd_u128_fallback;
2711	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignb_u128, iemAImpl_psignb_u128_fallback;
2712	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignw_u128, iemAImpl_psignw_u128_fallback;
2713	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignd_u128, iemAImpl_psignd_u128_fallback;
2714	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddw_u128, iemAImpl_phaddw_u128_fallback;
2715	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddd_u128, iemAImpl_phaddd_u128_fallback;
2716	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubw_u128, iemAImpl_phsubw_u128_fallback;
2717	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubd_u128, iemAImpl_phsubd_u128_fallback;
2718	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddsw_u128, iemAImpl_phaddsw_u128_fallback;
2719	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubsw_u128, iemAImpl_phsubsw_u128_fallback;
2720	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaddubsw_u128, iemAImpl_pmaddubsw_u128_fallback;
2721	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulhrsw_u128, iemAImpl_pmulhrsw_u128_fallback;
2722	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmuludq_u128;
2723	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packsswb_u128, iemAImpl_packuswb_u128;
2724	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packssdw_u128, iemAImpl_packusdw_u128;
2725	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllw_u128, iemAImpl_psrlw_u128, iemAImpl_psraw_u128;
2726	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pslld_u128, iemAImpl_psrld_u128, iemAImpl_psrad_u128;
2727	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllq_u128, iemAImpl_psrlq_u128;
2728	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhuw_u128;
2729	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pavgb_u128, iemAImpl_pavgw_u128;
2730	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psadbw_u128;
2731	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuldq_u128, iemAImpl_pmuldq_u128_fallback;
2732	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpcklps_u128, iemAImpl_unpcklpd_u128;
2733	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpckhps_u128, iemAImpl_unpckhpd_u128;
2734	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phminposuw_u128, iemAImpl_phminposuw_u128_fallback;
2735
2736	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpshufb_u128, iemAImpl_vpshufb_u128_fallback;
2737	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpand_u128, iemAImpl_vpand_u128_fallback;
2738	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpandn_u128, iemAImpl_vpandn_u128_fallback;
2739	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpor_u128, iemAImpl_vpor_u128_fallback;
2740	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpxor_u128, iemAImpl_vpxor_u128_fallback;
2741	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqb_u128, iemAImpl_vpcmpeqb_u128_fallback;
2742	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqw_u128, iemAImpl_vpcmpeqw_u128_fallback;
2743	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqd_u128, iemAImpl_vpcmpeqd_u128_fallback;
2744	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqq_u128, iemAImpl_vpcmpeqq_u128_fallback;
2745	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtb_u128, iemAImpl_vpcmpgtb_u128_fallback;
2746	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtw_u128, iemAImpl_vpcmpgtw_u128_fallback;
2747	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtd_u128, iemAImpl_vpcmpgtd_u128_fallback;
2748	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtq_u128, iemAImpl_vpcmpgtq_u128_fallback;
2749	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddb_u128, iemAImpl_vpaddb_u128_fallback;
2750	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddw_u128, iemAImpl_vpaddw_u128_fallback;
2751	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddd_u128, iemAImpl_vpaddd_u128_fallback;
2752	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddq_u128, iemAImpl_vpaddq_u128_fallback;
2753	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubb_u128, iemAImpl_vpsubb_u128_fallback;
2754	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubw_u128, iemAImpl_vpsubw_u128_fallback;
2755	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubd_u128, iemAImpl_vpsubd_u128_fallback;
2756	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubq_u128, iemAImpl_vpsubq_u128_fallback;
2757	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminub_u128, iemAImpl_vpminub_u128_fallback;
2758	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminuw_u128, iemAImpl_vpminuw_u128_fallback;
2759	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminud_u128, iemAImpl_vpminud_u128_fallback;
2760	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsb_u128, iemAImpl_vpminsb_u128_fallback;
2761	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsw_u128, iemAImpl_vpminsw_u128_fallback;
2762	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsd_u128, iemAImpl_vpminsd_u128_fallback;
2763	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxub_u128, iemAImpl_vpmaxub_u128_fallback;
2764	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxuw_u128, iemAImpl_vpmaxuw_u128_fallback;
2765	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxud_u128, iemAImpl_vpmaxud_u128_fallback;
2766	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsb_u128, iemAImpl_vpmaxsb_u128_fallback;
2767	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsw_u128, iemAImpl_vpmaxsw_u128_fallback;
2768	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsd_u128, iemAImpl_vpmaxsd_u128_fallback;
2769	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpacksswb_u128, iemAImpl_vpacksswb_u128_fallback;
2770	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackssdw_u128, iemAImpl_vpackssdw_u128_fallback;
2771	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackuswb_u128, iemAImpl_vpackuswb_u128_fallback;
2772	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackusdw_u128, iemAImpl_vpackusdw_u128_fallback;
2773	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmullw_u128, iemAImpl_vpmullw_u128_fallback;
2774	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulld_u128, iemAImpl_vpmulld_u128_fallback;
2775	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhw_u128, iemAImpl_vpmulhw_u128_fallback;
2776	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhuw_u128, iemAImpl_vpmulhuw_u128_fallback;
2777	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgb_u128, iemAImpl_vpavgb_u128_fallback;
2778	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgw_u128, iemAImpl_vpavgw_u128_fallback;
2779	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignb_u128, iemAImpl_vpsignb_u128_fallback;
2780	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignw_u128, iemAImpl_vpsignw_u128_fallback;
2781	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignd_u128, iemAImpl_vpsignd_u128_fallback;
2782	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddw_u128, iemAImpl_vphaddw_u128_fallback;
2783	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddd_u128, iemAImpl_vphaddd_u128_fallback;
2784	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubw_u128, iemAImpl_vphsubw_u128_fallback;
2785	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubd_u128, iemAImpl_vphsubd_u128_fallback;
2786	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddsw_u128, iemAImpl_vphaddsw_u128_fallback;
2787	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubsw_u128, iemAImpl_vphsubsw_u128_fallback;
2788	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddubsw_u128, iemAImpl_vpmaddubsw_u128_fallback;
2789	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhrsw_u128, iemAImpl_vpmulhrsw_u128_fallback;
2790	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsadbw_u128, iemAImpl_vpsadbw_u128_fallback;
2791	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuldq_u128, iemAImpl_vpmuldq_u128_fallback;
2792	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuludq_u128, iemAImpl_vpmuludq_u128_fallback;
2793	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsb_u128, iemAImpl_vpsubsb_u128_fallback;
2794	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsw_u128, iemAImpl_vpsubsw_u128_fallback;
2795	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusb_u128, iemAImpl_vpsubusb_u128_fallback;
2796	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusw_u128, iemAImpl_vpsubusw_u128_fallback;
2797	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusb_u128, iemAImpl_vpaddusb_u128_fallback;
2798	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusw_u128, iemAImpl_vpaddusw_u128_fallback;
2799	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsb_u128, iemAImpl_vpaddsb_u128_fallback;
2800	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsw_u128, iemAImpl_vpaddsw_u128_fallback;
2801
2802	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsb_u128, iemAImpl_vpabsb_u128_fallback;
2803	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsw_u128, iemAImpl_vpabsd_u128_fallback;
2804	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsd_u128, iemAImpl_vpabsw_u128_fallback;
2805	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vphminposuw_u128, iemAImpl_vphminposuw_u128_fallback;
2806
2807	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpshufb_u256, iemAImpl_vpshufb_u256_fallback;
2808	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpand_u256, iemAImpl_vpand_u256_fallback;
2809	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpandn_u256, iemAImpl_vpandn_u256_fallback;
2810	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpor_u256, iemAImpl_vpor_u256_fallback;
2811	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpxor_u256, iemAImpl_vpxor_u256_fallback;
2812	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqb_u256, iemAImpl_vpcmpeqb_u256_fallback;
2813	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqw_u256, iemAImpl_vpcmpeqw_u256_fallback;
2814	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqd_u256, iemAImpl_vpcmpeqd_u256_fallback;
2815	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqq_u256, iemAImpl_vpcmpeqq_u256_fallback;
2816	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtb_u256, iemAImpl_vpcmpgtb_u256_fallback;
2817	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtw_u256, iemAImpl_vpcmpgtw_u256_fallback;
2818	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtd_u256, iemAImpl_vpcmpgtd_u256_fallback;
2819	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtq_u256, iemAImpl_vpcmpgtq_u256_fallback;
2820	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddb_u256, iemAImpl_vpaddb_u256_fallback;
2821	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddw_u256, iemAImpl_vpaddw_u256_fallback;
2822	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddd_u256, iemAImpl_vpaddd_u256_fallback;
2823	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddq_u256, iemAImpl_vpaddq_u256_fallback;
2824	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubb_u256, iemAImpl_vpsubb_u256_fallback;
2825	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubw_u256, iemAImpl_vpsubw_u256_fallback;
2826	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubd_u256, iemAImpl_vpsubd_u256_fallback;
2827	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubq_u256, iemAImpl_vpsubq_u256_fallback;
2828	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminub_u256, iemAImpl_vpminub_u256_fallback;
2829	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminuw_u256, iemAImpl_vpminuw_u256_fallback;
2830	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminud_u256, iemAImpl_vpminud_u256_fallback;
2831	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsb_u256, iemAImpl_vpminsb_u256_fallback;
2832	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsw_u256, iemAImpl_vpminsw_u256_fallback;
2833	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsd_u256, iemAImpl_vpminsd_u256_fallback;
2834	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxub_u256, iemAImpl_vpmaxub_u256_fallback;
2835	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxuw_u256, iemAImpl_vpmaxuw_u256_fallback;
2836	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxud_u256, iemAImpl_vpmaxud_u256_fallback;
2837	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsb_u256, iemAImpl_vpmaxsb_u256_fallback;
2838	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsw_u256, iemAImpl_vpmaxsw_u256_fallback;
2839	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsd_u256, iemAImpl_vpmaxsd_u256_fallback;
2840	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpacksswb_u256, iemAImpl_vpacksswb_u256_fallback;
2841	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackssdw_u256, iemAImpl_vpackssdw_u256_fallback;
2842	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackuswb_u256, iemAImpl_vpackuswb_u256_fallback;
2843	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackusdw_u256, iemAImpl_vpackusdw_u256_fallback;
2844	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmullw_u256, iemAImpl_vpmullw_u256_fallback;
2845	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulld_u256, iemAImpl_vpmulld_u256_fallback;
2846	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhw_u256, iemAImpl_vpmulhw_u256_fallback;
2847	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhuw_u256, iemAImpl_vpmulhuw_u256_fallback;
2848	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgb_u256, iemAImpl_vpavgb_u256_fallback;
2849	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgw_u256, iemAImpl_vpavgw_u256_fallback;
2850	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignb_u256, iemAImpl_vpsignb_u256_fallback;
2851	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignw_u256, iemAImpl_vpsignw_u256_fallback;
2852	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignd_u256, iemAImpl_vpsignd_u256_fallback;
2853	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddw_u256, iemAImpl_vphaddw_u256_fallback;
2854	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddd_u256, iemAImpl_vphaddd_u256_fallback;
2855	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubw_u256, iemAImpl_vphsubw_u256_fallback;
2856	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubd_u256, iemAImpl_vphsubd_u256_fallback;
2857	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddsw_u256, iemAImpl_vphaddsw_u256_fallback;
2858	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubsw_u256, iemAImpl_vphsubsw_u256_fallback;
2859	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddubsw_u256, iemAImpl_vpmaddubsw_u256_fallback;
2860	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhrsw_u256, iemAImpl_vpmulhrsw_u256_fallback;
2861	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsadbw_u256, iemAImpl_vpsadbw_u256_fallback;
2862	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuldq_u256, iemAImpl_vpmuldq_u256_fallback;
2863	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuludq_u256, iemAImpl_vpmuludq_u256_fallback;
2864	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsb_u256, iemAImpl_vpsubsb_u256_fallback;
2865	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsw_u256, iemAImpl_vpsubsw_u256_fallback;
2866	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusb_u256, iemAImpl_vpsubusb_u256_fallback;
2867	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusw_u256, iemAImpl_vpsubusw_u256_fallback;
2868	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusb_u256, iemAImpl_vpaddusb_u256_fallback;
2869	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusw_u256, iemAImpl_vpaddusw_u256_fallback;
2870	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsb_u256, iemAImpl_vpaddsb_u256_fallback;
2871	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsw_u256, iemAImpl_vpaddsw_u256_fallback;
2872
2873	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsb_u256, iemAImpl_vpabsb_u256_fallback;
2874	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsw_u256, iemAImpl_vpabsw_u256_fallback;
2875	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsd_u256, iemAImpl_vpabsd_u256_fallback;
2876	/** @} */
2877
2878	/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
2879	* @{ */
2880	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
2881	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
2882	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpcklbw_u128, iemAImpl_vpunpcklbw_u128_fallback,
2883	iemAImpl_vpunpcklwd_u128, iemAImpl_vpunpcklwd_u128_fallback,
2884	iemAImpl_vpunpckldq_u128, iemAImpl_vpunpckldq_u128_fallback,
2885	iemAImpl_vpunpcklqdq_u128, iemAImpl_vpunpcklqdq_u128_fallback,
2886	iemAImpl_vunpcklps_u128, iemAImpl_vunpcklps_u128_fallback,
2887	iemAImpl_vunpcklpd_u128, iemAImpl_vunpcklpd_u128_fallback,
2888	iemAImpl_vunpckhps_u128, iemAImpl_vunpckhps_u128_fallback,
2889	iemAImpl_vunpckhpd_u128, iemAImpl_vunpckhpd_u128_fallback;
2890
2891	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpcklbw_u256, iemAImpl_vpunpcklbw_u256_fallback,
2892	iemAImpl_vpunpcklwd_u256, iemAImpl_vpunpcklwd_u256_fallback,
2893	iemAImpl_vpunpckldq_u256, iemAImpl_vpunpckldq_u256_fallback,
2894	iemAImpl_vpunpcklqdq_u256, iemAImpl_vpunpcklqdq_u256_fallback,
2895	iemAImpl_vunpcklps_u256, iemAImpl_vunpcklps_u256_fallback,
2896	iemAImpl_vunpcklpd_u256, iemAImpl_vunpcklpd_u256_fallback,
2897	iemAImpl_vunpckhps_u256, iemAImpl_vunpckhps_u256_fallback,
2898	iemAImpl_vunpckhpd_u256, iemAImpl_vunpckhpd_u256_fallback;
2899	/** @} */
2900
2901	/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
2902	* @{ */
2903	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
2904	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
2905	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpckhbw_u128, iemAImpl_vpunpckhbw_u128_fallback,
2906	iemAImpl_vpunpckhwd_u128, iemAImpl_vpunpckhwd_u128_fallback,
2907	iemAImpl_vpunpckhdq_u128, iemAImpl_vpunpckhdq_u128_fallback,
2908	iemAImpl_vpunpckhqdq_u128, iemAImpl_vpunpckhqdq_u128_fallback;
2909	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpckhbw_u256, iemAImpl_vpunpckhbw_u256_fallback,
2910	iemAImpl_vpunpckhwd_u256, iemAImpl_vpunpckhwd_u256_fallback,
2911	iemAImpl_vpunpckhdq_u256, iemAImpl_vpunpckhdq_u256_fallback,
2912	iemAImpl_vpunpckhqdq_u256, iemAImpl_vpunpckhqdq_u256_fallback;
2913	/** @} */
2914
2915	/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
2916	* @{ */
2917	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2918	typedef FNIEMAIMPLMEDIAPSHUFU128 *PFNIEMAIMPLMEDIAPSHUFU128;
2919	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
2920	typedef FNIEMAIMPLMEDIAPSHUFU256 *PFNIEMAIMPLMEDIAPSHUFU256;
2921	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw_u64,(uint64_t puDst, uint64_t const puSrc, uint8_t bEvil));
2922	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_pshufhw_u128, iemAImpl_pshuflw_u128, iemAImpl_pshufd_u128;
2923	#ifndef IEM_WITHOUT_ASSEMBLY
2924	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256, iemAImpl_vpshuflw_u256, iemAImpl_vpshufd_u256;
2925	#endif
2926	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256_fallback, iemAImpl_vpshuflw_u256_fallback, iemAImpl_vpshufd_u256_fallback;
2927	/** @} */
2928
2929	/** @name Media (SSE/MMX/AVX) operation: Shift Immediate Stuff (evil)
2930	* @{ */
2931	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU64,(uint64_t *puDst, uint8_t bShift));
2932	typedef FNIEMAIMPLMEDIAPSHIFTU64 *PFNIEMAIMPLMEDIAPSHIFTU64;
2933	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU128,(PRTUINT128U puDst, uint8_t bShift));
2934	typedef FNIEMAIMPLMEDIAPSHIFTU128 *PFNIEMAIMPLMEDIAPSHIFTU128;
2935	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU256,(PRTUINT256U puDst, uint8_t bShift));
2936	typedef FNIEMAIMPLMEDIAPSHIFTU256 *PFNIEMAIMPLMEDIAPSHIFTU256;
2937	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psllw_imm_u64, iemAImpl_pslld_imm_u64, iemAImpl_psllq_imm_u64;
2938	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psrlw_imm_u64, iemAImpl_psrld_imm_u64, iemAImpl_psrlq_imm_u64;
2939	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psraw_imm_u64, iemAImpl_psrad_imm_u64;
2940	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psllw_imm_u128, iemAImpl_pslld_imm_u128, iemAImpl_psllq_imm_u128;
2941	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psrlw_imm_u128, iemAImpl_psrld_imm_u128, iemAImpl_psrlq_imm_u128;
2942	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psraw_imm_u128, iemAImpl_psrad_imm_u128;
2943	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_pslldq_imm_u128, iemAImpl_psrldq_imm_u128;
2944	/** @} */
2945
2946	/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
2947	* @{ */
2948	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(uint64_t pu64Dst, uint64_t const puSrc));
2949	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(uint64_t *pu64Dst, PCRTUINT128U puSrc));
2950	#ifndef IEM_WITHOUT_ASSEMBLY
2951	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
2952	#endif
2953	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256_fallback,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
2954	/** @} */
2955
2956	/** @name Media (SSE/MMX/AVX) operations: Variable Blend Packed Bytes/R32/R64.
2957	* @{ */
2958	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puMask));
2959	typedef FNIEMAIMPLBLENDU128 *PFNIEMAIMPLBLENDU128;
2960	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, PCRTUINT128U puMask));
2961	typedef FNIEMAIMPLAVXBLENDU128 *PFNIEMAIMPLAVXBLENDU128;
2962	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, PCRTUINT256U puMask));
2963	typedef FNIEMAIMPLAVXBLENDU256 *PFNIEMAIMPLAVXBLENDU256;
2964
2965	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128;
2966	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128_fallback;
2967	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128;
2968	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128_fallback;
2969	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256;
2970	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256_fallback;
2971
2972	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128;
2973	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128_fallback;
2974	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128;
2975	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128_fallback;
2976	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256;
2977	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256_fallback;
2978
2979	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128;
2980	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128_fallback;
2981	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128;
2982	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128_fallback;
2983	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256;
2984	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256_fallback;
2985	/** @} */
2986
2987
2988	/** @name Media (SSE/MMX/AVX) operation: Sort this later
2989	* @{ */
2990	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
2991	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
2992	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovshdup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
2993	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovshdup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
2994	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
2995	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
2996
2997	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2998	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2999	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3000	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3001	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3002
3003	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3004	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3005	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3006	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3007	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3008
3009	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3010	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3011	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
3012	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3013	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3014
3015	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3016	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3017	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3018	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3019	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3020
3021	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3022	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3023	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3024	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3025	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3026
3027	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3028	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3029	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3030	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3031	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3032
3033	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3034	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3035	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3036	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3037	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3038
3039	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3040	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3041	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3042	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3043	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3044
3045	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3046	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3047	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
3048	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3049	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3050
3051	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3052	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3053	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3054	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3055	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3056
3057	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3058	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3059	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3060	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3061	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3062
3063	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3064	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3065	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3066	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3067	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3068
3069	IEM_DECL_IMPL_DEF(void, iemAImpl_shufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3070	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3071	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3072	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3073	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3074
3075	IEM_DECL_IMPL_DEF(void, iemAImpl_shufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3076	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3077	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3078	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3079	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3080
3081	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
3082	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64_fallback,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
3083
3084	IEM_DECL_IMPL_DEF(void, iemAImpl_pinsrw_u64,(uint64_t *pu64Dst, uint16_t u16Src, uint8_t bEvil));
3085	IEM_DECL_IMPL_DEF(void, iemAImpl_pinsrw_u128,(PRTUINT128U puDst, uint16_t u16Src, uint8_t bEvil));
3086	IEM_DECL_IMPL_DEF(void, iemAImpl_vpinsrw_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint16_t u16Src, uint8_t bEvil));
3087	IEM_DECL_IMPL_DEF(void, iemAImpl_vpinsrw_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint16_t u16Src, uint8_t bEvil));
3088
3089	IEM_DECL_IMPL_DEF(void, iemAImpl_pextrw_u64,(uint16_t *pu16Dst, uint64_t u64Src, uint8_t bEvil));
3090	IEM_DECL_IMPL_DEF(void, iemAImpl_pextrw_u128,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
3091	IEM_DECL_IMPL_DEF(void, iemAImpl_vpextrw_u128,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
3092	IEM_DECL_IMPL_DEF(void, iemAImpl_vpextrw_u128_fallback,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
3093
3094	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3095	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3096	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3097	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3098	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3099
3100	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3101	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3102	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3103	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3104	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3105
3106
3107	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3108	typedef FNIEMAIMPLMEDIAOPTF2U128IMM8 *PFNIEMAIMPLMEDIAOPTF2U128IMM8;
3109	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3110	typedef FNIEMAIMPLMEDIAOPTF3U128IMM8 *PFNIEMAIMPLMEDIAOPTF3U128IMM8;
3111	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3112	typedef FNIEMAIMPLMEDIAOPTF3U256IMM8 *PFNIEMAIMPLMEDIAOPTF3U256IMM8;
3113
3114	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_palignr_u128, iemAImpl_palignr_u128_fallback;
3115	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pblendw_u128, iemAImpl_pblendw_u128_fallback;
3116	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendps_u128, iemAImpl_blendps_u128_fallback;
3117	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendpd_u128, iemAImpl_blendpd_u128_fallback;
3118
3119	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpalignr_u128, iemAImpl_vpalignr_u128_fallback;
3120	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendw_u128, iemAImpl_vpblendw_u128_fallback;
3121	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendps_u128, iemAImpl_vblendps_u128_fallback;
3122	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendpd_u128, iemAImpl_vblendpd_u128_fallback;
3123
3124	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpalignr_u256, iemAImpl_vpalignr_u256_fallback;
3125	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendw_u256, iemAImpl_vpblendw_u256_fallback;
3126	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendps_u256, iemAImpl_vblendps_u256_fallback;
3127	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendpd_u256, iemAImpl_vblendpd_u256_fallback;
3128	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2i128_u256, iemAImpl_vperm2i128_u256_fallback;
3129	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2f128_u256, iemAImpl_vperm2f128_u256_fallback;
3130
3131	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesimc_u128, iemAImpl_aesimc_u128_fallback;
3132	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenc_u128, iemAImpl_aesenc_u128_fallback;
3133	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenclast_u128, iemAImpl_aesenclast_u128_fallback;
3134	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdec_u128, iemAImpl_aesdec_u128_fallback;
3135	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdeclast_u128, iemAImpl_aesdeclast_u128_fallback;
3136
3137	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesimc_u128, iemAImpl_vaesimc_u128_fallback;
3138	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenc_u128, iemAImpl_vaesenc_u128_fallback;
3139	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenclast_u128, iemAImpl_vaesenclast_u128_fallback;
3140	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdec_u128, iemAImpl_vaesdec_u128_fallback;
3141	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdeclast_u128, iemAImpl_vaesdeclast_u128_fallback;
3142
3143	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_aeskeygenassist_u128, iemAImpl_aeskeygenassist_u128_fallback;
3144
3145	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vaeskeygenassist_u128, iemAImpl_vaeskeygenassist_u128_fallback;
3146
3147	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1nexte_u128, iemAImpl_sha1nexte_u128_fallback;
3148	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg1_u128, iemAImpl_sha1msg1_u128_fallback;
3149	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg2_u128, iemAImpl_sha1msg2_u128_fallback;
3150	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg1_u128, iemAImpl_sha256msg1_u128_fallback;
3151	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg2_u128, iemAImpl_sha256msg2_u128_fallback;
3152	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_sha1rnds4_u128, iemAImpl_sha1rnds4_u128_fallback;
3153	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
3154	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
3155
3156	typedef struct IEMPCMPISTRXSRC
3157	{
3158	RTUINT128U uSrc1;
3159	RTUINT128U uSrc2;
3160	} IEMPCMPISTRXSRC;
3161	typedef IEMPCMPISTRXSRC *PIEMPCMPISTRXSRC;
3162	typedef const IEMPCMPISTRXSRC *PCIEMPCMPISTRXSRC;
3163
3164	typedef struct IEMPCMPESTRXSRC
3165	{
3166	RTUINT128U uSrc1;
3167	RTUINT128U uSrc2;
3168	uint64_t u64Rax;
3169	uint64_t u64Rdx;
3170	} IEMPCMPESTRXSRC;
3171	typedef IEMPCMPESTRXSRC *PIEMPCMPESTRXSRC;
3172	typedef const IEMPCMPESTRXSRC *PCIEMPCMPESTRXSRC;
3173
3174	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPISTRIU128IMM8,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
3175	typedef FNIEMAIMPLPCMPISTRIU128IMM8 *PFNIEMAIMPLPCMPISTRIU128IMM8;
3176	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRIU128IMM8,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
3177	typedef FNIEMAIMPLPCMPESTRIU128IMM8 *PFNIEMAIMPLPCMPESTRIU128IMM8;
3178
3179	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPISTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
3180	typedef FNIEMAIMPLPCMPISTRMU128IMM8 *PFNIEMAIMPLPCMPISTRMU128IMM8;
3181	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
3182	typedef FNIEMAIMPLPCMPESTRMU128IMM8 *PFNIEMAIMPLPCMPESTRMU128IMM8;
3183
3184	FNIEMAIMPLPCMPISTRIU128IMM8 iemAImpl_pcmpistri_u128, iemAImpl_pcmpistri_u128_fallback;
3185	FNIEMAIMPLPCMPESTRIU128IMM8 iemAImpl_pcmpestri_u128, iemAImpl_pcmpestri_u128_fallback;
3186	FNIEMAIMPLPCMPISTRMU128IMM8 iemAImpl_pcmpistrm_u128, iemAImpl_pcmpistrm_u128_fallback;
3187	FNIEMAIMPLPCMPESTRMU128IMM8 iemAImpl_pcmpestrm_u128, iemAImpl_pcmpestrm_u128_fallback;
3188
3189	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pclmulqdq_u128, iemAImpl_pclmulqdq_u128_fallback;
3190	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpclmulqdq_u128, iemAImpl_vpclmulqdq_u128_fallback;
3191
3192	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_mpsadbw_u128, iemAImpl_mpsadbw_u128_fallback;
3193	/** @} */
3194
3195	/** @name Media Odds and Ends
3196	* @{ */
3197	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U8,(uint32_t *puDst, uint8_t uSrc));
3198	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U16,(uint32_t *puDst, uint16_t uSrc));
3199	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U32,(uint32_t *puDst, uint32_t uSrc));
3200	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U64,(uint32_t *puDst, uint64_t uSrc));
3201	FNIEMAIMPLCR32U8 iemAImpl_crc32_u8, iemAImpl_crc32_u8_fallback;
3202	FNIEMAIMPLCR32U16 iemAImpl_crc32_u16, iemAImpl_crc32_u16_fallback;
3203	FNIEMAIMPLCR32U32 iemAImpl_crc32_u32, iemAImpl_crc32_u32_fallback;
3204	FNIEMAIMPLCR32U64 iemAImpl_crc32_u64, iemAImpl_crc32_u64_fallback;
3205
3206	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL128,(PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint32_t *pEFlags));
3207	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL256,(PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint32_t *pEFlags));
3208	FNIEMAIMPLF2EFL128 iemAImpl_ptest_u128;
3209	FNIEMAIMPLF2EFL256 iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback;
3210
3211	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I32U64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int32_t pi32Dst, const uint64_t pu64Src)); / pu64Src is a double precision floating point. */
3212	typedef FNIEMAIMPLSSEF2I32U64 *PFNIEMAIMPLSSEF2I32U64;
3213	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I64U64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int64_t pi64Dst, const uint64_t pu64Src)); / pu64Src is a double precision floating point. */
3214	typedef FNIEMAIMPLSSEF2I64U64 *PFNIEMAIMPLSSEF2I64U64;
3215	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I32U32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int32_t pi32Dst, const uint32_t pu32Src)); / pu32Src is a single precision floating point. */
3216	typedef FNIEMAIMPLSSEF2I32U32 *PFNIEMAIMPLSSEF2I32U32;
3217	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I64U32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int64_t pi64Dst, const uint32_t pu32Src)); / pu32Src is a single precision floating point. */
3218	typedef FNIEMAIMPLSSEF2I64U32 *PFNIEMAIMPLSSEF2I64U32;
3219
3220	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvttsd2si_i32_r64;
3221	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvtsd2si_i32_r64;
3222
3223	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvttsd2si_i64_r64;
3224	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvtsd2si_i64_r64;
3225
3226	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvttss2si_i32_r32;
3227	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvtss2si_i32_r32;
3228
3229	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvttss2si_i64_r32;
3230	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvtss2si_i64_r32;
3231
3232	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R32I32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT32U pr32Dst, const int32_t pi32Src));
3233	typedef FNIEMAIMPLSSEF2R32I32 *PFNIEMAIMPLSSEF2R32I32;
3234	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R32I64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT32U pr32Dst, const int64_t pi64Src));
3235	typedef FNIEMAIMPLSSEF2R32I64 *PFNIEMAIMPLSSEF2R32I64;
3236
3237	FNIEMAIMPLSSEF2R32I32 iemAImpl_cvtsi2ss_r32_i32;
3238	FNIEMAIMPLSSEF2R32I64 iemAImpl_cvtsi2ss_r32_i64;
3239
3240	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R64I32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT64U pr64Dst, const int32_t pi32Src));
3241	typedef FNIEMAIMPLSSEF2R64I32 *PFNIEMAIMPLSSEF2R64I32;
3242	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R64I64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT64U pr64Dst, const int64_t pi64Src));
3243	typedef FNIEMAIMPLSSEF2R64I64 *PFNIEMAIMPLSSEF2R64I64;
3244
3245	FNIEMAIMPLSSEF2R64I32 iemAImpl_cvtsi2sd_r64_i32;
3246	FNIEMAIMPLSSEF2R64I64 iemAImpl_cvtsi2sd_r64_i64;
3247
3248
3249	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFLMXCSR128,(uint32_t pfMxcsr, uint32_t pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
3250	typedef FNIEMAIMPLF2EFLMXCSR128 *PFNIEMAIMPLF2EFLMXCSR128;
3251
3252	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_ucomiss_u128;
3253	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback;
3254
3255	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_ucomisd_u128;
3256	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback;
3257
3258	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_comiss_u128;
3259	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback;
3260
3261	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_comisd_u128;
3262	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback;
3263
3264
3265	typedef struct IEMMEDIAF2XMMSRC
3266	{
3267	X86XMMREG uSrc1;
3268	X86XMMREG uSrc2;
3269	} IEMMEDIAF2XMMSRC;
3270	typedef IEMMEDIAF2XMMSRC *PIEMMEDIAF2XMMSRC;
3271	typedef const IEMMEDIAF2XMMSRC *PCIEMMEDIAF2XMMSRC;
3272
3273	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRF2XMMIMM8,(uint32_t *pfMxcsr, PX86XMMREG puDst, PCIEMMEDIAF2XMMSRC puSrc, uint8_t bEvil));
3274	typedef FNIEMAIMPLMXCSRF2XMMIMM8 *PFNIEMAIMPLMXCSRF2XMMIMM8;
3275
3276	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpps_u128;
3277	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmppd_u128;
3278	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpss_u128;
3279	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpsd_u128;
3280	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundss_u128;
3281	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundsd_u128;
3282
3283	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundps_u128, iemAImpl_roundps_u128_fallback;
3284	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundpd_u128, iemAImpl_roundpd_u128_fallback;
3285
3286	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_dpps_u128, iemAImpl_dpps_u128_fallback;
3287	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_dppd_u128, iemAImpl_dppd_u128_fallback;
3288
3289	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU64U128,(uint32_t pfMxcsr, uint64_t pu64Dst, PCX86XMMREG pSrc));
3290	typedef FNIEMAIMPLMXCSRU64U128 *PFNIEMAIMPLMXCSRU64U128;
3291
3292	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvtpd2pi_u128;
3293	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvttpd2pi_u128;
3294
3295	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU128U64,(uint32_t *pfMxcsr, PX86XMMREG pDst, uint64_t u64Src));
3296	typedef FNIEMAIMPLMXCSRU128U64 *PFNIEMAIMPLMXCSRU128U64;
3297
3298	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2ps_u128;
3299	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2pd_u128;
3300
3301	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU64U64,(uint32_t pfMxcsr, uint64_t pu64Dst, uint64_t u64Src));
3302	typedef FNIEMAIMPLMXCSRU64U64 *PFNIEMAIMPLMXCSRU64U64;
3303
3304	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvtps2pi_u128;
3305	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvttps2pi_u128;
3306
3307	/** @} */
3308
3309
3310	/** @name Function tables.
3311	* @{
3312	*/
3313
3314	/**
3315	* Function table for a binary operator providing implementation based on
3316	* operand size.
3317	*/
3318	typedef struct IEMOPBINSIZES
3319	{
3320	PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
3321	PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
3322	PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
3323	PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
3324	} IEMOPBINSIZES;
3325	/** Pointer to a binary operator function table. */
3326	typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
3327
3328
3329	/**
3330	* Function table for a unary operator providing implementation based on
3331	* operand size.
3332	*/
3333	typedef struct IEMOPUNARYSIZES
3334	{
3335	PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
3336	PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
3337	PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
3338	PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
3339	} IEMOPUNARYSIZES;
3340	/** Pointer to a unary operator function table. */
3341	typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
3342
3343
3344	/**
3345	* Function table for a shift operator providing implementation based on
3346	* operand size.
3347	*/
3348	typedef struct IEMOPSHIFTSIZES
3349	{
3350	PFNIEMAIMPLSHIFTU8 pfnNormalU8;
3351	PFNIEMAIMPLSHIFTU16 pfnNormalU16;
3352	PFNIEMAIMPLSHIFTU32 pfnNormalU32;
3353	PFNIEMAIMPLSHIFTU64 pfnNormalU64;
3354	} IEMOPSHIFTSIZES;
3355	/** Pointer to a shift operator function table. */
3356	typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
3357
3358
3359	/**
3360	* Function table for a multiplication or division operation.
3361	*/
3362	typedef struct IEMOPMULDIVSIZES
3363	{
3364	PFNIEMAIMPLMULDIVU8 pfnU8;
3365	PFNIEMAIMPLMULDIVU16 pfnU16;
3366	PFNIEMAIMPLMULDIVU32 pfnU32;
3367	PFNIEMAIMPLMULDIVU64 pfnU64;
3368	} IEMOPMULDIVSIZES;
3369	/** Pointer to a multiplication or division operation function table. */
3370	typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
3371
3372
3373	/**
3374	* Function table for a double precision shift operator providing implementation
3375	* based on operand size.
3376	*/
3377	typedef struct IEMOPSHIFTDBLSIZES
3378	{
3379	PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
3380	PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
3381	PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
3382	} IEMOPSHIFTDBLSIZES;
3383	/** Pointer to a double precision shift function table. */
3384	typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
3385
3386
3387	/**
3388	* Function table for media instruction taking two full sized media source
3389	* registers and one full sized destination register (AVX).
3390	*/
3391	typedef struct IEMOPMEDIAF3
3392	{
3393	PFNIEMAIMPLMEDIAF3U128 pfnU128;
3394	PFNIEMAIMPLMEDIAF3U256 pfnU256;
3395	} IEMOPMEDIAF3;
3396	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
3397	typedef IEMOPMEDIAF3 const *PCIEMOPMEDIAF3;
3398
3399	/** @def IEMOPMEDIAF3_INIT_VARS_EX
3400	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3401	* given functions as initializers. For use in AVX functions where a pair of
3402	* functions are only used once and the function table need not be public. */
3403	#ifndef TST_IEM_CHECK_MC
3404	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3405	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3406	static IEMOPMEDIAF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3407	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3408	# else
3409	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3410	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3411	# endif
3412	#else
3413	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3414	#endif
3415	/** @def IEMOPMEDIAF3_INIT_VARS
3416	* Generate AVX function tables for the @a a_InstrNm instruction.
3417	* @sa IEMOPMEDIAF3_INIT_VARS_EX */
3418	#define IEMOPMEDIAF3_INIT_VARS(a_InstrNm) \
3419	IEMOPMEDIAF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3420	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3421
3422	/**
3423	* Function table for media instruction taking two full sized media source
3424	* registers and one full sized destination register, but no additional state
3425	* (AVX).
3426	*/
3427	typedef struct IEMOPMEDIAOPTF3
3428	{
3429	PFNIEMAIMPLMEDIAOPTF3U128 pfnU128;
3430	PFNIEMAIMPLMEDIAOPTF3U256 pfnU256;
3431	} IEMOPMEDIAOPTF3;
3432	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
3433	typedef IEMOPMEDIAOPTF3 const *PCIEMOPMEDIAOPTF3;
3434
3435	/** @def IEMOPMEDIAOPTF3_INIT_VARS_EX
3436	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3437	* given functions as initializers. For use in AVX functions where a pair of
3438	* functions are only used once and the function table need not be public. */
3439	#ifndef TST_IEM_CHECK_MC
3440	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3441	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3442	static IEMOPMEDIAOPTF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3443	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3444	# else
3445	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3446	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3447	# endif
3448	#else
3449	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3450	#endif
3451	/** @def IEMOPMEDIAOPTF3_INIT_VARS
3452	* Generate AVX function tables for the @a a_InstrNm instruction.
3453	* @sa IEMOPMEDIAOPTF3_INIT_VARS_EX */
3454	#define IEMOPMEDIAOPTF3_INIT_VARS(a_InstrNm) \
3455	IEMOPMEDIAOPTF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3456	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3457
3458	/**
3459	* Function table for media instruction taking one full sized media source
3460	* registers and one full sized destination register, but no additional state
3461	* (AVX).
3462	*/
3463	typedef struct IEMOPMEDIAOPTF2
3464	{
3465	PFNIEMAIMPLMEDIAOPTF2U128 pfnU128;
3466	PFNIEMAIMPLMEDIAOPTF2U256 pfnU256;
3467	} IEMOPMEDIAOPTF2;
3468	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
3469	typedef IEMOPMEDIAOPTF2 const *PCIEMOPMEDIAOPTF2;
3470
3471	/** @def IEMOPMEDIAOPTF2_INIT_VARS_EX
3472	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3473	* given functions as initializers. For use in AVX functions where a pair of
3474	* functions are only used once and the function table need not be public. */
3475	#ifndef TST_IEM_CHECK_MC
3476	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3477	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3478	static IEMOPMEDIAOPTF2 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3479	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3480	# else
3481	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3482	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3483	# endif
3484	#else
3485	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3486	#endif
3487	/** @def IEMOPMEDIAOPTF2_INIT_VARS
3488	* Generate AVX function tables for the @a a_InstrNm instruction.
3489	* @sa IEMOPMEDIAOPTF2_INIT_VARS_EX */
3490	#define IEMOPMEDIAOPTF2_INIT_VARS(a_InstrNm) \
3491	IEMOPMEDIAOPTF2_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3492	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3493
3494	/**
3495	* Function table for media instruction taking two full sized media source
3496	* registers and one full sized destination register and an 8-bit immediate, but no additional state
3497	* (AVX).
3498	*/
3499	typedef struct IEMOPMEDIAOPTF3IMM8
3500	{
3501	PFNIEMAIMPLMEDIAOPTF3U128IMM8 pfnU128;
3502	PFNIEMAIMPLMEDIAOPTF3U256IMM8 pfnU256;
3503	} IEMOPMEDIAOPTF3IMM8;
3504	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
3505	typedef IEMOPMEDIAOPTF3IMM8 const *PCIEMOPMEDIAOPTF3IMM8;
3506
3507	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX
3508	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3509	* given functions as initializers. For use in AVX functions where a pair of
3510	* functions are only used once and the function table need not be public. */
3511	#ifndef TST_IEM_CHECK_MC
3512	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3513	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3514	static IEMOPMEDIAOPTF3IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3515	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3516	# else
3517	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3518	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3519	# endif
3520	#else
3521	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3522	#endif
3523	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS
3524	* Generate AVX function tables for the @a a_InstrNm instruction.
3525	* @sa IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX */
3526	#define IEMOPMEDIAOPTF3IMM8_INIT_VARS(a_InstrNm) \
3527	IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3528	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3529	/** @} */
3530
3531
3532	/**
3533	* Function table for blend type instruction taking three full sized media source
3534	* registers and one full sized destination register, but no additional state
3535	* (AVX).
3536	*/
3537	typedef struct IEMOPBLENDOP
3538	{
3539	PFNIEMAIMPLAVXBLENDU128 pfnU128;
3540	PFNIEMAIMPLAVXBLENDU256 pfnU256;
3541	} IEMOPBLENDOP;
3542	/** Pointer to a media operation function table for 4 full sized ops (AVX). */
3543	typedef IEMOPBLENDOP const *PCIEMOPBLENDOP;
3544
3545	/** @def IEMOPBLENDOP_INIT_VARS_EX
3546	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3547	* given functions as initializers. For use in AVX functions where a pair of
3548	* functions are only used once and the function table need not be public. */
3549	#ifndef TST_IEM_CHECK_MC
3550	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3551	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3552	static IEMOPBLENDOP const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3553	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3554	# else
3555	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3556	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3557	# endif
3558	#else
3559	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3560	#endif
3561	/** @def IEMOPBLENDOP_INIT_VARS
3562	* Generate AVX function tables for the @a a_InstrNm instruction.
3563	* @sa IEMOPBLENDOP_INIT_VARS_EX */
3564	#define IEMOPBLENDOP_INIT_VARS(a_InstrNm) \
3565	IEMOPBLENDOP_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3566	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3567
3568
3569	/** @name SSE/AVX single/double precision floating point operations.
3570	* @{ */
3571	/**
3572	* A SSE result.
3573	*/
3574	typedef struct IEMSSERESULT
3575	{
3576	/** The output value. */
3577	X86XMMREG uResult;
3578	/** The output status. */
3579	uint32_t MXCSR;
3580	} IEMSSERESULT;
3581	AssertCompileMemberOffset(IEMSSERESULT, MXCSR, 128 / 8);
3582	/** Pointer to a SSE result. */
3583	typedef IEMSSERESULT *PIEMSSERESULT;
3584	/** Pointer to a const SSE result. */
3585	typedef IEMSSERESULT const *PCIEMSSERESULT;
3586
3587
3588	/**
3589	* A AVX128 result.
3590	*/
3591	typedef struct IEMAVX128RESULT
3592	{
3593	/** The output value. */
3594	X86XMMREG uResult;
3595	/** The output status. */
3596	uint32_t MXCSR;
3597	} IEMAVX128RESULT;
3598	AssertCompileMemberOffset(IEMAVX128RESULT, MXCSR, 128 / 8);
3599	/** Pointer to a AVX128 result. */
3600	typedef IEMAVX128RESULT *PIEMAVX128RESULT;
3601	/** Pointer to a const AVX128 result. */
3602	typedef IEMAVX128RESULT const *PCIEMAVX128RESULT;
3603
3604
3605	/**
3606	* A AVX256 result.
3607	*/
3608	typedef struct IEMAVX256RESULT
3609	{
3610	/** The output value. */
3611	X86YMMREG uResult;
3612	/** The output status. */
3613	uint32_t MXCSR;
3614	} IEMAVX256RESULT;
3615	AssertCompileMemberOffset(IEMAVX256RESULT, MXCSR, 256 / 8);
3616	/** Pointer to a AVX256 result. */
3617	typedef IEMAVX256RESULT *PIEMAVX256RESULT;
3618	/** Pointer to a const AVX256 result. */
3619	typedef IEMAVX256RESULT const *PCIEMAVX256RESULT;
3620
3621
3622	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
3623	typedef FNIEMAIMPLFPSSEF2U128 *PFNIEMAIMPLFPSSEF2U128;
3624	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128R32,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
3625	typedef FNIEMAIMPLFPSSEF2U128R32 *PFNIEMAIMPLFPSSEF2U128R32;
3626	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128R64,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
3627	typedef FNIEMAIMPLFPSSEF2U128R64 *PFNIEMAIMPLFPSSEF2U128R64;
3628
3629	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
3630	typedef FNIEMAIMPLFPAVXF3U128 *PFNIEMAIMPLFPAVXF3U128;
3631	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128R32,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
3632	typedef FNIEMAIMPLFPAVXF3U128R32 *PFNIEMAIMPLFPAVXF3U128R32;
3633	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128R64,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
3634	typedef FNIEMAIMPLFPAVXF3U128R64 *PFNIEMAIMPLFPAVXF3U128R64;
3635
3636	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U256,(PX86XSAVEAREA pExtState, PIEMAVX256RESULT pResult, PCX86YMMREG puSrc1, PCX86YMMREG puSrc2));
3637	typedef FNIEMAIMPLFPAVXF3U256 *PFNIEMAIMPLFPAVXF3U256;
3638
3639	FNIEMAIMPLFPSSEF2U128 iemAImpl_addps_u128;
3640	FNIEMAIMPLFPSSEF2U128 iemAImpl_addpd_u128;
3641	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulps_u128;
3642	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulpd_u128;
3643	FNIEMAIMPLFPSSEF2U128 iemAImpl_subps_u128;
3644	FNIEMAIMPLFPSSEF2U128 iemAImpl_subpd_u128;
3645	FNIEMAIMPLFPSSEF2U128 iemAImpl_minps_u128;
3646	FNIEMAIMPLFPSSEF2U128 iemAImpl_minpd_u128;
3647	FNIEMAIMPLFPSSEF2U128 iemAImpl_divps_u128;
3648	FNIEMAIMPLFPSSEF2U128 iemAImpl_divpd_u128;
3649	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxps_u128;
3650	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxpd_u128;
3651	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddps_u128;
3652	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddpd_u128;
3653	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubps_u128;
3654	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubpd_u128;
3655	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtps_u128;
3656	FNIEMAIMPLFPSSEF2U128 iemAImpl_rsqrtps_u128;
3657	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtpd_u128;
3658	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubps_u128;
3659	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubpd_u128;
3660	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2ps_u128;
3661	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2pd_u128;
3662
3663	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2ps_u128;
3664	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2dq_u128;
3665	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttps2dq_u128;
3666	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttpd2dq_u128;
3667	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2pd_u128;
3668	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2dq_u128;
3669
3670	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_addss_u128_r32;
3671	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_addsd_u128_r64;
3672	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_mulss_u128_r32;
3673	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_mulsd_u128_r64;
3674	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_subss_u128_r32;
3675	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_subsd_u128_r64;
3676	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_minss_u128_r32;
3677	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_minsd_u128_r64;
3678	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_divss_u128_r32;
3679	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_divsd_u128_r64;
3680	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_maxss_u128_r32;
3681	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_maxsd_u128_r64;
3682	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_cvtss2sd_u128_r32;
3683	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_cvtsd2ss_u128_r64;
3684	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_sqrtss_u128_r32;
3685	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_sqrtsd_u128_r64;
3686	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_rsqrtss_u128_r32;
3687
3688	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddps_u128, iemAImpl_vaddps_u128_fallback;
3689	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddpd_u128, iemAImpl_vaddpd_u128_fallback;
3690	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulps_u128, iemAImpl_vmulps_u128_fallback;
3691	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulpd_u128, iemAImpl_vmulpd_u128_fallback;
3692	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubps_u128, iemAImpl_vsubps_u128_fallback;
3693	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubpd_u128, iemAImpl_vsubpd_u128_fallback;
3694	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminps_u128, iemAImpl_vminps_u128_fallback;
3695	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminpd_u128, iemAImpl_vminpd_u128_fallback;
3696	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivps_u128, iemAImpl_vdivps_u128_fallback;
3697	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivpd_u128, iemAImpl_vdivpd_u128_fallback;
3698	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxps_u128, iemAImpl_vmaxps_u128_fallback;
3699	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxpd_u128, iemAImpl_vmaxpd_u128_fallback;
3700	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddps_u128, iemAImpl_vhaddps_u128_fallback;
3701	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddpd_u128, iemAImpl_vhaddpd_u128_fallback;
3702	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubps_u128, iemAImpl_vhsubps_u128_fallback;
3703	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubpd_u128, iemAImpl_vhsubpd_u128_fallback;
3704	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtps_u128, iemAImpl_vsqrtps_u128_fallback;
3705	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtpd_u128, iemAImpl_vsqrtpd_u128_fallback;
3706	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubps_u128, iemAImpl_vaddsubps_u128_fallback;
3707	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubpd_u128, iemAImpl_vaddsubpd_u128_fallback;
3708	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtpd2ps_u128, iemAImpl_vcvtpd2ps_u128_fallback;
3709	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtps2pd_u128, iemAImpl_vcvtps2pd_u128_fallback;
3710
3711	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vaddss_u128_r32, iemAImpl_vaddss_u128_r32_fallback;
3712	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vaddsd_u128_r64, iemAImpl_vaddsd_u128_r64_fallback;
3713	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmulss_u128_r32, iemAImpl_vmulss_u128_r32_fallback;
3714	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmulsd_u128_r64, iemAImpl_vmulsd_u128_r64_fallback;
3715	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsubss_u128_r32, iemAImpl_vsubss_u128_r32_fallback;
3716	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsubsd_u128_r64, iemAImpl_vsubsd_u128_r64_fallback;
3717	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vminss_u128_r32, iemAImpl_vminss_u128_r32_fallback;
3718	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vminsd_u128_r64, iemAImpl_vminsd_u128_r64_fallback;
3719	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vdivss_u128_r32, iemAImpl_vdivss_u128_r32_fallback;
3720	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vdivsd_u128_r64, iemAImpl_vdivsd_u128_r64_fallback;
3721	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmaxss_u128_r32, iemAImpl_vmaxss_u128_r32_fallback;
3722	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmaxsd_u128_r64, iemAImpl_vmaxsd_u128_r64_fallback;
3723	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsqrtss_u128_r32, iemAImpl_vsqrtss_u128_r32_fallback;
3724	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsqrtsd_u128_r64, iemAImpl_vsqrtsd_u128_r64_fallback;
3725
3726	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddps_u256, iemAImpl_vaddps_u256_fallback;
3727	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddpd_u256, iemAImpl_vaddpd_u256_fallback;
3728	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulps_u256, iemAImpl_vmulps_u256_fallback;
3729	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulpd_u256, iemAImpl_vmulpd_u256_fallback;
3730	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubps_u256, iemAImpl_vsubps_u256_fallback;
3731	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubpd_u256, iemAImpl_vsubpd_u256_fallback;
3732	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminps_u256, iemAImpl_vminps_u256_fallback;
3733	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminpd_u256, iemAImpl_vminpd_u256_fallback;
3734	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivps_u256, iemAImpl_vdivps_u256_fallback;
3735	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivpd_u256, iemAImpl_vdivpd_u256_fallback;
3736	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxps_u256, iemAImpl_vmaxps_u256_fallback;
3737	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxpd_u256, iemAImpl_vmaxpd_u256_fallback;
3738	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddps_u256, iemAImpl_vhaddps_u256_fallback;
3739	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddpd_u256, iemAImpl_vhaddpd_u256_fallback;
3740	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubps_u256, iemAImpl_vhsubps_u256_fallback;
3741	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubpd_u256, iemAImpl_vhsubpd_u256_fallback;
3742	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubps_u256, iemAImpl_vhaddsubps_u256_fallback;
3743	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubpd_u256, iemAImpl_vhaddsubpd_u256_fallback;
3744	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtpd2ps_u256, iemAImpl_vcvtpd2ps_u256_fallback;
3745	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtps2pd_u256, iemAImpl_vcvtps2pd_u256_fallback;
3746	/** @} */
3747
3748	/** @name C instruction implementations for anything slightly complicated.
3749	* @{ */
3750
3751	/**
3752	* For typedef'ing or declaring a C instruction implementation function taking
3753	* no extra arguments.
3754	*
3755	* @param a_Name The name of the type.
3756	*/
3757	# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
3758	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
3759	/**
3760	* For defining a C instruction implementation function taking no extra
3761	* arguments.
3762	*
3763	* @param a_Name The name of the function
3764	*/
3765	# define IEM_CIMPL_DEF_0(a_Name) \
3766	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
3767	/**
3768	* Prototype version of IEM_CIMPL_DEF_0.
3769	*/
3770	# define IEM_CIMPL_PROTO_0(a_Name) \
3771	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
3772	/**
3773	* For calling a C instruction implementation function taking no extra
3774	* arguments.
3775	*
3776	* This special call macro adds default arguments to the call and allow us to
3777	* change these later.
3778	*
3779	* @param a_fn The name of the function.
3780	*/
3781	# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
3782
3783	/** Type for a C instruction implementation function taking no extra
3784	* arguments. */
3785	typedef IEM_CIMPL_DECL_TYPE_0(FNIEMCIMPL0);
3786	/** Function pointer type for a C instruction implementation function taking
3787	* no extra arguments. */
3788	typedef FNIEMCIMPL0 *PFNIEMCIMPL0;
3789
3790	/**
3791	* For typedef'ing or declaring a C instruction implementation function taking
3792	* one extra argument.
3793	*
3794	* @param a_Name The name of the type.
3795	* @param a_Type0 The argument type.
3796	* @param a_Arg0 The argument name.
3797	*/
3798	# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
3799	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
3800	/**
3801	* For defining a C instruction implementation function taking one extra
3802	* argument.
3803	*
3804	* @param a_Name The name of the function
3805	* @param a_Type0 The argument type.
3806	* @param a_Arg0 The argument name.
3807	*/
3808	# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
3809	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
3810	/**
3811	* Prototype version of IEM_CIMPL_DEF_1.
3812	*/
3813	# define IEM_CIMPL_PROTO_1(a_Name, a_Type0, a_Arg0) \
3814	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
3815	/**
3816	* For calling a C instruction implementation function taking one extra
3817	* argument.
3818	*
3819	* This special call macro adds default arguments to the call and allow us to
3820	* change these later.
3821	*
3822	* @param a_fn The name of the function.
3823	* @param a0 The name of the 1st argument.
3824	*/
3825	# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
3826
3827	/**
3828	* For typedef'ing or declaring a C instruction implementation function taking
3829	* two extra arguments.
3830	*
3831	* @param a_Name The name of the type.
3832	* @param a_Type0 The type of the 1st argument
3833	* @param a_Arg0 The name of the 1st argument.
3834	* @param a_Type1 The type of the 2nd argument.
3835	* @param a_Arg1 The name of the 2nd argument.
3836	*/
3837	# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
3838	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
3839	/**
3840	* For defining a C instruction implementation function taking two extra
3841	* arguments.
3842	*
3843	* @param a_Name The name of the function.
3844	* @param a_Type0 The type of the 1st argument
3845	* @param a_Arg0 The name of the 1st argument.
3846	* @param a_Type1 The type of the 2nd argument.
3847	* @param a_Arg1 The name of the 2nd argument.
3848	*/
3849	# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
3850	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
3851	/**
3852	* Prototype version of IEM_CIMPL_DEF_2.
3853	*/
3854	# define IEM_CIMPL_PROTO_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
3855	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
3856	/**
3857	* For calling a C instruction implementation function taking two extra
3858	* arguments.
3859	*
3860	* This special call macro adds default arguments to the call and allow us to
3861	* change these later.
3862	*
3863	* @param a_fn The name of the function.
3864	* @param a0 The name of the 1st argument.
3865	* @param a1 The name of the 2nd argument.
3866	*/
3867	# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
3868
3869	/**
3870	* For typedef'ing or declaring a C instruction implementation function taking
3871	* three extra arguments.
3872	*
3873	* @param a_Name The name of the type.
3874	* @param a_Type0 The type of the 1st argument
3875	* @param a_Arg0 The name of the 1st argument.
3876	* @param a_Type1 The type of the 2nd argument.
3877	* @param a_Arg1 The name of the 2nd argument.
3878	* @param a_Type2 The type of the 3rd argument.
3879	* @param a_Arg2 The name of the 3rd argument.
3880	*/
3881	# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
3882	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
3883	/**
3884	* For defining a C instruction implementation function taking three extra
3885	* arguments.
3886	*
3887	* @param a_Name The name of the function.
3888	* @param a_Type0 The type of the 1st argument
3889	* @param a_Arg0 The name of the 1st argument.
3890	* @param a_Type1 The type of the 2nd argument.
3891	* @param a_Arg1 The name of the 2nd argument.
3892	* @param a_Type2 The type of the 3rd argument.
3893	* @param a_Arg2 The name of the 3rd argument.
3894	*/
3895	# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
3896	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
3897	/**
3898	* Prototype version of IEM_CIMPL_DEF_3.
3899	*/
3900	# define IEM_CIMPL_PROTO_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
3901	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
3902	/**
3903	* For calling a C instruction implementation function taking three extra
3904	* arguments.
3905	*
3906	* This special call macro adds default arguments to the call and allow us to
3907	* change these later.
3908	*
3909	* @param a_fn The name of the function.
3910	* @param a0 The name of the 1st argument.
3911	* @param a1 The name of the 2nd argument.
3912	* @param a2 The name of the 3rd argument.
3913	*/
3914	# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
3915
3916
3917	/**
3918	* For typedef'ing or declaring a C instruction implementation function taking
3919	* four extra arguments.
3920	*
3921	* @param a_Name The name of the type.
3922	* @param a_Type0 The type of the 1st argument
3923	* @param a_Arg0 The name of the 1st argument.
3924	* @param a_Type1 The type of the 2nd argument.
3925	* @param a_Arg1 The name of the 2nd argument.
3926	* @param a_Type2 The type of the 3rd argument.
3927	* @param a_Arg2 The name of the 3rd argument.
3928	* @param a_Type3 The type of the 4th argument.
3929	* @param a_Arg3 The name of the 4th argument.
3930	*/
3931	# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
3932	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
3933	/**
3934	* For defining a C instruction implementation function taking four extra
3935	* arguments.
3936	*
3937	* @param a_Name The name of the function.
3938	* @param a_Type0 The type of the 1st argument
3939	* @param a_Arg0 The name of the 1st argument.
3940	* @param a_Type1 The type of the 2nd argument.
3941	* @param a_Arg1 The name of the 2nd argument.
3942	* @param a_Type2 The type of the 3rd argument.
3943	* @param a_Arg2 The name of the 3rd argument.
3944	* @param a_Type3 The type of the 4th argument.
3945	* @param a_Arg3 The name of the 4th argument.
3946	*/
3947	# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
3948	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3949	a_Type2 a_Arg2, a_Type3 a_Arg3))
3950	/**
3951	* Prototype version of IEM_CIMPL_DEF_4.
3952	*/
3953	# define IEM_CIMPL_PROTO_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
3954	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3955	a_Type2 a_Arg2, a_Type3 a_Arg3))
3956	/**
3957	* For calling a C instruction implementation function taking four extra
3958	* arguments.
3959	*
3960	* This special call macro adds default arguments to the call and allow us to
3961	* change these later.
3962	*
3963	* @param a_fn The name of the function.
3964	* @param a0 The name of the 1st argument.
3965	* @param a1 The name of the 2nd argument.
3966	* @param a2 The name of the 3rd argument.
3967	* @param a3 The name of the 4th argument.
3968	*/
3969	# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
3970
3971
3972	/**
3973	* For typedef'ing or declaring a C instruction implementation function taking
3974	* five extra arguments.
3975	*
3976	* @param a_Name The name of the type.
3977	* @param a_Type0 The type of the 1st argument
3978	* @param a_Arg0 The name of the 1st argument.
3979	* @param a_Type1 The type of the 2nd argument.
3980	* @param a_Arg1 The name of the 2nd argument.
3981	* @param a_Type2 The type of the 3rd argument.
3982	* @param a_Arg2 The name of the 3rd argument.
3983	* @param a_Type3 The type of the 4th argument.
3984	* @param a_Arg3 The name of the 4th argument.
3985	* @param a_Type4 The type of the 5th argument.
3986	* @param a_Arg4 The name of the 5th argument.
3987	*/
3988	# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
3989	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, \
3990	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
3991	a_Type3 a_Arg3, a_Type4 a_Arg4))
3992	/**
3993	* For defining a C instruction implementation function taking five extra
3994	* arguments.
3995	*
3996	* @param a_Name The name of the function.
3997	* @param a_Type0 The type of the 1st argument
3998	* @param a_Arg0 The name of the 1st argument.
3999	* @param a_Type1 The type of the 2nd argument.
4000	* @param a_Arg1 The name of the 2nd argument.
4001	* @param a_Type2 The type of the 3rd argument.
4002	* @param a_Arg2 The name of the 3rd argument.
4003	* @param a_Type3 The type of the 4th argument.
4004	* @param a_Arg3 The name of the 4th argument.
4005	* @param a_Type4 The type of the 5th argument.
4006	* @param a_Arg4 The name of the 5th argument.
4007	*/
4008	# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
4009	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4010	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
4011	/**
4012	* Prototype version of IEM_CIMPL_DEF_5.
4013	*/
4014	# define IEM_CIMPL_PROTO_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
4015	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4016	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
4017	/**
4018	* For calling a C instruction implementation function taking five extra
4019	* arguments.
4020	*
4021	* This special call macro adds default arguments to the call and allow us to
4022	* change these later.
4023	*
4024	* @param a_fn The name of the function.
4025	* @param a0 The name of the 1st argument.
4026	* @param a1 The name of the 2nd argument.
4027	* @param a2 The name of the 3rd argument.
4028	* @param a3 The name of the 4th argument.
4029	* @param a4 The name of the 5th argument.
4030	*/
4031	# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
4032
4033	/** @} */
4034
4035
4036	/** @name Opcode Decoder Function Types.
4037	* @{ */
4038
4039	/** @typedef PFNIEMOP
4040	* Pointer to an opcode decoder function.
4041	*/
4042
4043	/** @def FNIEMOP_DEF
4044	* Define an opcode decoder function.
4045	*
4046	* We're using macors for this so that adding and removing parameters as well as
4047	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL
4048	*
4049	* @param a_Name The function name.
4050	*/
4051
4052	/** @typedef PFNIEMOPRM
4053	* Pointer to an opcode decoder function with RM byte.
4054	*/
4055
4056	/** @def FNIEMOPRM_DEF
4057	* Define an opcode decoder function with RM byte.
4058	*
4059	* We're using macors for this so that adding and removing parameters as well as
4060	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL_1
4061	*
4062	* @param a_Name The function name.
4063	*/
4064
4065	#if defined(__GNUC__) && defined(RT_ARCH_X86)
4066	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOP)(PVMCPUCC pVCpu);
4067	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4068	# define FNIEMOP_DEF(a_Name) \
4069	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu)
4070	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4071	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
4072	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4073	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
4074
4075	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
4076	typedef VBOXSTRICTRC (__fastcall * PFNIEMOP)(PVMCPUCC pVCpu);
4077	typedef VBOXSTRICTRC (__fastcall * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4078	# define FNIEMOP_DEF(a_Name) \
4079	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
4080	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4081	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
4082	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4083	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
4084
4085	#elif defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
4086	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
4087	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4088	# define FNIEMOP_DEF(a_Name) \
4089	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu)
4090	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4091	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
4092	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4093	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
4094
4095	#else
4096	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
4097	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4098	# define FNIEMOP_DEF(a_Name) \
4099	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
4100	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4101	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
4102	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4103	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
4104
4105	#endif
4106	#define FNIEMOPRM_DEF(a_Name) FNIEMOP_DEF_1(a_Name, uint8_t, bRm)
4107
4108	/**
4109	* Call an opcode decoder function.
4110	*
4111	* We're using macors for this so that adding and removing parameters can be
4112	* done as we please. See FNIEMOP_DEF.
4113	*/
4114	#define FNIEMOP_CALL(a_pfn) (a_pfn)(pVCpu)
4115
4116	/**
4117	* Call a common opcode decoder function taking one extra argument.
4118	*
4119	* We're using macors for this so that adding and removing parameters can be
4120	* done as we please. See FNIEMOP_DEF_1.
4121	*/
4122	#define FNIEMOP_CALL_1(a_pfn, a0) (a_pfn)(pVCpu, a0)
4123
4124	/**
4125	* Call a common opcode decoder function taking one extra argument.
4126	*
4127	* We're using macors for this so that adding and removing parameters can be
4128	* done as we please. See FNIEMOP_DEF_1.
4129	*/
4130	#define FNIEMOP_CALL_2(a_pfn, a0, a1) (a_pfn)(pVCpu, a0, a1)
4131	/** @} */
4132
4133
4134	/** @name Misc Helpers
4135	* @{ */
4136
4137	/** Used to shut up GCC warnings about variables that 'may be used uninitialized'
4138	* due to GCC lacking knowledge about the value range of a switch. */
4139	#if RT_CPLUSPLUS_PREREQ(202000)
4140	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: [[unlikely]] AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
4141	#else
4142	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
4143	#endif
4144
4145	/** Variant of IEM_NOT_REACHED_DEFAULT_CASE_RET that returns a custom value. */
4146	#if RT_CPLUSPLUS_PREREQ(202000)
4147	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: [[unlikely]] AssertFailedReturn(a_RetValue)
4148	#else
4149	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: AssertFailedReturn(a_RetValue)
4150	#endif
4151
4152	/**
4153	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
4154	* occation.
4155	*/
4156	#ifdef LOG_ENABLED
4157	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
4158	do { \
4159	/Log/ LogAlways(("%s: returning IEM_RETURN_ASPECT_NOT_IMPLEMENTED (line %d)\n", __FUNCTION__, __LINE__)); \
4160	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
4161	} while (0)
4162	#else
4163	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
4164	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
4165	#endif
4166
4167	/**
4168	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
4169	* occation using the supplied logger statement.
4170	*
4171	* @param a_LoggerArgs What to log on failure.
4172	*/
4173	#ifdef LOG_ENABLED
4174	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
4175	do { \
4176	LogAlways((LOG_FN_FMT ": ", __PRETTY_FUNCTION__)); LogAlways(a_LoggerArgs); \
4177	/LogFunc(a_LoggerArgs);/ \
4178	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
4179	} while (0)
4180	#else
4181	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
4182	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
4183	#endif
4184
4185	/**
4186	* Gets the CPU mode (from fExec) as a IEMMODE value.
4187	*
4188	* @returns IEMMODE
4189	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4190	*/
4191	#define IEM_GET_CPU_MODE(a_pVCpu) ((a_pVCpu)->iem.s.fExec & IEM_F_MODE_CPUMODE_MASK)
4192
4193	/**
4194	* Check if we're currently executing in real or virtual 8086 mode.
4195	*
4196	* @returns @c true if it is, @c false if not.
4197	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4198	*/
4199	#define IEM_IS_REAL_OR_V86_MODE(a_pVCpu) (( ((a_pVCpu)->iem.s.fExec ^ IEM_F_MODE_X86_PROT_MASK) \
4200	& (IEM_F_MODE_X86_V86_MASK \| IEM_F_MODE_X86_PROT_MASK)) != 0)
4201
4202	/**
4203	* Check if we're currently executing in virtual 8086 mode.
4204	*
4205	* @returns @c true if it is, @c false if not.
4206	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4207	*/
4208	#define IEM_IS_V86_MODE(a_pVCpu) (((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_V86_MASK) != 0)
4209
4210	/**
4211	* Check if we're currently executing in long mode.
4212	*
4213	* @returns @c true if it is, @c false if not.
4214	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4215	*/
4216	#define IEM_IS_LONG_MODE(a_pVCpu) (CPUMIsGuestInLongModeEx(IEM_GET_CTX(a_pVCpu)))
4217
4218	/**
4219	* Check if we're currently executing in a 16-bit code segment.
4220	*
4221	* @returns @c true if it is, @c false if not.
4222	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4223	*/
4224	#define IEM_IS_16BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_16BIT)
4225
4226	/**
4227	* Check if we're currently executing in a 32-bit code segment.
4228	*
4229	* @returns @c true if it is, @c false if not.
4230	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4231	*/
4232	#define IEM_IS_32BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_32BIT)
4233
4234	/**
4235	* Check if we're currently executing in a 64-bit code segment.
4236	*
4237	* @returns @c true if it is, @c false if not.
4238	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4239	*/
4240	#define IEM_IS_64BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_64BIT)
4241
4242	/**
4243	* Check if we're currently executing in real mode.
4244	*
4245	* @returns @c true if it is, @c false if not.
4246	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4247	*/
4248	#define IEM_IS_REAL_MODE(a_pVCpu) (!((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_PROT_MASK))
4249
4250	/**
4251	* Gets the current protection level (CPL).
4252	*
4253	* @returns 0..3
4254	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4255	*/
4256	#define IEM_GET_CPL(a_pVCpu) (((a_pVCpu)->iem.s.fExec >> IEM_F_X86_CPL_SHIFT) & IEM_F_X86_CPL_SMASK)
4257
4258	/**
4259	* Sets the current protection level (CPL).
4260	*
4261	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4262	*/
4263	#define IEM_SET_CPL(a_pVCpu, a_uCpl) \
4264	do { (a_pVCpu)->iem.s.fExec = ((a_pVCpu)->iem.s.fExec & ~IEM_F_X86_CPL_MASK) \| ((a_uCpl) << IEM_F_X86_CPL_SHIFT); } while (0)
4265
4266	/**
4267	* Returns a (const) pointer to the CPUMFEATURES for the guest CPU.
4268	* @returns PCCPUMFEATURES
4269	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4270	*/
4271	#define IEM_GET_GUEST_CPU_FEATURES(a_pVCpu) (&((a_pVCpu)->CTX_SUFF(pVM)->cpum.ro.GuestFeatures))
4272
4273	/**
4274	* Returns a (const) pointer to the CPUMFEATURES for the host CPU.
4275	* @returns PCCPUMFEATURES
4276	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4277	*/
4278	#define IEM_GET_HOST_CPU_FEATURES(a_pVCpu) (&g_CpumHostFeatures.s)
4279
4280	/**
4281	* Evaluates to true if we're presenting an Intel CPU to the guest.
4282	*/
4283	#define IEM_IS_GUEST_CPU_INTEL(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL )
4284
4285	/**
4286	* Evaluates to true if we're presenting an AMD CPU to the guest.
4287	*/
4288	#define IEM_IS_GUEST_CPU_AMD(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_AMD \|\| (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_HYGON )
4289
4290	/**
4291	* Check if the address is canonical.
4292	*/
4293	#define IEM_IS_CANONICAL(a_u64Addr) X86_IS_CANONICAL(a_u64Addr)
4294
4295	/** Checks if the ModR/M byte is in register mode or not. */
4296	#define IEM_IS_MODRM_REG_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT) )
4297	/** Checks if the ModR/M byte is in memory mode or not. */
4298	#define IEM_IS_MODRM_MEM_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT) )
4299
4300	/**
4301	* Gets the register (reg) part of a ModR/M encoding, with REX.R added in.
4302	*
4303	* For use during decoding.
4304	*/
4305	#define IEM_GET_MODRM_REG(a_pVCpu, a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| (a_pVCpu)->iem.s.uRexReg )
4306	/**
4307	* Gets the r/m part of a ModR/M encoding as a register index, with REX.B added in.
4308	*
4309	* For use during decoding.
4310	*/
4311	#define IEM_GET_MODRM_RM(a_pVCpu, a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) \| (a_pVCpu)->iem.s.uRexB )
4312
4313	/**
4314	* Gets the register (reg) part of a ModR/M encoding, without REX.R.
4315	*
4316	* For use during decoding.
4317	*/
4318	#define IEM_GET_MODRM_REG_8(a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) )
4319	/**
4320	* Gets the r/m part of a ModR/M encoding as a register index, without REX.B.
4321	*
4322	* For use during decoding.
4323	*/
4324	#define IEM_GET_MODRM_RM_8(a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) )
4325
4326	/**
4327	* Gets the register (reg) part of a ModR/M encoding as an extended 8-bit
4328	* register index, with REX.R added in.
4329	*
4330	* For use during decoding.
4331	*
4332	* @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
4333	*/
4334	#define IEM_GET_MODRM_REG_EX8(a_pVCpu, a_bRm) \
4335	( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
4336	\|\| !((a_bRm) & (4 << X86_MODRM_REG_SHIFT)) /* IEM_GET_MODRM_REG(pVCpu, a_bRm) < 4 */ \
4337	? IEM_GET_MODRM_REG(pVCpu, a_bRm) : (((a_bRm) >> X86_MODRM_REG_SHIFT) & 3) \| 16)
4338	/**
4339	* Gets the r/m part of a ModR/M encoding as an extended 8-bit register index,
4340	* with REX.B added in.
4341	*
4342	* For use during decoding.
4343	*
4344	* @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
4345	*/
4346	#define IEM_GET_MODRM_RM_EX8(a_pVCpu, a_bRm) \
4347	( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
4348	\|\| !((a_bRm) & 4) /* IEM_GET_MODRM_RM(pVCpu, a_bRm) < 4 */ \
4349	? IEM_GET_MODRM_RM(pVCpu, a_bRm) : ((a_bRm) & 3) \| 16)
4350
4351	/**
4352	* Combines the prefix REX and ModR/M byte for passing to
4353	* iemOpHlpCalcRmEffAddrThreadedAddr64().
4354	*
4355	* @returns The ModRM byte but with bit 3 set to REX.B and bit 4 to REX.X.
4356	* The two bits are part of the REG sub-field, which isn't needed in
4357	* iemOpHlpCalcRmEffAddrThreadedAddr64().
4358	*
4359	* For use during decoding/recompiling.
4360	*/
4361	#define IEM_GET_MODRM_EX(a_pVCpu, a_bRm) \
4362	( ((a_bRm) & ~X86_MODRM_REG_MASK) \
4363	\| (uint8_t)( (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X)) >> (26 - 3) ) )
4364	AssertCompile(IEM_OP_PRF_REX_B == RT_BIT_32(26));
4365	AssertCompile(IEM_OP_PRF_REX_X == RT_BIT_32(27));
4366
4367	/**
4368	* Gets the effective VEX.VVVV value.
4369	*
4370	* The 4th bit is ignored if not 64-bit code.
4371	* @returns effective V-register value.
4372	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4373	*/
4374	#define IEM_GET_EFFECTIVE_VVVV(a_pVCpu) \
4375	(IEM_IS_64BIT_CODE(a_pVCpu) ? (a_pVCpu)->iem.s.uVex3rdReg : (a_pVCpu)->iem.s.uVex3rdReg & 7)
4376
4377
4378	/**
4379	* Checks if we're executing inside an AMD-V or VT-x guest.
4380	*/
4381	#if defined(VBOX_WITH_NESTED_HWVIRT_VMX) \|\| defined(VBOX_WITH_NESTED_HWVIRT_SVM)
4382	# define IEM_IS_IN_GUEST(a_pVCpu) RT_BOOL((a_pVCpu)->iem.s.fExec & IEM_F_X86_CTX_IN_GUEST)
4383	#else
4384	# define IEM_IS_IN_GUEST(a_pVCpu) false
4385	#endif
4386
4387
4388	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
4389
4390	/**
4391	* Check if the guest has entered VMX root operation.
4392	*/
4393	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxRootMode(IEM_GET_CTX(a_pVCpu)))
4394
4395	/**
4396	* Check if the guest has entered VMX non-root operation.
4397	*/
4398	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) ( ((a_pVCpu)->iem.s.fExec & (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST)) \
4399	== (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST) )
4400
4401	/**
4402	* Check if the nested-guest has the given Pin-based VM-execution control set.
4403	*/
4404	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_PinCtl) (CPUMIsGuestVmxPinCtlsSet(IEM_GET_CTX(a_pVCpu), (a_PinCtl)))
4405
4406	/**
4407	* Check if the nested-guest has the given Processor-based VM-execution control set.
4408	*/
4409	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_ProcCtl) (CPUMIsGuestVmxProcCtlsSet(IEM_GET_CTX(a_pVCpu), (a_ProcCtl)))
4410
4411	/**
4412	* Check if the nested-guest has the given Secondary Processor-based VM-execution
4413	* control set.
4414	*/
4415	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_ProcCtl2) (CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(a_pVCpu), (a_ProcCtl2)))
4416
4417	/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
4418	# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
4419
4420	/** Whether a shadow VMCS is present for the given VCPU. */
4421	# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
4422
4423	/** Gets the VMXON region pointer. */
4424	# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
4425
4426	/** Gets the guest-physical address of the current VMCS for the given VCPU. */
4427	# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
4428
4429	/** Whether a current VMCS is present for the given VCPU. */
4430	# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
4431
4432	/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
4433	# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
4434	do \
4435	{ \
4436	Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
4437	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
4438	} while (0)
4439
4440	/** Clears any current VMCS for the given VCPU. */
4441	# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
4442	do \
4443	{ \
4444	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
4445	} while (0)
4446
4447	/**
4448	* Invokes the VMX VM-exit handler for an instruction intercept.
4449	*/
4450	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) \
4451	do { return iemVmxVmexitInstr((a_pVCpu), (a_uExitReason), (a_cbInstr)); } while (0)
4452
4453	/**
4454	* Invokes the VMX VM-exit handler for an instruction intercept where the
4455	* instruction provides additional VM-exit information.
4456	*/
4457	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) \
4458	do { return iemVmxVmexitInstrNeedsInfo((a_pVCpu), (a_uExitReason), (a_uInstrId), (a_cbInstr)); } while (0)
4459
4460	/**
4461	* Invokes the VMX VM-exit handler for a task switch.
4462	*/
4463	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) \
4464	do { return iemVmxVmexitTaskSwitch((a_pVCpu), (a_enmTaskSwitch), (a_SelNewTss), (a_cbInstr)); } while (0)
4465
4466	/**
4467	* Invokes the VMX VM-exit handler for MWAIT.
4468	*/
4469	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) \
4470	do { return iemVmxVmexitInstrMwait((a_pVCpu), (a_fMonitorArmed), (a_cbInstr)); } while (0)
4471
4472	/**
4473	* Invokes the VMX VM-exit handler for EPT faults.
4474	*/
4475	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) \
4476	do { return iemVmxVmexitEpt(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr); } while (0)
4477
4478	/**
4479	* Invokes the VMX VM-exit handler.
4480	*/
4481	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) \
4482	do { return iemVmxVmexit((a_pVCpu), (a_uExitReason), (a_uExitQual)); } while (0)
4483
4484	#else
4485	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (false)
4486	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (false)
4487	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_cbInstr) (false)
4488	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_cbInstr) (false)
4489	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_cbInstr) (false)
4490	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4491	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4492	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4493	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4494	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4495	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) do { return VERR_VMX_IPE_1; } while (0)
4496
4497	#endif
4498
4499	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4500	/**
4501	* Checks if we're executing a guest using AMD-V.
4502	*/
4503	# define IEM_SVM_IS_IN_GUEST(a_pVCpu) ( (a_pVCpu->iem.s.fExec & (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST)) \
4504	== (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST))
4505	/**
4506	* Check if an SVM control/instruction intercept is set.
4507	*/
4508	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) \
4509	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmCtrlInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_Intercept)))
4510
4511	/**
4512	* Check if an SVM read CRx intercept is set.
4513	*/
4514	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
4515	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
4516
4517	/**
4518	* Check if an SVM write CRx intercept is set.
4519	*/
4520	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
4521	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
4522
4523	/**
4524	* Check if an SVM read DRx intercept is set.
4525	*/
4526	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
4527	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
4528
4529	/**
4530	* Check if an SVM write DRx intercept is set.
4531	*/
4532	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
4533	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
4534
4535	/**
4536	* Check if an SVM exception intercept is set.
4537	*/
4538	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) \
4539	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmXcptInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uVector)))
4540
4541	/**
4542	* Invokes the SVM \#VMEXIT handler for the nested-guest.
4543	*/
4544	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
4545	do { return iemSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2)); } while (0)
4546
4547	/**
4548	* Invokes the 'MOV CRx' SVM \#VMEXIT handler after constructing the
4549	* corresponding decode assist information.
4550	*/
4551	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) \
4552	do \
4553	{ \
4554	uint64_t uExitInfo1; \
4555	if ( IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmDecodeAssists \
4556	&& (a_enmAccessCrX) == IEMACCESSCRX_MOV_CRX) \
4557	uExitInfo1 = SVM_EXIT1_MOV_CRX_MASK \| ((a_iGReg) & 7); \
4558	else \
4559	uExitInfo1 = 0; \
4560	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, uExitInfo1, 0); \
4561	} while (0)
4562
4563	/** Check and handles SVM nested-guest instruction intercept and updates
4564	* NRIP if needed.
4565	*/
4566	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
4567	do \
4568	{ \
4569	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept)) \
4570	{ \
4571	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
4572	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2); \
4573	} \
4574	} while (0)
4575
4576	/** Checks and handles SVM nested-guest CR0 read intercept. */
4577	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
4578	do \
4579	{ \
4580	if (!IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, 0)) \
4581	{ /* probably likely */ } \
4582	else \
4583	{ \
4584	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
4585	IEM_SVM_VMEXIT_RET(a_pVCpu, SVM_EXIT_READ_CR0, a_uExitInfo1, a_uExitInfo2); \
4586	} \
4587	} while (0)
4588
4589	/**
4590	* Updates the NextRIP (NRI) field in the nested-guest VMCB.
4591	*/
4592	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) \
4593	do { \
4594	if (IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmNextRipSave) \
4595	CPUMGuestSvmUpdateNRip(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_cbInstr)); \
4596	} while (0)
4597
4598	#else
4599	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) (false)
4600	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
4601	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
4602	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
4603	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
4604	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) (false)
4605	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { return VERR_SVM_IPE_1; } while (0)
4606	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) do { return VERR_SVM_IPE_1; } while (0)
4607	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, \
4608	a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
4609	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
4610	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) do { } while (0)
4611
4612	#endif
4613
4614	/** @} */
4615
4616	uint32_t iemCalcExecDbgFlagsSlow(PVMCPUCC pVCpu);
4617	VBOXSTRICTRC iemExecInjectPendingTrap(PVMCPUCC pVCpu);
4618
4619
4620	/**
4621	* Selector descriptor table entry as fetched by iemMemFetchSelDesc.
4622	*/
4623	typedef union IEMSELDESC
4624	{
4625	/** The legacy view. */
4626	X86DESC Legacy;
4627	/** The long mode view. */
4628	X86DESC64 Long;
4629	} IEMSELDESC;
4630	/** Pointer to a selector descriptor table entry. */
4631	typedef IEMSELDESC *PIEMSELDESC;
4632
4633	/** @name Raising Exceptions.
4634	* @{ */
4635	VBOXSTRICTRC iemTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, uint32_t uNextEip, uint32_t fFlags,
4636	uint16_t uErr, uint64_t uCr2, RTSEL SelTSS, PIEMSELDESC pNewDescTSS) RT_NOEXCEPT;
4637
4638	VBOXSTRICTRC iemRaiseXcptOrInt(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags,
4639	uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
4640	#ifdef IEM_WITH_SETJMP
4641	DECL_NO_RETURN(void) iemRaiseXcptOrIntJmp(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector,
4642	uint32_t fFlags, uint16_t uErr, uint64_t uCr2) IEM_NOEXCEPT_MAY_LONGJMP;
4643	#endif
4644	VBOXSTRICTRC iemRaiseDivideError(PVMCPUCC pVCpu) RT_NOEXCEPT;
4645	VBOXSTRICTRC iemRaiseDebugException(PVMCPUCC pVCpu) RT_NOEXCEPT;
4646	VBOXSTRICTRC iemRaiseBoundRangeExceeded(PVMCPUCC pVCpu) RT_NOEXCEPT;
4647	VBOXSTRICTRC iemRaiseUndefinedOpcode(PVMCPUCC pVCpu) RT_NOEXCEPT;
4648	VBOXSTRICTRC iemRaiseDeviceNotAvailable(PVMCPUCC pVCpu) RT_NOEXCEPT;
4649	VBOXSTRICTRC iemRaiseTaskSwitchFaultWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
4650	VBOXSTRICTRC iemRaiseTaskSwitchFaultCurrentTSS(PVMCPUCC pVCpu) RT_NOEXCEPT;
4651	VBOXSTRICTRC iemRaiseTaskSwitchFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
4652	VBOXSTRICTRC iemRaiseTaskSwitchFaultBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
4653	/VBOXSTRICTRC iemRaiseSelectorNotPresent(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;/
4654	VBOXSTRICTRC iemRaiseSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
4655	VBOXSTRICTRC iemRaiseSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
4656	VBOXSTRICTRC iemRaiseStackSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
4657	VBOXSTRICTRC iemRaiseStackSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
4658	VBOXSTRICTRC iemRaiseGeneralProtectionFault(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
4659	VBOXSTRICTRC iemRaiseGeneralProtectionFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
4660	#ifdef IEM_WITH_SETJMP
4661	DECL_NO_RETURN(void) iemRaiseGeneralProtectionFault0Jmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4662	#endif
4663	VBOXSTRICTRC iemRaiseGeneralProtectionFaultBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
4664	VBOXSTRICTRC iemRaiseNotCanonical(PVMCPUCC pVCpu) RT_NOEXCEPT;
4665	VBOXSTRICTRC iemRaiseSelectorBounds(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
4666	#ifdef IEM_WITH_SETJMP
4667	DECL_NO_RETURN(void) iemRaiseSelectorBoundsJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
4668	#endif
4669	VBOXSTRICTRC iemRaiseSelectorBoundsBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
4670	#ifdef IEM_WITH_SETJMP
4671	DECL_NO_RETURN(void) iemRaiseSelectorBoundsBySelectorJmp(PVMCPUCC pVCpu, RTSEL Sel) IEM_NOEXCEPT_MAY_LONGJMP;
4672	#endif
4673	VBOXSTRICTRC iemRaiseSelectorInvalidAccess(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
4674	#ifdef IEM_WITH_SETJMP
4675	DECL_NO_RETURN(void) iemRaiseSelectorInvalidAccessJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
4676	#endif
4677	VBOXSTRICTRC iemRaisePageFault(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) RT_NOEXCEPT;
4678	#ifdef IEM_WITH_SETJMP
4679	DECL_NO_RETURN(void) iemRaisePageFaultJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) IEM_NOEXCEPT_MAY_LONGJMP;
4680	#endif
4681	VBOXSTRICTRC iemRaiseMathFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
4682	VBOXSTRICTRC iemRaiseAlignmentCheckException(PVMCPUCC pVCpu) RT_NOEXCEPT;
4683	#ifdef IEM_WITH_SETJMP
4684	DECL_NO_RETURN(void) iemRaiseAlignmentCheckExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4685	#endif
4686	VBOXSTRICTRC iemRaiseSimdFpException(PVMCPUCC pVCpu) RT_NOEXCEPT;
4687
4688	void iemLogSyscallProtModeInt(PVMCPUCC pVCpu, uint8_t u8Vector, uint8_t cbInstr);
4689
4690	IEM_CIMPL_DEF_0(iemCImplRaiseDivideError);
4691	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidLockPrefix);
4692	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidOpcode);
4693
4694	/**
4695	* Macro for calling iemCImplRaiseDivideError().
4696	*
4697	* This is for things that will _always_ decode to an \#DE, taking the
4698	* recompiler into consideration and everything.
4699	*
4700	* @return Strict VBox status code.
4701	*/
4702	#define IEMOP_RAISE_DIVIDE_ERROR_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, iemCImplRaiseDivideError)
4703
4704	/**
4705	* Macro for calling iemCImplRaiseInvalidLockPrefix().
4706	*
4707	* This is for things that will _always_ decode to an \#UD, taking the
4708	* recompiler into consideration and everything.
4709	*
4710	* @return Strict VBox status code.
4711	*/
4712	#define IEMOP_RAISE_INVALID_LOCK_PREFIX_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, iemCImplRaiseInvalidLockPrefix)
4713
4714	/**
4715	* Macro for calling iemCImplRaiseInvalidOpcode() for decode/static \#UDs.
4716	*
4717	* This is for things that will _always_ decode to an \#UD, taking the
4718	* recompiler into consideration and everything.
4719	*
4720	* @return Strict VBox status code.
4721	*/
4722	#define IEMOP_RAISE_INVALID_OPCODE_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, iemCImplRaiseInvalidOpcode)
4723
4724	/**
4725	* Macro for calling iemCImplRaiseInvalidOpcode() for runtime-style \#UDs.
4726	*
4727	* Using this macro means you've got _buggy_ _code_ and are doing things that
4728	* belongs exclusively in IEMAllCImpl.cpp during decoding.
4729	*
4730	* @return Strict VBox status code.
4731	* @see IEMOP_RAISE_INVALID_OPCODE_RET
4732	*/
4733	#define IEMOP_RAISE_INVALID_OPCODE_RUNTIME_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, iemCImplRaiseInvalidOpcode)
4734
4735	/** @} */
4736
4737	/** @name Register Access.
4738	* @{ */
4739	VBOXSTRICTRC iemRegRipRelativeJumpS8AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int8_t offNextInstr,
4740	IEMMODE enmEffOpSize) RT_NOEXCEPT;
4741	VBOXSTRICTRC iemRegRipRelativeJumpS16AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int16_t offNextInstr) RT_NOEXCEPT;
4742	VBOXSTRICTRC iemRegRipRelativeJumpS32AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int32_t offNextInstr,
4743	IEMMODE enmEffOpSize) RT_NOEXCEPT;
4744	VBOXSTRICTRC iemRegRipJumpU16AndFinishClearningRF(PVMCPUCC pVCpu, uint16_t uNewRip) RT_NOEXCEPT;
4745	VBOXSTRICTRC iemRegRipJumpU32AndFinishClearningRF(PVMCPUCC pVCpu, uint32_t uNewRip) RT_NOEXCEPT;
4746	VBOXSTRICTRC iemRegRipJumpU64AndFinishClearningRF(PVMCPUCC pVCpu, uint64_t uNewRip) RT_NOEXCEPT;
4747	/** @} */
4748
4749	/** @name FPU access and helpers.
4750	* @{ */
4751	void iemFpuPushResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
4752	void iemFpuPushResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4753	void iemFpuPushResultTwo(PVMCPUCC pVCpu, PIEMFPURESULTTWO pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
4754	void iemFpuStoreResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
4755	void iemFpuStoreResultThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
4756	void iemFpuStoreResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
4757	uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4758	void iemFpuStoreResultWithMemOpThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
4759	uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4760	void iemFpuUpdateOpcodeAndIp(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
4761	void iemFpuUpdateFSW(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
4762	void iemFpuUpdateFSWThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
4763	void iemFpuUpdateFSWWithMemOp(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4764	void iemFpuUpdateFSWThenPopPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
4765	void iemFpuUpdateFSWWithMemOpThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4766	void iemFpuStackUnderflow(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
4767	void iemFpuStackUnderflowWithMemOp(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4768	void iemFpuStackUnderflowThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
4769	void iemFpuStackUnderflowWithMemOpThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4770	void iemFpuStackUnderflowThenPopPop(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
4771	void iemFpuStackPushUnderflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
4772	void iemFpuStackPushUnderflowTwo(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
4773	void iemFpuStackPushOverflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
4774	void iemFpuStackPushOverflowWithMemOp(PVMCPUCC pVCpu, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4775	/** @} */
4776
4777	/** @name SSE+AVX SIMD access and helpers.
4778	* @{ */
4779	void iemSseStoreResult(PVMCPUCC pVCpu, PCIEMSSERESULT pResult, uint8_t iXmmReg) RT_NOEXCEPT;
4780	void iemSseUpdateMxcsr(PVMCPUCC pVCpu, uint32_t fMxcsr) RT_NOEXCEPT;
4781	/** @} */
4782
4783	/** @name Memory access.
4784	* @{ */
4785
4786	/** Report a \#GP instead of \#AC and do not restrict to ring-3 */
4787	#define IEM_MEMMAP_F_ALIGN_GP RT_BIT_32(16)
4788	/** SSE access that should report a \#GP instead of \#AC, unless MXCSR.MM=1
4789	* when it works like normal \#AC. Always used with IEM_MEMMAP_F_ALIGN_GP. */
4790	#define IEM_MEMMAP_F_ALIGN_SSE RT_BIT_32(17)
4791	/** If \#AC is applicable, raise it. Always used with IEM_MEMMAP_F_ALIGN_GP.
4792	* Users include FXSAVE & FXRSTOR. */
4793	#define IEM_MEMMAP_F_ALIGN_GP_OR_AC RT_BIT_32(18)
4794
4795	VBOXSTRICTRC iemMemMap(PVMCPUCC pVCpu, void **ppvMem, size_t cbMem, uint8_t iSegReg, RTGCPTR GCPtrMem,
4796	uint32_t fAccess, uint32_t uAlignCtl) RT_NOEXCEPT;
4797	VBOXSTRICTRC iemMemCommitAndUnmap(PVMCPUCC pVCpu, void *pvMem, uint32_t fAccess) RT_NOEXCEPT;
4798	#ifndef IN_RING3
4799	VBOXSTRICTRC iemMemCommitAndUnmapPostponeTroubleToR3(PVMCPUCC pVCpu, void *pvMem, uint32_t fAccess) RT_NOEXCEPT;
4800	#endif
4801	void iemMemRollback(PVMCPUCC pVCpu) RT_NOEXCEPT;
4802	VBOXSTRICTRC iemMemApplySegment(PVMCPUCC pVCpu, uint32_t fAccess, uint8_t iSegReg, size_t cbMem, PRTGCPTR pGCPtrMem) RT_NOEXCEPT;
4803	VBOXSTRICTRC iemMemMarkSelDescAccessed(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
4804	VBOXSTRICTRC iemMemPageTranslateAndCheckAccess(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t cbAccess, uint32_t fAccess, PRTGCPHYS pGCPhysMem) RT_NOEXCEPT;
4805
4806	void iemOpcodeFlushLight(PVMCPUCC pVCpu, uint8_t cbInstr);
4807	void iemOpcodeFlushHeavy(PVMCPUCC pVCpu, uint8_t cbInstr);
4808	#ifdef IEM_WITH_CODE_TLB
4809	void iemOpcodeFetchBytesJmp(PVMCPUCC pVCpu, size_t cbDst, void *pvDst) IEM_NOEXCEPT_MAY_LONGJMP;
4810	#else
4811	VBOXSTRICTRC iemOpcodeFetchMoreBytes(PVMCPUCC pVCpu, size_t cbMin) RT_NOEXCEPT;
4812	#endif
4813	#ifdef IEM_WITH_SETJMP
4814	uint8_t iemOpcodeGetNextU8SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4815	uint16_t iemOpcodeGetNextU16SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4816	uint32_t iemOpcodeGetNextU32SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4817	uint64_t iemOpcodeGetNextU64SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4818	#else
4819	VBOXSTRICTRC iemOpcodeGetNextU8Slow(PVMCPUCC pVCpu, uint8_t *pb) RT_NOEXCEPT;
4820	VBOXSTRICTRC iemOpcodeGetNextS8SxU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
4821	VBOXSTRICTRC iemOpcodeGetNextS8SxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
4822	VBOXSTRICTRC iemOpcodeGetNextS8SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
4823	VBOXSTRICTRC iemOpcodeGetNextU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
4824	VBOXSTRICTRC iemOpcodeGetNextU16ZxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
4825	VBOXSTRICTRC iemOpcodeGetNextU16ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
4826	VBOXSTRICTRC iemOpcodeGetNextU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
4827	VBOXSTRICTRC iemOpcodeGetNextU32ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
4828	VBOXSTRICTRC iemOpcodeGetNextS32SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
4829	VBOXSTRICTRC iemOpcodeGetNextU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
4830	#endif
4831
4832	VBOXSTRICTRC iemMemFetchDataU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4833	VBOXSTRICTRC iemMemFetchDataU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4834	VBOXSTRICTRC iemMemFetchDataU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4835	VBOXSTRICTRC iemMemFetchDataU32_ZX_U64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4836	VBOXSTRICTRC iemMemFetchDataU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4837	VBOXSTRICTRC iemMemFetchDataU64AlignedU128(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4838	VBOXSTRICTRC iemMemFetchDataR80(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4839	VBOXSTRICTRC iemMemFetchDataD80(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4840	VBOXSTRICTRC iemMemFetchDataU128(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4841	VBOXSTRICTRC iemMemFetchDataU128AlignedSse(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4842	VBOXSTRICTRC iemMemFetchDataU256(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4843	VBOXSTRICTRC iemMemFetchDataU256AlignedSse(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4844	VBOXSTRICTRC iemMemFetchDataXdtr(PVMCPUCC pVCpu, uint16_t *pcbLimit, PRTGCPTR pGCPtrBase, uint8_t iSegReg,
4845	RTGCPTR GCPtrMem, IEMMODE enmOpSize) RT_NOEXCEPT;
4846	#ifdef IEM_WITH_SETJMP
4847	uint8_t iemMemFetchDataU8SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4848	uint16_t iemMemFetchDataU16SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4849	uint32_t iemMemFetchDataU32SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4850	uint32_t iemMemFlatFetchDataU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4851	uint64_t iemMemFetchDataU64SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4852	uint64_t iemMemFetchDataU64AlignedU128SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4853	void iemMemFetchDataR80SafeJmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4854	void iemMemFetchDataD80SafeJmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4855	void iemMemFetchDataU128SafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4856	void iemMemFetchDataU128AlignedSseSafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4857	void iemMemFetchDataU256SafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4858	void iemMemFetchDataU256AlignedSseSafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4859	# if 0 /* these are inlined now */
4860	uint8_t iemMemFetchDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4861	uint16_t iemMemFetchDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4862	uint32_t iemMemFetchDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4863	uint32_t iemMemFlatFetchDataU32Jmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4864	uint64_t iemMemFetchDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4865	uint64_t iemMemFetchDataU64AlignedU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4866	# endif
4867	void iemMemFetchDataR80Jmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4868	void iemMemFetchDataD80Jmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4869	void iemMemFetchDataU128Jmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4870	void iemMemFetchDataU128AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4871	void iemMemFetchDataU256Jmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4872	void iemMemFetchDataU256AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4873	#endif
4874
4875	VBOXSTRICTRC iemMemFetchSysU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4876	VBOXSTRICTRC iemMemFetchSysU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4877	VBOXSTRICTRC iemMemFetchSysU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4878	VBOXSTRICTRC iemMemFetchSysU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4879	VBOXSTRICTRC iemMemFetchSelDesc(PVMCPUCC pVCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt) RT_NOEXCEPT;
4880
4881	VBOXSTRICTRC iemMemStoreDataU8(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) RT_NOEXCEPT;
4882	VBOXSTRICTRC iemMemStoreDataU16(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) RT_NOEXCEPT;
4883	VBOXSTRICTRC iemMemStoreDataU32(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) RT_NOEXCEPT;
4884	VBOXSTRICTRC iemMemStoreDataU64(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) RT_NOEXCEPT;
4885	VBOXSTRICTRC iemMemStoreDataU128(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
4886	VBOXSTRICTRC iemMemStoreDataU128AlignedSse(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
4887	VBOXSTRICTRC iemMemStoreDataU256(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
4888	VBOXSTRICTRC iemMemStoreDataU256AlignedAvx(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
4889	VBOXSTRICTRC iemMemStoreDataXdtr(PVMCPUCC pVCpu, uint16_t cbLimit, RTGCPTR GCPtrBase, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4890	#ifdef IEM_WITH_SETJMP
4891	void iemMemStoreDataU8SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
4892	void iemMemStoreDataU16SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
4893	void iemMemStoreDataU32SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
4894	void iemMemStoreDataU64SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
4895	void iemMemStoreDataU128SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
4896	void iemMemStoreDataU128AlignedSseSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
4897	void iemMemStoreDataU256SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
4898	void iemMemStoreDataU256AlignedAvxSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
4899	#if 0
4900	void iemMemStoreDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
4901	void iemMemStoreDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
4902	void iemMemStoreDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
4903	void iemMemStoreDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
4904	#endif
4905	void iemMemStoreDataU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
4906	void iemMemStoreDataU128AlignedSseJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
4907	void iemMemStoreDataU256Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
4908	void iemMemStoreDataU256AlignedAvxJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
4909	#endif
4910
4911	#ifdef IEM_WITH_SETJMP
4912	uint8_t iemMemMapDataU8RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4913	uint8_t iemMemMapDataU8WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4914	uint8_t const iemMemMapDataU8RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4915	uint16_t iemMemMapDataU16RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4916	uint16_t iemMemMapDataU16WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4917	uint16_t const iemMemMapDataU16RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4918	uint32_t iemMemMapDataU32RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4919	uint32_t iemMemMapDataU32WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4920	uint32_t const iemMemMapDataU32RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4921	uint64_t iemMemMapDataU64RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4922	uint64_t iemMemMapDataU64WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4923	uint64_t const iemMemMapDataU64RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4924
4925	void iemMemCommitAndUnmapRwSafeJmp(PVMCPUCC pVCpu, void *pvMem, uint8_t bMapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
4926	void iemMemCommitAndUnmapWoSafeJmp(PVMCPUCC pVCpu, void *pvMem, uint8_t bMapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
4927	void iemMemCommitAndUnmapRoSafeJmp(PVMCPUCC pVCpu, const void *pvMem, uint8_t bMapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
4928	#endif
4929
4930	VBOXSTRICTRC iemMemStackPushBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
4931	void *ppvMem, uint64_t puNewRsp) RT_NOEXCEPT;
4932	VBOXSTRICTRC iemMemStackPushCommitSpecial(PVMCPUCC pVCpu, void *pvMem, uint64_t uNewRsp) RT_NOEXCEPT;
4933	VBOXSTRICTRC iemMemStackPushU16(PVMCPUCC pVCpu, uint16_t u16Value) RT_NOEXCEPT;
4934	VBOXSTRICTRC iemMemStackPushU32(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
4935	VBOXSTRICTRC iemMemStackPushU64(PVMCPUCC pVCpu, uint64_t u64Value) RT_NOEXCEPT;
4936	VBOXSTRICTRC iemMemStackPushU16Ex(PVMCPUCC pVCpu, uint16_t u16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4937	VBOXSTRICTRC iemMemStackPushU32Ex(PVMCPUCC pVCpu, uint32_t u32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4938	VBOXSTRICTRC iemMemStackPushU64Ex(PVMCPUCC pVCpu, uint64_t u64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4939	VBOXSTRICTRC iemMemStackPushU32SReg(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
4940	VBOXSTRICTRC iemMemStackPopBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
4941	void const *ppvMem, uint64_t puNewRsp) RT_NOEXCEPT;
4942	VBOXSTRICTRC iemMemStackPopContinueSpecial(PVMCPUCC pVCpu, size_t off, size_t cbMem,
4943	void const **ppvMem, uint64_t uCurNewRsp) RT_NOEXCEPT;
4944	VBOXSTRICTRC iemMemStackPopDoneSpecial(PVMCPUCC pVCpu, void const *pvMem) RT_NOEXCEPT;
4945	VBOXSTRICTRC iemMemStackPopU16(PVMCPUCC pVCpu, uint16_t *pu16Value) RT_NOEXCEPT;
4946	VBOXSTRICTRC iemMemStackPopU32(PVMCPUCC pVCpu, uint32_t *pu32Value) RT_NOEXCEPT;
4947	VBOXSTRICTRC iemMemStackPopU64(PVMCPUCC pVCpu, uint64_t *pu64Value) RT_NOEXCEPT;
4948	VBOXSTRICTRC iemMemStackPopU16Ex(PVMCPUCC pVCpu, uint16_t *pu16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4949	VBOXSTRICTRC iemMemStackPopU32Ex(PVMCPUCC pVCpu, uint32_t *pu32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4950	VBOXSTRICTRC iemMemStackPopU64Ex(PVMCPUCC pVCpu, uint64_t *pu64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4951
4952	#ifdef IEM_WITH_SETJMP
4953	void iemMemStackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
4954	void iemMemStackPushU32SafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
4955	void iemMemStackPushU32SRegSafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
4956	void iemMemStackPushU64SafeJmp(PVMCPUCC pVCpu, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
4957	uint16_t iemMemStackPopU16SafeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4958	uint32_t iemMemStackPopU32SafeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4959	uint64_t iemMemStackPopU64SafeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4960
4961	void iemMemFlat32StackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
4962	void iemMemFlat32StackPushU32SafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
4963	void iemMemFlat32StackPushU32SRegSafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
4964	uint16_t iemMemFlat32StackPopU16SafeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4965	uint32_t iemMemFlat32StackPopU32SafeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4966
4967	void iemMemFlat64StackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
4968	void iemMemFlat64StackPushU64SafeJmp(PVMCPUCC pVCpu, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
4969	uint16_t iemMemFlat64StackPopU16SafeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4970	uint64_t iemMemFlat64StackPopU64SafeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4971	#endif
4972
4973	/** @} */
4974
4975	/** @name IEMAllCImpl.cpp
4976	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/'
4977	* @{ */
4978	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem16, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4979	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem32, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4980	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem64, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4981	IEM_CIMPL_PROTO_0(iemCImpl_popa_16);
4982	IEM_CIMPL_PROTO_0(iemCImpl_popa_32);
4983	IEM_CIMPL_PROTO_0(iemCImpl_pusha_16);
4984	IEM_CIMPL_PROTO_0(iemCImpl_pusha_32);
4985	IEM_CIMPL_PROTO_1(iemCImpl_pushf, IEMMODE, enmEffOpSize);
4986	IEM_CIMPL_PROTO_1(iemCImpl_popf, IEMMODE, enmEffOpSize);
4987	IEM_CIMPL_PROTO_1(iemCImpl_call_16, uint16_t, uNewPC);
4988	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_16, int16_t, offDisp);
4989	IEM_CIMPL_PROTO_1(iemCImpl_call_32, uint32_t, uNewPC);
4990	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_32, int32_t, offDisp);
4991	IEM_CIMPL_PROTO_1(iemCImpl_call_64, uint64_t, uNewPC);
4992	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_64, int64_t, offDisp);
4993	IEM_CIMPL_PROTO_3(iemCImpl_FarJmp, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
4994	IEM_CIMPL_PROTO_3(iemCImpl_callf, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
4995	typedef IEM_CIMPL_DECL_TYPE_3(FNIEMCIMPLFARBRANCH, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
4996	typedef FNIEMCIMPLFARBRANCH *PFNIEMCIMPLFARBRANCH;
4997	IEM_CIMPL_PROTO_2(iemCImpl_retf, IEMMODE, enmEffOpSize, uint16_t, cbPop);
4998	IEM_CIMPL_PROTO_0(iemCImpl_retn_16);
4999	IEM_CIMPL_PROTO_0(iemCImpl_retn_32);
5000	IEM_CIMPL_PROTO_0(iemCImpl_retn_64);
5001	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_16, uint16_t, cbPop);
5002	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_32, uint16_t, cbPop);
5003	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_64, uint16_t, cbPop);
5004	IEM_CIMPL_PROTO_3(iemCImpl_enter, IEMMODE, enmEffOpSize, uint16_t, cbFrame, uint8_t, cParameters);
5005	IEM_CIMPL_PROTO_1(iemCImpl_leave, IEMMODE, enmEffOpSize);
5006	IEM_CIMPL_PROTO_2(iemCImpl_int, uint8_t, u8Int, IEMINT, enmInt);
5007	IEM_CIMPL_PROTO_1(iemCImpl_iret_real_v8086, IEMMODE, enmEffOpSize);
5008	IEM_CIMPL_PROTO_4(iemCImpl_iret_prot_v8086, uint32_t, uNewEip, uint16_t, uNewCs, uint32_t, uNewFlags, uint64_t, uNewRsp);
5009	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot_NestedTask, IEMMODE, enmEffOpSize);
5010	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot, IEMMODE, enmEffOpSize);
5011	IEM_CIMPL_PROTO_1(iemCImpl_iret_64bit, IEMMODE, enmEffOpSize);
5012	IEM_CIMPL_PROTO_1(iemCImpl_iret, IEMMODE, enmEffOpSize);
5013	IEM_CIMPL_PROTO_0(iemCImpl_loadall286);
5014	IEM_CIMPL_PROTO_0(iemCImpl_syscall);
5015	IEM_CIMPL_PROTO_1(iemCImpl_sysret, IEMMODE, enmEffOpSize);
5016	IEM_CIMPL_PROTO_0(iemCImpl_sysenter);
5017	IEM_CIMPL_PROTO_1(iemCImpl_sysexit, IEMMODE, enmEffOpSize);
5018	IEM_CIMPL_PROTO_2(iemCImpl_LoadSReg, uint8_t, iSegReg, uint16_t, uSel);
5019	IEM_CIMPL_PROTO_2(iemCImpl_load_SReg, uint8_t, iSegReg, uint16_t, uSel);
5020	IEM_CIMPL_PROTO_2(iemCImpl_pop_Sreg, uint8_t, iSegReg, IEMMODE, enmEffOpSize);
5021	IEM_CIMPL_PROTO_5(iemCImpl_load_SReg_Greg, uint16_t, uSel, uint64_t, offSeg, uint8_t, iSegReg, uint8_t, iGReg, IEMMODE, enmEffOpSize);
5022	IEM_CIMPL_PROTO_2(iemCImpl_VerX, uint16_t, uSel, bool, fWrite);
5023	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u64, uint64_t *, pu64Dst, uint16_t, uSel, bool, fIsLar);
5024	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u16, uint16_t *, pu16Dst, uint16_t, uSel, bool, fIsLar);
5025	IEM_CIMPL_PROTO_3(iemCImpl_lgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
5026	IEM_CIMPL_PROTO_2(iemCImpl_sgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5027	IEM_CIMPL_PROTO_3(iemCImpl_lidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
5028	IEM_CIMPL_PROTO_2(iemCImpl_sidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5029	IEM_CIMPL_PROTO_1(iemCImpl_lldt, uint16_t, uNewLdt);
5030	IEM_CIMPL_PROTO_2(iemCImpl_sldt_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
5031	IEM_CIMPL_PROTO_2(iemCImpl_sldt_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5032	IEM_CIMPL_PROTO_1(iemCImpl_ltr, uint16_t, uNewTr);
5033	IEM_CIMPL_PROTO_2(iemCImpl_str_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
5034	IEM_CIMPL_PROTO_2(iemCImpl_str_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5035	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Cd, uint8_t, iGReg, uint8_t, iCrReg);
5036	IEM_CIMPL_PROTO_2(iemCImpl_smsw_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
5037	IEM_CIMPL_PROTO_2(iemCImpl_smsw_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5038	IEM_CIMPL_PROTO_4(iemCImpl_load_CrX, uint8_t, iCrReg, uint64_t, uNewCrX, IEMACCESSCRX, enmAccessCrX, uint8_t, iGReg);
5039	IEM_CIMPL_PROTO_2(iemCImpl_mov_Cd_Rd, uint8_t, iCrReg, uint8_t, iGReg);
5040	IEM_CIMPL_PROTO_2(iemCImpl_lmsw, uint16_t, u16NewMsw, RTGCPTR, GCPtrEffDst);
5041	IEM_CIMPL_PROTO_0(iemCImpl_clts);
5042	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Dd, uint8_t, iGReg, uint8_t, iDrReg);
5043	IEM_CIMPL_PROTO_2(iemCImpl_mov_Dd_Rd, uint8_t, iDrReg, uint8_t, iGReg);
5044	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Td, uint8_t, iGReg, uint8_t, iTrReg);
5045	IEM_CIMPL_PROTO_2(iemCImpl_mov_Td_Rd, uint8_t, iTrReg, uint8_t, iGReg);
5046	IEM_CIMPL_PROTO_1(iemCImpl_invlpg, RTGCPTR, GCPtrPage);
5047	IEM_CIMPL_PROTO_3(iemCImpl_invpcid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvpcidDesc, uint64_t, uInvpcidType);
5048	IEM_CIMPL_PROTO_0(iemCImpl_invd);
5049	IEM_CIMPL_PROTO_0(iemCImpl_wbinvd);
5050	IEM_CIMPL_PROTO_0(iemCImpl_rsm);
5051	IEM_CIMPL_PROTO_0(iemCImpl_rdtsc);
5052	IEM_CIMPL_PROTO_0(iemCImpl_rdtscp);
5053	IEM_CIMPL_PROTO_0(iemCImpl_rdpmc);
5054	IEM_CIMPL_PROTO_0(iemCImpl_rdmsr);
5055	IEM_CIMPL_PROTO_0(iemCImpl_wrmsr);
5056	IEM_CIMPL_PROTO_3(iemCImpl_in, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
5057	IEM_CIMPL_PROTO_2(iemCImpl_in_eAX_DX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
5058	IEM_CIMPL_PROTO_3(iemCImpl_out, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
5059	IEM_CIMPL_PROTO_2(iemCImpl_out_DX_eAX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
5060	IEM_CIMPL_PROTO_0(iemCImpl_cli);
5061	IEM_CIMPL_PROTO_0(iemCImpl_sti);
5062	IEM_CIMPL_PROTO_0(iemCImpl_hlt);
5063	IEM_CIMPL_PROTO_1(iemCImpl_monitor, uint8_t, iEffSeg);
5064	IEM_CIMPL_PROTO_0(iemCImpl_mwait);
5065	IEM_CIMPL_PROTO_0(iemCImpl_swapgs);
5066	IEM_CIMPL_PROTO_0(iemCImpl_cpuid);
5067	IEM_CIMPL_PROTO_1(iemCImpl_aad, uint8_t, bImm);
5068	IEM_CIMPL_PROTO_1(iemCImpl_aam, uint8_t, bImm);
5069	IEM_CIMPL_PROTO_0(iemCImpl_daa);
5070	IEM_CIMPL_PROTO_0(iemCImpl_das);
5071	IEM_CIMPL_PROTO_0(iemCImpl_aaa);
5072	IEM_CIMPL_PROTO_0(iemCImpl_aas);
5073	IEM_CIMPL_PROTO_3(iemCImpl_bound_16, int16_t, idxArray, int16_t, idxLowerBound, int16_t, idxUpperBound);
5074	IEM_CIMPL_PROTO_3(iemCImpl_bound_32, int32_t, idxArray, int32_t, idxLowerBound, int32_t, idxUpperBound);
5075	IEM_CIMPL_PROTO_0(iemCImpl_xgetbv);
5076	IEM_CIMPL_PROTO_0(iemCImpl_xsetbv);
5077	IEM_CIMPL_PROTO_4(iemCImpl_cmpxchg16b_fallback_rendezvous, PRTUINT128U, pu128Dst, PRTUINT128U, pu128RaxRdx,
5078	PRTUINT128U, pu128RbxRcx, uint32_t *, pEFlags);
5079	IEM_CIMPL_PROTO_2(iemCImpl_clflush_clflushopt, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5080	IEM_CIMPL_PROTO_1(iemCImpl_finit, bool, fCheckXcpts);
5081	IEM_CIMPL_PROTO_3(iemCImpl_fxsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5082	IEM_CIMPL_PROTO_3(iemCImpl_fxrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5083	IEM_CIMPL_PROTO_3(iemCImpl_xsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5084	IEM_CIMPL_PROTO_3(iemCImpl_xrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5085	IEM_CIMPL_PROTO_2(iemCImpl_stmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5086	IEM_CIMPL_PROTO_2(iemCImpl_vstmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5087	IEM_CIMPL_PROTO_2(iemCImpl_ldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5088	IEM_CIMPL_PROTO_3(iemCImpl_fnstenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5089	IEM_CIMPL_PROTO_3(iemCImpl_fnsave, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5090	IEM_CIMPL_PROTO_3(iemCImpl_fldenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
5091	IEM_CIMPL_PROTO_3(iemCImpl_frstor, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
5092	IEM_CIMPL_PROTO_1(iemCImpl_fldcw, uint16_t, u16Fcw);
5093	IEM_CIMPL_PROTO_2(iemCImpl_fxch_underflow, uint8_t, iStReg, uint16_t, uFpuOpcode);
5094	IEM_CIMPL_PROTO_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, bool, fUCmp, uint32_t, uPopAndFpuOpcode);
5095	/** @} */
5096
5097	/** @name IEMAllCImplStrInstr.cpp.h
5098	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/' -e 's/RT_CONCAT4(//' \
5099	* -e 's/,ADDR_SIZE)/64/g' -e 's/,OP_SIZE,/64/g' -e 's/,OP_rAX,/rax/g' IEMAllCImplStrInstr.cpp.h
5100	* @{ */
5101	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr16, uint8_t, iEffSeg);
5102	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr16, uint8_t, iEffSeg);
5103	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m16);
5104	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m16);
5105	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr16, uint8_t, iEffSeg);
5106	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m16);
5107	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m16, int8_t, iEffSeg);
5108	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr16, bool, fIoChecked);
5109	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr16, bool, fIoChecked);
5110	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5111	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5112
5113	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr16, uint8_t, iEffSeg);
5114	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr16, uint8_t, iEffSeg);
5115	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m16);
5116	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m16);
5117	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr16, uint8_t, iEffSeg);
5118	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m16);
5119	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m16, int8_t, iEffSeg);
5120	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr16, bool, fIoChecked);
5121	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr16, bool, fIoChecked);
5122	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5123	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5124
5125	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr16, uint8_t, iEffSeg);
5126	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr16, uint8_t, iEffSeg);
5127	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m16);
5128	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m16);
5129	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr16, uint8_t, iEffSeg);
5130	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m16);
5131	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m16, int8_t, iEffSeg);
5132	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr16, bool, fIoChecked);
5133	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr16, bool, fIoChecked);
5134	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5135	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5136
5137
5138	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr32, uint8_t, iEffSeg);
5139	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr32, uint8_t, iEffSeg);
5140	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m32);
5141	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m32);
5142	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr32, uint8_t, iEffSeg);
5143	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m32);
5144	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m32, int8_t, iEffSeg);
5145	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr32, bool, fIoChecked);
5146	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr32, bool, fIoChecked);
5147	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5148	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5149
5150	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr32, uint8_t, iEffSeg);
5151	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr32, uint8_t, iEffSeg);
5152	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m32);
5153	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m32);
5154	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr32, uint8_t, iEffSeg);
5155	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m32);
5156	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m32, int8_t, iEffSeg);
5157	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr32, bool, fIoChecked);
5158	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr32, bool, fIoChecked);
5159	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5160	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5161
5162	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr32, uint8_t, iEffSeg);
5163	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr32, uint8_t, iEffSeg);
5164	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m32);
5165	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m32);
5166	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr32, uint8_t, iEffSeg);
5167	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m32);
5168	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m32, int8_t, iEffSeg);
5169	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr32, bool, fIoChecked);
5170	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr32, bool, fIoChecked);
5171	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5172	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5173
5174	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr32, uint8_t, iEffSeg);
5175	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr32, uint8_t, iEffSeg);
5176	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m32);
5177	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m32);
5178	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr32, uint8_t, iEffSeg);
5179	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m32);
5180	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m32, int8_t, iEffSeg);
5181	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr32, bool, fIoChecked);
5182	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr32, bool, fIoChecked);
5183	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5184	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5185
5186
5187	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr64, uint8_t, iEffSeg);
5188	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr64, uint8_t, iEffSeg);
5189	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m64);
5190	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m64);
5191	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr64, uint8_t, iEffSeg);
5192	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m64);
5193	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m64, int8_t, iEffSeg);
5194	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr64, bool, fIoChecked);
5195	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr64, bool, fIoChecked);
5196	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5197	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5198
5199	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr64, uint8_t, iEffSeg);
5200	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr64, uint8_t, iEffSeg);
5201	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m64);
5202	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m64);
5203	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr64, uint8_t, iEffSeg);
5204	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m64);
5205	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m64, int8_t, iEffSeg);
5206	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr64, bool, fIoChecked);
5207	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr64, bool, fIoChecked);
5208	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5209	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5210
5211	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr64, uint8_t, iEffSeg);
5212	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr64, uint8_t, iEffSeg);
5213	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m64);
5214	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m64);
5215	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr64, uint8_t, iEffSeg);
5216	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m64);
5217	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m64, int8_t, iEffSeg);
5218	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr64, bool, fIoChecked);
5219	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr64, bool, fIoChecked);
5220	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5221	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5222
5223	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr64, uint8_t, iEffSeg);
5224	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr64, uint8_t, iEffSeg);
5225	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m64);
5226	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m64);
5227	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr64, uint8_t, iEffSeg);
5228	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m64);
5229	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m64, int8_t, iEffSeg);
5230	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr64, bool, fIoChecked);
5231	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr64, bool, fIoChecked);
5232	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5233	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5234	/** @} */
5235
5236	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5237	VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT;
5238	VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT;
5239	VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT;
5240	VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT;
5241	VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT;
5242	VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
5243	VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALK pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT;
5244	VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT;
5245	VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT;
5246	VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
5247	bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT;
5248	VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
5249	bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT;
5250	VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5251	VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5252	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5253	VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5254	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5255	VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5256	VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT;
5257	VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
5258	RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT;
5259	VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT;
5260	VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT;
5261	VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT;
5262	uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT;
5263	void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT;
5264	VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
5265	uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT;
5266	bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT;
5267	IEM_CIMPL_PROTO_0(iemCImpl_vmxoff);
5268	IEM_CIMPL_PROTO_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon);
5269	IEM_CIMPL_PROTO_0(iemCImpl_vmlaunch);
5270	IEM_CIMPL_PROTO_0(iemCImpl_vmresume);
5271	IEM_CIMPL_PROTO_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
5272	IEM_CIMPL_PROTO_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
5273	IEM_CIMPL_PROTO_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
5274	IEM_CIMPL_PROTO_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField);
5275	IEM_CIMPL_PROTO_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField);
5276	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField);
5277	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg32, uint64_t *, pu32Dst, uint32_t, u32VmcsField);
5278	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField);
5279	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField);
5280	IEM_CIMPL_PROTO_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType);
5281	IEM_CIMPL_PROTO_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType);
5282	IEM_CIMPL_PROTO_0(iemCImpl_vmx_pause);
5283	#endif
5284
5285	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5286	VBOXSTRICTRC iemSvmVmexit(PVMCPUCC pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2) RT_NOEXCEPT;
5287	VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr, uint64_t uCr2) RT_NOEXCEPT;
5288	VBOXSTRICTRC iemSvmHandleIOIntercept(PVMCPUCC pVCpu, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
5289	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, uint8_t cbInstr) RT_NOEXCEPT;
5290	VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPUCC pVCpu, uint32_t idMsr, bool fWrite, uint8_t cbInstr) RT_NOEXCEPT;
5291	IEM_CIMPL_PROTO_0(iemCImpl_vmrun);
5292	IEM_CIMPL_PROTO_0(iemCImpl_vmload);
5293	IEM_CIMPL_PROTO_0(iemCImpl_vmsave);
5294	IEM_CIMPL_PROTO_0(iemCImpl_clgi);
5295	IEM_CIMPL_PROTO_0(iemCImpl_stgi);
5296	IEM_CIMPL_PROTO_0(iemCImpl_invlpga);
5297	IEM_CIMPL_PROTO_0(iemCImpl_skinit);
5298	IEM_CIMPL_PROTO_0(iemCImpl_svm_pause);
5299	#endif
5300
5301	IEM_CIMPL_PROTO_0(iemCImpl_vmcall); /* vmx */
5302	IEM_CIMPL_PROTO_0(iemCImpl_vmmcall); /* svm */
5303	IEM_CIMPL_PROTO_1(iemCImpl_Hypercall, uint16_t, uDisOpcode); /* both */
5304
5305	extern const PFNIEMOP g_apfnIemInterpretOnlyOneByteMap[256];
5306	extern const PFNIEMOP g_apfnIemInterpretOnlyTwoByteMap[1024];
5307	extern const PFNIEMOP g_apfnIemInterpretOnlyThreeByte0f3a[1024];
5308	extern const PFNIEMOP g_apfnIemInterpretOnlyThreeByte0f38[1024];
5309	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap1[1024];
5310	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap2[1024];
5311	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap3[1024];
5312
5313	/*
5314	* Recompiler related stuff.
5315	*/
5316	extern const PFNIEMOP g_apfnIemThreadedRecompilerOneByteMap[256];
5317	extern const PFNIEMOP g_apfnIemThreadedRecompilerTwoByteMap[1024];
5318	extern const PFNIEMOP g_apfnIemThreadedRecompilerThreeByte0f3a[1024];
5319	extern const PFNIEMOP g_apfnIemThreadedRecompilerThreeByte0f38[1024];
5320	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap1[1024];
5321	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap2[1024];
5322	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap3[1024];
5323
5324	DECLCALLBACK(int) iemTbInit(PVMCC pVM, uint32_t cInitialTbs, uint32_t cMaxTbs,
5325	uint64_t cbInitialExec, uint64_t cbMaxExec, uint32_t cbChunkExec);
5326	void iemThreadedTbObsolete(PVMCPUCC pVCpu, PIEMTB pTb, bool fSafeToFree);
5327	void iemTbAllocatorProcessDelayedFrees(PVMCPU pVCpu, PIEMTBALLOCATOR pTbAllocator);
5328
5329
5330	/** @todo FNIEMTHREADEDFUNC and friends may need more work... */
5331	#if defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
5332	typedef VBOXSTRICTRC /__attribute__((__nothrow__))/ FNIEMTHREADEDFUNC(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
5333	typedef FNIEMTHREADEDFUNC *PFNIEMTHREADEDFUNC;
5334	# define IEM_DECL_IEMTHREADEDFUNC_DEF(a_Name) \
5335	VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2)
5336	# define IEM_DECL_IEMTHREADEDFUNC_PROTO(a_Name) \
5337	VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2)
5338
5339	#else
5340	typedef VBOXSTRICTRC (FNIEMTHREADEDFUNC)(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
5341	typedef FNIEMTHREADEDFUNC *PFNIEMTHREADEDFUNC;
5342	# define IEM_DECL_IEMTHREADEDFUNC_DEF(a_Name) \
5343	VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2) IEM_NOEXCEPT_MAY_LONGJMP
5344	# define IEM_DECL_IEMTHREADEDFUNC_PROTO(a_Name) \
5345	VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2) IEM_NOEXCEPT_MAY_LONGJMP
5346	#endif
5347
5348
5349	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_DeferToCImpl0);
5350
5351	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckIrq);
5352	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckMode);
5353	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckHwInstrBps);
5354	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLim);
5355
5356	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodes);
5357	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodes);
5358	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesConsiderCsLim);
5359
5360	/* Branching: */
5361	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndPcAndOpcodes);
5362	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckPcAndOpcodes);
5363	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckPcAndOpcodesConsiderCsLim);
5364
5365	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesLoadingTlb);
5366	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesLoadingTlb);
5367	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesLoadingTlbConsiderCsLim);
5368
5369	/* Natural page crossing: */
5370	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesAcrossPageLoadingTlb);
5371	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesAcrossPageLoadingTlb);
5372	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesAcrossPageLoadingTlbConsiderCsLim);
5373
5374	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesOnNextPageLoadingTlb);
5375	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNextPageLoadingTlb);
5376	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNextPageLoadingTlbConsiderCsLim);
5377
5378	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesOnNewPageLoadingTlb);
5379	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNewPageLoadingTlb);
5380	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNewPageLoadingTlbConsiderCsLim);
5381
5382	bool iemThreadedCompileEmitIrqCheckBefore(PVMCPUCC pVCpu, PIEMTB pTb);
5383	bool iemThreadedCompileBeginEmitCallsComplications(PVMCPUCC pVCpu, PIEMTB pTb);
5384
5385	/* Native recompiler public bits: */
5386	PIEMTB iemNativeRecompile(PVMCPUCC pVCpu, PIEMTB pTb);
5387	int iemExecMemAllocatorInit(PVMCPU pVCpu, uint64_t cbMax, uint64_t cbInitial, uint32_t cbChunk);
5388	void iemExecMemAllocatorFree(PVMCPU pVCpu, void *pv, size_t cb);
5389
5390
5391	/** @} */
5392
5393	RT_C_DECLS_END
5394
5395	#endif /* !VMM_INCLUDED_SRC_include_IEMInternal_h */
5396

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source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h@ 101330

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