IEMInternal.h@ 101518

Last change on this file since 101518 was 101484, checked in by vboxsync, 16 months ago
VMM/IEM: Basic register allocator sketches that incorporates simple skipping of guest register value loads. Sketched out varable and argument managmenet. Start telling GDB our jitted code to help with backtraces. ++ bugref:10371
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 279.3 KB

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1	/* $Id: IEMInternal.h 101484 2023-10-18 01:32:17Z vboxsync $ */
2	/** @file
3	* IEM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2011-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_IEMInternal_h
29	#define VMM_INCLUDED_SRC_include_IEMInternal_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#include <VBox/vmm/cpum.h>
35	#include <VBox/vmm/iem.h>
36	#include <VBox/vmm/pgm.h>
37	#include <VBox/vmm/stam.h>
38	#include <VBox/param.h>
39
40	#include <iprt/setjmp-without-sigmask.h>
41	#include <iprt/list.h>
42
43
44	RT_C_DECLS_BEGIN
45
46
47	/** @defgroup grp_iem_int Internals
48	* @ingroup grp_iem
49	* @internal
50	* @{
51	*/
52
53	/** For expanding symbol in slickedit and other products tagging and
54	* crossreferencing IEM symbols. */
55	#ifndef IEM_STATIC
56	# define IEM_STATIC static
57	#endif
58
59	/** @def IEM_WITH_SETJMP
60	* Enables alternative status code handling using setjmps.
61	*
62	* This adds a bit of expense via the setjmp() call since it saves all the
63	* non-volatile registers. However, it eliminates return code checks and allows
64	* for more optimal return value passing (return regs instead of stack buffer).
65	*/
66	#if defined(DOXYGEN_RUNNING) \|\| defined(RT_OS_WINDOWS) \|\| 1
67	# define IEM_WITH_SETJMP
68	#endif
69
70	/** @def IEM_WITH_THROW_CATCH
71	* Enables using C++ throw/catch as an alternative to setjmp/longjmp in user
72	* mode code when IEM_WITH_SETJMP is in effect.
73	*
74	* With GCC 11.3.1 and code TLB on linux, using throw/catch instead of
75	* setjmp/long resulted in bs2-test-1 running 3.00% faster and all but on test
76	* result value improving by more than 1%. (Best out of three.)
77	*
78	* With Visual C++ 2019 and code TLB on windows, using throw/catch instead of
79	* setjmp/long resulted in bs2-test-1 running 3.68% faster and all but some of
80	* the MMIO and CPUID tests ran noticeably faster. Variation is greater than on
81	* Linux, but it should be quite a bit faster for normal code.
82	*/
83	#if (defined(__cplusplus) && defined(IEM_WITH_SETJMP) && defined(IN_RING3) && (defined(__GNUC__) \|\| defined(_MSC_VER))) \
84	\|\| defined(DOXYGEN_RUNNING)
85	# define IEM_WITH_THROW_CATCH
86	#endif
87
88	/** @def IEM_DO_LONGJMP
89	*
90	* Wrapper around longjmp / throw.
91	*
92	* @param a_pVCpu The CPU handle.
93	* @param a_rc The status code jump back with / throw.
94	*/
95	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
96	# ifdef IEM_WITH_THROW_CATCH
97	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) throw int(a_rc)
98	# else
99	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) longjmp(*(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf), (a_rc))
100	# endif
101	#endif
102
103	/** For use with IEM function that may do a longjmp (when enabled).
104	*
105	* Visual C++ has trouble longjmp'ing from/over functions with the noexcept
106	* attribute. So, we indicate that function that may be part of a longjmp may
107	* throw "exceptions" and that the compiler should definitely not generate and
108	* std::terminate calling unwind code.
109	*
110	* Here is one example of this ending in std::terminate:
111	* @code{.txt}
112	00 00000041`cadfda10 00007ffc`5d5a1f9f ucrtbase!abort+0x4e
113	01 00000041`cadfda40 00007ffc`57af229a ucrtbase!terminate+0x1f
114	02 00000041`cadfda70 00007ffb`eec91030 VCRUNTIME140!__std_terminate+0xa [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\ehhelpers.cpp @ 192]
115	03 00000041`cadfdaa0 00007ffb`eec92c6d VCRUNTIME140_1!_CallSettingFrame+0x20 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\handlers.asm @ 50]
116	04 00000041`cadfdad0 00007ffb`eec93ae5 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToState+0x241 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 1085]
117	05 00000041`cadfdc00 00007ffb`eec92258 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToEmptyState+0x2d [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 218]
118	06 00000041`cadfdc30 00007ffb`eec940e9 VCRUNTIME140_1!__InternalCxxFrameHandler<__FrameHandler4>+0x194 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 304]
119	07 00000041`cadfdcd0 00007ffc`5f9f249f VCRUNTIME140_1!__CxxFrameHandler4+0xa9 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 290]
120	08 00000041`cadfdd40 00007ffc`5f980939 ntdll!RtlpExecuteHandlerForUnwind+0xf
121	09 00000041`cadfdd70 00007ffc`5f9a0edd ntdll!RtlUnwindEx+0x339
122	0a 00000041`cadfe490 00007ffc`57aff976 ntdll!RtlUnwind+0xcd
123	0b 00000041`cadfea00 00007ffb`e1b5de01 VCRUNTIME140!__longjmp_internal+0xe6 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\longjmp.asm @ 140]
124	0c (Inline Function) --------`-------- VBoxVMM!iemOpcodeGetNextU8SlowJmp+0x95 [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 1155]
125	0d 00000041`cadfea50 00007ffb`e1b60f6b VBoxVMM!iemOpcodeGetNextU8Jmp+0xc1 [L:\vbox-intern\src\VBox\VMM\include\IEMInline.h @ 402]
126	0e 00000041`cadfea90 00007ffb`e1cc6201 VBoxVMM!IEMExecForExits+0xdb [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 10185]
127	0f 00000041`cadfec70 00007ffb`e1d0df8d VBoxVMM!EMHistoryExec+0x4f1 [L:\vbox-intern\src\VBox\VMM\VMMAll\EMAll.cpp @ 452]
128	10 00000041`cadfed60 00007ffb`e1d0d4c0 VBoxVMM!nemR3WinHandleExitCpuId+0x79d [L:\vbox-intern\src\VBox\VMM\VMMAll\NEMAllNativeTemplate-win.cpp.h @ 1829] @encode
129	@endcode
130	*
131	* @see https://developercommunity.visualstudio.com/t/fragile-behavior-of-longjmp-called-from-noexcept-f/1532859
132	*/
133	#if defined(IEM_WITH_SETJMP) && (defined(_MSC_VER) \|\| defined(IEM_WITH_THROW_CATCH))
134	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT_EX(false)
135	#else
136	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT
137	#endif
138
139	#define IEM_IMPLEMENTS_TASKSWITCH
140
141	/** @def IEM_WITH_3DNOW
142	* Includes the 3DNow decoding. */
143	#if (!defined(IEM_WITH_3DNOW) && !defined(IEM_WITHOUT_3DNOW)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
144	# define IEM_WITH_3DNOW
145	#endif
146
147	/** @def IEM_WITH_THREE_0F_38
148	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
149	#if (!defined(IEM_WITH_THREE_0F_38) && !defined(IEM_WITHOUT_THREE_0F_38)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
150	# define IEM_WITH_THREE_0F_38
151	#endif
152
153	/** @def IEM_WITH_THREE_0F_3A
154	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
155	#if (!defined(IEM_WITH_THREE_0F_3A) && !defined(IEM_WITHOUT_THREE_0F_3A)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
156	# define IEM_WITH_THREE_0F_3A
157	#endif
158
159	/** @def IEM_WITH_VEX
160	* Includes the VEX decoding. */
161	#if (!defined(IEM_WITH_VEX) && !defined(IEM_WITHOUT_VEX)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
162	# define IEM_WITH_VEX
163	#endif
164
165	/** @def IEM_CFG_TARGET_CPU
166	* The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
167	*
168	* By default we allow this to be configured by the user via the
169	* CPUM/GuestCpuName config string, but this comes at a slight cost during
170	* decoding. So, for applications of this code where there is no need to
171	* be dynamic wrt target CPU, just modify this define.
172	*/
173	#if !defined(IEM_CFG_TARGET_CPU) \|\| defined(DOXYGEN_RUNNING)
174	# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
175	#endif
176
177	//#define IEM_WITH_CODE_TLB // - work in progress
178	//#define IEM_WITH_DATA_TLB // - work in progress
179
180
181	/** @def IEM_USE_UNALIGNED_DATA_ACCESS
182	* Use unaligned accesses instead of elaborate byte assembly. */
183	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86) \|\| defined(DOXYGEN_RUNNING)
184	# define IEM_USE_UNALIGNED_DATA_ACCESS
185	#endif
186
187	//#define IEM_LOG_MEMORY_WRITES
188
189	#if !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
190	/** Instruction statistics. */
191	typedef struct IEMINSTRSTATS
192	{
193	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
194	# include "IEMInstructionStatisticsTmpl.h"
195	# undef IEM_DO_INSTR_STAT
196	} IEMINSTRSTATS;
197	#else
198	struct IEMINSTRSTATS;
199	typedef struct IEMINSTRSTATS IEMINSTRSTATS;
200	#endif
201	/** Pointer to IEM instruction statistics. */
202	typedef IEMINSTRSTATS *PIEMINSTRSTATS;
203
204
205	/** @name IEMTARGETCPU_EFL_BEHAVIOR_XXX - IEMCPU::aidxTargetCpuEflFlavour
206	* @{ */
207	#define IEMTARGETCPU_EFL_BEHAVIOR_NATIVE 0 /*< Native x86 EFLAGS result; Intel EFLAGS when on non-x86 hosts. /
208	#define IEMTARGETCPU_EFL_BEHAVIOR_INTEL 1 /*< Intel EFLAGS result. /
209	#define IEMTARGETCPU_EFL_BEHAVIOR_AMD 2 /*< AMD EFLAGS result /
210	#define IEMTARGETCPU_EFL_BEHAVIOR_RESERVED 3 /*< Reserved/dummy entry slot that's the same as 0. /
211	#define IEMTARGETCPU_EFL_BEHAVIOR_MASK 3 /*< For masking the index before use. /
212	/** Selects the right variant from a_aArray.
213	* pVCpu is implicit in the caller context. */
214	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT(a_aArray) \
215	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[1] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
216	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for when no native worker can
217	* be used because the host CPU does not support the operation. */
218	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_NON_NATIVE(a_aArray) \
219	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
220	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for a two dimentional
221	* array paralleling IEMCPU::aidxTargetCpuEflFlavour and a single bit index
222	* into the two.
223	* @sa IEM_SELECT_NATIVE_OR_FALLBACK */
224	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
225	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
226	(a_aaArray[a_fNative][pVCpu->iem.s.aidxTargetCpuEflFlavour[a_fNative] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
227	#else
228	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
229	(a_aaArray[0][pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
230	#endif
231	/** @} */
232
233	/**
234	* Picks @a a_pfnNative or @a a_pfnFallback according to the host CPU feature
235	* indicator given by @a a_fCpumFeatureMember (CPUMFEATURES member).
236	*
237	* On non-x86 hosts, this will shortcut to the fallback w/o checking the
238	* indicator.
239	*
240	* @sa IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX
241	*/
242	#if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
243	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) \
244	(g_CpumHostFeatures.s.a_fCpumFeatureMember ? a_pfnNative : a_pfnFallback)
245	#else
246	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) (a_pfnFallback)
247	#endif
248
249
250	/**
251	* Extended operand mode that includes a representation of 8-bit.
252	*
253	* This is used for packing down modes when invoking some C instruction
254	* implementations.
255	*/
256	typedef enum IEMMODEX
257	{
258	IEMMODEX_16BIT = IEMMODE_16BIT,
259	IEMMODEX_32BIT = IEMMODE_32BIT,
260	IEMMODEX_64BIT = IEMMODE_64BIT,
261	IEMMODEX_8BIT
262	} IEMMODEX;
263	AssertCompileSize(IEMMODEX, 4);
264
265
266	/**
267	* Branch types.
268	*/
269	typedef enum IEMBRANCH
270	{
271	IEMBRANCH_JUMP = 1,
272	IEMBRANCH_CALL,
273	IEMBRANCH_TRAP,
274	IEMBRANCH_SOFTWARE_INT,
275	IEMBRANCH_HARDWARE_INT
276	} IEMBRANCH;
277	AssertCompileSize(IEMBRANCH, 4);
278
279
280	/**
281	* INT instruction types.
282	*/
283	typedef enum IEMINT
284	{
285	/** INT n instruction (opcode 0xcd imm). */
286	IEMINT_INTN = 0,
287	/** Single byte INT3 instruction (opcode 0xcc). */
288	IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
289	/** Single byte INTO instruction (opcode 0xce). */
290	IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
291	/** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
292	IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
293	} IEMINT;
294	AssertCompileSize(IEMINT, 4);
295
296
297	/**
298	* A FPU result.
299	*/
300	typedef struct IEMFPURESULT
301	{
302	/** The output value. */
303	RTFLOAT80U r80Result;
304	/** The output status. */
305	uint16_t FSW;
306	} IEMFPURESULT;
307	AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
308	/** Pointer to a FPU result. */
309	typedef IEMFPURESULT *PIEMFPURESULT;
310	/** Pointer to a const FPU result. */
311	typedef IEMFPURESULT const *PCIEMFPURESULT;
312
313
314	/**
315	* A FPU result consisting of two output values and FSW.
316	*/
317	typedef struct IEMFPURESULTTWO
318	{
319	/** The first output value. */
320	RTFLOAT80U r80Result1;
321	/** The output status. */
322	uint16_t FSW;
323	/** The second output value. */
324	RTFLOAT80U r80Result2;
325	} IEMFPURESULTTWO;
326	AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
327	AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
328	/** Pointer to a FPU result consisting of two output values and FSW. */
329	typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
330	/** Pointer to a const FPU result consisting of two output values and FSW. */
331	typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
332
333
334	/**
335	* IEM TLB entry.
336	*
337	* Lookup assembly:
338	* @code{.asm}
339	; Calculate tag.
340	mov rax, [VA]
341	shl rax, 16
342	shr rax, 16 + X86_PAGE_SHIFT
343	or rax, [uTlbRevision]
344
345	; Do indexing.
346	movzx ecx, al
347	lea rcx, [pTlbEntries + rcx]
348
349	; Check tag.
350	cmp [rcx + IEMTLBENTRY.uTag], rax
351	jne .TlbMiss
352
353	; Check access.
354	mov rax, ACCESS_FLAGS \| MAPPING_R3_NOT_VALID \| 0xffffff00
355	and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
356	cmp rax, [uTlbPhysRev]
357	jne .TlbMiss
358
359	; Calc address and we're done.
360	mov eax, X86_PAGE_OFFSET_MASK
361	and eax, [VA]
362	or rax, [rcx + IEMTLBENTRY.pMappingR3]
363	%ifdef VBOX_WITH_STATISTICS
364	inc qword [cTlbHits]
365	%endif
366	jmp .Done
367
368	.TlbMiss:
369	mov r8d, ACCESS_FLAGS
370	mov rdx, [VA]
371	mov rcx, [pVCpu]
372	call iemTlbTypeMiss
373	.Done:
374
375	@endcode
376	*
377	*/
378	typedef struct IEMTLBENTRY
379	{
380	/** The TLB entry tag.
381	* Bits 35 thru 0 are made up of the virtual address shifted right 12 bits, this
382	* is ASSUMING a virtual address width of 48 bits.
383	*
384	* Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
385	*
386	* The TLB lookup code uses the current TLB revision, which won't ever be zero,
387	* enabling an extremely cheap TLB invalidation most of the time. When the TLB
388	* revision wraps around though, the tags needs to be zeroed.
389	*
390	* @note Try use SHRD instruction? After seeing
391	* https://gmplib.org/~tege/x86-timing.pdf, maybe not.
392	*
393	* @todo This will need to be reorganized for 57-bit wide virtual address and
394	* PCID (currently 12 bits) and ASID (currently 6 bits) support. We'll
395	* have to move the TLB entry versioning entirely to the
396	* fFlagsAndPhysRev member then, 57 bit wide VAs means we'll only have
397	* 19 bits left (64 - 57 + 12 = 19) and they'll almost entire be
398	* consumed by PCID and ASID (12 + 6 = 18).
399	*/
400	uint64_t uTag;
401	/** Access flags and physical TLB revision.
402	*
403	* - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
404	* - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
405	* - Bit 2 - page tables - not user (complemented X86_PTE_US).
406	* - Bit 3 - pgm phys/virt - not directly writable.
407	* - Bit 4 - pgm phys page - not directly readable.
408	* - Bit 5 - page tables - not accessed (complemented X86_PTE_A).
409	* - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
410	* - Bit 7 - tlb entry - pMappingR3 member not valid.
411	* - Bits 63 thru 8 are used for the physical TLB revision number.
412	*
413	* We're using complemented bit meanings here because it makes it easy to check
414	* whether special action is required. For instance a user mode write access
415	* would do a "TEST fFlags, (X86_PTE_RW \| X86_PTE_US \| X86_PTE_D)" and a
416	* non-zero result would mean special handling needed because either it wasn't
417	* writable, or it wasn't user, or the page wasn't dirty. A user mode read
418	* access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
419	* need to check any PTE flag.
420	*/
421	uint64_t fFlagsAndPhysRev;
422	/** The guest physical page address. */
423	uint64_t GCPhys;
424	/** Pointer to the ring-3 mapping. */
425	R3PTRTYPE(uint8_t *) pbMappingR3;
426	#if HC_ARCH_BITS == 32
427	uint32_t u32Padding1;
428	#endif
429	} IEMTLBENTRY;
430	AssertCompileSize(IEMTLBENTRY, 32);
431	/** Pointer to an IEM TLB entry. */
432	typedef IEMTLBENTRY *PIEMTLBENTRY;
433
434	/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
435	* @{ */
436	#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /*< Page tables: Not executable. /
437	#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /*< Page tables: Not writable. /
438	#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /*< Page tables: Not user accessible (supervisor only). /
439	#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /*< Phys page: Not writable (access handler, ROM, whatever). /
440	#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /*< Phys page: Not readable (MMIO / access handler, ROM) /
441	#define IEMTLBE_F_PT_NO_ACCESSED RT_BIT_64(5) /*< Phys tables: Not accessed (need to be marked accessed). /
442	#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /*< Page tables: Not dirty (needs to be made dirty on write). /
443	#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(7) /*< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. /
444	#define IEMTLBE_F_PG_UNASSIGNED RT_BIT_64(8) /*< Phys page: Unassigned memory (not RAM, ROM, MMIO2 or MMIO). /
445	#define IEMTLBE_F_PG_CODE_PAGE RT_BIT_64(9) /*< Phys page: Code page. /
446	#define IEMTLBE_F_PHYS_REV UINT64_C(0xfffffffffffffc00) /*< Physical revision mask. @sa IEMTLB_PHYS_REV_INCR /
447	/** @} */
448
449
450	/**
451	* An IEM TLB.
452	*
453	* We've got two of these, one for data and one for instructions.
454	*/
455	typedef struct IEMTLB
456	{
457	/** The TLB entries.
458	* We've choosen 256 because that way we can obtain the result directly from a
459	* 8-bit register without an additional AND instruction. */
460	IEMTLBENTRY aEntries[256];
461	/** The TLB revision.
462	* This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
463	* by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
464	* the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
465	* (The revision zero indicates an invalid TLB entry.)
466	*
467	* The initial value is choosen to cause an early wraparound. */
468	uint64_t uTlbRevision;
469	/** The TLB physical address revision - shadow of PGM variable.
470	*
471	* This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
472	* incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
473	* a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
474	* as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
475	*
476	* The initial value is choosen to cause an early wraparound. */
477	uint64_t volatile uTlbPhysRev;
478
479	/* Statistics: */
480
481	/** TLB hits (VBOX_WITH_STATISTICS only). */
482	uint64_t cTlbHits;
483	/** TLB misses. */
484	uint32_t cTlbMisses;
485	/** Slow read path. */
486	uint32_t cTlbSlowReadPath;
487	/** Safe read path. */
488	uint32_t cTlbSafeReadPath;
489	/** Safe write path. */
490	uint32_t cTlbSafeWritePath;
491	#if 0
492	/** TLB misses because of tag mismatch. */
493	uint32_t cTlbMissesTag;
494	/** TLB misses because of virtual access violation. */
495	uint32_t cTlbMissesVirtAccess;
496	/** TLB misses because of dirty bit. */
497	uint32_t cTlbMissesDirty;
498	/** TLB misses because of MMIO */
499	uint32_t cTlbMissesMmio;
500	/** TLB misses because of write access handlers. */
501	uint32_t cTlbMissesWriteHandler;
502	/** TLB misses because no r3(/r0) mapping. */
503	uint32_t cTlbMissesMapping;
504	#endif
505	/** Alignment padding. */
506	uint32_t au32Padding[6];
507	} IEMTLB;
508	AssertCompileSizeAlignment(IEMTLB, 64);
509	/** IEMTLB::uTlbRevision increment. */
510	#define IEMTLB_REVISION_INCR RT_BIT_64(36)
511	/** IEMTLB::uTlbRevision mask. */
512	#define IEMTLB_REVISION_MASK (~(RT_BIT_64(36) - 1))
513	/** IEMTLB::uTlbPhysRev increment.
514	* @sa IEMTLBE_F_PHYS_REV */
515	#define IEMTLB_PHYS_REV_INCR RT_BIT_64(10)
516	/**
517	* Calculates the TLB tag for a virtual address.
518	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
519	* @param a_pTlb The TLB.
520	* @param a_GCPtr The virtual address. Must be RTGCPTR or same size or
521	* the clearing of the top 16 bits won't work (if 32-bit
522	* we'll end up with mostly zeros).
523	*/
524	#define IEMTLB_CALC_TAG(a_pTlb, a_GCPtr) ( IEMTLB_CALC_TAG_NO_REV(a_GCPtr) \| (a_pTlb)->uTlbRevision )
525	/**
526	* Calculates the TLB tag for a virtual address but without TLB revision.
527	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
528	* @param a_GCPtr The virtual address. Must be RTGCPTR or same size or
529	* the clearing of the top 16 bits won't work (if 32-bit
530	* we'll end up with mostly zeros).
531	*/
532	#define IEMTLB_CALC_TAG_NO_REV(a_GCPtr) ( (((a_GCPtr) << 16) >> (GUEST_PAGE_SHIFT + 16)) )
533	/**
534	* Converts a TLB tag value into a TLB index.
535	* @returns Index into IEMTLB::aEntries.
536	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
537	*/
538	#define IEMTLB_TAG_TO_INDEX(a_uTag) ( (uint8_t)(a_uTag) )
539	/**
540	* Converts a TLB tag value into a TLB index.
541	* @returns Index into IEMTLB::aEntries.
542	* @param a_pTlb The TLB.
543	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
544	*/
545	#define IEMTLB_TAG_TO_ENTRY(a_pTlb, a_uTag) ( &(a_pTlb)->aEntries[IEMTLB_TAG_TO_INDEX(a_uTag)] )
546
547
548	/** @name IEM_MC_F_XXX - MC block flags/clues.
549	* @todo Merge with IEM_CIMPL_F_XXX
550	* @{ */
551	#define IEM_MC_F_ONLY_8086 RT_BIT_32(0)
552	#define IEM_MC_F_MIN_186 RT_BIT_32(1)
553	#define IEM_MC_F_MIN_286 RT_BIT_32(2)
554	#define IEM_MC_F_NOT_286_OR_OLDER IEM_MC_F_MIN_386
555	#define IEM_MC_F_MIN_386 RT_BIT_32(3)
556	#define IEM_MC_F_MIN_486 RT_BIT_32(4)
557	#define IEM_MC_F_MIN_PENTIUM RT_BIT_32(5)
558	#define IEM_MC_F_MIN_PENTIUM_II IEM_MC_F_MIN_PENTIUM
559	#define IEM_MC_F_MIN_CORE IEM_MC_F_MIN_PENTIUM
560	#define IEM_MC_F_64BIT RT_BIT_32(6)
561	#define IEM_MC_F_NOT_64BIT RT_BIT_32(7)
562	/** @} */
563
564	/** @name IEM_CIMPL_F_XXX - State change clues for CIMPL calls.
565	*
566	* These clues are mainly for the recompiler, so that it can emit correct code.
567	*
568	* They are processed by the python script and which also automatically
569	* calculates flags for MC blocks based on the statements, extending the use of
570	* these flags to describe MC block behavior to the recompiler core. The python
571	* script pass the flags to the IEM_MC2_END_EMIT_CALLS macro, but mainly for
572	* error checking purposes. The script emits the necessary fEndTb = true and
573	* similar statements as this reduces compile time a tiny bit.
574	*
575	* @{ */
576	/** Flag set if direct branch, clear if absolute or indirect. */
577	#define IEM_CIMPL_F_BRANCH_DIRECT RT_BIT_32(0)
578	/** Flag set if indirect branch, clear if direct or relative.
579	* This is also used for all system control transfers (SYSCALL, SYSRET, INT, ++)
580	* as well as for return instructions (RET, IRET, RETF). */
581	#define IEM_CIMPL_F_BRANCH_INDIRECT RT_BIT_32(1)
582	/** Flag set if relative branch, clear if absolute or indirect. */
583	#define IEM_CIMPL_F_BRANCH_RELATIVE RT_BIT_32(2)
584	/** Flag set if conditional branch, clear if unconditional. */
585	#define IEM_CIMPL_F_BRANCH_CONDITIONAL RT_BIT_32(3)
586	/** Flag set if it's a far branch (changes CS). */
587	#define IEM_CIMPL_F_BRANCH_FAR RT_BIT_32(4)
588	/** Convenience: Testing any kind of branch. */
589	#define IEM_CIMPL_F_BRANCH_ANY (IEM_CIMPL_F_BRANCH_DIRECT \| IEM_CIMPL_F_BRANCH_INDIRECT \| IEM_CIMPL_F_BRANCH_RELATIVE)
590
591	/** Execution flags may change (IEMCPU::fExec). */
592	#define IEM_CIMPL_F_MODE RT_BIT_32(5)
593	/** May change significant portions of RFLAGS. */
594	#define IEM_CIMPL_F_RFLAGS RT_BIT_32(6)
595	/** May change the status bits (X86_EFL_STATUS_BITS) in RFLAGS. */
596	#define IEM_CIMPL_F_STATUS_FLAGS RT_BIT_32(7)
597	/** May trigger interrupt shadowing. */
598	#define IEM_CIMPL_F_INHIBIT_SHADOW RT_BIT_32(8)
599	/** May enable interrupts, so recheck IRQ immediately afterwards executing
600	* the instruction. */
601	#define IEM_CIMPL_F_CHECK_IRQ_AFTER RT_BIT_32(9)
602	/** May disable interrupts, so recheck IRQ immediately before executing the
603	* instruction. */
604	#define IEM_CIMPL_F_CHECK_IRQ_BEFORE RT_BIT_32(10)
605	/** Convenience: Check for IRQ both before and after an instruction. */
606	#define IEM_CIMPL_F_CHECK_IRQ_BEFORE_AND_AFTER (IEM_CIMPL_F_CHECK_IRQ_BEFORE \| IEM_CIMPL_F_CHECK_IRQ_AFTER)
607	/** May trigger a VM exit (treated like IEM_CIMPL_F_MODE atm). */
608	#define IEM_CIMPL_F_VMEXIT RT_BIT_32(11)
609	/** May modify FPU state.
610	* @todo Not sure if this is useful yet. */
611	#define IEM_CIMPL_F_FPU RT_BIT_32(12)
612	/** REP prefixed instruction which may yield before updating PC.
613	* @todo Not sure if this is useful, REP functions now return non-zero
614	* status if they don't update the PC. */
615	#define IEM_CIMPL_F_REP RT_BIT_32(13)
616	/** I/O instruction.
617	* @todo Not sure if this is useful yet. */
618	#define IEM_CIMPL_F_IO RT_BIT_32(14)
619	/** Force end of TB after the instruction. */
620	#define IEM_CIMPL_F_END_TB RT_BIT_32(15)
621	/** Convenience: Raise exception (technically unnecessary, since it shouldn't return VINF_SUCCESS). */
622	#define IEM_CIMPL_F_XCPT \
623	(IEM_CIMPL_F_BRANCH_INDIRECT \| IEM_CIMPL_F_BRANCH_FAR \| IEM_CIMPL_F_MODE \| IEM_CIMPL_F_RFLAGS \| IEM_CIMPL_F_VMEXIT)
624	/** @} */
625
626
627	/** @name IEM_F_XXX - Execution mode flags (IEMCPU::fExec, IEMTB::fFlags).
628	*
629	* These flags are set when entering IEM and adjusted as code is executed, such
630	* that they will always contain the current values as instructions are
631	* finished.
632	*
633	* In recompiled execution mode, (most of) these flags are included in the
634	* translation block selection key and stored in IEMTB::fFlags alongside the
635	* IEMTB_F_XXX flags. The latter flags uses bits 31 thru 24, which are all zero
636	* in IEMCPU::fExec.
637	*
638	* @{ */
639	/** Mode: The block target mode mask. */
640	#define IEM_F_MODE_MASK UINT32_C(0x0000001f)
641	/** Mode: The IEMMODE part of the IEMTB_F_MODE_MASK value. */
642	#define IEM_F_MODE_CPUMODE_MASK UINT32_C(0x00000003)
643	/** X86 Mode: Bit used to indicating pre-386 CPU in 16-bit mode (for eliminating
644	* conditional in EIP/IP updating), and flat wide open CS, SS DS, and ES in
645	* 32-bit mode (for simplifying most memory accesses). */
646	#define IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK UINT32_C(0x00000004)
647	/** X86 Mode: Bit indicating protected mode, real mode (or SMM) when not set. */
648	#define IEM_F_MODE_X86_PROT_MASK UINT32_C(0x00000008)
649	/** X86 Mode: Bit used to indicate virtual 8086 mode (only 16-bit). */
650	#define IEM_F_MODE_X86_V86_MASK UINT32_C(0x00000010)
651
652	/** X86 Mode: 16-bit on 386 or later. */
653	#define IEM_F_MODE_X86_16BIT UINT32_C(0x00000000)
654	/** X86 Mode: 80286, 80186 and 8086/88 targetting blocks (EIP update opt). */
655	#define IEM_F_MODE_X86_16BIT_PRE_386 UINT32_C(0x00000004)
656	/** X86 Mode: 16-bit protected mode on 386 or later. */
657	#define IEM_F_MODE_X86_16BIT_PROT UINT32_C(0x00000008)
658	/** X86 Mode: 16-bit protected mode on 386 or later. */
659	#define IEM_F_MODE_X86_16BIT_PROT_PRE_386 UINT32_C(0x0000000c)
660	/** X86 Mode: 16-bit virtual 8086 protected mode (on 386 or later). */
661	#define IEM_F_MODE_X86_16BIT_PROT_V86 UINT32_C(0x00000018)
662
663	/** X86 Mode: 32-bit on 386 or later. */
664	#define IEM_F_MODE_X86_32BIT UINT32_C(0x00000001)
665	/** X86 Mode: 32-bit mode with wide open flat CS, SS, DS and ES. */
666	#define IEM_F_MODE_X86_32BIT_FLAT UINT32_C(0x00000005)
667	/** X86 Mode: 32-bit protected mode. */
668	#define IEM_F_MODE_X86_32BIT_PROT UINT32_C(0x00000009)
669	/** X86 Mode: 32-bit protected mode with wide open flat CS, SS, DS and ES. */
670	#define IEM_F_MODE_X86_32BIT_PROT_FLAT UINT32_C(0x0000000d)
671
672	/** X86 Mode: 64-bit (includes protected, but not the flat bit). */
673	#define IEM_F_MODE_X86_64BIT UINT32_C(0x0000000a)
674
675
676	/** Bypass access handlers when set. */
677	#define IEM_F_BYPASS_HANDLERS UINT32_C(0x00010000)
678	/** Have pending hardware instruction breakpoints. */
679	#define IEM_F_PENDING_BRK_INSTR UINT32_C(0x00020000)
680	/** Have pending hardware data breakpoints. */
681	#define IEM_F_PENDING_BRK_DATA UINT32_C(0x00040000)
682
683	/** X86: Have pending hardware I/O breakpoints. */
684	#define IEM_F_PENDING_BRK_X86_IO UINT32_C(0x00000400)
685	/** X86: Disregard the lock prefix (implied or not) when set. */
686	#define IEM_F_X86_DISREGARD_LOCK UINT32_C(0x00000800)
687
688	/** Pending breakpoint mask (what iemCalcExecDbgFlags works out). */
689	#define IEM_F_PENDING_BRK_MASK (IEM_F_PENDING_BRK_INSTR \| IEM_F_PENDING_BRK_DATA \| IEM_F_PENDING_BRK_X86_IO)
690
691	/** Caller configurable options. */
692	#define IEM_F_USER_OPTS (IEM_F_BYPASS_HANDLERS \| IEM_F_X86_DISREGARD_LOCK)
693
694	/** X86: The current protection level (CPL) shift factor. */
695	#define IEM_F_X86_CPL_SHIFT 8
696	/** X86: The current protection level (CPL) mask. */
697	#define IEM_F_X86_CPL_MASK UINT32_C(0x00000300)
698	/** X86: The current protection level (CPL) shifted mask. */
699	#define IEM_F_X86_CPL_SMASK UINT32_C(0x00000003)
700
701	/** X86 execution context.
702	* The IEM_F_X86_CTX_XXX values are individual flags that can be combined (with
703	* the exception of IEM_F_X86_CTX_NORMAL). This allows running VMs from SMM
704	* mode. */
705	#define IEM_F_X86_CTX_MASK UINT32_C(0x0000f000)
706	/** X86 context: Plain regular execution context. */
707	#define IEM_F_X86_CTX_NORMAL UINT32_C(0x00000000)
708	/** X86 context: VT-x enabled. */
709	#define IEM_F_X86_CTX_VMX UINT32_C(0x00001000)
710	/** X86 context: AMD-V enabled. */
711	#define IEM_F_X86_CTX_SVM UINT32_C(0x00002000)
712	/** X86 context: In AMD-V or VT-x guest mode. */
713	#define IEM_F_X86_CTX_IN_GUEST UINT32_C(0x00004000)
714	/** X86 context: System management mode (SMM). */
715	#define IEM_F_X86_CTX_SMM UINT32_C(0x00008000)
716
717	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
718	* iemRegFinishClearingRF() most for most situations (CPUMCTX_DBG_HIT_DRX_MASK
719	* and CPUMCTX_DBG_DBGF_MASK are covered by the IEM_F_PENDING_BRK_XXX bits
720	* alread). */
721
722	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
723	* iemRegFinishClearingRF() most for most situations
724	* (CPUMCTX_DBG_HIT_DRX_MASK and CPUMCTX_DBG_DBGF_MASK are covered by
725	* the IEM_F_PENDING_BRK_XXX bits alread). */
726
727	/** @} */
728
729
730	/** @name IEMTB_F_XXX - Translation block flags (IEMTB::fFlags).
731	*
732	* Extends the IEM_F_XXX flags (subject to IEMTB_F_IEM_F_MASK) to make up the
733	* translation block flags. The combined flag mask (subject to
734	* IEMTB_F_KEY_MASK) is used as part of the lookup key for translation blocks.
735	*
736	* @{ */
737	/** Mask of IEM_F_XXX flags included in IEMTB_F_XXX. */
738	#define IEMTB_F_IEM_F_MASK UINT32_C(0x00ffffff)
739
740	/** Type: The block type mask. */
741	#define IEMTB_F_TYPE_MASK UINT32_C(0x03000000)
742	/** Type: Purly threaded recompiler (via tables). */
743	#define IEMTB_F_TYPE_THREADED UINT32_C(0x01000000)
744	/** Type: Native recompilation. */
745	#define IEMTB_F_TYPE_NATIVE UINT32_C(0x02000000)
746
747	/** Set when we're starting the block in an "interrupt shadow".
748	* We don't need to distingish between the two types of this mask, thus the one.
749	* @see CPUMCTX_INHIBIT_SHADOW, CPUMIsInInterruptShadow() */
750	#define IEMTB_F_INHIBIT_SHADOW UINT32_C(0x04000000)
751	/** Set when we're currently inhibiting NMIs
752	* @see CPUMCTX_INHIBIT_NMI, CPUMAreInterruptsInhibitedByNmi() */
753	#define IEMTB_F_INHIBIT_NMI UINT32_C(0x08000000)
754
755	/** Checks that EIP/IP is wihin CS.LIM before each instruction. Used when
756	* we're close the limit before starting a TB, as determined by
757	* iemGetTbFlagsForCurrentPc(). */
758	#define IEMTB_F_CS_LIM_CHECKS UINT32_C(0x10000000)
759
760	/** Mask of the IEMTB_F_XXX flags that are part of the TB lookup key.
761	* @note We skip the CPL as we don't currently generate ring-specific code,
762	* that's all handled in CIMPL functions.
763	*
764	* For the same reasons, we skip all of IEM_F_X86_CTX_MASK, with the
765	* exception of SMM (which we don't implement). */
766	#define IEMTB_F_KEY_MASK ( (UINT32_MAX & ~(IEM_F_X86_CTX_MASK \| IEM_F_X86_CPL_MASK \| IEMTB_F_TYPE_MASK)) \
767	\| IEM_F_X86_CTX_SMM)
768	/** @} */
769
770	AssertCompile( (IEM_F_MODE_X86_16BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
771	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
772	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_PROT_MASK));
773	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_V86_MASK));
774	AssertCompile( (IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
775	AssertCompile( IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
776	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_PROT_MASK));
777	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
778	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
779	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
780	AssertCompile( IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
781	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_V86_MASK));
782	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
783	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
784	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_PROT_MASK);
785	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
786	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_PROT_MASK);
787	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
788	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_V86_MASK);
789
790	AssertCompile( (IEM_F_MODE_X86_32BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
791	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
792	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_PROT_MASK));
793	AssertCompile( (IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
794	AssertCompile( IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
795	AssertCompile(!(IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_PROT_MASK));
796	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
797	AssertCompile(!(IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
798	AssertCompile( IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
799	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
800	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
801	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_PROT_MASK);
802
803	AssertCompile( (IEM_F_MODE_X86_64BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_64BIT);
804	AssertCompile( IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_PROT_MASK);
805	AssertCompile(!(IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
806
807	/** Native instruction type for use with the native code generator.
808	* This is a byte (uint8_t) for x86 and amd64 and uint32_t for the other(s). */
809	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
810	typedef uint8_t IEMNATIVEINSTR;
811	#else
812	typedef uint32_t IEMNATIVEINSTR;
813	#endif
814	/** Pointer to a native instruction unit. */
815	typedef IEMNATIVEINSTR *PIEMNATIVEINSTR;
816
817	/**
818	* A call for the threaded call table.
819	*/
820	typedef struct IEMTHRDEDCALLENTRY
821	{
822	/** The function to call (IEMTHREADEDFUNCS). */
823	uint16_t enmFunction;
824	/** Instruction number in the TB (for statistics). */
825	uint8_t idxInstr;
826	uint8_t uUnused0;
827
828	/** Offset into IEMTB::pabOpcodes. */
829	uint16_t offOpcode;
830	/** The opcode length. */
831	uint8_t cbOpcode;
832	/** Index in to IEMTB::aRanges. */
833	uint8_t idxRange;
834
835	/** Generic parameters. */
836	uint64_t auParams[3];
837	} IEMTHRDEDCALLENTRY;
838	AssertCompileSize(IEMTHRDEDCALLENTRY, sizeof(uint64_t) * 4);
839	/** Pointer to a threaded call entry. */
840	typedef struct IEMTHRDEDCALLENTRY *PIEMTHRDEDCALLENTRY;
841	/** Pointer to a const threaded call entry. */
842	typedef IEMTHRDEDCALLENTRY const *PCIEMTHRDEDCALLENTRY;
843
844	/**
845	* Native IEM TB 'function' typedef.
846	*
847	* This will throw/longjmp on occation.
848	*
849	* @note AMD64 doesn't have that many non-volatile registers and does sport
850	* 32-bit address displacments, so we don't need pCtx.
851	*
852	* On ARM64 pCtx allows us to directly address the whole register
853	* context without requiring a separate indexing register holding the
854	* offset. This saves an instruction loading the offset for each guest
855	* CPU context access, at the cost of a non-volatile register.
856	* Fortunately, ARM64 has quite a lot more registers.
857	*/
858	typedef
859	#ifdef RT_ARCH_AMD64
860	int FNIEMTBNATIVE(PVMCPUCC pVCpu)
861	#else
862	int FNIEMTBNATIVE(PVMCPUCC pVCpu, PCPUMCTX pCtx)
863	#endif
864	#if RT_CPLUSPLUS_PREREQ(201700)
865	IEM_NOEXCEPT_MAY_LONGJMP
866	#endif
867	;
868	/** Pointer to a native IEM TB entry point function.
869	* This will throw/longjmp on occation. */
870	typedef FNIEMTBNATIVE *PFNIEMTBNATIVE;
871
872
873	/**
874	* Translation block.
875	*
876	* The current plan is to just keep TBs and associated lookup hash table private
877	* to each VCpu as that simplifies TB removal greatly (no races) and generally
878	* avoids using expensive atomic primitives for updating lists and stuff.
879	*/
880	#pragma pack(2) /* to prevent the Thrd structure from being padded unnecessarily */
881	typedef struct IEMTB
882	{
883	/** Next block with the same hash table entry. */
884	struct IEMTB *pNext;
885	/** Usage counter. */
886	uint32_t cUsed;
887	/** The IEMCPU::msRecompilerPollNow last time it was used. */
888	uint32_t msLastUsed;
889	/** The allocation chunk this TB belongs to. */
890	uint8_t idxAllocChunk;
891
892	uint8_t abUnused[3];
893	uint32_t uUnused;
894
895
896	/** @name What uniquely identifies the block.
897	* @{ */
898	RTGCPHYS GCPhysPc;
899	/** IEMTB_F_XXX (i.e. IEM_F_XXX ++). */
900	uint32_t fFlags;
901	union
902	{
903	struct
904	{
905	/*< Relevant CS X86DESCATTR_XXX bits. /
906	uint16_t fAttr;
907	} x86;
908	};
909	/** @} */
910
911	/** Number of opcode ranges. */
912	uint8_t cRanges;
913	/** Statistics: Number of instructions in the block. */
914	uint8_t cInstructions;
915
916	/** Type specific info. */
917	union
918	{
919	struct
920	{
921	/** The call sequence table. */
922	PIEMTHRDEDCALLENTRY paCalls;
923	/** Number of calls in paCalls. */
924	uint16_t cCalls;
925	/** Number of calls allocated. */
926	uint16_t cAllocated;
927	} Thrd;
928	struct
929	{
930	/** The native instructions (PFNIEMTBNATIVE). */
931	PIEMNATIVEINSTR paInstructions;
932	/** Number of instructions pointed to by paInstructions. */
933	uint32_t cInstructions;
934	} Native;
935	/** Generic view for zeroing when freeing. */
936	struct
937	{
938	uintptr_t uPtr;
939	uint32_t uData;
940	} Gen;
941	};
942
943	/** Number of bytes of opcodes stored in pabOpcodes. */
944	uint16_t cbOpcodes;
945	/** The max storage available in the pabOpcodes block. */
946	uint16_t cbOpcodesAllocated;
947	/** Pointer to the opcode bytes this block was recompiled from. */
948	uint8_t *pabOpcodes;
949
950	/* --- 64 byte cache line end --- */
951
952	/** Opcode ranges.
953	*
954	* The opcode checkers and maybe TLB loading functions will use this to figure
955	* out what to do. The parameter will specify an entry and the opcode offset to
956	* start at and the minimum number of bytes to verify (instruction length).
957	*
958	* When VT-x and AMD-V looks up the opcode bytes for an exitting instruction,
959	* they'll first translate RIP (+ cbInstr - 1) to a physical address using the
960	* code TLB (must have a valid entry for that address) and scan the ranges to
961	* locate the corresponding opcodes. Probably.
962	*/
963	struct IEMTBOPCODERANGE
964	{
965	/** Offset within pabOpcodes. */
966	uint16_t offOpcodes;
967	/** Number of bytes. */
968	uint16_t cbOpcodes;
969	/** The page offset. */
970	RT_GCC_EXTENSION
971	uint16_t offPhysPage : 12;
972	/** Unused bits. */
973	RT_GCC_EXTENSION
974	uint16_t u2Unused : 2;
975	/** Index into GCPhysPc + aGCPhysPages for the physical page address. */
976	RT_GCC_EXTENSION
977	uint16_t idxPhysPage : 2;
978	} aRanges[8];
979
980	/** Physical pages that this TB covers.
981	* The GCPhysPc w/o page offset is element zero, so starting here with 1. */
982	RTGCPHYS aGCPhysPages[2];
983	} IEMTB;
984	#pragma pack()
985	AssertCompileMemberOffset(IEMTB, x86, 36);
986	AssertCompileMemberOffset(IEMTB, cRanges, 38);
987	AssertCompileMemberOffset(IEMTB, Thrd, 40);
988	AssertCompileMemberOffset(IEMTB, Thrd.cCalls, 48);
989	AssertCompileMemberOffset(IEMTB, cbOpcodes, 52);
990	AssertCompileMemberSize(IEMTB, aRanges[0], 6);
991	#if 1
992	AssertCompileSize(IEMTB, 128);
993	# define IEMTB_SIZE_IS_POWER_OF_TWO /*< The IEMTB size is a power of two. /
994	#else
995	AssertCompileSize(IEMTB, 168);
996	# undef IEMTB_SIZE_IS_POWER_OF_TWO
997	#endif
998
999	/** Pointer to a translation block. */
1000	typedef IEMTB *PIEMTB;
1001	/** Pointer to a const translation block. */
1002	typedef IEMTB const *PCIEMTB;
1003
1004	/**
1005	* A chunk of memory in the TB allocator.
1006	*/
1007	typedef struct IEMTBCHUNK
1008	{
1009	/** Pointer to the translation blocks in this chunk. */
1010	PIEMTB paTbs;
1011	#ifdef IN_RING0
1012	/** Allocation handle. */
1013	RTR0MEMOBJ hMemObj;
1014	#endif
1015	} IEMTBCHUNK;
1016
1017	/**
1018	* A per-CPU translation block allocator.
1019	*
1020	* Because of how the IEMTBCACHE uses the lower 6 bits of the TB address to keep
1021	* the length of the collision list, and of course also for cache line alignment
1022	* reasons, the TBs must be allocated with at least 64-byte alignment.
1023	* Memory is there therefore allocated using one of the page aligned allocators.
1024	*
1025	*
1026	* To avoid wasting too much memory, it is allocated piecemeal as needed,
1027	* in chunks (IEMTBCHUNK) of 2 MiB or more. The TB has an 8-bit chunk index
1028	* that enables us to quickly calculate the allocation bitmap position when
1029	* freeing the translation block.
1030	*/
1031	typedef struct IEMTBALLOCATOR
1032	{
1033	/** Magic value (IEMTBALLOCATOR_MAGIC). */
1034	uint32_t uMagic;
1035
1036	#ifdef IEMTB_SIZE_IS_POWER_OF_TWO
1037	/** Mask corresponding to cTbsPerChunk - 1. */
1038	uint32_t fChunkMask;
1039	/** Shift count corresponding to cTbsPerChunk. */
1040	uint8_t cChunkShift;
1041	#else
1042	uint32_t uUnused;
1043	uint8_t bUnused;
1044	#endif
1045	/** Number of chunks we're allowed to allocate. */
1046	uint8_t cMaxChunks;
1047	/** Number of chunks currently populated. */
1048	uint16_t cAllocatedChunks;
1049	/** Number of translation blocks per chunk. */
1050	uint32_t cTbsPerChunk;
1051	/** Chunk size. */
1052	uint32_t cbPerChunk;
1053
1054	/** The maximum number of TBs. */
1055	uint32_t cMaxTbs;
1056	/** Total number of TBs in the populated chunks.
1057	* (cAllocatedChunks * cTbsPerChunk) */
1058	uint32_t cTotalTbs;
1059	/** The current number of TBs in use.
1060	* The number of free TBs: cAllocatedTbs - cInUseTbs; */
1061	uint32_t cInUseTbs;
1062	/** Statistics: Number of the cInUseTbs that are native ones. */
1063	uint32_t cNativeTbs;
1064	/** Statistics: Number of the cInUseTbs that are threaded ones. */
1065	uint32_t cThreadedTbs;
1066
1067	/** Where to start pruning TBs from when we're out.
1068	* See iemTbAllocatorAllocSlow for details. */
1069	uint32_t iPruneFrom;
1070	/** Hint about which bit to start scanning the bitmap from. */
1071	uint32_t iStartHint;
1072
1073	/** Statistics: Number of TB allocation calls. */
1074	STAMCOUNTER StatAllocs;
1075	/** Statistics: Number of TB free calls. */
1076	STAMCOUNTER StatFrees;
1077	/** Statistics: Time spend pruning. */
1078	STAMPROFILE StatPrune;
1079
1080	/** The delayed free list (see iemTbAlloctorScheduleForFree). */
1081	PIEMTB pDelayedFreeHead;
1082
1083	/** Allocation chunks. */
1084	IEMTBCHUNK aChunks[256];
1085
1086	/** Allocation bitmap for all possible chunk chunks. */
1087	RT_FLEXIBLE_ARRAY_EXTENSION
1088	uint64_t bmAllocated[RT_FLEXIBLE_ARRAY];
1089	} IEMTBALLOCATOR;
1090	/** Pointer to a TB allocator. */
1091	typedef struct IEMTBALLOCATOR *PIEMTBALLOCATOR;
1092
1093	/** Magic value for the TB allocator (Emmet Harley Cohen). */
1094	#define IEMTBALLOCATOR_MAGIC UINT32_C(0x19900525)
1095
1096
1097	/**
1098	* A per-CPU translation block cache (hash table).
1099	*
1100	* The hash table is allocated once during IEM initialization and size double
1101	* the max TB count, rounded up to the nearest power of two (so we can use and
1102	* AND mask rather than a rest division when hashing).
1103	*/
1104	typedef struct IEMTBCACHE
1105	{
1106	/** Magic value (IEMTBCACHE_MAGIC). */
1107	uint32_t uMagic;
1108	/** Size of the hash table. This is a power of two. */
1109	uint32_t cHash;
1110	/** The mask corresponding to cHash. */
1111	uint32_t uHashMask;
1112	uint32_t uPadding;
1113
1114	/** @name Statistics
1115	* @{ */
1116	/** Number of collisions ever. */
1117	STAMCOUNTER cCollisions;
1118
1119	/** Statistics: Number of TB lookup misses. */
1120	STAMCOUNTER cLookupMisses;
1121	/** Statistics: Number of TB lookup hits (debug only). */
1122	STAMCOUNTER cLookupHits;
1123	STAMCOUNTER auPadding2[3];
1124	/** Statistics: Collision list length pruning. */
1125	STAMPROFILE StatPrune;
1126	/** @} */
1127
1128	/** The hash table itself.
1129	* @note The lower 6 bits of the pointer is used for keeping the collision
1130	* list length, so we can take action when it grows too long.
1131	* This works because TBs are allocated using a 64 byte (or
1132	* higher) alignment from page aligned chunks of memory, so the lower
1133	* 6 bits of the address will always be zero.
1134	* See IEMTBCACHE_PTR_COUNT_MASK, IEMTBCACHE_PTR_MAKE and friends.
1135	*/
1136	RT_FLEXIBLE_ARRAY_EXTENSION
1137	PIEMTB apHash[RT_FLEXIBLE_ARRAY];
1138	} IEMTBCACHE;
1139	/** Pointer to a per-CPU translation block cahce. */
1140	typedef IEMTBCACHE *PIEMTBCACHE;
1141
1142	/** Magic value for IEMTBCACHE (Johnny O'Neal). */
1143	#define IEMTBCACHE_MAGIC UINT32_C(0x19561010)
1144
1145	/** The collision count mask for IEMTBCACHE::apHash entries. */
1146	#define IEMTBCACHE_PTR_COUNT_MASK ((uintptr_t)0x3f)
1147	/** The max collision count for IEMTBCACHE::apHash entries before pruning. */
1148	#define IEMTBCACHE_PTR_MAX_COUNT ((uintptr_t)0x30)
1149	/** Combine a TB pointer and a collision list length into a value for an
1150	* IEMTBCACHE::apHash entry. */
1151	#define IEMTBCACHE_PTR_MAKE(a_pTb, a_cCount) (PIEMTB)((uintptr_t)(a_pTb) \| (a_cCount))
1152	/** Combine a TB pointer and a collision list length into a value for an
1153	* IEMTBCACHE::apHash entry. */
1154	#define IEMTBCACHE_PTR_GET_TB(a_pHashEntry) (PIEMTB)((uintptr_t)(a_pHashEntry) & ~IEMTBCACHE_PTR_COUNT_MASK)
1155	/** Combine a TB pointer and a collision list length into a value for an
1156	* IEMTBCACHE::apHash entry. */
1157	#define IEMTBCACHE_PTR_GET_COUNT(a_pHashEntry) ((uintptr_t)(a_pHashEntry) & IEMTBCACHE_PTR_COUNT_MASK)
1158
1159	/**
1160	* Calculates the hash table slot for a TB from physical PC address and TB flags.
1161	*/
1162	#define IEMTBCACHE_HASH(a_paCache, a_fTbFlags, a_GCPhysPc) \
1163	IEMTBCACHE_HASH_NO_KEY_MASK(a_paCache, (a_fTbFlags) & IEMTB_F_KEY_MASK, a_GCPhysPc)
1164
1165	/**
1166	* Calculates the hash table slot for a TB from physical PC address and TB
1167	* flags, ASSUMING the caller has applied IEMTB_F_KEY_MASK to @a a_fTbFlags.
1168	*/
1169	#define IEMTBCACHE_HASH_NO_KEY_MASK(a_paCache, a_fTbFlags, a_GCPhysPc) \
1170	(((uint32_t)(a_GCPhysPc) ^ (a_fTbFlags)) & (a_paCache)->uHashMask)
1171
1172
1173	/** @name IEMBRANCHED_F_XXX - Branched indicator (IEMCPU::fTbBranched).
1174	*
1175	* These flags parallels IEM_CIMPL_F_BRANCH_XXX.
1176	*
1177	* @{ */
1178	/** Value if no branching happened recently. */
1179	#define IEMBRANCHED_F_NO UINT8_C(0x00)
1180	/** Flag set if direct branch, clear if absolute or indirect. */
1181	#define IEMBRANCHED_F_DIRECT UINT8_C(0x01)
1182	/** Flag set if indirect branch, clear if direct or relative. */
1183	#define IEMBRANCHED_F_INDIRECT UINT8_C(0x02)
1184	/** Flag set if relative branch, clear if absolute or indirect. */
1185	#define IEMBRANCHED_F_RELATIVE UINT8_C(0x04)
1186	/** Flag set if conditional branch, clear if unconditional. */
1187	#define IEMBRANCHED_F_CONDITIONAL UINT8_C(0x08)
1188	/** Flag set if it's a far branch. */
1189	#define IEMBRANCHED_F_FAR UINT8_C(0x10)
1190	/** Flag set (by IEM_MC_REL_JMP_XXX) if it's a zero bytes relative jump. */
1191	#define IEMBRANCHED_F_ZERO UINT8_C(0x20)
1192	/** @} */
1193
1194
1195	/**
1196	* The per-CPU IEM state.
1197	*/
1198	typedef struct IEMCPU
1199	{
1200	/** Info status code that needs to be propagated to the IEM caller.
1201	* This cannot be passed internally, as it would complicate all success
1202	* checks within the interpreter making the code larger and almost impossible
1203	* to get right. Instead, we'll store status codes to pass on here. Each
1204	* source of these codes will perform appropriate sanity checks. */
1205	int32_t rcPassUp; /* 0x00 */
1206	/** Execution flag, IEM_F_XXX. */
1207	uint32_t fExec; /* 0x04 */
1208
1209	/** @name Decoder state.
1210	* @{ */
1211	#ifndef IEM_WITH_OPAQUE_DECODER_STATE
1212	# ifdef IEM_WITH_CODE_TLB
1213	/** The offset of the next instruction byte. */
1214	uint32_t offInstrNextByte; /* 0x08 */
1215	/** The number of bytes available at pbInstrBuf for the current instruction.
1216	* This takes the max opcode length into account so that doesn't need to be
1217	* checked separately. */
1218	uint32_t cbInstrBuf; /* 0x0c */
1219	/** Pointer to the page containing RIP, user specified buffer or abOpcode.
1220	* This can be NULL if the page isn't mappable for some reason, in which
1221	* case we'll do fallback stuff.
1222	*
1223	* If we're executing an instruction from a user specified buffer,
1224	* IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
1225	* aligned pointer but pointer to the user data.
1226	*
1227	* For instructions crossing pages, this will start on the first page and be
1228	* advanced to the next page by the time we've decoded the instruction. This
1229	* therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
1230	*/
1231	uint8_t const pbInstrBuf; / 0x10 */
1232	# if ARCH_BITS == 32
1233	uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
1234	# endif
1235	/** The program counter corresponding to pbInstrBuf.
1236	* This is set to a non-canonical address when we need to invalidate it. */
1237	uint64_t uInstrBufPc; /* 0x18 */
1238	/** The guest physical address corresponding to pbInstrBuf. */
1239	RTGCPHYS GCPhysInstrBuf; /* 0x20 */
1240	/** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
1241	* This takes the CS segment limit into account. */
1242	uint16_t cbInstrBufTotal; /* 0x28 */
1243	/** Offset into pbInstrBuf of the first byte of the current instruction.
1244	* Can be negative to efficiently handle cross page instructions. */
1245	int16_t offCurInstrStart; /* 0x2a */
1246
1247	/** The prefix mask (IEM_OP_PRF_XXX). */
1248	uint32_t fPrefixes; /* 0x2c */
1249	/** The extra REX ModR/M register field bit (REX.R << 3). */
1250	uint8_t uRexReg; /* 0x30 */
1251	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
1252	* (REX.B << 3). */
1253	uint8_t uRexB; /* 0x31 */
1254	/** The extra REX SIB index field bit (REX.X << 3). */
1255	uint8_t uRexIndex; /* 0x32 */
1256
1257	/** The effective segment register (X86_SREG_XXX). */
1258	uint8_t iEffSeg; /* 0x33 */
1259
1260	/** The offset of the ModR/M byte relative to the start of the instruction. */
1261	uint8_t offModRm; /* 0x34 */
1262
1263	# ifdef IEM_WITH_CODE_TLB_AND_OPCODE_BUF
1264	/** The current offset into abOpcode. */
1265	uint8_t offOpcode; /* 0x35 */
1266	# else
1267	uint8_t bUnused; /* 0x35 */
1268	# endif
1269	# else /* !IEM_WITH_CODE_TLB */
1270	/** The size of what has currently been fetched into abOpcode. */
1271	uint8_t cbOpcode; /* 0x08 */
1272	/** The current offset into abOpcode. */
1273	uint8_t offOpcode; /* 0x09 */
1274	/** The offset of the ModR/M byte relative to the start of the instruction. */
1275	uint8_t offModRm; /* 0x0a */
1276
1277	/** The effective segment register (X86_SREG_XXX). */
1278	uint8_t iEffSeg; /* 0x0b */
1279
1280	/** The prefix mask (IEM_OP_PRF_XXX). */
1281	uint32_t fPrefixes; /* 0x0c */
1282	/** The extra REX ModR/M register field bit (REX.R << 3). */
1283	uint8_t uRexReg; /* 0x10 */
1284	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
1285	* (REX.B << 3). */
1286	uint8_t uRexB; /* 0x11 */
1287	/** The extra REX SIB index field bit (REX.X << 3). */
1288	uint8_t uRexIndex; /* 0x12 */
1289
1290	# endif /* !IEM_WITH_CODE_TLB */
1291
1292	/** The effective operand mode. */
1293	IEMMODE enmEffOpSize; /* 0x36, 0x13 */
1294	/** The default addressing mode. */
1295	IEMMODE enmDefAddrMode; /* 0x37, 0x14 */
1296	/** The effective addressing mode. */
1297	IEMMODE enmEffAddrMode; /* 0x38, 0x15 */
1298	/** The default operand mode. */
1299	IEMMODE enmDefOpSize; /* 0x39, 0x16 */
1300
1301	/** Prefix index (VEX.pp) for two byte and three byte tables. */
1302	uint8_t idxPrefix; /* 0x3a, 0x17 */
1303	/** 3rd VEX/EVEX/XOP register.
1304	* Please use IEM_GET_EFFECTIVE_VVVV to access. */
1305	uint8_t uVex3rdReg; /* 0x3b, 0x18 */
1306	/** The VEX/EVEX/XOP length field. */
1307	uint8_t uVexLength; /* 0x3c, 0x19 */
1308	/** Additional EVEX stuff. */
1309	uint8_t fEvexStuff; /* 0x3d, 0x1a */
1310
1311	# ifndef IEM_WITH_CODE_TLB
1312	/** Explicit alignment padding. */
1313	uint8_t abAlignment2a[1]; /* 0x1b */
1314	# endif
1315	/** The FPU opcode (FOP). */
1316	uint16_t uFpuOpcode; /* 0x3e, 0x1c */
1317	# ifndef IEM_WITH_CODE_TLB
1318	/** Explicit alignment padding. */
1319	uint8_t abAlignment2b[2]; /* 0x1e */
1320	# endif
1321
1322	/** The opcode bytes. */
1323	uint8_t abOpcode[15]; /* 0x40, 0x20 */
1324	/** Explicit alignment padding. */
1325	# ifdef IEM_WITH_CODE_TLB
1326	//uint8_t abAlignment2c[0x4f - 0x4f]; /* 0x4f */
1327	# else
1328	uint8_t abAlignment2c[0x4f - 0x2f]; /* 0x2f */
1329	# endif
1330	#else /* IEM_WITH_OPAQUE_DECODER_STATE */
1331	uint8_t abOpaqueDecoder[0x4f - 0x8];
1332	#endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1333	/** @} */
1334
1335
1336	/** The number of active guest memory mappings. */
1337	uint8_t cActiveMappings; /* 0x4f, 0x4f */
1338
1339	/** Records for tracking guest memory mappings. */
1340	struct
1341	{
1342	/** The address of the mapped bytes. */
1343	R3R0PTRTYPE(void *) pv;
1344	/** The access flags (IEM_ACCESS_XXX).
1345	* IEM_ACCESS_INVALID if the entry is unused. */
1346	uint32_t fAccess;
1347	#if HC_ARCH_BITS == 64
1348	uint32_t u32Alignment4; /*< Alignment padding. /
1349	#endif
1350	} aMemMappings[3]; /* 0x50 LB 0x30 */
1351
1352	/** Locking records for the mapped memory. */
1353	union
1354	{
1355	PGMPAGEMAPLOCK Lock;
1356	uint64_t au64Padding[2];
1357	} aMemMappingLocks[3]; /* 0x80 LB 0x30 */
1358
1359	/** Bounce buffer info.
1360	* This runs in parallel to aMemMappings. */
1361	struct
1362	{
1363	/** The physical address of the first byte. */
1364	RTGCPHYS GCPhysFirst;
1365	/** The physical address of the second page. */
1366	RTGCPHYS GCPhysSecond;
1367	/** The number of bytes in the first page. */
1368	uint16_t cbFirst;
1369	/** The number of bytes in the second page. */
1370	uint16_t cbSecond;
1371	/** Whether it's unassigned memory. */
1372	bool fUnassigned;
1373	/** Explicit alignment padding. */
1374	bool afAlignment5[3];
1375	} aMemBbMappings[3]; /* 0xb0 LB 0x48 */
1376
1377	/** The flags of the current exception / interrupt. */
1378	uint32_t fCurXcpt; /* 0xf8 */
1379	/** The current exception / interrupt. */
1380	uint8_t uCurXcpt; /* 0xfc */
1381	/** Exception / interrupt recursion depth. */
1382	int8_t cXcptRecursions; /* 0xfb */
1383
1384	/** The next unused mapping index.
1385	* @todo try find room for this up with cActiveMappings. */
1386	uint8_t iNextMapping; /* 0xfd */
1387	uint8_t abAlignment7[1];
1388
1389	/** Bounce buffer storage.
1390	* This runs in parallel to aMemMappings and aMemBbMappings. */
1391	struct
1392	{
1393	uint8_t ab[512];
1394	} aBounceBuffers[3]; /* 0x100 LB 0x600 */
1395
1396
1397	/** Pointer set jump buffer - ring-3 context. */
1398	R3PTRTYPE(jmp_buf *) pJmpBufR3;
1399	/** Pointer set jump buffer - ring-0 context. */
1400	R0PTRTYPE(jmp_buf *) pJmpBufR0;
1401
1402	/** @todo Should move this near @a fCurXcpt later. */
1403	/** The CR2 for the current exception / interrupt. */
1404	uint64_t uCurXcptCr2;
1405	/** The error code for the current exception / interrupt. */
1406	uint32_t uCurXcptErr;
1407
1408	/** @name Statistics
1409	* @{ */
1410	/** The number of instructions we've executed. */
1411	uint32_t cInstructions;
1412	/** The number of potential exits. */
1413	uint32_t cPotentialExits;
1414	/** The number of bytes data or stack written (mostly for IEMExecOneEx).
1415	* This may contain uncommitted writes. */
1416	uint32_t cbWritten;
1417	/** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
1418	uint32_t cRetInstrNotImplemented;
1419	/** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
1420	uint32_t cRetAspectNotImplemented;
1421	/** Counts informational statuses returned (other than VINF_SUCCESS). */
1422	uint32_t cRetInfStatuses;
1423	/** Counts other error statuses returned. */
1424	uint32_t cRetErrStatuses;
1425	/** Number of times rcPassUp has been used. */
1426	uint32_t cRetPassUpStatus;
1427	/** Number of times RZ left with instruction commit pending for ring-3. */
1428	uint32_t cPendingCommit;
1429	/** Number of long jumps. */
1430	uint32_t cLongJumps;
1431	/** @} */
1432
1433	/** @name Target CPU information.
1434	* @{ */
1435	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
1436	/** The target CPU. */
1437	uint8_t uTargetCpu;
1438	#else
1439	uint8_t bTargetCpuPadding;
1440	#endif
1441	/** For selecting assembly works matching the target CPU EFLAGS behaviour, see
1442	* IEMTARGETCPU_EFL_BEHAVIOR_XXX for values, with the 1st entry for when no
1443	* native host support and the 2nd for when there is.
1444	*
1445	* The two values are typically indexed by a g_CpumHostFeatures bit.
1446	*
1447	* This is for instance used for the BSF & BSR instructions where AMD and
1448	* Intel CPUs produce different EFLAGS. */
1449	uint8_t aidxTargetCpuEflFlavour[2];
1450
1451	/** The CPU vendor. */
1452	CPUMCPUVENDOR enmCpuVendor;
1453	/** @} */
1454
1455	/** @name Host CPU information.
1456	* @{ */
1457	/** The CPU vendor. */
1458	CPUMCPUVENDOR enmHostCpuVendor;
1459	/** @} */
1460
1461	/** Counts RDMSR \#GP(0) LogRel(). */
1462	uint8_t cLogRelRdMsr;
1463	/** Counts WRMSR \#GP(0) LogRel(). */
1464	uint8_t cLogRelWrMsr;
1465	/** Alignment padding. */
1466	uint8_t abAlignment9[46];
1467
1468	/** @name Recompilation
1469	* @{ */
1470	/** Pointer to the current translation block.
1471	* This can either be one being executed or one being compiled. */
1472	R3PTRTYPE(PIEMTB) pCurTbR3;
1473	/** Fixed TB used for threaded recompilation.
1474	* This is allocated once with maxed-out sizes and re-used afterwards. */
1475	R3PTRTYPE(PIEMTB) pThrdCompileTbR3;
1476	/** Pointer to the ring-3 TB cache for this EMT. */
1477	R3PTRTYPE(PIEMTBCACHE) pTbCacheR3;
1478	/** The PC (RIP) at the start of pCurTbR3/pCurTbR0.
1479	* The TBs are based on physical addresses, so this is needed to correleated
1480	* RIP to opcode bytes stored in the TB (AMD-V / VT-x). */
1481	uint64_t uCurTbStartPc;
1482	/** Number of threaded TBs executed. */
1483	uint64_t cTbExecThreaded;
1484	/** Number of native TBs executed. */
1485	uint64_t cTbExecNative;
1486	/** Whether we need to check the opcode bytes for the current instruction.
1487	* This is set by a previous instruction if it modified memory or similar. */
1488	bool fTbCheckOpcodes;
1489	/** Indicates whether and how we just branched - IEMBRANCHED_F_XXX. */
1490	uint8_t fTbBranched;
1491	/** Set when GCPhysInstrBuf is updated because of a page crossing. */
1492	bool fTbCrossedPage;
1493	/** Whether to end the current TB. */
1494	bool fEndTb;
1495	/** Number of instructions before we need emit an IRQ check call again.
1496	* This helps making sure we don't execute too long w/o checking for
1497	* interrupts and immediately following instructions that may enable
1498	* interrupts (e.g. POPF, IRET, STI). With STI an additional hack is
1499	* required to make sure we check following the next instruction as well, see
1500	* fTbCurInstrIsSti. */
1501	uint8_t cInstrTillIrqCheck;
1502	/** Indicates that the current instruction is an STI. This is set by the
1503	* iemCImpl_sti code and subsequently cleared by the recompiler. */
1504	bool fTbCurInstrIsSti;
1505	/** Spaced reserved for recompiler data / alignment. */
1506	bool afRecompilerStuff1[2+4];
1507	/** The virtual sync time at the last timer poll call. */
1508	uint32_t msRecompilerPollNow;
1509	/** The IEM_CIMPL_F_XXX mask for the current instruction. */
1510	uint32_t fTbCurInstr;
1511	/** The IEM_CIMPL_F_XXX mask for the previous instruction. */
1512	uint32_t fTbPrevInstr;
1513	/** Previous GCPhysInstrBuf value - only valid if fTbCrossedPage is set. */
1514	RTGCPHYS GCPhysInstrBufPrev;
1515	/** Copy of IEMCPU::GCPhysInstrBuf after decoding a branch instruction.
1516	* This is used together with fTbBranched and GCVirtTbBranchSrcBuf to determin
1517	* whether a branch instruction jumps to a new page or stays within the
1518	* current one. */
1519	RTGCPHYS GCPhysTbBranchSrcBuf;
1520	/** Copy of IEMCPU::uInstrBufPc after decoding a branch instruction. */
1521	uint64_t GCVirtTbBranchSrcBuf;
1522	/** Pointer to the ring-3 TB allocator for this EMT. */
1523	R3PTRTYPE(PIEMTBALLOCATOR) pTbAllocatorR3;
1524	/** Pointer to the ring-3 executable memory allocator for this EMT. */
1525	R3PTRTYPE(struct IEMEXECMEMALLOCATOR *) pExecMemAllocatorR3;
1526	/** Pointer to the native recompiler state for ring-3. */
1527	R3PTRTYPE(struct IEMRECOMPILERSTATE *) pNativeRecompilerStateR3;
1528	/** Alignment padding. */
1529	uint64_t auAlignment10[4];
1530	/** Statistics: Times TB execution was broken off before reaching the end. */
1531	STAMCOUNTER StatTbExecBreaks;
1532	/** Statistics: Times BltIn_CheckIrq breaks out of the TB. */
1533	STAMCOUNTER StatCheckIrqBreaks;
1534	/** Statistics: Times BltIn_CheckMode breaks out of the TB. */
1535	STAMCOUNTER StatCheckModeBreaks;
1536	/** Statistics: Times a post jump target check missed and had to find new TB. */
1537	STAMCOUNTER StatCheckBranchMisses;
1538	/** Statistics: Times a jump or page crossing required a TB with CS.LIM checking. */
1539	STAMCOUNTER StatCheckNeedCsLimChecking;
1540	/** Threaded TB statistics: Number of instructions per TB. */
1541	STAMPROFILE StatTbThreadedInstr;
1542	/** Threaded TB statistics: Number of calls per TB. */
1543	STAMPROFILE StatTbThreadedCalls;
1544	/** Native TB statistics: Native code size per TB. */
1545	STAMPROFILE StatTbNativeCode;
1546	/** Native TB statistics: Profiling native recompilation. */
1547	STAMPROFILE StatNativeRecompilation;
1548	/** @} */
1549
1550	/** Data TLB.
1551	* @remarks Must be 64-byte aligned. */
1552	IEMTLB DataTlb;
1553	/** Instruction TLB.
1554	* @remarks Must be 64-byte aligned. */
1555	IEMTLB CodeTlb;
1556
1557	/** Exception statistics. */
1558	STAMCOUNTER aStatXcpts[32];
1559	/** Interrupt statistics. */
1560	uint32_t aStatInts[256];
1561
1562	#if defined(VBOX_WITH_STATISTICS) && !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
1563	/** Instruction statistics for ring-0/raw-mode. */
1564	IEMINSTRSTATS StatsRZ;
1565	/** Instruction statistics for ring-3. */
1566	IEMINSTRSTATS StatsR3;
1567	#endif
1568	} IEMCPU;
1569	AssertCompileMemberOffset(IEMCPU, cActiveMappings, 0x4f);
1570	AssertCompileMemberAlignment(IEMCPU, aMemMappings, 16);
1571	AssertCompileMemberAlignment(IEMCPU, aMemMappingLocks, 16);
1572	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 64);
1573	AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
1574	AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
1575
1576	/** Pointer to the per-CPU IEM state. */
1577	typedef IEMCPU *PIEMCPU;
1578	/** Pointer to the const per-CPU IEM state. */
1579	typedef IEMCPU const *PCIEMCPU;
1580
1581
1582	/** @def IEM_GET_CTX
1583	* Gets the guest CPU context for the calling EMT.
1584	* @returns PCPUMCTX
1585	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1586	*/
1587	#define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
1588
1589	/** @def IEM_CTX_ASSERT
1590	* Asserts that the @a a_fExtrnMbz is present in the CPU context.
1591	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1592	* @param a_fExtrnMbz The mask of CPUMCTX_EXTRN_XXX flags that must be zero.
1593	*/
1594	#define IEM_CTX_ASSERT(a_pVCpu, a_fExtrnMbz) \
1595	AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
1596	("fExtrn=%#RX64 & fExtrnMbz=%#RX64 -> %#RX64\n", \
1597	(a_pVCpu)->cpum.GstCtx.fExtrn, (a_fExtrnMbz), (a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz) ))
1598
1599	/** @def IEM_CTX_IMPORT_RET
1600	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
1601	*
1602	* Will call the keep to import the bits as needed.
1603	*
1604	* Returns on import failure.
1605	*
1606	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1607	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
1608	*/
1609	#define IEM_CTX_IMPORT_RET(a_pVCpu, a_fExtrnImport) \
1610	do { \
1611	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
1612	{ /* likely */ } \
1613	else \
1614	{ \
1615	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
1616	AssertRCReturn(rcCtxImport, rcCtxImport); \
1617	} \
1618	} while (0)
1619
1620	/** @def IEM_CTX_IMPORT_NORET
1621	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
1622	*
1623	* Will call the keep to import the bits as needed.
1624	*
1625	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1626	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
1627	*/
1628	#define IEM_CTX_IMPORT_NORET(a_pVCpu, a_fExtrnImport) \
1629	do { \
1630	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
1631	{ /* likely */ } \
1632	else \
1633	{ \
1634	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
1635	AssertLogRelRC(rcCtxImport); \
1636	} \
1637	} while (0)
1638
1639	/** @def IEM_CTX_IMPORT_JMP
1640	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
1641	*
1642	* Will call the keep to import the bits as needed.
1643	*
1644	* Jumps on import failure.
1645	*
1646	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1647	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
1648	*/
1649	#define IEM_CTX_IMPORT_JMP(a_pVCpu, a_fExtrnImport) \
1650	do { \
1651	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
1652	{ /* likely */ } \
1653	else \
1654	{ \
1655	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
1656	AssertRCStmt(rcCtxImport, IEM_DO_LONGJMP(pVCpu, rcCtxImport)); \
1657	} \
1658	} while (0)
1659
1660
1661
1662	/** @def IEM_GET_TARGET_CPU
1663	* Gets the current IEMTARGETCPU value.
1664	* @returns IEMTARGETCPU value.
1665	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1666	*/
1667	#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
1668	# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
1669	#else
1670	# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
1671	#endif
1672
1673	/** @def IEM_GET_INSTR_LEN
1674	* Gets the instruction length. */
1675	#ifdef IEM_WITH_CODE_TLB
1676	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
1677	#else
1678	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
1679	#endif
1680
1681	/** @def IEM_TRY_SETJMP
1682	* Wrapper around setjmp / try, hiding all the ugly differences.
1683	*
1684	* @note Use with extreme care as this is a fragile macro.
1685	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
1686	* @param a_rcTarget The variable that should receive the status code in case
1687	* of a longjmp/throw.
1688	*/
1689	/** @def IEM_TRY_SETJMP_AGAIN
1690	* For when setjmp / try is used again in the same variable scope as a previous
1691	* IEM_TRY_SETJMP invocation.
1692	*/
1693	/** @def IEM_CATCH_LONGJMP_BEGIN
1694	* Start wrapper for catch / setjmp-else.
1695	*
1696	* This will set up a scope.
1697	*
1698	* @note Use with extreme care as this is a fragile macro.
1699	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
1700	* @param a_rcTarget The variable that should receive the status code in case
1701	* of a longjmp/throw.
1702	*/
1703	/** @def IEM_CATCH_LONGJMP_END
1704	* End wrapper for catch / setjmp-else.
1705	*
1706	* This will close the scope set up by IEM_CATCH_LONGJMP_BEGIN and clean up the
1707	* state.
1708	*
1709	* @note Use with extreme care as this is a fragile macro.
1710	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
1711	*/
1712	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
1713	# ifdef IEM_WITH_THROW_CATCH
1714	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
1715	a_rcTarget = VINF_SUCCESS; \
1716	try
1717	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
1718	IEM_TRY_SETJMP(a_pVCpu, a_rcTarget)
1719	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
1720	catch (int rcThrown) \
1721	{ \
1722	a_rcTarget = rcThrown
1723	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
1724	} \
1725	((void)0)
1726	# else /* !IEM_WITH_THROW_CATCH */
1727	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
1728	jmp_buf JmpBuf; \
1729	jmp_buf * volatile pSavedJmpBuf = pVCpu->iem.s.CTX_SUFF(pJmpBuf); \
1730	pVCpu->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
1731	if ((rcStrict = setjmp(JmpBuf)) == 0)
1732	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
1733	pSavedJmpBuf = pVCpu->iem.s.CTX_SUFF(pJmpBuf); \
1734	pVCpu->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
1735	if ((rcStrict = setjmp(JmpBuf)) == 0)
1736	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
1737	else \
1738	{ \
1739	((void)0)
1740	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
1741	} \
1742	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = pSavedJmpBuf
1743	# endif /* !IEM_WITH_THROW_CATCH */
1744	#endif /* IEM_WITH_SETJMP */
1745
1746
1747	/**
1748	* Shared per-VM IEM data.
1749	*/
1750	typedef struct IEM
1751	{
1752	/** The VMX APIC-access page handler type. */
1753	PGMPHYSHANDLERTYPE hVmxApicAccessPage;
1754	#ifndef VBOX_WITHOUT_CPUID_HOST_CALL
1755	/** Set if the CPUID host call functionality is enabled. */
1756	bool fCpuIdHostCall;
1757	#endif
1758	} IEM;
1759
1760
1761
1762	/** @name IEM_ACCESS_XXX - Access details.
1763	* @{ */
1764	#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
1765	#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
1766	#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
1767	#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
1768	#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
1769	#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
1770	#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
1771	#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
1772	#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
1773	#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
1774	/** The writes are partial, so if initialize the bounce buffer with the
1775	* orignal RAM content. */
1776	#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
1777	/** Used in aMemMappings to indicate that the entry is bounce buffered. */
1778	#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
1779	/** Bounce buffer with ring-3 write pending, first page. */
1780	#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
1781	/** Bounce buffer with ring-3 write pending, second page. */
1782	#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
1783	/** Not locked, accessed via the TLB. */
1784	#define IEM_ACCESS_NOT_LOCKED UINT32_C(0x00001000)
1785	/** Valid bit mask. */
1786	#define IEM_ACCESS_VALID_MASK UINT32_C(0x00001fff)
1787	/** Shift count for the TLB flags (upper word). */
1788	#define IEM_ACCESS_SHIFT_TLB_FLAGS 16
1789
1790	/** Read+write data alias. */
1791	#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
1792	/** Write data alias. */
1793	#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
1794	/** Read data alias. */
1795	#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_DATA)
1796	/** Instruction fetch alias. */
1797	#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_WHAT_CODE)
1798	/** Stack write alias. */
1799	#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
1800	/** Stack read alias. */
1801	#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_STACK)
1802	/** Stack read+write alias. */
1803	#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
1804	/** Read system table alias. */
1805	#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_SYS)
1806	/** Read+write system table alias. */
1807	#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_SYS)
1808	/** @} */
1809
1810	/** @name Prefix constants (IEMCPU::fPrefixes)
1811	* @{ */
1812	#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /*< CS segment prefix (0x2e). /
1813	#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /*< SS segment prefix (0x36). /
1814	#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /*< DS segment prefix (0x3e). /
1815	#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /*< ES segment prefix (0x26). /
1816	#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /*< FS segment prefix (0x64). /
1817	#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /*< GS segment prefix (0x65). /
1818	#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
1819
1820	#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /*< Operand size prefix (0x66). /
1821	#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /*< REX.W prefix (0x48-0x4f). /
1822	#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /*< Address size prefix (0x67). /
1823
1824	#define IEM_OP_PRF_LOCK RT_BIT_32(16) /*< Lock prefix (0xf0). /
1825	#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /*< Repeat-not-zero prefix (0xf2). /
1826	#define IEM_OP_PRF_REPZ RT_BIT_32(18) /*< Repeat-if-zero prefix (0xf3). /
1827
1828	#define IEM_OP_PRF_REX RT_BIT_32(24) /*< Any REX prefix (0x40-0x4f). /
1829	#define IEM_OP_PRF_REX_R RT_BIT_32(25) /*< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). /
1830	#define IEM_OP_PRF_REX_B RT_BIT_32(26) /*< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). /
1831	#define IEM_OP_PRF_REX_X RT_BIT_32(27) /*< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). /
1832	/** Mask with all the REX prefix flags.
1833	* This is generally for use when needing to undo the REX prefixes when they
1834	* are followed legacy prefixes and therefore does not immediately preceed
1835	* the first opcode byte.
1836	* For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
1837	#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX \| IEM_OP_PRF_REX_R \| IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X \| IEM_OP_PRF_SIZE_REX_W )
1838
1839	#define IEM_OP_PRF_VEX RT_BIT_32(28) /*< Indiciates VEX prefix. /
1840	#define IEM_OP_PRF_EVEX RT_BIT_32(29) /*< Indiciates EVEX prefix. /
1841	#define IEM_OP_PRF_XOP RT_BIT_32(30) /*< Indiciates XOP prefix. /
1842	/** @} */
1843
1844	/** @name IEMOPFORM_XXX - Opcode forms
1845	* @note These are ORed together with IEMOPHINT_XXX.
1846	* @{ */
1847	/** ModR/M: reg, r/m */
1848	#define IEMOPFORM_RM 0
1849	/** ModR/M: reg, r/m (register) */
1850	#define IEMOPFORM_RM_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
1851	/** ModR/M: reg, r/m (memory) */
1852	#define IEMOPFORM_RM_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
1853	/** ModR/M: reg, r/m */
1854	#define IEMOPFORM_RMI 1
1855	/** ModR/M: reg, r/m (register) */
1856	#define IEMOPFORM_RMI_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
1857	/** ModR/M: reg, r/m (memory) */
1858	#define IEMOPFORM_RMI_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
1859	/** ModR/M: r/m, reg */
1860	#define IEMOPFORM_MR 2
1861	/** ModR/M: r/m (register), reg */
1862	#define IEMOPFORM_MR_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
1863	/** ModR/M: r/m (memory), reg */
1864	#define IEMOPFORM_MR_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
1865	/** ModR/M: r/m, reg */
1866	#define IEMOPFORM_MRI 3
1867	/** ModR/M: r/m (register), reg */
1868	#define IEMOPFORM_MRI_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
1869	/** ModR/M: r/m (memory), reg */
1870	#define IEMOPFORM_MRI_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
1871	/** ModR/M: r/m only */
1872	#define IEMOPFORM_M 4
1873	/** ModR/M: r/m only (register). */
1874	#define IEMOPFORM_M_REG (IEMOPFORM_M \| IEMOPFORM_MOD3)
1875	/** ModR/M: r/m only (memory). */
1876	#define IEMOPFORM_M_MEM (IEMOPFORM_M \| IEMOPFORM_NOT_MOD3)
1877	/** ModR/M: reg only */
1878	#define IEMOPFORM_R 5
1879
1880	/** VEX+ModR/M: reg, r/m */
1881	#define IEMOPFORM_VEX_RM 8
1882	/** VEX+ModR/M: reg, r/m (register) */
1883	#define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM \| IEMOPFORM_MOD3)
1884	/** VEX+ModR/M: reg, r/m (memory) */
1885	#define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM \| IEMOPFORM_NOT_MOD3)
1886	/** VEX+ModR/M: r/m, reg */
1887	#define IEMOPFORM_VEX_MR 9
1888	/** VEX+ModR/M: r/m (register), reg */
1889	#define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR \| IEMOPFORM_MOD3)
1890	/** VEX+ModR/M: r/m (memory), reg */
1891	#define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR \| IEMOPFORM_NOT_MOD3)
1892	/** VEX+ModR/M: r/m only */
1893	#define IEMOPFORM_VEX_M 10
1894	/** VEX+ModR/M: r/m only (register). */
1895	#define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M \| IEMOPFORM_MOD3)
1896	/** VEX+ModR/M: r/m only (memory). */
1897	#define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M \| IEMOPFORM_NOT_MOD3)
1898	/** VEX+ModR/M: reg only */
1899	#define IEMOPFORM_VEX_R 11
1900	/** VEX+ModR/M: reg, vvvv, r/m */
1901	#define IEMOPFORM_VEX_RVM 12
1902	/** VEX+ModR/M: reg, vvvv, r/m (register). */
1903	#define IEMOPFORM_VEX_RVM_REG (IEMOPFORM_VEX_RVM \| IEMOPFORM_MOD3)
1904	/** VEX+ModR/M: reg, vvvv, r/m (memory). */
1905	#define IEMOPFORM_VEX_RVM_MEM (IEMOPFORM_VEX_RVM \| IEMOPFORM_NOT_MOD3)
1906	/** VEX+ModR/M: reg, r/m, vvvv */
1907	#define IEMOPFORM_VEX_RMV 13
1908	/** VEX+ModR/M: reg, r/m, vvvv (register). */
1909	#define IEMOPFORM_VEX_RMV_REG (IEMOPFORM_VEX_RMV \| IEMOPFORM_MOD3)
1910	/** VEX+ModR/M: reg, r/m, vvvv (memory). */
1911	#define IEMOPFORM_VEX_RMV_MEM (IEMOPFORM_VEX_RMV \| IEMOPFORM_NOT_MOD3)
1912	/** VEX+ModR/M: reg, r/m, imm8 */
1913	#define IEMOPFORM_VEX_RMI 14
1914	/** VEX+ModR/M: reg, r/m, imm8 (register). */
1915	#define IEMOPFORM_VEX_RMI_REG (IEMOPFORM_VEX_RMI \| IEMOPFORM_MOD3)
1916	/** VEX+ModR/M: reg, r/m, imm8 (memory). */
1917	#define IEMOPFORM_VEX_RMI_MEM (IEMOPFORM_VEX_RMI \| IEMOPFORM_NOT_MOD3)
1918	/** VEX+ModR/M: r/m, vvvv, reg */
1919	#define IEMOPFORM_VEX_MVR 15
1920	/** VEX+ModR/M: r/m, vvvv, reg (register) */
1921	#define IEMOPFORM_VEX_MVR_REG (IEMOPFORM_VEX_MVR \| IEMOPFORM_MOD3)
1922	/** VEX+ModR/M: r/m, vvvv, reg (memory) */
1923	#define IEMOPFORM_VEX_MVR_MEM (IEMOPFORM_VEX_MVR \| IEMOPFORM_NOT_MOD3)
1924	/** VEX+ModR/M+/n: vvvv, r/m */
1925	#define IEMOPFORM_VEX_VM 16
1926	/** VEX+ModR/M+/n: vvvv, r/m (register) */
1927	#define IEMOPFORM_VEX_VM_REG (IEMOPFORM_VEX_VM \| IEMOPFORM_MOD3)
1928	/** VEX+ModR/M+/n: vvvv, r/m (memory) */
1929	#define IEMOPFORM_VEX_VM_MEM (IEMOPFORM_VEX_VM \| IEMOPFORM_NOT_MOD3)
1930
1931	/** Fixed register instruction, no R/M. */
1932	#define IEMOPFORM_FIXED 32
1933
1934	/** The r/m is a register. */
1935	#define IEMOPFORM_MOD3 RT_BIT_32(8)
1936	/** The r/m is a memory access. */
1937	#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
1938	/** @} */
1939
1940	/** @name IEMOPHINT_XXX - Additional Opcode Hints
1941	* @note These are ORed together with IEMOPFORM_XXX.
1942	* @{ */
1943	/** Ignores the operand size prefix (66h). */
1944	#define IEMOPHINT_IGNORES_OZ_PFX RT_BIT_32(10)
1945	/** Ignores REX.W (aka WIG). */
1946	#define IEMOPHINT_IGNORES_REXW RT_BIT_32(11)
1947	/** Both the operand size prefixes (66h + REX.W) are ignored. */
1948	#define IEMOPHINT_IGNORES_OP_SIZES (IEMOPHINT_IGNORES_OZ_PFX \| IEMOPHINT_IGNORES_REXW)
1949	/** Allowed with the lock prefix. */
1950	#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
1951	/** The VEX.L value is ignored (aka LIG). */
1952	#define IEMOPHINT_VEX_L_IGNORED RT_BIT_32(12)
1953	/** The VEX.L value must be zero (i.e. 128-bit width only). */
1954	#define IEMOPHINT_VEX_L_ZERO RT_BIT_32(13)
1955	/** The VEX.V value must be zero. */
1956	#define IEMOPHINT_VEX_V_ZERO RT_BIT_32(14)
1957
1958	/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
1959	#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
1960	/** @} */
1961
1962	/**
1963	* Possible hardware task switch sources.
1964	*/
1965	typedef enum IEMTASKSWITCH
1966	{
1967	/** Task switch caused by an interrupt/exception. */
1968	IEMTASKSWITCH_INT_XCPT = 1,
1969	/** Task switch caused by a far CALL. */
1970	IEMTASKSWITCH_CALL,
1971	/** Task switch caused by a far JMP. */
1972	IEMTASKSWITCH_JUMP,
1973	/** Task switch caused by an IRET. */
1974	IEMTASKSWITCH_IRET
1975	} IEMTASKSWITCH;
1976	AssertCompileSize(IEMTASKSWITCH, 4);
1977
1978	/**
1979	* Possible CrX load (write) sources.
1980	*/
1981	typedef enum IEMACCESSCRX
1982	{
1983	/** CrX access caused by 'mov crX' instruction. */
1984	IEMACCESSCRX_MOV_CRX,
1985	/** CrX (CR0) write caused by 'lmsw' instruction. */
1986	IEMACCESSCRX_LMSW,
1987	/** CrX (CR0) write caused by 'clts' instruction. */
1988	IEMACCESSCRX_CLTS,
1989	/** CrX (CR0) read caused by 'smsw' instruction. */
1990	IEMACCESSCRX_SMSW
1991	} IEMACCESSCRX;
1992
1993	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1994	/** @name IEM_SLAT_FAIL_XXX - Second-level address translation failure information.
1995	*
1996	* These flags provide further context to SLAT page-walk failures that could not be
1997	* determined by PGM (e.g, PGM is not privy to memory access permissions).
1998	*
1999	* @{
2000	*/
2001	/** Translating a nested-guest linear address failed accessing a nested-guest
2002	* physical address. */
2003	# define IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR RT_BIT_32(0)
2004	/** Translating a nested-guest linear address failed accessing a
2005	* paging-structure entry or updating accessed/dirty bits. */
2006	# define IEM_SLAT_FAIL_LINEAR_TO_PAGE_TABLE RT_BIT_32(1)
2007	/** @} */
2008
2009	DECLCALLBACK(FNPGMPHYSHANDLER) iemVmxApicAccessPageHandler;
2010	# ifndef IN_RING3
2011	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) iemVmxApicAccessPagePfHandler;
2012	# endif
2013	#endif
2014
2015	/**
2016	* Indicates to the verifier that the given flag set is undefined.
2017	*
2018	* Can be invoked again to add more flags.
2019	*
2020	* This is a NOOP if the verifier isn't compiled in.
2021	*
2022	* @note We're temporarily keeping this until code is converted to new
2023	* disassembler style opcode handling.
2024	*/
2025	#define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
2026
2027
2028	/** @def IEM_DECL_IMPL_TYPE
2029	* For typedef'ing an instruction implementation function.
2030	*
2031	* @param a_RetType The return type.
2032	* @param a_Name The name of the type.
2033	* @param a_ArgList The argument list enclosed in parentheses.
2034	*/
2035
2036	/** @def IEM_DECL_IMPL_DEF
2037	* For defining an instruction implementation function.
2038	*
2039	* @param a_RetType The return type.
2040	* @param a_Name The name of the type.
2041	* @param a_ArgList The argument list enclosed in parentheses.
2042	*/
2043
2044	#if defined(__GNUC__) && defined(RT_ARCH_X86)
2045	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2046	__attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
2047	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2048	__attribute__((__fastcall__, __nothrow__)) DECL_HIDDEN_ONLY(a_RetType) a_Name a_ArgList
2049	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2050	__attribute__((__fastcall__, __nothrow__)) DECL_HIDDEN_ONLY(a_RetType) a_Name a_ArgList
2051
2052	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
2053	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2054	a_RetType (__fastcall a_Name) a_ArgList
2055	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2056	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
2057	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2058	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
2059
2060	#elif __cplusplus >= 201700 /* P0012R1 support */
2061	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2062	a_RetType (VBOXCALL a_Name) a_ArgList RT_NOEXCEPT
2063	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2064	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList RT_NOEXCEPT
2065	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2066	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList RT_NOEXCEPT
2067
2068	#else
2069	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2070	a_RetType (VBOXCALL a_Name) a_ArgList
2071	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2072	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList
2073	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2074	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList
2075
2076	#endif
2077
2078	/** Defined in IEMAllAImplC.cpp but also used by IEMAllAImplA.asm. */
2079	RT_C_DECLS_BEGIN
2080	extern uint8_t const g_afParity[256];
2081	RT_C_DECLS_END
2082
2083
2084	/** @name Arithmetic assignment operations on bytes (binary).
2085	* @{ */
2086	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU8, (uint8_t pu8Dst, uint8_t u8Src, uint32_t pEFlags));
2087	typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
2088	FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
2089	FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
2090	FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
2091	FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
2092	FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
2093	FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
2094	FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
2095	/** @} */
2096
2097	/** @name Arithmetic assignment operations on words (binary).
2098	* @{ */
2099	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU16, (uint16_t pu16Dst, uint16_t u16Src, uint32_t pEFlags));
2100	typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
2101	FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
2102	FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
2103	FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
2104	FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
2105	FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
2106	FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
2107	FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
2108	/** @} */
2109
2110	/** @name Arithmetic assignment operations on double words (binary).
2111	* @{ */
2112	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU32, (uint32_t pu32Dst, uint32_t u32Src, uint32_t pEFlags));
2113	typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
2114	FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
2115	FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
2116	FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
2117	FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
2118	FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
2119	FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
2120	FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
2121	FNIEMAIMPLBINU32 iemAImpl_blsi_u32, iemAImpl_blsi_u32_fallback;
2122	FNIEMAIMPLBINU32 iemAImpl_blsr_u32, iemAImpl_blsr_u32_fallback;
2123	FNIEMAIMPLBINU32 iemAImpl_blsmsk_u32, iemAImpl_blsmsk_u32_fallback;
2124	/** @} */
2125
2126	/** @name Arithmetic assignment operations on quad words (binary).
2127	* @{ */
2128	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU64, (uint64_t pu64Dst, uint64_t u64Src, uint32_t pEFlags));
2129	typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
2130	FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
2131	FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
2132	FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
2133	FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
2134	FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
2135	FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
2136	FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
2137	FNIEMAIMPLBINU64 iemAImpl_blsi_u64, iemAImpl_blsi_u64_fallback;
2138	FNIEMAIMPLBINU64 iemAImpl_blsr_u64, iemAImpl_blsr_u64_fallback;
2139	FNIEMAIMPLBINU64 iemAImpl_blsmsk_u64, iemAImpl_blsmsk_u64_fallback;
2140	/** @} */
2141
2142	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINROU8,(uint8_t const pu8Dst, uint8_t u8Src, uint32_t pEFlags));
2143	typedef FNIEMAIMPLBINROU8 *PFNIEMAIMPLBINROU8;
2144	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINROU16,(uint16_t const pu16Dst, uint16_t u16Src, uint32_t pEFlags));
2145	typedef FNIEMAIMPLBINROU16 *PFNIEMAIMPLBINROU16;
2146	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINROU32,(uint32_t const pu32Dst, uint32_t u32Src, uint32_t pEFlags));
2147	typedef FNIEMAIMPLBINROU32 *PFNIEMAIMPLBINROU32;
2148	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINROU64,(uint64_t const pu64Dst, uint64_t u64Src, uint32_t pEFlags));
2149	typedef FNIEMAIMPLBINROU64 *PFNIEMAIMPLBINROU64;
2150
2151	/** @name Compare operations (thrown in with the binary ops).
2152	* @{ */
2153	FNIEMAIMPLBINROU8 iemAImpl_cmp_u8;
2154	FNIEMAIMPLBINROU16 iemAImpl_cmp_u16;
2155	FNIEMAIMPLBINROU32 iemAImpl_cmp_u32;
2156	FNIEMAIMPLBINROU64 iemAImpl_cmp_u64;
2157	/** @} */
2158
2159	/** @name Test operations (thrown in with the binary ops).
2160	* @{ */
2161	FNIEMAIMPLBINROU8 iemAImpl_test_u8;
2162	FNIEMAIMPLBINROU16 iemAImpl_test_u16;
2163	FNIEMAIMPLBINROU32 iemAImpl_test_u32;
2164	FNIEMAIMPLBINROU64 iemAImpl_test_u64;
2165	/** @} */
2166
2167	/** @name Bit operations operations (thrown in with the binary ops).
2168	* @{ */
2169	FNIEMAIMPLBINROU16 iemAImpl_bt_u16;
2170	FNIEMAIMPLBINROU32 iemAImpl_bt_u32;
2171	FNIEMAIMPLBINROU64 iemAImpl_bt_u64;
2172	FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
2173	FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
2174	FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
2175	FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
2176	FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
2177	FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
2178	FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
2179	FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
2180	FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
2181	/** @} */
2182
2183	/** @name Arithmetic three operand operations on double words (binary).
2184	* @{ */
2185	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32, (uint32_t pu32Dst, uint32_t u32Src1, uint32_t u32Src2, uint32_t pEFlags));
2186	typedef FNIEMAIMPLBINVEXU32 *PFNIEMAIMPLBINVEXU32;
2187	FNIEMAIMPLBINVEXU32 iemAImpl_andn_u32, iemAImpl_andn_u32_fallback;
2188	FNIEMAIMPLBINVEXU32 iemAImpl_bextr_u32, iemAImpl_bextr_u32_fallback;
2189	FNIEMAIMPLBINVEXU32 iemAImpl_bzhi_u32, iemAImpl_bzhi_u32_fallback;
2190	/** @} */
2191
2192	/** @name Arithmetic three operand operations on quad words (binary).
2193	* @{ */
2194	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64, (uint64_t pu64Dst, uint64_t u64Src1, uint64_t u64Src2, uint32_t pEFlags));
2195	typedef FNIEMAIMPLBINVEXU64 *PFNIEMAIMPLBINVEXU64;
2196	FNIEMAIMPLBINVEXU64 iemAImpl_andn_u64, iemAImpl_andn_u64_fallback;
2197	FNIEMAIMPLBINVEXU64 iemAImpl_bextr_u64, iemAImpl_bextr_u64_fallback;
2198	FNIEMAIMPLBINVEXU64 iemAImpl_bzhi_u64, iemAImpl_bzhi_u64_fallback;
2199	/** @} */
2200
2201	/** @name Arithmetic three operand operations on double words w/o EFLAGS (binary).
2202	* @{ */
2203	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32NOEFL, (uint32_t *pu32Dst, uint32_t u32Src1, uint32_t u32Src2));
2204	typedef FNIEMAIMPLBINVEXU32NOEFL *PFNIEMAIMPLBINVEXU32NOEFL;
2205	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pdep_u32, iemAImpl_pdep_u32_fallback;
2206	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pext_u32, iemAImpl_pext_u32_fallback;
2207	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_sarx_u32, iemAImpl_sarx_u32_fallback;
2208	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shlx_u32, iemAImpl_shlx_u32_fallback;
2209	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shrx_u32, iemAImpl_shrx_u32_fallback;
2210	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_rorx_u32;
2211	/** @} */
2212
2213	/** @name Arithmetic three operand operations on quad words w/o EFLAGS (binary).
2214	* @{ */
2215	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64NOEFL, (uint64_t *pu64Dst, uint64_t u64Src1, uint64_t u64Src2));
2216	typedef FNIEMAIMPLBINVEXU64NOEFL *PFNIEMAIMPLBINVEXU64NOEFL;
2217	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pdep_u64, iemAImpl_pdep_u64_fallback;
2218	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pext_u64, iemAImpl_pext_u64_fallback;
2219	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_sarx_u64, iemAImpl_sarx_u64_fallback;
2220	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shlx_u64, iemAImpl_shlx_u64_fallback;
2221	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shrx_u64, iemAImpl_shrx_u64_fallback;
2222	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_rorx_u64;
2223	/** @} */
2224
2225	/** @name MULX 32-bit and 64-bit.
2226	* @{ */
2227	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU32, (uint32_t puDst1, uint32_t puDst2, uint32_t uSrc1, uint32_t uSrc2));
2228	typedef FNIEMAIMPLMULXVEXU32 *PFNIEMAIMPLMULXVEXU32;
2229	FNIEMAIMPLMULXVEXU32 iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback;
2230
2231	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU64, (uint64_t puDst1, uint64_t puDst2, uint64_t uSrc1, uint64_t uSrc2));
2232	typedef FNIEMAIMPLMULXVEXU64 *PFNIEMAIMPLMULXVEXU64;
2233	FNIEMAIMPLMULXVEXU64 iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback;
2234	/** @} */
2235
2236
2237	/** @name Exchange memory with register operations.
2238	* @{ */
2239	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_locked, (uint8_t pu8Mem, uint8_t pu8Reg));
2240	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_locked,(uint16_t pu16Mem, uint16_t pu16Reg));
2241	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_locked,(uint32_t pu32Mem, uint32_t pu32Reg));
2242	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_locked,(uint64_t pu64Mem, uint64_t pu64Reg));
2243	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_unlocked, (uint8_t pu8Mem, uint8_t pu8Reg));
2244	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_unlocked,(uint16_t pu16Mem, uint16_t pu16Reg));
2245	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_unlocked,(uint32_t pu32Mem, uint32_t pu32Reg));
2246	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_unlocked,(uint64_t pu64Mem, uint64_t pu64Reg));
2247	/** @} */
2248
2249	/** @name Exchange and add operations.
2250	* @{ */
2251	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
2252	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
2253	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
2254	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
2255	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
2256	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
2257	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
2258	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
2259	/** @} */
2260
2261	/** @name Compare and exchange.
2262	* @{ */
2263	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
2264	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
2265	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
2266	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
2267	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
2268	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
2269	#if ARCH_BITS == 32
2270	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
2271	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
2272	#else
2273	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
2274	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
2275	#endif
2276	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
2277	uint32_t *pEFlags));
2278	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
2279	uint32_t *pEFlags));
2280	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
2281	uint32_t *pEFlags));
2282	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
2283	uint32_t *pEFlags));
2284	#ifndef RT_ARCH_ARM64
2285	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
2286	PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
2287	#endif
2288	/** @} */
2289
2290	/** @name Memory ordering
2291	* @{ */
2292	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
2293	typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
2294	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
2295	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
2296	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
2297	#ifndef RT_ARCH_ARM64
2298	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
2299	#endif
2300	/** @} */
2301
2302	/** @name Double precision shifts
2303	* @{ */
2304	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t pEFlags));
2305	typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
2306	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t pEFlags));
2307	typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
2308	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t pEFlags));
2309	typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
2310	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16, iemAImpl_shld_u16_amd, iemAImpl_shld_u16_intel;
2311	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32, iemAImpl_shld_u32_amd, iemAImpl_shld_u32_intel;
2312	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64, iemAImpl_shld_u64_amd, iemAImpl_shld_u64_intel;
2313	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16, iemAImpl_shrd_u16_amd, iemAImpl_shrd_u16_intel;
2314	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32, iemAImpl_shrd_u32_amd, iemAImpl_shrd_u32_intel;
2315	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64, iemAImpl_shrd_u64_amd, iemAImpl_shrd_u64_intel;
2316	/** @} */
2317
2318
2319	/** @name Bit search operations (thrown in with the binary ops).
2320	* @{ */
2321	FNIEMAIMPLBINU16 iemAImpl_bsf_u16, iemAImpl_bsf_u16_amd, iemAImpl_bsf_u16_intel;
2322	FNIEMAIMPLBINU32 iemAImpl_bsf_u32, iemAImpl_bsf_u32_amd, iemAImpl_bsf_u32_intel;
2323	FNIEMAIMPLBINU64 iemAImpl_bsf_u64, iemAImpl_bsf_u64_amd, iemAImpl_bsf_u64_intel;
2324	FNIEMAIMPLBINU16 iemAImpl_bsr_u16, iemAImpl_bsr_u16_amd, iemAImpl_bsr_u16_intel;
2325	FNIEMAIMPLBINU32 iemAImpl_bsr_u32, iemAImpl_bsr_u32_amd, iemAImpl_bsr_u32_intel;
2326	FNIEMAIMPLBINU64 iemAImpl_bsr_u64, iemAImpl_bsr_u64_amd, iemAImpl_bsr_u64_intel;
2327	FNIEMAIMPLBINU16 iemAImpl_lzcnt_u16, iemAImpl_lzcnt_u16_amd, iemAImpl_lzcnt_u16_intel;
2328	FNIEMAIMPLBINU32 iemAImpl_lzcnt_u32, iemAImpl_lzcnt_u32_amd, iemAImpl_lzcnt_u32_intel;
2329	FNIEMAIMPLBINU64 iemAImpl_lzcnt_u64, iemAImpl_lzcnt_u64_amd, iemAImpl_lzcnt_u64_intel;
2330	FNIEMAIMPLBINU16 iemAImpl_tzcnt_u16, iemAImpl_tzcnt_u16_amd, iemAImpl_tzcnt_u16_intel;
2331	FNIEMAIMPLBINU32 iemAImpl_tzcnt_u32, iemAImpl_tzcnt_u32_amd, iemAImpl_tzcnt_u32_intel;
2332	FNIEMAIMPLBINU64 iemAImpl_tzcnt_u64, iemAImpl_tzcnt_u64_amd, iemAImpl_tzcnt_u64_intel;
2333	FNIEMAIMPLBINU16 iemAImpl_popcnt_u16, iemAImpl_popcnt_u16_fallback;
2334	FNIEMAIMPLBINU32 iemAImpl_popcnt_u32, iemAImpl_popcnt_u32_fallback;
2335	FNIEMAIMPLBINU64 iemAImpl_popcnt_u64, iemAImpl_popcnt_u64_fallback;
2336	/** @} */
2337
2338	/** @name Signed multiplication operations (thrown in with the binary ops).
2339	* @{ */
2340	FNIEMAIMPLBINU16 iemAImpl_imul_two_u16, iemAImpl_imul_two_u16_amd, iemAImpl_imul_two_u16_intel;
2341	FNIEMAIMPLBINU32 iemAImpl_imul_two_u32, iemAImpl_imul_two_u32_amd, iemAImpl_imul_two_u32_intel;
2342	FNIEMAIMPLBINU64 iemAImpl_imul_two_u64, iemAImpl_imul_two_u64_amd, iemAImpl_imul_two_u64_intel;
2343	/** @} */
2344
2345	/** @name Arithmetic assignment operations on bytes (unary).
2346	* @{ */
2347	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t pu8Dst, uint32_t pEFlags));
2348	typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
2349	FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
2350	FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
2351	FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
2352	FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
2353	/** @} */
2354
2355	/** @name Arithmetic assignment operations on words (unary).
2356	* @{ */
2357	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t pu16Dst, uint32_t pEFlags));
2358	typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
2359	FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
2360	FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
2361	FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
2362	FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
2363	/** @} */
2364
2365	/** @name Arithmetic assignment operations on double words (unary).
2366	* @{ */
2367	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t pu32Dst, uint32_t pEFlags));
2368	typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
2369	FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
2370	FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
2371	FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
2372	FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
2373	/** @} */
2374
2375	/** @name Arithmetic assignment operations on quad words (unary).
2376	* @{ */
2377	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t pu64Dst, uint32_t pEFlags));
2378	typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
2379	FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
2380	FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
2381	FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
2382	FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
2383	/** @} */
2384
2385
2386	/** @name Shift operations on bytes (Group 2).
2387	* @{ */
2388	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU8,(uint8_t pu8Dst, uint8_t cShift, uint32_t pEFlags));
2389	typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
2390	FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8, iemAImpl_rol_u8_amd, iemAImpl_rol_u8_intel;
2391	FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8, iemAImpl_ror_u8_amd, iemAImpl_ror_u8_intel;
2392	FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8, iemAImpl_rcl_u8_amd, iemAImpl_rcl_u8_intel;
2393	FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8, iemAImpl_rcr_u8_amd, iemAImpl_rcr_u8_intel;
2394	FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8, iemAImpl_shl_u8_amd, iemAImpl_shl_u8_intel;
2395	FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8, iemAImpl_shr_u8_amd, iemAImpl_shr_u8_intel;
2396	FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8, iemAImpl_sar_u8_amd, iemAImpl_sar_u8_intel;
2397	/** @} */
2398
2399	/** @name Shift operations on words (Group 2).
2400	* @{ */
2401	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU16,(uint16_t pu16Dst, uint8_t cShift, uint32_t pEFlags));
2402	typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
2403	FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16, iemAImpl_rol_u16_amd, iemAImpl_rol_u16_intel;
2404	FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16, iemAImpl_ror_u16_amd, iemAImpl_ror_u16_intel;
2405	FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16, iemAImpl_rcl_u16_amd, iemAImpl_rcl_u16_intel;
2406	FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16, iemAImpl_rcr_u16_amd, iemAImpl_rcr_u16_intel;
2407	FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16, iemAImpl_shl_u16_amd, iemAImpl_shl_u16_intel;
2408	FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16, iemAImpl_shr_u16_amd, iemAImpl_shr_u16_intel;
2409	FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16, iemAImpl_sar_u16_amd, iemAImpl_sar_u16_intel;
2410	/** @} */
2411
2412	/** @name Shift operations on double words (Group 2).
2413	* @{ */
2414	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU32,(uint32_t pu32Dst, uint8_t cShift, uint32_t pEFlags));
2415	typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
2416	FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32, iemAImpl_rol_u32_amd, iemAImpl_rol_u32_intel;
2417	FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32, iemAImpl_ror_u32_amd, iemAImpl_ror_u32_intel;
2418	FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32, iemAImpl_rcl_u32_amd, iemAImpl_rcl_u32_intel;
2419	FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32, iemAImpl_rcr_u32_amd, iemAImpl_rcr_u32_intel;
2420	FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32, iemAImpl_shl_u32_amd, iemAImpl_shl_u32_intel;
2421	FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32, iemAImpl_shr_u32_amd, iemAImpl_shr_u32_intel;
2422	FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32, iemAImpl_sar_u32_amd, iemAImpl_sar_u32_intel;
2423	/** @} */
2424
2425	/** @name Shift operations on words (Group 2).
2426	* @{ */
2427	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU64,(uint64_t pu64Dst, uint8_t cShift, uint32_t pEFlags));
2428	typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
2429	FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64, iemAImpl_rol_u64_amd, iemAImpl_rol_u64_intel;
2430	FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64, iemAImpl_ror_u64_amd, iemAImpl_ror_u64_intel;
2431	FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64, iemAImpl_rcl_u64_amd, iemAImpl_rcl_u64_intel;
2432	FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64, iemAImpl_rcr_u64_amd, iemAImpl_rcr_u64_intel;
2433	FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64, iemAImpl_shl_u64_amd, iemAImpl_shl_u64_intel;
2434	FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64, iemAImpl_shr_u64_amd, iemAImpl_shr_u64_intel;
2435	FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64, iemAImpl_sar_u64_amd, iemAImpl_sar_u64_intel;
2436	/** @} */
2437
2438	/** @name Multiplication and division operations.
2439	* @{ */
2440	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t pu16AX, uint8_t u8FactorDivisor, uint32_t pEFlags));
2441	typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
2442	FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_mul_u8_amd, iemAImpl_mul_u8_intel;
2443	FNIEMAIMPLMULDIVU8 iemAImpl_imul_u8, iemAImpl_imul_u8_amd, iemAImpl_imul_u8_intel;
2444	FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_div_u8_amd, iemAImpl_div_u8_intel;
2445	FNIEMAIMPLMULDIVU8 iemAImpl_idiv_u8, iemAImpl_idiv_u8_amd, iemAImpl_idiv_u8_intel;
2446
2447	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t pu16AX, uint16_t pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
2448	typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
2449	FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_mul_u16_amd, iemAImpl_mul_u16_intel;
2450	FNIEMAIMPLMULDIVU16 iemAImpl_imul_u16, iemAImpl_imul_u16_amd, iemAImpl_imul_u16_intel;
2451	FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_div_u16_amd, iemAImpl_div_u16_intel;
2452	FNIEMAIMPLMULDIVU16 iemAImpl_idiv_u16, iemAImpl_idiv_u16_amd, iemAImpl_idiv_u16_intel;
2453
2454	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t pu32EAX, uint32_t pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
2455	typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
2456	FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_mul_u32_amd, iemAImpl_mul_u32_intel;
2457	FNIEMAIMPLMULDIVU32 iemAImpl_imul_u32, iemAImpl_imul_u32_amd, iemAImpl_imul_u32_intel;
2458	FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_div_u32_amd, iemAImpl_div_u32_intel;
2459	FNIEMAIMPLMULDIVU32 iemAImpl_idiv_u32, iemAImpl_idiv_u32_amd, iemAImpl_idiv_u32_intel;
2460
2461	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t pu64RAX, uint64_t pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
2462	typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
2463	FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_mul_u64_amd, iemAImpl_mul_u64_intel;
2464	FNIEMAIMPLMULDIVU64 iemAImpl_imul_u64, iemAImpl_imul_u64_amd, iemAImpl_imul_u64_intel;
2465	FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_div_u64_amd, iemAImpl_div_u64_intel;
2466	FNIEMAIMPLMULDIVU64 iemAImpl_idiv_u64, iemAImpl_idiv_u64_amd, iemAImpl_idiv_u64_intel;
2467	/** @} */
2468
2469	/** @name Byte Swap.
2470	* @{ */
2471	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t pu32Dst)); / Yes, 32-bit register access. */
2472	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
2473	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
2474	/** @} */
2475
2476	/** @name Misc.
2477	* @{ */
2478	FNIEMAIMPLBINU16 iemAImpl_arpl;
2479	/** @} */
2480
2481	/** @name RDRAND and RDSEED
2482	* @{ */
2483	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU16,(uint16_t puDst, uint32_t pEFlags));
2484	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU32,(uint32_t puDst, uint32_t pEFlags));
2485	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU64,(uint64_t puDst, uint32_t pEFlags));
2486	typedef FNIEMAIMPLRDRANDSEEDU16 *PFNIEMAIMPLRDRANDSEEDU16;
2487	typedef FNIEMAIMPLRDRANDSEEDU32 *PFNIEMAIMPLRDRANDSEEDU32;
2488	typedef FNIEMAIMPLRDRANDSEEDU64 *PFNIEMAIMPLRDRANDSEEDU64;
2489
2490	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdrand_u16, iemAImpl_rdrand_u16_fallback;
2491	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdrand_u32, iemAImpl_rdrand_u32_fallback;
2492	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdrand_u64, iemAImpl_rdrand_u64_fallback;
2493	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdseed_u16, iemAImpl_rdseed_u16_fallback;
2494	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdseed_u32, iemAImpl_rdseed_u32_fallback;
2495	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdseed_u64, iemAImpl_rdseed_u64_fallback;
2496	/** @} */
2497
2498	/** @name ADOX and ADCX
2499	* @{ */
2500	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLADXU32,(uint32_t puDst, uint32_t pfEFlags, uint32_t uSrc));
2501	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLADXU64,(uint64_t puDst, uint32_t pfEFlags, uint64_t uSrc));
2502	typedef FNIEMAIMPLADXU32 *PFNIEMAIMPLADXU32;
2503	typedef FNIEMAIMPLADXU64 *PFNIEMAIMPLADXU64;
2504
2505	FNIEMAIMPLADXU32 iemAImpl_adcx_u32, iemAImpl_adcx_u32_fallback;
2506	FNIEMAIMPLADXU64 iemAImpl_adcx_u64, iemAImpl_adcx_u64_fallback;
2507	FNIEMAIMPLADXU32 iemAImpl_adox_u32, iemAImpl_adox_u32_fallback;
2508	FNIEMAIMPLADXU64 iemAImpl_adox_u64, iemAImpl_adox_u64_fallback;
2509	/** @} */
2510
2511	/** @name FPU operations taking a 32-bit float argument
2512	* @{ */
2513	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2514	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
2515	typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
2516
2517	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2518	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
2519	typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
2520
2521	FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
2522	FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
2523	FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
2524	FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
2525	FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
2526	FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
2527	FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
2528
2529	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
2530	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2531	PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
2532	/** @} */
2533
2534	/** @name FPU operations taking a 64-bit float argument
2535	* @{ */
2536	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2537	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
2538	typedef FNIEMAIMPLFPUR64FSW *PFNIEMAIMPLFPUR64FSW;
2539
2540	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2541	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
2542	typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
2543
2544	FNIEMAIMPLFPUR64FSW iemAImpl_fcom_r80_by_r64;
2545	FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
2546	FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
2547	FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
2548	FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
2549	FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
2550	FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
2551
2552	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
2553	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2554	PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
2555	/** @} */
2556
2557	/** @name FPU operations taking a 80-bit float argument
2558	* @{ */
2559	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2560	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
2561	typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
2562	FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
2563	FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
2564	FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
2565	FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
2566	FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
2567	FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
2568	FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
2569	FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
2570	FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
2571
2572	FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80, iemAImpl_fpatan_r80_by_r80_amd, iemAImpl_fpatan_r80_by_r80_intel;
2573	FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80, iemAImpl_fyl2x_r80_by_r80_amd, iemAImpl_fyl2x_r80_by_r80_intel;
2574	FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80, iemAImpl_fyl2xp1_r80_by_r80_amd, iemAImpl_fyl2xp1_r80_by_r80_intel;
2575
2576	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2577	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
2578	typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
2579	FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
2580	FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
2581
2582	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
2583	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
2584	typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
2585	FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
2586	FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
2587
2588	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
2589	typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
2590	FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
2591	FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
2592	FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80, iemAImpl_f2xm1_r80_amd, iemAImpl_f2xm1_r80_intel;
2593	FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
2594	FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
2595	FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80, iemAImpl_fsin_r80_amd, iemAImpl_fsin_r80_intel;
2596	FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80, iemAImpl_fcos_r80_amd, iemAImpl_fcos_r80_intel;
2597
2598	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
2599	typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
2600	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
2601	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
2602
2603	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
2604	typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
2605	FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
2606	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
2607	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
2608	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
2609	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
2610	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
2611	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
2612
2613	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
2614	PCRTFLOAT80U pr80Val));
2615	typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
2616	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80, iemAImpl_fptan_r80_r80_amd, iemAImpl_fptan_r80_r80_intel;
2617	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
2618	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80, iemAImpl_fsincos_r80_r80_amd, iemAImpl_fsincos_r80_r80_intel;
2619
2620	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
2621	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2622	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
2623
2624	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_d80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTPBCD80U pd80Val));
2625	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_d80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2626	PRTPBCD80U pd80Dst, PCRTFLOAT80U pr80Src));
2627
2628	/** @} */
2629
2630	/** @name FPU operations taking a 16-bit signed integer argument
2631	* @{ */
2632	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2633	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
2634	typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
2635	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI16,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
2636	int16_t *pi16Dst, PCRTFLOAT80U pr80Src));
2637	typedef FNIEMAIMPLFPUSTR80TOI16 *PFNIEMAIMPLFPUSTR80TOI16;
2638
2639	FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
2640	FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
2641	FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
2642	FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
2643	FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
2644	FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
2645
2646	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2647	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
2648	typedef FNIEMAIMPLFPUI16FSW *PFNIEMAIMPLFPUI16FSW;
2649	FNIEMAIMPLFPUI16FSW iemAImpl_ficom_r80_by_i16;
2650
2651	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
2652	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fist_r80_to_i16;
2653	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fistt_r80_to_i16, iemAImpl_fistt_r80_to_i16_amd, iemAImpl_fistt_r80_to_i16_intel;
2654	/** @} */
2655
2656	/** @name FPU operations taking a 32-bit signed integer argument
2657	* @{ */
2658	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2659	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
2660	typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
2661	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI32,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
2662	int32_t *pi32Dst, PCRTFLOAT80U pr80Src));
2663	typedef FNIEMAIMPLFPUSTR80TOI32 *PFNIEMAIMPLFPUSTR80TOI32;
2664
2665	FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
2666	FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
2667	FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
2668	FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
2669	FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
2670	FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
2671
2672	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2673	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
2674	typedef FNIEMAIMPLFPUI32FSW *PFNIEMAIMPLFPUI32FSW;
2675	FNIEMAIMPLFPUI32FSW iemAImpl_ficom_r80_by_i32;
2676
2677	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
2678	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fist_r80_to_i32;
2679	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fistt_r80_to_i32;
2680	/** @} */
2681
2682	/** @name FPU operations taking a 64-bit signed integer argument
2683	* @{ */
2684	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI64,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
2685	int64_t *pi64Dst, PCRTFLOAT80U pr80Src));
2686	typedef FNIEMAIMPLFPUSTR80TOI64 *PFNIEMAIMPLFPUSTR80TOI64;
2687
2688	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
2689	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fist_r80_to_i64;
2690	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fistt_r80_to_i64;
2691	/** @} */
2692
2693
2694	/** Temporary type representing a 256-bit vector register. */
2695	typedef struct { uint64_t au64[4]; } IEMVMM256;
2696	/** Temporary type pointing to a 256-bit vector register. */
2697	typedef IEMVMM256 *PIEMVMM256;
2698	/** Temporary type pointing to a const 256-bit vector register. */
2699	typedef IEMVMM256 *PCIEMVMM256;
2700
2701
2702	/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
2703	* @{ */
2704	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t puDst, uint64_t const puSrc));
2705	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
2706	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U128,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
2707	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
2708	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U128,(PX86XSAVEAREA pExtState, PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
2709	typedef FNIEMAIMPLMEDIAF3U128 *PFNIEMAIMPLMEDIAF3U128;
2710	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U256,(PX86XSAVEAREA pExtState, PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
2711	typedef FNIEMAIMPLMEDIAF3U256 *PFNIEMAIMPLMEDIAF3U256;
2712	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U64,(uint64_t puDst, uint64_t const puSrc));
2713	typedef FNIEMAIMPLMEDIAOPTF2U64 *PFNIEMAIMPLMEDIAOPTF2U64;
2714	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128,(PRTUINT128U puDst, PCRTUINT128U puSrc));
2715	typedef FNIEMAIMPLMEDIAOPTF2U128 *PFNIEMAIMPLMEDIAOPTF2U128;
2716	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
2717	typedef FNIEMAIMPLMEDIAOPTF3U128 *PFNIEMAIMPLMEDIAOPTF3U128;
2718	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
2719	typedef FNIEMAIMPLMEDIAOPTF3U256 *PFNIEMAIMPLMEDIAOPTF3U256;
2720	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256,(PRTUINT256U puDst, PCRTUINT256U puSrc));
2721	typedef FNIEMAIMPLMEDIAOPTF2U256 *PFNIEMAIMPLMEDIAOPTF2U256;
2722	FNIEMAIMPLMEDIAF2U64 iemAImpl_pshufb_u64, iemAImpl_pshufb_u64_fallback;
2723	FNIEMAIMPLMEDIAF2U64 iemAImpl_pand_u64, iemAImpl_pandn_u64, iemAImpl_por_u64, iemAImpl_pxor_u64;
2724	FNIEMAIMPLMEDIAF2U64 iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
2725	FNIEMAIMPLMEDIAF2U64 iemAImpl_pcmpgtb_u64, iemAImpl_pcmpgtw_u64, iemAImpl_pcmpgtd_u64;
2726	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddb_u64, iemAImpl_paddsb_u64, iemAImpl_paddusb_u64;
2727	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddw_u64, iemAImpl_paddsw_u64, iemAImpl_paddusw_u64;
2728	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddd_u64;
2729	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddq_u64;
2730	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubb_u64, iemAImpl_psubsb_u64, iemAImpl_psubusb_u64;
2731	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubw_u64, iemAImpl_psubsw_u64, iemAImpl_psubusw_u64;
2732	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubd_u64;
2733	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubq_u64;
2734	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmaddwd_u64;
2735	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmullw_u64, iemAImpl_pmulhw_u64;
2736	FNIEMAIMPLMEDIAF2U64 iemAImpl_pminub_u64, iemAImpl_pmaxub_u64;
2737	FNIEMAIMPLMEDIAF2U64 iemAImpl_pminsw_u64, iemAImpl_pmaxsw_u64;
2738	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsb_u64, iemAImpl_pabsb_u64_fallback;
2739	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsw_u64, iemAImpl_pabsw_u64_fallback;
2740	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsd_u64, iemAImpl_pabsd_u64_fallback;
2741	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignb_u64, iemAImpl_psignb_u64_fallback;
2742	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignw_u64, iemAImpl_psignw_u64_fallback;
2743	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignd_u64, iemAImpl_psignd_u64_fallback;
2744	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddw_u64, iemAImpl_phaddw_u64_fallback;
2745	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddd_u64, iemAImpl_phaddd_u64_fallback;
2746	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubw_u64, iemAImpl_phsubw_u64_fallback;
2747	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubd_u64, iemAImpl_phsubd_u64_fallback;
2748	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddsw_u64, iemAImpl_phaddsw_u64_fallback;
2749	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubsw_u64, iemAImpl_phsubsw_u64_fallback;
2750	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmaddubsw_u64, iemAImpl_pmaddubsw_u64_fallback;
2751	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmulhrsw_u64, iemAImpl_pmulhrsw_u64_fallback;
2752	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmuludq_u64;
2753	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllw_u64, iemAImpl_psrlw_u64, iemAImpl_psraw_u64;
2754	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pslld_u64, iemAImpl_psrld_u64, iemAImpl_psrad_u64;
2755	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllq_u64, iemAImpl_psrlq_u64;
2756	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packsswb_u64, iemAImpl_packuswb_u64;
2757	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packssdw_u64;
2758	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhuw_u64;
2759	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pavgb_u64, iemAImpl_pavgw_u64;
2760	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psadbw_u64;
2761
2762	FNIEMAIMPLMEDIAF2U128 iemAImpl_pshufb_u128, iemAImpl_pshufb_u128_fallback;
2763	FNIEMAIMPLMEDIAF2U128 iemAImpl_pand_u128, iemAImpl_pandn_u128, iemAImpl_por_u128, iemAImpl_pxor_u128;
2764	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
2765	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpeqq_u128, iemAImpl_pcmpeqq_u128_fallback;
2766	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpgtb_u128, iemAImpl_pcmpgtw_u128, iemAImpl_pcmpgtd_u128;
2767	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpgtq_u128, iemAImpl_pcmpgtq_u128_fallback;
2768	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddb_u128, iemAImpl_paddsb_u128, iemAImpl_paddusb_u128;
2769	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddw_u128, iemAImpl_paddsw_u128, iemAImpl_paddusw_u128;
2770	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddd_u128;
2771	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddq_u128;
2772	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubb_u128, iemAImpl_psubsb_u128, iemAImpl_psubusb_u128;
2773	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubw_u128, iemAImpl_psubsw_u128, iemAImpl_psubusw_u128;
2774	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubd_u128;
2775	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubq_u128;
2776	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmullw_u128, iemAImpl_pmullw_u128_fallback;
2777	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulhw_u128;
2778	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulld_u128, iemAImpl_pmulld_u128_fallback;
2779	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaddwd_u128;
2780	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminub_u128;
2781	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminud_u128, iemAImpl_pminud_u128_fallback;
2782	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminuw_u128, iemAImpl_pminuw_u128_fallback;
2783	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsb_u128, iemAImpl_pminsb_u128_fallback;
2784	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsd_u128, iemAImpl_pminsd_u128_fallback;
2785	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsw_u128, iemAImpl_pminsw_u128_fallback;
2786	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxub_u128;
2787	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxud_u128, iemAImpl_pmaxud_u128_fallback;
2788	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxuw_u128, iemAImpl_pmaxuw_u128_fallback;
2789	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsb_u128, iemAImpl_pmaxsb_u128_fallback;
2790	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsw_u128;
2791	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsd_u128, iemAImpl_pmaxsd_u128_fallback;
2792	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsb_u128, iemAImpl_pabsb_u128_fallback;
2793	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsw_u128, iemAImpl_pabsw_u128_fallback;
2794	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsd_u128, iemAImpl_pabsd_u128_fallback;
2795	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignb_u128, iemAImpl_psignb_u128_fallback;
2796	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignw_u128, iemAImpl_psignw_u128_fallback;
2797	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignd_u128, iemAImpl_psignd_u128_fallback;
2798	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddw_u128, iemAImpl_phaddw_u128_fallback;
2799	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddd_u128, iemAImpl_phaddd_u128_fallback;
2800	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubw_u128, iemAImpl_phsubw_u128_fallback;
2801	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubd_u128, iemAImpl_phsubd_u128_fallback;
2802	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddsw_u128, iemAImpl_phaddsw_u128_fallback;
2803	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubsw_u128, iemAImpl_phsubsw_u128_fallback;
2804	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaddubsw_u128, iemAImpl_pmaddubsw_u128_fallback;
2805	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulhrsw_u128, iemAImpl_pmulhrsw_u128_fallback;
2806	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmuludq_u128;
2807	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packsswb_u128, iemAImpl_packuswb_u128;
2808	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packssdw_u128, iemAImpl_packusdw_u128;
2809	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllw_u128, iemAImpl_psrlw_u128, iemAImpl_psraw_u128;
2810	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pslld_u128, iemAImpl_psrld_u128, iemAImpl_psrad_u128;
2811	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllq_u128, iemAImpl_psrlq_u128;
2812	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhuw_u128;
2813	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pavgb_u128, iemAImpl_pavgw_u128;
2814	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psadbw_u128;
2815	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuldq_u128, iemAImpl_pmuldq_u128_fallback;
2816	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpcklps_u128, iemAImpl_unpcklpd_u128;
2817	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpckhps_u128, iemAImpl_unpckhpd_u128;
2818	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phminposuw_u128, iemAImpl_phminposuw_u128_fallback;
2819
2820	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpshufb_u128, iemAImpl_vpshufb_u128_fallback;
2821	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpand_u128, iemAImpl_vpand_u128_fallback;
2822	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpandn_u128, iemAImpl_vpandn_u128_fallback;
2823	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpor_u128, iemAImpl_vpor_u128_fallback;
2824	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpxor_u128, iemAImpl_vpxor_u128_fallback;
2825	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqb_u128, iemAImpl_vpcmpeqb_u128_fallback;
2826	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqw_u128, iemAImpl_vpcmpeqw_u128_fallback;
2827	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqd_u128, iemAImpl_vpcmpeqd_u128_fallback;
2828	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqq_u128, iemAImpl_vpcmpeqq_u128_fallback;
2829	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtb_u128, iemAImpl_vpcmpgtb_u128_fallback;
2830	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtw_u128, iemAImpl_vpcmpgtw_u128_fallback;
2831	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtd_u128, iemAImpl_vpcmpgtd_u128_fallback;
2832	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtq_u128, iemAImpl_vpcmpgtq_u128_fallback;
2833	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddb_u128, iemAImpl_vpaddb_u128_fallback;
2834	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddw_u128, iemAImpl_vpaddw_u128_fallback;
2835	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddd_u128, iemAImpl_vpaddd_u128_fallback;
2836	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddq_u128, iemAImpl_vpaddq_u128_fallback;
2837	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubb_u128, iemAImpl_vpsubb_u128_fallback;
2838	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubw_u128, iemAImpl_vpsubw_u128_fallback;
2839	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubd_u128, iemAImpl_vpsubd_u128_fallback;
2840	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubq_u128, iemAImpl_vpsubq_u128_fallback;
2841	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminub_u128, iemAImpl_vpminub_u128_fallback;
2842	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminuw_u128, iemAImpl_vpminuw_u128_fallback;
2843	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminud_u128, iemAImpl_vpminud_u128_fallback;
2844	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsb_u128, iemAImpl_vpminsb_u128_fallback;
2845	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsw_u128, iemAImpl_vpminsw_u128_fallback;
2846	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsd_u128, iemAImpl_vpminsd_u128_fallback;
2847	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxub_u128, iemAImpl_vpmaxub_u128_fallback;
2848	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxuw_u128, iemAImpl_vpmaxuw_u128_fallback;
2849	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxud_u128, iemAImpl_vpmaxud_u128_fallback;
2850	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsb_u128, iemAImpl_vpmaxsb_u128_fallback;
2851	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsw_u128, iemAImpl_vpmaxsw_u128_fallback;
2852	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsd_u128, iemAImpl_vpmaxsd_u128_fallback;
2853	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpacksswb_u128, iemAImpl_vpacksswb_u128_fallback;
2854	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackssdw_u128, iemAImpl_vpackssdw_u128_fallback;
2855	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackuswb_u128, iemAImpl_vpackuswb_u128_fallback;
2856	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackusdw_u128, iemAImpl_vpackusdw_u128_fallback;
2857	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmullw_u128, iemAImpl_vpmullw_u128_fallback;
2858	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulld_u128, iemAImpl_vpmulld_u128_fallback;
2859	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhw_u128, iemAImpl_vpmulhw_u128_fallback;
2860	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhuw_u128, iemAImpl_vpmulhuw_u128_fallback;
2861	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgb_u128, iemAImpl_vpavgb_u128_fallback;
2862	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgw_u128, iemAImpl_vpavgw_u128_fallback;
2863	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignb_u128, iemAImpl_vpsignb_u128_fallback;
2864	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignw_u128, iemAImpl_vpsignw_u128_fallback;
2865	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignd_u128, iemAImpl_vpsignd_u128_fallback;
2866	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddw_u128, iemAImpl_vphaddw_u128_fallback;
2867	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddd_u128, iemAImpl_vphaddd_u128_fallback;
2868	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubw_u128, iemAImpl_vphsubw_u128_fallback;
2869	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubd_u128, iemAImpl_vphsubd_u128_fallback;
2870	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddsw_u128, iemAImpl_vphaddsw_u128_fallback;
2871	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubsw_u128, iemAImpl_vphsubsw_u128_fallback;
2872	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddubsw_u128, iemAImpl_vpmaddubsw_u128_fallback;
2873	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhrsw_u128, iemAImpl_vpmulhrsw_u128_fallback;
2874	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsadbw_u128, iemAImpl_vpsadbw_u128_fallback;
2875	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuldq_u128, iemAImpl_vpmuldq_u128_fallback;
2876	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuludq_u128, iemAImpl_vpmuludq_u128_fallback;
2877	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsb_u128, iemAImpl_vpsubsb_u128_fallback;
2878	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsw_u128, iemAImpl_vpsubsw_u128_fallback;
2879	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusb_u128, iemAImpl_vpsubusb_u128_fallback;
2880	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusw_u128, iemAImpl_vpsubusw_u128_fallback;
2881	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusb_u128, iemAImpl_vpaddusb_u128_fallback;
2882	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusw_u128, iemAImpl_vpaddusw_u128_fallback;
2883	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsb_u128, iemAImpl_vpaddsb_u128_fallback;
2884	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsw_u128, iemAImpl_vpaddsw_u128_fallback;
2885
2886	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsb_u128, iemAImpl_vpabsb_u128_fallback;
2887	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsw_u128, iemAImpl_vpabsd_u128_fallback;
2888	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsd_u128, iemAImpl_vpabsw_u128_fallback;
2889	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vphminposuw_u128, iemAImpl_vphminposuw_u128_fallback;
2890
2891	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpshufb_u256, iemAImpl_vpshufb_u256_fallback;
2892	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpand_u256, iemAImpl_vpand_u256_fallback;
2893	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpandn_u256, iemAImpl_vpandn_u256_fallback;
2894	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpor_u256, iemAImpl_vpor_u256_fallback;
2895	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpxor_u256, iemAImpl_vpxor_u256_fallback;
2896	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqb_u256, iemAImpl_vpcmpeqb_u256_fallback;
2897	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqw_u256, iemAImpl_vpcmpeqw_u256_fallback;
2898	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqd_u256, iemAImpl_vpcmpeqd_u256_fallback;
2899	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqq_u256, iemAImpl_vpcmpeqq_u256_fallback;
2900	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtb_u256, iemAImpl_vpcmpgtb_u256_fallback;
2901	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtw_u256, iemAImpl_vpcmpgtw_u256_fallback;
2902	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtd_u256, iemAImpl_vpcmpgtd_u256_fallback;
2903	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtq_u256, iemAImpl_vpcmpgtq_u256_fallback;
2904	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddb_u256, iemAImpl_vpaddb_u256_fallback;
2905	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddw_u256, iemAImpl_vpaddw_u256_fallback;
2906	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddd_u256, iemAImpl_vpaddd_u256_fallback;
2907	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddq_u256, iemAImpl_vpaddq_u256_fallback;
2908	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubb_u256, iemAImpl_vpsubb_u256_fallback;
2909	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubw_u256, iemAImpl_vpsubw_u256_fallback;
2910	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubd_u256, iemAImpl_vpsubd_u256_fallback;
2911	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubq_u256, iemAImpl_vpsubq_u256_fallback;
2912	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminub_u256, iemAImpl_vpminub_u256_fallback;
2913	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminuw_u256, iemAImpl_vpminuw_u256_fallback;
2914	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminud_u256, iemAImpl_vpminud_u256_fallback;
2915	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsb_u256, iemAImpl_vpminsb_u256_fallback;
2916	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsw_u256, iemAImpl_vpminsw_u256_fallback;
2917	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsd_u256, iemAImpl_vpminsd_u256_fallback;
2918	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxub_u256, iemAImpl_vpmaxub_u256_fallback;
2919	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxuw_u256, iemAImpl_vpmaxuw_u256_fallback;
2920	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxud_u256, iemAImpl_vpmaxud_u256_fallback;
2921	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsb_u256, iemAImpl_vpmaxsb_u256_fallback;
2922	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsw_u256, iemAImpl_vpmaxsw_u256_fallback;
2923	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsd_u256, iemAImpl_vpmaxsd_u256_fallback;
2924	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpacksswb_u256, iemAImpl_vpacksswb_u256_fallback;
2925	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackssdw_u256, iemAImpl_vpackssdw_u256_fallback;
2926	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackuswb_u256, iemAImpl_vpackuswb_u256_fallback;
2927	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackusdw_u256, iemAImpl_vpackusdw_u256_fallback;
2928	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmullw_u256, iemAImpl_vpmullw_u256_fallback;
2929	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulld_u256, iemAImpl_vpmulld_u256_fallback;
2930	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhw_u256, iemAImpl_vpmulhw_u256_fallback;
2931	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhuw_u256, iemAImpl_vpmulhuw_u256_fallback;
2932	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgb_u256, iemAImpl_vpavgb_u256_fallback;
2933	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgw_u256, iemAImpl_vpavgw_u256_fallback;
2934	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignb_u256, iemAImpl_vpsignb_u256_fallback;
2935	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignw_u256, iemAImpl_vpsignw_u256_fallback;
2936	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignd_u256, iemAImpl_vpsignd_u256_fallback;
2937	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddw_u256, iemAImpl_vphaddw_u256_fallback;
2938	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddd_u256, iemAImpl_vphaddd_u256_fallback;
2939	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubw_u256, iemAImpl_vphsubw_u256_fallback;
2940	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubd_u256, iemAImpl_vphsubd_u256_fallback;
2941	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddsw_u256, iemAImpl_vphaddsw_u256_fallback;
2942	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubsw_u256, iemAImpl_vphsubsw_u256_fallback;
2943	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddubsw_u256, iemAImpl_vpmaddubsw_u256_fallback;
2944	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhrsw_u256, iemAImpl_vpmulhrsw_u256_fallback;
2945	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsadbw_u256, iemAImpl_vpsadbw_u256_fallback;
2946	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuldq_u256, iemAImpl_vpmuldq_u256_fallback;
2947	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuludq_u256, iemAImpl_vpmuludq_u256_fallback;
2948	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsb_u256, iemAImpl_vpsubsb_u256_fallback;
2949	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsw_u256, iemAImpl_vpsubsw_u256_fallback;
2950	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusb_u256, iemAImpl_vpsubusb_u256_fallback;
2951	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusw_u256, iemAImpl_vpsubusw_u256_fallback;
2952	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusb_u256, iemAImpl_vpaddusb_u256_fallback;
2953	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusw_u256, iemAImpl_vpaddusw_u256_fallback;
2954	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsb_u256, iemAImpl_vpaddsb_u256_fallback;
2955	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsw_u256, iemAImpl_vpaddsw_u256_fallback;
2956
2957	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsb_u256, iemAImpl_vpabsb_u256_fallback;
2958	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsw_u256, iemAImpl_vpabsw_u256_fallback;
2959	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsd_u256, iemAImpl_vpabsd_u256_fallback;
2960	/** @} */
2961
2962	/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
2963	* @{ */
2964	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
2965	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
2966	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpcklbw_u128, iemAImpl_vpunpcklbw_u128_fallback,
2967	iemAImpl_vpunpcklwd_u128, iemAImpl_vpunpcklwd_u128_fallback,
2968	iemAImpl_vpunpckldq_u128, iemAImpl_vpunpckldq_u128_fallback,
2969	iemAImpl_vpunpcklqdq_u128, iemAImpl_vpunpcklqdq_u128_fallback,
2970	iemAImpl_vunpcklps_u128, iemAImpl_vunpcklps_u128_fallback,
2971	iemAImpl_vunpcklpd_u128, iemAImpl_vunpcklpd_u128_fallback,
2972	iemAImpl_vunpckhps_u128, iemAImpl_vunpckhps_u128_fallback,
2973	iemAImpl_vunpckhpd_u128, iemAImpl_vunpckhpd_u128_fallback;
2974
2975	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpcklbw_u256, iemAImpl_vpunpcklbw_u256_fallback,
2976	iemAImpl_vpunpcklwd_u256, iemAImpl_vpunpcklwd_u256_fallback,
2977	iemAImpl_vpunpckldq_u256, iemAImpl_vpunpckldq_u256_fallback,
2978	iemAImpl_vpunpcklqdq_u256, iemAImpl_vpunpcklqdq_u256_fallback,
2979	iemAImpl_vunpcklps_u256, iemAImpl_vunpcklps_u256_fallback,
2980	iemAImpl_vunpcklpd_u256, iemAImpl_vunpcklpd_u256_fallback,
2981	iemAImpl_vunpckhps_u256, iemAImpl_vunpckhps_u256_fallback,
2982	iemAImpl_vunpckhpd_u256, iemAImpl_vunpckhpd_u256_fallback;
2983	/** @} */
2984
2985	/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
2986	* @{ */
2987	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
2988	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
2989	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpckhbw_u128, iemAImpl_vpunpckhbw_u128_fallback,
2990	iemAImpl_vpunpckhwd_u128, iemAImpl_vpunpckhwd_u128_fallback,
2991	iemAImpl_vpunpckhdq_u128, iemAImpl_vpunpckhdq_u128_fallback,
2992	iemAImpl_vpunpckhqdq_u128, iemAImpl_vpunpckhqdq_u128_fallback;
2993	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpckhbw_u256, iemAImpl_vpunpckhbw_u256_fallback,
2994	iemAImpl_vpunpckhwd_u256, iemAImpl_vpunpckhwd_u256_fallback,
2995	iemAImpl_vpunpckhdq_u256, iemAImpl_vpunpckhdq_u256_fallback,
2996	iemAImpl_vpunpckhqdq_u256, iemAImpl_vpunpckhqdq_u256_fallback;
2997	/** @} */
2998
2999	/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
3000	* @{ */
3001	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3002	typedef FNIEMAIMPLMEDIAPSHUFU128 *PFNIEMAIMPLMEDIAPSHUFU128;
3003	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
3004	typedef FNIEMAIMPLMEDIAPSHUFU256 *PFNIEMAIMPLMEDIAPSHUFU256;
3005	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw_u64,(uint64_t puDst, uint64_t const puSrc, uint8_t bEvil));
3006	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_pshufhw_u128, iemAImpl_pshuflw_u128, iemAImpl_pshufd_u128;
3007	#ifndef IEM_WITHOUT_ASSEMBLY
3008	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256, iemAImpl_vpshuflw_u256, iemAImpl_vpshufd_u256;
3009	#endif
3010	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256_fallback, iemAImpl_vpshuflw_u256_fallback, iemAImpl_vpshufd_u256_fallback;
3011	/** @} */
3012
3013	/** @name Media (SSE/MMX/AVX) operation: Shift Immediate Stuff (evil)
3014	* @{ */
3015	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU64,(uint64_t *puDst, uint8_t bShift));
3016	typedef FNIEMAIMPLMEDIAPSHIFTU64 *PFNIEMAIMPLMEDIAPSHIFTU64;
3017	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU128,(PRTUINT128U puDst, uint8_t bShift));
3018	typedef FNIEMAIMPLMEDIAPSHIFTU128 *PFNIEMAIMPLMEDIAPSHIFTU128;
3019	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU256,(PRTUINT256U puDst, uint8_t bShift));
3020	typedef FNIEMAIMPLMEDIAPSHIFTU256 *PFNIEMAIMPLMEDIAPSHIFTU256;
3021	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psllw_imm_u64, iemAImpl_pslld_imm_u64, iemAImpl_psllq_imm_u64;
3022	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psrlw_imm_u64, iemAImpl_psrld_imm_u64, iemAImpl_psrlq_imm_u64;
3023	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psraw_imm_u64, iemAImpl_psrad_imm_u64;
3024	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psllw_imm_u128, iemAImpl_pslld_imm_u128, iemAImpl_psllq_imm_u128;
3025	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psrlw_imm_u128, iemAImpl_psrld_imm_u128, iemAImpl_psrlq_imm_u128;
3026	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psraw_imm_u128, iemAImpl_psrad_imm_u128;
3027	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_pslldq_imm_u128, iemAImpl_psrldq_imm_u128;
3028	/** @} */
3029
3030	/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
3031	* @{ */
3032	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(uint64_t pu64Dst, uint64_t const puSrc));
3033	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(uint64_t *pu64Dst, PCRTUINT128U puSrc));
3034	#ifndef IEM_WITHOUT_ASSEMBLY
3035	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
3036	#endif
3037	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256_fallback,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
3038	/** @} */
3039
3040	/** @name Media (SSE/MMX/AVX) operations: Variable Blend Packed Bytes/R32/R64.
3041	* @{ */
3042	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puMask));
3043	typedef FNIEMAIMPLBLENDU128 *PFNIEMAIMPLBLENDU128;
3044	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, PCRTUINT128U puMask));
3045	typedef FNIEMAIMPLAVXBLENDU128 *PFNIEMAIMPLAVXBLENDU128;
3046	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, PCRTUINT256U puMask));
3047	typedef FNIEMAIMPLAVXBLENDU256 *PFNIEMAIMPLAVXBLENDU256;
3048
3049	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128;
3050	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128_fallback;
3051	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128;
3052	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128_fallback;
3053	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256;
3054	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256_fallback;
3055
3056	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128;
3057	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128_fallback;
3058	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128;
3059	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128_fallback;
3060	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256;
3061	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256_fallback;
3062
3063	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128;
3064	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128_fallback;
3065	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128;
3066	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128_fallback;
3067	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256;
3068	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256_fallback;
3069	/** @} */
3070
3071
3072	/** @name Media (SSE/MMX/AVX) operation: Sort this later
3073	* @{ */
3074	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
3075	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
3076	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovshdup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
3077	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovshdup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
3078	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
3079	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
3080
3081	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3082	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3083	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3084	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3085	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3086
3087	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3088	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3089	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3090	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3091	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3092
3093	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3094	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3095	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
3096	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3097	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3098
3099	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3100	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3101	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3102	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3103	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3104
3105	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3106	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3107	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3108	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3109	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3110
3111	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3112	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3113	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3114	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3115	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3116
3117	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3118	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3119	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3120	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3121	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3122
3123	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3124	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3125	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3126	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3127	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3128
3129	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3130	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3131	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
3132	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3133	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3134
3135	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3136	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3137	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3138	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3139	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3140
3141	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3142	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3143	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3144	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3145	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3146
3147	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3148	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3149	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3150	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3151	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3152
3153	IEM_DECL_IMPL_DEF(void, iemAImpl_shufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3154	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3155	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3156	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3157	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3158
3159	IEM_DECL_IMPL_DEF(void, iemAImpl_shufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3160	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3161	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3162	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3163	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3164
3165	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
3166	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64_fallback,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
3167
3168	IEM_DECL_IMPL_DEF(void, iemAImpl_pinsrw_u64,(uint64_t *pu64Dst, uint16_t u16Src, uint8_t bEvil));
3169	IEM_DECL_IMPL_DEF(void, iemAImpl_pinsrw_u128,(PRTUINT128U puDst, uint16_t u16Src, uint8_t bEvil));
3170	IEM_DECL_IMPL_DEF(void, iemAImpl_vpinsrw_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint16_t u16Src, uint8_t bEvil));
3171	IEM_DECL_IMPL_DEF(void, iemAImpl_vpinsrw_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint16_t u16Src, uint8_t bEvil));
3172
3173	IEM_DECL_IMPL_DEF(void, iemAImpl_pextrw_u64,(uint16_t *pu16Dst, uint64_t u64Src, uint8_t bEvil));
3174	IEM_DECL_IMPL_DEF(void, iemAImpl_pextrw_u128,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
3175	IEM_DECL_IMPL_DEF(void, iemAImpl_vpextrw_u128,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
3176	IEM_DECL_IMPL_DEF(void, iemAImpl_vpextrw_u128_fallback,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
3177
3178	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3179	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3180	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3181	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3182	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3183
3184	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3185	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3186	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3187	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3188	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3189
3190
3191	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3192	typedef FNIEMAIMPLMEDIAOPTF2U128IMM8 *PFNIEMAIMPLMEDIAOPTF2U128IMM8;
3193	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3194	typedef FNIEMAIMPLMEDIAOPTF3U128IMM8 *PFNIEMAIMPLMEDIAOPTF3U128IMM8;
3195	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3196	typedef FNIEMAIMPLMEDIAOPTF3U256IMM8 *PFNIEMAIMPLMEDIAOPTF3U256IMM8;
3197
3198	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_palignr_u128, iemAImpl_palignr_u128_fallback;
3199	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pblendw_u128, iemAImpl_pblendw_u128_fallback;
3200	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendps_u128, iemAImpl_blendps_u128_fallback;
3201	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendpd_u128, iemAImpl_blendpd_u128_fallback;
3202
3203	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpalignr_u128, iemAImpl_vpalignr_u128_fallback;
3204	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendw_u128, iemAImpl_vpblendw_u128_fallback;
3205	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendps_u128, iemAImpl_vblendps_u128_fallback;
3206	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendpd_u128, iemAImpl_vblendpd_u128_fallback;
3207
3208	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpalignr_u256, iemAImpl_vpalignr_u256_fallback;
3209	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendw_u256, iemAImpl_vpblendw_u256_fallback;
3210	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendps_u256, iemAImpl_vblendps_u256_fallback;
3211	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendpd_u256, iemAImpl_vblendpd_u256_fallback;
3212	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2i128_u256, iemAImpl_vperm2i128_u256_fallback;
3213	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2f128_u256, iemAImpl_vperm2f128_u256_fallback;
3214
3215	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesimc_u128, iemAImpl_aesimc_u128_fallback;
3216	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenc_u128, iemAImpl_aesenc_u128_fallback;
3217	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenclast_u128, iemAImpl_aesenclast_u128_fallback;
3218	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdec_u128, iemAImpl_aesdec_u128_fallback;
3219	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdeclast_u128, iemAImpl_aesdeclast_u128_fallback;
3220
3221	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesimc_u128, iemAImpl_vaesimc_u128_fallback;
3222	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenc_u128, iemAImpl_vaesenc_u128_fallback;
3223	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenclast_u128, iemAImpl_vaesenclast_u128_fallback;
3224	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdec_u128, iemAImpl_vaesdec_u128_fallback;
3225	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdeclast_u128, iemAImpl_vaesdeclast_u128_fallback;
3226
3227	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_aeskeygenassist_u128, iemAImpl_aeskeygenassist_u128_fallback;
3228
3229	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vaeskeygenassist_u128, iemAImpl_vaeskeygenassist_u128_fallback;
3230
3231	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1nexte_u128, iemAImpl_sha1nexte_u128_fallback;
3232	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg1_u128, iemAImpl_sha1msg1_u128_fallback;
3233	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg2_u128, iemAImpl_sha1msg2_u128_fallback;
3234	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg1_u128, iemAImpl_sha256msg1_u128_fallback;
3235	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg2_u128, iemAImpl_sha256msg2_u128_fallback;
3236	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_sha1rnds4_u128, iemAImpl_sha1rnds4_u128_fallback;
3237	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
3238	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
3239
3240	typedef struct IEMPCMPISTRXSRC
3241	{
3242	RTUINT128U uSrc1;
3243	RTUINT128U uSrc2;
3244	} IEMPCMPISTRXSRC;
3245	typedef IEMPCMPISTRXSRC *PIEMPCMPISTRXSRC;
3246	typedef const IEMPCMPISTRXSRC *PCIEMPCMPISTRXSRC;
3247
3248	typedef struct IEMPCMPESTRXSRC
3249	{
3250	RTUINT128U uSrc1;
3251	RTUINT128U uSrc2;
3252	uint64_t u64Rax;
3253	uint64_t u64Rdx;
3254	} IEMPCMPESTRXSRC;
3255	typedef IEMPCMPESTRXSRC *PIEMPCMPESTRXSRC;
3256	typedef const IEMPCMPESTRXSRC *PCIEMPCMPESTRXSRC;
3257
3258	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPISTRIU128IMM8,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
3259	typedef FNIEMAIMPLPCMPISTRIU128IMM8 *PFNIEMAIMPLPCMPISTRIU128IMM8;
3260	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRIU128IMM8,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
3261	typedef FNIEMAIMPLPCMPESTRIU128IMM8 *PFNIEMAIMPLPCMPESTRIU128IMM8;
3262
3263	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPISTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
3264	typedef FNIEMAIMPLPCMPISTRMU128IMM8 *PFNIEMAIMPLPCMPISTRMU128IMM8;
3265	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
3266	typedef FNIEMAIMPLPCMPESTRMU128IMM8 *PFNIEMAIMPLPCMPESTRMU128IMM8;
3267
3268	FNIEMAIMPLPCMPISTRIU128IMM8 iemAImpl_pcmpistri_u128, iemAImpl_pcmpistri_u128_fallback;
3269	FNIEMAIMPLPCMPESTRIU128IMM8 iemAImpl_pcmpestri_u128, iemAImpl_pcmpestri_u128_fallback;
3270	FNIEMAIMPLPCMPISTRMU128IMM8 iemAImpl_pcmpistrm_u128, iemAImpl_pcmpistrm_u128_fallback;
3271	FNIEMAIMPLPCMPESTRMU128IMM8 iemAImpl_pcmpestrm_u128, iemAImpl_pcmpestrm_u128_fallback;
3272
3273	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pclmulqdq_u128, iemAImpl_pclmulqdq_u128_fallback;
3274	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpclmulqdq_u128, iemAImpl_vpclmulqdq_u128_fallback;
3275
3276	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_mpsadbw_u128, iemAImpl_mpsadbw_u128_fallback;
3277	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vmpsadbw_u128, iemAImpl_vmpsadbw_u128_fallback;
3278	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vmpsadbw_u256, iemAImpl_vmpsadbw_u256_fallback;
3279	/** @} */
3280
3281	/** @name Media Odds and Ends
3282	* @{ */
3283	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U8,(uint32_t *puDst, uint8_t uSrc));
3284	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U16,(uint32_t *puDst, uint16_t uSrc));
3285	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U32,(uint32_t *puDst, uint32_t uSrc));
3286	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U64,(uint32_t *puDst, uint64_t uSrc));
3287	FNIEMAIMPLCR32U8 iemAImpl_crc32_u8, iemAImpl_crc32_u8_fallback;
3288	FNIEMAIMPLCR32U16 iemAImpl_crc32_u16, iemAImpl_crc32_u16_fallback;
3289	FNIEMAIMPLCR32U32 iemAImpl_crc32_u32, iemAImpl_crc32_u32_fallback;
3290	FNIEMAIMPLCR32U64 iemAImpl_crc32_u64, iemAImpl_crc32_u64_fallback;
3291
3292	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL128,(PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint32_t *pEFlags));
3293	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL256,(PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint32_t *pEFlags));
3294	FNIEMAIMPLF2EFL128 iemAImpl_ptest_u128;
3295	FNIEMAIMPLF2EFL256 iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback;
3296
3297	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I32U64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int32_t pi32Dst, const uint64_t pu64Src)); / pu64Src is a double precision floating point. */
3298	typedef FNIEMAIMPLSSEF2I32U64 *PFNIEMAIMPLSSEF2I32U64;
3299	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I64U64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int64_t pi64Dst, const uint64_t pu64Src)); / pu64Src is a double precision floating point. */
3300	typedef FNIEMAIMPLSSEF2I64U64 *PFNIEMAIMPLSSEF2I64U64;
3301	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I32U32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int32_t pi32Dst, const uint32_t pu32Src)); / pu32Src is a single precision floating point. */
3302	typedef FNIEMAIMPLSSEF2I32U32 *PFNIEMAIMPLSSEF2I32U32;
3303	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I64U32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int64_t pi64Dst, const uint32_t pu32Src)); / pu32Src is a single precision floating point. */
3304	typedef FNIEMAIMPLSSEF2I64U32 *PFNIEMAIMPLSSEF2I64U32;
3305
3306	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvttsd2si_i32_r64;
3307	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvtsd2si_i32_r64;
3308
3309	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvttsd2si_i64_r64;
3310	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvtsd2si_i64_r64;
3311
3312	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvttss2si_i32_r32;
3313	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvtss2si_i32_r32;
3314
3315	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvttss2si_i64_r32;
3316	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvtss2si_i64_r32;
3317
3318	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R32I32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT32U pr32Dst, const int32_t pi32Src));
3319	typedef FNIEMAIMPLSSEF2R32I32 *PFNIEMAIMPLSSEF2R32I32;
3320	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R32I64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT32U pr32Dst, const int64_t pi64Src));
3321	typedef FNIEMAIMPLSSEF2R32I64 *PFNIEMAIMPLSSEF2R32I64;
3322
3323	FNIEMAIMPLSSEF2R32I32 iemAImpl_cvtsi2ss_r32_i32;
3324	FNIEMAIMPLSSEF2R32I64 iemAImpl_cvtsi2ss_r32_i64;
3325
3326	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R64I32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT64U pr64Dst, const int32_t pi32Src));
3327	typedef FNIEMAIMPLSSEF2R64I32 *PFNIEMAIMPLSSEF2R64I32;
3328	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R64I64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT64U pr64Dst, const int64_t pi64Src));
3329	typedef FNIEMAIMPLSSEF2R64I64 *PFNIEMAIMPLSSEF2R64I64;
3330
3331	FNIEMAIMPLSSEF2R64I32 iemAImpl_cvtsi2sd_r64_i32;
3332	FNIEMAIMPLSSEF2R64I64 iemAImpl_cvtsi2sd_r64_i64;
3333
3334
3335	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFLMXCSR128,(uint32_t pfMxcsr, uint32_t pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
3336	typedef FNIEMAIMPLF2EFLMXCSR128 *PFNIEMAIMPLF2EFLMXCSR128;
3337
3338	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_ucomiss_u128;
3339	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback;
3340
3341	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_ucomisd_u128;
3342	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback;
3343
3344	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_comiss_u128;
3345	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback;
3346
3347	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_comisd_u128;
3348	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback;
3349
3350
3351	typedef struct IEMMEDIAF2XMMSRC
3352	{
3353	X86XMMREG uSrc1;
3354	X86XMMREG uSrc2;
3355	} IEMMEDIAF2XMMSRC;
3356	typedef IEMMEDIAF2XMMSRC *PIEMMEDIAF2XMMSRC;
3357	typedef const IEMMEDIAF2XMMSRC *PCIEMMEDIAF2XMMSRC;
3358
3359	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRF2XMMIMM8,(uint32_t *pfMxcsr, PX86XMMREG puDst, PCIEMMEDIAF2XMMSRC puSrc, uint8_t bEvil));
3360	typedef FNIEMAIMPLMXCSRF2XMMIMM8 *PFNIEMAIMPLMXCSRF2XMMIMM8;
3361
3362	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpps_u128;
3363	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmppd_u128;
3364	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpss_u128;
3365	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpsd_u128;
3366	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundss_u128;
3367	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundsd_u128;
3368
3369	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundps_u128, iemAImpl_roundps_u128_fallback;
3370	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundpd_u128, iemAImpl_roundpd_u128_fallback;
3371
3372	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_dpps_u128, iemAImpl_dpps_u128_fallback;
3373	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_dppd_u128, iemAImpl_dppd_u128_fallback;
3374
3375	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU64U128,(uint32_t pfMxcsr, uint64_t pu64Dst, PCX86XMMREG pSrc));
3376	typedef FNIEMAIMPLMXCSRU64U128 *PFNIEMAIMPLMXCSRU64U128;
3377
3378	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvtpd2pi_u128;
3379	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvttpd2pi_u128;
3380
3381	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU128U64,(uint32_t *pfMxcsr, PX86XMMREG pDst, uint64_t u64Src));
3382	typedef FNIEMAIMPLMXCSRU128U64 *PFNIEMAIMPLMXCSRU128U64;
3383
3384	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2ps_u128;
3385	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2pd_u128;
3386
3387	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU64U64,(uint32_t pfMxcsr, uint64_t pu64Dst, uint64_t u64Src));
3388	typedef FNIEMAIMPLMXCSRU64U64 *PFNIEMAIMPLMXCSRU64U64;
3389
3390	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvtps2pi_u128;
3391	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvttps2pi_u128;
3392
3393	/** @} */
3394
3395
3396	/** @name Function tables.
3397	* @{
3398	*/
3399
3400	/**
3401	* Function table for a binary operator providing implementation based on
3402	* operand size.
3403	*/
3404	typedef struct IEMOPBINSIZES
3405	{
3406	PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
3407	PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
3408	PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
3409	PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
3410	} IEMOPBINSIZES;
3411	/** Pointer to a binary operator function table. */
3412	typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
3413
3414
3415	/**
3416	* Function table for a unary operator providing implementation based on
3417	* operand size.
3418	*/
3419	typedef struct IEMOPUNARYSIZES
3420	{
3421	PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
3422	PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
3423	PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
3424	PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
3425	} IEMOPUNARYSIZES;
3426	/** Pointer to a unary operator function table. */
3427	typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
3428
3429
3430	/**
3431	* Function table for a shift operator providing implementation based on
3432	* operand size.
3433	*/
3434	typedef struct IEMOPSHIFTSIZES
3435	{
3436	PFNIEMAIMPLSHIFTU8 pfnNormalU8;
3437	PFNIEMAIMPLSHIFTU16 pfnNormalU16;
3438	PFNIEMAIMPLSHIFTU32 pfnNormalU32;
3439	PFNIEMAIMPLSHIFTU64 pfnNormalU64;
3440	} IEMOPSHIFTSIZES;
3441	/** Pointer to a shift operator function table. */
3442	typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
3443
3444
3445	/**
3446	* Function table for a multiplication or division operation.
3447	*/
3448	typedef struct IEMOPMULDIVSIZES
3449	{
3450	PFNIEMAIMPLMULDIVU8 pfnU8;
3451	PFNIEMAIMPLMULDIVU16 pfnU16;
3452	PFNIEMAIMPLMULDIVU32 pfnU32;
3453	PFNIEMAIMPLMULDIVU64 pfnU64;
3454	} IEMOPMULDIVSIZES;
3455	/** Pointer to a multiplication or division operation function table. */
3456	typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
3457
3458
3459	/**
3460	* Function table for a double precision shift operator providing implementation
3461	* based on operand size.
3462	*/
3463	typedef struct IEMOPSHIFTDBLSIZES
3464	{
3465	PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
3466	PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
3467	PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
3468	} IEMOPSHIFTDBLSIZES;
3469	/** Pointer to a double precision shift function table. */
3470	typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
3471
3472
3473	/**
3474	* Function table for media instruction taking two full sized media source
3475	* registers and one full sized destination register (AVX).
3476	*/
3477	typedef struct IEMOPMEDIAF3
3478	{
3479	PFNIEMAIMPLMEDIAF3U128 pfnU128;
3480	PFNIEMAIMPLMEDIAF3U256 pfnU256;
3481	} IEMOPMEDIAF3;
3482	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
3483	typedef IEMOPMEDIAF3 const *PCIEMOPMEDIAF3;
3484
3485	/** @def IEMOPMEDIAF3_INIT_VARS_EX
3486	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3487	* given functions as initializers. For use in AVX functions where a pair of
3488	* functions are only used once and the function table need not be public. */
3489	#ifndef TST_IEM_CHECK_MC
3490	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3491	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3492	static IEMOPMEDIAF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3493	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3494	# else
3495	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3496	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3497	# endif
3498	#else
3499	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3500	#endif
3501	/** @def IEMOPMEDIAF3_INIT_VARS
3502	* Generate AVX function tables for the @a a_InstrNm instruction.
3503	* @sa IEMOPMEDIAF3_INIT_VARS_EX */
3504	#define IEMOPMEDIAF3_INIT_VARS(a_InstrNm) \
3505	IEMOPMEDIAF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3506	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3507
3508	/**
3509	* Function table for media instruction taking two full sized media source
3510	* registers and one full sized destination register, but no additional state
3511	* (AVX).
3512	*/
3513	typedef struct IEMOPMEDIAOPTF3
3514	{
3515	PFNIEMAIMPLMEDIAOPTF3U128 pfnU128;
3516	PFNIEMAIMPLMEDIAOPTF3U256 pfnU256;
3517	} IEMOPMEDIAOPTF3;
3518	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
3519	typedef IEMOPMEDIAOPTF3 const *PCIEMOPMEDIAOPTF3;
3520
3521	/** @def IEMOPMEDIAOPTF3_INIT_VARS_EX
3522	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3523	* given functions as initializers. For use in AVX functions where a pair of
3524	* functions are only used once and the function table need not be public. */
3525	#ifndef TST_IEM_CHECK_MC
3526	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3527	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3528	static IEMOPMEDIAOPTF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3529	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3530	# else
3531	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3532	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3533	# endif
3534	#else
3535	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3536	#endif
3537	/** @def IEMOPMEDIAOPTF3_INIT_VARS
3538	* Generate AVX function tables for the @a a_InstrNm instruction.
3539	* @sa IEMOPMEDIAOPTF3_INIT_VARS_EX */
3540	#define IEMOPMEDIAOPTF3_INIT_VARS(a_InstrNm) \
3541	IEMOPMEDIAOPTF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3542	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3543
3544	/**
3545	* Function table for media instruction taking one full sized media source
3546	* registers and one full sized destination register, but no additional state
3547	* (AVX).
3548	*/
3549	typedef struct IEMOPMEDIAOPTF2
3550	{
3551	PFNIEMAIMPLMEDIAOPTF2U128 pfnU128;
3552	PFNIEMAIMPLMEDIAOPTF2U256 pfnU256;
3553	} IEMOPMEDIAOPTF2;
3554	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
3555	typedef IEMOPMEDIAOPTF2 const *PCIEMOPMEDIAOPTF2;
3556
3557	/** @def IEMOPMEDIAOPTF2_INIT_VARS_EX
3558	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3559	* given functions as initializers. For use in AVX functions where a pair of
3560	* functions are only used once and the function table need not be public. */
3561	#ifndef TST_IEM_CHECK_MC
3562	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3563	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3564	static IEMOPMEDIAOPTF2 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3565	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3566	# else
3567	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3568	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3569	# endif
3570	#else
3571	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3572	#endif
3573	/** @def IEMOPMEDIAOPTF2_INIT_VARS
3574	* Generate AVX function tables for the @a a_InstrNm instruction.
3575	* @sa IEMOPMEDIAOPTF2_INIT_VARS_EX */
3576	#define IEMOPMEDIAOPTF2_INIT_VARS(a_InstrNm) \
3577	IEMOPMEDIAOPTF2_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3578	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3579
3580	/**
3581	* Function table for media instruction taking two full sized media source
3582	* registers and one full sized destination register and an 8-bit immediate, but no additional state
3583	* (AVX).
3584	*/
3585	typedef struct IEMOPMEDIAOPTF3IMM8
3586	{
3587	PFNIEMAIMPLMEDIAOPTF3U128IMM8 pfnU128;
3588	PFNIEMAIMPLMEDIAOPTF3U256IMM8 pfnU256;
3589	} IEMOPMEDIAOPTF3IMM8;
3590	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
3591	typedef IEMOPMEDIAOPTF3IMM8 const *PCIEMOPMEDIAOPTF3IMM8;
3592
3593	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX
3594	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3595	* given functions as initializers. For use in AVX functions where a pair of
3596	* functions are only used once and the function table need not be public. */
3597	#ifndef TST_IEM_CHECK_MC
3598	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3599	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3600	static IEMOPMEDIAOPTF3IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3601	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3602	# else
3603	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3604	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3605	# endif
3606	#else
3607	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3608	#endif
3609	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS
3610	* Generate AVX function tables for the @a a_InstrNm instruction.
3611	* @sa IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX */
3612	#define IEMOPMEDIAOPTF3IMM8_INIT_VARS(a_InstrNm) \
3613	IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3614	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3615	/** @} */
3616
3617
3618	/**
3619	* Function table for blend type instruction taking three full sized media source
3620	* registers and one full sized destination register, but no additional state
3621	* (AVX).
3622	*/
3623	typedef struct IEMOPBLENDOP
3624	{
3625	PFNIEMAIMPLAVXBLENDU128 pfnU128;
3626	PFNIEMAIMPLAVXBLENDU256 pfnU256;
3627	} IEMOPBLENDOP;
3628	/** Pointer to a media operation function table for 4 full sized ops (AVX). */
3629	typedef IEMOPBLENDOP const *PCIEMOPBLENDOP;
3630
3631	/** @def IEMOPBLENDOP_INIT_VARS_EX
3632	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3633	* given functions as initializers. For use in AVX functions where a pair of
3634	* functions are only used once and the function table need not be public. */
3635	#ifndef TST_IEM_CHECK_MC
3636	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3637	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3638	static IEMOPBLENDOP const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3639	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3640	# else
3641	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3642	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3643	# endif
3644	#else
3645	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3646	#endif
3647	/** @def IEMOPBLENDOP_INIT_VARS
3648	* Generate AVX function tables for the @a a_InstrNm instruction.
3649	* @sa IEMOPBLENDOP_INIT_VARS_EX */
3650	#define IEMOPBLENDOP_INIT_VARS(a_InstrNm) \
3651	IEMOPBLENDOP_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3652	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3653
3654
3655	/** @name SSE/AVX single/double precision floating point operations.
3656	* @{ */
3657	/**
3658	* A SSE result.
3659	*/
3660	typedef struct IEMSSERESULT
3661	{
3662	/** The output value. */
3663	X86XMMREG uResult;
3664	/** The output status. */
3665	uint32_t MXCSR;
3666	} IEMSSERESULT;
3667	AssertCompileMemberOffset(IEMSSERESULT, MXCSR, 128 / 8);
3668	/** Pointer to a SSE result. */
3669	typedef IEMSSERESULT *PIEMSSERESULT;
3670	/** Pointer to a const SSE result. */
3671	typedef IEMSSERESULT const *PCIEMSSERESULT;
3672
3673
3674	/**
3675	* A AVX128 result.
3676	*/
3677	typedef struct IEMAVX128RESULT
3678	{
3679	/** The output value. */
3680	X86XMMREG uResult;
3681	/** The output status. */
3682	uint32_t MXCSR;
3683	} IEMAVX128RESULT;
3684	AssertCompileMemberOffset(IEMAVX128RESULT, MXCSR, 128 / 8);
3685	/** Pointer to a AVX128 result. */
3686	typedef IEMAVX128RESULT *PIEMAVX128RESULT;
3687	/** Pointer to a const AVX128 result. */
3688	typedef IEMAVX128RESULT const *PCIEMAVX128RESULT;
3689
3690
3691	/**
3692	* A AVX256 result.
3693	*/
3694	typedef struct IEMAVX256RESULT
3695	{
3696	/** The output value. */
3697	X86YMMREG uResult;
3698	/** The output status. */
3699	uint32_t MXCSR;
3700	} IEMAVX256RESULT;
3701	AssertCompileMemberOffset(IEMAVX256RESULT, MXCSR, 256 / 8);
3702	/** Pointer to a AVX256 result. */
3703	typedef IEMAVX256RESULT *PIEMAVX256RESULT;
3704	/** Pointer to a const AVX256 result. */
3705	typedef IEMAVX256RESULT const *PCIEMAVX256RESULT;
3706
3707
3708	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
3709	typedef FNIEMAIMPLFPSSEF2U128 *PFNIEMAIMPLFPSSEF2U128;
3710	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128R32,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
3711	typedef FNIEMAIMPLFPSSEF2U128R32 *PFNIEMAIMPLFPSSEF2U128R32;
3712	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128R64,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
3713	typedef FNIEMAIMPLFPSSEF2U128R64 *PFNIEMAIMPLFPSSEF2U128R64;
3714
3715	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
3716	typedef FNIEMAIMPLFPAVXF3U128 *PFNIEMAIMPLFPAVXF3U128;
3717	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128R32,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
3718	typedef FNIEMAIMPLFPAVXF3U128R32 *PFNIEMAIMPLFPAVXF3U128R32;
3719	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128R64,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
3720	typedef FNIEMAIMPLFPAVXF3U128R64 *PFNIEMAIMPLFPAVXF3U128R64;
3721
3722	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U256,(PX86XSAVEAREA pExtState, PIEMAVX256RESULT pResult, PCX86YMMREG puSrc1, PCX86YMMREG puSrc2));
3723	typedef FNIEMAIMPLFPAVXF3U256 *PFNIEMAIMPLFPAVXF3U256;
3724
3725	FNIEMAIMPLFPSSEF2U128 iemAImpl_addps_u128;
3726	FNIEMAIMPLFPSSEF2U128 iemAImpl_addpd_u128;
3727	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulps_u128;
3728	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulpd_u128;
3729	FNIEMAIMPLFPSSEF2U128 iemAImpl_subps_u128;
3730	FNIEMAIMPLFPSSEF2U128 iemAImpl_subpd_u128;
3731	FNIEMAIMPLFPSSEF2U128 iemAImpl_minps_u128;
3732	FNIEMAIMPLFPSSEF2U128 iemAImpl_minpd_u128;
3733	FNIEMAIMPLFPSSEF2U128 iemAImpl_divps_u128;
3734	FNIEMAIMPLFPSSEF2U128 iemAImpl_divpd_u128;
3735	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxps_u128;
3736	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxpd_u128;
3737	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddps_u128;
3738	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddpd_u128;
3739	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubps_u128;
3740	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubpd_u128;
3741	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtps_u128;
3742	FNIEMAIMPLFPSSEF2U128 iemAImpl_rsqrtps_u128;
3743	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtpd_u128;
3744	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubps_u128;
3745	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubpd_u128;
3746	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2ps_u128;
3747	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2pd_u128;
3748
3749	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2ps_u128;
3750	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2dq_u128;
3751	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttps2dq_u128;
3752	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttpd2dq_u128;
3753	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2pd_u128;
3754	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2dq_u128;
3755
3756	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_addss_u128_r32;
3757	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_addsd_u128_r64;
3758	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_mulss_u128_r32;
3759	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_mulsd_u128_r64;
3760	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_subss_u128_r32;
3761	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_subsd_u128_r64;
3762	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_minss_u128_r32;
3763	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_minsd_u128_r64;
3764	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_divss_u128_r32;
3765	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_divsd_u128_r64;
3766	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_maxss_u128_r32;
3767	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_maxsd_u128_r64;
3768	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_cvtss2sd_u128_r32;
3769	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_cvtsd2ss_u128_r64;
3770	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_sqrtss_u128_r32;
3771	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_sqrtsd_u128_r64;
3772	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_rsqrtss_u128_r32;
3773
3774	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddps_u128, iemAImpl_vaddps_u128_fallback;
3775	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddpd_u128, iemAImpl_vaddpd_u128_fallback;
3776	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulps_u128, iemAImpl_vmulps_u128_fallback;
3777	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulpd_u128, iemAImpl_vmulpd_u128_fallback;
3778	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubps_u128, iemAImpl_vsubps_u128_fallback;
3779	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubpd_u128, iemAImpl_vsubpd_u128_fallback;
3780	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminps_u128, iemAImpl_vminps_u128_fallback;
3781	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminpd_u128, iemAImpl_vminpd_u128_fallback;
3782	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivps_u128, iemAImpl_vdivps_u128_fallback;
3783	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivpd_u128, iemAImpl_vdivpd_u128_fallback;
3784	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxps_u128, iemAImpl_vmaxps_u128_fallback;
3785	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxpd_u128, iemAImpl_vmaxpd_u128_fallback;
3786	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddps_u128, iemAImpl_vhaddps_u128_fallback;
3787	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddpd_u128, iemAImpl_vhaddpd_u128_fallback;
3788	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubps_u128, iemAImpl_vhsubps_u128_fallback;
3789	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubpd_u128, iemAImpl_vhsubpd_u128_fallback;
3790	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtps_u128, iemAImpl_vsqrtps_u128_fallback;
3791	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtpd_u128, iemAImpl_vsqrtpd_u128_fallback;
3792	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubps_u128, iemAImpl_vaddsubps_u128_fallback;
3793	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubpd_u128, iemAImpl_vaddsubpd_u128_fallback;
3794	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtpd2ps_u128, iemAImpl_vcvtpd2ps_u128_fallback;
3795	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtps2pd_u128, iemAImpl_vcvtps2pd_u128_fallback;
3796
3797	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vaddss_u128_r32, iemAImpl_vaddss_u128_r32_fallback;
3798	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vaddsd_u128_r64, iemAImpl_vaddsd_u128_r64_fallback;
3799	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmulss_u128_r32, iemAImpl_vmulss_u128_r32_fallback;
3800	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmulsd_u128_r64, iemAImpl_vmulsd_u128_r64_fallback;
3801	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsubss_u128_r32, iemAImpl_vsubss_u128_r32_fallback;
3802	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsubsd_u128_r64, iemAImpl_vsubsd_u128_r64_fallback;
3803	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vminss_u128_r32, iemAImpl_vminss_u128_r32_fallback;
3804	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vminsd_u128_r64, iemAImpl_vminsd_u128_r64_fallback;
3805	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vdivss_u128_r32, iemAImpl_vdivss_u128_r32_fallback;
3806	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vdivsd_u128_r64, iemAImpl_vdivsd_u128_r64_fallback;
3807	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmaxss_u128_r32, iemAImpl_vmaxss_u128_r32_fallback;
3808	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmaxsd_u128_r64, iemAImpl_vmaxsd_u128_r64_fallback;
3809	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsqrtss_u128_r32, iemAImpl_vsqrtss_u128_r32_fallback;
3810	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsqrtsd_u128_r64, iemAImpl_vsqrtsd_u128_r64_fallback;
3811
3812	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddps_u256, iemAImpl_vaddps_u256_fallback;
3813	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddpd_u256, iemAImpl_vaddpd_u256_fallback;
3814	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulps_u256, iemAImpl_vmulps_u256_fallback;
3815	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulpd_u256, iemAImpl_vmulpd_u256_fallback;
3816	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubps_u256, iemAImpl_vsubps_u256_fallback;
3817	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubpd_u256, iemAImpl_vsubpd_u256_fallback;
3818	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminps_u256, iemAImpl_vminps_u256_fallback;
3819	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminpd_u256, iemAImpl_vminpd_u256_fallback;
3820	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivps_u256, iemAImpl_vdivps_u256_fallback;
3821	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivpd_u256, iemAImpl_vdivpd_u256_fallback;
3822	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxps_u256, iemAImpl_vmaxps_u256_fallback;
3823	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxpd_u256, iemAImpl_vmaxpd_u256_fallback;
3824	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddps_u256, iemAImpl_vhaddps_u256_fallback;
3825	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddpd_u256, iemAImpl_vhaddpd_u256_fallback;
3826	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubps_u256, iemAImpl_vhsubps_u256_fallback;
3827	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubpd_u256, iemAImpl_vhsubpd_u256_fallback;
3828	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubps_u256, iemAImpl_vhaddsubps_u256_fallback;
3829	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubpd_u256, iemAImpl_vhaddsubpd_u256_fallback;
3830	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtpd2ps_u256, iemAImpl_vcvtpd2ps_u256_fallback;
3831	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtps2pd_u256, iemAImpl_vcvtps2pd_u256_fallback;
3832	/** @} */
3833
3834	/** @name C instruction implementations for anything slightly complicated.
3835	* @{ */
3836
3837	/**
3838	* For typedef'ing or declaring a C instruction implementation function taking
3839	* no extra arguments.
3840	*
3841	* @param a_Name The name of the type.
3842	*/
3843	# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
3844	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
3845	/**
3846	* For defining a C instruction implementation function taking no extra
3847	* arguments.
3848	*
3849	* @param a_Name The name of the function
3850	*/
3851	# define IEM_CIMPL_DEF_0(a_Name) \
3852	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
3853	/**
3854	* Prototype version of IEM_CIMPL_DEF_0.
3855	*/
3856	# define IEM_CIMPL_PROTO_0(a_Name) \
3857	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
3858	/**
3859	* For calling a C instruction implementation function taking no extra
3860	* arguments.
3861	*
3862	* This special call macro adds default arguments to the call and allow us to
3863	* change these later.
3864	*
3865	* @param a_fn The name of the function.
3866	*/
3867	# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
3868
3869	/** Type for a C instruction implementation function taking no extra
3870	* arguments. */
3871	typedef IEM_CIMPL_DECL_TYPE_0(FNIEMCIMPL0);
3872	/** Function pointer type for a C instruction implementation function taking
3873	* no extra arguments. */
3874	typedef FNIEMCIMPL0 *PFNIEMCIMPL0;
3875
3876	/**
3877	* For typedef'ing or declaring a C instruction implementation function taking
3878	* one extra argument.
3879	*
3880	* @param a_Name The name of the type.
3881	* @param a_Type0 The argument type.
3882	* @param a_Arg0 The argument name.
3883	*/
3884	# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
3885	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
3886	/**
3887	* For defining a C instruction implementation function taking one extra
3888	* argument.
3889	*
3890	* @param a_Name The name of the function
3891	* @param a_Type0 The argument type.
3892	* @param a_Arg0 The argument name.
3893	*/
3894	# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
3895	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
3896	/**
3897	* Prototype version of IEM_CIMPL_DEF_1.
3898	*/
3899	# define IEM_CIMPL_PROTO_1(a_Name, a_Type0, a_Arg0) \
3900	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
3901	/**
3902	* For calling a C instruction implementation function taking one extra
3903	* argument.
3904	*
3905	* This special call macro adds default arguments to the call and allow us to
3906	* change these later.
3907	*
3908	* @param a_fn The name of the function.
3909	* @param a0 The name of the 1st argument.
3910	*/
3911	# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
3912
3913	/**
3914	* For typedef'ing or declaring a C instruction implementation function taking
3915	* two extra arguments.
3916	*
3917	* @param a_Name The name of the type.
3918	* @param a_Type0 The type of the 1st argument
3919	* @param a_Arg0 The name of the 1st argument.
3920	* @param a_Type1 The type of the 2nd argument.
3921	* @param a_Arg1 The name of the 2nd argument.
3922	*/
3923	# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
3924	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
3925	/**
3926	* For defining a C instruction implementation function taking two extra
3927	* arguments.
3928	*
3929	* @param a_Name The name of the function.
3930	* @param a_Type0 The type of the 1st argument
3931	* @param a_Arg0 The name of the 1st argument.
3932	* @param a_Type1 The type of the 2nd argument.
3933	* @param a_Arg1 The name of the 2nd argument.
3934	*/
3935	# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
3936	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
3937	/**
3938	* Prototype version of IEM_CIMPL_DEF_2.
3939	*/
3940	# define IEM_CIMPL_PROTO_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
3941	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
3942	/**
3943	* For calling a C instruction implementation function taking two extra
3944	* arguments.
3945	*
3946	* This special call macro adds default arguments to the call and allow us to
3947	* change these later.
3948	*
3949	* @param a_fn The name of the function.
3950	* @param a0 The name of the 1st argument.
3951	* @param a1 The name of the 2nd argument.
3952	*/
3953	# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
3954
3955	/**
3956	* For typedef'ing or declaring a C instruction implementation function taking
3957	* three extra arguments.
3958	*
3959	* @param a_Name The name of the type.
3960	* @param a_Type0 The type of the 1st argument
3961	* @param a_Arg0 The name of the 1st argument.
3962	* @param a_Type1 The type of the 2nd argument.
3963	* @param a_Arg1 The name of the 2nd argument.
3964	* @param a_Type2 The type of the 3rd argument.
3965	* @param a_Arg2 The name of the 3rd argument.
3966	*/
3967	# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
3968	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
3969	/**
3970	* For defining a C instruction implementation function taking three extra
3971	* arguments.
3972	*
3973	* @param a_Name The name of the function.
3974	* @param a_Type0 The type of the 1st argument
3975	* @param a_Arg0 The name of the 1st argument.
3976	* @param a_Type1 The type of the 2nd argument.
3977	* @param a_Arg1 The name of the 2nd argument.
3978	* @param a_Type2 The type of the 3rd argument.
3979	* @param a_Arg2 The name of the 3rd argument.
3980	*/
3981	# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
3982	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
3983	/**
3984	* Prototype version of IEM_CIMPL_DEF_3.
3985	*/
3986	# define IEM_CIMPL_PROTO_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
3987	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
3988	/**
3989	* For calling a C instruction implementation function taking three extra
3990	* arguments.
3991	*
3992	* This special call macro adds default arguments to the call and allow us to
3993	* change these later.
3994	*
3995	* @param a_fn The name of the function.
3996	* @param a0 The name of the 1st argument.
3997	* @param a1 The name of the 2nd argument.
3998	* @param a2 The name of the 3rd argument.
3999	*/
4000	# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
4001
4002
4003	/**
4004	* For typedef'ing or declaring a C instruction implementation function taking
4005	* four extra arguments.
4006	*
4007	* @param a_Name The name of the type.
4008	* @param a_Type0 The type of the 1st argument
4009	* @param a_Arg0 The name of the 1st argument.
4010	* @param a_Type1 The type of the 2nd argument.
4011	* @param a_Arg1 The name of the 2nd argument.
4012	* @param a_Type2 The type of the 3rd argument.
4013	* @param a_Arg2 The name of the 3rd argument.
4014	* @param a_Type3 The type of the 4th argument.
4015	* @param a_Arg3 The name of the 4th argument.
4016	*/
4017	# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
4018	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
4019	/**
4020	* For defining a C instruction implementation function taking four extra
4021	* arguments.
4022	*
4023	* @param a_Name The name of the function.
4024	* @param a_Type0 The type of the 1st argument
4025	* @param a_Arg0 The name of the 1st argument.
4026	* @param a_Type1 The type of the 2nd argument.
4027	* @param a_Arg1 The name of the 2nd argument.
4028	* @param a_Type2 The type of the 3rd argument.
4029	* @param a_Arg2 The name of the 3rd argument.
4030	* @param a_Type3 The type of the 4th argument.
4031	* @param a_Arg3 The name of the 4th argument.
4032	*/
4033	# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
4034	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4035	a_Type2 a_Arg2, a_Type3 a_Arg3))
4036	/**
4037	* Prototype version of IEM_CIMPL_DEF_4.
4038	*/
4039	# define IEM_CIMPL_PROTO_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
4040	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4041	a_Type2 a_Arg2, a_Type3 a_Arg3))
4042	/**
4043	* For calling a C instruction implementation function taking four extra
4044	* arguments.
4045	*
4046	* This special call macro adds default arguments to the call and allow us to
4047	* change these later.
4048	*
4049	* @param a_fn The name of the function.
4050	* @param a0 The name of the 1st argument.
4051	* @param a1 The name of the 2nd argument.
4052	* @param a2 The name of the 3rd argument.
4053	* @param a3 The name of the 4th argument.
4054	*/
4055	# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
4056
4057
4058	/**
4059	* For typedef'ing or declaring a C instruction implementation function taking
4060	* five extra arguments.
4061	*
4062	* @param a_Name The name of the type.
4063	* @param a_Type0 The type of the 1st argument
4064	* @param a_Arg0 The name of the 1st argument.
4065	* @param a_Type1 The type of the 2nd argument.
4066	* @param a_Arg1 The name of the 2nd argument.
4067	* @param a_Type2 The type of the 3rd argument.
4068	* @param a_Arg2 The name of the 3rd argument.
4069	* @param a_Type3 The type of the 4th argument.
4070	* @param a_Arg3 The name of the 4th argument.
4071	* @param a_Type4 The type of the 5th argument.
4072	* @param a_Arg4 The name of the 5th argument.
4073	*/
4074	# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
4075	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, \
4076	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
4077	a_Type3 a_Arg3, a_Type4 a_Arg4))
4078	/**
4079	* For defining a C instruction implementation function taking five extra
4080	* arguments.
4081	*
4082	* @param a_Name The name of the function.
4083	* @param a_Type0 The type of the 1st argument
4084	* @param a_Arg0 The name of the 1st argument.
4085	* @param a_Type1 The type of the 2nd argument.
4086	* @param a_Arg1 The name of the 2nd argument.
4087	* @param a_Type2 The type of the 3rd argument.
4088	* @param a_Arg2 The name of the 3rd argument.
4089	* @param a_Type3 The type of the 4th argument.
4090	* @param a_Arg3 The name of the 4th argument.
4091	* @param a_Type4 The type of the 5th argument.
4092	* @param a_Arg4 The name of the 5th argument.
4093	*/
4094	# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
4095	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4096	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
4097	/**
4098	* Prototype version of IEM_CIMPL_DEF_5.
4099	*/
4100	# define IEM_CIMPL_PROTO_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
4101	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4102	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
4103	/**
4104	* For calling a C instruction implementation function taking five extra
4105	* arguments.
4106	*
4107	* This special call macro adds default arguments to the call and allow us to
4108	* change these later.
4109	*
4110	* @param a_fn The name of the function.
4111	* @param a0 The name of the 1st argument.
4112	* @param a1 The name of the 2nd argument.
4113	* @param a2 The name of the 3rd argument.
4114	* @param a3 The name of the 4th argument.
4115	* @param a4 The name of the 5th argument.
4116	*/
4117	# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
4118
4119	/** @} */
4120
4121
4122	/** @name Opcode Decoder Function Types.
4123	* @{ */
4124
4125	/** @typedef PFNIEMOP
4126	* Pointer to an opcode decoder function.
4127	*/
4128
4129	/** @def FNIEMOP_DEF
4130	* Define an opcode decoder function.
4131	*
4132	* We're using macors for this so that adding and removing parameters as well as
4133	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL
4134	*
4135	* @param a_Name The function name.
4136	*/
4137
4138	/** @typedef PFNIEMOPRM
4139	* Pointer to an opcode decoder function with RM byte.
4140	*/
4141
4142	/** @def FNIEMOPRM_DEF
4143	* Define an opcode decoder function with RM byte.
4144	*
4145	* We're using macors for this so that adding and removing parameters as well as
4146	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL_1
4147	*
4148	* @param a_Name The function name.
4149	*/
4150
4151	#if defined(__GNUC__) && defined(RT_ARCH_X86)
4152	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOP)(PVMCPUCC pVCpu);
4153	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4154	# define FNIEMOP_DEF(a_Name) \
4155	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu)
4156	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4157	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
4158	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4159	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
4160
4161	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
4162	typedef VBOXSTRICTRC (__fastcall * PFNIEMOP)(PVMCPUCC pVCpu);
4163	typedef VBOXSTRICTRC (__fastcall * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4164	# define FNIEMOP_DEF(a_Name) \
4165	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
4166	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4167	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
4168	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4169	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
4170
4171	#elif defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
4172	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
4173	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4174	# define FNIEMOP_DEF(a_Name) \
4175	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu)
4176	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4177	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
4178	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4179	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
4180
4181	#else
4182	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
4183	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4184	# define FNIEMOP_DEF(a_Name) \
4185	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
4186	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4187	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
4188	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4189	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
4190
4191	#endif
4192	#define FNIEMOPRM_DEF(a_Name) FNIEMOP_DEF_1(a_Name, uint8_t, bRm)
4193
4194	/**
4195	* Call an opcode decoder function.
4196	*
4197	* We're using macors for this so that adding and removing parameters can be
4198	* done as we please. See FNIEMOP_DEF.
4199	*/
4200	#define FNIEMOP_CALL(a_pfn) (a_pfn)(pVCpu)
4201
4202	/**
4203	* Call a common opcode decoder function taking one extra argument.
4204	*
4205	* We're using macors for this so that adding and removing parameters can be
4206	* done as we please. See FNIEMOP_DEF_1.
4207	*/
4208	#define FNIEMOP_CALL_1(a_pfn, a0) (a_pfn)(pVCpu, a0)
4209
4210	/**
4211	* Call a common opcode decoder function taking one extra argument.
4212	*
4213	* We're using macors for this so that adding and removing parameters can be
4214	* done as we please. See FNIEMOP_DEF_1.
4215	*/
4216	#define FNIEMOP_CALL_2(a_pfn, a0, a1) (a_pfn)(pVCpu, a0, a1)
4217	/** @} */
4218
4219
4220	/** @name Misc Helpers
4221	* @{ */
4222
4223	/** Used to shut up GCC warnings about variables that 'may be used uninitialized'
4224	* due to GCC lacking knowledge about the value range of a switch. */
4225	#if RT_CPLUSPLUS_PREREQ(202000)
4226	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: [[unlikely]] AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
4227	#else
4228	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
4229	#endif
4230
4231	/** Variant of IEM_NOT_REACHED_DEFAULT_CASE_RET that returns a custom value. */
4232	#if RT_CPLUSPLUS_PREREQ(202000)
4233	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: [[unlikely]] AssertFailedReturn(a_RetValue)
4234	#else
4235	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: AssertFailedReturn(a_RetValue)
4236	#endif
4237
4238	/**
4239	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
4240	* occation.
4241	*/
4242	#ifdef LOG_ENABLED
4243	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
4244	do { \
4245	/Log/ LogAlways(("%s: returning IEM_RETURN_ASPECT_NOT_IMPLEMENTED (line %d)\n", __FUNCTION__, __LINE__)); \
4246	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
4247	} while (0)
4248	#else
4249	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
4250	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
4251	#endif
4252
4253	/**
4254	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
4255	* occation using the supplied logger statement.
4256	*
4257	* @param a_LoggerArgs What to log on failure.
4258	*/
4259	#ifdef LOG_ENABLED
4260	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
4261	do { \
4262	LogAlways((LOG_FN_FMT ": ", __PRETTY_FUNCTION__)); LogAlways(a_LoggerArgs); \
4263	/LogFunc(a_LoggerArgs);/ \
4264	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
4265	} while (0)
4266	#else
4267	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
4268	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
4269	#endif
4270
4271	/**
4272	* Gets the CPU mode (from fExec) as a IEMMODE value.
4273	*
4274	* @returns IEMMODE
4275	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4276	*/
4277	#define IEM_GET_CPU_MODE(a_pVCpu) ((a_pVCpu)->iem.s.fExec & IEM_F_MODE_CPUMODE_MASK)
4278
4279	/**
4280	* Check if we're currently executing in real or virtual 8086 mode.
4281	*
4282	* @returns @c true if it is, @c false if not.
4283	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4284	*/
4285	#define IEM_IS_REAL_OR_V86_MODE(a_pVCpu) (( ((a_pVCpu)->iem.s.fExec ^ IEM_F_MODE_X86_PROT_MASK) \
4286	& (IEM_F_MODE_X86_V86_MASK \| IEM_F_MODE_X86_PROT_MASK)) != 0)
4287
4288	/**
4289	* Check if we're currently executing in virtual 8086 mode.
4290	*
4291	* @returns @c true if it is, @c false if not.
4292	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4293	*/
4294	#define IEM_IS_V86_MODE(a_pVCpu) (((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_V86_MASK) != 0)
4295
4296	/**
4297	* Check if we're currently executing in long mode.
4298	*
4299	* @returns @c true if it is, @c false if not.
4300	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4301	*/
4302	#define IEM_IS_LONG_MODE(a_pVCpu) (CPUMIsGuestInLongModeEx(IEM_GET_CTX(a_pVCpu)))
4303
4304	/**
4305	* Check if we're currently executing in a 16-bit code segment.
4306	*
4307	* @returns @c true if it is, @c false if not.
4308	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4309	*/
4310	#define IEM_IS_16BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_16BIT)
4311
4312	/**
4313	* Check if we're currently executing in a 32-bit code segment.
4314	*
4315	* @returns @c true if it is, @c false if not.
4316	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4317	*/
4318	#define IEM_IS_32BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_32BIT)
4319
4320	/**
4321	* Check if we're currently executing in a 64-bit code segment.
4322	*
4323	* @returns @c true if it is, @c false if not.
4324	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4325	*/
4326	#define IEM_IS_64BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_64BIT)
4327
4328	/**
4329	* Check if we're currently executing in real mode.
4330	*
4331	* @returns @c true if it is, @c false if not.
4332	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4333	*/
4334	#define IEM_IS_REAL_MODE(a_pVCpu) (!((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_PROT_MASK))
4335
4336	/**
4337	* Gets the current protection level (CPL).
4338	*
4339	* @returns 0..3
4340	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4341	*/
4342	#define IEM_GET_CPL(a_pVCpu) (((a_pVCpu)->iem.s.fExec >> IEM_F_X86_CPL_SHIFT) & IEM_F_X86_CPL_SMASK)
4343
4344	/**
4345	* Sets the current protection level (CPL).
4346	*
4347	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4348	*/
4349	#define IEM_SET_CPL(a_pVCpu, a_uCpl) \
4350	do { (a_pVCpu)->iem.s.fExec = ((a_pVCpu)->iem.s.fExec & ~IEM_F_X86_CPL_MASK) \| ((a_uCpl) << IEM_F_X86_CPL_SHIFT); } while (0)
4351
4352	/**
4353	* Returns a (const) pointer to the CPUMFEATURES for the guest CPU.
4354	* @returns PCCPUMFEATURES
4355	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4356	*/
4357	#define IEM_GET_GUEST_CPU_FEATURES(a_pVCpu) (&((a_pVCpu)->CTX_SUFF(pVM)->cpum.ro.GuestFeatures))
4358
4359	/**
4360	* Returns a (const) pointer to the CPUMFEATURES for the host CPU.
4361	* @returns PCCPUMFEATURES
4362	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4363	*/
4364	#define IEM_GET_HOST_CPU_FEATURES(a_pVCpu) (&g_CpumHostFeatures.s)
4365
4366	/**
4367	* Evaluates to true if we're presenting an Intel CPU to the guest.
4368	*/
4369	#define IEM_IS_GUEST_CPU_INTEL(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL )
4370
4371	/**
4372	* Evaluates to true if we're presenting an AMD CPU to the guest.
4373	*/
4374	#define IEM_IS_GUEST_CPU_AMD(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_AMD \|\| (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_HYGON )
4375
4376	/**
4377	* Check if the address is canonical.
4378	*/
4379	#define IEM_IS_CANONICAL(a_u64Addr) X86_IS_CANONICAL(a_u64Addr)
4380
4381	/** Checks if the ModR/M byte is in register mode or not. */
4382	#define IEM_IS_MODRM_REG_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT) )
4383	/** Checks if the ModR/M byte is in memory mode or not. */
4384	#define IEM_IS_MODRM_MEM_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT) )
4385
4386	/**
4387	* Gets the register (reg) part of a ModR/M encoding, with REX.R added in.
4388	*
4389	* For use during decoding.
4390	*/
4391	#define IEM_GET_MODRM_REG(a_pVCpu, a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| (a_pVCpu)->iem.s.uRexReg )
4392	/**
4393	* Gets the r/m part of a ModR/M encoding as a register index, with REX.B added in.
4394	*
4395	* For use during decoding.
4396	*/
4397	#define IEM_GET_MODRM_RM(a_pVCpu, a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) \| (a_pVCpu)->iem.s.uRexB )
4398
4399	/**
4400	* Gets the register (reg) part of a ModR/M encoding, without REX.R.
4401	*
4402	* For use during decoding.
4403	*/
4404	#define IEM_GET_MODRM_REG_8(a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) )
4405	/**
4406	* Gets the r/m part of a ModR/M encoding as a register index, without REX.B.
4407	*
4408	* For use during decoding.
4409	*/
4410	#define IEM_GET_MODRM_RM_8(a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) )
4411
4412	/**
4413	* Gets the register (reg) part of a ModR/M encoding as an extended 8-bit
4414	* register index, with REX.R added in.
4415	*
4416	* For use during decoding.
4417	*
4418	* @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
4419	*/
4420	#define IEM_GET_MODRM_REG_EX8(a_pVCpu, a_bRm) \
4421	( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
4422	\|\| !((a_bRm) & (4 << X86_MODRM_REG_SHIFT)) /* IEM_GET_MODRM_REG(pVCpu, a_bRm) < 4 */ \
4423	? IEM_GET_MODRM_REG(pVCpu, a_bRm) : (((a_bRm) >> X86_MODRM_REG_SHIFT) & 3) \| 16)
4424	/**
4425	* Gets the r/m part of a ModR/M encoding as an extended 8-bit register index,
4426	* with REX.B added in.
4427	*
4428	* For use during decoding.
4429	*
4430	* @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
4431	*/
4432	#define IEM_GET_MODRM_RM_EX8(a_pVCpu, a_bRm) \
4433	( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
4434	\|\| !((a_bRm) & 4) /* IEM_GET_MODRM_RM(pVCpu, a_bRm) < 4 */ \
4435	? IEM_GET_MODRM_RM(pVCpu, a_bRm) : ((a_bRm) & 3) \| 16)
4436
4437	/**
4438	* Combines the prefix REX and ModR/M byte for passing to
4439	* iemOpHlpCalcRmEffAddrThreadedAddr64().
4440	*
4441	* @returns The ModRM byte but with bit 3 set to REX.B and bit 4 to REX.X.
4442	* The two bits are part of the REG sub-field, which isn't needed in
4443	* iemOpHlpCalcRmEffAddrThreadedAddr64().
4444	*
4445	* For use during decoding/recompiling.
4446	*/
4447	#define IEM_GET_MODRM_EX(a_pVCpu, a_bRm) \
4448	( ((a_bRm) & ~X86_MODRM_REG_MASK) \
4449	\| (uint8_t)( (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X)) >> (26 - 3) ) )
4450	AssertCompile(IEM_OP_PRF_REX_B == RT_BIT_32(26));
4451	AssertCompile(IEM_OP_PRF_REX_X == RT_BIT_32(27));
4452
4453	/**
4454	* Gets the effective VEX.VVVV value.
4455	*
4456	* The 4th bit is ignored if not 64-bit code.
4457	* @returns effective V-register value.
4458	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4459	*/
4460	#define IEM_GET_EFFECTIVE_VVVV(a_pVCpu) \
4461	(IEM_IS_64BIT_CODE(a_pVCpu) ? (a_pVCpu)->iem.s.uVex3rdReg : (a_pVCpu)->iem.s.uVex3rdReg & 7)
4462
4463
4464	/**
4465	* Checks if we're executing inside an AMD-V or VT-x guest.
4466	*/
4467	#if defined(VBOX_WITH_NESTED_HWVIRT_VMX) \|\| defined(VBOX_WITH_NESTED_HWVIRT_SVM)
4468	# define IEM_IS_IN_GUEST(a_pVCpu) RT_BOOL((a_pVCpu)->iem.s.fExec & IEM_F_X86_CTX_IN_GUEST)
4469	#else
4470	# define IEM_IS_IN_GUEST(a_pVCpu) false
4471	#endif
4472
4473
4474	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
4475
4476	/**
4477	* Check if the guest has entered VMX root operation.
4478	*/
4479	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxRootMode(IEM_GET_CTX(a_pVCpu)))
4480
4481	/**
4482	* Check if the guest has entered VMX non-root operation.
4483	*/
4484	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) ( ((a_pVCpu)->iem.s.fExec & (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST)) \
4485	== (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST) )
4486
4487	/**
4488	* Check if the nested-guest has the given Pin-based VM-execution control set.
4489	*/
4490	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_PinCtl) (CPUMIsGuestVmxPinCtlsSet(IEM_GET_CTX(a_pVCpu), (a_PinCtl)))
4491
4492	/**
4493	* Check if the nested-guest has the given Processor-based VM-execution control set.
4494	*/
4495	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_ProcCtl) (CPUMIsGuestVmxProcCtlsSet(IEM_GET_CTX(a_pVCpu), (a_ProcCtl)))
4496
4497	/**
4498	* Check if the nested-guest has the given Secondary Processor-based VM-execution
4499	* control set.
4500	*/
4501	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_ProcCtl2) (CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(a_pVCpu), (a_ProcCtl2)))
4502
4503	/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
4504	# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
4505
4506	/** Whether a shadow VMCS is present for the given VCPU. */
4507	# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
4508
4509	/** Gets the VMXON region pointer. */
4510	# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
4511
4512	/** Gets the guest-physical address of the current VMCS for the given VCPU. */
4513	# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
4514
4515	/** Whether a current VMCS is present for the given VCPU. */
4516	# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
4517
4518	/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
4519	# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
4520	do \
4521	{ \
4522	Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
4523	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
4524	} while (0)
4525
4526	/** Clears any current VMCS for the given VCPU. */
4527	# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
4528	do \
4529	{ \
4530	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
4531	} while (0)
4532
4533	/**
4534	* Invokes the VMX VM-exit handler for an instruction intercept.
4535	*/
4536	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) \
4537	do { return iemVmxVmexitInstr((a_pVCpu), (a_uExitReason), (a_cbInstr)); } while (0)
4538
4539	/**
4540	* Invokes the VMX VM-exit handler for an instruction intercept where the
4541	* instruction provides additional VM-exit information.
4542	*/
4543	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) \
4544	do { return iemVmxVmexitInstrNeedsInfo((a_pVCpu), (a_uExitReason), (a_uInstrId), (a_cbInstr)); } while (0)
4545
4546	/**
4547	* Invokes the VMX VM-exit handler for a task switch.
4548	*/
4549	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) \
4550	do { return iemVmxVmexitTaskSwitch((a_pVCpu), (a_enmTaskSwitch), (a_SelNewTss), (a_cbInstr)); } while (0)
4551
4552	/**
4553	* Invokes the VMX VM-exit handler for MWAIT.
4554	*/
4555	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) \
4556	do { return iemVmxVmexitInstrMwait((a_pVCpu), (a_fMonitorArmed), (a_cbInstr)); } while (0)
4557
4558	/**
4559	* Invokes the VMX VM-exit handler for EPT faults.
4560	*/
4561	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) \
4562	do { return iemVmxVmexitEpt(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr); } while (0)
4563
4564	/**
4565	* Invokes the VMX VM-exit handler.
4566	*/
4567	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) \
4568	do { return iemVmxVmexit((a_pVCpu), (a_uExitReason), (a_uExitQual)); } while (0)
4569
4570	#else
4571	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (false)
4572	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (false)
4573	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_cbInstr) (false)
4574	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_cbInstr) (false)
4575	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_cbInstr) (false)
4576	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4577	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4578	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4579	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4580	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4581	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) do { return VERR_VMX_IPE_1; } while (0)
4582
4583	#endif
4584
4585	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4586	/**
4587	* Checks if we're executing a guest using AMD-V.
4588	*/
4589	# define IEM_SVM_IS_IN_GUEST(a_pVCpu) ( (a_pVCpu->iem.s.fExec & (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST)) \
4590	== (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST))
4591	/**
4592	* Check if an SVM control/instruction intercept is set.
4593	*/
4594	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) \
4595	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmCtrlInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_Intercept)))
4596
4597	/**
4598	* Check if an SVM read CRx intercept is set.
4599	*/
4600	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
4601	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
4602
4603	/**
4604	* Check if an SVM write CRx intercept is set.
4605	*/
4606	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
4607	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
4608
4609	/**
4610	* Check if an SVM read DRx intercept is set.
4611	*/
4612	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
4613	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
4614
4615	/**
4616	* Check if an SVM write DRx intercept is set.
4617	*/
4618	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
4619	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
4620
4621	/**
4622	* Check if an SVM exception intercept is set.
4623	*/
4624	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) \
4625	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmXcptInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uVector)))
4626
4627	/**
4628	* Invokes the SVM \#VMEXIT handler for the nested-guest.
4629	*/
4630	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
4631	do { return iemSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2)); } while (0)
4632
4633	/**
4634	* Invokes the 'MOV CRx' SVM \#VMEXIT handler after constructing the
4635	* corresponding decode assist information.
4636	*/
4637	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) \
4638	do \
4639	{ \
4640	uint64_t uExitInfo1; \
4641	if ( IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmDecodeAssists \
4642	&& (a_enmAccessCrX) == IEMACCESSCRX_MOV_CRX) \
4643	uExitInfo1 = SVM_EXIT1_MOV_CRX_MASK \| ((a_iGReg) & 7); \
4644	else \
4645	uExitInfo1 = 0; \
4646	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, uExitInfo1, 0); \
4647	} while (0)
4648
4649	/** Check and handles SVM nested-guest instruction intercept and updates
4650	* NRIP if needed.
4651	*/
4652	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
4653	do \
4654	{ \
4655	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept)) \
4656	{ \
4657	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
4658	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2); \
4659	} \
4660	} while (0)
4661
4662	/** Checks and handles SVM nested-guest CR0 read intercept. */
4663	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
4664	do \
4665	{ \
4666	if (!IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, 0)) \
4667	{ /* probably likely */ } \
4668	else \
4669	{ \
4670	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
4671	IEM_SVM_VMEXIT_RET(a_pVCpu, SVM_EXIT_READ_CR0, a_uExitInfo1, a_uExitInfo2); \
4672	} \
4673	} while (0)
4674
4675	/**
4676	* Updates the NextRIP (NRI) field in the nested-guest VMCB.
4677	*/
4678	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) \
4679	do { \
4680	if (IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmNextRipSave) \
4681	CPUMGuestSvmUpdateNRip(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_cbInstr)); \
4682	} while (0)
4683
4684	#else
4685	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) (false)
4686	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
4687	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
4688	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
4689	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
4690	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) (false)
4691	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { return VERR_SVM_IPE_1; } while (0)
4692	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) do { return VERR_SVM_IPE_1; } while (0)
4693	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, \
4694	a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
4695	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
4696	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) do { } while (0)
4697
4698	#endif
4699
4700	/** @} */
4701
4702	uint32_t iemCalcExecDbgFlagsSlow(PVMCPUCC pVCpu);
4703	VBOXSTRICTRC iemExecInjectPendingTrap(PVMCPUCC pVCpu);
4704
4705
4706	/**
4707	* Selector descriptor table entry as fetched by iemMemFetchSelDesc.
4708	*/
4709	typedef union IEMSELDESC
4710	{
4711	/** The legacy view. */
4712	X86DESC Legacy;
4713	/** The long mode view. */
4714	X86DESC64 Long;
4715	} IEMSELDESC;
4716	/** Pointer to a selector descriptor table entry. */
4717	typedef IEMSELDESC *PIEMSELDESC;
4718
4719	/** @name Raising Exceptions.
4720	* @{ */
4721	VBOXSTRICTRC iemTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, uint32_t uNextEip, uint32_t fFlags,
4722	uint16_t uErr, uint64_t uCr2, RTSEL SelTSS, PIEMSELDESC pNewDescTSS) RT_NOEXCEPT;
4723
4724	VBOXSTRICTRC iemRaiseXcptOrInt(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags,
4725	uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
4726	#ifdef IEM_WITH_SETJMP
4727	DECL_NO_RETURN(void) iemRaiseXcptOrIntJmp(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector,
4728	uint32_t fFlags, uint16_t uErr, uint64_t uCr2) IEM_NOEXCEPT_MAY_LONGJMP;
4729	#endif
4730	VBOXSTRICTRC iemRaiseDivideError(PVMCPUCC pVCpu) RT_NOEXCEPT;
4731	VBOXSTRICTRC iemRaiseDebugException(PVMCPUCC pVCpu) RT_NOEXCEPT;
4732	VBOXSTRICTRC iemRaiseBoundRangeExceeded(PVMCPUCC pVCpu) RT_NOEXCEPT;
4733	VBOXSTRICTRC iemRaiseUndefinedOpcode(PVMCPUCC pVCpu) RT_NOEXCEPT;
4734	VBOXSTRICTRC iemRaiseDeviceNotAvailable(PVMCPUCC pVCpu) RT_NOEXCEPT;
4735	VBOXSTRICTRC iemRaiseTaskSwitchFaultWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
4736	VBOXSTRICTRC iemRaiseTaskSwitchFaultCurrentTSS(PVMCPUCC pVCpu) RT_NOEXCEPT;
4737	VBOXSTRICTRC iemRaiseTaskSwitchFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
4738	VBOXSTRICTRC iemRaiseTaskSwitchFaultBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
4739	/VBOXSTRICTRC iemRaiseSelectorNotPresent(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;/
4740	VBOXSTRICTRC iemRaiseSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
4741	VBOXSTRICTRC iemRaiseSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
4742	VBOXSTRICTRC iemRaiseStackSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
4743	VBOXSTRICTRC iemRaiseStackSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
4744	VBOXSTRICTRC iemRaiseGeneralProtectionFault(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
4745	VBOXSTRICTRC iemRaiseGeneralProtectionFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
4746	#ifdef IEM_WITH_SETJMP
4747	DECL_NO_RETURN(void) iemRaiseGeneralProtectionFault0Jmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4748	#endif
4749	VBOXSTRICTRC iemRaiseGeneralProtectionFaultBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
4750	VBOXSTRICTRC iemRaiseNotCanonical(PVMCPUCC pVCpu) RT_NOEXCEPT;
4751	VBOXSTRICTRC iemRaiseSelectorBounds(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
4752	#ifdef IEM_WITH_SETJMP
4753	DECL_NO_RETURN(void) iemRaiseSelectorBoundsJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
4754	#endif
4755	VBOXSTRICTRC iemRaiseSelectorBoundsBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
4756	#ifdef IEM_WITH_SETJMP
4757	DECL_NO_RETURN(void) iemRaiseSelectorBoundsBySelectorJmp(PVMCPUCC pVCpu, RTSEL Sel) IEM_NOEXCEPT_MAY_LONGJMP;
4758	#endif
4759	VBOXSTRICTRC iemRaiseSelectorInvalidAccess(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
4760	#ifdef IEM_WITH_SETJMP
4761	DECL_NO_RETURN(void) iemRaiseSelectorInvalidAccessJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
4762	#endif
4763	VBOXSTRICTRC iemRaisePageFault(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) RT_NOEXCEPT;
4764	#ifdef IEM_WITH_SETJMP
4765	DECL_NO_RETURN(void) iemRaisePageFaultJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) IEM_NOEXCEPT_MAY_LONGJMP;
4766	#endif
4767	VBOXSTRICTRC iemRaiseMathFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
4768	VBOXSTRICTRC iemRaiseAlignmentCheckException(PVMCPUCC pVCpu) RT_NOEXCEPT;
4769	#ifdef IEM_WITH_SETJMP
4770	DECL_NO_RETURN(void) iemRaiseAlignmentCheckExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4771	#endif
4772	VBOXSTRICTRC iemRaiseSimdFpException(PVMCPUCC pVCpu) RT_NOEXCEPT;
4773
4774	void iemLogSyscallProtModeInt(PVMCPUCC pVCpu, uint8_t u8Vector, uint8_t cbInstr);
4775
4776	IEM_CIMPL_DEF_0(iemCImplRaiseDivideError);
4777	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidLockPrefix);
4778	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidOpcode);
4779
4780	/**
4781	* Macro for calling iemCImplRaiseDivideError().
4782	*
4783	* This is for things that will _always_ decode to an \#DE, taking the
4784	* recompiler into consideration and everything.
4785	*
4786	* @return Strict VBox status code.
4787	*/
4788	#define IEMOP_RAISE_DIVIDE_ERROR_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, iemCImplRaiseDivideError)
4789
4790	/**
4791	* Macro for calling iemCImplRaiseInvalidLockPrefix().
4792	*
4793	* This is for things that will _always_ decode to an \#UD, taking the
4794	* recompiler into consideration and everything.
4795	*
4796	* @return Strict VBox status code.
4797	*/
4798	#define IEMOP_RAISE_INVALID_LOCK_PREFIX_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, iemCImplRaiseInvalidLockPrefix)
4799
4800	/**
4801	* Macro for calling iemCImplRaiseInvalidOpcode() for decode/static \#UDs.
4802	*
4803	* This is for things that will _always_ decode to an \#UD, taking the
4804	* recompiler into consideration and everything.
4805	*
4806	* @return Strict VBox status code.
4807	*/
4808	#define IEMOP_RAISE_INVALID_OPCODE_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, iemCImplRaiseInvalidOpcode)
4809
4810	/**
4811	* Macro for calling iemCImplRaiseInvalidOpcode() for runtime-style \#UDs.
4812	*
4813	* Using this macro means you've got _buggy_ _code_ and are doing things that
4814	* belongs exclusively in IEMAllCImpl.cpp during decoding.
4815	*
4816	* @return Strict VBox status code.
4817	* @see IEMOP_RAISE_INVALID_OPCODE_RET
4818	*/
4819	#define IEMOP_RAISE_INVALID_OPCODE_RUNTIME_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, iemCImplRaiseInvalidOpcode)
4820
4821	/** @} */
4822
4823	/** @name Register Access.
4824	* @{ */
4825	VBOXSTRICTRC iemRegRipRelativeJumpS8AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int8_t offNextInstr,
4826	IEMMODE enmEffOpSize) RT_NOEXCEPT;
4827	VBOXSTRICTRC iemRegRipRelativeJumpS16AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int16_t offNextInstr) RT_NOEXCEPT;
4828	VBOXSTRICTRC iemRegRipRelativeJumpS32AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int32_t offNextInstr,
4829	IEMMODE enmEffOpSize) RT_NOEXCEPT;
4830	VBOXSTRICTRC iemRegRipJumpU16AndFinishClearningRF(PVMCPUCC pVCpu, uint16_t uNewRip) RT_NOEXCEPT;
4831	VBOXSTRICTRC iemRegRipJumpU32AndFinishClearningRF(PVMCPUCC pVCpu, uint32_t uNewRip) RT_NOEXCEPT;
4832	VBOXSTRICTRC iemRegRipJumpU64AndFinishClearningRF(PVMCPUCC pVCpu, uint64_t uNewRip) RT_NOEXCEPT;
4833	/** @} */
4834
4835	/** @name FPU access and helpers.
4836	* @{ */
4837	void iemFpuPushResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
4838	void iemFpuPushResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4839	void iemFpuPushResultTwo(PVMCPUCC pVCpu, PIEMFPURESULTTWO pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
4840	void iemFpuStoreResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
4841	void iemFpuStoreResultThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
4842	void iemFpuStoreResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
4843	uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4844	void iemFpuStoreResultWithMemOpThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
4845	uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4846	void iemFpuUpdateOpcodeAndIp(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
4847	void iemFpuUpdateFSW(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
4848	void iemFpuUpdateFSWThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
4849	void iemFpuUpdateFSWWithMemOp(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4850	void iemFpuUpdateFSWThenPopPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
4851	void iemFpuUpdateFSWWithMemOpThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4852	void iemFpuStackUnderflow(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
4853	void iemFpuStackUnderflowWithMemOp(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4854	void iemFpuStackUnderflowThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
4855	void iemFpuStackUnderflowWithMemOpThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4856	void iemFpuStackUnderflowThenPopPop(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
4857	void iemFpuStackPushUnderflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
4858	void iemFpuStackPushUnderflowTwo(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
4859	void iemFpuStackPushOverflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
4860	void iemFpuStackPushOverflowWithMemOp(PVMCPUCC pVCpu, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4861	/** @} */
4862
4863	/** @name SSE+AVX SIMD access and helpers.
4864	* @{ */
4865	void iemSseStoreResult(PVMCPUCC pVCpu, PCIEMSSERESULT pResult, uint8_t iXmmReg) RT_NOEXCEPT;
4866	void iemSseUpdateMxcsr(PVMCPUCC pVCpu, uint32_t fMxcsr) RT_NOEXCEPT;
4867	/** @} */
4868
4869	/** @name Memory access.
4870	* @{ */
4871
4872	/** Report a \#GP instead of \#AC and do not restrict to ring-3 */
4873	#define IEM_MEMMAP_F_ALIGN_GP RT_BIT_32(16)
4874	/** SSE access that should report a \#GP instead of \#AC, unless MXCSR.MM=1
4875	* when it works like normal \#AC. Always used with IEM_MEMMAP_F_ALIGN_GP. */
4876	#define IEM_MEMMAP_F_ALIGN_SSE RT_BIT_32(17)
4877	/** If \#AC is applicable, raise it. Always used with IEM_MEMMAP_F_ALIGN_GP.
4878	* Users include FXSAVE & FXRSTOR. */
4879	#define IEM_MEMMAP_F_ALIGN_GP_OR_AC RT_BIT_32(18)
4880
4881	VBOXSTRICTRC iemMemMap(PVMCPUCC pVCpu, void **ppvMem, size_t cbMem, uint8_t iSegReg, RTGCPTR GCPtrMem,
4882	uint32_t fAccess, uint32_t uAlignCtl) RT_NOEXCEPT;
4883	VBOXSTRICTRC iemMemCommitAndUnmap(PVMCPUCC pVCpu, void *pvMem, uint32_t fAccess) RT_NOEXCEPT;
4884	#ifndef IN_RING3
4885	VBOXSTRICTRC iemMemCommitAndUnmapPostponeTroubleToR3(PVMCPUCC pVCpu, void *pvMem, uint32_t fAccess) RT_NOEXCEPT;
4886	#endif
4887	void iemMemRollback(PVMCPUCC pVCpu) RT_NOEXCEPT;
4888	VBOXSTRICTRC iemMemApplySegment(PVMCPUCC pVCpu, uint32_t fAccess, uint8_t iSegReg, size_t cbMem, PRTGCPTR pGCPtrMem) RT_NOEXCEPT;
4889	VBOXSTRICTRC iemMemMarkSelDescAccessed(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
4890	VBOXSTRICTRC iemMemPageTranslateAndCheckAccess(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t cbAccess, uint32_t fAccess, PRTGCPHYS pGCPhysMem) RT_NOEXCEPT;
4891
4892	void iemOpcodeFlushLight(PVMCPUCC pVCpu, uint8_t cbInstr);
4893	void iemOpcodeFlushHeavy(PVMCPUCC pVCpu, uint8_t cbInstr);
4894	#ifdef IEM_WITH_CODE_TLB
4895	void iemOpcodeFetchBytesJmp(PVMCPUCC pVCpu, size_t cbDst, void *pvDst) IEM_NOEXCEPT_MAY_LONGJMP;
4896	#else
4897	VBOXSTRICTRC iemOpcodeFetchMoreBytes(PVMCPUCC pVCpu, size_t cbMin) RT_NOEXCEPT;
4898	#endif
4899	#ifdef IEM_WITH_SETJMP
4900	uint8_t iemOpcodeGetNextU8SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4901	uint16_t iemOpcodeGetNextU16SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4902	uint32_t iemOpcodeGetNextU32SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4903	uint64_t iemOpcodeGetNextU64SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4904	#else
4905	VBOXSTRICTRC iemOpcodeGetNextU8Slow(PVMCPUCC pVCpu, uint8_t *pb) RT_NOEXCEPT;
4906	VBOXSTRICTRC iemOpcodeGetNextS8SxU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
4907	VBOXSTRICTRC iemOpcodeGetNextS8SxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
4908	VBOXSTRICTRC iemOpcodeGetNextS8SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
4909	VBOXSTRICTRC iemOpcodeGetNextU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
4910	VBOXSTRICTRC iemOpcodeGetNextU16ZxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
4911	VBOXSTRICTRC iemOpcodeGetNextU16ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
4912	VBOXSTRICTRC iemOpcodeGetNextU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
4913	VBOXSTRICTRC iemOpcodeGetNextU32ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
4914	VBOXSTRICTRC iemOpcodeGetNextS32SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
4915	VBOXSTRICTRC iemOpcodeGetNextU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
4916	#endif
4917
4918	VBOXSTRICTRC iemMemFetchDataU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4919	VBOXSTRICTRC iemMemFetchDataU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4920	VBOXSTRICTRC iemMemFetchDataU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4921	VBOXSTRICTRC iemMemFetchDataU32_ZX_U64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4922	VBOXSTRICTRC iemMemFetchDataU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4923	VBOXSTRICTRC iemMemFetchDataU64AlignedU128(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4924	VBOXSTRICTRC iemMemFetchDataR80(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4925	VBOXSTRICTRC iemMemFetchDataD80(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4926	VBOXSTRICTRC iemMemFetchDataU128(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4927	VBOXSTRICTRC iemMemFetchDataU128AlignedSse(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4928	VBOXSTRICTRC iemMemFetchDataU256(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4929	VBOXSTRICTRC iemMemFetchDataU256AlignedSse(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4930	VBOXSTRICTRC iemMemFetchDataXdtr(PVMCPUCC pVCpu, uint16_t *pcbLimit, PRTGCPTR pGCPtrBase, uint8_t iSegReg,
4931	RTGCPTR GCPtrMem, IEMMODE enmOpSize) RT_NOEXCEPT;
4932	#ifdef IEM_WITH_SETJMP
4933	uint8_t iemMemFetchDataU8SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4934	uint16_t iemMemFetchDataU16SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4935	uint32_t iemMemFetchDataU32SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4936	uint32_t iemMemFlatFetchDataU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4937	uint64_t iemMemFetchDataU64SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4938	uint64_t iemMemFetchDataU64AlignedU128SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4939	void iemMemFetchDataR80SafeJmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4940	void iemMemFetchDataD80SafeJmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4941	void iemMemFetchDataU128SafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4942	void iemMemFetchDataU128AlignedSseSafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4943	void iemMemFetchDataU256SafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4944	void iemMemFetchDataU256AlignedSseSafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4945	# if 0 /* these are inlined now */
4946	uint8_t iemMemFetchDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4947	uint16_t iemMemFetchDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4948	uint32_t iemMemFetchDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4949	uint32_t iemMemFlatFetchDataU32Jmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4950	uint64_t iemMemFetchDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4951	uint64_t iemMemFetchDataU64AlignedU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4952	# endif
4953	void iemMemFetchDataR80Jmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4954	void iemMemFetchDataD80Jmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4955	void iemMemFetchDataU128Jmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4956	void iemMemFetchDataU128AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4957	void iemMemFetchDataU256Jmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4958	void iemMemFetchDataU256AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4959	#endif
4960
4961	VBOXSTRICTRC iemMemFetchSysU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4962	VBOXSTRICTRC iemMemFetchSysU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4963	VBOXSTRICTRC iemMemFetchSysU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4964	VBOXSTRICTRC iemMemFetchSysU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4965	VBOXSTRICTRC iemMemFetchSelDesc(PVMCPUCC pVCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt) RT_NOEXCEPT;
4966
4967	VBOXSTRICTRC iemMemStoreDataU8(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) RT_NOEXCEPT;
4968	VBOXSTRICTRC iemMemStoreDataU16(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) RT_NOEXCEPT;
4969	VBOXSTRICTRC iemMemStoreDataU32(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) RT_NOEXCEPT;
4970	VBOXSTRICTRC iemMemStoreDataU64(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) RT_NOEXCEPT;
4971	VBOXSTRICTRC iemMemStoreDataU128(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
4972	VBOXSTRICTRC iemMemStoreDataU128AlignedSse(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
4973	VBOXSTRICTRC iemMemStoreDataU256(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
4974	VBOXSTRICTRC iemMemStoreDataU256AlignedAvx(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
4975	VBOXSTRICTRC iemMemStoreDataXdtr(PVMCPUCC pVCpu, uint16_t cbLimit, RTGCPTR GCPtrBase, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4976	#ifdef IEM_WITH_SETJMP
4977	void iemMemStoreDataU8SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
4978	void iemMemStoreDataU16SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
4979	void iemMemStoreDataU32SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
4980	void iemMemStoreDataU64SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
4981	void iemMemStoreDataU128SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
4982	void iemMemStoreDataU128AlignedSseSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
4983	void iemMemStoreDataU256SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
4984	void iemMemStoreDataU256AlignedAvxSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
4985	#if 0
4986	void iemMemStoreDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
4987	void iemMemStoreDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
4988	void iemMemStoreDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
4989	void iemMemStoreDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
4990	#endif
4991	void iemMemStoreDataU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
4992	void iemMemStoreDataU128AlignedSseJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
4993	void iemMemStoreDataU256Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
4994	void iemMemStoreDataU256AlignedAvxJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
4995	#endif
4996
4997	#ifdef IEM_WITH_SETJMP
4998	uint8_t iemMemMapDataU8RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4999	uint8_t iemMemMapDataU8WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5000	uint8_t const iemMemMapDataU8RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5001	uint16_t iemMemMapDataU16RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5002	uint16_t iemMemMapDataU16WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5003	uint16_t const iemMemMapDataU16RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5004	uint32_t iemMemMapDataU32RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5005	uint32_t iemMemMapDataU32WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5006	uint32_t const iemMemMapDataU32RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5007	uint64_t iemMemMapDataU64RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5008	uint64_t iemMemMapDataU64WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5009	uint64_t const iemMemMapDataU64RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5010
5011	void iemMemCommitAndUnmapRwSafeJmp(PVMCPUCC pVCpu, void *pvMem, uint8_t bMapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5012	void iemMemCommitAndUnmapWoSafeJmp(PVMCPUCC pVCpu, void *pvMem, uint8_t bMapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5013	void iemMemCommitAndUnmapRoSafeJmp(PVMCPUCC pVCpu, const void *pvMem, uint8_t bMapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5014	#endif
5015
5016	VBOXSTRICTRC iemMemStackPushBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
5017	void *ppvMem, uint64_t puNewRsp) RT_NOEXCEPT;
5018	VBOXSTRICTRC iemMemStackPushCommitSpecial(PVMCPUCC pVCpu, void *pvMem, uint64_t uNewRsp) RT_NOEXCEPT;
5019	VBOXSTRICTRC iemMemStackPushU16(PVMCPUCC pVCpu, uint16_t u16Value) RT_NOEXCEPT;
5020	VBOXSTRICTRC iemMemStackPushU32(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
5021	VBOXSTRICTRC iemMemStackPushU64(PVMCPUCC pVCpu, uint64_t u64Value) RT_NOEXCEPT;
5022	VBOXSTRICTRC iemMemStackPushU16Ex(PVMCPUCC pVCpu, uint16_t u16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5023	VBOXSTRICTRC iemMemStackPushU32Ex(PVMCPUCC pVCpu, uint32_t u32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5024	VBOXSTRICTRC iemMemStackPushU64Ex(PVMCPUCC pVCpu, uint64_t u64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5025	VBOXSTRICTRC iemMemStackPushU32SReg(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
5026	VBOXSTRICTRC iemMemStackPopBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
5027	void const *ppvMem, uint64_t puNewRsp) RT_NOEXCEPT;
5028	VBOXSTRICTRC iemMemStackPopContinueSpecial(PVMCPUCC pVCpu, size_t off, size_t cbMem,
5029	void const **ppvMem, uint64_t uCurNewRsp) RT_NOEXCEPT;
5030	VBOXSTRICTRC iemMemStackPopDoneSpecial(PVMCPUCC pVCpu, void const *pvMem) RT_NOEXCEPT;
5031	VBOXSTRICTRC iemMemStackPopU16(PVMCPUCC pVCpu, uint16_t *pu16Value) RT_NOEXCEPT;
5032	VBOXSTRICTRC iemMemStackPopU32(PVMCPUCC pVCpu, uint32_t *pu32Value) RT_NOEXCEPT;
5033	VBOXSTRICTRC iemMemStackPopU64(PVMCPUCC pVCpu, uint64_t *pu64Value) RT_NOEXCEPT;
5034	VBOXSTRICTRC iemMemStackPopU16Ex(PVMCPUCC pVCpu, uint16_t *pu16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5035	VBOXSTRICTRC iemMemStackPopU32Ex(PVMCPUCC pVCpu, uint32_t *pu32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5036	VBOXSTRICTRC iemMemStackPopU64Ex(PVMCPUCC pVCpu, uint64_t *pu64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5037
5038	#ifdef IEM_WITH_SETJMP
5039	void iemMemStackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5040	void iemMemStackPushU32SafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5041	void iemMemStackPushU32SRegSafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5042	void iemMemStackPushU64SafeJmp(PVMCPUCC pVCpu, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5043	uint16_t iemMemStackPopU16SafeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5044	uint32_t iemMemStackPopU32SafeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5045	uint64_t iemMemStackPopU64SafeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5046
5047	void iemMemFlat32StackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5048	void iemMemFlat32StackPushU32SafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5049	void iemMemFlat32StackPushU32SRegSafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5050	uint16_t iemMemFlat32StackPopU16SafeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5051	uint32_t iemMemFlat32StackPopU32SafeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5052
5053	void iemMemFlat64StackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5054	void iemMemFlat64StackPushU64SafeJmp(PVMCPUCC pVCpu, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5055	uint16_t iemMemFlat64StackPopU16SafeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5056	uint64_t iemMemFlat64StackPopU64SafeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5057	#endif
5058
5059	/** @} */
5060
5061	/** @name IEMAllCImpl.cpp
5062	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/'
5063	* @{ */
5064	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem16, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5065	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem32, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5066	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem64, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5067	IEM_CIMPL_PROTO_0(iemCImpl_popa_16);
5068	IEM_CIMPL_PROTO_0(iemCImpl_popa_32);
5069	IEM_CIMPL_PROTO_0(iemCImpl_pusha_16);
5070	IEM_CIMPL_PROTO_0(iemCImpl_pusha_32);
5071	IEM_CIMPL_PROTO_1(iemCImpl_pushf, IEMMODE, enmEffOpSize);
5072	IEM_CIMPL_PROTO_1(iemCImpl_popf, IEMMODE, enmEffOpSize);
5073	IEM_CIMPL_PROTO_1(iemCImpl_call_16, uint16_t, uNewPC);
5074	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_16, int16_t, offDisp);
5075	IEM_CIMPL_PROTO_1(iemCImpl_call_32, uint32_t, uNewPC);
5076	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_32, int32_t, offDisp);
5077	IEM_CIMPL_PROTO_1(iemCImpl_call_64, uint64_t, uNewPC);
5078	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_64, int64_t, offDisp);
5079	IEM_CIMPL_PROTO_3(iemCImpl_FarJmp, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
5080	IEM_CIMPL_PROTO_3(iemCImpl_callf, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
5081	typedef IEM_CIMPL_DECL_TYPE_3(FNIEMCIMPLFARBRANCH, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
5082	typedef FNIEMCIMPLFARBRANCH *PFNIEMCIMPLFARBRANCH;
5083	IEM_CIMPL_PROTO_2(iemCImpl_retf, IEMMODE, enmEffOpSize, uint16_t, cbPop);
5084	IEM_CIMPL_PROTO_0(iemCImpl_retn_16);
5085	IEM_CIMPL_PROTO_0(iemCImpl_retn_32);
5086	IEM_CIMPL_PROTO_0(iemCImpl_retn_64);
5087	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_16, uint16_t, cbPop);
5088	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_32, uint16_t, cbPop);
5089	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_64, uint16_t, cbPop);
5090	IEM_CIMPL_PROTO_3(iemCImpl_enter, IEMMODE, enmEffOpSize, uint16_t, cbFrame, uint8_t, cParameters);
5091	IEM_CIMPL_PROTO_1(iemCImpl_leave, IEMMODE, enmEffOpSize);
5092	IEM_CIMPL_PROTO_2(iemCImpl_int, uint8_t, u8Int, IEMINT, enmInt);
5093	IEM_CIMPL_PROTO_1(iemCImpl_iret_real_v8086, IEMMODE, enmEffOpSize);
5094	IEM_CIMPL_PROTO_4(iemCImpl_iret_prot_v8086, uint32_t, uNewEip, uint16_t, uNewCs, uint32_t, uNewFlags, uint64_t, uNewRsp);
5095	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot_NestedTask, IEMMODE, enmEffOpSize);
5096	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot, IEMMODE, enmEffOpSize);
5097	IEM_CIMPL_PROTO_1(iemCImpl_iret_64bit, IEMMODE, enmEffOpSize);
5098	IEM_CIMPL_PROTO_1(iemCImpl_iret, IEMMODE, enmEffOpSize);
5099	IEM_CIMPL_PROTO_0(iemCImpl_loadall286);
5100	IEM_CIMPL_PROTO_0(iemCImpl_syscall);
5101	IEM_CIMPL_PROTO_1(iemCImpl_sysret, IEMMODE, enmEffOpSize);
5102	IEM_CIMPL_PROTO_0(iemCImpl_sysenter);
5103	IEM_CIMPL_PROTO_1(iemCImpl_sysexit, IEMMODE, enmEffOpSize);
5104	IEM_CIMPL_PROTO_2(iemCImpl_LoadSReg, uint8_t, iSegReg, uint16_t, uSel);
5105	IEM_CIMPL_PROTO_2(iemCImpl_load_SReg, uint8_t, iSegReg, uint16_t, uSel);
5106	IEM_CIMPL_PROTO_2(iemCImpl_pop_Sreg, uint8_t, iSegReg, IEMMODE, enmEffOpSize);
5107	IEM_CIMPL_PROTO_5(iemCImpl_load_SReg_Greg, uint16_t, uSel, uint64_t, offSeg, uint8_t, iSegReg, uint8_t, iGReg, IEMMODE, enmEffOpSize);
5108	IEM_CIMPL_PROTO_2(iemCImpl_VerX, uint16_t, uSel, bool, fWrite);
5109	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u64, uint64_t *, pu64Dst, uint16_t, uSel, bool, fIsLar);
5110	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u16, uint16_t *, pu16Dst, uint16_t, uSel, bool, fIsLar);
5111	IEM_CIMPL_PROTO_3(iemCImpl_lgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
5112	IEM_CIMPL_PROTO_2(iemCImpl_sgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5113	IEM_CIMPL_PROTO_3(iemCImpl_lidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
5114	IEM_CIMPL_PROTO_2(iemCImpl_sidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5115	IEM_CIMPL_PROTO_1(iemCImpl_lldt, uint16_t, uNewLdt);
5116	IEM_CIMPL_PROTO_2(iemCImpl_sldt_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
5117	IEM_CIMPL_PROTO_2(iemCImpl_sldt_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5118	IEM_CIMPL_PROTO_1(iemCImpl_ltr, uint16_t, uNewTr);
5119	IEM_CIMPL_PROTO_2(iemCImpl_str_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
5120	IEM_CIMPL_PROTO_2(iemCImpl_str_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5121	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Cd, uint8_t, iGReg, uint8_t, iCrReg);
5122	IEM_CIMPL_PROTO_2(iemCImpl_smsw_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
5123	IEM_CIMPL_PROTO_2(iemCImpl_smsw_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5124	IEM_CIMPL_PROTO_4(iemCImpl_load_CrX, uint8_t, iCrReg, uint64_t, uNewCrX, IEMACCESSCRX, enmAccessCrX, uint8_t, iGReg);
5125	IEM_CIMPL_PROTO_2(iemCImpl_mov_Cd_Rd, uint8_t, iCrReg, uint8_t, iGReg);
5126	IEM_CIMPL_PROTO_2(iemCImpl_lmsw, uint16_t, u16NewMsw, RTGCPTR, GCPtrEffDst);
5127	IEM_CIMPL_PROTO_0(iemCImpl_clts);
5128	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Dd, uint8_t, iGReg, uint8_t, iDrReg);
5129	IEM_CIMPL_PROTO_2(iemCImpl_mov_Dd_Rd, uint8_t, iDrReg, uint8_t, iGReg);
5130	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Td, uint8_t, iGReg, uint8_t, iTrReg);
5131	IEM_CIMPL_PROTO_2(iemCImpl_mov_Td_Rd, uint8_t, iTrReg, uint8_t, iGReg);
5132	IEM_CIMPL_PROTO_1(iemCImpl_invlpg, RTGCPTR, GCPtrPage);
5133	IEM_CIMPL_PROTO_3(iemCImpl_invpcid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvpcidDesc, uint64_t, uInvpcidType);
5134	IEM_CIMPL_PROTO_0(iemCImpl_invd);
5135	IEM_CIMPL_PROTO_0(iemCImpl_wbinvd);
5136	IEM_CIMPL_PROTO_0(iemCImpl_rsm);
5137	IEM_CIMPL_PROTO_0(iemCImpl_rdtsc);
5138	IEM_CIMPL_PROTO_0(iemCImpl_rdtscp);
5139	IEM_CIMPL_PROTO_0(iemCImpl_rdpmc);
5140	IEM_CIMPL_PROTO_0(iemCImpl_rdmsr);
5141	IEM_CIMPL_PROTO_0(iemCImpl_wrmsr);
5142	IEM_CIMPL_PROTO_3(iemCImpl_in, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
5143	IEM_CIMPL_PROTO_2(iemCImpl_in_eAX_DX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
5144	IEM_CIMPL_PROTO_3(iemCImpl_out, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
5145	IEM_CIMPL_PROTO_2(iemCImpl_out_DX_eAX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
5146	IEM_CIMPL_PROTO_0(iemCImpl_cli);
5147	IEM_CIMPL_PROTO_0(iemCImpl_sti);
5148	IEM_CIMPL_PROTO_0(iemCImpl_hlt);
5149	IEM_CIMPL_PROTO_1(iemCImpl_monitor, uint8_t, iEffSeg);
5150	IEM_CIMPL_PROTO_0(iemCImpl_mwait);
5151	IEM_CIMPL_PROTO_0(iemCImpl_swapgs);
5152	IEM_CIMPL_PROTO_0(iemCImpl_cpuid);
5153	IEM_CIMPL_PROTO_1(iemCImpl_aad, uint8_t, bImm);
5154	IEM_CIMPL_PROTO_1(iemCImpl_aam, uint8_t, bImm);
5155	IEM_CIMPL_PROTO_0(iemCImpl_daa);
5156	IEM_CIMPL_PROTO_0(iemCImpl_das);
5157	IEM_CIMPL_PROTO_0(iemCImpl_aaa);
5158	IEM_CIMPL_PROTO_0(iemCImpl_aas);
5159	IEM_CIMPL_PROTO_3(iemCImpl_bound_16, int16_t, idxArray, int16_t, idxLowerBound, int16_t, idxUpperBound);
5160	IEM_CIMPL_PROTO_3(iemCImpl_bound_32, int32_t, idxArray, int32_t, idxLowerBound, int32_t, idxUpperBound);
5161	IEM_CIMPL_PROTO_0(iemCImpl_xgetbv);
5162	IEM_CIMPL_PROTO_0(iemCImpl_xsetbv);
5163	IEM_CIMPL_PROTO_4(iemCImpl_cmpxchg16b_fallback_rendezvous, PRTUINT128U, pu128Dst, PRTUINT128U, pu128RaxRdx,
5164	PRTUINT128U, pu128RbxRcx, uint32_t *, pEFlags);
5165	IEM_CIMPL_PROTO_2(iemCImpl_clflush_clflushopt, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5166	IEM_CIMPL_PROTO_1(iemCImpl_finit, bool, fCheckXcpts);
5167	IEM_CIMPL_PROTO_3(iemCImpl_fxsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5168	IEM_CIMPL_PROTO_3(iemCImpl_fxrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5169	IEM_CIMPL_PROTO_3(iemCImpl_xsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5170	IEM_CIMPL_PROTO_3(iemCImpl_xrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5171	IEM_CIMPL_PROTO_2(iemCImpl_stmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5172	IEM_CIMPL_PROTO_2(iemCImpl_vstmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5173	IEM_CIMPL_PROTO_2(iemCImpl_ldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5174	IEM_CIMPL_PROTO_3(iemCImpl_fnstenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5175	IEM_CIMPL_PROTO_3(iemCImpl_fnsave, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5176	IEM_CIMPL_PROTO_3(iemCImpl_fldenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
5177	IEM_CIMPL_PROTO_3(iemCImpl_frstor, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
5178	IEM_CIMPL_PROTO_1(iemCImpl_fldcw, uint16_t, u16Fcw);
5179	IEM_CIMPL_PROTO_2(iemCImpl_fxch_underflow, uint8_t, iStReg, uint16_t, uFpuOpcode);
5180	IEM_CIMPL_PROTO_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, bool, fUCmp, uint32_t, uPopAndFpuOpcode);
5181	IEM_CIMPL_PROTO_2(iemCImpl_rdseed, uint8_t, iReg, IEMMODE, enmEffOpSize);
5182	IEM_CIMPL_PROTO_2(iemCImpl_rdrand, uint8_t, iReg, IEMMODE, enmEffOpSize);
5183	/** @} */
5184
5185	/** @name IEMAllCImplStrInstr.cpp.h
5186	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/' -e 's/RT_CONCAT4(//' \
5187	* -e 's/,ADDR_SIZE)/64/g' -e 's/,OP_SIZE,/64/g' -e 's/,OP_rAX,/rax/g' IEMAllCImplStrInstr.cpp.h
5188	* @{ */
5189	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr16, uint8_t, iEffSeg);
5190	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr16, uint8_t, iEffSeg);
5191	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m16);
5192	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m16);
5193	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr16, uint8_t, iEffSeg);
5194	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m16);
5195	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m16, int8_t, iEffSeg);
5196	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr16, bool, fIoChecked);
5197	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr16, bool, fIoChecked);
5198	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5199	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5200
5201	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr16, uint8_t, iEffSeg);
5202	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr16, uint8_t, iEffSeg);
5203	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m16);
5204	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m16);
5205	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr16, uint8_t, iEffSeg);
5206	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m16);
5207	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m16, int8_t, iEffSeg);
5208	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr16, bool, fIoChecked);
5209	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr16, bool, fIoChecked);
5210	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5211	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5212
5213	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr16, uint8_t, iEffSeg);
5214	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr16, uint8_t, iEffSeg);
5215	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m16);
5216	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m16);
5217	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr16, uint8_t, iEffSeg);
5218	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m16);
5219	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m16, int8_t, iEffSeg);
5220	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr16, bool, fIoChecked);
5221	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr16, bool, fIoChecked);
5222	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5223	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5224
5225
5226	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr32, uint8_t, iEffSeg);
5227	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr32, uint8_t, iEffSeg);
5228	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m32);
5229	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m32);
5230	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr32, uint8_t, iEffSeg);
5231	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m32);
5232	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m32, int8_t, iEffSeg);
5233	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr32, bool, fIoChecked);
5234	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr32, bool, fIoChecked);
5235	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5236	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5237
5238	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr32, uint8_t, iEffSeg);
5239	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr32, uint8_t, iEffSeg);
5240	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m32);
5241	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m32);
5242	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr32, uint8_t, iEffSeg);
5243	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m32);
5244	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m32, int8_t, iEffSeg);
5245	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr32, bool, fIoChecked);
5246	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr32, bool, fIoChecked);
5247	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5248	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5249
5250	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr32, uint8_t, iEffSeg);
5251	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr32, uint8_t, iEffSeg);
5252	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m32);
5253	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m32);
5254	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr32, uint8_t, iEffSeg);
5255	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m32);
5256	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m32, int8_t, iEffSeg);
5257	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr32, bool, fIoChecked);
5258	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr32, bool, fIoChecked);
5259	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5260	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5261
5262	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr32, uint8_t, iEffSeg);
5263	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr32, uint8_t, iEffSeg);
5264	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m32);
5265	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m32);
5266	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr32, uint8_t, iEffSeg);
5267	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m32);
5268	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m32, int8_t, iEffSeg);
5269	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr32, bool, fIoChecked);
5270	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr32, bool, fIoChecked);
5271	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5272	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5273
5274
5275	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr64, uint8_t, iEffSeg);
5276	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr64, uint8_t, iEffSeg);
5277	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m64);
5278	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m64);
5279	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr64, uint8_t, iEffSeg);
5280	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m64);
5281	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m64, int8_t, iEffSeg);
5282	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr64, bool, fIoChecked);
5283	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr64, bool, fIoChecked);
5284	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5285	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5286
5287	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr64, uint8_t, iEffSeg);
5288	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr64, uint8_t, iEffSeg);
5289	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m64);
5290	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m64);
5291	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr64, uint8_t, iEffSeg);
5292	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m64);
5293	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m64, int8_t, iEffSeg);
5294	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr64, bool, fIoChecked);
5295	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr64, bool, fIoChecked);
5296	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5297	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5298
5299	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr64, uint8_t, iEffSeg);
5300	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr64, uint8_t, iEffSeg);
5301	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m64);
5302	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m64);
5303	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr64, uint8_t, iEffSeg);
5304	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m64);
5305	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m64, int8_t, iEffSeg);
5306	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr64, bool, fIoChecked);
5307	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr64, bool, fIoChecked);
5308	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5309	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5310
5311	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr64, uint8_t, iEffSeg);
5312	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr64, uint8_t, iEffSeg);
5313	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m64);
5314	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m64);
5315	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr64, uint8_t, iEffSeg);
5316	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m64);
5317	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m64, int8_t, iEffSeg);
5318	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr64, bool, fIoChecked);
5319	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr64, bool, fIoChecked);
5320	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5321	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5322	/** @} */
5323
5324	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5325	VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT;
5326	VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT;
5327	VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT;
5328	VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT;
5329	VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT;
5330	VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
5331	VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALK pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT;
5332	VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT;
5333	VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT;
5334	VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
5335	bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT;
5336	VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
5337	bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT;
5338	VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5339	VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5340	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5341	VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5342	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5343	VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5344	VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT;
5345	VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
5346	RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT;
5347	VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT;
5348	VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT;
5349	VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT;
5350	uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT;
5351	void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT;
5352	VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
5353	uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT;
5354	bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT;
5355	IEM_CIMPL_PROTO_0(iemCImpl_vmxoff);
5356	IEM_CIMPL_PROTO_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon);
5357	IEM_CIMPL_PROTO_0(iemCImpl_vmlaunch);
5358	IEM_CIMPL_PROTO_0(iemCImpl_vmresume);
5359	IEM_CIMPL_PROTO_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
5360	IEM_CIMPL_PROTO_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
5361	IEM_CIMPL_PROTO_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
5362	IEM_CIMPL_PROTO_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField);
5363	IEM_CIMPL_PROTO_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField);
5364	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField);
5365	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg32, uint64_t *, pu32Dst, uint32_t, u32VmcsField);
5366	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField);
5367	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField);
5368	IEM_CIMPL_PROTO_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType);
5369	IEM_CIMPL_PROTO_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType);
5370	IEM_CIMPL_PROTO_0(iemCImpl_vmx_pause);
5371	#endif
5372
5373	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5374	VBOXSTRICTRC iemSvmVmexit(PVMCPUCC pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2) RT_NOEXCEPT;
5375	VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr, uint64_t uCr2) RT_NOEXCEPT;
5376	VBOXSTRICTRC iemSvmHandleIOIntercept(PVMCPUCC pVCpu, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
5377	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, uint8_t cbInstr) RT_NOEXCEPT;
5378	VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPUCC pVCpu, uint32_t idMsr, bool fWrite, uint8_t cbInstr) RT_NOEXCEPT;
5379	IEM_CIMPL_PROTO_0(iemCImpl_vmrun);
5380	IEM_CIMPL_PROTO_0(iemCImpl_vmload);
5381	IEM_CIMPL_PROTO_0(iemCImpl_vmsave);
5382	IEM_CIMPL_PROTO_0(iemCImpl_clgi);
5383	IEM_CIMPL_PROTO_0(iemCImpl_stgi);
5384	IEM_CIMPL_PROTO_0(iemCImpl_invlpga);
5385	IEM_CIMPL_PROTO_0(iemCImpl_skinit);
5386	IEM_CIMPL_PROTO_0(iemCImpl_svm_pause);
5387	#endif
5388
5389	IEM_CIMPL_PROTO_0(iemCImpl_vmcall); /* vmx */
5390	IEM_CIMPL_PROTO_0(iemCImpl_vmmcall); /* svm */
5391	IEM_CIMPL_PROTO_1(iemCImpl_Hypercall, uint16_t, uDisOpcode); /* both */
5392
5393	extern const PFNIEMOP g_apfnIemInterpretOnlyOneByteMap[256];
5394	extern const PFNIEMOP g_apfnIemInterpretOnlyTwoByteMap[1024];
5395	extern const PFNIEMOP g_apfnIemInterpretOnlyThreeByte0f3a[1024];
5396	extern const PFNIEMOP g_apfnIemInterpretOnlyThreeByte0f38[1024];
5397	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap1[1024];
5398	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap2[1024];
5399	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap3[1024];
5400
5401	/*
5402	* Recompiler related stuff.
5403	*/
5404	extern const PFNIEMOP g_apfnIemThreadedRecompilerOneByteMap[256];
5405	extern const PFNIEMOP g_apfnIemThreadedRecompilerTwoByteMap[1024];
5406	extern const PFNIEMOP g_apfnIemThreadedRecompilerThreeByte0f3a[1024];
5407	extern const PFNIEMOP g_apfnIemThreadedRecompilerThreeByte0f38[1024];
5408	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap1[1024];
5409	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap2[1024];
5410	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap3[1024];
5411
5412	DECLCALLBACK(int) iemTbInit(PVMCC pVM, uint32_t cInitialTbs, uint32_t cMaxTbs,
5413	uint64_t cbInitialExec, uint64_t cbMaxExec, uint32_t cbChunkExec);
5414	void iemThreadedTbObsolete(PVMCPUCC pVCpu, PIEMTB pTb, bool fSafeToFree);
5415	void iemTbAllocatorProcessDelayedFrees(PVMCPU pVCpu, PIEMTBALLOCATOR pTbAllocator);
5416
5417
5418	/** @todo FNIEMTHREADEDFUNC and friends may need more work... */
5419	#if defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
5420	typedef VBOXSTRICTRC /__attribute__((__nothrow__))/ FNIEMTHREADEDFUNC(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
5421	typedef FNIEMTHREADEDFUNC *PFNIEMTHREADEDFUNC;
5422	# define IEM_DECL_IEMTHREADEDFUNC_DEF(a_Name) \
5423	VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2)
5424	# define IEM_DECL_IEMTHREADEDFUNC_PROTO(a_Name) \
5425	VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2)
5426
5427	#else
5428	typedef VBOXSTRICTRC (FNIEMTHREADEDFUNC)(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
5429	typedef FNIEMTHREADEDFUNC *PFNIEMTHREADEDFUNC;
5430	# define IEM_DECL_IEMTHREADEDFUNC_DEF(a_Name) \
5431	VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2) IEM_NOEXCEPT_MAY_LONGJMP
5432	# define IEM_DECL_IEMTHREADEDFUNC_PROTO(a_Name) \
5433	VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2) IEM_NOEXCEPT_MAY_LONGJMP
5434	#endif
5435
5436
5437	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_DeferToCImpl0);
5438
5439	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckIrq);
5440	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckMode);
5441	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckHwInstrBps);
5442	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLim);
5443
5444	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodes);
5445	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodes);
5446	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesConsiderCsLim);
5447
5448	/* Branching: */
5449	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndPcAndOpcodes);
5450	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckPcAndOpcodes);
5451	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckPcAndOpcodesConsiderCsLim);
5452
5453	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesLoadingTlb);
5454	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesLoadingTlb);
5455	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesLoadingTlbConsiderCsLim);
5456
5457	/* Natural page crossing: */
5458	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesAcrossPageLoadingTlb);
5459	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesAcrossPageLoadingTlb);
5460	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesAcrossPageLoadingTlbConsiderCsLim);
5461
5462	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesOnNextPageLoadingTlb);
5463	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNextPageLoadingTlb);
5464	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNextPageLoadingTlbConsiderCsLim);
5465
5466	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesOnNewPageLoadingTlb);
5467	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNewPageLoadingTlb);
5468	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNewPageLoadingTlbConsiderCsLim);
5469
5470	bool iemThreadedCompileEmitIrqCheckBefore(PVMCPUCC pVCpu, PIEMTB pTb);
5471	bool iemThreadedCompileBeginEmitCallsComplications(PVMCPUCC pVCpu, PIEMTB pTb);
5472
5473	/* Native recompiler public bits: */
5474	PIEMTB iemNativeRecompile(PVMCPUCC pVCpu, PIEMTB pTb);
5475	int iemExecMemAllocatorInit(PVMCPU pVCpu, uint64_t cbMax, uint64_t cbInitial, uint32_t cbChunk);
5476	void iemExecMemAllocatorFree(PVMCPU pVCpu, void *pv, size_t cb);
5477
5478
5479	/** @} */
5480
5481	RT_C_DECLS_END
5482
5483	#endif /* !VMM_INCLUDED_SRC_include_IEMInternal_h */
5484

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source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h@ 101518

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