IEMInternal.h@ 101547

Last change on this file since 101547 was 101547, checked in by vboxsync, 15 months ago
VMM/IEM: More TB disassembly and TB debuginfo. bugref:10371
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1	/* $Id: IEMInternal.h 101547 2023-10-23 00:50:37Z vboxsync $ */
2	/** @file
3	* IEM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2011-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_IEMInternal_h
29	#define VMM_INCLUDED_SRC_include_IEMInternal_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#include <VBox/vmm/cpum.h>
35	#include <VBox/vmm/iem.h>
36	#include <VBox/vmm/pgm.h>
37	#include <VBox/vmm/stam.h>
38	#include <VBox/param.h>
39
40	#include <iprt/setjmp-without-sigmask.h>
41	#include <iprt/list.h>
42
43
44	RT_C_DECLS_BEGIN
45
46
47	/** @defgroup grp_iem_int Internals
48	* @ingroup grp_iem
49	* @internal
50	* @{
51	*/
52
53	/** For expanding symbol in slickedit and other products tagging and
54	* crossreferencing IEM symbols. */
55	#ifndef IEM_STATIC
56	# define IEM_STATIC static
57	#endif
58
59	/** @def IEM_WITH_SETJMP
60	* Enables alternative status code handling using setjmps.
61	*
62	* This adds a bit of expense via the setjmp() call since it saves all the
63	* non-volatile registers. However, it eliminates return code checks and allows
64	* for more optimal return value passing (return regs instead of stack buffer).
65	*/
66	#if defined(DOXYGEN_RUNNING) \|\| defined(RT_OS_WINDOWS) \|\| 1
67	# define IEM_WITH_SETJMP
68	#endif
69
70	/** @def IEM_WITH_THROW_CATCH
71	* Enables using C++ throw/catch as an alternative to setjmp/longjmp in user
72	* mode code when IEM_WITH_SETJMP is in effect.
73	*
74	* With GCC 11.3.1 and code TLB on linux, using throw/catch instead of
75	* setjmp/long resulted in bs2-test-1 running 3.00% faster and all but on test
76	* result value improving by more than 1%. (Best out of three.)
77	*
78	* With Visual C++ 2019 and code TLB on windows, using throw/catch instead of
79	* setjmp/long resulted in bs2-test-1 running 3.68% faster and all but some of
80	* the MMIO and CPUID tests ran noticeably faster. Variation is greater than on
81	* Linux, but it should be quite a bit faster for normal code.
82	*/
83	#if (defined(__cplusplus) && defined(IEM_WITH_SETJMP) && defined(IN_RING3) && (defined(__GNUC__) \|\| defined(_MSC_VER))) \
84	\|\| defined(DOXYGEN_RUNNING)
85	# define IEM_WITH_THROW_CATCH
86	#endif
87
88	/** @def IEM_DO_LONGJMP
89	*
90	* Wrapper around longjmp / throw.
91	*
92	* @param a_pVCpu The CPU handle.
93	* @param a_rc The status code jump back with / throw.
94	*/
95	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
96	# ifdef IEM_WITH_THROW_CATCH
97	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) throw int(a_rc)
98	# else
99	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) longjmp(*(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf), (a_rc))
100	# endif
101	#endif
102
103	/** For use with IEM function that may do a longjmp (when enabled).
104	*
105	* Visual C++ has trouble longjmp'ing from/over functions with the noexcept
106	* attribute. So, we indicate that function that may be part of a longjmp may
107	* throw "exceptions" and that the compiler should definitely not generate and
108	* std::terminate calling unwind code.
109	*
110	* Here is one example of this ending in std::terminate:
111	* @code{.txt}
112	00 00000041`cadfda10 00007ffc`5d5a1f9f ucrtbase!abort+0x4e
113	01 00000041`cadfda40 00007ffc`57af229a ucrtbase!terminate+0x1f
114	02 00000041`cadfda70 00007ffb`eec91030 VCRUNTIME140!__std_terminate+0xa [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\ehhelpers.cpp @ 192]
115	03 00000041`cadfdaa0 00007ffb`eec92c6d VCRUNTIME140_1!_CallSettingFrame+0x20 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\handlers.asm @ 50]
116	04 00000041`cadfdad0 00007ffb`eec93ae5 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToState+0x241 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 1085]
117	05 00000041`cadfdc00 00007ffb`eec92258 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToEmptyState+0x2d [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 218]
118	06 00000041`cadfdc30 00007ffb`eec940e9 VCRUNTIME140_1!__InternalCxxFrameHandler<__FrameHandler4>+0x194 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 304]
119	07 00000041`cadfdcd0 00007ffc`5f9f249f VCRUNTIME140_1!__CxxFrameHandler4+0xa9 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 290]
120	08 00000041`cadfdd40 00007ffc`5f980939 ntdll!RtlpExecuteHandlerForUnwind+0xf
121	09 00000041`cadfdd70 00007ffc`5f9a0edd ntdll!RtlUnwindEx+0x339
122	0a 00000041`cadfe490 00007ffc`57aff976 ntdll!RtlUnwind+0xcd
123	0b 00000041`cadfea00 00007ffb`e1b5de01 VCRUNTIME140!__longjmp_internal+0xe6 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\longjmp.asm @ 140]
124	0c (Inline Function) --------`-------- VBoxVMM!iemOpcodeGetNextU8SlowJmp+0x95 [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 1155]
125	0d 00000041`cadfea50 00007ffb`e1b60f6b VBoxVMM!iemOpcodeGetNextU8Jmp+0xc1 [L:\vbox-intern\src\VBox\VMM\include\IEMInline.h @ 402]
126	0e 00000041`cadfea90 00007ffb`e1cc6201 VBoxVMM!IEMExecForExits+0xdb [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 10185]
127	0f 00000041`cadfec70 00007ffb`e1d0df8d VBoxVMM!EMHistoryExec+0x4f1 [L:\vbox-intern\src\VBox\VMM\VMMAll\EMAll.cpp @ 452]
128	10 00000041`cadfed60 00007ffb`e1d0d4c0 VBoxVMM!nemR3WinHandleExitCpuId+0x79d [L:\vbox-intern\src\VBox\VMM\VMMAll\NEMAllNativeTemplate-win.cpp.h @ 1829] @encode
129	@endcode
130	*
131	* @see https://developercommunity.visualstudio.com/t/fragile-behavior-of-longjmp-called-from-noexcept-f/1532859
132	*/
133	#if defined(IEM_WITH_SETJMP) && (defined(_MSC_VER) \|\| defined(IEM_WITH_THROW_CATCH))
134	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT_EX(false)
135	#else
136	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT
137	#endif
138
139	#define IEM_IMPLEMENTS_TASKSWITCH
140
141	/** @def IEM_WITH_3DNOW
142	* Includes the 3DNow decoding. */
143	#if (!defined(IEM_WITH_3DNOW) && !defined(IEM_WITHOUT_3DNOW)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
144	# define IEM_WITH_3DNOW
145	#endif
146
147	/** @def IEM_WITH_THREE_0F_38
148	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
149	#if (!defined(IEM_WITH_THREE_0F_38) && !defined(IEM_WITHOUT_THREE_0F_38)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
150	# define IEM_WITH_THREE_0F_38
151	#endif
152
153	/** @def IEM_WITH_THREE_0F_3A
154	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
155	#if (!defined(IEM_WITH_THREE_0F_3A) && !defined(IEM_WITHOUT_THREE_0F_3A)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
156	# define IEM_WITH_THREE_0F_3A
157	#endif
158
159	/** @def IEM_WITH_VEX
160	* Includes the VEX decoding. */
161	#if (!defined(IEM_WITH_VEX) && !defined(IEM_WITHOUT_VEX)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
162	# define IEM_WITH_VEX
163	#endif
164
165	/** @def IEM_CFG_TARGET_CPU
166	* The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
167	*
168	* By default we allow this to be configured by the user via the
169	* CPUM/GuestCpuName config string, but this comes at a slight cost during
170	* decoding. So, for applications of this code where there is no need to
171	* be dynamic wrt target CPU, just modify this define.
172	*/
173	#if !defined(IEM_CFG_TARGET_CPU) \|\| defined(DOXYGEN_RUNNING)
174	# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
175	#endif
176
177	//#define IEM_WITH_CODE_TLB // - work in progress
178	//#define IEM_WITH_DATA_TLB // - work in progress
179
180
181	/** @def IEM_USE_UNALIGNED_DATA_ACCESS
182	* Use unaligned accesses instead of elaborate byte assembly. */
183	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86) \|\| defined(DOXYGEN_RUNNING)
184	# define IEM_USE_UNALIGNED_DATA_ACCESS
185	#endif
186
187	//#define IEM_LOG_MEMORY_WRITES
188
189	#if !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
190	/** Instruction statistics. */
191	typedef struct IEMINSTRSTATS
192	{
193	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
194	# include "IEMInstructionStatisticsTmpl.h"
195	# undef IEM_DO_INSTR_STAT
196	} IEMINSTRSTATS;
197	#else
198	struct IEMINSTRSTATS;
199	typedef struct IEMINSTRSTATS IEMINSTRSTATS;
200	#endif
201	/** Pointer to IEM instruction statistics. */
202	typedef IEMINSTRSTATS *PIEMINSTRSTATS;
203
204
205	/** @name IEMTARGETCPU_EFL_BEHAVIOR_XXX - IEMCPU::aidxTargetCpuEflFlavour
206	* @{ */
207	#define IEMTARGETCPU_EFL_BEHAVIOR_NATIVE 0 /*< Native x86 EFLAGS result; Intel EFLAGS when on non-x86 hosts. /
208	#define IEMTARGETCPU_EFL_BEHAVIOR_INTEL 1 /*< Intel EFLAGS result. /
209	#define IEMTARGETCPU_EFL_BEHAVIOR_AMD 2 /*< AMD EFLAGS result /
210	#define IEMTARGETCPU_EFL_BEHAVIOR_RESERVED 3 /*< Reserved/dummy entry slot that's the same as 0. /
211	#define IEMTARGETCPU_EFL_BEHAVIOR_MASK 3 /*< For masking the index before use. /
212	/** Selects the right variant from a_aArray.
213	* pVCpu is implicit in the caller context. */
214	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT(a_aArray) \
215	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[1] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
216	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for when no native worker can
217	* be used because the host CPU does not support the operation. */
218	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_NON_NATIVE(a_aArray) \
219	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
220	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for a two dimentional
221	* array paralleling IEMCPU::aidxTargetCpuEflFlavour and a single bit index
222	* into the two.
223	* @sa IEM_SELECT_NATIVE_OR_FALLBACK */
224	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
225	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
226	(a_aaArray[a_fNative][pVCpu->iem.s.aidxTargetCpuEflFlavour[a_fNative] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
227	#else
228	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
229	(a_aaArray[0][pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
230	#endif
231	/** @} */
232
233	/**
234	* Picks @a a_pfnNative or @a a_pfnFallback according to the host CPU feature
235	* indicator given by @a a_fCpumFeatureMember (CPUMFEATURES member).
236	*
237	* On non-x86 hosts, this will shortcut to the fallback w/o checking the
238	* indicator.
239	*
240	* @sa IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX
241	*/
242	#if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
243	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) \
244	(g_CpumHostFeatures.s.a_fCpumFeatureMember ? a_pfnNative : a_pfnFallback)
245	#else
246	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) (a_pfnFallback)
247	#endif
248
249
250	/**
251	* Extended operand mode that includes a representation of 8-bit.
252	*
253	* This is used for packing down modes when invoking some C instruction
254	* implementations.
255	*/
256	typedef enum IEMMODEX
257	{
258	IEMMODEX_16BIT = IEMMODE_16BIT,
259	IEMMODEX_32BIT = IEMMODE_32BIT,
260	IEMMODEX_64BIT = IEMMODE_64BIT,
261	IEMMODEX_8BIT
262	} IEMMODEX;
263	AssertCompileSize(IEMMODEX, 4);
264
265
266	/**
267	* Branch types.
268	*/
269	typedef enum IEMBRANCH
270	{
271	IEMBRANCH_JUMP = 1,
272	IEMBRANCH_CALL,
273	IEMBRANCH_TRAP,
274	IEMBRANCH_SOFTWARE_INT,
275	IEMBRANCH_HARDWARE_INT
276	} IEMBRANCH;
277	AssertCompileSize(IEMBRANCH, 4);
278
279
280	/**
281	* INT instruction types.
282	*/
283	typedef enum IEMINT
284	{
285	/** INT n instruction (opcode 0xcd imm). */
286	IEMINT_INTN = 0,
287	/** Single byte INT3 instruction (opcode 0xcc). */
288	IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
289	/** Single byte INTO instruction (opcode 0xce). */
290	IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
291	/** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
292	IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
293	} IEMINT;
294	AssertCompileSize(IEMINT, 4);
295
296
297	/**
298	* A FPU result.
299	*/
300	typedef struct IEMFPURESULT
301	{
302	/** The output value. */
303	RTFLOAT80U r80Result;
304	/** The output status. */
305	uint16_t FSW;
306	} IEMFPURESULT;
307	AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
308	/** Pointer to a FPU result. */
309	typedef IEMFPURESULT *PIEMFPURESULT;
310	/** Pointer to a const FPU result. */
311	typedef IEMFPURESULT const *PCIEMFPURESULT;
312
313
314	/**
315	* A FPU result consisting of two output values and FSW.
316	*/
317	typedef struct IEMFPURESULTTWO
318	{
319	/** The first output value. */
320	RTFLOAT80U r80Result1;
321	/** The output status. */
322	uint16_t FSW;
323	/** The second output value. */
324	RTFLOAT80U r80Result2;
325	} IEMFPURESULTTWO;
326	AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
327	AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
328	/** Pointer to a FPU result consisting of two output values and FSW. */
329	typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
330	/** Pointer to a const FPU result consisting of two output values and FSW. */
331	typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
332
333
334	/**
335	* IEM TLB entry.
336	*
337	* Lookup assembly:
338	* @code{.asm}
339	; Calculate tag.
340	mov rax, [VA]
341	shl rax, 16
342	shr rax, 16 + X86_PAGE_SHIFT
343	or rax, [uTlbRevision]
344
345	; Do indexing.
346	movzx ecx, al
347	lea rcx, [pTlbEntries + rcx]
348
349	; Check tag.
350	cmp [rcx + IEMTLBENTRY.uTag], rax
351	jne .TlbMiss
352
353	; Check access.
354	mov rax, ACCESS_FLAGS \| MAPPING_R3_NOT_VALID \| 0xffffff00
355	and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
356	cmp rax, [uTlbPhysRev]
357	jne .TlbMiss
358
359	; Calc address and we're done.
360	mov eax, X86_PAGE_OFFSET_MASK
361	and eax, [VA]
362	or rax, [rcx + IEMTLBENTRY.pMappingR3]
363	%ifdef VBOX_WITH_STATISTICS
364	inc qword [cTlbHits]
365	%endif
366	jmp .Done
367
368	.TlbMiss:
369	mov r8d, ACCESS_FLAGS
370	mov rdx, [VA]
371	mov rcx, [pVCpu]
372	call iemTlbTypeMiss
373	.Done:
374
375	@endcode
376	*
377	*/
378	typedef struct IEMTLBENTRY
379	{
380	/** The TLB entry tag.
381	* Bits 35 thru 0 are made up of the virtual address shifted right 12 bits, this
382	* is ASSUMING a virtual address width of 48 bits.
383	*
384	* Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
385	*
386	* The TLB lookup code uses the current TLB revision, which won't ever be zero,
387	* enabling an extremely cheap TLB invalidation most of the time. When the TLB
388	* revision wraps around though, the tags needs to be zeroed.
389	*
390	* @note Try use SHRD instruction? After seeing
391	* https://gmplib.org/~tege/x86-timing.pdf, maybe not.
392	*
393	* @todo This will need to be reorganized for 57-bit wide virtual address and
394	* PCID (currently 12 bits) and ASID (currently 6 bits) support. We'll
395	* have to move the TLB entry versioning entirely to the
396	* fFlagsAndPhysRev member then, 57 bit wide VAs means we'll only have
397	* 19 bits left (64 - 57 + 12 = 19) and they'll almost entire be
398	* consumed by PCID and ASID (12 + 6 = 18).
399	*/
400	uint64_t uTag;
401	/** Access flags and physical TLB revision.
402	*
403	* - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
404	* - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
405	* - Bit 2 - page tables - not user (complemented X86_PTE_US).
406	* - Bit 3 - pgm phys/virt - not directly writable.
407	* - Bit 4 - pgm phys page - not directly readable.
408	* - Bit 5 - page tables - not accessed (complemented X86_PTE_A).
409	* - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
410	* - Bit 7 - tlb entry - pMappingR3 member not valid.
411	* - Bits 63 thru 8 are used for the physical TLB revision number.
412	*
413	* We're using complemented bit meanings here because it makes it easy to check
414	* whether special action is required. For instance a user mode write access
415	* would do a "TEST fFlags, (X86_PTE_RW \| X86_PTE_US \| X86_PTE_D)" and a
416	* non-zero result would mean special handling needed because either it wasn't
417	* writable, or it wasn't user, or the page wasn't dirty. A user mode read
418	* access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
419	* need to check any PTE flag.
420	*/
421	uint64_t fFlagsAndPhysRev;
422	/** The guest physical page address. */
423	uint64_t GCPhys;
424	/** Pointer to the ring-3 mapping. */
425	R3PTRTYPE(uint8_t *) pbMappingR3;
426	#if HC_ARCH_BITS == 32
427	uint32_t u32Padding1;
428	#endif
429	} IEMTLBENTRY;
430	AssertCompileSize(IEMTLBENTRY, 32);
431	/** Pointer to an IEM TLB entry. */
432	typedef IEMTLBENTRY *PIEMTLBENTRY;
433
434	/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
435	* @{ */
436	#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /*< Page tables: Not executable. /
437	#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /*< Page tables: Not writable. /
438	#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /*< Page tables: Not user accessible (supervisor only). /
439	#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /*< Phys page: Not writable (access handler, ROM, whatever). /
440	#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /*< Phys page: Not readable (MMIO / access handler, ROM) /
441	#define IEMTLBE_F_PT_NO_ACCESSED RT_BIT_64(5) /*< Phys tables: Not accessed (need to be marked accessed). /
442	#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /*< Page tables: Not dirty (needs to be made dirty on write). /
443	#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(7) /*< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. /
444	#define IEMTLBE_F_PG_UNASSIGNED RT_BIT_64(8) /*< Phys page: Unassigned memory (not RAM, ROM, MMIO2 or MMIO). /
445	#define IEMTLBE_F_PG_CODE_PAGE RT_BIT_64(9) /*< Phys page: Code page. /
446	#define IEMTLBE_F_PHYS_REV UINT64_C(0xfffffffffffffc00) /*< Physical revision mask. @sa IEMTLB_PHYS_REV_INCR /
447	/** @} */
448
449
450	/**
451	* An IEM TLB.
452	*
453	* We've got two of these, one for data and one for instructions.
454	*/
455	typedef struct IEMTLB
456	{
457	/** The TLB entries.
458	* We've choosen 256 because that way we can obtain the result directly from a
459	* 8-bit register without an additional AND instruction. */
460	IEMTLBENTRY aEntries[256];
461	/** The TLB revision.
462	* This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
463	* by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
464	* the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
465	* (The revision zero indicates an invalid TLB entry.)
466	*
467	* The initial value is choosen to cause an early wraparound. */
468	uint64_t uTlbRevision;
469	/** The TLB physical address revision - shadow of PGM variable.
470	*
471	* This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
472	* incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
473	* a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
474	* as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
475	*
476	* The initial value is choosen to cause an early wraparound. */
477	uint64_t volatile uTlbPhysRev;
478
479	/* Statistics: */
480
481	/** TLB hits (VBOX_WITH_STATISTICS only). */
482	uint64_t cTlbHits;
483	/** TLB misses. */
484	uint32_t cTlbMisses;
485	/** Slow read path. */
486	uint32_t cTlbSlowReadPath;
487	/** Safe read path. */
488	uint32_t cTlbSafeReadPath;
489	/** Safe write path. */
490	uint32_t cTlbSafeWritePath;
491	#if 0
492	/** TLB misses because of tag mismatch. */
493	uint32_t cTlbMissesTag;
494	/** TLB misses because of virtual access violation. */
495	uint32_t cTlbMissesVirtAccess;
496	/** TLB misses because of dirty bit. */
497	uint32_t cTlbMissesDirty;
498	/** TLB misses because of MMIO */
499	uint32_t cTlbMissesMmio;
500	/** TLB misses because of write access handlers. */
501	uint32_t cTlbMissesWriteHandler;
502	/** TLB misses because no r3(/r0) mapping. */
503	uint32_t cTlbMissesMapping;
504	#endif
505	/** Alignment padding. */
506	uint32_t au32Padding[6];
507	} IEMTLB;
508	AssertCompileSizeAlignment(IEMTLB, 64);
509	/** IEMTLB::uTlbRevision increment. */
510	#define IEMTLB_REVISION_INCR RT_BIT_64(36)
511	/** IEMTLB::uTlbRevision mask. */
512	#define IEMTLB_REVISION_MASK (~(RT_BIT_64(36) - 1))
513	/** IEMTLB::uTlbPhysRev increment.
514	* @sa IEMTLBE_F_PHYS_REV */
515	#define IEMTLB_PHYS_REV_INCR RT_BIT_64(10)
516	/**
517	* Calculates the TLB tag for a virtual address.
518	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
519	* @param a_pTlb The TLB.
520	* @param a_GCPtr The virtual address. Must be RTGCPTR or same size or
521	* the clearing of the top 16 bits won't work (if 32-bit
522	* we'll end up with mostly zeros).
523	*/
524	#define IEMTLB_CALC_TAG(a_pTlb, a_GCPtr) ( IEMTLB_CALC_TAG_NO_REV(a_GCPtr) \| (a_pTlb)->uTlbRevision )
525	/**
526	* Calculates the TLB tag for a virtual address but without TLB revision.
527	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
528	* @param a_GCPtr The virtual address. Must be RTGCPTR or same size or
529	* the clearing of the top 16 bits won't work (if 32-bit
530	* we'll end up with mostly zeros).
531	*/
532	#define IEMTLB_CALC_TAG_NO_REV(a_GCPtr) ( (((a_GCPtr) << 16) >> (GUEST_PAGE_SHIFT + 16)) )
533	/**
534	* Converts a TLB tag value into a TLB index.
535	* @returns Index into IEMTLB::aEntries.
536	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
537	*/
538	#define IEMTLB_TAG_TO_INDEX(a_uTag) ( (uint8_t)(a_uTag) )
539	/**
540	* Converts a TLB tag value into a TLB index.
541	* @returns Index into IEMTLB::aEntries.
542	* @param a_pTlb The TLB.
543	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
544	*/
545	#define IEMTLB_TAG_TO_ENTRY(a_pTlb, a_uTag) ( &(a_pTlb)->aEntries[IEMTLB_TAG_TO_INDEX(a_uTag)] )
546
547
548	/** @name IEM_MC_F_XXX - MC block flags/clues.
549	* @todo Merge with IEM_CIMPL_F_XXX
550	* @{ */
551	#define IEM_MC_F_ONLY_8086 RT_BIT_32(0)
552	#define IEM_MC_F_MIN_186 RT_BIT_32(1)
553	#define IEM_MC_F_MIN_286 RT_BIT_32(2)
554	#define IEM_MC_F_NOT_286_OR_OLDER IEM_MC_F_MIN_386
555	#define IEM_MC_F_MIN_386 RT_BIT_32(3)
556	#define IEM_MC_F_MIN_486 RT_BIT_32(4)
557	#define IEM_MC_F_MIN_PENTIUM RT_BIT_32(5)
558	#define IEM_MC_F_MIN_PENTIUM_II IEM_MC_F_MIN_PENTIUM
559	#define IEM_MC_F_MIN_CORE IEM_MC_F_MIN_PENTIUM
560	#define IEM_MC_F_64BIT RT_BIT_32(6)
561	#define IEM_MC_F_NOT_64BIT RT_BIT_32(7)
562	/** @} */
563
564	/** @name IEM_CIMPL_F_XXX - State change clues for CIMPL calls.
565	*
566	* These clues are mainly for the recompiler, so that it can emit correct code.
567	*
568	* They are processed by the python script and which also automatically
569	* calculates flags for MC blocks based on the statements, extending the use of
570	* these flags to describe MC block behavior to the recompiler core. The python
571	* script pass the flags to the IEM_MC2_END_EMIT_CALLS macro, but mainly for
572	* error checking purposes. The script emits the necessary fEndTb = true and
573	* similar statements as this reduces compile time a tiny bit.
574	*
575	* @{ */
576	/** Flag set if direct branch, clear if absolute or indirect. */
577	#define IEM_CIMPL_F_BRANCH_DIRECT RT_BIT_32(0)
578	/** Flag set if indirect branch, clear if direct or relative.
579	* This is also used for all system control transfers (SYSCALL, SYSRET, INT, ++)
580	* as well as for return instructions (RET, IRET, RETF). */
581	#define IEM_CIMPL_F_BRANCH_INDIRECT RT_BIT_32(1)
582	/** Flag set if relative branch, clear if absolute or indirect. */
583	#define IEM_CIMPL_F_BRANCH_RELATIVE RT_BIT_32(2)
584	/** Flag set if conditional branch, clear if unconditional. */
585	#define IEM_CIMPL_F_BRANCH_CONDITIONAL RT_BIT_32(3)
586	/** Flag set if it's a far branch (changes CS). */
587	#define IEM_CIMPL_F_BRANCH_FAR RT_BIT_32(4)
588	/** Convenience: Testing any kind of branch. */
589	#define IEM_CIMPL_F_BRANCH_ANY (IEM_CIMPL_F_BRANCH_DIRECT \| IEM_CIMPL_F_BRANCH_INDIRECT \| IEM_CIMPL_F_BRANCH_RELATIVE)
590
591	/** Execution flags may change (IEMCPU::fExec). */
592	#define IEM_CIMPL_F_MODE RT_BIT_32(5)
593	/** May change significant portions of RFLAGS. */
594	#define IEM_CIMPL_F_RFLAGS RT_BIT_32(6)
595	/** May change the status bits (X86_EFL_STATUS_BITS) in RFLAGS. */
596	#define IEM_CIMPL_F_STATUS_FLAGS RT_BIT_32(7)
597	/** May trigger interrupt shadowing. */
598	#define IEM_CIMPL_F_INHIBIT_SHADOW RT_BIT_32(8)
599	/** May enable interrupts, so recheck IRQ immediately afterwards executing
600	* the instruction. */
601	#define IEM_CIMPL_F_CHECK_IRQ_AFTER RT_BIT_32(9)
602	/** May disable interrupts, so recheck IRQ immediately before executing the
603	* instruction. */
604	#define IEM_CIMPL_F_CHECK_IRQ_BEFORE RT_BIT_32(10)
605	/** Convenience: Check for IRQ both before and after an instruction. */
606	#define IEM_CIMPL_F_CHECK_IRQ_BEFORE_AND_AFTER (IEM_CIMPL_F_CHECK_IRQ_BEFORE \| IEM_CIMPL_F_CHECK_IRQ_AFTER)
607	/** May trigger a VM exit (treated like IEM_CIMPL_F_MODE atm). */
608	#define IEM_CIMPL_F_VMEXIT RT_BIT_32(11)
609	/** May modify FPU state.
610	* @todo Not sure if this is useful yet. */
611	#define IEM_CIMPL_F_FPU RT_BIT_32(12)
612	/** REP prefixed instruction which may yield before updating PC.
613	* @todo Not sure if this is useful, REP functions now return non-zero
614	* status if they don't update the PC. */
615	#define IEM_CIMPL_F_REP RT_BIT_32(13)
616	/** I/O instruction.
617	* @todo Not sure if this is useful yet. */
618	#define IEM_CIMPL_F_IO RT_BIT_32(14)
619	/** Force end of TB after the instruction. */
620	#define IEM_CIMPL_F_END_TB RT_BIT_32(15)
621	/** Convenience: Raise exception (technically unnecessary, since it shouldn't return VINF_SUCCESS). */
622	#define IEM_CIMPL_F_XCPT \
623	(IEM_CIMPL_F_BRANCH_INDIRECT \| IEM_CIMPL_F_BRANCH_FAR \| IEM_CIMPL_F_MODE \| IEM_CIMPL_F_RFLAGS \| IEM_CIMPL_F_VMEXIT)
624	/** @} */
625
626
627	/** @name IEM_F_XXX - Execution mode flags (IEMCPU::fExec, IEMTB::fFlags).
628	*
629	* These flags are set when entering IEM and adjusted as code is executed, such
630	* that they will always contain the current values as instructions are
631	* finished.
632	*
633	* In recompiled execution mode, (most of) these flags are included in the
634	* translation block selection key and stored in IEMTB::fFlags alongside the
635	* IEMTB_F_XXX flags. The latter flags uses bits 31 thru 24, which are all zero
636	* in IEMCPU::fExec.
637	*
638	* @{ */
639	/** Mode: The block target mode mask. */
640	#define IEM_F_MODE_MASK UINT32_C(0x0000001f)
641	/** Mode: The IEMMODE part of the IEMTB_F_MODE_MASK value. */
642	#define IEM_F_MODE_CPUMODE_MASK UINT32_C(0x00000003)
643	/** X86 Mode: Bit used to indicating pre-386 CPU in 16-bit mode (for eliminating
644	* conditional in EIP/IP updating), and flat wide open CS, SS DS, and ES in
645	* 32-bit mode (for simplifying most memory accesses). */
646	#define IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK UINT32_C(0x00000004)
647	/** X86 Mode: Bit indicating protected mode, real mode (or SMM) when not set. */
648	#define IEM_F_MODE_X86_PROT_MASK UINT32_C(0x00000008)
649	/** X86 Mode: Bit used to indicate virtual 8086 mode (only 16-bit). */
650	#define IEM_F_MODE_X86_V86_MASK UINT32_C(0x00000010)
651
652	/** X86 Mode: 16-bit on 386 or later. */
653	#define IEM_F_MODE_X86_16BIT UINT32_C(0x00000000)
654	/** X86 Mode: 80286, 80186 and 8086/88 targetting blocks (EIP update opt). */
655	#define IEM_F_MODE_X86_16BIT_PRE_386 UINT32_C(0x00000004)
656	/** X86 Mode: 16-bit protected mode on 386 or later. */
657	#define IEM_F_MODE_X86_16BIT_PROT UINT32_C(0x00000008)
658	/** X86 Mode: 16-bit protected mode on 386 or later. */
659	#define IEM_F_MODE_X86_16BIT_PROT_PRE_386 UINT32_C(0x0000000c)
660	/** X86 Mode: 16-bit virtual 8086 protected mode (on 386 or later). */
661	#define IEM_F_MODE_X86_16BIT_PROT_V86 UINT32_C(0x00000018)
662
663	/** X86 Mode: 32-bit on 386 or later. */
664	#define IEM_F_MODE_X86_32BIT UINT32_C(0x00000001)
665	/** X86 Mode: 32-bit mode with wide open flat CS, SS, DS and ES. */
666	#define IEM_F_MODE_X86_32BIT_FLAT UINT32_C(0x00000005)
667	/** X86 Mode: 32-bit protected mode. */
668	#define IEM_F_MODE_X86_32BIT_PROT UINT32_C(0x00000009)
669	/** X86 Mode: 32-bit protected mode with wide open flat CS, SS, DS and ES. */
670	#define IEM_F_MODE_X86_32BIT_PROT_FLAT UINT32_C(0x0000000d)
671
672	/** X86 Mode: 64-bit (includes protected, but not the flat bit). */
673	#define IEM_F_MODE_X86_64BIT UINT32_C(0x0000000a)
674
675
676	/** Bypass access handlers when set. */
677	#define IEM_F_BYPASS_HANDLERS UINT32_C(0x00010000)
678	/** Have pending hardware instruction breakpoints. */
679	#define IEM_F_PENDING_BRK_INSTR UINT32_C(0x00020000)
680	/** Have pending hardware data breakpoints. */
681	#define IEM_F_PENDING_BRK_DATA UINT32_C(0x00040000)
682
683	/** X86: Have pending hardware I/O breakpoints. */
684	#define IEM_F_PENDING_BRK_X86_IO UINT32_C(0x00000400)
685	/** X86: Disregard the lock prefix (implied or not) when set. */
686	#define IEM_F_X86_DISREGARD_LOCK UINT32_C(0x00000800)
687
688	/** Pending breakpoint mask (what iemCalcExecDbgFlags works out). */
689	#define IEM_F_PENDING_BRK_MASK (IEM_F_PENDING_BRK_INSTR \| IEM_F_PENDING_BRK_DATA \| IEM_F_PENDING_BRK_X86_IO)
690
691	/** Caller configurable options. */
692	#define IEM_F_USER_OPTS (IEM_F_BYPASS_HANDLERS \| IEM_F_X86_DISREGARD_LOCK)
693
694	/** X86: The current protection level (CPL) shift factor. */
695	#define IEM_F_X86_CPL_SHIFT 8
696	/** X86: The current protection level (CPL) mask. */
697	#define IEM_F_X86_CPL_MASK UINT32_C(0x00000300)
698	/** X86: The current protection level (CPL) shifted mask. */
699	#define IEM_F_X86_CPL_SMASK UINT32_C(0x00000003)
700
701	/** X86 execution context.
702	* The IEM_F_X86_CTX_XXX values are individual flags that can be combined (with
703	* the exception of IEM_F_X86_CTX_NORMAL). This allows running VMs from SMM
704	* mode. */
705	#define IEM_F_X86_CTX_MASK UINT32_C(0x0000f000)
706	/** X86 context: Plain regular execution context. */
707	#define IEM_F_X86_CTX_NORMAL UINT32_C(0x00000000)
708	/** X86 context: VT-x enabled. */
709	#define IEM_F_X86_CTX_VMX UINT32_C(0x00001000)
710	/** X86 context: AMD-V enabled. */
711	#define IEM_F_X86_CTX_SVM UINT32_C(0x00002000)
712	/** X86 context: In AMD-V or VT-x guest mode. */
713	#define IEM_F_X86_CTX_IN_GUEST UINT32_C(0x00004000)
714	/** X86 context: System management mode (SMM). */
715	#define IEM_F_X86_CTX_SMM UINT32_C(0x00008000)
716
717	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
718	* iemRegFinishClearingRF() most for most situations (CPUMCTX_DBG_HIT_DRX_MASK
719	* and CPUMCTX_DBG_DBGF_MASK are covered by the IEM_F_PENDING_BRK_XXX bits
720	* alread). */
721
722	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
723	* iemRegFinishClearingRF() most for most situations
724	* (CPUMCTX_DBG_HIT_DRX_MASK and CPUMCTX_DBG_DBGF_MASK are covered by
725	* the IEM_F_PENDING_BRK_XXX bits alread). */
726
727	/** @} */
728
729
730	/** @name IEMTB_F_XXX - Translation block flags (IEMTB::fFlags).
731	*
732	* Extends the IEM_F_XXX flags (subject to IEMTB_F_IEM_F_MASK) to make up the
733	* translation block flags. The combined flag mask (subject to
734	* IEMTB_F_KEY_MASK) is used as part of the lookup key for translation blocks.
735	*
736	* @{ */
737	/** Mask of IEM_F_XXX flags included in IEMTB_F_XXX. */
738	#define IEMTB_F_IEM_F_MASK UINT32_C(0x00ffffff)
739
740	/** Type: The block type mask. */
741	#define IEMTB_F_TYPE_MASK UINT32_C(0x03000000)
742	/** Type: Purly threaded recompiler (via tables). */
743	#define IEMTB_F_TYPE_THREADED UINT32_C(0x01000000)
744	/** Type: Native recompilation. */
745	#define IEMTB_F_TYPE_NATIVE UINT32_C(0x02000000)
746
747	/** Set when we're starting the block in an "interrupt shadow".
748	* We don't need to distingish between the two types of this mask, thus the one.
749	* @see CPUMCTX_INHIBIT_SHADOW, CPUMIsInInterruptShadow() */
750	#define IEMTB_F_INHIBIT_SHADOW UINT32_C(0x04000000)
751	/** Set when we're currently inhibiting NMIs
752	* @see CPUMCTX_INHIBIT_NMI, CPUMAreInterruptsInhibitedByNmi() */
753	#define IEMTB_F_INHIBIT_NMI UINT32_C(0x08000000)
754
755	/** Checks that EIP/IP is wihin CS.LIM before each instruction. Used when
756	* we're close the limit before starting a TB, as determined by
757	* iemGetTbFlagsForCurrentPc(). */
758	#define IEMTB_F_CS_LIM_CHECKS UINT32_C(0x10000000)
759
760	/** Mask of the IEMTB_F_XXX flags that are part of the TB lookup key.
761	* @note We skip the CPL as we don't currently generate ring-specific code,
762	* that's all handled in CIMPL functions.
763	*
764	* For the same reasons, we skip all of IEM_F_X86_CTX_MASK, with the
765	* exception of SMM (which we don't implement). */
766	#define IEMTB_F_KEY_MASK ( (UINT32_MAX & ~(IEM_F_X86_CTX_MASK \| IEM_F_X86_CPL_MASK \| IEMTB_F_TYPE_MASK)) \
767	\| IEM_F_X86_CTX_SMM)
768	/** @} */
769
770	AssertCompile( (IEM_F_MODE_X86_16BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
771	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
772	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_PROT_MASK));
773	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_V86_MASK));
774	AssertCompile( (IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
775	AssertCompile( IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
776	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_PROT_MASK));
777	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
778	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
779	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
780	AssertCompile( IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
781	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_V86_MASK));
782	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
783	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
784	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_PROT_MASK);
785	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
786	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_PROT_MASK);
787	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
788	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_V86_MASK);
789
790	AssertCompile( (IEM_F_MODE_X86_32BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
791	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
792	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_PROT_MASK));
793	AssertCompile( (IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
794	AssertCompile( IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
795	AssertCompile(!(IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_PROT_MASK));
796	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
797	AssertCompile(!(IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
798	AssertCompile( IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
799	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
800	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
801	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_PROT_MASK);
802
803	AssertCompile( (IEM_F_MODE_X86_64BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_64BIT);
804	AssertCompile( IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_PROT_MASK);
805	AssertCompile(!(IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
806
807	/** Native instruction type for use with the native code generator.
808	* This is a byte (uint8_t) for x86 and amd64 and uint32_t for the other(s). */
809	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
810	typedef uint8_t IEMNATIVEINSTR;
811	#else
812	typedef uint32_t IEMNATIVEINSTR;
813	#endif
814	/** Pointer to a native instruction unit. */
815	typedef IEMNATIVEINSTR *PIEMNATIVEINSTR;
816	/** Pointer to a const native instruction unit. */
817	typedef IEMNATIVEINSTR const *PCIEMNATIVEINSTR;
818
819	/**
820	* A call for the threaded call table.
821	*/
822	typedef struct IEMTHRDEDCALLENTRY
823	{
824	/** The function to call (IEMTHREADEDFUNCS). */
825	uint16_t enmFunction;
826	/** Instruction number in the TB (for statistics). */
827	uint8_t idxInstr;
828	uint8_t uUnused0;
829
830	/** Offset into IEMTB::pabOpcodes. */
831	uint16_t offOpcode;
832	/** The opcode length. */
833	uint8_t cbOpcode;
834	/** Index in to IEMTB::aRanges. */
835	uint8_t idxRange;
836
837	/** Generic parameters. */
838	uint64_t auParams[3];
839	} IEMTHRDEDCALLENTRY;
840	AssertCompileSize(IEMTHRDEDCALLENTRY, sizeof(uint64_t) * 4);
841	/** Pointer to a threaded call entry. */
842	typedef struct IEMTHRDEDCALLENTRY *PIEMTHRDEDCALLENTRY;
843	/** Pointer to a const threaded call entry. */
844	typedef IEMTHRDEDCALLENTRY const *PCIEMTHRDEDCALLENTRY;
845
846	/**
847	* Native IEM TB 'function' typedef.
848	*
849	* This will throw/longjmp on occation.
850	*
851	* @note AMD64 doesn't have that many non-volatile registers and does sport
852	* 32-bit address displacments, so we don't need pCtx.
853	*
854	* On ARM64 pCtx allows us to directly address the whole register
855	* context without requiring a separate indexing register holding the
856	* offset. This saves an instruction loading the offset for each guest
857	* CPU context access, at the cost of a non-volatile register.
858	* Fortunately, ARM64 has quite a lot more registers.
859	*/
860	typedef
861	#ifdef RT_ARCH_AMD64
862	int FNIEMTBNATIVE(PVMCPUCC pVCpu)
863	#else
864	int FNIEMTBNATIVE(PVMCPUCC pVCpu, PCPUMCTX pCtx)
865	#endif
866	#if RT_CPLUSPLUS_PREREQ(201700)
867	IEM_NOEXCEPT_MAY_LONGJMP
868	#endif
869	;
870	/** Pointer to a native IEM TB entry point function.
871	* This will throw/longjmp on occation. */
872	typedef FNIEMTBNATIVE *PFNIEMTBNATIVE;
873
874
875	/**
876	* Translation block debug info entry type.
877	*/
878	typedef enum IEMTBDBGENTRYTYPE
879	{
880	kIemTbDbgEntryType_Invalid = 0,
881	/** The entry is for marking a native code position.
882	* Entries following this all apply to this position. */
883	kIemTbDbgEntryType_NativeOffset,
884	/** The entry is for a new guest instruction. */
885	kIemTbDbgEntryType_GuestInstruction,
886	/** Marks the start of a threaded call. */
887	kIemTbDbgEntryType_ThreadedCall,
888	/** Marks the location of a label. */
889	kIemTbDbgEntryType_Label,
890	/** Info about a host register shadowing a guest register. */
891	kIemTbDbgEntryType_GuestRegShadowing,
892	kIemTbDbgEntryType_End
893	} IEMTBDBGENTRYTYPE;
894
895	/**
896	* Translation block debug info entry.
897	*/
898	typedef union IEMTBDBGENTRY
899	{
900	/** Plain 32-bit view. */
901	uint32_t u;
902
903	/** Generic view for getting at the type field. */
904	struct
905	{
906	/** IEMTBDBGENTRYTYPE */
907	uint32_t uType : 4;
908	uint32_t uTypeSpecific : 28;
909	} Gen;
910
911	struct
912	{
913	/** kIemTbDbgEntryType_ThreadedCall1. */
914	uint32_t uType : 4;
915	/** Native code offset. */
916	uint32_t offNative : 28;
917	} NativeOffset;
918
919	struct
920	{
921	/** kIemTbDbgEntryType_GuestInstruction. */
922	uint32_t uType : 4;
923	uint32_t uUnused : 4;
924	/** The IEM_F_XXX flags. */
925	uint32_t fExec : 24;
926	} GuestInstruction;
927
928	struct
929	{
930	/* kIemTbDbgEntryType_ThreadedCall. */
931	uint32_t uType : 4;
932	uint32_t uUnused : 12;
933	/** The threaded call number (IEMTHREADEDFUNCS). */
934	uint32_t enmCall : 16;
935	} ThreadedCall;
936
937	struct
938	{
939	/* kIemTbDbgEntryType_Label. */
940	uint32_t uType : 4;
941	uint32_t uUnused : 4;
942	/** The label type (IEMNATIVELABELTYPE). */
943	uint32_t enmLabel : 8;
944	/** The label data. */
945	uint32_t uData : 16;
946	} Label;
947
948	struct
949	{
950	/* kIemTbDbgEntryType_GuestRegShadowing. */
951	uint32_t uType : 4;
952	uint32_t uUnused : 4;
953	/** The guest register being shadowed (IEMNATIVEGSTREG). */
954	uint32_t idxGstReg : 8;
955	/** The host new register number, UINT8_MAX if dropped. */
956	uint32_t idxHstReg : 8;
957	/** The previous host register number, UINT8_MAX if new. */
958	uint32_t idxHstRegPrev : 8;
959	} GuestRegShadowing;
960	} IEMTBDBGENTRY;
961	AssertCompileSize(IEMTBDBGENTRY, sizeof(uint32_t));
962	/** Pointer to a debug info entry. */
963	typedef IEMTBDBGENTRY *PIEMTBDBGENTRY;
964	/** Pointer to a const debug info entry. */
965	typedef IEMTBDBGENTRY const *PCIEMTBDBGENTRY;
966
967	/**
968	* Translation block debug info.
969	*/
970	typedef struct IEMTBDBG
971	{
972	/** Number of entries in aEntries. */
973	uint32_t cEntries;
974	/** Debug info entries. */
975	RT_FLEXIBLE_ARRAY_EXTENSION
976	IEMTBDBGENTRY aEntries[RT_FLEXIBLE_ARRAY];
977	} IEMTBDBG;
978	/** Pointer to TB debug info. */
979	typedef IEMTBDBG *PIEMTBDBG;
980	/** Pointer to const TB debug info. */
981	typedef IEMTBDBG const *PCIEMTBDBG;
982
983
984	/**
985	* Translation block.
986	*
987	* The current plan is to just keep TBs and associated lookup hash table private
988	* to each VCpu as that simplifies TB removal greatly (no races) and generally
989	* avoids using expensive atomic primitives for updating lists and stuff.
990	*/
991	#pragma pack(2) /* to prevent the Thrd structure from being padded unnecessarily */
992	typedef struct IEMTB
993	{
994	/** Next block with the same hash table entry. */
995	struct IEMTB *pNext;
996	/** Usage counter. */
997	uint32_t cUsed;
998	/** The IEMCPU::msRecompilerPollNow last time it was used. */
999	uint32_t msLastUsed;
1000
1001	/** @name What uniquely identifies the block.
1002	* @{ */
1003	RTGCPHYS GCPhysPc;
1004	/** IEMTB_F_XXX (i.e. IEM_F_XXX ++). */
1005	uint32_t fFlags;
1006	union
1007	{
1008	struct
1009	{
1010	/*< Relevant CS X86DESCATTR_XXX bits. /
1011	uint16_t fAttr;
1012	} x86;
1013	};
1014	/** @} */
1015
1016	/** Number of opcode ranges. */
1017	uint8_t cRanges;
1018	/** Statistics: Number of instructions in the block. */
1019	uint8_t cInstructions;
1020
1021	/** Type specific info. */
1022	union
1023	{
1024	struct
1025	{
1026	/** The call sequence table. */
1027	PIEMTHRDEDCALLENTRY paCalls;
1028	/** Number of calls in paCalls. */
1029	uint16_t cCalls;
1030	/** Number of calls allocated. */
1031	uint16_t cAllocated;
1032	} Thrd;
1033	struct
1034	{
1035	/** The native instructions (PFNIEMTBNATIVE). */
1036	PIEMNATIVEINSTR paInstructions;
1037	/** Number of instructions pointed to by paInstructions. */
1038	uint32_t cInstructions;
1039	} Native;
1040	/** Generic view for zeroing when freeing. */
1041	struct
1042	{
1043	uintptr_t uPtr;
1044	uint32_t uData;
1045	} Gen;
1046	};
1047
1048	/** The allocation chunk this TB belongs to. */
1049	uint8_t idxAllocChunk;
1050	uint8_t bUnused;
1051
1052	/** Number of bytes of opcodes stored in pabOpcodes.
1053	* @todo this field isn't really needed, aRanges keeps the actual info. */
1054	uint16_t cbOpcodes;
1055	/** Pointer to the opcode bytes this block was recompiled from. */
1056	uint8_t *pabOpcodes;
1057
1058	/** Debug info if enabled.
1059	* This is only generated by the native recompiler. */
1060	PIEMTBDBG pDbgInfo;
1061
1062	/* --- 64 byte cache line end --- */
1063
1064	/** Opcode ranges.
1065	*
1066	* The opcode checkers and maybe TLB loading functions will use this to figure
1067	* out what to do. The parameter will specify an entry and the opcode offset to
1068	* start at and the minimum number of bytes to verify (instruction length).
1069	*
1070	* When VT-x and AMD-V looks up the opcode bytes for an exitting instruction,
1071	* they'll first translate RIP (+ cbInstr - 1) to a physical address using the
1072	* code TLB (must have a valid entry for that address) and scan the ranges to
1073	* locate the corresponding opcodes. Probably.
1074	*/
1075	struct IEMTBOPCODERANGE
1076	{
1077	/** Offset within pabOpcodes. */
1078	uint16_t offOpcodes;
1079	/** Number of bytes. */
1080	uint16_t cbOpcodes;
1081	/** The page offset. */
1082	RT_GCC_EXTENSION
1083	uint16_t offPhysPage : 12;
1084	/** Unused bits. */
1085	RT_GCC_EXTENSION
1086	uint16_t u2Unused : 2;
1087	/** Index into GCPhysPc + aGCPhysPages for the physical page address. */
1088	RT_GCC_EXTENSION
1089	uint16_t idxPhysPage : 2;
1090	} aRanges[8];
1091
1092	/** Physical pages that this TB covers.
1093	* The GCPhysPc w/o page offset is element zero, so starting here with 1. */
1094	RTGCPHYS aGCPhysPages[2];
1095	} IEMTB;
1096	#pragma pack()
1097	AssertCompileMemberAlignment(IEMTB, GCPhysPc, sizeof(RTGCPHYS));
1098	AssertCompileMemberAlignment(IEMTB, Thrd, sizeof(void *));
1099	AssertCompileMemberAlignment(IEMTB, pabOpcodes, sizeof(void *));
1100	AssertCompileMemberAlignment(IEMTB, pDbgInfo, sizeof(void *));
1101	AssertCompileMemberAlignment(IEMTB, aGCPhysPages, sizeof(RTGCPHYS));
1102	AssertCompileMemberOffset(IEMTB, aRanges, 64);
1103	AssertCompileMemberSize(IEMTB, aRanges[0], 6);
1104	#if 1
1105	AssertCompileSize(IEMTB, 128);
1106	# define IEMTB_SIZE_IS_POWER_OF_TWO /*< The IEMTB size is a power of two. /
1107	#else
1108	AssertCompileSize(IEMTB, 168);
1109	# undef IEMTB_SIZE_IS_POWER_OF_TWO
1110	#endif
1111
1112	/** Pointer to a translation block. */
1113	typedef IEMTB *PIEMTB;
1114	/** Pointer to a const translation block. */
1115	typedef IEMTB const *PCIEMTB;
1116
1117	/**
1118	* A chunk of memory in the TB allocator.
1119	*/
1120	typedef struct IEMTBCHUNK
1121	{
1122	/** Pointer to the translation blocks in this chunk. */
1123	PIEMTB paTbs;
1124	#ifdef IN_RING0
1125	/** Allocation handle. */
1126	RTR0MEMOBJ hMemObj;
1127	#endif
1128	} IEMTBCHUNK;
1129
1130	/**
1131	* A per-CPU translation block allocator.
1132	*
1133	* Because of how the IEMTBCACHE uses the lower 6 bits of the TB address to keep
1134	* the length of the collision list, and of course also for cache line alignment
1135	* reasons, the TBs must be allocated with at least 64-byte alignment.
1136	* Memory is there therefore allocated using one of the page aligned allocators.
1137	*
1138	*
1139	* To avoid wasting too much memory, it is allocated piecemeal as needed,
1140	* in chunks (IEMTBCHUNK) of 2 MiB or more. The TB has an 8-bit chunk index
1141	* that enables us to quickly calculate the allocation bitmap position when
1142	* freeing the translation block.
1143	*/
1144	typedef struct IEMTBALLOCATOR
1145	{
1146	/** Magic value (IEMTBALLOCATOR_MAGIC). */
1147	uint32_t uMagic;
1148
1149	#ifdef IEMTB_SIZE_IS_POWER_OF_TWO
1150	/** Mask corresponding to cTbsPerChunk - 1. */
1151	uint32_t fChunkMask;
1152	/** Shift count corresponding to cTbsPerChunk. */
1153	uint8_t cChunkShift;
1154	#else
1155	uint32_t uUnused;
1156	uint8_t bUnused;
1157	#endif
1158	/** Number of chunks we're allowed to allocate. */
1159	uint8_t cMaxChunks;
1160	/** Number of chunks currently populated. */
1161	uint16_t cAllocatedChunks;
1162	/** Number of translation blocks per chunk. */
1163	uint32_t cTbsPerChunk;
1164	/** Chunk size. */
1165	uint32_t cbPerChunk;
1166
1167	/** The maximum number of TBs. */
1168	uint32_t cMaxTbs;
1169	/** Total number of TBs in the populated chunks.
1170	* (cAllocatedChunks * cTbsPerChunk) */
1171	uint32_t cTotalTbs;
1172	/** The current number of TBs in use.
1173	* The number of free TBs: cAllocatedTbs - cInUseTbs; */
1174	uint32_t cInUseTbs;
1175	/** Statistics: Number of the cInUseTbs that are native ones. */
1176	uint32_t cNativeTbs;
1177	/** Statistics: Number of the cInUseTbs that are threaded ones. */
1178	uint32_t cThreadedTbs;
1179
1180	/** Where to start pruning TBs from when we're out.
1181	* See iemTbAllocatorAllocSlow for details. */
1182	uint32_t iPruneFrom;
1183	/** Hint about which bit to start scanning the bitmap from. */
1184	uint32_t iStartHint;
1185
1186	/** Statistics: Number of TB allocation calls. */
1187	STAMCOUNTER StatAllocs;
1188	/** Statistics: Number of TB free calls. */
1189	STAMCOUNTER StatFrees;
1190	/** Statistics: Time spend pruning. */
1191	STAMPROFILE StatPrune;
1192
1193	/** The delayed free list (see iemTbAlloctorScheduleForFree). */
1194	PIEMTB pDelayedFreeHead;
1195
1196	/** Allocation chunks. */
1197	IEMTBCHUNK aChunks[256];
1198
1199	/** Allocation bitmap for all possible chunk chunks. */
1200	RT_FLEXIBLE_ARRAY_EXTENSION
1201	uint64_t bmAllocated[RT_FLEXIBLE_ARRAY];
1202	} IEMTBALLOCATOR;
1203	/** Pointer to a TB allocator. */
1204	typedef struct IEMTBALLOCATOR *PIEMTBALLOCATOR;
1205
1206	/** Magic value for the TB allocator (Emmet Harley Cohen). */
1207	#define IEMTBALLOCATOR_MAGIC UINT32_C(0x19900525)
1208
1209
1210	/**
1211	* A per-CPU translation block cache (hash table).
1212	*
1213	* The hash table is allocated once during IEM initialization and size double
1214	* the max TB count, rounded up to the nearest power of two (so we can use and
1215	* AND mask rather than a rest division when hashing).
1216	*/
1217	typedef struct IEMTBCACHE
1218	{
1219	/** Magic value (IEMTBCACHE_MAGIC). */
1220	uint32_t uMagic;
1221	/** Size of the hash table. This is a power of two. */
1222	uint32_t cHash;
1223	/** The mask corresponding to cHash. */
1224	uint32_t uHashMask;
1225	uint32_t uPadding;
1226
1227	/** @name Statistics
1228	* @{ */
1229	/** Number of collisions ever. */
1230	STAMCOUNTER cCollisions;
1231
1232	/** Statistics: Number of TB lookup misses. */
1233	STAMCOUNTER cLookupMisses;
1234	/** Statistics: Number of TB lookup hits (debug only). */
1235	STAMCOUNTER cLookupHits;
1236	STAMCOUNTER auPadding2[3];
1237	/** Statistics: Collision list length pruning. */
1238	STAMPROFILE StatPrune;
1239	/** @} */
1240
1241	/** The hash table itself.
1242	* @note The lower 6 bits of the pointer is used for keeping the collision
1243	* list length, so we can take action when it grows too long.
1244	* This works because TBs are allocated using a 64 byte (or
1245	* higher) alignment from page aligned chunks of memory, so the lower
1246	* 6 bits of the address will always be zero.
1247	* See IEMTBCACHE_PTR_COUNT_MASK, IEMTBCACHE_PTR_MAKE and friends.
1248	*/
1249	RT_FLEXIBLE_ARRAY_EXTENSION
1250	PIEMTB apHash[RT_FLEXIBLE_ARRAY];
1251	} IEMTBCACHE;
1252	/** Pointer to a per-CPU translation block cahce. */
1253	typedef IEMTBCACHE *PIEMTBCACHE;
1254
1255	/** Magic value for IEMTBCACHE (Johnny O'Neal). */
1256	#define IEMTBCACHE_MAGIC UINT32_C(0x19561010)
1257
1258	/** The collision count mask for IEMTBCACHE::apHash entries. */
1259	#define IEMTBCACHE_PTR_COUNT_MASK ((uintptr_t)0x3f)
1260	/** The max collision count for IEMTBCACHE::apHash entries before pruning. */
1261	#define IEMTBCACHE_PTR_MAX_COUNT ((uintptr_t)0x30)
1262	/** Combine a TB pointer and a collision list length into a value for an
1263	* IEMTBCACHE::apHash entry. */
1264	#define IEMTBCACHE_PTR_MAKE(a_pTb, a_cCount) (PIEMTB)((uintptr_t)(a_pTb) \| (a_cCount))
1265	/** Combine a TB pointer and a collision list length into a value for an
1266	* IEMTBCACHE::apHash entry. */
1267	#define IEMTBCACHE_PTR_GET_TB(a_pHashEntry) (PIEMTB)((uintptr_t)(a_pHashEntry) & ~IEMTBCACHE_PTR_COUNT_MASK)
1268	/** Combine a TB pointer and a collision list length into a value for an
1269	* IEMTBCACHE::apHash entry. */
1270	#define IEMTBCACHE_PTR_GET_COUNT(a_pHashEntry) ((uintptr_t)(a_pHashEntry) & IEMTBCACHE_PTR_COUNT_MASK)
1271
1272	/**
1273	* Calculates the hash table slot for a TB from physical PC address and TB flags.
1274	*/
1275	#define IEMTBCACHE_HASH(a_paCache, a_fTbFlags, a_GCPhysPc) \
1276	IEMTBCACHE_HASH_NO_KEY_MASK(a_paCache, (a_fTbFlags) & IEMTB_F_KEY_MASK, a_GCPhysPc)
1277
1278	/**
1279	* Calculates the hash table slot for a TB from physical PC address and TB
1280	* flags, ASSUMING the caller has applied IEMTB_F_KEY_MASK to @a a_fTbFlags.
1281	*/
1282	#define IEMTBCACHE_HASH_NO_KEY_MASK(a_paCache, a_fTbFlags, a_GCPhysPc) \
1283	(((uint32_t)(a_GCPhysPc) ^ (a_fTbFlags)) & (a_paCache)->uHashMask)
1284
1285
1286	/** @name IEMBRANCHED_F_XXX - Branched indicator (IEMCPU::fTbBranched).
1287	*
1288	* These flags parallels IEM_CIMPL_F_BRANCH_XXX.
1289	*
1290	* @{ */
1291	/** Value if no branching happened recently. */
1292	#define IEMBRANCHED_F_NO UINT8_C(0x00)
1293	/** Flag set if direct branch, clear if absolute or indirect. */
1294	#define IEMBRANCHED_F_DIRECT UINT8_C(0x01)
1295	/** Flag set if indirect branch, clear if direct or relative. */
1296	#define IEMBRANCHED_F_INDIRECT UINT8_C(0x02)
1297	/** Flag set if relative branch, clear if absolute or indirect. */
1298	#define IEMBRANCHED_F_RELATIVE UINT8_C(0x04)
1299	/** Flag set if conditional branch, clear if unconditional. */
1300	#define IEMBRANCHED_F_CONDITIONAL UINT8_C(0x08)
1301	/** Flag set if it's a far branch. */
1302	#define IEMBRANCHED_F_FAR UINT8_C(0x10)
1303	/** Flag set (by IEM_MC_REL_JMP_XXX) if it's a zero bytes relative jump. */
1304	#define IEMBRANCHED_F_ZERO UINT8_C(0x20)
1305	/** @} */
1306
1307
1308	/**
1309	* The per-CPU IEM state.
1310	*/
1311	typedef struct IEMCPU
1312	{
1313	/** Info status code that needs to be propagated to the IEM caller.
1314	* This cannot be passed internally, as it would complicate all success
1315	* checks within the interpreter making the code larger and almost impossible
1316	* to get right. Instead, we'll store status codes to pass on here. Each
1317	* source of these codes will perform appropriate sanity checks. */
1318	int32_t rcPassUp; /* 0x00 */
1319	/** Execution flag, IEM_F_XXX. */
1320	uint32_t fExec; /* 0x04 */
1321
1322	/** @name Decoder state.
1323	* @{ */
1324	#ifndef IEM_WITH_OPAQUE_DECODER_STATE
1325	# ifdef IEM_WITH_CODE_TLB
1326	/** The offset of the next instruction byte. */
1327	uint32_t offInstrNextByte; /* 0x08 */
1328	/** The number of bytes available at pbInstrBuf for the current instruction.
1329	* This takes the max opcode length into account so that doesn't need to be
1330	* checked separately. */
1331	uint32_t cbInstrBuf; /* 0x0c */
1332	/** Pointer to the page containing RIP, user specified buffer or abOpcode.
1333	* This can be NULL if the page isn't mappable for some reason, in which
1334	* case we'll do fallback stuff.
1335	*
1336	* If we're executing an instruction from a user specified buffer,
1337	* IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
1338	* aligned pointer but pointer to the user data.
1339	*
1340	* For instructions crossing pages, this will start on the first page and be
1341	* advanced to the next page by the time we've decoded the instruction. This
1342	* therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
1343	*/
1344	uint8_t const pbInstrBuf; / 0x10 */
1345	# if ARCH_BITS == 32
1346	uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
1347	# endif
1348	/** The program counter corresponding to pbInstrBuf.
1349	* This is set to a non-canonical address when we need to invalidate it. */
1350	uint64_t uInstrBufPc; /* 0x18 */
1351	/** The guest physical address corresponding to pbInstrBuf. */
1352	RTGCPHYS GCPhysInstrBuf; /* 0x20 */
1353	/** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
1354	* This takes the CS segment limit into account. */
1355	uint16_t cbInstrBufTotal; /* 0x28 */
1356	/** Offset into pbInstrBuf of the first byte of the current instruction.
1357	* Can be negative to efficiently handle cross page instructions. */
1358	int16_t offCurInstrStart; /* 0x2a */
1359
1360	/** The prefix mask (IEM_OP_PRF_XXX). */
1361	uint32_t fPrefixes; /* 0x2c */
1362	/** The extra REX ModR/M register field bit (REX.R << 3). */
1363	uint8_t uRexReg; /* 0x30 */
1364	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
1365	* (REX.B << 3). */
1366	uint8_t uRexB; /* 0x31 */
1367	/** The extra REX SIB index field bit (REX.X << 3). */
1368	uint8_t uRexIndex; /* 0x32 */
1369
1370	/** The effective segment register (X86_SREG_XXX). */
1371	uint8_t iEffSeg; /* 0x33 */
1372
1373	/** The offset of the ModR/M byte relative to the start of the instruction. */
1374	uint8_t offModRm; /* 0x34 */
1375
1376	# ifdef IEM_WITH_CODE_TLB_AND_OPCODE_BUF
1377	/** The current offset into abOpcode. */
1378	uint8_t offOpcode; /* 0x35 */
1379	# else
1380	uint8_t bUnused; /* 0x35 */
1381	# endif
1382	# else /* !IEM_WITH_CODE_TLB */
1383	/** The size of what has currently been fetched into abOpcode. */
1384	uint8_t cbOpcode; /* 0x08 */
1385	/** The current offset into abOpcode. */
1386	uint8_t offOpcode; /* 0x09 */
1387	/** The offset of the ModR/M byte relative to the start of the instruction. */
1388	uint8_t offModRm; /* 0x0a */
1389
1390	/** The effective segment register (X86_SREG_XXX). */
1391	uint8_t iEffSeg; /* 0x0b */
1392
1393	/** The prefix mask (IEM_OP_PRF_XXX). */
1394	uint32_t fPrefixes; /* 0x0c */
1395	/** The extra REX ModR/M register field bit (REX.R << 3). */
1396	uint8_t uRexReg; /* 0x10 */
1397	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
1398	* (REX.B << 3). */
1399	uint8_t uRexB; /* 0x11 */
1400	/** The extra REX SIB index field bit (REX.X << 3). */
1401	uint8_t uRexIndex; /* 0x12 */
1402
1403	# endif /* !IEM_WITH_CODE_TLB */
1404
1405	/** The effective operand mode. */
1406	IEMMODE enmEffOpSize; /* 0x36, 0x13 */
1407	/** The default addressing mode. */
1408	IEMMODE enmDefAddrMode; /* 0x37, 0x14 */
1409	/** The effective addressing mode. */
1410	IEMMODE enmEffAddrMode; /* 0x38, 0x15 */
1411	/** The default operand mode. */
1412	IEMMODE enmDefOpSize; /* 0x39, 0x16 */
1413
1414	/** Prefix index (VEX.pp) for two byte and three byte tables. */
1415	uint8_t idxPrefix; /* 0x3a, 0x17 */
1416	/** 3rd VEX/EVEX/XOP register.
1417	* Please use IEM_GET_EFFECTIVE_VVVV to access. */
1418	uint8_t uVex3rdReg; /* 0x3b, 0x18 */
1419	/** The VEX/EVEX/XOP length field. */
1420	uint8_t uVexLength; /* 0x3c, 0x19 */
1421	/** Additional EVEX stuff. */
1422	uint8_t fEvexStuff; /* 0x3d, 0x1a */
1423
1424	# ifndef IEM_WITH_CODE_TLB
1425	/** Explicit alignment padding. */
1426	uint8_t abAlignment2a[1]; /* 0x1b */
1427	# endif
1428	/** The FPU opcode (FOP). */
1429	uint16_t uFpuOpcode; /* 0x3e, 0x1c */
1430	# ifndef IEM_WITH_CODE_TLB
1431	/** Explicit alignment padding. */
1432	uint8_t abAlignment2b[2]; /* 0x1e */
1433	# endif
1434
1435	/** The opcode bytes. */
1436	uint8_t abOpcode[15]; /* 0x40, 0x20 */
1437	/** Explicit alignment padding. */
1438	# ifdef IEM_WITH_CODE_TLB
1439	//uint8_t abAlignment2c[0x4f - 0x4f]; /* 0x4f */
1440	# else
1441	uint8_t abAlignment2c[0x4f - 0x2f]; /* 0x2f */
1442	# endif
1443	#else /* IEM_WITH_OPAQUE_DECODER_STATE */
1444	uint8_t abOpaqueDecoder[0x4f - 0x8];
1445	#endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1446	/** @} */
1447
1448
1449	/** The number of active guest memory mappings. */
1450	uint8_t cActiveMappings; /* 0x4f, 0x4f */
1451
1452	/** Records for tracking guest memory mappings. */
1453	struct
1454	{
1455	/** The address of the mapped bytes. */
1456	R3R0PTRTYPE(void *) pv;
1457	/** The access flags (IEM_ACCESS_XXX).
1458	* IEM_ACCESS_INVALID if the entry is unused. */
1459	uint32_t fAccess;
1460	#if HC_ARCH_BITS == 64
1461	uint32_t u32Alignment4; /*< Alignment padding. /
1462	#endif
1463	} aMemMappings[3]; /* 0x50 LB 0x30 */
1464
1465	/** Locking records for the mapped memory. */
1466	union
1467	{
1468	PGMPAGEMAPLOCK Lock;
1469	uint64_t au64Padding[2];
1470	} aMemMappingLocks[3]; /* 0x80 LB 0x30 */
1471
1472	/** Bounce buffer info.
1473	* This runs in parallel to aMemMappings. */
1474	struct
1475	{
1476	/** The physical address of the first byte. */
1477	RTGCPHYS GCPhysFirst;
1478	/** The physical address of the second page. */
1479	RTGCPHYS GCPhysSecond;
1480	/** The number of bytes in the first page. */
1481	uint16_t cbFirst;
1482	/** The number of bytes in the second page. */
1483	uint16_t cbSecond;
1484	/** Whether it's unassigned memory. */
1485	bool fUnassigned;
1486	/** Explicit alignment padding. */
1487	bool afAlignment5[3];
1488	} aMemBbMappings[3]; /* 0xb0 LB 0x48 */
1489
1490	/** The flags of the current exception / interrupt. */
1491	uint32_t fCurXcpt; /* 0xf8 */
1492	/** The current exception / interrupt. */
1493	uint8_t uCurXcpt; /* 0xfc */
1494	/** Exception / interrupt recursion depth. */
1495	int8_t cXcptRecursions; /* 0xfb */
1496
1497	/** The next unused mapping index.
1498	* @todo try find room for this up with cActiveMappings. */
1499	uint8_t iNextMapping; /* 0xfd */
1500	uint8_t abAlignment7[1];
1501
1502	/** Bounce buffer storage.
1503	* This runs in parallel to aMemMappings and aMemBbMappings. */
1504	struct
1505	{
1506	uint8_t ab[512];
1507	} aBounceBuffers[3]; /* 0x100 LB 0x600 */
1508
1509
1510	/** Pointer set jump buffer - ring-3 context. */
1511	R3PTRTYPE(jmp_buf *) pJmpBufR3;
1512	/** Pointer set jump buffer - ring-0 context. */
1513	R0PTRTYPE(jmp_buf *) pJmpBufR0;
1514
1515	/** @todo Should move this near @a fCurXcpt later. */
1516	/** The CR2 for the current exception / interrupt. */
1517	uint64_t uCurXcptCr2;
1518	/** The error code for the current exception / interrupt. */
1519	uint32_t uCurXcptErr;
1520
1521	/** @name Statistics
1522	* @{ */
1523	/** The number of instructions we've executed. */
1524	uint32_t cInstructions;
1525	/** The number of potential exits. */
1526	uint32_t cPotentialExits;
1527	/** The number of bytes data or stack written (mostly for IEMExecOneEx).
1528	* This may contain uncommitted writes. */
1529	uint32_t cbWritten;
1530	/** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
1531	uint32_t cRetInstrNotImplemented;
1532	/** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
1533	uint32_t cRetAspectNotImplemented;
1534	/** Counts informational statuses returned (other than VINF_SUCCESS). */
1535	uint32_t cRetInfStatuses;
1536	/** Counts other error statuses returned. */
1537	uint32_t cRetErrStatuses;
1538	/** Number of times rcPassUp has been used. */
1539	uint32_t cRetPassUpStatus;
1540	/** Number of times RZ left with instruction commit pending for ring-3. */
1541	uint32_t cPendingCommit;
1542	/** Number of long jumps. */
1543	uint32_t cLongJumps;
1544	/** @} */
1545
1546	/** @name Target CPU information.
1547	* @{ */
1548	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
1549	/** The target CPU. */
1550	uint8_t uTargetCpu;
1551	#else
1552	uint8_t bTargetCpuPadding;
1553	#endif
1554	/** For selecting assembly works matching the target CPU EFLAGS behaviour, see
1555	* IEMTARGETCPU_EFL_BEHAVIOR_XXX for values, with the 1st entry for when no
1556	* native host support and the 2nd for when there is.
1557	*
1558	* The two values are typically indexed by a g_CpumHostFeatures bit.
1559	*
1560	* This is for instance used for the BSF & BSR instructions where AMD and
1561	* Intel CPUs produce different EFLAGS. */
1562	uint8_t aidxTargetCpuEflFlavour[2];
1563
1564	/** The CPU vendor. */
1565	CPUMCPUVENDOR enmCpuVendor;
1566	/** @} */
1567
1568	/** @name Host CPU information.
1569	* @{ */
1570	/** The CPU vendor. */
1571	CPUMCPUVENDOR enmHostCpuVendor;
1572	/** @} */
1573
1574	/** Counts RDMSR \#GP(0) LogRel(). */
1575	uint8_t cLogRelRdMsr;
1576	/** Counts WRMSR \#GP(0) LogRel(). */
1577	uint8_t cLogRelWrMsr;
1578	/** Alignment padding. */
1579	uint8_t abAlignment9[46];
1580
1581	/** @name Recompilation
1582	* @{ */
1583	/** Pointer to the current translation block.
1584	* This can either be one being executed or one being compiled. */
1585	R3PTRTYPE(PIEMTB) pCurTbR3;
1586	/** Fixed TB used for threaded recompilation.
1587	* This is allocated once with maxed-out sizes and re-used afterwards. */
1588	R3PTRTYPE(PIEMTB) pThrdCompileTbR3;
1589	/** Pointer to the ring-3 TB cache for this EMT. */
1590	R3PTRTYPE(PIEMTBCACHE) pTbCacheR3;
1591	/** The PC (RIP) at the start of pCurTbR3/pCurTbR0.
1592	* The TBs are based on physical addresses, so this is needed to correleated
1593	* RIP to opcode bytes stored in the TB (AMD-V / VT-x). */
1594	uint64_t uCurTbStartPc;
1595	/** Number of threaded TBs executed. */
1596	uint64_t cTbExecThreaded;
1597	/** Number of native TBs executed. */
1598	uint64_t cTbExecNative;
1599	/** Whether we need to check the opcode bytes for the current instruction.
1600	* This is set by a previous instruction if it modified memory or similar. */
1601	bool fTbCheckOpcodes;
1602	/** Indicates whether and how we just branched - IEMBRANCHED_F_XXX. */
1603	uint8_t fTbBranched;
1604	/** Set when GCPhysInstrBuf is updated because of a page crossing. */
1605	bool fTbCrossedPage;
1606	/** Whether to end the current TB. */
1607	bool fEndTb;
1608	/** Number of instructions before we need emit an IRQ check call again.
1609	* This helps making sure we don't execute too long w/o checking for
1610	* interrupts and immediately following instructions that may enable
1611	* interrupts (e.g. POPF, IRET, STI). With STI an additional hack is
1612	* required to make sure we check following the next instruction as well, see
1613	* fTbCurInstrIsSti. */
1614	uint8_t cInstrTillIrqCheck;
1615	/** Indicates that the current instruction is an STI. This is set by the
1616	* iemCImpl_sti code and subsequently cleared by the recompiler. */
1617	bool fTbCurInstrIsSti;
1618	/** The size of the IEMTB::pabOpcodes allocation in pThrdCompileTbR3. */
1619	uint16_t cbOpcodesAllocated;
1620	/** Spaced reserved for recompiler data / alignment. */
1621	bool afRecompilerStuff1[4];
1622	/** The virtual sync time at the last timer poll call. */
1623	uint32_t msRecompilerPollNow;
1624	/** The IEM_CIMPL_F_XXX mask for the current instruction. */
1625	uint32_t fTbCurInstr;
1626	/** The IEM_CIMPL_F_XXX mask for the previous instruction. */
1627	uint32_t fTbPrevInstr;
1628	/** Previous GCPhysInstrBuf value - only valid if fTbCrossedPage is set. */
1629	RTGCPHYS GCPhysInstrBufPrev;
1630	/** Copy of IEMCPU::GCPhysInstrBuf after decoding a branch instruction.
1631	* This is used together with fTbBranched and GCVirtTbBranchSrcBuf to determin
1632	* whether a branch instruction jumps to a new page or stays within the
1633	* current one. */
1634	RTGCPHYS GCPhysTbBranchSrcBuf;
1635	/** Copy of IEMCPU::uInstrBufPc after decoding a branch instruction. */
1636	uint64_t GCVirtTbBranchSrcBuf;
1637	/** Pointer to the ring-3 TB allocator for this EMT. */
1638	R3PTRTYPE(PIEMTBALLOCATOR) pTbAllocatorR3;
1639	/** Pointer to the ring-3 executable memory allocator for this EMT. */
1640	R3PTRTYPE(struct IEMEXECMEMALLOCATOR *) pExecMemAllocatorR3;
1641	/** Pointer to the native recompiler state for ring-3. */
1642	R3PTRTYPE(struct IEMRECOMPILERSTATE *) pNativeRecompilerStateR3;
1643	/** Alignment padding. */
1644	uint64_t auAlignment10[4];
1645	/** Statistics: Times TB execution was broken off before reaching the end. */
1646	STAMCOUNTER StatTbExecBreaks;
1647	/** Statistics: Times BltIn_CheckIrq breaks out of the TB. */
1648	STAMCOUNTER StatCheckIrqBreaks;
1649	/** Statistics: Times BltIn_CheckMode breaks out of the TB. */
1650	STAMCOUNTER StatCheckModeBreaks;
1651	/** Statistics: Times a post jump target check missed and had to find new TB. */
1652	STAMCOUNTER StatCheckBranchMisses;
1653	/** Statistics: Times a jump or page crossing required a TB with CS.LIM checking. */
1654	STAMCOUNTER StatCheckNeedCsLimChecking;
1655	/** Threaded TB statistics: Number of instructions per TB. */
1656	STAMPROFILE StatTbThreadedInstr;
1657	/** Threaded TB statistics: Number of calls per TB. */
1658	STAMPROFILE StatTbThreadedCalls;
1659	/** Native TB statistics: Native code size per TB. */
1660	STAMPROFILE StatTbNativeCode;
1661	/** Native TB statistics: Profiling native recompilation. */
1662	STAMPROFILE StatNativeRecompilation;
1663	/** @} */
1664
1665	/** Data TLB.
1666	* @remarks Must be 64-byte aligned. */
1667	IEMTLB DataTlb;
1668	/** Instruction TLB.
1669	* @remarks Must be 64-byte aligned. */
1670	IEMTLB CodeTlb;
1671
1672	/** Exception statistics. */
1673	STAMCOUNTER aStatXcpts[32];
1674	/** Interrupt statistics. */
1675	uint32_t aStatInts[256];
1676
1677	#if defined(VBOX_WITH_STATISTICS) && !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
1678	/** Instruction statistics for ring-0/raw-mode. */
1679	IEMINSTRSTATS StatsRZ;
1680	/** Instruction statistics for ring-3. */
1681	IEMINSTRSTATS StatsR3;
1682	#endif
1683	} IEMCPU;
1684	AssertCompileMemberOffset(IEMCPU, cActiveMappings, 0x4f);
1685	AssertCompileMemberAlignment(IEMCPU, aMemMappings, 16);
1686	AssertCompileMemberAlignment(IEMCPU, aMemMappingLocks, 16);
1687	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 64);
1688	AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
1689	AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
1690
1691	/** Pointer to the per-CPU IEM state. */
1692	typedef IEMCPU *PIEMCPU;
1693	/** Pointer to the const per-CPU IEM state. */
1694	typedef IEMCPU const *PCIEMCPU;
1695
1696
1697	/** @def IEM_GET_CTX
1698	* Gets the guest CPU context for the calling EMT.
1699	* @returns PCPUMCTX
1700	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1701	*/
1702	#define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
1703
1704	/** @def IEM_CTX_ASSERT
1705	* Asserts that the @a a_fExtrnMbz is present in the CPU context.
1706	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1707	* @param a_fExtrnMbz The mask of CPUMCTX_EXTRN_XXX flags that must be zero.
1708	*/
1709	#define IEM_CTX_ASSERT(a_pVCpu, a_fExtrnMbz) \
1710	AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
1711	("fExtrn=%#RX64 & fExtrnMbz=%#RX64 -> %#RX64\n", \
1712	(a_pVCpu)->cpum.GstCtx.fExtrn, (a_fExtrnMbz), (a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz) ))
1713
1714	/** @def IEM_CTX_IMPORT_RET
1715	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
1716	*
1717	* Will call the keep to import the bits as needed.
1718	*
1719	* Returns on import failure.
1720	*
1721	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1722	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
1723	*/
1724	#define IEM_CTX_IMPORT_RET(a_pVCpu, a_fExtrnImport) \
1725	do { \
1726	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
1727	{ /* likely */ } \
1728	else \
1729	{ \
1730	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
1731	AssertRCReturn(rcCtxImport, rcCtxImport); \
1732	} \
1733	} while (0)
1734
1735	/** @def IEM_CTX_IMPORT_NORET
1736	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
1737	*
1738	* Will call the keep to import the bits as needed.
1739	*
1740	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1741	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
1742	*/
1743	#define IEM_CTX_IMPORT_NORET(a_pVCpu, a_fExtrnImport) \
1744	do { \
1745	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
1746	{ /* likely */ } \
1747	else \
1748	{ \
1749	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
1750	AssertLogRelRC(rcCtxImport); \
1751	} \
1752	} while (0)
1753
1754	/** @def IEM_CTX_IMPORT_JMP
1755	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
1756	*
1757	* Will call the keep to import the bits as needed.
1758	*
1759	* Jumps on import failure.
1760	*
1761	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1762	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
1763	*/
1764	#define IEM_CTX_IMPORT_JMP(a_pVCpu, a_fExtrnImport) \
1765	do { \
1766	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
1767	{ /* likely */ } \
1768	else \
1769	{ \
1770	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
1771	AssertRCStmt(rcCtxImport, IEM_DO_LONGJMP(pVCpu, rcCtxImport)); \
1772	} \
1773	} while (0)
1774
1775
1776
1777	/** @def IEM_GET_TARGET_CPU
1778	* Gets the current IEMTARGETCPU value.
1779	* @returns IEMTARGETCPU value.
1780	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1781	*/
1782	#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
1783	# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
1784	#else
1785	# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
1786	#endif
1787
1788	/** @def IEM_GET_INSTR_LEN
1789	* Gets the instruction length. */
1790	#ifdef IEM_WITH_CODE_TLB
1791	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
1792	#else
1793	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
1794	#endif
1795
1796	/** @def IEM_TRY_SETJMP
1797	* Wrapper around setjmp / try, hiding all the ugly differences.
1798	*
1799	* @note Use with extreme care as this is a fragile macro.
1800	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
1801	* @param a_rcTarget The variable that should receive the status code in case
1802	* of a longjmp/throw.
1803	*/
1804	/** @def IEM_TRY_SETJMP_AGAIN
1805	* For when setjmp / try is used again in the same variable scope as a previous
1806	* IEM_TRY_SETJMP invocation.
1807	*/
1808	/** @def IEM_CATCH_LONGJMP_BEGIN
1809	* Start wrapper for catch / setjmp-else.
1810	*
1811	* This will set up a scope.
1812	*
1813	* @note Use with extreme care as this is a fragile macro.
1814	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
1815	* @param a_rcTarget The variable that should receive the status code in case
1816	* of a longjmp/throw.
1817	*/
1818	/** @def IEM_CATCH_LONGJMP_END
1819	* End wrapper for catch / setjmp-else.
1820	*
1821	* This will close the scope set up by IEM_CATCH_LONGJMP_BEGIN and clean up the
1822	* state.
1823	*
1824	* @note Use with extreme care as this is a fragile macro.
1825	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
1826	*/
1827	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
1828	# ifdef IEM_WITH_THROW_CATCH
1829	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
1830	a_rcTarget = VINF_SUCCESS; \
1831	try
1832	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
1833	IEM_TRY_SETJMP(a_pVCpu, a_rcTarget)
1834	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
1835	catch (int rcThrown) \
1836	{ \
1837	a_rcTarget = rcThrown
1838	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
1839	} \
1840	((void)0)
1841	# else /* !IEM_WITH_THROW_CATCH */
1842	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
1843	jmp_buf JmpBuf; \
1844	jmp_buf * volatile pSavedJmpBuf = pVCpu->iem.s.CTX_SUFF(pJmpBuf); \
1845	pVCpu->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
1846	if ((rcStrict = setjmp(JmpBuf)) == 0)
1847	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
1848	pSavedJmpBuf = pVCpu->iem.s.CTX_SUFF(pJmpBuf); \
1849	pVCpu->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
1850	if ((rcStrict = setjmp(JmpBuf)) == 0)
1851	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
1852	else \
1853	{ \
1854	((void)0)
1855	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
1856	} \
1857	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = pSavedJmpBuf
1858	# endif /* !IEM_WITH_THROW_CATCH */
1859	#endif /* IEM_WITH_SETJMP */
1860
1861
1862	/**
1863	* Shared per-VM IEM data.
1864	*/
1865	typedef struct IEM
1866	{
1867	/** The VMX APIC-access page handler type. */
1868	PGMPHYSHANDLERTYPE hVmxApicAccessPage;
1869	#ifndef VBOX_WITHOUT_CPUID_HOST_CALL
1870	/** Set if the CPUID host call functionality is enabled. */
1871	bool fCpuIdHostCall;
1872	#endif
1873	} IEM;
1874
1875
1876
1877	/** @name IEM_ACCESS_XXX - Access details.
1878	* @{ */
1879	#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
1880	#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
1881	#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
1882	#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
1883	#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
1884	#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
1885	#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
1886	#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
1887	#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
1888	#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
1889	/** The writes are partial, so if initialize the bounce buffer with the
1890	* orignal RAM content. */
1891	#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
1892	/** Used in aMemMappings to indicate that the entry is bounce buffered. */
1893	#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
1894	/** Bounce buffer with ring-3 write pending, first page. */
1895	#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
1896	/** Bounce buffer with ring-3 write pending, second page. */
1897	#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
1898	/** Not locked, accessed via the TLB. */
1899	#define IEM_ACCESS_NOT_LOCKED UINT32_C(0x00001000)
1900	/** Valid bit mask. */
1901	#define IEM_ACCESS_VALID_MASK UINT32_C(0x00001fff)
1902	/** Shift count for the TLB flags (upper word). */
1903	#define IEM_ACCESS_SHIFT_TLB_FLAGS 16
1904
1905	/** Read+write data alias. */
1906	#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
1907	/** Write data alias. */
1908	#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
1909	/** Read data alias. */
1910	#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_DATA)
1911	/** Instruction fetch alias. */
1912	#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_WHAT_CODE)
1913	/** Stack write alias. */
1914	#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
1915	/** Stack read alias. */
1916	#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_STACK)
1917	/** Stack read+write alias. */
1918	#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
1919	/** Read system table alias. */
1920	#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_SYS)
1921	/** Read+write system table alias. */
1922	#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_SYS)
1923	/** @} */
1924
1925	/** @name Prefix constants (IEMCPU::fPrefixes)
1926	* @{ */
1927	#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /*< CS segment prefix (0x2e). /
1928	#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /*< SS segment prefix (0x36). /
1929	#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /*< DS segment prefix (0x3e). /
1930	#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /*< ES segment prefix (0x26). /
1931	#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /*< FS segment prefix (0x64). /
1932	#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /*< GS segment prefix (0x65). /
1933	#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
1934
1935	#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /*< Operand size prefix (0x66). /
1936	#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /*< REX.W prefix (0x48-0x4f). /
1937	#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /*< Address size prefix (0x67). /
1938
1939	#define IEM_OP_PRF_LOCK RT_BIT_32(16) /*< Lock prefix (0xf0). /
1940	#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /*< Repeat-not-zero prefix (0xf2). /
1941	#define IEM_OP_PRF_REPZ RT_BIT_32(18) /*< Repeat-if-zero prefix (0xf3). /
1942
1943	#define IEM_OP_PRF_REX RT_BIT_32(24) /*< Any REX prefix (0x40-0x4f). /
1944	#define IEM_OP_PRF_REX_R RT_BIT_32(25) /*< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). /
1945	#define IEM_OP_PRF_REX_B RT_BIT_32(26) /*< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). /
1946	#define IEM_OP_PRF_REX_X RT_BIT_32(27) /*< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). /
1947	/** Mask with all the REX prefix flags.
1948	* This is generally for use when needing to undo the REX prefixes when they
1949	* are followed legacy prefixes and therefore does not immediately preceed
1950	* the first opcode byte.
1951	* For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
1952	#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX \| IEM_OP_PRF_REX_R \| IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X \| IEM_OP_PRF_SIZE_REX_W )
1953
1954	#define IEM_OP_PRF_VEX RT_BIT_32(28) /*< Indiciates VEX prefix. /
1955	#define IEM_OP_PRF_EVEX RT_BIT_32(29) /*< Indiciates EVEX prefix. /
1956	#define IEM_OP_PRF_XOP RT_BIT_32(30) /*< Indiciates XOP prefix. /
1957	/** @} */
1958
1959	/** @name IEMOPFORM_XXX - Opcode forms
1960	* @note These are ORed together with IEMOPHINT_XXX.
1961	* @{ */
1962	/** ModR/M: reg, r/m */
1963	#define IEMOPFORM_RM 0
1964	/** ModR/M: reg, r/m (register) */
1965	#define IEMOPFORM_RM_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
1966	/** ModR/M: reg, r/m (memory) */
1967	#define IEMOPFORM_RM_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
1968	/** ModR/M: reg, r/m */
1969	#define IEMOPFORM_RMI 1
1970	/** ModR/M: reg, r/m (register) */
1971	#define IEMOPFORM_RMI_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
1972	/** ModR/M: reg, r/m (memory) */
1973	#define IEMOPFORM_RMI_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
1974	/** ModR/M: r/m, reg */
1975	#define IEMOPFORM_MR 2
1976	/** ModR/M: r/m (register), reg */
1977	#define IEMOPFORM_MR_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
1978	/** ModR/M: r/m (memory), reg */
1979	#define IEMOPFORM_MR_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
1980	/** ModR/M: r/m, reg */
1981	#define IEMOPFORM_MRI 3
1982	/** ModR/M: r/m (register), reg */
1983	#define IEMOPFORM_MRI_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
1984	/** ModR/M: r/m (memory), reg */
1985	#define IEMOPFORM_MRI_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
1986	/** ModR/M: r/m only */
1987	#define IEMOPFORM_M 4
1988	/** ModR/M: r/m only (register). */
1989	#define IEMOPFORM_M_REG (IEMOPFORM_M \| IEMOPFORM_MOD3)
1990	/** ModR/M: r/m only (memory). */
1991	#define IEMOPFORM_M_MEM (IEMOPFORM_M \| IEMOPFORM_NOT_MOD3)
1992	/** ModR/M: reg only */
1993	#define IEMOPFORM_R 5
1994
1995	/** VEX+ModR/M: reg, r/m */
1996	#define IEMOPFORM_VEX_RM 8
1997	/** VEX+ModR/M: reg, r/m (register) */
1998	#define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM \| IEMOPFORM_MOD3)
1999	/** VEX+ModR/M: reg, r/m (memory) */
2000	#define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM \| IEMOPFORM_NOT_MOD3)
2001	/** VEX+ModR/M: r/m, reg */
2002	#define IEMOPFORM_VEX_MR 9
2003	/** VEX+ModR/M: r/m (register), reg */
2004	#define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR \| IEMOPFORM_MOD3)
2005	/** VEX+ModR/M: r/m (memory), reg */
2006	#define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR \| IEMOPFORM_NOT_MOD3)
2007	/** VEX+ModR/M: r/m only */
2008	#define IEMOPFORM_VEX_M 10
2009	/** VEX+ModR/M: r/m only (register). */
2010	#define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M \| IEMOPFORM_MOD3)
2011	/** VEX+ModR/M: r/m only (memory). */
2012	#define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M \| IEMOPFORM_NOT_MOD3)
2013	/** VEX+ModR/M: reg only */
2014	#define IEMOPFORM_VEX_R 11
2015	/** VEX+ModR/M: reg, vvvv, r/m */
2016	#define IEMOPFORM_VEX_RVM 12
2017	/** VEX+ModR/M: reg, vvvv, r/m (register). */
2018	#define IEMOPFORM_VEX_RVM_REG (IEMOPFORM_VEX_RVM \| IEMOPFORM_MOD3)
2019	/** VEX+ModR/M: reg, vvvv, r/m (memory). */
2020	#define IEMOPFORM_VEX_RVM_MEM (IEMOPFORM_VEX_RVM \| IEMOPFORM_NOT_MOD3)
2021	/** VEX+ModR/M: reg, r/m, vvvv */
2022	#define IEMOPFORM_VEX_RMV 13
2023	/** VEX+ModR/M: reg, r/m, vvvv (register). */
2024	#define IEMOPFORM_VEX_RMV_REG (IEMOPFORM_VEX_RMV \| IEMOPFORM_MOD3)
2025	/** VEX+ModR/M: reg, r/m, vvvv (memory). */
2026	#define IEMOPFORM_VEX_RMV_MEM (IEMOPFORM_VEX_RMV \| IEMOPFORM_NOT_MOD3)
2027	/** VEX+ModR/M: reg, r/m, imm8 */
2028	#define IEMOPFORM_VEX_RMI 14
2029	/** VEX+ModR/M: reg, r/m, imm8 (register). */
2030	#define IEMOPFORM_VEX_RMI_REG (IEMOPFORM_VEX_RMI \| IEMOPFORM_MOD3)
2031	/** VEX+ModR/M: reg, r/m, imm8 (memory). */
2032	#define IEMOPFORM_VEX_RMI_MEM (IEMOPFORM_VEX_RMI \| IEMOPFORM_NOT_MOD3)
2033	/** VEX+ModR/M: r/m, vvvv, reg */
2034	#define IEMOPFORM_VEX_MVR 15
2035	/** VEX+ModR/M: r/m, vvvv, reg (register) */
2036	#define IEMOPFORM_VEX_MVR_REG (IEMOPFORM_VEX_MVR \| IEMOPFORM_MOD3)
2037	/** VEX+ModR/M: r/m, vvvv, reg (memory) */
2038	#define IEMOPFORM_VEX_MVR_MEM (IEMOPFORM_VEX_MVR \| IEMOPFORM_NOT_MOD3)
2039	/** VEX+ModR/M+/n: vvvv, r/m */
2040	#define IEMOPFORM_VEX_VM 16
2041	/** VEX+ModR/M+/n: vvvv, r/m (register) */
2042	#define IEMOPFORM_VEX_VM_REG (IEMOPFORM_VEX_VM \| IEMOPFORM_MOD3)
2043	/** VEX+ModR/M+/n: vvvv, r/m (memory) */
2044	#define IEMOPFORM_VEX_VM_MEM (IEMOPFORM_VEX_VM \| IEMOPFORM_NOT_MOD3)
2045
2046	/** Fixed register instruction, no R/M. */
2047	#define IEMOPFORM_FIXED 32
2048
2049	/** The r/m is a register. */
2050	#define IEMOPFORM_MOD3 RT_BIT_32(8)
2051	/** The r/m is a memory access. */
2052	#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
2053	/** @} */
2054
2055	/** @name IEMOPHINT_XXX - Additional Opcode Hints
2056	* @note These are ORed together with IEMOPFORM_XXX.
2057	* @{ */
2058	/** Ignores the operand size prefix (66h). */
2059	#define IEMOPHINT_IGNORES_OZ_PFX RT_BIT_32(10)
2060	/** Ignores REX.W (aka WIG). */
2061	#define IEMOPHINT_IGNORES_REXW RT_BIT_32(11)
2062	/** Both the operand size prefixes (66h + REX.W) are ignored. */
2063	#define IEMOPHINT_IGNORES_OP_SIZES (IEMOPHINT_IGNORES_OZ_PFX \| IEMOPHINT_IGNORES_REXW)
2064	/** Allowed with the lock prefix. */
2065	#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
2066	/** The VEX.L value is ignored (aka LIG). */
2067	#define IEMOPHINT_VEX_L_IGNORED RT_BIT_32(12)
2068	/** The VEX.L value must be zero (i.e. 128-bit width only). */
2069	#define IEMOPHINT_VEX_L_ZERO RT_BIT_32(13)
2070	/** The VEX.V value must be zero. */
2071	#define IEMOPHINT_VEX_V_ZERO RT_BIT_32(14)
2072
2073	/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
2074	#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
2075	/** @} */
2076
2077	/**
2078	* Possible hardware task switch sources.
2079	*/
2080	typedef enum IEMTASKSWITCH
2081	{
2082	/** Task switch caused by an interrupt/exception. */
2083	IEMTASKSWITCH_INT_XCPT = 1,
2084	/** Task switch caused by a far CALL. */
2085	IEMTASKSWITCH_CALL,
2086	/** Task switch caused by a far JMP. */
2087	IEMTASKSWITCH_JUMP,
2088	/** Task switch caused by an IRET. */
2089	IEMTASKSWITCH_IRET
2090	} IEMTASKSWITCH;
2091	AssertCompileSize(IEMTASKSWITCH, 4);
2092
2093	/**
2094	* Possible CrX load (write) sources.
2095	*/
2096	typedef enum IEMACCESSCRX
2097	{
2098	/** CrX access caused by 'mov crX' instruction. */
2099	IEMACCESSCRX_MOV_CRX,
2100	/** CrX (CR0) write caused by 'lmsw' instruction. */
2101	IEMACCESSCRX_LMSW,
2102	/** CrX (CR0) write caused by 'clts' instruction. */
2103	IEMACCESSCRX_CLTS,
2104	/** CrX (CR0) read caused by 'smsw' instruction. */
2105	IEMACCESSCRX_SMSW
2106	} IEMACCESSCRX;
2107
2108	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2109	/** @name IEM_SLAT_FAIL_XXX - Second-level address translation failure information.
2110	*
2111	* These flags provide further context to SLAT page-walk failures that could not be
2112	* determined by PGM (e.g, PGM is not privy to memory access permissions).
2113	*
2114	* @{
2115	*/
2116	/** Translating a nested-guest linear address failed accessing a nested-guest
2117	* physical address. */
2118	# define IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR RT_BIT_32(0)
2119	/** Translating a nested-guest linear address failed accessing a
2120	* paging-structure entry or updating accessed/dirty bits. */
2121	# define IEM_SLAT_FAIL_LINEAR_TO_PAGE_TABLE RT_BIT_32(1)
2122	/** @} */
2123
2124	DECLCALLBACK(FNPGMPHYSHANDLER) iemVmxApicAccessPageHandler;
2125	# ifndef IN_RING3
2126	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) iemVmxApicAccessPagePfHandler;
2127	# endif
2128	#endif
2129
2130	/**
2131	* Indicates to the verifier that the given flag set is undefined.
2132	*
2133	* Can be invoked again to add more flags.
2134	*
2135	* This is a NOOP if the verifier isn't compiled in.
2136	*
2137	* @note We're temporarily keeping this until code is converted to new
2138	* disassembler style opcode handling.
2139	*/
2140	#define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
2141
2142
2143	/** @def IEM_DECL_IMPL_TYPE
2144	* For typedef'ing an instruction implementation function.
2145	*
2146	* @param a_RetType The return type.
2147	* @param a_Name The name of the type.
2148	* @param a_ArgList The argument list enclosed in parentheses.
2149	*/
2150
2151	/** @def IEM_DECL_IMPL_DEF
2152	* For defining an instruction implementation function.
2153	*
2154	* @param a_RetType The return type.
2155	* @param a_Name The name of the type.
2156	* @param a_ArgList The argument list enclosed in parentheses.
2157	*/
2158
2159	#if defined(__GNUC__) && defined(RT_ARCH_X86)
2160	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2161	__attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
2162	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2163	__attribute__((__fastcall__, __nothrow__)) DECL_HIDDEN_ONLY(a_RetType) a_Name a_ArgList
2164	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2165	__attribute__((__fastcall__, __nothrow__)) DECL_HIDDEN_ONLY(a_RetType) a_Name a_ArgList
2166
2167	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
2168	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2169	a_RetType (__fastcall a_Name) a_ArgList
2170	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2171	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
2172	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2173	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
2174
2175	#elif __cplusplus >= 201700 /* P0012R1 support */
2176	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2177	a_RetType (VBOXCALL a_Name) a_ArgList RT_NOEXCEPT
2178	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2179	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList RT_NOEXCEPT
2180	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2181	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList RT_NOEXCEPT
2182
2183	#else
2184	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2185	a_RetType (VBOXCALL a_Name) a_ArgList
2186	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2187	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList
2188	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2189	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList
2190
2191	#endif
2192
2193	/** Defined in IEMAllAImplC.cpp but also used by IEMAllAImplA.asm. */
2194	RT_C_DECLS_BEGIN
2195	extern uint8_t const g_afParity[256];
2196	RT_C_DECLS_END
2197
2198
2199	/** @name Arithmetic assignment operations on bytes (binary).
2200	* @{ */
2201	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU8, (uint8_t pu8Dst, uint8_t u8Src, uint32_t pEFlags));
2202	typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
2203	FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
2204	FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
2205	FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
2206	FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
2207	FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
2208	FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
2209	FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
2210	/** @} */
2211
2212	/** @name Arithmetic assignment operations on words (binary).
2213	* @{ */
2214	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU16, (uint16_t pu16Dst, uint16_t u16Src, uint32_t pEFlags));
2215	typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
2216	FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
2217	FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
2218	FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
2219	FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
2220	FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
2221	FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
2222	FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
2223	/** @} */
2224
2225	/** @name Arithmetic assignment operations on double words (binary).
2226	* @{ */
2227	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU32, (uint32_t pu32Dst, uint32_t u32Src, uint32_t pEFlags));
2228	typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
2229	FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
2230	FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
2231	FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
2232	FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
2233	FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
2234	FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
2235	FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
2236	FNIEMAIMPLBINU32 iemAImpl_blsi_u32, iemAImpl_blsi_u32_fallback;
2237	FNIEMAIMPLBINU32 iemAImpl_blsr_u32, iemAImpl_blsr_u32_fallback;
2238	FNIEMAIMPLBINU32 iemAImpl_blsmsk_u32, iemAImpl_blsmsk_u32_fallback;
2239	/** @} */
2240
2241	/** @name Arithmetic assignment operations on quad words (binary).
2242	* @{ */
2243	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU64, (uint64_t pu64Dst, uint64_t u64Src, uint32_t pEFlags));
2244	typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
2245	FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
2246	FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
2247	FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
2248	FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
2249	FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
2250	FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
2251	FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
2252	FNIEMAIMPLBINU64 iemAImpl_blsi_u64, iemAImpl_blsi_u64_fallback;
2253	FNIEMAIMPLBINU64 iemAImpl_blsr_u64, iemAImpl_blsr_u64_fallback;
2254	FNIEMAIMPLBINU64 iemAImpl_blsmsk_u64, iemAImpl_blsmsk_u64_fallback;
2255	/** @} */
2256
2257	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINROU8,(uint8_t const pu8Dst, uint8_t u8Src, uint32_t pEFlags));
2258	typedef FNIEMAIMPLBINROU8 *PFNIEMAIMPLBINROU8;
2259	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINROU16,(uint16_t const pu16Dst, uint16_t u16Src, uint32_t pEFlags));
2260	typedef FNIEMAIMPLBINROU16 *PFNIEMAIMPLBINROU16;
2261	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINROU32,(uint32_t const pu32Dst, uint32_t u32Src, uint32_t pEFlags));
2262	typedef FNIEMAIMPLBINROU32 *PFNIEMAIMPLBINROU32;
2263	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINROU64,(uint64_t const pu64Dst, uint64_t u64Src, uint32_t pEFlags));
2264	typedef FNIEMAIMPLBINROU64 *PFNIEMAIMPLBINROU64;
2265
2266	/** @name Compare operations (thrown in with the binary ops).
2267	* @{ */
2268	FNIEMAIMPLBINROU8 iemAImpl_cmp_u8;
2269	FNIEMAIMPLBINROU16 iemAImpl_cmp_u16;
2270	FNIEMAIMPLBINROU32 iemAImpl_cmp_u32;
2271	FNIEMAIMPLBINROU64 iemAImpl_cmp_u64;
2272	/** @} */
2273
2274	/** @name Test operations (thrown in with the binary ops).
2275	* @{ */
2276	FNIEMAIMPLBINROU8 iemAImpl_test_u8;
2277	FNIEMAIMPLBINROU16 iemAImpl_test_u16;
2278	FNIEMAIMPLBINROU32 iemAImpl_test_u32;
2279	FNIEMAIMPLBINROU64 iemAImpl_test_u64;
2280	/** @} */
2281
2282	/** @name Bit operations operations (thrown in with the binary ops).
2283	* @{ */
2284	FNIEMAIMPLBINROU16 iemAImpl_bt_u16;
2285	FNIEMAIMPLBINROU32 iemAImpl_bt_u32;
2286	FNIEMAIMPLBINROU64 iemAImpl_bt_u64;
2287	FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
2288	FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
2289	FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
2290	FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
2291	FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
2292	FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
2293	FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
2294	FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
2295	FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
2296	/** @} */
2297
2298	/** @name Arithmetic three operand operations on double words (binary).
2299	* @{ */
2300	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32, (uint32_t pu32Dst, uint32_t u32Src1, uint32_t u32Src2, uint32_t pEFlags));
2301	typedef FNIEMAIMPLBINVEXU32 *PFNIEMAIMPLBINVEXU32;
2302	FNIEMAIMPLBINVEXU32 iemAImpl_andn_u32, iemAImpl_andn_u32_fallback;
2303	FNIEMAIMPLBINVEXU32 iemAImpl_bextr_u32, iemAImpl_bextr_u32_fallback;
2304	FNIEMAIMPLBINVEXU32 iemAImpl_bzhi_u32, iemAImpl_bzhi_u32_fallback;
2305	/** @} */
2306
2307	/** @name Arithmetic three operand operations on quad words (binary).
2308	* @{ */
2309	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64, (uint64_t pu64Dst, uint64_t u64Src1, uint64_t u64Src2, uint32_t pEFlags));
2310	typedef FNIEMAIMPLBINVEXU64 *PFNIEMAIMPLBINVEXU64;
2311	FNIEMAIMPLBINVEXU64 iemAImpl_andn_u64, iemAImpl_andn_u64_fallback;
2312	FNIEMAIMPLBINVEXU64 iemAImpl_bextr_u64, iemAImpl_bextr_u64_fallback;
2313	FNIEMAIMPLBINVEXU64 iemAImpl_bzhi_u64, iemAImpl_bzhi_u64_fallback;
2314	/** @} */
2315
2316	/** @name Arithmetic three operand operations on double words w/o EFLAGS (binary).
2317	* @{ */
2318	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32NOEFL, (uint32_t *pu32Dst, uint32_t u32Src1, uint32_t u32Src2));
2319	typedef FNIEMAIMPLBINVEXU32NOEFL *PFNIEMAIMPLBINVEXU32NOEFL;
2320	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pdep_u32, iemAImpl_pdep_u32_fallback;
2321	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pext_u32, iemAImpl_pext_u32_fallback;
2322	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_sarx_u32, iemAImpl_sarx_u32_fallback;
2323	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shlx_u32, iemAImpl_shlx_u32_fallback;
2324	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shrx_u32, iemAImpl_shrx_u32_fallback;
2325	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_rorx_u32;
2326	/** @} */
2327
2328	/** @name Arithmetic three operand operations on quad words w/o EFLAGS (binary).
2329	* @{ */
2330	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64NOEFL, (uint64_t *pu64Dst, uint64_t u64Src1, uint64_t u64Src2));
2331	typedef FNIEMAIMPLBINVEXU64NOEFL *PFNIEMAIMPLBINVEXU64NOEFL;
2332	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pdep_u64, iemAImpl_pdep_u64_fallback;
2333	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pext_u64, iemAImpl_pext_u64_fallback;
2334	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_sarx_u64, iemAImpl_sarx_u64_fallback;
2335	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shlx_u64, iemAImpl_shlx_u64_fallback;
2336	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shrx_u64, iemAImpl_shrx_u64_fallback;
2337	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_rorx_u64;
2338	/** @} */
2339
2340	/** @name MULX 32-bit and 64-bit.
2341	* @{ */
2342	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU32, (uint32_t puDst1, uint32_t puDst2, uint32_t uSrc1, uint32_t uSrc2));
2343	typedef FNIEMAIMPLMULXVEXU32 *PFNIEMAIMPLMULXVEXU32;
2344	FNIEMAIMPLMULXVEXU32 iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback;
2345
2346	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU64, (uint64_t puDst1, uint64_t puDst2, uint64_t uSrc1, uint64_t uSrc2));
2347	typedef FNIEMAIMPLMULXVEXU64 *PFNIEMAIMPLMULXVEXU64;
2348	FNIEMAIMPLMULXVEXU64 iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback;
2349	/** @} */
2350
2351
2352	/** @name Exchange memory with register operations.
2353	* @{ */
2354	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_locked, (uint8_t pu8Mem, uint8_t pu8Reg));
2355	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_locked,(uint16_t pu16Mem, uint16_t pu16Reg));
2356	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_locked,(uint32_t pu32Mem, uint32_t pu32Reg));
2357	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_locked,(uint64_t pu64Mem, uint64_t pu64Reg));
2358	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_unlocked, (uint8_t pu8Mem, uint8_t pu8Reg));
2359	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_unlocked,(uint16_t pu16Mem, uint16_t pu16Reg));
2360	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_unlocked,(uint32_t pu32Mem, uint32_t pu32Reg));
2361	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_unlocked,(uint64_t pu64Mem, uint64_t pu64Reg));
2362	/** @} */
2363
2364	/** @name Exchange and add operations.
2365	* @{ */
2366	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
2367	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
2368	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
2369	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
2370	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
2371	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
2372	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
2373	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
2374	/** @} */
2375
2376	/** @name Compare and exchange.
2377	* @{ */
2378	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
2379	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
2380	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
2381	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
2382	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
2383	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
2384	#if ARCH_BITS == 32
2385	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
2386	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
2387	#else
2388	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
2389	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
2390	#endif
2391	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
2392	uint32_t *pEFlags));
2393	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
2394	uint32_t *pEFlags));
2395	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
2396	uint32_t *pEFlags));
2397	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
2398	uint32_t *pEFlags));
2399	#ifndef RT_ARCH_ARM64
2400	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
2401	PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
2402	#endif
2403	/** @} */
2404
2405	/** @name Memory ordering
2406	* @{ */
2407	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
2408	typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
2409	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
2410	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
2411	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
2412	#ifndef RT_ARCH_ARM64
2413	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
2414	#endif
2415	/** @} */
2416
2417	/** @name Double precision shifts
2418	* @{ */
2419	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t pEFlags));
2420	typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
2421	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t pEFlags));
2422	typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
2423	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t pEFlags));
2424	typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
2425	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16, iemAImpl_shld_u16_amd, iemAImpl_shld_u16_intel;
2426	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32, iemAImpl_shld_u32_amd, iemAImpl_shld_u32_intel;
2427	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64, iemAImpl_shld_u64_amd, iemAImpl_shld_u64_intel;
2428	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16, iemAImpl_shrd_u16_amd, iemAImpl_shrd_u16_intel;
2429	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32, iemAImpl_shrd_u32_amd, iemAImpl_shrd_u32_intel;
2430	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64, iemAImpl_shrd_u64_amd, iemAImpl_shrd_u64_intel;
2431	/** @} */
2432
2433
2434	/** @name Bit search operations (thrown in with the binary ops).
2435	* @{ */
2436	FNIEMAIMPLBINU16 iemAImpl_bsf_u16, iemAImpl_bsf_u16_amd, iemAImpl_bsf_u16_intel;
2437	FNIEMAIMPLBINU32 iemAImpl_bsf_u32, iemAImpl_bsf_u32_amd, iemAImpl_bsf_u32_intel;
2438	FNIEMAIMPLBINU64 iemAImpl_bsf_u64, iemAImpl_bsf_u64_amd, iemAImpl_bsf_u64_intel;
2439	FNIEMAIMPLBINU16 iemAImpl_bsr_u16, iemAImpl_bsr_u16_amd, iemAImpl_bsr_u16_intel;
2440	FNIEMAIMPLBINU32 iemAImpl_bsr_u32, iemAImpl_bsr_u32_amd, iemAImpl_bsr_u32_intel;
2441	FNIEMAIMPLBINU64 iemAImpl_bsr_u64, iemAImpl_bsr_u64_amd, iemAImpl_bsr_u64_intel;
2442	FNIEMAIMPLBINU16 iemAImpl_lzcnt_u16, iemAImpl_lzcnt_u16_amd, iemAImpl_lzcnt_u16_intel;
2443	FNIEMAIMPLBINU32 iemAImpl_lzcnt_u32, iemAImpl_lzcnt_u32_amd, iemAImpl_lzcnt_u32_intel;
2444	FNIEMAIMPLBINU64 iemAImpl_lzcnt_u64, iemAImpl_lzcnt_u64_amd, iemAImpl_lzcnt_u64_intel;
2445	FNIEMAIMPLBINU16 iemAImpl_tzcnt_u16, iemAImpl_tzcnt_u16_amd, iemAImpl_tzcnt_u16_intel;
2446	FNIEMAIMPLBINU32 iemAImpl_tzcnt_u32, iemAImpl_tzcnt_u32_amd, iemAImpl_tzcnt_u32_intel;
2447	FNIEMAIMPLBINU64 iemAImpl_tzcnt_u64, iemAImpl_tzcnt_u64_amd, iemAImpl_tzcnt_u64_intel;
2448	FNIEMAIMPLBINU16 iemAImpl_popcnt_u16, iemAImpl_popcnt_u16_fallback;
2449	FNIEMAIMPLBINU32 iemAImpl_popcnt_u32, iemAImpl_popcnt_u32_fallback;
2450	FNIEMAIMPLBINU64 iemAImpl_popcnt_u64, iemAImpl_popcnt_u64_fallback;
2451	/** @} */
2452
2453	/** @name Signed multiplication operations (thrown in with the binary ops).
2454	* @{ */
2455	FNIEMAIMPLBINU16 iemAImpl_imul_two_u16, iemAImpl_imul_two_u16_amd, iemAImpl_imul_two_u16_intel;
2456	FNIEMAIMPLBINU32 iemAImpl_imul_two_u32, iemAImpl_imul_two_u32_amd, iemAImpl_imul_two_u32_intel;
2457	FNIEMAIMPLBINU64 iemAImpl_imul_two_u64, iemAImpl_imul_two_u64_amd, iemAImpl_imul_two_u64_intel;
2458	/** @} */
2459
2460	/** @name Arithmetic assignment operations on bytes (unary).
2461	* @{ */
2462	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t pu8Dst, uint32_t pEFlags));
2463	typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
2464	FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
2465	FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
2466	FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
2467	FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
2468	/** @} */
2469
2470	/** @name Arithmetic assignment operations on words (unary).
2471	* @{ */
2472	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t pu16Dst, uint32_t pEFlags));
2473	typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
2474	FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
2475	FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
2476	FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
2477	FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
2478	/** @} */
2479
2480	/** @name Arithmetic assignment operations on double words (unary).
2481	* @{ */
2482	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t pu32Dst, uint32_t pEFlags));
2483	typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
2484	FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
2485	FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
2486	FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
2487	FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
2488	/** @} */
2489
2490	/** @name Arithmetic assignment operations on quad words (unary).
2491	* @{ */
2492	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t pu64Dst, uint32_t pEFlags));
2493	typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
2494	FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
2495	FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
2496	FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
2497	FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
2498	/** @} */
2499
2500
2501	/** @name Shift operations on bytes (Group 2).
2502	* @{ */
2503	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU8,(uint8_t pu8Dst, uint8_t cShift, uint32_t pEFlags));
2504	typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
2505	FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8, iemAImpl_rol_u8_amd, iemAImpl_rol_u8_intel;
2506	FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8, iemAImpl_ror_u8_amd, iemAImpl_ror_u8_intel;
2507	FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8, iemAImpl_rcl_u8_amd, iemAImpl_rcl_u8_intel;
2508	FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8, iemAImpl_rcr_u8_amd, iemAImpl_rcr_u8_intel;
2509	FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8, iemAImpl_shl_u8_amd, iemAImpl_shl_u8_intel;
2510	FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8, iemAImpl_shr_u8_amd, iemAImpl_shr_u8_intel;
2511	FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8, iemAImpl_sar_u8_amd, iemAImpl_sar_u8_intel;
2512	/** @} */
2513
2514	/** @name Shift operations on words (Group 2).
2515	* @{ */
2516	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU16,(uint16_t pu16Dst, uint8_t cShift, uint32_t pEFlags));
2517	typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
2518	FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16, iemAImpl_rol_u16_amd, iemAImpl_rol_u16_intel;
2519	FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16, iemAImpl_ror_u16_amd, iemAImpl_ror_u16_intel;
2520	FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16, iemAImpl_rcl_u16_amd, iemAImpl_rcl_u16_intel;
2521	FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16, iemAImpl_rcr_u16_amd, iemAImpl_rcr_u16_intel;
2522	FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16, iemAImpl_shl_u16_amd, iemAImpl_shl_u16_intel;
2523	FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16, iemAImpl_shr_u16_amd, iemAImpl_shr_u16_intel;
2524	FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16, iemAImpl_sar_u16_amd, iemAImpl_sar_u16_intel;
2525	/** @} */
2526
2527	/** @name Shift operations on double words (Group 2).
2528	* @{ */
2529	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU32,(uint32_t pu32Dst, uint8_t cShift, uint32_t pEFlags));
2530	typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
2531	FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32, iemAImpl_rol_u32_amd, iemAImpl_rol_u32_intel;
2532	FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32, iemAImpl_ror_u32_amd, iemAImpl_ror_u32_intel;
2533	FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32, iemAImpl_rcl_u32_amd, iemAImpl_rcl_u32_intel;
2534	FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32, iemAImpl_rcr_u32_amd, iemAImpl_rcr_u32_intel;
2535	FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32, iemAImpl_shl_u32_amd, iemAImpl_shl_u32_intel;
2536	FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32, iemAImpl_shr_u32_amd, iemAImpl_shr_u32_intel;
2537	FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32, iemAImpl_sar_u32_amd, iemAImpl_sar_u32_intel;
2538	/** @} */
2539
2540	/** @name Shift operations on words (Group 2).
2541	* @{ */
2542	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU64,(uint64_t pu64Dst, uint8_t cShift, uint32_t pEFlags));
2543	typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
2544	FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64, iemAImpl_rol_u64_amd, iemAImpl_rol_u64_intel;
2545	FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64, iemAImpl_ror_u64_amd, iemAImpl_ror_u64_intel;
2546	FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64, iemAImpl_rcl_u64_amd, iemAImpl_rcl_u64_intel;
2547	FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64, iemAImpl_rcr_u64_amd, iemAImpl_rcr_u64_intel;
2548	FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64, iemAImpl_shl_u64_amd, iemAImpl_shl_u64_intel;
2549	FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64, iemAImpl_shr_u64_amd, iemAImpl_shr_u64_intel;
2550	FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64, iemAImpl_sar_u64_amd, iemAImpl_sar_u64_intel;
2551	/** @} */
2552
2553	/** @name Multiplication and division operations.
2554	* @{ */
2555	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t pu16AX, uint8_t u8FactorDivisor, uint32_t pEFlags));
2556	typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
2557	FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_mul_u8_amd, iemAImpl_mul_u8_intel;
2558	FNIEMAIMPLMULDIVU8 iemAImpl_imul_u8, iemAImpl_imul_u8_amd, iemAImpl_imul_u8_intel;
2559	FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_div_u8_amd, iemAImpl_div_u8_intel;
2560	FNIEMAIMPLMULDIVU8 iemAImpl_idiv_u8, iemAImpl_idiv_u8_amd, iemAImpl_idiv_u8_intel;
2561
2562	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t pu16AX, uint16_t pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
2563	typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
2564	FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_mul_u16_amd, iemAImpl_mul_u16_intel;
2565	FNIEMAIMPLMULDIVU16 iemAImpl_imul_u16, iemAImpl_imul_u16_amd, iemAImpl_imul_u16_intel;
2566	FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_div_u16_amd, iemAImpl_div_u16_intel;
2567	FNIEMAIMPLMULDIVU16 iemAImpl_idiv_u16, iemAImpl_idiv_u16_amd, iemAImpl_idiv_u16_intel;
2568
2569	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t pu32EAX, uint32_t pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
2570	typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
2571	FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_mul_u32_amd, iemAImpl_mul_u32_intel;
2572	FNIEMAIMPLMULDIVU32 iemAImpl_imul_u32, iemAImpl_imul_u32_amd, iemAImpl_imul_u32_intel;
2573	FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_div_u32_amd, iemAImpl_div_u32_intel;
2574	FNIEMAIMPLMULDIVU32 iemAImpl_idiv_u32, iemAImpl_idiv_u32_amd, iemAImpl_idiv_u32_intel;
2575
2576	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t pu64RAX, uint64_t pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
2577	typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
2578	FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_mul_u64_amd, iemAImpl_mul_u64_intel;
2579	FNIEMAIMPLMULDIVU64 iemAImpl_imul_u64, iemAImpl_imul_u64_amd, iemAImpl_imul_u64_intel;
2580	FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_div_u64_amd, iemAImpl_div_u64_intel;
2581	FNIEMAIMPLMULDIVU64 iemAImpl_idiv_u64, iemAImpl_idiv_u64_amd, iemAImpl_idiv_u64_intel;
2582	/** @} */
2583
2584	/** @name Byte Swap.
2585	* @{ */
2586	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t pu32Dst)); / Yes, 32-bit register access. */
2587	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
2588	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
2589	/** @} */
2590
2591	/** @name Misc.
2592	* @{ */
2593	FNIEMAIMPLBINU16 iemAImpl_arpl;
2594	/** @} */
2595
2596	/** @name RDRAND and RDSEED
2597	* @{ */
2598	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU16,(uint16_t puDst, uint32_t pEFlags));
2599	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU32,(uint32_t puDst, uint32_t pEFlags));
2600	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU64,(uint64_t puDst, uint32_t pEFlags));
2601	typedef FNIEMAIMPLRDRANDSEEDU16 *PFNIEMAIMPLRDRANDSEEDU16;
2602	typedef FNIEMAIMPLRDRANDSEEDU32 *PFNIEMAIMPLRDRANDSEEDU32;
2603	typedef FNIEMAIMPLRDRANDSEEDU64 *PFNIEMAIMPLRDRANDSEEDU64;
2604
2605	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdrand_u16, iemAImpl_rdrand_u16_fallback;
2606	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdrand_u32, iemAImpl_rdrand_u32_fallback;
2607	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdrand_u64, iemAImpl_rdrand_u64_fallback;
2608	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdseed_u16, iemAImpl_rdseed_u16_fallback;
2609	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdseed_u32, iemAImpl_rdseed_u32_fallback;
2610	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdseed_u64, iemAImpl_rdseed_u64_fallback;
2611	/** @} */
2612
2613	/** @name ADOX and ADCX
2614	* @{ */
2615	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLADXU32,(uint32_t puDst, uint32_t pfEFlags, uint32_t uSrc));
2616	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLADXU64,(uint64_t puDst, uint32_t pfEFlags, uint64_t uSrc));
2617	typedef FNIEMAIMPLADXU32 *PFNIEMAIMPLADXU32;
2618	typedef FNIEMAIMPLADXU64 *PFNIEMAIMPLADXU64;
2619
2620	FNIEMAIMPLADXU32 iemAImpl_adcx_u32, iemAImpl_adcx_u32_fallback;
2621	FNIEMAIMPLADXU64 iemAImpl_adcx_u64, iemAImpl_adcx_u64_fallback;
2622	FNIEMAIMPLADXU32 iemAImpl_adox_u32, iemAImpl_adox_u32_fallback;
2623	FNIEMAIMPLADXU64 iemAImpl_adox_u64, iemAImpl_adox_u64_fallback;
2624	/** @} */
2625
2626	/** @name FPU operations taking a 32-bit float argument
2627	* @{ */
2628	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2629	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
2630	typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
2631
2632	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2633	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
2634	typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
2635
2636	FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
2637	FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
2638	FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
2639	FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
2640	FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
2641	FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
2642	FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
2643
2644	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
2645	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2646	PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
2647	/** @} */
2648
2649	/** @name FPU operations taking a 64-bit float argument
2650	* @{ */
2651	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2652	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
2653	typedef FNIEMAIMPLFPUR64FSW *PFNIEMAIMPLFPUR64FSW;
2654
2655	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2656	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
2657	typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
2658
2659	FNIEMAIMPLFPUR64FSW iemAImpl_fcom_r80_by_r64;
2660	FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
2661	FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
2662	FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
2663	FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
2664	FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
2665	FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
2666
2667	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
2668	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2669	PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
2670	/** @} */
2671
2672	/** @name FPU operations taking a 80-bit float argument
2673	* @{ */
2674	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2675	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
2676	typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
2677	FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
2678	FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
2679	FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
2680	FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
2681	FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
2682	FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
2683	FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
2684	FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
2685	FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
2686
2687	FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80, iemAImpl_fpatan_r80_by_r80_amd, iemAImpl_fpatan_r80_by_r80_intel;
2688	FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80, iemAImpl_fyl2x_r80_by_r80_amd, iemAImpl_fyl2x_r80_by_r80_intel;
2689	FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80, iemAImpl_fyl2xp1_r80_by_r80_amd, iemAImpl_fyl2xp1_r80_by_r80_intel;
2690
2691	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2692	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
2693	typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
2694	FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
2695	FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
2696
2697	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
2698	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
2699	typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
2700	FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
2701	FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
2702
2703	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
2704	typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
2705	FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
2706	FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
2707	FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80, iemAImpl_f2xm1_r80_amd, iemAImpl_f2xm1_r80_intel;
2708	FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
2709	FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
2710	FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80, iemAImpl_fsin_r80_amd, iemAImpl_fsin_r80_intel;
2711	FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80, iemAImpl_fcos_r80_amd, iemAImpl_fcos_r80_intel;
2712
2713	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
2714	typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
2715	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
2716	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
2717
2718	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
2719	typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
2720	FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
2721	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
2722	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
2723	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
2724	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
2725	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
2726	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
2727
2728	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
2729	PCRTFLOAT80U pr80Val));
2730	typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
2731	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80, iemAImpl_fptan_r80_r80_amd, iemAImpl_fptan_r80_r80_intel;
2732	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
2733	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80, iemAImpl_fsincos_r80_r80_amd, iemAImpl_fsincos_r80_r80_intel;
2734
2735	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
2736	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2737	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
2738
2739	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_d80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTPBCD80U pd80Val));
2740	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_d80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2741	PRTPBCD80U pd80Dst, PCRTFLOAT80U pr80Src));
2742
2743	/** @} */
2744
2745	/** @name FPU operations taking a 16-bit signed integer argument
2746	* @{ */
2747	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2748	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
2749	typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
2750	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI16,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
2751	int16_t *pi16Dst, PCRTFLOAT80U pr80Src));
2752	typedef FNIEMAIMPLFPUSTR80TOI16 *PFNIEMAIMPLFPUSTR80TOI16;
2753
2754	FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
2755	FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
2756	FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
2757	FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
2758	FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
2759	FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
2760
2761	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2762	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
2763	typedef FNIEMAIMPLFPUI16FSW *PFNIEMAIMPLFPUI16FSW;
2764	FNIEMAIMPLFPUI16FSW iemAImpl_ficom_r80_by_i16;
2765
2766	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
2767	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fist_r80_to_i16;
2768	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fistt_r80_to_i16, iemAImpl_fistt_r80_to_i16_amd, iemAImpl_fistt_r80_to_i16_intel;
2769	/** @} */
2770
2771	/** @name FPU operations taking a 32-bit signed integer argument
2772	* @{ */
2773	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2774	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
2775	typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
2776	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI32,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
2777	int32_t *pi32Dst, PCRTFLOAT80U pr80Src));
2778	typedef FNIEMAIMPLFPUSTR80TOI32 *PFNIEMAIMPLFPUSTR80TOI32;
2779
2780	FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
2781	FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
2782	FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
2783	FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
2784	FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
2785	FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
2786
2787	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2788	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
2789	typedef FNIEMAIMPLFPUI32FSW *PFNIEMAIMPLFPUI32FSW;
2790	FNIEMAIMPLFPUI32FSW iemAImpl_ficom_r80_by_i32;
2791
2792	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
2793	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fist_r80_to_i32;
2794	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fistt_r80_to_i32;
2795	/** @} */
2796
2797	/** @name FPU operations taking a 64-bit signed integer argument
2798	* @{ */
2799	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI64,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
2800	int64_t *pi64Dst, PCRTFLOAT80U pr80Src));
2801	typedef FNIEMAIMPLFPUSTR80TOI64 *PFNIEMAIMPLFPUSTR80TOI64;
2802
2803	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
2804	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fist_r80_to_i64;
2805	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fistt_r80_to_i64;
2806	/** @} */
2807
2808
2809	/** Temporary type representing a 256-bit vector register. */
2810	typedef struct { uint64_t au64[4]; } IEMVMM256;
2811	/** Temporary type pointing to a 256-bit vector register. */
2812	typedef IEMVMM256 *PIEMVMM256;
2813	/** Temporary type pointing to a const 256-bit vector register. */
2814	typedef IEMVMM256 *PCIEMVMM256;
2815
2816
2817	/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
2818	* @{ */
2819	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t puDst, uint64_t const puSrc));
2820	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
2821	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U128,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
2822	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
2823	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U128,(PX86XSAVEAREA pExtState, PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
2824	typedef FNIEMAIMPLMEDIAF3U128 *PFNIEMAIMPLMEDIAF3U128;
2825	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U256,(PX86XSAVEAREA pExtState, PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
2826	typedef FNIEMAIMPLMEDIAF3U256 *PFNIEMAIMPLMEDIAF3U256;
2827	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U64,(uint64_t puDst, uint64_t const puSrc));
2828	typedef FNIEMAIMPLMEDIAOPTF2U64 *PFNIEMAIMPLMEDIAOPTF2U64;
2829	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128,(PRTUINT128U puDst, PCRTUINT128U puSrc));
2830	typedef FNIEMAIMPLMEDIAOPTF2U128 *PFNIEMAIMPLMEDIAOPTF2U128;
2831	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
2832	typedef FNIEMAIMPLMEDIAOPTF3U128 *PFNIEMAIMPLMEDIAOPTF3U128;
2833	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
2834	typedef FNIEMAIMPLMEDIAOPTF3U256 *PFNIEMAIMPLMEDIAOPTF3U256;
2835	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256,(PRTUINT256U puDst, PCRTUINT256U puSrc));
2836	typedef FNIEMAIMPLMEDIAOPTF2U256 *PFNIEMAIMPLMEDIAOPTF2U256;
2837	FNIEMAIMPLMEDIAF2U64 iemAImpl_pshufb_u64, iemAImpl_pshufb_u64_fallback;
2838	FNIEMAIMPLMEDIAF2U64 iemAImpl_pand_u64, iemAImpl_pandn_u64, iemAImpl_por_u64, iemAImpl_pxor_u64;
2839	FNIEMAIMPLMEDIAF2U64 iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
2840	FNIEMAIMPLMEDIAF2U64 iemAImpl_pcmpgtb_u64, iemAImpl_pcmpgtw_u64, iemAImpl_pcmpgtd_u64;
2841	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddb_u64, iemAImpl_paddsb_u64, iemAImpl_paddusb_u64;
2842	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddw_u64, iemAImpl_paddsw_u64, iemAImpl_paddusw_u64;
2843	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddd_u64;
2844	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddq_u64;
2845	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubb_u64, iemAImpl_psubsb_u64, iemAImpl_psubusb_u64;
2846	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubw_u64, iemAImpl_psubsw_u64, iemAImpl_psubusw_u64;
2847	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubd_u64;
2848	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubq_u64;
2849	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmaddwd_u64;
2850	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmullw_u64, iemAImpl_pmulhw_u64;
2851	FNIEMAIMPLMEDIAF2U64 iemAImpl_pminub_u64, iemAImpl_pmaxub_u64;
2852	FNIEMAIMPLMEDIAF2U64 iemAImpl_pminsw_u64, iemAImpl_pmaxsw_u64;
2853	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsb_u64, iemAImpl_pabsb_u64_fallback;
2854	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsw_u64, iemAImpl_pabsw_u64_fallback;
2855	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsd_u64, iemAImpl_pabsd_u64_fallback;
2856	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignb_u64, iemAImpl_psignb_u64_fallback;
2857	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignw_u64, iemAImpl_psignw_u64_fallback;
2858	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignd_u64, iemAImpl_psignd_u64_fallback;
2859	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddw_u64, iemAImpl_phaddw_u64_fallback;
2860	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddd_u64, iemAImpl_phaddd_u64_fallback;
2861	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubw_u64, iemAImpl_phsubw_u64_fallback;
2862	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubd_u64, iemAImpl_phsubd_u64_fallback;
2863	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddsw_u64, iemAImpl_phaddsw_u64_fallback;
2864	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubsw_u64, iemAImpl_phsubsw_u64_fallback;
2865	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmaddubsw_u64, iemAImpl_pmaddubsw_u64_fallback;
2866	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmulhrsw_u64, iemAImpl_pmulhrsw_u64_fallback;
2867	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmuludq_u64;
2868	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllw_u64, iemAImpl_psrlw_u64, iemAImpl_psraw_u64;
2869	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pslld_u64, iemAImpl_psrld_u64, iemAImpl_psrad_u64;
2870	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllq_u64, iemAImpl_psrlq_u64;
2871	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packsswb_u64, iemAImpl_packuswb_u64;
2872	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packssdw_u64;
2873	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhuw_u64;
2874	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pavgb_u64, iemAImpl_pavgw_u64;
2875	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psadbw_u64;
2876
2877	FNIEMAIMPLMEDIAF2U128 iemAImpl_pshufb_u128, iemAImpl_pshufb_u128_fallback;
2878	FNIEMAIMPLMEDIAF2U128 iemAImpl_pand_u128, iemAImpl_pandn_u128, iemAImpl_por_u128, iemAImpl_pxor_u128;
2879	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
2880	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpeqq_u128, iemAImpl_pcmpeqq_u128_fallback;
2881	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpgtb_u128, iemAImpl_pcmpgtw_u128, iemAImpl_pcmpgtd_u128;
2882	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpgtq_u128, iemAImpl_pcmpgtq_u128_fallback;
2883	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddb_u128, iemAImpl_paddsb_u128, iemAImpl_paddusb_u128;
2884	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddw_u128, iemAImpl_paddsw_u128, iemAImpl_paddusw_u128;
2885	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddd_u128;
2886	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddq_u128;
2887	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubb_u128, iemAImpl_psubsb_u128, iemAImpl_psubusb_u128;
2888	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubw_u128, iemAImpl_psubsw_u128, iemAImpl_psubusw_u128;
2889	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubd_u128;
2890	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubq_u128;
2891	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmullw_u128, iemAImpl_pmullw_u128_fallback;
2892	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulhw_u128;
2893	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulld_u128, iemAImpl_pmulld_u128_fallback;
2894	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaddwd_u128;
2895	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminub_u128;
2896	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminud_u128, iemAImpl_pminud_u128_fallback;
2897	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminuw_u128, iemAImpl_pminuw_u128_fallback;
2898	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsb_u128, iemAImpl_pminsb_u128_fallback;
2899	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsd_u128, iemAImpl_pminsd_u128_fallback;
2900	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsw_u128, iemAImpl_pminsw_u128_fallback;
2901	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxub_u128;
2902	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxud_u128, iemAImpl_pmaxud_u128_fallback;
2903	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxuw_u128, iemAImpl_pmaxuw_u128_fallback;
2904	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsb_u128, iemAImpl_pmaxsb_u128_fallback;
2905	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsw_u128;
2906	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsd_u128, iemAImpl_pmaxsd_u128_fallback;
2907	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsb_u128, iemAImpl_pabsb_u128_fallback;
2908	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsw_u128, iemAImpl_pabsw_u128_fallback;
2909	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsd_u128, iemAImpl_pabsd_u128_fallback;
2910	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignb_u128, iemAImpl_psignb_u128_fallback;
2911	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignw_u128, iemAImpl_psignw_u128_fallback;
2912	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignd_u128, iemAImpl_psignd_u128_fallback;
2913	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddw_u128, iemAImpl_phaddw_u128_fallback;
2914	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddd_u128, iemAImpl_phaddd_u128_fallback;
2915	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubw_u128, iemAImpl_phsubw_u128_fallback;
2916	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubd_u128, iemAImpl_phsubd_u128_fallback;
2917	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddsw_u128, iemAImpl_phaddsw_u128_fallback;
2918	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubsw_u128, iemAImpl_phsubsw_u128_fallback;
2919	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaddubsw_u128, iemAImpl_pmaddubsw_u128_fallback;
2920	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulhrsw_u128, iemAImpl_pmulhrsw_u128_fallback;
2921	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmuludq_u128;
2922	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packsswb_u128, iemAImpl_packuswb_u128;
2923	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packssdw_u128, iemAImpl_packusdw_u128;
2924	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllw_u128, iemAImpl_psrlw_u128, iemAImpl_psraw_u128;
2925	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pslld_u128, iemAImpl_psrld_u128, iemAImpl_psrad_u128;
2926	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllq_u128, iemAImpl_psrlq_u128;
2927	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhuw_u128;
2928	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pavgb_u128, iemAImpl_pavgw_u128;
2929	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psadbw_u128;
2930	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuldq_u128, iemAImpl_pmuldq_u128_fallback;
2931	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpcklps_u128, iemAImpl_unpcklpd_u128;
2932	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpckhps_u128, iemAImpl_unpckhpd_u128;
2933	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phminposuw_u128, iemAImpl_phminposuw_u128_fallback;
2934
2935	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpshufb_u128, iemAImpl_vpshufb_u128_fallback;
2936	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpand_u128, iemAImpl_vpand_u128_fallback;
2937	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpandn_u128, iemAImpl_vpandn_u128_fallback;
2938	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpor_u128, iemAImpl_vpor_u128_fallback;
2939	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpxor_u128, iemAImpl_vpxor_u128_fallback;
2940	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqb_u128, iemAImpl_vpcmpeqb_u128_fallback;
2941	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqw_u128, iemAImpl_vpcmpeqw_u128_fallback;
2942	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqd_u128, iemAImpl_vpcmpeqd_u128_fallback;
2943	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqq_u128, iemAImpl_vpcmpeqq_u128_fallback;
2944	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtb_u128, iemAImpl_vpcmpgtb_u128_fallback;
2945	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtw_u128, iemAImpl_vpcmpgtw_u128_fallback;
2946	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtd_u128, iemAImpl_vpcmpgtd_u128_fallback;
2947	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtq_u128, iemAImpl_vpcmpgtq_u128_fallback;
2948	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddb_u128, iemAImpl_vpaddb_u128_fallback;
2949	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddw_u128, iemAImpl_vpaddw_u128_fallback;
2950	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddd_u128, iemAImpl_vpaddd_u128_fallback;
2951	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddq_u128, iemAImpl_vpaddq_u128_fallback;
2952	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubb_u128, iemAImpl_vpsubb_u128_fallback;
2953	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubw_u128, iemAImpl_vpsubw_u128_fallback;
2954	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubd_u128, iemAImpl_vpsubd_u128_fallback;
2955	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubq_u128, iemAImpl_vpsubq_u128_fallback;
2956	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminub_u128, iemAImpl_vpminub_u128_fallback;
2957	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminuw_u128, iemAImpl_vpminuw_u128_fallback;
2958	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminud_u128, iemAImpl_vpminud_u128_fallback;
2959	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsb_u128, iemAImpl_vpminsb_u128_fallback;
2960	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsw_u128, iemAImpl_vpminsw_u128_fallback;
2961	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsd_u128, iemAImpl_vpminsd_u128_fallback;
2962	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxub_u128, iemAImpl_vpmaxub_u128_fallback;
2963	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxuw_u128, iemAImpl_vpmaxuw_u128_fallback;
2964	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxud_u128, iemAImpl_vpmaxud_u128_fallback;
2965	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsb_u128, iemAImpl_vpmaxsb_u128_fallback;
2966	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsw_u128, iemAImpl_vpmaxsw_u128_fallback;
2967	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsd_u128, iemAImpl_vpmaxsd_u128_fallback;
2968	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpacksswb_u128, iemAImpl_vpacksswb_u128_fallback;
2969	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackssdw_u128, iemAImpl_vpackssdw_u128_fallback;
2970	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackuswb_u128, iemAImpl_vpackuswb_u128_fallback;
2971	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackusdw_u128, iemAImpl_vpackusdw_u128_fallback;
2972	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmullw_u128, iemAImpl_vpmullw_u128_fallback;
2973	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulld_u128, iemAImpl_vpmulld_u128_fallback;
2974	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhw_u128, iemAImpl_vpmulhw_u128_fallback;
2975	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhuw_u128, iemAImpl_vpmulhuw_u128_fallback;
2976	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgb_u128, iemAImpl_vpavgb_u128_fallback;
2977	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgw_u128, iemAImpl_vpavgw_u128_fallback;
2978	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignb_u128, iemAImpl_vpsignb_u128_fallback;
2979	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignw_u128, iemAImpl_vpsignw_u128_fallback;
2980	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignd_u128, iemAImpl_vpsignd_u128_fallback;
2981	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddw_u128, iemAImpl_vphaddw_u128_fallback;
2982	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddd_u128, iemAImpl_vphaddd_u128_fallback;
2983	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubw_u128, iemAImpl_vphsubw_u128_fallback;
2984	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubd_u128, iemAImpl_vphsubd_u128_fallback;
2985	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddsw_u128, iemAImpl_vphaddsw_u128_fallback;
2986	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubsw_u128, iemAImpl_vphsubsw_u128_fallback;
2987	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddubsw_u128, iemAImpl_vpmaddubsw_u128_fallback;
2988	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhrsw_u128, iemAImpl_vpmulhrsw_u128_fallback;
2989	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsadbw_u128, iemAImpl_vpsadbw_u128_fallback;
2990	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuldq_u128, iemAImpl_vpmuldq_u128_fallback;
2991	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuludq_u128, iemAImpl_vpmuludq_u128_fallback;
2992	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsb_u128, iemAImpl_vpsubsb_u128_fallback;
2993	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsw_u128, iemAImpl_vpsubsw_u128_fallback;
2994	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusb_u128, iemAImpl_vpsubusb_u128_fallback;
2995	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusw_u128, iemAImpl_vpsubusw_u128_fallback;
2996	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusb_u128, iemAImpl_vpaddusb_u128_fallback;
2997	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusw_u128, iemAImpl_vpaddusw_u128_fallback;
2998	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsb_u128, iemAImpl_vpaddsb_u128_fallback;
2999	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsw_u128, iemAImpl_vpaddsw_u128_fallback;
3000
3001	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsb_u128, iemAImpl_vpabsb_u128_fallback;
3002	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsw_u128, iemAImpl_vpabsd_u128_fallback;
3003	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsd_u128, iemAImpl_vpabsw_u128_fallback;
3004	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vphminposuw_u128, iemAImpl_vphminposuw_u128_fallback;
3005
3006	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpshufb_u256, iemAImpl_vpshufb_u256_fallback;
3007	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpand_u256, iemAImpl_vpand_u256_fallback;
3008	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpandn_u256, iemAImpl_vpandn_u256_fallback;
3009	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpor_u256, iemAImpl_vpor_u256_fallback;
3010	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpxor_u256, iemAImpl_vpxor_u256_fallback;
3011	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqb_u256, iemAImpl_vpcmpeqb_u256_fallback;
3012	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqw_u256, iemAImpl_vpcmpeqw_u256_fallback;
3013	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqd_u256, iemAImpl_vpcmpeqd_u256_fallback;
3014	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqq_u256, iemAImpl_vpcmpeqq_u256_fallback;
3015	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtb_u256, iemAImpl_vpcmpgtb_u256_fallback;
3016	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtw_u256, iemAImpl_vpcmpgtw_u256_fallback;
3017	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtd_u256, iemAImpl_vpcmpgtd_u256_fallback;
3018	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtq_u256, iemAImpl_vpcmpgtq_u256_fallback;
3019	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddb_u256, iemAImpl_vpaddb_u256_fallback;
3020	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddw_u256, iemAImpl_vpaddw_u256_fallback;
3021	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddd_u256, iemAImpl_vpaddd_u256_fallback;
3022	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddq_u256, iemAImpl_vpaddq_u256_fallback;
3023	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubb_u256, iemAImpl_vpsubb_u256_fallback;
3024	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubw_u256, iemAImpl_vpsubw_u256_fallback;
3025	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubd_u256, iemAImpl_vpsubd_u256_fallback;
3026	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubq_u256, iemAImpl_vpsubq_u256_fallback;
3027	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminub_u256, iemAImpl_vpminub_u256_fallback;
3028	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminuw_u256, iemAImpl_vpminuw_u256_fallback;
3029	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminud_u256, iemAImpl_vpminud_u256_fallback;
3030	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsb_u256, iemAImpl_vpminsb_u256_fallback;
3031	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsw_u256, iemAImpl_vpminsw_u256_fallback;
3032	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsd_u256, iemAImpl_vpminsd_u256_fallback;
3033	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxub_u256, iemAImpl_vpmaxub_u256_fallback;
3034	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxuw_u256, iemAImpl_vpmaxuw_u256_fallback;
3035	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxud_u256, iemAImpl_vpmaxud_u256_fallback;
3036	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsb_u256, iemAImpl_vpmaxsb_u256_fallback;
3037	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsw_u256, iemAImpl_vpmaxsw_u256_fallback;
3038	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsd_u256, iemAImpl_vpmaxsd_u256_fallback;
3039	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpacksswb_u256, iemAImpl_vpacksswb_u256_fallback;
3040	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackssdw_u256, iemAImpl_vpackssdw_u256_fallback;
3041	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackuswb_u256, iemAImpl_vpackuswb_u256_fallback;
3042	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackusdw_u256, iemAImpl_vpackusdw_u256_fallback;
3043	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmullw_u256, iemAImpl_vpmullw_u256_fallback;
3044	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulld_u256, iemAImpl_vpmulld_u256_fallback;
3045	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhw_u256, iemAImpl_vpmulhw_u256_fallback;
3046	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhuw_u256, iemAImpl_vpmulhuw_u256_fallback;
3047	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgb_u256, iemAImpl_vpavgb_u256_fallback;
3048	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgw_u256, iemAImpl_vpavgw_u256_fallback;
3049	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignb_u256, iemAImpl_vpsignb_u256_fallback;
3050	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignw_u256, iemAImpl_vpsignw_u256_fallback;
3051	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignd_u256, iemAImpl_vpsignd_u256_fallback;
3052	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddw_u256, iemAImpl_vphaddw_u256_fallback;
3053	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddd_u256, iemAImpl_vphaddd_u256_fallback;
3054	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubw_u256, iemAImpl_vphsubw_u256_fallback;
3055	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubd_u256, iemAImpl_vphsubd_u256_fallback;
3056	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddsw_u256, iemAImpl_vphaddsw_u256_fallback;
3057	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubsw_u256, iemAImpl_vphsubsw_u256_fallback;
3058	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddubsw_u256, iemAImpl_vpmaddubsw_u256_fallback;
3059	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhrsw_u256, iemAImpl_vpmulhrsw_u256_fallback;
3060	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsadbw_u256, iemAImpl_vpsadbw_u256_fallback;
3061	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuldq_u256, iemAImpl_vpmuldq_u256_fallback;
3062	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuludq_u256, iemAImpl_vpmuludq_u256_fallback;
3063	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsb_u256, iemAImpl_vpsubsb_u256_fallback;
3064	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsw_u256, iemAImpl_vpsubsw_u256_fallback;
3065	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusb_u256, iemAImpl_vpsubusb_u256_fallback;
3066	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusw_u256, iemAImpl_vpsubusw_u256_fallback;
3067	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusb_u256, iemAImpl_vpaddusb_u256_fallback;
3068	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusw_u256, iemAImpl_vpaddusw_u256_fallback;
3069	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsb_u256, iemAImpl_vpaddsb_u256_fallback;
3070	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsw_u256, iemAImpl_vpaddsw_u256_fallback;
3071
3072	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsb_u256, iemAImpl_vpabsb_u256_fallback;
3073	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsw_u256, iemAImpl_vpabsw_u256_fallback;
3074	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsd_u256, iemAImpl_vpabsd_u256_fallback;
3075	/** @} */
3076
3077	/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
3078	* @{ */
3079	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
3080	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
3081	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpcklbw_u128, iemAImpl_vpunpcklbw_u128_fallback,
3082	iemAImpl_vpunpcklwd_u128, iemAImpl_vpunpcklwd_u128_fallback,
3083	iemAImpl_vpunpckldq_u128, iemAImpl_vpunpckldq_u128_fallback,
3084	iemAImpl_vpunpcklqdq_u128, iemAImpl_vpunpcklqdq_u128_fallback,
3085	iemAImpl_vunpcklps_u128, iemAImpl_vunpcklps_u128_fallback,
3086	iemAImpl_vunpcklpd_u128, iemAImpl_vunpcklpd_u128_fallback,
3087	iemAImpl_vunpckhps_u128, iemAImpl_vunpckhps_u128_fallback,
3088	iemAImpl_vunpckhpd_u128, iemAImpl_vunpckhpd_u128_fallback;
3089
3090	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpcklbw_u256, iemAImpl_vpunpcklbw_u256_fallback,
3091	iemAImpl_vpunpcklwd_u256, iemAImpl_vpunpcklwd_u256_fallback,
3092	iemAImpl_vpunpckldq_u256, iemAImpl_vpunpckldq_u256_fallback,
3093	iemAImpl_vpunpcklqdq_u256, iemAImpl_vpunpcklqdq_u256_fallback,
3094	iemAImpl_vunpcklps_u256, iemAImpl_vunpcklps_u256_fallback,
3095	iemAImpl_vunpcklpd_u256, iemAImpl_vunpcklpd_u256_fallback,
3096	iemAImpl_vunpckhps_u256, iemAImpl_vunpckhps_u256_fallback,
3097	iemAImpl_vunpckhpd_u256, iemAImpl_vunpckhpd_u256_fallback;
3098	/** @} */
3099
3100	/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
3101	* @{ */
3102	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
3103	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
3104	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpckhbw_u128, iemAImpl_vpunpckhbw_u128_fallback,
3105	iemAImpl_vpunpckhwd_u128, iemAImpl_vpunpckhwd_u128_fallback,
3106	iemAImpl_vpunpckhdq_u128, iemAImpl_vpunpckhdq_u128_fallback,
3107	iemAImpl_vpunpckhqdq_u128, iemAImpl_vpunpckhqdq_u128_fallback;
3108	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpckhbw_u256, iemAImpl_vpunpckhbw_u256_fallback,
3109	iemAImpl_vpunpckhwd_u256, iemAImpl_vpunpckhwd_u256_fallback,
3110	iemAImpl_vpunpckhdq_u256, iemAImpl_vpunpckhdq_u256_fallback,
3111	iemAImpl_vpunpckhqdq_u256, iemAImpl_vpunpckhqdq_u256_fallback;
3112	/** @} */
3113
3114	/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
3115	* @{ */
3116	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3117	typedef FNIEMAIMPLMEDIAPSHUFU128 *PFNIEMAIMPLMEDIAPSHUFU128;
3118	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
3119	typedef FNIEMAIMPLMEDIAPSHUFU256 *PFNIEMAIMPLMEDIAPSHUFU256;
3120	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw_u64,(uint64_t puDst, uint64_t const puSrc, uint8_t bEvil));
3121	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_pshufhw_u128, iemAImpl_pshuflw_u128, iemAImpl_pshufd_u128;
3122	#ifndef IEM_WITHOUT_ASSEMBLY
3123	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256, iemAImpl_vpshuflw_u256, iemAImpl_vpshufd_u256;
3124	#endif
3125	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256_fallback, iemAImpl_vpshuflw_u256_fallback, iemAImpl_vpshufd_u256_fallback;
3126	/** @} */
3127
3128	/** @name Media (SSE/MMX/AVX) operation: Shift Immediate Stuff (evil)
3129	* @{ */
3130	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU64,(uint64_t *puDst, uint8_t bShift));
3131	typedef FNIEMAIMPLMEDIAPSHIFTU64 *PFNIEMAIMPLMEDIAPSHIFTU64;
3132	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU128,(PRTUINT128U puDst, uint8_t bShift));
3133	typedef FNIEMAIMPLMEDIAPSHIFTU128 *PFNIEMAIMPLMEDIAPSHIFTU128;
3134	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU256,(PRTUINT256U puDst, uint8_t bShift));
3135	typedef FNIEMAIMPLMEDIAPSHIFTU256 *PFNIEMAIMPLMEDIAPSHIFTU256;
3136	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psllw_imm_u64, iemAImpl_pslld_imm_u64, iemAImpl_psllq_imm_u64;
3137	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psrlw_imm_u64, iemAImpl_psrld_imm_u64, iemAImpl_psrlq_imm_u64;
3138	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psraw_imm_u64, iemAImpl_psrad_imm_u64;
3139	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psllw_imm_u128, iemAImpl_pslld_imm_u128, iemAImpl_psllq_imm_u128;
3140	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psrlw_imm_u128, iemAImpl_psrld_imm_u128, iemAImpl_psrlq_imm_u128;
3141	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psraw_imm_u128, iemAImpl_psrad_imm_u128;
3142	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_pslldq_imm_u128, iemAImpl_psrldq_imm_u128;
3143	/** @} */
3144
3145	/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
3146	* @{ */
3147	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(uint64_t pu64Dst, uint64_t const puSrc));
3148	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(uint64_t *pu64Dst, PCRTUINT128U puSrc));
3149	#ifndef IEM_WITHOUT_ASSEMBLY
3150	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
3151	#endif
3152	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256_fallback,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
3153	/** @} */
3154
3155	/** @name Media (SSE/MMX/AVX) operations: Variable Blend Packed Bytes/R32/R64.
3156	* @{ */
3157	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puMask));
3158	typedef FNIEMAIMPLBLENDU128 *PFNIEMAIMPLBLENDU128;
3159	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, PCRTUINT128U puMask));
3160	typedef FNIEMAIMPLAVXBLENDU128 *PFNIEMAIMPLAVXBLENDU128;
3161	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, PCRTUINT256U puMask));
3162	typedef FNIEMAIMPLAVXBLENDU256 *PFNIEMAIMPLAVXBLENDU256;
3163
3164	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128;
3165	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128_fallback;
3166	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128;
3167	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128_fallback;
3168	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256;
3169	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256_fallback;
3170
3171	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128;
3172	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128_fallback;
3173	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128;
3174	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128_fallback;
3175	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256;
3176	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256_fallback;
3177
3178	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128;
3179	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128_fallback;
3180	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128;
3181	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128_fallback;
3182	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256;
3183	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256_fallback;
3184	/** @} */
3185
3186
3187	/** @name Media (SSE/MMX/AVX) operation: Sort this later
3188	* @{ */
3189	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
3190	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
3191	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovshdup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
3192	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovshdup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
3193	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
3194	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
3195
3196	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3197	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3198	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3199	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3200	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3201
3202	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3203	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3204	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3205	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3206	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3207
3208	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3209	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3210	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
3211	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3212	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3213
3214	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3215	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3216	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3217	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3218	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3219
3220	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3221	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3222	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3223	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3224	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3225
3226	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3227	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3228	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3229	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3230	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3231
3232	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3233	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3234	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3235	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3236	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3237
3238	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3239	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3240	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3241	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3242	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3243
3244	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3245	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3246	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
3247	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3248	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3249
3250	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3251	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3252	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3253	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3254	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3255
3256	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3257	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3258	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3259	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3260	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3261
3262	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3263	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3264	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3265	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3266	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3267
3268	IEM_DECL_IMPL_DEF(void, iemAImpl_shufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3269	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3270	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3271	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3272	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3273
3274	IEM_DECL_IMPL_DEF(void, iemAImpl_shufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3275	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3276	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3277	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3278	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3279
3280	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
3281	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64_fallback,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
3282
3283	IEM_DECL_IMPL_DEF(void, iemAImpl_pinsrw_u64,(uint64_t *pu64Dst, uint16_t u16Src, uint8_t bEvil));
3284	IEM_DECL_IMPL_DEF(void, iemAImpl_pinsrw_u128,(PRTUINT128U puDst, uint16_t u16Src, uint8_t bEvil));
3285	IEM_DECL_IMPL_DEF(void, iemAImpl_vpinsrw_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint16_t u16Src, uint8_t bEvil));
3286	IEM_DECL_IMPL_DEF(void, iemAImpl_vpinsrw_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint16_t u16Src, uint8_t bEvil));
3287
3288	IEM_DECL_IMPL_DEF(void, iemAImpl_pextrw_u64,(uint16_t *pu16Dst, uint64_t u64Src, uint8_t bEvil));
3289	IEM_DECL_IMPL_DEF(void, iemAImpl_pextrw_u128,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
3290	IEM_DECL_IMPL_DEF(void, iemAImpl_vpextrw_u128,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
3291	IEM_DECL_IMPL_DEF(void, iemAImpl_vpextrw_u128_fallback,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
3292
3293	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3294	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3295	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3296	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3297	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3298
3299	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3300	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3301	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3302	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3303	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3304
3305
3306	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3307	typedef FNIEMAIMPLMEDIAOPTF2U128IMM8 *PFNIEMAIMPLMEDIAOPTF2U128IMM8;
3308	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3309	typedef FNIEMAIMPLMEDIAOPTF3U128IMM8 *PFNIEMAIMPLMEDIAOPTF3U128IMM8;
3310	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3311	typedef FNIEMAIMPLMEDIAOPTF3U256IMM8 *PFNIEMAIMPLMEDIAOPTF3U256IMM8;
3312
3313	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_palignr_u128, iemAImpl_palignr_u128_fallback;
3314	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pblendw_u128, iemAImpl_pblendw_u128_fallback;
3315	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendps_u128, iemAImpl_blendps_u128_fallback;
3316	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendpd_u128, iemAImpl_blendpd_u128_fallback;
3317
3318	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpalignr_u128, iemAImpl_vpalignr_u128_fallback;
3319	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendw_u128, iemAImpl_vpblendw_u128_fallback;
3320	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendps_u128, iemAImpl_vblendps_u128_fallback;
3321	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendpd_u128, iemAImpl_vblendpd_u128_fallback;
3322
3323	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpalignr_u256, iemAImpl_vpalignr_u256_fallback;
3324	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendw_u256, iemAImpl_vpblendw_u256_fallback;
3325	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendps_u256, iemAImpl_vblendps_u256_fallback;
3326	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendpd_u256, iemAImpl_vblendpd_u256_fallback;
3327	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2i128_u256, iemAImpl_vperm2i128_u256_fallback;
3328	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2f128_u256, iemAImpl_vperm2f128_u256_fallback;
3329
3330	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesimc_u128, iemAImpl_aesimc_u128_fallback;
3331	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenc_u128, iemAImpl_aesenc_u128_fallback;
3332	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenclast_u128, iemAImpl_aesenclast_u128_fallback;
3333	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdec_u128, iemAImpl_aesdec_u128_fallback;
3334	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdeclast_u128, iemAImpl_aesdeclast_u128_fallback;
3335
3336	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesimc_u128, iemAImpl_vaesimc_u128_fallback;
3337	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenc_u128, iemAImpl_vaesenc_u128_fallback;
3338	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenclast_u128, iemAImpl_vaesenclast_u128_fallback;
3339	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdec_u128, iemAImpl_vaesdec_u128_fallback;
3340	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdeclast_u128, iemAImpl_vaesdeclast_u128_fallback;
3341
3342	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_aeskeygenassist_u128, iemAImpl_aeskeygenassist_u128_fallback;
3343
3344	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vaeskeygenassist_u128, iemAImpl_vaeskeygenassist_u128_fallback;
3345
3346	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1nexte_u128, iemAImpl_sha1nexte_u128_fallback;
3347	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg1_u128, iemAImpl_sha1msg1_u128_fallback;
3348	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg2_u128, iemAImpl_sha1msg2_u128_fallback;
3349	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg1_u128, iemAImpl_sha256msg1_u128_fallback;
3350	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg2_u128, iemAImpl_sha256msg2_u128_fallback;
3351	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_sha1rnds4_u128, iemAImpl_sha1rnds4_u128_fallback;
3352	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
3353	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
3354
3355	typedef struct IEMPCMPISTRXSRC
3356	{
3357	RTUINT128U uSrc1;
3358	RTUINT128U uSrc2;
3359	} IEMPCMPISTRXSRC;
3360	typedef IEMPCMPISTRXSRC *PIEMPCMPISTRXSRC;
3361	typedef const IEMPCMPISTRXSRC *PCIEMPCMPISTRXSRC;
3362
3363	typedef struct IEMPCMPESTRXSRC
3364	{
3365	RTUINT128U uSrc1;
3366	RTUINT128U uSrc2;
3367	uint64_t u64Rax;
3368	uint64_t u64Rdx;
3369	} IEMPCMPESTRXSRC;
3370	typedef IEMPCMPESTRXSRC *PIEMPCMPESTRXSRC;
3371	typedef const IEMPCMPESTRXSRC *PCIEMPCMPESTRXSRC;
3372
3373	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPISTRIU128IMM8,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
3374	typedef FNIEMAIMPLPCMPISTRIU128IMM8 *PFNIEMAIMPLPCMPISTRIU128IMM8;
3375	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRIU128IMM8,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
3376	typedef FNIEMAIMPLPCMPESTRIU128IMM8 *PFNIEMAIMPLPCMPESTRIU128IMM8;
3377
3378	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPISTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
3379	typedef FNIEMAIMPLPCMPISTRMU128IMM8 *PFNIEMAIMPLPCMPISTRMU128IMM8;
3380	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
3381	typedef FNIEMAIMPLPCMPESTRMU128IMM8 *PFNIEMAIMPLPCMPESTRMU128IMM8;
3382
3383	FNIEMAIMPLPCMPISTRIU128IMM8 iemAImpl_pcmpistri_u128, iemAImpl_pcmpistri_u128_fallback;
3384	FNIEMAIMPLPCMPESTRIU128IMM8 iemAImpl_pcmpestri_u128, iemAImpl_pcmpestri_u128_fallback;
3385	FNIEMAIMPLPCMPISTRMU128IMM8 iemAImpl_pcmpistrm_u128, iemAImpl_pcmpistrm_u128_fallback;
3386	FNIEMAIMPLPCMPESTRMU128IMM8 iemAImpl_pcmpestrm_u128, iemAImpl_pcmpestrm_u128_fallback;
3387
3388	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pclmulqdq_u128, iemAImpl_pclmulqdq_u128_fallback;
3389	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpclmulqdq_u128, iemAImpl_vpclmulqdq_u128_fallback;
3390
3391	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_mpsadbw_u128, iemAImpl_mpsadbw_u128_fallback;
3392	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vmpsadbw_u128, iemAImpl_vmpsadbw_u128_fallback;
3393	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vmpsadbw_u256, iemAImpl_vmpsadbw_u256_fallback;
3394	/** @} */
3395
3396	/** @name Media Odds and Ends
3397	* @{ */
3398	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U8,(uint32_t *puDst, uint8_t uSrc));
3399	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U16,(uint32_t *puDst, uint16_t uSrc));
3400	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U32,(uint32_t *puDst, uint32_t uSrc));
3401	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U64,(uint32_t *puDst, uint64_t uSrc));
3402	FNIEMAIMPLCR32U8 iemAImpl_crc32_u8, iemAImpl_crc32_u8_fallback;
3403	FNIEMAIMPLCR32U16 iemAImpl_crc32_u16, iemAImpl_crc32_u16_fallback;
3404	FNIEMAIMPLCR32U32 iemAImpl_crc32_u32, iemAImpl_crc32_u32_fallback;
3405	FNIEMAIMPLCR32U64 iemAImpl_crc32_u64, iemAImpl_crc32_u64_fallback;
3406
3407	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL128,(PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint32_t *pEFlags));
3408	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL256,(PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint32_t *pEFlags));
3409	FNIEMAIMPLF2EFL128 iemAImpl_ptest_u128;
3410	FNIEMAIMPLF2EFL256 iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback;
3411
3412	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I32U64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int32_t pi32Dst, const uint64_t pu64Src)); / pu64Src is a double precision floating point. */
3413	typedef FNIEMAIMPLSSEF2I32U64 *PFNIEMAIMPLSSEF2I32U64;
3414	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I64U64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int64_t pi64Dst, const uint64_t pu64Src)); / pu64Src is a double precision floating point. */
3415	typedef FNIEMAIMPLSSEF2I64U64 *PFNIEMAIMPLSSEF2I64U64;
3416	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I32U32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int32_t pi32Dst, const uint32_t pu32Src)); / pu32Src is a single precision floating point. */
3417	typedef FNIEMAIMPLSSEF2I32U32 *PFNIEMAIMPLSSEF2I32U32;
3418	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I64U32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int64_t pi64Dst, const uint32_t pu32Src)); / pu32Src is a single precision floating point. */
3419	typedef FNIEMAIMPLSSEF2I64U32 *PFNIEMAIMPLSSEF2I64U32;
3420
3421	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvttsd2si_i32_r64;
3422	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvtsd2si_i32_r64;
3423
3424	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvttsd2si_i64_r64;
3425	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvtsd2si_i64_r64;
3426
3427	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvttss2si_i32_r32;
3428	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvtss2si_i32_r32;
3429
3430	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvttss2si_i64_r32;
3431	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvtss2si_i64_r32;
3432
3433	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R32I32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT32U pr32Dst, const int32_t pi32Src));
3434	typedef FNIEMAIMPLSSEF2R32I32 *PFNIEMAIMPLSSEF2R32I32;
3435	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R32I64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT32U pr32Dst, const int64_t pi64Src));
3436	typedef FNIEMAIMPLSSEF2R32I64 *PFNIEMAIMPLSSEF2R32I64;
3437
3438	FNIEMAIMPLSSEF2R32I32 iemAImpl_cvtsi2ss_r32_i32;
3439	FNIEMAIMPLSSEF2R32I64 iemAImpl_cvtsi2ss_r32_i64;
3440
3441	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R64I32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT64U pr64Dst, const int32_t pi32Src));
3442	typedef FNIEMAIMPLSSEF2R64I32 *PFNIEMAIMPLSSEF2R64I32;
3443	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R64I64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT64U pr64Dst, const int64_t pi64Src));
3444	typedef FNIEMAIMPLSSEF2R64I64 *PFNIEMAIMPLSSEF2R64I64;
3445
3446	FNIEMAIMPLSSEF2R64I32 iemAImpl_cvtsi2sd_r64_i32;
3447	FNIEMAIMPLSSEF2R64I64 iemAImpl_cvtsi2sd_r64_i64;
3448
3449
3450	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFLMXCSR128,(uint32_t pfMxcsr, uint32_t pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
3451	typedef FNIEMAIMPLF2EFLMXCSR128 *PFNIEMAIMPLF2EFLMXCSR128;
3452
3453	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_ucomiss_u128;
3454	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback;
3455
3456	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_ucomisd_u128;
3457	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback;
3458
3459	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_comiss_u128;
3460	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback;
3461
3462	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_comisd_u128;
3463	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback;
3464
3465
3466	typedef struct IEMMEDIAF2XMMSRC
3467	{
3468	X86XMMREG uSrc1;
3469	X86XMMREG uSrc2;
3470	} IEMMEDIAF2XMMSRC;
3471	typedef IEMMEDIAF2XMMSRC *PIEMMEDIAF2XMMSRC;
3472	typedef const IEMMEDIAF2XMMSRC *PCIEMMEDIAF2XMMSRC;
3473
3474	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRF2XMMIMM8,(uint32_t *pfMxcsr, PX86XMMREG puDst, PCIEMMEDIAF2XMMSRC puSrc, uint8_t bEvil));
3475	typedef FNIEMAIMPLMXCSRF2XMMIMM8 *PFNIEMAIMPLMXCSRF2XMMIMM8;
3476
3477	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpps_u128;
3478	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmppd_u128;
3479	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpss_u128;
3480	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpsd_u128;
3481	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundss_u128;
3482	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundsd_u128;
3483
3484	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundps_u128, iemAImpl_roundps_u128_fallback;
3485	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundpd_u128, iemAImpl_roundpd_u128_fallback;
3486
3487	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_dpps_u128, iemAImpl_dpps_u128_fallback;
3488	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_dppd_u128, iemAImpl_dppd_u128_fallback;
3489
3490	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU64U128,(uint32_t pfMxcsr, uint64_t pu64Dst, PCX86XMMREG pSrc));
3491	typedef FNIEMAIMPLMXCSRU64U128 *PFNIEMAIMPLMXCSRU64U128;
3492
3493	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvtpd2pi_u128;
3494	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvttpd2pi_u128;
3495
3496	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU128U64,(uint32_t *pfMxcsr, PX86XMMREG pDst, uint64_t u64Src));
3497	typedef FNIEMAIMPLMXCSRU128U64 *PFNIEMAIMPLMXCSRU128U64;
3498
3499	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2ps_u128;
3500	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2pd_u128;
3501
3502	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU64U64,(uint32_t pfMxcsr, uint64_t pu64Dst, uint64_t u64Src));
3503	typedef FNIEMAIMPLMXCSRU64U64 *PFNIEMAIMPLMXCSRU64U64;
3504
3505	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvtps2pi_u128;
3506	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvttps2pi_u128;
3507
3508	/** @} */
3509
3510
3511	/** @name Function tables.
3512	* @{
3513	*/
3514
3515	/**
3516	* Function table for a binary operator providing implementation based on
3517	* operand size.
3518	*/
3519	typedef struct IEMOPBINSIZES
3520	{
3521	PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
3522	PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
3523	PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
3524	PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
3525	} IEMOPBINSIZES;
3526	/** Pointer to a binary operator function table. */
3527	typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
3528
3529
3530	/**
3531	* Function table for a unary operator providing implementation based on
3532	* operand size.
3533	*/
3534	typedef struct IEMOPUNARYSIZES
3535	{
3536	PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
3537	PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
3538	PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
3539	PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
3540	} IEMOPUNARYSIZES;
3541	/** Pointer to a unary operator function table. */
3542	typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
3543
3544
3545	/**
3546	* Function table for a shift operator providing implementation based on
3547	* operand size.
3548	*/
3549	typedef struct IEMOPSHIFTSIZES
3550	{
3551	PFNIEMAIMPLSHIFTU8 pfnNormalU8;
3552	PFNIEMAIMPLSHIFTU16 pfnNormalU16;
3553	PFNIEMAIMPLSHIFTU32 pfnNormalU32;
3554	PFNIEMAIMPLSHIFTU64 pfnNormalU64;
3555	} IEMOPSHIFTSIZES;
3556	/** Pointer to a shift operator function table. */
3557	typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
3558
3559
3560	/**
3561	* Function table for a multiplication or division operation.
3562	*/
3563	typedef struct IEMOPMULDIVSIZES
3564	{
3565	PFNIEMAIMPLMULDIVU8 pfnU8;
3566	PFNIEMAIMPLMULDIVU16 pfnU16;
3567	PFNIEMAIMPLMULDIVU32 pfnU32;
3568	PFNIEMAIMPLMULDIVU64 pfnU64;
3569	} IEMOPMULDIVSIZES;
3570	/** Pointer to a multiplication or division operation function table. */
3571	typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
3572
3573
3574	/**
3575	* Function table for a double precision shift operator providing implementation
3576	* based on operand size.
3577	*/
3578	typedef struct IEMOPSHIFTDBLSIZES
3579	{
3580	PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
3581	PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
3582	PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
3583	} IEMOPSHIFTDBLSIZES;
3584	/** Pointer to a double precision shift function table. */
3585	typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
3586
3587
3588	/**
3589	* Function table for media instruction taking two full sized media source
3590	* registers and one full sized destination register (AVX).
3591	*/
3592	typedef struct IEMOPMEDIAF3
3593	{
3594	PFNIEMAIMPLMEDIAF3U128 pfnU128;
3595	PFNIEMAIMPLMEDIAF3U256 pfnU256;
3596	} IEMOPMEDIAF3;
3597	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
3598	typedef IEMOPMEDIAF3 const *PCIEMOPMEDIAF3;
3599
3600	/** @def IEMOPMEDIAF3_INIT_VARS_EX
3601	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3602	* given functions as initializers. For use in AVX functions where a pair of
3603	* functions are only used once and the function table need not be public. */
3604	#ifndef TST_IEM_CHECK_MC
3605	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3606	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3607	static IEMOPMEDIAF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3608	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3609	# else
3610	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3611	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3612	# endif
3613	#else
3614	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3615	#endif
3616	/** @def IEMOPMEDIAF3_INIT_VARS
3617	* Generate AVX function tables for the @a a_InstrNm instruction.
3618	* @sa IEMOPMEDIAF3_INIT_VARS_EX */
3619	#define IEMOPMEDIAF3_INIT_VARS(a_InstrNm) \
3620	IEMOPMEDIAF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3621	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3622
3623	/**
3624	* Function table for media instruction taking two full sized media source
3625	* registers and one full sized destination register, but no additional state
3626	* (AVX).
3627	*/
3628	typedef struct IEMOPMEDIAOPTF3
3629	{
3630	PFNIEMAIMPLMEDIAOPTF3U128 pfnU128;
3631	PFNIEMAIMPLMEDIAOPTF3U256 pfnU256;
3632	} IEMOPMEDIAOPTF3;
3633	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
3634	typedef IEMOPMEDIAOPTF3 const *PCIEMOPMEDIAOPTF3;
3635
3636	/** @def IEMOPMEDIAOPTF3_INIT_VARS_EX
3637	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3638	* given functions as initializers. For use in AVX functions where a pair of
3639	* functions are only used once and the function table need not be public. */
3640	#ifndef TST_IEM_CHECK_MC
3641	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3642	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3643	static IEMOPMEDIAOPTF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3644	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3645	# else
3646	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3647	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3648	# endif
3649	#else
3650	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3651	#endif
3652	/** @def IEMOPMEDIAOPTF3_INIT_VARS
3653	* Generate AVX function tables for the @a a_InstrNm instruction.
3654	* @sa IEMOPMEDIAOPTF3_INIT_VARS_EX */
3655	#define IEMOPMEDIAOPTF3_INIT_VARS(a_InstrNm) \
3656	IEMOPMEDIAOPTF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3657	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3658
3659	/**
3660	* Function table for media instruction taking one full sized media source
3661	* registers and one full sized destination register, but no additional state
3662	* (AVX).
3663	*/
3664	typedef struct IEMOPMEDIAOPTF2
3665	{
3666	PFNIEMAIMPLMEDIAOPTF2U128 pfnU128;
3667	PFNIEMAIMPLMEDIAOPTF2U256 pfnU256;
3668	} IEMOPMEDIAOPTF2;
3669	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
3670	typedef IEMOPMEDIAOPTF2 const *PCIEMOPMEDIAOPTF2;
3671
3672	/** @def IEMOPMEDIAOPTF2_INIT_VARS_EX
3673	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3674	* given functions as initializers. For use in AVX functions where a pair of
3675	* functions are only used once and the function table need not be public. */
3676	#ifndef TST_IEM_CHECK_MC
3677	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3678	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3679	static IEMOPMEDIAOPTF2 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3680	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3681	# else
3682	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3683	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3684	# endif
3685	#else
3686	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3687	#endif
3688	/** @def IEMOPMEDIAOPTF2_INIT_VARS
3689	* Generate AVX function tables for the @a a_InstrNm instruction.
3690	* @sa IEMOPMEDIAOPTF2_INIT_VARS_EX */
3691	#define IEMOPMEDIAOPTF2_INIT_VARS(a_InstrNm) \
3692	IEMOPMEDIAOPTF2_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3693	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3694
3695	/**
3696	* Function table for media instruction taking two full sized media source
3697	* registers and one full sized destination register and an 8-bit immediate, but no additional state
3698	* (AVX).
3699	*/
3700	typedef struct IEMOPMEDIAOPTF3IMM8
3701	{
3702	PFNIEMAIMPLMEDIAOPTF3U128IMM8 pfnU128;
3703	PFNIEMAIMPLMEDIAOPTF3U256IMM8 pfnU256;
3704	} IEMOPMEDIAOPTF3IMM8;
3705	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
3706	typedef IEMOPMEDIAOPTF3IMM8 const *PCIEMOPMEDIAOPTF3IMM8;
3707
3708	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX
3709	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3710	* given functions as initializers. For use in AVX functions where a pair of
3711	* functions are only used once and the function table need not be public. */
3712	#ifndef TST_IEM_CHECK_MC
3713	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3714	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3715	static IEMOPMEDIAOPTF3IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3716	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3717	# else
3718	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3719	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3720	# endif
3721	#else
3722	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3723	#endif
3724	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS
3725	* Generate AVX function tables for the @a a_InstrNm instruction.
3726	* @sa IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX */
3727	#define IEMOPMEDIAOPTF3IMM8_INIT_VARS(a_InstrNm) \
3728	IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3729	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3730	/** @} */
3731
3732
3733	/**
3734	* Function table for blend type instruction taking three full sized media source
3735	* registers and one full sized destination register, but no additional state
3736	* (AVX).
3737	*/
3738	typedef struct IEMOPBLENDOP
3739	{
3740	PFNIEMAIMPLAVXBLENDU128 pfnU128;
3741	PFNIEMAIMPLAVXBLENDU256 pfnU256;
3742	} IEMOPBLENDOP;
3743	/** Pointer to a media operation function table for 4 full sized ops (AVX). */
3744	typedef IEMOPBLENDOP const *PCIEMOPBLENDOP;
3745
3746	/** @def IEMOPBLENDOP_INIT_VARS_EX
3747	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3748	* given functions as initializers. For use in AVX functions where a pair of
3749	* functions are only used once and the function table need not be public. */
3750	#ifndef TST_IEM_CHECK_MC
3751	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3752	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3753	static IEMOPBLENDOP const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3754	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3755	# else
3756	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3757	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3758	# endif
3759	#else
3760	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3761	#endif
3762	/** @def IEMOPBLENDOP_INIT_VARS
3763	* Generate AVX function tables for the @a a_InstrNm instruction.
3764	* @sa IEMOPBLENDOP_INIT_VARS_EX */
3765	#define IEMOPBLENDOP_INIT_VARS(a_InstrNm) \
3766	IEMOPBLENDOP_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3767	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3768
3769
3770	/** @name SSE/AVX single/double precision floating point operations.
3771	* @{ */
3772	/**
3773	* A SSE result.
3774	*/
3775	typedef struct IEMSSERESULT
3776	{
3777	/** The output value. */
3778	X86XMMREG uResult;
3779	/** The output status. */
3780	uint32_t MXCSR;
3781	} IEMSSERESULT;
3782	AssertCompileMemberOffset(IEMSSERESULT, MXCSR, 128 / 8);
3783	/** Pointer to a SSE result. */
3784	typedef IEMSSERESULT *PIEMSSERESULT;
3785	/** Pointer to a const SSE result. */
3786	typedef IEMSSERESULT const *PCIEMSSERESULT;
3787
3788
3789	/**
3790	* A AVX128 result.
3791	*/
3792	typedef struct IEMAVX128RESULT
3793	{
3794	/** The output value. */
3795	X86XMMREG uResult;
3796	/** The output status. */
3797	uint32_t MXCSR;
3798	} IEMAVX128RESULT;
3799	AssertCompileMemberOffset(IEMAVX128RESULT, MXCSR, 128 / 8);
3800	/** Pointer to a AVX128 result. */
3801	typedef IEMAVX128RESULT *PIEMAVX128RESULT;
3802	/** Pointer to a const AVX128 result. */
3803	typedef IEMAVX128RESULT const *PCIEMAVX128RESULT;
3804
3805
3806	/**
3807	* A AVX256 result.
3808	*/
3809	typedef struct IEMAVX256RESULT
3810	{
3811	/** The output value. */
3812	X86YMMREG uResult;
3813	/** The output status. */
3814	uint32_t MXCSR;
3815	} IEMAVX256RESULT;
3816	AssertCompileMemberOffset(IEMAVX256RESULT, MXCSR, 256 / 8);
3817	/** Pointer to a AVX256 result. */
3818	typedef IEMAVX256RESULT *PIEMAVX256RESULT;
3819	/** Pointer to a const AVX256 result. */
3820	typedef IEMAVX256RESULT const *PCIEMAVX256RESULT;
3821
3822
3823	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
3824	typedef FNIEMAIMPLFPSSEF2U128 *PFNIEMAIMPLFPSSEF2U128;
3825	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128R32,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
3826	typedef FNIEMAIMPLFPSSEF2U128R32 *PFNIEMAIMPLFPSSEF2U128R32;
3827	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128R64,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
3828	typedef FNIEMAIMPLFPSSEF2U128R64 *PFNIEMAIMPLFPSSEF2U128R64;
3829
3830	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
3831	typedef FNIEMAIMPLFPAVXF3U128 *PFNIEMAIMPLFPAVXF3U128;
3832	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128R32,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
3833	typedef FNIEMAIMPLFPAVXF3U128R32 *PFNIEMAIMPLFPAVXF3U128R32;
3834	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128R64,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
3835	typedef FNIEMAIMPLFPAVXF3U128R64 *PFNIEMAIMPLFPAVXF3U128R64;
3836
3837	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U256,(PX86XSAVEAREA pExtState, PIEMAVX256RESULT pResult, PCX86YMMREG puSrc1, PCX86YMMREG puSrc2));
3838	typedef FNIEMAIMPLFPAVXF3U256 *PFNIEMAIMPLFPAVXF3U256;
3839
3840	FNIEMAIMPLFPSSEF2U128 iemAImpl_addps_u128;
3841	FNIEMAIMPLFPSSEF2U128 iemAImpl_addpd_u128;
3842	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulps_u128;
3843	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulpd_u128;
3844	FNIEMAIMPLFPSSEF2U128 iemAImpl_subps_u128;
3845	FNIEMAIMPLFPSSEF2U128 iemAImpl_subpd_u128;
3846	FNIEMAIMPLFPSSEF2U128 iemAImpl_minps_u128;
3847	FNIEMAIMPLFPSSEF2U128 iemAImpl_minpd_u128;
3848	FNIEMAIMPLFPSSEF2U128 iemAImpl_divps_u128;
3849	FNIEMAIMPLFPSSEF2U128 iemAImpl_divpd_u128;
3850	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxps_u128;
3851	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxpd_u128;
3852	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddps_u128;
3853	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddpd_u128;
3854	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubps_u128;
3855	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubpd_u128;
3856	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtps_u128;
3857	FNIEMAIMPLFPSSEF2U128 iemAImpl_rsqrtps_u128;
3858	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtpd_u128;
3859	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubps_u128;
3860	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubpd_u128;
3861	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2ps_u128;
3862	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2pd_u128;
3863
3864	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2ps_u128;
3865	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2dq_u128;
3866	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttps2dq_u128;
3867	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttpd2dq_u128;
3868	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2pd_u128;
3869	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2dq_u128;
3870
3871	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_addss_u128_r32;
3872	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_addsd_u128_r64;
3873	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_mulss_u128_r32;
3874	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_mulsd_u128_r64;
3875	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_subss_u128_r32;
3876	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_subsd_u128_r64;
3877	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_minss_u128_r32;
3878	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_minsd_u128_r64;
3879	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_divss_u128_r32;
3880	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_divsd_u128_r64;
3881	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_maxss_u128_r32;
3882	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_maxsd_u128_r64;
3883	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_cvtss2sd_u128_r32;
3884	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_cvtsd2ss_u128_r64;
3885	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_sqrtss_u128_r32;
3886	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_sqrtsd_u128_r64;
3887	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_rsqrtss_u128_r32;
3888
3889	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddps_u128, iemAImpl_vaddps_u128_fallback;
3890	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddpd_u128, iemAImpl_vaddpd_u128_fallback;
3891	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulps_u128, iemAImpl_vmulps_u128_fallback;
3892	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulpd_u128, iemAImpl_vmulpd_u128_fallback;
3893	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubps_u128, iemAImpl_vsubps_u128_fallback;
3894	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubpd_u128, iemAImpl_vsubpd_u128_fallback;
3895	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminps_u128, iemAImpl_vminps_u128_fallback;
3896	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminpd_u128, iemAImpl_vminpd_u128_fallback;
3897	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivps_u128, iemAImpl_vdivps_u128_fallback;
3898	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivpd_u128, iemAImpl_vdivpd_u128_fallback;
3899	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxps_u128, iemAImpl_vmaxps_u128_fallback;
3900	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxpd_u128, iemAImpl_vmaxpd_u128_fallback;
3901	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddps_u128, iemAImpl_vhaddps_u128_fallback;
3902	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddpd_u128, iemAImpl_vhaddpd_u128_fallback;
3903	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubps_u128, iemAImpl_vhsubps_u128_fallback;
3904	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubpd_u128, iemAImpl_vhsubpd_u128_fallback;
3905	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtps_u128, iemAImpl_vsqrtps_u128_fallback;
3906	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtpd_u128, iemAImpl_vsqrtpd_u128_fallback;
3907	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubps_u128, iemAImpl_vaddsubps_u128_fallback;
3908	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubpd_u128, iemAImpl_vaddsubpd_u128_fallback;
3909	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtpd2ps_u128, iemAImpl_vcvtpd2ps_u128_fallback;
3910	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtps2pd_u128, iemAImpl_vcvtps2pd_u128_fallback;
3911
3912	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vaddss_u128_r32, iemAImpl_vaddss_u128_r32_fallback;
3913	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vaddsd_u128_r64, iemAImpl_vaddsd_u128_r64_fallback;
3914	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmulss_u128_r32, iemAImpl_vmulss_u128_r32_fallback;
3915	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmulsd_u128_r64, iemAImpl_vmulsd_u128_r64_fallback;
3916	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsubss_u128_r32, iemAImpl_vsubss_u128_r32_fallback;
3917	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsubsd_u128_r64, iemAImpl_vsubsd_u128_r64_fallback;
3918	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vminss_u128_r32, iemAImpl_vminss_u128_r32_fallback;
3919	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vminsd_u128_r64, iemAImpl_vminsd_u128_r64_fallback;
3920	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vdivss_u128_r32, iemAImpl_vdivss_u128_r32_fallback;
3921	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vdivsd_u128_r64, iemAImpl_vdivsd_u128_r64_fallback;
3922	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmaxss_u128_r32, iemAImpl_vmaxss_u128_r32_fallback;
3923	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmaxsd_u128_r64, iemAImpl_vmaxsd_u128_r64_fallback;
3924	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsqrtss_u128_r32, iemAImpl_vsqrtss_u128_r32_fallback;
3925	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsqrtsd_u128_r64, iemAImpl_vsqrtsd_u128_r64_fallback;
3926
3927	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddps_u256, iemAImpl_vaddps_u256_fallback;
3928	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddpd_u256, iemAImpl_vaddpd_u256_fallback;
3929	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulps_u256, iemAImpl_vmulps_u256_fallback;
3930	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulpd_u256, iemAImpl_vmulpd_u256_fallback;
3931	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubps_u256, iemAImpl_vsubps_u256_fallback;
3932	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubpd_u256, iemAImpl_vsubpd_u256_fallback;
3933	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminps_u256, iemAImpl_vminps_u256_fallback;
3934	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminpd_u256, iemAImpl_vminpd_u256_fallback;
3935	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivps_u256, iemAImpl_vdivps_u256_fallback;
3936	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivpd_u256, iemAImpl_vdivpd_u256_fallback;
3937	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxps_u256, iemAImpl_vmaxps_u256_fallback;
3938	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxpd_u256, iemAImpl_vmaxpd_u256_fallback;
3939	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddps_u256, iemAImpl_vhaddps_u256_fallback;
3940	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddpd_u256, iemAImpl_vhaddpd_u256_fallback;
3941	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubps_u256, iemAImpl_vhsubps_u256_fallback;
3942	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubpd_u256, iemAImpl_vhsubpd_u256_fallback;
3943	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubps_u256, iemAImpl_vhaddsubps_u256_fallback;
3944	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubpd_u256, iemAImpl_vhaddsubpd_u256_fallback;
3945	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtpd2ps_u256, iemAImpl_vcvtpd2ps_u256_fallback;
3946	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtps2pd_u256, iemAImpl_vcvtps2pd_u256_fallback;
3947	/** @} */
3948
3949	/** @name C instruction implementations for anything slightly complicated.
3950	* @{ */
3951
3952	/**
3953	* For typedef'ing or declaring a C instruction implementation function taking
3954	* no extra arguments.
3955	*
3956	* @param a_Name The name of the type.
3957	*/
3958	# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
3959	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
3960	/**
3961	* For defining a C instruction implementation function taking no extra
3962	* arguments.
3963	*
3964	* @param a_Name The name of the function
3965	*/
3966	# define IEM_CIMPL_DEF_0(a_Name) \
3967	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
3968	/**
3969	* Prototype version of IEM_CIMPL_DEF_0.
3970	*/
3971	# define IEM_CIMPL_PROTO_0(a_Name) \
3972	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
3973	/**
3974	* For calling a C instruction implementation function taking no extra
3975	* arguments.
3976	*
3977	* This special call macro adds default arguments to the call and allow us to
3978	* change these later.
3979	*
3980	* @param a_fn The name of the function.
3981	*/
3982	# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
3983
3984	/** Type for a C instruction implementation function taking no extra
3985	* arguments. */
3986	typedef IEM_CIMPL_DECL_TYPE_0(FNIEMCIMPL0);
3987	/** Function pointer type for a C instruction implementation function taking
3988	* no extra arguments. */
3989	typedef FNIEMCIMPL0 *PFNIEMCIMPL0;
3990
3991	/**
3992	* For typedef'ing or declaring a C instruction implementation function taking
3993	* one extra argument.
3994	*
3995	* @param a_Name The name of the type.
3996	* @param a_Type0 The argument type.
3997	* @param a_Arg0 The argument name.
3998	*/
3999	# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
4000	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
4001	/**
4002	* For defining a C instruction implementation function taking one extra
4003	* argument.
4004	*
4005	* @param a_Name The name of the function
4006	* @param a_Type0 The argument type.
4007	* @param a_Arg0 The argument name.
4008	*/
4009	# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
4010	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
4011	/**
4012	* Prototype version of IEM_CIMPL_DEF_1.
4013	*/
4014	# define IEM_CIMPL_PROTO_1(a_Name, a_Type0, a_Arg0) \
4015	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
4016	/**
4017	* For calling a C instruction implementation function taking one extra
4018	* argument.
4019	*
4020	* This special call macro adds default arguments to the call and allow us to
4021	* change these later.
4022	*
4023	* @param a_fn The name of the function.
4024	* @param a0 The name of the 1st argument.
4025	*/
4026	# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
4027
4028	/**
4029	* For typedef'ing or declaring a C instruction implementation function taking
4030	* two extra arguments.
4031	*
4032	* @param a_Name The name of the type.
4033	* @param a_Type0 The type of the 1st argument
4034	* @param a_Arg0 The name of the 1st argument.
4035	* @param a_Type1 The type of the 2nd argument.
4036	* @param a_Arg1 The name of the 2nd argument.
4037	*/
4038	# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
4039	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
4040	/**
4041	* For defining a C instruction implementation function taking two extra
4042	* arguments.
4043	*
4044	* @param a_Name The name of the function.
4045	* @param a_Type0 The type of the 1st argument
4046	* @param a_Arg0 The name of the 1st argument.
4047	* @param a_Type1 The type of the 2nd argument.
4048	* @param a_Arg1 The name of the 2nd argument.
4049	*/
4050	# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
4051	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
4052	/**
4053	* Prototype version of IEM_CIMPL_DEF_2.
4054	*/
4055	# define IEM_CIMPL_PROTO_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
4056	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
4057	/**
4058	* For calling a C instruction implementation function taking two extra
4059	* arguments.
4060	*
4061	* This special call macro adds default arguments to the call and allow us to
4062	* change these later.
4063	*
4064	* @param a_fn The name of the function.
4065	* @param a0 The name of the 1st argument.
4066	* @param a1 The name of the 2nd argument.
4067	*/
4068	# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
4069
4070	/**
4071	* For typedef'ing or declaring a C instruction implementation function taking
4072	* three extra arguments.
4073	*
4074	* @param a_Name The name of the type.
4075	* @param a_Type0 The type of the 1st argument
4076	* @param a_Arg0 The name of the 1st argument.
4077	* @param a_Type1 The type of the 2nd argument.
4078	* @param a_Arg1 The name of the 2nd argument.
4079	* @param a_Type2 The type of the 3rd argument.
4080	* @param a_Arg2 The name of the 3rd argument.
4081	*/
4082	# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
4083	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
4084	/**
4085	* For defining a C instruction implementation function taking three extra
4086	* arguments.
4087	*
4088	* @param a_Name The name of the function.
4089	* @param a_Type0 The type of the 1st argument
4090	* @param a_Arg0 The name of the 1st argument.
4091	* @param a_Type1 The type of the 2nd argument.
4092	* @param a_Arg1 The name of the 2nd argument.
4093	* @param a_Type2 The type of the 3rd argument.
4094	* @param a_Arg2 The name of the 3rd argument.
4095	*/
4096	# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
4097	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
4098	/**
4099	* Prototype version of IEM_CIMPL_DEF_3.
4100	*/
4101	# define IEM_CIMPL_PROTO_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
4102	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
4103	/**
4104	* For calling a C instruction implementation function taking three extra
4105	* arguments.
4106	*
4107	* This special call macro adds default arguments to the call and allow us to
4108	* change these later.
4109	*
4110	* @param a_fn The name of the function.
4111	* @param a0 The name of the 1st argument.
4112	* @param a1 The name of the 2nd argument.
4113	* @param a2 The name of the 3rd argument.
4114	*/
4115	# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
4116
4117
4118	/**
4119	* For typedef'ing or declaring a C instruction implementation function taking
4120	* four extra arguments.
4121	*
4122	* @param a_Name The name of the type.
4123	* @param a_Type0 The type of the 1st argument
4124	* @param a_Arg0 The name of the 1st argument.
4125	* @param a_Type1 The type of the 2nd argument.
4126	* @param a_Arg1 The name of the 2nd argument.
4127	* @param a_Type2 The type of the 3rd argument.
4128	* @param a_Arg2 The name of the 3rd argument.
4129	* @param a_Type3 The type of the 4th argument.
4130	* @param a_Arg3 The name of the 4th argument.
4131	*/
4132	# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
4133	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
4134	/**
4135	* For defining a C instruction implementation function taking four extra
4136	* arguments.
4137	*
4138	* @param a_Name The name of the function.
4139	* @param a_Type0 The type of the 1st argument
4140	* @param a_Arg0 The name of the 1st argument.
4141	* @param a_Type1 The type of the 2nd argument.
4142	* @param a_Arg1 The name of the 2nd argument.
4143	* @param a_Type2 The type of the 3rd argument.
4144	* @param a_Arg2 The name of the 3rd argument.
4145	* @param a_Type3 The type of the 4th argument.
4146	* @param a_Arg3 The name of the 4th argument.
4147	*/
4148	# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
4149	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4150	a_Type2 a_Arg2, a_Type3 a_Arg3))
4151	/**
4152	* Prototype version of IEM_CIMPL_DEF_4.
4153	*/
4154	# define IEM_CIMPL_PROTO_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
4155	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4156	a_Type2 a_Arg2, a_Type3 a_Arg3))
4157	/**
4158	* For calling a C instruction implementation function taking four extra
4159	* arguments.
4160	*
4161	* This special call macro adds default arguments to the call and allow us to
4162	* change these later.
4163	*
4164	* @param a_fn The name of the function.
4165	* @param a0 The name of the 1st argument.
4166	* @param a1 The name of the 2nd argument.
4167	* @param a2 The name of the 3rd argument.
4168	* @param a3 The name of the 4th argument.
4169	*/
4170	# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
4171
4172
4173	/**
4174	* For typedef'ing or declaring a C instruction implementation function taking
4175	* five extra arguments.
4176	*
4177	* @param a_Name The name of the type.
4178	* @param a_Type0 The type of the 1st argument
4179	* @param a_Arg0 The name of the 1st argument.
4180	* @param a_Type1 The type of the 2nd argument.
4181	* @param a_Arg1 The name of the 2nd argument.
4182	* @param a_Type2 The type of the 3rd argument.
4183	* @param a_Arg2 The name of the 3rd argument.
4184	* @param a_Type3 The type of the 4th argument.
4185	* @param a_Arg3 The name of the 4th argument.
4186	* @param a_Type4 The type of the 5th argument.
4187	* @param a_Arg4 The name of the 5th argument.
4188	*/
4189	# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
4190	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, \
4191	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
4192	a_Type3 a_Arg3, a_Type4 a_Arg4))
4193	/**
4194	* For defining a C instruction implementation function taking five extra
4195	* arguments.
4196	*
4197	* @param a_Name The name of the function.
4198	* @param a_Type0 The type of the 1st argument
4199	* @param a_Arg0 The name of the 1st argument.
4200	* @param a_Type1 The type of the 2nd argument.
4201	* @param a_Arg1 The name of the 2nd argument.
4202	* @param a_Type2 The type of the 3rd argument.
4203	* @param a_Arg2 The name of the 3rd argument.
4204	* @param a_Type3 The type of the 4th argument.
4205	* @param a_Arg3 The name of the 4th argument.
4206	* @param a_Type4 The type of the 5th argument.
4207	* @param a_Arg4 The name of the 5th argument.
4208	*/
4209	# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
4210	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4211	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
4212	/**
4213	* Prototype version of IEM_CIMPL_DEF_5.
4214	*/
4215	# define IEM_CIMPL_PROTO_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
4216	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4217	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
4218	/**
4219	* For calling a C instruction implementation function taking five extra
4220	* arguments.
4221	*
4222	* This special call macro adds default arguments to the call and allow us to
4223	* change these later.
4224	*
4225	* @param a_fn The name of the function.
4226	* @param a0 The name of the 1st argument.
4227	* @param a1 The name of the 2nd argument.
4228	* @param a2 The name of the 3rd argument.
4229	* @param a3 The name of the 4th argument.
4230	* @param a4 The name of the 5th argument.
4231	*/
4232	# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
4233
4234	/** @} */
4235
4236
4237	/** @name Opcode Decoder Function Types.
4238	* @{ */
4239
4240	/** @typedef PFNIEMOP
4241	* Pointer to an opcode decoder function.
4242	*/
4243
4244	/** @def FNIEMOP_DEF
4245	* Define an opcode decoder function.
4246	*
4247	* We're using macors for this so that adding and removing parameters as well as
4248	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL
4249	*
4250	* @param a_Name The function name.
4251	*/
4252
4253	/** @typedef PFNIEMOPRM
4254	* Pointer to an opcode decoder function with RM byte.
4255	*/
4256
4257	/** @def FNIEMOPRM_DEF
4258	* Define an opcode decoder function with RM byte.
4259	*
4260	* We're using macors for this so that adding and removing parameters as well as
4261	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL_1
4262	*
4263	* @param a_Name The function name.
4264	*/
4265
4266	#if defined(__GNUC__) && defined(RT_ARCH_X86)
4267	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOP)(PVMCPUCC pVCpu);
4268	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4269	# define FNIEMOP_DEF(a_Name) \
4270	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu)
4271	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4272	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
4273	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4274	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
4275
4276	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
4277	typedef VBOXSTRICTRC (__fastcall * PFNIEMOP)(PVMCPUCC pVCpu);
4278	typedef VBOXSTRICTRC (__fastcall * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4279	# define FNIEMOP_DEF(a_Name) \
4280	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
4281	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4282	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
4283	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4284	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
4285
4286	#elif defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
4287	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
4288	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4289	# define FNIEMOP_DEF(a_Name) \
4290	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu)
4291	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4292	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
4293	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4294	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
4295
4296	#else
4297	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
4298	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4299	# define FNIEMOP_DEF(a_Name) \
4300	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
4301	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4302	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
4303	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4304	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
4305
4306	#endif
4307	#define FNIEMOPRM_DEF(a_Name) FNIEMOP_DEF_1(a_Name, uint8_t, bRm)
4308
4309	/**
4310	* Call an opcode decoder function.
4311	*
4312	* We're using macors for this so that adding and removing parameters can be
4313	* done as we please. See FNIEMOP_DEF.
4314	*/
4315	#define FNIEMOP_CALL(a_pfn) (a_pfn)(pVCpu)
4316
4317	/**
4318	* Call a common opcode decoder function taking one extra argument.
4319	*
4320	* We're using macors for this so that adding and removing parameters can be
4321	* done as we please. See FNIEMOP_DEF_1.
4322	*/
4323	#define FNIEMOP_CALL_1(a_pfn, a0) (a_pfn)(pVCpu, a0)
4324
4325	/**
4326	* Call a common opcode decoder function taking one extra argument.
4327	*
4328	* We're using macors for this so that adding and removing parameters can be
4329	* done as we please. See FNIEMOP_DEF_1.
4330	*/
4331	#define FNIEMOP_CALL_2(a_pfn, a0, a1) (a_pfn)(pVCpu, a0, a1)
4332	/** @} */
4333
4334
4335	/** @name Misc Helpers
4336	* @{ */
4337
4338	/** Used to shut up GCC warnings about variables that 'may be used uninitialized'
4339	* due to GCC lacking knowledge about the value range of a switch. */
4340	#if RT_CPLUSPLUS_PREREQ(202000)
4341	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: [[unlikely]] AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
4342	#else
4343	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
4344	#endif
4345
4346	/** Variant of IEM_NOT_REACHED_DEFAULT_CASE_RET that returns a custom value. */
4347	#if RT_CPLUSPLUS_PREREQ(202000)
4348	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: [[unlikely]] AssertFailedReturn(a_RetValue)
4349	#else
4350	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: AssertFailedReturn(a_RetValue)
4351	#endif
4352
4353	/**
4354	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
4355	* occation.
4356	*/
4357	#ifdef LOG_ENABLED
4358	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
4359	do { \
4360	/Log/ LogAlways(("%s: returning IEM_RETURN_ASPECT_NOT_IMPLEMENTED (line %d)\n", __FUNCTION__, __LINE__)); \
4361	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
4362	} while (0)
4363	#else
4364	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
4365	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
4366	#endif
4367
4368	/**
4369	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
4370	* occation using the supplied logger statement.
4371	*
4372	* @param a_LoggerArgs What to log on failure.
4373	*/
4374	#ifdef LOG_ENABLED
4375	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
4376	do { \
4377	LogAlways((LOG_FN_FMT ": ", __PRETTY_FUNCTION__)); LogAlways(a_LoggerArgs); \
4378	/LogFunc(a_LoggerArgs);/ \
4379	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
4380	} while (0)
4381	#else
4382	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
4383	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
4384	#endif
4385
4386	/**
4387	* Gets the CPU mode (from fExec) as a IEMMODE value.
4388	*
4389	* @returns IEMMODE
4390	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4391	*/
4392	#define IEM_GET_CPU_MODE(a_pVCpu) ((a_pVCpu)->iem.s.fExec & IEM_F_MODE_CPUMODE_MASK)
4393
4394	/**
4395	* Check if we're currently executing in real or virtual 8086 mode.
4396	*
4397	* @returns @c true if it is, @c false if not.
4398	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4399	*/
4400	#define IEM_IS_REAL_OR_V86_MODE(a_pVCpu) (( ((a_pVCpu)->iem.s.fExec ^ IEM_F_MODE_X86_PROT_MASK) \
4401	& (IEM_F_MODE_X86_V86_MASK \| IEM_F_MODE_X86_PROT_MASK)) != 0)
4402
4403	/**
4404	* Check if we're currently executing in virtual 8086 mode.
4405	*
4406	* @returns @c true if it is, @c false if not.
4407	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4408	*/
4409	#define IEM_IS_V86_MODE(a_pVCpu) (((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_V86_MASK) != 0)
4410
4411	/**
4412	* Check if we're currently executing in long mode.
4413	*
4414	* @returns @c true if it is, @c false if not.
4415	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4416	*/
4417	#define IEM_IS_LONG_MODE(a_pVCpu) (CPUMIsGuestInLongModeEx(IEM_GET_CTX(a_pVCpu)))
4418
4419	/**
4420	* Check if we're currently executing in a 16-bit code segment.
4421	*
4422	* @returns @c true if it is, @c false if not.
4423	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4424	*/
4425	#define IEM_IS_16BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_16BIT)
4426
4427	/**
4428	* Check if we're currently executing in a 32-bit code segment.
4429	*
4430	* @returns @c true if it is, @c false if not.
4431	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4432	*/
4433	#define IEM_IS_32BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_32BIT)
4434
4435	/**
4436	* Check if we're currently executing in a 64-bit code segment.
4437	*
4438	* @returns @c true if it is, @c false if not.
4439	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4440	*/
4441	#define IEM_IS_64BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_64BIT)
4442
4443	/**
4444	* Check if we're currently executing in real mode.
4445	*
4446	* @returns @c true if it is, @c false if not.
4447	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4448	*/
4449	#define IEM_IS_REAL_MODE(a_pVCpu) (!((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_PROT_MASK))
4450
4451	/**
4452	* Gets the current protection level (CPL).
4453	*
4454	* @returns 0..3
4455	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4456	*/
4457	#define IEM_GET_CPL(a_pVCpu) (((a_pVCpu)->iem.s.fExec >> IEM_F_X86_CPL_SHIFT) & IEM_F_X86_CPL_SMASK)
4458
4459	/**
4460	* Sets the current protection level (CPL).
4461	*
4462	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4463	*/
4464	#define IEM_SET_CPL(a_pVCpu, a_uCpl) \
4465	do { (a_pVCpu)->iem.s.fExec = ((a_pVCpu)->iem.s.fExec & ~IEM_F_X86_CPL_MASK) \| ((a_uCpl) << IEM_F_X86_CPL_SHIFT); } while (0)
4466
4467	/**
4468	* Returns a (const) pointer to the CPUMFEATURES for the guest CPU.
4469	* @returns PCCPUMFEATURES
4470	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4471	*/
4472	#define IEM_GET_GUEST_CPU_FEATURES(a_pVCpu) (&((a_pVCpu)->CTX_SUFF(pVM)->cpum.ro.GuestFeatures))
4473
4474	/**
4475	* Returns a (const) pointer to the CPUMFEATURES for the host CPU.
4476	* @returns PCCPUMFEATURES
4477	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4478	*/
4479	#define IEM_GET_HOST_CPU_FEATURES(a_pVCpu) (&g_CpumHostFeatures.s)
4480
4481	/**
4482	* Evaluates to true if we're presenting an Intel CPU to the guest.
4483	*/
4484	#define IEM_IS_GUEST_CPU_INTEL(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL )
4485
4486	/**
4487	* Evaluates to true if we're presenting an AMD CPU to the guest.
4488	*/
4489	#define IEM_IS_GUEST_CPU_AMD(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_AMD \|\| (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_HYGON )
4490
4491	/**
4492	* Check if the address is canonical.
4493	*/
4494	#define IEM_IS_CANONICAL(a_u64Addr) X86_IS_CANONICAL(a_u64Addr)
4495
4496	/** Checks if the ModR/M byte is in register mode or not. */
4497	#define IEM_IS_MODRM_REG_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT) )
4498	/** Checks if the ModR/M byte is in memory mode or not. */
4499	#define IEM_IS_MODRM_MEM_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT) )
4500
4501	/**
4502	* Gets the register (reg) part of a ModR/M encoding, with REX.R added in.
4503	*
4504	* For use during decoding.
4505	*/
4506	#define IEM_GET_MODRM_REG(a_pVCpu, a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| (a_pVCpu)->iem.s.uRexReg )
4507	/**
4508	* Gets the r/m part of a ModR/M encoding as a register index, with REX.B added in.
4509	*
4510	* For use during decoding.
4511	*/
4512	#define IEM_GET_MODRM_RM(a_pVCpu, a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) \| (a_pVCpu)->iem.s.uRexB )
4513
4514	/**
4515	* Gets the register (reg) part of a ModR/M encoding, without REX.R.
4516	*
4517	* For use during decoding.
4518	*/
4519	#define IEM_GET_MODRM_REG_8(a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) )
4520	/**
4521	* Gets the r/m part of a ModR/M encoding as a register index, without REX.B.
4522	*
4523	* For use during decoding.
4524	*/
4525	#define IEM_GET_MODRM_RM_8(a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) )
4526
4527	/**
4528	* Gets the register (reg) part of a ModR/M encoding as an extended 8-bit
4529	* register index, with REX.R added in.
4530	*
4531	* For use during decoding.
4532	*
4533	* @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
4534	*/
4535	#define IEM_GET_MODRM_REG_EX8(a_pVCpu, a_bRm) \
4536	( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
4537	\|\| !((a_bRm) & (4 << X86_MODRM_REG_SHIFT)) /* IEM_GET_MODRM_REG(pVCpu, a_bRm) < 4 */ \
4538	? IEM_GET_MODRM_REG(pVCpu, a_bRm) : (((a_bRm) >> X86_MODRM_REG_SHIFT) & 3) \| 16)
4539	/**
4540	* Gets the r/m part of a ModR/M encoding as an extended 8-bit register index,
4541	* with REX.B added in.
4542	*
4543	* For use during decoding.
4544	*
4545	* @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
4546	*/
4547	#define IEM_GET_MODRM_RM_EX8(a_pVCpu, a_bRm) \
4548	( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
4549	\|\| !((a_bRm) & 4) /* IEM_GET_MODRM_RM(pVCpu, a_bRm) < 4 */ \
4550	? IEM_GET_MODRM_RM(pVCpu, a_bRm) : ((a_bRm) & 3) \| 16)
4551
4552	/**
4553	* Combines the prefix REX and ModR/M byte for passing to
4554	* iemOpHlpCalcRmEffAddrThreadedAddr64().
4555	*
4556	* @returns The ModRM byte but with bit 3 set to REX.B and bit 4 to REX.X.
4557	* The two bits are part of the REG sub-field, which isn't needed in
4558	* iemOpHlpCalcRmEffAddrThreadedAddr64().
4559	*
4560	* For use during decoding/recompiling.
4561	*/
4562	#define IEM_GET_MODRM_EX(a_pVCpu, a_bRm) \
4563	( ((a_bRm) & ~X86_MODRM_REG_MASK) \
4564	\| (uint8_t)( (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X)) >> (26 - 3) ) )
4565	AssertCompile(IEM_OP_PRF_REX_B == RT_BIT_32(26));
4566	AssertCompile(IEM_OP_PRF_REX_X == RT_BIT_32(27));
4567
4568	/**
4569	* Gets the effective VEX.VVVV value.
4570	*
4571	* The 4th bit is ignored if not 64-bit code.
4572	* @returns effective V-register value.
4573	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4574	*/
4575	#define IEM_GET_EFFECTIVE_VVVV(a_pVCpu) \
4576	(IEM_IS_64BIT_CODE(a_pVCpu) ? (a_pVCpu)->iem.s.uVex3rdReg : (a_pVCpu)->iem.s.uVex3rdReg & 7)
4577
4578
4579	/**
4580	* Checks if we're executing inside an AMD-V or VT-x guest.
4581	*/
4582	#if defined(VBOX_WITH_NESTED_HWVIRT_VMX) \|\| defined(VBOX_WITH_NESTED_HWVIRT_SVM)
4583	# define IEM_IS_IN_GUEST(a_pVCpu) RT_BOOL((a_pVCpu)->iem.s.fExec & IEM_F_X86_CTX_IN_GUEST)
4584	#else
4585	# define IEM_IS_IN_GUEST(a_pVCpu) false
4586	#endif
4587
4588
4589	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
4590
4591	/**
4592	* Check if the guest has entered VMX root operation.
4593	*/
4594	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxRootMode(IEM_GET_CTX(a_pVCpu)))
4595
4596	/**
4597	* Check if the guest has entered VMX non-root operation.
4598	*/
4599	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) ( ((a_pVCpu)->iem.s.fExec & (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST)) \
4600	== (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST) )
4601
4602	/**
4603	* Check if the nested-guest has the given Pin-based VM-execution control set.
4604	*/
4605	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_PinCtl) (CPUMIsGuestVmxPinCtlsSet(IEM_GET_CTX(a_pVCpu), (a_PinCtl)))
4606
4607	/**
4608	* Check if the nested-guest has the given Processor-based VM-execution control set.
4609	*/
4610	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_ProcCtl) (CPUMIsGuestVmxProcCtlsSet(IEM_GET_CTX(a_pVCpu), (a_ProcCtl)))
4611
4612	/**
4613	* Check if the nested-guest has the given Secondary Processor-based VM-execution
4614	* control set.
4615	*/
4616	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_ProcCtl2) (CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(a_pVCpu), (a_ProcCtl2)))
4617
4618	/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
4619	# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
4620
4621	/** Whether a shadow VMCS is present for the given VCPU. */
4622	# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
4623
4624	/** Gets the VMXON region pointer. */
4625	# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
4626
4627	/** Gets the guest-physical address of the current VMCS for the given VCPU. */
4628	# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
4629
4630	/** Whether a current VMCS is present for the given VCPU. */
4631	# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
4632
4633	/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
4634	# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
4635	do \
4636	{ \
4637	Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
4638	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
4639	} while (0)
4640
4641	/** Clears any current VMCS for the given VCPU. */
4642	# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
4643	do \
4644	{ \
4645	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
4646	} while (0)
4647
4648	/**
4649	* Invokes the VMX VM-exit handler for an instruction intercept.
4650	*/
4651	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) \
4652	do { return iemVmxVmexitInstr((a_pVCpu), (a_uExitReason), (a_cbInstr)); } while (0)
4653
4654	/**
4655	* Invokes the VMX VM-exit handler for an instruction intercept where the
4656	* instruction provides additional VM-exit information.
4657	*/
4658	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) \
4659	do { return iemVmxVmexitInstrNeedsInfo((a_pVCpu), (a_uExitReason), (a_uInstrId), (a_cbInstr)); } while (0)
4660
4661	/**
4662	* Invokes the VMX VM-exit handler for a task switch.
4663	*/
4664	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) \
4665	do { return iemVmxVmexitTaskSwitch((a_pVCpu), (a_enmTaskSwitch), (a_SelNewTss), (a_cbInstr)); } while (0)
4666
4667	/**
4668	* Invokes the VMX VM-exit handler for MWAIT.
4669	*/
4670	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) \
4671	do { return iemVmxVmexitInstrMwait((a_pVCpu), (a_fMonitorArmed), (a_cbInstr)); } while (0)
4672
4673	/**
4674	* Invokes the VMX VM-exit handler for EPT faults.
4675	*/
4676	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) \
4677	do { return iemVmxVmexitEpt(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr); } while (0)
4678
4679	/**
4680	* Invokes the VMX VM-exit handler.
4681	*/
4682	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) \
4683	do { return iemVmxVmexit((a_pVCpu), (a_uExitReason), (a_uExitQual)); } while (0)
4684
4685	#else
4686	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (false)
4687	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (false)
4688	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_cbInstr) (false)
4689	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_cbInstr) (false)
4690	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_cbInstr) (false)
4691	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4692	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4693	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4694	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4695	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4696	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) do { return VERR_VMX_IPE_1; } while (0)
4697
4698	#endif
4699
4700	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4701	/**
4702	* Checks if we're executing a guest using AMD-V.
4703	*/
4704	# define IEM_SVM_IS_IN_GUEST(a_pVCpu) ( (a_pVCpu->iem.s.fExec & (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST)) \
4705	== (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST))
4706	/**
4707	* Check if an SVM control/instruction intercept is set.
4708	*/
4709	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) \
4710	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmCtrlInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_Intercept)))
4711
4712	/**
4713	* Check if an SVM read CRx intercept is set.
4714	*/
4715	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
4716	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
4717
4718	/**
4719	* Check if an SVM write CRx intercept is set.
4720	*/
4721	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
4722	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
4723
4724	/**
4725	* Check if an SVM read DRx intercept is set.
4726	*/
4727	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
4728	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
4729
4730	/**
4731	* Check if an SVM write DRx intercept is set.
4732	*/
4733	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
4734	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
4735
4736	/**
4737	* Check if an SVM exception intercept is set.
4738	*/
4739	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) \
4740	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmXcptInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uVector)))
4741
4742	/**
4743	* Invokes the SVM \#VMEXIT handler for the nested-guest.
4744	*/
4745	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
4746	do { return iemSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2)); } while (0)
4747
4748	/**
4749	* Invokes the 'MOV CRx' SVM \#VMEXIT handler after constructing the
4750	* corresponding decode assist information.
4751	*/
4752	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) \
4753	do \
4754	{ \
4755	uint64_t uExitInfo1; \
4756	if ( IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmDecodeAssists \
4757	&& (a_enmAccessCrX) == IEMACCESSCRX_MOV_CRX) \
4758	uExitInfo1 = SVM_EXIT1_MOV_CRX_MASK \| ((a_iGReg) & 7); \
4759	else \
4760	uExitInfo1 = 0; \
4761	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, uExitInfo1, 0); \
4762	} while (0)
4763
4764	/** Check and handles SVM nested-guest instruction intercept and updates
4765	* NRIP if needed.
4766	*/
4767	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
4768	do \
4769	{ \
4770	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept)) \
4771	{ \
4772	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
4773	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2); \
4774	} \
4775	} while (0)
4776
4777	/** Checks and handles SVM nested-guest CR0 read intercept. */
4778	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
4779	do \
4780	{ \
4781	if (!IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, 0)) \
4782	{ /* probably likely */ } \
4783	else \
4784	{ \
4785	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
4786	IEM_SVM_VMEXIT_RET(a_pVCpu, SVM_EXIT_READ_CR0, a_uExitInfo1, a_uExitInfo2); \
4787	} \
4788	} while (0)
4789
4790	/**
4791	* Updates the NextRIP (NRI) field in the nested-guest VMCB.
4792	*/
4793	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) \
4794	do { \
4795	if (IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmNextRipSave) \
4796	CPUMGuestSvmUpdateNRip(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_cbInstr)); \
4797	} while (0)
4798
4799	#else
4800	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) (false)
4801	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
4802	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
4803	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
4804	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
4805	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) (false)
4806	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { return VERR_SVM_IPE_1; } while (0)
4807	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) do { return VERR_SVM_IPE_1; } while (0)
4808	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, \
4809	a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
4810	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
4811	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) do { } while (0)
4812
4813	#endif
4814
4815	/** @} */
4816
4817	uint32_t iemCalcExecDbgFlagsSlow(PVMCPUCC pVCpu);
4818	VBOXSTRICTRC iemExecInjectPendingTrap(PVMCPUCC pVCpu);
4819
4820
4821	/**
4822	* Selector descriptor table entry as fetched by iemMemFetchSelDesc.
4823	*/
4824	typedef union IEMSELDESC
4825	{
4826	/** The legacy view. */
4827	X86DESC Legacy;
4828	/** The long mode view. */
4829	X86DESC64 Long;
4830	} IEMSELDESC;
4831	/** Pointer to a selector descriptor table entry. */
4832	typedef IEMSELDESC *PIEMSELDESC;
4833
4834	/** @name Raising Exceptions.
4835	* @{ */
4836	VBOXSTRICTRC iemTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, uint32_t uNextEip, uint32_t fFlags,
4837	uint16_t uErr, uint64_t uCr2, RTSEL SelTSS, PIEMSELDESC pNewDescTSS) RT_NOEXCEPT;
4838
4839	VBOXSTRICTRC iemRaiseXcptOrInt(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags,
4840	uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
4841	#ifdef IEM_WITH_SETJMP
4842	DECL_NO_RETURN(void) iemRaiseXcptOrIntJmp(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector,
4843	uint32_t fFlags, uint16_t uErr, uint64_t uCr2) IEM_NOEXCEPT_MAY_LONGJMP;
4844	#endif
4845	VBOXSTRICTRC iemRaiseDivideError(PVMCPUCC pVCpu) RT_NOEXCEPT;
4846	VBOXSTRICTRC iemRaiseDebugException(PVMCPUCC pVCpu) RT_NOEXCEPT;
4847	VBOXSTRICTRC iemRaiseBoundRangeExceeded(PVMCPUCC pVCpu) RT_NOEXCEPT;
4848	VBOXSTRICTRC iemRaiseUndefinedOpcode(PVMCPUCC pVCpu) RT_NOEXCEPT;
4849	VBOXSTRICTRC iemRaiseDeviceNotAvailable(PVMCPUCC pVCpu) RT_NOEXCEPT;
4850	VBOXSTRICTRC iemRaiseTaskSwitchFaultWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
4851	VBOXSTRICTRC iemRaiseTaskSwitchFaultCurrentTSS(PVMCPUCC pVCpu) RT_NOEXCEPT;
4852	VBOXSTRICTRC iemRaiseTaskSwitchFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
4853	VBOXSTRICTRC iemRaiseTaskSwitchFaultBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
4854	/VBOXSTRICTRC iemRaiseSelectorNotPresent(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;/
4855	VBOXSTRICTRC iemRaiseSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
4856	VBOXSTRICTRC iemRaiseSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
4857	VBOXSTRICTRC iemRaiseStackSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
4858	VBOXSTRICTRC iemRaiseStackSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
4859	VBOXSTRICTRC iemRaiseGeneralProtectionFault(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
4860	VBOXSTRICTRC iemRaiseGeneralProtectionFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
4861	#ifdef IEM_WITH_SETJMP
4862	DECL_NO_RETURN(void) iemRaiseGeneralProtectionFault0Jmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4863	#endif
4864	VBOXSTRICTRC iemRaiseGeneralProtectionFaultBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
4865	VBOXSTRICTRC iemRaiseNotCanonical(PVMCPUCC pVCpu) RT_NOEXCEPT;
4866	VBOXSTRICTRC iemRaiseSelectorBounds(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
4867	#ifdef IEM_WITH_SETJMP
4868	DECL_NO_RETURN(void) iemRaiseSelectorBoundsJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
4869	#endif
4870	VBOXSTRICTRC iemRaiseSelectorBoundsBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
4871	#ifdef IEM_WITH_SETJMP
4872	DECL_NO_RETURN(void) iemRaiseSelectorBoundsBySelectorJmp(PVMCPUCC pVCpu, RTSEL Sel) IEM_NOEXCEPT_MAY_LONGJMP;
4873	#endif
4874	VBOXSTRICTRC iemRaiseSelectorInvalidAccess(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
4875	#ifdef IEM_WITH_SETJMP
4876	DECL_NO_RETURN(void) iemRaiseSelectorInvalidAccessJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
4877	#endif
4878	VBOXSTRICTRC iemRaisePageFault(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) RT_NOEXCEPT;
4879	#ifdef IEM_WITH_SETJMP
4880	DECL_NO_RETURN(void) iemRaisePageFaultJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) IEM_NOEXCEPT_MAY_LONGJMP;
4881	#endif
4882	VBOXSTRICTRC iemRaiseMathFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
4883	VBOXSTRICTRC iemRaiseAlignmentCheckException(PVMCPUCC pVCpu) RT_NOEXCEPT;
4884	#ifdef IEM_WITH_SETJMP
4885	DECL_NO_RETURN(void) iemRaiseAlignmentCheckExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4886	#endif
4887	VBOXSTRICTRC iemRaiseSimdFpException(PVMCPUCC pVCpu) RT_NOEXCEPT;
4888
4889	void iemLogSyscallProtModeInt(PVMCPUCC pVCpu, uint8_t u8Vector, uint8_t cbInstr);
4890
4891	IEM_CIMPL_DEF_0(iemCImplRaiseDivideError);
4892	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidLockPrefix);
4893	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidOpcode);
4894
4895	/**
4896	* Macro for calling iemCImplRaiseDivideError().
4897	*
4898	* This is for things that will _always_ decode to an \#DE, taking the
4899	* recompiler into consideration and everything.
4900	*
4901	* @return Strict VBox status code.
4902	*/
4903	#define IEMOP_RAISE_DIVIDE_ERROR_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, iemCImplRaiseDivideError)
4904
4905	/**
4906	* Macro for calling iemCImplRaiseInvalidLockPrefix().
4907	*
4908	* This is for things that will _always_ decode to an \#UD, taking the
4909	* recompiler into consideration and everything.
4910	*
4911	* @return Strict VBox status code.
4912	*/
4913	#define IEMOP_RAISE_INVALID_LOCK_PREFIX_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, iemCImplRaiseInvalidLockPrefix)
4914
4915	/**
4916	* Macro for calling iemCImplRaiseInvalidOpcode() for decode/static \#UDs.
4917	*
4918	* This is for things that will _always_ decode to an \#UD, taking the
4919	* recompiler into consideration and everything.
4920	*
4921	* @return Strict VBox status code.
4922	*/
4923	#define IEMOP_RAISE_INVALID_OPCODE_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, iemCImplRaiseInvalidOpcode)
4924
4925	/**
4926	* Macro for calling iemCImplRaiseInvalidOpcode() for runtime-style \#UDs.
4927	*
4928	* Using this macro means you've got _buggy_ _code_ and are doing things that
4929	* belongs exclusively in IEMAllCImpl.cpp during decoding.
4930	*
4931	* @return Strict VBox status code.
4932	* @see IEMOP_RAISE_INVALID_OPCODE_RET
4933	*/
4934	#define IEMOP_RAISE_INVALID_OPCODE_RUNTIME_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, iemCImplRaiseInvalidOpcode)
4935
4936	/** @} */
4937
4938	/** @name Register Access.
4939	* @{ */
4940	VBOXSTRICTRC iemRegRipRelativeJumpS8AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int8_t offNextInstr,
4941	IEMMODE enmEffOpSize) RT_NOEXCEPT;
4942	VBOXSTRICTRC iemRegRipRelativeJumpS16AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int16_t offNextInstr) RT_NOEXCEPT;
4943	VBOXSTRICTRC iemRegRipRelativeJumpS32AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int32_t offNextInstr,
4944	IEMMODE enmEffOpSize) RT_NOEXCEPT;
4945	VBOXSTRICTRC iemRegRipJumpU16AndFinishClearningRF(PVMCPUCC pVCpu, uint16_t uNewRip) RT_NOEXCEPT;
4946	VBOXSTRICTRC iemRegRipJumpU32AndFinishClearningRF(PVMCPUCC pVCpu, uint32_t uNewRip) RT_NOEXCEPT;
4947	VBOXSTRICTRC iemRegRipJumpU64AndFinishClearningRF(PVMCPUCC pVCpu, uint64_t uNewRip) RT_NOEXCEPT;
4948	/** @} */
4949
4950	/** @name FPU access and helpers.
4951	* @{ */
4952	void iemFpuPushResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
4953	void iemFpuPushResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4954	void iemFpuPushResultTwo(PVMCPUCC pVCpu, PIEMFPURESULTTWO pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
4955	void iemFpuStoreResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
4956	void iemFpuStoreResultThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
4957	void iemFpuStoreResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
4958	uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4959	void iemFpuStoreResultWithMemOpThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
4960	uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4961	void iemFpuUpdateOpcodeAndIp(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
4962	void iemFpuUpdateFSW(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
4963	void iemFpuUpdateFSWThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
4964	void iemFpuUpdateFSWWithMemOp(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4965	void iemFpuUpdateFSWThenPopPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
4966	void iemFpuUpdateFSWWithMemOpThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4967	void iemFpuStackUnderflow(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
4968	void iemFpuStackUnderflowWithMemOp(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4969	void iemFpuStackUnderflowThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
4970	void iemFpuStackUnderflowWithMemOpThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4971	void iemFpuStackUnderflowThenPopPop(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
4972	void iemFpuStackPushUnderflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
4973	void iemFpuStackPushUnderflowTwo(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
4974	void iemFpuStackPushOverflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
4975	void iemFpuStackPushOverflowWithMemOp(PVMCPUCC pVCpu, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4976	/** @} */
4977
4978	/** @name SSE+AVX SIMD access and helpers.
4979	* @{ */
4980	void iemSseStoreResult(PVMCPUCC pVCpu, PCIEMSSERESULT pResult, uint8_t iXmmReg) RT_NOEXCEPT;
4981	void iemSseUpdateMxcsr(PVMCPUCC pVCpu, uint32_t fMxcsr) RT_NOEXCEPT;
4982	/** @} */
4983
4984	/** @name Memory access.
4985	* @{ */
4986
4987	/** Report a \#GP instead of \#AC and do not restrict to ring-3 */
4988	#define IEM_MEMMAP_F_ALIGN_GP RT_BIT_32(16)
4989	/** SSE access that should report a \#GP instead of \#AC, unless MXCSR.MM=1
4990	* when it works like normal \#AC. Always used with IEM_MEMMAP_F_ALIGN_GP. */
4991	#define IEM_MEMMAP_F_ALIGN_SSE RT_BIT_32(17)
4992	/** If \#AC is applicable, raise it. Always used with IEM_MEMMAP_F_ALIGN_GP.
4993	* Users include FXSAVE & FXRSTOR. */
4994	#define IEM_MEMMAP_F_ALIGN_GP_OR_AC RT_BIT_32(18)
4995
4996	VBOXSTRICTRC iemMemMap(PVMCPUCC pVCpu, void **ppvMem, size_t cbMem, uint8_t iSegReg, RTGCPTR GCPtrMem,
4997	uint32_t fAccess, uint32_t uAlignCtl) RT_NOEXCEPT;
4998	VBOXSTRICTRC iemMemCommitAndUnmap(PVMCPUCC pVCpu, void *pvMem, uint32_t fAccess) RT_NOEXCEPT;
4999	#ifndef IN_RING3
5000	VBOXSTRICTRC iemMemCommitAndUnmapPostponeTroubleToR3(PVMCPUCC pVCpu, void *pvMem, uint32_t fAccess) RT_NOEXCEPT;
5001	#endif
5002	void iemMemRollback(PVMCPUCC pVCpu) RT_NOEXCEPT;
5003	VBOXSTRICTRC iemMemApplySegment(PVMCPUCC pVCpu, uint32_t fAccess, uint8_t iSegReg, size_t cbMem, PRTGCPTR pGCPtrMem) RT_NOEXCEPT;
5004	VBOXSTRICTRC iemMemMarkSelDescAccessed(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5005	VBOXSTRICTRC iemMemPageTranslateAndCheckAccess(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t cbAccess, uint32_t fAccess, PRTGCPHYS pGCPhysMem) RT_NOEXCEPT;
5006
5007	void iemOpcodeFlushLight(PVMCPUCC pVCpu, uint8_t cbInstr);
5008	void iemOpcodeFlushHeavy(PVMCPUCC pVCpu, uint8_t cbInstr);
5009	#ifdef IEM_WITH_CODE_TLB
5010	void iemOpcodeFetchBytesJmp(PVMCPUCC pVCpu, size_t cbDst, void *pvDst) IEM_NOEXCEPT_MAY_LONGJMP;
5011	#else
5012	VBOXSTRICTRC iemOpcodeFetchMoreBytes(PVMCPUCC pVCpu, size_t cbMin) RT_NOEXCEPT;
5013	#endif
5014	#ifdef IEM_WITH_SETJMP
5015	uint8_t iemOpcodeGetNextU8SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5016	uint16_t iemOpcodeGetNextU16SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5017	uint32_t iemOpcodeGetNextU32SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5018	uint64_t iemOpcodeGetNextU64SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5019	#else
5020	VBOXSTRICTRC iemOpcodeGetNextU8Slow(PVMCPUCC pVCpu, uint8_t *pb) RT_NOEXCEPT;
5021	VBOXSTRICTRC iemOpcodeGetNextS8SxU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
5022	VBOXSTRICTRC iemOpcodeGetNextS8SxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
5023	VBOXSTRICTRC iemOpcodeGetNextS8SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5024	VBOXSTRICTRC iemOpcodeGetNextU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
5025	VBOXSTRICTRC iemOpcodeGetNextU16ZxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
5026	VBOXSTRICTRC iemOpcodeGetNextU16ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5027	VBOXSTRICTRC iemOpcodeGetNextU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
5028	VBOXSTRICTRC iemOpcodeGetNextU32ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5029	VBOXSTRICTRC iemOpcodeGetNextS32SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5030	VBOXSTRICTRC iemOpcodeGetNextU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5031	#endif
5032
5033	VBOXSTRICTRC iemMemFetchDataU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5034	VBOXSTRICTRC iemMemFetchDataU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5035	VBOXSTRICTRC iemMemFetchDataU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5036	VBOXSTRICTRC iemMemFetchDataU32_ZX_U64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5037	VBOXSTRICTRC iemMemFetchDataU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5038	VBOXSTRICTRC iemMemFetchDataU64AlignedU128(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5039	VBOXSTRICTRC iemMemFetchDataR80(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5040	VBOXSTRICTRC iemMemFetchDataD80(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5041	VBOXSTRICTRC iemMemFetchDataU128(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5042	VBOXSTRICTRC iemMemFetchDataU128AlignedSse(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5043	VBOXSTRICTRC iemMemFetchDataU256(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5044	VBOXSTRICTRC iemMemFetchDataU256AlignedSse(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5045	VBOXSTRICTRC iemMemFetchDataXdtr(PVMCPUCC pVCpu, uint16_t *pcbLimit, PRTGCPTR pGCPtrBase, uint8_t iSegReg,
5046	RTGCPTR GCPtrMem, IEMMODE enmOpSize) RT_NOEXCEPT;
5047	#ifdef IEM_WITH_SETJMP
5048	uint8_t iemMemFetchDataU8SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5049	uint16_t iemMemFetchDataU16SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5050	uint32_t iemMemFetchDataU32SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5051	uint32_t iemMemFlatFetchDataU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5052	uint64_t iemMemFetchDataU64SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5053	uint64_t iemMemFetchDataU64AlignedU128SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5054	void iemMemFetchDataR80SafeJmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5055	void iemMemFetchDataD80SafeJmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5056	void iemMemFetchDataU128SafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5057	void iemMemFetchDataU128AlignedSseSafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5058	void iemMemFetchDataU256SafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5059	void iemMemFetchDataU256AlignedSseSafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5060	# if 0 /* these are inlined now */
5061	uint8_t iemMemFetchDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5062	uint16_t iemMemFetchDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5063	uint32_t iemMemFetchDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5064	uint32_t iemMemFlatFetchDataU32Jmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5065	uint64_t iemMemFetchDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5066	uint64_t iemMemFetchDataU64AlignedU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5067	# endif
5068	void iemMemFetchDataR80Jmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5069	void iemMemFetchDataD80Jmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5070	void iemMemFetchDataU128Jmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5071	void iemMemFetchDataU128AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5072	void iemMemFetchDataU256Jmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5073	void iemMemFetchDataU256AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5074	#endif
5075
5076	VBOXSTRICTRC iemMemFetchSysU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5077	VBOXSTRICTRC iemMemFetchSysU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5078	VBOXSTRICTRC iemMemFetchSysU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5079	VBOXSTRICTRC iemMemFetchSysU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5080	VBOXSTRICTRC iemMemFetchSelDesc(PVMCPUCC pVCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt) RT_NOEXCEPT;
5081
5082	VBOXSTRICTRC iemMemStoreDataU8(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) RT_NOEXCEPT;
5083	VBOXSTRICTRC iemMemStoreDataU16(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) RT_NOEXCEPT;
5084	VBOXSTRICTRC iemMemStoreDataU32(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) RT_NOEXCEPT;
5085	VBOXSTRICTRC iemMemStoreDataU64(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) RT_NOEXCEPT;
5086	VBOXSTRICTRC iemMemStoreDataU128(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
5087	VBOXSTRICTRC iemMemStoreDataU128AlignedSse(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
5088	VBOXSTRICTRC iemMemStoreDataU256(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
5089	VBOXSTRICTRC iemMemStoreDataU256AlignedAvx(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
5090	VBOXSTRICTRC iemMemStoreDataXdtr(PVMCPUCC pVCpu, uint16_t cbLimit, RTGCPTR GCPtrBase, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5091	#ifdef IEM_WITH_SETJMP
5092	void iemMemStoreDataU8SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
5093	void iemMemStoreDataU16SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
5094	void iemMemStoreDataU32SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
5095	void iemMemStoreDataU64SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
5096	void iemMemStoreDataU128SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5097	void iemMemStoreDataU128AlignedSseSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5098	void iemMemStoreDataU256SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5099	void iemMemStoreDataU256AlignedAvxSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5100	#if 0
5101	void iemMemStoreDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
5102	void iemMemStoreDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
5103	void iemMemStoreDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
5104	void iemMemStoreDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
5105	#endif
5106	void iemMemStoreDataU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5107	void iemMemStoreDataU128AlignedSseJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5108	void iemMemStoreDataU256Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5109	void iemMemStoreDataU256AlignedAvxJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5110	#endif
5111
5112	#ifdef IEM_WITH_SETJMP
5113	uint8_t iemMemMapDataU8RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5114	uint8_t iemMemMapDataU8WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5115	uint8_t const iemMemMapDataU8RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5116	uint16_t iemMemMapDataU16RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5117	uint16_t iemMemMapDataU16WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5118	uint16_t const iemMemMapDataU16RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5119	uint32_t iemMemMapDataU32RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5120	uint32_t iemMemMapDataU32WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5121	uint32_t const iemMemMapDataU32RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5122	uint64_t iemMemMapDataU64RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5123	uint64_t iemMemMapDataU64WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5124	uint64_t const iemMemMapDataU64RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5125
5126	void iemMemCommitAndUnmapRwSafeJmp(PVMCPUCC pVCpu, void *pvMem, uint8_t bMapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5127	void iemMemCommitAndUnmapWoSafeJmp(PVMCPUCC pVCpu, void *pvMem, uint8_t bMapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5128	void iemMemCommitAndUnmapRoSafeJmp(PVMCPUCC pVCpu, const void *pvMem, uint8_t bMapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5129	#endif
5130
5131	VBOXSTRICTRC iemMemStackPushBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
5132	void *ppvMem, uint64_t puNewRsp) RT_NOEXCEPT;
5133	VBOXSTRICTRC iemMemStackPushCommitSpecial(PVMCPUCC pVCpu, void *pvMem, uint64_t uNewRsp) RT_NOEXCEPT;
5134	VBOXSTRICTRC iemMemStackPushU16(PVMCPUCC pVCpu, uint16_t u16Value) RT_NOEXCEPT;
5135	VBOXSTRICTRC iemMemStackPushU32(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
5136	VBOXSTRICTRC iemMemStackPushU64(PVMCPUCC pVCpu, uint64_t u64Value) RT_NOEXCEPT;
5137	VBOXSTRICTRC iemMemStackPushU16Ex(PVMCPUCC pVCpu, uint16_t u16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5138	VBOXSTRICTRC iemMemStackPushU32Ex(PVMCPUCC pVCpu, uint32_t u32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5139	VBOXSTRICTRC iemMemStackPushU64Ex(PVMCPUCC pVCpu, uint64_t u64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5140	VBOXSTRICTRC iemMemStackPushU32SReg(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
5141	VBOXSTRICTRC iemMemStackPopBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
5142	void const *ppvMem, uint64_t puNewRsp) RT_NOEXCEPT;
5143	VBOXSTRICTRC iemMemStackPopContinueSpecial(PVMCPUCC pVCpu, size_t off, size_t cbMem,
5144	void const **ppvMem, uint64_t uCurNewRsp) RT_NOEXCEPT;
5145	VBOXSTRICTRC iemMemStackPopDoneSpecial(PVMCPUCC pVCpu, void const *pvMem) RT_NOEXCEPT;
5146	VBOXSTRICTRC iemMemStackPopU16(PVMCPUCC pVCpu, uint16_t *pu16Value) RT_NOEXCEPT;
5147	VBOXSTRICTRC iemMemStackPopU32(PVMCPUCC pVCpu, uint32_t *pu32Value) RT_NOEXCEPT;
5148	VBOXSTRICTRC iemMemStackPopU64(PVMCPUCC pVCpu, uint64_t *pu64Value) RT_NOEXCEPT;
5149	VBOXSTRICTRC iemMemStackPopU16Ex(PVMCPUCC pVCpu, uint16_t *pu16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5150	VBOXSTRICTRC iemMemStackPopU32Ex(PVMCPUCC pVCpu, uint32_t *pu32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5151	VBOXSTRICTRC iemMemStackPopU64Ex(PVMCPUCC pVCpu, uint64_t *pu64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5152
5153	#ifdef IEM_WITH_SETJMP
5154	void iemMemStackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5155	void iemMemStackPushU32SafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5156	void iemMemStackPushU32SRegSafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5157	void iemMemStackPushU64SafeJmp(PVMCPUCC pVCpu, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5158	uint16_t iemMemStackPopU16SafeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5159	uint32_t iemMemStackPopU32SafeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5160	uint64_t iemMemStackPopU64SafeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5161
5162	void iemMemFlat32StackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5163	void iemMemFlat32StackPushU32SafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5164	void iemMemFlat32StackPushU32SRegSafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5165	uint16_t iemMemFlat32StackPopU16SafeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5166	uint32_t iemMemFlat32StackPopU32SafeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5167
5168	void iemMemFlat64StackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5169	void iemMemFlat64StackPushU64SafeJmp(PVMCPUCC pVCpu, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5170	uint16_t iemMemFlat64StackPopU16SafeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5171	uint64_t iemMemFlat64StackPopU64SafeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5172	#endif
5173
5174	/** @} */
5175
5176	/** @name IEMAllCImpl.cpp
5177	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/'
5178	* @{ */
5179	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem16, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5180	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem32, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5181	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem64, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5182	IEM_CIMPL_PROTO_0(iemCImpl_popa_16);
5183	IEM_CIMPL_PROTO_0(iemCImpl_popa_32);
5184	IEM_CIMPL_PROTO_0(iemCImpl_pusha_16);
5185	IEM_CIMPL_PROTO_0(iemCImpl_pusha_32);
5186	IEM_CIMPL_PROTO_1(iemCImpl_pushf, IEMMODE, enmEffOpSize);
5187	IEM_CIMPL_PROTO_1(iemCImpl_popf, IEMMODE, enmEffOpSize);
5188	IEM_CIMPL_PROTO_1(iemCImpl_call_16, uint16_t, uNewPC);
5189	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_16, int16_t, offDisp);
5190	IEM_CIMPL_PROTO_1(iemCImpl_call_32, uint32_t, uNewPC);
5191	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_32, int32_t, offDisp);
5192	IEM_CIMPL_PROTO_1(iemCImpl_call_64, uint64_t, uNewPC);
5193	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_64, int64_t, offDisp);
5194	IEM_CIMPL_PROTO_3(iemCImpl_FarJmp, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
5195	IEM_CIMPL_PROTO_3(iemCImpl_callf, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
5196	typedef IEM_CIMPL_DECL_TYPE_3(FNIEMCIMPLFARBRANCH, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
5197	typedef FNIEMCIMPLFARBRANCH *PFNIEMCIMPLFARBRANCH;
5198	IEM_CIMPL_PROTO_2(iemCImpl_retf, IEMMODE, enmEffOpSize, uint16_t, cbPop);
5199	IEM_CIMPL_PROTO_0(iemCImpl_retn_16);
5200	IEM_CIMPL_PROTO_0(iemCImpl_retn_32);
5201	IEM_CIMPL_PROTO_0(iemCImpl_retn_64);
5202	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_16, uint16_t, cbPop);
5203	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_32, uint16_t, cbPop);
5204	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_64, uint16_t, cbPop);
5205	IEM_CIMPL_PROTO_3(iemCImpl_enter, IEMMODE, enmEffOpSize, uint16_t, cbFrame, uint8_t, cParameters);
5206	IEM_CIMPL_PROTO_1(iemCImpl_leave, IEMMODE, enmEffOpSize);
5207	IEM_CIMPL_PROTO_2(iemCImpl_int, uint8_t, u8Int, IEMINT, enmInt);
5208	IEM_CIMPL_PROTO_1(iemCImpl_iret_real_v8086, IEMMODE, enmEffOpSize);
5209	IEM_CIMPL_PROTO_4(iemCImpl_iret_prot_v8086, uint32_t, uNewEip, uint16_t, uNewCs, uint32_t, uNewFlags, uint64_t, uNewRsp);
5210	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot_NestedTask, IEMMODE, enmEffOpSize);
5211	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot, IEMMODE, enmEffOpSize);
5212	IEM_CIMPL_PROTO_1(iemCImpl_iret_64bit, IEMMODE, enmEffOpSize);
5213	IEM_CIMPL_PROTO_1(iemCImpl_iret, IEMMODE, enmEffOpSize);
5214	IEM_CIMPL_PROTO_0(iemCImpl_loadall286);
5215	IEM_CIMPL_PROTO_0(iemCImpl_syscall);
5216	IEM_CIMPL_PROTO_1(iemCImpl_sysret, IEMMODE, enmEffOpSize);
5217	IEM_CIMPL_PROTO_0(iemCImpl_sysenter);
5218	IEM_CIMPL_PROTO_1(iemCImpl_sysexit, IEMMODE, enmEffOpSize);
5219	IEM_CIMPL_PROTO_2(iemCImpl_LoadSReg, uint8_t, iSegReg, uint16_t, uSel);
5220	IEM_CIMPL_PROTO_2(iemCImpl_load_SReg, uint8_t, iSegReg, uint16_t, uSel);
5221	IEM_CIMPL_PROTO_2(iemCImpl_pop_Sreg, uint8_t, iSegReg, IEMMODE, enmEffOpSize);
5222	IEM_CIMPL_PROTO_5(iemCImpl_load_SReg_Greg, uint16_t, uSel, uint64_t, offSeg, uint8_t, iSegReg, uint8_t, iGReg, IEMMODE, enmEffOpSize);
5223	IEM_CIMPL_PROTO_2(iemCImpl_VerX, uint16_t, uSel, bool, fWrite);
5224	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u64, uint64_t *, pu64Dst, uint16_t, uSel, bool, fIsLar);
5225	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u16, uint16_t *, pu16Dst, uint16_t, uSel, bool, fIsLar);
5226	IEM_CIMPL_PROTO_3(iemCImpl_lgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
5227	IEM_CIMPL_PROTO_2(iemCImpl_sgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5228	IEM_CIMPL_PROTO_3(iemCImpl_lidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
5229	IEM_CIMPL_PROTO_2(iemCImpl_sidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5230	IEM_CIMPL_PROTO_1(iemCImpl_lldt, uint16_t, uNewLdt);
5231	IEM_CIMPL_PROTO_2(iemCImpl_sldt_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
5232	IEM_CIMPL_PROTO_2(iemCImpl_sldt_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5233	IEM_CIMPL_PROTO_1(iemCImpl_ltr, uint16_t, uNewTr);
5234	IEM_CIMPL_PROTO_2(iemCImpl_str_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
5235	IEM_CIMPL_PROTO_2(iemCImpl_str_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5236	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Cd, uint8_t, iGReg, uint8_t, iCrReg);
5237	IEM_CIMPL_PROTO_2(iemCImpl_smsw_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
5238	IEM_CIMPL_PROTO_2(iemCImpl_smsw_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5239	IEM_CIMPL_PROTO_4(iemCImpl_load_CrX, uint8_t, iCrReg, uint64_t, uNewCrX, IEMACCESSCRX, enmAccessCrX, uint8_t, iGReg);
5240	IEM_CIMPL_PROTO_2(iemCImpl_mov_Cd_Rd, uint8_t, iCrReg, uint8_t, iGReg);
5241	IEM_CIMPL_PROTO_2(iemCImpl_lmsw, uint16_t, u16NewMsw, RTGCPTR, GCPtrEffDst);
5242	IEM_CIMPL_PROTO_0(iemCImpl_clts);
5243	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Dd, uint8_t, iGReg, uint8_t, iDrReg);
5244	IEM_CIMPL_PROTO_2(iemCImpl_mov_Dd_Rd, uint8_t, iDrReg, uint8_t, iGReg);
5245	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Td, uint8_t, iGReg, uint8_t, iTrReg);
5246	IEM_CIMPL_PROTO_2(iemCImpl_mov_Td_Rd, uint8_t, iTrReg, uint8_t, iGReg);
5247	IEM_CIMPL_PROTO_1(iemCImpl_invlpg, RTGCPTR, GCPtrPage);
5248	IEM_CIMPL_PROTO_3(iemCImpl_invpcid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvpcidDesc, uint64_t, uInvpcidType);
5249	IEM_CIMPL_PROTO_0(iemCImpl_invd);
5250	IEM_CIMPL_PROTO_0(iemCImpl_wbinvd);
5251	IEM_CIMPL_PROTO_0(iemCImpl_rsm);
5252	IEM_CIMPL_PROTO_0(iemCImpl_rdtsc);
5253	IEM_CIMPL_PROTO_0(iemCImpl_rdtscp);
5254	IEM_CIMPL_PROTO_0(iemCImpl_rdpmc);
5255	IEM_CIMPL_PROTO_0(iemCImpl_rdmsr);
5256	IEM_CIMPL_PROTO_0(iemCImpl_wrmsr);
5257	IEM_CIMPL_PROTO_3(iemCImpl_in, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
5258	IEM_CIMPL_PROTO_2(iemCImpl_in_eAX_DX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
5259	IEM_CIMPL_PROTO_3(iemCImpl_out, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
5260	IEM_CIMPL_PROTO_2(iemCImpl_out_DX_eAX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
5261	IEM_CIMPL_PROTO_0(iemCImpl_cli);
5262	IEM_CIMPL_PROTO_0(iemCImpl_sti);
5263	IEM_CIMPL_PROTO_0(iemCImpl_hlt);
5264	IEM_CIMPL_PROTO_1(iemCImpl_monitor, uint8_t, iEffSeg);
5265	IEM_CIMPL_PROTO_0(iemCImpl_mwait);
5266	IEM_CIMPL_PROTO_0(iemCImpl_swapgs);
5267	IEM_CIMPL_PROTO_0(iemCImpl_cpuid);
5268	IEM_CIMPL_PROTO_1(iemCImpl_aad, uint8_t, bImm);
5269	IEM_CIMPL_PROTO_1(iemCImpl_aam, uint8_t, bImm);
5270	IEM_CIMPL_PROTO_0(iemCImpl_daa);
5271	IEM_CIMPL_PROTO_0(iemCImpl_das);
5272	IEM_CIMPL_PROTO_0(iemCImpl_aaa);
5273	IEM_CIMPL_PROTO_0(iemCImpl_aas);
5274	IEM_CIMPL_PROTO_3(iemCImpl_bound_16, int16_t, idxArray, int16_t, idxLowerBound, int16_t, idxUpperBound);
5275	IEM_CIMPL_PROTO_3(iemCImpl_bound_32, int32_t, idxArray, int32_t, idxLowerBound, int32_t, idxUpperBound);
5276	IEM_CIMPL_PROTO_0(iemCImpl_xgetbv);
5277	IEM_CIMPL_PROTO_0(iemCImpl_xsetbv);
5278	IEM_CIMPL_PROTO_4(iemCImpl_cmpxchg16b_fallback_rendezvous, PRTUINT128U, pu128Dst, PRTUINT128U, pu128RaxRdx,
5279	PRTUINT128U, pu128RbxRcx, uint32_t *, pEFlags);
5280	IEM_CIMPL_PROTO_2(iemCImpl_clflush_clflushopt, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5281	IEM_CIMPL_PROTO_1(iemCImpl_finit, bool, fCheckXcpts);
5282	IEM_CIMPL_PROTO_3(iemCImpl_fxsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5283	IEM_CIMPL_PROTO_3(iemCImpl_fxrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5284	IEM_CIMPL_PROTO_3(iemCImpl_xsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5285	IEM_CIMPL_PROTO_3(iemCImpl_xrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5286	IEM_CIMPL_PROTO_2(iemCImpl_stmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5287	IEM_CIMPL_PROTO_2(iemCImpl_vstmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5288	IEM_CIMPL_PROTO_2(iemCImpl_ldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5289	IEM_CIMPL_PROTO_3(iemCImpl_fnstenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5290	IEM_CIMPL_PROTO_3(iemCImpl_fnsave, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5291	IEM_CIMPL_PROTO_3(iemCImpl_fldenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
5292	IEM_CIMPL_PROTO_3(iemCImpl_frstor, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
5293	IEM_CIMPL_PROTO_1(iemCImpl_fldcw, uint16_t, u16Fcw);
5294	IEM_CIMPL_PROTO_2(iemCImpl_fxch_underflow, uint8_t, iStReg, uint16_t, uFpuOpcode);
5295	IEM_CIMPL_PROTO_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, bool, fUCmp, uint32_t, uPopAndFpuOpcode);
5296	IEM_CIMPL_PROTO_2(iemCImpl_rdseed, uint8_t, iReg, IEMMODE, enmEffOpSize);
5297	IEM_CIMPL_PROTO_2(iemCImpl_rdrand, uint8_t, iReg, IEMMODE, enmEffOpSize);
5298	/** @} */
5299
5300	/** @name IEMAllCImplStrInstr.cpp.h
5301	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/' -e 's/RT_CONCAT4(//' \
5302	* -e 's/,ADDR_SIZE)/64/g' -e 's/,OP_SIZE,/64/g' -e 's/,OP_rAX,/rax/g' IEMAllCImplStrInstr.cpp.h
5303	* @{ */
5304	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr16, uint8_t, iEffSeg);
5305	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr16, uint8_t, iEffSeg);
5306	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m16);
5307	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m16);
5308	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr16, uint8_t, iEffSeg);
5309	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m16);
5310	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m16, int8_t, iEffSeg);
5311	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr16, bool, fIoChecked);
5312	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr16, bool, fIoChecked);
5313	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5314	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5315
5316	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr16, uint8_t, iEffSeg);
5317	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr16, uint8_t, iEffSeg);
5318	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m16);
5319	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m16);
5320	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr16, uint8_t, iEffSeg);
5321	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m16);
5322	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m16, int8_t, iEffSeg);
5323	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr16, bool, fIoChecked);
5324	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr16, bool, fIoChecked);
5325	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5326	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5327
5328	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr16, uint8_t, iEffSeg);
5329	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr16, uint8_t, iEffSeg);
5330	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m16);
5331	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m16);
5332	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr16, uint8_t, iEffSeg);
5333	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m16);
5334	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m16, int8_t, iEffSeg);
5335	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr16, bool, fIoChecked);
5336	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr16, bool, fIoChecked);
5337	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5338	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5339
5340
5341	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr32, uint8_t, iEffSeg);
5342	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr32, uint8_t, iEffSeg);
5343	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m32);
5344	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m32);
5345	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr32, uint8_t, iEffSeg);
5346	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m32);
5347	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m32, int8_t, iEffSeg);
5348	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr32, bool, fIoChecked);
5349	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr32, bool, fIoChecked);
5350	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5351	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5352
5353	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr32, uint8_t, iEffSeg);
5354	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr32, uint8_t, iEffSeg);
5355	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m32);
5356	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m32);
5357	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr32, uint8_t, iEffSeg);
5358	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m32);
5359	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m32, int8_t, iEffSeg);
5360	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr32, bool, fIoChecked);
5361	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr32, bool, fIoChecked);
5362	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5363	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5364
5365	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr32, uint8_t, iEffSeg);
5366	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr32, uint8_t, iEffSeg);
5367	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m32);
5368	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m32);
5369	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr32, uint8_t, iEffSeg);
5370	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m32);
5371	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m32, int8_t, iEffSeg);
5372	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr32, bool, fIoChecked);
5373	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr32, bool, fIoChecked);
5374	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5375	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5376
5377	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr32, uint8_t, iEffSeg);
5378	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr32, uint8_t, iEffSeg);
5379	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m32);
5380	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m32);
5381	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr32, uint8_t, iEffSeg);
5382	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m32);
5383	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m32, int8_t, iEffSeg);
5384	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr32, bool, fIoChecked);
5385	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr32, bool, fIoChecked);
5386	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5387	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5388
5389
5390	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr64, uint8_t, iEffSeg);
5391	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr64, uint8_t, iEffSeg);
5392	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m64);
5393	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m64);
5394	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr64, uint8_t, iEffSeg);
5395	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m64);
5396	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m64, int8_t, iEffSeg);
5397	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr64, bool, fIoChecked);
5398	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr64, bool, fIoChecked);
5399	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5400	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5401
5402	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr64, uint8_t, iEffSeg);
5403	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr64, uint8_t, iEffSeg);
5404	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m64);
5405	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m64);
5406	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr64, uint8_t, iEffSeg);
5407	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m64);
5408	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m64, int8_t, iEffSeg);
5409	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr64, bool, fIoChecked);
5410	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr64, bool, fIoChecked);
5411	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5412	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5413
5414	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr64, uint8_t, iEffSeg);
5415	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr64, uint8_t, iEffSeg);
5416	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m64);
5417	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m64);
5418	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr64, uint8_t, iEffSeg);
5419	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m64);
5420	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m64, int8_t, iEffSeg);
5421	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr64, bool, fIoChecked);
5422	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr64, bool, fIoChecked);
5423	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5424	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5425
5426	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr64, uint8_t, iEffSeg);
5427	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr64, uint8_t, iEffSeg);
5428	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m64);
5429	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m64);
5430	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr64, uint8_t, iEffSeg);
5431	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m64);
5432	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m64, int8_t, iEffSeg);
5433	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr64, bool, fIoChecked);
5434	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr64, bool, fIoChecked);
5435	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5436	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5437	/** @} */
5438
5439	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5440	VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT;
5441	VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT;
5442	VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT;
5443	VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT;
5444	VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT;
5445	VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
5446	VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALK pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT;
5447	VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT;
5448	VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT;
5449	VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
5450	bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT;
5451	VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
5452	bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT;
5453	VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5454	VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5455	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5456	VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5457	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5458	VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5459	VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT;
5460	VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
5461	RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT;
5462	VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT;
5463	VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT;
5464	VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT;
5465	uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT;
5466	void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT;
5467	VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
5468	uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT;
5469	bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT;
5470	IEM_CIMPL_PROTO_0(iemCImpl_vmxoff);
5471	IEM_CIMPL_PROTO_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon);
5472	IEM_CIMPL_PROTO_0(iemCImpl_vmlaunch);
5473	IEM_CIMPL_PROTO_0(iemCImpl_vmresume);
5474	IEM_CIMPL_PROTO_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
5475	IEM_CIMPL_PROTO_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
5476	IEM_CIMPL_PROTO_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
5477	IEM_CIMPL_PROTO_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField);
5478	IEM_CIMPL_PROTO_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField);
5479	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField);
5480	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg32, uint64_t *, pu32Dst, uint32_t, u32VmcsField);
5481	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField);
5482	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField);
5483	IEM_CIMPL_PROTO_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType);
5484	IEM_CIMPL_PROTO_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType);
5485	IEM_CIMPL_PROTO_0(iemCImpl_vmx_pause);
5486	#endif
5487
5488	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5489	VBOXSTRICTRC iemSvmVmexit(PVMCPUCC pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2) RT_NOEXCEPT;
5490	VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr, uint64_t uCr2) RT_NOEXCEPT;
5491	VBOXSTRICTRC iemSvmHandleIOIntercept(PVMCPUCC pVCpu, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
5492	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, uint8_t cbInstr) RT_NOEXCEPT;
5493	VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPUCC pVCpu, uint32_t idMsr, bool fWrite, uint8_t cbInstr) RT_NOEXCEPT;
5494	IEM_CIMPL_PROTO_0(iemCImpl_vmrun);
5495	IEM_CIMPL_PROTO_0(iemCImpl_vmload);
5496	IEM_CIMPL_PROTO_0(iemCImpl_vmsave);
5497	IEM_CIMPL_PROTO_0(iemCImpl_clgi);
5498	IEM_CIMPL_PROTO_0(iemCImpl_stgi);
5499	IEM_CIMPL_PROTO_0(iemCImpl_invlpga);
5500	IEM_CIMPL_PROTO_0(iemCImpl_skinit);
5501	IEM_CIMPL_PROTO_0(iemCImpl_svm_pause);
5502	#endif
5503
5504	IEM_CIMPL_PROTO_0(iemCImpl_vmcall); /* vmx */
5505	IEM_CIMPL_PROTO_0(iemCImpl_vmmcall); /* svm */
5506	IEM_CIMPL_PROTO_1(iemCImpl_Hypercall, uint16_t, uDisOpcode); /* both */
5507
5508	extern const PFNIEMOP g_apfnIemInterpretOnlyOneByteMap[256];
5509	extern const PFNIEMOP g_apfnIemInterpretOnlyTwoByteMap[1024];
5510	extern const PFNIEMOP g_apfnIemInterpretOnlyThreeByte0f3a[1024];
5511	extern const PFNIEMOP g_apfnIemInterpretOnlyThreeByte0f38[1024];
5512	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap1[1024];
5513	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap2[1024];
5514	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap3[1024];
5515
5516	/*
5517	* Recompiler related stuff.
5518	*/
5519	extern const PFNIEMOP g_apfnIemThreadedRecompilerOneByteMap[256];
5520	extern const PFNIEMOP g_apfnIemThreadedRecompilerTwoByteMap[1024];
5521	extern const PFNIEMOP g_apfnIemThreadedRecompilerThreeByte0f3a[1024];
5522	extern const PFNIEMOP g_apfnIemThreadedRecompilerThreeByte0f38[1024];
5523	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap1[1024];
5524	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap2[1024];
5525	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap3[1024];
5526
5527	DECLCALLBACK(int) iemTbInit(PVMCC pVM, uint32_t cInitialTbs, uint32_t cMaxTbs,
5528	uint64_t cbInitialExec, uint64_t cbMaxExec, uint32_t cbChunkExec);
5529	void iemThreadedTbObsolete(PVMCPUCC pVCpu, PIEMTB pTb, bool fSafeToFree);
5530	void iemTbAllocatorProcessDelayedFrees(PVMCPU pVCpu, PIEMTBALLOCATOR pTbAllocator);
5531
5532
5533	/** @todo FNIEMTHREADEDFUNC and friends may need more work... */
5534	#if defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
5535	typedef VBOXSTRICTRC /__attribute__((__nothrow__))/ FNIEMTHREADEDFUNC(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
5536	typedef FNIEMTHREADEDFUNC *PFNIEMTHREADEDFUNC;
5537	# define IEM_DECL_IEMTHREADEDFUNC_DEF(a_Name) \
5538	VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2)
5539	# define IEM_DECL_IEMTHREADEDFUNC_PROTO(a_Name) \
5540	VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2)
5541
5542	#else
5543	typedef VBOXSTRICTRC (FNIEMTHREADEDFUNC)(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
5544	typedef FNIEMTHREADEDFUNC *PFNIEMTHREADEDFUNC;
5545	# define IEM_DECL_IEMTHREADEDFUNC_DEF(a_Name) \
5546	VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2) IEM_NOEXCEPT_MAY_LONGJMP
5547	# define IEM_DECL_IEMTHREADEDFUNC_PROTO(a_Name) \
5548	VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2) IEM_NOEXCEPT_MAY_LONGJMP
5549	#endif
5550
5551
5552	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_DeferToCImpl0);
5553
5554	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckIrq);
5555	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckMode);
5556	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckHwInstrBps);
5557	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLim);
5558
5559	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodes);
5560	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodes);
5561	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesConsiderCsLim);
5562
5563	/* Branching: */
5564	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndPcAndOpcodes);
5565	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckPcAndOpcodes);
5566	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckPcAndOpcodesConsiderCsLim);
5567
5568	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesLoadingTlb);
5569	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesLoadingTlb);
5570	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesLoadingTlbConsiderCsLim);
5571
5572	/* Natural page crossing: */
5573	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesAcrossPageLoadingTlb);
5574	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesAcrossPageLoadingTlb);
5575	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesAcrossPageLoadingTlbConsiderCsLim);
5576
5577	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesOnNextPageLoadingTlb);
5578	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNextPageLoadingTlb);
5579	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNextPageLoadingTlbConsiderCsLim);
5580
5581	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesOnNewPageLoadingTlb);
5582	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNewPageLoadingTlb);
5583	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNewPageLoadingTlbConsiderCsLim);
5584
5585	bool iemThreadedCompileEmitIrqCheckBefore(PVMCPUCC pVCpu, PIEMTB pTb);
5586	bool iemThreadedCompileBeginEmitCallsComplications(PVMCPUCC pVCpu, PIEMTB pTb);
5587
5588	/* Native recompiler public bits: */
5589	PIEMTB iemNativeRecompile(PVMCPUCC pVCpu, PIEMTB pTb);
5590	int iemExecMemAllocatorInit(PVMCPU pVCpu, uint64_t cbMax, uint64_t cbInitial, uint32_t cbChunk);
5591	void iemExecMemAllocatorFree(PVMCPU pVCpu, void *pv, size_t cb);
5592
5593
5594	/** @} */
5595
5596	RT_C_DECLS_END
5597
5598	#endif /* !VMM_INCLUDED_SRC_include_IEMInternal_h */
5599

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source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h@ 101547

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