IEMInternal.h@ 102077

Last change on this file since 102077 was 102077, checked in by vboxsync, 15 months ago
VMM/IEM,STAM: Native translation of IEM_MC_REF_EFLAGS, IEM_MC_REF_GREG_U16, IEM_MC_CALL_VOID_AIMPL_X and IEM_MC_CALL_AIMPL_X. Added STAMUNIT_BYTES_PER_TB. bugref:10371
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 285.1 KB

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1	/* $Id: IEMInternal.h 102077 2023-11-13 11:52:34Z vboxsync $ */
2	/** @file
3	* IEM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2011-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_IEMInternal_h
29	#define VMM_INCLUDED_SRC_include_IEMInternal_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#include <VBox/vmm/cpum.h>
35	#include <VBox/vmm/iem.h>
36	#include <VBox/vmm/pgm.h>
37	#include <VBox/vmm/stam.h>
38	#include <VBox/param.h>
39
40	#include <iprt/setjmp-without-sigmask.h>
41	#include <iprt/list.h>
42
43
44	RT_C_DECLS_BEGIN
45
46
47	/** @defgroup grp_iem_int Internals
48	* @ingroup grp_iem
49	* @internal
50	* @{
51	*/
52
53	/** For expanding symbol in slickedit and other products tagging and
54	* crossreferencing IEM symbols. */
55	#ifndef IEM_STATIC
56	# define IEM_STATIC static
57	#endif
58
59	/** @def IEM_WITH_SETJMP
60	* Enables alternative status code handling using setjmps.
61	*
62	* This adds a bit of expense via the setjmp() call since it saves all the
63	* non-volatile registers. However, it eliminates return code checks and allows
64	* for more optimal return value passing (return regs instead of stack buffer).
65	*/
66	#if defined(DOXYGEN_RUNNING) \|\| defined(RT_OS_WINDOWS) \|\| 1
67	# define IEM_WITH_SETJMP
68	#endif
69
70	/** @def IEM_WITH_THROW_CATCH
71	* Enables using C++ throw/catch as an alternative to setjmp/longjmp in user
72	* mode code when IEM_WITH_SETJMP is in effect.
73	*
74	* With GCC 11.3.1 and code TLB on linux, using throw/catch instead of
75	* setjmp/long resulted in bs2-test-1 running 3.00% faster and all but on test
76	* result value improving by more than 1%. (Best out of three.)
77	*
78	* With Visual C++ 2019 and code TLB on windows, using throw/catch instead of
79	* setjmp/long resulted in bs2-test-1 running 3.68% faster and all but some of
80	* the MMIO and CPUID tests ran noticeably faster. Variation is greater than on
81	* Linux, but it should be quite a bit faster for normal code.
82	*/
83	#if (defined(__cplusplus) && defined(IEM_WITH_SETJMP) && defined(IN_RING3) && (defined(__GNUC__) \|\| defined(_MSC_VER))) \
84	\|\| defined(DOXYGEN_RUNNING)
85	# define IEM_WITH_THROW_CATCH
86	#endif
87
88	/** @def IEM_DO_LONGJMP
89	*
90	* Wrapper around longjmp / throw.
91	*
92	* @param a_pVCpu The CPU handle.
93	* @param a_rc The status code jump back with / throw.
94	*/
95	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
96	# ifdef IEM_WITH_THROW_CATCH
97	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) throw int(a_rc)
98	# else
99	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) longjmp(*(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf), (a_rc))
100	# endif
101	#endif
102
103	/** For use with IEM function that may do a longjmp (when enabled).
104	*
105	* Visual C++ has trouble longjmp'ing from/over functions with the noexcept
106	* attribute. So, we indicate that function that may be part of a longjmp may
107	* throw "exceptions" and that the compiler should definitely not generate and
108	* std::terminate calling unwind code.
109	*
110	* Here is one example of this ending in std::terminate:
111	* @code{.txt}
112	00 00000041`cadfda10 00007ffc`5d5a1f9f ucrtbase!abort+0x4e
113	01 00000041`cadfda40 00007ffc`57af229a ucrtbase!terminate+0x1f
114	02 00000041`cadfda70 00007ffb`eec91030 VCRUNTIME140!__std_terminate+0xa [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\ehhelpers.cpp @ 192]
115	03 00000041`cadfdaa0 00007ffb`eec92c6d VCRUNTIME140_1!_CallSettingFrame+0x20 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\handlers.asm @ 50]
116	04 00000041`cadfdad0 00007ffb`eec93ae5 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToState+0x241 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 1085]
117	05 00000041`cadfdc00 00007ffb`eec92258 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToEmptyState+0x2d [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 218]
118	06 00000041`cadfdc30 00007ffb`eec940e9 VCRUNTIME140_1!__InternalCxxFrameHandler<__FrameHandler4>+0x194 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 304]
119	07 00000041`cadfdcd0 00007ffc`5f9f249f VCRUNTIME140_1!__CxxFrameHandler4+0xa9 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 290]
120	08 00000041`cadfdd40 00007ffc`5f980939 ntdll!RtlpExecuteHandlerForUnwind+0xf
121	09 00000041`cadfdd70 00007ffc`5f9a0edd ntdll!RtlUnwindEx+0x339
122	0a 00000041`cadfe490 00007ffc`57aff976 ntdll!RtlUnwind+0xcd
123	0b 00000041`cadfea00 00007ffb`e1b5de01 VCRUNTIME140!__longjmp_internal+0xe6 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\longjmp.asm @ 140]
124	0c (Inline Function) --------`-------- VBoxVMM!iemOpcodeGetNextU8SlowJmp+0x95 [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 1155]
125	0d 00000041`cadfea50 00007ffb`e1b60f6b VBoxVMM!iemOpcodeGetNextU8Jmp+0xc1 [L:\vbox-intern\src\VBox\VMM\include\IEMInline.h @ 402]
126	0e 00000041`cadfea90 00007ffb`e1cc6201 VBoxVMM!IEMExecForExits+0xdb [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 10185]
127	0f 00000041`cadfec70 00007ffb`e1d0df8d VBoxVMM!EMHistoryExec+0x4f1 [L:\vbox-intern\src\VBox\VMM\VMMAll\EMAll.cpp @ 452]
128	10 00000041`cadfed60 00007ffb`e1d0d4c0 VBoxVMM!nemR3WinHandleExitCpuId+0x79d [L:\vbox-intern\src\VBox\VMM\VMMAll\NEMAllNativeTemplate-win.cpp.h @ 1829] @encode
129	@endcode
130	*
131	* @see https://developercommunity.visualstudio.com/t/fragile-behavior-of-longjmp-called-from-noexcept-f/1532859
132	*/
133	#if defined(IEM_WITH_SETJMP) && (defined(_MSC_VER) \|\| defined(IEM_WITH_THROW_CATCH))
134	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT_EX(false)
135	#else
136	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT
137	#endif
138
139	#define IEM_IMPLEMENTS_TASKSWITCH
140
141	/** @def IEM_WITH_3DNOW
142	* Includes the 3DNow decoding. */
143	#if (!defined(IEM_WITH_3DNOW) && !defined(IEM_WITHOUT_3DNOW)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
144	# define IEM_WITH_3DNOW
145	#endif
146
147	/** @def IEM_WITH_THREE_0F_38
148	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
149	#if (!defined(IEM_WITH_THREE_0F_38) && !defined(IEM_WITHOUT_THREE_0F_38)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
150	# define IEM_WITH_THREE_0F_38
151	#endif
152
153	/** @def IEM_WITH_THREE_0F_3A
154	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
155	#if (!defined(IEM_WITH_THREE_0F_3A) && !defined(IEM_WITHOUT_THREE_0F_3A)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
156	# define IEM_WITH_THREE_0F_3A
157	#endif
158
159	/** @def IEM_WITH_VEX
160	* Includes the VEX decoding. */
161	#if (!defined(IEM_WITH_VEX) && !defined(IEM_WITHOUT_VEX)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
162	# define IEM_WITH_VEX
163	#endif
164
165	/** @def IEM_CFG_TARGET_CPU
166	* The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
167	*
168	* By default we allow this to be configured by the user via the
169	* CPUM/GuestCpuName config string, but this comes at a slight cost during
170	* decoding. So, for applications of this code where there is no need to
171	* be dynamic wrt target CPU, just modify this define.
172	*/
173	#if !defined(IEM_CFG_TARGET_CPU) \|\| defined(DOXYGEN_RUNNING)
174	# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
175	#endif
176
177	//#define IEM_WITH_CODE_TLB // - work in progress
178	//#define IEM_WITH_DATA_TLB // - work in progress
179
180
181	/** @def IEM_USE_UNALIGNED_DATA_ACCESS
182	* Use unaligned accesses instead of elaborate byte assembly. */
183	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86) \|\| defined(DOXYGEN_RUNNING)
184	# define IEM_USE_UNALIGNED_DATA_ACCESS
185	#endif
186
187	//#define IEM_LOG_MEMORY_WRITES
188
189	#if !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
190	/** Instruction statistics. */
191	typedef struct IEMINSTRSTATS
192	{
193	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
194	# include "IEMInstructionStatisticsTmpl.h"
195	# undef IEM_DO_INSTR_STAT
196	} IEMINSTRSTATS;
197	#else
198	struct IEMINSTRSTATS;
199	typedef struct IEMINSTRSTATS IEMINSTRSTATS;
200	#endif
201	/** Pointer to IEM instruction statistics. */
202	typedef IEMINSTRSTATS *PIEMINSTRSTATS;
203
204
205	/** @name IEMTARGETCPU_EFL_BEHAVIOR_XXX - IEMCPU::aidxTargetCpuEflFlavour
206	* @{ */
207	#define IEMTARGETCPU_EFL_BEHAVIOR_NATIVE 0 /*< Native x86 EFLAGS result; Intel EFLAGS when on non-x86 hosts. /
208	#define IEMTARGETCPU_EFL_BEHAVIOR_INTEL 1 /*< Intel EFLAGS result. /
209	#define IEMTARGETCPU_EFL_BEHAVIOR_AMD 2 /*< AMD EFLAGS result /
210	#define IEMTARGETCPU_EFL_BEHAVIOR_RESERVED 3 /*< Reserved/dummy entry slot that's the same as 0. /
211	#define IEMTARGETCPU_EFL_BEHAVIOR_MASK 3 /*< For masking the index before use. /
212	/** Selects the right variant from a_aArray.
213	* pVCpu is implicit in the caller context. */
214	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT(a_aArray) \
215	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[1] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
216	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for when no native worker can
217	* be used because the host CPU does not support the operation. */
218	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_NON_NATIVE(a_aArray) \
219	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
220	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for a two dimentional
221	* array paralleling IEMCPU::aidxTargetCpuEflFlavour and a single bit index
222	* into the two.
223	* @sa IEM_SELECT_NATIVE_OR_FALLBACK */
224	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
225	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
226	(a_aaArray[a_fNative][pVCpu->iem.s.aidxTargetCpuEflFlavour[a_fNative] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
227	#else
228	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
229	(a_aaArray[0][pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
230	#endif
231	/** @} */
232
233	/**
234	* Picks @a a_pfnNative or @a a_pfnFallback according to the host CPU feature
235	* indicator given by @a a_fCpumFeatureMember (CPUMFEATURES member).
236	*
237	* On non-x86 hosts, this will shortcut to the fallback w/o checking the
238	* indicator.
239	*
240	* @sa IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX
241	*/
242	#if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
243	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) \
244	(g_CpumHostFeatures.s.a_fCpumFeatureMember ? a_pfnNative : a_pfnFallback)
245	#else
246	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) (a_pfnFallback)
247	#endif
248
249
250	/**
251	* Extended operand mode that includes a representation of 8-bit.
252	*
253	* This is used for packing down modes when invoking some C instruction
254	* implementations.
255	*/
256	typedef enum IEMMODEX
257	{
258	IEMMODEX_16BIT = IEMMODE_16BIT,
259	IEMMODEX_32BIT = IEMMODE_32BIT,
260	IEMMODEX_64BIT = IEMMODE_64BIT,
261	IEMMODEX_8BIT
262	} IEMMODEX;
263	AssertCompileSize(IEMMODEX, 4);
264
265
266	/**
267	* Branch types.
268	*/
269	typedef enum IEMBRANCH
270	{
271	IEMBRANCH_JUMP = 1,
272	IEMBRANCH_CALL,
273	IEMBRANCH_TRAP,
274	IEMBRANCH_SOFTWARE_INT,
275	IEMBRANCH_HARDWARE_INT
276	} IEMBRANCH;
277	AssertCompileSize(IEMBRANCH, 4);
278
279
280	/**
281	* INT instruction types.
282	*/
283	typedef enum IEMINT
284	{
285	/** INT n instruction (opcode 0xcd imm). */
286	IEMINT_INTN = 0,
287	/** Single byte INT3 instruction (opcode 0xcc). */
288	IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
289	/** Single byte INTO instruction (opcode 0xce). */
290	IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
291	/** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
292	IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
293	} IEMINT;
294	AssertCompileSize(IEMINT, 4);
295
296
297	/**
298	* A FPU result.
299	*/
300	typedef struct IEMFPURESULT
301	{
302	/** The output value. */
303	RTFLOAT80U r80Result;
304	/** The output status. */
305	uint16_t FSW;
306	} IEMFPURESULT;
307	AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
308	/** Pointer to a FPU result. */
309	typedef IEMFPURESULT *PIEMFPURESULT;
310	/** Pointer to a const FPU result. */
311	typedef IEMFPURESULT const *PCIEMFPURESULT;
312
313
314	/**
315	* A FPU result consisting of two output values and FSW.
316	*/
317	typedef struct IEMFPURESULTTWO
318	{
319	/** The first output value. */
320	RTFLOAT80U r80Result1;
321	/** The output status. */
322	uint16_t FSW;
323	/** The second output value. */
324	RTFLOAT80U r80Result2;
325	} IEMFPURESULTTWO;
326	AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
327	AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
328	/** Pointer to a FPU result consisting of two output values and FSW. */
329	typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
330	/** Pointer to a const FPU result consisting of two output values and FSW. */
331	typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
332
333
334	/**
335	* IEM TLB entry.
336	*
337	* Lookup assembly:
338	* @code{.asm}
339	; Calculate tag.
340	mov rax, [VA]
341	shl rax, 16
342	shr rax, 16 + X86_PAGE_SHIFT
343	or rax, [uTlbRevision]
344
345	; Do indexing.
346	movzx ecx, al
347	lea rcx, [pTlbEntries + rcx]
348
349	; Check tag.
350	cmp [rcx + IEMTLBENTRY.uTag], rax
351	jne .TlbMiss
352
353	; Check access.
354	mov rax, ACCESS_FLAGS \| MAPPING_R3_NOT_VALID \| 0xffffff00
355	and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
356	cmp rax, [uTlbPhysRev]
357	jne .TlbMiss
358
359	; Calc address and we're done.
360	mov eax, X86_PAGE_OFFSET_MASK
361	and eax, [VA]
362	or rax, [rcx + IEMTLBENTRY.pMappingR3]
363	%ifdef VBOX_WITH_STATISTICS
364	inc qword [cTlbHits]
365	%endif
366	jmp .Done
367
368	.TlbMiss:
369	mov r8d, ACCESS_FLAGS
370	mov rdx, [VA]
371	mov rcx, [pVCpu]
372	call iemTlbTypeMiss
373	.Done:
374
375	@endcode
376	*
377	*/
378	typedef struct IEMTLBENTRY
379	{
380	/** The TLB entry tag.
381	* Bits 35 thru 0 are made up of the virtual address shifted right 12 bits, this
382	* is ASSUMING a virtual address width of 48 bits.
383	*
384	* Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
385	*
386	* The TLB lookup code uses the current TLB revision, which won't ever be zero,
387	* enabling an extremely cheap TLB invalidation most of the time. When the TLB
388	* revision wraps around though, the tags needs to be zeroed.
389	*
390	* @note Try use SHRD instruction? After seeing
391	* https://gmplib.org/~tege/x86-timing.pdf, maybe not.
392	*
393	* @todo This will need to be reorganized for 57-bit wide virtual address and
394	* PCID (currently 12 bits) and ASID (currently 6 bits) support. We'll
395	* have to move the TLB entry versioning entirely to the
396	* fFlagsAndPhysRev member then, 57 bit wide VAs means we'll only have
397	* 19 bits left (64 - 57 + 12 = 19) and they'll almost entire be
398	* consumed by PCID and ASID (12 + 6 = 18).
399	*/
400	uint64_t uTag;
401	/** Access flags and physical TLB revision.
402	*
403	* - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
404	* - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
405	* - Bit 2 - page tables - not user (complemented X86_PTE_US).
406	* - Bit 3 - pgm phys/virt - not directly writable.
407	* - Bit 4 - pgm phys page - not directly readable.
408	* - Bit 5 - page tables - not accessed (complemented X86_PTE_A).
409	* - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
410	* - Bit 7 - tlb entry - pMappingR3 member not valid.
411	* - Bits 63 thru 8 are used for the physical TLB revision number.
412	*
413	* We're using complemented bit meanings here because it makes it easy to check
414	* whether special action is required. For instance a user mode write access
415	* would do a "TEST fFlags, (X86_PTE_RW \| X86_PTE_US \| X86_PTE_D)" and a
416	* non-zero result would mean special handling needed because either it wasn't
417	* writable, or it wasn't user, or the page wasn't dirty. A user mode read
418	* access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
419	* need to check any PTE flag.
420	*/
421	uint64_t fFlagsAndPhysRev;
422	/** The guest physical page address. */
423	uint64_t GCPhys;
424	/** Pointer to the ring-3 mapping. */
425	R3PTRTYPE(uint8_t *) pbMappingR3;
426	#if HC_ARCH_BITS == 32
427	uint32_t u32Padding1;
428	#endif
429	} IEMTLBENTRY;
430	AssertCompileSize(IEMTLBENTRY, 32);
431	/** Pointer to an IEM TLB entry. */
432	typedef IEMTLBENTRY *PIEMTLBENTRY;
433
434	/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
435	* @{ */
436	#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /*< Page tables: Not executable. /
437	#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /*< Page tables: Not writable. /
438	#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /*< Page tables: Not user accessible (supervisor only). /
439	#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /*< Phys page: Not writable (access handler, ROM, whatever). /
440	#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /*< Phys page: Not readable (MMIO / access handler, ROM) /
441	#define IEMTLBE_F_PT_NO_ACCESSED RT_BIT_64(5) /*< Phys tables: Not accessed (need to be marked accessed). /
442	#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /*< Page tables: Not dirty (needs to be made dirty on write). /
443	#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(7) /*< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. /
444	#define IEMTLBE_F_PG_UNASSIGNED RT_BIT_64(8) /*< Phys page: Unassigned memory (not RAM, ROM, MMIO2 or MMIO). /
445	#define IEMTLBE_F_PG_CODE_PAGE RT_BIT_64(9) /*< Phys page: Code page. /
446	#define IEMTLBE_F_PHYS_REV UINT64_C(0xfffffffffffffc00) /*< Physical revision mask. @sa IEMTLB_PHYS_REV_INCR /
447	/** @} */
448
449
450	/**
451	* An IEM TLB.
452	*
453	* We've got two of these, one for data and one for instructions.
454	*/
455	typedef struct IEMTLB
456	{
457	/** The TLB entries.
458	* We've choosen 256 because that way we can obtain the result directly from a
459	* 8-bit register without an additional AND instruction. */
460	IEMTLBENTRY aEntries[256];
461	/** The TLB revision.
462	* This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
463	* by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
464	* the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
465	* (The revision zero indicates an invalid TLB entry.)
466	*
467	* The initial value is choosen to cause an early wraparound. */
468	uint64_t uTlbRevision;
469	/** The TLB physical address revision - shadow of PGM variable.
470	*
471	* This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
472	* incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
473	* a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
474	* as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
475	*
476	* The initial value is choosen to cause an early wraparound. */
477	uint64_t volatile uTlbPhysRev;
478
479	/* Statistics: */
480
481	/** TLB hits (VBOX_WITH_STATISTICS only). */
482	uint64_t cTlbHits;
483	/** TLB misses. */
484	uint32_t cTlbMisses;
485	/** Slow read path. */
486	uint32_t cTlbSlowReadPath;
487	/** Safe read path. */
488	uint32_t cTlbSafeReadPath;
489	/** Safe write path. */
490	uint32_t cTlbSafeWritePath;
491	#if 0
492	/** TLB misses because of tag mismatch. */
493	uint32_t cTlbMissesTag;
494	/** TLB misses because of virtual access violation. */
495	uint32_t cTlbMissesVirtAccess;
496	/** TLB misses because of dirty bit. */
497	uint32_t cTlbMissesDirty;
498	/** TLB misses because of MMIO */
499	uint32_t cTlbMissesMmio;
500	/** TLB misses because of write access handlers. */
501	uint32_t cTlbMissesWriteHandler;
502	/** TLB misses because no r3(/r0) mapping. */
503	uint32_t cTlbMissesMapping;
504	#endif
505	/** Alignment padding. */
506	uint32_t au32Padding[6];
507	} IEMTLB;
508	AssertCompileSizeAlignment(IEMTLB, 64);
509	/** IEMTLB::uTlbRevision increment. */
510	#define IEMTLB_REVISION_INCR RT_BIT_64(36)
511	/** IEMTLB::uTlbRevision mask. */
512	#define IEMTLB_REVISION_MASK (~(RT_BIT_64(36) - 1))
513	/** IEMTLB::uTlbPhysRev increment.
514	* @sa IEMTLBE_F_PHYS_REV */
515	#define IEMTLB_PHYS_REV_INCR RT_BIT_64(10)
516	/**
517	* Calculates the TLB tag for a virtual address.
518	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
519	* @param a_pTlb The TLB.
520	* @param a_GCPtr The virtual address. Must be RTGCPTR or same size or
521	* the clearing of the top 16 bits won't work (if 32-bit
522	* we'll end up with mostly zeros).
523	*/
524	#define IEMTLB_CALC_TAG(a_pTlb, a_GCPtr) ( IEMTLB_CALC_TAG_NO_REV(a_GCPtr) \| (a_pTlb)->uTlbRevision )
525	/**
526	* Calculates the TLB tag for a virtual address but without TLB revision.
527	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
528	* @param a_GCPtr The virtual address. Must be RTGCPTR or same size or
529	* the clearing of the top 16 bits won't work (if 32-bit
530	* we'll end up with mostly zeros).
531	*/
532	#define IEMTLB_CALC_TAG_NO_REV(a_GCPtr) ( (((a_GCPtr) << 16) >> (GUEST_PAGE_SHIFT + 16)) )
533	/**
534	* Converts a TLB tag value into a TLB index.
535	* @returns Index into IEMTLB::aEntries.
536	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
537	*/
538	#define IEMTLB_TAG_TO_INDEX(a_uTag) ( (uint8_t)(a_uTag) )
539	/**
540	* Converts a TLB tag value into a TLB index.
541	* @returns Index into IEMTLB::aEntries.
542	* @param a_pTlb The TLB.
543	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
544	*/
545	#define IEMTLB_TAG_TO_ENTRY(a_pTlb, a_uTag) ( &(a_pTlb)->aEntries[IEMTLB_TAG_TO_INDEX(a_uTag)] )
546
547
548	/** @name IEM_MC_F_XXX - MC block flags/clues.
549	* @todo Merge with IEM_CIMPL_F_XXX
550	* @{ */
551	#define IEM_MC_F_ONLY_8086 RT_BIT_32(0)
552	#define IEM_MC_F_MIN_186 RT_BIT_32(1)
553	#define IEM_MC_F_MIN_286 RT_BIT_32(2)
554	#define IEM_MC_F_NOT_286_OR_OLDER IEM_MC_F_MIN_386
555	#define IEM_MC_F_MIN_386 RT_BIT_32(3)
556	#define IEM_MC_F_MIN_486 RT_BIT_32(4)
557	#define IEM_MC_F_MIN_PENTIUM RT_BIT_32(5)
558	#define IEM_MC_F_MIN_PENTIUM_II IEM_MC_F_MIN_PENTIUM
559	#define IEM_MC_F_MIN_CORE IEM_MC_F_MIN_PENTIUM
560	#define IEM_MC_F_64BIT RT_BIT_32(6)
561	#define IEM_MC_F_NOT_64BIT RT_BIT_32(7)
562	/** This is set by IEMAllN8vePython.py to indicate a variation without the
563	* flags-clearing-and-checking, when there is also a variation with that.
564	* @note Do not use this manully, it's only for python and for testing in
565	* the native recompiler! */
566	#define IEM_MC_F_WITHOUT_FLAGS RT_BIT_32(8)
567	/** @} */
568
569	/** @name IEM_CIMPL_F_XXX - State change clues for CIMPL calls.
570	*
571	* These clues are mainly for the recompiler, so that it can emit correct code.
572	*
573	* They are processed by the python script and which also automatically
574	* calculates flags for MC blocks based on the statements, extending the use of
575	* these flags to describe MC block behavior to the recompiler core. The python
576	* script pass the flags to the IEM_MC2_END_EMIT_CALLS macro, but mainly for
577	* error checking purposes. The script emits the necessary fEndTb = true and
578	* similar statements as this reduces compile time a tiny bit.
579	*
580	* @{ */
581	/** Flag set if direct branch, clear if absolute or indirect. */
582	#define IEM_CIMPL_F_BRANCH_DIRECT RT_BIT_32(0)
583	/** Flag set if indirect branch, clear if direct or relative.
584	* This is also used for all system control transfers (SYSCALL, SYSRET, INT, ++)
585	* as well as for return instructions (RET, IRET, RETF). */
586	#define IEM_CIMPL_F_BRANCH_INDIRECT RT_BIT_32(1)
587	/** Flag set if relative branch, clear if absolute or indirect. */
588	#define IEM_CIMPL_F_BRANCH_RELATIVE RT_BIT_32(2)
589	/** Flag set if conditional branch, clear if unconditional. */
590	#define IEM_CIMPL_F_BRANCH_CONDITIONAL RT_BIT_32(3)
591	/** Flag set if it's a far branch (changes CS). */
592	#define IEM_CIMPL_F_BRANCH_FAR RT_BIT_32(4)
593	/** Convenience: Testing any kind of branch. */
594	#define IEM_CIMPL_F_BRANCH_ANY (IEM_CIMPL_F_BRANCH_DIRECT \| IEM_CIMPL_F_BRANCH_INDIRECT \| IEM_CIMPL_F_BRANCH_RELATIVE)
595
596	/** Execution flags may change (IEMCPU::fExec). */
597	#define IEM_CIMPL_F_MODE RT_BIT_32(5)
598	/** May change significant portions of RFLAGS. */
599	#define IEM_CIMPL_F_RFLAGS RT_BIT_32(6)
600	/** May change the status bits (X86_EFL_STATUS_BITS) in RFLAGS. */
601	#define IEM_CIMPL_F_STATUS_FLAGS RT_BIT_32(7)
602	/** May trigger interrupt shadowing. */
603	#define IEM_CIMPL_F_INHIBIT_SHADOW RT_BIT_32(8)
604	/** May enable interrupts, so recheck IRQ immediately afterwards executing
605	* the instruction. */
606	#define IEM_CIMPL_F_CHECK_IRQ_AFTER RT_BIT_32(9)
607	/** May disable interrupts, so recheck IRQ immediately before executing the
608	* instruction. */
609	#define IEM_CIMPL_F_CHECK_IRQ_BEFORE RT_BIT_32(10)
610	/** Convenience: Check for IRQ both before and after an instruction. */
611	#define IEM_CIMPL_F_CHECK_IRQ_BEFORE_AND_AFTER (IEM_CIMPL_F_CHECK_IRQ_BEFORE \| IEM_CIMPL_F_CHECK_IRQ_AFTER)
612	/** May trigger a VM exit (treated like IEM_CIMPL_F_MODE atm). */
613	#define IEM_CIMPL_F_VMEXIT RT_BIT_32(11)
614	/** May modify FPU state.
615	* @todo Not sure if this is useful yet. */
616	#define IEM_CIMPL_F_FPU RT_BIT_32(12)
617	/** REP prefixed instruction which may yield before updating PC.
618	* @todo Not sure if this is useful, REP functions now return non-zero
619	* status if they don't update the PC. */
620	#define IEM_CIMPL_F_REP RT_BIT_32(13)
621	/** I/O instruction.
622	* @todo Not sure if this is useful yet. */
623	#define IEM_CIMPL_F_IO RT_BIT_32(14)
624	/** Force end of TB after the instruction. */
625	#define IEM_CIMPL_F_END_TB RT_BIT_32(15)
626	/** Flag set if a branch may also modify the stack (push/pop return address). */
627	#define IEM_CIMPL_F_BRANCH_STACK RT_BIT_32(16)
628	/** Flag set if a branch may also modify the stack (push/pop return address)
629	* and switch it (load/restore SS:RSP). */
630	#define IEM_CIMPL_F_BRANCH_STACK_FAR RT_BIT_32(17)
631	/** Convenience: Raise exception (technically unnecessary, since it shouldn't return VINF_SUCCESS). */
632	#define IEM_CIMPL_F_XCPT \
633	(IEM_CIMPL_F_BRANCH_INDIRECT \| IEM_CIMPL_F_BRANCH_FAR \| IEM_CIMPL_F_BRANCH_STACK_FAR \
634	\| IEM_CIMPL_F_MODE \| IEM_CIMPL_F_RFLAGS \| IEM_CIMPL_F_VMEXIT)
635
636	/** The block calls a C-implementation instruction function with two implicit arguments.
637	* Mutually exclusive with IEM_CIMPL_F_CALLS_AIMPL and
638	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
639	* @note The python scripts will add this is missing. */
640	#define IEM_CIMPL_F_CALLS_CIMPL RT_BIT_32(18)
641	/** The block calls an ASM-implementation instruction function.
642	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL and
643	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
644	* @note The python scripts will add this is missing. */
645	#define IEM_CIMPL_F_CALLS_AIMPL RT_BIT_32(19)
646	/** The block calls an ASM-implementation instruction function with an implicit
647	* X86FXSTATE pointer argument.
648	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL and IEM_CIMPL_F_CALLS_AIMPL.
649	* @note The python scripts will add this is missing. */
650	#define IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE RT_BIT_32(20)
651	/** @} */
652
653
654	/** @name IEM_F_XXX - Execution mode flags (IEMCPU::fExec, IEMTB::fFlags).
655	*
656	* These flags are set when entering IEM and adjusted as code is executed, such
657	* that they will always contain the current values as instructions are
658	* finished.
659	*
660	* In recompiled execution mode, (most of) these flags are included in the
661	* translation block selection key and stored in IEMTB::fFlags alongside the
662	* IEMTB_F_XXX flags. The latter flags uses bits 31 thru 24, which are all zero
663	* in IEMCPU::fExec.
664	*
665	* @{ */
666	/** Mode: The block target mode mask. */
667	#define IEM_F_MODE_MASK UINT32_C(0x0000001f)
668	/** Mode: The IEMMODE part of the IEMTB_F_MODE_MASK value. */
669	#define IEM_F_MODE_CPUMODE_MASK UINT32_C(0x00000003)
670	/** X86 Mode: Bit used to indicating pre-386 CPU in 16-bit mode (for eliminating
671	* conditional in EIP/IP updating), and flat wide open CS, SS DS, and ES in
672	* 32-bit mode (for simplifying most memory accesses). */
673	#define IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK UINT32_C(0x00000004)
674	/** X86 Mode: Bit indicating protected mode, real mode (or SMM) when not set. */
675	#define IEM_F_MODE_X86_PROT_MASK UINT32_C(0x00000008)
676	/** X86 Mode: Bit used to indicate virtual 8086 mode (only 16-bit). */
677	#define IEM_F_MODE_X86_V86_MASK UINT32_C(0x00000010)
678
679	/** X86 Mode: 16-bit on 386 or later. */
680	#define IEM_F_MODE_X86_16BIT UINT32_C(0x00000000)
681	/** X86 Mode: 80286, 80186 and 8086/88 targetting blocks (EIP update opt). */
682	#define IEM_F_MODE_X86_16BIT_PRE_386 UINT32_C(0x00000004)
683	/** X86 Mode: 16-bit protected mode on 386 or later. */
684	#define IEM_F_MODE_X86_16BIT_PROT UINT32_C(0x00000008)
685	/** X86 Mode: 16-bit protected mode on 386 or later. */
686	#define IEM_F_MODE_X86_16BIT_PROT_PRE_386 UINT32_C(0x0000000c)
687	/** X86 Mode: 16-bit virtual 8086 protected mode (on 386 or later). */
688	#define IEM_F_MODE_X86_16BIT_PROT_V86 UINT32_C(0x00000018)
689
690	/** X86 Mode: 32-bit on 386 or later. */
691	#define IEM_F_MODE_X86_32BIT UINT32_C(0x00000001)
692	/** X86 Mode: 32-bit mode with wide open flat CS, SS, DS and ES. */
693	#define IEM_F_MODE_X86_32BIT_FLAT UINT32_C(0x00000005)
694	/** X86 Mode: 32-bit protected mode. */
695	#define IEM_F_MODE_X86_32BIT_PROT UINT32_C(0x00000009)
696	/** X86 Mode: 32-bit protected mode with wide open flat CS, SS, DS and ES. */
697	#define IEM_F_MODE_X86_32BIT_PROT_FLAT UINT32_C(0x0000000d)
698
699	/** X86 Mode: 64-bit (includes protected, but not the flat bit). */
700	#define IEM_F_MODE_X86_64BIT UINT32_C(0x0000000a)
701
702
703	/** Bypass access handlers when set. */
704	#define IEM_F_BYPASS_HANDLERS UINT32_C(0x00010000)
705	/** Have pending hardware instruction breakpoints. */
706	#define IEM_F_PENDING_BRK_INSTR UINT32_C(0x00020000)
707	/** Have pending hardware data breakpoints. */
708	#define IEM_F_PENDING_BRK_DATA UINT32_C(0x00040000)
709
710	/** X86: Have pending hardware I/O breakpoints. */
711	#define IEM_F_PENDING_BRK_X86_IO UINT32_C(0x00000400)
712	/** X86: Disregard the lock prefix (implied or not) when set. */
713	#define IEM_F_X86_DISREGARD_LOCK UINT32_C(0x00000800)
714
715	/** Pending breakpoint mask (what iemCalcExecDbgFlags works out). */
716	#define IEM_F_PENDING_BRK_MASK (IEM_F_PENDING_BRK_INSTR \| IEM_F_PENDING_BRK_DATA \| IEM_F_PENDING_BRK_X86_IO)
717
718	/** Caller configurable options. */
719	#define IEM_F_USER_OPTS (IEM_F_BYPASS_HANDLERS \| IEM_F_X86_DISREGARD_LOCK)
720
721	/** X86: The current protection level (CPL) shift factor. */
722	#define IEM_F_X86_CPL_SHIFT 8
723	/** X86: The current protection level (CPL) mask. */
724	#define IEM_F_X86_CPL_MASK UINT32_C(0x00000300)
725	/** X86: The current protection level (CPL) shifted mask. */
726	#define IEM_F_X86_CPL_SMASK UINT32_C(0x00000003)
727
728	/** X86 execution context.
729	* The IEM_F_X86_CTX_XXX values are individual flags that can be combined (with
730	* the exception of IEM_F_X86_CTX_NORMAL). This allows running VMs from SMM
731	* mode. */
732	#define IEM_F_X86_CTX_MASK UINT32_C(0x0000f000)
733	/** X86 context: Plain regular execution context. */
734	#define IEM_F_X86_CTX_NORMAL UINT32_C(0x00000000)
735	/** X86 context: VT-x enabled. */
736	#define IEM_F_X86_CTX_VMX UINT32_C(0x00001000)
737	/** X86 context: AMD-V enabled. */
738	#define IEM_F_X86_CTX_SVM UINT32_C(0x00002000)
739	/** X86 context: In AMD-V or VT-x guest mode. */
740	#define IEM_F_X86_CTX_IN_GUEST UINT32_C(0x00004000)
741	/** X86 context: System management mode (SMM). */
742	#define IEM_F_X86_CTX_SMM UINT32_C(0x00008000)
743
744	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
745	* iemRegFinishClearingRF() most for most situations (CPUMCTX_DBG_HIT_DRX_MASK
746	* and CPUMCTX_DBG_DBGF_MASK are covered by the IEM_F_PENDING_BRK_XXX bits
747	* alread). */
748
749	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
750	* iemRegFinishClearingRF() most for most situations
751	* (CPUMCTX_DBG_HIT_DRX_MASK and CPUMCTX_DBG_DBGF_MASK are covered by
752	* the IEM_F_PENDING_BRK_XXX bits alread). */
753
754	/** @} */
755
756
757	/** @name IEMTB_F_XXX - Translation block flags (IEMTB::fFlags).
758	*
759	* Extends the IEM_F_XXX flags (subject to IEMTB_F_IEM_F_MASK) to make up the
760	* translation block flags. The combined flag mask (subject to
761	* IEMTB_F_KEY_MASK) is used as part of the lookup key for translation blocks.
762	*
763	* @{ */
764	/** Mask of IEM_F_XXX flags included in IEMTB_F_XXX. */
765	#define IEMTB_F_IEM_F_MASK UINT32_C(0x00ffffff)
766
767	/** Type: The block type mask. */
768	#define IEMTB_F_TYPE_MASK UINT32_C(0x03000000)
769	/** Type: Purly threaded recompiler (via tables). */
770	#define IEMTB_F_TYPE_THREADED UINT32_C(0x01000000)
771	/** Type: Native recompilation. */
772	#define IEMTB_F_TYPE_NATIVE UINT32_C(0x02000000)
773
774	/** Set when we're starting the block in an "interrupt shadow".
775	* We don't need to distingish between the two types of this mask, thus the one.
776	* @see CPUMCTX_INHIBIT_SHADOW, CPUMIsInInterruptShadow() */
777	#define IEMTB_F_INHIBIT_SHADOW UINT32_C(0x04000000)
778	/** Set when we're currently inhibiting NMIs
779	* @see CPUMCTX_INHIBIT_NMI, CPUMAreInterruptsInhibitedByNmi() */
780	#define IEMTB_F_INHIBIT_NMI UINT32_C(0x08000000)
781
782	/** Checks that EIP/IP is wihin CS.LIM before each instruction. Used when
783	* we're close the limit before starting a TB, as determined by
784	* iemGetTbFlagsForCurrentPc(). */
785	#define IEMTB_F_CS_LIM_CHECKS UINT32_C(0x10000000)
786
787	/** Mask of the IEMTB_F_XXX flags that are part of the TB lookup key.
788	* @note We skip the CPL as we don't currently generate ring-specific code,
789	* that's all handled in CIMPL functions.
790	*
791	* For the same reasons, we skip all of IEM_F_X86_CTX_MASK, with the
792	* exception of SMM (which we don't implement). */
793	#define IEMTB_F_KEY_MASK ( (UINT32_MAX & ~(IEM_F_X86_CTX_MASK \| IEM_F_X86_CPL_MASK \| IEMTB_F_TYPE_MASK)) \
794	\| IEM_F_X86_CTX_SMM)
795	/** @} */
796
797	AssertCompile( (IEM_F_MODE_X86_16BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
798	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
799	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_PROT_MASK));
800	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_V86_MASK));
801	AssertCompile( (IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
802	AssertCompile( IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
803	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_PROT_MASK));
804	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
805	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
806	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
807	AssertCompile( IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
808	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_V86_MASK));
809	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
810	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
811	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_PROT_MASK);
812	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
813	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_PROT_MASK);
814	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
815	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_V86_MASK);
816
817	AssertCompile( (IEM_F_MODE_X86_32BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
818	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
819	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_PROT_MASK));
820	AssertCompile( (IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
821	AssertCompile( IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
822	AssertCompile(!(IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_PROT_MASK));
823	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
824	AssertCompile(!(IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
825	AssertCompile( IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
826	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
827	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
828	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_PROT_MASK);
829
830	AssertCompile( (IEM_F_MODE_X86_64BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_64BIT);
831	AssertCompile( IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_PROT_MASK);
832	AssertCompile(!(IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
833
834	/** Native instruction type for use with the native code generator.
835	* This is a byte (uint8_t) for x86 and amd64 and uint32_t for the other(s). */
836	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
837	typedef uint8_t IEMNATIVEINSTR;
838	#else
839	typedef uint32_t IEMNATIVEINSTR;
840	#endif
841	/** Pointer to a native instruction unit. */
842	typedef IEMNATIVEINSTR *PIEMNATIVEINSTR;
843	/** Pointer to a const native instruction unit. */
844	typedef IEMNATIVEINSTR const *PCIEMNATIVEINSTR;
845
846	/**
847	* A call for the threaded call table.
848	*/
849	typedef struct IEMTHRDEDCALLENTRY
850	{
851	/** The function to call (IEMTHREADEDFUNCS). */
852	uint16_t enmFunction;
853	/** Instruction number in the TB (for statistics). */
854	uint8_t idxInstr;
855	uint8_t uUnused0;
856
857	/** Offset into IEMTB::pabOpcodes. */
858	uint16_t offOpcode;
859	/** The opcode length. */
860	uint8_t cbOpcode;
861	/** Index in to IEMTB::aRanges. */
862	uint8_t idxRange;
863
864	/** Generic parameters. */
865	uint64_t auParams[3];
866	} IEMTHRDEDCALLENTRY;
867	AssertCompileSize(IEMTHRDEDCALLENTRY, sizeof(uint64_t) * 4);
868	/** Pointer to a threaded call entry. */
869	typedef struct IEMTHRDEDCALLENTRY *PIEMTHRDEDCALLENTRY;
870	/** Pointer to a const threaded call entry. */
871	typedef IEMTHRDEDCALLENTRY const *PCIEMTHRDEDCALLENTRY;
872
873	/**
874	* Native IEM TB 'function' typedef.
875	*
876	* This will throw/longjmp on occation.
877	*
878	* @note AMD64 doesn't have that many non-volatile registers and does sport
879	* 32-bit address displacments, so we don't need pCtx.
880	*
881	* On ARM64 pCtx allows us to directly address the whole register
882	* context without requiring a separate indexing register holding the
883	* offset. This saves an instruction loading the offset for each guest
884	* CPU context access, at the cost of a non-volatile register.
885	* Fortunately, ARM64 has quite a lot more registers.
886	*/
887	typedef
888	#ifdef RT_ARCH_AMD64
889	int FNIEMTBNATIVE(PVMCPUCC pVCpu)
890	#else
891	int FNIEMTBNATIVE(PVMCPUCC pVCpu, PCPUMCTX pCtx)
892	#endif
893	#if RT_CPLUSPLUS_PREREQ(201700)
894	IEM_NOEXCEPT_MAY_LONGJMP
895	#endif
896	;
897	/** Pointer to a native IEM TB entry point function.
898	* This will throw/longjmp on occation. */
899	typedef FNIEMTBNATIVE *PFNIEMTBNATIVE;
900
901
902	/**
903	* Translation block debug info entry type.
904	*/
905	typedef enum IEMTBDBGENTRYTYPE
906	{
907	kIemTbDbgEntryType_Invalid = 0,
908	/** The entry is for marking a native code position.
909	* Entries following this all apply to this position. */
910	kIemTbDbgEntryType_NativeOffset,
911	/** The entry is for a new guest instruction. */
912	kIemTbDbgEntryType_GuestInstruction,
913	/** Marks the start of a threaded call. */
914	kIemTbDbgEntryType_ThreadedCall,
915	/** Marks the location of a label. */
916	kIemTbDbgEntryType_Label,
917	/** Info about a host register shadowing a guest register. */
918	kIemTbDbgEntryType_GuestRegShadowing,
919	kIemTbDbgEntryType_End
920	} IEMTBDBGENTRYTYPE;
921
922	/**
923	* Translation block debug info entry.
924	*/
925	typedef union IEMTBDBGENTRY
926	{
927	/** Plain 32-bit view. */
928	uint32_t u;
929
930	/** Generic view for getting at the type field. */
931	struct
932	{
933	/** IEMTBDBGENTRYTYPE */
934	uint32_t uType : 4;
935	uint32_t uTypeSpecific : 28;
936	} Gen;
937
938	struct
939	{
940	/** kIemTbDbgEntryType_ThreadedCall1. */
941	uint32_t uType : 4;
942	/** Native code offset. */
943	uint32_t offNative : 28;
944	} NativeOffset;
945
946	struct
947	{
948	/** kIemTbDbgEntryType_GuestInstruction. */
949	uint32_t uType : 4;
950	uint32_t uUnused : 4;
951	/** The IEM_F_XXX flags. */
952	uint32_t fExec : 24;
953	} GuestInstruction;
954
955	struct
956	{
957	/* kIemTbDbgEntryType_ThreadedCall. */
958	uint32_t uType : 4;
959	/** Set if the call was recompiled to native code, clear if just calling
960	* threaded function. */
961	uint32_t fRecompiled : 1;
962	uint32_t uUnused : 11;
963	/** The threaded call number (IEMTHREADEDFUNCS). */
964	uint32_t enmCall : 16;
965	} ThreadedCall;
966
967	struct
968	{
969	/* kIemTbDbgEntryType_Label. */
970	uint32_t uType : 4;
971	uint32_t uUnused : 4;
972	/** The label type (IEMNATIVELABELTYPE). */
973	uint32_t enmLabel : 8;
974	/** The label data. */
975	uint32_t uData : 16;
976	} Label;
977
978	struct
979	{
980	/* kIemTbDbgEntryType_GuestRegShadowing. */
981	uint32_t uType : 4;
982	uint32_t uUnused : 4;
983	/** The guest register being shadowed (IEMNATIVEGSTREG). */
984	uint32_t idxGstReg : 8;
985	/** The host new register number, UINT8_MAX if dropped. */
986	uint32_t idxHstReg : 8;
987	/** The previous host register number, UINT8_MAX if new. */
988	uint32_t idxHstRegPrev : 8;
989	} GuestRegShadowing;
990	} IEMTBDBGENTRY;
991	AssertCompileSize(IEMTBDBGENTRY, sizeof(uint32_t));
992	/** Pointer to a debug info entry. */
993	typedef IEMTBDBGENTRY *PIEMTBDBGENTRY;
994	/** Pointer to a const debug info entry. */
995	typedef IEMTBDBGENTRY const *PCIEMTBDBGENTRY;
996
997	/**
998	* Translation block debug info.
999	*/
1000	typedef struct IEMTBDBG
1001	{
1002	/** Number of entries in aEntries. */
1003	uint32_t cEntries;
1004	/** Debug info entries. */
1005	RT_FLEXIBLE_ARRAY_EXTENSION
1006	IEMTBDBGENTRY aEntries[RT_FLEXIBLE_ARRAY];
1007	} IEMTBDBG;
1008	/** Pointer to TB debug info. */
1009	typedef IEMTBDBG *PIEMTBDBG;
1010	/** Pointer to const TB debug info. */
1011	typedef IEMTBDBG const *PCIEMTBDBG;
1012
1013
1014	/**
1015	* Translation block.
1016	*
1017	* The current plan is to just keep TBs and associated lookup hash table private
1018	* to each VCpu as that simplifies TB removal greatly (no races) and generally
1019	* avoids using expensive atomic primitives for updating lists and stuff.
1020	*/
1021	#pragma pack(2) /* to prevent the Thrd structure from being padded unnecessarily */
1022	typedef struct IEMTB
1023	{
1024	/** Next block with the same hash table entry. */
1025	struct IEMTB *pNext;
1026	/** Usage counter. */
1027	uint32_t cUsed;
1028	/** The IEMCPU::msRecompilerPollNow last time it was used. */
1029	uint32_t msLastUsed;
1030
1031	/** @name What uniquely identifies the block.
1032	* @{ */
1033	RTGCPHYS GCPhysPc;
1034	/** IEMTB_F_XXX (i.e. IEM_F_XXX ++). */
1035	uint32_t fFlags;
1036	union
1037	{
1038	struct
1039	{
1040	/*< Relevant CS X86DESCATTR_XXX bits. /
1041	uint16_t fAttr;
1042	} x86;
1043	};
1044	/** @} */
1045
1046	/** Number of opcode ranges. */
1047	uint8_t cRanges;
1048	/** Statistics: Number of instructions in the block. */
1049	uint8_t cInstructions;
1050
1051	/** Type specific info. */
1052	union
1053	{
1054	struct
1055	{
1056	/** The call sequence table. */
1057	PIEMTHRDEDCALLENTRY paCalls;
1058	/** Number of calls in paCalls. */
1059	uint16_t cCalls;
1060	/** Number of calls allocated. */
1061	uint16_t cAllocated;
1062	} Thrd;
1063	struct
1064	{
1065	/** The native instructions (PFNIEMTBNATIVE). */
1066	PIEMNATIVEINSTR paInstructions;
1067	/** Number of instructions pointed to by paInstructions. */
1068	uint32_t cInstructions;
1069	} Native;
1070	/** Generic view for zeroing when freeing. */
1071	struct
1072	{
1073	uintptr_t uPtr;
1074	uint32_t uData;
1075	} Gen;
1076	};
1077
1078	/** The allocation chunk this TB belongs to. */
1079	uint8_t idxAllocChunk;
1080	uint8_t bUnused;
1081
1082	/** Number of bytes of opcodes stored in pabOpcodes.
1083	* @todo this field isn't really needed, aRanges keeps the actual info. */
1084	uint16_t cbOpcodes;
1085	/** Pointer to the opcode bytes this block was recompiled from. */
1086	uint8_t *pabOpcodes;
1087
1088	/** Debug info if enabled.
1089	* This is only generated by the native recompiler. */
1090	PIEMTBDBG pDbgInfo;
1091
1092	/* --- 64 byte cache line end --- */
1093
1094	/** Opcode ranges.
1095	*
1096	* The opcode checkers and maybe TLB loading functions will use this to figure
1097	* out what to do. The parameter will specify an entry and the opcode offset to
1098	* start at and the minimum number of bytes to verify (instruction length).
1099	*
1100	* When VT-x and AMD-V looks up the opcode bytes for an exitting instruction,
1101	* they'll first translate RIP (+ cbInstr - 1) to a physical address using the
1102	* code TLB (must have a valid entry for that address) and scan the ranges to
1103	* locate the corresponding opcodes. Probably.
1104	*/
1105	struct IEMTBOPCODERANGE
1106	{
1107	/** Offset within pabOpcodes. */
1108	uint16_t offOpcodes;
1109	/** Number of bytes. */
1110	uint16_t cbOpcodes;
1111	/** The page offset. */
1112	RT_GCC_EXTENSION
1113	uint16_t offPhysPage : 12;
1114	/** Unused bits. */
1115	RT_GCC_EXTENSION
1116	uint16_t u2Unused : 2;
1117	/** Index into GCPhysPc + aGCPhysPages for the physical page address. */
1118	RT_GCC_EXTENSION
1119	uint16_t idxPhysPage : 2;
1120	} aRanges[8];
1121
1122	/** Physical pages that this TB covers.
1123	* The GCPhysPc w/o page offset is element zero, so starting here with 1. */
1124	RTGCPHYS aGCPhysPages[2];
1125	} IEMTB;
1126	#pragma pack()
1127	AssertCompileMemberAlignment(IEMTB, GCPhysPc, sizeof(RTGCPHYS));
1128	AssertCompileMemberAlignment(IEMTB, Thrd, sizeof(void *));
1129	AssertCompileMemberAlignment(IEMTB, pabOpcodes, sizeof(void *));
1130	AssertCompileMemberAlignment(IEMTB, pDbgInfo, sizeof(void *));
1131	AssertCompileMemberAlignment(IEMTB, aGCPhysPages, sizeof(RTGCPHYS));
1132	AssertCompileMemberOffset(IEMTB, aRanges, 64);
1133	AssertCompileMemberSize(IEMTB, aRanges[0], 6);
1134	#if 1
1135	AssertCompileSize(IEMTB, 128);
1136	# define IEMTB_SIZE_IS_POWER_OF_TWO /*< The IEMTB size is a power of two. /
1137	#else
1138	AssertCompileSize(IEMTB, 168);
1139	# undef IEMTB_SIZE_IS_POWER_OF_TWO
1140	#endif
1141
1142	/** Pointer to a translation block. */
1143	typedef IEMTB *PIEMTB;
1144	/** Pointer to a const translation block. */
1145	typedef IEMTB const *PCIEMTB;
1146
1147	/**
1148	* A chunk of memory in the TB allocator.
1149	*/
1150	typedef struct IEMTBCHUNK
1151	{
1152	/** Pointer to the translation blocks in this chunk. */
1153	PIEMTB paTbs;
1154	#ifdef IN_RING0
1155	/** Allocation handle. */
1156	RTR0MEMOBJ hMemObj;
1157	#endif
1158	} IEMTBCHUNK;
1159
1160	/**
1161	* A per-CPU translation block allocator.
1162	*
1163	* Because of how the IEMTBCACHE uses the lower 6 bits of the TB address to keep
1164	* the length of the collision list, and of course also for cache line alignment
1165	* reasons, the TBs must be allocated with at least 64-byte alignment.
1166	* Memory is there therefore allocated using one of the page aligned allocators.
1167	*
1168	*
1169	* To avoid wasting too much memory, it is allocated piecemeal as needed,
1170	* in chunks (IEMTBCHUNK) of 2 MiB or more. The TB has an 8-bit chunk index
1171	* that enables us to quickly calculate the allocation bitmap position when
1172	* freeing the translation block.
1173	*/
1174	typedef struct IEMTBALLOCATOR
1175	{
1176	/** Magic value (IEMTBALLOCATOR_MAGIC). */
1177	uint32_t uMagic;
1178
1179	#ifdef IEMTB_SIZE_IS_POWER_OF_TWO
1180	/** Mask corresponding to cTbsPerChunk - 1. */
1181	uint32_t fChunkMask;
1182	/** Shift count corresponding to cTbsPerChunk. */
1183	uint8_t cChunkShift;
1184	#else
1185	uint32_t uUnused;
1186	uint8_t bUnused;
1187	#endif
1188	/** Number of chunks we're allowed to allocate. */
1189	uint8_t cMaxChunks;
1190	/** Number of chunks currently populated. */
1191	uint16_t cAllocatedChunks;
1192	/** Number of translation blocks per chunk. */
1193	uint32_t cTbsPerChunk;
1194	/** Chunk size. */
1195	uint32_t cbPerChunk;
1196
1197	/** The maximum number of TBs. */
1198	uint32_t cMaxTbs;
1199	/** Total number of TBs in the populated chunks.
1200	* (cAllocatedChunks * cTbsPerChunk) */
1201	uint32_t cTotalTbs;
1202	/** The current number of TBs in use.
1203	* The number of free TBs: cAllocatedTbs - cInUseTbs; */
1204	uint32_t cInUseTbs;
1205	/** Statistics: Number of the cInUseTbs that are native ones. */
1206	uint32_t cNativeTbs;
1207	/** Statistics: Number of the cInUseTbs that are threaded ones. */
1208	uint32_t cThreadedTbs;
1209
1210	/** Where to start pruning TBs from when we're out.
1211	* See iemTbAllocatorAllocSlow for details. */
1212	uint32_t iPruneFrom;
1213	/** Hint about which bit to start scanning the bitmap from. */
1214	uint32_t iStartHint;
1215
1216	/** Statistics: Number of TB allocation calls. */
1217	STAMCOUNTER StatAllocs;
1218	/** Statistics: Number of TB free calls. */
1219	STAMCOUNTER StatFrees;
1220	/** Statistics: Time spend pruning. */
1221	STAMPROFILE StatPrune;
1222
1223	/** The delayed free list (see iemTbAlloctorScheduleForFree). */
1224	PIEMTB pDelayedFreeHead;
1225
1226	/** Allocation chunks. */
1227	IEMTBCHUNK aChunks[256];
1228
1229	/** Allocation bitmap for all possible chunk chunks. */
1230	RT_FLEXIBLE_ARRAY_EXTENSION
1231	uint64_t bmAllocated[RT_FLEXIBLE_ARRAY];
1232	} IEMTBALLOCATOR;
1233	/** Pointer to a TB allocator. */
1234	typedef struct IEMTBALLOCATOR *PIEMTBALLOCATOR;
1235
1236	/** Magic value for the TB allocator (Emmet Harley Cohen). */
1237	#define IEMTBALLOCATOR_MAGIC UINT32_C(0x19900525)
1238
1239
1240	/**
1241	* A per-CPU translation block cache (hash table).
1242	*
1243	* The hash table is allocated once during IEM initialization and size double
1244	* the max TB count, rounded up to the nearest power of two (so we can use and
1245	* AND mask rather than a rest division when hashing).
1246	*/
1247	typedef struct IEMTBCACHE
1248	{
1249	/** Magic value (IEMTBCACHE_MAGIC). */
1250	uint32_t uMagic;
1251	/** Size of the hash table. This is a power of two. */
1252	uint32_t cHash;
1253	/** The mask corresponding to cHash. */
1254	uint32_t uHashMask;
1255	uint32_t uPadding;
1256
1257	/** @name Statistics
1258	* @{ */
1259	/** Number of collisions ever. */
1260	STAMCOUNTER cCollisions;
1261
1262	/** Statistics: Number of TB lookup misses. */
1263	STAMCOUNTER cLookupMisses;
1264	/** Statistics: Number of TB lookup hits (debug only). */
1265	STAMCOUNTER cLookupHits;
1266	STAMCOUNTER auPadding2[3];
1267	/** Statistics: Collision list length pruning. */
1268	STAMPROFILE StatPrune;
1269	/** @} */
1270
1271	/** The hash table itself.
1272	* @note The lower 6 bits of the pointer is used for keeping the collision
1273	* list length, so we can take action when it grows too long.
1274	* This works because TBs are allocated using a 64 byte (or
1275	* higher) alignment from page aligned chunks of memory, so the lower
1276	* 6 bits of the address will always be zero.
1277	* See IEMTBCACHE_PTR_COUNT_MASK, IEMTBCACHE_PTR_MAKE and friends.
1278	*/
1279	RT_FLEXIBLE_ARRAY_EXTENSION
1280	PIEMTB apHash[RT_FLEXIBLE_ARRAY];
1281	} IEMTBCACHE;
1282	/** Pointer to a per-CPU translation block cahce. */
1283	typedef IEMTBCACHE *PIEMTBCACHE;
1284
1285	/** Magic value for IEMTBCACHE (Johnny O'Neal). */
1286	#define IEMTBCACHE_MAGIC UINT32_C(0x19561010)
1287
1288	/** The collision count mask for IEMTBCACHE::apHash entries. */
1289	#define IEMTBCACHE_PTR_COUNT_MASK ((uintptr_t)0x3f)
1290	/** The max collision count for IEMTBCACHE::apHash entries before pruning. */
1291	#define IEMTBCACHE_PTR_MAX_COUNT ((uintptr_t)0x30)
1292	/** Combine a TB pointer and a collision list length into a value for an
1293	* IEMTBCACHE::apHash entry. */
1294	#define IEMTBCACHE_PTR_MAKE(a_pTb, a_cCount) (PIEMTB)((uintptr_t)(a_pTb) \| (a_cCount))
1295	/** Combine a TB pointer and a collision list length into a value for an
1296	* IEMTBCACHE::apHash entry. */
1297	#define IEMTBCACHE_PTR_GET_TB(a_pHashEntry) (PIEMTB)((uintptr_t)(a_pHashEntry) & ~IEMTBCACHE_PTR_COUNT_MASK)
1298	/** Combine a TB pointer and a collision list length into a value for an
1299	* IEMTBCACHE::apHash entry. */
1300	#define IEMTBCACHE_PTR_GET_COUNT(a_pHashEntry) ((uintptr_t)(a_pHashEntry) & IEMTBCACHE_PTR_COUNT_MASK)
1301
1302	/**
1303	* Calculates the hash table slot for a TB from physical PC address and TB flags.
1304	*/
1305	#define IEMTBCACHE_HASH(a_paCache, a_fTbFlags, a_GCPhysPc) \
1306	IEMTBCACHE_HASH_NO_KEY_MASK(a_paCache, (a_fTbFlags) & IEMTB_F_KEY_MASK, a_GCPhysPc)
1307
1308	/**
1309	* Calculates the hash table slot for a TB from physical PC address and TB
1310	* flags, ASSUMING the caller has applied IEMTB_F_KEY_MASK to @a a_fTbFlags.
1311	*/
1312	#define IEMTBCACHE_HASH_NO_KEY_MASK(a_paCache, a_fTbFlags, a_GCPhysPc) \
1313	(((uint32_t)(a_GCPhysPc) ^ (a_fTbFlags)) & (a_paCache)->uHashMask)
1314
1315
1316	/** @name IEMBRANCHED_F_XXX - Branched indicator (IEMCPU::fTbBranched).
1317	*
1318	* These flags parallels the main IEM_CIMPL_F_BRANCH_XXX flags.
1319	*
1320	* @{ */
1321	/** Value if no branching happened recently. */
1322	#define IEMBRANCHED_F_NO UINT8_C(0x00)
1323	/** Flag set if direct branch, clear if absolute or indirect. */
1324	#define IEMBRANCHED_F_DIRECT UINT8_C(0x01)
1325	/** Flag set if indirect branch, clear if direct or relative. */
1326	#define IEMBRANCHED_F_INDIRECT UINT8_C(0x02)
1327	/** Flag set if relative branch, clear if absolute or indirect. */
1328	#define IEMBRANCHED_F_RELATIVE UINT8_C(0x04)
1329	/** Flag set if conditional branch, clear if unconditional. */
1330	#define IEMBRANCHED_F_CONDITIONAL UINT8_C(0x08)
1331	/** Flag set if it's a far branch. */
1332	#define IEMBRANCHED_F_FAR UINT8_C(0x10)
1333	/** Flag set if the stack pointer is modified. */
1334	#define IEMBRANCHED_F_STACK UINT8_C(0x20)
1335	/** Flag set if the stack pointer and (maybe) the stack segment are modified. */
1336	#define IEMBRANCHED_F_STACK_FAR UINT8_C(0x40)
1337	/** Flag set (by IEM_MC_REL_JMP_XXX) if it's a zero bytes relative jump. */
1338	#define IEMBRANCHED_F_ZERO UINT8_C(0x80)
1339	/** @} */
1340
1341
1342	/**
1343	* The per-CPU IEM state.
1344	*/
1345	typedef struct IEMCPU
1346	{
1347	/** Info status code that needs to be propagated to the IEM caller.
1348	* This cannot be passed internally, as it would complicate all success
1349	* checks within the interpreter making the code larger and almost impossible
1350	* to get right. Instead, we'll store status codes to pass on here. Each
1351	* source of these codes will perform appropriate sanity checks. */
1352	int32_t rcPassUp; /* 0x00 */
1353	/** Execution flag, IEM_F_XXX. */
1354	uint32_t fExec; /* 0x04 */
1355
1356	/** @name Decoder state.
1357	* @{ */
1358	#ifndef IEM_WITH_OPAQUE_DECODER_STATE
1359	# ifdef IEM_WITH_CODE_TLB
1360	/** The offset of the next instruction byte. */
1361	uint32_t offInstrNextByte; /* 0x08 */
1362	/** The number of bytes available at pbInstrBuf for the current instruction.
1363	* This takes the max opcode length into account so that doesn't need to be
1364	* checked separately. */
1365	uint32_t cbInstrBuf; /* 0x0c */
1366	/** Pointer to the page containing RIP, user specified buffer or abOpcode.
1367	* This can be NULL if the page isn't mappable for some reason, in which
1368	* case we'll do fallback stuff.
1369	*
1370	* If we're executing an instruction from a user specified buffer,
1371	* IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
1372	* aligned pointer but pointer to the user data.
1373	*
1374	* For instructions crossing pages, this will start on the first page and be
1375	* advanced to the next page by the time we've decoded the instruction. This
1376	* therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
1377	*/
1378	uint8_t const pbInstrBuf; / 0x10 */
1379	# if ARCH_BITS == 32
1380	uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
1381	# endif
1382	/** The program counter corresponding to pbInstrBuf.
1383	* This is set to a non-canonical address when we need to invalidate it. */
1384	uint64_t uInstrBufPc; /* 0x18 */
1385	/** The guest physical address corresponding to pbInstrBuf. */
1386	RTGCPHYS GCPhysInstrBuf; /* 0x20 */
1387	/** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
1388	* This takes the CS segment limit into account. */
1389	uint16_t cbInstrBufTotal; /* 0x28 */
1390	/** Offset into pbInstrBuf of the first byte of the current instruction.
1391	* Can be negative to efficiently handle cross page instructions. */
1392	int16_t offCurInstrStart; /* 0x2a */
1393
1394	/** The prefix mask (IEM_OP_PRF_XXX). */
1395	uint32_t fPrefixes; /* 0x2c */
1396	/** The extra REX ModR/M register field bit (REX.R << 3). */
1397	uint8_t uRexReg; /* 0x30 */
1398	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
1399	* (REX.B << 3). */
1400	uint8_t uRexB; /* 0x31 */
1401	/** The extra REX SIB index field bit (REX.X << 3). */
1402	uint8_t uRexIndex; /* 0x32 */
1403
1404	/** The effective segment register (X86_SREG_XXX). */
1405	uint8_t iEffSeg; /* 0x33 */
1406
1407	/** The offset of the ModR/M byte relative to the start of the instruction. */
1408	uint8_t offModRm; /* 0x34 */
1409
1410	# ifdef IEM_WITH_CODE_TLB_AND_OPCODE_BUF
1411	/** The current offset into abOpcode. */
1412	uint8_t offOpcode; /* 0x35 */
1413	# else
1414	uint8_t bUnused; /* 0x35 */
1415	# endif
1416	# else /* !IEM_WITH_CODE_TLB */
1417	/** The size of what has currently been fetched into abOpcode. */
1418	uint8_t cbOpcode; /* 0x08 */
1419	/** The current offset into abOpcode. */
1420	uint8_t offOpcode; /* 0x09 */
1421	/** The offset of the ModR/M byte relative to the start of the instruction. */
1422	uint8_t offModRm; /* 0x0a */
1423
1424	/** The effective segment register (X86_SREG_XXX). */
1425	uint8_t iEffSeg; /* 0x0b */
1426
1427	/** The prefix mask (IEM_OP_PRF_XXX). */
1428	uint32_t fPrefixes; /* 0x0c */
1429	/** The extra REX ModR/M register field bit (REX.R << 3). */
1430	uint8_t uRexReg; /* 0x10 */
1431	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
1432	* (REX.B << 3). */
1433	uint8_t uRexB; /* 0x11 */
1434	/** The extra REX SIB index field bit (REX.X << 3). */
1435	uint8_t uRexIndex; /* 0x12 */
1436
1437	# endif /* !IEM_WITH_CODE_TLB */
1438
1439	/** The effective operand mode. */
1440	IEMMODE enmEffOpSize; /* 0x36, 0x13 */
1441	/** The default addressing mode. */
1442	IEMMODE enmDefAddrMode; /* 0x37, 0x14 */
1443	/** The effective addressing mode. */
1444	IEMMODE enmEffAddrMode; /* 0x38, 0x15 */
1445	/** The default operand mode. */
1446	IEMMODE enmDefOpSize; /* 0x39, 0x16 */
1447
1448	/** Prefix index (VEX.pp) for two byte and three byte tables. */
1449	uint8_t idxPrefix; /* 0x3a, 0x17 */
1450	/** 3rd VEX/EVEX/XOP register.
1451	* Please use IEM_GET_EFFECTIVE_VVVV to access. */
1452	uint8_t uVex3rdReg; /* 0x3b, 0x18 */
1453	/** The VEX/EVEX/XOP length field. */
1454	uint8_t uVexLength; /* 0x3c, 0x19 */
1455	/** Additional EVEX stuff. */
1456	uint8_t fEvexStuff; /* 0x3d, 0x1a */
1457
1458	# ifndef IEM_WITH_CODE_TLB
1459	/** Explicit alignment padding. */
1460	uint8_t abAlignment2a[1]; /* 0x1b */
1461	# endif
1462	/** The FPU opcode (FOP). */
1463	uint16_t uFpuOpcode; /* 0x3e, 0x1c */
1464	# ifndef IEM_WITH_CODE_TLB
1465	/** Explicit alignment padding. */
1466	uint8_t abAlignment2b[2]; /* 0x1e */
1467	# endif
1468
1469	/** The opcode bytes. */
1470	uint8_t abOpcode[15]; /* 0x40, 0x20 */
1471	/** Explicit alignment padding. */
1472	# ifdef IEM_WITH_CODE_TLB
1473	//uint8_t abAlignment2c[0x4f - 0x4f]; /* 0x4f */
1474	# else
1475	uint8_t abAlignment2c[0x4f - 0x2f]; /* 0x2f */
1476	# endif
1477	#else /* IEM_WITH_OPAQUE_DECODER_STATE */
1478	uint8_t abOpaqueDecoder[0x4f - 0x8];
1479	#endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1480	/** @} */
1481
1482
1483	/** The number of active guest memory mappings. */
1484	uint8_t cActiveMappings; /* 0x4f, 0x4f */
1485
1486	/** Records for tracking guest memory mappings. */
1487	struct
1488	{
1489	/** The address of the mapped bytes. */
1490	R3R0PTRTYPE(void *) pv;
1491	/** The access flags (IEM_ACCESS_XXX).
1492	* IEM_ACCESS_INVALID if the entry is unused. */
1493	uint32_t fAccess;
1494	#if HC_ARCH_BITS == 64
1495	uint32_t u32Alignment4; /*< Alignment padding. /
1496	#endif
1497	} aMemMappings[3]; /* 0x50 LB 0x30 */
1498
1499	/** Locking records for the mapped memory. */
1500	union
1501	{
1502	PGMPAGEMAPLOCK Lock;
1503	uint64_t au64Padding[2];
1504	} aMemMappingLocks[3]; /* 0x80 LB 0x30 */
1505
1506	/** Bounce buffer info.
1507	* This runs in parallel to aMemMappings. */
1508	struct
1509	{
1510	/** The physical address of the first byte. */
1511	RTGCPHYS GCPhysFirst;
1512	/** The physical address of the second page. */
1513	RTGCPHYS GCPhysSecond;
1514	/** The number of bytes in the first page. */
1515	uint16_t cbFirst;
1516	/** The number of bytes in the second page. */
1517	uint16_t cbSecond;
1518	/** Whether it's unassigned memory. */
1519	bool fUnassigned;
1520	/** Explicit alignment padding. */
1521	bool afAlignment5[3];
1522	} aMemBbMappings[3]; /* 0xb0 LB 0x48 */
1523
1524	/** The flags of the current exception / interrupt. */
1525	uint32_t fCurXcpt; /* 0xf8 */
1526	/** The current exception / interrupt. */
1527	uint8_t uCurXcpt; /* 0xfc */
1528	/** Exception / interrupt recursion depth. */
1529	int8_t cXcptRecursions; /* 0xfb */
1530
1531	/** The next unused mapping index.
1532	* @todo try find room for this up with cActiveMappings. */
1533	uint8_t iNextMapping; /* 0xfd */
1534	uint8_t abAlignment7[1];
1535
1536	/** Bounce buffer storage.
1537	* This runs in parallel to aMemMappings and aMemBbMappings. */
1538	struct
1539	{
1540	uint8_t ab[512];
1541	} aBounceBuffers[3]; /* 0x100 LB 0x600 */
1542
1543
1544	/** Pointer set jump buffer - ring-3 context. */
1545	R3PTRTYPE(jmp_buf *) pJmpBufR3;
1546	/** Pointer set jump buffer - ring-0 context. */
1547	R0PTRTYPE(jmp_buf *) pJmpBufR0;
1548
1549	/** @todo Should move this near @a fCurXcpt later. */
1550	/** The CR2 for the current exception / interrupt. */
1551	uint64_t uCurXcptCr2;
1552	/** The error code for the current exception / interrupt. */
1553	uint32_t uCurXcptErr;
1554
1555	/** @name Statistics
1556	* @{ */
1557	/** The number of instructions we've executed. */
1558	uint32_t cInstructions;
1559	/** The number of potential exits. */
1560	uint32_t cPotentialExits;
1561	/** The number of bytes data or stack written (mostly for IEMExecOneEx).
1562	* This may contain uncommitted writes. */
1563	uint32_t cbWritten;
1564	/** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
1565	uint32_t cRetInstrNotImplemented;
1566	/** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
1567	uint32_t cRetAspectNotImplemented;
1568	/** Counts informational statuses returned (other than VINF_SUCCESS). */
1569	uint32_t cRetInfStatuses;
1570	/** Counts other error statuses returned. */
1571	uint32_t cRetErrStatuses;
1572	/** Number of times rcPassUp has been used. */
1573	uint32_t cRetPassUpStatus;
1574	/** Number of times RZ left with instruction commit pending for ring-3. */
1575	uint32_t cPendingCommit;
1576	/** Number of long jumps. */
1577	uint32_t cLongJumps;
1578	/** @} */
1579
1580	/** @name Target CPU information.
1581	* @{ */
1582	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
1583	/** The target CPU. */
1584	uint8_t uTargetCpu;
1585	#else
1586	uint8_t bTargetCpuPadding;
1587	#endif
1588	/** For selecting assembly works matching the target CPU EFLAGS behaviour, see
1589	* IEMTARGETCPU_EFL_BEHAVIOR_XXX for values, with the 1st entry for when no
1590	* native host support and the 2nd for when there is.
1591	*
1592	* The two values are typically indexed by a g_CpumHostFeatures bit.
1593	*
1594	* This is for instance used for the BSF & BSR instructions where AMD and
1595	* Intel CPUs produce different EFLAGS. */
1596	uint8_t aidxTargetCpuEflFlavour[2];
1597
1598	/** The CPU vendor. */
1599	CPUMCPUVENDOR enmCpuVendor;
1600	/** @} */
1601
1602	/** @name Host CPU information.
1603	* @{ */
1604	/** The CPU vendor. */
1605	CPUMCPUVENDOR enmHostCpuVendor;
1606	/** @} */
1607
1608	/** Counts RDMSR \#GP(0) LogRel(). */
1609	uint8_t cLogRelRdMsr;
1610	/** Counts WRMSR \#GP(0) LogRel(). */
1611	uint8_t cLogRelWrMsr;
1612	/** Alignment padding. */
1613	uint8_t abAlignment9[46];
1614
1615	/** @name Recompilation
1616	* @{ */
1617	/** Pointer to the current translation block.
1618	* This can either be one being executed or one being compiled. */
1619	R3PTRTYPE(PIEMTB) pCurTbR3;
1620	/** Fixed TB used for threaded recompilation.
1621	* This is allocated once with maxed-out sizes and re-used afterwards. */
1622	R3PTRTYPE(PIEMTB) pThrdCompileTbR3;
1623	/** Pointer to the ring-3 TB cache for this EMT. */
1624	R3PTRTYPE(PIEMTBCACHE) pTbCacheR3;
1625	/** The PC (RIP) at the start of pCurTbR3/pCurTbR0.
1626	* The TBs are based on physical addresses, so this is needed to correleated
1627	* RIP to opcode bytes stored in the TB (AMD-V / VT-x). */
1628	uint64_t uCurTbStartPc;
1629	/** Number of threaded TBs executed. */
1630	uint64_t cTbExecThreaded;
1631	/** Number of native TBs executed. */
1632	uint64_t cTbExecNative;
1633	/** Whether we need to check the opcode bytes for the current instruction.
1634	* This is set by a previous instruction if it modified memory or similar. */
1635	bool fTbCheckOpcodes;
1636	/** Indicates whether and how we just branched - IEMBRANCHED_F_XXX. */
1637	uint8_t fTbBranched;
1638	/** Set when GCPhysInstrBuf is updated because of a page crossing. */
1639	bool fTbCrossedPage;
1640	/** Whether to end the current TB. */
1641	bool fEndTb;
1642	/** Number of instructions before we need emit an IRQ check call again.
1643	* This helps making sure we don't execute too long w/o checking for
1644	* interrupts and immediately following instructions that may enable
1645	* interrupts (e.g. POPF, IRET, STI). With STI an additional hack is
1646	* required to make sure we check following the next instruction as well, see
1647	* fTbCurInstrIsSti. */
1648	uint8_t cInstrTillIrqCheck;
1649	/** Indicates that the current instruction is an STI. This is set by the
1650	* iemCImpl_sti code and subsequently cleared by the recompiler. */
1651	bool fTbCurInstrIsSti;
1652	/** The size of the IEMTB::pabOpcodes allocation in pThrdCompileTbR3. */
1653	uint16_t cbOpcodesAllocated;
1654	/** Spaced reserved for recompiler data / alignment. */
1655	bool afRecompilerStuff1[4];
1656	/** The virtual sync time at the last timer poll call. */
1657	uint32_t msRecompilerPollNow;
1658	/** The IEM_CIMPL_F_XXX mask for the current instruction. */
1659	uint32_t fTbCurInstr;
1660	/** The IEM_CIMPL_F_XXX mask for the previous instruction. */
1661	uint32_t fTbPrevInstr;
1662	/** Previous GCPhysInstrBuf value - only valid if fTbCrossedPage is set. */
1663	RTGCPHYS GCPhysInstrBufPrev;
1664	/** Copy of IEMCPU::GCPhysInstrBuf after decoding a branch instruction.
1665	* This is used together with fTbBranched and GCVirtTbBranchSrcBuf to determin
1666	* whether a branch instruction jumps to a new page or stays within the
1667	* current one. */
1668	RTGCPHYS GCPhysTbBranchSrcBuf;
1669	/** Copy of IEMCPU::uInstrBufPc after decoding a branch instruction. */
1670	uint64_t GCVirtTbBranchSrcBuf;
1671	/** Pointer to the ring-3 TB allocator for this EMT. */
1672	R3PTRTYPE(PIEMTBALLOCATOR) pTbAllocatorR3;
1673	/** Pointer to the ring-3 executable memory allocator for this EMT. */
1674	R3PTRTYPE(struct IEMEXECMEMALLOCATOR *) pExecMemAllocatorR3;
1675	/** Pointer to the native recompiler state for ring-3. */
1676	R3PTRTYPE(struct IEMRECOMPILERSTATE *) pNativeRecompilerStateR3;
1677	/** Alignment padding. */
1678	uint64_t auAlignment10[3];
1679	/** Statistics: Times TB execution was broken off before reaching the end. */
1680	STAMCOUNTER StatTbExecBreaks;
1681	/** Statistics: Times BltIn_CheckIrq breaks out of the TB. */
1682	STAMCOUNTER StatCheckIrqBreaks;
1683	/** Statistics: Times BltIn_CheckMode breaks out of the TB. */
1684	STAMCOUNTER StatCheckModeBreaks;
1685	/** Statistics: Times a post jump target check missed and had to find new TB. */
1686	STAMCOUNTER StatCheckBranchMisses;
1687	/** Statistics: Times a jump or page crossing required a TB with CS.LIM checking. */
1688	STAMCOUNTER StatCheckNeedCsLimChecking;
1689	/** Native TB statistics: Number of fully recompiled TBs. */
1690	STAMCOUNTER StatNativeFullyRecompiledTbs;
1691	/** Threaded TB statistics: Number of instructions per TB. */
1692	STAMPROFILE StatTbThreadedInstr;
1693	/** Threaded TB statistics: Number of calls per TB. */
1694	STAMPROFILE StatTbThreadedCalls;
1695	/** Native TB statistics: Native code size per TB. */
1696	STAMPROFILE StatTbNativeCode;
1697	/** Native TB statistics: Profiling native recompilation. */
1698	STAMPROFILE StatNativeRecompilation;
1699	/** Native TB statistics: Number of calls per TB that were recompiled properly. */
1700	STAMPROFILE StatNativeCallsRecompiled;
1701	/** Native TB statistics: Number of threaded calls per TB that weren't recompiled. */
1702	STAMPROFILE StatNativeCallsThreaded;
1703	/** @} */
1704
1705	/** Data TLB.
1706	* @remarks Must be 64-byte aligned. */
1707	IEMTLB DataTlb;
1708	/** Instruction TLB.
1709	* @remarks Must be 64-byte aligned. */
1710	IEMTLB CodeTlb;
1711
1712	/** Exception statistics. */
1713	STAMCOUNTER aStatXcpts[32];
1714	/** Interrupt statistics. */
1715	uint32_t aStatInts[256];
1716
1717	#if defined(VBOX_WITH_STATISTICS) && !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
1718	/** Instruction statistics for ring-0/raw-mode. */
1719	IEMINSTRSTATS StatsRZ;
1720	/** Instruction statistics for ring-3. */
1721	IEMINSTRSTATS StatsR3;
1722	#endif
1723	} IEMCPU;
1724	AssertCompileMemberOffset(IEMCPU, cActiveMappings, 0x4f);
1725	AssertCompileMemberAlignment(IEMCPU, aMemMappings, 16);
1726	AssertCompileMemberAlignment(IEMCPU, aMemMappingLocks, 16);
1727	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 64);
1728	AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
1729	AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
1730
1731	/** Pointer to the per-CPU IEM state. */
1732	typedef IEMCPU *PIEMCPU;
1733	/** Pointer to the const per-CPU IEM state. */
1734	typedef IEMCPU const *PCIEMCPU;
1735
1736
1737	/** @def IEM_GET_CTX
1738	* Gets the guest CPU context for the calling EMT.
1739	* @returns PCPUMCTX
1740	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1741	*/
1742	#define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
1743
1744	/** @def IEM_CTX_ASSERT
1745	* Asserts that the @a a_fExtrnMbz is present in the CPU context.
1746	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1747	* @param a_fExtrnMbz The mask of CPUMCTX_EXTRN_XXX flags that must be zero.
1748	*/
1749	#define IEM_CTX_ASSERT(a_pVCpu, a_fExtrnMbz) \
1750	AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
1751	("fExtrn=%#RX64 & fExtrnMbz=%#RX64 -> %#RX64\n", \
1752	(a_pVCpu)->cpum.GstCtx.fExtrn, (a_fExtrnMbz), (a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz) ))
1753
1754	/** @def IEM_CTX_IMPORT_RET
1755	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
1756	*
1757	* Will call the keep to import the bits as needed.
1758	*
1759	* Returns on import failure.
1760	*
1761	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1762	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
1763	*/
1764	#define IEM_CTX_IMPORT_RET(a_pVCpu, a_fExtrnImport) \
1765	do { \
1766	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
1767	{ /* likely */ } \
1768	else \
1769	{ \
1770	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
1771	AssertRCReturn(rcCtxImport, rcCtxImport); \
1772	} \
1773	} while (0)
1774
1775	/** @def IEM_CTX_IMPORT_NORET
1776	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
1777	*
1778	* Will call the keep to import the bits as needed.
1779	*
1780	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1781	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
1782	*/
1783	#define IEM_CTX_IMPORT_NORET(a_pVCpu, a_fExtrnImport) \
1784	do { \
1785	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
1786	{ /* likely */ } \
1787	else \
1788	{ \
1789	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
1790	AssertLogRelRC(rcCtxImport); \
1791	} \
1792	} while (0)
1793
1794	/** @def IEM_CTX_IMPORT_JMP
1795	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
1796	*
1797	* Will call the keep to import the bits as needed.
1798	*
1799	* Jumps on import failure.
1800	*
1801	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1802	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
1803	*/
1804	#define IEM_CTX_IMPORT_JMP(a_pVCpu, a_fExtrnImport) \
1805	do { \
1806	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
1807	{ /* likely */ } \
1808	else \
1809	{ \
1810	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
1811	AssertRCStmt(rcCtxImport, IEM_DO_LONGJMP(pVCpu, rcCtxImport)); \
1812	} \
1813	} while (0)
1814
1815
1816
1817	/** @def IEM_GET_TARGET_CPU
1818	* Gets the current IEMTARGETCPU value.
1819	* @returns IEMTARGETCPU value.
1820	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1821	*/
1822	#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
1823	# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
1824	#else
1825	# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
1826	#endif
1827
1828	/** @def IEM_GET_INSTR_LEN
1829	* Gets the instruction length. */
1830	#ifdef IEM_WITH_CODE_TLB
1831	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
1832	#else
1833	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
1834	#endif
1835
1836	/** @def IEM_TRY_SETJMP
1837	* Wrapper around setjmp / try, hiding all the ugly differences.
1838	*
1839	* @note Use with extreme care as this is a fragile macro.
1840	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
1841	* @param a_rcTarget The variable that should receive the status code in case
1842	* of a longjmp/throw.
1843	*/
1844	/** @def IEM_TRY_SETJMP_AGAIN
1845	* For when setjmp / try is used again in the same variable scope as a previous
1846	* IEM_TRY_SETJMP invocation.
1847	*/
1848	/** @def IEM_CATCH_LONGJMP_BEGIN
1849	* Start wrapper for catch / setjmp-else.
1850	*
1851	* This will set up a scope.
1852	*
1853	* @note Use with extreme care as this is a fragile macro.
1854	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
1855	* @param a_rcTarget The variable that should receive the status code in case
1856	* of a longjmp/throw.
1857	*/
1858	/** @def IEM_CATCH_LONGJMP_END
1859	* End wrapper for catch / setjmp-else.
1860	*
1861	* This will close the scope set up by IEM_CATCH_LONGJMP_BEGIN and clean up the
1862	* state.
1863	*
1864	* @note Use with extreme care as this is a fragile macro.
1865	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
1866	*/
1867	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
1868	# ifdef IEM_WITH_THROW_CATCH
1869	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
1870	a_rcTarget = VINF_SUCCESS; \
1871	try
1872	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
1873	IEM_TRY_SETJMP(a_pVCpu, a_rcTarget)
1874	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
1875	catch (int rcThrown) \
1876	{ \
1877	a_rcTarget = rcThrown
1878	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
1879	} \
1880	((void)0)
1881	# else /* !IEM_WITH_THROW_CATCH */
1882	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
1883	jmp_buf JmpBuf; \
1884	jmp_buf * volatile pSavedJmpBuf = (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf); \
1885	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
1886	if ((rcStrict = setjmp(JmpBuf)) == 0)
1887	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
1888	pSavedJmpBuf = (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf); \
1889	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
1890	if ((rcStrict = setjmp(JmpBuf)) == 0)
1891	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
1892	else \
1893	{ \
1894	((void)0)
1895	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
1896	} \
1897	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = pSavedJmpBuf
1898	# endif /* !IEM_WITH_THROW_CATCH */
1899	#endif /* IEM_WITH_SETJMP */
1900
1901
1902	/**
1903	* Shared per-VM IEM data.
1904	*/
1905	typedef struct IEM
1906	{
1907	/** The VMX APIC-access page handler type. */
1908	PGMPHYSHANDLERTYPE hVmxApicAccessPage;
1909	#ifndef VBOX_WITHOUT_CPUID_HOST_CALL
1910	/** Set if the CPUID host call functionality is enabled. */
1911	bool fCpuIdHostCall;
1912	#endif
1913	} IEM;
1914
1915
1916
1917	/** @name IEM_ACCESS_XXX - Access details.
1918	* @{ */
1919	#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
1920	#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
1921	#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
1922	#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
1923	#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
1924	#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
1925	#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
1926	#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
1927	#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
1928	#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
1929	/** The writes are partial, so if initialize the bounce buffer with the
1930	* orignal RAM content. */
1931	#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
1932	/** Used in aMemMappings to indicate that the entry is bounce buffered. */
1933	#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
1934	/** Bounce buffer with ring-3 write pending, first page. */
1935	#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
1936	/** Bounce buffer with ring-3 write pending, second page. */
1937	#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
1938	/** Not locked, accessed via the TLB. */
1939	#define IEM_ACCESS_NOT_LOCKED UINT32_C(0x00001000)
1940	/** Valid bit mask. */
1941	#define IEM_ACCESS_VALID_MASK UINT32_C(0x00001fff)
1942	/** Shift count for the TLB flags (upper word). */
1943	#define IEM_ACCESS_SHIFT_TLB_FLAGS 16
1944
1945	/** Read+write data alias. */
1946	#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
1947	/** Write data alias. */
1948	#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
1949	/** Read data alias. */
1950	#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_DATA)
1951	/** Instruction fetch alias. */
1952	#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_WHAT_CODE)
1953	/** Stack write alias. */
1954	#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
1955	/** Stack read alias. */
1956	#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_STACK)
1957	/** Stack read+write alias. */
1958	#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
1959	/** Read system table alias. */
1960	#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_SYS)
1961	/** Read+write system table alias. */
1962	#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_SYS)
1963	/** @} */
1964
1965	/** @name Prefix constants (IEMCPU::fPrefixes)
1966	* @{ */
1967	#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /*< CS segment prefix (0x2e). /
1968	#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /*< SS segment prefix (0x36). /
1969	#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /*< DS segment prefix (0x3e). /
1970	#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /*< ES segment prefix (0x26). /
1971	#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /*< FS segment prefix (0x64). /
1972	#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /*< GS segment prefix (0x65). /
1973	#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
1974
1975	#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /*< Operand size prefix (0x66). /
1976	#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /*< REX.W prefix (0x48-0x4f). /
1977	#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /*< Address size prefix (0x67). /
1978
1979	#define IEM_OP_PRF_LOCK RT_BIT_32(16) /*< Lock prefix (0xf0). /
1980	#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /*< Repeat-not-zero prefix (0xf2). /
1981	#define IEM_OP_PRF_REPZ RT_BIT_32(18) /*< Repeat-if-zero prefix (0xf3). /
1982
1983	#define IEM_OP_PRF_REX RT_BIT_32(24) /*< Any REX prefix (0x40-0x4f). /
1984	#define IEM_OP_PRF_REX_R RT_BIT_32(25) /*< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). /
1985	#define IEM_OP_PRF_REX_B RT_BIT_32(26) /*< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). /
1986	#define IEM_OP_PRF_REX_X RT_BIT_32(27) /*< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). /
1987	/** Mask with all the REX prefix flags.
1988	* This is generally for use when needing to undo the REX prefixes when they
1989	* are followed legacy prefixes and therefore does not immediately preceed
1990	* the first opcode byte.
1991	* For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
1992	#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX \| IEM_OP_PRF_REX_R \| IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X \| IEM_OP_PRF_SIZE_REX_W )
1993
1994	#define IEM_OP_PRF_VEX RT_BIT_32(28) /*< Indiciates VEX prefix. /
1995	#define IEM_OP_PRF_EVEX RT_BIT_32(29) /*< Indiciates EVEX prefix. /
1996	#define IEM_OP_PRF_XOP RT_BIT_32(30) /*< Indiciates XOP prefix. /
1997	/** @} */
1998
1999	/** @name IEMOPFORM_XXX - Opcode forms
2000	* @note These are ORed together with IEMOPHINT_XXX.
2001	* @{ */
2002	/** ModR/M: reg, r/m */
2003	#define IEMOPFORM_RM 0
2004	/** ModR/M: reg, r/m (register) */
2005	#define IEMOPFORM_RM_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
2006	/** ModR/M: reg, r/m (memory) */
2007	#define IEMOPFORM_RM_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
2008	/** ModR/M: reg, r/m */
2009	#define IEMOPFORM_RMI 1
2010	/** ModR/M: reg, r/m (register) */
2011	#define IEMOPFORM_RMI_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
2012	/** ModR/M: reg, r/m (memory) */
2013	#define IEMOPFORM_RMI_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
2014	/** ModR/M: r/m, reg */
2015	#define IEMOPFORM_MR 2
2016	/** ModR/M: r/m (register), reg */
2017	#define IEMOPFORM_MR_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
2018	/** ModR/M: r/m (memory), reg */
2019	#define IEMOPFORM_MR_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
2020	/** ModR/M: r/m, reg */
2021	#define IEMOPFORM_MRI 3
2022	/** ModR/M: r/m (register), reg */
2023	#define IEMOPFORM_MRI_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
2024	/** ModR/M: r/m (memory), reg */
2025	#define IEMOPFORM_MRI_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
2026	/** ModR/M: r/m only */
2027	#define IEMOPFORM_M 4
2028	/** ModR/M: r/m only (register). */
2029	#define IEMOPFORM_M_REG (IEMOPFORM_M \| IEMOPFORM_MOD3)
2030	/** ModR/M: r/m only (memory). */
2031	#define IEMOPFORM_M_MEM (IEMOPFORM_M \| IEMOPFORM_NOT_MOD3)
2032	/** ModR/M: reg only */
2033	#define IEMOPFORM_R 5
2034
2035	/** VEX+ModR/M: reg, r/m */
2036	#define IEMOPFORM_VEX_RM 8
2037	/** VEX+ModR/M: reg, r/m (register) */
2038	#define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM \| IEMOPFORM_MOD3)
2039	/** VEX+ModR/M: reg, r/m (memory) */
2040	#define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM \| IEMOPFORM_NOT_MOD3)
2041	/** VEX+ModR/M: r/m, reg */
2042	#define IEMOPFORM_VEX_MR 9
2043	/** VEX+ModR/M: r/m (register), reg */
2044	#define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR \| IEMOPFORM_MOD3)
2045	/** VEX+ModR/M: r/m (memory), reg */
2046	#define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR \| IEMOPFORM_NOT_MOD3)
2047	/** VEX+ModR/M: r/m only */
2048	#define IEMOPFORM_VEX_M 10
2049	/** VEX+ModR/M: r/m only (register). */
2050	#define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M \| IEMOPFORM_MOD3)
2051	/** VEX+ModR/M: r/m only (memory). */
2052	#define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M \| IEMOPFORM_NOT_MOD3)
2053	/** VEX+ModR/M: reg only */
2054	#define IEMOPFORM_VEX_R 11
2055	/** VEX+ModR/M: reg, vvvv, r/m */
2056	#define IEMOPFORM_VEX_RVM 12
2057	/** VEX+ModR/M: reg, vvvv, r/m (register). */
2058	#define IEMOPFORM_VEX_RVM_REG (IEMOPFORM_VEX_RVM \| IEMOPFORM_MOD3)
2059	/** VEX+ModR/M: reg, vvvv, r/m (memory). */
2060	#define IEMOPFORM_VEX_RVM_MEM (IEMOPFORM_VEX_RVM \| IEMOPFORM_NOT_MOD3)
2061	/** VEX+ModR/M: reg, r/m, vvvv */
2062	#define IEMOPFORM_VEX_RMV 13
2063	/** VEX+ModR/M: reg, r/m, vvvv (register). */
2064	#define IEMOPFORM_VEX_RMV_REG (IEMOPFORM_VEX_RMV \| IEMOPFORM_MOD3)
2065	/** VEX+ModR/M: reg, r/m, vvvv (memory). */
2066	#define IEMOPFORM_VEX_RMV_MEM (IEMOPFORM_VEX_RMV \| IEMOPFORM_NOT_MOD3)
2067	/** VEX+ModR/M: reg, r/m, imm8 */
2068	#define IEMOPFORM_VEX_RMI 14
2069	/** VEX+ModR/M: reg, r/m, imm8 (register). */
2070	#define IEMOPFORM_VEX_RMI_REG (IEMOPFORM_VEX_RMI \| IEMOPFORM_MOD3)
2071	/** VEX+ModR/M: reg, r/m, imm8 (memory). */
2072	#define IEMOPFORM_VEX_RMI_MEM (IEMOPFORM_VEX_RMI \| IEMOPFORM_NOT_MOD3)
2073	/** VEX+ModR/M: r/m, vvvv, reg */
2074	#define IEMOPFORM_VEX_MVR 15
2075	/** VEX+ModR/M: r/m, vvvv, reg (register) */
2076	#define IEMOPFORM_VEX_MVR_REG (IEMOPFORM_VEX_MVR \| IEMOPFORM_MOD3)
2077	/** VEX+ModR/M: r/m, vvvv, reg (memory) */
2078	#define IEMOPFORM_VEX_MVR_MEM (IEMOPFORM_VEX_MVR \| IEMOPFORM_NOT_MOD3)
2079	/** VEX+ModR/M+/n: vvvv, r/m */
2080	#define IEMOPFORM_VEX_VM 16
2081	/** VEX+ModR/M+/n: vvvv, r/m (register) */
2082	#define IEMOPFORM_VEX_VM_REG (IEMOPFORM_VEX_VM \| IEMOPFORM_MOD3)
2083	/** VEX+ModR/M+/n: vvvv, r/m (memory) */
2084	#define IEMOPFORM_VEX_VM_MEM (IEMOPFORM_VEX_VM \| IEMOPFORM_NOT_MOD3)
2085
2086	/** Fixed register instruction, no R/M. */
2087	#define IEMOPFORM_FIXED 32
2088
2089	/** The r/m is a register. */
2090	#define IEMOPFORM_MOD3 RT_BIT_32(8)
2091	/** The r/m is a memory access. */
2092	#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
2093	/** @} */
2094
2095	/** @name IEMOPHINT_XXX - Additional Opcode Hints
2096	* @note These are ORed together with IEMOPFORM_XXX.
2097	* @{ */
2098	/** Ignores the operand size prefix (66h). */
2099	#define IEMOPHINT_IGNORES_OZ_PFX RT_BIT_32(10)
2100	/** Ignores REX.W (aka WIG). */
2101	#define IEMOPHINT_IGNORES_REXW RT_BIT_32(11)
2102	/** Both the operand size prefixes (66h + REX.W) are ignored. */
2103	#define IEMOPHINT_IGNORES_OP_SIZES (IEMOPHINT_IGNORES_OZ_PFX \| IEMOPHINT_IGNORES_REXW)
2104	/** Allowed with the lock prefix. */
2105	#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
2106	/** The VEX.L value is ignored (aka LIG). */
2107	#define IEMOPHINT_VEX_L_IGNORED RT_BIT_32(12)
2108	/** The VEX.L value must be zero (i.e. 128-bit width only). */
2109	#define IEMOPHINT_VEX_L_ZERO RT_BIT_32(13)
2110	/** The VEX.V value must be zero. */
2111	#define IEMOPHINT_VEX_V_ZERO RT_BIT_32(14)
2112
2113	/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
2114	#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
2115	/** @} */
2116
2117	/**
2118	* Possible hardware task switch sources.
2119	*/
2120	typedef enum IEMTASKSWITCH
2121	{
2122	/** Task switch caused by an interrupt/exception. */
2123	IEMTASKSWITCH_INT_XCPT = 1,
2124	/** Task switch caused by a far CALL. */
2125	IEMTASKSWITCH_CALL,
2126	/** Task switch caused by a far JMP. */
2127	IEMTASKSWITCH_JUMP,
2128	/** Task switch caused by an IRET. */
2129	IEMTASKSWITCH_IRET
2130	} IEMTASKSWITCH;
2131	AssertCompileSize(IEMTASKSWITCH, 4);
2132
2133	/**
2134	* Possible CrX load (write) sources.
2135	*/
2136	typedef enum IEMACCESSCRX
2137	{
2138	/** CrX access caused by 'mov crX' instruction. */
2139	IEMACCESSCRX_MOV_CRX,
2140	/** CrX (CR0) write caused by 'lmsw' instruction. */
2141	IEMACCESSCRX_LMSW,
2142	/** CrX (CR0) write caused by 'clts' instruction. */
2143	IEMACCESSCRX_CLTS,
2144	/** CrX (CR0) read caused by 'smsw' instruction. */
2145	IEMACCESSCRX_SMSW
2146	} IEMACCESSCRX;
2147
2148	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2149	/** @name IEM_SLAT_FAIL_XXX - Second-level address translation failure information.
2150	*
2151	* These flags provide further context to SLAT page-walk failures that could not be
2152	* determined by PGM (e.g, PGM is not privy to memory access permissions).
2153	*
2154	* @{
2155	*/
2156	/** Translating a nested-guest linear address failed accessing a nested-guest
2157	* physical address. */
2158	# define IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR RT_BIT_32(0)
2159	/** Translating a nested-guest linear address failed accessing a
2160	* paging-structure entry or updating accessed/dirty bits. */
2161	# define IEM_SLAT_FAIL_LINEAR_TO_PAGE_TABLE RT_BIT_32(1)
2162	/** @} */
2163
2164	DECLCALLBACK(FNPGMPHYSHANDLER) iemVmxApicAccessPageHandler;
2165	# ifndef IN_RING3
2166	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) iemVmxApicAccessPagePfHandler;
2167	# endif
2168	#endif
2169
2170	/**
2171	* Indicates to the verifier that the given flag set is undefined.
2172	*
2173	* Can be invoked again to add more flags.
2174	*
2175	* This is a NOOP if the verifier isn't compiled in.
2176	*
2177	* @note We're temporarily keeping this until code is converted to new
2178	* disassembler style opcode handling.
2179	*/
2180	#define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
2181
2182
2183	/** @def IEM_DECL_IMPL_TYPE
2184	* For typedef'ing an instruction implementation function.
2185	*
2186	* @param a_RetType The return type.
2187	* @param a_Name The name of the type.
2188	* @param a_ArgList The argument list enclosed in parentheses.
2189	*/
2190
2191	/** @def IEM_DECL_IMPL_DEF
2192	* For defining an instruction implementation function.
2193	*
2194	* @param a_RetType The return type.
2195	* @param a_Name The name of the type.
2196	* @param a_ArgList The argument list enclosed in parentheses.
2197	*/
2198
2199	#if defined(__GNUC__) && defined(RT_ARCH_X86)
2200	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2201	__attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
2202	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2203	__attribute__((__fastcall__, __nothrow__)) DECL_HIDDEN_ONLY(a_RetType) a_Name a_ArgList
2204	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2205	__attribute__((__fastcall__, __nothrow__)) DECL_HIDDEN_ONLY(a_RetType) a_Name a_ArgList
2206
2207	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
2208	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2209	a_RetType (__fastcall a_Name) a_ArgList
2210	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2211	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
2212	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2213	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
2214
2215	#elif __cplusplus >= 201700 /* P0012R1 support */
2216	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2217	a_RetType (VBOXCALL a_Name) a_ArgList RT_NOEXCEPT
2218	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2219	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList RT_NOEXCEPT
2220	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2221	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList RT_NOEXCEPT
2222
2223	#else
2224	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2225	a_RetType (VBOXCALL a_Name) a_ArgList
2226	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2227	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList
2228	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2229	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList
2230
2231	#endif
2232
2233	/** Defined in IEMAllAImplC.cpp but also used by IEMAllAImplA.asm. */
2234	RT_C_DECLS_BEGIN
2235	extern uint8_t const g_afParity[256];
2236	RT_C_DECLS_END
2237
2238
2239	/** @name Arithmetic assignment operations on bytes (binary).
2240	* @{ */
2241	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU8, (uint8_t pu8Dst, uint8_t u8Src, uint32_t pEFlags));
2242	typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
2243	FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
2244	FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
2245	FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
2246	FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
2247	FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
2248	FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
2249	FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
2250	/** @} */
2251
2252	/** @name Arithmetic assignment operations on words (binary).
2253	* @{ */
2254	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU16, (uint16_t pu16Dst, uint16_t u16Src, uint32_t pEFlags));
2255	typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
2256	FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
2257	FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
2258	FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
2259	FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
2260	FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
2261	FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
2262	FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
2263	/** @} */
2264
2265	/** @name Arithmetic assignment operations on double words (binary).
2266	* @{ */
2267	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU32, (uint32_t pu32Dst, uint32_t u32Src, uint32_t pEFlags));
2268	typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
2269	FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
2270	FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
2271	FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
2272	FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
2273	FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
2274	FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
2275	FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
2276	FNIEMAIMPLBINU32 iemAImpl_blsi_u32, iemAImpl_blsi_u32_fallback;
2277	FNIEMAIMPLBINU32 iemAImpl_blsr_u32, iemAImpl_blsr_u32_fallback;
2278	FNIEMAIMPLBINU32 iemAImpl_blsmsk_u32, iemAImpl_blsmsk_u32_fallback;
2279	/** @} */
2280
2281	/** @name Arithmetic assignment operations on quad words (binary).
2282	* @{ */
2283	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU64, (uint64_t pu64Dst, uint64_t u64Src, uint32_t pEFlags));
2284	typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
2285	FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
2286	FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
2287	FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
2288	FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
2289	FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
2290	FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
2291	FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
2292	FNIEMAIMPLBINU64 iemAImpl_blsi_u64, iemAImpl_blsi_u64_fallback;
2293	FNIEMAIMPLBINU64 iemAImpl_blsr_u64, iemAImpl_blsr_u64_fallback;
2294	FNIEMAIMPLBINU64 iemAImpl_blsmsk_u64, iemAImpl_blsmsk_u64_fallback;
2295	/** @} */
2296
2297	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINROU8,(uint8_t const pu8Dst, uint8_t u8Src, uint32_t pEFlags));
2298	typedef FNIEMAIMPLBINROU8 *PFNIEMAIMPLBINROU8;
2299	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINROU16,(uint16_t const pu16Dst, uint16_t u16Src, uint32_t pEFlags));
2300	typedef FNIEMAIMPLBINROU16 *PFNIEMAIMPLBINROU16;
2301	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINROU32,(uint32_t const pu32Dst, uint32_t u32Src, uint32_t pEFlags));
2302	typedef FNIEMAIMPLBINROU32 *PFNIEMAIMPLBINROU32;
2303	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINROU64,(uint64_t const pu64Dst, uint64_t u64Src, uint32_t pEFlags));
2304	typedef FNIEMAIMPLBINROU64 *PFNIEMAIMPLBINROU64;
2305
2306	/** @name Compare operations (thrown in with the binary ops).
2307	* @{ */
2308	FNIEMAIMPLBINROU8 iemAImpl_cmp_u8;
2309	FNIEMAIMPLBINROU16 iemAImpl_cmp_u16;
2310	FNIEMAIMPLBINROU32 iemAImpl_cmp_u32;
2311	FNIEMAIMPLBINROU64 iemAImpl_cmp_u64;
2312	/** @} */
2313
2314	/** @name Test operations (thrown in with the binary ops).
2315	* @{ */
2316	FNIEMAIMPLBINROU8 iemAImpl_test_u8;
2317	FNIEMAIMPLBINROU16 iemAImpl_test_u16;
2318	FNIEMAIMPLBINROU32 iemAImpl_test_u32;
2319	FNIEMAIMPLBINROU64 iemAImpl_test_u64;
2320	/** @} */
2321
2322	/** @name Bit operations operations (thrown in with the binary ops).
2323	* @{ */
2324	FNIEMAIMPLBINROU16 iemAImpl_bt_u16;
2325	FNIEMAIMPLBINROU32 iemAImpl_bt_u32;
2326	FNIEMAIMPLBINROU64 iemAImpl_bt_u64;
2327	FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
2328	FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
2329	FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
2330	FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
2331	FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
2332	FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
2333	FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
2334	FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
2335	FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
2336	/** @} */
2337
2338	/** @name Arithmetic three operand operations on double words (binary).
2339	* @{ */
2340	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32, (uint32_t pu32Dst, uint32_t u32Src1, uint32_t u32Src2, uint32_t pEFlags));
2341	typedef FNIEMAIMPLBINVEXU32 *PFNIEMAIMPLBINVEXU32;
2342	FNIEMAIMPLBINVEXU32 iemAImpl_andn_u32, iemAImpl_andn_u32_fallback;
2343	FNIEMAIMPLBINVEXU32 iemAImpl_bextr_u32, iemAImpl_bextr_u32_fallback;
2344	FNIEMAIMPLBINVEXU32 iemAImpl_bzhi_u32, iemAImpl_bzhi_u32_fallback;
2345	/** @} */
2346
2347	/** @name Arithmetic three operand operations on quad words (binary).
2348	* @{ */
2349	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64, (uint64_t pu64Dst, uint64_t u64Src1, uint64_t u64Src2, uint32_t pEFlags));
2350	typedef FNIEMAIMPLBINVEXU64 *PFNIEMAIMPLBINVEXU64;
2351	FNIEMAIMPLBINVEXU64 iemAImpl_andn_u64, iemAImpl_andn_u64_fallback;
2352	FNIEMAIMPLBINVEXU64 iemAImpl_bextr_u64, iemAImpl_bextr_u64_fallback;
2353	FNIEMAIMPLBINVEXU64 iemAImpl_bzhi_u64, iemAImpl_bzhi_u64_fallback;
2354	/** @} */
2355
2356	/** @name Arithmetic three operand operations on double words w/o EFLAGS (binary).
2357	* @{ */
2358	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32NOEFL, (uint32_t *pu32Dst, uint32_t u32Src1, uint32_t u32Src2));
2359	typedef FNIEMAIMPLBINVEXU32NOEFL *PFNIEMAIMPLBINVEXU32NOEFL;
2360	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pdep_u32, iemAImpl_pdep_u32_fallback;
2361	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pext_u32, iemAImpl_pext_u32_fallback;
2362	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_sarx_u32, iemAImpl_sarx_u32_fallback;
2363	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shlx_u32, iemAImpl_shlx_u32_fallback;
2364	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shrx_u32, iemAImpl_shrx_u32_fallback;
2365	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_rorx_u32;
2366	/** @} */
2367
2368	/** @name Arithmetic three operand operations on quad words w/o EFLAGS (binary).
2369	* @{ */
2370	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64NOEFL, (uint64_t *pu64Dst, uint64_t u64Src1, uint64_t u64Src2));
2371	typedef FNIEMAIMPLBINVEXU64NOEFL *PFNIEMAIMPLBINVEXU64NOEFL;
2372	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pdep_u64, iemAImpl_pdep_u64_fallback;
2373	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pext_u64, iemAImpl_pext_u64_fallback;
2374	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_sarx_u64, iemAImpl_sarx_u64_fallback;
2375	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shlx_u64, iemAImpl_shlx_u64_fallback;
2376	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shrx_u64, iemAImpl_shrx_u64_fallback;
2377	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_rorx_u64;
2378	/** @} */
2379
2380	/** @name MULX 32-bit and 64-bit.
2381	* @{ */
2382	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU32, (uint32_t puDst1, uint32_t puDst2, uint32_t uSrc1, uint32_t uSrc2));
2383	typedef FNIEMAIMPLMULXVEXU32 *PFNIEMAIMPLMULXVEXU32;
2384	FNIEMAIMPLMULXVEXU32 iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback;
2385
2386	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU64, (uint64_t puDst1, uint64_t puDst2, uint64_t uSrc1, uint64_t uSrc2));
2387	typedef FNIEMAIMPLMULXVEXU64 *PFNIEMAIMPLMULXVEXU64;
2388	FNIEMAIMPLMULXVEXU64 iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback;
2389	/** @} */
2390
2391
2392	/** @name Exchange memory with register operations.
2393	* @{ */
2394	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_locked, (uint8_t pu8Mem, uint8_t pu8Reg));
2395	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_locked,(uint16_t pu16Mem, uint16_t pu16Reg));
2396	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_locked,(uint32_t pu32Mem, uint32_t pu32Reg));
2397	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_locked,(uint64_t pu64Mem, uint64_t pu64Reg));
2398	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_unlocked, (uint8_t pu8Mem, uint8_t pu8Reg));
2399	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_unlocked,(uint16_t pu16Mem, uint16_t pu16Reg));
2400	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_unlocked,(uint32_t pu32Mem, uint32_t pu32Reg));
2401	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_unlocked,(uint64_t pu64Mem, uint64_t pu64Reg));
2402	/** @} */
2403
2404	/** @name Exchange and add operations.
2405	* @{ */
2406	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
2407	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
2408	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
2409	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
2410	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
2411	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
2412	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
2413	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
2414	/** @} */
2415
2416	/** @name Compare and exchange.
2417	* @{ */
2418	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
2419	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
2420	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
2421	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
2422	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
2423	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
2424	#if ARCH_BITS == 32
2425	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
2426	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
2427	#else
2428	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
2429	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
2430	#endif
2431	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
2432	uint32_t *pEFlags));
2433	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
2434	uint32_t *pEFlags));
2435	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
2436	uint32_t *pEFlags));
2437	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
2438	uint32_t *pEFlags));
2439	#ifndef RT_ARCH_ARM64
2440	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
2441	PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
2442	#endif
2443	/** @} */
2444
2445	/** @name Memory ordering
2446	* @{ */
2447	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
2448	typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
2449	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
2450	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
2451	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
2452	#ifndef RT_ARCH_ARM64
2453	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
2454	#endif
2455	/** @} */
2456
2457	/** @name Double precision shifts
2458	* @{ */
2459	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t pEFlags));
2460	typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
2461	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t pEFlags));
2462	typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
2463	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t pEFlags));
2464	typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
2465	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16, iemAImpl_shld_u16_amd, iemAImpl_shld_u16_intel;
2466	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32, iemAImpl_shld_u32_amd, iemAImpl_shld_u32_intel;
2467	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64, iemAImpl_shld_u64_amd, iemAImpl_shld_u64_intel;
2468	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16, iemAImpl_shrd_u16_amd, iemAImpl_shrd_u16_intel;
2469	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32, iemAImpl_shrd_u32_amd, iemAImpl_shrd_u32_intel;
2470	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64, iemAImpl_shrd_u64_amd, iemAImpl_shrd_u64_intel;
2471	/** @} */
2472
2473
2474	/** @name Bit search operations (thrown in with the binary ops).
2475	* @{ */
2476	FNIEMAIMPLBINU16 iemAImpl_bsf_u16, iemAImpl_bsf_u16_amd, iemAImpl_bsf_u16_intel;
2477	FNIEMAIMPLBINU32 iemAImpl_bsf_u32, iemAImpl_bsf_u32_amd, iemAImpl_bsf_u32_intel;
2478	FNIEMAIMPLBINU64 iemAImpl_bsf_u64, iemAImpl_bsf_u64_amd, iemAImpl_bsf_u64_intel;
2479	FNIEMAIMPLBINU16 iemAImpl_bsr_u16, iemAImpl_bsr_u16_amd, iemAImpl_bsr_u16_intel;
2480	FNIEMAIMPLBINU32 iemAImpl_bsr_u32, iemAImpl_bsr_u32_amd, iemAImpl_bsr_u32_intel;
2481	FNIEMAIMPLBINU64 iemAImpl_bsr_u64, iemAImpl_bsr_u64_amd, iemAImpl_bsr_u64_intel;
2482	FNIEMAIMPLBINU16 iemAImpl_lzcnt_u16, iemAImpl_lzcnt_u16_amd, iemAImpl_lzcnt_u16_intel;
2483	FNIEMAIMPLBINU32 iemAImpl_lzcnt_u32, iemAImpl_lzcnt_u32_amd, iemAImpl_lzcnt_u32_intel;
2484	FNIEMAIMPLBINU64 iemAImpl_lzcnt_u64, iemAImpl_lzcnt_u64_amd, iemAImpl_lzcnt_u64_intel;
2485	FNIEMAIMPLBINU16 iemAImpl_tzcnt_u16, iemAImpl_tzcnt_u16_amd, iemAImpl_tzcnt_u16_intel;
2486	FNIEMAIMPLBINU32 iemAImpl_tzcnt_u32, iemAImpl_tzcnt_u32_amd, iemAImpl_tzcnt_u32_intel;
2487	FNIEMAIMPLBINU64 iemAImpl_tzcnt_u64, iemAImpl_tzcnt_u64_amd, iemAImpl_tzcnt_u64_intel;
2488	FNIEMAIMPLBINU16 iemAImpl_popcnt_u16, iemAImpl_popcnt_u16_fallback;
2489	FNIEMAIMPLBINU32 iemAImpl_popcnt_u32, iemAImpl_popcnt_u32_fallback;
2490	FNIEMAIMPLBINU64 iemAImpl_popcnt_u64, iemAImpl_popcnt_u64_fallback;
2491	/** @} */
2492
2493	/** @name Signed multiplication operations (thrown in with the binary ops).
2494	* @{ */
2495	FNIEMAIMPLBINU16 iemAImpl_imul_two_u16, iemAImpl_imul_two_u16_amd, iemAImpl_imul_two_u16_intel;
2496	FNIEMAIMPLBINU32 iemAImpl_imul_two_u32, iemAImpl_imul_two_u32_amd, iemAImpl_imul_two_u32_intel;
2497	FNIEMAIMPLBINU64 iemAImpl_imul_two_u64, iemAImpl_imul_two_u64_amd, iemAImpl_imul_two_u64_intel;
2498	/** @} */
2499
2500	/** @name Arithmetic assignment operations on bytes (unary).
2501	* @{ */
2502	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t pu8Dst, uint32_t pEFlags));
2503	typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
2504	FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
2505	FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
2506	FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
2507	FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
2508	/** @} */
2509
2510	/** @name Arithmetic assignment operations on words (unary).
2511	* @{ */
2512	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t pu16Dst, uint32_t pEFlags));
2513	typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
2514	FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
2515	FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
2516	FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
2517	FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
2518	/** @} */
2519
2520	/** @name Arithmetic assignment operations on double words (unary).
2521	* @{ */
2522	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t pu32Dst, uint32_t pEFlags));
2523	typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
2524	FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
2525	FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
2526	FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
2527	FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
2528	/** @} */
2529
2530	/** @name Arithmetic assignment operations on quad words (unary).
2531	* @{ */
2532	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t pu64Dst, uint32_t pEFlags));
2533	typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
2534	FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
2535	FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
2536	FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
2537	FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
2538	/** @} */
2539
2540
2541	/** @name Shift operations on bytes (Group 2).
2542	* @{ */
2543	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU8,(uint8_t pu8Dst, uint8_t cShift, uint32_t pEFlags));
2544	typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
2545	FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8, iemAImpl_rol_u8_amd, iemAImpl_rol_u8_intel;
2546	FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8, iemAImpl_ror_u8_amd, iemAImpl_ror_u8_intel;
2547	FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8, iemAImpl_rcl_u8_amd, iemAImpl_rcl_u8_intel;
2548	FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8, iemAImpl_rcr_u8_amd, iemAImpl_rcr_u8_intel;
2549	FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8, iemAImpl_shl_u8_amd, iemAImpl_shl_u8_intel;
2550	FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8, iemAImpl_shr_u8_amd, iemAImpl_shr_u8_intel;
2551	FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8, iemAImpl_sar_u8_amd, iemAImpl_sar_u8_intel;
2552	/** @} */
2553
2554	/** @name Shift operations on words (Group 2).
2555	* @{ */
2556	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU16,(uint16_t pu16Dst, uint8_t cShift, uint32_t pEFlags));
2557	typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
2558	FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16, iemAImpl_rol_u16_amd, iemAImpl_rol_u16_intel;
2559	FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16, iemAImpl_ror_u16_amd, iemAImpl_ror_u16_intel;
2560	FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16, iemAImpl_rcl_u16_amd, iemAImpl_rcl_u16_intel;
2561	FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16, iemAImpl_rcr_u16_amd, iemAImpl_rcr_u16_intel;
2562	FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16, iemAImpl_shl_u16_amd, iemAImpl_shl_u16_intel;
2563	FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16, iemAImpl_shr_u16_amd, iemAImpl_shr_u16_intel;
2564	FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16, iemAImpl_sar_u16_amd, iemAImpl_sar_u16_intel;
2565	/** @} */
2566
2567	/** @name Shift operations on double words (Group 2).
2568	* @{ */
2569	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU32,(uint32_t pu32Dst, uint8_t cShift, uint32_t pEFlags));
2570	typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
2571	FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32, iemAImpl_rol_u32_amd, iemAImpl_rol_u32_intel;
2572	FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32, iemAImpl_ror_u32_amd, iemAImpl_ror_u32_intel;
2573	FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32, iemAImpl_rcl_u32_amd, iemAImpl_rcl_u32_intel;
2574	FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32, iemAImpl_rcr_u32_amd, iemAImpl_rcr_u32_intel;
2575	FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32, iemAImpl_shl_u32_amd, iemAImpl_shl_u32_intel;
2576	FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32, iemAImpl_shr_u32_amd, iemAImpl_shr_u32_intel;
2577	FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32, iemAImpl_sar_u32_amd, iemAImpl_sar_u32_intel;
2578	/** @} */
2579
2580	/** @name Shift operations on words (Group 2).
2581	* @{ */
2582	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU64,(uint64_t pu64Dst, uint8_t cShift, uint32_t pEFlags));
2583	typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
2584	FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64, iemAImpl_rol_u64_amd, iemAImpl_rol_u64_intel;
2585	FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64, iemAImpl_ror_u64_amd, iemAImpl_ror_u64_intel;
2586	FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64, iemAImpl_rcl_u64_amd, iemAImpl_rcl_u64_intel;
2587	FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64, iemAImpl_rcr_u64_amd, iemAImpl_rcr_u64_intel;
2588	FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64, iemAImpl_shl_u64_amd, iemAImpl_shl_u64_intel;
2589	FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64, iemAImpl_shr_u64_amd, iemAImpl_shr_u64_intel;
2590	FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64, iemAImpl_sar_u64_amd, iemAImpl_sar_u64_intel;
2591	/** @} */
2592
2593	/** @name Multiplication and division operations.
2594	* @{ */
2595	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t pu16AX, uint8_t u8FactorDivisor, uint32_t pEFlags));
2596	typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
2597	FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_mul_u8_amd, iemAImpl_mul_u8_intel;
2598	FNIEMAIMPLMULDIVU8 iemAImpl_imul_u8, iemAImpl_imul_u8_amd, iemAImpl_imul_u8_intel;
2599	FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_div_u8_amd, iemAImpl_div_u8_intel;
2600	FNIEMAIMPLMULDIVU8 iemAImpl_idiv_u8, iemAImpl_idiv_u8_amd, iemAImpl_idiv_u8_intel;
2601
2602	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t pu16AX, uint16_t pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
2603	typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
2604	FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_mul_u16_amd, iemAImpl_mul_u16_intel;
2605	FNIEMAIMPLMULDIVU16 iemAImpl_imul_u16, iemAImpl_imul_u16_amd, iemAImpl_imul_u16_intel;
2606	FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_div_u16_amd, iemAImpl_div_u16_intel;
2607	FNIEMAIMPLMULDIVU16 iemAImpl_idiv_u16, iemAImpl_idiv_u16_amd, iemAImpl_idiv_u16_intel;
2608
2609	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t pu32EAX, uint32_t pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
2610	typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
2611	FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_mul_u32_amd, iemAImpl_mul_u32_intel;
2612	FNIEMAIMPLMULDIVU32 iemAImpl_imul_u32, iemAImpl_imul_u32_amd, iemAImpl_imul_u32_intel;
2613	FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_div_u32_amd, iemAImpl_div_u32_intel;
2614	FNIEMAIMPLMULDIVU32 iemAImpl_idiv_u32, iemAImpl_idiv_u32_amd, iemAImpl_idiv_u32_intel;
2615
2616	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t pu64RAX, uint64_t pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
2617	typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
2618	FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_mul_u64_amd, iemAImpl_mul_u64_intel;
2619	FNIEMAIMPLMULDIVU64 iemAImpl_imul_u64, iemAImpl_imul_u64_amd, iemAImpl_imul_u64_intel;
2620	FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_div_u64_amd, iemAImpl_div_u64_intel;
2621	FNIEMAIMPLMULDIVU64 iemAImpl_idiv_u64, iemAImpl_idiv_u64_amd, iemAImpl_idiv_u64_intel;
2622	/** @} */
2623
2624	/** @name Byte Swap.
2625	* @{ */
2626	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t pu32Dst)); / Yes, 32-bit register access. */
2627	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
2628	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
2629	/** @} */
2630
2631	/** @name Misc.
2632	* @{ */
2633	FNIEMAIMPLBINU16 iemAImpl_arpl;
2634	/** @} */
2635
2636	/** @name RDRAND and RDSEED
2637	* @{ */
2638	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU16,(uint16_t puDst, uint32_t pEFlags));
2639	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU32,(uint32_t puDst, uint32_t pEFlags));
2640	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU64,(uint64_t puDst, uint32_t pEFlags));
2641	typedef FNIEMAIMPLRDRANDSEEDU16 *PFNIEMAIMPLRDRANDSEEDU16;
2642	typedef FNIEMAIMPLRDRANDSEEDU32 *PFNIEMAIMPLRDRANDSEEDU32;
2643	typedef FNIEMAIMPLRDRANDSEEDU64 *PFNIEMAIMPLRDRANDSEEDU64;
2644
2645	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdrand_u16, iemAImpl_rdrand_u16_fallback;
2646	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdrand_u32, iemAImpl_rdrand_u32_fallback;
2647	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdrand_u64, iemAImpl_rdrand_u64_fallback;
2648	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdseed_u16, iemAImpl_rdseed_u16_fallback;
2649	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdseed_u32, iemAImpl_rdseed_u32_fallback;
2650	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdseed_u64, iemAImpl_rdseed_u64_fallback;
2651	/** @} */
2652
2653	/** @name ADOX and ADCX
2654	* @{ */
2655	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLADXU32,(uint32_t puDst, uint32_t pfEFlags, uint32_t uSrc));
2656	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLADXU64,(uint64_t puDst, uint32_t pfEFlags, uint64_t uSrc));
2657	typedef FNIEMAIMPLADXU32 *PFNIEMAIMPLADXU32;
2658	typedef FNIEMAIMPLADXU64 *PFNIEMAIMPLADXU64;
2659
2660	FNIEMAIMPLADXU32 iemAImpl_adcx_u32, iemAImpl_adcx_u32_fallback;
2661	FNIEMAIMPLADXU64 iemAImpl_adcx_u64, iemAImpl_adcx_u64_fallback;
2662	FNIEMAIMPLADXU32 iemAImpl_adox_u32, iemAImpl_adox_u32_fallback;
2663	FNIEMAIMPLADXU64 iemAImpl_adox_u64, iemAImpl_adox_u64_fallback;
2664	/** @} */
2665
2666	/** @name FPU operations taking a 32-bit float argument
2667	* @{ */
2668	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2669	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
2670	typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
2671
2672	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2673	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
2674	typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
2675
2676	FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
2677	FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
2678	FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
2679	FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
2680	FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
2681	FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
2682	FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
2683
2684	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
2685	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2686	PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
2687	/** @} */
2688
2689	/** @name FPU operations taking a 64-bit float argument
2690	* @{ */
2691	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2692	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
2693	typedef FNIEMAIMPLFPUR64FSW *PFNIEMAIMPLFPUR64FSW;
2694
2695	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2696	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
2697	typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
2698
2699	FNIEMAIMPLFPUR64FSW iemAImpl_fcom_r80_by_r64;
2700	FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
2701	FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
2702	FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
2703	FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
2704	FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
2705	FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
2706
2707	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
2708	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2709	PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
2710	/** @} */
2711
2712	/** @name FPU operations taking a 80-bit float argument
2713	* @{ */
2714	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2715	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
2716	typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
2717	FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
2718	FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
2719	FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
2720	FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
2721	FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
2722	FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
2723	FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
2724	FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
2725	FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
2726
2727	FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80, iemAImpl_fpatan_r80_by_r80_amd, iemAImpl_fpatan_r80_by_r80_intel;
2728	FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80, iemAImpl_fyl2x_r80_by_r80_amd, iemAImpl_fyl2x_r80_by_r80_intel;
2729	FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80, iemAImpl_fyl2xp1_r80_by_r80_amd, iemAImpl_fyl2xp1_r80_by_r80_intel;
2730
2731	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2732	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
2733	typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
2734	FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
2735	FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
2736
2737	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
2738	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
2739	typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
2740	FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
2741	FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
2742
2743	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
2744	typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
2745	FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
2746	FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
2747	FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80, iemAImpl_f2xm1_r80_amd, iemAImpl_f2xm1_r80_intel;
2748	FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
2749	FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
2750	FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80, iemAImpl_fsin_r80_amd, iemAImpl_fsin_r80_intel;
2751	FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80, iemAImpl_fcos_r80_amd, iemAImpl_fcos_r80_intel;
2752
2753	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
2754	typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
2755	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
2756	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
2757
2758	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
2759	typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
2760	FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
2761	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
2762	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
2763	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
2764	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
2765	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
2766	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
2767
2768	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
2769	PCRTFLOAT80U pr80Val));
2770	typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
2771	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80, iemAImpl_fptan_r80_r80_amd, iemAImpl_fptan_r80_r80_intel;
2772	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
2773	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80, iemAImpl_fsincos_r80_r80_amd, iemAImpl_fsincos_r80_r80_intel;
2774
2775	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
2776	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2777	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
2778
2779	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_d80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTPBCD80U pd80Val));
2780	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_d80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2781	PRTPBCD80U pd80Dst, PCRTFLOAT80U pr80Src));
2782
2783	/** @} */
2784
2785	/** @name FPU operations taking a 16-bit signed integer argument
2786	* @{ */
2787	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2788	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
2789	typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
2790	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI16,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
2791	int16_t *pi16Dst, PCRTFLOAT80U pr80Src));
2792	typedef FNIEMAIMPLFPUSTR80TOI16 *PFNIEMAIMPLFPUSTR80TOI16;
2793
2794	FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
2795	FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
2796	FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
2797	FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
2798	FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
2799	FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
2800
2801	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2802	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
2803	typedef FNIEMAIMPLFPUI16FSW *PFNIEMAIMPLFPUI16FSW;
2804	FNIEMAIMPLFPUI16FSW iemAImpl_ficom_r80_by_i16;
2805
2806	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
2807	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fist_r80_to_i16;
2808	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fistt_r80_to_i16, iemAImpl_fistt_r80_to_i16_amd, iemAImpl_fistt_r80_to_i16_intel;
2809	/** @} */
2810
2811	/** @name FPU operations taking a 32-bit signed integer argument
2812	* @{ */
2813	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2814	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
2815	typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
2816	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI32,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
2817	int32_t *pi32Dst, PCRTFLOAT80U pr80Src));
2818	typedef FNIEMAIMPLFPUSTR80TOI32 *PFNIEMAIMPLFPUSTR80TOI32;
2819
2820	FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
2821	FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
2822	FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
2823	FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
2824	FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
2825	FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
2826
2827	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2828	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
2829	typedef FNIEMAIMPLFPUI32FSW *PFNIEMAIMPLFPUI32FSW;
2830	FNIEMAIMPLFPUI32FSW iemAImpl_ficom_r80_by_i32;
2831
2832	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
2833	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fist_r80_to_i32;
2834	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fistt_r80_to_i32;
2835	/** @} */
2836
2837	/** @name FPU operations taking a 64-bit signed integer argument
2838	* @{ */
2839	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI64,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
2840	int64_t *pi64Dst, PCRTFLOAT80U pr80Src));
2841	typedef FNIEMAIMPLFPUSTR80TOI64 *PFNIEMAIMPLFPUSTR80TOI64;
2842
2843	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
2844	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fist_r80_to_i64;
2845	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fistt_r80_to_i64;
2846	/** @} */
2847
2848
2849	/** Temporary type representing a 256-bit vector register. */
2850	typedef struct { uint64_t au64[4]; } IEMVMM256;
2851	/** Temporary type pointing to a 256-bit vector register. */
2852	typedef IEMVMM256 *PIEMVMM256;
2853	/** Temporary type pointing to a const 256-bit vector register. */
2854	typedef IEMVMM256 *PCIEMVMM256;
2855
2856
2857	/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
2858	* @{ */
2859	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t puDst, uint64_t const puSrc));
2860	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
2861	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U128,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
2862	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
2863	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U128,(PX86XSAVEAREA pExtState, PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
2864	typedef FNIEMAIMPLMEDIAF3U128 *PFNIEMAIMPLMEDIAF3U128;
2865	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U256,(PX86XSAVEAREA pExtState, PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
2866	typedef FNIEMAIMPLMEDIAF3U256 *PFNIEMAIMPLMEDIAF3U256;
2867	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U64,(uint64_t puDst, uint64_t const puSrc));
2868	typedef FNIEMAIMPLMEDIAOPTF2U64 *PFNIEMAIMPLMEDIAOPTF2U64;
2869	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128,(PRTUINT128U puDst, PCRTUINT128U puSrc));
2870	typedef FNIEMAIMPLMEDIAOPTF2U128 *PFNIEMAIMPLMEDIAOPTF2U128;
2871	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
2872	typedef FNIEMAIMPLMEDIAOPTF3U128 *PFNIEMAIMPLMEDIAOPTF3U128;
2873	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
2874	typedef FNIEMAIMPLMEDIAOPTF3U256 *PFNIEMAIMPLMEDIAOPTF3U256;
2875	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256,(PRTUINT256U puDst, PCRTUINT256U puSrc));
2876	typedef FNIEMAIMPLMEDIAOPTF2U256 *PFNIEMAIMPLMEDIAOPTF2U256;
2877	FNIEMAIMPLMEDIAF2U64 iemAImpl_pshufb_u64, iemAImpl_pshufb_u64_fallback;
2878	FNIEMAIMPLMEDIAF2U64 iemAImpl_pand_u64, iemAImpl_pandn_u64, iemAImpl_por_u64, iemAImpl_pxor_u64;
2879	FNIEMAIMPLMEDIAF2U64 iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
2880	FNIEMAIMPLMEDIAF2U64 iemAImpl_pcmpgtb_u64, iemAImpl_pcmpgtw_u64, iemAImpl_pcmpgtd_u64;
2881	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddb_u64, iemAImpl_paddsb_u64, iemAImpl_paddusb_u64;
2882	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddw_u64, iemAImpl_paddsw_u64, iemAImpl_paddusw_u64;
2883	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddd_u64;
2884	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddq_u64;
2885	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubb_u64, iemAImpl_psubsb_u64, iemAImpl_psubusb_u64;
2886	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubw_u64, iemAImpl_psubsw_u64, iemAImpl_psubusw_u64;
2887	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubd_u64;
2888	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubq_u64;
2889	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmaddwd_u64;
2890	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmullw_u64, iemAImpl_pmulhw_u64;
2891	FNIEMAIMPLMEDIAF2U64 iemAImpl_pminub_u64, iemAImpl_pmaxub_u64;
2892	FNIEMAIMPLMEDIAF2U64 iemAImpl_pminsw_u64, iemAImpl_pmaxsw_u64;
2893	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsb_u64, iemAImpl_pabsb_u64_fallback;
2894	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsw_u64, iemAImpl_pabsw_u64_fallback;
2895	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsd_u64, iemAImpl_pabsd_u64_fallback;
2896	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignb_u64, iemAImpl_psignb_u64_fallback;
2897	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignw_u64, iemAImpl_psignw_u64_fallback;
2898	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignd_u64, iemAImpl_psignd_u64_fallback;
2899	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddw_u64, iemAImpl_phaddw_u64_fallback;
2900	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddd_u64, iemAImpl_phaddd_u64_fallback;
2901	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubw_u64, iemAImpl_phsubw_u64_fallback;
2902	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubd_u64, iemAImpl_phsubd_u64_fallback;
2903	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddsw_u64, iemAImpl_phaddsw_u64_fallback;
2904	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubsw_u64, iemAImpl_phsubsw_u64_fallback;
2905	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmaddubsw_u64, iemAImpl_pmaddubsw_u64_fallback;
2906	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmulhrsw_u64, iemAImpl_pmulhrsw_u64_fallback;
2907	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmuludq_u64;
2908	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllw_u64, iemAImpl_psrlw_u64, iemAImpl_psraw_u64;
2909	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pslld_u64, iemAImpl_psrld_u64, iemAImpl_psrad_u64;
2910	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllq_u64, iemAImpl_psrlq_u64;
2911	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packsswb_u64, iemAImpl_packuswb_u64;
2912	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packssdw_u64;
2913	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhuw_u64;
2914	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pavgb_u64, iemAImpl_pavgw_u64;
2915	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psadbw_u64;
2916
2917	FNIEMAIMPLMEDIAF2U128 iemAImpl_pshufb_u128, iemAImpl_pshufb_u128_fallback;
2918	FNIEMAIMPLMEDIAF2U128 iemAImpl_pand_u128, iemAImpl_pandn_u128, iemAImpl_por_u128, iemAImpl_pxor_u128;
2919	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
2920	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpeqq_u128, iemAImpl_pcmpeqq_u128_fallback;
2921	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpgtb_u128, iemAImpl_pcmpgtw_u128, iemAImpl_pcmpgtd_u128;
2922	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpgtq_u128, iemAImpl_pcmpgtq_u128_fallback;
2923	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddb_u128, iemAImpl_paddsb_u128, iemAImpl_paddusb_u128;
2924	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddw_u128, iemAImpl_paddsw_u128, iemAImpl_paddusw_u128;
2925	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddd_u128;
2926	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddq_u128;
2927	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubb_u128, iemAImpl_psubsb_u128, iemAImpl_psubusb_u128;
2928	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubw_u128, iemAImpl_psubsw_u128, iemAImpl_psubusw_u128;
2929	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubd_u128;
2930	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubq_u128;
2931	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmullw_u128, iemAImpl_pmullw_u128_fallback;
2932	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulhw_u128;
2933	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulld_u128, iemAImpl_pmulld_u128_fallback;
2934	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaddwd_u128;
2935	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminub_u128;
2936	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminud_u128, iemAImpl_pminud_u128_fallback;
2937	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminuw_u128, iemAImpl_pminuw_u128_fallback;
2938	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsb_u128, iemAImpl_pminsb_u128_fallback;
2939	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsd_u128, iemAImpl_pminsd_u128_fallback;
2940	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsw_u128, iemAImpl_pminsw_u128_fallback;
2941	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxub_u128;
2942	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxud_u128, iemAImpl_pmaxud_u128_fallback;
2943	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxuw_u128, iemAImpl_pmaxuw_u128_fallback;
2944	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsb_u128, iemAImpl_pmaxsb_u128_fallback;
2945	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsw_u128;
2946	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsd_u128, iemAImpl_pmaxsd_u128_fallback;
2947	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsb_u128, iemAImpl_pabsb_u128_fallback;
2948	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsw_u128, iemAImpl_pabsw_u128_fallback;
2949	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsd_u128, iemAImpl_pabsd_u128_fallback;
2950	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignb_u128, iemAImpl_psignb_u128_fallback;
2951	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignw_u128, iemAImpl_psignw_u128_fallback;
2952	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignd_u128, iemAImpl_psignd_u128_fallback;
2953	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddw_u128, iemAImpl_phaddw_u128_fallback;
2954	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddd_u128, iemAImpl_phaddd_u128_fallback;
2955	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubw_u128, iemAImpl_phsubw_u128_fallback;
2956	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubd_u128, iemAImpl_phsubd_u128_fallback;
2957	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddsw_u128, iemAImpl_phaddsw_u128_fallback;
2958	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubsw_u128, iemAImpl_phsubsw_u128_fallback;
2959	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaddubsw_u128, iemAImpl_pmaddubsw_u128_fallback;
2960	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulhrsw_u128, iemAImpl_pmulhrsw_u128_fallback;
2961	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmuludq_u128;
2962	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packsswb_u128, iemAImpl_packuswb_u128;
2963	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packssdw_u128, iemAImpl_packusdw_u128;
2964	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllw_u128, iemAImpl_psrlw_u128, iemAImpl_psraw_u128;
2965	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pslld_u128, iemAImpl_psrld_u128, iemAImpl_psrad_u128;
2966	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllq_u128, iemAImpl_psrlq_u128;
2967	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhuw_u128;
2968	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pavgb_u128, iemAImpl_pavgw_u128;
2969	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psadbw_u128;
2970	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuldq_u128, iemAImpl_pmuldq_u128_fallback;
2971	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpcklps_u128, iemAImpl_unpcklpd_u128;
2972	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpckhps_u128, iemAImpl_unpckhpd_u128;
2973	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phminposuw_u128, iemAImpl_phminposuw_u128_fallback;
2974
2975	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpshufb_u128, iemAImpl_vpshufb_u128_fallback;
2976	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpand_u128, iemAImpl_vpand_u128_fallback;
2977	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpandn_u128, iemAImpl_vpandn_u128_fallback;
2978	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpor_u128, iemAImpl_vpor_u128_fallback;
2979	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpxor_u128, iemAImpl_vpxor_u128_fallback;
2980	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqb_u128, iemAImpl_vpcmpeqb_u128_fallback;
2981	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqw_u128, iemAImpl_vpcmpeqw_u128_fallback;
2982	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqd_u128, iemAImpl_vpcmpeqd_u128_fallback;
2983	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqq_u128, iemAImpl_vpcmpeqq_u128_fallback;
2984	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtb_u128, iemAImpl_vpcmpgtb_u128_fallback;
2985	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtw_u128, iemAImpl_vpcmpgtw_u128_fallback;
2986	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtd_u128, iemAImpl_vpcmpgtd_u128_fallback;
2987	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtq_u128, iemAImpl_vpcmpgtq_u128_fallback;
2988	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddb_u128, iemAImpl_vpaddb_u128_fallback;
2989	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddw_u128, iemAImpl_vpaddw_u128_fallback;
2990	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddd_u128, iemAImpl_vpaddd_u128_fallback;
2991	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddq_u128, iemAImpl_vpaddq_u128_fallback;
2992	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubb_u128, iemAImpl_vpsubb_u128_fallback;
2993	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubw_u128, iemAImpl_vpsubw_u128_fallback;
2994	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubd_u128, iemAImpl_vpsubd_u128_fallback;
2995	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubq_u128, iemAImpl_vpsubq_u128_fallback;
2996	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminub_u128, iemAImpl_vpminub_u128_fallback;
2997	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminuw_u128, iemAImpl_vpminuw_u128_fallback;
2998	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminud_u128, iemAImpl_vpminud_u128_fallback;
2999	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsb_u128, iemAImpl_vpminsb_u128_fallback;
3000	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsw_u128, iemAImpl_vpminsw_u128_fallback;
3001	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsd_u128, iemAImpl_vpminsd_u128_fallback;
3002	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxub_u128, iemAImpl_vpmaxub_u128_fallback;
3003	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxuw_u128, iemAImpl_vpmaxuw_u128_fallback;
3004	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxud_u128, iemAImpl_vpmaxud_u128_fallback;
3005	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsb_u128, iemAImpl_vpmaxsb_u128_fallback;
3006	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsw_u128, iemAImpl_vpmaxsw_u128_fallback;
3007	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsd_u128, iemAImpl_vpmaxsd_u128_fallback;
3008	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpacksswb_u128, iemAImpl_vpacksswb_u128_fallback;
3009	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackssdw_u128, iemAImpl_vpackssdw_u128_fallback;
3010	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackuswb_u128, iemAImpl_vpackuswb_u128_fallback;
3011	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackusdw_u128, iemAImpl_vpackusdw_u128_fallback;
3012	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmullw_u128, iemAImpl_vpmullw_u128_fallback;
3013	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulld_u128, iemAImpl_vpmulld_u128_fallback;
3014	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhw_u128, iemAImpl_vpmulhw_u128_fallback;
3015	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhuw_u128, iemAImpl_vpmulhuw_u128_fallback;
3016	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgb_u128, iemAImpl_vpavgb_u128_fallback;
3017	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgw_u128, iemAImpl_vpavgw_u128_fallback;
3018	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignb_u128, iemAImpl_vpsignb_u128_fallback;
3019	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignw_u128, iemAImpl_vpsignw_u128_fallback;
3020	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignd_u128, iemAImpl_vpsignd_u128_fallback;
3021	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddw_u128, iemAImpl_vphaddw_u128_fallback;
3022	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddd_u128, iemAImpl_vphaddd_u128_fallback;
3023	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubw_u128, iemAImpl_vphsubw_u128_fallback;
3024	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubd_u128, iemAImpl_vphsubd_u128_fallback;
3025	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddsw_u128, iemAImpl_vphaddsw_u128_fallback;
3026	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubsw_u128, iemAImpl_vphsubsw_u128_fallback;
3027	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddubsw_u128, iemAImpl_vpmaddubsw_u128_fallback;
3028	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhrsw_u128, iemAImpl_vpmulhrsw_u128_fallback;
3029	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsadbw_u128, iemAImpl_vpsadbw_u128_fallback;
3030	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuldq_u128, iemAImpl_vpmuldq_u128_fallback;
3031	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuludq_u128, iemAImpl_vpmuludq_u128_fallback;
3032	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsb_u128, iemAImpl_vpsubsb_u128_fallback;
3033	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsw_u128, iemAImpl_vpsubsw_u128_fallback;
3034	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusb_u128, iemAImpl_vpsubusb_u128_fallback;
3035	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusw_u128, iemAImpl_vpsubusw_u128_fallback;
3036	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusb_u128, iemAImpl_vpaddusb_u128_fallback;
3037	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusw_u128, iemAImpl_vpaddusw_u128_fallback;
3038	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsb_u128, iemAImpl_vpaddsb_u128_fallback;
3039	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsw_u128, iemAImpl_vpaddsw_u128_fallback;
3040
3041	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsb_u128, iemAImpl_vpabsb_u128_fallback;
3042	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsw_u128, iemAImpl_vpabsd_u128_fallback;
3043	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsd_u128, iemAImpl_vpabsw_u128_fallback;
3044	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vphminposuw_u128, iemAImpl_vphminposuw_u128_fallback;
3045
3046	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpshufb_u256, iemAImpl_vpshufb_u256_fallback;
3047	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpand_u256, iemAImpl_vpand_u256_fallback;
3048	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpandn_u256, iemAImpl_vpandn_u256_fallback;
3049	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpor_u256, iemAImpl_vpor_u256_fallback;
3050	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpxor_u256, iemAImpl_vpxor_u256_fallback;
3051	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqb_u256, iemAImpl_vpcmpeqb_u256_fallback;
3052	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqw_u256, iemAImpl_vpcmpeqw_u256_fallback;
3053	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqd_u256, iemAImpl_vpcmpeqd_u256_fallback;
3054	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqq_u256, iemAImpl_vpcmpeqq_u256_fallback;
3055	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtb_u256, iemAImpl_vpcmpgtb_u256_fallback;
3056	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtw_u256, iemAImpl_vpcmpgtw_u256_fallback;
3057	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtd_u256, iemAImpl_vpcmpgtd_u256_fallback;
3058	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtq_u256, iemAImpl_vpcmpgtq_u256_fallback;
3059	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddb_u256, iemAImpl_vpaddb_u256_fallback;
3060	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddw_u256, iemAImpl_vpaddw_u256_fallback;
3061	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddd_u256, iemAImpl_vpaddd_u256_fallback;
3062	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddq_u256, iemAImpl_vpaddq_u256_fallback;
3063	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubb_u256, iemAImpl_vpsubb_u256_fallback;
3064	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubw_u256, iemAImpl_vpsubw_u256_fallback;
3065	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubd_u256, iemAImpl_vpsubd_u256_fallback;
3066	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubq_u256, iemAImpl_vpsubq_u256_fallback;
3067	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminub_u256, iemAImpl_vpminub_u256_fallback;
3068	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminuw_u256, iemAImpl_vpminuw_u256_fallback;
3069	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminud_u256, iemAImpl_vpminud_u256_fallback;
3070	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsb_u256, iemAImpl_vpminsb_u256_fallback;
3071	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsw_u256, iemAImpl_vpminsw_u256_fallback;
3072	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsd_u256, iemAImpl_vpminsd_u256_fallback;
3073	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxub_u256, iemAImpl_vpmaxub_u256_fallback;
3074	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxuw_u256, iemAImpl_vpmaxuw_u256_fallback;
3075	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxud_u256, iemAImpl_vpmaxud_u256_fallback;
3076	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsb_u256, iemAImpl_vpmaxsb_u256_fallback;
3077	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsw_u256, iemAImpl_vpmaxsw_u256_fallback;
3078	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsd_u256, iemAImpl_vpmaxsd_u256_fallback;
3079	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpacksswb_u256, iemAImpl_vpacksswb_u256_fallback;
3080	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackssdw_u256, iemAImpl_vpackssdw_u256_fallback;
3081	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackuswb_u256, iemAImpl_vpackuswb_u256_fallback;
3082	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackusdw_u256, iemAImpl_vpackusdw_u256_fallback;
3083	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmullw_u256, iemAImpl_vpmullw_u256_fallback;
3084	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulld_u256, iemAImpl_vpmulld_u256_fallback;
3085	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhw_u256, iemAImpl_vpmulhw_u256_fallback;
3086	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhuw_u256, iemAImpl_vpmulhuw_u256_fallback;
3087	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgb_u256, iemAImpl_vpavgb_u256_fallback;
3088	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgw_u256, iemAImpl_vpavgw_u256_fallback;
3089	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignb_u256, iemAImpl_vpsignb_u256_fallback;
3090	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignw_u256, iemAImpl_vpsignw_u256_fallback;
3091	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignd_u256, iemAImpl_vpsignd_u256_fallback;
3092	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddw_u256, iemAImpl_vphaddw_u256_fallback;
3093	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddd_u256, iemAImpl_vphaddd_u256_fallback;
3094	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubw_u256, iemAImpl_vphsubw_u256_fallback;
3095	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubd_u256, iemAImpl_vphsubd_u256_fallback;
3096	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddsw_u256, iemAImpl_vphaddsw_u256_fallback;
3097	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubsw_u256, iemAImpl_vphsubsw_u256_fallback;
3098	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddubsw_u256, iemAImpl_vpmaddubsw_u256_fallback;
3099	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhrsw_u256, iemAImpl_vpmulhrsw_u256_fallback;
3100	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsadbw_u256, iemAImpl_vpsadbw_u256_fallback;
3101	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuldq_u256, iemAImpl_vpmuldq_u256_fallback;
3102	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuludq_u256, iemAImpl_vpmuludq_u256_fallback;
3103	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsb_u256, iemAImpl_vpsubsb_u256_fallback;
3104	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsw_u256, iemAImpl_vpsubsw_u256_fallback;
3105	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusb_u256, iemAImpl_vpsubusb_u256_fallback;
3106	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusw_u256, iemAImpl_vpsubusw_u256_fallback;
3107	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusb_u256, iemAImpl_vpaddusb_u256_fallback;
3108	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusw_u256, iemAImpl_vpaddusw_u256_fallback;
3109	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsb_u256, iemAImpl_vpaddsb_u256_fallback;
3110	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsw_u256, iemAImpl_vpaddsw_u256_fallback;
3111
3112	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsb_u256, iemAImpl_vpabsb_u256_fallback;
3113	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsw_u256, iemAImpl_vpabsw_u256_fallback;
3114	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsd_u256, iemAImpl_vpabsd_u256_fallback;
3115	/** @} */
3116
3117	/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
3118	* @{ */
3119	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
3120	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
3121	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpcklbw_u128, iemAImpl_vpunpcklbw_u128_fallback,
3122	iemAImpl_vpunpcklwd_u128, iemAImpl_vpunpcklwd_u128_fallback,
3123	iemAImpl_vpunpckldq_u128, iemAImpl_vpunpckldq_u128_fallback,
3124	iemAImpl_vpunpcklqdq_u128, iemAImpl_vpunpcklqdq_u128_fallback,
3125	iemAImpl_vunpcklps_u128, iemAImpl_vunpcklps_u128_fallback,
3126	iemAImpl_vunpcklpd_u128, iemAImpl_vunpcklpd_u128_fallback,
3127	iemAImpl_vunpckhps_u128, iemAImpl_vunpckhps_u128_fallback,
3128	iemAImpl_vunpckhpd_u128, iemAImpl_vunpckhpd_u128_fallback;
3129
3130	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpcklbw_u256, iemAImpl_vpunpcklbw_u256_fallback,
3131	iemAImpl_vpunpcklwd_u256, iemAImpl_vpunpcklwd_u256_fallback,
3132	iemAImpl_vpunpckldq_u256, iemAImpl_vpunpckldq_u256_fallback,
3133	iemAImpl_vpunpcklqdq_u256, iemAImpl_vpunpcklqdq_u256_fallback,
3134	iemAImpl_vunpcklps_u256, iemAImpl_vunpcklps_u256_fallback,
3135	iemAImpl_vunpcklpd_u256, iemAImpl_vunpcklpd_u256_fallback,
3136	iemAImpl_vunpckhps_u256, iemAImpl_vunpckhps_u256_fallback,
3137	iemAImpl_vunpckhpd_u256, iemAImpl_vunpckhpd_u256_fallback;
3138	/** @} */
3139
3140	/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
3141	* @{ */
3142	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
3143	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
3144	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpckhbw_u128, iemAImpl_vpunpckhbw_u128_fallback,
3145	iemAImpl_vpunpckhwd_u128, iemAImpl_vpunpckhwd_u128_fallback,
3146	iemAImpl_vpunpckhdq_u128, iemAImpl_vpunpckhdq_u128_fallback,
3147	iemAImpl_vpunpckhqdq_u128, iemAImpl_vpunpckhqdq_u128_fallback;
3148	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpckhbw_u256, iemAImpl_vpunpckhbw_u256_fallback,
3149	iemAImpl_vpunpckhwd_u256, iemAImpl_vpunpckhwd_u256_fallback,
3150	iemAImpl_vpunpckhdq_u256, iemAImpl_vpunpckhdq_u256_fallback,
3151	iemAImpl_vpunpckhqdq_u256, iemAImpl_vpunpckhqdq_u256_fallback;
3152	/** @} */
3153
3154	/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
3155	* @{ */
3156	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3157	typedef FNIEMAIMPLMEDIAPSHUFU128 *PFNIEMAIMPLMEDIAPSHUFU128;
3158	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
3159	typedef FNIEMAIMPLMEDIAPSHUFU256 *PFNIEMAIMPLMEDIAPSHUFU256;
3160	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw_u64,(uint64_t puDst, uint64_t const puSrc, uint8_t bEvil));
3161	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_pshufhw_u128, iemAImpl_pshuflw_u128, iemAImpl_pshufd_u128;
3162	#ifndef IEM_WITHOUT_ASSEMBLY
3163	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256, iemAImpl_vpshuflw_u256, iemAImpl_vpshufd_u256;
3164	#endif
3165	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256_fallback, iemAImpl_vpshuflw_u256_fallback, iemAImpl_vpshufd_u256_fallback;
3166	/** @} */
3167
3168	/** @name Media (SSE/MMX/AVX) operation: Shift Immediate Stuff (evil)
3169	* @{ */
3170	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU64,(uint64_t *puDst, uint8_t bShift));
3171	typedef FNIEMAIMPLMEDIAPSHIFTU64 *PFNIEMAIMPLMEDIAPSHIFTU64;
3172	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU128,(PRTUINT128U puDst, uint8_t bShift));
3173	typedef FNIEMAIMPLMEDIAPSHIFTU128 *PFNIEMAIMPLMEDIAPSHIFTU128;
3174	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU256,(PRTUINT256U puDst, uint8_t bShift));
3175	typedef FNIEMAIMPLMEDIAPSHIFTU256 *PFNIEMAIMPLMEDIAPSHIFTU256;
3176	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psllw_imm_u64, iemAImpl_pslld_imm_u64, iemAImpl_psllq_imm_u64;
3177	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psrlw_imm_u64, iemAImpl_psrld_imm_u64, iemAImpl_psrlq_imm_u64;
3178	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psraw_imm_u64, iemAImpl_psrad_imm_u64;
3179	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psllw_imm_u128, iemAImpl_pslld_imm_u128, iemAImpl_psllq_imm_u128;
3180	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psrlw_imm_u128, iemAImpl_psrld_imm_u128, iemAImpl_psrlq_imm_u128;
3181	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psraw_imm_u128, iemAImpl_psrad_imm_u128;
3182	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_pslldq_imm_u128, iemAImpl_psrldq_imm_u128;
3183	/** @} */
3184
3185	/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
3186	* @{ */
3187	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(uint64_t pu64Dst, uint64_t const puSrc));
3188	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(uint64_t *pu64Dst, PCRTUINT128U puSrc));
3189	#ifndef IEM_WITHOUT_ASSEMBLY
3190	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
3191	#endif
3192	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256_fallback,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
3193	/** @} */
3194
3195	/** @name Media (SSE/MMX/AVX) operations: Variable Blend Packed Bytes/R32/R64.
3196	* @{ */
3197	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puMask));
3198	typedef FNIEMAIMPLBLENDU128 *PFNIEMAIMPLBLENDU128;
3199	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, PCRTUINT128U puMask));
3200	typedef FNIEMAIMPLAVXBLENDU128 *PFNIEMAIMPLAVXBLENDU128;
3201	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, PCRTUINT256U puMask));
3202	typedef FNIEMAIMPLAVXBLENDU256 *PFNIEMAIMPLAVXBLENDU256;
3203
3204	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128;
3205	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128_fallback;
3206	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128;
3207	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128_fallback;
3208	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256;
3209	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256_fallback;
3210
3211	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128;
3212	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128_fallback;
3213	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128;
3214	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128_fallback;
3215	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256;
3216	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256_fallback;
3217
3218	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128;
3219	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128_fallback;
3220	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128;
3221	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128_fallback;
3222	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256;
3223	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256_fallback;
3224	/** @} */
3225
3226
3227	/** @name Media (SSE/MMX/AVX) operation: Sort this later
3228	* @{ */
3229	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
3230	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
3231	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovshdup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
3232	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovshdup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
3233	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
3234	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
3235
3236	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3237	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3238	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3239	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3240	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3241
3242	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3243	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3244	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3245	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3246	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3247
3248	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3249	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3250	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
3251	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3252	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3253
3254	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3255	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3256	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3257	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3258	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3259
3260	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3261	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3262	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3263	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3264	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3265
3266	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3267	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3268	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3269	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3270	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3271
3272	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3273	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3274	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3275	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3276	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3277
3278	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3279	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3280	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3281	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3282	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3283
3284	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3285	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3286	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
3287	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3288	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3289
3290	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3291	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3292	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3293	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3294	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3295
3296	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3297	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3298	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3299	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3300	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3301
3302	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3303	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3304	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3305	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3306	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3307
3308	IEM_DECL_IMPL_DEF(void, iemAImpl_shufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3309	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3310	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3311	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3312	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3313
3314	IEM_DECL_IMPL_DEF(void, iemAImpl_shufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3315	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3316	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3317	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3318	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3319
3320	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
3321	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64_fallback,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
3322
3323	IEM_DECL_IMPL_DEF(void, iemAImpl_pinsrw_u64,(uint64_t *pu64Dst, uint16_t u16Src, uint8_t bEvil));
3324	IEM_DECL_IMPL_DEF(void, iemAImpl_pinsrw_u128,(PRTUINT128U puDst, uint16_t u16Src, uint8_t bEvil));
3325	IEM_DECL_IMPL_DEF(void, iemAImpl_vpinsrw_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint16_t u16Src, uint8_t bEvil));
3326	IEM_DECL_IMPL_DEF(void, iemAImpl_vpinsrw_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint16_t u16Src, uint8_t bEvil));
3327
3328	IEM_DECL_IMPL_DEF(void, iemAImpl_pextrw_u64,(uint16_t *pu16Dst, uint64_t u64Src, uint8_t bEvil));
3329	IEM_DECL_IMPL_DEF(void, iemAImpl_pextrw_u128,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
3330	IEM_DECL_IMPL_DEF(void, iemAImpl_vpextrw_u128,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
3331	IEM_DECL_IMPL_DEF(void, iemAImpl_vpextrw_u128_fallback,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
3332
3333	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3334	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3335	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3336	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3337	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3338
3339	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3340	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3341	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3342	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3343	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3344
3345
3346	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3347	typedef FNIEMAIMPLMEDIAOPTF2U128IMM8 *PFNIEMAIMPLMEDIAOPTF2U128IMM8;
3348	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3349	typedef FNIEMAIMPLMEDIAOPTF3U128IMM8 *PFNIEMAIMPLMEDIAOPTF3U128IMM8;
3350	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3351	typedef FNIEMAIMPLMEDIAOPTF3U256IMM8 *PFNIEMAIMPLMEDIAOPTF3U256IMM8;
3352
3353	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_palignr_u128, iemAImpl_palignr_u128_fallback;
3354	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pblendw_u128, iemAImpl_pblendw_u128_fallback;
3355	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendps_u128, iemAImpl_blendps_u128_fallback;
3356	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendpd_u128, iemAImpl_blendpd_u128_fallback;
3357
3358	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpalignr_u128, iemAImpl_vpalignr_u128_fallback;
3359	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendw_u128, iemAImpl_vpblendw_u128_fallback;
3360	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendps_u128, iemAImpl_vblendps_u128_fallback;
3361	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendpd_u128, iemAImpl_vblendpd_u128_fallback;
3362
3363	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpalignr_u256, iemAImpl_vpalignr_u256_fallback;
3364	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendw_u256, iemAImpl_vpblendw_u256_fallback;
3365	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendps_u256, iemAImpl_vblendps_u256_fallback;
3366	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendpd_u256, iemAImpl_vblendpd_u256_fallback;
3367	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2i128_u256, iemAImpl_vperm2i128_u256_fallback;
3368	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2f128_u256, iemAImpl_vperm2f128_u256_fallback;
3369
3370	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesimc_u128, iemAImpl_aesimc_u128_fallback;
3371	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenc_u128, iemAImpl_aesenc_u128_fallback;
3372	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenclast_u128, iemAImpl_aesenclast_u128_fallback;
3373	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdec_u128, iemAImpl_aesdec_u128_fallback;
3374	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdeclast_u128, iemAImpl_aesdeclast_u128_fallback;
3375
3376	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesimc_u128, iemAImpl_vaesimc_u128_fallback;
3377	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenc_u128, iemAImpl_vaesenc_u128_fallback;
3378	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenclast_u128, iemAImpl_vaesenclast_u128_fallback;
3379	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdec_u128, iemAImpl_vaesdec_u128_fallback;
3380	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdeclast_u128, iemAImpl_vaesdeclast_u128_fallback;
3381
3382	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_aeskeygenassist_u128, iemAImpl_aeskeygenassist_u128_fallback;
3383
3384	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vaeskeygenassist_u128, iemAImpl_vaeskeygenassist_u128_fallback;
3385
3386	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1nexte_u128, iemAImpl_sha1nexte_u128_fallback;
3387	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg1_u128, iemAImpl_sha1msg1_u128_fallback;
3388	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg2_u128, iemAImpl_sha1msg2_u128_fallback;
3389	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg1_u128, iemAImpl_sha256msg1_u128_fallback;
3390	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg2_u128, iemAImpl_sha256msg2_u128_fallback;
3391	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_sha1rnds4_u128, iemAImpl_sha1rnds4_u128_fallback;
3392	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
3393	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
3394
3395	typedef struct IEMPCMPISTRXSRC
3396	{
3397	RTUINT128U uSrc1;
3398	RTUINT128U uSrc2;
3399	} IEMPCMPISTRXSRC;
3400	typedef IEMPCMPISTRXSRC *PIEMPCMPISTRXSRC;
3401	typedef const IEMPCMPISTRXSRC *PCIEMPCMPISTRXSRC;
3402
3403	typedef struct IEMPCMPESTRXSRC
3404	{
3405	RTUINT128U uSrc1;
3406	RTUINT128U uSrc2;
3407	uint64_t u64Rax;
3408	uint64_t u64Rdx;
3409	} IEMPCMPESTRXSRC;
3410	typedef IEMPCMPESTRXSRC *PIEMPCMPESTRXSRC;
3411	typedef const IEMPCMPESTRXSRC *PCIEMPCMPESTRXSRC;
3412
3413	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPISTRIU128IMM8,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
3414	typedef FNIEMAIMPLPCMPISTRIU128IMM8 *PFNIEMAIMPLPCMPISTRIU128IMM8;
3415	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRIU128IMM8,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
3416	typedef FNIEMAIMPLPCMPESTRIU128IMM8 *PFNIEMAIMPLPCMPESTRIU128IMM8;
3417
3418	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPISTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
3419	typedef FNIEMAIMPLPCMPISTRMU128IMM8 *PFNIEMAIMPLPCMPISTRMU128IMM8;
3420	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
3421	typedef FNIEMAIMPLPCMPESTRMU128IMM8 *PFNIEMAIMPLPCMPESTRMU128IMM8;
3422
3423	FNIEMAIMPLPCMPISTRIU128IMM8 iemAImpl_pcmpistri_u128, iemAImpl_pcmpistri_u128_fallback;
3424	FNIEMAIMPLPCMPESTRIU128IMM8 iemAImpl_pcmpestri_u128, iemAImpl_pcmpestri_u128_fallback;
3425	FNIEMAIMPLPCMPISTRMU128IMM8 iemAImpl_pcmpistrm_u128, iemAImpl_pcmpistrm_u128_fallback;
3426	FNIEMAIMPLPCMPESTRMU128IMM8 iemAImpl_pcmpestrm_u128, iemAImpl_pcmpestrm_u128_fallback;
3427
3428	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pclmulqdq_u128, iemAImpl_pclmulqdq_u128_fallback;
3429	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpclmulqdq_u128, iemAImpl_vpclmulqdq_u128_fallback;
3430
3431	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_mpsadbw_u128, iemAImpl_mpsadbw_u128_fallback;
3432	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vmpsadbw_u128, iemAImpl_vmpsadbw_u128_fallback;
3433	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vmpsadbw_u256, iemAImpl_vmpsadbw_u256_fallback;
3434	/** @} */
3435
3436	/** @name Media Odds and Ends
3437	* @{ */
3438	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U8,(uint32_t *puDst, uint8_t uSrc));
3439	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U16,(uint32_t *puDst, uint16_t uSrc));
3440	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U32,(uint32_t *puDst, uint32_t uSrc));
3441	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U64,(uint32_t *puDst, uint64_t uSrc));
3442	FNIEMAIMPLCR32U8 iemAImpl_crc32_u8, iemAImpl_crc32_u8_fallback;
3443	FNIEMAIMPLCR32U16 iemAImpl_crc32_u16, iemAImpl_crc32_u16_fallback;
3444	FNIEMAIMPLCR32U32 iemAImpl_crc32_u32, iemAImpl_crc32_u32_fallback;
3445	FNIEMAIMPLCR32U64 iemAImpl_crc32_u64, iemAImpl_crc32_u64_fallback;
3446
3447	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL128,(PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint32_t *pEFlags));
3448	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL256,(PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint32_t *pEFlags));
3449	FNIEMAIMPLF2EFL128 iemAImpl_ptest_u128;
3450	FNIEMAIMPLF2EFL256 iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback;
3451
3452	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I32U64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int32_t pi32Dst, const uint64_t pu64Src)); / pu64Src is a double precision floating point. */
3453	typedef FNIEMAIMPLSSEF2I32U64 *PFNIEMAIMPLSSEF2I32U64;
3454	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I64U64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int64_t pi64Dst, const uint64_t pu64Src)); / pu64Src is a double precision floating point. */
3455	typedef FNIEMAIMPLSSEF2I64U64 *PFNIEMAIMPLSSEF2I64U64;
3456	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I32U32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int32_t pi32Dst, const uint32_t pu32Src)); / pu32Src is a single precision floating point. */
3457	typedef FNIEMAIMPLSSEF2I32U32 *PFNIEMAIMPLSSEF2I32U32;
3458	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I64U32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int64_t pi64Dst, const uint32_t pu32Src)); / pu32Src is a single precision floating point. */
3459	typedef FNIEMAIMPLSSEF2I64U32 *PFNIEMAIMPLSSEF2I64U32;
3460
3461	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvttsd2si_i32_r64;
3462	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvtsd2si_i32_r64;
3463
3464	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvttsd2si_i64_r64;
3465	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvtsd2si_i64_r64;
3466
3467	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvttss2si_i32_r32;
3468	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvtss2si_i32_r32;
3469
3470	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvttss2si_i64_r32;
3471	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvtss2si_i64_r32;
3472
3473	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R32I32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT32U pr32Dst, const int32_t pi32Src));
3474	typedef FNIEMAIMPLSSEF2R32I32 *PFNIEMAIMPLSSEF2R32I32;
3475	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R32I64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT32U pr32Dst, const int64_t pi64Src));
3476	typedef FNIEMAIMPLSSEF2R32I64 *PFNIEMAIMPLSSEF2R32I64;
3477
3478	FNIEMAIMPLSSEF2R32I32 iemAImpl_cvtsi2ss_r32_i32;
3479	FNIEMAIMPLSSEF2R32I64 iemAImpl_cvtsi2ss_r32_i64;
3480
3481	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R64I32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT64U pr64Dst, const int32_t pi32Src));
3482	typedef FNIEMAIMPLSSEF2R64I32 *PFNIEMAIMPLSSEF2R64I32;
3483	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R64I64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT64U pr64Dst, const int64_t pi64Src));
3484	typedef FNIEMAIMPLSSEF2R64I64 *PFNIEMAIMPLSSEF2R64I64;
3485
3486	FNIEMAIMPLSSEF2R64I32 iemAImpl_cvtsi2sd_r64_i32;
3487	FNIEMAIMPLSSEF2R64I64 iemAImpl_cvtsi2sd_r64_i64;
3488
3489
3490	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFLMXCSR128,(uint32_t pfMxcsr, uint32_t pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
3491	typedef FNIEMAIMPLF2EFLMXCSR128 *PFNIEMAIMPLF2EFLMXCSR128;
3492
3493	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_ucomiss_u128;
3494	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback;
3495
3496	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_ucomisd_u128;
3497	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback;
3498
3499	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_comiss_u128;
3500	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback;
3501
3502	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_comisd_u128;
3503	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback;
3504
3505
3506	typedef struct IEMMEDIAF2XMMSRC
3507	{
3508	X86XMMREG uSrc1;
3509	X86XMMREG uSrc2;
3510	} IEMMEDIAF2XMMSRC;
3511	typedef IEMMEDIAF2XMMSRC *PIEMMEDIAF2XMMSRC;
3512	typedef const IEMMEDIAF2XMMSRC *PCIEMMEDIAF2XMMSRC;
3513
3514	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRF2XMMIMM8,(uint32_t *pfMxcsr, PX86XMMREG puDst, PCIEMMEDIAF2XMMSRC puSrc, uint8_t bEvil));
3515	typedef FNIEMAIMPLMXCSRF2XMMIMM8 *PFNIEMAIMPLMXCSRF2XMMIMM8;
3516
3517	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpps_u128;
3518	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmppd_u128;
3519	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpss_u128;
3520	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpsd_u128;
3521	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundss_u128;
3522	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundsd_u128;
3523
3524	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundps_u128, iemAImpl_roundps_u128_fallback;
3525	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundpd_u128, iemAImpl_roundpd_u128_fallback;
3526
3527	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_dpps_u128, iemAImpl_dpps_u128_fallback;
3528	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_dppd_u128, iemAImpl_dppd_u128_fallback;
3529
3530	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU64U128,(uint32_t pfMxcsr, uint64_t pu64Dst, PCX86XMMREG pSrc));
3531	typedef FNIEMAIMPLMXCSRU64U128 *PFNIEMAIMPLMXCSRU64U128;
3532
3533	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvtpd2pi_u128;
3534	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvttpd2pi_u128;
3535
3536	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU128U64,(uint32_t *pfMxcsr, PX86XMMREG pDst, uint64_t u64Src));
3537	typedef FNIEMAIMPLMXCSRU128U64 *PFNIEMAIMPLMXCSRU128U64;
3538
3539	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2ps_u128;
3540	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2pd_u128;
3541
3542	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU64U64,(uint32_t pfMxcsr, uint64_t pu64Dst, uint64_t u64Src));
3543	typedef FNIEMAIMPLMXCSRU64U64 *PFNIEMAIMPLMXCSRU64U64;
3544
3545	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvtps2pi_u128;
3546	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvttps2pi_u128;
3547
3548	/** @} */
3549
3550
3551	/** @name Function tables.
3552	* @{
3553	*/
3554
3555	/**
3556	* Function table for a binary operator providing implementation based on
3557	* operand size.
3558	*/
3559	typedef struct IEMOPBINSIZES
3560	{
3561	PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
3562	PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
3563	PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
3564	PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
3565	} IEMOPBINSIZES;
3566	/** Pointer to a binary operator function table. */
3567	typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
3568
3569
3570	/**
3571	* Function table for a unary operator providing implementation based on
3572	* operand size.
3573	*/
3574	typedef struct IEMOPUNARYSIZES
3575	{
3576	PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
3577	PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
3578	PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
3579	PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
3580	} IEMOPUNARYSIZES;
3581	/** Pointer to a unary operator function table. */
3582	typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
3583
3584
3585	/**
3586	* Function table for a shift operator providing implementation based on
3587	* operand size.
3588	*/
3589	typedef struct IEMOPSHIFTSIZES
3590	{
3591	PFNIEMAIMPLSHIFTU8 pfnNormalU8;
3592	PFNIEMAIMPLSHIFTU16 pfnNormalU16;
3593	PFNIEMAIMPLSHIFTU32 pfnNormalU32;
3594	PFNIEMAIMPLSHIFTU64 pfnNormalU64;
3595	} IEMOPSHIFTSIZES;
3596	/** Pointer to a shift operator function table. */
3597	typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
3598
3599
3600	/**
3601	* Function table for a multiplication or division operation.
3602	*/
3603	typedef struct IEMOPMULDIVSIZES
3604	{
3605	PFNIEMAIMPLMULDIVU8 pfnU8;
3606	PFNIEMAIMPLMULDIVU16 pfnU16;
3607	PFNIEMAIMPLMULDIVU32 pfnU32;
3608	PFNIEMAIMPLMULDIVU64 pfnU64;
3609	} IEMOPMULDIVSIZES;
3610	/** Pointer to a multiplication or division operation function table. */
3611	typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
3612
3613
3614	/**
3615	* Function table for a double precision shift operator providing implementation
3616	* based on operand size.
3617	*/
3618	typedef struct IEMOPSHIFTDBLSIZES
3619	{
3620	PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
3621	PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
3622	PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
3623	} IEMOPSHIFTDBLSIZES;
3624	/** Pointer to a double precision shift function table. */
3625	typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
3626
3627
3628	/**
3629	* Function table for media instruction taking two full sized media source
3630	* registers and one full sized destination register (AVX).
3631	*/
3632	typedef struct IEMOPMEDIAF3
3633	{
3634	PFNIEMAIMPLMEDIAF3U128 pfnU128;
3635	PFNIEMAIMPLMEDIAF3U256 pfnU256;
3636	} IEMOPMEDIAF3;
3637	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
3638	typedef IEMOPMEDIAF3 const *PCIEMOPMEDIAF3;
3639
3640	/** @def IEMOPMEDIAF3_INIT_VARS_EX
3641	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3642	* given functions as initializers. For use in AVX functions where a pair of
3643	* functions are only used once and the function table need not be public. */
3644	#ifndef TST_IEM_CHECK_MC
3645	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3646	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3647	static IEMOPMEDIAF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3648	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3649	# else
3650	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3651	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3652	# endif
3653	#else
3654	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3655	#endif
3656	/** @def IEMOPMEDIAF3_INIT_VARS
3657	* Generate AVX function tables for the @a a_InstrNm instruction.
3658	* @sa IEMOPMEDIAF3_INIT_VARS_EX */
3659	#define IEMOPMEDIAF3_INIT_VARS(a_InstrNm) \
3660	IEMOPMEDIAF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3661	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3662
3663	/**
3664	* Function table for media instruction taking two full sized media source
3665	* registers and one full sized destination register, but no additional state
3666	* (AVX).
3667	*/
3668	typedef struct IEMOPMEDIAOPTF3
3669	{
3670	PFNIEMAIMPLMEDIAOPTF3U128 pfnU128;
3671	PFNIEMAIMPLMEDIAOPTF3U256 pfnU256;
3672	} IEMOPMEDIAOPTF3;
3673	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
3674	typedef IEMOPMEDIAOPTF3 const *PCIEMOPMEDIAOPTF3;
3675
3676	/** @def IEMOPMEDIAOPTF3_INIT_VARS_EX
3677	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3678	* given functions as initializers. For use in AVX functions where a pair of
3679	* functions are only used once and the function table need not be public. */
3680	#ifndef TST_IEM_CHECK_MC
3681	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3682	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3683	static IEMOPMEDIAOPTF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3684	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3685	# else
3686	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3687	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3688	# endif
3689	#else
3690	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3691	#endif
3692	/** @def IEMOPMEDIAOPTF3_INIT_VARS
3693	* Generate AVX function tables for the @a a_InstrNm instruction.
3694	* @sa IEMOPMEDIAOPTF3_INIT_VARS_EX */
3695	#define IEMOPMEDIAOPTF3_INIT_VARS(a_InstrNm) \
3696	IEMOPMEDIAOPTF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3697	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3698
3699	/**
3700	* Function table for media instruction taking one full sized media source
3701	* registers and one full sized destination register, but no additional state
3702	* (AVX).
3703	*/
3704	typedef struct IEMOPMEDIAOPTF2
3705	{
3706	PFNIEMAIMPLMEDIAOPTF2U128 pfnU128;
3707	PFNIEMAIMPLMEDIAOPTF2U256 pfnU256;
3708	} IEMOPMEDIAOPTF2;
3709	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
3710	typedef IEMOPMEDIAOPTF2 const *PCIEMOPMEDIAOPTF2;
3711
3712	/** @def IEMOPMEDIAOPTF2_INIT_VARS_EX
3713	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3714	* given functions as initializers. For use in AVX functions where a pair of
3715	* functions are only used once and the function table need not be public. */
3716	#ifndef TST_IEM_CHECK_MC
3717	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3718	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3719	static IEMOPMEDIAOPTF2 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3720	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3721	# else
3722	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3723	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3724	# endif
3725	#else
3726	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3727	#endif
3728	/** @def IEMOPMEDIAOPTF2_INIT_VARS
3729	* Generate AVX function tables for the @a a_InstrNm instruction.
3730	* @sa IEMOPMEDIAOPTF2_INIT_VARS_EX */
3731	#define IEMOPMEDIAOPTF2_INIT_VARS(a_InstrNm) \
3732	IEMOPMEDIAOPTF2_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3733	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3734
3735	/**
3736	* Function table for media instruction taking two full sized media source
3737	* registers and one full sized destination register and an 8-bit immediate, but no additional state
3738	* (AVX).
3739	*/
3740	typedef struct IEMOPMEDIAOPTF3IMM8
3741	{
3742	PFNIEMAIMPLMEDIAOPTF3U128IMM8 pfnU128;
3743	PFNIEMAIMPLMEDIAOPTF3U256IMM8 pfnU256;
3744	} IEMOPMEDIAOPTF3IMM8;
3745	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
3746	typedef IEMOPMEDIAOPTF3IMM8 const *PCIEMOPMEDIAOPTF3IMM8;
3747
3748	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX
3749	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3750	* given functions as initializers. For use in AVX functions where a pair of
3751	* functions are only used once and the function table need not be public. */
3752	#ifndef TST_IEM_CHECK_MC
3753	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3754	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3755	static IEMOPMEDIAOPTF3IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3756	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3757	# else
3758	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3759	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3760	# endif
3761	#else
3762	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3763	#endif
3764	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS
3765	* Generate AVX function tables for the @a a_InstrNm instruction.
3766	* @sa IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX */
3767	#define IEMOPMEDIAOPTF3IMM8_INIT_VARS(a_InstrNm) \
3768	IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3769	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3770	/** @} */
3771
3772
3773	/**
3774	* Function table for blend type instruction taking three full sized media source
3775	* registers and one full sized destination register, but no additional state
3776	* (AVX).
3777	*/
3778	typedef struct IEMOPBLENDOP
3779	{
3780	PFNIEMAIMPLAVXBLENDU128 pfnU128;
3781	PFNIEMAIMPLAVXBLENDU256 pfnU256;
3782	} IEMOPBLENDOP;
3783	/** Pointer to a media operation function table for 4 full sized ops (AVX). */
3784	typedef IEMOPBLENDOP const *PCIEMOPBLENDOP;
3785
3786	/** @def IEMOPBLENDOP_INIT_VARS_EX
3787	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3788	* given functions as initializers. For use in AVX functions where a pair of
3789	* functions are only used once and the function table need not be public. */
3790	#ifndef TST_IEM_CHECK_MC
3791	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3792	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3793	static IEMOPBLENDOP const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3794	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3795	# else
3796	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3797	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3798	# endif
3799	#else
3800	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3801	#endif
3802	/** @def IEMOPBLENDOP_INIT_VARS
3803	* Generate AVX function tables for the @a a_InstrNm instruction.
3804	* @sa IEMOPBLENDOP_INIT_VARS_EX */
3805	#define IEMOPBLENDOP_INIT_VARS(a_InstrNm) \
3806	IEMOPBLENDOP_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3807	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3808
3809
3810	/** @name SSE/AVX single/double precision floating point operations.
3811	* @{ */
3812	/**
3813	* A SSE result.
3814	*/
3815	typedef struct IEMSSERESULT
3816	{
3817	/** The output value. */
3818	X86XMMREG uResult;
3819	/** The output status. */
3820	uint32_t MXCSR;
3821	} IEMSSERESULT;
3822	AssertCompileMemberOffset(IEMSSERESULT, MXCSR, 128 / 8);
3823	/** Pointer to a SSE result. */
3824	typedef IEMSSERESULT *PIEMSSERESULT;
3825	/** Pointer to a const SSE result. */
3826	typedef IEMSSERESULT const *PCIEMSSERESULT;
3827
3828
3829	/**
3830	* A AVX128 result.
3831	*/
3832	typedef struct IEMAVX128RESULT
3833	{
3834	/** The output value. */
3835	X86XMMREG uResult;
3836	/** The output status. */
3837	uint32_t MXCSR;
3838	} IEMAVX128RESULT;
3839	AssertCompileMemberOffset(IEMAVX128RESULT, MXCSR, 128 / 8);
3840	/** Pointer to a AVX128 result. */
3841	typedef IEMAVX128RESULT *PIEMAVX128RESULT;
3842	/** Pointer to a const AVX128 result. */
3843	typedef IEMAVX128RESULT const *PCIEMAVX128RESULT;
3844
3845
3846	/**
3847	* A AVX256 result.
3848	*/
3849	typedef struct IEMAVX256RESULT
3850	{
3851	/** The output value. */
3852	X86YMMREG uResult;
3853	/** The output status. */
3854	uint32_t MXCSR;
3855	} IEMAVX256RESULT;
3856	AssertCompileMemberOffset(IEMAVX256RESULT, MXCSR, 256 / 8);
3857	/** Pointer to a AVX256 result. */
3858	typedef IEMAVX256RESULT *PIEMAVX256RESULT;
3859	/** Pointer to a const AVX256 result. */
3860	typedef IEMAVX256RESULT const *PCIEMAVX256RESULT;
3861
3862
3863	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
3864	typedef FNIEMAIMPLFPSSEF2U128 *PFNIEMAIMPLFPSSEF2U128;
3865	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128R32,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
3866	typedef FNIEMAIMPLFPSSEF2U128R32 *PFNIEMAIMPLFPSSEF2U128R32;
3867	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128R64,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
3868	typedef FNIEMAIMPLFPSSEF2U128R64 *PFNIEMAIMPLFPSSEF2U128R64;
3869
3870	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
3871	typedef FNIEMAIMPLFPAVXF3U128 *PFNIEMAIMPLFPAVXF3U128;
3872	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128R32,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
3873	typedef FNIEMAIMPLFPAVXF3U128R32 *PFNIEMAIMPLFPAVXF3U128R32;
3874	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128R64,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
3875	typedef FNIEMAIMPLFPAVXF3U128R64 *PFNIEMAIMPLFPAVXF3U128R64;
3876
3877	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U256,(PX86XSAVEAREA pExtState, PIEMAVX256RESULT pResult, PCX86YMMREG puSrc1, PCX86YMMREG puSrc2));
3878	typedef FNIEMAIMPLFPAVXF3U256 *PFNIEMAIMPLFPAVXF3U256;
3879
3880	FNIEMAIMPLFPSSEF2U128 iemAImpl_addps_u128;
3881	FNIEMAIMPLFPSSEF2U128 iemAImpl_addpd_u128;
3882	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulps_u128;
3883	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulpd_u128;
3884	FNIEMAIMPLFPSSEF2U128 iemAImpl_subps_u128;
3885	FNIEMAIMPLFPSSEF2U128 iemAImpl_subpd_u128;
3886	FNIEMAIMPLFPSSEF2U128 iemAImpl_minps_u128;
3887	FNIEMAIMPLFPSSEF2U128 iemAImpl_minpd_u128;
3888	FNIEMAIMPLFPSSEF2U128 iemAImpl_divps_u128;
3889	FNIEMAIMPLFPSSEF2U128 iemAImpl_divpd_u128;
3890	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxps_u128;
3891	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxpd_u128;
3892	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddps_u128;
3893	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddpd_u128;
3894	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubps_u128;
3895	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubpd_u128;
3896	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtps_u128;
3897	FNIEMAIMPLFPSSEF2U128 iemAImpl_rsqrtps_u128;
3898	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtpd_u128;
3899	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubps_u128;
3900	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubpd_u128;
3901	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2ps_u128;
3902	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2pd_u128;
3903
3904	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2ps_u128;
3905	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2dq_u128;
3906	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttps2dq_u128;
3907	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttpd2dq_u128;
3908	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2pd_u128;
3909	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2dq_u128;
3910
3911	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_addss_u128_r32;
3912	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_addsd_u128_r64;
3913	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_mulss_u128_r32;
3914	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_mulsd_u128_r64;
3915	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_subss_u128_r32;
3916	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_subsd_u128_r64;
3917	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_minss_u128_r32;
3918	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_minsd_u128_r64;
3919	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_divss_u128_r32;
3920	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_divsd_u128_r64;
3921	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_maxss_u128_r32;
3922	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_maxsd_u128_r64;
3923	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_cvtss2sd_u128_r32;
3924	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_cvtsd2ss_u128_r64;
3925	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_sqrtss_u128_r32;
3926	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_sqrtsd_u128_r64;
3927	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_rsqrtss_u128_r32;
3928
3929	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddps_u128, iemAImpl_vaddps_u128_fallback;
3930	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddpd_u128, iemAImpl_vaddpd_u128_fallback;
3931	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulps_u128, iemAImpl_vmulps_u128_fallback;
3932	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulpd_u128, iemAImpl_vmulpd_u128_fallback;
3933	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubps_u128, iemAImpl_vsubps_u128_fallback;
3934	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubpd_u128, iemAImpl_vsubpd_u128_fallback;
3935	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminps_u128, iemAImpl_vminps_u128_fallback;
3936	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminpd_u128, iemAImpl_vminpd_u128_fallback;
3937	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivps_u128, iemAImpl_vdivps_u128_fallback;
3938	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivpd_u128, iemAImpl_vdivpd_u128_fallback;
3939	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxps_u128, iemAImpl_vmaxps_u128_fallback;
3940	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxpd_u128, iemAImpl_vmaxpd_u128_fallback;
3941	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddps_u128, iemAImpl_vhaddps_u128_fallback;
3942	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddpd_u128, iemAImpl_vhaddpd_u128_fallback;
3943	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubps_u128, iemAImpl_vhsubps_u128_fallback;
3944	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubpd_u128, iemAImpl_vhsubpd_u128_fallback;
3945	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtps_u128, iemAImpl_vsqrtps_u128_fallback;
3946	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtpd_u128, iemAImpl_vsqrtpd_u128_fallback;
3947	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubps_u128, iemAImpl_vaddsubps_u128_fallback;
3948	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubpd_u128, iemAImpl_vaddsubpd_u128_fallback;
3949	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtpd2ps_u128, iemAImpl_vcvtpd2ps_u128_fallback;
3950	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtps2pd_u128, iemAImpl_vcvtps2pd_u128_fallback;
3951
3952	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vaddss_u128_r32, iemAImpl_vaddss_u128_r32_fallback;
3953	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vaddsd_u128_r64, iemAImpl_vaddsd_u128_r64_fallback;
3954	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmulss_u128_r32, iemAImpl_vmulss_u128_r32_fallback;
3955	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmulsd_u128_r64, iemAImpl_vmulsd_u128_r64_fallback;
3956	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsubss_u128_r32, iemAImpl_vsubss_u128_r32_fallback;
3957	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsubsd_u128_r64, iemAImpl_vsubsd_u128_r64_fallback;
3958	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vminss_u128_r32, iemAImpl_vminss_u128_r32_fallback;
3959	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vminsd_u128_r64, iemAImpl_vminsd_u128_r64_fallback;
3960	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vdivss_u128_r32, iemAImpl_vdivss_u128_r32_fallback;
3961	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vdivsd_u128_r64, iemAImpl_vdivsd_u128_r64_fallback;
3962	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmaxss_u128_r32, iemAImpl_vmaxss_u128_r32_fallback;
3963	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmaxsd_u128_r64, iemAImpl_vmaxsd_u128_r64_fallback;
3964	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsqrtss_u128_r32, iemAImpl_vsqrtss_u128_r32_fallback;
3965	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsqrtsd_u128_r64, iemAImpl_vsqrtsd_u128_r64_fallback;
3966
3967	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddps_u256, iemAImpl_vaddps_u256_fallback;
3968	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddpd_u256, iemAImpl_vaddpd_u256_fallback;
3969	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulps_u256, iemAImpl_vmulps_u256_fallback;
3970	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulpd_u256, iemAImpl_vmulpd_u256_fallback;
3971	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubps_u256, iemAImpl_vsubps_u256_fallback;
3972	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubpd_u256, iemAImpl_vsubpd_u256_fallback;
3973	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminps_u256, iemAImpl_vminps_u256_fallback;
3974	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminpd_u256, iemAImpl_vminpd_u256_fallback;
3975	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivps_u256, iemAImpl_vdivps_u256_fallback;
3976	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivpd_u256, iemAImpl_vdivpd_u256_fallback;
3977	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxps_u256, iemAImpl_vmaxps_u256_fallback;
3978	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxpd_u256, iemAImpl_vmaxpd_u256_fallback;
3979	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddps_u256, iemAImpl_vhaddps_u256_fallback;
3980	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddpd_u256, iemAImpl_vhaddpd_u256_fallback;
3981	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubps_u256, iemAImpl_vhsubps_u256_fallback;
3982	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubpd_u256, iemAImpl_vhsubpd_u256_fallback;
3983	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubps_u256, iemAImpl_vhaddsubps_u256_fallback;
3984	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubpd_u256, iemAImpl_vhaddsubpd_u256_fallback;
3985	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtpd2ps_u256, iemAImpl_vcvtpd2ps_u256_fallback;
3986	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtps2pd_u256, iemAImpl_vcvtps2pd_u256_fallback;
3987	/** @} */
3988
3989	/** @name C instruction implementations for anything slightly complicated.
3990	* @{ */
3991
3992	/**
3993	* For typedef'ing or declaring a C instruction implementation function taking
3994	* no extra arguments.
3995	*
3996	* @param a_Name The name of the type.
3997	*/
3998	# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
3999	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
4000	/**
4001	* For defining a C instruction implementation function taking no extra
4002	* arguments.
4003	*
4004	* @param a_Name The name of the function
4005	*/
4006	# define IEM_CIMPL_DEF_0(a_Name) \
4007	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
4008	/**
4009	* Prototype version of IEM_CIMPL_DEF_0.
4010	*/
4011	# define IEM_CIMPL_PROTO_0(a_Name) \
4012	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
4013	/**
4014	* For calling a C instruction implementation function taking no extra
4015	* arguments.
4016	*
4017	* This special call macro adds default arguments to the call and allow us to
4018	* change these later.
4019	*
4020	* @param a_fn The name of the function.
4021	*/
4022	# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
4023
4024	/** Type for a C instruction implementation function taking no extra
4025	* arguments. */
4026	typedef IEM_CIMPL_DECL_TYPE_0(FNIEMCIMPL0);
4027	/** Function pointer type for a C instruction implementation function taking
4028	* no extra arguments. */
4029	typedef FNIEMCIMPL0 *PFNIEMCIMPL0;
4030
4031	/**
4032	* For typedef'ing or declaring a C instruction implementation function taking
4033	* one extra argument.
4034	*
4035	* @param a_Name The name of the type.
4036	* @param a_Type0 The argument type.
4037	* @param a_Arg0 The argument name.
4038	*/
4039	# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
4040	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
4041	/**
4042	* For defining a C instruction implementation function taking one extra
4043	* argument.
4044	*
4045	* @param a_Name The name of the function
4046	* @param a_Type0 The argument type.
4047	* @param a_Arg0 The argument name.
4048	*/
4049	# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
4050	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
4051	/**
4052	* Prototype version of IEM_CIMPL_DEF_1.
4053	*/
4054	# define IEM_CIMPL_PROTO_1(a_Name, a_Type0, a_Arg0) \
4055	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
4056	/**
4057	* For calling a C instruction implementation function taking one extra
4058	* argument.
4059	*
4060	* This special call macro adds default arguments to the call and allow us to
4061	* change these later.
4062	*
4063	* @param a_fn The name of the function.
4064	* @param a0 The name of the 1st argument.
4065	*/
4066	# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
4067
4068	/**
4069	* For typedef'ing or declaring a C instruction implementation function taking
4070	* two extra arguments.
4071	*
4072	* @param a_Name The name of the type.
4073	* @param a_Type0 The type of the 1st argument
4074	* @param a_Arg0 The name of the 1st argument.
4075	* @param a_Type1 The type of the 2nd argument.
4076	* @param a_Arg1 The name of the 2nd argument.
4077	*/
4078	# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
4079	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
4080	/**
4081	* For defining a C instruction implementation function taking two extra
4082	* arguments.
4083	*
4084	* @param a_Name The name of the function.
4085	* @param a_Type0 The type of the 1st argument
4086	* @param a_Arg0 The name of the 1st argument.
4087	* @param a_Type1 The type of the 2nd argument.
4088	* @param a_Arg1 The name of the 2nd argument.
4089	*/
4090	# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
4091	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
4092	/**
4093	* Prototype version of IEM_CIMPL_DEF_2.
4094	*/
4095	# define IEM_CIMPL_PROTO_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
4096	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
4097	/**
4098	* For calling a C instruction implementation function taking two extra
4099	* arguments.
4100	*
4101	* This special call macro adds default arguments to the call and allow us to
4102	* change these later.
4103	*
4104	* @param a_fn The name of the function.
4105	* @param a0 The name of the 1st argument.
4106	* @param a1 The name of the 2nd argument.
4107	*/
4108	# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
4109
4110	/**
4111	* For typedef'ing or declaring a C instruction implementation function taking
4112	* three extra arguments.
4113	*
4114	* @param a_Name The name of the type.
4115	* @param a_Type0 The type of the 1st argument
4116	* @param a_Arg0 The name of the 1st argument.
4117	* @param a_Type1 The type of the 2nd argument.
4118	* @param a_Arg1 The name of the 2nd argument.
4119	* @param a_Type2 The type of the 3rd argument.
4120	* @param a_Arg2 The name of the 3rd argument.
4121	*/
4122	# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
4123	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
4124	/**
4125	* For defining a C instruction implementation function taking three extra
4126	* arguments.
4127	*
4128	* @param a_Name The name of the function.
4129	* @param a_Type0 The type of the 1st argument
4130	* @param a_Arg0 The name of the 1st argument.
4131	* @param a_Type1 The type of the 2nd argument.
4132	* @param a_Arg1 The name of the 2nd argument.
4133	* @param a_Type2 The type of the 3rd argument.
4134	* @param a_Arg2 The name of the 3rd argument.
4135	*/
4136	# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
4137	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
4138	/**
4139	* Prototype version of IEM_CIMPL_DEF_3.
4140	*/
4141	# define IEM_CIMPL_PROTO_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
4142	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
4143	/**
4144	* For calling a C instruction implementation function taking three extra
4145	* arguments.
4146	*
4147	* This special call macro adds default arguments to the call and allow us to
4148	* change these later.
4149	*
4150	* @param a_fn The name of the function.
4151	* @param a0 The name of the 1st argument.
4152	* @param a1 The name of the 2nd argument.
4153	* @param a2 The name of the 3rd argument.
4154	*/
4155	# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
4156
4157
4158	/**
4159	* For typedef'ing or declaring a C instruction implementation function taking
4160	* four extra arguments.
4161	*
4162	* @param a_Name The name of the type.
4163	* @param a_Type0 The type of the 1st argument
4164	* @param a_Arg0 The name of the 1st argument.
4165	* @param a_Type1 The type of the 2nd argument.
4166	* @param a_Arg1 The name of the 2nd argument.
4167	* @param a_Type2 The type of the 3rd argument.
4168	* @param a_Arg2 The name of the 3rd argument.
4169	* @param a_Type3 The type of the 4th argument.
4170	* @param a_Arg3 The name of the 4th argument.
4171	*/
4172	# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
4173	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
4174	/**
4175	* For defining a C instruction implementation function taking four extra
4176	* arguments.
4177	*
4178	* @param a_Name The name of the function.
4179	* @param a_Type0 The type of the 1st argument
4180	* @param a_Arg0 The name of the 1st argument.
4181	* @param a_Type1 The type of the 2nd argument.
4182	* @param a_Arg1 The name of the 2nd argument.
4183	* @param a_Type2 The type of the 3rd argument.
4184	* @param a_Arg2 The name of the 3rd argument.
4185	* @param a_Type3 The type of the 4th argument.
4186	* @param a_Arg3 The name of the 4th argument.
4187	*/
4188	# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
4189	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4190	a_Type2 a_Arg2, a_Type3 a_Arg3))
4191	/**
4192	* Prototype version of IEM_CIMPL_DEF_4.
4193	*/
4194	# define IEM_CIMPL_PROTO_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
4195	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4196	a_Type2 a_Arg2, a_Type3 a_Arg3))
4197	/**
4198	* For calling a C instruction implementation function taking four extra
4199	* arguments.
4200	*
4201	* This special call macro adds default arguments to the call and allow us to
4202	* change these later.
4203	*
4204	* @param a_fn The name of the function.
4205	* @param a0 The name of the 1st argument.
4206	* @param a1 The name of the 2nd argument.
4207	* @param a2 The name of the 3rd argument.
4208	* @param a3 The name of the 4th argument.
4209	*/
4210	# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
4211
4212
4213	/**
4214	* For typedef'ing or declaring a C instruction implementation function taking
4215	* five extra arguments.
4216	*
4217	* @param a_Name The name of the type.
4218	* @param a_Type0 The type of the 1st argument
4219	* @param a_Arg0 The name of the 1st argument.
4220	* @param a_Type1 The type of the 2nd argument.
4221	* @param a_Arg1 The name of the 2nd argument.
4222	* @param a_Type2 The type of the 3rd argument.
4223	* @param a_Arg2 The name of the 3rd argument.
4224	* @param a_Type3 The type of the 4th argument.
4225	* @param a_Arg3 The name of the 4th argument.
4226	* @param a_Type4 The type of the 5th argument.
4227	* @param a_Arg4 The name of the 5th argument.
4228	*/
4229	# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
4230	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, \
4231	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
4232	a_Type3 a_Arg3, a_Type4 a_Arg4))
4233	/**
4234	* For defining a C instruction implementation function taking five extra
4235	* arguments.
4236	*
4237	* @param a_Name The name of the function.
4238	* @param a_Type0 The type of the 1st argument
4239	* @param a_Arg0 The name of the 1st argument.
4240	* @param a_Type1 The type of the 2nd argument.
4241	* @param a_Arg1 The name of the 2nd argument.
4242	* @param a_Type2 The type of the 3rd argument.
4243	* @param a_Arg2 The name of the 3rd argument.
4244	* @param a_Type3 The type of the 4th argument.
4245	* @param a_Arg3 The name of the 4th argument.
4246	* @param a_Type4 The type of the 5th argument.
4247	* @param a_Arg4 The name of the 5th argument.
4248	*/
4249	# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
4250	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4251	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
4252	/**
4253	* Prototype version of IEM_CIMPL_DEF_5.
4254	*/
4255	# define IEM_CIMPL_PROTO_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
4256	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4257	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
4258	/**
4259	* For calling a C instruction implementation function taking five extra
4260	* arguments.
4261	*
4262	* This special call macro adds default arguments to the call and allow us to
4263	* change these later.
4264	*
4265	* @param a_fn The name of the function.
4266	* @param a0 The name of the 1st argument.
4267	* @param a1 The name of the 2nd argument.
4268	* @param a2 The name of the 3rd argument.
4269	* @param a3 The name of the 4th argument.
4270	* @param a4 The name of the 5th argument.
4271	*/
4272	# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
4273
4274	/** @} */
4275
4276
4277	/** @name Opcode Decoder Function Types.
4278	* @{ */
4279
4280	/** @typedef PFNIEMOP
4281	* Pointer to an opcode decoder function.
4282	*/
4283
4284	/** @def FNIEMOP_DEF
4285	* Define an opcode decoder function.
4286	*
4287	* We're using macors for this so that adding and removing parameters as well as
4288	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL
4289	*
4290	* @param a_Name The function name.
4291	*/
4292
4293	/** @typedef PFNIEMOPRM
4294	* Pointer to an opcode decoder function with RM byte.
4295	*/
4296
4297	/** @def FNIEMOPRM_DEF
4298	* Define an opcode decoder function with RM byte.
4299	*
4300	* We're using macors for this so that adding and removing parameters as well as
4301	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL_1
4302	*
4303	* @param a_Name The function name.
4304	*/
4305
4306	#if defined(__GNUC__) && defined(RT_ARCH_X86)
4307	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOP)(PVMCPUCC pVCpu);
4308	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4309	# define FNIEMOP_DEF(a_Name) \
4310	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu)
4311	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4312	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
4313	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4314	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
4315
4316	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
4317	typedef VBOXSTRICTRC (__fastcall * PFNIEMOP)(PVMCPUCC pVCpu);
4318	typedef VBOXSTRICTRC (__fastcall * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4319	# define FNIEMOP_DEF(a_Name) \
4320	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
4321	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4322	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
4323	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4324	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
4325
4326	#elif defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
4327	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
4328	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4329	# define FNIEMOP_DEF(a_Name) \
4330	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu)
4331	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4332	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
4333	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4334	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
4335
4336	#else
4337	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
4338	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4339	# define FNIEMOP_DEF(a_Name) \
4340	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
4341	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4342	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
4343	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4344	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
4345
4346	#endif
4347	#define FNIEMOPRM_DEF(a_Name) FNIEMOP_DEF_1(a_Name, uint8_t, bRm)
4348
4349	/**
4350	* Call an opcode decoder function.
4351	*
4352	* We're using macors for this so that adding and removing parameters can be
4353	* done as we please. See FNIEMOP_DEF.
4354	*/
4355	#define FNIEMOP_CALL(a_pfn) (a_pfn)(pVCpu)
4356
4357	/**
4358	* Call a common opcode decoder function taking one extra argument.
4359	*
4360	* We're using macors for this so that adding and removing parameters can be
4361	* done as we please. See FNIEMOP_DEF_1.
4362	*/
4363	#define FNIEMOP_CALL_1(a_pfn, a0) (a_pfn)(pVCpu, a0)
4364
4365	/**
4366	* Call a common opcode decoder function taking one extra argument.
4367	*
4368	* We're using macors for this so that adding and removing parameters can be
4369	* done as we please. See FNIEMOP_DEF_1.
4370	*/
4371	#define FNIEMOP_CALL_2(a_pfn, a0, a1) (a_pfn)(pVCpu, a0, a1)
4372	/** @} */
4373
4374
4375	/** @name Misc Helpers
4376	* @{ */
4377
4378	/** Used to shut up GCC warnings about variables that 'may be used uninitialized'
4379	* due to GCC lacking knowledge about the value range of a switch. */
4380	#if RT_CPLUSPLUS_PREREQ(202000)
4381	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: [[unlikely]] AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
4382	#else
4383	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
4384	#endif
4385
4386	/** Variant of IEM_NOT_REACHED_DEFAULT_CASE_RET that returns a custom value. */
4387	#if RT_CPLUSPLUS_PREREQ(202000)
4388	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: [[unlikely]] AssertFailedReturn(a_RetValue)
4389	#else
4390	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: AssertFailedReturn(a_RetValue)
4391	#endif
4392
4393	/**
4394	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
4395	* occation.
4396	*/
4397	#ifdef LOG_ENABLED
4398	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
4399	do { \
4400	/Log/ LogAlways(("%s: returning IEM_RETURN_ASPECT_NOT_IMPLEMENTED (line %d)\n", __FUNCTION__, __LINE__)); \
4401	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
4402	} while (0)
4403	#else
4404	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
4405	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
4406	#endif
4407
4408	/**
4409	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
4410	* occation using the supplied logger statement.
4411	*
4412	* @param a_LoggerArgs What to log on failure.
4413	*/
4414	#ifdef LOG_ENABLED
4415	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
4416	do { \
4417	LogAlways((LOG_FN_FMT ": ", __PRETTY_FUNCTION__)); LogAlways(a_LoggerArgs); \
4418	/LogFunc(a_LoggerArgs);/ \
4419	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
4420	} while (0)
4421	#else
4422	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
4423	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
4424	#endif
4425
4426	/**
4427	* Gets the CPU mode (from fExec) as a IEMMODE value.
4428	*
4429	* @returns IEMMODE
4430	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4431	*/
4432	#define IEM_GET_CPU_MODE(a_pVCpu) ((a_pVCpu)->iem.s.fExec & IEM_F_MODE_CPUMODE_MASK)
4433
4434	/**
4435	* Check if we're currently executing in real or virtual 8086 mode.
4436	*
4437	* @returns @c true if it is, @c false if not.
4438	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4439	*/
4440	#define IEM_IS_REAL_OR_V86_MODE(a_pVCpu) (( ((a_pVCpu)->iem.s.fExec ^ IEM_F_MODE_X86_PROT_MASK) \
4441	& (IEM_F_MODE_X86_V86_MASK \| IEM_F_MODE_X86_PROT_MASK)) != 0)
4442
4443	/**
4444	* Check if we're currently executing in virtual 8086 mode.
4445	*
4446	* @returns @c true if it is, @c false if not.
4447	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4448	*/
4449	#define IEM_IS_V86_MODE(a_pVCpu) (((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_V86_MASK) != 0)
4450
4451	/**
4452	* Check if we're currently executing in long mode.
4453	*
4454	* @returns @c true if it is, @c false if not.
4455	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4456	*/
4457	#define IEM_IS_LONG_MODE(a_pVCpu) (CPUMIsGuestInLongModeEx(IEM_GET_CTX(a_pVCpu)))
4458
4459	/**
4460	* Check if we're currently executing in a 16-bit code segment.
4461	*
4462	* @returns @c true if it is, @c false if not.
4463	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4464	*/
4465	#define IEM_IS_16BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_16BIT)
4466
4467	/**
4468	* Check if we're currently executing in a 32-bit code segment.
4469	*
4470	* @returns @c true if it is, @c false if not.
4471	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4472	*/
4473	#define IEM_IS_32BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_32BIT)
4474
4475	/**
4476	* Check if we're currently executing in a 64-bit code segment.
4477	*
4478	* @returns @c true if it is, @c false if not.
4479	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4480	*/
4481	#define IEM_IS_64BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_64BIT)
4482
4483	/**
4484	* Check if we're currently executing in real mode.
4485	*
4486	* @returns @c true if it is, @c false if not.
4487	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4488	*/
4489	#define IEM_IS_REAL_MODE(a_pVCpu) (!((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_PROT_MASK))
4490
4491	/**
4492	* Gets the current protection level (CPL).
4493	*
4494	* @returns 0..3
4495	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4496	*/
4497	#define IEM_GET_CPL(a_pVCpu) (((a_pVCpu)->iem.s.fExec >> IEM_F_X86_CPL_SHIFT) & IEM_F_X86_CPL_SMASK)
4498
4499	/**
4500	* Sets the current protection level (CPL).
4501	*
4502	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4503	*/
4504	#define IEM_SET_CPL(a_pVCpu, a_uCpl) \
4505	do { (a_pVCpu)->iem.s.fExec = ((a_pVCpu)->iem.s.fExec & ~IEM_F_X86_CPL_MASK) \| ((a_uCpl) << IEM_F_X86_CPL_SHIFT); } while (0)
4506
4507	/**
4508	* Returns a (const) pointer to the CPUMFEATURES for the guest CPU.
4509	* @returns PCCPUMFEATURES
4510	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4511	*/
4512	#define IEM_GET_GUEST_CPU_FEATURES(a_pVCpu) (&((a_pVCpu)->CTX_SUFF(pVM)->cpum.ro.GuestFeatures))
4513
4514	/**
4515	* Returns a (const) pointer to the CPUMFEATURES for the host CPU.
4516	* @returns PCCPUMFEATURES
4517	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4518	*/
4519	#define IEM_GET_HOST_CPU_FEATURES(a_pVCpu) (&g_CpumHostFeatures.s)
4520
4521	/**
4522	* Evaluates to true if we're presenting an Intel CPU to the guest.
4523	*/
4524	#define IEM_IS_GUEST_CPU_INTEL(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL )
4525
4526	/**
4527	* Evaluates to true if we're presenting an AMD CPU to the guest.
4528	*/
4529	#define IEM_IS_GUEST_CPU_AMD(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_AMD \|\| (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_HYGON )
4530
4531	/**
4532	* Check if the address is canonical.
4533	*/
4534	#define IEM_IS_CANONICAL(a_u64Addr) X86_IS_CANONICAL(a_u64Addr)
4535
4536	/** Checks if the ModR/M byte is in register mode or not. */
4537	#define IEM_IS_MODRM_REG_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT) )
4538	/** Checks if the ModR/M byte is in memory mode or not. */
4539	#define IEM_IS_MODRM_MEM_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT) )
4540
4541	/**
4542	* Gets the register (reg) part of a ModR/M encoding, with REX.R added in.
4543	*
4544	* For use during decoding.
4545	*/
4546	#define IEM_GET_MODRM_REG(a_pVCpu, a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| (a_pVCpu)->iem.s.uRexReg )
4547	/**
4548	* Gets the r/m part of a ModR/M encoding as a register index, with REX.B added in.
4549	*
4550	* For use during decoding.
4551	*/
4552	#define IEM_GET_MODRM_RM(a_pVCpu, a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) \| (a_pVCpu)->iem.s.uRexB )
4553
4554	/**
4555	* Gets the register (reg) part of a ModR/M encoding, without REX.R.
4556	*
4557	* For use during decoding.
4558	*/
4559	#define IEM_GET_MODRM_REG_8(a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) )
4560	/**
4561	* Gets the r/m part of a ModR/M encoding as a register index, without REX.B.
4562	*
4563	* For use during decoding.
4564	*/
4565	#define IEM_GET_MODRM_RM_8(a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) )
4566
4567	/**
4568	* Gets the register (reg) part of a ModR/M encoding as an extended 8-bit
4569	* register index, with REX.R added in.
4570	*
4571	* For use during decoding.
4572	*
4573	* @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
4574	*/
4575	#define IEM_GET_MODRM_REG_EX8(a_pVCpu, a_bRm) \
4576	( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
4577	\|\| !((a_bRm) & (4 << X86_MODRM_REG_SHIFT)) /* IEM_GET_MODRM_REG(pVCpu, a_bRm) < 4 */ \
4578	? IEM_GET_MODRM_REG(pVCpu, a_bRm) : (((a_bRm) >> X86_MODRM_REG_SHIFT) & 3) \| 16)
4579	/**
4580	* Gets the r/m part of a ModR/M encoding as an extended 8-bit register index,
4581	* with REX.B added in.
4582	*
4583	* For use during decoding.
4584	*
4585	* @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
4586	*/
4587	#define IEM_GET_MODRM_RM_EX8(a_pVCpu, a_bRm) \
4588	( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
4589	\|\| !((a_bRm) & 4) /* IEM_GET_MODRM_RM(pVCpu, a_bRm) < 4 */ \
4590	? IEM_GET_MODRM_RM(pVCpu, a_bRm) : ((a_bRm) & 3) \| 16)
4591
4592	/**
4593	* Combines the prefix REX and ModR/M byte for passing to
4594	* iemOpHlpCalcRmEffAddrThreadedAddr64().
4595	*
4596	* @returns The ModRM byte but with bit 3 set to REX.B and bit 4 to REX.X.
4597	* The two bits are part of the REG sub-field, which isn't needed in
4598	* iemOpHlpCalcRmEffAddrThreadedAddr64().
4599	*
4600	* For use during decoding/recompiling.
4601	*/
4602	#define IEM_GET_MODRM_EX(a_pVCpu, a_bRm) \
4603	( ((a_bRm) & ~X86_MODRM_REG_MASK) \
4604	\| (uint8_t)( (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X)) >> (26 - 3) ) )
4605	AssertCompile(IEM_OP_PRF_REX_B == RT_BIT_32(26));
4606	AssertCompile(IEM_OP_PRF_REX_X == RT_BIT_32(27));
4607
4608	/**
4609	* Gets the effective VEX.VVVV value.
4610	*
4611	* The 4th bit is ignored if not 64-bit code.
4612	* @returns effective V-register value.
4613	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4614	*/
4615	#define IEM_GET_EFFECTIVE_VVVV(a_pVCpu) \
4616	(IEM_IS_64BIT_CODE(a_pVCpu) ? (a_pVCpu)->iem.s.uVex3rdReg : (a_pVCpu)->iem.s.uVex3rdReg & 7)
4617
4618
4619	/**
4620	* Checks if we're executing inside an AMD-V or VT-x guest.
4621	*/
4622	#if defined(VBOX_WITH_NESTED_HWVIRT_VMX) \|\| defined(VBOX_WITH_NESTED_HWVIRT_SVM)
4623	# define IEM_IS_IN_GUEST(a_pVCpu) RT_BOOL((a_pVCpu)->iem.s.fExec & IEM_F_X86_CTX_IN_GUEST)
4624	#else
4625	# define IEM_IS_IN_GUEST(a_pVCpu) false
4626	#endif
4627
4628
4629	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
4630
4631	/**
4632	* Check if the guest has entered VMX root operation.
4633	*/
4634	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxRootMode(IEM_GET_CTX(a_pVCpu)))
4635
4636	/**
4637	* Check if the guest has entered VMX non-root operation.
4638	*/
4639	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) ( ((a_pVCpu)->iem.s.fExec & (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST)) \
4640	== (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST) )
4641
4642	/**
4643	* Check if the nested-guest has the given Pin-based VM-execution control set.
4644	*/
4645	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_PinCtl) (CPUMIsGuestVmxPinCtlsSet(IEM_GET_CTX(a_pVCpu), (a_PinCtl)))
4646
4647	/**
4648	* Check if the nested-guest has the given Processor-based VM-execution control set.
4649	*/
4650	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_ProcCtl) (CPUMIsGuestVmxProcCtlsSet(IEM_GET_CTX(a_pVCpu), (a_ProcCtl)))
4651
4652	/**
4653	* Check if the nested-guest has the given Secondary Processor-based VM-execution
4654	* control set.
4655	*/
4656	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_ProcCtl2) (CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(a_pVCpu), (a_ProcCtl2)))
4657
4658	/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
4659	# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
4660
4661	/** Whether a shadow VMCS is present for the given VCPU. */
4662	# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
4663
4664	/** Gets the VMXON region pointer. */
4665	# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
4666
4667	/** Gets the guest-physical address of the current VMCS for the given VCPU. */
4668	# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
4669
4670	/** Whether a current VMCS is present for the given VCPU. */
4671	# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
4672
4673	/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
4674	# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
4675	do \
4676	{ \
4677	Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
4678	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
4679	} while (0)
4680
4681	/** Clears any current VMCS for the given VCPU. */
4682	# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
4683	do \
4684	{ \
4685	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
4686	} while (0)
4687
4688	/**
4689	* Invokes the VMX VM-exit handler for an instruction intercept.
4690	*/
4691	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) \
4692	do { return iemVmxVmexitInstr((a_pVCpu), (a_uExitReason), (a_cbInstr)); } while (0)
4693
4694	/**
4695	* Invokes the VMX VM-exit handler for an instruction intercept where the
4696	* instruction provides additional VM-exit information.
4697	*/
4698	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) \
4699	do { return iemVmxVmexitInstrNeedsInfo((a_pVCpu), (a_uExitReason), (a_uInstrId), (a_cbInstr)); } while (0)
4700
4701	/**
4702	* Invokes the VMX VM-exit handler for a task switch.
4703	*/
4704	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) \
4705	do { return iemVmxVmexitTaskSwitch((a_pVCpu), (a_enmTaskSwitch), (a_SelNewTss), (a_cbInstr)); } while (0)
4706
4707	/**
4708	* Invokes the VMX VM-exit handler for MWAIT.
4709	*/
4710	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) \
4711	do { return iemVmxVmexitInstrMwait((a_pVCpu), (a_fMonitorArmed), (a_cbInstr)); } while (0)
4712
4713	/**
4714	* Invokes the VMX VM-exit handler for EPT faults.
4715	*/
4716	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) \
4717	do { return iemVmxVmexitEpt(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr); } while (0)
4718
4719	/**
4720	* Invokes the VMX VM-exit handler.
4721	*/
4722	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) \
4723	do { return iemVmxVmexit((a_pVCpu), (a_uExitReason), (a_uExitQual)); } while (0)
4724
4725	#else
4726	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (false)
4727	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (false)
4728	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_cbInstr) (false)
4729	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_cbInstr) (false)
4730	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_cbInstr) (false)
4731	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4732	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4733	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4734	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4735	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4736	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) do { return VERR_VMX_IPE_1; } while (0)
4737
4738	#endif
4739
4740	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4741	/**
4742	* Checks if we're executing a guest using AMD-V.
4743	*/
4744	# define IEM_SVM_IS_IN_GUEST(a_pVCpu) ( (a_pVCpu->iem.s.fExec & (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST)) \
4745	== (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST))
4746	/**
4747	* Check if an SVM control/instruction intercept is set.
4748	*/
4749	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) \
4750	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmCtrlInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_Intercept)))
4751
4752	/**
4753	* Check if an SVM read CRx intercept is set.
4754	*/
4755	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
4756	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
4757
4758	/**
4759	* Check if an SVM write CRx intercept is set.
4760	*/
4761	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
4762	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
4763
4764	/**
4765	* Check if an SVM read DRx intercept is set.
4766	*/
4767	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
4768	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
4769
4770	/**
4771	* Check if an SVM write DRx intercept is set.
4772	*/
4773	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
4774	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
4775
4776	/**
4777	* Check if an SVM exception intercept is set.
4778	*/
4779	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) \
4780	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmXcptInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uVector)))
4781
4782	/**
4783	* Invokes the SVM \#VMEXIT handler for the nested-guest.
4784	*/
4785	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
4786	do { return iemSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2)); } while (0)
4787
4788	/**
4789	* Invokes the 'MOV CRx' SVM \#VMEXIT handler after constructing the
4790	* corresponding decode assist information.
4791	*/
4792	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) \
4793	do \
4794	{ \
4795	uint64_t uExitInfo1; \
4796	if ( IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmDecodeAssists \
4797	&& (a_enmAccessCrX) == IEMACCESSCRX_MOV_CRX) \
4798	uExitInfo1 = SVM_EXIT1_MOV_CRX_MASK \| ((a_iGReg) & 7); \
4799	else \
4800	uExitInfo1 = 0; \
4801	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, uExitInfo1, 0); \
4802	} while (0)
4803
4804	/** Check and handles SVM nested-guest instruction intercept and updates
4805	* NRIP if needed.
4806	*/
4807	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
4808	do \
4809	{ \
4810	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept)) \
4811	{ \
4812	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
4813	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2); \
4814	} \
4815	} while (0)
4816
4817	/** Checks and handles SVM nested-guest CR0 read intercept. */
4818	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
4819	do \
4820	{ \
4821	if (!IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, 0)) \
4822	{ /* probably likely */ } \
4823	else \
4824	{ \
4825	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
4826	IEM_SVM_VMEXIT_RET(a_pVCpu, SVM_EXIT_READ_CR0, a_uExitInfo1, a_uExitInfo2); \
4827	} \
4828	} while (0)
4829
4830	/**
4831	* Updates the NextRIP (NRI) field in the nested-guest VMCB.
4832	*/
4833	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) \
4834	do { \
4835	if (IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmNextRipSave) \
4836	CPUMGuestSvmUpdateNRip(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_cbInstr)); \
4837	} while (0)
4838
4839	#else
4840	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) (false)
4841	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
4842	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
4843	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
4844	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
4845	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) (false)
4846	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { return VERR_SVM_IPE_1; } while (0)
4847	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) do { return VERR_SVM_IPE_1; } while (0)
4848	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, \
4849	a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
4850	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
4851	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) do { } while (0)
4852
4853	#endif
4854
4855	/** @} */
4856
4857	uint32_t iemCalcExecDbgFlagsSlow(PVMCPUCC pVCpu);
4858	VBOXSTRICTRC iemExecInjectPendingTrap(PVMCPUCC pVCpu);
4859
4860
4861	/**
4862	* Selector descriptor table entry as fetched by iemMemFetchSelDesc.
4863	*/
4864	typedef union IEMSELDESC
4865	{
4866	/** The legacy view. */
4867	X86DESC Legacy;
4868	/** The long mode view. */
4869	X86DESC64 Long;
4870	} IEMSELDESC;
4871	/** Pointer to a selector descriptor table entry. */
4872	typedef IEMSELDESC *PIEMSELDESC;
4873
4874	/** @name Raising Exceptions.
4875	* @{ */
4876	VBOXSTRICTRC iemTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, uint32_t uNextEip, uint32_t fFlags,
4877	uint16_t uErr, uint64_t uCr2, RTSEL SelTSS, PIEMSELDESC pNewDescTSS) RT_NOEXCEPT;
4878
4879	VBOXSTRICTRC iemRaiseXcptOrInt(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags,
4880	uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
4881	#ifdef IEM_WITH_SETJMP
4882	DECL_NO_RETURN(void) iemRaiseXcptOrIntJmp(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector,
4883	uint32_t fFlags, uint16_t uErr, uint64_t uCr2) IEM_NOEXCEPT_MAY_LONGJMP;
4884	#endif
4885	VBOXSTRICTRC iemRaiseDivideError(PVMCPUCC pVCpu) RT_NOEXCEPT;
4886	VBOXSTRICTRC iemRaiseDebugException(PVMCPUCC pVCpu) RT_NOEXCEPT;
4887	VBOXSTRICTRC iemRaiseBoundRangeExceeded(PVMCPUCC pVCpu) RT_NOEXCEPT;
4888	VBOXSTRICTRC iemRaiseUndefinedOpcode(PVMCPUCC pVCpu) RT_NOEXCEPT;
4889	VBOXSTRICTRC iemRaiseDeviceNotAvailable(PVMCPUCC pVCpu) RT_NOEXCEPT;
4890	VBOXSTRICTRC iemRaiseTaskSwitchFaultWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
4891	VBOXSTRICTRC iemRaiseTaskSwitchFaultCurrentTSS(PVMCPUCC pVCpu) RT_NOEXCEPT;
4892	VBOXSTRICTRC iemRaiseTaskSwitchFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
4893	VBOXSTRICTRC iemRaiseTaskSwitchFaultBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
4894	/VBOXSTRICTRC iemRaiseSelectorNotPresent(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;/
4895	VBOXSTRICTRC iemRaiseSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
4896	VBOXSTRICTRC iemRaiseSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
4897	VBOXSTRICTRC iemRaiseStackSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
4898	VBOXSTRICTRC iemRaiseStackSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
4899	VBOXSTRICTRC iemRaiseGeneralProtectionFault(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
4900	VBOXSTRICTRC iemRaiseGeneralProtectionFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
4901	#ifdef IEM_WITH_SETJMP
4902	DECL_NO_RETURN(void) iemRaiseGeneralProtectionFault0Jmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4903	#endif
4904	VBOXSTRICTRC iemRaiseGeneralProtectionFaultBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
4905	VBOXSTRICTRC iemRaiseNotCanonical(PVMCPUCC pVCpu) RT_NOEXCEPT;
4906	VBOXSTRICTRC iemRaiseSelectorBounds(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
4907	#ifdef IEM_WITH_SETJMP
4908	DECL_NO_RETURN(void) iemRaiseSelectorBoundsJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
4909	#endif
4910	VBOXSTRICTRC iemRaiseSelectorBoundsBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
4911	#ifdef IEM_WITH_SETJMP
4912	DECL_NO_RETURN(void) iemRaiseSelectorBoundsBySelectorJmp(PVMCPUCC pVCpu, RTSEL Sel) IEM_NOEXCEPT_MAY_LONGJMP;
4913	#endif
4914	VBOXSTRICTRC iemRaiseSelectorInvalidAccess(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
4915	#ifdef IEM_WITH_SETJMP
4916	DECL_NO_RETURN(void) iemRaiseSelectorInvalidAccessJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
4917	#endif
4918	VBOXSTRICTRC iemRaisePageFault(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) RT_NOEXCEPT;
4919	#ifdef IEM_WITH_SETJMP
4920	DECL_NO_RETURN(void) iemRaisePageFaultJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) IEM_NOEXCEPT_MAY_LONGJMP;
4921	#endif
4922	VBOXSTRICTRC iemRaiseMathFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
4923	VBOXSTRICTRC iemRaiseAlignmentCheckException(PVMCPUCC pVCpu) RT_NOEXCEPT;
4924	#ifdef IEM_WITH_SETJMP
4925	DECL_NO_RETURN(void) iemRaiseAlignmentCheckExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4926	#endif
4927	VBOXSTRICTRC iemRaiseSimdFpException(PVMCPUCC pVCpu) RT_NOEXCEPT;
4928
4929	void iemLogSyscallProtModeInt(PVMCPUCC pVCpu, uint8_t u8Vector, uint8_t cbInstr);
4930
4931	IEM_CIMPL_DEF_0(iemCImplRaiseDivideError);
4932	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidLockPrefix);
4933	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidOpcode);
4934
4935	/**
4936	* Macro for calling iemCImplRaiseDivideError().
4937	*
4938	* This is for things that will _always_ decode to an \#DE, taking the
4939	* recompiler into consideration and everything.
4940	*
4941	* @return Strict VBox status code.
4942	*/
4943	#define IEMOP_RAISE_DIVIDE_ERROR_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseDivideError)
4944
4945	/**
4946	* Macro for calling iemCImplRaiseInvalidLockPrefix().
4947	*
4948	* This is for things that will _always_ decode to an \#UD, taking the
4949	* recompiler into consideration and everything.
4950	*
4951	* @return Strict VBox status code.
4952	*/
4953	#define IEMOP_RAISE_INVALID_LOCK_PREFIX_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidLockPrefix)
4954
4955	/**
4956	* Macro for calling iemCImplRaiseInvalidOpcode() for decode/static \#UDs.
4957	*
4958	* This is for things that will _always_ decode to an \#UD, taking the
4959	* recompiler into consideration and everything.
4960	*
4961	* @return Strict VBox status code.
4962	*/
4963	#define IEMOP_RAISE_INVALID_OPCODE_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidOpcode)
4964
4965	/**
4966	* Macro for calling iemCImplRaiseInvalidOpcode() for runtime-style \#UDs.
4967	*
4968	* Using this macro means you've got _buggy_ _code_ and are doing things that
4969	* belongs exclusively in IEMAllCImpl.cpp during decoding.
4970	*
4971	* @return Strict VBox status code.
4972	* @see IEMOP_RAISE_INVALID_OPCODE_RET
4973	*/
4974	#define IEMOP_RAISE_INVALID_OPCODE_RUNTIME_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidOpcode)
4975
4976	/** @} */
4977
4978	/** @name Register Access.
4979	* @{ */
4980	VBOXSTRICTRC iemRegRipRelativeJumpS8AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int8_t offNextInstr,
4981	IEMMODE enmEffOpSize) RT_NOEXCEPT;
4982	VBOXSTRICTRC iemRegRipRelativeJumpS16AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int16_t offNextInstr) RT_NOEXCEPT;
4983	VBOXSTRICTRC iemRegRipRelativeJumpS32AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int32_t offNextInstr,
4984	IEMMODE enmEffOpSize) RT_NOEXCEPT;
4985	VBOXSTRICTRC iemRegRipJumpU16AndFinishClearningRF(PVMCPUCC pVCpu, uint16_t uNewRip) RT_NOEXCEPT;
4986	VBOXSTRICTRC iemRegRipJumpU32AndFinishClearningRF(PVMCPUCC pVCpu, uint32_t uNewRip) RT_NOEXCEPT;
4987	VBOXSTRICTRC iemRegRipJumpU64AndFinishClearningRF(PVMCPUCC pVCpu, uint64_t uNewRip) RT_NOEXCEPT;
4988	/** @} */
4989
4990	/** @name FPU access and helpers.
4991	* @{ */
4992	void iemFpuPushResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
4993	void iemFpuPushResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4994	void iemFpuPushResultTwo(PVMCPUCC pVCpu, PIEMFPURESULTTWO pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
4995	void iemFpuStoreResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
4996	void iemFpuStoreResultThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
4997	void iemFpuStoreResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
4998	uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
4999	void iemFpuStoreResultWithMemOpThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
5000	uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5001	void iemFpuUpdateOpcodeAndIp(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5002	void iemFpuUpdateFSW(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
5003	void iemFpuUpdateFSWThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
5004	void iemFpuUpdateFSWWithMemOp(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5005	void iemFpuUpdateFSWThenPopPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
5006	void iemFpuUpdateFSWWithMemOpThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5007	void iemFpuStackUnderflow(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
5008	void iemFpuStackUnderflowWithMemOp(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5009	void iemFpuStackUnderflowThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
5010	void iemFpuStackUnderflowWithMemOpThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5011	void iemFpuStackUnderflowThenPopPop(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5012	void iemFpuStackPushUnderflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5013	void iemFpuStackPushUnderflowTwo(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5014	void iemFpuStackPushOverflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5015	void iemFpuStackPushOverflowWithMemOp(PVMCPUCC pVCpu, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5016	/** @} */
5017
5018	/** @name SSE+AVX SIMD access and helpers.
5019	* @{ */
5020	void iemSseStoreResult(PVMCPUCC pVCpu, PCIEMSSERESULT pResult, uint8_t iXmmReg) RT_NOEXCEPT;
5021	void iemSseUpdateMxcsr(PVMCPUCC pVCpu, uint32_t fMxcsr) RT_NOEXCEPT;
5022	/** @} */
5023
5024	/** @name Memory access.
5025	* @{ */
5026
5027	/** Report a \#GP instead of \#AC and do not restrict to ring-3 */
5028	#define IEM_MEMMAP_F_ALIGN_GP RT_BIT_32(16)
5029	/** SSE access that should report a \#GP instead of \#AC, unless MXCSR.MM=1
5030	* when it works like normal \#AC. Always used with IEM_MEMMAP_F_ALIGN_GP. */
5031	#define IEM_MEMMAP_F_ALIGN_SSE RT_BIT_32(17)
5032	/** If \#AC is applicable, raise it. Always used with IEM_MEMMAP_F_ALIGN_GP.
5033	* Users include FXSAVE & FXRSTOR. */
5034	#define IEM_MEMMAP_F_ALIGN_GP_OR_AC RT_BIT_32(18)
5035
5036	VBOXSTRICTRC iemMemMap(PVMCPUCC pVCpu, void **ppvMem, size_t cbMem, uint8_t iSegReg, RTGCPTR GCPtrMem,
5037	uint32_t fAccess, uint32_t uAlignCtl) RT_NOEXCEPT;
5038	VBOXSTRICTRC iemMemCommitAndUnmap(PVMCPUCC pVCpu, void *pvMem, uint32_t fAccess) RT_NOEXCEPT;
5039	#ifndef IN_RING3
5040	VBOXSTRICTRC iemMemCommitAndUnmapPostponeTroubleToR3(PVMCPUCC pVCpu, void *pvMem, uint32_t fAccess) RT_NOEXCEPT;
5041	#endif
5042	void iemMemRollback(PVMCPUCC pVCpu) RT_NOEXCEPT;
5043	VBOXSTRICTRC iemMemApplySegment(PVMCPUCC pVCpu, uint32_t fAccess, uint8_t iSegReg, size_t cbMem, PRTGCPTR pGCPtrMem) RT_NOEXCEPT;
5044	VBOXSTRICTRC iemMemMarkSelDescAccessed(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5045	VBOXSTRICTRC iemMemPageTranslateAndCheckAccess(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t cbAccess, uint32_t fAccess, PRTGCPHYS pGCPhysMem) RT_NOEXCEPT;
5046
5047	void iemOpcodeFlushLight(PVMCPUCC pVCpu, uint8_t cbInstr);
5048	void iemOpcodeFlushHeavy(PVMCPUCC pVCpu, uint8_t cbInstr);
5049	#ifdef IEM_WITH_CODE_TLB
5050	void iemOpcodeFetchBytesJmp(PVMCPUCC pVCpu, size_t cbDst, void *pvDst) IEM_NOEXCEPT_MAY_LONGJMP;
5051	#else
5052	VBOXSTRICTRC iemOpcodeFetchMoreBytes(PVMCPUCC pVCpu, size_t cbMin) RT_NOEXCEPT;
5053	#endif
5054	#ifdef IEM_WITH_SETJMP
5055	uint8_t iemOpcodeGetNextU8SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5056	uint16_t iemOpcodeGetNextU16SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5057	uint32_t iemOpcodeGetNextU32SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5058	uint64_t iemOpcodeGetNextU64SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5059	#else
5060	VBOXSTRICTRC iemOpcodeGetNextU8Slow(PVMCPUCC pVCpu, uint8_t *pb) RT_NOEXCEPT;
5061	VBOXSTRICTRC iemOpcodeGetNextS8SxU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
5062	VBOXSTRICTRC iemOpcodeGetNextS8SxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
5063	VBOXSTRICTRC iemOpcodeGetNextS8SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5064	VBOXSTRICTRC iemOpcodeGetNextU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
5065	VBOXSTRICTRC iemOpcodeGetNextU16ZxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
5066	VBOXSTRICTRC iemOpcodeGetNextU16ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5067	VBOXSTRICTRC iemOpcodeGetNextU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
5068	VBOXSTRICTRC iemOpcodeGetNextU32ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5069	VBOXSTRICTRC iemOpcodeGetNextS32SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5070	VBOXSTRICTRC iemOpcodeGetNextU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5071	#endif
5072
5073	VBOXSTRICTRC iemMemFetchDataU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5074	VBOXSTRICTRC iemMemFetchDataU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5075	VBOXSTRICTRC iemMemFetchDataU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5076	VBOXSTRICTRC iemMemFetchDataU32_ZX_U64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5077	VBOXSTRICTRC iemMemFetchDataU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5078	VBOXSTRICTRC iemMemFetchDataU64AlignedU128(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5079	VBOXSTRICTRC iemMemFetchDataR80(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5080	VBOXSTRICTRC iemMemFetchDataD80(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5081	VBOXSTRICTRC iemMemFetchDataU128(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5082	VBOXSTRICTRC iemMemFetchDataU128AlignedSse(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5083	VBOXSTRICTRC iemMemFetchDataU256(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5084	VBOXSTRICTRC iemMemFetchDataU256AlignedSse(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5085	VBOXSTRICTRC iemMemFetchDataXdtr(PVMCPUCC pVCpu, uint16_t *pcbLimit, PRTGCPTR pGCPtrBase, uint8_t iSegReg,
5086	RTGCPTR GCPtrMem, IEMMODE enmOpSize) RT_NOEXCEPT;
5087	#ifdef IEM_WITH_SETJMP
5088	uint8_t iemMemFetchDataU8SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5089	uint16_t iemMemFetchDataU16SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5090	uint32_t iemMemFetchDataU32SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5091	uint32_t iemMemFlatFetchDataU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5092	uint64_t iemMemFetchDataU64SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5093	uint64_t iemMemFetchDataU64AlignedU128SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5094	void iemMemFetchDataR80SafeJmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5095	void iemMemFetchDataD80SafeJmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5096	void iemMemFetchDataU128SafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5097	void iemMemFetchDataU128AlignedSseSafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5098	void iemMemFetchDataU256SafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5099	void iemMemFetchDataU256AlignedSseSafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5100	# if 0 /* these are inlined now */
5101	uint8_t iemMemFetchDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5102	uint16_t iemMemFetchDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5103	uint32_t iemMemFetchDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5104	uint32_t iemMemFlatFetchDataU32Jmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5105	uint64_t iemMemFetchDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5106	uint64_t iemMemFetchDataU64AlignedU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5107	# endif
5108	void iemMemFetchDataR80Jmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5109	void iemMemFetchDataD80Jmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5110	void iemMemFetchDataU128Jmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5111	void iemMemFetchDataU128AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5112	void iemMemFetchDataU256Jmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5113	void iemMemFetchDataU256AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5114	#endif
5115
5116	VBOXSTRICTRC iemMemFetchSysU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5117	VBOXSTRICTRC iemMemFetchSysU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5118	VBOXSTRICTRC iemMemFetchSysU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5119	VBOXSTRICTRC iemMemFetchSysU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5120	VBOXSTRICTRC iemMemFetchSelDesc(PVMCPUCC pVCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt) RT_NOEXCEPT;
5121
5122	VBOXSTRICTRC iemMemStoreDataU8(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) RT_NOEXCEPT;
5123	VBOXSTRICTRC iemMemStoreDataU16(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) RT_NOEXCEPT;
5124	VBOXSTRICTRC iemMemStoreDataU32(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) RT_NOEXCEPT;
5125	VBOXSTRICTRC iemMemStoreDataU64(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) RT_NOEXCEPT;
5126	VBOXSTRICTRC iemMemStoreDataU128(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
5127	VBOXSTRICTRC iemMemStoreDataU128AlignedSse(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
5128	VBOXSTRICTRC iemMemStoreDataU256(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
5129	VBOXSTRICTRC iemMemStoreDataU256AlignedAvx(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
5130	VBOXSTRICTRC iemMemStoreDataXdtr(PVMCPUCC pVCpu, uint16_t cbLimit, RTGCPTR GCPtrBase, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5131	#ifdef IEM_WITH_SETJMP
5132	void iemMemStoreDataU8SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
5133	void iemMemStoreDataU16SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
5134	void iemMemStoreDataU32SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
5135	void iemMemStoreDataU64SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
5136	void iemMemStoreDataU128SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5137	void iemMemStoreDataU128AlignedSseSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5138	void iemMemStoreDataU256SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5139	void iemMemStoreDataU256AlignedAvxSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5140	#if 0
5141	void iemMemStoreDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
5142	void iemMemStoreDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
5143	void iemMemStoreDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
5144	void iemMemStoreDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
5145	#endif
5146	void iemMemStoreDataU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5147	void iemMemStoreDataU128AlignedSseJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5148	void iemMemStoreDataU256Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5149	void iemMemStoreDataU256AlignedAvxJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5150	#endif
5151
5152	#ifdef IEM_WITH_SETJMP
5153	uint8_t iemMemMapDataU8RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5154	uint8_t iemMemMapDataU8WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5155	uint8_t const iemMemMapDataU8RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5156	uint16_t iemMemMapDataU16RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5157	uint16_t iemMemMapDataU16WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5158	uint16_t const iemMemMapDataU16RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5159	uint32_t iemMemMapDataU32RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5160	uint32_t iemMemMapDataU32WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5161	uint32_t const iemMemMapDataU32RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5162	uint64_t iemMemMapDataU64RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5163	uint64_t iemMemMapDataU64WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5164	uint64_t const iemMemMapDataU64RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5165
5166	void iemMemCommitAndUnmapRwSafeJmp(PVMCPUCC pVCpu, void *pvMem, uint8_t bMapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5167	void iemMemCommitAndUnmapWoSafeJmp(PVMCPUCC pVCpu, void *pvMem, uint8_t bMapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5168	void iemMemCommitAndUnmapRoSafeJmp(PVMCPUCC pVCpu, const void *pvMem, uint8_t bMapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5169	#endif
5170
5171	VBOXSTRICTRC iemMemStackPushBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
5172	void *ppvMem, uint64_t puNewRsp) RT_NOEXCEPT;
5173	VBOXSTRICTRC iemMemStackPushCommitSpecial(PVMCPUCC pVCpu, void *pvMem, uint64_t uNewRsp) RT_NOEXCEPT;
5174	VBOXSTRICTRC iemMemStackPushU16(PVMCPUCC pVCpu, uint16_t u16Value) RT_NOEXCEPT;
5175	VBOXSTRICTRC iemMemStackPushU32(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
5176	VBOXSTRICTRC iemMemStackPushU64(PVMCPUCC pVCpu, uint64_t u64Value) RT_NOEXCEPT;
5177	VBOXSTRICTRC iemMemStackPushU16Ex(PVMCPUCC pVCpu, uint16_t u16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5178	VBOXSTRICTRC iemMemStackPushU32Ex(PVMCPUCC pVCpu, uint32_t u32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5179	VBOXSTRICTRC iemMemStackPushU64Ex(PVMCPUCC pVCpu, uint64_t u64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5180	VBOXSTRICTRC iemMemStackPushU32SReg(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
5181	VBOXSTRICTRC iemMemStackPopBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
5182	void const *ppvMem, uint64_t puNewRsp) RT_NOEXCEPT;
5183	VBOXSTRICTRC iemMemStackPopContinueSpecial(PVMCPUCC pVCpu, size_t off, size_t cbMem,
5184	void const **ppvMem, uint64_t uCurNewRsp) RT_NOEXCEPT;
5185	VBOXSTRICTRC iemMemStackPopDoneSpecial(PVMCPUCC pVCpu, void const *pvMem) RT_NOEXCEPT;
5186	VBOXSTRICTRC iemMemStackPopU16(PVMCPUCC pVCpu, uint16_t *pu16Value) RT_NOEXCEPT;
5187	VBOXSTRICTRC iemMemStackPopU32(PVMCPUCC pVCpu, uint32_t *pu32Value) RT_NOEXCEPT;
5188	VBOXSTRICTRC iemMemStackPopU64(PVMCPUCC pVCpu, uint64_t *pu64Value) RT_NOEXCEPT;
5189	VBOXSTRICTRC iemMemStackPopU16Ex(PVMCPUCC pVCpu, uint16_t *pu16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5190	VBOXSTRICTRC iemMemStackPopU32Ex(PVMCPUCC pVCpu, uint32_t *pu32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5191	VBOXSTRICTRC iemMemStackPopU64Ex(PVMCPUCC pVCpu, uint64_t *pu64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5192
5193	#ifdef IEM_WITH_SETJMP
5194	void iemMemStackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5195	void iemMemStackPushU32SafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5196	void iemMemStackPushU32SRegSafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5197	void iemMemStackPushU64SafeJmp(PVMCPUCC pVCpu, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5198	uint16_t iemMemStackPopU16SafeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5199	uint32_t iemMemStackPopU32SafeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5200	uint64_t iemMemStackPopU64SafeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5201
5202	void iemMemFlat32StackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5203	void iemMemFlat32StackPushU32SafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5204	void iemMemFlat32StackPushU32SRegSafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5205	uint16_t iemMemFlat32StackPopU16SafeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5206	uint32_t iemMemFlat32StackPopU32SafeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5207
5208	void iemMemFlat64StackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5209	void iemMemFlat64StackPushU64SafeJmp(PVMCPUCC pVCpu, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5210	uint16_t iemMemFlat64StackPopU16SafeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5211	uint64_t iemMemFlat64StackPopU64SafeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5212	#endif
5213
5214	/** @} */
5215
5216	/** @name IEMAllCImpl.cpp
5217	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/'
5218	* @{ */
5219	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem16, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5220	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem32, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5221	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem64, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5222	IEM_CIMPL_PROTO_0(iemCImpl_popa_16);
5223	IEM_CIMPL_PROTO_0(iemCImpl_popa_32);
5224	IEM_CIMPL_PROTO_0(iemCImpl_pusha_16);
5225	IEM_CIMPL_PROTO_0(iemCImpl_pusha_32);
5226	IEM_CIMPL_PROTO_1(iemCImpl_pushf, IEMMODE, enmEffOpSize);
5227	IEM_CIMPL_PROTO_1(iemCImpl_popf, IEMMODE, enmEffOpSize);
5228	IEM_CIMPL_PROTO_1(iemCImpl_call_16, uint16_t, uNewPC);
5229	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_16, int16_t, offDisp);
5230	IEM_CIMPL_PROTO_1(iemCImpl_call_32, uint32_t, uNewPC);
5231	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_32, int32_t, offDisp);
5232	IEM_CIMPL_PROTO_1(iemCImpl_call_64, uint64_t, uNewPC);
5233	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_64, int64_t, offDisp);
5234	IEM_CIMPL_PROTO_3(iemCImpl_FarJmp, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
5235	IEM_CIMPL_PROTO_3(iemCImpl_callf, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
5236	typedef IEM_CIMPL_DECL_TYPE_3(FNIEMCIMPLFARBRANCH, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
5237	typedef FNIEMCIMPLFARBRANCH *PFNIEMCIMPLFARBRANCH;
5238	IEM_CIMPL_PROTO_2(iemCImpl_retf, IEMMODE, enmEffOpSize, uint16_t, cbPop);
5239	IEM_CIMPL_PROTO_0(iemCImpl_retn_16);
5240	IEM_CIMPL_PROTO_0(iemCImpl_retn_32);
5241	IEM_CIMPL_PROTO_0(iemCImpl_retn_64);
5242	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_16, uint16_t, cbPop);
5243	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_32, uint16_t, cbPop);
5244	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_64, uint16_t, cbPop);
5245	IEM_CIMPL_PROTO_3(iemCImpl_enter, IEMMODE, enmEffOpSize, uint16_t, cbFrame, uint8_t, cParameters);
5246	IEM_CIMPL_PROTO_1(iemCImpl_leave, IEMMODE, enmEffOpSize);
5247	IEM_CIMPL_PROTO_2(iemCImpl_int, uint8_t, u8Int, IEMINT, enmInt);
5248	IEM_CIMPL_PROTO_1(iemCImpl_iret_real_v8086, IEMMODE, enmEffOpSize);
5249	IEM_CIMPL_PROTO_4(iemCImpl_iret_prot_v8086, uint32_t, uNewEip, uint16_t, uNewCs, uint32_t, uNewFlags, uint64_t, uNewRsp);
5250	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot_NestedTask, IEMMODE, enmEffOpSize);
5251	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot, IEMMODE, enmEffOpSize);
5252	IEM_CIMPL_PROTO_1(iemCImpl_iret_64bit, IEMMODE, enmEffOpSize);
5253	IEM_CIMPL_PROTO_1(iemCImpl_iret, IEMMODE, enmEffOpSize);
5254	IEM_CIMPL_PROTO_0(iemCImpl_loadall286);
5255	IEM_CIMPL_PROTO_0(iemCImpl_syscall);
5256	IEM_CIMPL_PROTO_1(iemCImpl_sysret, IEMMODE, enmEffOpSize);
5257	IEM_CIMPL_PROTO_0(iemCImpl_sysenter);
5258	IEM_CIMPL_PROTO_1(iemCImpl_sysexit, IEMMODE, enmEffOpSize);
5259	IEM_CIMPL_PROTO_2(iemCImpl_LoadSReg, uint8_t, iSegReg, uint16_t, uSel);
5260	IEM_CIMPL_PROTO_2(iemCImpl_load_SReg, uint8_t, iSegReg, uint16_t, uSel);
5261	IEM_CIMPL_PROTO_2(iemCImpl_pop_Sreg, uint8_t, iSegReg, IEMMODE, enmEffOpSize);
5262	IEM_CIMPL_PROTO_5(iemCImpl_load_SReg_Greg, uint16_t, uSel, uint64_t, offSeg, uint8_t, iSegReg, uint8_t, iGReg, IEMMODE, enmEffOpSize);
5263	IEM_CIMPL_PROTO_2(iemCImpl_VerX, uint16_t, uSel, bool, fWrite);
5264	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u64, uint64_t *, pu64Dst, uint16_t, uSel, bool, fIsLar);
5265	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u16, uint16_t *, pu16Dst, uint16_t, uSel, bool, fIsLar);
5266	IEM_CIMPL_PROTO_3(iemCImpl_lgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
5267	IEM_CIMPL_PROTO_2(iemCImpl_sgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5268	IEM_CIMPL_PROTO_3(iemCImpl_lidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
5269	IEM_CIMPL_PROTO_2(iemCImpl_sidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5270	IEM_CIMPL_PROTO_1(iemCImpl_lldt, uint16_t, uNewLdt);
5271	IEM_CIMPL_PROTO_2(iemCImpl_sldt_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
5272	IEM_CIMPL_PROTO_2(iemCImpl_sldt_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5273	IEM_CIMPL_PROTO_1(iemCImpl_ltr, uint16_t, uNewTr);
5274	IEM_CIMPL_PROTO_2(iemCImpl_str_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
5275	IEM_CIMPL_PROTO_2(iemCImpl_str_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5276	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Cd, uint8_t, iGReg, uint8_t, iCrReg);
5277	IEM_CIMPL_PROTO_2(iemCImpl_smsw_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
5278	IEM_CIMPL_PROTO_2(iemCImpl_smsw_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5279	IEM_CIMPL_PROTO_4(iemCImpl_load_CrX, uint8_t, iCrReg, uint64_t, uNewCrX, IEMACCESSCRX, enmAccessCrX, uint8_t, iGReg);
5280	IEM_CIMPL_PROTO_2(iemCImpl_mov_Cd_Rd, uint8_t, iCrReg, uint8_t, iGReg);
5281	IEM_CIMPL_PROTO_2(iemCImpl_lmsw, uint16_t, u16NewMsw, RTGCPTR, GCPtrEffDst);
5282	IEM_CIMPL_PROTO_0(iemCImpl_clts);
5283	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Dd, uint8_t, iGReg, uint8_t, iDrReg);
5284	IEM_CIMPL_PROTO_2(iemCImpl_mov_Dd_Rd, uint8_t, iDrReg, uint8_t, iGReg);
5285	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Td, uint8_t, iGReg, uint8_t, iTrReg);
5286	IEM_CIMPL_PROTO_2(iemCImpl_mov_Td_Rd, uint8_t, iTrReg, uint8_t, iGReg);
5287	IEM_CIMPL_PROTO_1(iemCImpl_invlpg, RTGCPTR, GCPtrPage);
5288	IEM_CIMPL_PROTO_3(iemCImpl_invpcid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvpcidDesc, uint64_t, uInvpcidType);
5289	IEM_CIMPL_PROTO_0(iemCImpl_invd);
5290	IEM_CIMPL_PROTO_0(iemCImpl_wbinvd);
5291	IEM_CIMPL_PROTO_0(iemCImpl_rsm);
5292	IEM_CIMPL_PROTO_0(iemCImpl_rdtsc);
5293	IEM_CIMPL_PROTO_0(iemCImpl_rdtscp);
5294	IEM_CIMPL_PROTO_0(iemCImpl_rdpmc);
5295	IEM_CIMPL_PROTO_0(iemCImpl_rdmsr);
5296	IEM_CIMPL_PROTO_0(iemCImpl_wrmsr);
5297	IEM_CIMPL_PROTO_3(iemCImpl_in, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
5298	IEM_CIMPL_PROTO_2(iemCImpl_in_eAX_DX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
5299	IEM_CIMPL_PROTO_3(iemCImpl_out, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
5300	IEM_CIMPL_PROTO_2(iemCImpl_out_DX_eAX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
5301	IEM_CIMPL_PROTO_0(iemCImpl_cli);
5302	IEM_CIMPL_PROTO_0(iemCImpl_sti);
5303	IEM_CIMPL_PROTO_0(iemCImpl_hlt);
5304	IEM_CIMPL_PROTO_1(iemCImpl_monitor, uint8_t, iEffSeg);
5305	IEM_CIMPL_PROTO_0(iemCImpl_mwait);
5306	IEM_CIMPL_PROTO_0(iemCImpl_swapgs);
5307	IEM_CIMPL_PROTO_0(iemCImpl_cpuid);
5308	IEM_CIMPL_PROTO_1(iemCImpl_aad, uint8_t, bImm);
5309	IEM_CIMPL_PROTO_1(iemCImpl_aam, uint8_t, bImm);
5310	IEM_CIMPL_PROTO_0(iemCImpl_daa);
5311	IEM_CIMPL_PROTO_0(iemCImpl_das);
5312	IEM_CIMPL_PROTO_0(iemCImpl_aaa);
5313	IEM_CIMPL_PROTO_0(iemCImpl_aas);
5314	IEM_CIMPL_PROTO_3(iemCImpl_bound_16, int16_t, idxArray, int16_t, idxLowerBound, int16_t, idxUpperBound);
5315	IEM_CIMPL_PROTO_3(iemCImpl_bound_32, int32_t, idxArray, int32_t, idxLowerBound, int32_t, idxUpperBound);
5316	IEM_CIMPL_PROTO_0(iemCImpl_xgetbv);
5317	IEM_CIMPL_PROTO_0(iemCImpl_xsetbv);
5318	IEM_CIMPL_PROTO_4(iemCImpl_cmpxchg16b_fallback_rendezvous, PRTUINT128U, pu128Dst, PRTUINT128U, pu128RaxRdx,
5319	PRTUINT128U, pu128RbxRcx, uint32_t *, pEFlags);
5320	IEM_CIMPL_PROTO_2(iemCImpl_clflush_clflushopt, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5321	IEM_CIMPL_PROTO_1(iemCImpl_finit, bool, fCheckXcpts);
5322	IEM_CIMPL_PROTO_3(iemCImpl_fxsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5323	IEM_CIMPL_PROTO_3(iemCImpl_fxrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5324	IEM_CIMPL_PROTO_3(iemCImpl_xsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5325	IEM_CIMPL_PROTO_3(iemCImpl_xrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5326	IEM_CIMPL_PROTO_2(iemCImpl_stmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5327	IEM_CIMPL_PROTO_2(iemCImpl_vstmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5328	IEM_CIMPL_PROTO_2(iemCImpl_ldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5329	IEM_CIMPL_PROTO_3(iemCImpl_fnstenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5330	IEM_CIMPL_PROTO_3(iemCImpl_fnsave, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5331	IEM_CIMPL_PROTO_3(iemCImpl_fldenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
5332	IEM_CIMPL_PROTO_3(iemCImpl_frstor, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
5333	IEM_CIMPL_PROTO_1(iemCImpl_fldcw, uint16_t, u16Fcw);
5334	IEM_CIMPL_PROTO_2(iemCImpl_fxch_underflow, uint8_t, iStReg, uint16_t, uFpuOpcode);
5335	IEM_CIMPL_PROTO_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, bool, fUCmp, uint32_t, uPopAndFpuOpcode);
5336	IEM_CIMPL_PROTO_2(iemCImpl_rdseed, uint8_t, iReg, IEMMODE, enmEffOpSize);
5337	IEM_CIMPL_PROTO_2(iemCImpl_rdrand, uint8_t, iReg, IEMMODE, enmEffOpSize);
5338	/** @} */
5339
5340	/** @name IEMAllCImplStrInstr.cpp.h
5341	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/' -e 's/RT_CONCAT4(//' \
5342	* -e 's/,ADDR_SIZE)/64/g' -e 's/,OP_SIZE,/64/g' -e 's/,OP_rAX,/rax/g' IEMAllCImplStrInstr.cpp.h
5343	* @{ */
5344	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr16, uint8_t, iEffSeg);
5345	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr16, uint8_t, iEffSeg);
5346	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m16);
5347	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m16);
5348	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr16, uint8_t, iEffSeg);
5349	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m16);
5350	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m16, int8_t, iEffSeg);
5351	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr16, bool, fIoChecked);
5352	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr16, bool, fIoChecked);
5353	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5354	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5355
5356	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr16, uint8_t, iEffSeg);
5357	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr16, uint8_t, iEffSeg);
5358	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m16);
5359	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m16);
5360	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr16, uint8_t, iEffSeg);
5361	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m16);
5362	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m16, int8_t, iEffSeg);
5363	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr16, bool, fIoChecked);
5364	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr16, bool, fIoChecked);
5365	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5366	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5367
5368	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr16, uint8_t, iEffSeg);
5369	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr16, uint8_t, iEffSeg);
5370	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m16);
5371	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m16);
5372	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr16, uint8_t, iEffSeg);
5373	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m16);
5374	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m16, int8_t, iEffSeg);
5375	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr16, bool, fIoChecked);
5376	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr16, bool, fIoChecked);
5377	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5378	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5379
5380
5381	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr32, uint8_t, iEffSeg);
5382	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr32, uint8_t, iEffSeg);
5383	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m32);
5384	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m32);
5385	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr32, uint8_t, iEffSeg);
5386	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m32);
5387	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m32, int8_t, iEffSeg);
5388	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr32, bool, fIoChecked);
5389	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr32, bool, fIoChecked);
5390	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5391	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5392
5393	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr32, uint8_t, iEffSeg);
5394	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr32, uint8_t, iEffSeg);
5395	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m32);
5396	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m32);
5397	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr32, uint8_t, iEffSeg);
5398	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m32);
5399	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m32, int8_t, iEffSeg);
5400	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr32, bool, fIoChecked);
5401	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr32, bool, fIoChecked);
5402	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5403	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5404
5405	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr32, uint8_t, iEffSeg);
5406	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr32, uint8_t, iEffSeg);
5407	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m32);
5408	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m32);
5409	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr32, uint8_t, iEffSeg);
5410	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m32);
5411	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m32, int8_t, iEffSeg);
5412	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr32, bool, fIoChecked);
5413	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr32, bool, fIoChecked);
5414	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5415	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5416
5417	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr32, uint8_t, iEffSeg);
5418	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr32, uint8_t, iEffSeg);
5419	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m32);
5420	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m32);
5421	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr32, uint8_t, iEffSeg);
5422	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m32);
5423	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m32, int8_t, iEffSeg);
5424	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr32, bool, fIoChecked);
5425	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr32, bool, fIoChecked);
5426	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5427	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5428
5429
5430	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr64, uint8_t, iEffSeg);
5431	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr64, uint8_t, iEffSeg);
5432	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m64);
5433	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m64);
5434	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr64, uint8_t, iEffSeg);
5435	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m64);
5436	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m64, int8_t, iEffSeg);
5437	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr64, bool, fIoChecked);
5438	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr64, bool, fIoChecked);
5439	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5440	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5441
5442	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr64, uint8_t, iEffSeg);
5443	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr64, uint8_t, iEffSeg);
5444	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m64);
5445	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m64);
5446	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr64, uint8_t, iEffSeg);
5447	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m64);
5448	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m64, int8_t, iEffSeg);
5449	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr64, bool, fIoChecked);
5450	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr64, bool, fIoChecked);
5451	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5452	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5453
5454	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr64, uint8_t, iEffSeg);
5455	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr64, uint8_t, iEffSeg);
5456	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m64);
5457	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m64);
5458	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr64, uint8_t, iEffSeg);
5459	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m64);
5460	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m64, int8_t, iEffSeg);
5461	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr64, bool, fIoChecked);
5462	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr64, bool, fIoChecked);
5463	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5464	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5465
5466	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr64, uint8_t, iEffSeg);
5467	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr64, uint8_t, iEffSeg);
5468	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m64);
5469	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m64);
5470	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr64, uint8_t, iEffSeg);
5471	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m64);
5472	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m64, int8_t, iEffSeg);
5473	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr64, bool, fIoChecked);
5474	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr64, bool, fIoChecked);
5475	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5476	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5477	/** @} */
5478
5479	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5480	VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT;
5481	VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT;
5482	VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT;
5483	VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT;
5484	VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT;
5485	VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
5486	VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALK pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT;
5487	VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT;
5488	VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT;
5489	VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
5490	bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT;
5491	VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
5492	bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT;
5493	VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5494	VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5495	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5496	VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5497	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5498	VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5499	VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT;
5500	VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
5501	RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT;
5502	VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT;
5503	VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT;
5504	VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT;
5505	uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT;
5506	void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT;
5507	VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
5508	uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT;
5509	bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT;
5510	IEM_CIMPL_PROTO_0(iemCImpl_vmxoff);
5511	IEM_CIMPL_PROTO_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon);
5512	IEM_CIMPL_PROTO_0(iemCImpl_vmlaunch);
5513	IEM_CIMPL_PROTO_0(iemCImpl_vmresume);
5514	IEM_CIMPL_PROTO_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
5515	IEM_CIMPL_PROTO_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
5516	IEM_CIMPL_PROTO_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
5517	IEM_CIMPL_PROTO_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField);
5518	IEM_CIMPL_PROTO_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField);
5519	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField);
5520	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg32, uint64_t *, pu32Dst, uint32_t, u32VmcsField);
5521	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField);
5522	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField);
5523	IEM_CIMPL_PROTO_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType);
5524	IEM_CIMPL_PROTO_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType);
5525	IEM_CIMPL_PROTO_0(iemCImpl_vmx_pause);
5526	#endif
5527
5528	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5529	VBOXSTRICTRC iemSvmVmexit(PVMCPUCC pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2) RT_NOEXCEPT;
5530	VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr, uint64_t uCr2) RT_NOEXCEPT;
5531	VBOXSTRICTRC iemSvmHandleIOIntercept(PVMCPUCC pVCpu, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
5532	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, uint8_t cbInstr) RT_NOEXCEPT;
5533	VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPUCC pVCpu, uint32_t idMsr, bool fWrite, uint8_t cbInstr) RT_NOEXCEPT;
5534	IEM_CIMPL_PROTO_0(iemCImpl_vmrun);
5535	IEM_CIMPL_PROTO_0(iemCImpl_vmload);
5536	IEM_CIMPL_PROTO_0(iemCImpl_vmsave);
5537	IEM_CIMPL_PROTO_0(iemCImpl_clgi);
5538	IEM_CIMPL_PROTO_0(iemCImpl_stgi);
5539	IEM_CIMPL_PROTO_0(iemCImpl_invlpga);
5540	IEM_CIMPL_PROTO_0(iemCImpl_skinit);
5541	IEM_CIMPL_PROTO_0(iemCImpl_svm_pause);
5542	#endif
5543
5544	IEM_CIMPL_PROTO_0(iemCImpl_vmcall); /* vmx */
5545	IEM_CIMPL_PROTO_0(iemCImpl_vmmcall); /* svm */
5546	IEM_CIMPL_PROTO_1(iemCImpl_Hypercall, uint16_t, uDisOpcode); /* both */
5547
5548	extern const PFNIEMOP g_apfnIemInterpretOnlyOneByteMap[256];
5549	extern const PFNIEMOP g_apfnIemInterpretOnlyTwoByteMap[1024];
5550	extern const PFNIEMOP g_apfnIemInterpretOnlyThreeByte0f3a[1024];
5551	extern const PFNIEMOP g_apfnIemInterpretOnlyThreeByte0f38[1024];
5552	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap1[1024];
5553	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap2[1024];
5554	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap3[1024];
5555
5556	/*
5557	* Recompiler related stuff.
5558	*/
5559	extern const PFNIEMOP g_apfnIemThreadedRecompilerOneByteMap[256];
5560	extern const PFNIEMOP g_apfnIemThreadedRecompilerTwoByteMap[1024];
5561	extern const PFNIEMOP g_apfnIemThreadedRecompilerThreeByte0f3a[1024];
5562	extern const PFNIEMOP g_apfnIemThreadedRecompilerThreeByte0f38[1024];
5563	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap1[1024];
5564	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap2[1024];
5565	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap3[1024];
5566
5567	DECLCALLBACK(int) iemTbInit(PVMCC pVM, uint32_t cInitialTbs, uint32_t cMaxTbs,
5568	uint64_t cbInitialExec, uint64_t cbMaxExec, uint32_t cbChunkExec);
5569	void iemThreadedTbObsolete(PVMCPUCC pVCpu, PIEMTB pTb, bool fSafeToFree);
5570	void iemTbAllocatorProcessDelayedFrees(PVMCPU pVCpu, PIEMTBALLOCATOR pTbAllocator);
5571
5572
5573	/** @todo FNIEMTHREADEDFUNC and friends may need more work... */
5574	#if defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
5575	typedef VBOXSTRICTRC /__attribute__((__nothrow__))/ FNIEMTHREADEDFUNC(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
5576	typedef FNIEMTHREADEDFUNC *PFNIEMTHREADEDFUNC;
5577	# define IEM_DECL_IEMTHREADEDFUNC_DEF(a_Name) \
5578	VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2)
5579	# define IEM_DECL_IEMTHREADEDFUNC_PROTO(a_Name) \
5580	VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2)
5581
5582	#else
5583	typedef VBOXSTRICTRC (FNIEMTHREADEDFUNC)(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
5584	typedef FNIEMTHREADEDFUNC *PFNIEMTHREADEDFUNC;
5585	# define IEM_DECL_IEMTHREADEDFUNC_DEF(a_Name) \
5586	VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2) IEM_NOEXCEPT_MAY_LONGJMP
5587	# define IEM_DECL_IEMTHREADEDFUNC_PROTO(a_Name) \
5588	VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2) IEM_NOEXCEPT_MAY_LONGJMP
5589	#endif
5590
5591
5592	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_DeferToCImpl0);
5593
5594	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckIrq);
5595	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckMode);
5596	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckHwInstrBps);
5597	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLim);
5598
5599	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodes);
5600	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodes);
5601	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesConsiderCsLim);
5602
5603	/* Branching: */
5604	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndPcAndOpcodes);
5605	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckPcAndOpcodes);
5606	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckPcAndOpcodesConsiderCsLim);
5607
5608	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesLoadingTlb);
5609	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesLoadingTlb);
5610	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesLoadingTlbConsiderCsLim);
5611
5612	/* Natural page crossing: */
5613	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesAcrossPageLoadingTlb);
5614	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesAcrossPageLoadingTlb);
5615	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesAcrossPageLoadingTlbConsiderCsLim);
5616
5617	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesOnNextPageLoadingTlb);
5618	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNextPageLoadingTlb);
5619	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNextPageLoadingTlbConsiderCsLim);
5620
5621	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesOnNewPageLoadingTlb);
5622	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNewPageLoadingTlb);
5623	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNewPageLoadingTlbConsiderCsLim);
5624
5625	bool iemThreadedCompileEmitIrqCheckBefore(PVMCPUCC pVCpu, PIEMTB pTb);
5626	bool iemThreadedCompileBeginEmitCallsComplications(PVMCPUCC pVCpu, PIEMTB pTb);
5627
5628	/* Native recompiler public bits: */
5629	DECLHIDDEN(PIEMTB) iemNativeRecompile(PVMCPUCC pVCpu, PIEMTB pTb) RT_NOEXCEPT;
5630	int iemExecMemAllocatorInit(PVMCPU pVCpu, uint64_t cbMax, uint64_t cbInitial, uint32_t cbChunk);
5631	void iemExecMemAllocatorFree(PVMCPU pVCpu, void *pv, size_t cb);
5632
5633
5634	/** @} */
5635
5636	RT_C_DECLS_END
5637
5638	#endif /* !VMM_INCLUDED_SRC_include_IEMInternal_h */
5639

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source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h@ 102077

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