IEMInternal.h@ 102817

Last change on this file since 102817 was 102817, checked in by vboxsync, 13 months ago
IEM: Added RCPSS/RCPPS assembly imlementation and C stubs.
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1	/* $Id: IEMInternal.h 102817 2024-01-10 13:56:06Z vboxsync $ */
2	/** @file
3	* IEM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2011-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_IEMInternal_h
29	#define VMM_INCLUDED_SRC_include_IEMInternal_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#include <VBox/vmm/cpum.h>
35	#include <VBox/vmm/iem.h>
36	#include <VBox/vmm/pgm.h>
37	#include <VBox/vmm/stam.h>
38	#include <VBox/param.h>
39
40	#include <iprt/setjmp-without-sigmask.h>
41	#include <iprt/list.h>
42
43
44	RT_C_DECLS_BEGIN
45
46
47	/** @defgroup grp_iem_int Internals
48	* @ingroup grp_iem
49	* @internal
50	* @{
51	*/
52
53	/** For expanding symbol in slickedit and other products tagging and
54	* crossreferencing IEM symbols. */
55	#ifndef IEM_STATIC
56	# define IEM_STATIC static
57	#endif
58
59	/** @def IEM_WITH_SETJMP
60	* Enables alternative status code handling using setjmps.
61	*
62	* This adds a bit of expense via the setjmp() call since it saves all the
63	* non-volatile registers. However, it eliminates return code checks and allows
64	* for more optimal return value passing (return regs instead of stack buffer).
65	*/
66	#if defined(DOXYGEN_RUNNING) \|\| defined(RT_OS_WINDOWS) \|\| 1
67	# define IEM_WITH_SETJMP
68	#endif
69
70	/** @def IEM_WITH_THROW_CATCH
71	* Enables using C++ throw/catch as an alternative to setjmp/longjmp in user
72	* mode code when IEM_WITH_SETJMP is in effect.
73	*
74	* With GCC 11.3.1 and code TLB on linux, using throw/catch instead of
75	* setjmp/long resulted in bs2-test-1 running 3.00% faster and all but on test
76	* result value improving by more than 1%. (Best out of three.)
77	*
78	* With Visual C++ 2019 and code TLB on windows, using throw/catch instead of
79	* setjmp/long resulted in bs2-test-1 running 3.68% faster and all but some of
80	* the MMIO and CPUID tests ran noticeably faster. Variation is greater than on
81	* Linux, but it should be quite a bit faster for normal code.
82	*/
83	#if (defined(__cplusplus) && defined(IEM_WITH_SETJMP) && defined(IN_RING3) && (defined(__GNUC__) \|\| defined(_MSC_VER))) \
84	\|\| defined(DOXYGEN_RUNNING)
85	# define IEM_WITH_THROW_CATCH
86	#endif
87
88	/** @def IEM_DO_LONGJMP
89	*
90	* Wrapper around longjmp / throw.
91	*
92	* @param a_pVCpu The CPU handle.
93	* @param a_rc The status code jump back with / throw.
94	*/
95	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
96	# ifdef IEM_WITH_THROW_CATCH
97	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) throw int(a_rc)
98	# else
99	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) longjmp(*(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf), (a_rc))
100	# endif
101	#endif
102
103	/** For use with IEM function that may do a longjmp (when enabled).
104	*
105	* Visual C++ has trouble longjmp'ing from/over functions with the noexcept
106	* attribute. So, we indicate that function that may be part of a longjmp may
107	* throw "exceptions" and that the compiler should definitely not generate and
108	* std::terminate calling unwind code.
109	*
110	* Here is one example of this ending in std::terminate:
111	* @code{.txt}
112	00 00000041`cadfda10 00007ffc`5d5a1f9f ucrtbase!abort+0x4e
113	01 00000041`cadfda40 00007ffc`57af229a ucrtbase!terminate+0x1f
114	02 00000041`cadfda70 00007ffb`eec91030 VCRUNTIME140!__std_terminate+0xa [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\ehhelpers.cpp @ 192]
115	03 00000041`cadfdaa0 00007ffb`eec92c6d VCRUNTIME140_1!_CallSettingFrame+0x20 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\handlers.asm @ 50]
116	04 00000041`cadfdad0 00007ffb`eec93ae5 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToState+0x241 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 1085]
117	05 00000041`cadfdc00 00007ffb`eec92258 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToEmptyState+0x2d [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 218]
118	06 00000041`cadfdc30 00007ffb`eec940e9 VCRUNTIME140_1!__InternalCxxFrameHandler<__FrameHandler4>+0x194 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 304]
119	07 00000041`cadfdcd0 00007ffc`5f9f249f VCRUNTIME140_1!__CxxFrameHandler4+0xa9 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 290]
120	08 00000041`cadfdd40 00007ffc`5f980939 ntdll!RtlpExecuteHandlerForUnwind+0xf
121	09 00000041`cadfdd70 00007ffc`5f9a0edd ntdll!RtlUnwindEx+0x339
122	0a 00000041`cadfe490 00007ffc`57aff976 ntdll!RtlUnwind+0xcd
123	0b 00000041`cadfea00 00007ffb`e1b5de01 VCRUNTIME140!__longjmp_internal+0xe6 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\longjmp.asm @ 140]
124	0c (Inline Function) --------`-------- VBoxVMM!iemOpcodeGetNextU8SlowJmp+0x95 [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 1155]
125	0d 00000041`cadfea50 00007ffb`e1b60f6b VBoxVMM!iemOpcodeGetNextU8Jmp+0xc1 [L:\vbox-intern\src\VBox\VMM\include\IEMInline.h @ 402]
126	0e 00000041`cadfea90 00007ffb`e1cc6201 VBoxVMM!IEMExecForExits+0xdb [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 10185]
127	0f 00000041`cadfec70 00007ffb`e1d0df8d VBoxVMM!EMHistoryExec+0x4f1 [L:\vbox-intern\src\VBox\VMM\VMMAll\EMAll.cpp @ 452]
128	10 00000041`cadfed60 00007ffb`e1d0d4c0 VBoxVMM!nemR3WinHandleExitCpuId+0x79d [L:\vbox-intern\src\VBox\VMM\VMMAll\NEMAllNativeTemplate-win.cpp.h @ 1829] @encode
129	@endcode
130	*
131	* @see https://developercommunity.visualstudio.com/t/fragile-behavior-of-longjmp-called-from-noexcept-f/1532859
132	*/
133	#if defined(IEM_WITH_SETJMP) && (defined(_MSC_VER) \|\| defined(IEM_WITH_THROW_CATCH))
134	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT_EX(false)
135	#else
136	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT
137	#endif
138
139	#define IEM_IMPLEMENTS_TASKSWITCH
140
141	/** @def IEM_WITH_3DNOW
142	* Includes the 3DNow decoding. */
143	#if (!defined(IEM_WITH_3DNOW) && !defined(IEM_WITHOUT_3DNOW)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
144	# define IEM_WITH_3DNOW
145	#endif
146
147	/** @def IEM_WITH_THREE_0F_38
148	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
149	#if (!defined(IEM_WITH_THREE_0F_38) && !defined(IEM_WITHOUT_THREE_0F_38)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
150	# define IEM_WITH_THREE_0F_38
151	#endif
152
153	/** @def IEM_WITH_THREE_0F_3A
154	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
155	#if (!defined(IEM_WITH_THREE_0F_3A) && !defined(IEM_WITHOUT_THREE_0F_3A)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
156	# define IEM_WITH_THREE_0F_3A
157	#endif
158
159	/** @def IEM_WITH_VEX
160	* Includes the VEX decoding. */
161	#if (!defined(IEM_WITH_VEX) && !defined(IEM_WITHOUT_VEX)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
162	# define IEM_WITH_VEX
163	#endif
164
165	/** @def IEM_CFG_TARGET_CPU
166	* The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
167	*
168	* By default we allow this to be configured by the user via the
169	* CPUM/GuestCpuName config string, but this comes at a slight cost during
170	* decoding. So, for applications of this code where there is no need to
171	* be dynamic wrt target CPU, just modify this define.
172	*/
173	#if !defined(IEM_CFG_TARGET_CPU) \|\| defined(DOXYGEN_RUNNING)
174	# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
175	#endif
176
177	//#define IEM_WITH_CODE_TLB // - work in progress
178	//#define IEM_WITH_DATA_TLB // - work in progress
179
180
181	/** @def IEM_USE_UNALIGNED_DATA_ACCESS
182	* Use unaligned accesses instead of elaborate byte assembly. */
183	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86) \|\| defined(DOXYGEN_RUNNING)
184	# define IEM_USE_UNALIGNED_DATA_ACCESS
185	#endif
186
187	//#define IEM_LOG_MEMORY_WRITES
188
189	#if !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
190	/** Instruction statistics. */
191	typedef struct IEMINSTRSTATS
192	{
193	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
194	# include "IEMInstructionStatisticsTmpl.h"
195	# undef IEM_DO_INSTR_STAT
196	} IEMINSTRSTATS;
197	#else
198	struct IEMINSTRSTATS;
199	typedef struct IEMINSTRSTATS IEMINSTRSTATS;
200	#endif
201	/** Pointer to IEM instruction statistics. */
202	typedef IEMINSTRSTATS *PIEMINSTRSTATS;
203
204
205	/** @name IEMTARGETCPU_EFL_BEHAVIOR_XXX - IEMCPU::aidxTargetCpuEflFlavour
206	* @{ */
207	#define IEMTARGETCPU_EFL_BEHAVIOR_NATIVE 0 /*< Native x86 EFLAGS result; Intel EFLAGS when on non-x86 hosts. /
208	#define IEMTARGETCPU_EFL_BEHAVIOR_INTEL 1 /*< Intel EFLAGS result. /
209	#define IEMTARGETCPU_EFL_BEHAVIOR_AMD 2 /*< AMD EFLAGS result /
210	#define IEMTARGETCPU_EFL_BEHAVIOR_RESERVED 3 /*< Reserved/dummy entry slot that's the same as 0. /
211	#define IEMTARGETCPU_EFL_BEHAVIOR_MASK 3 /*< For masking the index before use. /
212	/** Selects the right variant from a_aArray.
213	* pVCpu is implicit in the caller context. */
214	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT(a_aArray) \
215	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[1] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
216	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for when no native worker can
217	* be used because the host CPU does not support the operation. */
218	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_NON_NATIVE(a_aArray) \
219	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
220	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for a two dimentional
221	* array paralleling IEMCPU::aidxTargetCpuEflFlavour and a single bit index
222	* into the two.
223	* @sa IEM_SELECT_NATIVE_OR_FALLBACK */
224	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
225	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
226	(a_aaArray[a_fNative][pVCpu->iem.s.aidxTargetCpuEflFlavour[a_fNative] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
227	#else
228	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
229	(a_aaArray[0][pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
230	#endif
231	/** @} */
232
233	/**
234	* Picks @a a_pfnNative or @a a_pfnFallback according to the host CPU feature
235	* indicator given by @a a_fCpumFeatureMember (CPUMFEATURES member).
236	*
237	* On non-x86 hosts, this will shortcut to the fallback w/o checking the
238	* indicator.
239	*
240	* @sa IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX
241	*/
242	#if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
243	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) \
244	(g_CpumHostFeatures.s.a_fCpumFeatureMember ? a_pfnNative : a_pfnFallback)
245	#else
246	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) (a_pfnFallback)
247	#endif
248
249
250	/**
251	* Extended operand mode that includes a representation of 8-bit.
252	*
253	* This is used for packing down modes when invoking some C instruction
254	* implementations.
255	*/
256	typedef enum IEMMODEX
257	{
258	IEMMODEX_16BIT = IEMMODE_16BIT,
259	IEMMODEX_32BIT = IEMMODE_32BIT,
260	IEMMODEX_64BIT = IEMMODE_64BIT,
261	IEMMODEX_8BIT
262	} IEMMODEX;
263	AssertCompileSize(IEMMODEX, 4);
264
265
266	/**
267	* Branch types.
268	*/
269	typedef enum IEMBRANCH
270	{
271	IEMBRANCH_JUMP = 1,
272	IEMBRANCH_CALL,
273	IEMBRANCH_TRAP,
274	IEMBRANCH_SOFTWARE_INT,
275	IEMBRANCH_HARDWARE_INT
276	} IEMBRANCH;
277	AssertCompileSize(IEMBRANCH, 4);
278
279
280	/**
281	* INT instruction types.
282	*/
283	typedef enum IEMINT
284	{
285	/** INT n instruction (opcode 0xcd imm). */
286	IEMINT_INTN = 0,
287	/** Single byte INT3 instruction (opcode 0xcc). */
288	IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
289	/** Single byte INTO instruction (opcode 0xce). */
290	IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
291	/** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
292	IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
293	} IEMINT;
294	AssertCompileSize(IEMINT, 4);
295
296
297	/**
298	* A FPU result.
299	*/
300	typedef struct IEMFPURESULT
301	{
302	/** The output value. */
303	RTFLOAT80U r80Result;
304	/** The output status. */
305	uint16_t FSW;
306	} IEMFPURESULT;
307	AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
308	/** Pointer to a FPU result. */
309	typedef IEMFPURESULT *PIEMFPURESULT;
310	/** Pointer to a const FPU result. */
311	typedef IEMFPURESULT const *PCIEMFPURESULT;
312
313
314	/**
315	* A FPU result consisting of two output values and FSW.
316	*/
317	typedef struct IEMFPURESULTTWO
318	{
319	/** The first output value. */
320	RTFLOAT80U r80Result1;
321	/** The output status. */
322	uint16_t FSW;
323	/** The second output value. */
324	RTFLOAT80U r80Result2;
325	} IEMFPURESULTTWO;
326	AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
327	AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
328	/** Pointer to a FPU result consisting of two output values and FSW. */
329	typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
330	/** Pointer to a const FPU result consisting of two output values and FSW. */
331	typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
332
333
334	/**
335	* IEM TLB entry.
336	*
337	* Lookup assembly:
338	* @code{.asm}
339	; Calculate tag.
340	mov rax, [VA]
341	shl rax, 16
342	shr rax, 16 + X86_PAGE_SHIFT
343	or rax, [uTlbRevision]
344
345	; Do indexing.
346	movzx ecx, al
347	lea rcx, [pTlbEntries + rcx]
348
349	; Check tag.
350	cmp [rcx + IEMTLBENTRY.uTag], rax
351	jne .TlbMiss
352
353	; Check access.
354	mov rax, ACCESS_FLAGS \| MAPPING_R3_NOT_VALID \| 0xffffff00
355	and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
356	cmp rax, [uTlbPhysRev]
357	jne .TlbMiss
358
359	; Calc address and we're done.
360	mov eax, X86_PAGE_OFFSET_MASK
361	and eax, [VA]
362	or rax, [rcx + IEMTLBENTRY.pMappingR3]
363	%ifdef VBOX_WITH_STATISTICS
364	inc qword [cTlbHits]
365	%endif
366	jmp .Done
367
368	.TlbMiss:
369	mov r8d, ACCESS_FLAGS
370	mov rdx, [VA]
371	mov rcx, [pVCpu]
372	call iemTlbTypeMiss
373	.Done:
374
375	@endcode
376	*
377	*/
378	typedef struct IEMTLBENTRY
379	{
380	/** The TLB entry tag.
381	* Bits 35 thru 0 are made up of the virtual address shifted right 12 bits, this
382	* is ASSUMING a virtual address width of 48 bits.
383	*
384	* Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
385	*
386	* The TLB lookup code uses the current TLB revision, which won't ever be zero,
387	* enabling an extremely cheap TLB invalidation most of the time. When the TLB
388	* revision wraps around though, the tags needs to be zeroed.
389	*
390	* @note Try use SHRD instruction? After seeing
391	* https://gmplib.org/~tege/x86-timing.pdf, maybe not.
392	*
393	* @todo This will need to be reorganized for 57-bit wide virtual address and
394	* PCID (currently 12 bits) and ASID (currently 6 bits) support. We'll
395	* have to move the TLB entry versioning entirely to the
396	* fFlagsAndPhysRev member then, 57 bit wide VAs means we'll only have
397	* 19 bits left (64 - 57 + 12 = 19) and they'll almost entire be
398	* consumed by PCID and ASID (12 + 6 = 18).
399	*/
400	uint64_t uTag;
401	/** Access flags and physical TLB revision.
402	*
403	* - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
404	* - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
405	* - Bit 2 - page tables - not user (complemented X86_PTE_US).
406	* - Bit 3 - pgm phys/virt - not directly writable.
407	* - Bit 4 - pgm phys page - not directly readable.
408	* - Bit 5 - page tables - not accessed (complemented X86_PTE_A).
409	* - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
410	* - Bit 7 - tlb entry - pMappingR3 member not valid.
411	* - Bits 63 thru 8 are used for the physical TLB revision number.
412	*
413	* We're using complemented bit meanings here because it makes it easy to check
414	* whether special action is required. For instance a user mode write access
415	* would do a "TEST fFlags, (X86_PTE_RW \| X86_PTE_US \| X86_PTE_D)" and a
416	* non-zero result would mean special handling needed because either it wasn't
417	* writable, or it wasn't user, or the page wasn't dirty. A user mode read
418	* access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
419	* need to check any PTE flag.
420	*/
421	uint64_t fFlagsAndPhysRev;
422	/** The guest physical page address. */
423	uint64_t GCPhys;
424	/** Pointer to the ring-3 mapping. */
425	R3PTRTYPE(uint8_t *) pbMappingR3;
426	#if HC_ARCH_BITS == 32
427	uint32_t u32Padding1;
428	#endif
429	} IEMTLBENTRY;
430	AssertCompileSize(IEMTLBENTRY, 32);
431	/** Pointer to an IEM TLB entry. */
432	typedef IEMTLBENTRY *PIEMTLBENTRY;
433
434	/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
435	* @{ */
436	#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /*< Page tables: Not executable. /
437	#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /*< Page tables: Not writable. /
438	#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /*< Page tables: Not user accessible (supervisor only). /
439	#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /*< Phys page: Not writable (access handler, ROM, whatever). /
440	#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /*< Phys page: Not readable (MMIO / access handler, ROM) /
441	#define IEMTLBE_F_PT_NO_ACCESSED RT_BIT_64(5) /*< Phys tables: Not accessed (need to be marked accessed). /
442	#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /*< Page tables: Not dirty (needs to be made dirty on write). /
443	#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(7) /*< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. /
444	#define IEMTLBE_F_PG_UNASSIGNED RT_BIT_64(8) /*< Phys page: Unassigned memory (not RAM, ROM, MMIO2 or MMIO). /
445	#define IEMTLBE_F_PG_CODE_PAGE RT_BIT_64(9) /*< Phys page: Code page. /
446	#define IEMTLBE_F_PHYS_REV UINT64_C(0xfffffffffffffc00) /*< Physical revision mask. @sa IEMTLB_PHYS_REV_INCR /
447	/** @} */
448
449
450	/**
451	* An IEM TLB.
452	*
453	* We've got two of these, one for data and one for instructions.
454	*/
455	typedef struct IEMTLB
456	{
457	/** The TLB entries.
458	* We've choosen 256 because that way we can obtain the result directly from a
459	* 8-bit register without an additional AND instruction. */
460	IEMTLBENTRY aEntries[256];
461	/** The TLB revision.
462	* This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
463	* by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
464	* the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
465	* (The revision zero indicates an invalid TLB entry.)
466	*
467	* The initial value is choosen to cause an early wraparound. */
468	uint64_t uTlbRevision;
469	/** The TLB physical address revision - shadow of PGM variable.
470	*
471	* This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
472	* incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
473	* a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
474	* as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
475	*
476	* The initial value is choosen to cause an early wraparound. */
477	uint64_t volatile uTlbPhysRev;
478
479	/* Statistics: */
480
481	/** TLB hits (VBOX_WITH_STATISTICS only). */
482	uint64_t cTlbHits;
483	/** TLB misses. */
484	uint32_t cTlbMisses;
485	/** Slow read path. */
486	uint32_t cTlbSlowReadPath;
487	/** Safe read path. */
488	uint32_t cTlbSafeReadPath;
489	/** Safe write path. */
490	uint32_t cTlbSafeWritePath;
491	#if 0
492	/** TLB misses because of tag mismatch. */
493	uint32_t cTlbMissesTag;
494	/** TLB misses because of virtual access violation. */
495	uint32_t cTlbMissesVirtAccess;
496	/** TLB misses because of dirty bit. */
497	uint32_t cTlbMissesDirty;
498	/** TLB misses because of MMIO */
499	uint32_t cTlbMissesMmio;
500	/** TLB misses because of write access handlers. */
501	uint32_t cTlbMissesWriteHandler;
502	/** TLB misses because no r3(/r0) mapping. */
503	uint32_t cTlbMissesMapping;
504	#endif
505	/** Alignment padding. */
506	uint32_t au32Padding[6];
507	} IEMTLB;
508	AssertCompileSizeAlignment(IEMTLB, 64);
509	/** IEMTLB::uTlbRevision increment. */
510	#define IEMTLB_REVISION_INCR RT_BIT_64(36)
511	/** IEMTLB::uTlbRevision mask. */
512	#define IEMTLB_REVISION_MASK (~(RT_BIT_64(36) - 1))
513	/** IEMTLB::uTlbPhysRev increment.
514	* @sa IEMTLBE_F_PHYS_REV */
515	#define IEMTLB_PHYS_REV_INCR RT_BIT_64(10)
516	/**
517	* Calculates the TLB tag for a virtual address.
518	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
519	* @param a_pTlb The TLB.
520	* @param a_GCPtr The virtual address. Must be RTGCPTR or same size or
521	* the clearing of the top 16 bits won't work (if 32-bit
522	* we'll end up with mostly zeros).
523	*/
524	#define IEMTLB_CALC_TAG(a_pTlb, a_GCPtr) ( IEMTLB_CALC_TAG_NO_REV(a_GCPtr) \| (a_pTlb)->uTlbRevision )
525	/**
526	* Calculates the TLB tag for a virtual address but without TLB revision.
527	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
528	* @param a_GCPtr The virtual address. Must be RTGCPTR or same size or
529	* the clearing of the top 16 bits won't work (if 32-bit
530	* we'll end up with mostly zeros).
531	*/
532	#define IEMTLB_CALC_TAG_NO_REV(a_GCPtr) ( (((a_GCPtr) << 16) >> (GUEST_PAGE_SHIFT + 16)) )
533	/**
534	* Converts a TLB tag value into a TLB index.
535	* @returns Index into IEMTLB::aEntries.
536	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
537	*/
538	#define IEMTLB_TAG_TO_INDEX(a_uTag) ( (uint8_t)(a_uTag) )
539	/**
540	* Converts a TLB tag value into a TLB index.
541	* @returns Index into IEMTLB::aEntries.
542	* @param a_pTlb The TLB.
543	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
544	*/
545	#define IEMTLB_TAG_TO_ENTRY(a_pTlb, a_uTag) ( &(a_pTlb)->aEntries[IEMTLB_TAG_TO_INDEX(a_uTag)] )
546
547
548	/** @name IEM_MC_F_XXX - MC block flags/clues.
549	* @todo Merge with IEM_CIMPL_F_XXX
550	* @{ */
551	#define IEM_MC_F_ONLY_8086 RT_BIT_32(0)
552	#define IEM_MC_F_MIN_186 RT_BIT_32(1)
553	#define IEM_MC_F_MIN_286 RT_BIT_32(2)
554	#define IEM_MC_F_NOT_286_OR_OLDER IEM_MC_F_MIN_386
555	#define IEM_MC_F_MIN_386 RT_BIT_32(3)
556	#define IEM_MC_F_MIN_486 RT_BIT_32(4)
557	#define IEM_MC_F_MIN_PENTIUM RT_BIT_32(5)
558	#define IEM_MC_F_MIN_PENTIUM_II IEM_MC_F_MIN_PENTIUM
559	#define IEM_MC_F_MIN_CORE IEM_MC_F_MIN_PENTIUM
560	#define IEM_MC_F_64BIT RT_BIT_32(6)
561	#define IEM_MC_F_NOT_64BIT RT_BIT_32(7)
562	/** This is set by IEMAllN8vePython.py to indicate a variation without the
563	* flags-clearing-and-checking, when there is also a variation with that.
564	* @note Do not use this manully, it's only for python and for testing in
565	* the native recompiler! */
566	#define IEM_MC_F_WITHOUT_FLAGS RT_BIT_32(8)
567	/** @} */
568
569	/** @name IEM_CIMPL_F_XXX - State change clues for CIMPL calls.
570	*
571	* These clues are mainly for the recompiler, so that it can emit correct code.
572	*
573	* They are processed by the python script and which also automatically
574	* calculates flags for MC blocks based on the statements, extending the use of
575	* these flags to describe MC block behavior to the recompiler core. The python
576	* script pass the flags to the IEM_MC2_END_EMIT_CALLS macro, but mainly for
577	* error checking purposes. The script emits the necessary fEndTb = true and
578	* similar statements as this reduces compile time a tiny bit.
579	*
580	* @{ */
581	/** Flag set if direct branch, clear if absolute or indirect. */
582	#define IEM_CIMPL_F_BRANCH_DIRECT RT_BIT_32(0)
583	/** Flag set if indirect branch, clear if direct or relative.
584	* This is also used for all system control transfers (SYSCALL, SYSRET, INT, ++)
585	* as well as for return instructions (RET, IRET, RETF). */
586	#define IEM_CIMPL_F_BRANCH_INDIRECT RT_BIT_32(1)
587	/** Flag set if relative branch, clear if absolute or indirect. */
588	#define IEM_CIMPL_F_BRANCH_RELATIVE RT_BIT_32(2)
589	/** Flag set if conditional branch, clear if unconditional. */
590	#define IEM_CIMPL_F_BRANCH_CONDITIONAL RT_BIT_32(3)
591	/** Flag set if it's a far branch (changes CS). */
592	#define IEM_CIMPL_F_BRANCH_FAR RT_BIT_32(4)
593	/** Convenience: Testing any kind of branch. */
594	#define IEM_CIMPL_F_BRANCH_ANY (IEM_CIMPL_F_BRANCH_DIRECT \| IEM_CIMPL_F_BRANCH_INDIRECT \| IEM_CIMPL_F_BRANCH_RELATIVE)
595
596	/** Execution flags may change (IEMCPU::fExec). */
597	#define IEM_CIMPL_F_MODE RT_BIT_32(5)
598	/** May change significant portions of RFLAGS. */
599	#define IEM_CIMPL_F_RFLAGS RT_BIT_32(6)
600	/** May change the status bits (X86_EFL_STATUS_BITS) in RFLAGS. */
601	#define IEM_CIMPL_F_STATUS_FLAGS RT_BIT_32(7)
602	/** May trigger interrupt shadowing. */
603	#define IEM_CIMPL_F_INHIBIT_SHADOW RT_BIT_32(8)
604	/** May enable interrupts, so recheck IRQ immediately afterwards executing
605	* the instruction. */
606	#define IEM_CIMPL_F_CHECK_IRQ_AFTER RT_BIT_32(9)
607	/** May disable interrupts, so recheck IRQ immediately before executing the
608	* instruction. */
609	#define IEM_CIMPL_F_CHECK_IRQ_BEFORE RT_BIT_32(10)
610	/** Convenience: Check for IRQ both before and after an instruction. */
611	#define IEM_CIMPL_F_CHECK_IRQ_BEFORE_AND_AFTER (IEM_CIMPL_F_CHECK_IRQ_BEFORE \| IEM_CIMPL_F_CHECK_IRQ_AFTER)
612	/** May trigger a VM exit (treated like IEM_CIMPL_F_MODE atm). */
613	#define IEM_CIMPL_F_VMEXIT RT_BIT_32(11)
614	/** May modify FPU state.
615	* @todo Not sure if this is useful yet. */
616	#define IEM_CIMPL_F_FPU RT_BIT_32(12)
617	/** REP prefixed instruction which may yield before updating PC.
618	* @todo Not sure if this is useful, REP functions now return non-zero
619	* status if they don't update the PC. */
620	#define IEM_CIMPL_F_REP RT_BIT_32(13)
621	/** I/O instruction.
622	* @todo Not sure if this is useful yet. */
623	#define IEM_CIMPL_F_IO RT_BIT_32(14)
624	/** Force end of TB after the instruction. */
625	#define IEM_CIMPL_F_END_TB RT_BIT_32(15)
626	/** Flag set if a branch may also modify the stack (push/pop return address). */
627	#define IEM_CIMPL_F_BRANCH_STACK RT_BIT_32(16)
628	/** Flag set if a branch may also modify the stack (push/pop return address)
629	* and switch it (load/restore SS:RSP). */
630	#define IEM_CIMPL_F_BRANCH_STACK_FAR RT_BIT_32(17)
631	/** Convenience: Raise exception (technically unnecessary, since it shouldn't return VINF_SUCCESS). */
632	#define IEM_CIMPL_F_XCPT \
633	(IEM_CIMPL_F_BRANCH_INDIRECT \| IEM_CIMPL_F_BRANCH_FAR \| IEM_CIMPL_F_BRANCH_STACK_FAR \
634	\| IEM_CIMPL_F_MODE \| IEM_CIMPL_F_RFLAGS \| IEM_CIMPL_F_VMEXIT)
635
636	/** The block calls a C-implementation instruction function with two implicit arguments.
637	* Mutually exclusive with IEM_CIMPL_F_CALLS_AIMPL and
638	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
639	* @note The python scripts will add this is missing. */
640	#define IEM_CIMPL_F_CALLS_CIMPL RT_BIT_32(18)
641	/** The block calls an ASM-implementation instruction function.
642	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL and
643	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
644	* @note The python scripts will add this is missing. */
645	#define IEM_CIMPL_F_CALLS_AIMPL RT_BIT_32(19)
646	/** The block calls an ASM-implementation instruction function with an implicit
647	* X86FXSTATE pointer argument.
648	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL and IEM_CIMPL_F_CALLS_AIMPL.
649	* @note The python scripts will add this is missing. */
650	#define IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE RT_BIT_32(20)
651	/** @} */
652
653
654	/** @name IEM_F_XXX - Execution mode flags (IEMCPU::fExec, IEMTB::fFlags).
655	*
656	* These flags are set when entering IEM and adjusted as code is executed, such
657	* that they will always contain the current values as instructions are
658	* finished.
659	*
660	* In recompiled execution mode, (most of) these flags are included in the
661	* translation block selection key and stored in IEMTB::fFlags alongside the
662	* IEMTB_F_XXX flags. The latter flags uses bits 31 thru 24, which are all zero
663	* in IEMCPU::fExec.
664	*
665	* @{ */
666	/** Mode: The block target mode mask. */
667	#define IEM_F_MODE_MASK UINT32_C(0x0000001f)
668	/** Mode: The IEMMODE part of the IEMTB_F_MODE_MASK value. */
669	#define IEM_F_MODE_CPUMODE_MASK UINT32_C(0x00000003)
670	/** X86 Mode: Bit used to indicating pre-386 CPU in 16-bit mode (for eliminating
671	* conditional in EIP/IP updating), and flat wide open CS, SS, DS, and ES in
672	* 32-bit mode (for simplifying most memory accesses). */
673	#define IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK UINT32_C(0x00000004)
674	/** X86 Mode: Bit indicating protected mode, real mode (or SMM) when not set. */
675	#define IEM_F_MODE_X86_PROT_MASK UINT32_C(0x00000008)
676	/** X86 Mode: Bit used to indicate virtual 8086 mode (only 16-bit). */
677	#define IEM_F_MODE_X86_V86_MASK UINT32_C(0x00000010)
678
679	/** X86 Mode: 16-bit on 386 or later. */
680	#define IEM_F_MODE_X86_16BIT UINT32_C(0x00000000)
681	/** X86 Mode: 80286, 80186 and 8086/88 targetting blocks (EIP update opt). */
682	#define IEM_F_MODE_X86_16BIT_PRE_386 UINT32_C(0x00000004)
683	/** X86 Mode: 16-bit protected mode on 386 or later. */
684	#define IEM_F_MODE_X86_16BIT_PROT UINT32_C(0x00000008)
685	/** X86 Mode: 16-bit protected mode on 386 or later. */
686	#define IEM_F_MODE_X86_16BIT_PROT_PRE_386 UINT32_C(0x0000000c)
687	/** X86 Mode: 16-bit virtual 8086 protected mode (on 386 or later). */
688	#define IEM_F_MODE_X86_16BIT_PROT_V86 UINT32_C(0x00000018)
689
690	/** X86 Mode: 32-bit on 386 or later. */
691	#define IEM_F_MODE_X86_32BIT UINT32_C(0x00000001)
692	/** X86 Mode: 32-bit mode with wide open flat CS, SS, DS and ES. */
693	#define IEM_F_MODE_X86_32BIT_FLAT UINT32_C(0x00000005)
694	/** X86 Mode: 32-bit protected mode. */
695	#define IEM_F_MODE_X86_32BIT_PROT UINT32_C(0x00000009)
696	/** X86 Mode: 32-bit protected mode with wide open flat CS, SS, DS and ES. */
697	#define IEM_F_MODE_X86_32BIT_PROT_FLAT UINT32_C(0x0000000d)
698
699	/** X86 Mode: 64-bit (includes protected, but not the flat bit). */
700	#define IEM_F_MODE_X86_64BIT UINT32_C(0x0000000a)
701
702	/** X86 Mode: Checks if @a a_fExec represent a FLAT mode. */
703	#define IEM_F_MODE_X86_IS_FLAT(a_fExec) ( ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_64BIT \
704	\|\| ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_32BIT_PROT_FLAT \
705	\|\| ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_32BIT_FLAT)
706
707	/** Bypass access handlers when set. */
708	#define IEM_F_BYPASS_HANDLERS UINT32_C(0x00010000)
709	/** Have pending hardware instruction breakpoints. */
710	#define IEM_F_PENDING_BRK_INSTR UINT32_C(0x00020000)
711	/** Have pending hardware data breakpoints. */
712	#define IEM_F_PENDING_BRK_DATA UINT32_C(0x00040000)
713
714	/** X86: Have pending hardware I/O breakpoints. */
715	#define IEM_F_PENDING_BRK_X86_IO UINT32_C(0x00000400)
716	/** X86: Disregard the lock prefix (implied or not) when set. */
717	#define IEM_F_X86_DISREGARD_LOCK UINT32_C(0x00000800)
718
719	/** Pending breakpoint mask (what iemCalcExecDbgFlags works out). */
720	#define IEM_F_PENDING_BRK_MASK (IEM_F_PENDING_BRK_INSTR \| IEM_F_PENDING_BRK_DATA \| IEM_F_PENDING_BRK_X86_IO)
721
722	/** Caller configurable options. */
723	#define IEM_F_USER_OPTS (IEM_F_BYPASS_HANDLERS \| IEM_F_X86_DISREGARD_LOCK)
724
725	/** X86: The current protection level (CPL) shift factor. */
726	#define IEM_F_X86_CPL_SHIFT 8
727	/** X86: The current protection level (CPL) mask. */
728	#define IEM_F_X86_CPL_MASK UINT32_C(0x00000300)
729	/** X86: The current protection level (CPL) shifted mask. */
730	#define IEM_F_X86_CPL_SMASK UINT32_C(0x00000003)
731
732	/** X86 execution context.
733	* The IEM_F_X86_CTX_XXX values are individual flags that can be combined (with
734	* the exception of IEM_F_X86_CTX_NORMAL). This allows running VMs from SMM
735	* mode. */
736	#define IEM_F_X86_CTX_MASK UINT32_C(0x0000f000)
737	/** X86 context: Plain regular execution context. */
738	#define IEM_F_X86_CTX_NORMAL UINT32_C(0x00000000)
739	/** X86 context: VT-x enabled. */
740	#define IEM_F_X86_CTX_VMX UINT32_C(0x00001000)
741	/** X86 context: AMD-V enabled. */
742	#define IEM_F_X86_CTX_SVM UINT32_C(0x00002000)
743	/** X86 context: In AMD-V or VT-x guest mode. */
744	#define IEM_F_X86_CTX_IN_GUEST UINT32_C(0x00004000)
745	/** X86 context: System management mode (SMM). */
746	#define IEM_F_X86_CTX_SMM UINT32_C(0x00008000)
747
748	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
749	* iemRegFinishClearingRF() most for most situations (CPUMCTX_DBG_HIT_DRX_MASK
750	* and CPUMCTX_DBG_DBGF_MASK are covered by the IEM_F_PENDING_BRK_XXX bits
751	* alread). */
752
753	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
754	* iemRegFinishClearingRF() most for most situations
755	* (CPUMCTX_DBG_HIT_DRX_MASK and CPUMCTX_DBG_DBGF_MASK are covered by
756	* the IEM_F_PENDING_BRK_XXX bits alread). */
757
758	/** @} */
759
760
761	/** @name IEMTB_F_XXX - Translation block flags (IEMTB::fFlags).
762	*
763	* Extends the IEM_F_XXX flags (subject to IEMTB_F_IEM_F_MASK) to make up the
764	* translation block flags. The combined flag mask (subject to
765	* IEMTB_F_KEY_MASK) is used as part of the lookup key for translation blocks.
766	*
767	* @{ */
768	/** Mask of IEM_F_XXX flags included in IEMTB_F_XXX. */
769	#define IEMTB_F_IEM_F_MASK UINT32_C(0x00ffffff)
770
771	/** Type: The block type mask. */
772	#define IEMTB_F_TYPE_MASK UINT32_C(0x03000000)
773	/** Type: Purly threaded recompiler (via tables). */
774	#define IEMTB_F_TYPE_THREADED UINT32_C(0x01000000)
775	/** Type: Native recompilation. */
776	#define IEMTB_F_TYPE_NATIVE UINT32_C(0x02000000)
777
778	/** Set when we're starting the block in an "interrupt shadow".
779	* We don't need to distingish between the two types of this mask, thus the one.
780	* @see CPUMCTX_INHIBIT_SHADOW, CPUMIsInInterruptShadow() */
781	#define IEMTB_F_INHIBIT_SHADOW UINT32_C(0x04000000)
782	/** Set when we're currently inhibiting NMIs
783	* @see CPUMCTX_INHIBIT_NMI, CPUMAreInterruptsInhibitedByNmi() */
784	#define IEMTB_F_INHIBIT_NMI UINT32_C(0x08000000)
785
786	/** Checks that EIP/IP is wihin CS.LIM before each instruction. Used when
787	* we're close the limit before starting a TB, as determined by
788	* iemGetTbFlagsForCurrentPc(). */
789	#define IEMTB_F_CS_LIM_CHECKS UINT32_C(0x10000000)
790
791	/** Mask of the IEMTB_F_XXX flags that are part of the TB lookup key.
792	*
793	* @note We skip all of IEM_F_X86_CTX_MASK, with the exception of SMM (which we
794	* don't implement), because we don't currently generate any context
795	* specific code - that's all handled in CIMPL functions.
796	*
797	* For the threaded recompiler we don't generate any CPL specific code
798	* either, but the native recompiler does for memory access (saves getting
799	* the CPL from fExec and turning it into IEMTLBE_F_PT_NO_USER).
800	* Since most OSes will not share code between rings, this shouldn't
801	* have any real effect on TB/memory/recompiling load.
802	*/
803	#define IEMTB_F_KEY_MASK ((UINT32_MAX & ~(IEM_F_X86_CTX_MASK \| IEMTB_F_TYPE_MASK)) \| IEM_F_X86_CTX_SMM)
804	/** @} */
805
806	AssertCompile( (IEM_F_MODE_X86_16BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
807	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
808	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_PROT_MASK));
809	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_V86_MASK));
810	AssertCompile( (IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
811	AssertCompile( IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
812	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_PROT_MASK));
813	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
814	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
815	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
816	AssertCompile( IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
817	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_V86_MASK));
818	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
819	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
820	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_PROT_MASK);
821	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
822	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_PROT_MASK);
823	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
824	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_V86_MASK);
825
826	AssertCompile( (IEM_F_MODE_X86_32BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
827	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
828	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_PROT_MASK));
829	AssertCompile( (IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
830	AssertCompile( IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
831	AssertCompile(!(IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_PROT_MASK));
832	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
833	AssertCompile(!(IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
834	AssertCompile( IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
835	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
836	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
837	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_PROT_MASK);
838
839	AssertCompile( (IEM_F_MODE_X86_64BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_64BIT);
840	AssertCompile( IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_PROT_MASK);
841	AssertCompile(!(IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
842
843	/** Native instruction type for use with the native code generator.
844	* This is a byte (uint8_t) for x86 and amd64 and uint32_t for the other(s). */
845	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
846	typedef uint8_t IEMNATIVEINSTR;
847	#else
848	typedef uint32_t IEMNATIVEINSTR;
849	#endif
850	/** Pointer to a native instruction unit. */
851	typedef IEMNATIVEINSTR *PIEMNATIVEINSTR;
852	/** Pointer to a const native instruction unit. */
853	typedef IEMNATIVEINSTR const *PCIEMNATIVEINSTR;
854
855	/**
856	* A call for the threaded call table.
857	*/
858	typedef struct IEMTHRDEDCALLENTRY
859	{
860	/** The function to call (IEMTHREADEDFUNCS). */
861	uint16_t enmFunction;
862	/** Instruction number in the TB (for statistics). */
863	uint8_t idxInstr;
864	uint8_t uUnused0;
865
866	/** Offset into IEMTB::pabOpcodes. */
867	uint16_t offOpcode;
868	/** The opcode length. */
869	uint8_t cbOpcode;
870	/** Index in to IEMTB::aRanges. */
871	uint8_t idxRange;
872
873	/** Generic parameters. */
874	uint64_t auParams[3];
875	} IEMTHRDEDCALLENTRY;
876	AssertCompileSize(IEMTHRDEDCALLENTRY, sizeof(uint64_t) * 4);
877	/** Pointer to a threaded call entry. */
878	typedef struct IEMTHRDEDCALLENTRY *PIEMTHRDEDCALLENTRY;
879	/** Pointer to a const threaded call entry. */
880	typedef IEMTHRDEDCALLENTRY const *PCIEMTHRDEDCALLENTRY;
881
882	/**
883	* Native IEM TB 'function' typedef.
884	*
885	* This will throw/longjmp on occation.
886	*
887	* @note AMD64 doesn't have that many non-volatile registers and does sport
888	* 32-bit address displacments, so we don't need pCtx.
889	*
890	* On ARM64 pCtx allows us to directly address the whole register
891	* context without requiring a separate indexing register holding the
892	* offset. This saves an instruction loading the offset for each guest
893	* CPU context access, at the cost of a non-volatile register.
894	* Fortunately, ARM64 has quite a lot more registers.
895	*/
896	typedef
897	#ifdef RT_ARCH_AMD64
898	int FNIEMTBNATIVE(PVMCPUCC pVCpu)
899	#else
900	int FNIEMTBNATIVE(PVMCPUCC pVCpu, PCPUMCTX pCtx)
901	#endif
902	#if RT_CPLUSPLUS_PREREQ(201700)
903	IEM_NOEXCEPT_MAY_LONGJMP
904	#endif
905	;
906	/** Pointer to a native IEM TB entry point function.
907	* This will throw/longjmp on occation. */
908	typedef FNIEMTBNATIVE *PFNIEMTBNATIVE;
909
910
911	/**
912	* Translation block debug info entry type.
913	*/
914	typedef enum IEMTBDBGENTRYTYPE
915	{
916	kIemTbDbgEntryType_Invalid = 0,
917	/** The entry is for marking a native code position.
918	* Entries following this all apply to this position. */
919	kIemTbDbgEntryType_NativeOffset,
920	/** The entry is for a new guest instruction. */
921	kIemTbDbgEntryType_GuestInstruction,
922	/** Marks the start of a threaded call. */
923	kIemTbDbgEntryType_ThreadedCall,
924	/** Marks the location of a label. */
925	kIemTbDbgEntryType_Label,
926	/** Info about a host register shadowing a guest register. */
927	kIemTbDbgEntryType_GuestRegShadowing,
928	kIemTbDbgEntryType_End
929	} IEMTBDBGENTRYTYPE;
930
931	/**
932	* Translation block debug info entry.
933	*/
934	typedef union IEMTBDBGENTRY
935	{
936	/** Plain 32-bit view. */
937	uint32_t u;
938
939	/** Generic view for getting at the type field. */
940	struct
941	{
942	/** IEMTBDBGENTRYTYPE */
943	uint32_t uType : 4;
944	uint32_t uTypeSpecific : 28;
945	} Gen;
946
947	struct
948	{
949	/** kIemTbDbgEntryType_ThreadedCall1. */
950	uint32_t uType : 4;
951	/** Native code offset. */
952	uint32_t offNative : 28;
953	} NativeOffset;
954
955	struct
956	{
957	/** kIemTbDbgEntryType_GuestInstruction. */
958	uint32_t uType : 4;
959	uint32_t uUnused : 4;
960	/** The IEM_F_XXX flags. */
961	uint32_t fExec : 24;
962	} GuestInstruction;
963
964	struct
965	{
966	/* kIemTbDbgEntryType_ThreadedCall. */
967	uint32_t uType : 4;
968	/** Set if the call was recompiled to native code, clear if just calling
969	* threaded function. */
970	uint32_t fRecompiled : 1;
971	uint32_t uUnused : 11;
972	/** The threaded call number (IEMTHREADEDFUNCS). */
973	uint32_t enmCall : 16;
974	} ThreadedCall;
975
976	struct
977	{
978	/* kIemTbDbgEntryType_Label. */
979	uint32_t uType : 4;
980	uint32_t uUnused : 4;
981	/** The label type (IEMNATIVELABELTYPE). */
982	uint32_t enmLabel : 8;
983	/** The label data. */
984	uint32_t uData : 16;
985	} Label;
986
987	struct
988	{
989	/* kIemTbDbgEntryType_GuestRegShadowing. */
990	uint32_t uType : 4;
991	uint32_t uUnused : 4;
992	/** The guest register being shadowed (IEMNATIVEGSTREG). */
993	uint32_t idxGstReg : 8;
994	/** The host new register number, UINT8_MAX if dropped. */
995	uint32_t idxHstReg : 8;
996	/** The previous host register number, UINT8_MAX if new. */
997	uint32_t idxHstRegPrev : 8;
998	} GuestRegShadowing;
999	} IEMTBDBGENTRY;
1000	AssertCompileSize(IEMTBDBGENTRY, sizeof(uint32_t));
1001	/** Pointer to a debug info entry. */
1002	typedef IEMTBDBGENTRY *PIEMTBDBGENTRY;
1003	/** Pointer to a const debug info entry. */
1004	typedef IEMTBDBGENTRY const *PCIEMTBDBGENTRY;
1005
1006	/**
1007	* Translation block debug info.
1008	*/
1009	typedef struct IEMTBDBG
1010	{
1011	/** Number of entries in aEntries. */
1012	uint32_t cEntries;
1013	/** Debug info entries. */
1014	RT_FLEXIBLE_ARRAY_EXTENSION
1015	IEMTBDBGENTRY aEntries[RT_FLEXIBLE_ARRAY];
1016	} IEMTBDBG;
1017	/** Pointer to TB debug info. */
1018	typedef IEMTBDBG *PIEMTBDBG;
1019	/** Pointer to const TB debug info. */
1020	typedef IEMTBDBG const *PCIEMTBDBG;
1021
1022
1023	/**
1024	* Translation block.
1025	*
1026	* The current plan is to just keep TBs and associated lookup hash table private
1027	* to each VCpu as that simplifies TB removal greatly (no races) and generally
1028	* avoids using expensive atomic primitives for updating lists and stuff.
1029	*/
1030	#pragma pack(2) /* to prevent the Thrd structure from being padded unnecessarily */
1031	typedef struct IEMTB
1032	{
1033	/** Next block with the same hash table entry. */
1034	struct IEMTB *pNext;
1035	/** Usage counter. */
1036	uint32_t cUsed;
1037	/** The IEMCPU::msRecompilerPollNow last time it was used. */
1038	uint32_t msLastUsed;
1039
1040	/** @name What uniquely identifies the block.
1041	* @{ */
1042	RTGCPHYS GCPhysPc;
1043	/** IEMTB_F_XXX (i.e. IEM_F_XXX ++). */
1044	uint32_t fFlags;
1045	union
1046	{
1047	struct
1048	{
1049	/*< Relevant CS X86DESCATTR_XXX bits. /
1050	uint16_t fAttr;
1051	} x86;
1052	};
1053	/** @} */
1054
1055	/** Number of opcode ranges. */
1056	uint8_t cRanges;
1057	/** Statistics: Number of instructions in the block. */
1058	uint8_t cInstructions;
1059
1060	/** Type specific info. */
1061	union
1062	{
1063	struct
1064	{
1065	/** The call sequence table. */
1066	PIEMTHRDEDCALLENTRY paCalls;
1067	/** Number of calls in paCalls. */
1068	uint16_t cCalls;
1069	/** Number of calls allocated. */
1070	uint16_t cAllocated;
1071	} Thrd;
1072	struct
1073	{
1074	/** The native instructions (PFNIEMTBNATIVE). */
1075	PIEMNATIVEINSTR paInstructions;
1076	/** Number of instructions pointed to by paInstructions. */
1077	uint32_t cInstructions;
1078	} Native;
1079	/** Generic view for zeroing when freeing. */
1080	struct
1081	{
1082	uintptr_t uPtr;
1083	uint32_t uData;
1084	} Gen;
1085	};
1086
1087	/** The allocation chunk this TB belongs to. */
1088	uint8_t idxAllocChunk;
1089	uint8_t bUnused;
1090
1091	/** Number of bytes of opcodes stored in pabOpcodes.
1092	* @todo this field isn't really needed, aRanges keeps the actual info. */
1093	uint16_t cbOpcodes;
1094	/** Pointer to the opcode bytes this block was recompiled from. */
1095	uint8_t *pabOpcodes;
1096
1097	/** Debug info if enabled.
1098	* This is only generated by the native recompiler. */
1099	PIEMTBDBG pDbgInfo;
1100
1101	/* --- 64 byte cache line end --- */
1102
1103	/** Opcode ranges.
1104	*
1105	* The opcode checkers and maybe TLB loading functions will use this to figure
1106	* out what to do. The parameter will specify an entry and the opcode offset to
1107	* start at and the minimum number of bytes to verify (instruction length).
1108	*
1109	* When VT-x and AMD-V looks up the opcode bytes for an exitting instruction,
1110	* they'll first translate RIP (+ cbInstr - 1) to a physical address using the
1111	* code TLB (must have a valid entry for that address) and scan the ranges to
1112	* locate the corresponding opcodes. Probably.
1113	*/
1114	struct IEMTBOPCODERANGE
1115	{
1116	/** Offset within pabOpcodes. */
1117	uint16_t offOpcodes;
1118	/** Number of bytes. */
1119	uint16_t cbOpcodes;
1120	/** The page offset. */
1121	RT_GCC_EXTENSION
1122	uint16_t offPhysPage : 12;
1123	/** Unused bits. */
1124	RT_GCC_EXTENSION
1125	uint16_t u2Unused : 2;
1126	/** Index into GCPhysPc + aGCPhysPages for the physical page address. */
1127	RT_GCC_EXTENSION
1128	uint16_t idxPhysPage : 2;
1129	} aRanges[8];
1130
1131	/** Physical pages that this TB covers.
1132	* The GCPhysPc w/o page offset is element zero, so starting here with 1. */
1133	RTGCPHYS aGCPhysPages[2];
1134	} IEMTB;
1135	#pragma pack()
1136	AssertCompileMemberAlignment(IEMTB, GCPhysPc, sizeof(RTGCPHYS));
1137	AssertCompileMemberAlignment(IEMTB, Thrd, sizeof(void *));
1138	AssertCompileMemberAlignment(IEMTB, pabOpcodes, sizeof(void *));
1139	AssertCompileMemberAlignment(IEMTB, pDbgInfo, sizeof(void *));
1140	AssertCompileMemberAlignment(IEMTB, aGCPhysPages, sizeof(RTGCPHYS));
1141	AssertCompileMemberOffset(IEMTB, aRanges, 64);
1142	AssertCompileMemberSize(IEMTB, aRanges[0], 6);
1143	#if 1
1144	AssertCompileSize(IEMTB, 128);
1145	# define IEMTB_SIZE_IS_POWER_OF_TWO /*< The IEMTB size is a power of two. /
1146	#else
1147	AssertCompileSize(IEMTB, 168);
1148	# undef IEMTB_SIZE_IS_POWER_OF_TWO
1149	#endif
1150
1151	/** Pointer to a translation block. */
1152	typedef IEMTB *PIEMTB;
1153	/** Pointer to a const translation block. */
1154	typedef IEMTB const *PCIEMTB;
1155
1156	/**
1157	* A chunk of memory in the TB allocator.
1158	*/
1159	typedef struct IEMTBCHUNK
1160	{
1161	/** Pointer to the translation blocks in this chunk. */
1162	PIEMTB paTbs;
1163	#ifdef IN_RING0
1164	/** Allocation handle. */
1165	RTR0MEMOBJ hMemObj;
1166	#endif
1167	} IEMTBCHUNK;
1168
1169	/**
1170	* A per-CPU translation block allocator.
1171	*
1172	* Because of how the IEMTBCACHE uses the lower 6 bits of the TB address to keep
1173	* the length of the collision list, and of course also for cache line alignment
1174	* reasons, the TBs must be allocated with at least 64-byte alignment.
1175	* Memory is there therefore allocated using one of the page aligned allocators.
1176	*
1177	*
1178	* To avoid wasting too much memory, it is allocated piecemeal as needed,
1179	* in chunks (IEMTBCHUNK) of 2 MiB or more. The TB has an 8-bit chunk index
1180	* that enables us to quickly calculate the allocation bitmap position when
1181	* freeing the translation block.
1182	*/
1183	typedef struct IEMTBALLOCATOR
1184	{
1185	/** Magic value (IEMTBALLOCATOR_MAGIC). */
1186	uint32_t uMagic;
1187
1188	#ifdef IEMTB_SIZE_IS_POWER_OF_TWO
1189	/** Mask corresponding to cTbsPerChunk - 1. */
1190	uint32_t fChunkMask;
1191	/** Shift count corresponding to cTbsPerChunk. */
1192	uint8_t cChunkShift;
1193	#else
1194	uint32_t uUnused;
1195	uint8_t bUnused;
1196	#endif
1197	/** Number of chunks we're allowed to allocate. */
1198	uint8_t cMaxChunks;
1199	/** Number of chunks currently populated. */
1200	uint16_t cAllocatedChunks;
1201	/** Number of translation blocks per chunk. */
1202	uint32_t cTbsPerChunk;
1203	/** Chunk size. */
1204	uint32_t cbPerChunk;
1205
1206	/** The maximum number of TBs. */
1207	uint32_t cMaxTbs;
1208	/** Total number of TBs in the populated chunks.
1209	* (cAllocatedChunks * cTbsPerChunk) */
1210	uint32_t cTotalTbs;
1211	/** The current number of TBs in use.
1212	* The number of free TBs: cAllocatedTbs - cInUseTbs; */
1213	uint32_t cInUseTbs;
1214	/** Statistics: Number of the cInUseTbs that are native ones. */
1215	uint32_t cNativeTbs;
1216	/** Statistics: Number of the cInUseTbs that are threaded ones. */
1217	uint32_t cThreadedTbs;
1218
1219	/** Where to start pruning TBs from when we're out.
1220	* See iemTbAllocatorAllocSlow for details. */
1221	uint32_t iPruneFrom;
1222	/** Hint about which bit to start scanning the bitmap from. */
1223	uint32_t iStartHint;
1224	/** Where to start pruning native TBs from when we're out of executable memory.
1225	* See iemTbAllocatorFreeupNativeSpace for details. */
1226	uint32_t iPruneNativeFrom;
1227	uint32_t uPadding;
1228
1229	/** Statistics: Number of TB allocation calls. */
1230	STAMCOUNTER StatAllocs;
1231	/** Statistics: Number of TB free calls. */
1232	STAMCOUNTER StatFrees;
1233	/** Statistics: Time spend pruning. */
1234	STAMPROFILE StatPrune;
1235	/** Statistics: Time spend pruning native TBs. */
1236	STAMPROFILE StatPruneNative;
1237
1238	/** The delayed free list (see iemTbAlloctorScheduleForFree). */
1239	PIEMTB pDelayedFreeHead;
1240
1241	/** Allocation chunks. */
1242	IEMTBCHUNK aChunks[256];
1243
1244	/** Allocation bitmap for all possible chunk chunks. */
1245	RT_FLEXIBLE_ARRAY_EXTENSION
1246	uint64_t bmAllocated[RT_FLEXIBLE_ARRAY];
1247	} IEMTBALLOCATOR;
1248	/** Pointer to a TB allocator. */
1249	typedef struct IEMTBALLOCATOR *PIEMTBALLOCATOR;
1250
1251	/** Magic value for the TB allocator (Emmet Harley Cohen). */
1252	#define IEMTBALLOCATOR_MAGIC UINT32_C(0x19900525)
1253
1254
1255	/**
1256	* A per-CPU translation block cache (hash table).
1257	*
1258	* The hash table is allocated once during IEM initialization and size double
1259	* the max TB count, rounded up to the nearest power of two (so we can use and
1260	* AND mask rather than a rest division when hashing).
1261	*/
1262	typedef struct IEMTBCACHE
1263	{
1264	/** Magic value (IEMTBCACHE_MAGIC). */
1265	uint32_t uMagic;
1266	/** Size of the hash table. This is a power of two. */
1267	uint32_t cHash;
1268	/** The mask corresponding to cHash. */
1269	uint32_t uHashMask;
1270	uint32_t uPadding;
1271
1272	/** @name Statistics
1273	* @{ */
1274	/** Number of collisions ever. */
1275	STAMCOUNTER cCollisions;
1276
1277	/** Statistics: Number of TB lookup misses. */
1278	STAMCOUNTER cLookupMisses;
1279	/** Statistics: Number of TB lookup hits (debug only). */
1280	STAMCOUNTER cLookupHits;
1281	STAMCOUNTER auPadding2[3];
1282	/** Statistics: Collision list length pruning. */
1283	STAMPROFILE StatPrune;
1284	/** @} */
1285
1286	/** The hash table itself.
1287	* @note The lower 6 bits of the pointer is used for keeping the collision
1288	* list length, so we can take action when it grows too long.
1289	* This works because TBs are allocated using a 64 byte (or
1290	* higher) alignment from page aligned chunks of memory, so the lower
1291	* 6 bits of the address will always be zero.
1292	* See IEMTBCACHE_PTR_COUNT_MASK, IEMTBCACHE_PTR_MAKE and friends.
1293	*/
1294	RT_FLEXIBLE_ARRAY_EXTENSION
1295	PIEMTB apHash[RT_FLEXIBLE_ARRAY];
1296	} IEMTBCACHE;
1297	/** Pointer to a per-CPU translation block cahce. */
1298	typedef IEMTBCACHE *PIEMTBCACHE;
1299
1300	/** Magic value for IEMTBCACHE (Johnny O'Neal). */
1301	#define IEMTBCACHE_MAGIC UINT32_C(0x19561010)
1302
1303	/** The collision count mask for IEMTBCACHE::apHash entries. */
1304	#define IEMTBCACHE_PTR_COUNT_MASK ((uintptr_t)0x3f)
1305	/** The max collision count for IEMTBCACHE::apHash entries before pruning. */
1306	#define IEMTBCACHE_PTR_MAX_COUNT ((uintptr_t)0x30)
1307	/** Combine a TB pointer and a collision list length into a value for an
1308	* IEMTBCACHE::apHash entry. */
1309	#define IEMTBCACHE_PTR_MAKE(a_pTb, a_cCount) (PIEMTB)((uintptr_t)(a_pTb) \| (a_cCount))
1310	/** Combine a TB pointer and a collision list length into a value for an
1311	* IEMTBCACHE::apHash entry. */
1312	#define IEMTBCACHE_PTR_GET_TB(a_pHashEntry) (PIEMTB)((uintptr_t)(a_pHashEntry) & ~IEMTBCACHE_PTR_COUNT_MASK)
1313	/** Combine a TB pointer and a collision list length into a value for an
1314	* IEMTBCACHE::apHash entry. */
1315	#define IEMTBCACHE_PTR_GET_COUNT(a_pHashEntry) ((uintptr_t)(a_pHashEntry) & IEMTBCACHE_PTR_COUNT_MASK)
1316
1317	/**
1318	* Calculates the hash table slot for a TB from physical PC address and TB flags.
1319	*/
1320	#define IEMTBCACHE_HASH(a_paCache, a_fTbFlags, a_GCPhysPc) \
1321	IEMTBCACHE_HASH_NO_KEY_MASK(a_paCache, (a_fTbFlags) & IEMTB_F_KEY_MASK, a_GCPhysPc)
1322
1323	/**
1324	* Calculates the hash table slot for a TB from physical PC address and TB
1325	* flags, ASSUMING the caller has applied IEMTB_F_KEY_MASK to @a a_fTbFlags.
1326	*/
1327	#define IEMTBCACHE_HASH_NO_KEY_MASK(a_paCache, a_fTbFlags, a_GCPhysPc) \
1328	(((uint32_t)(a_GCPhysPc) ^ (a_fTbFlags)) & (a_paCache)->uHashMask)
1329
1330
1331	/** @name IEMBRANCHED_F_XXX - Branched indicator (IEMCPU::fTbBranched).
1332	*
1333	* These flags parallels the main IEM_CIMPL_F_BRANCH_XXX flags.
1334	*
1335	* @{ */
1336	/** Value if no branching happened recently. */
1337	#define IEMBRANCHED_F_NO UINT8_C(0x00)
1338	/** Flag set if direct branch, clear if absolute or indirect. */
1339	#define IEMBRANCHED_F_DIRECT UINT8_C(0x01)
1340	/** Flag set if indirect branch, clear if direct or relative. */
1341	#define IEMBRANCHED_F_INDIRECT UINT8_C(0x02)
1342	/** Flag set if relative branch, clear if absolute or indirect. */
1343	#define IEMBRANCHED_F_RELATIVE UINT8_C(0x04)
1344	/** Flag set if conditional branch, clear if unconditional. */
1345	#define IEMBRANCHED_F_CONDITIONAL UINT8_C(0x08)
1346	/** Flag set if it's a far branch. */
1347	#define IEMBRANCHED_F_FAR UINT8_C(0x10)
1348	/** Flag set if the stack pointer is modified. */
1349	#define IEMBRANCHED_F_STACK UINT8_C(0x20)
1350	/** Flag set if the stack pointer and (maybe) the stack segment are modified. */
1351	#define IEMBRANCHED_F_STACK_FAR UINT8_C(0x40)
1352	/** Flag set (by IEM_MC_REL_JMP_XXX) if it's a zero bytes relative jump. */
1353	#define IEMBRANCHED_F_ZERO UINT8_C(0x80)
1354	/** @} */
1355
1356
1357	/**
1358	* The per-CPU IEM state.
1359	*/
1360	typedef struct IEMCPU
1361	{
1362	/** Info status code that needs to be propagated to the IEM caller.
1363	* This cannot be passed internally, as it would complicate all success
1364	* checks within the interpreter making the code larger and almost impossible
1365	* to get right. Instead, we'll store status codes to pass on here. Each
1366	* source of these codes will perform appropriate sanity checks. */
1367	int32_t rcPassUp; /* 0x00 */
1368	/** Execution flag, IEM_F_XXX. */
1369	uint32_t fExec; /* 0x04 */
1370
1371	/** @name Decoder state.
1372	* @{ */
1373	#ifdef IEM_WITH_CODE_TLB
1374	/** The offset of the next instruction byte. */
1375	uint32_t offInstrNextByte; /* 0x08 */
1376	/** The number of bytes available at pbInstrBuf for the current instruction.
1377	* This takes the max opcode length into account so that doesn't need to be
1378	* checked separately. */
1379	uint32_t cbInstrBuf; /* 0x0c */
1380	/** Pointer to the page containing RIP, user specified buffer or abOpcode.
1381	* This can be NULL if the page isn't mappable for some reason, in which
1382	* case we'll do fallback stuff.
1383	*
1384	* If we're executing an instruction from a user specified buffer,
1385	* IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
1386	* aligned pointer but pointer to the user data.
1387	*
1388	* For instructions crossing pages, this will start on the first page and be
1389	* advanced to the next page by the time we've decoded the instruction. This
1390	* therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
1391	*/
1392	uint8_t const pbInstrBuf; / 0x10 */
1393	# if ARCH_BITS == 32
1394	uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
1395	# endif
1396	/** The program counter corresponding to pbInstrBuf.
1397	* This is set to a non-canonical address when we need to invalidate it. */
1398	uint64_t uInstrBufPc; /* 0x18 */
1399	/** The guest physical address corresponding to pbInstrBuf. */
1400	RTGCPHYS GCPhysInstrBuf; /* 0x20 */
1401	/** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
1402	* This takes the CS segment limit into account.
1403	* @note Set to zero when the code TLB is flushed to trigger TLB reload. */
1404	uint16_t cbInstrBufTotal; /* 0x28 */
1405	# ifndef IEM_WITH_OPAQUE_DECODER_STATE
1406	/** Offset into pbInstrBuf of the first byte of the current instruction.
1407	* Can be negative to efficiently handle cross page instructions. */
1408	int16_t offCurInstrStart; /* 0x2a */
1409
1410	/** The prefix mask (IEM_OP_PRF_XXX). */
1411	uint32_t fPrefixes; /* 0x2c */
1412	/** The extra REX ModR/M register field bit (REX.R << 3). */
1413	uint8_t uRexReg; /* 0x30 */
1414	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
1415	* (REX.B << 3). */
1416	uint8_t uRexB; /* 0x31 */
1417	/** The extra REX SIB index field bit (REX.X << 3). */
1418	uint8_t uRexIndex; /* 0x32 */
1419
1420	/** The effective segment register (X86_SREG_XXX). */
1421	uint8_t iEffSeg; /* 0x33 */
1422
1423	/** The offset of the ModR/M byte relative to the start of the instruction. */
1424	uint8_t offModRm; /* 0x34 */
1425
1426	# ifdef IEM_WITH_CODE_TLB_AND_OPCODE_BUF
1427	/** The current offset into abOpcode. */
1428	uint8_t offOpcode; /* 0x35 */
1429	# else
1430	uint8_t bUnused; /* 0x35 */
1431	# endif
1432	# else /* IEM_WITH_OPAQUE_DECODER_STATE */
1433	uint8_t abOpaqueDecoderPart1[0x36 - 0x2a];
1434	# endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1435
1436	#else /* !IEM_WITH_CODE_TLB */
1437	# ifndef IEM_WITH_OPAQUE_DECODER_STATE
1438	/** The size of what has currently been fetched into abOpcode. */
1439	uint8_t cbOpcode; /* 0x08 */
1440	/** The current offset into abOpcode. */
1441	uint8_t offOpcode; /* 0x09 */
1442	/** The offset of the ModR/M byte relative to the start of the instruction. */
1443	uint8_t offModRm; /* 0x0a */
1444
1445	/** The effective segment register (X86_SREG_XXX). */
1446	uint8_t iEffSeg; /* 0x0b */
1447
1448	/** The prefix mask (IEM_OP_PRF_XXX). */
1449	uint32_t fPrefixes; /* 0x0c */
1450	/** The extra REX ModR/M register field bit (REX.R << 3). */
1451	uint8_t uRexReg; /* 0x10 */
1452	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
1453	* (REX.B << 3). */
1454	uint8_t uRexB; /* 0x11 */
1455	/** The extra REX SIB index field bit (REX.X << 3). */
1456	uint8_t uRexIndex; /* 0x12 */
1457
1458	# else /* IEM_WITH_OPAQUE_DECODER_STATE */
1459	uint8_t abOpaqueDecoderPart1[0x13 - 0x08];
1460	# endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1461	#endif /* !IEM_WITH_CODE_TLB */
1462
1463	#ifndef IEM_WITH_OPAQUE_DECODER_STATE
1464	/** The effective operand mode. */
1465	IEMMODE enmEffOpSize; /* 0x36, 0x13 */
1466	/** The default addressing mode. */
1467	IEMMODE enmDefAddrMode; /* 0x37, 0x14 */
1468	/** The effective addressing mode. */
1469	IEMMODE enmEffAddrMode; /* 0x38, 0x15 */
1470	/** The default operand mode. */
1471	IEMMODE enmDefOpSize; /* 0x39, 0x16 */
1472
1473	/** Prefix index (VEX.pp) for two byte and three byte tables. */
1474	uint8_t idxPrefix; /* 0x3a, 0x17 */
1475	/** 3rd VEX/EVEX/XOP register.
1476	* Please use IEM_GET_EFFECTIVE_VVVV to access. */
1477	uint8_t uVex3rdReg; /* 0x3b, 0x18 */
1478	/** The VEX/EVEX/XOP length field. */
1479	uint8_t uVexLength; /* 0x3c, 0x19 */
1480	/** Additional EVEX stuff. */
1481	uint8_t fEvexStuff; /* 0x3d, 0x1a */
1482
1483	# ifndef IEM_WITH_CODE_TLB
1484	/** Explicit alignment padding. */
1485	uint8_t abAlignment2a[1]; /* 0x1b */
1486	# endif
1487	/** The FPU opcode (FOP). */
1488	uint16_t uFpuOpcode; /* 0x3e, 0x1c */
1489	# ifndef IEM_WITH_CODE_TLB
1490	/** Explicit alignment padding. */
1491	uint8_t abAlignment2b[2]; /* 0x1e */
1492	# endif
1493
1494	/** The opcode bytes. */
1495	uint8_t abOpcode[15]; /* 0x40, 0x20 */
1496	/** Explicit alignment padding. */
1497	# ifdef IEM_WITH_CODE_TLB
1498	//uint8_t abAlignment2c[0x4f - 0x4f]; /* 0x4f */
1499	# else
1500	uint8_t abAlignment2c[0x4f - 0x2f]; /* 0x2f */
1501	# endif
1502
1503	#else /* IEM_WITH_OPAQUE_DECODER_STATE */
1504	# ifdef IEM_WITH_CODE_TLB
1505	uint8_t abOpaqueDecoderPart2[0x4f - 0x36];
1506	# else
1507	uint8_t abOpaqueDecoderPart2[0x4f - 0x13];
1508	# endif
1509	#endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1510	/** @} */
1511
1512
1513	/** The number of active guest memory mappings. */
1514	uint8_t cActiveMappings; /* 0x4f, 0x4f */
1515
1516	/** Records for tracking guest memory mappings. */
1517	struct
1518	{
1519	/** The address of the mapped bytes. */
1520	R3R0PTRTYPE(void *) pv;
1521	/** The access flags (IEM_ACCESS_XXX).
1522	* IEM_ACCESS_INVALID if the entry is unused. */
1523	uint32_t fAccess;
1524	#if HC_ARCH_BITS == 64
1525	uint32_t u32Alignment4; /*< Alignment padding. /
1526	#endif
1527	} aMemMappings[3]; /* 0x50 LB 0x30 */
1528
1529	/** Locking records for the mapped memory. */
1530	union
1531	{
1532	PGMPAGEMAPLOCK Lock;
1533	uint64_t au64Padding[2];
1534	} aMemMappingLocks[3]; /* 0x80 LB 0x30 */
1535
1536	/** Bounce buffer info.
1537	* This runs in parallel to aMemMappings. */
1538	struct
1539	{
1540	/** The physical address of the first byte. */
1541	RTGCPHYS GCPhysFirst;
1542	/** The physical address of the second page. */
1543	RTGCPHYS GCPhysSecond;
1544	/** The number of bytes in the first page. */
1545	uint16_t cbFirst;
1546	/** The number of bytes in the second page. */
1547	uint16_t cbSecond;
1548	/** Whether it's unassigned memory. */
1549	bool fUnassigned;
1550	/** Explicit alignment padding. */
1551	bool afAlignment5[3];
1552	} aMemBbMappings[3]; /* 0xb0 LB 0x48 */
1553
1554	/** The flags of the current exception / interrupt. */
1555	uint32_t fCurXcpt; /* 0xf8 */
1556	/** The current exception / interrupt. */
1557	uint8_t uCurXcpt; /* 0xfc */
1558	/** Exception / interrupt recursion depth. */
1559	int8_t cXcptRecursions; /* 0xfb */
1560
1561	/** The next unused mapping index.
1562	* @todo try find room for this up with cActiveMappings. */
1563	uint8_t iNextMapping; /* 0xfd */
1564	uint8_t abAlignment7[1];
1565
1566	/** Bounce buffer storage.
1567	* This runs in parallel to aMemMappings and aMemBbMappings. */
1568	struct
1569	{
1570	uint8_t ab[512];
1571	} aBounceBuffers[3]; /* 0x100 LB 0x600 */
1572
1573
1574	/** Pointer set jump buffer - ring-3 context. */
1575	R3PTRTYPE(jmp_buf *) pJmpBufR3;
1576	/** Pointer set jump buffer - ring-0 context. */
1577	R0PTRTYPE(jmp_buf *) pJmpBufR0;
1578
1579	/** @todo Should move this near @a fCurXcpt later. */
1580	/** The CR2 for the current exception / interrupt. */
1581	uint64_t uCurXcptCr2;
1582	/** The error code for the current exception / interrupt. */
1583	uint32_t uCurXcptErr;
1584
1585	/** @name Statistics
1586	* @{ */
1587	/** The number of instructions we've executed. */
1588	uint32_t cInstructions;
1589	/** The number of potential exits. */
1590	uint32_t cPotentialExits;
1591	/** The number of bytes data or stack written (mostly for IEMExecOneEx).
1592	* This may contain uncommitted writes. */
1593	uint32_t cbWritten;
1594	/** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
1595	uint32_t cRetInstrNotImplemented;
1596	/** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
1597	uint32_t cRetAspectNotImplemented;
1598	/** Counts informational statuses returned (other than VINF_SUCCESS). */
1599	uint32_t cRetInfStatuses;
1600	/** Counts other error statuses returned. */
1601	uint32_t cRetErrStatuses;
1602	/** Number of times rcPassUp has been used. */
1603	uint32_t cRetPassUpStatus;
1604	/** Number of times RZ left with instruction commit pending for ring-3. */
1605	uint32_t cPendingCommit;
1606	/** Number of long jumps. */
1607	uint32_t cLongJumps;
1608	/** @} */
1609
1610	/** @name Target CPU information.
1611	* @{ */
1612	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
1613	/** The target CPU. */
1614	uint8_t uTargetCpu;
1615	#else
1616	uint8_t bTargetCpuPadding;
1617	#endif
1618	/** For selecting assembly works matching the target CPU EFLAGS behaviour, see
1619	* IEMTARGETCPU_EFL_BEHAVIOR_XXX for values, with the 1st entry for when no
1620	* native host support and the 2nd for when there is.
1621	*
1622	* The two values are typically indexed by a g_CpumHostFeatures bit.
1623	*
1624	* This is for instance used for the BSF & BSR instructions where AMD and
1625	* Intel CPUs produce different EFLAGS. */
1626	uint8_t aidxTargetCpuEflFlavour[2];
1627
1628	/** The CPU vendor. */
1629	CPUMCPUVENDOR enmCpuVendor;
1630	/** @} */
1631
1632	/** @name Host CPU information.
1633	* @{ */
1634	/** The CPU vendor. */
1635	CPUMCPUVENDOR enmHostCpuVendor;
1636	/** @} */
1637
1638	/** Counts RDMSR \#GP(0) LogRel(). */
1639	uint8_t cLogRelRdMsr;
1640	/** Counts WRMSR \#GP(0) LogRel(). */
1641	uint8_t cLogRelWrMsr;
1642	/** Alignment padding. */
1643	uint8_t abAlignment9[46];
1644
1645	/** @name Recompilation
1646	* @{ */
1647	/** Pointer to the current translation block.
1648	* This can either be one being executed or one being compiled. */
1649	R3PTRTYPE(PIEMTB) pCurTbR3;
1650	/** Fixed TB used for threaded recompilation.
1651	* This is allocated once with maxed-out sizes and re-used afterwards. */
1652	R3PTRTYPE(PIEMTB) pThrdCompileTbR3;
1653	/** Pointer to the ring-3 TB cache for this EMT. */
1654	R3PTRTYPE(PIEMTBCACHE) pTbCacheR3;
1655	/** The PC (RIP) at the start of pCurTbR3/pCurTbR0.
1656	* The TBs are based on physical addresses, so this is needed to correleated
1657	* RIP to opcode bytes stored in the TB (AMD-V / VT-x). */
1658	uint64_t uCurTbStartPc;
1659	/** Number of threaded TBs executed. */
1660	uint64_t cTbExecThreaded;
1661	/** Number of native TBs executed. */
1662	uint64_t cTbExecNative;
1663	/** Whether we need to check the opcode bytes for the current instruction.
1664	* This is set by a previous instruction if it modified memory or similar. */
1665	bool fTbCheckOpcodes;
1666	/** Indicates whether and how we just branched - IEMBRANCHED_F_XXX. */
1667	uint8_t fTbBranched;
1668	/** Set when GCPhysInstrBuf is updated because of a page crossing. */
1669	bool fTbCrossedPage;
1670	/** Whether to end the current TB. */
1671	bool fEndTb;
1672	/** Number of instructions before we need emit an IRQ check call again.
1673	* This helps making sure we don't execute too long w/o checking for
1674	* interrupts and immediately following instructions that may enable
1675	* interrupts (e.g. POPF, IRET, STI). With STI an additional hack is
1676	* required to make sure we check following the next instruction as well, see
1677	* fTbCurInstrIsSti. */
1678	uint8_t cInstrTillIrqCheck;
1679	/** Indicates that the current instruction is an STI. This is set by the
1680	* iemCImpl_sti code and subsequently cleared by the recompiler. */
1681	bool fTbCurInstrIsSti;
1682	/** The size of the IEMTB::pabOpcodes allocation in pThrdCompileTbR3. */
1683	uint16_t cbOpcodesAllocated;
1684	/** The current instruction number in a native TB.
1685	* This is set by code that may trigger an unexpected TB exit (throw/longjmp)
1686	* and will be picked up by the TB execution loop. Only used when
1687	* IEMNATIVE_WITH_INSTRUCTION_COUNTING is defined. */
1688	uint8_t idxTbCurInstr;
1689	/** Spaced reserved for recompiler data / alignment. */
1690	bool afRecompilerStuff1[3];
1691	/** The virtual sync time at the last timer poll call. */
1692	uint32_t msRecompilerPollNow;
1693	/** The IEM_CIMPL_F_XXX mask for the current instruction. */
1694	uint32_t fTbCurInstr;
1695	/** The IEM_CIMPL_F_XXX mask for the previous instruction. */
1696	uint32_t fTbPrevInstr;
1697	/** Previous GCPhysInstrBuf value - only valid if fTbCrossedPage is set. */
1698	RTGCPHYS GCPhysInstrBufPrev;
1699	/** Copy of IEMCPU::GCPhysInstrBuf after decoding a branch instruction.
1700	* This is used together with fTbBranched and GCVirtTbBranchSrcBuf to determin
1701	* whether a branch instruction jumps to a new page or stays within the
1702	* current one. */
1703	RTGCPHYS GCPhysTbBranchSrcBuf;
1704	/** Copy of IEMCPU::uInstrBufPc after decoding a branch instruction. */
1705	uint64_t GCVirtTbBranchSrcBuf;
1706	/** Pointer to the ring-3 TB allocator for this EMT. */
1707	R3PTRTYPE(PIEMTBALLOCATOR) pTbAllocatorR3;
1708	/** Pointer to the ring-3 executable memory allocator for this EMT. */
1709	R3PTRTYPE(struct IEMEXECMEMALLOCATOR *) pExecMemAllocatorR3;
1710	/** Pointer to the native recompiler state for ring-3. */
1711	R3PTRTYPE(struct IEMRECOMPILERSTATE *) pNativeRecompilerStateR3;
1712
1713	/** Statistics: Times TB execution was broken off before reaching the end. */
1714	STAMCOUNTER StatTbExecBreaks;
1715	/** Statistics: Times BltIn_CheckIrq breaks out of the TB. */
1716	STAMCOUNTER StatCheckIrqBreaks;
1717	/** Statistics: Times BltIn_CheckMode breaks out of the TB. */
1718	STAMCOUNTER StatCheckModeBreaks;
1719	/** Statistics: Times a post jump target check missed and had to find new TB. */
1720	STAMCOUNTER StatCheckBranchMisses;
1721	/** Statistics: Times a jump or page crossing required a TB with CS.LIM checking. */
1722	STAMCOUNTER StatCheckNeedCsLimChecking;
1723	/** Native TB statistics: Number of fully recompiled TBs. */
1724	STAMCOUNTER StatNativeFullyRecompiledTbs;
1725	/** Threaded TB statistics: Number of instructions per TB. */
1726	STAMPROFILE StatTbThreadedInstr;
1727	/** Threaded TB statistics: Number of calls per TB. */
1728	STAMPROFILE StatTbThreadedCalls;
1729	/** Native TB statistics: Native code size per TB. */
1730	STAMPROFILE StatTbNativeCode;
1731	/** Native TB statistics: Profiling native recompilation. */
1732	STAMPROFILE StatNativeRecompilation;
1733	/** Native TB statistics: Number of calls per TB that were recompiled properly. */
1734	STAMPROFILE StatNativeCallsRecompiled;
1735	/** Native TB statistics: Number of threaded calls per TB that weren't recompiled. */
1736	STAMPROFILE StatNativeCallsThreaded;
1737	/** Native recompiled execution: TLB hits for data fetches. */
1738	STAMCOUNTER StatNativeTlbHitsForFetch;
1739	/** Native recompiled execution: TLB hits for data stores. */
1740	STAMCOUNTER StatNativeTlbHitsForStore;
1741	/** Native recompiled execution: TLB hits for stack accesses. */
1742	STAMCOUNTER StatNativeTlbHitsForStack;
1743	/** Native recompiled execution: TLB hits for mapped accesses. */
1744	STAMCOUNTER StatNativeTlbHitsForMapped;
1745	uint64_t au64Padding[7];
1746	/** @} */
1747
1748	/** Data TLB.
1749	* @remarks Must be 64-byte aligned. */
1750	IEMTLB DataTlb;
1751	/** Instruction TLB.
1752	* @remarks Must be 64-byte aligned. */
1753	IEMTLB CodeTlb;
1754
1755	/** Exception statistics. */
1756	STAMCOUNTER aStatXcpts[32];
1757	/** Interrupt statistics. */
1758	uint32_t aStatInts[256];
1759
1760	#if defined(VBOX_WITH_STATISTICS) && !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
1761	/** Instruction statistics for ring-0/raw-mode. */
1762	IEMINSTRSTATS StatsRZ;
1763	/** Instruction statistics for ring-3. */
1764	IEMINSTRSTATS StatsR3;
1765	#endif
1766	} IEMCPU;
1767	AssertCompileMemberOffset(IEMCPU, cActiveMappings, 0x4f);
1768	AssertCompileMemberAlignment(IEMCPU, aMemMappings, 16);
1769	AssertCompileMemberAlignment(IEMCPU, aMemMappingLocks, 16);
1770	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 64);
1771	AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
1772	AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
1773
1774	/** Pointer to the per-CPU IEM state. */
1775	typedef IEMCPU *PIEMCPU;
1776	/** Pointer to the const per-CPU IEM state. */
1777	typedef IEMCPU const *PCIEMCPU;
1778
1779
1780	/** @def IEM_GET_CTX
1781	* Gets the guest CPU context for the calling EMT.
1782	* @returns PCPUMCTX
1783	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1784	*/
1785	#define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
1786
1787	/** @def IEM_CTX_ASSERT
1788	* Asserts that the @a a_fExtrnMbz is present in the CPU context.
1789	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1790	* @param a_fExtrnMbz The mask of CPUMCTX_EXTRN_XXX flags that must be zero.
1791	*/
1792	#define IEM_CTX_ASSERT(a_pVCpu, a_fExtrnMbz) \
1793	AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
1794	("fExtrn=%#RX64 & fExtrnMbz=%#RX64 -> %#RX64\n", \
1795	(a_pVCpu)->cpum.GstCtx.fExtrn, (a_fExtrnMbz), (a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz) ))
1796
1797	/** @def IEM_CTX_IMPORT_RET
1798	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
1799	*
1800	* Will call the keep to import the bits as needed.
1801	*
1802	* Returns on import failure.
1803	*
1804	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1805	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
1806	*/
1807	#define IEM_CTX_IMPORT_RET(a_pVCpu, a_fExtrnImport) \
1808	do { \
1809	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
1810	{ /* likely */ } \
1811	else \
1812	{ \
1813	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
1814	AssertRCReturn(rcCtxImport, rcCtxImport); \
1815	} \
1816	} while (0)
1817
1818	/** @def IEM_CTX_IMPORT_NORET
1819	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
1820	*
1821	* Will call the keep to import the bits as needed.
1822	*
1823	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1824	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
1825	*/
1826	#define IEM_CTX_IMPORT_NORET(a_pVCpu, a_fExtrnImport) \
1827	do { \
1828	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
1829	{ /* likely */ } \
1830	else \
1831	{ \
1832	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
1833	AssertLogRelRC(rcCtxImport); \
1834	} \
1835	} while (0)
1836
1837	/** @def IEM_CTX_IMPORT_JMP
1838	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
1839	*
1840	* Will call the keep to import the bits as needed.
1841	*
1842	* Jumps on import failure.
1843	*
1844	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1845	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
1846	*/
1847	#define IEM_CTX_IMPORT_JMP(a_pVCpu, a_fExtrnImport) \
1848	do { \
1849	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
1850	{ /* likely */ } \
1851	else \
1852	{ \
1853	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
1854	AssertRCStmt(rcCtxImport, IEM_DO_LONGJMP(pVCpu, rcCtxImport)); \
1855	} \
1856	} while (0)
1857
1858
1859
1860	/** @def IEM_GET_TARGET_CPU
1861	* Gets the current IEMTARGETCPU value.
1862	* @returns IEMTARGETCPU value.
1863	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1864	*/
1865	#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
1866	# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
1867	#else
1868	# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
1869	#endif
1870
1871	/** @def IEM_GET_INSTR_LEN
1872	* Gets the instruction length. */
1873	#ifdef IEM_WITH_CODE_TLB
1874	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
1875	#else
1876	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
1877	#endif
1878
1879	/** @def IEM_TRY_SETJMP
1880	* Wrapper around setjmp / try, hiding all the ugly differences.
1881	*
1882	* @note Use with extreme care as this is a fragile macro.
1883	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
1884	* @param a_rcTarget The variable that should receive the status code in case
1885	* of a longjmp/throw.
1886	*/
1887	/** @def IEM_TRY_SETJMP_AGAIN
1888	* For when setjmp / try is used again in the same variable scope as a previous
1889	* IEM_TRY_SETJMP invocation.
1890	*/
1891	/** @def IEM_CATCH_LONGJMP_BEGIN
1892	* Start wrapper for catch / setjmp-else.
1893	*
1894	* This will set up a scope.
1895	*
1896	* @note Use with extreme care as this is a fragile macro.
1897	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
1898	* @param a_rcTarget The variable that should receive the status code in case
1899	* of a longjmp/throw.
1900	*/
1901	/** @def IEM_CATCH_LONGJMP_END
1902	* End wrapper for catch / setjmp-else.
1903	*
1904	* This will close the scope set up by IEM_CATCH_LONGJMP_BEGIN and clean up the
1905	* state.
1906	*
1907	* @note Use with extreme care as this is a fragile macro.
1908	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
1909	*/
1910	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
1911	# ifdef IEM_WITH_THROW_CATCH
1912	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
1913	a_rcTarget = VINF_SUCCESS; \
1914	try
1915	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
1916	IEM_TRY_SETJMP(a_pVCpu, a_rcTarget)
1917	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
1918	catch (int rcThrown) \
1919	{ \
1920	a_rcTarget = rcThrown
1921	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
1922	} \
1923	((void)0)
1924	# else /* !IEM_WITH_THROW_CATCH */
1925	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
1926	jmp_buf JmpBuf; \
1927	jmp_buf * volatile pSavedJmpBuf = (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf); \
1928	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
1929	if ((rcStrict = setjmp(JmpBuf)) == 0)
1930	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
1931	pSavedJmpBuf = (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf); \
1932	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
1933	if ((rcStrict = setjmp(JmpBuf)) == 0)
1934	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
1935	else \
1936	{ \
1937	((void)0)
1938	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
1939	} \
1940	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = pSavedJmpBuf
1941	# endif /* !IEM_WITH_THROW_CATCH */
1942	#endif /* IEM_WITH_SETJMP */
1943
1944
1945	/**
1946	* Shared per-VM IEM data.
1947	*/
1948	typedef struct IEM
1949	{
1950	/** The VMX APIC-access page handler type. */
1951	PGMPHYSHANDLERTYPE hVmxApicAccessPage;
1952	#ifndef VBOX_WITHOUT_CPUID_HOST_CALL
1953	/** Set if the CPUID host call functionality is enabled. */
1954	bool fCpuIdHostCall;
1955	#endif
1956	} IEM;
1957
1958
1959
1960	/** @name IEM_ACCESS_XXX - Access details.
1961	* @{ */
1962	#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
1963	#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
1964	#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
1965	#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
1966	#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
1967	#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
1968	#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
1969	#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
1970	#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
1971	#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
1972	/** The writes are partial, so if initialize the bounce buffer with the
1973	* orignal RAM content. */
1974	#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
1975	/** Used in aMemMappings to indicate that the entry is bounce buffered. */
1976	#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
1977	/** Bounce buffer with ring-3 write pending, first page. */
1978	#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
1979	/** Bounce buffer with ring-3 write pending, second page. */
1980	#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
1981	/** Not locked, accessed via the TLB. */
1982	#define IEM_ACCESS_NOT_LOCKED UINT32_C(0x00001000)
1983	/** Valid bit mask. */
1984	#define IEM_ACCESS_VALID_MASK UINT32_C(0x00001fff)
1985	/** Shift count for the TLB flags (upper word). */
1986	#define IEM_ACCESS_SHIFT_TLB_FLAGS 16
1987
1988	/** Read+write data alias. */
1989	#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
1990	/** Write data alias. */
1991	#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
1992	/** Read data alias. */
1993	#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_DATA)
1994	/** Instruction fetch alias. */
1995	#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_WHAT_CODE)
1996	/** Stack write alias. */
1997	#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
1998	/** Stack read alias. */
1999	#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_STACK)
2000	/** Stack read+write alias. */
2001	#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
2002	/** Read system table alias. */
2003	#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_SYS)
2004	/** Read+write system table alias. */
2005	#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_SYS)
2006	/** @} */
2007
2008	/** @name Prefix constants (IEMCPU::fPrefixes)
2009	* @{ */
2010	#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /*< CS segment prefix (0x2e). /
2011	#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /*< SS segment prefix (0x36). /
2012	#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /*< DS segment prefix (0x3e). /
2013	#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /*< ES segment prefix (0x26). /
2014	#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /*< FS segment prefix (0x64). /
2015	#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /*< GS segment prefix (0x65). /
2016	#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
2017
2018	#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /*< Operand size prefix (0x66). /
2019	#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /*< REX.W prefix (0x48-0x4f). /
2020	#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /*< Address size prefix (0x67). /
2021
2022	#define IEM_OP_PRF_LOCK RT_BIT_32(16) /*< Lock prefix (0xf0). /
2023	#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /*< Repeat-not-zero prefix (0xf2). /
2024	#define IEM_OP_PRF_REPZ RT_BIT_32(18) /*< Repeat-if-zero prefix (0xf3). /
2025
2026	#define IEM_OP_PRF_REX RT_BIT_32(24) /*< Any REX prefix (0x40-0x4f). /
2027	#define IEM_OP_PRF_REX_R RT_BIT_32(25) /*< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). /
2028	#define IEM_OP_PRF_REX_B RT_BIT_32(26) /*< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). /
2029	#define IEM_OP_PRF_REX_X RT_BIT_32(27) /*< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). /
2030	/** Mask with all the REX prefix flags.
2031	* This is generally for use when needing to undo the REX prefixes when they
2032	* are followed legacy prefixes and therefore does not immediately preceed
2033	* the first opcode byte.
2034	* For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
2035	#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX \| IEM_OP_PRF_REX_R \| IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X \| IEM_OP_PRF_SIZE_REX_W )
2036
2037	#define IEM_OP_PRF_VEX RT_BIT_32(28) /*< Indiciates VEX prefix. /
2038	#define IEM_OP_PRF_EVEX RT_BIT_32(29) /*< Indiciates EVEX prefix. /
2039	#define IEM_OP_PRF_XOP RT_BIT_32(30) /*< Indiciates XOP prefix. /
2040	/** @} */
2041
2042	/** @name IEMOPFORM_XXX - Opcode forms
2043	* @note These are ORed together with IEMOPHINT_XXX.
2044	* @{ */
2045	/** ModR/M: reg, r/m */
2046	#define IEMOPFORM_RM 0
2047	/** ModR/M: reg, r/m (register) */
2048	#define IEMOPFORM_RM_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
2049	/** ModR/M: reg, r/m (memory) */
2050	#define IEMOPFORM_RM_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
2051	/** ModR/M: reg, r/m */
2052	#define IEMOPFORM_RMI 1
2053	/** ModR/M: reg, r/m (register) */
2054	#define IEMOPFORM_RMI_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
2055	/** ModR/M: reg, r/m (memory) */
2056	#define IEMOPFORM_RMI_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
2057	/** ModR/M: r/m, reg */
2058	#define IEMOPFORM_MR 2
2059	/** ModR/M: r/m (register), reg */
2060	#define IEMOPFORM_MR_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
2061	/** ModR/M: r/m (memory), reg */
2062	#define IEMOPFORM_MR_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
2063	/** ModR/M: r/m, reg */
2064	#define IEMOPFORM_MRI 3
2065	/** ModR/M: r/m (register), reg */
2066	#define IEMOPFORM_MRI_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
2067	/** ModR/M: r/m (memory), reg */
2068	#define IEMOPFORM_MRI_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
2069	/** ModR/M: r/m only */
2070	#define IEMOPFORM_M 4
2071	/** ModR/M: r/m only (register). */
2072	#define IEMOPFORM_M_REG (IEMOPFORM_M \| IEMOPFORM_MOD3)
2073	/** ModR/M: r/m only (memory). */
2074	#define IEMOPFORM_M_MEM (IEMOPFORM_M \| IEMOPFORM_NOT_MOD3)
2075	/** ModR/M: reg only */
2076	#define IEMOPFORM_R 5
2077
2078	/** VEX+ModR/M: reg, r/m */
2079	#define IEMOPFORM_VEX_RM 8
2080	/** VEX+ModR/M: reg, r/m (register) */
2081	#define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM \| IEMOPFORM_MOD3)
2082	/** VEX+ModR/M: reg, r/m (memory) */
2083	#define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM \| IEMOPFORM_NOT_MOD3)
2084	/** VEX+ModR/M: r/m, reg */
2085	#define IEMOPFORM_VEX_MR 9
2086	/** VEX+ModR/M: r/m (register), reg */
2087	#define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR \| IEMOPFORM_MOD3)
2088	/** VEX+ModR/M: r/m (memory), reg */
2089	#define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR \| IEMOPFORM_NOT_MOD3)
2090	/** VEX+ModR/M: r/m only */
2091	#define IEMOPFORM_VEX_M 10
2092	/** VEX+ModR/M: r/m only (register). */
2093	#define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M \| IEMOPFORM_MOD3)
2094	/** VEX+ModR/M: r/m only (memory). */
2095	#define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M \| IEMOPFORM_NOT_MOD3)
2096	/** VEX+ModR/M: reg only */
2097	#define IEMOPFORM_VEX_R 11
2098	/** VEX+ModR/M: reg, vvvv, r/m */
2099	#define IEMOPFORM_VEX_RVM 12
2100	/** VEX+ModR/M: reg, vvvv, r/m (register). */
2101	#define IEMOPFORM_VEX_RVM_REG (IEMOPFORM_VEX_RVM \| IEMOPFORM_MOD3)
2102	/** VEX+ModR/M: reg, vvvv, r/m (memory). */
2103	#define IEMOPFORM_VEX_RVM_MEM (IEMOPFORM_VEX_RVM \| IEMOPFORM_NOT_MOD3)
2104	/** VEX+ModR/M: reg, r/m, vvvv */
2105	#define IEMOPFORM_VEX_RMV 13
2106	/** VEX+ModR/M: reg, r/m, vvvv (register). */
2107	#define IEMOPFORM_VEX_RMV_REG (IEMOPFORM_VEX_RMV \| IEMOPFORM_MOD3)
2108	/** VEX+ModR/M: reg, r/m, vvvv (memory). */
2109	#define IEMOPFORM_VEX_RMV_MEM (IEMOPFORM_VEX_RMV \| IEMOPFORM_NOT_MOD3)
2110	/** VEX+ModR/M: reg, r/m, imm8 */
2111	#define IEMOPFORM_VEX_RMI 14
2112	/** VEX+ModR/M: reg, r/m, imm8 (register). */
2113	#define IEMOPFORM_VEX_RMI_REG (IEMOPFORM_VEX_RMI \| IEMOPFORM_MOD3)
2114	/** VEX+ModR/M: reg, r/m, imm8 (memory). */
2115	#define IEMOPFORM_VEX_RMI_MEM (IEMOPFORM_VEX_RMI \| IEMOPFORM_NOT_MOD3)
2116	/** VEX+ModR/M: r/m, vvvv, reg */
2117	#define IEMOPFORM_VEX_MVR 15
2118	/** VEX+ModR/M: r/m, vvvv, reg (register) */
2119	#define IEMOPFORM_VEX_MVR_REG (IEMOPFORM_VEX_MVR \| IEMOPFORM_MOD3)
2120	/** VEX+ModR/M: r/m, vvvv, reg (memory) */
2121	#define IEMOPFORM_VEX_MVR_MEM (IEMOPFORM_VEX_MVR \| IEMOPFORM_NOT_MOD3)
2122	/** VEX+ModR/M+/n: vvvv, r/m */
2123	#define IEMOPFORM_VEX_VM 16
2124	/** VEX+ModR/M+/n: vvvv, r/m (register) */
2125	#define IEMOPFORM_VEX_VM_REG (IEMOPFORM_VEX_VM \| IEMOPFORM_MOD3)
2126	/** VEX+ModR/M+/n: vvvv, r/m (memory) */
2127	#define IEMOPFORM_VEX_VM_MEM (IEMOPFORM_VEX_VM \| IEMOPFORM_NOT_MOD3)
2128
2129	/** Fixed register instruction, no R/M. */
2130	#define IEMOPFORM_FIXED 32
2131
2132	/** The r/m is a register. */
2133	#define IEMOPFORM_MOD3 RT_BIT_32(8)
2134	/** The r/m is a memory access. */
2135	#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
2136	/** @} */
2137
2138	/** @name IEMOPHINT_XXX - Additional Opcode Hints
2139	* @note These are ORed together with IEMOPFORM_XXX.
2140	* @{ */
2141	/** Ignores the operand size prefix (66h). */
2142	#define IEMOPHINT_IGNORES_OZ_PFX RT_BIT_32(10)
2143	/** Ignores REX.W (aka WIG). */
2144	#define IEMOPHINT_IGNORES_REXW RT_BIT_32(11)
2145	/** Both the operand size prefixes (66h + REX.W) are ignored. */
2146	#define IEMOPHINT_IGNORES_OP_SIZES (IEMOPHINT_IGNORES_OZ_PFX \| IEMOPHINT_IGNORES_REXW)
2147	/** Allowed with the lock prefix. */
2148	#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
2149	/** The VEX.L value is ignored (aka LIG). */
2150	#define IEMOPHINT_VEX_L_IGNORED RT_BIT_32(12)
2151	/** The VEX.L value must be zero (i.e. 128-bit width only). */
2152	#define IEMOPHINT_VEX_L_ZERO RT_BIT_32(13)
2153	/** The VEX.V value must be zero. */
2154	#define IEMOPHINT_VEX_V_ZERO RT_BIT_32(14)
2155
2156	/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
2157	#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
2158	/** @} */
2159
2160	/**
2161	* Possible hardware task switch sources.
2162	*/
2163	typedef enum IEMTASKSWITCH
2164	{
2165	/** Task switch caused by an interrupt/exception. */
2166	IEMTASKSWITCH_INT_XCPT = 1,
2167	/** Task switch caused by a far CALL. */
2168	IEMTASKSWITCH_CALL,
2169	/** Task switch caused by a far JMP. */
2170	IEMTASKSWITCH_JUMP,
2171	/** Task switch caused by an IRET. */
2172	IEMTASKSWITCH_IRET
2173	} IEMTASKSWITCH;
2174	AssertCompileSize(IEMTASKSWITCH, 4);
2175
2176	/**
2177	* Possible CrX load (write) sources.
2178	*/
2179	typedef enum IEMACCESSCRX
2180	{
2181	/** CrX access caused by 'mov crX' instruction. */
2182	IEMACCESSCRX_MOV_CRX,
2183	/** CrX (CR0) write caused by 'lmsw' instruction. */
2184	IEMACCESSCRX_LMSW,
2185	/** CrX (CR0) write caused by 'clts' instruction. */
2186	IEMACCESSCRX_CLTS,
2187	/** CrX (CR0) read caused by 'smsw' instruction. */
2188	IEMACCESSCRX_SMSW
2189	} IEMACCESSCRX;
2190
2191	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2192	/** @name IEM_SLAT_FAIL_XXX - Second-level address translation failure information.
2193	*
2194	* These flags provide further context to SLAT page-walk failures that could not be
2195	* determined by PGM (e.g, PGM is not privy to memory access permissions).
2196	*
2197	* @{
2198	*/
2199	/** Translating a nested-guest linear address failed accessing a nested-guest
2200	* physical address. */
2201	# define IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR RT_BIT_32(0)
2202	/** Translating a nested-guest linear address failed accessing a
2203	* paging-structure entry or updating accessed/dirty bits. */
2204	# define IEM_SLAT_FAIL_LINEAR_TO_PAGE_TABLE RT_BIT_32(1)
2205	/** @} */
2206
2207	DECLCALLBACK(FNPGMPHYSHANDLER) iemVmxApicAccessPageHandler;
2208	# ifndef IN_RING3
2209	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) iemVmxApicAccessPagePfHandler;
2210	# endif
2211	#endif
2212
2213	/**
2214	* Indicates to the verifier that the given flag set is undefined.
2215	*
2216	* Can be invoked again to add more flags.
2217	*
2218	* This is a NOOP if the verifier isn't compiled in.
2219	*
2220	* @note We're temporarily keeping this until code is converted to new
2221	* disassembler style opcode handling.
2222	*/
2223	#define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
2224
2225
2226	/** @def IEM_DECL_IMPL_TYPE
2227	* For typedef'ing an instruction implementation function.
2228	*
2229	* @param a_RetType The return type.
2230	* @param a_Name The name of the type.
2231	* @param a_ArgList The argument list enclosed in parentheses.
2232	*/
2233
2234	/** @def IEM_DECL_IMPL_DEF
2235	* For defining an instruction implementation function.
2236	*
2237	* @param a_RetType The return type.
2238	* @param a_Name The name of the type.
2239	* @param a_ArgList The argument list enclosed in parentheses.
2240	*/
2241
2242	#if defined(__GNUC__) && defined(RT_ARCH_X86)
2243	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2244	__attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
2245	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2246	__attribute__((__fastcall__, __nothrow__)) DECL_HIDDEN_ONLY(a_RetType) a_Name a_ArgList
2247	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2248	__attribute__((__fastcall__, __nothrow__)) DECL_HIDDEN_ONLY(a_RetType) a_Name a_ArgList
2249
2250	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
2251	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2252	a_RetType (__fastcall a_Name) a_ArgList
2253	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2254	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
2255	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2256	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
2257
2258	#elif __cplusplus >= 201700 /* P0012R1 support */
2259	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2260	a_RetType (VBOXCALL a_Name) a_ArgList RT_NOEXCEPT
2261	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2262	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList RT_NOEXCEPT
2263	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2264	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList RT_NOEXCEPT
2265
2266	#else
2267	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2268	a_RetType (VBOXCALL a_Name) a_ArgList
2269	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2270	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList
2271	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2272	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList
2273
2274	#endif
2275
2276	/** Defined in IEMAllAImplC.cpp but also used by IEMAllAImplA.asm. */
2277	RT_C_DECLS_BEGIN
2278	extern uint8_t const g_afParity[256];
2279	RT_C_DECLS_END
2280
2281
2282	/** @name Arithmetic assignment operations on bytes (binary).
2283	* @{ */
2284	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU8, (uint8_t pu8Dst, uint8_t u8Src, uint32_t pEFlags));
2285	typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
2286	FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
2287	FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
2288	FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
2289	FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
2290	FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
2291	FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
2292	FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
2293	/** @} */
2294
2295	/** @name Arithmetic assignment operations on words (binary).
2296	* @{ */
2297	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU16, (uint16_t pu16Dst, uint16_t u16Src, uint32_t pEFlags));
2298	typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
2299	FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
2300	FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
2301	FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
2302	FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
2303	FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
2304	FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
2305	FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
2306	/** @} */
2307
2308	/** @name Arithmetic assignment operations on double words (binary).
2309	* @{ */
2310	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU32, (uint32_t pu32Dst, uint32_t u32Src, uint32_t pEFlags));
2311	typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
2312	FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
2313	FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
2314	FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
2315	FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
2316	FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
2317	FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
2318	FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
2319	FNIEMAIMPLBINU32 iemAImpl_blsi_u32, iemAImpl_blsi_u32_fallback;
2320	FNIEMAIMPLBINU32 iemAImpl_blsr_u32, iemAImpl_blsr_u32_fallback;
2321	FNIEMAIMPLBINU32 iemAImpl_blsmsk_u32, iemAImpl_blsmsk_u32_fallback;
2322	/** @} */
2323
2324	/** @name Arithmetic assignment operations on quad words (binary).
2325	* @{ */
2326	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU64, (uint64_t pu64Dst, uint64_t u64Src, uint32_t pEFlags));
2327	typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
2328	FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
2329	FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
2330	FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
2331	FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
2332	FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
2333	FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
2334	FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
2335	FNIEMAIMPLBINU64 iemAImpl_blsi_u64, iemAImpl_blsi_u64_fallback;
2336	FNIEMAIMPLBINU64 iemAImpl_blsr_u64, iemAImpl_blsr_u64_fallback;
2337	FNIEMAIMPLBINU64 iemAImpl_blsmsk_u64, iemAImpl_blsmsk_u64_fallback;
2338	/** @} */
2339
2340	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINROU8,(uint8_t const pu8Dst, uint8_t u8Src, uint32_t pEFlags));
2341	typedef FNIEMAIMPLBINROU8 *PFNIEMAIMPLBINROU8;
2342	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINROU16,(uint16_t const pu16Dst, uint16_t u16Src, uint32_t pEFlags));
2343	typedef FNIEMAIMPLBINROU16 *PFNIEMAIMPLBINROU16;
2344	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINROU32,(uint32_t const pu32Dst, uint32_t u32Src, uint32_t pEFlags));
2345	typedef FNIEMAIMPLBINROU32 *PFNIEMAIMPLBINROU32;
2346	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINROU64,(uint64_t const pu64Dst, uint64_t u64Src, uint32_t pEFlags));
2347	typedef FNIEMAIMPLBINROU64 *PFNIEMAIMPLBINROU64;
2348
2349	/** @name Compare operations (thrown in with the binary ops).
2350	* @{ */
2351	FNIEMAIMPLBINROU8 iemAImpl_cmp_u8;
2352	FNIEMAIMPLBINROU16 iemAImpl_cmp_u16;
2353	FNIEMAIMPLBINROU32 iemAImpl_cmp_u32;
2354	FNIEMAIMPLBINROU64 iemAImpl_cmp_u64;
2355	/** @} */
2356
2357	/** @name Test operations (thrown in with the binary ops).
2358	* @{ */
2359	FNIEMAIMPLBINROU8 iemAImpl_test_u8;
2360	FNIEMAIMPLBINROU16 iemAImpl_test_u16;
2361	FNIEMAIMPLBINROU32 iemAImpl_test_u32;
2362	FNIEMAIMPLBINROU64 iemAImpl_test_u64;
2363	/** @} */
2364
2365	/** @name Bit operations operations (thrown in with the binary ops).
2366	* @{ */
2367	FNIEMAIMPLBINROU16 iemAImpl_bt_u16;
2368	FNIEMAIMPLBINROU32 iemAImpl_bt_u32;
2369	FNIEMAIMPLBINROU64 iemAImpl_bt_u64;
2370	FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
2371	FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
2372	FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
2373	FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
2374	FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
2375	FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
2376	FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
2377	FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
2378	FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
2379	/** @} */
2380
2381	/** @name Arithmetic three operand operations on double words (binary).
2382	* @{ */
2383	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32, (uint32_t pu32Dst, uint32_t u32Src1, uint32_t u32Src2, uint32_t pEFlags));
2384	typedef FNIEMAIMPLBINVEXU32 *PFNIEMAIMPLBINVEXU32;
2385	FNIEMAIMPLBINVEXU32 iemAImpl_andn_u32, iemAImpl_andn_u32_fallback;
2386	FNIEMAIMPLBINVEXU32 iemAImpl_bextr_u32, iemAImpl_bextr_u32_fallback;
2387	FNIEMAIMPLBINVEXU32 iemAImpl_bzhi_u32, iemAImpl_bzhi_u32_fallback;
2388	/** @} */
2389
2390	/** @name Arithmetic three operand operations on quad words (binary).
2391	* @{ */
2392	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64, (uint64_t pu64Dst, uint64_t u64Src1, uint64_t u64Src2, uint32_t pEFlags));
2393	typedef FNIEMAIMPLBINVEXU64 *PFNIEMAIMPLBINVEXU64;
2394	FNIEMAIMPLBINVEXU64 iemAImpl_andn_u64, iemAImpl_andn_u64_fallback;
2395	FNIEMAIMPLBINVEXU64 iemAImpl_bextr_u64, iemAImpl_bextr_u64_fallback;
2396	FNIEMAIMPLBINVEXU64 iemAImpl_bzhi_u64, iemAImpl_bzhi_u64_fallback;
2397	/** @} */
2398
2399	/** @name Arithmetic three operand operations on double words w/o EFLAGS (binary).
2400	* @{ */
2401	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32NOEFL, (uint32_t *pu32Dst, uint32_t u32Src1, uint32_t u32Src2));
2402	typedef FNIEMAIMPLBINVEXU32NOEFL *PFNIEMAIMPLBINVEXU32NOEFL;
2403	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pdep_u32, iemAImpl_pdep_u32_fallback;
2404	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pext_u32, iemAImpl_pext_u32_fallback;
2405	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_sarx_u32, iemAImpl_sarx_u32_fallback;
2406	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shlx_u32, iemAImpl_shlx_u32_fallback;
2407	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shrx_u32, iemAImpl_shrx_u32_fallback;
2408	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_rorx_u32;
2409	/** @} */
2410
2411	/** @name Arithmetic three operand operations on quad words w/o EFLAGS (binary).
2412	* @{ */
2413	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64NOEFL, (uint64_t *pu64Dst, uint64_t u64Src1, uint64_t u64Src2));
2414	typedef FNIEMAIMPLBINVEXU64NOEFL *PFNIEMAIMPLBINVEXU64NOEFL;
2415	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pdep_u64, iemAImpl_pdep_u64_fallback;
2416	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pext_u64, iemAImpl_pext_u64_fallback;
2417	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_sarx_u64, iemAImpl_sarx_u64_fallback;
2418	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shlx_u64, iemAImpl_shlx_u64_fallback;
2419	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shrx_u64, iemAImpl_shrx_u64_fallback;
2420	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_rorx_u64;
2421	/** @} */
2422
2423	/** @name MULX 32-bit and 64-bit.
2424	* @{ */
2425	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU32, (uint32_t puDst1, uint32_t puDst2, uint32_t uSrc1, uint32_t uSrc2));
2426	typedef FNIEMAIMPLMULXVEXU32 *PFNIEMAIMPLMULXVEXU32;
2427	FNIEMAIMPLMULXVEXU32 iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback;
2428
2429	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU64, (uint64_t puDst1, uint64_t puDst2, uint64_t uSrc1, uint64_t uSrc2));
2430	typedef FNIEMAIMPLMULXVEXU64 *PFNIEMAIMPLMULXVEXU64;
2431	FNIEMAIMPLMULXVEXU64 iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback;
2432	/** @} */
2433
2434
2435	/** @name Exchange memory with register operations.
2436	* @{ */
2437	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_locked, (uint8_t pu8Mem, uint8_t pu8Reg));
2438	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_locked,(uint16_t pu16Mem, uint16_t pu16Reg));
2439	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_locked,(uint32_t pu32Mem, uint32_t pu32Reg));
2440	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_locked,(uint64_t pu64Mem, uint64_t pu64Reg));
2441	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_unlocked, (uint8_t pu8Mem, uint8_t pu8Reg));
2442	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_unlocked,(uint16_t pu16Mem, uint16_t pu16Reg));
2443	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_unlocked,(uint32_t pu32Mem, uint32_t pu32Reg));
2444	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_unlocked,(uint64_t pu64Mem, uint64_t pu64Reg));
2445	/** @} */
2446
2447	/** @name Exchange and add operations.
2448	* @{ */
2449	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
2450	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
2451	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
2452	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
2453	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
2454	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
2455	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
2456	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
2457	/** @} */
2458
2459	/** @name Compare and exchange.
2460	* @{ */
2461	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
2462	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
2463	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
2464	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
2465	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
2466	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
2467	#if ARCH_BITS == 32
2468	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
2469	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
2470	#else
2471	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
2472	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
2473	#endif
2474	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
2475	uint32_t *pEFlags));
2476	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
2477	uint32_t *pEFlags));
2478	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
2479	uint32_t *pEFlags));
2480	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
2481	uint32_t *pEFlags));
2482	#ifndef RT_ARCH_ARM64
2483	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
2484	PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
2485	#endif
2486	/** @} */
2487
2488	/** @name Memory ordering
2489	* @{ */
2490	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
2491	typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
2492	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
2493	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
2494	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
2495	#ifndef RT_ARCH_ARM64
2496	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
2497	#endif
2498	/** @} */
2499
2500	/** @name Double precision shifts
2501	* @{ */
2502	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t pEFlags));
2503	typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
2504	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t pEFlags));
2505	typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
2506	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t pEFlags));
2507	typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
2508	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16, iemAImpl_shld_u16_amd, iemAImpl_shld_u16_intel;
2509	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32, iemAImpl_shld_u32_amd, iemAImpl_shld_u32_intel;
2510	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64, iemAImpl_shld_u64_amd, iemAImpl_shld_u64_intel;
2511	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16, iemAImpl_shrd_u16_amd, iemAImpl_shrd_u16_intel;
2512	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32, iemAImpl_shrd_u32_amd, iemAImpl_shrd_u32_intel;
2513	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64, iemAImpl_shrd_u64_amd, iemAImpl_shrd_u64_intel;
2514	/** @} */
2515
2516
2517	/** @name Bit search operations (thrown in with the binary ops).
2518	* @{ */
2519	FNIEMAIMPLBINU16 iemAImpl_bsf_u16, iemAImpl_bsf_u16_amd, iemAImpl_bsf_u16_intel;
2520	FNIEMAIMPLBINU32 iemAImpl_bsf_u32, iemAImpl_bsf_u32_amd, iemAImpl_bsf_u32_intel;
2521	FNIEMAIMPLBINU64 iemAImpl_bsf_u64, iemAImpl_bsf_u64_amd, iemAImpl_bsf_u64_intel;
2522	FNIEMAIMPLBINU16 iemAImpl_bsr_u16, iemAImpl_bsr_u16_amd, iemAImpl_bsr_u16_intel;
2523	FNIEMAIMPLBINU32 iemAImpl_bsr_u32, iemAImpl_bsr_u32_amd, iemAImpl_bsr_u32_intel;
2524	FNIEMAIMPLBINU64 iemAImpl_bsr_u64, iemAImpl_bsr_u64_amd, iemAImpl_bsr_u64_intel;
2525	FNIEMAIMPLBINU16 iemAImpl_lzcnt_u16, iemAImpl_lzcnt_u16_amd, iemAImpl_lzcnt_u16_intel;
2526	FNIEMAIMPLBINU32 iemAImpl_lzcnt_u32, iemAImpl_lzcnt_u32_amd, iemAImpl_lzcnt_u32_intel;
2527	FNIEMAIMPLBINU64 iemAImpl_lzcnt_u64, iemAImpl_lzcnt_u64_amd, iemAImpl_lzcnt_u64_intel;
2528	FNIEMAIMPLBINU16 iemAImpl_tzcnt_u16, iemAImpl_tzcnt_u16_amd, iemAImpl_tzcnt_u16_intel;
2529	FNIEMAIMPLBINU32 iemAImpl_tzcnt_u32, iemAImpl_tzcnt_u32_amd, iemAImpl_tzcnt_u32_intel;
2530	FNIEMAIMPLBINU64 iemAImpl_tzcnt_u64, iemAImpl_tzcnt_u64_amd, iemAImpl_tzcnt_u64_intel;
2531	FNIEMAIMPLBINU16 iemAImpl_popcnt_u16, iemAImpl_popcnt_u16_fallback;
2532	FNIEMAIMPLBINU32 iemAImpl_popcnt_u32, iemAImpl_popcnt_u32_fallback;
2533	FNIEMAIMPLBINU64 iemAImpl_popcnt_u64, iemAImpl_popcnt_u64_fallback;
2534	/** @} */
2535
2536	/** @name Signed multiplication operations (thrown in with the binary ops).
2537	* @{ */
2538	FNIEMAIMPLBINU16 iemAImpl_imul_two_u16, iemAImpl_imul_two_u16_amd, iemAImpl_imul_two_u16_intel;
2539	FNIEMAIMPLBINU32 iemAImpl_imul_two_u32, iemAImpl_imul_two_u32_amd, iemAImpl_imul_two_u32_intel;
2540	FNIEMAIMPLBINU64 iemAImpl_imul_two_u64, iemAImpl_imul_two_u64_amd, iemAImpl_imul_two_u64_intel;
2541	/** @} */
2542
2543	/** @name Arithmetic assignment operations on bytes (unary).
2544	* @{ */
2545	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t pu8Dst, uint32_t pEFlags));
2546	typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
2547	FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
2548	FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
2549	FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
2550	FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
2551	/** @} */
2552
2553	/** @name Arithmetic assignment operations on words (unary).
2554	* @{ */
2555	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t pu16Dst, uint32_t pEFlags));
2556	typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
2557	FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
2558	FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
2559	FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
2560	FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
2561	/** @} */
2562
2563	/** @name Arithmetic assignment operations on double words (unary).
2564	* @{ */
2565	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t pu32Dst, uint32_t pEFlags));
2566	typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
2567	FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
2568	FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
2569	FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
2570	FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
2571	/** @} */
2572
2573	/** @name Arithmetic assignment operations on quad words (unary).
2574	* @{ */
2575	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t pu64Dst, uint32_t pEFlags));
2576	typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
2577	FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
2578	FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
2579	FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
2580	FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
2581	/** @} */
2582
2583
2584	/** @name Shift operations on bytes (Group 2).
2585	* @{ */
2586	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU8,(uint8_t pu8Dst, uint8_t cShift, uint32_t pEFlags));
2587	typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
2588	FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8, iemAImpl_rol_u8_amd, iemAImpl_rol_u8_intel;
2589	FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8, iemAImpl_ror_u8_amd, iemAImpl_ror_u8_intel;
2590	FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8, iemAImpl_rcl_u8_amd, iemAImpl_rcl_u8_intel;
2591	FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8, iemAImpl_rcr_u8_amd, iemAImpl_rcr_u8_intel;
2592	FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8, iemAImpl_shl_u8_amd, iemAImpl_shl_u8_intel;
2593	FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8, iemAImpl_shr_u8_amd, iemAImpl_shr_u8_intel;
2594	FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8, iemAImpl_sar_u8_amd, iemAImpl_sar_u8_intel;
2595	/** @} */
2596
2597	/** @name Shift operations on words (Group 2).
2598	* @{ */
2599	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU16,(uint16_t pu16Dst, uint8_t cShift, uint32_t pEFlags));
2600	typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
2601	FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16, iemAImpl_rol_u16_amd, iemAImpl_rol_u16_intel;
2602	FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16, iemAImpl_ror_u16_amd, iemAImpl_ror_u16_intel;
2603	FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16, iemAImpl_rcl_u16_amd, iemAImpl_rcl_u16_intel;
2604	FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16, iemAImpl_rcr_u16_amd, iemAImpl_rcr_u16_intel;
2605	FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16, iemAImpl_shl_u16_amd, iemAImpl_shl_u16_intel;
2606	FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16, iemAImpl_shr_u16_amd, iemAImpl_shr_u16_intel;
2607	FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16, iemAImpl_sar_u16_amd, iemAImpl_sar_u16_intel;
2608	/** @} */
2609
2610	/** @name Shift operations on double words (Group 2).
2611	* @{ */
2612	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU32,(uint32_t pu32Dst, uint8_t cShift, uint32_t pEFlags));
2613	typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
2614	FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32, iemAImpl_rol_u32_amd, iemAImpl_rol_u32_intel;
2615	FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32, iemAImpl_ror_u32_amd, iemAImpl_ror_u32_intel;
2616	FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32, iemAImpl_rcl_u32_amd, iemAImpl_rcl_u32_intel;
2617	FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32, iemAImpl_rcr_u32_amd, iemAImpl_rcr_u32_intel;
2618	FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32, iemAImpl_shl_u32_amd, iemAImpl_shl_u32_intel;
2619	FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32, iemAImpl_shr_u32_amd, iemAImpl_shr_u32_intel;
2620	FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32, iemAImpl_sar_u32_amd, iemAImpl_sar_u32_intel;
2621	/** @} */
2622
2623	/** @name Shift operations on words (Group 2).
2624	* @{ */
2625	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU64,(uint64_t pu64Dst, uint8_t cShift, uint32_t pEFlags));
2626	typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
2627	FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64, iemAImpl_rol_u64_amd, iemAImpl_rol_u64_intel;
2628	FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64, iemAImpl_ror_u64_amd, iemAImpl_ror_u64_intel;
2629	FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64, iemAImpl_rcl_u64_amd, iemAImpl_rcl_u64_intel;
2630	FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64, iemAImpl_rcr_u64_amd, iemAImpl_rcr_u64_intel;
2631	FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64, iemAImpl_shl_u64_amd, iemAImpl_shl_u64_intel;
2632	FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64, iemAImpl_shr_u64_amd, iemAImpl_shr_u64_intel;
2633	FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64, iemAImpl_sar_u64_amd, iemAImpl_sar_u64_intel;
2634	/** @} */
2635
2636	/** @name Multiplication and division operations.
2637	* @{ */
2638	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t pu16AX, uint8_t u8FactorDivisor, uint32_t pEFlags));
2639	typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
2640	FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_mul_u8_amd, iemAImpl_mul_u8_intel;
2641	FNIEMAIMPLMULDIVU8 iemAImpl_imul_u8, iemAImpl_imul_u8_amd, iemAImpl_imul_u8_intel;
2642	FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_div_u8_amd, iemAImpl_div_u8_intel;
2643	FNIEMAIMPLMULDIVU8 iemAImpl_idiv_u8, iemAImpl_idiv_u8_amd, iemAImpl_idiv_u8_intel;
2644
2645	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t pu16AX, uint16_t pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
2646	typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
2647	FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_mul_u16_amd, iemAImpl_mul_u16_intel;
2648	FNIEMAIMPLMULDIVU16 iemAImpl_imul_u16, iemAImpl_imul_u16_amd, iemAImpl_imul_u16_intel;
2649	FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_div_u16_amd, iemAImpl_div_u16_intel;
2650	FNIEMAIMPLMULDIVU16 iemAImpl_idiv_u16, iemAImpl_idiv_u16_amd, iemAImpl_idiv_u16_intel;
2651
2652	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t pu32EAX, uint32_t pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
2653	typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
2654	FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_mul_u32_amd, iemAImpl_mul_u32_intel;
2655	FNIEMAIMPLMULDIVU32 iemAImpl_imul_u32, iemAImpl_imul_u32_amd, iemAImpl_imul_u32_intel;
2656	FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_div_u32_amd, iemAImpl_div_u32_intel;
2657	FNIEMAIMPLMULDIVU32 iemAImpl_idiv_u32, iemAImpl_idiv_u32_amd, iemAImpl_idiv_u32_intel;
2658
2659	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t pu64RAX, uint64_t pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
2660	typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
2661	FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_mul_u64_amd, iemAImpl_mul_u64_intel;
2662	FNIEMAIMPLMULDIVU64 iemAImpl_imul_u64, iemAImpl_imul_u64_amd, iemAImpl_imul_u64_intel;
2663	FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_div_u64_amd, iemAImpl_div_u64_intel;
2664	FNIEMAIMPLMULDIVU64 iemAImpl_idiv_u64, iemAImpl_idiv_u64_amd, iemAImpl_idiv_u64_intel;
2665	/** @} */
2666
2667	/** @name Byte Swap.
2668	* @{ */
2669	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t pu32Dst)); / Yes, 32-bit register access. */
2670	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
2671	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
2672	/** @} */
2673
2674	/** @name Misc.
2675	* @{ */
2676	FNIEMAIMPLBINU16 iemAImpl_arpl;
2677	/** @} */
2678
2679	/** @name RDRAND and RDSEED
2680	* @{ */
2681	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU16,(uint16_t puDst, uint32_t pEFlags));
2682	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU32,(uint32_t puDst, uint32_t pEFlags));
2683	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU64,(uint64_t puDst, uint32_t pEFlags));
2684	typedef FNIEMAIMPLRDRANDSEEDU16 *PFNIEMAIMPLRDRANDSEEDU16;
2685	typedef FNIEMAIMPLRDRANDSEEDU32 *PFNIEMAIMPLRDRANDSEEDU32;
2686	typedef FNIEMAIMPLRDRANDSEEDU64 *PFNIEMAIMPLRDRANDSEEDU64;
2687
2688	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdrand_u16, iemAImpl_rdrand_u16_fallback;
2689	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdrand_u32, iemAImpl_rdrand_u32_fallback;
2690	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdrand_u64, iemAImpl_rdrand_u64_fallback;
2691	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdseed_u16, iemAImpl_rdseed_u16_fallback;
2692	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdseed_u32, iemAImpl_rdseed_u32_fallback;
2693	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdseed_u64, iemAImpl_rdseed_u64_fallback;
2694	/** @} */
2695
2696	/** @name ADOX and ADCX
2697	* @{ */
2698	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLADXU32,(uint32_t puDst, uint32_t pfEFlags, uint32_t uSrc));
2699	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLADXU64,(uint64_t puDst, uint32_t pfEFlags, uint64_t uSrc));
2700	typedef FNIEMAIMPLADXU32 *PFNIEMAIMPLADXU32;
2701	typedef FNIEMAIMPLADXU64 *PFNIEMAIMPLADXU64;
2702
2703	FNIEMAIMPLADXU32 iemAImpl_adcx_u32, iemAImpl_adcx_u32_fallback;
2704	FNIEMAIMPLADXU64 iemAImpl_adcx_u64, iemAImpl_adcx_u64_fallback;
2705	FNIEMAIMPLADXU32 iemAImpl_adox_u32, iemAImpl_adox_u32_fallback;
2706	FNIEMAIMPLADXU64 iemAImpl_adox_u64, iemAImpl_adox_u64_fallback;
2707	/** @} */
2708
2709	/** @name FPU operations taking a 32-bit float argument
2710	* @{ */
2711	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2712	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
2713	typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
2714
2715	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2716	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
2717	typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
2718
2719	FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
2720	FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
2721	FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
2722	FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
2723	FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
2724	FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
2725	FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
2726
2727	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
2728	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2729	PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
2730	/** @} */
2731
2732	/** @name FPU operations taking a 64-bit float argument
2733	* @{ */
2734	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2735	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
2736	typedef FNIEMAIMPLFPUR64FSW *PFNIEMAIMPLFPUR64FSW;
2737
2738	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2739	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
2740	typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
2741
2742	FNIEMAIMPLFPUR64FSW iemAImpl_fcom_r80_by_r64;
2743	FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
2744	FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
2745	FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
2746	FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
2747	FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
2748	FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
2749
2750	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
2751	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2752	PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
2753	/** @} */
2754
2755	/** @name FPU operations taking a 80-bit float argument
2756	* @{ */
2757	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2758	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
2759	typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
2760	FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
2761	FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
2762	FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
2763	FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
2764	FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
2765	FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
2766	FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
2767	FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
2768	FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
2769
2770	FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80, iemAImpl_fpatan_r80_by_r80_amd, iemAImpl_fpatan_r80_by_r80_intel;
2771	FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80, iemAImpl_fyl2x_r80_by_r80_amd, iemAImpl_fyl2x_r80_by_r80_intel;
2772	FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80, iemAImpl_fyl2xp1_r80_by_r80_amd, iemAImpl_fyl2xp1_r80_by_r80_intel;
2773
2774	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2775	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
2776	typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
2777	FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
2778	FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
2779
2780	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
2781	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
2782	typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
2783	FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
2784	FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
2785
2786	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
2787	typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
2788	FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
2789	FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
2790	FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80, iemAImpl_f2xm1_r80_amd, iemAImpl_f2xm1_r80_intel;
2791	FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
2792	FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
2793	FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80, iemAImpl_fsin_r80_amd, iemAImpl_fsin_r80_intel;
2794	FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80, iemAImpl_fcos_r80_amd, iemAImpl_fcos_r80_intel;
2795
2796	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
2797	typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
2798	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
2799	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
2800
2801	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
2802	typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
2803	FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
2804	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
2805	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
2806	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
2807	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
2808	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
2809	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
2810
2811	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
2812	PCRTFLOAT80U pr80Val));
2813	typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
2814	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80, iemAImpl_fptan_r80_r80_amd, iemAImpl_fptan_r80_r80_intel;
2815	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
2816	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80, iemAImpl_fsincos_r80_r80_amd, iemAImpl_fsincos_r80_r80_intel;
2817
2818	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
2819	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2820	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
2821
2822	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_d80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTPBCD80U pd80Val));
2823	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_d80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2824	PRTPBCD80U pd80Dst, PCRTFLOAT80U pr80Src));
2825
2826	/** @} */
2827
2828	/** @name FPU operations taking a 16-bit signed integer argument
2829	* @{ */
2830	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2831	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
2832	typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
2833	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI16,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
2834	int16_t *pi16Dst, PCRTFLOAT80U pr80Src));
2835	typedef FNIEMAIMPLFPUSTR80TOI16 *PFNIEMAIMPLFPUSTR80TOI16;
2836
2837	FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
2838	FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
2839	FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
2840	FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
2841	FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
2842	FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
2843
2844	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2845	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
2846	typedef FNIEMAIMPLFPUI16FSW *PFNIEMAIMPLFPUI16FSW;
2847	FNIEMAIMPLFPUI16FSW iemAImpl_ficom_r80_by_i16;
2848
2849	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
2850	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fist_r80_to_i16;
2851	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fistt_r80_to_i16, iemAImpl_fistt_r80_to_i16_amd, iemAImpl_fistt_r80_to_i16_intel;
2852	/** @} */
2853
2854	/** @name FPU operations taking a 32-bit signed integer argument
2855	* @{ */
2856	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2857	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
2858	typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
2859	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI32,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
2860	int32_t *pi32Dst, PCRTFLOAT80U pr80Src));
2861	typedef FNIEMAIMPLFPUSTR80TOI32 *PFNIEMAIMPLFPUSTR80TOI32;
2862
2863	FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
2864	FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
2865	FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
2866	FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
2867	FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
2868	FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
2869
2870	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2871	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
2872	typedef FNIEMAIMPLFPUI32FSW *PFNIEMAIMPLFPUI32FSW;
2873	FNIEMAIMPLFPUI32FSW iemAImpl_ficom_r80_by_i32;
2874
2875	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
2876	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fist_r80_to_i32;
2877	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fistt_r80_to_i32;
2878	/** @} */
2879
2880	/** @name FPU operations taking a 64-bit signed integer argument
2881	* @{ */
2882	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI64,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
2883	int64_t *pi64Dst, PCRTFLOAT80U pr80Src));
2884	typedef FNIEMAIMPLFPUSTR80TOI64 *PFNIEMAIMPLFPUSTR80TOI64;
2885
2886	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
2887	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fist_r80_to_i64;
2888	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fistt_r80_to_i64;
2889	/** @} */
2890
2891
2892	/** Temporary type representing a 256-bit vector register. */
2893	typedef struct { uint64_t au64[4]; } IEMVMM256;
2894	/** Temporary type pointing to a 256-bit vector register. */
2895	typedef IEMVMM256 *PIEMVMM256;
2896	/** Temporary type pointing to a const 256-bit vector register. */
2897	typedef IEMVMM256 *PCIEMVMM256;
2898
2899
2900	/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
2901	* @{ */
2902	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t puDst, uint64_t const puSrc));
2903	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
2904	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U128,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
2905	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
2906	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U128,(PX86XSAVEAREA pExtState, PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
2907	typedef FNIEMAIMPLMEDIAF3U128 *PFNIEMAIMPLMEDIAF3U128;
2908	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U256,(PX86XSAVEAREA pExtState, PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
2909	typedef FNIEMAIMPLMEDIAF3U256 *PFNIEMAIMPLMEDIAF3U256;
2910	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U64,(uint64_t puDst, uint64_t const puSrc));
2911	typedef FNIEMAIMPLMEDIAOPTF2U64 *PFNIEMAIMPLMEDIAOPTF2U64;
2912	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128,(PRTUINT128U puDst, PCRTUINT128U puSrc));
2913	typedef FNIEMAIMPLMEDIAOPTF2U128 *PFNIEMAIMPLMEDIAOPTF2U128;
2914	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
2915	typedef FNIEMAIMPLMEDIAOPTF3U128 *PFNIEMAIMPLMEDIAOPTF3U128;
2916	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
2917	typedef FNIEMAIMPLMEDIAOPTF3U256 *PFNIEMAIMPLMEDIAOPTF3U256;
2918	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256,(PRTUINT256U puDst, PCRTUINT256U puSrc));
2919	typedef FNIEMAIMPLMEDIAOPTF2U256 *PFNIEMAIMPLMEDIAOPTF2U256;
2920	FNIEMAIMPLMEDIAF2U64 iemAImpl_pshufb_u64, iemAImpl_pshufb_u64_fallback;
2921	FNIEMAIMPLMEDIAF2U64 iemAImpl_pand_u64, iemAImpl_pandn_u64, iemAImpl_por_u64, iemAImpl_pxor_u64;
2922	FNIEMAIMPLMEDIAF2U64 iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
2923	FNIEMAIMPLMEDIAF2U64 iemAImpl_pcmpgtb_u64, iemAImpl_pcmpgtw_u64, iemAImpl_pcmpgtd_u64;
2924	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddb_u64, iemAImpl_paddsb_u64, iemAImpl_paddusb_u64;
2925	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddw_u64, iemAImpl_paddsw_u64, iemAImpl_paddusw_u64;
2926	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddd_u64;
2927	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddq_u64;
2928	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubb_u64, iemAImpl_psubsb_u64, iemAImpl_psubusb_u64;
2929	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubw_u64, iemAImpl_psubsw_u64, iemAImpl_psubusw_u64;
2930	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubd_u64;
2931	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubq_u64;
2932	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmaddwd_u64;
2933	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmullw_u64, iemAImpl_pmulhw_u64;
2934	FNIEMAIMPLMEDIAF2U64 iemAImpl_pminub_u64, iemAImpl_pmaxub_u64;
2935	FNIEMAIMPLMEDIAF2U64 iemAImpl_pminsw_u64, iemAImpl_pmaxsw_u64;
2936	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsb_u64, iemAImpl_pabsb_u64_fallback;
2937	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsw_u64, iemAImpl_pabsw_u64_fallback;
2938	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsd_u64, iemAImpl_pabsd_u64_fallback;
2939	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignb_u64, iemAImpl_psignb_u64_fallback;
2940	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignw_u64, iemAImpl_psignw_u64_fallback;
2941	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignd_u64, iemAImpl_psignd_u64_fallback;
2942	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddw_u64, iemAImpl_phaddw_u64_fallback;
2943	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddd_u64, iemAImpl_phaddd_u64_fallback;
2944	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubw_u64, iemAImpl_phsubw_u64_fallback;
2945	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubd_u64, iemAImpl_phsubd_u64_fallback;
2946	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddsw_u64, iemAImpl_phaddsw_u64_fallback;
2947	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubsw_u64, iemAImpl_phsubsw_u64_fallback;
2948	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmaddubsw_u64, iemAImpl_pmaddubsw_u64_fallback;
2949	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmulhrsw_u64, iemAImpl_pmulhrsw_u64_fallback;
2950	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmuludq_u64;
2951	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllw_u64, iemAImpl_psrlw_u64, iemAImpl_psraw_u64;
2952	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pslld_u64, iemAImpl_psrld_u64, iemAImpl_psrad_u64;
2953	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllq_u64, iemAImpl_psrlq_u64;
2954	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packsswb_u64, iemAImpl_packuswb_u64;
2955	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packssdw_u64;
2956	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhuw_u64;
2957	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pavgb_u64, iemAImpl_pavgw_u64;
2958	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psadbw_u64;
2959
2960	FNIEMAIMPLMEDIAF2U128 iemAImpl_pshufb_u128, iemAImpl_pshufb_u128_fallback;
2961	FNIEMAIMPLMEDIAF2U128 iemAImpl_pand_u128, iemAImpl_pandn_u128, iemAImpl_por_u128, iemAImpl_pxor_u128;
2962	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
2963	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpeqq_u128, iemAImpl_pcmpeqq_u128_fallback;
2964	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpgtb_u128, iemAImpl_pcmpgtw_u128, iemAImpl_pcmpgtd_u128;
2965	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpgtq_u128, iemAImpl_pcmpgtq_u128_fallback;
2966	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddb_u128, iemAImpl_paddsb_u128, iemAImpl_paddusb_u128;
2967	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddw_u128, iemAImpl_paddsw_u128, iemAImpl_paddusw_u128;
2968	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddd_u128;
2969	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddq_u128;
2970	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubb_u128, iemAImpl_psubsb_u128, iemAImpl_psubusb_u128;
2971	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubw_u128, iemAImpl_psubsw_u128, iemAImpl_psubusw_u128;
2972	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubd_u128;
2973	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubq_u128;
2974	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmullw_u128, iemAImpl_pmullw_u128_fallback;
2975	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulhw_u128;
2976	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulld_u128, iemAImpl_pmulld_u128_fallback;
2977	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaddwd_u128;
2978	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminub_u128;
2979	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminud_u128, iemAImpl_pminud_u128_fallback;
2980	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminuw_u128, iemAImpl_pminuw_u128_fallback;
2981	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsb_u128, iemAImpl_pminsb_u128_fallback;
2982	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsd_u128, iemAImpl_pminsd_u128_fallback;
2983	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsw_u128, iemAImpl_pminsw_u128_fallback;
2984	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxub_u128;
2985	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxud_u128, iemAImpl_pmaxud_u128_fallback;
2986	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxuw_u128, iemAImpl_pmaxuw_u128_fallback;
2987	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsb_u128, iemAImpl_pmaxsb_u128_fallback;
2988	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsw_u128;
2989	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsd_u128, iemAImpl_pmaxsd_u128_fallback;
2990	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsb_u128, iemAImpl_pabsb_u128_fallback;
2991	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsw_u128, iemAImpl_pabsw_u128_fallback;
2992	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsd_u128, iemAImpl_pabsd_u128_fallback;
2993	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignb_u128, iemAImpl_psignb_u128_fallback;
2994	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignw_u128, iemAImpl_psignw_u128_fallback;
2995	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignd_u128, iemAImpl_psignd_u128_fallback;
2996	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddw_u128, iemAImpl_phaddw_u128_fallback;
2997	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddd_u128, iemAImpl_phaddd_u128_fallback;
2998	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubw_u128, iemAImpl_phsubw_u128_fallback;
2999	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubd_u128, iemAImpl_phsubd_u128_fallback;
3000	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddsw_u128, iemAImpl_phaddsw_u128_fallback;
3001	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubsw_u128, iemAImpl_phsubsw_u128_fallback;
3002	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaddubsw_u128, iemAImpl_pmaddubsw_u128_fallback;
3003	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulhrsw_u128, iemAImpl_pmulhrsw_u128_fallback;
3004	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmuludq_u128;
3005	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packsswb_u128, iemAImpl_packuswb_u128;
3006	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packssdw_u128, iemAImpl_packusdw_u128;
3007	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllw_u128, iemAImpl_psrlw_u128, iemAImpl_psraw_u128;
3008	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pslld_u128, iemAImpl_psrld_u128, iemAImpl_psrad_u128;
3009	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllq_u128, iemAImpl_psrlq_u128;
3010	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhuw_u128;
3011	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pavgb_u128, iemAImpl_pavgw_u128;
3012	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psadbw_u128;
3013	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuldq_u128, iemAImpl_pmuldq_u128_fallback;
3014	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpcklps_u128, iemAImpl_unpcklpd_u128;
3015	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpckhps_u128, iemAImpl_unpckhpd_u128;
3016	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phminposuw_u128, iemAImpl_phminposuw_u128_fallback;
3017
3018	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpshufb_u128, iemAImpl_vpshufb_u128_fallback;
3019	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpand_u128, iemAImpl_vpand_u128_fallback;
3020	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpandn_u128, iemAImpl_vpandn_u128_fallback;
3021	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpor_u128, iemAImpl_vpor_u128_fallback;
3022	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpxor_u128, iemAImpl_vpxor_u128_fallback;
3023	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqb_u128, iemAImpl_vpcmpeqb_u128_fallback;
3024	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqw_u128, iemAImpl_vpcmpeqw_u128_fallback;
3025	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqd_u128, iemAImpl_vpcmpeqd_u128_fallback;
3026	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqq_u128, iemAImpl_vpcmpeqq_u128_fallback;
3027	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtb_u128, iemAImpl_vpcmpgtb_u128_fallback;
3028	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtw_u128, iemAImpl_vpcmpgtw_u128_fallback;
3029	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtd_u128, iemAImpl_vpcmpgtd_u128_fallback;
3030	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtq_u128, iemAImpl_vpcmpgtq_u128_fallback;
3031	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddb_u128, iemAImpl_vpaddb_u128_fallback;
3032	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddw_u128, iemAImpl_vpaddw_u128_fallback;
3033	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddd_u128, iemAImpl_vpaddd_u128_fallback;
3034	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddq_u128, iemAImpl_vpaddq_u128_fallback;
3035	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubb_u128, iemAImpl_vpsubb_u128_fallback;
3036	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubw_u128, iemAImpl_vpsubw_u128_fallback;
3037	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubd_u128, iemAImpl_vpsubd_u128_fallback;
3038	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubq_u128, iemAImpl_vpsubq_u128_fallback;
3039	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminub_u128, iemAImpl_vpminub_u128_fallback;
3040	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminuw_u128, iemAImpl_vpminuw_u128_fallback;
3041	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminud_u128, iemAImpl_vpminud_u128_fallback;
3042	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsb_u128, iemAImpl_vpminsb_u128_fallback;
3043	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsw_u128, iemAImpl_vpminsw_u128_fallback;
3044	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsd_u128, iemAImpl_vpminsd_u128_fallback;
3045	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxub_u128, iemAImpl_vpmaxub_u128_fallback;
3046	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxuw_u128, iemAImpl_vpmaxuw_u128_fallback;
3047	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxud_u128, iemAImpl_vpmaxud_u128_fallback;
3048	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsb_u128, iemAImpl_vpmaxsb_u128_fallback;
3049	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsw_u128, iemAImpl_vpmaxsw_u128_fallback;
3050	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsd_u128, iemAImpl_vpmaxsd_u128_fallback;
3051	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpacksswb_u128, iemAImpl_vpacksswb_u128_fallback;
3052	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackssdw_u128, iemAImpl_vpackssdw_u128_fallback;
3053	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackuswb_u128, iemAImpl_vpackuswb_u128_fallback;
3054	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackusdw_u128, iemAImpl_vpackusdw_u128_fallback;
3055	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmullw_u128, iemAImpl_vpmullw_u128_fallback;
3056	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulld_u128, iemAImpl_vpmulld_u128_fallback;
3057	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhw_u128, iemAImpl_vpmulhw_u128_fallback;
3058	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhuw_u128, iemAImpl_vpmulhuw_u128_fallback;
3059	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgb_u128, iemAImpl_vpavgb_u128_fallback;
3060	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgw_u128, iemAImpl_vpavgw_u128_fallback;
3061	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignb_u128, iemAImpl_vpsignb_u128_fallback;
3062	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignw_u128, iemAImpl_vpsignw_u128_fallback;
3063	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignd_u128, iemAImpl_vpsignd_u128_fallback;
3064	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddw_u128, iemAImpl_vphaddw_u128_fallback;
3065	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddd_u128, iemAImpl_vphaddd_u128_fallback;
3066	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubw_u128, iemAImpl_vphsubw_u128_fallback;
3067	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubd_u128, iemAImpl_vphsubd_u128_fallback;
3068	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddsw_u128, iemAImpl_vphaddsw_u128_fallback;
3069	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubsw_u128, iemAImpl_vphsubsw_u128_fallback;
3070	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddubsw_u128, iemAImpl_vpmaddubsw_u128_fallback;
3071	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhrsw_u128, iemAImpl_vpmulhrsw_u128_fallback;
3072	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsadbw_u128, iemAImpl_vpsadbw_u128_fallback;
3073	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuldq_u128, iemAImpl_vpmuldq_u128_fallback;
3074	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuludq_u128, iemAImpl_vpmuludq_u128_fallback;
3075	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsb_u128, iemAImpl_vpsubsb_u128_fallback;
3076	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsw_u128, iemAImpl_vpsubsw_u128_fallback;
3077	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusb_u128, iemAImpl_vpsubusb_u128_fallback;
3078	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusw_u128, iemAImpl_vpsubusw_u128_fallback;
3079	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusb_u128, iemAImpl_vpaddusb_u128_fallback;
3080	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusw_u128, iemAImpl_vpaddusw_u128_fallback;
3081	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsb_u128, iemAImpl_vpaddsb_u128_fallback;
3082	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsw_u128, iemAImpl_vpaddsw_u128_fallback;
3083
3084	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsb_u128, iemAImpl_vpabsb_u128_fallback;
3085	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsw_u128, iemAImpl_vpabsd_u128_fallback;
3086	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsd_u128, iemAImpl_vpabsw_u128_fallback;
3087	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vphminposuw_u128, iemAImpl_vphminposuw_u128_fallback;
3088
3089	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpshufb_u256, iemAImpl_vpshufb_u256_fallback;
3090	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpand_u256, iemAImpl_vpand_u256_fallback;
3091	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpandn_u256, iemAImpl_vpandn_u256_fallback;
3092	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpor_u256, iemAImpl_vpor_u256_fallback;
3093	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpxor_u256, iemAImpl_vpxor_u256_fallback;
3094	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqb_u256, iemAImpl_vpcmpeqb_u256_fallback;
3095	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqw_u256, iemAImpl_vpcmpeqw_u256_fallback;
3096	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqd_u256, iemAImpl_vpcmpeqd_u256_fallback;
3097	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqq_u256, iemAImpl_vpcmpeqq_u256_fallback;
3098	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtb_u256, iemAImpl_vpcmpgtb_u256_fallback;
3099	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtw_u256, iemAImpl_vpcmpgtw_u256_fallback;
3100	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtd_u256, iemAImpl_vpcmpgtd_u256_fallback;
3101	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtq_u256, iemAImpl_vpcmpgtq_u256_fallback;
3102	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddb_u256, iemAImpl_vpaddb_u256_fallback;
3103	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddw_u256, iemAImpl_vpaddw_u256_fallback;
3104	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddd_u256, iemAImpl_vpaddd_u256_fallback;
3105	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddq_u256, iemAImpl_vpaddq_u256_fallback;
3106	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubb_u256, iemAImpl_vpsubb_u256_fallback;
3107	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubw_u256, iemAImpl_vpsubw_u256_fallback;
3108	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubd_u256, iemAImpl_vpsubd_u256_fallback;
3109	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubq_u256, iemAImpl_vpsubq_u256_fallback;
3110	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminub_u256, iemAImpl_vpminub_u256_fallback;
3111	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminuw_u256, iemAImpl_vpminuw_u256_fallback;
3112	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminud_u256, iemAImpl_vpminud_u256_fallback;
3113	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsb_u256, iemAImpl_vpminsb_u256_fallback;
3114	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsw_u256, iemAImpl_vpminsw_u256_fallback;
3115	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsd_u256, iemAImpl_vpminsd_u256_fallback;
3116	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxub_u256, iemAImpl_vpmaxub_u256_fallback;
3117	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxuw_u256, iemAImpl_vpmaxuw_u256_fallback;
3118	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxud_u256, iemAImpl_vpmaxud_u256_fallback;
3119	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsb_u256, iemAImpl_vpmaxsb_u256_fallback;
3120	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsw_u256, iemAImpl_vpmaxsw_u256_fallback;
3121	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsd_u256, iemAImpl_vpmaxsd_u256_fallback;
3122	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpacksswb_u256, iemAImpl_vpacksswb_u256_fallback;
3123	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackssdw_u256, iemAImpl_vpackssdw_u256_fallback;
3124	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackuswb_u256, iemAImpl_vpackuswb_u256_fallback;
3125	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackusdw_u256, iemAImpl_vpackusdw_u256_fallback;
3126	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmullw_u256, iemAImpl_vpmullw_u256_fallback;
3127	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulld_u256, iemAImpl_vpmulld_u256_fallback;
3128	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhw_u256, iemAImpl_vpmulhw_u256_fallback;
3129	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhuw_u256, iemAImpl_vpmulhuw_u256_fallback;
3130	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgb_u256, iemAImpl_vpavgb_u256_fallback;
3131	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgw_u256, iemAImpl_vpavgw_u256_fallback;
3132	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignb_u256, iemAImpl_vpsignb_u256_fallback;
3133	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignw_u256, iemAImpl_vpsignw_u256_fallback;
3134	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignd_u256, iemAImpl_vpsignd_u256_fallback;
3135	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddw_u256, iemAImpl_vphaddw_u256_fallback;
3136	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddd_u256, iemAImpl_vphaddd_u256_fallback;
3137	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubw_u256, iemAImpl_vphsubw_u256_fallback;
3138	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubd_u256, iemAImpl_vphsubd_u256_fallback;
3139	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddsw_u256, iemAImpl_vphaddsw_u256_fallback;
3140	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubsw_u256, iemAImpl_vphsubsw_u256_fallback;
3141	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddubsw_u256, iemAImpl_vpmaddubsw_u256_fallback;
3142	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhrsw_u256, iemAImpl_vpmulhrsw_u256_fallback;
3143	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsadbw_u256, iemAImpl_vpsadbw_u256_fallback;
3144	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuldq_u256, iemAImpl_vpmuldq_u256_fallback;
3145	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuludq_u256, iemAImpl_vpmuludq_u256_fallback;
3146	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsb_u256, iemAImpl_vpsubsb_u256_fallback;
3147	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsw_u256, iemAImpl_vpsubsw_u256_fallback;
3148	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusb_u256, iemAImpl_vpsubusb_u256_fallback;
3149	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusw_u256, iemAImpl_vpsubusw_u256_fallback;
3150	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusb_u256, iemAImpl_vpaddusb_u256_fallback;
3151	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusw_u256, iemAImpl_vpaddusw_u256_fallback;
3152	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsb_u256, iemAImpl_vpaddsb_u256_fallback;
3153	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsw_u256, iemAImpl_vpaddsw_u256_fallback;
3154
3155	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsb_u256, iemAImpl_vpabsb_u256_fallback;
3156	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsw_u256, iemAImpl_vpabsw_u256_fallback;
3157	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsd_u256, iemAImpl_vpabsd_u256_fallback;
3158	/** @} */
3159
3160	/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
3161	* @{ */
3162	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
3163	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
3164	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpcklbw_u128, iemAImpl_vpunpcklbw_u128_fallback,
3165	iemAImpl_vpunpcklwd_u128, iemAImpl_vpunpcklwd_u128_fallback,
3166	iemAImpl_vpunpckldq_u128, iemAImpl_vpunpckldq_u128_fallback,
3167	iemAImpl_vpunpcklqdq_u128, iemAImpl_vpunpcklqdq_u128_fallback,
3168	iemAImpl_vunpcklps_u128, iemAImpl_vunpcklps_u128_fallback,
3169	iemAImpl_vunpcklpd_u128, iemAImpl_vunpcklpd_u128_fallback,
3170	iemAImpl_vunpckhps_u128, iemAImpl_vunpckhps_u128_fallback,
3171	iemAImpl_vunpckhpd_u128, iemAImpl_vunpckhpd_u128_fallback;
3172
3173	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpcklbw_u256, iemAImpl_vpunpcklbw_u256_fallback,
3174	iemAImpl_vpunpcklwd_u256, iemAImpl_vpunpcklwd_u256_fallback,
3175	iemAImpl_vpunpckldq_u256, iemAImpl_vpunpckldq_u256_fallback,
3176	iemAImpl_vpunpcklqdq_u256, iemAImpl_vpunpcklqdq_u256_fallback,
3177	iemAImpl_vunpcklps_u256, iemAImpl_vunpcklps_u256_fallback,
3178	iemAImpl_vunpcklpd_u256, iemAImpl_vunpcklpd_u256_fallback,
3179	iemAImpl_vunpckhps_u256, iemAImpl_vunpckhps_u256_fallback,
3180	iemAImpl_vunpckhpd_u256, iemAImpl_vunpckhpd_u256_fallback;
3181	/** @} */
3182
3183	/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
3184	* @{ */
3185	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
3186	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
3187	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpckhbw_u128, iemAImpl_vpunpckhbw_u128_fallback,
3188	iemAImpl_vpunpckhwd_u128, iemAImpl_vpunpckhwd_u128_fallback,
3189	iemAImpl_vpunpckhdq_u128, iemAImpl_vpunpckhdq_u128_fallback,
3190	iemAImpl_vpunpckhqdq_u128, iemAImpl_vpunpckhqdq_u128_fallback;
3191	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpckhbw_u256, iemAImpl_vpunpckhbw_u256_fallback,
3192	iemAImpl_vpunpckhwd_u256, iemAImpl_vpunpckhwd_u256_fallback,
3193	iemAImpl_vpunpckhdq_u256, iemAImpl_vpunpckhdq_u256_fallback,
3194	iemAImpl_vpunpckhqdq_u256, iemAImpl_vpunpckhqdq_u256_fallback;
3195	/** @} */
3196
3197	/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
3198	* @{ */
3199	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3200	typedef FNIEMAIMPLMEDIAPSHUFU128 *PFNIEMAIMPLMEDIAPSHUFU128;
3201	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
3202	typedef FNIEMAIMPLMEDIAPSHUFU256 *PFNIEMAIMPLMEDIAPSHUFU256;
3203	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw_u64,(uint64_t puDst, uint64_t const puSrc, uint8_t bEvil));
3204	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_pshufhw_u128, iemAImpl_pshuflw_u128, iemAImpl_pshufd_u128;
3205	#ifndef IEM_WITHOUT_ASSEMBLY
3206	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256, iemAImpl_vpshuflw_u256, iemAImpl_vpshufd_u256;
3207	#endif
3208	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256_fallback, iemAImpl_vpshuflw_u256_fallback, iemAImpl_vpshufd_u256_fallback;
3209	/** @} */
3210
3211	/** @name Media (SSE/MMX/AVX) operation: Shift Immediate Stuff (evil)
3212	* @{ */
3213	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU64,(uint64_t *puDst, uint8_t bShift));
3214	typedef FNIEMAIMPLMEDIAPSHIFTU64 *PFNIEMAIMPLMEDIAPSHIFTU64;
3215	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU128,(PRTUINT128U puDst, uint8_t bShift));
3216	typedef FNIEMAIMPLMEDIAPSHIFTU128 *PFNIEMAIMPLMEDIAPSHIFTU128;
3217	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU256,(PRTUINT256U puDst, uint8_t bShift));
3218	typedef FNIEMAIMPLMEDIAPSHIFTU256 *PFNIEMAIMPLMEDIAPSHIFTU256;
3219	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psllw_imm_u64, iemAImpl_pslld_imm_u64, iemAImpl_psllq_imm_u64;
3220	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psrlw_imm_u64, iemAImpl_psrld_imm_u64, iemAImpl_psrlq_imm_u64;
3221	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psraw_imm_u64, iemAImpl_psrad_imm_u64;
3222	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psllw_imm_u128, iemAImpl_pslld_imm_u128, iemAImpl_psllq_imm_u128;
3223	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psrlw_imm_u128, iemAImpl_psrld_imm_u128, iemAImpl_psrlq_imm_u128;
3224	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psraw_imm_u128, iemAImpl_psrad_imm_u128;
3225	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_pslldq_imm_u128, iemAImpl_psrldq_imm_u128;
3226	/** @} */
3227
3228	/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
3229	* @{ */
3230	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(uint64_t pu64Dst, uint64_t const puSrc));
3231	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(uint64_t *pu64Dst, PCRTUINT128U puSrc));
3232	#ifndef IEM_WITHOUT_ASSEMBLY
3233	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
3234	#endif
3235	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256_fallback,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
3236	/** @} */
3237
3238	/** @name Media (SSE/MMX/AVX) operations: Variable Blend Packed Bytes/R32/R64.
3239	* @{ */
3240	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puMask));
3241	typedef FNIEMAIMPLBLENDU128 *PFNIEMAIMPLBLENDU128;
3242	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, PCRTUINT128U puMask));
3243	typedef FNIEMAIMPLAVXBLENDU128 *PFNIEMAIMPLAVXBLENDU128;
3244	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, PCRTUINT256U puMask));
3245	typedef FNIEMAIMPLAVXBLENDU256 *PFNIEMAIMPLAVXBLENDU256;
3246
3247	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128;
3248	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128_fallback;
3249	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128;
3250	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128_fallback;
3251	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256;
3252	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256_fallback;
3253
3254	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128;
3255	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128_fallback;
3256	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128;
3257	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128_fallback;
3258	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256;
3259	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256_fallback;
3260
3261	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128;
3262	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128_fallback;
3263	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128;
3264	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128_fallback;
3265	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256;
3266	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256_fallback;
3267	/** @} */
3268
3269
3270	/** @name Media (SSE/MMX/AVX) operation: Sort this later
3271	* @{ */
3272	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
3273	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
3274	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovshdup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
3275	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovshdup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
3276	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
3277	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
3278
3279	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3280	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3281	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3282	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3283	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3284
3285	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3286	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3287	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3288	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3289	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3290
3291	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3292	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3293	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
3294	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3295	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3296
3297	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3298	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3299	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3300	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3301	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3302
3303	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3304	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3305	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3306	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3307	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3308
3309	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3310	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3311	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3312	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3313	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3314
3315	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3316	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3317	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3318	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3319	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3320
3321	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3322	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3323	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3324	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3325	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3326
3327	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3328	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3329	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
3330	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3331	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3332
3333	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3334	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3335	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3336	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3337	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3338
3339	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3340	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3341	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3342	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3343	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3344
3345	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3346	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3347	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3348	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3349	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3350
3351	IEM_DECL_IMPL_DEF(void, iemAImpl_shufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3352	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3353	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3354	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3355	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3356
3357	IEM_DECL_IMPL_DEF(void, iemAImpl_shufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3358	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3359	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3360	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3361	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3362
3363	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
3364	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64_fallback,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
3365
3366	IEM_DECL_IMPL_DEF(void, iemAImpl_pinsrw_u64,(uint64_t *pu64Dst, uint16_t u16Src, uint8_t bEvil));
3367	IEM_DECL_IMPL_DEF(void, iemAImpl_pinsrw_u128,(PRTUINT128U puDst, uint16_t u16Src, uint8_t bEvil));
3368	IEM_DECL_IMPL_DEF(void, iemAImpl_vpinsrw_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint16_t u16Src, uint8_t bEvil));
3369	IEM_DECL_IMPL_DEF(void, iemAImpl_vpinsrw_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint16_t u16Src, uint8_t bEvil));
3370
3371	IEM_DECL_IMPL_DEF(void, iemAImpl_pextrw_u64,(uint16_t *pu16Dst, uint64_t u64Src, uint8_t bEvil));
3372	IEM_DECL_IMPL_DEF(void, iemAImpl_pextrw_u128,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
3373	IEM_DECL_IMPL_DEF(void, iemAImpl_vpextrw_u128,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
3374	IEM_DECL_IMPL_DEF(void, iemAImpl_vpextrw_u128_fallback,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
3375
3376	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3377	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3378	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3379	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3380	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3381
3382	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3383	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3384	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3385	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3386	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3387
3388
3389	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3390	typedef FNIEMAIMPLMEDIAOPTF2U128IMM8 *PFNIEMAIMPLMEDIAOPTF2U128IMM8;
3391	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3392	typedef FNIEMAIMPLMEDIAOPTF3U128IMM8 *PFNIEMAIMPLMEDIAOPTF3U128IMM8;
3393	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3394	typedef FNIEMAIMPLMEDIAOPTF3U256IMM8 *PFNIEMAIMPLMEDIAOPTF3U256IMM8;
3395
3396	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_palignr_u128, iemAImpl_palignr_u128_fallback;
3397	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pblendw_u128, iemAImpl_pblendw_u128_fallback;
3398	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendps_u128, iemAImpl_blendps_u128_fallback;
3399	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendpd_u128, iemAImpl_blendpd_u128_fallback;
3400
3401	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpalignr_u128, iemAImpl_vpalignr_u128_fallback;
3402	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendw_u128, iemAImpl_vpblendw_u128_fallback;
3403	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendps_u128, iemAImpl_vblendps_u128_fallback;
3404	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendpd_u128, iemAImpl_vblendpd_u128_fallback;
3405
3406	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpalignr_u256, iemAImpl_vpalignr_u256_fallback;
3407	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendw_u256, iemAImpl_vpblendw_u256_fallback;
3408	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendps_u256, iemAImpl_vblendps_u256_fallback;
3409	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendpd_u256, iemAImpl_vblendpd_u256_fallback;
3410	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2i128_u256, iemAImpl_vperm2i128_u256_fallback;
3411	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2f128_u256, iemAImpl_vperm2f128_u256_fallback;
3412
3413	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesimc_u128, iemAImpl_aesimc_u128_fallback;
3414	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenc_u128, iemAImpl_aesenc_u128_fallback;
3415	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenclast_u128, iemAImpl_aesenclast_u128_fallback;
3416	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdec_u128, iemAImpl_aesdec_u128_fallback;
3417	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdeclast_u128, iemAImpl_aesdeclast_u128_fallback;
3418
3419	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesimc_u128, iemAImpl_vaesimc_u128_fallback;
3420	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenc_u128, iemAImpl_vaesenc_u128_fallback;
3421	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenclast_u128, iemAImpl_vaesenclast_u128_fallback;
3422	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdec_u128, iemAImpl_vaesdec_u128_fallback;
3423	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdeclast_u128, iemAImpl_vaesdeclast_u128_fallback;
3424
3425	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_aeskeygenassist_u128, iemAImpl_aeskeygenassist_u128_fallback;
3426
3427	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vaeskeygenassist_u128, iemAImpl_vaeskeygenassist_u128_fallback;
3428
3429	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1nexte_u128, iemAImpl_sha1nexte_u128_fallback;
3430	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg1_u128, iemAImpl_sha1msg1_u128_fallback;
3431	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg2_u128, iemAImpl_sha1msg2_u128_fallback;
3432	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg1_u128, iemAImpl_sha256msg1_u128_fallback;
3433	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg2_u128, iemAImpl_sha256msg2_u128_fallback;
3434	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_sha1rnds4_u128, iemAImpl_sha1rnds4_u128_fallback;
3435	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
3436	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
3437
3438	typedef struct IEMPCMPISTRXSRC
3439	{
3440	RTUINT128U uSrc1;
3441	RTUINT128U uSrc2;
3442	} IEMPCMPISTRXSRC;
3443	typedef IEMPCMPISTRXSRC *PIEMPCMPISTRXSRC;
3444	typedef const IEMPCMPISTRXSRC *PCIEMPCMPISTRXSRC;
3445
3446	typedef struct IEMPCMPESTRXSRC
3447	{
3448	RTUINT128U uSrc1;
3449	RTUINT128U uSrc2;
3450	uint64_t u64Rax;
3451	uint64_t u64Rdx;
3452	} IEMPCMPESTRXSRC;
3453	typedef IEMPCMPESTRXSRC *PIEMPCMPESTRXSRC;
3454	typedef const IEMPCMPESTRXSRC *PCIEMPCMPESTRXSRC;
3455
3456	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPISTRIU128IMM8,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
3457	typedef FNIEMAIMPLPCMPISTRIU128IMM8 *PFNIEMAIMPLPCMPISTRIU128IMM8;
3458	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRIU128IMM8,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
3459	typedef FNIEMAIMPLPCMPESTRIU128IMM8 *PFNIEMAIMPLPCMPESTRIU128IMM8;
3460
3461	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPISTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
3462	typedef FNIEMAIMPLPCMPISTRMU128IMM8 *PFNIEMAIMPLPCMPISTRMU128IMM8;
3463	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
3464	typedef FNIEMAIMPLPCMPESTRMU128IMM8 *PFNIEMAIMPLPCMPESTRMU128IMM8;
3465
3466	FNIEMAIMPLPCMPISTRIU128IMM8 iemAImpl_pcmpistri_u128, iemAImpl_pcmpistri_u128_fallback;
3467	FNIEMAIMPLPCMPESTRIU128IMM8 iemAImpl_pcmpestri_u128, iemAImpl_pcmpestri_u128_fallback;
3468	FNIEMAIMPLPCMPISTRMU128IMM8 iemAImpl_pcmpistrm_u128, iemAImpl_pcmpistrm_u128_fallback;
3469	FNIEMAIMPLPCMPESTRMU128IMM8 iemAImpl_pcmpestrm_u128, iemAImpl_pcmpestrm_u128_fallback;
3470
3471	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pclmulqdq_u128, iemAImpl_pclmulqdq_u128_fallback;
3472	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpclmulqdq_u128, iemAImpl_vpclmulqdq_u128_fallback;
3473
3474	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_mpsadbw_u128, iemAImpl_mpsadbw_u128_fallback;
3475	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vmpsadbw_u128, iemAImpl_vmpsadbw_u128_fallback;
3476	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vmpsadbw_u256, iemAImpl_vmpsadbw_u256_fallback;
3477	/** @} */
3478
3479	/** @name Media Odds and Ends
3480	* @{ */
3481	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U8,(uint32_t *puDst, uint8_t uSrc));
3482	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U16,(uint32_t *puDst, uint16_t uSrc));
3483	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U32,(uint32_t *puDst, uint32_t uSrc));
3484	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U64,(uint32_t *puDst, uint64_t uSrc));
3485	FNIEMAIMPLCR32U8 iemAImpl_crc32_u8, iemAImpl_crc32_u8_fallback;
3486	FNIEMAIMPLCR32U16 iemAImpl_crc32_u16, iemAImpl_crc32_u16_fallback;
3487	FNIEMAIMPLCR32U32 iemAImpl_crc32_u32, iemAImpl_crc32_u32_fallback;
3488	FNIEMAIMPLCR32U64 iemAImpl_crc32_u64, iemAImpl_crc32_u64_fallback;
3489
3490	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL128,(PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint32_t *pEFlags));
3491	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL256,(PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint32_t *pEFlags));
3492	FNIEMAIMPLF2EFL128 iemAImpl_ptest_u128;
3493	FNIEMAIMPLF2EFL256 iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback;
3494
3495	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I32U64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int32_t pi32Dst, const uint64_t pu64Src)); / pu64Src is a double precision floating point. */
3496	typedef FNIEMAIMPLSSEF2I32U64 *PFNIEMAIMPLSSEF2I32U64;
3497	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I64U64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int64_t pi64Dst, const uint64_t pu64Src)); / pu64Src is a double precision floating point. */
3498	typedef FNIEMAIMPLSSEF2I64U64 *PFNIEMAIMPLSSEF2I64U64;
3499	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I32U32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int32_t pi32Dst, const uint32_t pu32Src)); / pu32Src is a single precision floating point. */
3500	typedef FNIEMAIMPLSSEF2I32U32 *PFNIEMAIMPLSSEF2I32U32;
3501	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I64U32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int64_t pi64Dst, const uint32_t pu32Src)); / pu32Src is a single precision floating point. */
3502	typedef FNIEMAIMPLSSEF2I64U32 *PFNIEMAIMPLSSEF2I64U32;
3503
3504	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvttsd2si_i32_r64;
3505	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvtsd2si_i32_r64;
3506
3507	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvttsd2si_i64_r64;
3508	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvtsd2si_i64_r64;
3509
3510	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvttss2si_i32_r32;
3511	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvtss2si_i32_r32;
3512
3513	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvttss2si_i64_r32;
3514	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvtss2si_i64_r32;
3515
3516	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R32I32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT32U pr32Dst, const int32_t pi32Src));
3517	typedef FNIEMAIMPLSSEF2R32I32 *PFNIEMAIMPLSSEF2R32I32;
3518	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R32I64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT32U pr32Dst, const int64_t pi64Src));
3519	typedef FNIEMAIMPLSSEF2R32I64 *PFNIEMAIMPLSSEF2R32I64;
3520
3521	FNIEMAIMPLSSEF2R32I32 iemAImpl_cvtsi2ss_r32_i32;
3522	FNIEMAIMPLSSEF2R32I64 iemAImpl_cvtsi2ss_r32_i64;
3523
3524	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R64I32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT64U pr64Dst, const int32_t pi32Src));
3525	typedef FNIEMAIMPLSSEF2R64I32 *PFNIEMAIMPLSSEF2R64I32;
3526	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R64I64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT64U pr64Dst, const int64_t pi64Src));
3527	typedef FNIEMAIMPLSSEF2R64I64 *PFNIEMAIMPLSSEF2R64I64;
3528
3529	FNIEMAIMPLSSEF2R64I32 iemAImpl_cvtsi2sd_r64_i32;
3530	FNIEMAIMPLSSEF2R64I64 iemAImpl_cvtsi2sd_r64_i64;
3531
3532
3533	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFLMXCSR128,(uint32_t pfMxcsr, uint32_t pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
3534	typedef FNIEMAIMPLF2EFLMXCSR128 *PFNIEMAIMPLF2EFLMXCSR128;
3535
3536	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_ucomiss_u128;
3537	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback;
3538
3539	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_ucomisd_u128;
3540	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback;
3541
3542	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_comiss_u128;
3543	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback;
3544
3545	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_comisd_u128;
3546	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback;
3547
3548
3549	typedef struct IEMMEDIAF2XMMSRC
3550	{
3551	X86XMMREG uSrc1;
3552	X86XMMREG uSrc2;
3553	} IEMMEDIAF2XMMSRC;
3554	typedef IEMMEDIAF2XMMSRC *PIEMMEDIAF2XMMSRC;
3555	typedef const IEMMEDIAF2XMMSRC *PCIEMMEDIAF2XMMSRC;
3556
3557	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRF2XMMIMM8,(uint32_t *pfMxcsr, PX86XMMREG puDst, PCIEMMEDIAF2XMMSRC puSrc, uint8_t bEvil));
3558	typedef FNIEMAIMPLMXCSRF2XMMIMM8 *PFNIEMAIMPLMXCSRF2XMMIMM8;
3559
3560	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpps_u128;
3561	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmppd_u128;
3562	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpss_u128;
3563	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpsd_u128;
3564	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundss_u128;
3565	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundsd_u128;
3566
3567	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundps_u128, iemAImpl_roundps_u128_fallback;
3568	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundpd_u128, iemAImpl_roundpd_u128_fallback;
3569
3570	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_dpps_u128, iemAImpl_dpps_u128_fallback;
3571	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_dppd_u128, iemAImpl_dppd_u128_fallback;
3572
3573	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU64U128,(uint32_t pfMxcsr, uint64_t pu64Dst, PCX86XMMREG pSrc));
3574	typedef FNIEMAIMPLMXCSRU64U128 *PFNIEMAIMPLMXCSRU64U128;
3575
3576	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvtpd2pi_u128;
3577	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvttpd2pi_u128;
3578
3579	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU128U64,(uint32_t *pfMxcsr, PX86XMMREG pDst, uint64_t u64Src));
3580	typedef FNIEMAIMPLMXCSRU128U64 *PFNIEMAIMPLMXCSRU128U64;
3581
3582	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2ps_u128;
3583	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2pd_u128;
3584
3585	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU64U64,(uint32_t pfMxcsr, uint64_t pu64Dst, uint64_t u64Src));
3586	typedef FNIEMAIMPLMXCSRU64U64 *PFNIEMAIMPLMXCSRU64U64;
3587
3588	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvtps2pi_u128;
3589	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvttps2pi_u128;
3590
3591	/** @} */
3592
3593
3594	/** @name Function tables.
3595	* @{
3596	*/
3597
3598	/**
3599	* Function table for a binary operator providing implementation based on
3600	* operand size.
3601	*/
3602	typedef struct IEMOPBINSIZES
3603	{
3604	PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
3605	PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
3606	PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
3607	PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
3608	} IEMOPBINSIZES;
3609	/** Pointer to a binary operator function table. */
3610	typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
3611
3612
3613	/**
3614	* Function table for a unary operator providing implementation based on
3615	* operand size.
3616	*/
3617	typedef struct IEMOPUNARYSIZES
3618	{
3619	PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
3620	PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
3621	PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
3622	PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
3623	} IEMOPUNARYSIZES;
3624	/** Pointer to a unary operator function table. */
3625	typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
3626
3627
3628	/**
3629	* Function table for a shift operator providing implementation based on
3630	* operand size.
3631	*/
3632	typedef struct IEMOPSHIFTSIZES
3633	{
3634	PFNIEMAIMPLSHIFTU8 pfnNormalU8;
3635	PFNIEMAIMPLSHIFTU16 pfnNormalU16;
3636	PFNIEMAIMPLSHIFTU32 pfnNormalU32;
3637	PFNIEMAIMPLSHIFTU64 pfnNormalU64;
3638	} IEMOPSHIFTSIZES;
3639	/** Pointer to a shift operator function table. */
3640	typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
3641
3642
3643	/**
3644	* Function table for a multiplication or division operation.
3645	*/
3646	typedef struct IEMOPMULDIVSIZES
3647	{
3648	PFNIEMAIMPLMULDIVU8 pfnU8;
3649	PFNIEMAIMPLMULDIVU16 pfnU16;
3650	PFNIEMAIMPLMULDIVU32 pfnU32;
3651	PFNIEMAIMPLMULDIVU64 pfnU64;
3652	} IEMOPMULDIVSIZES;
3653	/** Pointer to a multiplication or division operation function table. */
3654	typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
3655
3656
3657	/**
3658	* Function table for a double precision shift operator providing implementation
3659	* based on operand size.
3660	*/
3661	typedef struct IEMOPSHIFTDBLSIZES
3662	{
3663	PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
3664	PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
3665	PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
3666	} IEMOPSHIFTDBLSIZES;
3667	/** Pointer to a double precision shift function table. */
3668	typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
3669
3670
3671	/**
3672	* Function table for media instruction taking two full sized media source
3673	* registers and one full sized destination register (AVX).
3674	*/
3675	typedef struct IEMOPMEDIAF3
3676	{
3677	PFNIEMAIMPLMEDIAF3U128 pfnU128;
3678	PFNIEMAIMPLMEDIAF3U256 pfnU256;
3679	} IEMOPMEDIAF3;
3680	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
3681	typedef IEMOPMEDIAF3 const *PCIEMOPMEDIAF3;
3682
3683	/** @def IEMOPMEDIAF3_INIT_VARS_EX
3684	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3685	* given functions as initializers. For use in AVX functions where a pair of
3686	* functions are only used once and the function table need not be public. */
3687	#ifndef TST_IEM_CHECK_MC
3688	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3689	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3690	static IEMOPMEDIAF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3691	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3692	# else
3693	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3694	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3695	# endif
3696	#else
3697	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3698	#endif
3699	/** @def IEMOPMEDIAF3_INIT_VARS
3700	* Generate AVX function tables for the @a a_InstrNm instruction.
3701	* @sa IEMOPMEDIAF3_INIT_VARS_EX */
3702	#define IEMOPMEDIAF3_INIT_VARS(a_InstrNm) \
3703	IEMOPMEDIAF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3704	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3705
3706	/**
3707	* Function table for media instruction taking two full sized media source
3708	* registers and one full sized destination register, but no additional state
3709	* (AVX).
3710	*/
3711	typedef struct IEMOPMEDIAOPTF3
3712	{
3713	PFNIEMAIMPLMEDIAOPTF3U128 pfnU128;
3714	PFNIEMAIMPLMEDIAOPTF3U256 pfnU256;
3715	} IEMOPMEDIAOPTF3;
3716	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
3717	typedef IEMOPMEDIAOPTF3 const *PCIEMOPMEDIAOPTF3;
3718
3719	/** @def IEMOPMEDIAOPTF3_INIT_VARS_EX
3720	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3721	* given functions as initializers. For use in AVX functions where a pair of
3722	* functions are only used once and the function table need not be public. */
3723	#ifndef TST_IEM_CHECK_MC
3724	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3725	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3726	static IEMOPMEDIAOPTF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3727	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3728	# else
3729	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3730	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3731	# endif
3732	#else
3733	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3734	#endif
3735	/** @def IEMOPMEDIAOPTF3_INIT_VARS
3736	* Generate AVX function tables for the @a a_InstrNm instruction.
3737	* @sa IEMOPMEDIAOPTF3_INIT_VARS_EX */
3738	#define IEMOPMEDIAOPTF3_INIT_VARS(a_InstrNm) \
3739	IEMOPMEDIAOPTF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3740	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3741
3742	/**
3743	* Function table for media instruction taking one full sized media source
3744	* registers and one full sized destination register, but no additional state
3745	* (AVX).
3746	*/
3747	typedef struct IEMOPMEDIAOPTF2
3748	{
3749	PFNIEMAIMPLMEDIAOPTF2U128 pfnU128;
3750	PFNIEMAIMPLMEDIAOPTF2U256 pfnU256;
3751	} IEMOPMEDIAOPTF2;
3752	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
3753	typedef IEMOPMEDIAOPTF2 const *PCIEMOPMEDIAOPTF2;
3754
3755	/** @def IEMOPMEDIAOPTF2_INIT_VARS_EX
3756	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3757	* given functions as initializers. For use in AVX functions where a pair of
3758	* functions are only used once and the function table need not be public. */
3759	#ifndef TST_IEM_CHECK_MC
3760	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3761	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3762	static IEMOPMEDIAOPTF2 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3763	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3764	# else
3765	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3766	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3767	# endif
3768	#else
3769	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3770	#endif
3771	/** @def IEMOPMEDIAOPTF2_INIT_VARS
3772	* Generate AVX function tables for the @a a_InstrNm instruction.
3773	* @sa IEMOPMEDIAOPTF2_INIT_VARS_EX */
3774	#define IEMOPMEDIAOPTF2_INIT_VARS(a_InstrNm) \
3775	IEMOPMEDIAOPTF2_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3776	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3777
3778	/**
3779	* Function table for media instruction taking two full sized media source
3780	* registers and one full sized destination register and an 8-bit immediate, but no additional state
3781	* (AVX).
3782	*/
3783	typedef struct IEMOPMEDIAOPTF3IMM8
3784	{
3785	PFNIEMAIMPLMEDIAOPTF3U128IMM8 pfnU128;
3786	PFNIEMAIMPLMEDIAOPTF3U256IMM8 pfnU256;
3787	} IEMOPMEDIAOPTF3IMM8;
3788	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
3789	typedef IEMOPMEDIAOPTF3IMM8 const *PCIEMOPMEDIAOPTF3IMM8;
3790
3791	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX
3792	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3793	* given functions as initializers. For use in AVX functions where a pair of
3794	* functions are only used once and the function table need not be public. */
3795	#ifndef TST_IEM_CHECK_MC
3796	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3797	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3798	static IEMOPMEDIAOPTF3IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3799	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3800	# else
3801	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3802	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3803	# endif
3804	#else
3805	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3806	#endif
3807	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS
3808	* Generate AVX function tables for the @a a_InstrNm instruction.
3809	* @sa IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX */
3810	#define IEMOPMEDIAOPTF3IMM8_INIT_VARS(a_InstrNm) \
3811	IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3812	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3813	/** @} */
3814
3815
3816	/**
3817	* Function table for blend type instruction taking three full sized media source
3818	* registers and one full sized destination register, but no additional state
3819	* (AVX).
3820	*/
3821	typedef struct IEMOPBLENDOP
3822	{
3823	PFNIEMAIMPLAVXBLENDU128 pfnU128;
3824	PFNIEMAIMPLAVXBLENDU256 pfnU256;
3825	} IEMOPBLENDOP;
3826	/** Pointer to a media operation function table for 4 full sized ops (AVX). */
3827	typedef IEMOPBLENDOP const *PCIEMOPBLENDOP;
3828
3829	/** @def IEMOPBLENDOP_INIT_VARS_EX
3830	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
3831	* given functions as initializers. For use in AVX functions where a pair of
3832	* functions are only used once and the function table need not be public. */
3833	#ifndef TST_IEM_CHECK_MC
3834	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
3835	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3836	static IEMOPBLENDOP const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
3837	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3838	# else
3839	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
3840	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
3841	# endif
3842	#else
3843	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
3844	#endif
3845	/** @def IEMOPBLENDOP_INIT_VARS
3846	* Generate AVX function tables for the @a a_InstrNm instruction.
3847	* @sa IEMOPBLENDOP_INIT_VARS_EX */
3848	#define IEMOPBLENDOP_INIT_VARS(a_InstrNm) \
3849	IEMOPBLENDOP_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
3850	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
3851
3852
3853	/** @name SSE/AVX single/double precision floating point operations.
3854	* @{ */
3855	/**
3856	* A SSE result.
3857	*/
3858	typedef struct IEMSSERESULT
3859	{
3860	/** The output value. */
3861	X86XMMREG uResult;
3862	/** The output status. */
3863	uint32_t MXCSR;
3864	} IEMSSERESULT;
3865	AssertCompileMemberOffset(IEMSSERESULT, MXCSR, 128 / 8);
3866	/** Pointer to a SSE result. */
3867	typedef IEMSSERESULT *PIEMSSERESULT;
3868	/** Pointer to a const SSE result. */
3869	typedef IEMSSERESULT const *PCIEMSSERESULT;
3870
3871
3872	/**
3873	* A AVX128 result.
3874	*/
3875	typedef struct IEMAVX128RESULT
3876	{
3877	/** The output value. */
3878	X86XMMREG uResult;
3879	/** The output status. */
3880	uint32_t MXCSR;
3881	} IEMAVX128RESULT;
3882	AssertCompileMemberOffset(IEMAVX128RESULT, MXCSR, 128 / 8);
3883	/** Pointer to a AVX128 result. */
3884	typedef IEMAVX128RESULT *PIEMAVX128RESULT;
3885	/** Pointer to a const AVX128 result. */
3886	typedef IEMAVX128RESULT const *PCIEMAVX128RESULT;
3887
3888
3889	/**
3890	* A AVX256 result.
3891	*/
3892	typedef struct IEMAVX256RESULT
3893	{
3894	/** The output value. */
3895	X86YMMREG uResult;
3896	/** The output status. */
3897	uint32_t MXCSR;
3898	} IEMAVX256RESULT;
3899	AssertCompileMemberOffset(IEMAVX256RESULT, MXCSR, 256 / 8);
3900	/** Pointer to a AVX256 result. */
3901	typedef IEMAVX256RESULT *PIEMAVX256RESULT;
3902	/** Pointer to a const AVX256 result. */
3903	typedef IEMAVX256RESULT const *PCIEMAVX256RESULT;
3904
3905
3906	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
3907	typedef FNIEMAIMPLFPSSEF2U128 *PFNIEMAIMPLFPSSEF2U128;
3908	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128R32,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
3909	typedef FNIEMAIMPLFPSSEF2U128R32 *PFNIEMAIMPLFPSSEF2U128R32;
3910	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128R64,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
3911	typedef FNIEMAIMPLFPSSEF2U128R64 *PFNIEMAIMPLFPSSEF2U128R64;
3912
3913	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
3914	typedef FNIEMAIMPLFPAVXF3U128 *PFNIEMAIMPLFPAVXF3U128;
3915	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128R32,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
3916	typedef FNIEMAIMPLFPAVXF3U128R32 *PFNIEMAIMPLFPAVXF3U128R32;
3917	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128R64,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
3918	typedef FNIEMAIMPLFPAVXF3U128R64 *PFNIEMAIMPLFPAVXF3U128R64;
3919
3920	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U256,(PX86XSAVEAREA pExtState, PIEMAVX256RESULT pResult, PCX86YMMREG puSrc1, PCX86YMMREG puSrc2));
3921	typedef FNIEMAIMPLFPAVXF3U256 *PFNIEMAIMPLFPAVXF3U256;
3922
3923	FNIEMAIMPLFPSSEF2U128 iemAImpl_addps_u128;
3924	FNIEMAIMPLFPSSEF2U128 iemAImpl_addpd_u128;
3925	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulps_u128;
3926	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulpd_u128;
3927	FNIEMAIMPLFPSSEF2U128 iemAImpl_subps_u128;
3928	FNIEMAIMPLFPSSEF2U128 iemAImpl_subpd_u128;
3929	FNIEMAIMPLFPSSEF2U128 iemAImpl_minps_u128;
3930	FNIEMAIMPLFPSSEF2U128 iemAImpl_minpd_u128;
3931	FNIEMAIMPLFPSSEF2U128 iemAImpl_divps_u128;
3932	FNIEMAIMPLFPSSEF2U128 iemAImpl_divpd_u128;
3933	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxps_u128;
3934	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxpd_u128;
3935	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddps_u128;
3936	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddpd_u128;
3937	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubps_u128;
3938	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubpd_u128;
3939	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtps_u128;
3940	FNIEMAIMPLFPSSEF2U128 iemAImpl_rsqrtps_u128;
3941	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtpd_u128;
3942	FNIEMAIMPLFPSSEF2U128 iemAImpl_rcpps_u128;
3943	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubps_u128;
3944	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubpd_u128;
3945	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2ps_u128;
3946	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2pd_u128;
3947
3948	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2ps_u128;
3949	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2dq_u128;
3950	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttps2dq_u128;
3951	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttpd2dq_u128;
3952	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2pd_u128;
3953	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2dq_u128;
3954
3955	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_addss_u128_r32;
3956	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_addsd_u128_r64;
3957	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_mulss_u128_r32;
3958	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_mulsd_u128_r64;
3959	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_subss_u128_r32;
3960	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_subsd_u128_r64;
3961	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_minss_u128_r32;
3962	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_minsd_u128_r64;
3963	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_divss_u128_r32;
3964	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_divsd_u128_r64;
3965	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_maxss_u128_r32;
3966	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_maxsd_u128_r64;
3967	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_cvtss2sd_u128_r32;
3968	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_cvtsd2ss_u128_r64;
3969	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_sqrtss_u128_r32;
3970	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_sqrtsd_u128_r64;
3971	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_rsqrtss_u128_r32;
3972	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_rcpss_u128_r32;
3973
3974	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddps_u128, iemAImpl_vaddps_u128_fallback;
3975	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddpd_u128, iemAImpl_vaddpd_u128_fallback;
3976	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulps_u128, iemAImpl_vmulps_u128_fallback;
3977	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulpd_u128, iemAImpl_vmulpd_u128_fallback;
3978	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubps_u128, iemAImpl_vsubps_u128_fallback;
3979	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubpd_u128, iemAImpl_vsubpd_u128_fallback;
3980	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminps_u128, iemAImpl_vminps_u128_fallback;
3981	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminpd_u128, iemAImpl_vminpd_u128_fallback;
3982	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivps_u128, iemAImpl_vdivps_u128_fallback;
3983	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivpd_u128, iemAImpl_vdivpd_u128_fallback;
3984	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxps_u128, iemAImpl_vmaxps_u128_fallback;
3985	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxpd_u128, iemAImpl_vmaxpd_u128_fallback;
3986	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddps_u128, iemAImpl_vhaddps_u128_fallback;
3987	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddpd_u128, iemAImpl_vhaddpd_u128_fallback;
3988	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubps_u128, iemAImpl_vhsubps_u128_fallback;
3989	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubpd_u128, iemAImpl_vhsubpd_u128_fallback;
3990	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtps_u128, iemAImpl_vsqrtps_u128_fallback;
3991	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtpd_u128, iemAImpl_vsqrtpd_u128_fallback;
3992	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubps_u128, iemAImpl_vaddsubps_u128_fallback;
3993	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubpd_u128, iemAImpl_vaddsubpd_u128_fallback;
3994	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtpd2ps_u128, iemAImpl_vcvtpd2ps_u128_fallback;
3995	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtps2pd_u128, iemAImpl_vcvtps2pd_u128_fallback;
3996
3997	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vaddss_u128_r32, iemAImpl_vaddss_u128_r32_fallback;
3998	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vaddsd_u128_r64, iemAImpl_vaddsd_u128_r64_fallback;
3999	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmulss_u128_r32, iemAImpl_vmulss_u128_r32_fallback;
4000	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmulsd_u128_r64, iemAImpl_vmulsd_u128_r64_fallback;
4001	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsubss_u128_r32, iemAImpl_vsubss_u128_r32_fallback;
4002	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsubsd_u128_r64, iemAImpl_vsubsd_u128_r64_fallback;
4003	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vminss_u128_r32, iemAImpl_vminss_u128_r32_fallback;
4004	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vminsd_u128_r64, iemAImpl_vminsd_u128_r64_fallback;
4005	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vdivss_u128_r32, iemAImpl_vdivss_u128_r32_fallback;
4006	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vdivsd_u128_r64, iemAImpl_vdivsd_u128_r64_fallback;
4007	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmaxss_u128_r32, iemAImpl_vmaxss_u128_r32_fallback;
4008	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmaxsd_u128_r64, iemAImpl_vmaxsd_u128_r64_fallback;
4009	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsqrtss_u128_r32, iemAImpl_vsqrtss_u128_r32_fallback;
4010	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsqrtsd_u128_r64, iemAImpl_vsqrtsd_u128_r64_fallback;
4011
4012	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddps_u256, iemAImpl_vaddps_u256_fallback;
4013	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddpd_u256, iemAImpl_vaddpd_u256_fallback;
4014	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulps_u256, iemAImpl_vmulps_u256_fallback;
4015	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulpd_u256, iemAImpl_vmulpd_u256_fallback;
4016	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubps_u256, iemAImpl_vsubps_u256_fallback;
4017	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubpd_u256, iemAImpl_vsubpd_u256_fallback;
4018	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminps_u256, iemAImpl_vminps_u256_fallback;
4019	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminpd_u256, iemAImpl_vminpd_u256_fallback;
4020	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivps_u256, iemAImpl_vdivps_u256_fallback;
4021	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivpd_u256, iemAImpl_vdivpd_u256_fallback;
4022	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxps_u256, iemAImpl_vmaxps_u256_fallback;
4023	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxpd_u256, iemAImpl_vmaxpd_u256_fallback;
4024	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddps_u256, iemAImpl_vhaddps_u256_fallback;
4025	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddpd_u256, iemAImpl_vhaddpd_u256_fallback;
4026	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubps_u256, iemAImpl_vhsubps_u256_fallback;
4027	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubpd_u256, iemAImpl_vhsubpd_u256_fallback;
4028	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubps_u256, iemAImpl_vhaddsubps_u256_fallback;
4029	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubpd_u256, iemAImpl_vhaddsubpd_u256_fallback;
4030	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtpd2ps_u256, iemAImpl_vcvtpd2ps_u256_fallback;
4031	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtps2pd_u256, iemAImpl_vcvtps2pd_u256_fallback;
4032	/** @} */
4033
4034	/** @name C instruction implementations for anything slightly complicated.
4035	* @{ */
4036
4037	/**
4038	* For typedef'ing or declaring a C instruction implementation function taking
4039	* no extra arguments.
4040	*
4041	* @param a_Name The name of the type.
4042	*/
4043	# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
4044	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
4045	/**
4046	* For defining a C instruction implementation function taking no extra
4047	* arguments.
4048	*
4049	* @param a_Name The name of the function
4050	*/
4051	# define IEM_CIMPL_DEF_0(a_Name) \
4052	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
4053	/**
4054	* Prototype version of IEM_CIMPL_DEF_0.
4055	*/
4056	# define IEM_CIMPL_PROTO_0(a_Name) \
4057	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
4058	/**
4059	* For calling a C instruction implementation function taking no extra
4060	* arguments.
4061	*
4062	* This special call macro adds default arguments to the call and allow us to
4063	* change these later.
4064	*
4065	* @param a_fn The name of the function.
4066	*/
4067	# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
4068
4069	/** Type for a C instruction implementation function taking no extra
4070	* arguments. */
4071	typedef IEM_CIMPL_DECL_TYPE_0(FNIEMCIMPL0);
4072	/** Function pointer type for a C instruction implementation function taking
4073	* no extra arguments. */
4074	typedef FNIEMCIMPL0 *PFNIEMCIMPL0;
4075
4076	/**
4077	* For typedef'ing or declaring a C instruction implementation function taking
4078	* one extra argument.
4079	*
4080	* @param a_Name The name of the type.
4081	* @param a_Type0 The argument type.
4082	* @param a_Arg0 The argument name.
4083	*/
4084	# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
4085	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
4086	/**
4087	* For defining a C instruction implementation function taking one extra
4088	* argument.
4089	*
4090	* @param a_Name The name of the function
4091	* @param a_Type0 The argument type.
4092	* @param a_Arg0 The argument name.
4093	*/
4094	# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
4095	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
4096	/**
4097	* Prototype version of IEM_CIMPL_DEF_1.
4098	*/
4099	# define IEM_CIMPL_PROTO_1(a_Name, a_Type0, a_Arg0) \
4100	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
4101	/**
4102	* For calling a C instruction implementation function taking one extra
4103	* argument.
4104	*
4105	* This special call macro adds default arguments to the call and allow us to
4106	* change these later.
4107	*
4108	* @param a_fn The name of the function.
4109	* @param a0 The name of the 1st argument.
4110	*/
4111	# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
4112
4113	/**
4114	* For typedef'ing or declaring a C instruction implementation function taking
4115	* two extra arguments.
4116	*
4117	* @param a_Name The name of the type.
4118	* @param a_Type0 The type of the 1st argument
4119	* @param a_Arg0 The name of the 1st argument.
4120	* @param a_Type1 The type of the 2nd argument.
4121	* @param a_Arg1 The name of the 2nd argument.
4122	*/
4123	# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
4124	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
4125	/**
4126	* For defining a C instruction implementation function taking two extra
4127	* arguments.
4128	*
4129	* @param a_Name The name of the function.
4130	* @param a_Type0 The type of the 1st argument
4131	* @param a_Arg0 The name of the 1st argument.
4132	* @param a_Type1 The type of the 2nd argument.
4133	* @param a_Arg1 The name of the 2nd argument.
4134	*/
4135	# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
4136	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
4137	/**
4138	* Prototype version of IEM_CIMPL_DEF_2.
4139	*/
4140	# define IEM_CIMPL_PROTO_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
4141	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
4142	/**
4143	* For calling a C instruction implementation function taking two extra
4144	* arguments.
4145	*
4146	* This special call macro adds default arguments to the call and allow us to
4147	* change these later.
4148	*
4149	* @param a_fn The name of the function.
4150	* @param a0 The name of the 1st argument.
4151	* @param a1 The name of the 2nd argument.
4152	*/
4153	# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
4154
4155	/**
4156	* For typedef'ing or declaring a C instruction implementation function taking
4157	* three extra arguments.
4158	*
4159	* @param a_Name The name of the type.
4160	* @param a_Type0 The type of the 1st argument
4161	* @param a_Arg0 The name of the 1st argument.
4162	* @param a_Type1 The type of the 2nd argument.
4163	* @param a_Arg1 The name of the 2nd argument.
4164	* @param a_Type2 The type of the 3rd argument.
4165	* @param a_Arg2 The name of the 3rd argument.
4166	*/
4167	# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
4168	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
4169	/**
4170	* For defining a C instruction implementation function taking three extra
4171	* arguments.
4172	*
4173	* @param a_Name The name of the function.
4174	* @param a_Type0 The type of the 1st argument
4175	* @param a_Arg0 The name of the 1st argument.
4176	* @param a_Type1 The type of the 2nd argument.
4177	* @param a_Arg1 The name of the 2nd argument.
4178	* @param a_Type2 The type of the 3rd argument.
4179	* @param a_Arg2 The name of the 3rd argument.
4180	*/
4181	# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
4182	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
4183	/**
4184	* Prototype version of IEM_CIMPL_DEF_3.
4185	*/
4186	# define IEM_CIMPL_PROTO_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
4187	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
4188	/**
4189	* For calling a C instruction implementation function taking three extra
4190	* arguments.
4191	*
4192	* This special call macro adds default arguments to the call and allow us to
4193	* change these later.
4194	*
4195	* @param a_fn The name of the function.
4196	* @param a0 The name of the 1st argument.
4197	* @param a1 The name of the 2nd argument.
4198	* @param a2 The name of the 3rd argument.
4199	*/
4200	# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
4201
4202
4203	/**
4204	* For typedef'ing or declaring a C instruction implementation function taking
4205	* four extra arguments.
4206	*
4207	* @param a_Name The name of the type.
4208	* @param a_Type0 The type of the 1st argument
4209	* @param a_Arg0 The name of the 1st argument.
4210	* @param a_Type1 The type of the 2nd argument.
4211	* @param a_Arg1 The name of the 2nd argument.
4212	* @param a_Type2 The type of the 3rd argument.
4213	* @param a_Arg2 The name of the 3rd argument.
4214	* @param a_Type3 The type of the 4th argument.
4215	* @param a_Arg3 The name of the 4th argument.
4216	*/
4217	# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
4218	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
4219	/**
4220	* For defining a C instruction implementation function taking four extra
4221	* arguments.
4222	*
4223	* @param a_Name The name of the function.
4224	* @param a_Type0 The type of the 1st argument
4225	* @param a_Arg0 The name of the 1st argument.
4226	* @param a_Type1 The type of the 2nd argument.
4227	* @param a_Arg1 The name of the 2nd argument.
4228	* @param a_Type2 The type of the 3rd argument.
4229	* @param a_Arg2 The name of the 3rd argument.
4230	* @param a_Type3 The type of the 4th argument.
4231	* @param a_Arg3 The name of the 4th argument.
4232	*/
4233	# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
4234	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4235	a_Type2 a_Arg2, a_Type3 a_Arg3))
4236	/**
4237	* Prototype version of IEM_CIMPL_DEF_4.
4238	*/
4239	# define IEM_CIMPL_PROTO_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
4240	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4241	a_Type2 a_Arg2, a_Type3 a_Arg3))
4242	/**
4243	* For calling a C instruction implementation function taking four extra
4244	* arguments.
4245	*
4246	* This special call macro adds default arguments to the call and allow us to
4247	* change these later.
4248	*
4249	* @param a_fn The name of the function.
4250	* @param a0 The name of the 1st argument.
4251	* @param a1 The name of the 2nd argument.
4252	* @param a2 The name of the 3rd argument.
4253	* @param a3 The name of the 4th argument.
4254	*/
4255	# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
4256
4257
4258	/**
4259	* For typedef'ing or declaring a C instruction implementation function taking
4260	* five extra arguments.
4261	*
4262	* @param a_Name The name of the type.
4263	* @param a_Type0 The type of the 1st argument
4264	* @param a_Arg0 The name of the 1st argument.
4265	* @param a_Type1 The type of the 2nd argument.
4266	* @param a_Arg1 The name of the 2nd argument.
4267	* @param a_Type2 The type of the 3rd argument.
4268	* @param a_Arg2 The name of the 3rd argument.
4269	* @param a_Type3 The type of the 4th argument.
4270	* @param a_Arg3 The name of the 4th argument.
4271	* @param a_Type4 The type of the 5th argument.
4272	* @param a_Arg4 The name of the 5th argument.
4273	*/
4274	# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
4275	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, \
4276	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
4277	a_Type3 a_Arg3, a_Type4 a_Arg4))
4278	/**
4279	* For defining a C instruction implementation function taking five extra
4280	* arguments.
4281	*
4282	* @param a_Name The name of the function.
4283	* @param a_Type0 The type of the 1st argument
4284	* @param a_Arg0 The name of the 1st argument.
4285	* @param a_Type1 The type of the 2nd argument.
4286	* @param a_Arg1 The name of the 2nd argument.
4287	* @param a_Type2 The type of the 3rd argument.
4288	* @param a_Arg2 The name of the 3rd argument.
4289	* @param a_Type3 The type of the 4th argument.
4290	* @param a_Arg3 The name of the 4th argument.
4291	* @param a_Type4 The type of the 5th argument.
4292	* @param a_Arg4 The name of the 5th argument.
4293	*/
4294	# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
4295	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4296	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
4297	/**
4298	* Prototype version of IEM_CIMPL_DEF_5.
4299	*/
4300	# define IEM_CIMPL_PROTO_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
4301	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4302	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
4303	/**
4304	* For calling a C instruction implementation function taking five extra
4305	* arguments.
4306	*
4307	* This special call macro adds default arguments to the call and allow us to
4308	* change these later.
4309	*
4310	* @param a_fn The name of the function.
4311	* @param a0 The name of the 1st argument.
4312	* @param a1 The name of the 2nd argument.
4313	* @param a2 The name of the 3rd argument.
4314	* @param a3 The name of the 4th argument.
4315	* @param a4 The name of the 5th argument.
4316	*/
4317	# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
4318
4319	/** @} */
4320
4321
4322	/** @name Opcode Decoder Function Types.
4323	* @{ */
4324
4325	/** @typedef PFNIEMOP
4326	* Pointer to an opcode decoder function.
4327	*/
4328
4329	/** @def FNIEMOP_DEF
4330	* Define an opcode decoder function.
4331	*
4332	* We're using macors for this so that adding and removing parameters as well as
4333	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL
4334	*
4335	* @param a_Name The function name.
4336	*/
4337
4338	/** @typedef PFNIEMOPRM
4339	* Pointer to an opcode decoder function with RM byte.
4340	*/
4341
4342	/** @def FNIEMOPRM_DEF
4343	* Define an opcode decoder function with RM byte.
4344	*
4345	* We're using macors for this so that adding and removing parameters as well as
4346	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL_1
4347	*
4348	* @param a_Name The function name.
4349	*/
4350
4351	#if defined(__GNUC__) && defined(RT_ARCH_X86)
4352	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOP)(PVMCPUCC pVCpu);
4353	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4354	# define FNIEMOP_DEF(a_Name) \
4355	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu)
4356	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4357	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
4358	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4359	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
4360
4361	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
4362	typedef VBOXSTRICTRC (__fastcall * PFNIEMOP)(PVMCPUCC pVCpu);
4363	typedef VBOXSTRICTRC (__fastcall * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4364	# define FNIEMOP_DEF(a_Name) \
4365	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
4366	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4367	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
4368	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4369	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
4370
4371	#elif defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
4372	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
4373	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4374	# define FNIEMOP_DEF(a_Name) \
4375	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu)
4376	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4377	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
4378	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4379	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
4380
4381	#else
4382	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
4383	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4384	# define FNIEMOP_DEF(a_Name) \
4385	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
4386	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4387	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
4388	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4389	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
4390
4391	#endif
4392	#define FNIEMOPRM_DEF(a_Name) FNIEMOP_DEF_1(a_Name, uint8_t, bRm)
4393
4394	/**
4395	* Call an opcode decoder function.
4396	*
4397	* We're using macors for this so that adding and removing parameters can be
4398	* done as we please. See FNIEMOP_DEF.
4399	*/
4400	#define FNIEMOP_CALL(a_pfn) (a_pfn)(pVCpu)
4401
4402	/**
4403	* Call a common opcode decoder function taking one extra argument.
4404	*
4405	* We're using macors for this so that adding and removing parameters can be
4406	* done as we please. See FNIEMOP_DEF_1.
4407	*/
4408	#define FNIEMOP_CALL_1(a_pfn, a0) (a_pfn)(pVCpu, a0)
4409
4410	/**
4411	* Call a common opcode decoder function taking one extra argument.
4412	*
4413	* We're using macors for this so that adding and removing parameters can be
4414	* done as we please. See FNIEMOP_DEF_1.
4415	*/
4416	#define FNIEMOP_CALL_2(a_pfn, a0, a1) (a_pfn)(pVCpu, a0, a1)
4417	/** @} */
4418
4419
4420	/** @name Misc Helpers
4421	* @{ */
4422
4423	/** Used to shut up GCC warnings about variables that 'may be used uninitialized'
4424	* due to GCC lacking knowledge about the value range of a switch. */
4425	#if RT_CPLUSPLUS_PREREQ(202000)
4426	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: [[unlikely]] AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
4427	#else
4428	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
4429	#endif
4430
4431	/** Variant of IEM_NOT_REACHED_DEFAULT_CASE_RET that returns a custom value. */
4432	#if RT_CPLUSPLUS_PREREQ(202000)
4433	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: [[unlikely]] AssertFailedReturn(a_RetValue)
4434	#else
4435	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: AssertFailedReturn(a_RetValue)
4436	#endif
4437
4438	/**
4439	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
4440	* occation.
4441	*/
4442	#ifdef LOG_ENABLED
4443	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
4444	do { \
4445	/Log/ LogAlways(("%s: returning IEM_RETURN_ASPECT_NOT_IMPLEMENTED (line %d)\n", __FUNCTION__, __LINE__)); \
4446	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
4447	} while (0)
4448	#else
4449	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
4450	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
4451	#endif
4452
4453	/**
4454	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
4455	* occation using the supplied logger statement.
4456	*
4457	* @param a_LoggerArgs What to log on failure.
4458	*/
4459	#ifdef LOG_ENABLED
4460	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
4461	do { \
4462	LogAlways((LOG_FN_FMT ": ", __PRETTY_FUNCTION__)); LogAlways(a_LoggerArgs); \
4463	/LogFunc(a_LoggerArgs);/ \
4464	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
4465	} while (0)
4466	#else
4467	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
4468	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
4469	#endif
4470
4471	/**
4472	* Gets the CPU mode (from fExec) as a IEMMODE value.
4473	*
4474	* @returns IEMMODE
4475	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4476	*/
4477	#define IEM_GET_CPU_MODE(a_pVCpu) ((a_pVCpu)->iem.s.fExec & IEM_F_MODE_CPUMODE_MASK)
4478
4479	/**
4480	* Check if we're currently executing in real or virtual 8086 mode.
4481	*
4482	* @returns @c true if it is, @c false if not.
4483	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4484	*/
4485	#define IEM_IS_REAL_OR_V86_MODE(a_pVCpu) (( ((a_pVCpu)->iem.s.fExec ^ IEM_F_MODE_X86_PROT_MASK) \
4486	& (IEM_F_MODE_X86_V86_MASK \| IEM_F_MODE_X86_PROT_MASK)) != 0)
4487
4488	/**
4489	* Check if we're currently executing in virtual 8086 mode.
4490	*
4491	* @returns @c true if it is, @c false if not.
4492	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4493	*/
4494	#define IEM_IS_V86_MODE(a_pVCpu) (((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_V86_MASK) != 0)
4495
4496	/**
4497	* Check if we're currently executing in long mode.
4498	*
4499	* @returns @c true if it is, @c false if not.
4500	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4501	*/
4502	#define IEM_IS_LONG_MODE(a_pVCpu) (CPUMIsGuestInLongModeEx(IEM_GET_CTX(a_pVCpu)))
4503
4504	/**
4505	* Check if we're currently executing in a 16-bit code segment.
4506	*
4507	* @returns @c true if it is, @c false if not.
4508	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4509	*/
4510	#define IEM_IS_16BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_16BIT)
4511
4512	/**
4513	* Check if we're currently executing in a 32-bit code segment.
4514	*
4515	* @returns @c true if it is, @c false if not.
4516	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4517	*/
4518	#define IEM_IS_32BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_32BIT)
4519
4520	/**
4521	* Check if we're currently executing in a 64-bit code segment.
4522	*
4523	* @returns @c true if it is, @c false if not.
4524	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4525	*/
4526	#define IEM_IS_64BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_64BIT)
4527
4528	/**
4529	* Check if we're currently executing in real mode.
4530	*
4531	* @returns @c true if it is, @c false if not.
4532	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4533	*/
4534	#define IEM_IS_REAL_MODE(a_pVCpu) (!((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_PROT_MASK))
4535
4536	/**
4537	* Gets the current protection level (CPL).
4538	*
4539	* @returns 0..3
4540	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4541	*/
4542	#define IEM_GET_CPL(a_pVCpu) (((a_pVCpu)->iem.s.fExec >> IEM_F_X86_CPL_SHIFT) & IEM_F_X86_CPL_SMASK)
4543
4544	/**
4545	* Sets the current protection level (CPL).
4546	*
4547	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4548	*/
4549	#define IEM_SET_CPL(a_pVCpu, a_uCpl) \
4550	do { (a_pVCpu)->iem.s.fExec = ((a_pVCpu)->iem.s.fExec & ~IEM_F_X86_CPL_MASK) \| ((a_uCpl) << IEM_F_X86_CPL_SHIFT); } while (0)
4551
4552	/**
4553	* Returns a (const) pointer to the CPUMFEATURES for the guest CPU.
4554	* @returns PCCPUMFEATURES
4555	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4556	*/
4557	#define IEM_GET_GUEST_CPU_FEATURES(a_pVCpu) (&((a_pVCpu)->CTX_SUFF(pVM)->cpum.ro.GuestFeatures))
4558
4559	/**
4560	* Returns a (const) pointer to the CPUMFEATURES for the host CPU.
4561	* @returns PCCPUMFEATURES
4562	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4563	*/
4564	#define IEM_GET_HOST_CPU_FEATURES(a_pVCpu) (&g_CpumHostFeatures.s)
4565
4566	/**
4567	* Evaluates to true if we're presenting an Intel CPU to the guest.
4568	*/
4569	#define IEM_IS_GUEST_CPU_INTEL(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL )
4570
4571	/**
4572	* Evaluates to true if we're presenting an AMD CPU to the guest.
4573	*/
4574	#define IEM_IS_GUEST_CPU_AMD(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_AMD \|\| (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_HYGON )
4575
4576	/**
4577	* Check if the address is canonical.
4578	*/
4579	#define IEM_IS_CANONICAL(a_u64Addr) X86_IS_CANONICAL(a_u64Addr)
4580
4581	/** Checks if the ModR/M byte is in register mode or not. */
4582	#define IEM_IS_MODRM_REG_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT) )
4583	/** Checks if the ModR/M byte is in memory mode or not. */
4584	#define IEM_IS_MODRM_MEM_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT) )
4585
4586	/**
4587	* Gets the register (reg) part of a ModR/M encoding, with REX.R added in.
4588	*
4589	* For use during decoding.
4590	*/
4591	#define IEM_GET_MODRM_REG(a_pVCpu, a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| (a_pVCpu)->iem.s.uRexReg )
4592	/**
4593	* Gets the r/m part of a ModR/M encoding as a register index, with REX.B added in.
4594	*
4595	* For use during decoding.
4596	*/
4597	#define IEM_GET_MODRM_RM(a_pVCpu, a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) \| (a_pVCpu)->iem.s.uRexB )
4598
4599	/**
4600	* Gets the register (reg) part of a ModR/M encoding, without REX.R.
4601	*
4602	* For use during decoding.
4603	*/
4604	#define IEM_GET_MODRM_REG_8(a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) )
4605	/**
4606	* Gets the r/m part of a ModR/M encoding as a register index, without REX.B.
4607	*
4608	* For use during decoding.
4609	*/
4610	#define IEM_GET_MODRM_RM_8(a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) )
4611
4612	/**
4613	* Gets the register (reg) part of a ModR/M encoding as an extended 8-bit
4614	* register index, with REX.R added in.
4615	*
4616	* For use during decoding.
4617	*
4618	* @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
4619	*/
4620	#define IEM_GET_MODRM_REG_EX8(a_pVCpu, a_bRm) \
4621	( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
4622	\|\| !((a_bRm) & (4 << X86_MODRM_REG_SHIFT)) /* IEM_GET_MODRM_REG(pVCpu, a_bRm) < 4 */ \
4623	? IEM_GET_MODRM_REG(pVCpu, a_bRm) : (((a_bRm) >> X86_MODRM_REG_SHIFT) & 3) \| 16)
4624	/**
4625	* Gets the r/m part of a ModR/M encoding as an extended 8-bit register index,
4626	* with REX.B added in.
4627	*
4628	* For use during decoding.
4629	*
4630	* @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
4631	*/
4632	#define IEM_GET_MODRM_RM_EX8(a_pVCpu, a_bRm) \
4633	( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
4634	\|\| !((a_bRm) & 4) /* IEM_GET_MODRM_RM(pVCpu, a_bRm) < 4 */ \
4635	? IEM_GET_MODRM_RM(pVCpu, a_bRm) : ((a_bRm) & 3) \| 16)
4636
4637	/**
4638	* Combines the prefix REX and ModR/M byte for passing to
4639	* iemOpHlpCalcRmEffAddrThreadedAddr64().
4640	*
4641	* @returns The ModRM byte but with bit 3 set to REX.B and bit 4 to REX.X.
4642	* The two bits are part of the REG sub-field, which isn't needed in
4643	* iemOpHlpCalcRmEffAddrThreadedAddr64().
4644	*
4645	* For use during decoding/recompiling.
4646	*/
4647	#define IEM_GET_MODRM_EX(a_pVCpu, a_bRm) \
4648	( ((a_bRm) & ~X86_MODRM_REG_MASK) \
4649	\| (uint8_t)( (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X)) >> (26 - 3) ) )
4650	AssertCompile(IEM_OP_PRF_REX_B == RT_BIT_32(26));
4651	AssertCompile(IEM_OP_PRF_REX_X == RT_BIT_32(27));
4652
4653	/**
4654	* Gets the effective VEX.VVVV value.
4655	*
4656	* The 4th bit is ignored if not 64-bit code.
4657	* @returns effective V-register value.
4658	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4659	*/
4660	#define IEM_GET_EFFECTIVE_VVVV(a_pVCpu) \
4661	(IEM_IS_64BIT_CODE(a_pVCpu) ? (a_pVCpu)->iem.s.uVex3rdReg : (a_pVCpu)->iem.s.uVex3rdReg & 7)
4662
4663
4664	/**
4665	* Checks if we're executing inside an AMD-V or VT-x guest.
4666	*/
4667	#if defined(VBOX_WITH_NESTED_HWVIRT_VMX) \|\| defined(VBOX_WITH_NESTED_HWVIRT_SVM)
4668	# define IEM_IS_IN_GUEST(a_pVCpu) RT_BOOL((a_pVCpu)->iem.s.fExec & IEM_F_X86_CTX_IN_GUEST)
4669	#else
4670	# define IEM_IS_IN_GUEST(a_pVCpu) false
4671	#endif
4672
4673
4674	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
4675
4676	/**
4677	* Check if the guest has entered VMX root operation.
4678	*/
4679	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxRootMode(IEM_GET_CTX(a_pVCpu)))
4680
4681	/**
4682	* Check if the guest has entered VMX non-root operation.
4683	*/
4684	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) ( ((a_pVCpu)->iem.s.fExec & (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST)) \
4685	== (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST) )
4686
4687	/**
4688	* Check if the nested-guest has the given Pin-based VM-execution control set.
4689	*/
4690	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_PinCtl) (CPUMIsGuestVmxPinCtlsSet(IEM_GET_CTX(a_pVCpu), (a_PinCtl)))
4691
4692	/**
4693	* Check if the nested-guest has the given Processor-based VM-execution control set.
4694	*/
4695	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_ProcCtl) (CPUMIsGuestVmxProcCtlsSet(IEM_GET_CTX(a_pVCpu), (a_ProcCtl)))
4696
4697	/**
4698	* Check if the nested-guest has the given Secondary Processor-based VM-execution
4699	* control set.
4700	*/
4701	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_ProcCtl2) (CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(a_pVCpu), (a_ProcCtl2)))
4702
4703	/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
4704	# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
4705
4706	/** Whether a shadow VMCS is present for the given VCPU. */
4707	# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
4708
4709	/** Gets the VMXON region pointer. */
4710	# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
4711
4712	/** Gets the guest-physical address of the current VMCS for the given VCPU. */
4713	# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
4714
4715	/** Whether a current VMCS is present for the given VCPU. */
4716	# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
4717
4718	/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
4719	# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
4720	do \
4721	{ \
4722	Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
4723	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
4724	} while (0)
4725
4726	/** Clears any current VMCS for the given VCPU. */
4727	# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
4728	do \
4729	{ \
4730	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
4731	} while (0)
4732
4733	/**
4734	* Invokes the VMX VM-exit handler for an instruction intercept.
4735	*/
4736	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) \
4737	do { return iemVmxVmexitInstr((a_pVCpu), (a_uExitReason), (a_cbInstr)); } while (0)
4738
4739	/**
4740	* Invokes the VMX VM-exit handler for an instruction intercept where the
4741	* instruction provides additional VM-exit information.
4742	*/
4743	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) \
4744	do { return iemVmxVmexitInstrNeedsInfo((a_pVCpu), (a_uExitReason), (a_uInstrId), (a_cbInstr)); } while (0)
4745
4746	/**
4747	* Invokes the VMX VM-exit handler for a task switch.
4748	*/
4749	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) \
4750	do { return iemVmxVmexitTaskSwitch((a_pVCpu), (a_enmTaskSwitch), (a_SelNewTss), (a_cbInstr)); } while (0)
4751
4752	/**
4753	* Invokes the VMX VM-exit handler for MWAIT.
4754	*/
4755	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) \
4756	do { return iemVmxVmexitInstrMwait((a_pVCpu), (a_fMonitorArmed), (a_cbInstr)); } while (0)
4757
4758	/**
4759	* Invokes the VMX VM-exit handler for EPT faults.
4760	*/
4761	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) \
4762	do { return iemVmxVmexitEpt(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr); } while (0)
4763
4764	/**
4765	* Invokes the VMX VM-exit handler.
4766	*/
4767	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) \
4768	do { return iemVmxVmexit((a_pVCpu), (a_uExitReason), (a_uExitQual)); } while (0)
4769
4770	#else
4771	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (false)
4772	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (false)
4773	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_cbInstr) (false)
4774	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_cbInstr) (false)
4775	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_cbInstr) (false)
4776	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4777	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4778	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4779	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4780	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
4781	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) do { return VERR_VMX_IPE_1; } while (0)
4782
4783	#endif
4784
4785	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4786	/**
4787	* Checks if we're executing a guest using AMD-V.
4788	*/
4789	# define IEM_SVM_IS_IN_GUEST(a_pVCpu) ( (a_pVCpu->iem.s.fExec & (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST)) \
4790	== (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST))
4791	/**
4792	* Check if an SVM control/instruction intercept is set.
4793	*/
4794	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) \
4795	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmCtrlInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_Intercept)))
4796
4797	/**
4798	* Check if an SVM read CRx intercept is set.
4799	*/
4800	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
4801	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
4802
4803	/**
4804	* Check if an SVM write CRx intercept is set.
4805	*/
4806	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
4807	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
4808
4809	/**
4810	* Check if an SVM read DRx intercept is set.
4811	*/
4812	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
4813	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
4814
4815	/**
4816	* Check if an SVM write DRx intercept is set.
4817	*/
4818	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
4819	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
4820
4821	/**
4822	* Check if an SVM exception intercept is set.
4823	*/
4824	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) \
4825	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmXcptInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uVector)))
4826
4827	/**
4828	* Invokes the SVM \#VMEXIT handler for the nested-guest.
4829	*/
4830	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
4831	do { return iemSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2)); } while (0)
4832
4833	/**
4834	* Invokes the 'MOV CRx' SVM \#VMEXIT handler after constructing the
4835	* corresponding decode assist information.
4836	*/
4837	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) \
4838	do \
4839	{ \
4840	uint64_t uExitInfo1; \
4841	if ( IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmDecodeAssists \
4842	&& (a_enmAccessCrX) == IEMACCESSCRX_MOV_CRX) \
4843	uExitInfo1 = SVM_EXIT1_MOV_CRX_MASK \| ((a_iGReg) & 7); \
4844	else \
4845	uExitInfo1 = 0; \
4846	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, uExitInfo1, 0); \
4847	} while (0)
4848
4849	/** Check and handles SVM nested-guest instruction intercept and updates
4850	* NRIP if needed.
4851	*/
4852	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
4853	do \
4854	{ \
4855	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept)) \
4856	{ \
4857	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
4858	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2); \
4859	} \
4860	} while (0)
4861
4862	/** Checks and handles SVM nested-guest CR0 read intercept. */
4863	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
4864	do \
4865	{ \
4866	if (!IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, 0)) \
4867	{ /* probably likely */ } \
4868	else \
4869	{ \
4870	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
4871	IEM_SVM_VMEXIT_RET(a_pVCpu, SVM_EXIT_READ_CR0, a_uExitInfo1, a_uExitInfo2); \
4872	} \
4873	} while (0)
4874
4875	/**
4876	* Updates the NextRIP (NRI) field in the nested-guest VMCB.
4877	*/
4878	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) \
4879	do { \
4880	if (IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmNextRipSave) \
4881	CPUMGuestSvmUpdateNRip(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_cbInstr)); \
4882	} while (0)
4883
4884	#else
4885	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) (false)
4886	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
4887	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
4888	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
4889	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
4890	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) (false)
4891	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { return VERR_SVM_IPE_1; } while (0)
4892	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) do { return VERR_SVM_IPE_1; } while (0)
4893	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, \
4894	a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
4895	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
4896	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) do { } while (0)
4897
4898	#endif
4899
4900	/** @} */
4901
4902	uint32_t iemCalcExecDbgFlagsSlow(PVMCPUCC pVCpu);
4903	VBOXSTRICTRC iemExecInjectPendingTrap(PVMCPUCC pVCpu);
4904
4905
4906	/**
4907	* Selector descriptor table entry as fetched by iemMemFetchSelDesc.
4908	*/
4909	typedef union IEMSELDESC
4910	{
4911	/** The legacy view. */
4912	X86DESC Legacy;
4913	/** The long mode view. */
4914	X86DESC64 Long;
4915	} IEMSELDESC;
4916	/** Pointer to a selector descriptor table entry. */
4917	typedef IEMSELDESC *PIEMSELDESC;
4918
4919	/** @name Raising Exceptions.
4920	* @{ */
4921	VBOXSTRICTRC iemTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, uint32_t uNextEip, uint32_t fFlags,
4922	uint16_t uErr, uint64_t uCr2, RTSEL SelTSS, PIEMSELDESC pNewDescTSS) RT_NOEXCEPT;
4923
4924	VBOXSTRICTRC iemRaiseXcptOrInt(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags,
4925	uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
4926	#ifdef IEM_WITH_SETJMP
4927	DECL_NO_RETURN(void) iemRaiseXcptOrIntJmp(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector,
4928	uint32_t fFlags, uint16_t uErr, uint64_t uCr2) IEM_NOEXCEPT_MAY_LONGJMP;
4929	#endif
4930	VBOXSTRICTRC iemRaiseDivideError(PVMCPUCC pVCpu) RT_NOEXCEPT;
4931	VBOXSTRICTRC iemRaiseDebugException(PVMCPUCC pVCpu) RT_NOEXCEPT;
4932	VBOXSTRICTRC iemRaiseBoundRangeExceeded(PVMCPUCC pVCpu) RT_NOEXCEPT;
4933	VBOXSTRICTRC iemRaiseUndefinedOpcode(PVMCPUCC pVCpu) RT_NOEXCEPT;
4934	VBOXSTRICTRC iemRaiseDeviceNotAvailable(PVMCPUCC pVCpu) RT_NOEXCEPT;
4935	VBOXSTRICTRC iemRaiseTaskSwitchFaultWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
4936	VBOXSTRICTRC iemRaiseTaskSwitchFaultCurrentTSS(PVMCPUCC pVCpu) RT_NOEXCEPT;
4937	VBOXSTRICTRC iemRaiseTaskSwitchFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
4938	VBOXSTRICTRC iemRaiseTaskSwitchFaultBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
4939	/VBOXSTRICTRC iemRaiseSelectorNotPresent(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;/
4940	VBOXSTRICTRC iemRaiseSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
4941	VBOXSTRICTRC iemRaiseSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
4942	VBOXSTRICTRC iemRaiseStackSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
4943	VBOXSTRICTRC iemRaiseStackSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
4944	VBOXSTRICTRC iemRaiseGeneralProtectionFault(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
4945	VBOXSTRICTRC iemRaiseGeneralProtectionFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
4946	#ifdef IEM_WITH_SETJMP
4947	DECL_NO_RETURN(void) iemRaiseGeneralProtectionFault0Jmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4948	#endif
4949	VBOXSTRICTRC iemRaiseGeneralProtectionFaultBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
4950	VBOXSTRICTRC iemRaiseNotCanonical(PVMCPUCC pVCpu) RT_NOEXCEPT;
4951	VBOXSTRICTRC iemRaiseSelectorBounds(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
4952	#ifdef IEM_WITH_SETJMP
4953	DECL_NO_RETURN(void) iemRaiseSelectorBoundsJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
4954	#endif
4955	VBOXSTRICTRC iemRaiseSelectorBoundsBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
4956	#ifdef IEM_WITH_SETJMP
4957	DECL_NO_RETURN(void) iemRaiseSelectorBoundsBySelectorJmp(PVMCPUCC pVCpu, RTSEL Sel) IEM_NOEXCEPT_MAY_LONGJMP;
4958	#endif
4959	VBOXSTRICTRC iemRaiseSelectorInvalidAccess(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
4960	#ifdef IEM_WITH_SETJMP
4961	DECL_NO_RETURN(void) iemRaiseSelectorInvalidAccessJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
4962	#endif
4963	VBOXSTRICTRC iemRaisePageFault(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) RT_NOEXCEPT;
4964	#ifdef IEM_WITH_SETJMP
4965	DECL_NO_RETURN(void) iemRaisePageFaultJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) IEM_NOEXCEPT_MAY_LONGJMP;
4966	#endif
4967	VBOXSTRICTRC iemRaiseMathFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
4968	VBOXSTRICTRC iemRaiseAlignmentCheckException(PVMCPUCC pVCpu) RT_NOEXCEPT;
4969	#ifdef IEM_WITH_SETJMP
4970	DECL_NO_RETURN(void) iemRaiseAlignmentCheckExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
4971	#endif
4972	VBOXSTRICTRC iemRaiseSimdFpException(PVMCPUCC pVCpu) RT_NOEXCEPT;
4973
4974	void iemLogSyscallProtModeInt(PVMCPUCC pVCpu, uint8_t u8Vector, uint8_t cbInstr);
4975
4976	IEM_CIMPL_DEF_0(iemCImplRaiseDivideError);
4977	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidLockPrefix);
4978	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidOpcode);
4979
4980	/**
4981	* Macro for calling iemCImplRaiseDivideError().
4982	*
4983	* This is for things that will _always_ decode to an \#DE, taking the
4984	* recompiler into consideration and everything.
4985	*
4986	* @return Strict VBox status code.
4987	*/
4988	#define IEMOP_RAISE_DIVIDE_ERROR_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseDivideError)
4989
4990	/**
4991	* Macro for calling iemCImplRaiseInvalidLockPrefix().
4992	*
4993	* This is for things that will _always_ decode to an \#UD, taking the
4994	* recompiler into consideration and everything.
4995	*
4996	* @return Strict VBox status code.
4997	*/
4998	#define IEMOP_RAISE_INVALID_LOCK_PREFIX_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidLockPrefix)
4999
5000	/**
5001	* Macro for calling iemCImplRaiseInvalidOpcode() for decode/static \#UDs.
5002	*
5003	* This is for things that will _always_ decode to an \#UD, taking the
5004	* recompiler into consideration and everything.
5005	*
5006	* @return Strict VBox status code.
5007	*/
5008	#define IEMOP_RAISE_INVALID_OPCODE_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidOpcode)
5009
5010	/**
5011	* Macro for calling iemCImplRaiseInvalidOpcode() for runtime-style \#UDs.
5012	*
5013	* Using this macro means you've got _buggy_ _code_ and are doing things that
5014	* belongs exclusively in IEMAllCImpl.cpp during decoding.
5015	*
5016	* @return Strict VBox status code.
5017	* @see IEMOP_RAISE_INVALID_OPCODE_RET
5018	*/
5019	#define IEMOP_RAISE_INVALID_OPCODE_RUNTIME_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidOpcode)
5020
5021	/** @} */
5022
5023	/** @name Register Access.
5024	* @{ */
5025	VBOXSTRICTRC iemRegRipRelativeJumpS8AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int8_t offNextInstr,
5026	IEMMODE enmEffOpSize) RT_NOEXCEPT;
5027	VBOXSTRICTRC iemRegRipRelativeJumpS16AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int16_t offNextInstr) RT_NOEXCEPT;
5028	VBOXSTRICTRC iemRegRipRelativeJumpS32AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int32_t offNextInstr,
5029	IEMMODE enmEffOpSize) RT_NOEXCEPT;
5030	/** @} */
5031
5032	/** @name FPU access and helpers.
5033	* @{ */
5034	void iemFpuPushResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
5035	void iemFpuPushResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5036	void iemFpuPushResultTwo(PVMCPUCC pVCpu, PIEMFPURESULTTWO pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
5037	void iemFpuStoreResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
5038	void iemFpuStoreResultThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
5039	void iemFpuStoreResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
5040	uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5041	void iemFpuStoreResultWithMemOpThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
5042	uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5043	void iemFpuUpdateOpcodeAndIp(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5044	void iemFpuUpdateFSW(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
5045	void iemFpuUpdateFSWThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
5046	void iemFpuUpdateFSWWithMemOp(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5047	void iemFpuUpdateFSWThenPopPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
5048	void iemFpuUpdateFSWWithMemOpThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5049	void iemFpuStackUnderflow(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
5050	void iemFpuStackUnderflowWithMemOp(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5051	void iemFpuStackUnderflowThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
5052	void iemFpuStackUnderflowWithMemOpThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5053	void iemFpuStackUnderflowThenPopPop(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5054	void iemFpuStackPushUnderflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5055	void iemFpuStackPushUnderflowTwo(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5056	void iemFpuStackPushOverflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5057	void iemFpuStackPushOverflowWithMemOp(PVMCPUCC pVCpu, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5058	/** @} */
5059
5060	/** @name SSE+AVX SIMD access and helpers.
5061	* @{ */
5062	void iemSseStoreResult(PVMCPUCC pVCpu, PCIEMSSERESULT pResult, uint8_t iXmmReg) RT_NOEXCEPT;
5063	void iemSseUpdateMxcsr(PVMCPUCC pVCpu, uint32_t fMxcsr) RT_NOEXCEPT;
5064	/** @} */
5065
5066	/** @name Memory access.
5067	* @{ */
5068
5069	/** Report a \#GP instead of \#AC and do not restrict to ring-3 */
5070	#define IEM_MEMMAP_F_ALIGN_GP RT_BIT_32(16)
5071	/** SSE access that should report a \#GP instead of \#AC, unless MXCSR.MM=1
5072	* when it works like normal \#AC. Always used with IEM_MEMMAP_F_ALIGN_GP. */
5073	#define IEM_MEMMAP_F_ALIGN_SSE RT_BIT_32(17)
5074	/** If \#AC is applicable, raise it. Always used with IEM_MEMMAP_F_ALIGN_GP.
5075	* Users include FXSAVE & FXRSTOR. */
5076	#define IEM_MEMMAP_F_ALIGN_GP_OR_AC RT_BIT_32(18)
5077
5078	VBOXSTRICTRC iemMemMap(PVMCPUCC pVCpu, void *ppvMem, uint8_t pbUnmapInfo, size_t cbMem, uint8_t iSegReg, RTGCPTR GCPtrMem,
5079	uint32_t fAccess, uint32_t uAlignCtl) RT_NOEXCEPT;
5080	VBOXSTRICTRC iemMemCommitAndUnmap(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5081	#ifndef IN_RING3
5082	VBOXSTRICTRC iemMemCommitAndUnmapPostponeTroubleToR3(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5083	#endif
5084	void iemMemRollbackAndUnmap(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5085	void iemMemRollback(PVMCPUCC pVCpu) RT_NOEXCEPT;
5086	VBOXSTRICTRC iemMemApplySegment(PVMCPUCC pVCpu, uint32_t fAccess, uint8_t iSegReg, size_t cbMem, PRTGCPTR pGCPtrMem) RT_NOEXCEPT;
5087	VBOXSTRICTRC iemMemMarkSelDescAccessed(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5088	VBOXSTRICTRC iemMemPageTranslateAndCheckAccess(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t cbAccess, uint32_t fAccess, PRTGCPHYS pGCPhysMem) RT_NOEXCEPT;
5089
5090	void iemOpcodeFlushLight(PVMCPUCC pVCpu, uint8_t cbInstr);
5091	void iemOpcodeFlushHeavy(PVMCPUCC pVCpu, uint8_t cbInstr);
5092	#ifdef IEM_WITH_CODE_TLB
5093	void iemOpcodeFetchBytesJmp(PVMCPUCC pVCpu, size_t cbDst, void *pvDst) IEM_NOEXCEPT_MAY_LONGJMP;
5094	#else
5095	VBOXSTRICTRC iemOpcodeFetchMoreBytes(PVMCPUCC pVCpu, size_t cbMin) RT_NOEXCEPT;
5096	#endif
5097	#ifdef IEM_WITH_SETJMP
5098	uint8_t iemOpcodeGetNextU8SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5099	uint16_t iemOpcodeGetNextU16SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5100	uint32_t iemOpcodeGetNextU32SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5101	uint64_t iemOpcodeGetNextU64SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5102	#else
5103	VBOXSTRICTRC iemOpcodeGetNextU8Slow(PVMCPUCC pVCpu, uint8_t *pb) RT_NOEXCEPT;
5104	VBOXSTRICTRC iemOpcodeGetNextS8SxU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
5105	VBOXSTRICTRC iemOpcodeGetNextS8SxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
5106	VBOXSTRICTRC iemOpcodeGetNextS8SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5107	VBOXSTRICTRC iemOpcodeGetNextU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
5108	VBOXSTRICTRC iemOpcodeGetNextU16ZxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
5109	VBOXSTRICTRC iemOpcodeGetNextU16ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5110	VBOXSTRICTRC iemOpcodeGetNextU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
5111	VBOXSTRICTRC iemOpcodeGetNextU32ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5112	VBOXSTRICTRC iemOpcodeGetNextS32SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5113	VBOXSTRICTRC iemOpcodeGetNextU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5114	#endif
5115
5116	VBOXSTRICTRC iemMemFetchDataU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5117	VBOXSTRICTRC iemMemFetchDataU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5118	VBOXSTRICTRC iemMemFetchDataU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5119	VBOXSTRICTRC iemMemFetchDataU32_ZX_U64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5120	VBOXSTRICTRC iemMemFetchDataU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5121	VBOXSTRICTRC iemMemFetchDataU64AlignedU128(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5122	VBOXSTRICTRC iemMemFetchDataR80(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5123	VBOXSTRICTRC iemMemFetchDataD80(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5124	VBOXSTRICTRC iemMemFetchDataU128(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5125	VBOXSTRICTRC iemMemFetchDataU128AlignedSse(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5126	VBOXSTRICTRC iemMemFetchDataU256(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5127	VBOXSTRICTRC iemMemFetchDataU256AlignedSse(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5128	VBOXSTRICTRC iemMemFetchDataXdtr(PVMCPUCC pVCpu, uint16_t *pcbLimit, PRTGCPTR pGCPtrBase, uint8_t iSegReg,
5129	RTGCPTR GCPtrMem, IEMMODE enmOpSize) RT_NOEXCEPT;
5130	#ifdef IEM_WITH_SETJMP
5131	uint8_t iemMemFetchDataU8SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5132	uint16_t iemMemFetchDataU16SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5133	uint32_t iemMemFetchDataU32SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5134	uint32_t iemMemFlatFetchDataU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5135	uint64_t iemMemFetchDataU64SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5136	uint64_t iemMemFetchDataU64AlignedU128SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5137	void iemMemFetchDataR80SafeJmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5138	void iemMemFetchDataD80SafeJmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5139	void iemMemFetchDataU128SafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5140	void iemMemFetchDataU128AlignedSseSafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5141	void iemMemFetchDataU256SafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5142	void iemMemFetchDataU256AlignedSseSafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5143	# if 0 /* these are inlined now */
5144	uint8_t iemMemFetchDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5145	uint16_t iemMemFetchDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5146	uint32_t iemMemFetchDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5147	uint32_t iemMemFlatFetchDataU32Jmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5148	uint64_t iemMemFetchDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5149	uint64_t iemMemFetchDataU64AlignedU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5150	void iemMemFetchDataR80Jmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5151	void iemMemFetchDataD80Jmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5152	void iemMemFetchDataU128Jmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5153	# endif
5154	void iemMemFetchDataU128AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5155	void iemMemFetchDataU256Jmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5156	void iemMemFetchDataU256AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5157	#endif
5158
5159	VBOXSTRICTRC iemMemFetchSysU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5160	VBOXSTRICTRC iemMemFetchSysU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5161	VBOXSTRICTRC iemMemFetchSysU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5162	VBOXSTRICTRC iemMemFetchSysU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5163	VBOXSTRICTRC iemMemFetchSelDesc(PVMCPUCC pVCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt) RT_NOEXCEPT;
5164
5165	VBOXSTRICTRC iemMemStoreDataU8(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) RT_NOEXCEPT;
5166	VBOXSTRICTRC iemMemStoreDataU16(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) RT_NOEXCEPT;
5167	VBOXSTRICTRC iemMemStoreDataU32(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) RT_NOEXCEPT;
5168	VBOXSTRICTRC iemMemStoreDataU64(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) RT_NOEXCEPT;
5169	VBOXSTRICTRC iemMemStoreDataU128(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
5170	VBOXSTRICTRC iemMemStoreDataU128AlignedSse(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
5171	VBOXSTRICTRC iemMemStoreDataU256(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
5172	VBOXSTRICTRC iemMemStoreDataU256AlignedAvx(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
5173	VBOXSTRICTRC iemMemStoreDataXdtr(PVMCPUCC pVCpu, uint16_t cbLimit, RTGCPTR GCPtrBase, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5174	#ifdef IEM_WITH_SETJMP
5175	void iemMemStoreDataU8SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
5176	void iemMemStoreDataU16SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
5177	void iemMemStoreDataU32SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
5178	void iemMemStoreDataU64SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
5179	void iemMemStoreDataU128SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5180	void iemMemStoreDataU128AlignedSseSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5181	void iemMemStoreDataU256SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5182	void iemMemStoreDataU256AlignedAvxSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5183	void iemMemStoreDataR80SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTFLOAT80U pr80Value) IEM_NOEXCEPT_MAY_LONGJMP;
5184	void iemMemStoreDataD80SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTPBCD80U pd80Value) IEM_NOEXCEPT_MAY_LONGJMP;
5185	#if 0
5186	void iemMemStoreDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
5187	void iemMemStoreDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
5188	void iemMemStoreDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
5189	void iemMemStoreDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
5190	void iemMemStoreDataU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5191	#endif
5192	void iemMemStoreDataU128AlignedSseJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5193	void iemMemStoreDataU256Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5194	void iemMemStoreDataU256AlignedAvxJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5195	#endif
5196
5197	#ifdef IEM_WITH_SETJMP
5198	uint8_t iemMemMapDataU8RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5199	uint8_t iemMemMapDataU8WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5200	uint8_t const iemMemMapDataU8RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5201	uint16_t iemMemMapDataU16RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5202	uint16_t iemMemMapDataU16WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5203	uint16_t const iemMemMapDataU16RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5204	uint32_t iemMemMapDataU32RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5205	uint32_t iemMemMapDataU32WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5206	uint32_t const iemMemMapDataU32RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5207	uint64_t iemMemMapDataU64RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5208	uint64_t iemMemMapDataU64WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5209	uint64_t const iemMemMapDataU64RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5210	PRTFLOAT80U iemMemMapDataR80RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5211	PRTFLOAT80U iemMemMapDataR80WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5212	PCRTFLOAT80U iemMemMapDataR80RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5213	PRTPBCD80U iemMemMapDataD80RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5214	PRTPBCD80U iemMemMapDataD80WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5215	PCRTPBCD80U iemMemMapDataD80RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5216	PRTUINT128U iemMemMapDataU128RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5217	PRTUINT128U iemMemMapDataU128WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5218	PCRTUINT128U iemMemMapDataU128RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5219
5220	void iemMemCommitAndUnmapJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5221	void iemMemCommitAndUnmapRwSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5222	void iemMemCommitAndUnmapWoSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5223	void iemMemCommitAndUnmapRoSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5224	void iemMemRollbackAndUnmapWoSafe(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5225	#endif
5226
5227	VBOXSTRICTRC iemMemStackPushBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
5228	void *ppvMem, uint8_t pbUnmapInfo, uint64_t *puNewRsp) RT_NOEXCEPT;
5229	VBOXSTRICTRC iemMemStackPushCommitSpecial(PVMCPUCC pVCpu, uint8_t bUnmapInfo, uint64_t uNewRsp) RT_NOEXCEPT;
5230	VBOXSTRICTRC iemMemStackPushU16(PVMCPUCC pVCpu, uint16_t u16Value) RT_NOEXCEPT;
5231	VBOXSTRICTRC iemMemStackPushU32(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
5232	VBOXSTRICTRC iemMemStackPushU64(PVMCPUCC pVCpu, uint64_t u64Value) RT_NOEXCEPT;
5233	VBOXSTRICTRC iemMemStackPushU16Ex(PVMCPUCC pVCpu, uint16_t u16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5234	VBOXSTRICTRC iemMemStackPushU32Ex(PVMCPUCC pVCpu, uint32_t u32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5235	VBOXSTRICTRC iemMemStackPushU64Ex(PVMCPUCC pVCpu, uint64_t u64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5236	VBOXSTRICTRC iemMemStackPushU32SReg(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
5237	VBOXSTRICTRC iemMemStackPopBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
5238	void const *ppvMem, uint8_t pbUnmapInfo, uint64_t *puNewRsp) RT_NOEXCEPT;
5239	VBOXSTRICTRC iemMemStackPopContinueSpecial(PVMCPUCC pVCpu, size_t off, size_t cbMem,
5240	void const *ppvMem, uint8_t pbUnmapInfo, uint64_t uCurNewRsp) RT_NOEXCEPT;
5241	VBOXSTRICTRC iemMemStackPopDoneSpecial(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5242	VBOXSTRICTRC iemMemStackPopU16(PVMCPUCC pVCpu, uint16_t *pu16Value) RT_NOEXCEPT;
5243	VBOXSTRICTRC iemMemStackPopU32(PVMCPUCC pVCpu, uint32_t *pu32Value) RT_NOEXCEPT;
5244	VBOXSTRICTRC iemMemStackPopU64(PVMCPUCC pVCpu, uint64_t *pu64Value) RT_NOEXCEPT;
5245	VBOXSTRICTRC iemMemStackPopU16Ex(PVMCPUCC pVCpu, uint16_t *pu16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5246	VBOXSTRICTRC iemMemStackPopU32Ex(PVMCPUCC pVCpu, uint32_t *pu32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5247	VBOXSTRICTRC iemMemStackPopU64Ex(PVMCPUCC pVCpu, uint64_t *pu64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5248
5249	#ifdef IEM_WITH_SETJMP
5250	void iemMemStackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5251	void iemMemStackPushU32SafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5252	void iemMemStackPushU32SRegSafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5253	void iemMemStackPushU64SafeJmp(PVMCPUCC pVCpu, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5254	void iemMemStackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5255	void iemMemStackPopGRegU32SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5256	void iemMemStackPopGRegU64SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5257
5258	void iemMemFlat32StackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5259	void iemMemFlat32StackPushU32SafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5260	void iemMemFlat32StackPushU32SRegSafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5261	void iemMemFlat32StackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5262	void iemMemFlat32StackPopGRegU32SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5263
5264	void iemMemFlat64StackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5265	void iemMemFlat64StackPushU64SafeJmp(PVMCPUCC pVCpu, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5266	void iemMemFlat64StackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5267	void iemMemFlat64StackPopGRegU64SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5268
5269	void iemMemStoreStackU16SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5270	void iemMemStoreStackU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5271	void iemMemStoreStackU32SRegSafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5272	void iemMemStoreStackU64SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5273
5274	uint16_t iemMemFetchStackU16SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5275	uint32_t iemMemFetchStackU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5276	uint64_t iemMemFetchStackU64SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5277
5278	#endif
5279
5280	/** @} */
5281
5282	/** @name IEMAllCImpl.cpp
5283	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/'
5284	* @{ */
5285	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem16, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5286	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem32, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5287	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem64, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5288	IEM_CIMPL_PROTO_0(iemCImpl_popa_16);
5289	IEM_CIMPL_PROTO_0(iemCImpl_popa_32);
5290	IEM_CIMPL_PROTO_0(iemCImpl_pusha_16);
5291	IEM_CIMPL_PROTO_0(iemCImpl_pusha_32);
5292	IEM_CIMPL_PROTO_1(iemCImpl_pushf, IEMMODE, enmEffOpSize);
5293	IEM_CIMPL_PROTO_1(iemCImpl_popf, IEMMODE, enmEffOpSize);
5294	IEM_CIMPL_PROTO_1(iemCImpl_call_16, uint16_t, uNewPC);
5295	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_16, int16_t, offDisp);
5296	IEM_CIMPL_PROTO_1(iemCImpl_call_32, uint32_t, uNewPC);
5297	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_32, int32_t, offDisp);
5298	IEM_CIMPL_PROTO_1(iemCImpl_call_64, uint64_t, uNewPC);
5299	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_64, int64_t, offDisp);
5300	IEM_CIMPL_PROTO_3(iemCImpl_FarJmp, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
5301	IEM_CIMPL_PROTO_3(iemCImpl_callf, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
5302	typedef IEM_CIMPL_DECL_TYPE_3(FNIEMCIMPLFARBRANCH, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
5303	typedef FNIEMCIMPLFARBRANCH *PFNIEMCIMPLFARBRANCH;
5304	IEM_CIMPL_PROTO_2(iemCImpl_retf, IEMMODE, enmEffOpSize, uint16_t, cbPop);
5305	IEM_CIMPL_PROTO_0(iemCImpl_retn_16);
5306	IEM_CIMPL_PROTO_0(iemCImpl_retn_32);
5307	IEM_CIMPL_PROTO_0(iemCImpl_retn_64);
5308	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_16, uint16_t, cbPop);
5309	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_32, uint16_t, cbPop);
5310	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_64, uint16_t, cbPop);
5311	IEM_CIMPL_PROTO_3(iemCImpl_enter, IEMMODE, enmEffOpSize, uint16_t, cbFrame, uint8_t, cParameters);
5312	IEM_CIMPL_PROTO_1(iemCImpl_leave, IEMMODE, enmEffOpSize);
5313	IEM_CIMPL_PROTO_2(iemCImpl_int, uint8_t, u8Int, IEMINT, enmInt);
5314	IEM_CIMPL_PROTO_1(iemCImpl_iret_real_v8086, IEMMODE, enmEffOpSize);
5315	IEM_CIMPL_PROTO_4(iemCImpl_iret_prot_v8086, uint32_t, uNewEip, uint16_t, uNewCs, uint32_t, uNewFlags, uint64_t, uNewRsp);
5316	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot_NestedTask, IEMMODE, enmEffOpSize);
5317	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot, IEMMODE, enmEffOpSize);
5318	IEM_CIMPL_PROTO_1(iemCImpl_iret_64bit, IEMMODE, enmEffOpSize);
5319	IEM_CIMPL_PROTO_1(iemCImpl_iret, IEMMODE, enmEffOpSize);
5320	IEM_CIMPL_PROTO_0(iemCImpl_loadall286);
5321	IEM_CIMPL_PROTO_0(iemCImpl_syscall);
5322	IEM_CIMPL_PROTO_1(iemCImpl_sysret, IEMMODE, enmEffOpSize);
5323	IEM_CIMPL_PROTO_0(iemCImpl_sysenter);
5324	IEM_CIMPL_PROTO_1(iemCImpl_sysexit, IEMMODE, enmEffOpSize);
5325	IEM_CIMPL_PROTO_2(iemCImpl_LoadSReg, uint8_t, iSegReg, uint16_t, uSel);
5326	IEM_CIMPL_PROTO_2(iemCImpl_load_SReg, uint8_t, iSegReg, uint16_t, uSel);
5327	IEM_CIMPL_PROTO_2(iemCImpl_pop_Sreg, uint8_t, iSegReg, IEMMODE, enmEffOpSize);
5328	IEM_CIMPL_PROTO_5(iemCImpl_load_SReg_Greg, uint16_t, uSel, uint64_t, offSeg, uint8_t, iSegReg, uint8_t, iGReg, IEMMODE, enmEffOpSize);
5329	IEM_CIMPL_PROTO_2(iemCImpl_VerX, uint16_t, uSel, bool, fWrite);
5330	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u64, uint64_t *, pu64Dst, uint16_t, uSel, bool, fIsLar);
5331	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u16, uint16_t *, pu16Dst, uint16_t, uSel, bool, fIsLar);
5332	IEM_CIMPL_PROTO_3(iemCImpl_lgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
5333	IEM_CIMPL_PROTO_2(iemCImpl_sgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5334	IEM_CIMPL_PROTO_3(iemCImpl_lidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
5335	IEM_CIMPL_PROTO_2(iemCImpl_sidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5336	IEM_CIMPL_PROTO_1(iemCImpl_lldt, uint16_t, uNewLdt);
5337	IEM_CIMPL_PROTO_2(iemCImpl_sldt_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
5338	IEM_CIMPL_PROTO_2(iemCImpl_sldt_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5339	IEM_CIMPL_PROTO_1(iemCImpl_ltr, uint16_t, uNewTr);
5340	IEM_CIMPL_PROTO_2(iemCImpl_str_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
5341	IEM_CIMPL_PROTO_2(iemCImpl_str_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5342	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Cd, uint8_t, iGReg, uint8_t, iCrReg);
5343	IEM_CIMPL_PROTO_2(iemCImpl_smsw_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
5344	IEM_CIMPL_PROTO_2(iemCImpl_smsw_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5345	IEM_CIMPL_PROTO_4(iemCImpl_load_CrX, uint8_t, iCrReg, uint64_t, uNewCrX, IEMACCESSCRX, enmAccessCrX, uint8_t, iGReg);
5346	IEM_CIMPL_PROTO_2(iemCImpl_mov_Cd_Rd, uint8_t, iCrReg, uint8_t, iGReg);
5347	IEM_CIMPL_PROTO_2(iemCImpl_lmsw, uint16_t, u16NewMsw, RTGCPTR, GCPtrEffDst);
5348	IEM_CIMPL_PROTO_0(iemCImpl_clts);
5349	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Dd, uint8_t, iGReg, uint8_t, iDrReg);
5350	IEM_CIMPL_PROTO_2(iemCImpl_mov_Dd_Rd, uint8_t, iDrReg, uint8_t, iGReg);
5351	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Td, uint8_t, iGReg, uint8_t, iTrReg);
5352	IEM_CIMPL_PROTO_2(iemCImpl_mov_Td_Rd, uint8_t, iTrReg, uint8_t, iGReg);
5353	IEM_CIMPL_PROTO_1(iemCImpl_invlpg, RTGCPTR, GCPtrPage);
5354	IEM_CIMPL_PROTO_3(iemCImpl_invpcid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvpcidDesc, uint64_t, uInvpcidType);
5355	IEM_CIMPL_PROTO_0(iemCImpl_invd);
5356	IEM_CIMPL_PROTO_0(iemCImpl_wbinvd);
5357	IEM_CIMPL_PROTO_0(iemCImpl_rsm);
5358	IEM_CIMPL_PROTO_0(iemCImpl_rdtsc);
5359	IEM_CIMPL_PROTO_0(iemCImpl_rdtscp);
5360	IEM_CIMPL_PROTO_0(iemCImpl_rdpmc);
5361	IEM_CIMPL_PROTO_0(iemCImpl_rdmsr);
5362	IEM_CIMPL_PROTO_0(iemCImpl_wrmsr);
5363	IEM_CIMPL_PROTO_3(iemCImpl_in, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
5364	IEM_CIMPL_PROTO_2(iemCImpl_in_eAX_DX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
5365	IEM_CIMPL_PROTO_3(iemCImpl_out, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
5366	IEM_CIMPL_PROTO_2(iemCImpl_out_DX_eAX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
5367	IEM_CIMPL_PROTO_0(iemCImpl_cli);
5368	IEM_CIMPL_PROTO_0(iemCImpl_sti);
5369	IEM_CIMPL_PROTO_0(iemCImpl_hlt);
5370	IEM_CIMPL_PROTO_1(iemCImpl_monitor, uint8_t, iEffSeg);
5371	IEM_CIMPL_PROTO_0(iemCImpl_mwait);
5372	IEM_CIMPL_PROTO_0(iemCImpl_swapgs);
5373	IEM_CIMPL_PROTO_0(iemCImpl_cpuid);
5374	IEM_CIMPL_PROTO_1(iemCImpl_aad, uint8_t, bImm);
5375	IEM_CIMPL_PROTO_1(iemCImpl_aam, uint8_t, bImm);
5376	IEM_CIMPL_PROTO_0(iemCImpl_daa);
5377	IEM_CIMPL_PROTO_0(iemCImpl_das);
5378	IEM_CIMPL_PROTO_0(iemCImpl_aaa);
5379	IEM_CIMPL_PROTO_0(iemCImpl_aas);
5380	IEM_CIMPL_PROTO_3(iemCImpl_bound_16, int16_t, idxArray, int16_t, idxLowerBound, int16_t, idxUpperBound);
5381	IEM_CIMPL_PROTO_3(iemCImpl_bound_32, int32_t, idxArray, int32_t, idxLowerBound, int32_t, idxUpperBound);
5382	IEM_CIMPL_PROTO_0(iemCImpl_xgetbv);
5383	IEM_CIMPL_PROTO_0(iemCImpl_xsetbv);
5384	IEM_CIMPL_PROTO_5(iemCImpl_cmpxchg16b_fallback_rendezvous, PRTUINT128U, pu128Dst, PRTUINT128U, pu128RaxRdx,
5385	PRTUINT128U, pu128RbxRcx, uint32_t *, pEFlags, uint8_t, bUnmapInfo);
5386	IEM_CIMPL_PROTO_2(iemCImpl_clflush_clflushopt, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5387	IEM_CIMPL_PROTO_1(iemCImpl_finit, bool, fCheckXcpts);
5388	IEM_CIMPL_PROTO_3(iemCImpl_fxsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5389	IEM_CIMPL_PROTO_3(iemCImpl_fxrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5390	IEM_CIMPL_PROTO_3(iemCImpl_xsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5391	IEM_CIMPL_PROTO_3(iemCImpl_xrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5392	IEM_CIMPL_PROTO_2(iemCImpl_stmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5393	IEM_CIMPL_PROTO_2(iemCImpl_vstmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5394	IEM_CIMPL_PROTO_2(iemCImpl_ldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5395	IEM_CIMPL_PROTO_3(iemCImpl_fnstenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5396	IEM_CIMPL_PROTO_3(iemCImpl_fnsave, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5397	IEM_CIMPL_PROTO_3(iemCImpl_fldenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
5398	IEM_CIMPL_PROTO_3(iemCImpl_frstor, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
5399	IEM_CIMPL_PROTO_1(iemCImpl_fldcw, uint16_t, u16Fcw);
5400	IEM_CIMPL_PROTO_2(iemCImpl_fxch_underflow, uint8_t, iStReg, uint16_t, uFpuOpcode);
5401	IEM_CIMPL_PROTO_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, bool, fUCmp, uint32_t, uPopAndFpuOpcode);
5402	IEM_CIMPL_PROTO_2(iemCImpl_rdseed, uint8_t, iReg, IEMMODE, enmEffOpSize);
5403	IEM_CIMPL_PROTO_2(iemCImpl_rdrand, uint8_t, iReg, IEMMODE, enmEffOpSize);
5404	/** @} */
5405
5406	/** @name IEMAllCImplStrInstr.cpp.h
5407	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/' -e 's/RT_CONCAT4(//' \
5408	* -e 's/,ADDR_SIZE)/64/g' -e 's/,OP_SIZE,/64/g' -e 's/,OP_rAX,/rax/g' IEMAllCImplStrInstr.cpp.h
5409	* @{ */
5410	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr16, uint8_t, iEffSeg);
5411	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr16, uint8_t, iEffSeg);
5412	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m16);
5413	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m16);
5414	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr16, uint8_t, iEffSeg);
5415	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m16);
5416	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m16, int8_t, iEffSeg);
5417	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr16, bool, fIoChecked);
5418	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr16, bool, fIoChecked);
5419	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5420	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5421
5422	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr16, uint8_t, iEffSeg);
5423	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr16, uint8_t, iEffSeg);
5424	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m16);
5425	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m16);
5426	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr16, uint8_t, iEffSeg);
5427	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m16);
5428	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m16, int8_t, iEffSeg);
5429	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr16, bool, fIoChecked);
5430	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr16, bool, fIoChecked);
5431	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5432	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5433
5434	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr16, uint8_t, iEffSeg);
5435	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr16, uint8_t, iEffSeg);
5436	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m16);
5437	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m16);
5438	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr16, uint8_t, iEffSeg);
5439	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m16);
5440	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m16, int8_t, iEffSeg);
5441	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr16, bool, fIoChecked);
5442	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr16, bool, fIoChecked);
5443	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5444	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5445
5446
5447	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr32, uint8_t, iEffSeg);
5448	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr32, uint8_t, iEffSeg);
5449	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m32);
5450	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m32);
5451	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr32, uint8_t, iEffSeg);
5452	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m32);
5453	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m32, int8_t, iEffSeg);
5454	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr32, bool, fIoChecked);
5455	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr32, bool, fIoChecked);
5456	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5457	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5458
5459	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr32, uint8_t, iEffSeg);
5460	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr32, uint8_t, iEffSeg);
5461	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m32);
5462	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m32);
5463	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr32, uint8_t, iEffSeg);
5464	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m32);
5465	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m32, int8_t, iEffSeg);
5466	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr32, bool, fIoChecked);
5467	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr32, bool, fIoChecked);
5468	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5469	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5470
5471	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr32, uint8_t, iEffSeg);
5472	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr32, uint8_t, iEffSeg);
5473	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m32);
5474	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m32);
5475	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr32, uint8_t, iEffSeg);
5476	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m32);
5477	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m32, int8_t, iEffSeg);
5478	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr32, bool, fIoChecked);
5479	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr32, bool, fIoChecked);
5480	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5481	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5482
5483	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr32, uint8_t, iEffSeg);
5484	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr32, uint8_t, iEffSeg);
5485	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m32);
5486	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m32);
5487	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr32, uint8_t, iEffSeg);
5488	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m32);
5489	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m32, int8_t, iEffSeg);
5490	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr32, bool, fIoChecked);
5491	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr32, bool, fIoChecked);
5492	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5493	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5494
5495
5496	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr64, uint8_t, iEffSeg);
5497	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr64, uint8_t, iEffSeg);
5498	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m64);
5499	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m64);
5500	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr64, uint8_t, iEffSeg);
5501	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m64);
5502	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m64, int8_t, iEffSeg);
5503	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr64, bool, fIoChecked);
5504	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr64, bool, fIoChecked);
5505	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5506	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5507
5508	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr64, uint8_t, iEffSeg);
5509	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr64, uint8_t, iEffSeg);
5510	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m64);
5511	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m64);
5512	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr64, uint8_t, iEffSeg);
5513	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m64);
5514	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m64, int8_t, iEffSeg);
5515	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr64, bool, fIoChecked);
5516	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr64, bool, fIoChecked);
5517	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5518	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5519
5520	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr64, uint8_t, iEffSeg);
5521	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr64, uint8_t, iEffSeg);
5522	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m64);
5523	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m64);
5524	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr64, uint8_t, iEffSeg);
5525	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m64);
5526	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m64, int8_t, iEffSeg);
5527	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr64, bool, fIoChecked);
5528	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr64, bool, fIoChecked);
5529	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5530	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5531
5532	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr64, uint8_t, iEffSeg);
5533	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr64, uint8_t, iEffSeg);
5534	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m64);
5535	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m64);
5536	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr64, uint8_t, iEffSeg);
5537	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m64);
5538	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m64, int8_t, iEffSeg);
5539	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr64, bool, fIoChecked);
5540	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr64, bool, fIoChecked);
5541	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5542	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5543	/** @} */
5544
5545	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5546	VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT;
5547	VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT;
5548	VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT;
5549	VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT;
5550	VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT;
5551	VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
5552	VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALK pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT;
5553	VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT;
5554	VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT;
5555	VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
5556	bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT;
5557	VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
5558	bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT;
5559	VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5560	VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5561	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5562	VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5563	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5564	VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5565	VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT;
5566	VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
5567	RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT;
5568	VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT;
5569	VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT;
5570	VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT;
5571	uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT;
5572	void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT;
5573	VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
5574	uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT;
5575	bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT;
5576	IEM_CIMPL_PROTO_0(iemCImpl_vmxoff);
5577	IEM_CIMPL_PROTO_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon);
5578	IEM_CIMPL_PROTO_0(iemCImpl_vmlaunch);
5579	IEM_CIMPL_PROTO_0(iemCImpl_vmresume);
5580	IEM_CIMPL_PROTO_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
5581	IEM_CIMPL_PROTO_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
5582	IEM_CIMPL_PROTO_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
5583	IEM_CIMPL_PROTO_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField);
5584	IEM_CIMPL_PROTO_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField);
5585	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField);
5586	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg32, uint64_t *, pu32Dst, uint32_t, u32VmcsField);
5587	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField);
5588	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField);
5589	IEM_CIMPL_PROTO_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType);
5590	IEM_CIMPL_PROTO_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType);
5591	IEM_CIMPL_PROTO_0(iemCImpl_vmx_pause);
5592	#endif
5593
5594	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5595	VBOXSTRICTRC iemSvmVmexit(PVMCPUCC pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2) RT_NOEXCEPT;
5596	VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr, uint64_t uCr2) RT_NOEXCEPT;
5597	VBOXSTRICTRC iemSvmHandleIOIntercept(PVMCPUCC pVCpu, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
5598	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, uint8_t cbInstr) RT_NOEXCEPT;
5599	VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPUCC pVCpu, uint32_t idMsr, bool fWrite, uint8_t cbInstr) RT_NOEXCEPT;
5600	IEM_CIMPL_PROTO_0(iemCImpl_vmrun);
5601	IEM_CIMPL_PROTO_0(iemCImpl_vmload);
5602	IEM_CIMPL_PROTO_0(iemCImpl_vmsave);
5603	IEM_CIMPL_PROTO_0(iemCImpl_clgi);
5604	IEM_CIMPL_PROTO_0(iemCImpl_stgi);
5605	IEM_CIMPL_PROTO_0(iemCImpl_invlpga);
5606	IEM_CIMPL_PROTO_0(iemCImpl_skinit);
5607	IEM_CIMPL_PROTO_0(iemCImpl_svm_pause);
5608	#endif
5609
5610	IEM_CIMPL_PROTO_0(iemCImpl_vmcall); /* vmx */
5611	IEM_CIMPL_PROTO_0(iemCImpl_vmmcall); /* svm */
5612	IEM_CIMPL_PROTO_1(iemCImpl_Hypercall, uint16_t, uDisOpcode); /* both */
5613
5614	extern const PFNIEMOP g_apfnIemInterpretOnlyOneByteMap[256];
5615	extern const PFNIEMOP g_apfnIemInterpretOnlyTwoByteMap[1024];
5616	extern const PFNIEMOP g_apfnIemInterpretOnlyThreeByte0f3a[1024];
5617	extern const PFNIEMOP g_apfnIemInterpretOnlyThreeByte0f38[1024];
5618	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap1[1024];
5619	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap2[1024];
5620	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap3[1024];
5621
5622	/*
5623	* Recompiler related stuff.
5624	*/
5625	extern const PFNIEMOP g_apfnIemThreadedRecompilerOneByteMap[256];
5626	extern const PFNIEMOP g_apfnIemThreadedRecompilerTwoByteMap[1024];
5627	extern const PFNIEMOP g_apfnIemThreadedRecompilerThreeByte0f3a[1024];
5628	extern const PFNIEMOP g_apfnIemThreadedRecompilerThreeByte0f38[1024];
5629	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap1[1024];
5630	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap2[1024];
5631	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap3[1024];
5632
5633	DECLCALLBACK(int) iemTbInit(PVMCC pVM, uint32_t cInitialTbs, uint32_t cMaxTbs,
5634	uint64_t cbInitialExec, uint64_t cbMaxExec, uint32_t cbChunkExec);
5635	void iemThreadedTbObsolete(PVMCPUCC pVCpu, PIEMTB pTb, bool fSafeToFree);
5636	void iemTbAllocatorProcessDelayedFrees(PVMCPUCC pVCpu, PIEMTBALLOCATOR pTbAllocator);
5637	void iemTbAllocatorFreeupNativeSpace(PVMCPUCC pVCpu, uint32_t cNeededInstrs);
5638
5639
5640	/** @todo FNIEMTHREADEDFUNC and friends may need more work... */
5641	#if defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
5642	typedef VBOXSTRICTRC /__attribute__((__nothrow__))/ FNIEMTHREADEDFUNC(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
5643	typedef FNIEMTHREADEDFUNC *PFNIEMTHREADEDFUNC;
5644	# define IEM_DECL_IEMTHREADEDFUNC_DEF(a_Name) \
5645	VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2)
5646	# define IEM_DECL_IEMTHREADEDFUNC_PROTO(a_Name) \
5647	VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2)
5648
5649	#else
5650	typedef VBOXSTRICTRC (FNIEMTHREADEDFUNC)(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
5651	typedef FNIEMTHREADEDFUNC *PFNIEMTHREADEDFUNC;
5652	# define IEM_DECL_IEMTHREADEDFUNC_DEF(a_Name) \
5653	VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2) IEM_NOEXCEPT_MAY_LONGJMP
5654	# define IEM_DECL_IEMTHREADEDFUNC_PROTO(a_Name) \
5655	VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2) IEM_NOEXCEPT_MAY_LONGJMP
5656	#endif
5657
5658
5659	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_Nop);
5660	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_LogCpuState);
5661
5662	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_DeferToCImpl0);
5663
5664	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckIrq);
5665	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckMode);
5666	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckHwInstrBps);
5667	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLim);
5668
5669	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodes);
5670	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodes);
5671	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesConsiderCsLim);
5672
5673	/* Branching: */
5674	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndPcAndOpcodes);
5675	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckPcAndOpcodes);
5676	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckPcAndOpcodesConsiderCsLim);
5677
5678	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesLoadingTlb);
5679	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesLoadingTlb);
5680	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesLoadingTlbConsiderCsLim);
5681
5682	/* Natural page crossing: */
5683	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesAcrossPageLoadingTlb);
5684	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesAcrossPageLoadingTlb);
5685	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesAcrossPageLoadingTlbConsiderCsLim);
5686
5687	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesOnNextPageLoadingTlb);
5688	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNextPageLoadingTlb);
5689	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNextPageLoadingTlbConsiderCsLim);
5690
5691	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesOnNewPageLoadingTlb);
5692	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNewPageLoadingTlb);
5693	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNewPageLoadingTlbConsiderCsLim);
5694
5695	bool iemThreadedCompileEmitIrqCheckBefore(PVMCPUCC pVCpu, PIEMTB pTb);
5696	bool iemThreadedCompileBeginEmitCallsComplications(PVMCPUCC pVCpu, PIEMTB pTb);
5697
5698	/* Native recompiler public bits: */
5699	DECLHIDDEN(PIEMTB) iemNativeRecompile(PVMCPUCC pVCpu, PIEMTB pTb) RT_NOEXCEPT;
5700	DECLHIDDEN(void) iemNativeDisassembleTb(PCIEMTB pTb, PCDBGFINFOHLP pHlp) RT_NOEXCEPT;
5701	int iemExecMemAllocatorInit(PVMCPU pVCpu, uint64_t cbMax, uint64_t cbInitial, uint32_t cbChunk);
5702	void iemExecMemAllocatorFree(PVMCPU pVCpu, void *pv, size_t cb);
5703
5704
5705	/** @} */
5706
5707	RT_C_DECLS_END
5708
5709	#endif /* !VMM_INCLUDED_SRC_include_IEMInternal_h */
5710

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source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h@ 102817

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