IEMInternal.h@ 104019

Last change on this file since 104019 was 104019, checked in by vboxsync, 11 months ago
VMM/IEM: Made IEM_MC_CALL_AVX_AIMPL_[34] deal with its hidden parameter the same way as the FPU, MMX and SSE AIMPL calls. Made IEM_MC_BEGIN_EX get a parameter count including hidden paramenters, saving a call to iemNativeArgGetHiddenArgCount for every block. The count is only used by iemNativeVarRegisterAcquire. bugref:10370 bugref:10614
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 313.3 KB

Line
1	/* $Id: IEMInternal.h 104019 2024-03-24 01:07:36Z vboxsync $ */
2	/** @file
3	* IEM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2011-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_IEMInternal_h
29	#define VMM_INCLUDED_SRC_include_IEMInternal_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#include <VBox/vmm/cpum.h>
35	#include <VBox/vmm/iem.h>
36	#include <VBox/vmm/pgm.h>
37	#include <VBox/vmm/stam.h>
38	#include <VBox/param.h>
39
40	#include <iprt/setjmp-without-sigmask.h>
41	#include <iprt/list.h>
42
43
44	RT_C_DECLS_BEGIN
45
46
47	/** @defgroup grp_iem_int Internals
48	* @ingroup grp_iem
49	* @internal
50	* @{
51	*/
52
53	/** For expanding symbol in slickedit and other products tagging and
54	* crossreferencing IEM symbols. */
55	#ifndef IEM_STATIC
56	# define IEM_STATIC static
57	#endif
58
59	/** @def IEM_WITH_SETJMP
60	* Enables alternative status code handling using setjmps.
61	*
62	* This adds a bit of expense via the setjmp() call since it saves all the
63	* non-volatile registers. However, it eliminates return code checks and allows
64	* for more optimal return value passing (return regs instead of stack buffer).
65	*/
66	#if defined(DOXYGEN_RUNNING) \|\| defined(RT_OS_WINDOWS) \|\| 1
67	# define IEM_WITH_SETJMP
68	#endif
69
70	/** @def IEM_WITH_THROW_CATCH
71	* Enables using C++ throw/catch as an alternative to setjmp/longjmp in user
72	* mode code when IEM_WITH_SETJMP is in effect.
73	*
74	* With GCC 11.3.1 and code TLB on linux, using throw/catch instead of
75	* setjmp/long resulted in bs2-test-1 running 3.00% faster and all but on test
76	* result value improving by more than 1%. (Best out of three.)
77	*
78	* With Visual C++ 2019 and code TLB on windows, using throw/catch instead of
79	* setjmp/long resulted in bs2-test-1 running 3.68% faster and all but some of
80	* the MMIO and CPUID tests ran noticeably faster. Variation is greater than on
81	* Linux, but it should be quite a bit faster for normal code.
82	*/
83	#if (defined(__cplusplus) && defined(IEM_WITH_SETJMP) && defined(IN_RING3) && (defined(__GNUC__) \|\| defined(_MSC_VER))) \
84	\|\| defined(DOXYGEN_RUNNING)
85	# define IEM_WITH_THROW_CATCH
86	#endif
87
88	/** @def IEMNATIVE_WITH_DELAYED_PC_UPDATING
89	* Enables the delayed PC updating optimization (see @bugref{10373}).
90	*/
91	#if defined(DOXYGEN_RUNNING) \|\| 1
92	# define IEMNATIVE_WITH_DELAYED_PC_UPDATING
93	#endif
94
95	/** Enables the SIMD register allocator @bugref{10614}. */
96	#if defined(DOXYGEN_RUNNING) \|\| 1
97	# define IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
98	#endif
99	/** Enables access to even callee saved registers. */
100	//# define IEMNATIVE_WITH_SIMD_REG_ACCESS_ALL_REGISTERS
101
102	/** @def VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
103	* Enables a quicker alternative to throw/longjmp for IEM_DO_LONGJMP when
104	* executing native translation blocks.
105	*
106	* This exploits the fact that we save all non-volatile registers in the TB
107	* prologue and thus just need to do the same as the TB epilogue to get the
108	* effect of a longjmp/throw. Since MSC marks XMM6 thru XMM15 as
109	* non-volatile (and does something even more crazy for ARM), this probably
110	* won't work reliably on Windows. */
111	#if defined(DOXYGEN_RUNNING) \|\| (!defined(RT_OS_WINDOWS) && (defined(RT_ARCH_ARM64) /\|\| defined(_RT_ARCH_AMD64)/))
112	# define VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
113	#endif
114	#ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
115	# if !defined(IN_RING3) \
116	\|\| !defined(VBOX_WITH_IEM_RECOMPILER) \
117	\|\| !defined(VBOX_WITH_IEM_NATIVE_RECOMPILER)
118	# undef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
119	# elif defined(RT_OS_WINDOWS)
120	# pragma message("VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP is not safe to use on windows")
121	# endif
122	#endif
123
124
125	/** @def IEM_DO_LONGJMP
126	*
127	* Wrapper around longjmp / throw.
128	*
129	* @param a_pVCpu The CPU handle.
130	* @param a_rc The status code jump back with / throw.
131	*/
132	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
133	# ifdef IEM_WITH_THROW_CATCH
134	# ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
135	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) do { \
136	if ((a_pVCpu)->iem.s.pvTbFramePointerR3) \
137	iemNativeTbLongJmp((a_pVCpu)->iem.s.pvTbFramePointerR3, (a_rc)); \
138	throw int(a_rc); \
139	} while (0)
140	# else
141	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) throw int(a_rc)
142	# endif
143	# else
144	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) longjmp(*(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf), (a_rc))
145	# endif
146	#endif
147
148	/** For use with IEM function that may do a longjmp (when enabled).
149	*
150	* Visual C++ has trouble longjmp'ing from/over functions with the noexcept
151	* attribute. So, we indicate that function that may be part of a longjmp may
152	* throw "exceptions" and that the compiler should definitely not generate and
153	* std::terminate calling unwind code.
154	*
155	* Here is one example of this ending in std::terminate:
156	* @code{.txt}
157	00 00000041`cadfda10 00007ffc`5d5a1f9f ucrtbase!abort+0x4e
158	01 00000041`cadfda40 00007ffc`57af229a ucrtbase!terminate+0x1f
159	02 00000041`cadfda70 00007ffb`eec91030 VCRUNTIME140!__std_terminate+0xa [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\ehhelpers.cpp @ 192]
160	03 00000041`cadfdaa0 00007ffb`eec92c6d VCRUNTIME140_1!_CallSettingFrame+0x20 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\handlers.asm @ 50]
161	04 00000041`cadfdad0 00007ffb`eec93ae5 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToState+0x241 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 1085]
162	05 00000041`cadfdc00 00007ffb`eec92258 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToEmptyState+0x2d [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 218]
163	06 00000041`cadfdc30 00007ffb`eec940e9 VCRUNTIME140_1!__InternalCxxFrameHandler<__FrameHandler4>+0x194 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 304]
164	07 00000041`cadfdcd0 00007ffc`5f9f249f VCRUNTIME140_1!__CxxFrameHandler4+0xa9 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 290]
165	08 00000041`cadfdd40 00007ffc`5f980939 ntdll!RtlpExecuteHandlerForUnwind+0xf
166	09 00000041`cadfdd70 00007ffc`5f9a0edd ntdll!RtlUnwindEx+0x339
167	0a 00000041`cadfe490 00007ffc`57aff976 ntdll!RtlUnwind+0xcd
168	0b 00000041`cadfea00 00007ffb`e1b5de01 VCRUNTIME140!__longjmp_internal+0xe6 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\longjmp.asm @ 140]
169	0c (Inline Function) --------`-------- VBoxVMM!iemOpcodeGetNextU8SlowJmp+0x95 [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 1155]
170	0d 00000041`cadfea50 00007ffb`e1b60f6b VBoxVMM!iemOpcodeGetNextU8Jmp+0xc1 [L:\vbox-intern\src\VBox\VMM\include\IEMInline.h @ 402]
171	0e 00000041`cadfea90 00007ffb`e1cc6201 VBoxVMM!IEMExecForExits+0xdb [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 10185]
172	0f 00000041`cadfec70 00007ffb`e1d0df8d VBoxVMM!EMHistoryExec+0x4f1 [L:\vbox-intern\src\VBox\VMM\VMMAll\EMAll.cpp @ 452]
173	10 00000041`cadfed60 00007ffb`e1d0d4c0 VBoxVMM!nemR3WinHandleExitCpuId+0x79d [L:\vbox-intern\src\VBox\VMM\VMMAll\NEMAllNativeTemplate-win.cpp.h @ 1829] @encode
174	@endcode
175	*
176	* @see https://developercommunity.visualstudio.com/t/fragile-behavior-of-longjmp-called-from-noexcept-f/1532859
177	*/
178	#if defined(IEM_WITH_SETJMP) && (defined(_MSC_VER) \|\| defined(IEM_WITH_THROW_CATCH))
179	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT_EX(false)
180	#else
181	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT
182	#endif
183
184	#define IEM_IMPLEMENTS_TASKSWITCH
185
186	/** @def IEM_WITH_3DNOW
187	* Includes the 3DNow decoding. */
188	#if (!defined(IEM_WITH_3DNOW) && !defined(IEM_WITHOUT_3DNOW)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
189	# define IEM_WITH_3DNOW
190	#endif
191
192	/** @def IEM_WITH_THREE_0F_38
193	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
194	#if (!defined(IEM_WITH_THREE_0F_38) && !defined(IEM_WITHOUT_THREE_0F_38)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
195	# define IEM_WITH_THREE_0F_38
196	#endif
197
198	/** @def IEM_WITH_THREE_0F_3A
199	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
200	#if (!defined(IEM_WITH_THREE_0F_3A) && !defined(IEM_WITHOUT_THREE_0F_3A)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
201	# define IEM_WITH_THREE_0F_3A
202	#endif
203
204	/** @def IEM_WITH_VEX
205	* Includes the VEX decoding. */
206	#if (!defined(IEM_WITH_VEX) && !defined(IEM_WITHOUT_VEX)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
207	# define IEM_WITH_VEX
208	#endif
209
210	/** @def IEM_CFG_TARGET_CPU
211	* The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
212	*
213	* By default we allow this to be configured by the user via the
214	* CPUM/GuestCpuName config string, but this comes at a slight cost during
215	* decoding. So, for applications of this code where there is no need to
216	* be dynamic wrt target CPU, just modify this define.
217	*/
218	#if !defined(IEM_CFG_TARGET_CPU) \|\| defined(DOXYGEN_RUNNING)
219	# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
220	#endif
221
222	//#define IEM_WITH_CODE_TLB // - work in progress
223	//#define IEM_WITH_DATA_TLB // - work in progress
224
225
226	/** @def IEM_USE_UNALIGNED_DATA_ACCESS
227	* Use unaligned accesses instead of elaborate byte assembly. */
228	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86) \|\| defined(DOXYGEN_RUNNING)
229	# define IEM_USE_UNALIGNED_DATA_ACCESS
230	#endif
231
232	//#define IEM_LOG_MEMORY_WRITES
233
234	#if !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
235	/** Instruction statistics. */
236	typedef struct IEMINSTRSTATS
237	{
238	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
239	# include "IEMInstructionStatisticsTmpl.h"
240	# undef IEM_DO_INSTR_STAT
241	} IEMINSTRSTATS;
242	#else
243	struct IEMINSTRSTATS;
244	typedef struct IEMINSTRSTATS IEMINSTRSTATS;
245	#endif
246	/** Pointer to IEM instruction statistics. */
247	typedef IEMINSTRSTATS *PIEMINSTRSTATS;
248
249
250	/** @name IEMTARGETCPU_EFL_BEHAVIOR_XXX - IEMCPU::aidxTargetCpuEflFlavour
251	* @{ */
252	#define IEMTARGETCPU_EFL_BEHAVIOR_NATIVE 0 /*< Native x86 EFLAGS result; Intel EFLAGS when on non-x86 hosts. /
253	#define IEMTARGETCPU_EFL_BEHAVIOR_INTEL 1 /*< Intel EFLAGS result. /
254	#define IEMTARGETCPU_EFL_BEHAVIOR_AMD 2 /*< AMD EFLAGS result /
255	#define IEMTARGETCPU_EFL_BEHAVIOR_RESERVED 3 /*< Reserved/dummy entry slot that's the same as 0. /
256	#define IEMTARGETCPU_EFL_BEHAVIOR_MASK 3 /*< For masking the index before use. /
257	/** Selects the right variant from a_aArray.
258	* pVCpu is implicit in the caller context. */
259	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT(a_aArray) \
260	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[1] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
261	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for when no native worker can
262	* be used because the host CPU does not support the operation. */
263	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_NON_NATIVE(a_aArray) \
264	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
265	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for a two dimentional
266	* array paralleling IEMCPU::aidxTargetCpuEflFlavour and a single bit index
267	* into the two.
268	* @sa IEM_SELECT_NATIVE_OR_FALLBACK */
269	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
270	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
271	(a_aaArray[a_fNative][pVCpu->iem.s.aidxTargetCpuEflFlavour[a_fNative] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
272	#else
273	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
274	(a_aaArray[0][pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
275	#endif
276	/** @} */
277
278	/**
279	* Picks @a a_pfnNative or @a a_pfnFallback according to the host CPU feature
280	* indicator given by @a a_fCpumFeatureMember (CPUMFEATURES member).
281	*
282	* On non-x86 hosts, this will shortcut to the fallback w/o checking the
283	* indicator.
284	*
285	* @sa IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX
286	*/
287	#if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
288	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) \
289	(g_CpumHostFeatures.s.a_fCpumFeatureMember ? a_pfnNative : a_pfnFallback)
290	#else
291	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) (a_pfnFallback)
292	#endif
293
294
295	/**
296	* Extended operand mode that includes a representation of 8-bit.
297	*
298	* This is used for packing down modes when invoking some C instruction
299	* implementations.
300	*/
301	typedef enum IEMMODEX
302	{
303	IEMMODEX_16BIT = IEMMODE_16BIT,
304	IEMMODEX_32BIT = IEMMODE_32BIT,
305	IEMMODEX_64BIT = IEMMODE_64BIT,
306	IEMMODEX_8BIT
307	} IEMMODEX;
308	AssertCompileSize(IEMMODEX, 4);
309
310
311	/**
312	* Branch types.
313	*/
314	typedef enum IEMBRANCH
315	{
316	IEMBRANCH_JUMP = 1,
317	IEMBRANCH_CALL,
318	IEMBRANCH_TRAP,
319	IEMBRANCH_SOFTWARE_INT,
320	IEMBRANCH_HARDWARE_INT
321	} IEMBRANCH;
322	AssertCompileSize(IEMBRANCH, 4);
323
324
325	/**
326	* INT instruction types.
327	*/
328	typedef enum IEMINT
329	{
330	/** INT n instruction (opcode 0xcd imm). */
331	IEMINT_INTN = 0,
332	/** Single byte INT3 instruction (opcode 0xcc). */
333	IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
334	/** Single byte INTO instruction (opcode 0xce). */
335	IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
336	/** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
337	IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
338	} IEMINT;
339	AssertCompileSize(IEMINT, 4);
340
341
342	/**
343	* A FPU result.
344	*/
345	typedef struct IEMFPURESULT
346	{
347	/** The output value. */
348	RTFLOAT80U r80Result;
349	/** The output status. */
350	uint16_t FSW;
351	} IEMFPURESULT;
352	AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
353	/** Pointer to a FPU result. */
354	typedef IEMFPURESULT *PIEMFPURESULT;
355	/** Pointer to a const FPU result. */
356	typedef IEMFPURESULT const *PCIEMFPURESULT;
357
358
359	/**
360	* A FPU result consisting of two output values and FSW.
361	*/
362	typedef struct IEMFPURESULTTWO
363	{
364	/** The first output value. */
365	RTFLOAT80U r80Result1;
366	/** The output status. */
367	uint16_t FSW;
368	/** The second output value. */
369	RTFLOAT80U r80Result2;
370	} IEMFPURESULTTWO;
371	AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
372	AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
373	/** Pointer to a FPU result consisting of two output values and FSW. */
374	typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
375	/** Pointer to a const FPU result consisting of two output values and FSW. */
376	typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
377
378
379	/**
380	* IEM TLB entry.
381	*
382	* Lookup assembly:
383	* @code{.asm}
384	; Calculate tag.
385	mov rax, [VA]
386	shl rax, 16
387	shr rax, 16 + X86_PAGE_SHIFT
388	or rax, [uTlbRevision]
389
390	; Do indexing.
391	movzx ecx, al
392	lea rcx, [pTlbEntries + rcx]
393
394	; Check tag.
395	cmp [rcx + IEMTLBENTRY.uTag], rax
396	jne .TlbMiss
397
398	; Check access.
399	mov rax, ACCESS_FLAGS \| MAPPING_R3_NOT_VALID \| 0xffffff00
400	and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
401	cmp rax, [uTlbPhysRev]
402	jne .TlbMiss
403
404	; Calc address and we're done.
405	mov eax, X86_PAGE_OFFSET_MASK
406	and eax, [VA]
407	or rax, [rcx + IEMTLBENTRY.pMappingR3]
408	%ifdef VBOX_WITH_STATISTICS
409	inc qword [cTlbHits]
410	%endif
411	jmp .Done
412
413	.TlbMiss:
414	mov r8d, ACCESS_FLAGS
415	mov rdx, [VA]
416	mov rcx, [pVCpu]
417	call iemTlbTypeMiss
418	.Done:
419
420	@endcode
421	*
422	*/
423	typedef struct IEMTLBENTRY
424	{
425	/** The TLB entry tag.
426	* Bits 35 thru 0 are made up of the virtual address shifted right 12 bits, this
427	* is ASSUMING a virtual address width of 48 bits.
428	*
429	* Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
430	*
431	* The TLB lookup code uses the current TLB revision, which won't ever be zero,
432	* enabling an extremely cheap TLB invalidation most of the time. When the TLB
433	* revision wraps around though, the tags needs to be zeroed.
434	*
435	* @note Try use SHRD instruction? After seeing
436	* https://gmplib.org/~tege/x86-timing.pdf, maybe not.
437	*
438	* @todo This will need to be reorganized for 57-bit wide virtual address and
439	* PCID (currently 12 bits) and ASID (currently 6 bits) support. We'll
440	* have to move the TLB entry versioning entirely to the
441	* fFlagsAndPhysRev member then, 57 bit wide VAs means we'll only have
442	* 19 bits left (64 - 57 + 12 = 19) and they'll almost entire be
443	* consumed by PCID and ASID (12 + 6 = 18).
444	*/
445	uint64_t uTag;
446	/** Access flags and physical TLB revision.
447	*
448	* - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
449	* - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
450	* - Bit 2 - page tables - not user (complemented X86_PTE_US).
451	* - Bit 3 - pgm phys/virt - not directly writable.
452	* - Bit 4 - pgm phys page - not directly readable.
453	* - Bit 5 - page tables - not accessed (complemented X86_PTE_A).
454	* - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
455	* - Bit 7 - tlb entry - pMappingR3 member not valid.
456	* - Bits 63 thru 8 are used for the physical TLB revision number.
457	*
458	* We're using complemented bit meanings here because it makes it easy to check
459	* whether special action is required. For instance a user mode write access
460	* would do a "TEST fFlags, (X86_PTE_RW \| X86_PTE_US \| X86_PTE_D)" and a
461	* non-zero result would mean special handling needed because either it wasn't
462	* writable, or it wasn't user, or the page wasn't dirty. A user mode read
463	* access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
464	* need to check any PTE flag.
465	*/
466	uint64_t fFlagsAndPhysRev;
467	/** The guest physical page address. */
468	uint64_t GCPhys;
469	/** Pointer to the ring-3 mapping. */
470	R3PTRTYPE(uint8_t *) pbMappingR3;
471	#if HC_ARCH_BITS == 32
472	uint32_t u32Padding1;
473	#endif
474	} IEMTLBENTRY;
475	AssertCompileSize(IEMTLBENTRY, 32);
476	/** Pointer to an IEM TLB entry. */
477	typedef IEMTLBENTRY *PIEMTLBENTRY;
478
479	/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
480	* @{ */
481	#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /*< Page tables: Not executable. /
482	#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /*< Page tables: Not writable. /
483	#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /*< Page tables: Not user accessible (supervisor only). /
484	#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /*< Phys page: Not writable (access handler, ROM, whatever). /
485	#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /*< Phys page: Not readable (MMIO / access handler, ROM) /
486	#define IEMTLBE_F_PT_NO_ACCESSED RT_BIT_64(5) /*< Phys tables: Not accessed (need to be marked accessed). /
487	#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /*< Page tables: Not dirty (needs to be made dirty on write). /
488	#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(7) /*< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. /
489	#define IEMTLBE_F_PG_UNASSIGNED RT_BIT_64(8) /*< Phys page: Unassigned memory (not RAM, ROM, MMIO2 or MMIO). /
490	#define IEMTLBE_F_PG_CODE_PAGE RT_BIT_64(9) /*< Phys page: Code page. /
491	#define IEMTLBE_F_PHYS_REV UINT64_C(0xfffffffffffffc00) /*< Physical revision mask. @sa IEMTLB_PHYS_REV_INCR /
492	/** @} */
493
494
495	/**
496	* An IEM TLB.
497	*
498	* We've got two of these, one for data and one for instructions.
499	*/
500	typedef struct IEMTLB
501	{
502	/** The TLB entries.
503	* We've choosen 256 because that way we can obtain the result directly from a
504	* 8-bit register without an additional AND instruction. */
505	IEMTLBENTRY aEntries[256];
506	/** The TLB revision.
507	* This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
508	* by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
509	* the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
510	* (The revision zero indicates an invalid TLB entry.)
511	*
512	* The initial value is choosen to cause an early wraparound. */
513	uint64_t uTlbRevision;
514	/** The TLB physical address revision - shadow of PGM variable.
515	*
516	* This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
517	* incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
518	* a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
519	* as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
520	*
521	* The initial value is choosen to cause an early wraparound. */
522	uint64_t volatile uTlbPhysRev;
523
524	/* Statistics: */
525
526	/** TLB hits (VBOX_WITH_STATISTICS only). */
527	uint64_t cTlbHits;
528	/** TLB misses. */
529	uint32_t cTlbMisses;
530	/** Slow read path. */
531	uint32_t cTlbSlowReadPath;
532	/** Safe read path. */
533	uint32_t cTlbSafeReadPath;
534	/** Safe write path. */
535	uint32_t cTlbSafeWritePath;
536	#if 0
537	/** TLB misses because of tag mismatch. */
538	uint32_t cTlbMissesTag;
539	/** TLB misses because of virtual access violation. */
540	uint32_t cTlbMissesVirtAccess;
541	/** TLB misses because of dirty bit. */
542	uint32_t cTlbMissesDirty;
543	/** TLB misses because of MMIO */
544	uint32_t cTlbMissesMmio;
545	/** TLB misses because of write access handlers. */
546	uint32_t cTlbMissesWriteHandler;
547	/** TLB misses because no r3(/r0) mapping. */
548	uint32_t cTlbMissesMapping;
549	#endif
550	/** Alignment padding. */
551	uint32_t au32Padding[6];
552	} IEMTLB;
553	AssertCompileSizeAlignment(IEMTLB, 64);
554	/** IEMTLB::uTlbRevision increment. */
555	#define IEMTLB_REVISION_INCR RT_BIT_64(36)
556	/** IEMTLB::uTlbRevision mask. */
557	#define IEMTLB_REVISION_MASK (~(RT_BIT_64(36) - 1))
558	/** IEMTLB::uTlbPhysRev increment.
559	* @sa IEMTLBE_F_PHYS_REV */
560	#define IEMTLB_PHYS_REV_INCR RT_BIT_64(10)
561	/**
562	* Calculates the TLB tag for a virtual address.
563	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
564	* @param a_pTlb The TLB.
565	* @param a_GCPtr The virtual address. Must be RTGCPTR or same size or
566	* the clearing of the top 16 bits won't work (if 32-bit
567	* we'll end up with mostly zeros).
568	*/
569	#define IEMTLB_CALC_TAG(a_pTlb, a_GCPtr) ( IEMTLB_CALC_TAG_NO_REV(a_GCPtr) \| (a_pTlb)->uTlbRevision )
570	/**
571	* Calculates the TLB tag for a virtual address but without TLB revision.
572	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
573	* @param a_GCPtr The virtual address. Must be RTGCPTR or same size or
574	* the clearing of the top 16 bits won't work (if 32-bit
575	* we'll end up with mostly zeros).
576	*/
577	#define IEMTLB_CALC_TAG_NO_REV(a_GCPtr) ( (((a_GCPtr) << 16) >> (GUEST_PAGE_SHIFT + 16)) )
578	/**
579	* Converts a TLB tag value into a TLB index.
580	* @returns Index into IEMTLB::aEntries.
581	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
582	*/
583	#define IEMTLB_TAG_TO_INDEX(a_uTag) ( (uint8_t)(a_uTag) )
584	/**
585	* Converts a TLB tag value into a TLB index.
586	* @returns Index into IEMTLB::aEntries.
587	* @param a_pTlb The TLB.
588	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
589	*/
590	#define IEMTLB_TAG_TO_ENTRY(a_pTlb, a_uTag) ( &(a_pTlb)->aEntries[IEMTLB_TAG_TO_INDEX(a_uTag)] )
591
592
593	/** @name IEM_MC_F_XXX - MC block flags/clues.
594	* @todo Merge with IEM_CIMPL_F_XXX
595	* @{ */
596	#define IEM_MC_F_ONLY_8086 RT_BIT_32(0)
597	#define IEM_MC_F_MIN_186 RT_BIT_32(1)
598	#define IEM_MC_F_MIN_286 RT_BIT_32(2)
599	#define IEM_MC_F_NOT_286_OR_OLDER IEM_MC_F_MIN_386
600	#define IEM_MC_F_MIN_386 RT_BIT_32(3)
601	#define IEM_MC_F_MIN_486 RT_BIT_32(4)
602	#define IEM_MC_F_MIN_PENTIUM RT_BIT_32(5)
603	#define IEM_MC_F_MIN_PENTIUM_II IEM_MC_F_MIN_PENTIUM
604	#define IEM_MC_F_MIN_CORE IEM_MC_F_MIN_PENTIUM
605	#define IEM_MC_F_64BIT RT_BIT_32(6)
606	#define IEM_MC_F_NOT_64BIT RT_BIT_32(7)
607	/** This is set by IEMAllN8vePython.py to indicate a variation without the
608	* flags-clearing-and-checking, when there is also a variation with that.
609	* @note Do not use this manully, it's only for python and for testing in
610	* the native recompiler! */
611	#define IEM_MC_F_WITHOUT_FLAGS RT_BIT_32(8)
612	/** @} */
613
614	/** @name IEM_CIMPL_F_XXX - State change clues for CIMPL calls.
615	*
616	* These clues are mainly for the recompiler, so that it can emit correct code.
617	*
618	* They are processed by the python script and which also automatically
619	* calculates flags for MC blocks based on the statements, extending the use of
620	* these flags to describe MC block behavior to the recompiler core. The python
621	* script pass the flags to the IEM_MC2_END_EMIT_CALLS macro, but mainly for
622	* error checking purposes. The script emits the necessary fEndTb = true and
623	* similar statements as this reduces compile time a tiny bit.
624	*
625	* @{ */
626	/** Flag set if direct branch, clear if absolute or indirect. */
627	#define IEM_CIMPL_F_BRANCH_DIRECT RT_BIT_32(0)
628	/** Flag set if indirect branch, clear if direct or relative.
629	* This is also used for all system control transfers (SYSCALL, SYSRET, INT, ++)
630	* as well as for return instructions (RET, IRET, RETF). */
631	#define IEM_CIMPL_F_BRANCH_INDIRECT RT_BIT_32(1)
632	/** Flag set if relative branch, clear if absolute or indirect. */
633	#define IEM_CIMPL_F_BRANCH_RELATIVE RT_BIT_32(2)
634	/** Flag set if conditional branch, clear if unconditional. */
635	#define IEM_CIMPL_F_BRANCH_CONDITIONAL RT_BIT_32(3)
636	/** Flag set if it's a far branch (changes CS). */
637	#define IEM_CIMPL_F_BRANCH_FAR RT_BIT_32(4)
638	/** Convenience: Testing any kind of branch. */
639	#define IEM_CIMPL_F_BRANCH_ANY (IEM_CIMPL_F_BRANCH_DIRECT \| IEM_CIMPL_F_BRANCH_INDIRECT \| IEM_CIMPL_F_BRANCH_RELATIVE)
640
641	/** Execution flags may change (IEMCPU::fExec). */
642	#define IEM_CIMPL_F_MODE RT_BIT_32(5)
643	/** May change significant portions of RFLAGS. */
644	#define IEM_CIMPL_F_RFLAGS RT_BIT_32(6)
645	/** May change the status bits (X86_EFL_STATUS_BITS) in RFLAGS. */
646	#define IEM_CIMPL_F_STATUS_FLAGS RT_BIT_32(7)
647	/** May trigger interrupt shadowing. */
648	#define IEM_CIMPL_F_INHIBIT_SHADOW RT_BIT_32(8)
649	/** May enable interrupts, so recheck IRQ immediately afterwards executing
650	* the instruction. */
651	#define IEM_CIMPL_F_CHECK_IRQ_AFTER RT_BIT_32(9)
652	/** May disable interrupts, so recheck IRQ immediately before executing the
653	* instruction. */
654	#define IEM_CIMPL_F_CHECK_IRQ_BEFORE RT_BIT_32(10)
655	/** Convenience: Check for IRQ both before and after an instruction. */
656	#define IEM_CIMPL_F_CHECK_IRQ_BEFORE_AND_AFTER (IEM_CIMPL_F_CHECK_IRQ_BEFORE \| IEM_CIMPL_F_CHECK_IRQ_AFTER)
657	/** May trigger a VM exit (treated like IEM_CIMPL_F_MODE atm). */
658	#define IEM_CIMPL_F_VMEXIT RT_BIT_32(11)
659	/** May modify FPU state.
660	* @todo Not sure if this is useful yet. */
661	#define IEM_CIMPL_F_FPU RT_BIT_32(12)
662	/** REP prefixed instruction which may yield before updating PC.
663	* @todo Not sure if this is useful, REP functions now return non-zero
664	* status if they don't update the PC. */
665	#define IEM_CIMPL_F_REP RT_BIT_32(13)
666	/** I/O instruction.
667	* @todo Not sure if this is useful yet. */
668	#define IEM_CIMPL_F_IO RT_BIT_32(14)
669	/** Force end of TB after the instruction. */
670	#define IEM_CIMPL_F_END_TB RT_BIT_32(15)
671	/** Flag set if a branch may also modify the stack (push/pop return address). */
672	#define IEM_CIMPL_F_BRANCH_STACK RT_BIT_32(16)
673	/** Flag set if a branch may also modify the stack (push/pop return address)
674	* and switch it (load/restore SS:RSP). */
675	#define IEM_CIMPL_F_BRANCH_STACK_FAR RT_BIT_32(17)
676	/** Convenience: Raise exception (technically unnecessary, since it shouldn't return VINF_SUCCESS). */
677	#define IEM_CIMPL_F_XCPT \
678	(IEM_CIMPL_F_BRANCH_INDIRECT \| IEM_CIMPL_F_BRANCH_FAR \| IEM_CIMPL_F_BRANCH_STACK_FAR \
679	\| IEM_CIMPL_F_MODE \| IEM_CIMPL_F_RFLAGS \| IEM_CIMPL_F_VMEXIT)
680
681	/** The block calls a C-implementation instruction function with two implicit arguments.
682	* Mutually exclusive with IEM_CIMPL_F_CALLS_AIMPL and
683	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
684	* @note The python scripts will add this if missing. */
685	#define IEM_CIMPL_F_CALLS_CIMPL RT_BIT_32(18)
686	/** The block calls an ASM-implementation instruction function.
687	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL and
688	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
689	* @note The python scripts will add this if missing. */
690	#define IEM_CIMPL_F_CALLS_AIMPL RT_BIT_32(19)
691	/** The block calls an ASM-implementation instruction function with an implicit
692	* X86FXSTATE pointer argument.
693	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL, IEM_CIMPL_F_CALLS_AIMPL and
694	* IEM_CIMPL_F_CALLS_AIMPL_WITH_XSTATE.
695	* @note The python scripts will add this if missing. */
696	#define IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE RT_BIT_32(20)
697	/** The block calls an ASM-implementation instruction function with an implicit
698	* X86XSAVEAREA pointer argument.
699	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL, IEM_CIMPL_F_CALLS_AIMPL and
700	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
701	* @note No different from IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE, so same value.
702	* @note The python scripts will add this if missing. */
703	#define IEM_CIMPL_F_CALLS_AIMPL_WITH_XSTATE IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE
704	/** @} */
705
706
707	/** @name IEM_F_XXX - Execution mode flags (IEMCPU::fExec, IEMTB::fFlags).
708	*
709	* These flags are set when entering IEM and adjusted as code is executed, such
710	* that they will always contain the current values as instructions are
711	* finished.
712	*
713	* In recompiled execution mode, (most of) these flags are included in the
714	* translation block selection key and stored in IEMTB::fFlags alongside the
715	* IEMTB_F_XXX flags. The latter flags uses bits 31 thru 24, which are all zero
716	* in IEMCPU::fExec.
717	*
718	* @{ */
719	/** Mode: The block target mode mask. */
720	#define IEM_F_MODE_MASK UINT32_C(0x0000001f)
721	/** Mode: The IEMMODE part of the IEMTB_F_MODE_MASK value. */
722	#define IEM_F_MODE_CPUMODE_MASK UINT32_C(0x00000003)
723	/** X86 Mode: Bit used to indicating pre-386 CPU in 16-bit mode (for eliminating
724	* conditional in EIP/IP updating), and flat wide open CS, SS, DS, and ES in
725	* 32-bit mode (for simplifying most memory accesses). */
726	#define IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK UINT32_C(0x00000004)
727	/** X86 Mode: Bit indicating protected mode, real mode (or SMM) when not set. */
728	#define IEM_F_MODE_X86_PROT_MASK UINT32_C(0x00000008)
729	/** X86 Mode: Bit used to indicate virtual 8086 mode (only 16-bit). */
730	#define IEM_F_MODE_X86_V86_MASK UINT32_C(0x00000010)
731
732	/** X86 Mode: 16-bit on 386 or later. */
733	#define IEM_F_MODE_X86_16BIT UINT32_C(0x00000000)
734	/** X86 Mode: 80286, 80186 and 8086/88 targetting blocks (EIP update opt). */
735	#define IEM_F_MODE_X86_16BIT_PRE_386 UINT32_C(0x00000004)
736	/** X86 Mode: 16-bit protected mode on 386 or later. */
737	#define IEM_F_MODE_X86_16BIT_PROT UINT32_C(0x00000008)
738	/** X86 Mode: 16-bit protected mode on 386 or later. */
739	#define IEM_F_MODE_X86_16BIT_PROT_PRE_386 UINT32_C(0x0000000c)
740	/** X86 Mode: 16-bit virtual 8086 protected mode (on 386 or later). */
741	#define IEM_F_MODE_X86_16BIT_PROT_V86 UINT32_C(0x00000018)
742
743	/** X86 Mode: 32-bit on 386 or later. */
744	#define IEM_F_MODE_X86_32BIT UINT32_C(0x00000001)
745	/** X86 Mode: 32-bit mode with wide open flat CS, SS, DS and ES. */
746	#define IEM_F_MODE_X86_32BIT_FLAT UINT32_C(0x00000005)
747	/** X86 Mode: 32-bit protected mode. */
748	#define IEM_F_MODE_X86_32BIT_PROT UINT32_C(0x00000009)
749	/** X86 Mode: 32-bit protected mode with wide open flat CS, SS, DS and ES. */
750	#define IEM_F_MODE_X86_32BIT_PROT_FLAT UINT32_C(0x0000000d)
751
752	/** X86 Mode: 64-bit (includes protected, but not the flat bit). */
753	#define IEM_F_MODE_X86_64BIT UINT32_C(0x0000000a)
754
755	/** X86 Mode: Checks if @a a_fExec represent a FLAT mode. */
756	#define IEM_F_MODE_X86_IS_FLAT(a_fExec) ( ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_64BIT \
757	\|\| ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_32BIT_PROT_FLAT \
758	\|\| ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_32BIT_FLAT)
759
760	/** Bypass access handlers when set. */
761	#define IEM_F_BYPASS_HANDLERS UINT32_C(0x00010000)
762	/** Have pending hardware instruction breakpoints. */
763	#define IEM_F_PENDING_BRK_INSTR UINT32_C(0x00020000)
764	/** Have pending hardware data breakpoints. */
765	#define IEM_F_PENDING_BRK_DATA UINT32_C(0x00040000)
766
767	/** X86: Have pending hardware I/O breakpoints. */
768	#define IEM_F_PENDING_BRK_X86_IO UINT32_C(0x00000400)
769	/** X86: Disregard the lock prefix (implied or not) when set. */
770	#define IEM_F_X86_DISREGARD_LOCK UINT32_C(0x00000800)
771
772	/** Pending breakpoint mask (what iemCalcExecDbgFlags works out). */
773	#define IEM_F_PENDING_BRK_MASK (IEM_F_PENDING_BRK_INSTR \| IEM_F_PENDING_BRK_DATA \| IEM_F_PENDING_BRK_X86_IO)
774
775	/** Caller configurable options. */
776	#define IEM_F_USER_OPTS (IEM_F_BYPASS_HANDLERS \| IEM_F_X86_DISREGARD_LOCK)
777
778	/** X86: The current protection level (CPL) shift factor. */
779	#define IEM_F_X86_CPL_SHIFT 8
780	/** X86: The current protection level (CPL) mask. */
781	#define IEM_F_X86_CPL_MASK UINT32_C(0x00000300)
782	/** X86: The current protection level (CPL) shifted mask. */
783	#define IEM_F_X86_CPL_SMASK UINT32_C(0x00000003)
784
785	/** X86 execution context.
786	* The IEM_F_X86_CTX_XXX values are individual flags that can be combined (with
787	* the exception of IEM_F_X86_CTX_NORMAL). This allows running VMs from SMM
788	* mode. */
789	#define IEM_F_X86_CTX_MASK UINT32_C(0x0000f000)
790	/** X86 context: Plain regular execution context. */
791	#define IEM_F_X86_CTX_NORMAL UINT32_C(0x00000000)
792	/** X86 context: VT-x enabled. */
793	#define IEM_F_X86_CTX_VMX UINT32_C(0x00001000)
794	/** X86 context: AMD-V enabled. */
795	#define IEM_F_X86_CTX_SVM UINT32_C(0x00002000)
796	/** X86 context: In AMD-V or VT-x guest mode. */
797	#define IEM_F_X86_CTX_IN_GUEST UINT32_C(0x00004000)
798	/** X86 context: System management mode (SMM). */
799	#define IEM_F_X86_CTX_SMM UINT32_C(0x00008000)
800
801	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
802	* iemRegFinishClearingRF() most for most situations (CPUMCTX_DBG_HIT_DRX_MASK
803	* and CPUMCTX_DBG_DBGF_MASK are covered by the IEM_F_PENDING_BRK_XXX bits
804	* alread). */
805
806	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
807	* iemRegFinishClearingRF() most for most situations
808	* (CPUMCTX_DBG_HIT_DRX_MASK and CPUMCTX_DBG_DBGF_MASK are covered by
809	* the IEM_F_PENDING_BRK_XXX bits alread). */
810
811	/** @} */
812
813
814	/** @name IEMTB_F_XXX - Translation block flags (IEMTB::fFlags).
815	*
816	* Extends the IEM_F_XXX flags (subject to IEMTB_F_IEM_F_MASK) to make up the
817	* translation block flags. The combined flag mask (subject to
818	* IEMTB_F_KEY_MASK) is used as part of the lookup key for translation blocks.
819	*
820	* @{ */
821	/** Mask of IEM_F_XXX flags included in IEMTB_F_XXX. */
822	#define IEMTB_F_IEM_F_MASK UINT32_C(0x00ffffff)
823
824	/** Type: The block type mask. */
825	#define IEMTB_F_TYPE_MASK UINT32_C(0x03000000)
826	/** Type: Purly threaded recompiler (via tables). */
827	#define IEMTB_F_TYPE_THREADED UINT32_C(0x01000000)
828	/** Type: Native recompilation. */
829	#define IEMTB_F_TYPE_NATIVE UINT32_C(0x02000000)
830
831	/** Set when we're starting the block in an "interrupt shadow".
832	* We don't need to distingish between the two types of this mask, thus the one.
833	* @see CPUMCTX_INHIBIT_SHADOW, CPUMIsInInterruptShadow() */
834	#define IEMTB_F_INHIBIT_SHADOW UINT32_C(0x04000000)
835	/** Set when we're currently inhibiting NMIs
836	* @see CPUMCTX_INHIBIT_NMI, CPUMAreInterruptsInhibitedByNmi() */
837	#define IEMTB_F_INHIBIT_NMI UINT32_C(0x08000000)
838
839	/** Checks that EIP/IP is wihin CS.LIM before each instruction. Used when
840	* we're close the limit before starting a TB, as determined by
841	* iemGetTbFlagsForCurrentPc(). */
842	#define IEMTB_F_CS_LIM_CHECKS UINT32_C(0x10000000)
843
844	/** Mask of the IEMTB_F_XXX flags that are part of the TB lookup key.
845	*
846	* @note We skip all of IEM_F_X86_CTX_MASK, with the exception of SMM (which we
847	* don't implement), because we don't currently generate any context
848	* specific code - that's all handled in CIMPL functions.
849	*
850	* For the threaded recompiler we don't generate any CPL specific code
851	* either, but the native recompiler does for memory access (saves getting
852	* the CPL from fExec and turning it into IEMTLBE_F_PT_NO_USER).
853	* Since most OSes will not share code between rings, this shouldn't
854	* have any real effect on TB/memory/recompiling load.
855	*/
856	#define IEMTB_F_KEY_MASK ((UINT32_MAX & ~(IEM_F_X86_CTX_MASK \| IEMTB_F_TYPE_MASK)) \| IEM_F_X86_CTX_SMM)
857	/** @} */
858
859	AssertCompile( (IEM_F_MODE_X86_16BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
860	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
861	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_PROT_MASK));
862	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_V86_MASK));
863	AssertCompile( (IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
864	AssertCompile( IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
865	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_PROT_MASK));
866	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
867	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
868	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
869	AssertCompile( IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
870	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_V86_MASK));
871	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
872	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
873	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_PROT_MASK);
874	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
875	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_PROT_MASK);
876	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
877	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_V86_MASK);
878
879	AssertCompile( (IEM_F_MODE_X86_32BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
880	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
881	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_PROT_MASK));
882	AssertCompile( (IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
883	AssertCompile( IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
884	AssertCompile(!(IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_PROT_MASK));
885	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
886	AssertCompile(!(IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
887	AssertCompile( IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
888	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
889	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
890	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_PROT_MASK);
891
892	AssertCompile( (IEM_F_MODE_X86_64BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_64BIT);
893	AssertCompile( IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_PROT_MASK);
894	AssertCompile(!(IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
895
896	/** Native instruction type for use with the native code generator.
897	* This is a byte (uint8_t) for x86 and amd64 and uint32_t for the other(s). */
898	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
899	typedef uint8_t IEMNATIVEINSTR;
900	#else
901	typedef uint32_t IEMNATIVEINSTR;
902	#endif
903	/** Pointer to a native instruction unit. */
904	typedef IEMNATIVEINSTR *PIEMNATIVEINSTR;
905	/** Pointer to a const native instruction unit. */
906	typedef IEMNATIVEINSTR const *PCIEMNATIVEINSTR;
907
908	/**
909	* A call for the threaded call table.
910	*/
911	typedef struct IEMTHRDEDCALLENTRY
912	{
913	/** The function to call (IEMTHREADEDFUNCS). */
914	uint16_t enmFunction;
915	/** Instruction number in the TB (for statistics). */
916	uint8_t idxInstr;
917	uint8_t uUnused0;
918
919	/** Offset into IEMTB::pabOpcodes. */
920	uint16_t offOpcode;
921	/** The opcode length. */
922	uint8_t cbOpcode;
923	/** Index in to IEMTB::aRanges. */
924	uint8_t idxRange;
925
926	/** Generic parameters. */
927	uint64_t auParams[3];
928	} IEMTHRDEDCALLENTRY;
929	AssertCompileSize(IEMTHRDEDCALLENTRY, sizeof(uint64_t) * 4);
930	/** Pointer to a threaded call entry. */
931	typedef struct IEMTHRDEDCALLENTRY *PIEMTHRDEDCALLENTRY;
932	/** Pointer to a const threaded call entry. */
933	typedef IEMTHRDEDCALLENTRY const *PCIEMTHRDEDCALLENTRY;
934
935	/**
936	* Native IEM TB 'function' typedef.
937	*
938	* This will throw/longjmp on occation.
939	*
940	* @note AMD64 doesn't have that many non-volatile registers and does sport
941	* 32-bit address displacments, so we don't need pCtx.
942	*
943	* On ARM64 pCtx allows us to directly address the whole register
944	* context without requiring a separate indexing register holding the
945	* offset. This saves an instruction loading the offset for each guest
946	* CPU context access, at the cost of a non-volatile register.
947	* Fortunately, ARM64 has quite a lot more registers.
948	*/
949	typedef
950	#ifdef RT_ARCH_AMD64
951	int FNIEMTBNATIVE(PVMCPUCC pVCpu)
952	#else
953	int FNIEMTBNATIVE(PVMCPUCC pVCpu, PCPUMCTX pCtx)
954	#endif
955	#if RT_CPLUSPLUS_PREREQ(201700)
956	IEM_NOEXCEPT_MAY_LONGJMP
957	#endif
958	;
959	/** Pointer to a native IEM TB entry point function.
960	* This will throw/longjmp on occation. */
961	typedef FNIEMTBNATIVE *PFNIEMTBNATIVE;
962
963
964	/**
965	* Translation block debug info entry type.
966	*/
967	typedef enum IEMTBDBGENTRYTYPE
968	{
969	kIemTbDbgEntryType_Invalid = 0,
970	/** The entry is for marking a native code position.
971	* Entries following this all apply to this position. */
972	kIemTbDbgEntryType_NativeOffset,
973	/** The entry is for a new guest instruction. */
974	kIemTbDbgEntryType_GuestInstruction,
975	/** Marks the start of a threaded call. */
976	kIemTbDbgEntryType_ThreadedCall,
977	/** Marks the location of a label. */
978	kIemTbDbgEntryType_Label,
979	/** Info about a host register shadowing a guest register. */
980	kIemTbDbgEntryType_GuestRegShadowing,
981	#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
982	/** Info about a host SIMD register shadowing a guest SIMD register. */
983	kIemTbDbgEntryType_GuestSimdRegShadowing,
984	#endif
985	#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING
986	/** Info about a delayed RIP update. */
987	kIemTbDbgEntryType_DelayedPcUpdate,
988	#endif
989	kIemTbDbgEntryType_End
990	} IEMTBDBGENTRYTYPE;
991
992	/**
993	* Translation block debug info entry.
994	*/
995	typedef union IEMTBDBGENTRY
996	{
997	/** Plain 32-bit view. */
998	uint32_t u;
999
1000	/** Generic view for getting at the type field. */
1001	struct
1002	{
1003	/** IEMTBDBGENTRYTYPE */
1004	uint32_t uType : 4;
1005	uint32_t uTypeSpecific : 28;
1006	} Gen;
1007
1008	struct
1009	{
1010	/** kIemTbDbgEntryType_ThreadedCall1. */
1011	uint32_t uType : 4;
1012	/** Native code offset. */
1013	uint32_t offNative : 28;
1014	} NativeOffset;
1015
1016	struct
1017	{
1018	/** kIemTbDbgEntryType_GuestInstruction. */
1019	uint32_t uType : 4;
1020	uint32_t uUnused : 4;
1021	/** The IEM_F_XXX flags. */
1022	uint32_t fExec : 24;
1023	} GuestInstruction;
1024
1025	struct
1026	{
1027	/* kIemTbDbgEntryType_ThreadedCall. */
1028	uint32_t uType : 4;
1029	/** Set if the call was recompiled to native code, clear if just calling
1030	* threaded function. */
1031	uint32_t fRecompiled : 1;
1032	uint32_t uUnused : 11;
1033	/** The threaded call number (IEMTHREADEDFUNCS). */
1034	uint32_t enmCall : 16;
1035	} ThreadedCall;
1036
1037	struct
1038	{
1039	/* kIemTbDbgEntryType_Label. */
1040	uint32_t uType : 4;
1041	uint32_t uUnused : 4;
1042	/** The label type (IEMNATIVELABELTYPE). */
1043	uint32_t enmLabel : 8;
1044	/** The label data. */
1045	uint32_t uData : 16;
1046	} Label;
1047
1048	struct
1049	{
1050	/* kIemTbDbgEntryType_GuestRegShadowing. */
1051	uint32_t uType : 4;
1052	uint32_t uUnused : 4;
1053	/** The guest register being shadowed (IEMNATIVEGSTREG). */
1054	uint32_t idxGstReg : 8;
1055	/** The host new register number, UINT8_MAX if dropped. */
1056	uint32_t idxHstReg : 8;
1057	/** The previous host register number, UINT8_MAX if new. */
1058	uint32_t idxHstRegPrev : 8;
1059	} GuestRegShadowing;
1060
1061	#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
1062	struct
1063	{
1064	/* kIemTbDbgEntryType_GuestSimdRegShadowing. */
1065	uint32_t uType : 4;
1066	uint32_t uUnused : 4;
1067	/** The guest register being shadowed (IEMNATIVEGSTSIMDREG). */
1068	uint32_t idxGstSimdReg : 8;
1069	/** The host new register number, UINT8_MAX if dropped. */
1070	uint32_t idxHstSimdReg : 8;
1071	/** The previous host register number, UINT8_MAX if new. */
1072	uint32_t idxHstSimdRegPrev : 8;
1073	} GuestSimdRegShadowing;
1074	#endif
1075
1076	#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING
1077	struct
1078	{
1079	/* kIemTbDbgEntryType_DelayedPcUpdate. */
1080	uint32_t uType : 4;
1081	/* The instruction offset added to the program counter. */
1082	uint32_t offPc : 14;
1083	/** Number of instructions skipped. */
1084	uint32_t cInstrSkipped : 14;
1085	} DelayedPcUpdate;
1086	#endif
1087
1088	} IEMTBDBGENTRY;
1089	AssertCompileSize(IEMTBDBGENTRY, sizeof(uint32_t));
1090	/** Pointer to a debug info entry. */
1091	typedef IEMTBDBGENTRY *PIEMTBDBGENTRY;
1092	/** Pointer to a const debug info entry. */
1093	typedef IEMTBDBGENTRY const *PCIEMTBDBGENTRY;
1094
1095	/**
1096	* Translation block debug info.
1097	*/
1098	typedef struct IEMTBDBG
1099	{
1100	/** Number of entries in aEntries. */
1101	uint32_t cEntries;
1102	/** Debug info entries. */
1103	RT_FLEXIBLE_ARRAY_EXTENSION
1104	IEMTBDBGENTRY aEntries[RT_FLEXIBLE_ARRAY];
1105	} IEMTBDBG;
1106	/** Pointer to TB debug info. */
1107	typedef IEMTBDBG *PIEMTBDBG;
1108	/** Pointer to const TB debug info. */
1109	typedef IEMTBDBG const *PCIEMTBDBG;
1110
1111
1112	/**
1113	* Translation block.
1114	*
1115	* The current plan is to just keep TBs and associated lookup hash table private
1116	* to each VCpu as that simplifies TB removal greatly (no races) and generally
1117	* avoids using expensive atomic primitives for updating lists and stuff.
1118	*/
1119	#pragma pack(2) /* to prevent the Thrd structure from being padded unnecessarily */
1120	typedef struct IEMTB
1121	{
1122	/** Next block with the same hash table entry. */
1123	struct IEMTB *pNext;
1124	/** Usage counter. */
1125	uint32_t cUsed;
1126	/** The IEMCPU::msRecompilerPollNow last time it was used. */
1127	uint32_t msLastUsed;
1128
1129	/** @name What uniquely identifies the block.
1130	* @{ */
1131	RTGCPHYS GCPhysPc;
1132	/** IEMTB_F_XXX (i.e. IEM_F_XXX ++). */
1133	uint32_t fFlags;
1134	union
1135	{
1136	struct
1137	{
1138	/*< Relevant CS X86DESCATTR_XXX bits. /
1139	uint16_t fAttr;
1140	} x86;
1141	};
1142	/** @} */
1143
1144	/** Number of opcode ranges. */
1145	uint8_t cRanges;
1146	/** Statistics: Number of instructions in the block. */
1147	uint8_t cInstructions;
1148
1149	/** Type specific info. */
1150	union
1151	{
1152	struct
1153	{
1154	/** The call sequence table. */
1155	PIEMTHRDEDCALLENTRY paCalls;
1156	/** Number of calls in paCalls. */
1157	uint16_t cCalls;
1158	/** Number of calls allocated. */
1159	uint16_t cAllocated;
1160	} Thrd;
1161	struct
1162	{
1163	/** The native instructions (PFNIEMTBNATIVE). */
1164	PIEMNATIVEINSTR paInstructions;
1165	/** Number of instructions pointed to by paInstructions. */
1166	uint32_t cInstructions;
1167	} Native;
1168	/** Generic view for zeroing when freeing. */
1169	struct
1170	{
1171	uintptr_t uPtr;
1172	uint32_t uData;
1173	} Gen;
1174	};
1175
1176	/** The allocation chunk this TB belongs to. */
1177	uint8_t idxAllocChunk;
1178	uint8_t bUnused;
1179
1180	/** Number of bytes of opcodes stored in pabOpcodes.
1181	* @todo this field isn't really needed, aRanges keeps the actual info. */
1182	uint16_t cbOpcodes;
1183	/** Pointer to the opcode bytes this block was recompiled from. */
1184	uint8_t *pabOpcodes;
1185
1186	/** Debug info if enabled.
1187	* This is only generated by the native recompiler. */
1188	PIEMTBDBG pDbgInfo;
1189
1190	/* --- 64 byte cache line end --- */
1191
1192	/** Opcode ranges.
1193	*
1194	* The opcode checkers and maybe TLB loading functions will use this to figure
1195	* out what to do. The parameter will specify an entry and the opcode offset to
1196	* start at and the minimum number of bytes to verify (instruction length).
1197	*
1198	* When VT-x and AMD-V looks up the opcode bytes for an exitting instruction,
1199	* they'll first translate RIP (+ cbInstr - 1) to a physical address using the
1200	* code TLB (must have a valid entry for that address) and scan the ranges to
1201	* locate the corresponding opcodes. Probably.
1202	*/
1203	struct IEMTBOPCODERANGE
1204	{
1205	/** Offset within pabOpcodes. */
1206	uint16_t offOpcodes;
1207	/** Number of bytes. */
1208	uint16_t cbOpcodes;
1209	/** The page offset. */
1210	RT_GCC_EXTENSION
1211	uint16_t offPhysPage : 12;
1212	/** Unused bits. */
1213	RT_GCC_EXTENSION
1214	uint16_t u2Unused : 2;
1215	/** Index into GCPhysPc + aGCPhysPages for the physical page address. */
1216	RT_GCC_EXTENSION
1217	uint16_t idxPhysPage : 2;
1218	} aRanges[8];
1219
1220	/** Physical pages that this TB covers.
1221	* The GCPhysPc w/o page offset is element zero, so starting here with 1. */
1222	RTGCPHYS aGCPhysPages[2];
1223	} IEMTB;
1224	#pragma pack()
1225	AssertCompileMemberAlignment(IEMTB, GCPhysPc, sizeof(RTGCPHYS));
1226	AssertCompileMemberAlignment(IEMTB, Thrd, sizeof(void *));
1227	AssertCompileMemberAlignment(IEMTB, pabOpcodes, sizeof(void *));
1228	AssertCompileMemberAlignment(IEMTB, pDbgInfo, sizeof(void *));
1229	AssertCompileMemberAlignment(IEMTB, aGCPhysPages, sizeof(RTGCPHYS));
1230	AssertCompileMemberOffset(IEMTB, aRanges, 64);
1231	AssertCompileMemberSize(IEMTB, aRanges[0], 6);
1232	#if 1
1233	AssertCompileSize(IEMTB, 128);
1234	# define IEMTB_SIZE_IS_POWER_OF_TWO /*< The IEMTB size is a power of two. /
1235	#else
1236	AssertCompileSize(IEMTB, 168);
1237	# undef IEMTB_SIZE_IS_POWER_OF_TWO
1238	#endif
1239
1240	/** Pointer to a translation block. */
1241	typedef IEMTB *PIEMTB;
1242	/** Pointer to a const translation block. */
1243	typedef IEMTB const *PCIEMTB;
1244
1245	/**
1246	* A chunk of memory in the TB allocator.
1247	*/
1248	typedef struct IEMTBCHUNK
1249	{
1250	/** Pointer to the translation blocks in this chunk. */
1251	PIEMTB paTbs;
1252	#ifdef IN_RING0
1253	/** Allocation handle. */
1254	RTR0MEMOBJ hMemObj;
1255	#endif
1256	} IEMTBCHUNK;
1257
1258	/**
1259	* A per-CPU translation block allocator.
1260	*
1261	* Because of how the IEMTBCACHE uses the lower 6 bits of the TB address to keep
1262	* the length of the collision list, and of course also for cache line alignment
1263	* reasons, the TBs must be allocated with at least 64-byte alignment.
1264	* Memory is there therefore allocated using one of the page aligned allocators.
1265	*
1266	*
1267	* To avoid wasting too much memory, it is allocated piecemeal as needed,
1268	* in chunks (IEMTBCHUNK) of 2 MiB or more. The TB has an 8-bit chunk index
1269	* that enables us to quickly calculate the allocation bitmap position when
1270	* freeing the translation block.
1271	*/
1272	typedef struct IEMTBALLOCATOR
1273	{
1274	/** Magic value (IEMTBALLOCATOR_MAGIC). */
1275	uint32_t uMagic;
1276
1277	#ifdef IEMTB_SIZE_IS_POWER_OF_TWO
1278	/** Mask corresponding to cTbsPerChunk - 1. */
1279	uint32_t fChunkMask;
1280	/** Shift count corresponding to cTbsPerChunk. */
1281	uint8_t cChunkShift;
1282	#else
1283	uint32_t uUnused;
1284	uint8_t bUnused;
1285	#endif
1286	/** Number of chunks we're allowed to allocate. */
1287	uint8_t cMaxChunks;
1288	/** Number of chunks currently populated. */
1289	uint16_t cAllocatedChunks;
1290	/** Number of translation blocks per chunk. */
1291	uint32_t cTbsPerChunk;
1292	/** Chunk size. */
1293	uint32_t cbPerChunk;
1294
1295	/** The maximum number of TBs. */
1296	uint32_t cMaxTbs;
1297	/** Total number of TBs in the populated chunks.
1298	* (cAllocatedChunks * cTbsPerChunk) */
1299	uint32_t cTotalTbs;
1300	/** The current number of TBs in use.
1301	* The number of free TBs: cAllocatedTbs - cInUseTbs; */
1302	uint32_t cInUseTbs;
1303	/** Statistics: Number of the cInUseTbs that are native ones. */
1304	uint32_t cNativeTbs;
1305	/** Statistics: Number of the cInUseTbs that are threaded ones. */
1306	uint32_t cThreadedTbs;
1307
1308	/** Where to start pruning TBs from when we're out.
1309	* See iemTbAllocatorAllocSlow for details. */
1310	uint32_t iPruneFrom;
1311	/** Hint about which bit to start scanning the bitmap from. */
1312	uint32_t iStartHint;
1313	/** Where to start pruning native TBs from when we're out of executable memory.
1314	* See iemTbAllocatorFreeupNativeSpace for details. */
1315	uint32_t iPruneNativeFrom;
1316	uint32_t uPadding;
1317
1318	/** Statistics: Number of TB allocation calls. */
1319	STAMCOUNTER StatAllocs;
1320	/** Statistics: Number of TB free calls. */
1321	STAMCOUNTER StatFrees;
1322	/** Statistics: Time spend pruning. */
1323	STAMPROFILE StatPrune;
1324	/** Statistics: Time spend pruning native TBs. */
1325	STAMPROFILE StatPruneNative;
1326
1327	/** The delayed free list (see iemTbAlloctorScheduleForFree). */
1328	PIEMTB pDelayedFreeHead;
1329
1330	/** Allocation chunks. */
1331	IEMTBCHUNK aChunks[256];
1332
1333	/** Allocation bitmap for all possible chunk chunks. */
1334	RT_FLEXIBLE_ARRAY_EXTENSION
1335	uint64_t bmAllocated[RT_FLEXIBLE_ARRAY];
1336	} IEMTBALLOCATOR;
1337	/** Pointer to a TB allocator. */
1338	typedef struct IEMTBALLOCATOR *PIEMTBALLOCATOR;
1339
1340	/** Magic value for the TB allocator (Emmet Harley Cohen). */
1341	#define IEMTBALLOCATOR_MAGIC UINT32_C(0x19900525)
1342
1343
1344	/**
1345	* A per-CPU translation block cache (hash table).
1346	*
1347	* The hash table is allocated once during IEM initialization and size double
1348	* the max TB count, rounded up to the nearest power of two (so we can use and
1349	* AND mask rather than a rest division when hashing).
1350	*/
1351	typedef struct IEMTBCACHE
1352	{
1353	/** Magic value (IEMTBCACHE_MAGIC). */
1354	uint32_t uMagic;
1355	/** Size of the hash table. This is a power of two. */
1356	uint32_t cHash;
1357	/** The mask corresponding to cHash. */
1358	uint32_t uHashMask;
1359	uint32_t uPadding;
1360
1361	/** @name Statistics
1362	* @{ */
1363	/** Number of collisions ever. */
1364	STAMCOUNTER cCollisions;
1365
1366	/** Statistics: Number of TB lookup misses. */
1367	STAMCOUNTER cLookupMisses;
1368	/** Statistics: Number of TB lookup hits (debug only). */
1369	STAMCOUNTER cLookupHits;
1370	STAMCOUNTER auPadding2[3];
1371	/** Statistics: Collision list length pruning. */
1372	STAMPROFILE StatPrune;
1373	/** @} */
1374
1375	/** The hash table itself.
1376	* @note The lower 6 bits of the pointer is used for keeping the collision
1377	* list length, so we can take action when it grows too long.
1378	* This works because TBs are allocated using a 64 byte (or
1379	* higher) alignment from page aligned chunks of memory, so the lower
1380	* 6 bits of the address will always be zero.
1381	* See IEMTBCACHE_PTR_COUNT_MASK, IEMTBCACHE_PTR_MAKE and friends.
1382	*/
1383	RT_FLEXIBLE_ARRAY_EXTENSION
1384	PIEMTB apHash[RT_FLEXIBLE_ARRAY];
1385	} IEMTBCACHE;
1386	/** Pointer to a per-CPU translation block cahce. */
1387	typedef IEMTBCACHE *PIEMTBCACHE;
1388
1389	/** Magic value for IEMTBCACHE (Johnny O'Neal). */
1390	#define IEMTBCACHE_MAGIC UINT32_C(0x19561010)
1391
1392	/** The collision count mask for IEMTBCACHE::apHash entries. */
1393	#define IEMTBCACHE_PTR_COUNT_MASK ((uintptr_t)0x3f)
1394	/** The max collision count for IEMTBCACHE::apHash entries before pruning. */
1395	#define IEMTBCACHE_PTR_MAX_COUNT ((uintptr_t)0x30)
1396	/** Combine a TB pointer and a collision list length into a value for an
1397	* IEMTBCACHE::apHash entry. */
1398	#define IEMTBCACHE_PTR_MAKE(a_pTb, a_cCount) (PIEMTB)((uintptr_t)(a_pTb) \| (a_cCount))
1399	/** Combine a TB pointer and a collision list length into a value for an
1400	* IEMTBCACHE::apHash entry. */
1401	#define IEMTBCACHE_PTR_GET_TB(a_pHashEntry) (PIEMTB)((uintptr_t)(a_pHashEntry) & ~IEMTBCACHE_PTR_COUNT_MASK)
1402	/** Combine a TB pointer and a collision list length into a value for an
1403	* IEMTBCACHE::apHash entry. */
1404	#define IEMTBCACHE_PTR_GET_COUNT(a_pHashEntry) ((uintptr_t)(a_pHashEntry) & IEMTBCACHE_PTR_COUNT_MASK)
1405
1406	/**
1407	* Calculates the hash table slot for a TB from physical PC address and TB flags.
1408	*/
1409	#define IEMTBCACHE_HASH(a_paCache, a_fTbFlags, a_GCPhysPc) \
1410	IEMTBCACHE_HASH_NO_KEY_MASK(a_paCache, (a_fTbFlags) & IEMTB_F_KEY_MASK, a_GCPhysPc)
1411
1412	/**
1413	* Calculates the hash table slot for a TB from physical PC address and TB
1414	* flags, ASSUMING the caller has applied IEMTB_F_KEY_MASK to @a a_fTbFlags.
1415	*/
1416	#define IEMTBCACHE_HASH_NO_KEY_MASK(a_paCache, a_fTbFlags, a_GCPhysPc) \
1417	(((uint32_t)(a_GCPhysPc) ^ (a_fTbFlags)) & (a_paCache)->uHashMask)
1418
1419
1420	/** @name IEMBRANCHED_F_XXX - Branched indicator (IEMCPU::fTbBranched).
1421	*
1422	* These flags parallels the main IEM_CIMPL_F_BRANCH_XXX flags.
1423	*
1424	* @{ */
1425	/** Value if no branching happened recently. */
1426	#define IEMBRANCHED_F_NO UINT8_C(0x00)
1427	/** Flag set if direct branch, clear if absolute or indirect. */
1428	#define IEMBRANCHED_F_DIRECT UINT8_C(0x01)
1429	/** Flag set if indirect branch, clear if direct or relative. */
1430	#define IEMBRANCHED_F_INDIRECT UINT8_C(0x02)
1431	/** Flag set if relative branch, clear if absolute or indirect. */
1432	#define IEMBRANCHED_F_RELATIVE UINT8_C(0x04)
1433	/** Flag set if conditional branch, clear if unconditional. */
1434	#define IEMBRANCHED_F_CONDITIONAL UINT8_C(0x08)
1435	/** Flag set if it's a far branch. */
1436	#define IEMBRANCHED_F_FAR UINT8_C(0x10)
1437	/** Flag set if the stack pointer is modified. */
1438	#define IEMBRANCHED_F_STACK UINT8_C(0x20)
1439	/** Flag set if the stack pointer and (maybe) the stack segment are modified. */
1440	#define IEMBRANCHED_F_STACK_FAR UINT8_C(0x40)
1441	/** Flag set (by IEM_MC_REL_JMP_XXX) if it's a zero bytes relative jump. */
1442	#define IEMBRANCHED_F_ZERO UINT8_C(0x80)
1443	/** @} */
1444
1445
1446	/**
1447	* The per-CPU IEM state.
1448	*/
1449	typedef struct IEMCPU
1450	{
1451	/** Info status code that needs to be propagated to the IEM caller.
1452	* This cannot be passed internally, as it would complicate all success
1453	* checks within the interpreter making the code larger and almost impossible
1454	* to get right. Instead, we'll store status codes to pass on here. Each
1455	* source of these codes will perform appropriate sanity checks. */
1456	int32_t rcPassUp; /* 0x00 */
1457	/** Execution flag, IEM_F_XXX. */
1458	uint32_t fExec; /* 0x04 */
1459
1460	/** @name Decoder state.
1461	* @{ */
1462	#ifdef IEM_WITH_CODE_TLB
1463	/** The offset of the next instruction byte. */
1464	uint32_t offInstrNextByte; /* 0x08 */
1465	/** The number of bytes available at pbInstrBuf for the current instruction.
1466	* This takes the max opcode length into account so that doesn't need to be
1467	* checked separately. */
1468	uint32_t cbInstrBuf; /* 0x0c */
1469	/** Pointer to the page containing RIP, user specified buffer or abOpcode.
1470	* This can be NULL if the page isn't mappable for some reason, in which
1471	* case we'll do fallback stuff.
1472	*
1473	* If we're executing an instruction from a user specified buffer,
1474	* IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
1475	* aligned pointer but pointer to the user data.
1476	*
1477	* For instructions crossing pages, this will start on the first page and be
1478	* advanced to the next page by the time we've decoded the instruction. This
1479	* therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
1480	*/
1481	uint8_t const pbInstrBuf; / 0x10 */
1482	# if ARCH_BITS == 32
1483	uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
1484	# endif
1485	/** The program counter corresponding to pbInstrBuf.
1486	* This is set to a non-canonical address when we need to invalidate it. */
1487	uint64_t uInstrBufPc; /* 0x18 */
1488	/** The guest physical address corresponding to pbInstrBuf. */
1489	RTGCPHYS GCPhysInstrBuf; /* 0x20 */
1490	/** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
1491	* This takes the CS segment limit into account.
1492	* @note Set to zero when the code TLB is flushed to trigger TLB reload. */
1493	uint16_t cbInstrBufTotal; /* 0x28 */
1494	# ifndef IEM_WITH_OPAQUE_DECODER_STATE
1495	/** Offset into pbInstrBuf of the first byte of the current instruction.
1496	* Can be negative to efficiently handle cross page instructions. */
1497	int16_t offCurInstrStart; /* 0x2a */
1498
1499	/** The prefix mask (IEM_OP_PRF_XXX). */
1500	uint32_t fPrefixes; /* 0x2c */
1501	/** The extra REX ModR/M register field bit (REX.R << 3). */
1502	uint8_t uRexReg; /* 0x30 */
1503	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
1504	* (REX.B << 3). */
1505	uint8_t uRexB; /* 0x31 */
1506	/** The extra REX SIB index field bit (REX.X << 3). */
1507	uint8_t uRexIndex; /* 0x32 */
1508
1509	/** The effective segment register (X86_SREG_XXX). */
1510	uint8_t iEffSeg; /* 0x33 */
1511
1512	/** The offset of the ModR/M byte relative to the start of the instruction. */
1513	uint8_t offModRm; /* 0x34 */
1514
1515	# ifdef IEM_WITH_CODE_TLB_AND_OPCODE_BUF
1516	/** The current offset into abOpcode. */
1517	uint8_t offOpcode; /* 0x35 */
1518	# else
1519	uint8_t bUnused; /* 0x35 */
1520	# endif
1521	# else /* IEM_WITH_OPAQUE_DECODER_STATE */
1522	uint8_t abOpaqueDecoderPart1[0x36 - 0x2a];
1523	# endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1524
1525	#else /* !IEM_WITH_CODE_TLB */
1526	# ifndef IEM_WITH_OPAQUE_DECODER_STATE
1527	/** The size of what has currently been fetched into abOpcode. */
1528	uint8_t cbOpcode; /* 0x08 */
1529	/** The current offset into abOpcode. */
1530	uint8_t offOpcode; /* 0x09 */
1531	/** The offset of the ModR/M byte relative to the start of the instruction. */
1532	uint8_t offModRm; /* 0x0a */
1533
1534	/** The effective segment register (X86_SREG_XXX). */
1535	uint8_t iEffSeg; /* 0x0b */
1536
1537	/** The prefix mask (IEM_OP_PRF_XXX). */
1538	uint32_t fPrefixes; /* 0x0c */
1539	/** The extra REX ModR/M register field bit (REX.R << 3). */
1540	uint8_t uRexReg; /* 0x10 */
1541	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
1542	* (REX.B << 3). */
1543	uint8_t uRexB; /* 0x11 */
1544	/** The extra REX SIB index field bit (REX.X << 3). */
1545	uint8_t uRexIndex; /* 0x12 */
1546
1547	# else /* IEM_WITH_OPAQUE_DECODER_STATE */
1548	uint8_t abOpaqueDecoderPart1[0x13 - 0x08];
1549	# endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1550	#endif /* !IEM_WITH_CODE_TLB */
1551
1552	#ifndef IEM_WITH_OPAQUE_DECODER_STATE
1553	/** The effective operand mode. */
1554	IEMMODE enmEffOpSize; /* 0x36, 0x13 */
1555	/** The default addressing mode. */
1556	IEMMODE enmDefAddrMode; /* 0x37, 0x14 */
1557	/** The effective addressing mode. */
1558	IEMMODE enmEffAddrMode; /* 0x38, 0x15 */
1559	/** The default operand mode. */
1560	IEMMODE enmDefOpSize; /* 0x39, 0x16 */
1561
1562	/** Prefix index (VEX.pp) for two byte and three byte tables. */
1563	uint8_t idxPrefix; /* 0x3a, 0x17 */
1564	/** 3rd VEX/EVEX/XOP register.
1565	* Please use IEM_GET_EFFECTIVE_VVVV to access. */
1566	uint8_t uVex3rdReg; /* 0x3b, 0x18 */
1567	/** The VEX/EVEX/XOP length field. */
1568	uint8_t uVexLength; /* 0x3c, 0x19 */
1569	/** Additional EVEX stuff. */
1570	uint8_t fEvexStuff; /* 0x3d, 0x1a */
1571
1572	# ifndef IEM_WITH_CODE_TLB
1573	/** Explicit alignment padding. */
1574	uint8_t abAlignment2a[1]; /* 0x1b */
1575	# endif
1576	/** The FPU opcode (FOP). */
1577	uint16_t uFpuOpcode; /* 0x3e, 0x1c */
1578	# ifndef IEM_WITH_CODE_TLB
1579	/** Explicit alignment padding. */
1580	uint8_t abAlignment2b[2]; /* 0x1e */
1581	# endif
1582
1583	/** The opcode bytes. */
1584	uint8_t abOpcode[15]; /* 0x40, 0x20 */
1585	/** Explicit alignment padding. */
1586	# ifdef IEM_WITH_CODE_TLB
1587	//uint8_t abAlignment2c[0x4f - 0x4f]; /* 0x4f */
1588	# else
1589	uint8_t abAlignment2c[0x4f - 0x2f]; /* 0x2f */
1590	# endif
1591
1592	#else /* IEM_WITH_OPAQUE_DECODER_STATE */
1593	# ifdef IEM_WITH_CODE_TLB
1594	uint8_t abOpaqueDecoderPart2[0x4f - 0x36];
1595	# else
1596	uint8_t abOpaqueDecoderPart2[0x4f - 0x13];
1597	# endif
1598	#endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1599	/** @} */
1600
1601
1602	/** The number of active guest memory mappings. */
1603	uint8_t cActiveMappings; /* 0x4f, 0x4f */
1604
1605	/** Records for tracking guest memory mappings. */
1606	struct
1607	{
1608	/** The address of the mapped bytes. */
1609	R3R0PTRTYPE(void *) pv;
1610	/** The access flags (IEM_ACCESS_XXX).
1611	* IEM_ACCESS_INVALID if the entry is unused. */
1612	uint32_t fAccess;
1613	#if HC_ARCH_BITS == 64
1614	uint32_t u32Alignment4; /*< Alignment padding. /
1615	#endif
1616	} aMemMappings[3]; /* 0x50 LB 0x30 */
1617
1618	/** Locking records for the mapped memory. */
1619	union
1620	{
1621	PGMPAGEMAPLOCK Lock;
1622	uint64_t au64Padding[2];
1623	} aMemMappingLocks[3]; /* 0x80 LB 0x30 */
1624
1625	/** Bounce buffer info.
1626	* This runs in parallel to aMemMappings. */
1627	struct
1628	{
1629	/** The physical address of the first byte. */
1630	RTGCPHYS GCPhysFirst;
1631	/** The physical address of the second page. */
1632	RTGCPHYS GCPhysSecond;
1633	/** The number of bytes in the first page. */
1634	uint16_t cbFirst;
1635	/** The number of bytes in the second page. */
1636	uint16_t cbSecond;
1637	/** Whether it's unassigned memory. */
1638	bool fUnassigned;
1639	/** Explicit alignment padding. */
1640	bool afAlignment5[3];
1641	} aMemBbMappings[3]; /* 0xb0 LB 0x48 */
1642
1643	/** The flags of the current exception / interrupt. */
1644	uint32_t fCurXcpt; /* 0xf8 */
1645	/** The current exception / interrupt. */
1646	uint8_t uCurXcpt; /* 0xfc */
1647	/** Exception / interrupt recursion depth. */
1648	int8_t cXcptRecursions; /* 0xfb */
1649
1650	/** The next unused mapping index.
1651	* @todo try find room for this up with cActiveMappings. */
1652	uint8_t iNextMapping; /* 0xfd */
1653	uint8_t abAlignment7[1];
1654
1655	/** Bounce buffer storage.
1656	* This runs in parallel to aMemMappings and aMemBbMappings. */
1657	struct
1658	{
1659	uint8_t ab[512];
1660	} aBounceBuffers[3]; /* 0x100 LB 0x600 */
1661
1662
1663	/** Pointer set jump buffer - ring-3 context. */
1664	R3PTRTYPE(jmp_buf *) pJmpBufR3;
1665	/** Pointer set jump buffer - ring-0 context. */
1666	R0PTRTYPE(jmp_buf *) pJmpBufR0;
1667
1668	/** @todo Should move this near @a fCurXcpt later. */
1669	/** The CR2 for the current exception / interrupt. */
1670	uint64_t uCurXcptCr2;
1671	/** The error code for the current exception / interrupt. */
1672	uint32_t uCurXcptErr;
1673
1674	/** @name Statistics
1675	* @{ */
1676	/** The number of instructions we've executed. */
1677	uint32_t cInstructions;
1678	/** The number of potential exits. */
1679	uint32_t cPotentialExits;
1680	/** The number of bytes data or stack written (mostly for IEMExecOneEx).
1681	* This may contain uncommitted writes. */
1682	uint32_t cbWritten;
1683	/** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
1684	uint32_t cRetInstrNotImplemented;
1685	/** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
1686	uint32_t cRetAspectNotImplemented;
1687	/** Counts informational statuses returned (other than VINF_SUCCESS). */
1688	uint32_t cRetInfStatuses;
1689	/** Counts other error statuses returned. */
1690	uint32_t cRetErrStatuses;
1691	/** Number of times rcPassUp has been used. */
1692	uint32_t cRetPassUpStatus;
1693	/** Number of times RZ left with instruction commit pending for ring-3. */
1694	uint32_t cPendingCommit;
1695	/** Number of misaligned (host sense) atomic instruction accesses. */
1696	uint32_t cMisalignedAtomics;
1697	/** Number of long jumps. */
1698	uint32_t cLongJumps;
1699	/** @} */
1700
1701	/** @name Target CPU information.
1702	* @{ */
1703	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
1704	/** The target CPU. */
1705	uint8_t uTargetCpu;
1706	#else
1707	uint8_t bTargetCpuPadding;
1708	#endif
1709	/** For selecting assembly works matching the target CPU EFLAGS behaviour, see
1710	* IEMTARGETCPU_EFL_BEHAVIOR_XXX for values, with the 1st entry for when no
1711	* native host support and the 2nd for when there is.
1712	*
1713	* The two values are typically indexed by a g_CpumHostFeatures bit.
1714	*
1715	* This is for instance used for the BSF & BSR instructions where AMD and
1716	* Intel CPUs produce different EFLAGS. */
1717	uint8_t aidxTargetCpuEflFlavour[2];
1718
1719	/** The CPU vendor. */
1720	CPUMCPUVENDOR enmCpuVendor;
1721	/** @} */
1722
1723	/** @name Host CPU information.
1724	* @{ */
1725	/** The CPU vendor. */
1726	CPUMCPUVENDOR enmHostCpuVendor;
1727	/** @} */
1728
1729	/** Counts RDMSR \#GP(0) LogRel(). */
1730	uint8_t cLogRelRdMsr;
1731	/** Counts WRMSR \#GP(0) LogRel(). */
1732	uint8_t cLogRelWrMsr;
1733	/** Alignment padding. */
1734	uint8_t abAlignment9[42];
1735
1736	/** @name Recompilation
1737	* @{ */
1738	/** Pointer to the current translation block.
1739	* This can either be one being executed or one being compiled. */
1740	R3PTRTYPE(PIEMTB) pCurTbR3;
1741	#ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
1742	/** Frame pointer for the last native TB to execute. */
1743	R3PTRTYPE(void *) pvTbFramePointerR3;
1744	#else
1745	R3PTRTYPE(void *) pvUnusedR3;
1746	#endif
1747	/** Fixed TB used for threaded recompilation.
1748	* This is allocated once with maxed-out sizes and re-used afterwards. */
1749	R3PTRTYPE(PIEMTB) pThrdCompileTbR3;
1750	/** Pointer to the ring-3 TB cache for this EMT. */
1751	R3PTRTYPE(PIEMTBCACHE) pTbCacheR3;
1752	/** The PC (RIP) at the start of pCurTbR3/pCurTbR0.
1753	* The TBs are based on physical addresses, so this is needed to correleated
1754	* RIP to opcode bytes stored in the TB (AMD-V / VT-x). */
1755	uint64_t uCurTbStartPc;
1756	/** Number of threaded TBs executed. */
1757	uint64_t cTbExecThreaded;
1758	/** Number of native TBs executed. */
1759	uint64_t cTbExecNative;
1760	/** Whether we need to check the opcode bytes for the current instruction.
1761	* This is set by a previous instruction if it modified memory or similar. */
1762	bool fTbCheckOpcodes;
1763	/** Indicates whether and how we just branched - IEMBRANCHED_F_XXX. */
1764	uint8_t fTbBranched;
1765	/** Set when GCPhysInstrBuf is updated because of a page crossing. */
1766	bool fTbCrossedPage;
1767	/** Whether to end the current TB. */
1768	bool fEndTb;
1769	/** Number of instructions before we need emit an IRQ check call again.
1770	* This helps making sure we don't execute too long w/o checking for
1771	* interrupts and immediately following instructions that may enable
1772	* interrupts (e.g. POPF, IRET, STI). With STI an additional hack is
1773	* required to make sure we check following the next instruction as well, see
1774	* fTbCurInstrIsSti. */
1775	uint8_t cInstrTillIrqCheck;
1776	/** Indicates that the current instruction is an STI. This is set by the
1777	* iemCImpl_sti code and subsequently cleared by the recompiler. */
1778	bool fTbCurInstrIsSti;
1779	/** The size of the IEMTB::pabOpcodes allocation in pThrdCompileTbR3. */
1780	uint16_t cbOpcodesAllocated;
1781	/** The current instruction number in a native TB.
1782	* This is set by code that may trigger an unexpected TB exit (throw/longjmp)
1783	* and will be picked up by the TB execution loop. Only used when
1784	* IEMNATIVE_WITH_INSTRUCTION_COUNTING is defined. */
1785	uint8_t idxTbCurInstr;
1786	/** Spaced reserved for recompiler data / alignment. */
1787	bool afRecompilerStuff1[3];
1788	/** The virtual sync time at the last timer poll call. */
1789	uint32_t msRecompilerPollNow;
1790	/** The IEM_CIMPL_F_XXX mask for the current instruction. */
1791	uint32_t fTbCurInstr;
1792	/** The IEM_CIMPL_F_XXX mask for the previous instruction. */
1793	uint32_t fTbPrevInstr;
1794	/** Previous GCPhysInstrBuf value - only valid if fTbCrossedPage is set. */
1795	RTGCPHYS GCPhysInstrBufPrev;
1796	/** Strict: Tracking skipped EFLAGS calculations. Any bits set here are
1797	* currently not up to date in EFLAGS. */
1798	uint32_t fSkippingEFlags;
1799	uint32_t au32Padding[1];
1800	/** Pointer to the ring-3 TB allocator for this EMT. */
1801	R3PTRTYPE(PIEMTBALLOCATOR) pTbAllocatorR3;
1802	/** Pointer to the ring-3 executable memory allocator for this EMT. */
1803	R3PTRTYPE(struct IEMEXECMEMALLOCATOR *) pExecMemAllocatorR3;
1804	/** Pointer to the native recompiler state for ring-3. */
1805	R3PTRTYPE(struct IEMRECOMPILERSTATE *) pNativeRecompilerStateR3;
1806
1807	/** Statistics: Times TB execution was broken off before reaching the end. */
1808	STAMCOUNTER StatTbExecBreaks;
1809	/** Statistics: Times BltIn_CheckIrq breaks out of the TB. */
1810	STAMCOUNTER StatCheckIrqBreaks;
1811	/** Statistics: Times BltIn_CheckMode breaks out of the TB. */
1812	STAMCOUNTER StatCheckModeBreaks;
1813	/** Statistics: Times a post jump target check missed and had to find new TB. */
1814	STAMCOUNTER StatCheckBranchMisses;
1815	/** Statistics: Times a jump or page crossing required a TB with CS.LIM checking. */
1816	STAMCOUNTER StatCheckNeedCsLimChecking;
1817	/** Native TB statistics: Number of fully recompiled TBs. */
1818	STAMCOUNTER StatNativeFullyRecompiledTbs;
1819	/** Threaded TB statistics: Number of instructions per TB. */
1820	STAMPROFILE StatTbThreadedInstr;
1821	/** Threaded TB statistics: Number of calls per TB. */
1822	STAMPROFILE StatTbThreadedCalls;
1823	/** Native TB statistics: Native code size per TB. */
1824	STAMPROFILE StatTbNativeCode;
1825	/** Native TB statistics: Profiling native recompilation. */
1826	STAMPROFILE StatNativeRecompilation;
1827	/** Native TB statistics: Number of calls per TB that were recompiled properly. */
1828	STAMPROFILE StatNativeCallsRecompiled;
1829	/** Native TB statistics: Number of threaded calls per TB that weren't recompiled. */
1830	STAMPROFILE StatNativeCallsThreaded;
1831	/** Native recompiled execution: TLB hits for data fetches. */
1832	STAMCOUNTER StatNativeTlbHitsForFetch;
1833	/** Native recompiled execution: TLB hits for data stores. */
1834	STAMCOUNTER StatNativeTlbHitsForStore;
1835	/** Native recompiled execution: TLB hits for stack accesses. */
1836	STAMCOUNTER StatNativeTlbHitsForStack;
1837	/** Native recompiled execution: TLB hits for mapped accesses. */
1838	STAMCOUNTER StatNativeTlbHitsForMapped;
1839	/** Native recompiled execution: Code TLB misses for new page. */
1840	STAMCOUNTER StatNativeCodeTlbMissesNewPage;
1841	/** Native recompiled execution: Code TLB hits for new page. */
1842	STAMCOUNTER StatNativeCodeTlbHitsForNewPage;
1843	/** Native recompiled execution: Code TLB misses for new page with offset. */
1844	STAMCOUNTER StatNativeCodeTlbMissesNewPageWithOffset;
1845	/** Native recompiled execution: Code TLB hits for new page with offset. */
1846	STAMCOUNTER StatNativeCodeTlbHitsForNewPageWithOffset;
1847
1848	/** Native recompiler: Number of calls to iemNativeRegAllocFindFree. */
1849	STAMCOUNTER StatNativeRegFindFree;
1850	/** Native recompiler: Number of times iemNativeRegAllocFindFree needed
1851	* to free a variable. */
1852	STAMCOUNTER StatNativeRegFindFreeVar;
1853	/** Native recompiler: Number of times iemNativeRegAllocFindFree did
1854	* not need to free any variables. */
1855	STAMCOUNTER StatNativeRegFindFreeNoVar;
1856	/** Native recompiler: Liveness info freed shadowed guest registers in
1857	* iemNativeRegAllocFindFree. */
1858	STAMCOUNTER StatNativeRegFindFreeLivenessUnshadowed;
1859	/** Native recompiler: Liveness info helped with the allocation in
1860	* iemNativeRegAllocFindFree. */
1861	STAMCOUNTER StatNativeRegFindFreeLivenessHelped;
1862
1863	/** Native recompiler: Number of times status flags calc has been skipped. */
1864	STAMCOUNTER StatNativeEflSkippedArithmetic;
1865	/** Native recompiler: Number of times status flags calc has been skipped. */
1866	STAMCOUNTER StatNativeEflSkippedLogical;
1867
1868	/** Native recompiler: Number of opportunities to skip EFLAGS.CF updating. */
1869	STAMCOUNTER StatNativeLivenessEflCfSkippable;
1870	/** Native recompiler: Number of opportunities to skip EFLAGS.PF updating. */
1871	STAMCOUNTER StatNativeLivenessEflPfSkippable;
1872	/** Native recompiler: Number of opportunities to skip EFLAGS.AF updating. */
1873	STAMCOUNTER StatNativeLivenessEflAfSkippable;
1874	/** Native recompiler: Number of opportunities to skip EFLAGS.ZF updating. */
1875	STAMCOUNTER StatNativeLivenessEflZfSkippable;
1876	/** Native recompiler: Number of opportunities to skip EFLAGS.SF updating. */
1877	STAMCOUNTER StatNativeLivenessEflSfSkippable;
1878	/** Native recompiler: Number of opportunities to skip EFLAGS.OF updating. */
1879	STAMCOUNTER StatNativeLivenessEflOfSkippable;
1880	/** Native recompiler: Number of required EFLAGS.CF updates. */
1881	STAMCOUNTER StatNativeLivenessEflCfRequired;
1882	/** Native recompiler: Number of required EFLAGS.PF updates. */
1883	STAMCOUNTER StatNativeLivenessEflPfRequired;
1884	/** Native recompiler: Number of required EFLAGS.AF updates. */
1885	STAMCOUNTER StatNativeLivenessEflAfRequired;
1886	/** Native recompiler: Number of required EFLAGS.ZF updates. */
1887	STAMCOUNTER StatNativeLivenessEflZfRequired;
1888	/** Native recompiler: Number of required EFLAGS.SF updates. */
1889	STAMCOUNTER StatNativeLivenessEflSfRequired;
1890	/** Native recompiler: Number of required EFLAGS.OF updates. */
1891	STAMCOUNTER StatNativeLivenessEflOfRequired;
1892	/** Native recompiler: Number of potentially delayable EFLAGS.CF updates. */
1893	STAMCOUNTER StatNativeLivenessEflCfDelayable;
1894	/** Native recompiler: Number of potentially delayable EFLAGS.PF updates. */
1895	STAMCOUNTER StatNativeLivenessEflPfDelayable;
1896	/** Native recompiler: Number of potentially delayable EFLAGS.AF updates. */
1897	STAMCOUNTER StatNativeLivenessEflAfDelayable;
1898	/** Native recompiler: Number of potentially delayable EFLAGS.ZF updates. */
1899	STAMCOUNTER StatNativeLivenessEflZfDelayable;
1900	/** Native recompiler: Number of potentially delayable EFLAGS.SF updates. */
1901	STAMCOUNTER StatNativeLivenessEflSfDelayable;
1902	/** Native recompiler: Number of potentially delayable EFLAGS.OF updates. */
1903	STAMCOUNTER StatNativeLivenessEflOfDelayable;
1904
1905	/** Native recompiler: Number of potential PC updates in total. */
1906	STAMCOUNTER StatNativePcUpdateTotal;
1907	/** Native recompiler: Number of PC updates which could be delayed. */
1908	STAMCOUNTER StatNativePcUpdateDelayed;
1909
1910	#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
1911	/** Native recompiler: Number of calls to iemNativeSimdRegAllocFindFree. */
1912	STAMCOUNTER StatNativeSimdRegFindFree;
1913	/** Native recompiler: Number of times iemNativeSimdRegAllocFindFree needed
1914	* to free a variable. */
1915	STAMCOUNTER StatNativeSimdRegFindFreeVar;
1916	/** Native recompiler: Number of times iemNativeSimdRegAllocFindFree did
1917	* not need to free any variables. */
1918	STAMCOUNTER StatNativeSimdRegFindFreeNoVar;
1919	/** Native recompiler: Liveness info freed shadowed guest registers in
1920	* iemNativeSimdRegAllocFindFree. */
1921	STAMCOUNTER StatNativeSimdRegFindFreeLivenessUnshadowed;
1922	/** Native recompiler: Liveness info helped with the allocation in
1923	* iemNativeSimdRegAllocFindFree. */
1924	STAMCOUNTER StatNativeSimdRegFindFreeLivenessHelped;
1925
1926	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() checks. */
1927	STAMCOUNTER StatNativeMaybeDeviceNotAvailXcptCheckPotential;
1928	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() checks. */
1929	STAMCOUNTER StatNativeMaybeSseXcptCheckPotential;
1930	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() checks. */
1931	STAMCOUNTER StatNativeMaybeAvxXcptCheckPotential;
1932
1933	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() checks omitted. */
1934	STAMCOUNTER StatNativeMaybeDeviceNotAvailXcptCheckOmitted;
1935	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() checks omitted. */
1936	STAMCOUNTER StatNativeMaybeSseXcptCheckOmitted;
1937	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() checks omitted. */
1938	STAMCOUNTER StatNativeMaybeAvxXcptCheckOmitted;
1939	#endif
1940
1941	uint64_t au64Padding[5];
1942	/** @} */
1943
1944	/** Data TLB.
1945	* @remarks Must be 64-byte aligned. */
1946	IEMTLB DataTlb;
1947	/** Instruction TLB.
1948	* @remarks Must be 64-byte aligned. */
1949	IEMTLB CodeTlb;
1950
1951	/** Exception statistics. */
1952	STAMCOUNTER aStatXcpts[32];
1953	/** Interrupt statistics. */
1954	uint32_t aStatInts[256];
1955
1956	#if defined(VBOX_WITH_STATISTICS) && !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
1957	/** Instruction statistics for ring-0/raw-mode. */
1958	IEMINSTRSTATS StatsRZ;
1959	/** Instruction statistics for ring-3. */
1960	IEMINSTRSTATS StatsR3;
1961	# ifdef VBOX_WITH_IEM_RECOMPILER
1962	/** Statistics per threaded function call.
1963	* Updated by both the threaded and native recompilers. */
1964	uint32_t acThreadedFuncStats[0x5000 /20480/];
1965	# endif
1966	#endif
1967	} IEMCPU;
1968	AssertCompileMemberOffset(IEMCPU, cActiveMappings, 0x4f);
1969	AssertCompileMemberAlignment(IEMCPU, aMemMappings, 16);
1970	AssertCompileMemberAlignment(IEMCPU, aMemMappingLocks, 16);
1971	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 64);
1972	AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
1973	AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
1974
1975	/** Pointer to the per-CPU IEM state. */
1976	typedef IEMCPU *PIEMCPU;
1977	/** Pointer to the const per-CPU IEM state. */
1978	typedef IEMCPU const *PCIEMCPU;
1979
1980
1981	/** @def IEM_GET_CTX
1982	* Gets the guest CPU context for the calling EMT.
1983	* @returns PCPUMCTX
1984	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1985	*/
1986	#define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
1987
1988	/** @def IEM_CTX_ASSERT
1989	* Asserts that the @a a_fExtrnMbz is present in the CPU context.
1990	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
1991	* @param a_fExtrnMbz The mask of CPUMCTX_EXTRN_XXX flags that must be zero.
1992	*/
1993	#define IEM_CTX_ASSERT(a_pVCpu, a_fExtrnMbz) \
1994	AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
1995	("fExtrn=%#RX64 & fExtrnMbz=%#RX64 -> %#RX64\n", \
1996	(a_pVCpu)->cpum.GstCtx.fExtrn, (a_fExtrnMbz), (a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz) ))
1997
1998	/** @def IEM_CTX_IMPORT_RET
1999	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
2000	*
2001	* Will call the keep to import the bits as needed.
2002	*
2003	* Returns on import failure.
2004	*
2005	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2006	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
2007	*/
2008	#define IEM_CTX_IMPORT_RET(a_pVCpu, a_fExtrnImport) \
2009	do { \
2010	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
2011	{ /* likely */ } \
2012	else \
2013	{ \
2014	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
2015	AssertRCReturn(rcCtxImport, rcCtxImport); \
2016	} \
2017	} while (0)
2018
2019	/** @def IEM_CTX_IMPORT_NORET
2020	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
2021	*
2022	* Will call the keep to import the bits as needed.
2023	*
2024	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2025	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
2026	*/
2027	#define IEM_CTX_IMPORT_NORET(a_pVCpu, a_fExtrnImport) \
2028	do { \
2029	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
2030	{ /* likely */ } \
2031	else \
2032	{ \
2033	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
2034	AssertLogRelRC(rcCtxImport); \
2035	} \
2036	} while (0)
2037
2038	/** @def IEM_CTX_IMPORT_JMP
2039	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
2040	*
2041	* Will call the keep to import the bits as needed.
2042	*
2043	* Jumps on import failure.
2044	*
2045	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2046	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
2047	*/
2048	#define IEM_CTX_IMPORT_JMP(a_pVCpu, a_fExtrnImport) \
2049	do { \
2050	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
2051	{ /* likely */ } \
2052	else \
2053	{ \
2054	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
2055	AssertRCStmt(rcCtxImport, IEM_DO_LONGJMP(pVCpu, rcCtxImport)); \
2056	} \
2057	} while (0)
2058
2059
2060
2061	/** @def IEM_GET_TARGET_CPU
2062	* Gets the current IEMTARGETCPU value.
2063	* @returns IEMTARGETCPU value.
2064	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2065	*/
2066	#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
2067	# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
2068	#else
2069	# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
2070	#endif
2071
2072	/** @def IEM_GET_INSTR_LEN
2073	* Gets the instruction length. */
2074	#ifdef IEM_WITH_CODE_TLB
2075	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
2076	#else
2077	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
2078	#endif
2079
2080	/** @def IEM_TRY_SETJMP
2081	* Wrapper around setjmp / try, hiding all the ugly differences.
2082	*
2083	* @note Use with extreme care as this is a fragile macro.
2084	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2085	* @param a_rcTarget The variable that should receive the status code in case
2086	* of a longjmp/throw.
2087	*/
2088	/** @def IEM_TRY_SETJMP_AGAIN
2089	* For when setjmp / try is used again in the same variable scope as a previous
2090	* IEM_TRY_SETJMP invocation.
2091	*/
2092	/** @def IEM_CATCH_LONGJMP_BEGIN
2093	* Start wrapper for catch / setjmp-else.
2094	*
2095	* This will set up a scope.
2096	*
2097	* @note Use with extreme care as this is a fragile macro.
2098	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2099	* @param a_rcTarget The variable that should receive the status code in case
2100	* of a longjmp/throw.
2101	*/
2102	/** @def IEM_CATCH_LONGJMP_END
2103	* End wrapper for catch / setjmp-else.
2104	*
2105	* This will close the scope set up by IEM_CATCH_LONGJMP_BEGIN and clean up the
2106	* state.
2107	*
2108	* @note Use with extreme care as this is a fragile macro.
2109	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2110	*/
2111	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
2112	# ifdef IEM_WITH_THROW_CATCH
2113	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
2114	a_rcTarget = VINF_SUCCESS; \
2115	try
2116	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
2117	IEM_TRY_SETJMP(a_pVCpu, a_rcTarget)
2118	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
2119	catch (int rcThrown) \
2120	{ \
2121	a_rcTarget = rcThrown
2122	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
2123	} \
2124	((void)0)
2125	# else /* !IEM_WITH_THROW_CATCH */
2126	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
2127	jmp_buf JmpBuf; \
2128	jmp_buf * volatile pSavedJmpBuf = (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf); \
2129	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
2130	if ((rcStrict = setjmp(JmpBuf)) == 0)
2131	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
2132	pSavedJmpBuf = (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf); \
2133	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
2134	if ((rcStrict = setjmp(JmpBuf)) == 0)
2135	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
2136	else \
2137	{ \
2138	((void)0)
2139	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
2140	} \
2141	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = pSavedJmpBuf
2142	# endif /* !IEM_WITH_THROW_CATCH */
2143	#endif /* IEM_WITH_SETJMP */
2144
2145
2146	/**
2147	* Shared per-VM IEM data.
2148	*/
2149	typedef struct IEM
2150	{
2151	/** The VMX APIC-access page handler type. */
2152	PGMPHYSHANDLERTYPE hVmxApicAccessPage;
2153	#ifndef VBOX_WITHOUT_CPUID_HOST_CALL
2154	/** Set if the CPUID host call functionality is enabled. */
2155	bool fCpuIdHostCall;
2156	#endif
2157	} IEM;
2158
2159
2160
2161	/** @name IEM_ACCESS_XXX - Access details.
2162	* @{ */
2163	#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
2164	#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
2165	#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
2166	#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
2167	#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
2168	#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
2169	#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
2170	#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
2171	#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
2172	#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
2173	/** The writes are partial, so if initialize the bounce buffer with the
2174	* orignal RAM content. */
2175	#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
2176	/** Used in aMemMappings to indicate that the entry is bounce buffered. */
2177	#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
2178	/** Bounce buffer with ring-3 write pending, first page. */
2179	#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
2180	/** Bounce buffer with ring-3 write pending, second page. */
2181	#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
2182	/** Not locked, accessed via the TLB. */
2183	#define IEM_ACCESS_NOT_LOCKED UINT32_C(0x00001000)
2184	/** Atomic access.
2185	* This enables special alignment checks and the VINF_EM_EMULATE_SPLIT_LOCK
2186	* fallback for misaligned stuff. See @bugref{10547}. */
2187	#define IEM_ACCESS_ATOMIC UINT32_C(0x00002000)
2188	/** Valid bit mask. */
2189	#define IEM_ACCESS_VALID_MASK UINT32_C(0x00003fff)
2190	/** Shift count for the TLB flags (upper word). */
2191	#define IEM_ACCESS_SHIFT_TLB_FLAGS 16
2192
2193	/** Atomic read+write data alias. */
2194	#define IEM_ACCESS_DATA_ATOMIC (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA \| IEM_ACCESS_ATOMIC)
2195	/** Read+write data alias. */
2196	#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
2197	/** Write data alias. */
2198	#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
2199	/** Read data alias. */
2200	#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_DATA)
2201	/** Instruction fetch alias. */
2202	#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_WHAT_CODE)
2203	/** Stack write alias. */
2204	#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
2205	/** Stack read alias. */
2206	#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_STACK)
2207	/** Stack read+write alias. */
2208	#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
2209	/** Read system table alias. */
2210	#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_SYS)
2211	/** Read+write system table alias. */
2212	#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_SYS)
2213	/** @} */
2214
2215	/** @name Prefix constants (IEMCPU::fPrefixes)
2216	* @{ */
2217	#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /*< CS segment prefix (0x2e). /
2218	#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /*< SS segment prefix (0x36). /
2219	#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /*< DS segment prefix (0x3e). /
2220	#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /*< ES segment prefix (0x26). /
2221	#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /*< FS segment prefix (0x64). /
2222	#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /*< GS segment prefix (0x65). /
2223	#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
2224
2225	#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /*< Operand size prefix (0x66). /
2226	#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /*< REX.W prefix (0x48-0x4f). /
2227	#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /*< Address size prefix (0x67). /
2228
2229	#define IEM_OP_PRF_LOCK RT_BIT_32(16) /*< Lock prefix (0xf0). /
2230	#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /*< Repeat-not-zero prefix (0xf2). /
2231	#define IEM_OP_PRF_REPZ RT_BIT_32(18) /*< Repeat-if-zero prefix (0xf3). /
2232
2233	#define IEM_OP_PRF_REX RT_BIT_32(24) /*< Any REX prefix (0x40-0x4f). /
2234	#define IEM_OP_PRF_REX_B RT_BIT_32(25) /*< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). /
2235	#define IEM_OP_PRF_REX_X RT_BIT_32(26) /*< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). /
2236	#define IEM_OP_PRF_REX_R RT_BIT_32(27) /*< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). /
2237	/** Mask with all the REX prefix flags.
2238	* This is generally for use when needing to undo the REX prefixes when they
2239	* are followed legacy prefixes and therefore does not immediately preceed
2240	* the first opcode byte.
2241	* For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
2242	#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX \| IEM_OP_PRF_REX_R \| IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X \| IEM_OP_PRF_SIZE_REX_W )
2243
2244	#define IEM_OP_PRF_VEX RT_BIT_32(28) /*< Indiciates VEX prefix. /
2245	#define IEM_OP_PRF_EVEX RT_BIT_32(29) /*< Indiciates EVEX prefix. /
2246	#define IEM_OP_PRF_XOP RT_BIT_32(30) /*< Indiciates XOP prefix. /
2247	/** @} */
2248
2249	/** @name IEMOPFORM_XXX - Opcode forms
2250	* @note These are ORed together with IEMOPHINT_XXX.
2251	* @{ */
2252	/** ModR/M: reg, r/m */
2253	#define IEMOPFORM_RM 0
2254	/** ModR/M: reg, r/m (register) */
2255	#define IEMOPFORM_RM_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
2256	/** ModR/M: reg, r/m (memory) */
2257	#define IEMOPFORM_RM_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
2258	/** ModR/M: reg, r/m, imm */
2259	#define IEMOPFORM_RMI 1
2260	/** ModR/M: reg, r/m (register), imm */
2261	#define IEMOPFORM_RMI_REG (IEMOPFORM_RMI \| IEMOPFORM_MOD3)
2262	/** ModR/M: reg, r/m (memory), imm */
2263	#define IEMOPFORM_RMI_MEM (IEMOPFORM_RMI \| IEMOPFORM_NOT_MOD3)
2264	/** ModR/M: reg, r/m, xmm0 */
2265	#define IEMOPFORM_RM0 2
2266	/** ModR/M: reg, r/m (register), xmm0 */
2267	#define IEMOPFORM_RM0_REG (IEMOPFORM_RM0 \| IEMOPFORM_MOD3)
2268	/** ModR/M: reg, r/m (memory), xmm0 */
2269	#define IEMOPFORM_RM0_MEM (IEMOPFORM_RM0 \| IEMOPFORM_NOT_MOD3)
2270	/** ModR/M: r/m, reg */
2271	#define IEMOPFORM_MR 3
2272	/** ModR/M: r/m (register), reg */
2273	#define IEMOPFORM_MR_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
2274	/** ModR/M: r/m (memory), reg */
2275	#define IEMOPFORM_MR_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
2276	/** ModR/M: r/m, reg, imm */
2277	#define IEMOPFORM_MRI 4
2278	/** ModR/M: r/m (register), reg, imm */
2279	#define IEMOPFORM_MRI_REG (IEMOPFORM_MRI \| IEMOPFORM_MOD3)
2280	/** ModR/M: r/m (memory), reg, imm */
2281	#define IEMOPFORM_MRI_MEM (IEMOPFORM_MRI \| IEMOPFORM_NOT_MOD3)
2282	/** ModR/M: r/m only */
2283	#define IEMOPFORM_M 5
2284	/** ModR/M: r/m only (register). */
2285	#define IEMOPFORM_M_REG (IEMOPFORM_M \| IEMOPFORM_MOD3)
2286	/** ModR/M: r/m only (memory). */
2287	#define IEMOPFORM_M_MEM (IEMOPFORM_M \| IEMOPFORM_NOT_MOD3)
2288	/** ModR/M: r/m, imm */
2289	#define IEMOPFORM_MI 6
2290	/** ModR/M: r/m (register), imm */
2291	#define IEMOPFORM_MI_REG (IEMOPFORM_MI \| IEMOPFORM_MOD3)
2292	/** ModR/M: r/m (memory), imm */
2293	#define IEMOPFORM_MI_MEM (IEMOPFORM_MI \| IEMOPFORM_NOT_MOD3)
2294	/** ModR/M: r/m, 1 (shift and rotate instructions) */
2295	#define IEMOPFORM_M1 7
2296	/** ModR/M: r/m (register), 1. */
2297	#define IEMOPFORM_M1_REG (IEMOPFORM_M1 \| IEMOPFORM_MOD3)
2298	/** ModR/M: r/m (memory), 1. */
2299	#define IEMOPFORM_M1_MEM (IEMOPFORM_M1 \| IEMOPFORM_NOT_MOD3)
2300	/** ModR/M: r/m, CL (shift and rotate instructions)
2301	* @todo This should just've been a generic fixed register. But the python
2302	* code doesn't needs more convincing. */
2303	#define IEMOPFORM_M_CL 8
2304	/** ModR/M: r/m (register), CL. */
2305	#define IEMOPFORM_M_CL_REG (IEMOPFORM_M_CL \| IEMOPFORM_MOD3)
2306	/** ModR/M: r/m (memory), CL. */
2307	#define IEMOPFORM_M_CL_MEM (IEMOPFORM_M_CL \| IEMOPFORM_NOT_MOD3)
2308	/** ModR/M: reg only */
2309	#define IEMOPFORM_R 9
2310
2311	/** VEX+ModR/M: reg, r/m */
2312	#define IEMOPFORM_VEX_RM 16
2313	/** VEX+ModR/M: reg, r/m (register) */
2314	#define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM \| IEMOPFORM_MOD3)
2315	/** VEX+ModR/M: reg, r/m (memory) */
2316	#define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM \| IEMOPFORM_NOT_MOD3)
2317	/** VEX+ModR/M: r/m, reg */
2318	#define IEMOPFORM_VEX_MR 17
2319	/** VEX+ModR/M: r/m (register), reg */
2320	#define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR \| IEMOPFORM_MOD3)
2321	/** VEX+ModR/M: r/m (memory), reg */
2322	#define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR \| IEMOPFORM_NOT_MOD3)
2323	/** VEX+ModR/M: r/m, reg, imm8 */
2324	#define IEMOPFORM_VEX_MRI 18
2325	/** VEX+ModR/M: r/m (register), reg, imm8 */
2326	#define IEMOPFORM_VEX_MRI_REG (IEMOPFORM_VEX_MRI \| IEMOPFORM_MOD3)
2327	/** VEX+ModR/M: r/m (memory), reg, imm8 */
2328	#define IEMOPFORM_VEX_MRI_MEM (IEMOPFORM_VEX_MRI \| IEMOPFORM_NOT_MOD3)
2329	/** VEX+ModR/M: r/m only */
2330	#define IEMOPFORM_VEX_M 19
2331	/** VEX+ModR/M: r/m only (register). */
2332	#define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M \| IEMOPFORM_MOD3)
2333	/** VEX+ModR/M: r/m only (memory). */
2334	#define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M \| IEMOPFORM_NOT_MOD3)
2335	/** VEX+ModR/M: reg only */
2336	#define IEMOPFORM_VEX_R 20
2337	/** VEX+ModR/M: reg, vvvv, r/m */
2338	#define IEMOPFORM_VEX_RVM 21
2339	/** VEX+ModR/M: reg, vvvv, r/m (register). */
2340	#define IEMOPFORM_VEX_RVM_REG (IEMOPFORM_VEX_RVM \| IEMOPFORM_MOD3)
2341	/** VEX+ModR/M: reg, vvvv, r/m (memory). */
2342	#define IEMOPFORM_VEX_RVM_MEM (IEMOPFORM_VEX_RVM \| IEMOPFORM_NOT_MOD3)
2343	/** VEX+ModR/M: reg, vvvv, r/m, imm */
2344	#define IEMOPFORM_VEX_RVMI 22
2345	/** VEX+ModR/M: reg, vvvv, r/m (register), imm. */
2346	#define IEMOPFORM_VEX_RVMI_REG (IEMOPFORM_VEX_RVMI \| IEMOPFORM_MOD3)
2347	/** VEX+ModR/M: reg, vvvv, r/m (memory), imm. */
2348	#define IEMOPFORM_VEX_RVMI_MEM (IEMOPFORM_VEX_RVMI \| IEMOPFORM_NOT_MOD3)
2349	/** VEX+ModR/M: reg, vvvv, r/m, imm(reg) */
2350	#define IEMOPFORM_VEX_RVMR 23
2351	/** VEX+ModR/M: reg, vvvv, r/m (register), imm(reg). */
2352	#define IEMOPFORM_VEX_RVMR_REG (IEMOPFORM_VEX_RVMI \| IEMOPFORM_MOD3)
2353	/** VEX+ModR/M: reg, vvvv, r/m (memory), imm(reg). */
2354	#define IEMOPFORM_VEX_RVMR_MEM (IEMOPFORM_VEX_RVMI \| IEMOPFORM_NOT_MOD3)
2355	/** VEX+ModR/M: reg, r/m, vvvv */
2356	#define IEMOPFORM_VEX_RMV 24
2357	/** VEX+ModR/M: reg, r/m, vvvv (register). */
2358	#define IEMOPFORM_VEX_RMV_REG (IEMOPFORM_VEX_RMV \| IEMOPFORM_MOD3)
2359	/** VEX+ModR/M: reg, r/m, vvvv (memory). */
2360	#define IEMOPFORM_VEX_RMV_MEM (IEMOPFORM_VEX_RMV \| IEMOPFORM_NOT_MOD3)
2361	/** VEX+ModR/M: reg, r/m, imm8 */
2362	#define IEMOPFORM_VEX_RMI 25
2363	/** VEX+ModR/M: reg, r/m, imm8 (register). */
2364	#define IEMOPFORM_VEX_RMI_REG (IEMOPFORM_VEX_RMI \| IEMOPFORM_MOD3)
2365	/** VEX+ModR/M: reg, r/m, imm8 (memory). */
2366	#define IEMOPFORM_VEX_RMI_MEM (IEMOPFORM_VEX_RMI \| IEMOPFORM_NOT_MOD3)
2367	/** VEX+ModR/M: r/m, vvvv, reg */
2368	#define IEMOPFORM_VEX_MVR 26
2369	/** VEX+ModR/M: r/m, vvvv, reg (register) */
2370	#define IEMOPFORM_VEX_MVR_REG (IEMOPFORM_VEX_MVR \| IEMOPFORM_MOD3)
2371	/** VEX+ModR/M: r/m, vvvv, reg (memory) */
2372	#define IEMOPFORM_VEX_MVR_MEM (IEMOPFORM_VEX_MVR \| IEMOPFORM_NOT_MOD3)
2373	/** VEX+ModR/M+/n: vvvv, r/m */
2374	#define IEMOPFORM_VEX_VM 27
2375	/** VEX+ModR/M+/n: vvvv, r/m (register) */
2376	#define IEMOPFORM_VEX_VM_REG (IEMOPFORM_VEX_VM \| IEMOPFORM_MOD3)
2377	/** VEX+ModR/M+/n: vvvv, r/m (memory) */
2378	#define IEMOPFORM_VEX_VM_MEM (IEMOPFORM_VEX_VM \| IEMOPFORM_NOT_MOD3)
2379	/** VEX+ModR/M+/n: vvvv, r/m, imm8 */
2380	#define IEMOPFORM_VEX_VMI 28
2381	/** VEX+ModR/M+/n: vvvv, r/m, imm8 (register) */
2382	#define IEMOPFORM_VEX_VMI_REG (IEMOPFORM_VEX_VMI \| IEMOPFORM_MOD3)
2383	/** VEX+ModR/M+/n: vvvv, r/m, imm8 (memory) */
2384	#define IEMOPFORM_VEX_VMI_MEM (IEMOPFORM_VEX_VMI \| IEMOPFORM_NOT_MOD3)
2385
2386	/** Fixed register instruction, no R/M. */
2387	#define IEMOPFORM_FIXED 32
2388
2389	/** The r/m is a register. */
2390	#define IEMOPFORM_MOD3 RT_BIT_32(8)
2391	/** The r/m is a memory access. */
2392	#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
2393	/** @} */
2394
2395	/** @name IEMOPHINT_XXX - Additional Opcode Hints
2396	* @note These are ORed together with IEMOPFORM_XXX.
2397	* @{ */
2398	/** Ignores the operand size prefix (66h). */
2399	#define IEMOPHINT_IGNORES_OZ_PFX RT_BIT_32(10)
2400	/** Ignores REX.W (aka WIG). */
2401	#define IEMOPHINT_IGNORES_REXW RT_BIT_32(11)
2402	/** Both the operand size prefixes (66h + REX.W) are ignored. */
2403	#define IEMOPHINT_IGNORES_OP_SIZES (IEMOPHINT_IGNORES_OZ_PFX \| IEMOPHINT_IGNORES_REXW)
2404	/** Allowed with the lock prefix. */
2405	#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
2406	/** The VEX.L value is ignored (aka LIG). */
2407	#define IEMOPHINT_VEX_L_IGNORED RT_BIT_32(12)
2408	/** The VEX.L value must be zero (i.e. 128-bit width only). */
2409	#define IEMOPHINT_VEX_L_ZERO RT_BIT_32(13)
2410	/** The VEX.L value must be one (i.e. 256-bit width only). */
2411	#define IEMOPHINT_VEX_L_ONE RT_BIT_32(14)
2412	/** The VEX.V value must be zero. */
2413	#define IEMOPHINT_VEX_V_ZERO RT_BIT_32(15)
2414	/** The REX.W/VEX.V value must be zero. */
2415	#define IEMOPHINT_REX_W_ZERO RT_BIT_32(16)
2416	#define IEMOPHINT_VEX_W_ZERO IEMOPHINT_REX_W_ZERO
2417	/** The REX.W/VEX.V value must be one. */
2418	#define IEMOPHINT_REX_W_ONE RT_BIT_32(17)
2419	#define IEMOPHINT_VEX_W_ONE IEMOPHINT_REX_W_ONE
2420
2421	/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
2422	#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
2423	/** @} */
2424
2425	/**
2426	* Possible hardware task switch sources.
2427	*/
2428	typedef enum IEMTASKSWITCH
2429	{
2430	/** Task switch caused by an interrupt/exception. */
2431	IEMTASKSWITCH_INT_XCPT = 1,
2432	/** Task switch caused by a far CALL. */
2433	IEMTASKSWITCH_CALL,
2434	/** Task switch caused by a far JMP. */
2435	IEMTASKSWITCH_JUMP,
2436	/** Task switch caused by an IRET. */
2437	IEMTASKSWITCH_IRET
2438	} IEMTASKSWITCH;
2439	AssertCompileSize(IEMTASKSWITCH, 4);
2440
2441	/**
2442	* Possible CrX load (write) sources.
2443	*/
2444	typedef enum IEMACCESSCRX
2445	{
2446	/** CrX access caused by 'mov crX' instruction. */
2447	IEMACCESSCRX_MOV_CRX,
2448	/** CrX (CR0) write caused by 'lmsw' instruction. */
2449	IEMACCESSCRX_LMSW,
2450	/** CrX (CR0) write caused by 'clts' instruction. */
2451	IEMACCESSCRX_CLTS,
2452	/** CrX (CR0) read caused by 'smsw' instruction. */
2453	IEMACCESSCRX_SMSW
2454	} IEMACCESSCRX;
2455
2456	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2457	/** @name IEM_SLAT_FAIL_XXX - Second-level address translation failure information.
2458	*
2459	* These flags provide further context to SLAT page-walk failures that could not be
2460	* determined by PGM (e.g, PGM is not privy to memory access permissions).
2461	*
2462	* @{
2463	*/
2464	/** Translating a nested-guest linear address failed accessing a nested-guest
2465	* physical address. */
2466	# define IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR RT_BIT_32(0)
2467	/** Translating a nested-guest linear address failed accessing a
2468	* paging-structure entry or updating accessed/dirty bits. */
2469	# define IEM_SLAT_FAIL_LINEAR_TO_PAGE_TABLE RT_BIT_32(1)
2470	/** @} */
2471
2472	DECLCALLBACK(FNPGMPHYSHANDLER) iemVmxApicAccessPageHandler;
2473	# ifndef IN_RING3
2474	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) iemVmxApicAccessPagePfHandler;
2475	# endif
2476	#endif
2477
2478	/**
2479	* Indicates to the verifier that the given flag set is undefined.
2480	*
2481	* Can be invoked again to add more flags.
2482	*
2483	* This is a NOOP if the verifier isn't compiled in.
2484	*
2485	* @note We're temporarily keeping this until code is converted to new
2486	* disassembler style opcode handling.
2487	*/
2488	#define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
2489
2490
2491	/** @def IEM_DECL_IMPL_TYPE
2492	* For typedef'ing an instruction implementation function.
2493	*
2494	* @param a_RetType The return type.
2495	* @param a_Name The name of the type.
2496	* @param a_ArgList The argument list enclosed in parentheses.
2497	*/
2498
2499	/** @def IEM_DECL_IMPL_DEF
2500	* For defining an instruction implementation function.
2501	*
2502	* @param a_RetType The return type.
2503	* @param a_Name The name of the type.
2504	* @param a_ArgList The argument list enclosed in parentheses.
2505	*/
2506
2507	#if defined(__GNUC__) && defined(RT_ARCH_X86)
2508	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2509	__attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
2510	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2511	__attribute__((__fastcall__, __nothrow__)) DECL_HIDDEN_ONLY(a_RetType) a_Name a_ArgList
2512	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2513	__attribute__((__fastcall__, __nothrow__)) DECL_HIDDEN_ONLY(a_RetType) a_Name a_ArgList
2514
2515	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
2516	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2517	a_RetType (__fastcall a_Name) a_ArgList
2518	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2519	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
2520	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2521	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
2522
2523	#elif __cplusplus >= 201700 /* P0012R1 support */
2524	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2525	a_RetType (VBOXCALL a_Name) a_ArgList RT_NOEXCEPT
2526	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2527	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList RT_NOEXCEPT
2528	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2529	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList RT_NOEXCEPT
2530
2531	#else
2532	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2533	a_RetType (VBOXCALL a_Name) a_ArgList
2534	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2535	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList
2536	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2537	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList
2538
2539	#endif
2540
2541	/** Defined in IEMAllAImplC.cpp but also used by IEMAllAImplA.asm. */
2542	RT_C_DECLS_BEGIN
2543	extern uint8_t const g_afParity[256];
2544	RT_C_DECLS_END
2545
2546
2547	/** @name Arithmetic assignment operations on bytes (binary).
2548	* @{ */
2549	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU8, (uint8_t pu8Dst, uint8_t u8Src, uint32_t pEFlags));
2550	typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
2551	FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
2552	FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
2553	FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
2554	FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
2555	FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
2556	FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
2557	FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
2558	/** @} */
2559
2560	/** @name Arithmetic assignment operations on words (binary).
2561	* @{ */
2562	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU16, (uint16_t pu16Dst, uint16_t u16Src, uint32_t pEFlags));
2563	typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
2564	FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
2565	FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
2566	FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
2567	FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
2568	FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
2569	FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
2570	FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
2571	/** @} */
2572
2573	/** @name Arithmetic assignment operations on double words (binary).
2574	* @{ */
2575	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU32, (uint32_t pu32Dst, uint32_t u32Src, uint32_t pEFlags));
2576	typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
2577	FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
2578	FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
2579	FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
2580	FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
2581	FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
2582	FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
2583	FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
2584	FNIEMAIMPLBINU32 iemAImpl_blsi_u32, iemAImpl_blsi_u32_fallback;
2585	FNIEMAIMPLBINU32 iemAImpl_blsr_u32, iemAImpl_blsr_u32_fallback;
2586	FNIEMAIMPLBINU32 iemAImpl_blsmsk_u32, iemAImpl_blsmsk_u32_fallback;
2587	/** @} */
2588
2589	/** @name Arithmetic assignment operations on quad words (binary).
2590	* @{ */
2591	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU64, (uint64_t pu64Dst, uint64_t u64Src, uint32_t pEFlags));
2592	typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
2593	FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
2594	FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
2595	FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
2596	FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
2597	FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
2598	FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
2599	FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
2600	FNIEMAIMPLBINU64 iemAImpl_blsi_u64, iemAImpl_blsi_u64_fallback;
2601	FNIEMAIMPLBINU64 iemAImpl_blsr_u64, iemAImpl_blsr_u64_fallback;
2602	FNIEMAIMPLBINU64 iemAImpl_blsmsk_u64, iemAImpl_blsmsk_u64_fallback;
2603	/** @} */
2604
2605	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINROU8,(uint8_t const pu8Dst, uint8_t u8Src, uint32_t pEFlags));
2606	typedef FNIEMAIMPLBINROU8 *PFNIEMAIMPLBINROU8;
2607	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINROU16,(uint16_t const pu16Dst, uint16_t u16Src, uint32_t pEFlags));
2608	typedef FNIEMAIMPLBINROU16 *PFNIEMAIMPLBINROU16;
2609	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINROU32,(uint32_t const pu32Dst, uint32_t u32Src, uint32_t pEFlags));
2610	typedef FNIEMAIMPLBINROU32 *PFNIEMAIMPLBINROU32;
2611	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINROU64,(uint64_t const pu64Dst, uint64_t u64Src, uint32_t pEFlags));
2612	typedef FNIEMAIMPLBINROU64 *PFNIEMAIMPLBINROU64;
2613
2614	/** @name Compare operations (thrown in with the binary ops).
2615	* @{ */
2616	FNIEMAIMPLBINROU8 iemAImpl_cmp_u8;
2617	FNIEMAIMPLBINROU16 iemAImpl_cmp_u16;
2618	FNIEMAIMPLBINROU32 iemAImpl_cmp_u32;
2619	FNIEMAIMPLBINROU64 iemAImpl_cmp_u64;
2620	/** @} */
2621
2622	/** @name Test operations (thrown in with the binary ops).
2623	* @{ */
2624	FNIEMAIMPLBINROU8 iemAImpl_test_u8;
2625	FNIEMAIMPLBINROU16 iemAImpl_test_u16;
2626	FNIEMAIMPLBINROU32 iemAImpl_test_u32;
2627	FNIEMAIMPLBINROU64 iemAImpl_test_u64;
2628	/** @} */
2629
2630	/** @name Bit operations operations (thrown in with the binary ops).
2631	* @{ */
2632	FNIEMAIMPLBINROU16 iemAImpl_bt_u16;
2633	FNIEMAIMPLBINROU32 iemAImpl_bt_u32;
2634	FNIEMAIMPLBINROU64 iemAImpl_bt_u64;
2635	FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
2636	FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
2637	FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
2638	FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
2639	FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
2640	FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
2641	FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
2642	FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
2643	FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
2644	/** @} */
2645
2646	/** @name Arithmetic three operand operations on double words (binary).
2647	* @{ */
2648	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32, (uint32_t pu32Dst, uint32_t u32Src1, uint32_t u32Src2, uint32_t pEFlags));
2649	typedef FNIEMAIMPLBINVEXU32 *PFNIEMAIMPLBINVEXU32;
2650	FNIEMAIMPLBINVEXU32 iemAImpl_andn_u32, iemAImpl_andn_u32_fallback;
2651	FNIEMAIMPLBINVEXU32 iemAImpl_bextr_u32, iemAImpl_bextr_u32_fallback;
2652	FNIEMAIMPLBINVEXU32 iemAImpl_bzhi_u32, iemAImpl_bzhi_u32_fallback;
2653	/** @} */
2654
2655	/** @name Arithmetic three operand operations on quad words (binary).
2656	* @{ */
2657	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64, (uint64_t pu64Dst, uint64_t u64Src1, uint64_t u64Src2, uint32_t pEFlags));
2658	typedef FNIEMAIMPLBINVEXU64 *PFNIEMAIMPLBINVEXU64;
2659	FNIEMAIMPLBINVEXU64 iemAImpl_andn_u64, iemAImpl_andn_u64_fallback;
2660	FNIEMAIMPLBINVEXU64 iemAImpl_bextr_u64, iemAImpl_bextr_u64_fallback;
2661	FNIEMAIMPLBINVEXU64 iemAImpl_bzhi_u64, iemAImpl_bzhi_u64_fallback;
2662	/** @} */
2663
2664	/** @name Arithmetic three operand operations on double words w/o EFLAGS (binary).
2665	* @{ */
2666	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32NOEFL, (uint32_t *pu32Dst, uint32_t u32Src1, uint32_t u32Src2));
2667	typedef FNIEMAIMPLBINVEXU32NOEFL *PFNIEMAIMPLBINVEXU32NOEFL;
2668	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pdep_u32, iemAImpl_pdep_u32_fallback;
2669	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pext_u32, iemAImpl_pext_u32_fallback;
2670	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_sarx_u32, iemAImpl_sarx_u32_fallback;
2671	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shlx_u32, iemAImpl_shlx_u32_fallback;
2672	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shrx_u32, iemAImpl_shrx_u32_fallback;
2673	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_rorx_u32;
2674	/** @} */
2675
2676	/** @name Arithmetic three operand operations on quad words w/o EFLAGS (binary).
2677	* @{ */
2678	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64NOEFL, (uint64_t *pu64Dst, uint64_t u64Src1, uint64_t u64Src2));
2679	typedef FNIEMAIMPLBINVEXU64NOEFL *PFNIEMAIMPLBINVEXU64NOEFL;
2680	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pdep_u64, iemAImpl_pdep_u64_fallback;
2681	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pext_u64, iemAImpl_pext_u64_fallback;
2682	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_sarx_u64, iemAImpl_sarx_u64_fallback;
2683	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shlx_u64, iemAImpl_shlx_u64_fallback;
2684	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shrx_u64, iemAImpl_shrx_u64_fallback;
2685	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_rorx_u64;
2686	/** @} */
2687
2688	/** @name MULX 32-bit and 64-bit.
2689	* @{ */
2690	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU32, (uint32_t puDst1, uint32_t puDst2, uint32_t uSrc1, uint32_t uSrc2));
2691	typedef FNIEMAIMPLMULXVEXU32 *PFNIEMAIMPLMULXVEXU32;
2692	FNIEMAIMPLMULXVEXU32 iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback;
2693
2694	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU64, (uint64_t puDst1, uint64_t puDst2, uint64_t uSrc1, uint64_t uSrc2));
2695	typedef FNIEMAIMPLMULXVEXU64 *PFNIEMAIMPLMULXVEXU64;
2696	FNIEMAIMPLMULXVEXU64 iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback;
2697	/** @} */
2698
2699
2700	/** @name Exchange memory with register operations.
2701	* @{ */
2702	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_locked, (uint8_t pu8Mem, uint8_t pu8Reg));
2703	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_locked,(uint16_t pu16Mem, uint16_t pu16Reg));
2704	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_locked,(uint32_t pu32Mem, uint32_t pu32Reg));
2705	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_locked,(uint64_t pu64Mem, uint64_t pu64Reg));
2706	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_unlocked, (uint8_t pu8Mem, uint8_t pu8Reg));
2707	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_unlocked,(uint16_t pu16Mem, uint16_t pu16Reg));
2708	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_unlocked,(uint32_t pu32Mem, uint32_t pu32Reg));
2709	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_unlocked,(uint64_t pu64Mem, uint64_t pu64Reg));
2710	/** @} */
2711
2712	/** @name Exchange and add operations.
2713	* @{ */
2714	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
2715	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
2716	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
2717	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
2718	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
2719	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
2720	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
2721	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
2722	/** @} */
2723
2724	/** @name Compare and exchange.
2725	* @{ */
2726	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
2727	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
2728	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
2729	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
2730	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
2731	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
2732	#if ARCH_BITS == 32
2733	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
2734	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
2735	#else
2736	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
2737	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
2738	#endif
2739	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
2740	uint32_t *pEFlags));
2741	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
2742	uint32_t *pEFlags));
2743	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
2744	uint32_t *pEFlags));
2745	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
2746	uint32_t *pEFlags));
2747	#ifndef RT_ARCH_ARM64
2748	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
2749	PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
2750	#endif
2751	/** @} */
2752
2753	/** @name Memory ordering
2754	* @{ */
2755	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
2756	typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
2757	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
2758	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
2759	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
2760	#ifndef RT_ARCH_ARM64
2761	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
2762	#endif
2763	/** @} */
2764
2765	/** @name Double precision shifts
2766	* @{ */
2767	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t pEFlags));
2768	typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
2769	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t pEFlags));
2770	typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
2771	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t pEFlags));
2772	typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
2773	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16, iemAImpl_shld_u16_amd, iemAImpl_shld_u16_intel;
2774	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32, iemAImpl_shld_u32_amd, iemAImpl_shld_u32_intel;
2775	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64, iemAImpl_shld_u64_amd, iemAImpl_shld_u64_intel;
2776	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16, iemAImpl_shrd_u16_amd, iemAImpl_shrd_u16_intel;
2777	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32, iemAImpl_shrd_u32_amd, iemAImpl_shrd_u32_intel;
2778	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64, iemAImpl_shrd_u64_amd, iemAImpl_shrd_u64_intel;
2779	/** @} */
2780
2781
2782	/** @name Bit search operations (thrown in with the binary ops).
2783	* @{ */
2784	FNIEMAIMPLBINU16 iemAImpl_bsf_u16, iemAImpl_bsf_u16_amd, iemAImpl_bsf_u16_intel;
2785	FNIEMAIMPLBINU32 iemAImpl_bsf_u32, iemAImpl_bsf_u32_amd, iemAImpl_bsf_u32_intel;
2786	FNIEMAIMPLBINU64 iemAImpl_bsf_u64, iemAImpl_bsf_u64_amd, iemAImpl_bsf_u64_intel;
2787	FNIEMAIMPLBINU16 iemAImpl_bsr_u16, iemAImpl_bsr_u16_amd, iemAImpl_bsr_u16_intel;
2788	FNIEMAIMPLBINU32 iemAImpl_bsr_u32, iemAImpl_bsr_u32_amd, iemAImpl_bsr_u32_intel;
2789	FNIEMAIMPLBINU64 iemAImpl_bsr_u64, iemAImpl_bsr_u64_amd, iemAImpl_bsr_u64_intel;
2790	FNIEMAIMPLBINU16 iemAImpl_lzcnt_u16, iemAImpl_lzcnt_u16_amd, iemAImpl_lzcnt_u16_intel;
2791	FNIEMAIMPLBINU32 iemAImpl_lzcnt_u32, iemAImpl_lzcnt_u32_amd, iemAImpl_lzcnt_u32_intel;
2792	FNIEMAIMPLBINU64 iemAImpl_lzcnt_u64, iemAImpl_lzcnt_u64_amd, iemAImpl_lzcnt_u64_intel;
2793	FNIEMAIMPLBINU16 iemAImpl_tzcnt_u16, iemAImpl_tzcnt_u16_amd, iemAImpl_tzcnt_u16_intel;
2794	FNIEMAIMPLBINU32 iemAImpl_tzcnt_u32, iemAImpl_tzcnt_u32_amd, iemAImpl_tzcnt_u32_intel;
2795	FNIEMAIMPLBINU64 iemAImpl_tzcnt_u64, iemAImpl_tzcnt_u64_amd, iemAImpl_tzcnt_u64_intel;
2796	FNIEMAIMPLBINU16 iemAImpl_popcnt_u16, iemAImpl_popcnt_u16_fallback;
2797	FNIEMAIMPLBINU32 iemAImpl_popcnt_u32, iemAImpl_popcnt_u32_fallback;
2798	FNIEMAIMPLBINU64 iemAImpl_popcnt_u64, iemAImpl_popcnt_u64_fallback;
2799	/** @} */
2800
2801	/** @name Signed multiplication operations (thrown in with the binary ops).
2802	* @{ */
2803	FNIEMAIMPLBINU16 iemAImpl_imul_two_u16, iemAImpl_imul_two_u16_amd, iemAImpl_imul_two_u16_intel;
2804	FNIEMAIMPLBINU32 iemAImpl_imul_two_u32, iemAImpl_imul_two_u32_amd, iemAImpl_imul_two_u32_intel;
2805	FNIEMAIMPLBINU64 iemAImpl_imul_two_u64, iemAImpl_imul_two_u64_amd, iemAImpl_imul_two_u64_intel;
2806	/** @} */
2807
2808	/** @name Arithmetic assignment operations on bytes (unary).
2809	* @{ */
2810	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t pu8Dst, uint32_t pEFlags));
2811	typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
2812	FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
2813	FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
2814	FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
2815	FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
2816	/** @} */
2817
2818	/** @name Arithmetic assignment operations on words (unary).
2819	* @{ */
2820	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t pu16Dst, uint32_t pEFlags));
2821	typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
2822	FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
2823	FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
2824	FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
2825	FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
2826	/** @} */
2827
2828	/** @name Arithmetic assignment operations on double words (unary).
2829	* @{ */
2830	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t pu32Dst, uint32_t pEFlags));
2831	typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
2832	FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
2833	FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
2834	FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
2835	FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
2836	/** @} */
2837
2838	/** @name Arithmetic assignment operations on quad words (unary).
2839	* @{ */
2840	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t pu64Dst, uint32_t pEFlags));
2841	typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
2842	FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
2843	FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
2844	FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
2845	FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
2846	/** @} */
2847
2848
2849	/** @name Shift operations on bytes (Group 2).
2850	* @{ */
2851	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU8,(uint8_t pu8Dst, uint8_t cShift, uint32_t pEFlags));
2852	typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
2853	FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8, iemAImpl_rol_u8_amd, iemAImpl_rol_u8_intel;
2854	FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8, iemAImpl_ror_u8_amd, iemAImpl_ror_u8_intel;
2855	FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8, iemAImpl_rcl_u8_amd, iemAImpl_rcl_u8_intel;
2856	FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8, iemAImpl_rcr_u8_amd, iemAImpl_rcr_u8_intel;
2857	FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8, iemAImpl_shl_u8_amd, iemAImpl_shl_u8_intel;
2858	FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8, iemAImpl_shr_u8_amd, iemAImpl_shr_u8_intel;
2859	FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8, iemAImpl_sar_u8_amd, iemAImpl_sar_u8_intel;
2860	/** @} */
2861
2862	/** @name Shift operations on words (Group 2).
2863	* @{ */
2864	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU16,(uint16_t pu16Dst, uint8_t cShift, uint32_t pEFlags));
2865	typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
2866	FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16, iemAImpl_rol_u16_amd, iemAImpl_rol_u16_intel;
2867	FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16, iemAImpl_ror_u16_amd, iemAImpl_ror_u16_intel;
2868	FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16, iemAImpl_rcl_u16_amd, iemAImpl_rcl_u16_intel;
2869	FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16, iemAImpl_rcr_u16_amd, iemAImpl_rcr_u16_intel;
2870	FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16, iemAImpl_shl_u16_amd, iemAImpl_shl_u16_intel;
2871	FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16, iemAImpl_shr_u16_amd, iemAImpl_shr_u16_intel;
2872	FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16, iemAImpl_sar_u16_amd, iemAImpl_sar_u16_intel;
2873	/** @} */
2874
2875	/** @name Shift operations on double words (Group 2).
2876	* @{ */
2877	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU32,(uint32_t pu32Dst, uint8_t cShift, uint32_t pEFlags));
2878	typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
2879	FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32, iemAImpl_rol_u32_amd, iemAImpl_rol_u32_intel;
2880	FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32, iemAImpl_ror_u32_amd, iemAImpl_ror_u32_intel;
2881	FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32, iemAImpl_rcl_u32_amd, iemAImpl_rcl_u32_intel;
2882	FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32, iemAImpl_rcr_u32_amd, iemAImpl_rcr_u32_intel;
2883	FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32, iemAImpl_shl_u32_amd, iemAImpl_shl_u32_intel;
2884	FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32, iemAImpl_shr_u32_amd, iemAImpl_shr_u32_intel;
2885	FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32, iemAImpl_sar_u32_amd, iemAImpl_sar_u32_intel;
2886	/** @} */
2887
2888	/** @name Shift operations on words (Group 2).
2889	* @{ */
2890	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU64,(uint64_t pu64Dst, uint8_t cShift, uint32_t pEFlags));
2891	typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
2892	FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64, iemAImpl_rol_u64_amd, iemAImpl_rol_u64_intel;
2893	FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64, iemAImpl_ror_u64_amd, iemAImpl_ror_u64_intel;
2894	FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64, iemAImpl_rcl_u64_amd, iemAImpl_rcl_u64_intel;
2895	FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64, iemAImpl_rcr_u64_amd, iemAImpl_rcr_u64_intel;
2896	FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64, iemAImpl_shl_u64_amd, iemAImpl_shl_u64_intel;
2897	FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64, iemAImpl_shr_u64_amd, iemAImpl_shr_u64_intel;
2898	FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64, iemAImpl_sar_u64_amd, iemAImpl_sar_u64_intel;
2899	/** @} */
2900
2901	/** @name Multiplication and division operations.
2902	* @{ */
2903	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t pu16AX, uint8_t u8FactorDivisor, uint32_t pEFlags));
2904	typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
2905	FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_mul_u8_amd, iemAImpl_mul_u8_intel;
2906	FNIEMAIMPLMULDIVU8 iemAImpl_imul_u8, iemAImpl_imul_u8_amd, iemAImpl_imul_u8_intel;
2907	FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_div_u8_amd, iemAImpl_div_u8_intel;
2908	FNIEMAIMPLMULDIVU8 iemAImpl_idiv_u8, iemAImpl_idiv_u8_amd, iemAImpl_idiv_u8_intel;
2909
2910	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t pu16AX, uint16_t pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
2911	typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
2912	FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_mul_u16_amd, iemAImpl_mul_u16_intel;
2913	FNIEMAIMPLMULDIVU16 iemAImpl_imul_u16, iemAImpl_imul_u16_amd, iemAImpl_imul_u16_intel;
2914	FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_div_u16_amd, iemAImpl_div_u16_intel;
2915	FNIEMAIMPLMULDIVU16 iemAImpl_idiv_u16, iemAImpl_idiv_u16_amd, iemAImpl_idiv_u16_intel;
2916
2917	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t pu32EAX, uint32_t pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
2918	typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
2919	FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_mul_u32_amd, iemAImpl_mul_u32_intel;
2920	FNIEMAIMPLMULDIVU32 iemAImpl_imul_u32, iemAImpl_imul_u32_amd, iemAImpl_imul_u32_intel;
2921	FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_div_u32_amd, iemAImpl_div_u32_intel;
2922	FNIEMAIMPLMULDIVU32 iemAImpl_idiv_u32, iemAImpl_idiv_u32_amd, iemAImpl_idiv_u32_intel;
2923
2924	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t pu64RAX, uint64_t pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
2925	typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
2926	FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_mul_u64_amd, iemAImpl_mul_u64_intel;
2927	FNIEMAIMPLMULDIVU64 iemAImpl_imul_u64, iemAImpl_imul_u64_amd, iemAImpl_imul_u64_intel;
2928	FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_div_u64_amd, iemAImpl_div_u64_intel;
2929	FNIEMAIMPLMULDIVU64 iemAImpl_idiv_u64, iemAImpl_idiv_u64_amd, iemAImpl_idiv_u64_intel;
2930	/** @} */
2931
2932	/** @name Byte Swap.
2933	* @{ */
2934	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t pu32Dst)); / Yes, 32-bit register access. */
2935	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
2936	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
2937	/** @} */
2938
2939	/** @name Misc.
2940	* @{ */
2941	FNIEMAIMPLBINU16 iemAImpl_arpl;
2942	/** @} */
2943
2944	/** @name RDRAND and RDSEED
2945	* @{ */
2946	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU16,(uint16_t puDst, uint32_t pEFlags));
2947	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU32,(uint32_t puDst, uint32_t pEFlags));
2948	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU64,(uint64_t puDst, uint32_t pEFlags));
2949	typedef FNIEMAIMPLRDRANDSEEDU16 *PFNIEMAIMPLRDRANDSEEDU16;
2950	typedef FNIEMAIMPLRDRANDSEEDU32 *PFNIEMAIMPLRDRANDSEEDU32;
2951	typedef FNIEMAIMPLRDRANDSEEDU64 *PFNIEMAIMPLRDRANDSEEDU64;
2952
2953	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdrand_u16, iemAImpl_rdrand_u16_fallback;
2954	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdrand_u32, iemAImpl_rdrand_u32_fallback;
2955	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdrand_u64, iemAImpl_rdrand_u64_fallback;
2956	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdseed_u16, iemAImpl_rdseed_u16_fallback;
2957	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdseed_u32, iemAImpl_rdseed_u32_fallback;
2958	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdseed_u64, iemAImpl_rdseed_u64_fallback;
2959	/** @} */
2960
2961	/** @name ADOX and ADCX
2962	* @{ */
2963	FNIEMAIMPLBINU32 iemAImpl_adcx_u32, iemAImpl_adcx_u32_fallback;
2964	FNIEMAIMPLBINU64 iemAImpl_adcx_u64, iemAImpl_adcx_u64_fallback;
2965	FNIEMAIMPLBINU32 iemAImpl_adox_u32, iemAImpl_adox_u32_fallback;
2966	FNIEMAIMPLBINU64 iemAImpl_adox_u64, iemAImpl_adox_u64_fallback;
2967	/** @} */
2968
2969	/** @name FPU operations taking a 32-bit float argument
2970	* @{ */
2971	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2972	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
2973	typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
2974
2975	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2976	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
2977	typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
2978
2979	FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
2980	FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
2981	FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
2982	FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
2983	FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
2984	FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
2985	FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
2986
2987	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
2988	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
2989	PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
2990	/** @} */
2991
2992	/** @name FPU operations taking a 64-bit float argument
2993	* @{ */
2994	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
2995	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
2996	typedef FNIEMAIMPLFPUR64FSW *PFNIEMAIMPLFPUR64FSW;
2997
2998	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
2999	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
3000	typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
3001
3002	FNIEMAIMPLFPUR64FSW iemAImpl_fcom_r80_by_r64;
3003	FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
3004	FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
3005	FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
3006	FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
3007	FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
3008	FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
3009
3010	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
3011	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3012	PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
3013	/** @} */
3014
3015	/** @name FPU operations taking a 80-bit float argument
3016	* @{ */
3017	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3018	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
3019	typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
3020	FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
3021	FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
3022	FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
3023	FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
3024	FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
3025	FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
3026	FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
3027	FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
3028	FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
3029
3030	FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80, iemAImpl_fpatan_r80_by_r80_amd, iemAImpl_fpatan_r80_by_r80_intel;
3031	FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80, iemAImpl_fyl2x_r80_by_r80_amd, iemAImpl_fyl2x_r80_by_r80_intel;
3032	FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80, iemAImpl_fyl2xp1_r80_by_r80_amd, iemAImpl_fyl2xp1_r80_by_r80_intel;
3033
3034	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3035	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
3036	typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
3037	FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
3038	FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
3039
3040	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
3041	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
3042	typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
3043	FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
3044	FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
3045
3046	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
3047	typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
3048	FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
3049	FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
3050	FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80, iemAImpl_f2xm1_r80_amd, iemAImpl_f2xm1_r80_intel;
3051	FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
3052	FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
3053	FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80, iemAImpl_fsin_r80_amd, iemAImpl_fsin_r80_intel;
3054	FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80, iemAImpl_fcos_r80_amd, iemAImpl_fcos_r80_intel;
3055
3056	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
3057	typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
3058	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
3059	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
3060
3061	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
3062	typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
3063	FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
3064	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
3065	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
3066	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
3067	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
3068	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
3069	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
3070
3071	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
3072	PCRTFLOAT80U pr80Val));
3073	typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
3074	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80, iemAImpl_fptan_r80_r80_amd, iemAImpl_fptan_r80_r80_intel;
3075	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
3076	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80, iemAImpl_fsincos_r80_r80_amd, iemAImpl_fsincos_r80_r80_intel;
3077
3078	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
3079	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3080	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
3081
3082	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_d80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTPBCD80U pd80Val));
3083	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_d80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3084	PRTPBCD80U pd80Dst, PCRTFLOAT80U pr80Src));
3085
3086	/** @} */
3087
3088	/** @name FPU operations taking a 16-bit signed integer argument
3089	* @{ */
3090	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3091	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
3092	typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
3093	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI16,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3094	int16_t *pi16Dst, PCRTFLOAT80U pr80Src));
3095	typedef FNIEMAIMPLFPUSTR80TOI16 *PFNIEMAIMPLFPUSTR80TOI16;
3096
3097	FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
3098	FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
3099	FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
3100	FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
3101	FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
3102	FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
3103
3104	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3105	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
3106	typedef FNIEMAIMPLFPUI16FSW *PFNIEMAIMPLFPUI16FSW;
3107	FNIEMAIMPLFPUI16FSW iemAImpl_ficom_r80_by_i16;
3108
3109	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
3110	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fist_r80_to_i16;
3111	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fistt_r80_to_i16, iemAImpl_fistt_r80_to_i16_amd, iemAImpl_fistt_r80_to_i16_intel;
3112	/** @} */
3113
3114	/** @name FPU operations taking a 32-bit signed integer argument
3115	* @{ */
3116	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3117	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
3118	typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
3119	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI32,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3120	int32_t *pi32Dst, PCRTFLOAT80U pr80Src));
3121	typedef FNIEMAIMPLFPUSTR80TOI32 *PFNIEMAIMPLFPUSTR80TOI32;
3122
3123	FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
3124	FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
3125	FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
3126	FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
3127	FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
3128	FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
3129
3130	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3131	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
3132	typedef FNIEMAIMPLFPUI32FSW *PFNIEMAIMPLFPUI32FSW;
3133	FNIEMAIMPLFPUI32FSW iemAImpl_ficom_r80_by_i32;
3134
3135	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
3136	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fist_r80_to_i32;
3137	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fistt_r80_to_i32;
3138	/** @} */
3139
3140	/** @name FPU operations taking a 64-bit signed integer argument
3141	* @{ */
3142	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI64,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3143	int64_t *pi64Dst, PCRTFLOAT80U pr80Src));
3144	typedef FNIEMAIMPLFPUSTR80TOI64 *PFNIEMAIMPLFPUSTR80TOI64;
3145
3146	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
3147	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fist_r80_to_i64;
3148	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fistt_r80_to_i64;
3149	/** @} */
3150
3151
3152	/** Temporary type representing a 256-bit vector register. */
3153	typedef struct { uint64_t au64[4]; } IEMVMM256;
3154	/** Temporary type pointing to a 256-bit vector register. */
3155	typedef IEMVMM256 *PIEMVMM256;
3156	/** Temporary type pointing to a const 256-bit vector register. */
3157	typedef IEMVMM256 *PCIEMVMM256;
3158
3159
3160	/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
3161	* @{ */
3162	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t puDst, uint64_t const puSrc));
3163	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
3164	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U128,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
3165	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
3166	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U128,(PX86XSAVEAREA pExtState, PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
3167	typedef FNIEMAIMPLMEDIAF3U128 *PFNIEMAIMPLMEDIAF3U128;
3168	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U256,(PX86XSAVEAREA pExtState, PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
3169	typedef FNIEMAIMPLMEDIAF3U256 *PFNIEMAIMPLMEDIAF3U256;
3170	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U64,(uint64_t puDst, uint64_t const puSrc));
3171	typedef FNIEMAIMPLMEDIAOPTF2U64 *PFNIEMAIMPLMEDIAOPTF2U64;
3172	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128,(PRTUINT128U puDst, PCRTUINT128U puSrc));
3173	typedef FNIEMAIMPLMEDIAOPTF2U128 *PFNIEMAIMPLMEDIAOPTF2U128;
3174	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
3175	typedef FNIEMAIMPLMEDIAOPTF3U128 *PFNIEMAIMPLMEDIAOPTF3U128;
3176	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
3177	typedef FNIEMAIMPLMEDIAOPTF3U256 *PFNIEMAIMPLMEDIAOPTF3U256;
3178	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256,(PRTUINT256U puDst, PCRTUINT256U puSrc));
3179	typedef FNIEMAIMPLMEDIAOPTF2U256 *PFNIEMAIMPLMEDIAOPTF2U256;
3180	FNIEMAIMPLMEDIAF2U64 iemAImpl_pshufb_u64, iemAImpl_pshufb_u64_fallback;
3181	FNIEMAIMPLMEDIAF2U64 iemAImpl_pand_u64, iemAImpl_pandn_u64, iemAImpl_por_u64, iemAImpl_pxor_u64;
3182	FNIEMAIMPLMEDIAF2U64 iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
3183	FNIEMAIMPLMEDIAF2U64 iemAImpl_pcmpgtb_u64, iemAImpl_pcmpgtw_u64, iemAImpl_pcmpgtd_u64;
3184	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddb_u64, iemAImpl_paddsb_u64, iemAImpl_paddusb_u64;
3185	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddw_u64, iemAImpl_paddsw_u64, iemAImpl_paddusw_u64;
3186	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddd_u64;
3187	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddq_u64;
3188	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubb_u64, iemAImpl_psubsb_u64, iemAImpl_psubusb_u64;
3189	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubw_u64, iemAImpl_psubsw_u64, iemAImpl_psubusw_u64;
3190	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubd_u64;
3191	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubq_u64;
3192	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmaddwd_u64, iemAImpl_pmaddwd_u64_fallback;
3193	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmullw_u64, iemAImpl_pmulhw_u64;
3194	FNIEMAIMPLMEDIAF2U64 iemAImpl_pminub_u64, iemAImpl_pmaxub_u64;
3195	FNIEMAIMPLMEDIAF2U64 iemAImpl_pminsw_u64, iemAImpl_pmaxsw_u64;
3196	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsb_u64, iemAImpl_pabsb_u64_fallback;
3197	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsw_u64, iemAImpl_pabsw_u64_fallback;
3198	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsd_u64, iemAImpl_pabsd_u64_fallback;
3199	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignb_u64, iemAImpl_psignb_u64_fallback;
3200	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignw_u64, iemAImpl_psignw_u64_fallback;
3201	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignd_u64, iemAImpl_psignd_u64_fallback;
3202	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddw_u64, iemAImpl_phaddw_u64_fallback;
3203	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddd_u64, iemAImpl_phaddd_u64_fallback;
3204	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubw_u64, iemAImpl_phsubw_u64_fallback;
3205	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubd_u64, iemAImpl_phsubd_u64_fallback;
3206	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddsw_u64, iemAImpl_phaddsw_u64_fallback;
3207	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubsw_u64, iemAImpl_phsubsw_u64_fallback;
3208	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmaddubsw_u64, iemAImpl_pmaddubsw_u64_fallback;
3209	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmulhrsw_u64, iemAImpl_pmulhrsw_u64_fallback;
3210	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmuludq_u64;
3211	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllw_u64, iemAImpl_psrlw_u64, iemAImpl_psraw_u64;
3212	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pslld_u64, iemAImpl_psrld_u64, iemAImpl_psrad_u64;
3213	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllq_u64, iemAImpl_psrlq_u64;
3214	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packsswb_u64, iemAImpl_packuswb_u64;
3215	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packssdw_u64;
3216	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhuw_u64;
3217	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pavgb_u64, iemAImpl_pavgw_u64;
3218	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psadbw_u64;
3219
3220	FNIEMAIMPLMEDIAF2U128 iemAImpl_pshufb_u128, iemAImpl_pshufb_u128_fallback;
3221	FNIEMAIMPLMEDIAF2U128 iemAImpl_pand_u128, iemAImpl_pandn_u128, iemAImpl_por_u128, iemAImpl_pxor_u128;
3222	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
3223	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpeqq_u128, iemAImpl_pcmpeqq_u128_fallback;
3224	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpgtb_u128, iemAImpl_pcmpgtw_u128, iemAImpl_pcmpgtd_u128;
3225	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpgtq_u128, iemAImpl_pcmpgtq_u128_fallback;
3226	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddb_u128, iemAImpl_paddsb_u128, iemAImpl_paddusb_u128;
3227	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddw_u128, iemAImpl_paddsw_u128, iemAImpl_paddusw_u128;
3228	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddd_u128;
3229	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddq_u128;
3230	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubb_u128, iemAImpl_psubsb_u128, iemAImpl_psubusb_u128;
3231	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubw_u128, iemAImpl_psubsw_u128, iemAImpl_psubusw_u128;
3232	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubd_u128;
3233	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubq_u128;
3234	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmullw_u128, iemAImpl_pmullw_u128_fallback;
3235	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulhw_u128;
3236	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulld_u128, iemAImpl_pmulld_u128_fallback;
3237	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaddwd_u128, iemAImpl_pmaddwd_u128_fallback;
3238	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminub_u128;
3239	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminud_u128, iemAImpl_pminud_u128_fallback;
3240	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminuw_u128, iemAImpl_pminuw_u128_fallback;
3241	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsb_u128, iemAImpl_pminsb_u128_fallback;
3242	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsd_u128, iemAImpl_pminsd_u128_fallback;
3243	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsw_u128, iemAImpl_pminsw_u128_fallback;
3244	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxub_u128;
3245	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxud_u128, iemAImpl_pmaxud_u128_fallback;
3246	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxuw_u128, iemAImpl_pmaxuw_u128_fallback;
3247	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsb_u128, iemAImpl_pmaxsb_u128_fallback;
3248	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsw_u128;
3249	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsd_u128, iemAImpl_pmaxsd_u128_fallback;
3250	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsb_u128, iemAImpl_pabsb_u128_fallback;
3251	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsw_u128, iemAImpl_pabsw_u128_fallback;
3252	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsd_u128, iemAImpl_pabsd_u128_fallback;
3253	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignb_u128, iemAImpl_psignb_u128_fallback;
3254	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignw_u128, iemAImpl_psignw_u128_fallback;
3255	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignd_u128, iemAImpl_psignd_u128_fallback;
3256	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddw_u128, iemAImpl_phaddw_u128_fallback;
3257	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddd_u128, iemAImpl_phaddd_u128_fallback;
3258	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubw_u128, iemAImpl_phsubw_u128_fallback;
3259	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubd_u128, iemAImpl_phsubd_u128_fallback;
3260	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddsw_u128, iemAImpl_phaddsw_u128_fallback;
3261	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubsw_u128, iemAImpl_phsubsw_u128_fallback;
3262	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaddubsw_u128, iemAImpl_pmaddubsw_u128_fallback;
3263	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulhrsw_u128, iemAImpl_pmulhrsw_u128_fallback;
3264	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmuludq_u128;
3265	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaddwd_u128, iemAImpl_pmaddwd_u128_fallback;
3266	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packsswb_u128, iemAImpl_packuswb_u128;
3267	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packssdw_u128, iemAImpl_packusdw_u128;
3268	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllw_u128, iemAImpl_psrlw_u128, iemAImpl_psraw_u128;
3269	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pslld_u128, iemAImpl_psrld_u128, iemAImpl_psrad_u128;
3270	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllq_u128, iemAImpl_psrlq_u128;
3271	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhuw_u128;
3272	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pavgb_u128, iemAImpl_pavgw_u128;
3273	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psadbw_u128;
3274	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuldq_u128, iemAImpl_pmuldq_u128_fallback;
3275	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpcklps_u128, iemAImpl_unpcklpd_u128;
3276	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpckhps_u128, iemAImpl_unpckhpd_u128;
3277	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phminposuw_u128, iemAImpl_phminposuw_u128_fallback;
3278
3279	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpshufb_u128, iemAImpl_vpshufb_u128_fallback;
3280	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpand_u128, iemAImpl_vpand_u128_fallback;
3281	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpandn_u128, iemAImpl_vpandn_u128_fallback;
3282	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpor_u128, iemAImpl_vpor_u128_fallback;
3283	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpxor_u128, iemAImpl_vpxor_u128_fallback;
3284	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqb_u128, iemAImpl_vpcmpeqb_u128_fallback;
3285	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqw_u128, iemAImpl_vpcmpeqw_u128_fallback;
3286	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqd_u128, iemAImpl_vpcmpeqd_u128_fallback;
3287	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqq_u128, iemAImpl_vpcmpeqq_u128_fallback;
3288	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtb_u128, iemAImpl_vpcmpgtb_u128_fallback;
3289	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtw_u128, iemAImpl_vpcmpgtw_u128_fallback;
3290	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtd_u128, iemAImpl_vpcmpgtd_u128_fallback;
3291	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtq_u128, iemAImpl_vpcmpgtq_u128_fallback;
3292	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddb_u128, iemAImpl_vpaddb_u128_fallback;
3293	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddw_u128, iemAImpl_vpaddw_u128_fallback;
3294	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddd_u128, iemAImpl_vpaddd_u128_fallback;
3295	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddq_u128, iemAImpl_vpaddq_u128_fallback;
3296	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubb_u128, iemAImpl_vpsubb_u128_fallback;
3297	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubw_u128, iemAImpl_vpsubw_u128_fallback;
3298	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubd_u128, iemAImpl_vpsubd_u128_fallback;
3299	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubq_u128, iemAImpl_vpsubq_u128_fallback;
3300	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminub_u128, iemAImpl_vpminub_u128_fallback;
3301	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminuw_u128, iemAImpl_vpminuw_u128_fallback;
3302	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminud_u128, iemAImpl_vpminud_u128_fallback;
3303	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsb_u128, iemAImpl_vpminsb_u128_fallback;
3304	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsw_u128, iemAImpl_vpminsw_u128_fallback;
3305	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsd_u128, iemAImpl_vpminsd_u128_fallback;
3306	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxub_u128, iemAImpl_vpmaxub_u128_fallback;
3307	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxuw_u128, iemAImpl_vpmaxuw_u128_fallback;
3308	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxud_u128, iemAImpl_vpmaxud_u128_fallback;
3309	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsb_u128, iemAImpl_vpmaxsb_u128_fallback;
3310	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsw_u128, iemAImpl_vpmaxsw_u128_fallback;
3311	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsd_u128, iemAImpl_vpmaxsd_u128_fallback;
3312	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpacksswb_u128, iemAImpl_vpacksswb_u128_fallback;
3313	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackssdw_u128, iemAImpl_vpackssdw_u128_fallback;
3314	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackuswb_u128, iemAImpl_vpackuswb_u128_fallback;
3315	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackusdw_u128, iemAImpl_vpackusdw_u128_fallback;
3316	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmullw_u128, iemAImpl_vpmullw_u128_fallback;
3317	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulld_u128, iemAImpl_vpmulld_u128_fallback;
3318	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhw_u128, iemAImpl_vpmulhw_u128_fallback;
3319	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhuw_u128, iemAImpl_vpmulhuw_u128_fallback;
3320	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgb_u128, iemAImpl_vpavgb_u128_fallback;
3321	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgw_u128, iemAImpl_vpavgw_u128_fallback;
3322	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignb_u128, iemAImpl_vpsignb_u128_fallback;
3323	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignw_u128, iemAImpl_vpsignw_u128_fallback;
3324	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignd_u128, iemAImpl_vpsignd_u128_fallback;
3325	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddw_u128, iemAImpl_vphaddw_u128_fallback;
3326	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddd_u128, iemAImpl_vphaddd_u128_fallback;
3327	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubw_u128, iemAImpl_vphsubw_u128_fallback;
3328	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubd_u128, iemAImpl_vphsubd_u128_fallback;
3329	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddsw_u128, iemAImpl_vphaddsw_u128_fallback;
3330	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubsw_u128, iemAImpl_vphsubsw_u128_fallback;
3331	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddubsw_u128, iemAImpl_vpmaddubsw_u128_fallback;
3332	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhrsw_u128, iemAImpl_vpmulhrsw_u128_fallback;
3333	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsadbw_u128, iemAImpl_vpsadbw_u128_fallback;
3334	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuldq_u128, iemAImpl_vpmuldq_u128_fallback;
3335	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuludq_u128, iemAImpl_vpmuludq_u128_fallback;
3336	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsb_u128, iemAImpl_vpsubsb_u128_fallback;
3337	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsw_u128, iemAImpl_vpsubsw_u128_fallback;
3338	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusb_u128, iemAImpl_vpsubusb_u128_fallback;
3339	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusw_u128, iemAImpl_vpsubusw_u128_fallback;
3340	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusb_u128, iemAImpl_vpaddusb_u128_fallback;
3341	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusw_u128, iemAImpl_vpaddusw_u128_fallback;
3342	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsb_u128, iemAImpl_vpaddsb_u128_fallback;
3343	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsw_u128, iemAImpl_vpaddsw_u128_fallback;
3344	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllw_u128, iemAImpl_vpsllw_u128_fallback;
3345	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpslld_u128, iemAImpl_vpslld_u128_fallback;
3346	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllq_u128, iemAImpl_vpsllq_u128_fallback;
3347	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsraw_u128, iemAImpl_vpsraw_u128_fallback;
3348	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrad_u128, iemAImpl_vpsrad_u128_fallback;
3349	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlw_u128, iemAImpl_vpsrlw_u128_fallback;
3350	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrld_u128, iemAImpl_vpsrld_u128_fallback;
3351	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlq_u128, iemAImpl_vpsrlq_u128_fallback;
3352	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddwd_u128, iemAImpl_vpmaddwd_u128_fallback;
3353
3354	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsb_u128, iemAImpl_vpabsb_u128_fallback;
3355	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsw_u128, iemAImpl_vpabsd_u128_fallback;
3356	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsd_u128, iemAImpl_vpabsw_u128_fallback;
3357	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vphminposuw_u128, iemAImpl_vphminposuw_u128_fallback;
3358
3359	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpshufb_u256, iemAImpl_vpshufb_u256_fallback;
3360	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpand_u256, iemAImpl_vpand_u256_fallback;
3361	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpandn_u256, iemAImpl_vpandn_u256_fallback;
3362	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpor_u256, iemAImpl_vpor_u256_fallback;
3363	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpxor_u256, iemAImpl_vpxor_u256_fallback;
3364	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqb_u256, iemAImpl_vpcmpeqb_u256_fallback;
3365	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqw_u256, iemAImpl_vpcmpeqw_u256_fallback;
3366	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqd_u256, iemAImpl_vpcmpeqd_u256_fallback;
3367	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqq_u256, iemAImpl_vpcmpeqq_u256_fallback;
3368	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtb_u256, iemAImpl_vpcmpgtb_u256_fallback;
3369	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtw_u256, iemAImpl_vpcmpgtw_u256_fallback;
3370	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtd_u256, iemAImpl_vpcmpgtd_u256_fallback;
3371	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtq_u256, iemAImpl_vpcmpgtq_u256_fallback;
3372	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddb_u256, iemAImpl_vpaddb_u256_fallback;
3373	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddw_u256, iemAImpl_vpaddw_u256_fallback;
3374	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddd_u256, iemAImpl_vpaddd_u256_fallback;
3375	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddq_u256, iemAImpl_vpaddq_u256_fallback;
3376	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubb_u256, iemAImpl_vpsubb_u256_fallback;
3377	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubw_u256, iemAImpl_vpsubw_u256_fallback;
3378	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubd_u256, iemAImpl_vpsubd_u256_fallback;
3379	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubq_u256, iemAImpl_vpsubq_u256_fallback;
3380	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminub_u256, iemAImpl_vpminub_u256_fallback;
3381	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminuw_u256, iemAImpl_vpminuw_u256_fallback;
3382	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminud_u256, iemAImpl_vpminud_u256_fallback;
3383	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsb_u256, iemAImpl_vpminsb_u256_fallback;
3384	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsw_u256, iemAImpl_vpminsw_u256_fallback;
3385	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsd_u256, iemAImpl_vpminsd_u256_fallback;
3386	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxub_u256, iemAImpl_vpmaxub_u256_fallback;
3387	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxuw_u256, iemAImpl_vpmaxuw_u256_fallback;
3388	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxud_u256, iemAImpl_vpmaxud_u256_fallback;
3389	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsb_u256, iemAImpl_vpmaxsb_u256_fallback;
3390	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsw_u256, iemAImpl_vpmaxsw_u256_fallback;
3391	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsd_u256, iemAImpl_vpmaxsd_u256_fallback;
3392	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpacksswb_u256, iemAImpl_vpacksswb_u256_fallback;
3393	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackssdw_u256, iemAImpl_vpackssdw_u256_fallback;
3394	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackuswb_u256, iemAImpl_vpackuswb_u256_fallback;
3395	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackusdw_u256, iemAImpl_vpackusdw_u256_fallback;
3396	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmullw_u256, iemAImpl_vpmullw_u256_fallback;
3397	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulld_u256, iemAImpl_vpmulld_u256_fallback;
3398	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhw_u256, iemAImpl_vpmulhw_u256_fallback;
3399	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhuw_u256, iemAImpl_vpmulhuw_u256_fallback;
3400	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgb_u256, iemAImpl_vpavgb_u256_fallback;
3401	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgw_u256, iemAImpl_vpavgw_u256_fallback;
3402	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignb_u256, iemAImpl_vpsignb_u256_fallback;
3403	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignw_u256, iemAImpl_vpsignw_u256_fallback;
3404	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignd_u256, iemAImpl_vpsignd_u256_fallback;
3405	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddw_u256, iemAImpl_vphaddw_u256_fallback;
3406	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddd_u256, iemAImpl_vphaddd_u256_fallback;
3407	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubw_u256, iemAImpl_vphsubw_u256_fallback;
3408	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubd_u256, iemAImpl_vphsubd_u256_fallback;
3409	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddsw_u256, iemAImpl_vphaddsw_u256_fallback;
3410	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubsw_u256, iemAImpl_vphsubsw_u256_fallback;
3411	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddubsw_u256, iemAImpl_vpmaddubsw_u256_fallback;
3412	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhrsw_u256, iemAImpl_vpmulhrsw_u256_fallback;
3413	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsadbw_u256, iemAImpl_vpsadbw_u256_fallback;
3414	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuldq_u256, iemAImpl_vpmuldq_u256_fallback;
3415	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuludq_u256, iemAImpl_vpmuludq_u256_fallback;
3416	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsb_u256, iemAImpl_vpsubsb_u256_fallback;
3417	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsw_u256, iemAImpl_vpsubsw_u256_fallback;
3418	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusb_u256, iemAImpl_vpsubusb_u256_fallback;
3419	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusw_u256, iemAImpl_vpsubusw_u256_fallback;
3420	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusb_u256, iemAImpl_vpaddusb_u256_fallback;
3421	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusw_u256, iemAImpl_vpaddusw_u256_fallback;
3422	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsb_u256, iemAImpl_vpaddsb_u256_fallback;
3423	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsw_u256, iemAImpl_vpaddsw_u256_fallback;
3424	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllw_u256, iemAImpl_vpsllw_u256_fallback;
3425	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpslld_u256, iemAImpl_vpslld_u256_fallback;
3426	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllq_u256, iemAImpl_vpsllq_u256_fallback;
3427	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsraw_u256, iemAImpl_vpsraw_u256_fallback;
3428	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrad_u256, iemAImpl_vpsrad_u256_fallback;
3429	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlw_u256, iemAImpl_vpsrlw_u256_fallback;
3430	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrld_u256, iemAImpl_vpsrld_u256_fallback;
3431	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlq_u256, iemAImpl_vpsrlq_u256_fallback;
3432	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddwd_u256, iemAImpl_vpmaddwd_u256_fallback;
3433
3434	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsb_u256, iemAImpl_vpabsb_u256_fallback;
3435	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsw_u256, iemAImpl_vpabsw_u256_fallback;
3436	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsd_u256, iemAImpl_vpabsd_u256_fallback;
3437	/** @} */
3438
3439	/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
3440	* @{ */
3441	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
3442	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
3443	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpcklbw_u128, iemAImpl_vpunpcklbw_u128_fallback,
3444	iemAImpl_vpunpcklwd_u128, iemAImpl_vpunpcklwd_u128_fallback,
3445	iemAImpl_vpunpckldq_u128, iemAImpl_vpunpckldq_u128_fallback,
3446	iemAImpl_vpunpcklqdq_u128, iemAImpl_vpunpcklqdq_u128_fallback,
3447	iemAImpl_vunpcklps_u128, iemAImpl_vunpcklps_u128_fallback,
3448	iemAImpl_vunpcklpd_u128, iemAImpl_vunpcklpd_u128_fallback,
3449	iemAImpl_vunpckhps_u128, iemAImpl_vunpckhps_u128_fallback,
3450	iemAImpl_vunpckhpd_u128, iemAImpl_vunpckhpd_u128_fallback;
3451
3452	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpcklbw_u256, iemAImpl_vpunpcklbw_u256_fallback,
3453	iemAImpl_vpunpcklwd_u256, iemAImpl_vpunpcklwd_u256_fallback,
3454	iemAImpl_vpunpckldq_u256, iemAImpl_vpunpckldq_u256_fallback,
3455	iemAImpl_vpunpcklqdq_u256, iemAImpl_vpunpcklqdq_u256_fallback,
3456	iemAImpl_vunpcklps_u256, iemAImpl_vunpcklps_u256_fallback,
3457	iemAImpl_vunpcklpd_u256, iemAImpl_vunpcklpd_u256_fallback,
3458	iemAImpl_vunpckhps_u256, iemAImpl_vunpckhps_u256_fallback,
3459	iemAImpl_vunpckhpd_u256, iemAImpl_vunpckhpd_u256_fallback;
3460	/** @} */
3461
3462	/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
3463	* @{ */
3464	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
3465	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
3466	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpckhbw_u128, iemAImpl_vpunpckhbw_u128_fallback,
3467	iemAImpl_vpunpckhwd_u128, iemAImpl_vpunpckhwd_u128_fallback,
3468	iemAImpl_vpunpckhdq_u128, iemAImpl_vpunpckhdq_u128_fallback,
3469	iemAImpl_vpunpckhqdq_u128, iemAImpl_vpunpckhqdq_u128_fallback;
3470	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpckhbw_u256, iemAImpl_vpunpckhbw_u256_fallback,
3471	iemAImpl_vpunpckhwd_u256, iemAImpl_vpunpckhwd_u256_fallback,
3472	iemAImpl_vpunpckhdq_u256, iemAImpl_vpunpckhdq_u256_fallback,
3473	iemAImpl_vpunpckhqdq_u256, iemAImpl_vpunpckhqdq_u256_fallback;
3474	/** @} */
3475
3476	/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
3477	* @{ */
3478	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3479	typedef FNIEMAIMPLMEDIAPSHUFU128 *PFNIEMAIMPLMEDIAPSHUFU128;
3480	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
3481	typedef FNIEMAIMPLMEDIAPSHUFU256 *PFNIEMAIMPLMEDIAPSHUFU256;
3482	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw_u64,(uint64_t puDst, uint64_t const puSrc, uint8_t bEvil));
3483	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_pshufhw_u128, iemAImpl_pshuflw_u128, iemAImpl_pshufd_u128;
3484	#ifndef IEM_WITHOUT_ASSEMBLY
3485	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256, iemAImpl_vpshuflw_u256, iemAImpl_vpshufd_u256;
3486	#endif
3487	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256_fallback, iemAImpl_vpshuflw_u256_fallback, iemAImpl_vpshufd_u256_fallback;
3488	/** @} */
3489
3490	/** @name Media (SSE/MMX/AVX) operation: Shift Immediate Stuff (evil)
3491	* @{ */
3492	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU64,(uint64_t *puDst, uint8_t bShift));
3493	typedef FNIEMAIMPLMEDIAPSHIFTU64 *PFNIEMAIMPLMEDIAPSHIFTU64;
3494	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU128,(PRTUINT128U puDst, uint8_t bShift));
3495	typedef FNIEMAIMPLMEDIAPSHIFTU128 *PFNIEMAIMPLMEDIAPSHIFTU128;
3496	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU256,(PRTUINT256U puDst, uint8_t bShift));
3497	typedef FNIEMAIMPLMEDIAPSHIFTU256 *PFNIEMAIMPLMEDIAPSHIFTU256;
3498	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psllw_imm_u64, iemAImpl_pslld_imm_u64, iemAImpl_psllq_imm_u64;
3499	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psrlw_imm_u64, iemAImpl_psrld_imm_u64, iemAImpl_psrlq_imm_u64;
3500	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psraw_imm_u64, iemAImpl_psrad_imm_u64;
3501	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psllw_imm_u128, iemAImpl_pslld_imm_u128, iemAImpl_psllq_imm_u128;
3502	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psrlw_imm_u128, iemAImpl_psrld_imm_u128, iemAImpl_psrlq_imm_u128;
3503	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psraw_imm_u128, iemAImpl_psrad_imm_u128;
3504	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_pslldq_imm_u128, iemAImpl_psrldq_imm_u128;
3505	/** @} */
3506
3507	/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
3508	* @{ */
3509	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(uint64_t pu64Dst, uint64_t const puSrc));
3510	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(uint64_t *pu64Dst, PCRTUINT128U puSrc));
3511	#ifndef IEM_WITHOUT_ASSEMBLY
3512	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
3513	#endif
3514	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256_fallback,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
3515	/** @} */
3516
3517	/** @name Media (SSE/MMX/AVX) operations: Variable Blend Packed Bytes/R32/R64.
3518	* @{ */
3519	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puMask));
3520	typedef FNIEMAIMPLBLENDU128 *PFNIEMAIMPLBLENDU128;
3521	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, PCRTUINT128U puMask));
3522	typedef FNIEMAIMPLAVXBLENDU128 *PFNIEMAIMPLAVXBLENDU128;
3523	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, PCRTUINT256U puMask));
3524	typedef FNIEMAIMPLAVXBLENDU256 *PFNIEMAIMPLAVXBLENDU256;
3525
3526	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128;
3527	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128_fallback;
3528	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128;
3529	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128_fallback;
3530	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256;
3531	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256_fallback;
3532
3533	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128;
3534	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128_fallback;
3535	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128;
3536	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128_fallback;
3537	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256;
3538	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256_fallback;
3539
3540	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128;
3541	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128_fallback;
3542	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128;
3543	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128_fallback;
3544	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256;
3545	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256_fallback;
3546	/** @} */
3547
3548
3549	/** @name Media (SSE/MMX/AVX) operation: Sort this later
3550	* @{ */
3551	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
3552	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
3553	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovshdup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
3554	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovshdup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
3555	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
3556	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
3557
3558	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3559	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3560	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3561	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3562	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3563
3564	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3565	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3566	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3567	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3568	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3569
3570	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3571	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3572	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
3573	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3574	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3575
3576	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3577	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3578	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3579	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3580	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3581
3582	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3583	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3584	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3585	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3586	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3587
3588	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3589	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3590	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3591	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3592	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3593
3594	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3595	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3596	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3597	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3598	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3599
3600	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3601	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3602	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3603	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3604	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3605
3606	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3607	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3608	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
3609	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3610	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3611
3612	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3613	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3614	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3615	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3616	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3617
3618	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3619	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3620	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3621	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3622	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3623
3624	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3625	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3626	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3627	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3628	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3629
3630	IEM_DECL_IMPL_DEF(void, iemAImpl_shufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3631	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3632	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3633	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3634	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3635
3636	IEM_DECL_IMPL_DEF(void, iemAImpl_shufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3637	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3638	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3639	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3640	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3641
3642	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
3643	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64_fallback,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
3644
3645	IEM_DECL_IMPL_DEF(void, iemAImpl_pinsrw_u64,(uint64_t *pu64Dst, uint16_t u16Src, uint8_t bEvil));
3646	IEM_DECL_IMPL_DEF(void, iemAImpl_pinsrw_u128,(PRTUINT128U puDst, uint16_t u16Src, uint8_t bEvil));
3647	IEM_DECL_IMPL_DEF(void, iemAImpl_vpinsrw_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint16_t u16Src, uint8_t bEvil));
3648	IEM_DECL_IMPL_DEF(void, iemAImpl_vpinsrw_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint16_t u16Src, uint8_t bEvil));
3649
3650	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3651	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3652	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3653	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3654	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3655
3656	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3657	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3658	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3659	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3660	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3661
3662
3663	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3664	typedef FNIEMAIMPLMEDIAOPTF2U128IMM8 *PFNIEMAIMPLMEDIAOPTF2U128IMM8;
3665	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
3666	typedef FNIEMAIMPLMEDIAOPTF2U256IMM8 *PFNIEMAIMPLMEDIAOPTF2U256IMM8;
3667	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3668	typedef FNIEMAIMPLMEDIAOPTF3U128IMM8 *PFNIEMAIMPLMEDIAOPTF3U128IMM8;
3669	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3670	typedef FNIEMAIMPLMEDIAOPTF3U256IMM8 *PFNIEMAIMPLMEDIAOPTF3U256IMM8;
3671
3672	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_palignr_u128, iemAImpl_palignr_u128_fallback;
3673	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pblendw_u128, iemAImpl_pblendw_u128_fallback;
3674	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendps_u128, iemAImpl_blendps_u128_fallback;
3675	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendpd_u128, iemAImpl_blendpd_u128_fallback;
3676
3677	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpalignr_u128, iemAImpl_vpalignr_u128_fallback;
3678	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendw_u128, iemAImpl_vpblendw_u128_fallback;
3679	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendd_u128, iemAImpl_vpblendd_u128_fallback;
3680	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendps_u128, iemAImpl_vblendps_u128_fallback;
3681	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendpd_u128, iemAImpl_vblendpd_u128_fallback;
3682
3683	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpalignr_u256, iemAImpl_vpalignr_u256_fallback;
3684	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendw_u256, iemAImpl_vpblendw_u256_fallback;
3685	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendd_u256, iemAImpl_vpblendd_u256_fallback;
3686	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendps_u256, iemAImpl_vblendps_u256_fallback;
3687	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendpd_u256, iemAImpl_vblendpd_u256_fallback;
3688	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2i128_u256, iemAImpl_vperm2i128_u256_fallback;
3689	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2f128_u256, iemAImpl_vperm2f128_u256_fallback;
3690
3691	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesimc_u128, iemAImpl_aesimc_u128_fallback;
3692	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenc_u128, iemAImpl_aesenc_u128_fallback;
3693	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenclast_u128, iemAImpl_aesenclast_u128_fallback;
3694	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdec_u128, iemAImpl_aesdec_u128_fallback;
3695	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdeclast_u128, iemAImpl_aesdeclast_u128_fallback;
3696
3697	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesimc_u128, iemAImpl_vaesimc_u128_fallback;
3698	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenc_u128, iemAImpl_vaesenc_u128_fallback;
3699	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenclast_u128, iemAImpl_vaesenclast_u128_fallback;
3700	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdec_u128, iemAImpl_vaesdec_u128_fallback;
3701	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdeclast_u128, iemAImpl_vaesdeclast_u128_fallback;
3702
3703	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_aeskeygenassist_u128, iemAImpl_aeskeygenassist_u128_fallback;
3704
3705	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vaeskeygenassist_u128, iemAImpl_vaeskeygenassist_u128_fallback;
3706
3707	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1nexte_u128, iemAImpl_sha1nexte_u128_fallback;
3708	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg1_u128, iemAImpl_sha1msg1_u128_fallback;
3709	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg2_u128, iemAImpl_sha1msg2_u128_fallback;
3710	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg1_u128, iemAImpl_sha256msg1_u128_fallback;
3711	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg2_u128, iemAImpl_sha256msg2_u128_fallback;
3712	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_sha1rnds4_u128, iemAImpl_sha1rnds4_u128_fallback;
3713	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
3714	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
3715
3716	typedef struct IEMPCMPISTRXSRC
3717	{
3718	RTUINT128U uSrc1;
3719	RTUINT128U uSrc2;
3720	} IEMPCMPISTRXSRC;
3721	typedef IEMPCMPISTRXSRC *PIEMPCMPISTRXSRC;
3722	typedef const IEMPCMPISTRXSRC *PCIEMPCMPISTRXSRC;
3723
3724	typedef struct IEMPCMPESTRXSRC
3725	{
3726	RTUINT128U uSrc1;
3727	RTUINT128U uSrc2;
3728	uint64_t u64Rax;
3729	uint64_t u64Rdx;
3730	} IEMPCMPESTRXSRC;
3731	typedef IEMPCMPESTRXSRC *PIEMPCMPESTRXSRC;
3732	typedef const IEMPCMPESTRXSRC *PCIEMPCMPESTRXSRC;
3733
3734	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPISTRIU128IMM8,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
3735	typedef FNIEMAIMPLPCMPISTRIU128IMM8 *PFNIEMAIMPLPCMPISTRIU128IMM8;
3736	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRIU128IMM8,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
3737	typedef FNIEMAIMPLPCMPESTRIU128IMM8 *PFNIEMAIMPLPCMPESTRIU128IMM8;
3738
3739	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPISTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
3740	typedef FNIEMAIMPLPCMPISTRMU128IMM8 *PFNIEMAIMPLPCMPISTRMU128IMM8;
3741	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
3742	typedef FNIEMAIMPLPCMPESTRMU128IMM8 *PFNIEMAIMPLPCMPESTRMU128IMM8;
3743
3744	FNIEMAIMPLPCMPISTRIU128IMM8 iemAImpl_pcmpistri_u128, iemAImpl_pcmpistri_u128_fallback;
3745	FNIEMAIMPLPCMPESTRIU128IMM8 iemAImpl_pcmpestri_u128, iemAImpl_pcmpestri_u128_fallback;
3746	FNIEMAIMPLPCMPISTRMU128IMM8 iemAImpl_pcmpistrm_u128, iemAImpl_pcmpistrm_u128_fallback;
3747	FNIEMAIMPLPCMPESTRMU128IMM8 iemAImpl_pcmpestrm_u128, iemAImpl_pcmpestrm_u128_fallback;
3748
3749	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pclmulqdq_u128, iemAImpl_pclmulqdq_u128_fallback;
3750	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpclmulqdq_u128, iemAImpl_vpclmulqdq_u128_fallback;
3751
3752	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_mpsadbw_u128, iemAImpl_mpsadbw_u128_fallback;
3753	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vmpsadbw_u128, iemAImpl_vmpsadbw_u128_fallback;
3754	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vmpsadbw_u256, iemAImpl_vmpsadbw_u256_fallback;
3755
3756	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsllw_imm_u128, iemAImpl_vpsllw_imm_u128_fallback;
3757	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsllw_imm_u256, iemAImpl_vpsllw_imm_u256_fallback;
3758	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpslld_imm_u128, iemAImpl_vpslld_imm_u128_fallback;
3759	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpslld_imm_u256, iemAImpl_vpslld_imm_u256_fallback;
3760	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsllq_imm_u128, iemAImpl_vpsllq_imm_u128_fallback;
3761	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsllq_imm_u256, iemAImpl_vpsllq_imm_u256_fallback;
3762
3763	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsraw_imm_u128, iemAImpl_vpsraw_imm_u128_fallback;
3764	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsraw_imm_u256, iemAImpl_vpsraw_imm_u256_fallback;
3765	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrad_imm_u128, iemAImpl_vpsrad_imm_u128_fallback;
3766	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrad_imm_u256, iemAImpl_vpsrad_imm_u256_fallback;
3767
3768	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrlw_imm_u128, iemAImpl_vpsrlw_imm_u128_fallback;
3769	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrlw_imm_u256, iemAImpl_vpsrlw_imm_u256_fallback;
3770	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrld_imm_u128, iemAImpl_vpsrld_imm_u128_fallback;
3771	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrld_imm_u256, iemAImpl_vpsrld_imm_u256_fallback;
3772	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrlq_imm_u128, iemAImpl_vpsrlq_imm_u128_fallback;
3773	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrlq_imm_u256, iemAImpl_vpsrlq_imm_u256_fallback;
3774	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrldq_imm_u128, iemAImpl_vpsrldq_imm_u128_fallback;
3775	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrldq_imm_u256, iemAImpl_vpsrldq_imm_u256_fallback;
3776
3777	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpermilps_u128, iemAImpl_vpermilps_u128_fallback;
3778	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_vpermilps_imm_u128, iemAImpl_vpermilps_imm_u128_fallback;
3779	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpermilps_u256, iemAImpl_vpermilps_u256_fallback;
3780	FNIEMAIMPLMEDIAOPTF2U256IMM8 iemAImpl_vpermilps_imm_u256, iemAImpl_vpermilps_imm_u256_fallback;
3781
3782	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpermilpd_u128, iemAImpl_vpermilpd_u128_fallback;
3783	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_vpermilpd_imm_u128, iemAImpl_vpermilpd_imm_u128_fallback;
3784	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpermilpd_u256, iemAImpl_vpermilpd_u256_fallback;
3785	FNIEMAIMPLMEDIAOPTF2U256IMM8 iemAImpl_vpermilpd_imm_u256, iemAImpl_vpermilpd_imm_u256_fallback;
3786
3787	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllvd_u128, iemAImpl_vpsllvd_u128_fallback;
3788	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllvd_u256, iemAImpl_vpsllvd_u256_fallback;
3789	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllvq_u128, iemAImpl_vpsllvq_u128_fallback;
3790	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllvq_u256, iemAImpl_vpsllvq_u256_fallback;
3791	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsravd_u128, iemAImpl_vpsravd_u128_fallback;
3792	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsravd_u256, iemAImpl_vpsravd_u256_fallback;
3793	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlvd_u128, iemAImpl_vpsrlvd_u128_fallback;
3794	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlvd_u256, iemAImpl_vpsrlvd_u256_fallback;
3795	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlvq_u128, iemAImpl_vpsrlvq_u128_fallback;
3796	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlvq_u256, iemAImpl_vpsrlvq_u256_fallback;
3797	/** @} */
3798
3799	/** @name Media Odds and Ends
3800	* @{ */
3801	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U8,(uint32_t *puDst, uint8_t uSrc));
3802	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U16,(uint32_t *puDst, uint16_t uSrc));
3803	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U32,(uint32_t *puDst, uint32_t uSrc));
3804	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U64,(uint32_t *puDst, uint64_t uSrc));
3805	FNIEMAIMPLCR32U8 iemAImpl_crc32_u8, iemAImpl_crc32_u8_fallback;
3806	FNIEMAIMPLCR32U16 iemAImpl_crc32_u16, iemAImpl_crc32_u16_fallback;
3807	FNIEMAIMPLCR32U32 iemAImpl_crc32_u32, iemAImpl_crc32_u32_fallback;
3808	FNIEMAIMPLCR32U64 iemAImpl_crc32_u64, iemAImpl_crc32_u64_fallback;
3809
3810	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL128,(PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint32_t *pEFlags));
3811	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL256,(PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint32_t *pEFlags));
3812	FNIEMAIMPLF2EFL128 iemAImpl_ptest_u128;
3813	FNIEMAIMPLF2EFL256 iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback;
3814
3815	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I32U64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int32_t pi32Dst, const uint64_t pu64Src)); / pu64Src is a double precision floating point. */
3816	typedef FNIEMAIMPLSSEF2I32U64 *PFNIEMAIMPLSSEF2I32U64;
3817	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I64U64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int64_t pi64Dst, const uint64_t pu64Src)); / pu64Src is a double precision floating point. */
3818	typedef FNIEMAIMPLSSEF2I64U64 *PFNIEMAIMPLSSEF2I64U64;
3819	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I32U32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int32_t pi32Dst, const uint32_t pu32Src)); / pu32Src is a single precision floating point. */
3820	typedef FNIEMAIMPLSSEF2I32U32 *PFNIEMAIMPLSSEF2I32U32;
3821	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I64U32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int64_t pi64Dst, const uint32_t pu32Src)); / pu32Src is a single precision floating point. */
3822	typedef FNIEMAIMPLSSEF2I64U32 *PFNIEMAIMPLSSEF2I64U32;
3823
3824	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvttsd2si_i32_r64;
3825	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvtsd2si_i32_r64;
3826
3827	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvttsd2si_i64_r64;
3828	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvtsd2si_i64_r64;
3829
3830	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvttss2si_i32_r32;
3831	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvtss2si_i32_r32;
3832
3833	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvttss2si_i64_r32;
3834	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvtss2si_i64_r32;
3835
3836	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R32I32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT32U pr32Dst, const int32_t pi32Src));
3837	typedef FNIEMAIMPLSSEF2R32I32 *PFNIEMAIMPLSSEF2R32I32;
3838	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R32I64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT32U pr32Dst, const int64_t pi64Src));
3839	typedef FNIEMAIMPLSSEF2R32I64 *PFNIEMAIMPLSSEF2R32I64;
3840
3841	FNIEMAIMPLSSEF2R32I32 iemAImpl_cvtsi2ss_r32_i32;
3842	FNIEMAIMPLSSEF2R32I64 iemAImpl_cvtsi2ss_r32_i64;
3843
3844	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R64I32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT64U pr64Dst, const int32_t pi32Src));
3845	typedef FNIEMAIMPLSSEF2R64I32 *PFNIEMAIMPLSSEF2R64I32;
3846	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R64I64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT64U pr64Dst, const int64_t pi64Src));
3847	typedef FNIEMAIMPLSSEF2R64I64 *PFNIEMAIMPLSSEF2R64I64;
3848
3849	FNIEMAIMPLSSEF2R64I32 iemAImpl_cvtsi2sd_r64_i32;
3850	FNIEMAIMPLSSEF2R64I64 iemAImpl_cvtsi2sd_r64_i64;
3851
3852
3853	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFLMXCSR128,(uint32_t pfMxcsr, uint32_t pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
3854	typedef FNIEMAIMPLF2EFLMXCSR128 *PFNIEMAIMPLF2EFLMXCSR128;
3855
3856	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_ucomiss_u128;
3857	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback;
3858
3859	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_ucomisd_u128;
3860	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback;
3861
3862	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_comiss_u128;
3863	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback;
3864
3865	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_comisd_u128;
3866	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback;
3867
3868
3869	typedef struct IEMMEDIAF2XMMSRC
3870	{
3871	X86XMMREG uSrc1;
3872	X86XMMREG uSrc2;
3873	} IEMMEDIAF2XMMSRC;
3874	typedef IEMMEDIAF2XMMSRC *PIEMMEDIAF2XMMSRC;
3875	typedef const IEMMEDIAF2XMMSRC *PCIEMMEDIAF2XMMSRC;
3876
3877	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRF2XMMIMM8,(uint32_t *pfMxcsr, PX86XMMREG puDst, PCIEMMEDIAF2XMMSRC puSrc, uint8_t bEvil));
3878	typedef FNIEMAIMPLMXCSRF2XMMIMM8 *PFNIEMAIMPLMXCSRF2XMMIMM8;
3879
3880	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpps_u128;
3881	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmppd_u128;
3882	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpss_u128;
3883	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpsd_u128;
3884	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundss_u128;
3885	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundsd_u128;
3886
3887	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundps_u128, iemAImpl_roundps_u128_fallback;
3888	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundpd_u128, iemAImpl_roundpd_u128_fallback;
3889
3890	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_dpps_u128, iemAImpl_dpps_u128_fallback;
3891	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_dppd_u128, iemAImpl_dppd_u128_fallback;
3892
3893	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU64U128,(uint32_t pfMxcsr, uint64_t pu64Dst, PCX86XMMREG pSrc));
3894	typedef FNIEMAIMPLMXCSRU64U128 *PFNIEMAIMPLMXCSRU64U128;
3895
3896	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvtpd2pi_u128;
3897	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvttpd2pi_u128;
3898
3899	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU128U64,(uint32_t *pfMxcsr, PX86XMMREG pDst, uint64_t u64Src));
3900	typedef FNIEMAIMPLMXCSRU128U64 *PFNIEMAIMPLMXCSRU128U64;
3901
3902	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2ps_u128;
3903	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2pd_u128;
3904
3905	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU64U64,(uint32_t pfMxcsr, uint64_t pu64Dst, uint64_t u64Src));
3906	typedef FNIEMAIMPLMXCSRU64U64 *PFNIEMAIMPLMXCSRU64U64;
3907
3908	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvtps2pi_u128;
3909	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvttps2pi_u128;
3910
3911	/** @} */
3912
3913
3914	/** @name Function tables.
3915	* @{
3916	*/
3917
3918	/**
3919	* Function table for a binary operator providing implementation based on
3920	* operand size.
3921	*/
3922	typedef struct IEMOPBINSIZES
3923	{
3924	PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
3925	PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
3926	PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
3927	PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
3928	} IEMOPBINSIZES;
3929	/** Pointer to a binary operator function table. */
3930	typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
3931
3932
3933	/**
3934	* Function table for a unary operator providing implementation based on
3935	* operand size.
3936	*/
3937	typedef struct IEMOPUNARYSIZES
3938	{
3939	PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
3940	PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
3941	PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
3942	PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
3943	} IEMOPUNARYSIZES;
3944	/** Pointer to a unary operator function table. */
3945	typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
3946
3947
3948	/**
3949	* Function table for a shift operator providing implementation based on
3950	* operand size.
3951	*/
3952	typedef struct IEMOPSHIFTSIZES
3953	{
3954	PFNIEMAIMPLSHIFTU8 pfnNormalU8;
3955	PFNIEMAIMPLSHIFTU16 pfnNormalU16;
3956	PFNIEMAIMPLSHIFTU32 pfnNormalU32;
3957	PFNIEMAIMPLSHIFTU64 pfnNormalU64;
3958	} IEMOPSHIFTSIZES;
3959	/** Pointer to a shift operator function table. */
3960	typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
3961
3962
3963	/**
3964	* Function table for a multiplication or division operation.
3965	*/
3966	typedef struct IEMOPMULDIVSIZES
3967	{
3968	PFNIEMAIMPLMULDIVU8 pfnU8;
3969	PFNIEMAIMPLMULDIVU16 pfnU16;
3970	PFNIEMAIMPLMULDIVU32 pfnU32;
3971	PFNIEMAIMPLMULDIVU64 pfnU64;
3972	} IEMOPMULDIVSIZES;
3973	/** Pointer to a multiplication or division operation function table. */
3974	typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
3975
3976
3977	/**
3978	* Function table for a double precision shift operator providing implementation
3979	* based on operand size.
3980	*/
3981	typedef struct IEMOPSHIFTDBLSIZES
3982	{
3983	PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
3984	PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
3985	PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
3986	} IEMOPSHIFTDBLSIZES;
3987	/** Pointer to a double precision shift function table. */
3988	typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
3989
3990
3991	/**
3992	* Function table for media instruction taking two full sized media source
3993	* registers and one full sized destination register (AVX).
3994	*/
3995	typedef struct IEMOPMEDIAF3
3996	{
3997	PFNIEMAIMPLMEDIAF3U128 pfnU128;
3998	PFNIEMAIMPLMEDIAF3U256 pfnU256;
3999	} IEMOPMEDIAF3;
4000	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
4001	typedef IEMOPMEDIAF3 const *PCIEMOPMEDIAF3;
4002
4003	/** @def IEMOPMEDIAF3_INIT_VARS_EX
4004	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4005	* given functions as initializers. For use in AVX functions where a pair of
4006	* functions are only used once and the function table need not be public. */
4007	#ifndef TST_IEM_CHECK_MC
4008	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4009	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4010	static IEMOPMEDIAF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4011	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4012	# else
4013	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4014	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4015	# endif
4016	#else
4017	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4018	#endif
4019	/** @def IEMOPMEDIAF3_INIT_VARS
4020	* Generate AVX function tables for the @a a_InstrNm instruction.
4021	* @sa IEMOPMEDIAF3_INIT_VARS_EX */
4022	#define IEMOPMEDIAF3_INIT_VARS(a_InstrNm) \
4023	IEMOPMEDIAF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4024	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4025
4026	/**
4027	* Function table for media instruction taking two full sized media source
4028	* registers and one full sized destination register, but no additional state
4029	* (AVX).
4030	*/
4031	typedef struct IEMOPMEDIAOPTF3
4032	{
4033	PFNIEMAIMPLMEDIAOPTF3U128 pfnU128;
4034	PFNIEMAIMPLMEDIAOPTF3U256 pfnU256;
4035	} IEMOPMEDIAOPTF3;
4036	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
4037	typedef IEMOPMEDIAOPTF3 const *PCIEMOPMEDIAOPTF3;
4038
4039	/** @def IEMOPMEDIAOPTF3_INIT_VARS_EX
4040	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4041	* given functions as initializers. For use in AVX functions where a pair of
4042	* functions are only used once and the function table need not be public. */
4043	#ifndef TST_IEM_CHECK_MC
4044	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4045	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4046	static IEMOPMEDIAOPTF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4047	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4048	# else
4049	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4050	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4051	# endif
4052	#else
4053	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4054	#endif
4055	/** @def IEMOPMEDIAOPTF3_INIT_VARS
4056	* Generate AVX function tables for the @a a_InstrNm instruction.
4057	* @sa IEMOPMEDIAOPTF3_INIT_VARS_EX */
4058	#define IEMOPMEDIAOPTF3_INIT_VARS(a_InstrNm) \
4059	IEMOPMEDIAOPTF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4060	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4061
4062	/**
4063	* Function table for media instruction taking one full sized media source
4064	* registers and one full sized destination register, but no additional state
4065	* (AVX).
4066	*/
4067	typedef struct IEMOPMEDIAOPTF2
4068	{
4069	PFNIEMAIMPLMEDIAOPTF2U128 pfnU128;
4070	PFNIEMAIMPLMEDIAOPTF2U256 pfnU256;
4071	} IEMOPMEDIAOPTF2;
4072	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
4073	typedef IEMOPMEDIAOPTF2 const *PCIEMOPMEDIAOPTF2;
4074
4075	/** @def IEMOPMEDIAOPTF2_INIT_VARS_EX
4076	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4077	* given functions as initializers. For use in AVX functions where a pair of
4078	* functions are only used once and the function table need not be public. */
4079	#ifndef TST_IEM_CHECK_MC
4080	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4081	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4082	static IEMOPMEDIAOPTF2 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4083	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4084	# else
4085	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4086	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4087	# endif
4088	#else
4089	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4090	#endif
4091	/** @def IEMOPMEDIAOPTF2_INIT_VARS
4092	* Generate AVX function tables for the @a a_InstrNm instruction.
4093	* @sa IEMOPMEDIAOPTF2_INIT_VARS_EX */
4094	#define IEMOPMEDIAOPTF2_INIT_VARS(a_InstrNm) \
4095	IEMOPMEDIAOPTF2_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4096	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4097
4098	/**
4099	* Function table for media instruction taking one full sized media source
4100	* register and one full sized destination register and an 8-bit immediate, but no additional state
4101	* (AVX).
4102	*/
4103	typedef struct IEMOPMEDIAOPTF2IMM8
4104	{
4105	PFNIEMAIMPLMEDIAOPTF2U128IMM8 pfnU128;
4106	PFNIEMAIMPLMEDIAOPTF2U256IMM8 pfnU256;
4107	} IEMOPMEDIAOPTF2IMM8;
4108	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
4109	typedef IEMOPMEDIAOPTF2IMM8 const *PCIEMOPMEDIAOPTF2IMM8;
4110
4111	/** @def IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX
4112	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4113	* given functions as initializers. For use in AVX functions where a pair of
4114	* functions are only used once and the function table need not be public. */
4115	#ifndef TST_IEM_CHECK_MC
4116	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4117	# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4118	static IEMOPMEDIAOPTF2IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4119	static IEMOPMEDIAOPTF2IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4120	# else
4121	# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4122	static IEMOPMEDIAOPTF2IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4123	# endif
4124	#else
4125	# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4126	#endif
4127	/** @def IEMOPMEDIAOPTF2IMM8_INIT_VARS
4128	* Generate AVX function tables for the @a a_InstrNm instruction.
4129	* @sa IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX */
4130	#define IEMOPMEDIAOPTF2IMM8_INIT_VARS(a_InstrNm) \
4131	IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u256),\
4132	RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u256_fallback))
4133
4134	/**
4135	* Function table for media instruction taking two full sized media source
4136	* registers and one full sized destination register and an 8-bit immediate, but no additional state
4137	* (AVX).
4138	*/
4139	typedef struct IEMOPMEDIAOPTF3IMM8
4140	{
4141	PFNIEMAIMPLMEDIAOPTF3U128IMM8 pfnU128;
4142	PFNIEMAIMPLMEDIAOPTF3U256IMM8 pfnU256;
4143	} IEMOPMEDIAOPTF3IMM8;
4144	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
4145	typedef IEMOPMEDIAOPTF3IMM8 const *PCIEMOPMEDIAOPTF3IMM8;
4146
4147	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX
4148	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4149	* given functions as initializers. For use in AVX functions where a pair of
4150	* functions are only used once and the function table need not be public. */
4151	#ifndef TST_IEM_CHECK_MC
4152	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4153	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4154	static IEMOPMEDIAOPTF3IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4155	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4156	# else
4157	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4158	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4159	# endif
4160	#else
4161	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4162	#endif
4163	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS
4164	* Generate AVX function tables for the @a a_InstrNm instruction.
4165	* @sa IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX */
4166	#define IEMOPMEDIAOPTF3IMM8_INIT_VARS(a_InstrNm) \
4167	IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4168	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4169	/** @} */
4170
4171
4172	/**
4173	* Function table for blend type instruction taking three full sized media source
4174	* registers and one full sized destination register, but no additional state
4175	* (AVX).
4176	*/
4177	typedef struct IEMOPBLENDOP
4178	{
4179	PFNIEMAIMPLAVXBLENDU128 pfnU128;
4180	PFNIEMAIMPLAVXBLENDU256 pfnU256;
4181	} IEMOPBLENDOP;
4182	/** Pointer to a media operation function table for 4 full sized ops (AVX). */
4183	typedef IEMOPBLENDOP const *PCIEMOPBLENDOP;
4184
4185	/** @def IEMOPBLENDOP_INIT_VARS_EX
4186	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4187	* given functions as initializers. For use in AVX functions where a pair of
4188	* functions are only used once and the function table need not be public. */
4189	#ifndef TST_IEM_CHECK_MC
4190	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4191	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4192	static IEMOPBLENDOP const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4193	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4194	# else
4195	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4196	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4197	# endif
4198	#else
4199	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4200	#endif
4201	/** @def IEMOPBLENDOP_INIT_VARS
4202	* Generate AVX function tables for the @a a_InstrNm instruction.
4203	* @sa IEMOPBLENDOP_INIT_VARS_EX */
4204	#define IEMOPBLENDOP_INIT_VARS(a_InstrNm) \
4205	IEMOPBLENDOP_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4206	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4207
4208
4209	/** @name SSE/AVX single/double precision floating point operations.
4210	* @{ */
4211	/**
4212	* A SSE result.
4213	*/
4214	typedef struct IEMSSERESULT
4215	{
4216	/** The output value. */
4217	X86XMMREG uResult;
4218	/** The output status. */
4219	uint32_t MXCSR;
4220	} IEMSSERESULT;
4221	AssertCompileMemberOffset(IEMSSERESULT, MXCSR, 128 / 8);
4222	/** Pointer to a SSE result. */
4223	typedef IEMSSERESULT *PIEMSSERESULT;
4224	/** Pointer to a const SSE result. */
4225	typedef IEMSSERESULT const *PCIEMSSERESULT;
4226
4227
4228	/**
4229	* A AVX128 result.
4230	*/
4231	typedef struct IEMAVX128RESULT
4232	{
4233	/** The output value. */
4234	X86XMMREG uResult;
4235	/** The output status. */
4236	uint32_t MXCSR;
4237	} IEMAVX128RESULT;
4238	AssertCompileMemberOffset(IEMAVX128RESULT, MXCSR, 128 / 8);
4239	/** Pointer to a AVX128 result. */
4240	typedef IEMAVX128RESULT *PIEMAVX128RESULT;
4241	/** Pointer to a const AVX128 result. */
4242	typedef IEMAVX128RESULT const *PCIEMAVX128RESULT;
4243
4244
4245	/**
4246	* A AVX256 result.
4247	*/
4248	typedef struct IEMAVX256RESULT
4249	{
4250	/** The output value. */
4251	X86YMMREG uResult;
4252	/** The output status. */
4253	uint32_t MXCSR;
4254	} IEMAVX256RESULT;
4255	AssertCompileMemberOffset(IEMAVX256RESULT, MXCSR, 256 / 8);
4256	/** Pointer to a AVX256 result. */
4257	typedef IEMAVX256RESULT *PIEMAVX256RESULT;
4258	/** Pointer to a const AVX256 result. */
4259	typedef IEMAVX256RESULT const *PCIEMAVX256RESULT;
4260
4261
4262	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
4263	typedef FNIEMAIMPLFPSSEF2U128 *PFNIEMAIMPLFPSSEF2U128;
4264	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128R32,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
4265	typedef FNIEMAIMPLFPSSEF2U128R32 *PFNIEMAIMPLFPSSEF2U128R32;
4266	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128R64,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
4267	typedef FNIEMAIMPLFPSSEF2U128R64 *PFNIEMAIMPLFPSSEF2U128R64;
4268
4269	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
4270	typedef FNIEMAIMPLFPAVXF3U128 *PFNIEMAIMPLFPAVXF3U128;
4271	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128R32,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
4272	typedef FNIEMAIMPLFPAVXF3U128R32 *PFNIEMAIMPLFPAVXF3U128R32;
4273	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128R64,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
4274	typedef FNIEMAIMPLFPAVXF3U128R64 *PFNIEMAIMPLFPAVXF3U128R64;
4275
4276	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U256,(PX86XSAVEAREA pExtState, PIEMAVX256RESULT pResult, PCX86YMMREG puSrc1, PCX86YMMREG puSrc2));
4277	typedef FNIEMAIMPLFPAVXF3U256 *PFNIEMAIMPLFPAVXF3U256;
4278
4279	FNIEMAIMPLFPSSEF2U128 iemAImpl_addps_u128;
4280	FNIEMAIMPLFPSSEF2U128 iemAImpl_addpd_u128;
4281	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulps_u128;
4282	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulpd_u128;
4283	FNIEMAIMPLFPSSEF2U128 iemAImpl_subps_u128;
4284	FNIEMAIMPLFPSSEF2U128 iemAImpl_subpd_u128;
4285	FNIEMAIMPLFPSSEF2U128 iemAImpl_minps_u128;
4286	FNIEMAIMPLFPSSEF2U128 iemAImpl_minpd_u128;
4287	FNIEMAIMPLFPSSEF2U128 iemAImpl_divps_u128;
4288	FNIEMAIMPLFPSSEF2U128 iemAImpl_divpd_u128;
4289	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxps_u128;
4290	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxpd_u128;
4291	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddps_u128;
4292	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddpd_u128;
4293	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubps_u128;
4294	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubpd_u128;
4295	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtps_u128;
4296	FNIEMAIMPLFPSSEF2U128 iemAImpl_rsqrtps_u128;
4297	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtpd_u128;
4298	FNIEMAIMPLFPSSEF2U128 iemAImpl_rcpps_u128;
4299	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubps_u128;
4300	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubpd_u128;
4301	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2ps_u128;
4302	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2pd_u128;
4303
4304	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2ps_u128;
4305	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2dq_u128;
4306	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttps2dq_u128;
4307	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttpd2dq_u128;
4308	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2pd_u128;
4309	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2dq_u128;
4310
4311	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_addss_u128_r32;
4312	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_addsd_u128_r64;
4313	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_mulss_u128_r32;
4314	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_mulsd_u128_r64;
4315	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_subss_u128_r32;
4316	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_subsd_u128_r64;
4317	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_minss_u128_r32;
4318	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_minsd_u128_r64;
4319	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_divss_u128_r32;
4320	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_divsd_u128_r64;
4321	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_maxss_u128_r32;
4322	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_maxsd_u128_r64;
4323	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_cvtss2sd_u128_r32;
4324	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_cvtsd2ss_u128_r64;
4325	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_sqrtss_u128_r32;
4326	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_sqrtsd_u128_r64;
4327	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_rsqrtss_u128_r32;
4328	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_rcpss_u128_r32;
4329
4330	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddps_u128, iemAImpl_vaddps_u128_fallback;
4331	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddpd_u128, iemAImpl_vaddpd_u128_fallback;
4332	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulps_u128, iemAImpl_vmulps_u128_fallback;
4333	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulpd_u128, iemAImpl_vmulpd_u128_fallback;
4334	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubps_u128, iemAImpl_vsubps_u128_fallback;
4335	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubpd_u128, iemAImpl_vsubpd_u128_fallback;
4336	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminps_u128, iemAImpl_vminps_u128_fallback;
4337	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminpd_u128, iemAImpl_vminpd_u128_fallback;
4338	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivps_u128, iemAImpl_vdivps_u128_fallback;
4339	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivpd_u128, iemAImpl_vdivpd_u128_fallback;
4340	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxps_u128, iemAImpl_vmaxps_u128_fallback;
4341	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxpd_u128, iemAImpl_vmaxpd_u128_fallback;
4342	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddps_u128, iemAImpl_vhaddps_u128_fallback;
4343	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddpd_u128, iemAImpl_vhaddpd_u128_fallback;
4344	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubps_u128, iemAImpl_vhsubps_u128_fallback;
4345	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubpd_u128, iemAImpl_vhsubpd_u128_fallback;
4346	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtps_u128, iemAImpl_vsqrtps_u128_fallback;
4347	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtpd_u128, iemAImpl_vsqrtpd_u128_fallback;
4348	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubps_u128, iemAImpl_vaddsubps_u128_fallback;
4349	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubpd_u128, iemAImpl_vaddsubpd_u128_fallback;
4350	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtpd2ps_u128, iemAImpl_vcvtpd2ps_u128_fallback;
4351	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtps2pd_u128, iemAImpl_vcvtps2pd_u128_fallback;
4352
4353	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vaddss_u128_r32, iemAImpl_vaddss_u128_r32_fallback;
4354	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vaddsd_u128_r64, iemAImpl_vaddsd_u128_r64_fallback;
4355	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmulss_u128_r32, iemAImpl_vmulss_u128_r32_fallback;
4356	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmulsd_u128_r64, iemAImpl_vmulsd_u128_r64_fallback;
4357	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsubss_u128_r32, iemAImpl_vsubss_u128_r32_fallback;
4358	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsubsd_u128_r64, iemAImpl_vsubsd_u128_r64_fallback;
4359	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vminss_u128_r32, iemAImpl_vminss_u128_r32_fallback;
4360	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vminsd_u128_r64, iemAImpl_vminsd_u128_r64_fallback;
4361	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vdivss_u128_r32, iemAImpl_vdivss_u128_r32_fallback;
4362	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vdivsd_u128_r64, iemAImpl_vdivsd_u128_r64_fallback;
4363	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmaxss_u128_r32, iemAImpl_vmaxss_u128_r32_fallback;
4364	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmaxsd_u128_r64, iemAImpl_vmaxsd_u128_r64_fallback;
4365	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsqrtss_u128_r32, iemAImpl_vsqrtss_u128_r32_fallback;
4366	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsqrtsd_u128_r64, iemAImpl_vsqrtsd_u128_r64_fallback;
4367
4368	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddps_u256, iemAImpl_vaddps_u256_fallback;
4369	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddpd_u256, iemAImpl_vaddpd_u256_fallback;
4370	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulps_u256, iemAImpl_vmulps_u256_fallback;
4371	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulpd_u256, iemAImpl_vmulpd_u256_fallback;
4372	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubps_u256, iemAImpl_vsubps_u256_fallback;
4373	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubpd_u256, iemAImpl_vsubpd_u256_fallback;
4374	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminps_u256, iemAImpl_vminps_u256_fallback;
4375	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminpd_u256, iemAImpl_vminpd_u256_fallback;
4376	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivps_u256, iemAImpl_vdivps_u256_fallback;
4377	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivpd_u256, iemAImpl_vdivpd_u256_fallback;
4378	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxps_u256, iemAImpl_vmaxps_u256_fallback;
4379	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxpd_u256, iemAImpl_vmaxpd_u256_fallback;
4380	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddps_u256, iemAImpl_vhaddps_u256_fallback;
4381	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddpd_u256, iemAImpl_vhaddpd_u256_fallback;
4382	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubps_u256, iemAImpl_vhsubps_u256_fallback;
4383	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubpd_u256, iemAImpl_vhsubpd_u256_fallback;
4384	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubps_u256, iemAImpl_vhaddsubps_u256_fallback;
4385	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubpd_u256, iemAImpl_vhaddsubpd_u256_fallback;
4386	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtpd2ps_u256, iemAImpl_vcvtpd2ps_u256_fallback;
4387	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtps2pd_u256, iemAImpl_vcvtps2pd_u256_fallback;
4388	/** @} */
4389
4390	/** @name C instruction implementations for anything slightly complicated.
4391	* @{ */
4392
4393	/**
4394	* For typedef'ing or declaring a C instruction implementation function taking
4395	* no extra arguments.
4396	*
4397	* @param a_Name The name of the type.
4398	*/
4399	# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
4400	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
4401	/**
4402	* For defining a C instruction implementation function taking no extra
4403	* arguments.
4404	*
4405	* @param a_Name The name of the function
4406	*/
4407	# define IEM_CIMPL_DEF_0(a_Name) \
4408	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
4409	/**
4410	* Prototype version of IEM_CIMPL_DEF_0.
4411	*/
4412	# define IEM_CIMPL_PROTO_0(a_Name) \
4413	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
4414	/**
4415	* For calling a C instruction implementation function taking no extra
4416	* arguments.
4417	*
4418	* This special call macro adds default arguments to the call and allow us to
4419	* change these later.
4420	*
4421	* @param a_fn The name of the function.
4422	*/
4423	# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
4424
4425	/** Type for a C instruction implementation function taking no extra
4426	* arguments. */
4427	typedef IEM_CIMPL_DECL_TYPE_0(FNIEMCIMPL0);
4428	/** Function pointer type for a C instruction implementation function taking
4429	* no extra arguments. */
4430	typedef FNIEMCIMPL0 *PFNIEMCIMPL0;
4431
4432	/**
4433	* For typedef'ing or declaring a C instruction implementation function taking
4434	* one extra argument.
4435	*
4436	* @param a_Name The name of the type.
4437	* @param a_Type0 The argument type.
4438	* @param a_Arg0 The argument name.
4439	*/
4440	# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
4441	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
4442	/**
4443	* For defining a C instruction implementation function taking one extra
4444	* argument.
4445	*
4446	* @param a_Name The name of the function
4447	* @param a_Type0 The argument type.
4448	* @param a_Arg0 The argument name.
4449	*/
4450	# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
4451	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
4452	/**
4453	* Prototype version of IEM_CIMPL_DEF_1.
4454	*/
4455	# define IEM_CIMPL_PROTO_1(a_Name, a_Type0, a_Arg0) \
4456	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
4457	/**
4458	* For calling a C instruction implementation function taking one extra
4459	* argument.
4460	*
4461	* This special call macro adds default arguments to the call and allow us to
4462	* change these later.
4463	*
4464	* @param a_fn The name of the function.
4465	* @param a0 The name of the 1st argument.
4466	*/
4467	# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
4468
4469	/**
4470	* For typedef'ing or declaring a C instruction implementation function taking
4471	* two extra arguments.
4472	*
4473	* @param a_Name The name of the type.
4474	* @param a_Type0 The type of the 1st argument
4475	* @param a_Arg0 The name of the 1st argument.
4476	* @param a_Type1 The type of the 2nd argument.
4477	* @param a_Arg1 The name of the 2nd argument.
4478	*/
4479	# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
4480	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
4481	/**
4482	* For defining a C instruction implementation function taking two extra
4483	* arguments.
4484	*
4485	* @param a_Name The name of the function.
4486	* @param a_Type0 The type of the 1st argument
4487	* @param a_Arg0 The name of the 1st argument.
4488	* @param a_Type1 The type of the 2nd argument.
4489	* @param a_Arg1 The name of the 2nd argument.
4490	*/
4491	# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
4492	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
4493	/**
4494	* Prototype version of IEM_CIMPL_DEF_2.
4495	*/
4496	# define IEM_CIMPL_PROTO_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
4497	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
4498	/**
4499	* For calling a C instruction implementation function taking two extra
4500	* arguments.
4501	*
4502	* This special call macro adds default arguments to the call and allow us to
4503	* change these later.
4504	*
4505	* @param a_fn The name of the function.
4506	* @param a0 The name of the 1st argument.
4507	* @param a1 The name of the 2nd argument.
4508	*/
4509	# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
4510
4511	/**
4512	* For typedef'ing or declaring a C instruction implementation function taking
4513	* three extra arguments.
4514	*
4515	* @param a_Name The name of the type.
4516	* @param a_Type0 The type of the 1st argument
4517	* @param a_Arg0 The name of the 1st argument.
4518	* @param a_Type1 The type of the 2nd argument.
4519	* @param a_Arg1 The name of the 2nd argument.
4520	* @param a_Type2 The type of the 3rd argument.
4521	* @param a_Arg2 The name of the 3rd argument.
4522	*/
4523	# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
4524	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
4525	/**
4526	* For defining a C instruction implementation function taking three extra
4527	* arguments.
4528	*
4529	* @param a_Name The name of the function.
4530	* @param a_Type0 The type of the 1st argument
4531	* @param a_Arg0 The name of the 1st argument.
4532	* @param a_Type1 The type of the 2nd argument.
4533	* @param a_Arg1 The name of the 2nd argument.
4534	* @param a_Type2 The type of the 3rd argument.
4535	* @param a_Arg2 The name of the 3rd argument.
4536	*/
4537	# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
4538	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
4539	/**
4540	* Prototype version of IEM_CIMPL_DEF_3.
4541	*/
4542	# define IEM_CIMPL_PROTO_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
4543	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
4544	/**
4545	* For calling a C instruction implementation function taking three extra
4546	* arguments.
4547	*
4548	* This special call macro adds default arguments to the call and allow us to
4549	* change these later.
4550	*
4551	* @param a_fn The name of the function.
4552	* @param a0 The name of the 1st argument.
4553	* @param a1 The name of the 2nd argument.
4554	* @param a2 The name of the 3rd argument.
4555	*/
4556	# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
4557
4558
4559	/**
4560	* For typedef'ing or declaring a C instruction implementation function taking
4561	* four extra arguments.
4562	*
4563	* @param a_Name The name of the type.
4564	* @param a_Type0 The type of the 1st argument
4565	* @param a_Arg0 The name of the 1st argument.
4566	* @param a_Type1 The type of the 2nd argument.
4567	* @param a_Arg1 The name of the 2nd argument.
4568	* @param a_Type2 The type of the 3rd argument.
4569	* @param a_Arg2 The name of the 3rd argument.
4570	* @param a_Type3 The type of the 4th argument.
4571	* @param a_Arg3 The name of the 4th argument.
4572	*/
4573	# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
4574	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
4575	/**
4576	* For defining a C instruction implementation function taking four extra
4577	* arguments.
4578	*
4579	* @param a_Name The name of the function.
4580	* @param a_Type0 The type of the 1st argument
4581	* @param a_Arg0 The name of the 1st argument.
4582	* @param a_Type1 The type of the 2nd argument.
4583	* @param a_Arg1 The name of the 2nd argument.
4584	* @param a_Type2 The type of the 3rd argument.
4585	* @param a_Arg2 The name of the 3rd argument.
4586	* @param a_Type3 The type of the 4th argument.
4587	* @param a_Arg3 The name of the 4th argument.
4588	*/
4589	# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
4590	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4591	a_Type2 a_Arg2, a_Type3 a_Arg3))
4592	/**
4593	* Prototype version of IEM_CIMPL_DEF_4.
4594	*/
4595	# define IEM_CIMPL_PROTO_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
4596	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4597	a_Type2 a_Arg2, a_Type3 a_Arg3))
4598	/**
4599	* For calling a C instruction implementation function taking four extra
4600	* arguments.
4601	*
4602	* This special call macro adds default arguments to the call and allow us to
4603	* change these later.
4604	*
4605	* @param a_fn The name of the function.
4606	* @param a0 The name of the 1st argument.
4607	* @param a1 The name of the 2nd argument.
4608	* @param a2 The name of the 3rd argument.
4609	* @param a3 The name of the 4th argument.
4610	*/
4611	# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
4612
4613
4614	/**
4615	* For typedef'ing or declaring a C instruction implementation function taking
4616	* five extra arguments.
4617	*
4618	* @param a_Name The name of the type.
4619	* @param a_Type0 The type of the 1st argument
4620	* @param a_Arg0 The name of the 1st argument.
4621	* @param a_Type1 The type of the 2nd argument.
4622	* @param a_Arg1 The name of the 2nd argument.
4623	* @param a_Type2 The type of the 3rd argument.
4624	* @param a_Arg2 The name of the 3rd argument.
4625	* @param a_Type3 The type of the 4th argument.
4626	* @param a_Arg3 The name of the 4th argument.
4627	* @param a_Type4 The type of the 5th argument.
4628	* @param a_Arg4 The name of the 5th argument.
4629	*/
4630	# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
4631	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, \
4632	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
4633	a_Type3 a_Arg3, a_Type4 a_Arg4))
4634	/**
4635	* For defining a C instruction implementation function taking five extra
4636	* arguments.
4637	*
4638	* @param a_Name The name of the function.
4639	* @param a_Type0 The type of the 1st argument
4640	* @param a_Arg0 The name of the 1st argument.
4641	* @param a_Type1 The type of the 2nd argument.
4642	* @param a_Arg1 The name of the 2nd argument.
4643	* @param a_Type2 The type of the 3rd argument.
4644	* @param a_Arg2 The name of the 3rd argument.
4645	* @param a_Type3 The type of the 4th argument.
4646	* @param a_Arg3 The name of the 4th argument.
4647	* @param a_Type4 The type of the 5th argument.
4648	* @param a_Arg4 The name of the 5th argument.
4649	*/
4650	# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
4651	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4652	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
4653	/**
4654	* Prototype version of IEM_CIMPL_DEF_5.
4655	*/
4656	# define IEM_CIMPL_PROTO_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
4657	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4658	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
4659	/**
4660	* For calling a C instruction implementation function taking five extra
4661	* arguments.
4662	*
4663	* This special call macro adds default arguments to the call and allow us to
4664	* change these later.
4665	*
4666	* @param a_fn The name of the function.
4667	* @param a0 The name of the 1st argument.
4668	* @param a1 The name of the 2nd argument.
4669	* @param a2 The name of the 3rd argument.
4670	* @param a3 The name of the 4th argument.
4671	* @param a4 The name of the 5th argument.
4672	*/
4673	# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
4674
4675	/** @} */
4676
4677
4678	/** @name Opcode Decoder Function Types.
4679	* @{ */
4680
4681	/** @typedef PFNIEMOP
4682	* Pointer to an opcode decoder function.
4683	*/
4684
4685	/** @def FNIEMOP_DEF
4686	* Define an opcode decoder function.
4687	*
4688	* We're using macors for this so that adding and removing parameters as well as
4689	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL
4690	*
4691	* @param a_Name The function name.
4692	*/
4693
4694	/** @typedef PFNIEMOPRM
4695	* Pointer to an opcode decoder function with RM byte.
4696	*/
4697
4698	/** @def FNIEMOPRM_DEF
4699	* Define an opcode decoder function with RM byte.
4700	*
4701	* We're using macors for this so that adding and removing parameters as well as
4702	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL_1
4703	*
4704	* @param a_Name The function name.
4705	*/
4706
4707	#if defined(__GNUC__) && defined(RT_ARCH_X86)
4708	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOP)(PVMCPUCC pVCpu);
4709	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4710	# define FNIEMOP_DEF(a_Name) \
4711	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu)
4712	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4713	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
4714	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4715	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
4716
4717	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
4718	typedef VBOXSTRICTRC (__fastcall * PFNIEMOP)(PVMCPUCC pVCpu);
4719	typedef VBOXSTRICTRC (__fastcall * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4720	# define FNIEMOP_DEF(a_Name) \
4721	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
4722	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4723	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
4724	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4725	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
4726
4727	#elif defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
4728	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
4729	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4730	# define FNIEMOP_DEF(a_Name) \
4731	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu)
4732	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4733	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
4734	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4735	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
4736
4737	#else
4738	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
4739	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4740	# define FNIEMOP_DEF(a_Name) \
4741	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
4742	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4743	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
4744	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4745	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
4746
4747	#endif
4748	#define FNIEMOPRM_DEF(a_Name) FNIEMOP_DEF_1(a_Name, uint8_t, bRm)
4749
4750	/**
4751	* Call an opcode decoder function.
4752	*
4753	* We're using macors for this so that adding and removing parameters can be
4754	* done as we please. See FNIEMOP_DEF.
4755	*/
4756	#define FNIEMOP_CALL(a_pfn) (a_pfn)(pVCpu)
4757
4758	/**
4759	* Call a common opcode decoder function taking one extra argument.
4760	*
4761	* We're using macors for this so that adding and removing parameters can be
4762	* done as we please. See FNIEMOP_DEF_1.
4763	*/
4764	#define FNIEMOP_CALL_1(a_pfn, a0) (a_pfn)(pVCpu, a0)
4765
4766	/**
4767	* Call a common opcode decoder function taking one extra argument.
4768	*
4769	* We're using macors for this so that adding and removing parameters can be
4770	* done as we please. See FNIEMOP_DEF_1.
4771	*/
4772	#define FNIEMOP_CALL_2(a_pfn, a0, a1) (a_pfn)(pVCpu, a0, a1)
4773	/** @} */
4774
4775
4776	/** @name Misc Helpers
4777	* @{ */
4778
4779	/** Used to shut up GCC warnings about variables that 'may be used uninitialized'
4780	* due to GCC lacking knowledge about the value range of a switch. */
4781	#if RT_CPLUSPLUS_PREREQ(202000)
4782	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: [[unlikely]] AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
4783	#else
4784	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
4785	#endif
4786
4787	/** Variant of IEM_NOT_REACHED_DEFAULT_CASE_RET that returns a custom value. */
4788	#if RT_CPLUSPLUS_PREREQ(202000)
4789	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: [[unlikely]] AssertFailedReturn(a_RetValue)
4790	#else
4791	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: AssertFailedReturn(a_RetValue)
4792	#endif
4793
4794	/**
4795	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
4796	* occation.
4797	*/
4798	#ifdef LOG_ENABLED
4799	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
4800	do { \
4801	/Log/ LogAlways(("%s: returning IEM_RETURN_ASPECT_NOT_IMPLEMENTED (line %d)\n", __FUNCTION__, __LINE__)); \
4802	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
4803	} while (0)
4804	#else
4805	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
4806	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
4807	#endif
4808
4809	/**
4810	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
4811	* occation using the supplied logger statement.
4812	*
4813	* @param a_LoggerArgs What to log on failure.
4814	*/
4815	#ifdef LOG_ENABLED
4816	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
4817	do { \
4818	LogAlways((LOG_FN_FMT ": ", __PRETTY_FUNCTION__)); LogAlways(a_LoggerArgs); \
4819	/LogFunc(a_LoggerArgs);/ \
4820	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
4821	} while (0)
4822	#else
4823	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
4824	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
4825	#endif
4826
4827	/**
4828	* Gets the CPU mode (from fExec) as a IEMMODE value.
4829	*
4830	* @returns IEMMODE
4831	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4832	*/
4833	#define IEM_GET_CPU_MODE(a_pVCpu) ((a_pVCpu)->iem.s.fExec & IEM_F_MODE_CPUMODE_MASK)
4834
4835	/**
4836	* Check if we're currently executing in real or virtual 8086 mode.
4837	*
4838	* @returns @c true if it is, @c false if not.
4839	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4840	*/
4841	#define IEM_IS_REAL_OR_V86_MODE(a_pVCpu) (( ((a_pVCpu)->iem.s.fExec ^ IEM_F_MODE_X86_PROT_MASK) \
4842	& (IEM_F_MODE_X86_V86_MASK \| IEM_F_MODE_X86_PROT_MASK)) != 0)
4843
4844	/**
4845	* Check if we're currently executing in virtual 8086 mode.
4846	*
4847	* @returns @c true if it is, @c false if not.
4848	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4849	*/
4850	#define IEM_IS_V86_MODE(a_pVCpu) (((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_V86_MASK) != 0)
4851
4852	/**
4853	* Check if we're currently executing in long mode.
4854	*
4855	* @returns @c true if it is, @c false if not.
4856	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4857	*/
4858	#define IEM_IS_LONG_MODE(a_pVCpu) (CPUMIsGuestInLongModeEx(IEM_GET_CTX(a_pVCpu)))
4859
4860	/**
4861	* Check if we're currently executing in a 16-bit code segment.
4862	*
4863	* @returns @c true if it is, @c false if not.
4864	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4865	*/
4866	#define IEM_IS_16BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_16BIT)
4867
4868	/**
4869	* Check if we're currently executing in a 32-bit code segment.
4870	*
4871	* @returns @c true if it is, @c false if not.
4872	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4873	*/
4874	#define IEM_IS_32BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_32BIT)
4875
4876	/**
4877	* Check if we're currently executing in a 64-bit code segment.
4878	*
4879	* @returns @c true if it is, @c false if not.
4880	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4881	*/
4882	#define IEM_IS_64BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_64BIT)
4883
4884	/**
4885	* Check if we're currently executing in real mode.
4886	*
4887	* @returns @c true if it is, @c false if not.
4888	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4889	*/
4890	#define IEM_IS_REAL_MODE(a_pVCpu) (!((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_PROT_MASK))
4891
4892	/**
4893	* Gets the current protection level (CPL).
4894	*
4895	* @returns 0..3
4896	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4897	*/
4898	#define IEM_GET_CPL(a_pVCpu) (((a_pVCpu)->iem.s.fExec >> IEM_F_X86_CPL_SHIFT) & IEM_F_X86_CPL_SMASK)
4899
4900	/**
4901	* Sets the current protection level (CPL).
4902	*
4903	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4904	*/
4905	#define IEM_SET_CPL(a_pVCpu, a_uCpl) \
4906	do { (a_pVCpu)->iem.s.fExec = ((a_pVCpu)->iem.s.fExec & ~IEM_F_X86_CPL_MASK) \| ((a_uCpl) << IEM_F_X86_CPL_SHIFT); } while (0)
4907
4908	/**
4909	* Returns a (const) pointer to the CPUMFEATURES for the guest CPU.
4910	* @returns PCCPUMFEATURES
4911	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4912	*/
4913	#define IEM_GET_GUEST_CPU_FEATURES(a_pVCpu) (&((a_pVCpu)->CTX_SUFF(pVM)->cpum.ro.GuestFeatures))
4914
4915	/**
4916	* Returns a (const) pointer to the CPUMFEATURES for the host CPU.
4917	* @returns PCCPUMFEATURES
4918	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4919	*/
4920	#define IEM_GET_HOST_CPU_FEATURES(a_pVCpu) (&g_CpumHostFeatures.s)
4921
4922	/**
4923	* Evaluates to true if we're presenting an Intel CPU to the guest.
4924	*/
4925	#define IEM_IS_GUEST_CPU_INTEL(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL )
4926
4927	/**
4928	* Evaluates to true if we're presenting an AMD CPU to the guest.
4929	*/
4930	#define IEM_IS_GUEST_CPU_AMD(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_AMD \|\| (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_HYGON )
4931
4932	/**
4933	* Check if the address is canonical.
4934	*/
4935	#define IEM_IS_CANONICAL(a_u64Addr) X86_IS_CANONICAL(a_u64Addr)
4936
4937	/** Checks if the ModR/M byte is in register mode or not. */
4938	#define IEM_IS_MODRM_REG_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT) )
4939	/** Checks if the ModR/M byte is in memory mode or not. */
4940	#define IEM_IS_MODRM_MEM_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT) )
4941
4942	/**
4943	* Gets the register (reg) part of a ModR/M encoding, with REX.R added in.
4944	*
4945	* For use during decoding.
4946	*/
4947	#define IEM_GET_MODRM_REG(a_pVCpu, a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| (a_pVCpu)->iem.s.uRexReg )
4948	/**
4949	* Gets the r/m part of a ModR/M encoding as a register index, with REX.B added in.
4950	*
4951	* For use during decoding.
4952	*/
4953	#define IEM_GET_MODRM_RM(a_pVCpu, a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) \| (a_pVCpu)->iem.s.uRexB )
4954
4955	/**
4956	* Gets the register (reg) part of a ModR/M encoding, without REX.R.
4957	*
4958	* For use during decoding.
4959	*/
4960	#define IEM_GET_MODRM_REG_8(a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) )
4961	/**
4962	* Gets the r/m part of a ModR/M encoding as a register index, without REX.B.
4963	*
4964	* For use during decoding.
4965	*/
4966	#define IEM_GET_MODRM_RM_8(a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) )
4967
4968	/**
4969	* Gets the register (reg) part of a ModR/M encoding as an extended 8-bit
4970	* register index, with REX.R added in.
4971	*
4972	* For use during decoding.
4973	*
4974	* @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
4975	*/
4976	#define IEM_GET_MODRM_REG_EX8(a_pVCpu, a_bRm) \
4977	( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
4978	\|\| !((a_bRm) & (4 << X86_MODRM_REG_SHIFT)) /* IEM_GET_MODRM_REG(pVCpu, a_bRm) < 4 */ \
4979	? IEM_GET_MODRM_REG(pVCpu, a_bRm) : (((a_bRm) >> X86_MODRM_REG_SHIFT) & 3) \| 16)
4980	/**
4981	* Gets the r/m part of a ModR/M encoding as an extended 8-bit register index,
4982	* with REX.B added in.
4983	*
4984	* For use during decoding.
4985	*
4986	* @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
4987	*/
4988	#define IEM_GET_MODRM_RM_EX8(a_pVCpu, a_bRm) \
4989	( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
4990	\|\| !((a_bRm) & 4) /* IEM_GET_MODRM_RM(pVCpu, a_bRm) < 4 */ \
4991	? IEM_GET_MODRM_RM(pVCpu, a_bRm) : ((a_bRm) & 3) \| 16)
4992
4993	/**
4994	* Combines the prefix REX and ModR/M byte for passing to
4995	* iemOpHlpCalcRmEffAddrThreadedAddr64().
4996	*
4997	* @returns The ModRM byte but with bit 3 set to REX.B and bit 4 to REX.X.
4998	* The two bits are part of the REG sub-field, which isn't needed in
4999	* iemOpHlpCalcRmEffAddrThreadedAddr64().
5000	*
5001	* For use during decoding/recompiling.
5002	*/
5003	#define IEM_GET_MODRM_EX(a_pVCpu, a_bRm) \
5004	( ((a_bRm) & ~X86_MODRM_REG_MASK) \
5005	\| (uint8_t)( (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X)) >> (25 - 3) ) )
5006	AssertCompile(IEM_OP_PRF_REX_B == RT_BIT_32(25));
5007	AssertCompile(IEM_OP_PRF_REX_X == RT_BIT_32(26));
5008
5009	/**
5010	* Gets the effective VEX.VVVV value.
5011	*
5012	* The 4th bit is ignored if not 64-bit code.
5013	* @returns effective V-register value.
5014	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5015	*/
5016	#define IEM_GET_EFFECTIVE_VVVV(a_pVCpu) \
5017	(IEM_IS_64BIT_CODE(a_pVCpu) ? (a_pVCpu)->iem.s.uVex3rdReg : (a_pVCpu)->iem.s.uVex3rdReg & 7)
5018
5019
5020	/**
5021	* Gets the register (reg) part of a the special 4th register byte used by
5022	* vblendvps and vblendvpd.
5023	*
5024	* For use during decoding.
5025	*/
5026	#define IEM_GET_IMM8_REG(a_pVCpu, a_bRegImm8) \
5027	(IEM_IS_64BIT_CODE(a_pVCpu) ? (a_bRegImm8) >> 4 : ((a_bRegImm8) >> 4) & 7)
5028
5029
5030	/**
5031	* Checks if we're executing inside an AMD-V or VT-x guest.
5032	*/
5033	#if defined(VBOX_WITH_NESTED_HWVIRT_VMX) \|\| defined(VBOX_WITH_NESTED_HWVIRT_SVM)
5034	# define IEM_IS_IN_GUEST(a_pVCpu) RT_BOOL((a_pVCpu)->iem.s.fExec & IEM_F_X86_CTX_IN_GUEST)
5035	#else
5036	# define IEM_IS_IN_GUEST(a_pVCpu) false
5037	#endif
5038
5039
5040	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5041
5042	/**
5043	* Check if the guest has entered VMX root operation.
5044	*/
5045	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxRootMode(IEM_GET_CTX(a_pVCpu)))
5046
5047	/**
5048	* Check if the guest has entered VMX non-root operation.
5049	*/
5050	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) ( ((a_pVCpu)->iem.s.fExec & (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST)) \
5051	== (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST) )
5052
5053	/**
5054	* Check if the nested-guest has the given Pin-based VM-execution control set.
5055	*/
5056	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_PinCtl) (CPUMIsGuestVmxPinCtlsSet(IEM_GET_CTX(a_pVCpu), (a_PinCtl)))
5057
5058	/**
5059	* Check if the nested-guest has the given Processor-based VM-execution control set.
5060	*/
5061	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_ProcCtl) (CPUMIsGuestVmxProcCtlsSet(IEM_GET_CTX(a_pVCpu), (a_ProcCtl)))
5062
5063	/**
5064	* Check if the nested-guest has the given Secondary Processor-based VM-execution
5065	* control set.
5066	*/
5067	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_ProcCtl2) (CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(a_pVCpu), (a_ProcCtl2)))
5068
5069	/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
5070	# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
5071
5072	/** Whether a shadow VMCS is present for the given VCPU. */
5073	# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
5074
5075	/** Gets the VMXON region pointer. */
5076	# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
5077
5078	/** Gets the guest-physical address of the current VMCS for the given VCPU. */
5079	# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
5080
5081	/** Whether a current VMCS is present for the given VCPU. */
5082	# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
5083
5084	/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
5085	# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
5086	do \
5087	{ \
5088	Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
5089	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
5090	} while (0)
5091
5092	/** Clears any current VMCS for the given VCPU. */
5093	# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
5094	do \
5095	{ \
5096	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
5097	} while (0)
5098
5099	/**
5100	* Invokes the VMX VM-exit handler for an instruction intercept.
5101	*/
5102	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) \
5103	do { return iemVmxVmexitInstr((a_pVCpu), (a_uExitReason), (a_cbInstr)); } while (0)
5104
5105	/**
5106	* Invokes the VMX VM-exit handler for an instruction intercept where the
5107	* instruction provides additional VM-exit information.
5108	*/
5109	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) \
5110	do { return iemVmxVmexitInstrNeedsInfo((a_pVCpu), (a_uExitReason), (a_uInstrId), (a_cbInstr)); } while (0)
5111
5112	/**
5113	* Invokes the VMX VM-exit handler for a task switch.
5114	*/
5115	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) \
5116	do { return iemVmxVmexitTaskSwitch((a_pVCpu), (a_enmTaskSwitch), (a_SelNewTss), (a_cbInstr)); } while (0)
5117
5118	/**
5119	* Invokes the VMX VM-exit handler for MWAIT.
5120	*/
5121	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) \
5122	do { return iemVmxVmexitInstrMwait((a_pVCpu), (a_fMonitorArmed), (a_cbInstr)); } while (0)
5123
5124	/**
5125	* Invokes the VMX VM-exit handler for EPT faults.
5126	*/
5127	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) \
5128	do { return iemVmxVmexitEpt(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr); } while (0)
5129
5130	/**
5131	* Invokes the VMX VM-exit handler.
5132	*/
5133	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) \
5134	do { return iemVmxVmexit((a_pVCpu), (a_uExitReason), (a_uExitQual)); } while (0)
5135
5136	#else
5137	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (false)
5138	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (false)
5139	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_cbInstr) (false)
5140	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_cbInstr) (false)
5141	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_cbInstr) (false)
5142	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5143	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5144	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5145	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5146	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5147	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) do { return VERR_VMX_IPE_1; } while (0)
5148
5149	#endif
5150
5151	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5152	/**
5153	* Checks if we're executing a guest using AMD-V.
5154	*/
5155	# define IEM_SVM_IS_IN_GUEST(a_pVCpu) ( (a_pVCpu->iem.s.fExec & (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST)) \
5156	== (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST))
5157	/**
5158	* Check if an SVM control/instruction intercept is set.
5159	*/
5160	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) \
5161	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmCtrlInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_Intercept)))
5162
5163	/**
5164	* Check if an SVM read CRx intercept is set.
5165	*/
5166	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
5167	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
5168
5169	/**
5170	* Check if an SVM write CRx intercept is set.
5171	*/
5172	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
5173	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
5174
5175	/**
5176	* Check if an SVM read DRx intercept is set.
5177	*/
5178	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
5179	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
5180
5181	/**
5182	* Check if an SVM write DRx intercept is set.
5183	*/
5184	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
5185	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
5186
5187	/**
5188	* Check if an SVM exception intercept is set.
5189	*/
5190	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) \
5191	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmXcptInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uVector)))
5192
5193	/**
5194	* Invokes the SVM \#VMEXIT handler for the nested-guest.
5195	*/
5196	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
5197	do { return iemSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2)); } while (0)
5198
5199	/**
5200	* Invokes the 'MOV CRx' SVM \#VMEXIT handler after constructing the
5201	* corresponding decode assist information.
5202	*/
5203	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) \
5204	do \
5205	{ \
5206	uint64_t uExitInfo1; \
5207	if ( IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmDecodeAssists \
5208	&& (a_enmAccessCrX) == IEMACCESSCRX_MOV_CRX) \
5209	uExitInfo1 = SVM_EXIT1_MOV_CRX_MASK \| ((a_iGReg) & 7); \
5210	else \
5211	uExitInfo1 = 0; \
5212	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, uExitInfo1, 0); \
5213	} while (0)
5214
5215	/** Check and handles SVM nested-guest instruction intercept and updates
5216	* NRIP if needed.
5217	*/
5218	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
5219	do \
5220	{ \
5221	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept)) \
5222	{ \
5223	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
5224	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2); \
5225	} \
5226	} while (0)
5227
5228	/** Checks and handles SVM nested-guest CR0 read intercept. */
5229	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
5230	do \
5231	{ \
5232	if (!IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, 0)) \
5233	{ /* probably likely */ } \
5234	else \
5235	{ \
5236	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
5237	IEM_SVM_VMEXIT_RET(a_pVCpu, SVM_EXIT_READ_CR0, a_uExitInfo1, a_uExitInfo2); \
5238	} \
5239	} while (0)
5240
5241	/**
5242	* Updates the NextRIP (NRI) field in the nested-guest VMCB.
5243	*/
5244	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) \
5245	do { \
5246	if (IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmNextRipSave) \
5247	CPUMGuestSvmUpdateNRip(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_cbInstr)); \
5248	} while (0)
5249
5250	#else
5251	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) (false)
5252	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
5253	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
5254	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
5255	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
5256	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) (false)
5257	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { return VERR_SVM_IPE_1; } while (0)
5258	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) do { return VERR_SVM_IPE_1; } while (0)
5259	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, \
5260	a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
5261	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
5262	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) do { } while (0)
5263
5264	#endif
5265
5266	/** @} */
5267
5268	uint32_t iemCalcExecDbgFlagsSlow(PVMCPUCC pVCpu);
5269	VBOXSTRICTRC iemExecInjectPendingTrap(PVMCPUCC pVCpu);
5270
5271
5272	/**
5273	* Selector descriptor table entry as fetched by iemMemFetchSelDesc.
5274	*/
5275	typedef union IEMSELDESC
5276	{
5277	/** The legacy view. */
5278	X86DESC Legacy;
5279	/** The long mode view. */
5280	X86DESC64 Long;
5281	} IEMSELDESC;
5282	/** Pointer to a selector descriptor table entry. */
5283	typedef IEMSELDESC *PIEMSELDESC;
5284
5285	/** @name Raising Exceptions.
5286	* @{ */
5287	VBOXSTRICTRC iemTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, uint32_t uNextEip, uint32_t fFlags,
5288	uint16_t uErr, uint64_t uCr2, RTSEL SelTSS, PIEMSELDESC pNewDescTSS) RT_NOEXCEPT;
5289
5290	VBOXSTRICTRC iemRaiseXcptOrInt(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags,
5291	uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
5292	#ifdef IEM_WITH_SETJMP
5293	DECL_NO_RETURN(void) iemRaiseXcptOrIntJmp(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector,
5294	uint32_t fFlags, uint16_t uErr, uint64_t uCr2) IEM_NOEXCEPT_MAY_LONGJMP;
5295	#endif
5296	VBOXSTRICTRC iemRaiseDivideError(PVMCPUCC pVCpu) RT_NOEXCEPT;
5297	#ifdef IEM_WITH_SETJMP
5298	DECL_NO_RETURN(void) iemRaiseDivideErrorJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5299	#endif
5300	VBOXSTRICTRC iemRaiseDebugException(PVMCPUCC pVCpu) RT_NOEXCEPT;
5301	VBOXSTRICTRC iemRaiseBoundRangeExceeded(PVMCPUCC pVCpu) RT_NOEXCEPT;
5302	VBOXSTRICTRC iemRaiseUndefinedOpcode(PVMCPUCC pVCpu) RT_NOEXCEPT;
5303	#ifdef IEM_WITH_SETJMP
5304	DECL_NO_RETURN(void) iemRaiseUndefinedOpcodeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5305	#endif
5306	VBOXSTRICTRC iemRaiseDeviceNotAvailable(PVMCPUCC pVCpu) RT_NOEXCEPT;
5307	#ifdef IEM_WITH_SETJMP
5308	DECL_NO_RETURN(void) iemRaiseDeviceNotAvailableJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5309	#endif
5310	VBOXSTRICTRC iemRaiseTaskSwitchFaultWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5311	VBOXSTRICTRC iemRaiseTaskSwitchFaultCurrentTSS(PVMCPUCC pVCpu) RT_NOEXCEPT;
5312	VBOXSTRICTRC iemRaiseTaskSwitchFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
5313	VBOXSTRICTRC iemRaiseTaskSwitchFaultBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5314	/VBOXSTRICTRC iemRaiseSelectorNotPresent(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;/
5315	VBOXSTRICTRC iemRaiseSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5316	VBOXSTRICTRC iemRaiseSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5317	VBOXSTRICTRC iemRaiseStackSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5318	VBOXSTRICTRC iemRaiseStackSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5319	VBOXSTRICTRC iemRaiseGeneralProtectionFault(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5320	VBOXSTRICTRC iemRaiseGeneralProtectionFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
5321	#ifdef IEM_WITH_SETJMP
5322	DECL_NO_RETURN(void) iemRaiseGeneralProtectionFault0Jmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5323	#endif
5324	VBOXSTRICTRC iemRaiseGeneralProtectionFaultBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
5325	VBOXSTRICTRC iemRaiseNotCanonical(PVMCPUCC pVCpu) RT_NOEXCEPT;
5326	VBOXSTRICTRC iemRaiseSelectorBounds(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
5327	#ifdef IEM_WITH_SETJMP
5328	DECL_NO_RETURN(void) iemRaiseSelectorBoundsJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
5329	#endif
5330	VBOXSTRICTRC iemRaiseSelectorBoundsBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
5331	#ifdef IEM_WITH_SETJMP
5332	DECL_NO_RETURN(void) iemRaiseSelectorBoundsBySelectorJmp(PVMCPUCC pVCpu, RTSEL Sel) IEM_NOEXCEPT_MAY_LONGJMP;
5333	#endif
5334	VBOXSTRICTRC iemRaiseSelectorInvalidAccess(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
5335	#ifdef IEM_WITH_SETJMP
5336	DECL_NO_RETURN(void) iemRaiseSelectorInvalidAccessJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
5337	#endif
5338	VBOXSTRICTRC iemRaisePageFault(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) RT_NOEXCEPT;
5339	#ifdef IEM_WITH_SETJMP
5340	DECL_NO_RETURN(void) iemRaisePageFaultJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) IEM_NOEXCEPT_MAY_LONGJMP;
5341	#endif
5342	VBOXSTRICTRC iemRaiseMathFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
5343	#ifdef IEM_WITH_SETJMP
5344	DECL_NO_RETURN(void) iemRaiseMathFaultJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5345	#endif
5346	VBOXSTRICTRC iemRaiseAlignmentCheckException(PVMCPUCC pVCpu) RT_NOEXCEPT;
5347	#ifdef IEM_WITH_SETJMP
5348	DECL_NO_RETURN(void) iemRaiseAlignmentCheckExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5349	#endif
5350	VBOXSTRICTRC iemRaiseSimdFpException(PVMCPUCC pVCpu) RT_NOEXCEPT;
5351	#ifdef IEM_WITH_SETJMP
5352	DECL_NO_RETURN(void) iemRaiseSimdFpExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5353	#endif
5354
5355	void iemLogSyscallRealModeInt(PVMCPUCC pVCpu, uint8_t u8Vector, uint8_t cbInstr);
5356	void iemLogSyscallProtModeInt(PVMCPUCC pVCpu, uint8_t u8Vector, uint8_t cbInstr);
5357
5358	IEM_CIMPL_DEF_0(iemCImplRaiseDivideError);
5359	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidLockPrefix);
5360	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidOpcode);
5361
5362	/**
5363	* Macro for calling iemCImplRaiseDivideError().
5364	*
5365	* This is for things that will _always_ decode to an \#DE, taking the
5366	* recompiler into consideration and everything.
5367	*
5368	* @return Strict VBox status code.
5369	*/
5370	#define IEMOP_RAISE_DIVIDE_ERROR_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseDivideError)
5371
5372	/**
5373	* Macro for calling iemCImplRaiseInvalidLockPrefix().
5374	*
5375	* This is for things that will _always_ decode to an \#UD, taking the
5376	* recompiler into consideration and everything.
5377	*
5378	* @return Strict VBox status code.
5379	*/
5380	#define IEMOP_RAISE_INVALID_LOCK_PREFIX_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidLockPrefix)
5381
5382	/**
5383	* Macro for calling iemCImplRaiseInvalidOpcode() for decode/static \#UDs.
5384	*
5385	* This is for things that will _always_ decode to an \#UD, taking the
5386	* recompiler into consideration and everything.
5387	*
5388	* @return Strict VBox status code.
5389	*/
5390	#define IEMOP_RAISE_INVALID_OPCODE_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidOpcode)
5391
5392	/**
5393	* Macro for calling iemCImplRaiseInvalidOpcode() for runtime-style \#UDs.
5394	*
5395	* Using this macro means you've got _buggy_ _code_ and are doing things that
5396	* belongs exclusively in IEMAllCImpl.cpp during decoding.
5397	*
5398	* @return Strict VBox status code.
5399	* @see IEMOP_RAISE_INVALID_OPCODE_RET
5400	*/
5401	#define IEMOP_RAISE_INVALID_OPCODE_RUNTIME_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidOpcode)
5402
5403	/** @} */
5404
5405	/** @name Register Access.
5406	* @{ */
5407	VBOXSTRICTRC iemRegRipRelativeJumpS8AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int8_t offNextInstr,
5408	IEMMODE enmEffOpSize) RT_NOEXCEPT;
5409	VBOXSTRICTRC iemRegRipRelativeJumpS16AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int16_t offNextInstr) RT_NOEXCEPT;
5410	VBOXSTRICTRC iemRegRipRelativeJumpS32AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int32_t offNextInstr,
5411	IEMMODE enmEffOpSize) RT_NOEXCEPT;
5412	/** @} */
5413
5414	/** @name FPU access and helpers.
5415	* @{ */
5416	void iemFpuPushResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
5417	void iemFpuPushResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5418	void iemFpuPushResultTwo(PVMCPUCC pVCpu, PIEMFPURESULTTWO pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
5419	void iemFpuStoreResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
5420	void iemFpuStoreResultThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
5421	void iemFpuStoreResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
5422	uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5423	void iemFpuStoreResultWithMemOpThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
5424	uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5425	void iemFpuUpdateOpcodeAndIp(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5426	void iemFpuUpdateFSW(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
5427	void iemFpuUpdateFSWThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
5428	void iemFpuUpdateFSWWithMemOp(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5429	void iemFpuUpdateFSWThenPopPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
5430	void iemFpuUpdateFSWWithMemOpThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5431	void iemFpuStackUnderflow(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
5432	void iemFpuStackUnderflowWithMemOp(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5433	void iemFpuStackUnderflowThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
5434	void iemFpuStackUnderflowWithMemOpThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5435	void iemFpuStackUnderflowThenPopPop(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5436	void iemFpuStackPushUnderflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5437	void iemFpuStackPushUnderflowTwo(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5438	void iemFpuStackPushOverflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5439	void iemFpuStackPushOverflowWithMemOp(PVMCPUCC pVCpu, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5440	/** @} */
5441
5442	/** @name SSE+AVX SIMD access and helpers.
5443	* @{ */
5444	void iemSseStoreResult(PVMCPUCC pVCpu, PCIEMSSERESULT pResult, uint8_t iXmmReg) RT_NOEXCEPT;
5445	void iemSseUpdateMxcsr(PVMCPUCC pVCpu, uint32_t fMxcsr) RT_NOEXCEPT;
5446	/** @} */
5447
5448	/** @name Memory access.
5449	* @{ */
5450
5451	/** Report a \#GP instead of \#AC and do not restrict to ring-3 */
5452	#define IEM_MEMMAP_F_ALIGN_GP RT_BIT_32(16)
5453	/** SSE access that should report a \#GP instead of \#AC, unless MXCSR.MM=1
5454	* when it works like normal \#AC. Always used with IEM_MEMMAP_F_ALIGN_GP. */
5455	#define IEM_MEMMAP_F_ALIGN_SSE RT_BIT_32(17)
5456	/** If \#AC is applicable, raise it. Always used with IEM_MEMMAP_F_ALIGN_GP.
5457	* Users include FXSAVE & FXRSTOR. */
5458	#define IEM_MEMMAP_F_ALIGN_GP_OR_AC RT_BIT_32(18)
5459
5460	VBOXSTRICTRC iemMemMap(PVMCPUCC pVCpu, void *ppvMem, uint8_t pbUnmapInfo, size_t cbMem, uint8_t iSegReg, RTGCPTR GCPtrMem,
5461	uint32_t fAccess, uint32_t uAlignCtl) RT_NOEXCEPT;
5462	VBOXSTRICTRC iemMemCommitAndUnmap(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5463	#ifndef IN_RING3
5464	VBOXSTRICTRC iemMemCommitAndUnmapPostponeTroubleToR3(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5465	#endif
5466	void iemMemRollbackAndUnmap(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5467	void iemMemRollback(PVMCPUCC pVCpu) RT_NOEXCEPT;
5468	VBOXSTRICTRC iemMemApplySegment(PVMCPUCC pVCpu, uint32_t fAccess, uint8_t iSegReg, size_t cbMem, PRTGCPTR pGCPtrMem) RT_NOEXCEPT;
5469	VBOXSTRICTRC iemMemMarkSelDescAccessed(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5470	VBOXSTRICTRC iemMemPageTranslateAndCheckAccess(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t cbAccess, uint32_t fAccess, PRTGCPHYS pGCPhysMem) RT_NOEXCEPT;
5471
5472	void iemOpcodeFlushLight(PVMCPUCC pVCpu, uint8_t cbInstr);
5473	void iemOpcodeFlushHeavy(PVMCPUCC pVCpu, uint8_t cbInstr);
5474	#ifdef IEM_WITH_CODE_TLB
5475	void iemOpcodeFetchBytesJmp(PVMCPUCC pVCpu, size_t cbDst, void *pvDst) IEM_NOEXCEPT_MAY_LONGJMP;
5476	#else
5477	VBOXSTRICTRC iemOpcodeFetchMoreBytes(PVMCPUCC pVCpu, size_t cbMin) RT_NOEXCEPT;
5478	#endif
5479	#ifdef IEM_WITH_SETJMP
5480	uint8_t iemOpcodeGetNextU8SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5481	uint16_t iemOpcodeGetNextU16SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5482	uint32_t iemOpcodeGetNextU32SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5483	uint64_t iemOpcodeGetNextU64SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5484	#else
5485	VBOXSTRICTRC iemOpcodeGetNextU8Slow(PVMCPUCC pVCpu, uint8_t *pb) RT_NOEXCEPT;
5486	VBOXSTRICTRC iemOpcodeGetNextS8SxU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
5487	VBOXSTRICTRC iemOpcodeGetNextS8SxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
5488	VBOXSTRICTRC iemOpcodeGetNextS8SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5489	VBOXSTRICTRC iemOpcodeGetNextU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
5490	VBOXSTRICTRC iemOpcodeGetNextU16ZxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
5491	VBOXSTRICTRC iemOpcodeGetNextU16ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5492	VBOXSTRICTRC iemOpcodeGetNextU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
5493	VBOXSTRICTRC iemOpcodeGetNextU32ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5494	VBOXSTRICTRC iemOpcodeGetNextS32SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5495	VBOXSTRICTRC iemOpcodeGetNextU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5496	#endif
5497
5498	VBOXSTRICTRC iemMemFetchDataU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5499	VBOXSTRICTRC iemMemFetchDataU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5500	VBOXSTRICTRC iemMemFetchDataU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5501	VBOXSTRICTRC iemMemFetchDataU32_ZX_U64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5502	VBOXSTRICTRC iemMemFetchDataU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5503	VBOXSTRICTRC iemMemFetchDataU64AlignedU128(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5504	VBOXSTRICTRC iemMemFetchDataR80(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5505	VBOXSTRICTRC iemMemFetchDataD80(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5506	VBOXSTRICTRC iemMemFetchDataU128(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5507	VBOXSTRICTRC iemMemFetchDataU128NoAc(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5508	VBOXSTRICTRC iemMemFetchDataU128AlignedSse(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5509	VBOXSTRICTRC iemMemFetchDataU256(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5510	VBOXSTRICTRC iemMemFetchDataU256NoAc(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5511	VBOXSTRICTRC iemMemFetchDataU256AlignedAvx(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5512	VBOXSTRICTRC iemMemFetchDataXdtr(PVMCPUCC pVCpu, uint16_t *pcbLimit, PRTGCPTR pGCPtrBase, uint8_t iSegReg,
5513	RTGCPTR GCPtrMem, IEMMODE enmOpSize) RT_NOEXCEPT;
5514	#ifdef IEM_WITH_SETJMP
5515	uint8_t iemMemFetchDataU8SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5516	uint16_t iemMemFetchDataU16SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5517	uint32_t iemMemFetchDataU32SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5518	uint32_t iemMemFlatFetchDataU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5519	uint64_t iemMemFetchDataU64SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5520	uint64_t iemMemFetchDataU64AlignedU128SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5521	void iemMemFetchDataR80SafeJmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5522	void iemMemFetchDataD80SafeJmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5523	void iemMemFetchDataU128SafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5524	void iemMemFetchDataU128NoAcSafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5525	void iemMemFetchDataU128AlignedSseSafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5526	void iemMemFetchDataU256SafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5527	void iemMemFetchDataU256NoAcSafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5528	void iemMemFetchDataU256AlignedAvxSafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5529	# if 0 /* these are inlined now */
5530	uint8_t iemMemFetchDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5531	uint16_t iemMemFetchDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5532	uint32_t iemMemFetchDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5533	uint32_t iemMemFlatFetchDataU32Jmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5534	uint64_t iemMemFetchDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5535	uint64_t iemMemFetchDataU64AlignedU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5536	void iemMemFetchDataR80Jmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5537	void iemMemFetchDataD80Jmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5538	void iemMemFetchDataU128Jmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5539	void iemMemFetchDataU128NoAcJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5540	void iemMemFetchDataU128AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5541	void iemMemFetchDataU256NoAcJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5542	void iemMemFetchDataU256AlignedAvxJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5543	# endif
5544	void iemMemFetchDataU256Jmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5545	#endif
5546
5547	VBOXSTRICTRC iemMemFetchSysU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5548	VBOXSTRICTRC iemMemFetchSysU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5549	VBOXSTRICTRC iemMemFetchSysU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5550	VBOXSTRICTRC iemMemFetchSysU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5551	VBOXSTRICTRC iemMemFetchSelDesc(PVMCPUCC pVCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt) RT_NOEXCEPT;
5552
5553	VBOXSTRICTRC iemMemStoreDataU8(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) RT_NOEXCEPT;
5554	VBOXSTRICTRC iemMemStoreDataU16(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) RT_NOEXCEPT;
5555	VBOXSTRICTRC iemMemStoreDataU32(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) RT_NOEXCEPT;
5556	VBOXSTRICTRC iemMemStoreDataU64(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) RT_NOEXCEPT;
5557	VBOXSTRICTRC iemMemStoreDataU128(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
5558	VBOXSTRICTRC iemMemStoreDataU128NoAc(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
5559	VBOXSTRICTRC iemMemStoreDataU128AlignedSse(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
5560	VBOXSTRICTRC iemMemStoreDataU256(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
5561	VBOXSTRICTRC iemMemStoreDataU256NoAc(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
5562	VBOXSTRICTRC iemMemStoreDataU256AlignedAvx(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
5563	VBOXSTRICTRC iemMemStoreDataXdtr(PVMCPUCC pVCpu, uint16_t cbLimit, RTGCPTR GCPtrBase, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5564	#ifdef IEM_WITH_SETJMP
5565	void iemMemStoreDataU8SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
5566	void iemMemStoreDataU16SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
5567	void iemMemStoreDataU32SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
5568	void iemMemStoreDataU64SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
5569	void iemMemStoreDataU128SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5570	void iemMemStoreDataU128NoAcSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT128U pu128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5571	void iemMemStoreDataU128AlignedSseSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT128U pu128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5572	void iemMemStoreDataU256SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5573	void iemMemStoreDataU256NoAcSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5574	void iemMemStoreDataU256AlignedAvxSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5575	void iemMemStoreDataR80SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTFLOAT80U pr80Value) IEM_NOEXCEPT_MAY_LONGJMP;
5576	void iemMemStoreDataD80SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTPBCD80U pd80Value) IEM_NOEXCEPT_MAY_LONGJMP;
5577	#if 0
5578	void iemMemStoreDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
5579	void iemMemStoreDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
5580	void iemMemStoreDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
5581	void iemMemStoreDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
5582	void iemMemStoreDataU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5583	void iemMemStoreDataNoAcU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5584	void iemMemStoreDataU256NoAcJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5585	void iemMemStoreDataU256AlignedAvxJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5586	#endif
5587	void iemMemStoreDataU128AlignedSseJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5588	void iemMemStoreDataU256Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5589	#endif
5590
5591	#ifdef IEM_WITH_SETJMP
5592	uint8_t iemMemMapDataU8RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5593	uint8_t iemMemMapDataU8AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5594	uint8_t iemMemMapDataU8WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5595	uint8_t const iemMemMapDataU8RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5596	uint16_t iemMemMapDataU16RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5597	uint16_t iemMemMapDataU16AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5598	uint16_t iemMemMapDataU16WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5599	uint16_t const iemMemMapDataU16RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5600	uint32_t iemMemMapDataU32RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5601	uint32_t iemMemMapDataU32AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5602	uint32_t iemMemMapDataU32WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5603	uint32_t const iemMemMapDataU32RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5604	uint64_t iemMemMapDataU64RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5605	uint64_t iemMemMapDataU64AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5606	uint64_t iemMemMapDataU64WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5607	uint64_t const iemMemMapDataU64RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5608	PRTFLOAT80U iemMemMapDataR80RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5609	PRTFLOAT80U iemMemMapDataR80WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5610	PCRTFLOAT80U iemMemMapDataR80RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5611	PRTPBCD80U iemMemMapDataD80RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5612	PRTPBCD80U iemMemMapDataD80WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5613	PCRTPBCD80U iemMemMapDataD80RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5614	PRTUINT128U iemMemMapDataU128RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5615	PRTUINT128U iemMemMapDataU128AtSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5616	PRTUINT128U iemMemMapDataU128WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5617	PCRTUINT128U iemMemMapDataU128RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5618
5619	void iemMemCommitAndUnmapJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5620	void iemMemCommitAndUnmapRwSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5621	void iemMemCommitAndUnmapAtSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5622	void iemMemCommitAndUnmapWoSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5623	void iemMemCommitAndUnmapRoSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5624	void iemMemRollbackAndUnmapWoSafe(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5625	#endif
5626
5627	VBOXSTRICTRC iemMemStackPushBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
5628	void *ppvMem, uint8_t pbUnmapInfo, uint64_t *puNewRsp) RT_NOEXCEPT;
5629	VBOXSTRICTRC iemMemStackPushCommitSpecial(PVMCPUCC pVCpu, uint8_t bUnmapInfo, uint64_t uNewRsp) RT_NOEXCEPT;
5630	VBOXSTRICTRC iemMemStackPushU16(PVMCPUCC pVCpu, uint16_t u16Value) RT_NOEXCEPT;
5631	VBOXSTRICTRC iemMemStackPushU32(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
5632	VBOXSTRICTRC iemMemStackPushU64(PVMCPUCC pVCpu, uint64_t u64Value) RT_NOEXCEPT;
5633	VBOXSTRICTRC iemMemStackPushU16Ex(PVMCPUCC pVCpu, uint16_t u16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5634	VBOXSTRICTRC iemMemStackPushU32Ex(PVMCPUCC pVCpu, uint32_t u32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5635	VBOXSTRICTRC iemMemStackPushU64Ex(PVMCPUCC pVCpu, uint64_t u64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5636	VBOXSTRICTRC iemMemStackPushU32SReg(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
5637	VBOXSTRICTRC iemMemStackPopBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
5638	void const *ppvMem, uint8_t pbUnmapInfo, uint64_t *puNewRsp) RT_NOEXCEPT;
5639	VBOXSTRICTRC iemMemStackPopContinueSpecial(PVMCPUCC pVCpu, size_t off, size_t cbMem,
5640	void const *ppvMem, uint8_t pbUnmapInfo, uint64_t uCurNewRsp) RT_NOEXCEPT;
5641	VBOXSTRICTRC iemMemStackPopDoneSpecial(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5642	VBOXSTRICTRC iemMemStackPopU16(PVMCPUCC pVCpu, uint16_t *pu16Value) RT_NOEXCEPT;
5643	VBOXSTRICTRC iemMemStackPopU32(PVMCPUCC pVCpu, uint32_t *pu32Value) RT_NOEXCEPT;
5644	VBOXSTRICTRC iemMemStackPopU64(PVMCPUCC pVCpu, uint64_t *pu64Value) RT_NOEXCEPT;
5645	VBOXSTRICTRC iemMemStackPopU16Ex(PVMCPUCC pVCpu, uint16_t *pu16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5646	VBOXSTRICTRC iemMemStackPopU32Ex(PVMCPUCC pVCpu, uint32_t *pu32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5647	VBOXSTRICTRC iemMemStackPopU64Ex(PVMCPUCC pVCpu, uint64_t *pu64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5648
5649	#ifdef IEM_WITH_SETJMP
5650	void iemMemStackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5651	void iemMemStackPushU32SafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5652	void iemMemStackPushU32SRegSafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5653	void iemMemStackPushU64SafeJmp(PVMCPUCC pVCpu, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5654	void iemMemStackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5655	void iemMemStackPopGRegU32SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5656	void iemMemStackPopGRegU64SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5657
5658	void iemMemFlat32StackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5659	void iemMemFlat32StackPushU32SafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5660	void iemMemFlat32StackPushU32SRegSafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5661	void iemMemFlat32StackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5662	void iemMemFlat32StackPopGRegU32SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5663
5664	void iemMemFlat64StackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5665	void iemMemFlat64StackPushU64SafeJmp(PVMCPUCC pVCpu, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5666	void iemMemFlat64StackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5667	void iemMemFlat64StackPopGRegU64SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5668
5669	void iemMemStoreStackU16SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5670	void iemMemStoreStackU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5671	void iemMemStoreStackU32SRegSafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5672	void iemMemStoreStackU64SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5673
5674	uint16_t iemMemFetchStackU16SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5675	uint32_t iemMemFetchStackU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5676	uint64_t iemMemFetchStackU64SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5677
5678	#endif
5679
5680	/** @} */
5681
5682	/** @name IEMAllCImpl.cpp
5683	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/'
5684	* @{ */
5685	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem16, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5686	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem32, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5687	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem64, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5688	IEM_CIMPL_PROTO_0(iemCImpl_popa_16);
5689	IEM_CIMPL_PROTO_0(iemCImpl_popa_32);
5690	IEM_CIMPL_PROTO_0(iemCImpl_pusha_16);
5691	IEM_CIMPL_PROTO_0(iemCImpl_pusha_32);
5692	IEM_CIMPL_PROTO_1(iemCImpl_pushf, IEMMODE, enmEffOpSize);
5693	IEM_CIMPL_PROTO_1(iemCImpl_popf, IEMMODE, enmEffOpSize);
5694	IEM_CIMPL_PROTO_1(iemCImpl_call_16, uint16_t, uNewPC);
5695	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_16, int16_t, offDisp);
5696	IEM_CIMPL_PROTO_1(iemCImpl_call_32, uint32_t, uNewPC);
5697	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_32, int32_t, offDisp);
5698	IEM_CIMPL_PROTO_1(iemCImpl_call_64, uint64_t, uNewPC);
5699	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_64, int64_t, offDisp);
5700	IEM_CIMPL_PROTO_3(iemCImpl_FarJmp, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
5701	IEM_CIMPL_PROTO_3(iemCImpl_callf, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
5702	typedef IEM_CIMPL_DECL_TYPE_3(FNIEMCIMPLFARBRANCH, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
5703	typedef FNIEMCIMPLFARBRANCH *PFNIEMCIMPLFARBRANCH;
5704	IEM_CIMPL_PROTO_2(iemCImpl_retf, IEMMODE, enmEffOpSize, uint16_t, cbPop);
5705	IEM_CIMPL_PROTO_0(iemCImpl_retn_16);
5706	IEM_CIMPL_PROTO_0(iemCImpl_retn_32);
5707	IEM_CIMPL_PROTO_0(iemCImpl_retn_64);
5708	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_16, uint16_t, cbPop);
5709	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_32, uint16_t, cbPop);
5710	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_64, uint16_t, cbPop);
5711	IEM_CIMPL_PROTO_3(iemCImpl_enter, IEMMODE, enmEffOpSize, uint16_t, cbFrame, uint8_t, cParameters);
5712	IEM_CIMPL_PROTO_1(iemCImpl_leave, IEMMODE, enmEffOpSize);
5713	IEM_CIMPL_PROTO_2(iemCImpl_int, uint8_t, u8Int, IEMINT, enmInt);
5714	IEM_CIMPL_PROTO_1(iemCImpl_iret_real_v8086, IEMMODE, enmEffOpSize);
5715	IEM_CIMPL_PROTO_4(iemCImpl_iret_prot_v8086, uint32_t, uNewEip, uint16_t, uNewCs, uint32_t, uNewFlags, uint64_t, uNewRsp);
5716	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot_NestedTask, IEMMODE, enmEffOpSize);
5717	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot, IEMMODE, enmEffOpSize);
5718	IEM_CIMPL_PROTO_1(iemCImpl_iret_64bit, IEMMODE, enmEffOpSize);
5719	IEM_CIMPL_PROTO_1(iemCImpl_iret, IEMMODE, enmEffOpSize);
5720	IEM_CIMPL_PROTO_0(iemCImpl_loadall286);
5721	IEM_CIMPL_PROTO_0(iemCImpl_syscall);
5722	IEM_CIMPL_PROTO_1(iemCImpl_sysret, IEMMODE, enmEffOpSize);
5723	IEM_CIMPL_PROTO_0(iemCImpl_sysenter);
5724	IEM_CIMPL_PROTO_1(iemCImpl_sysexit, IEMMODE, enmEffOpSize);
5725	IEM_CIMPL_PROTO_2(iemCImpl_LoadSReg, uint8_t, iSegReg, uint16_t, uSel);
5726	IEM_CIMPL_PROTO_2(iemCImpl_load_SReg, uint8_t, iSegReg, uint16_t, uSel);
5727	IEM_CIMPL_PROTO_2(iemCImpl_pop_Sreg, uint8_t, iSegReg, IEMMODE, enmEffOpSize);
5728	IEM_CIMPL_PROTO_5(iemCImpl_load_SReg_Greg, uint16_t, uSel, uint64_t, offSeg, uint8_t, iSegReg, uint8_t, iGReg, IEMMODE, enmEffOpSize);
5729	IEM_CIMPL_PROTO_2(iemCImpl_VerX, uint16_t, uSel, bool, fWrite);
5730	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u64, uint64_t *, pu64Dst, uint16_t, uSel, bool, fIsLar);
5731	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u16, uint16_t *, pu16Dst, uint16_t, uSel, bool, fIsLar);
5732	IEM_CIMPL_PROTO_3(iemCImpl_lgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
5733	IEM_CIMPL_PROTO_2(iemCImpl_sgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5734	IEM_CIMPL_PROTO_3(iemCImpl_lidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
5735	IEM_CIMPL_PROTO_2(iemCImpl_sidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5736	IEM_CIMPL_PROTO_1(iemCImpl_lldt, uint16_t, uNewLdt);
5737	IEM_CIMPL_PROTO_2(iemCImpl_sldt_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
5738	IEM_CIMPL_PROTO_2(iemCImpl_sldt_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5739	IEM_CIMPL_PROTO_1(iemCImpl_ltr, uint16_t, uNewTr);
5740	IEM_CIMPL_PROTO_2(iemCImpl_str_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
5741	IEM_CIMPL_PROTO_2(iemCImpl_str_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5742	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Cd, uint8_t, iGReg, uint8_t, iCrReg);
5743	IEM_CIMPL_PROTO_2(iemCImpl_smsw_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
5744	IEM_CIMPL_PROTO_2(iemCImpl_smsw_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5745	IEM_CIMPL_PROTO_4(iemCImpl_load_CrX, uint8_t, iCrReg, uint64_t, uNewCrX, IEMACCESSCRX, enmAccessCrX, uint8_t, iGReg);
5746	IEM_CIMPL_PROTO_2(iemCImpl_mov_Cd_Rd, uint8_t, iCrReg, uint8_t, iGReg);
5747	IEM_CIMPL_PROTO_2(iemCImpl_lmsw, uint16_t, u16NewMsw, RTGCPTR, GCPtrEffDst);
5748	IEM_CIMPL_PROTO_0(iemCImpl_clts);
5749	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Dd, uint8_t, iGReg, uint8_t, iDrReg);
5750	IEM_CIMPL_PROTO_2(iemCImpl_mov_Dd_Rd, uint8_t, iDrReg, uint8_t, iGReg);
5751	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Td, uint8_t, iGReg, uint8_t, iTrReg);
5752	IEM_CIMPL_PROTO_2(iemCImpl_mov_Td_Rd, uint8_t, iTrReg, uint8_t, iGReg);
5753	IEM_CIMPL_PROTO_1(iemCImpl_invlpg, RTGCPTR, GCPtrPage);
5754	IEM_CIMPL_PROTO_3(iemCImpl_invpcid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvpcidDesc, uint64_t, uInvpcidType);
5755	IEM_CIMPL_PROTO_0(iemCImpl_invd);
5756	IEM_CIMPL_PROTO_0(iemCImpl_wbinvd);
5757	IEM_CIMPL_PROTO_0(iemCImpl_rsm);
5758	IEM_CIMPL_PROTO_0(iemCImpl_rdtsc);
5759	IEM_CIMPL_PROTO_0(iemCImpl_rdtscp);
5760	IEM_CIMPL_PROTO_0(iemCImpl_rdpmc);
5761	IEM_CIMPL_PROTO_0(iemCImpl_rdmsr);
5762	IEM_CIMPL_PROTO_0(iemCImpl_wrmsr);
5763	IEM_CIMPL_PROTO_3(iemCImpl_in, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
5764	IEM_CIMPL_PROTO_2(iemCImpl_in_eAX_DX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
5765	IEM_CIMPL_PROTO_3(iemCImpl_out, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
5766	IEM_CIMPL_PROTO_2(iemCImpl_out_DX_eAX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
5767	IEM_CIMPL_PROTO_0(iemCImpl_cli);
5768	IEM_CIMPL_PROTO_0(iemCImpl_sti);
5769	IEM_CIMPL_PROTO_0(iemCImpl_hlt);
5770	IEM_CIMPL_PROTO_1(iemCImpl_monitor, uint8_t, iEffSeg);
5771	IEM_CIMPL_PROTO_0(iemCImpl_mwait);
5772	IEM_CIMPL_PROTO_0(iemCImpl_swapgs);
5773	IEM_CIMPL_PROTO_0(iemCImpl_cpuid);
5774	IEM_CIMPL_PROTO_1(iemCImpl_aad, uint8_t, bImm);
5775	IEM_CIMPL_PROTO_1(iemCImpl_aam, uint8_t, bImm);
5776	IEM_CIMPL_PROTO_0(iemCImpl_daa);
5777	IEM_CIMPL_PROTO_0(iemCImpl_das);
5778	IEM_CIMPL_PROTO_0(iemCImpl_aaa);
5779	IEM_CIMPL_PROTO_0(iemCImpl_aas);
5780	IEM_CIMPL_PROTO_3(iemCImpl_bound_16, int16_t, idxArray, int16_t, idxLowerBound, int16_t, idxUpperBound);
5781	IEM_CIMPL_PROTO_3(iemCImpl_bound_32, int32_t, idxArray, int32_t, idxLowerBound, int32_t, idxUpperBound);
5782	IEM_CIMPL_PROTO_0(iemCImpl_xgetbv);
5783	IEM_CIMPL_PROTO_0(iemCImpl_xsetbv);
5784	IEM_CIMPL_PROTO_5(iemCImpl_cmpxchg16b_fallback_rendezvous, PRTUINT128U, pu128Dst, PRTUINT128U, pu128RaxRdx,
5785	PRTUINT128U, pu128RbxRcx, uint32_t *, pEFlags, uint8_t, bUnmapInfo);
5786	IEM_CIMPL_PROTO_2(iemCImpl_clflush_clflushopt, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5787	IEM_CIMPL_PROTO_1(iemCImpl_finit, bool, fCheckXcpts);
5788	IEM_CIMPL_PROTO_3(iemCImpl_fxsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5789	IEM_CIMPL_PROTO_3(iemCImpl_fxrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5790	IEM_CIMPL_PROTO_3(iemCImpl_xsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5791	IEM_CIMPL_PROTO_3(iemCImpl_xrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5792	IEM_CIMPL_PROTO_2(iemCImpl_stmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5793	IEM_CIMPL_PROTO_2(iemCImpl_vstmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5794	IEM_CIMPL_PROTO_2(iemCImpl_ldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5795	IEM_CIMPL_PROTO_3(iemCImpl_fnstenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5796	IEM_CIMPL_PROTO_3(iemCImpl_fnsave, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5797	IEM_CIMPL_PROTO_3(iemCImpl_fldenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
5798	IEM_CIMPL_PROTO_3(iemCImpl_frstor, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
5799	IEM_CIMPL_PROTO_1(iemCImpl_fldcw, uint16_t, u16Fcw);
5800	IEM_CIMPL_PROTO_2(iemCImpl_fxch_underflow, uint8_t, iStReg, uint16_t, uFpuOpcode);
5801	IEM_CIMPL_PROTO_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, bool, fUCmp, uint32_t, uPopAndFpuOpcode);
5802	IEM_CIMPL_PROTO_2(iemCImpl_rdseed, uint8_t, iReg, IEMMODE, enmEffOpSize);
5803	IEM_CIMPL_PROTO_2(iemCImpl_rdrand, uint8_t, iReg, IEMMODE, enmEffOpSize);
5804	/** @} */
5805
5806	/** @name IEMAllCImplStrInstr.cpp.h
5807	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/' -e 's/RT_CONCAT4(//' \
5808	* -e 's/,ADDR_SIZE)/64/g' -e 's/,OP_SIZE,/64/g' -e 's/,OP_rAX,/rax/g' IEMAllCImplStrInstr.cpp.h
5809	* @{ */
5810	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr16, uint8_t, iEffSeg);
5811	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr16, uint8_t, iEffSeg);
5812	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m16);
5813	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m16);
5814	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr16, uint8_t, iEffSeg);
5815	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m16);
5816	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m16, int8_t, iEffSeg);
5817	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr16, bool, fIoChecked);
5818	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr16, bool, fIoChecked);
5819	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5820	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5821
5822	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr16, uint8_t, iEffSeg);
5823	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr16, uint8_t, iEffSeg);
5824	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m16);
5825	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m16);
5826	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr16, uint8_t, iEffSeg);
5827	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m16);
5828	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m16, int8_t, iEffSeg);
5829	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr16, bool, fIoChecked);
5830	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr16, bool, fIoChecked);
5831	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5832	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5833
5834	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr16, uint8_t, iEffSeg);
5835	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr16, uint8_t, iEffSeg);
5836	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m16);
5837	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m16);
5838	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr16, uint8_t, iEffSeg);
5839	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m16);
5840	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m16, int8_t, iEffSeg);
5841	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr16, bool, fIoChecked);
5842	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr16, bool, fIoChecked);
5843	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5844	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5845
5846
5847	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr32, uint8_t, iEffSeg);
5848	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr32, uint8_t, iEffSeg);
5849	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m32);
5850	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m32);
5851	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr32, uint8_t, iEffSeg);
5852	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m32);
5853	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m32, int8_t, iEffSeg);
5854	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr32, bool, fIoChecked);
5855	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr32, bool, fIoChecked);
5856	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5857	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5858
5859	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr32, uint8_t, iEffSeg);
5860	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr32, uint8_t, iEffSeg);
5861	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m32);
5862	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m32);
5863	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr32, uint8_t, iEffSeg);
5864	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m32);
5865	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m32, int8_t, iEffSeg);
5866	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr32, bool, fIoChecked);
5867	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr32, bool, fIoChecked);
5868	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5869	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5870
5871	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr32, uint8_t, iEffSeg);
5872	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr32, uint8_t, iEffSeg);
5873	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m32);
5874	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m32);
5875	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr32, uint8_t, iEffSeg);
5876	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m32);
5877	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m32, int8_t, iEffSeg);
5878	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr32, bool, fIoChecked);
5879	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr32, bool, fIoChecked);
5880	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5881	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5882
5883	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr32, uint8_t, iEffSeg);
5884	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr32, uint8_t, iEffSeg);
5885	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m32);
5886	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m32);
5887	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr32, uint8_t, iEffSeg);
5888	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m32);
5889	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m32, int8_t, iEffSeg);
5890	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr32, bool, fIoChecked);
5891	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr32, bool, fIoChecked);
5892	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5893	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5894
5895
5896	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr64, uint8_t, iEffSeg);
5897	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr64, uint8_t, iEffSeg);
5898	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m64);
5899	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m64);
5900	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr64, uint8_t, iEffSeg);
5901	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m64);
5902	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m64, int8_t, iEffSeg);
5903	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr64, bool, fIoChecked);
5904	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr64, bool, fIoChecked);
5905	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5906	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5907
5908	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr64, uint8_t, iEffSeg);
5909	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr64, uint8_t, iEffSeg);
5910	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m64);
5911	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m64);
5912	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr64, uint8_t, iEffSeg);
5913	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m64);
5914	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m64, int8_t, iEffSeg);
5915	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr64, bool, fIoChecked);
5916	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr64, bool, fIoChecked);
5917	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5918	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5919
5920	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr64, uint8_t, iEffSeg);
5921	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr64, uint8_t, iEffSeg);
5922	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m64);
5923	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m64);
5924	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr64, uint8_t, iEffSeg);
5925	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m64);
5926	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m64, int8_t, iEffSeg);
5927	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr64, bool, fIoChecked);
5928	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr64, bool, fIoChecked);
5929	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5930	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5931
5932	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr64, uint8_t, iEffSeg);
5933	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr64, uint8_t, iEffSeg);
5934	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m64);
5935	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m64);
5936	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr64, uint8_t, iEffSeg);
5937	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m64);
5938	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m64, int8_t, iEffSeg);
5939	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr64, bool, fIoChecked);
5940	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr64, bool, fIoChecked);
5941	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5942	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5943	/** @} */
5944
5945	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5946	VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT;
5947	VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT;
5948	VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT;
5949	VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT;
5950	VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT;
5951	VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
5952	VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALK pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT;
5953	VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT;
5954	VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT;
5955	VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
5956	bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT;
5957	VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
5958	bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT;
5959	VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5960	VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5961	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5962	VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5963	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5964	VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
5965	VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT;
5966	VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
5967	RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT;
5968	VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT;
5969	VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT;
5970	VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT;
5971	uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT;
5972	void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT;
5973	VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
5974	uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT;
5975	bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT;
5976	IEM_CIMPL_PROTO_0(iemCImpl_vmxoff);
5977	IEM_CIMPL_PROTO_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon);
5978	IEM_CIMPL_PROTO_0(iemCImpl_vmlaunch);
5979	IEM_CIMPL_PROTO_0(iemCImpl_vmresume);
5980	IEM_CIMPL_PROTO_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
5981	IEM_CIMPL_PROTO_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
5982	IEM_CIMPL_PROTO_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
5983	IEM_CIMPL_PROTO_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField);
5984	IEM_CIMPL_PROTO_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField);
5985	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField);
5986	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg32, uint64_t *, pu32Dst, uint32_t, u32VmcsField);
5987	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField);
5988	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField);
5989	IEM_CIMPL_PROTO_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType);
5990	IEM_CIMPL_PROTO_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType);
5991	IEM_CIMPL_PROTO_0(iemCImpl_vmx_pause);
5992	#endif
5993
5994	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5995	VBOXSTRICTRC iemSvmVmexit(PVMCPUCC pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2) RT_NOEXCEPT;
5996	VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr, uint64_t uCr2) RT_NOEXCEPT;
5997	VBOXSTRICTRC iemSvmHandleIOIntercept(PVMCPUCC pVCpu, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
5998	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, uint8_t cbInstr) RT_NOEXCEPT;
5999	VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPUCC pVCpu, uint32_t idMsr, bool fWrite, uint8_t cbInstr) RT_NOEXCEPT;
6000	IEM_CIMPL_PROTO_0(iemCImpl_vmrun);
6001	IEM_CIMPL_PROTO_0(iemCImpl_vmload);
6002	IEM_CIMPL_PROTO_0(iemCImpl_vmsave);
6003	IEM_CIMPL_PROTO_0(iemCImpl_clgi);
6004	IEM_CIMPL_PROTO_0(iemCImpl_stgi);
6005	IEM_CIMPL_PROTO_0(iemCImpl_invlpga);
6006	IEM_CIMPL_PROTO_0(iemCImpl_skinit);
6007	IEM_CIMPL_PROTO_0(iemCImpl_svm_pause);
6008	#endif
6009
6010	IEM_CIMPL_PROTO_0(iemCImpl_vmcall); /* vmx */
6011	IEM_CIMPL_PROTO_0(iemCImpl_vmmcall); /* svm */
6012	IEM_CIMPL_PROTO_1(iemCImpl_Hypercall, uint16_t, uDisOpcode); /* both */
6013
6014	extern const PFNIEMOP g_apfnIemInterpretOnlyOneByteMap[256];
6015	extern const PFNIEMOP g_apfnIemInterpretOnlyTwoByteMap[1024];
6016	extern const PFNIEMOP g_apfnIemInterpretOnlyThreeByte0f3a[1024];
6017	extern const PFNIEMOP g_apfnIemInterpretOnlyThreeByte0f38[1024];
6018	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap1[1024];
6019	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap2[1024];
6020	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap3[1024];
6021
6022	/*
6023	* Recompiler related stuff.
6024	*/
6025	extern const PFNIEMOP g_apfnIemThreadedRecompilerOneByteMap[256];
6026	extern const PFNIEMOP g_apfnIemThreadedRecompilerTwoByteMap[1024];
6027	extern const PFNIEMOP g_apfnIemThreadedRecompilerThreeByte0f3a[1024];
6028	extern const PFNIEMOP g_apfnIemThreadedRecompilerThreeByte0f38[1024];
6029	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap1[1024];
6030	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap2[1024];
6031	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap3[1024];
6032
6033	DECLCALLBACK(int) iemTbInit(PVMCC pVM, uint32_t cInitialTbs, uint32_t cMaxTbs,
6034	uint64_t cbInitialExec, uint64_t cbMaxExec, uint32_t cbChunkExec);
6035	void iemThreadedTbObsolete(PVMCPUCC pVCpu, PIEMTB pTb, bool fSafeToFree);
6036	void iemTbAllocatorProcessDelayedFrees(PVMCPUCC pVCpu, PIEMTBALLOCATOR pTbAllocator);
6037	void iemTbAllocatorFreeupNativeSpace(PVMCPUCC pVCpu, uint32_t cNeededInstrs);
6038	DECLHIDDEN(const char ) iemTbFlagsToString(uint32_t fFlags, char pszBuf, size_t cbBuf) RT_NOEXCEPT;
6039	DECLHIDDEN(void) iemThreadedDisassembleTb(PCIEMTB pTb, PCDBGFINFOHLP pHlp) RT_NOEXCEPT;
6040
6041
6042	/** @todo FNIEMTHREADEDFUNC and friends may need more work... */
6043	#if defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
6044	typedef VBOXSTRICTRC /__attribute__((__nothrow__))/ FNIEMTHREADEDFUNC(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
6045	typedef FNIEMTHREADEDFUNC *PFNIEMTHREADEDFUNC;
6046	# define IEM_DECL_IEMTHREADEDFUNC_DEF(a_Name) \
6047	VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2)
6048	# define IEM_DECL_IEMTHREADEDFUNC_PROTO(a_Name) \
6049	VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2)
6050
6051	#else
6052	typedef VBOXSTRICTRC (FNIEMTHREADEDFUNC)(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
6053	typedef FNIEMTHREADEDFUNC *PFNIEMTHREADEDFUNC;
6054	# define IEM_DECL_IEMTHREADEDFUNC_DEF(a_Name) \
6055	VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2) IEM_NOEXCEPT_MAY_LONGJMP
6056	# define IEM_DECL_IEMTHREADEDFUNC_PROTO(a_Name) \
6057	VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2) IEM_NOEXCEPT_MAY_LONGJMP
6058	#endif
6059
6060
6061	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_Nop);
6062	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_LogCpuState);
6063
6064	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_DeferToCImpl0);
6065
6066	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckIrq);
6067	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckMode);
6068	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckHwInstrBps);
6069	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLim);
6070
6071	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodes);
6072	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodes);
6073	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesConsiderCsLim);
6074
6075	/* Branching: */
6076	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndPcAndOpcodes);
6077	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckPcAndOpcodes);
6078	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckPcAndOpcodesConsiderCsLim);
6079
6080	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesLoadingTlb);
6081	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesLoadingTlb);
6082	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesLoadingTlbConsiderCsLim);
6083
6084	/* Natural page crossing: */
6085	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesAcrossPageLoadingTlb);
6086	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesAcrossPageLoadingTlb);
6087	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesAcrossPageLoadingTlbConsiderCsLim);
6088
6089	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesOnNextPageLoadingTlb);
6090	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNextPageLoadingTlb);
6091	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNextPageLoadingTlbConsiderCsLim);
6092
6093	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesOnNewPageLoadingTlb);
6094	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNewPageLoadingTlb);
6095	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNewPageLoadingTlbConsiderCsLim);
6096
6097	bool iemThreadedCompileEmitIrqCheckBefore(PVMCPUCC pVCpu, PIEMTB pTb);
6098	bool iemThreadedCompileBeginEmitCallsComplications(PVMCPUCC pVCpu, PIEMTB pTb);
6099
6100	/* Native recompiler public bits: */
6101	DECLHIDDEN(PIEMTB) iemNativeRecompile(PVMCPUCC pVCpu, PIEMTB pTb) RT_NOEXCEPT;
6102	DECLHIDDEN(void) iemNativeDisassembleTb(PCIEMTB pTb, PCDBGFINFOHLP pHlp) RT_NOEXCEPT;
6103	int iemExecMemAllocatorInit(PVMCPU pVCpu, uint64_t cbMax, uint64_t cbInitial, uint32_t cbChunk);
6104	void iemExecMemAllocatorFree(PVMCPU pVCpu, void *pv, size_t cb);
6105	DECLASM(DECL_NO_RETURN(void)) iemNativeTbLongJmp(void *pvFramePointer, int rc) RT_NOEXCEPT;
6106
6107
6108	/** @} */
6109
6110	RT_C_DECLS_END
6111
6112	#endif /* !VMM_INCLUDED_SRC_include_IEMInternal_h */
6113

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h@ 104019

Download in other formats: