IEMInternal.h@ 104378

Last change on this file since 104378 was 104378, checked in by vboxsync, 8 months ago
VMM/IEM: Automtically convert IEMInternal.h & IEMN8veRecompiler.h into nasm/yasm include files so IEMAllN8veHlpA.asm can make use of some of the constants define in them for the prolog code. bugref:10653 bugref:10370
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 320.1 KB

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1	/* $Id: IEMInternal.h 104378 2024-04-19 14:43:14Z vboxsync $ */
2	/** @file
3	* IEM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2011-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_IEMInternal_h
29	#define VMM_INCLUDED_SRC_include_IEMInternal_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#ifndef RT_IN_ASSEMBLER
35	# include <VBox/vmm/cpum.h>
36	# include <VBox/vmm/iem.h>
37	# include <VBox/vmm/pgm.h>
38	# include <VBox/vmm/stam.h>
39	# include <VBox/param.h>
40
41	# include <iprt/setjmp-without-sigmask.h>
42	# include <iprt/list.h>
43	#endif /* !RT_IN_ASSEMBLER */
44
45
46	RT_C_DECLS_BEGIN
47
48
49	/** @defgroup grp_iem_int Internals
50	* @ingroup grp_iem
51	* @internal
52	* @{
53	*/
54
55	/* Make doxygen happy w/o overcomplicating the #if checks. */
56	#ifdef DOXYGEN_RUNNING
57	# define IEM_WITH_THROW_CATCH
58	# define VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
59	#endif
60
61	/** For expanding symbol in slickedit and other products tagging and
62	* crossreferencing IEM symbols. */
63	#ifndef IEM_STATIC
64	# define IEM_STATIC static
65	#endif
66
67	/** @def IEM_WITH_SETJMP
68	* Enables alternative status code handling using setjmps.
69	*
70	* This adds a bit of expense via the setjmp() call since it saves all the
71	* non-volatile registers. However, it eliminates return code checks and allows
72	* for more optimal return value passing (return regs instead of stack buffer).
73	*/
74	#if defined(DOXYGEN_RUNNING) \|\| defined(RT_OS_WINDOWS) \|\| 1
75	# define IEM_WITH_SETJMP
76	#endif
77
78	/** @def IEM_WITH_THROW_CATCH
79	* Enables using C++ throw/catch as an alternative to setjmp/longjmp in user
80	* mode code when IEM_WITH_SETJMP is in effect.
81	*
82	* With GCC 11.3.1 and code TLB on linux, using throw/catch instead of
83	* setjmp/long resulted in bs2-test-1 running 3.00% faster and all but on test
84	* result value improving by more than 1%. (Best out of three.)
85	*
86	* With Visual C++ 2019 and code TLB on windows, using throw/catch instead of
87	* setjmp/long resulted in bs2-test-1 running 3.68% faster and all but some of
88	* the MMIO and CPUID tests ran noticeably faster. Variation is greater than on
89	* Linux, but it should be quite a bit faster for normal code.
90	*/
91	#if defined(__cplusplus) && defined(IEM_WITH_SETJMP) && defined(IN_RING3) && (defined(__GNUC__) \|\| defined(_MSC_VER)) /* ASM-NOINC-START */
92	# define IEM_WITH_THROW_CATCH
93	#endif /ASM-NOINC-END/
94
95	/** @def IEMNATIVE_WITH_DELAYED_PC_UPDATING
96	* Enables the delayed PC updating optimization (see @bugref{10373}).
97	*/
98	#if defined(DOXYGEN_RUNNING) \|\| 1
99	# define IEMNATIVE_WITH_DELAYED_PC_UPDATING
100	#endif
101
102	/** Enables the SIMD register allocator @bugref{10614}. */
103	#if defined(DOXYGEN_RUNNING) \|\| 1
104	# define IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
105	#endif
106	/** Enables access to even callee saved registers. */
107	//# define IEMNATIVE_WITH_SIMD_REG_ACCESS_ALL_REGISTERS
108
109	#if defined(DOXYGEN_RUNNING) \|\| 1
110	/** @def IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
111	* Delay the writeback or dirty registers as long as possible. */
112	# define IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
113	#endif
114
115	/** @def VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
116	* Enables a quicker alternative to throw/longjmp for IEM_DO_LONGJMP when
117	* executing native translation blocks.
118	*
119	* This exploits the fact that we save all non-volatile registers in the TB
120	* prologue and thus just need to do the same as the TB epilogue to get the
121	* effect of a longjmp/throw. Since MSC marks XMM6 thru XMM15 as
122	* non-volatile (and does something even more crazy for ARM), this probably
123	* won't work reliably on Windows. */
124	#ifdef RT_ARCH_ARM64
125	# ifndef RT_OS_WINDOWS
126	# define VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
127	# endif
128	#endif
129	/* ASM-NOINC-START */
130	#ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
131	# if !defined(IN_RING3) \
132	\|\| !defined(VBOX_WITH_IEM_RECOMPILER) \
133	\|\| !defined(VBOX_WITH_IEM_NATIVE_RECOMPILER)
134	# undef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
135	# elif defined(RT_OS_WINDOWS)
136	# pragma message("VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP is not safe to use on windows")
137	# endif
138	#endif
139
140
141	/** @def IEM_DO_LONGJMP
142	*
143	* Wrapper around longjmp / throw.
144	*
145	* @param a_pVCpu The CPU handle.
146	* @param a_rc The status code jump back with / throw.
147	*/
148	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
149	# ifdef IEM_WITH_THROW_CATCH
150	# ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
151	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) do { \
152	if ((a_pVCpu)->iem.s.pvTbFramePointerR3) \
153	iemNativeTbLongJmp((a_pVCpu)->iem.s.pvTbFramePointerR3, (a_rc)); \
154	throw int(a_rc); \
155	} while (0)
156	# else
157	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) throw int(a_rc)
158	# endif
159	# else
160	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) longjmp(*(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf), (a_rc))
161	# endif
162	#endif
163
164	/** For use with IEM function that may do a longjmp (when enabled).
165	*
166	* Visual C++ has trouble longjmp'ing from/over functions with the noexcept
167	* attribute. So, we indicate that function that may be part of a longjmp may
168	* throw "exceptions" and that the compiler should definitely not generate and
169	* std::terminate calling unwind code.
170	*
171	* Here is one example of this ending in std::terminate:
172	* @code{.txt}
173	00 00000041`cadfda10 00007ffc`5d5a1f9f ucrtbase!abort+0x4e
174	01 00000041`cadfda40 00007ffc`57af229a ucrtbase!terminate+0x1f
175	02 00000041`cadfda70 00007ffb`eec91030 VCRUNTIME140!__std_terminate+0xa [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\ehhelpers.cpp @ 192]
176	03 00000041`cadfdaa0 00007ffb`eec92c6d VCRUNTIME140_1!_CallSettingFrame+0x20 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\handlers.asm @ 50]
177	04 00000041`cadfdad0 00007ffb`eec93ae5 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToState+0x241 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 1085]
178	05 00000041`cadfdc00 00007ffb`eec92258 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToEmptyState+0x2d [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 218]
179	06 00000041`cadfdc30 00007ffb`eec940e9 VCRUNTIME140_1!__InternalCxxFrameHandler<__FrameHandler4>+0x194 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 304]
180	07 00000041`cadfdcd0 00007ffc`5f9f249f VCRUNTIME140_1!__CxxFrameHandler4+0xa9 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 290]
181	08 00000041`cadfdd40 00007ffc`5f980939 ntdll!RtlpExecuteHandlerForUnwind+0xf
182	09 00000041`cadfdd70 00007ffc`5f9a0edd ntdll!RtlUnwindEx+0x339
183	0a 00000041`cadfe490 00007ffc`57aff976 ntdll!RtlUnwind+0xcd
184	0b 00000041`cadfea00 00007ffb`e1b5de01 VCRUNTIME140!__longjmp_internal+0xe6 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\longjmp.asm @ 140]
185	0c (Inline Function) --------`-------- VBoxVMM!iemOpcodeGetNextU8SlowJmp+0x95 [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 1155]
186	0d 00000041`cadfea50 00007ffb`e1b60f6b VBoxVMM!iemOpcodeGetNextU8Jmp+0xc1 [L:\vbox-intern\src\VBox\VMM\include\IEMInline.h @ 402]
187	0e 00000041`cadfea90 00007ffb`e1cc6201 VBoxVMM!IEMExecForExits+0xdb [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 10185]
188	0f 00000041`cadfec70 00007ffb`e1d0df8d VBoxVMM!EMHistoryExec+0x4f1 [L:\vbox-intern\src\VBox\VMM\VMMAll\EMAll.cpp @ 452]
189	10 00000041`cadfed60 00007ffb`e1d0d4c0 VBoxVMM!nemR3WinHandleExitCpuId+0x79d [L:\vbox-intern\src\VBox\VMM\VMMAll\NEMAllNativeTemplate-win.cpp.h @ 1829] @encode
190	@endcode
191	*
192	* @see https://developercommunity.visualstudio.com/t/fragile-behavior-of-longjmp-called-from-noexcept-f/1532859
193	*/
194	#if defined(IEM_WITH_SETJMP) && (defined(_MSC_VER) \|\| defined(IEM_WITH_THROW_CATCH))
195	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT_EX(false)
196	#else
197	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT
198	#endif
199	/* ASM-NOINC-END */
200
201	#define IEM_IMPLEMENTS_TASKSWITCH
202
203	/** @def IEM_WITH_3DNOW
204	* Includes the 3DNow decoding. */
205	#if !defined(IEM_WITH_3DNOW) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
206	# ifndef IEM_WITHOUT_3DNOW
207	# define IEM_WITH_3DNOW
208	# endif
209	#endif
210
211	/** @def IEM_WITH_THREE_0F_38
212	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
213	#if !defined(IEM_WITH_THREE_0F_38) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
214	# ifdef IEM_WITHOUT_THREE_0F_38
215	# define IEM_WITH_THREE_0F_38
216	# endif
217	#endif
218
219	/** @def IEM_WITH_THREE_0F_3A
220	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
221	#if !defined(IEM_WITH_THREE_0F_3A) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
222	# ifndef IEM_WITHOUT_THREE_0F_3A
223	# define IEM_WITH_THREE_0F_3A
224	# endif
225	#endif
226
227	/** @def IEM_WITH_VEX
228	* Includes the VEX decoding. */
229	#if !defined(IEM_WITH_VEX) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
230	# ifndef IEM_WITHOUT_VEX
231	# define IEM_WITH_VEX
232	# endif
233	#endif
234
235	/** @def IEM_CFG_TARGET_CPU
236	* The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
237	*
238	* By default we allow this to be configured by the user via the
239	* CPUM/GuestCpuName config string, but this comes at a slight cost during
240	* decoding. So, for applications of this code where there is no need to
241	* be dynamic wrt target CPU, just modify this define.
242	*/
243	#if !defined(IEM_CFG_TARGET_CPU) \|\| defined(DOXYGEN_RUNNING)
244	# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
245	#endif
246
247	//#define IEM_WITH_CODE_TLB // - work in progress
248	//#define IEM_WITH_DATA_TLB // - work in progress
249
250
251	/** @def IEM_USE_UNALIGNED_DATA_ACCESS
252	* Use unaligned accesses instead of elaborate byte assembly. */
253	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86) \|\| defined(DOXYGEN_RUNNING) /ASM-NOINC/
254	# define IEM_USE_UNALIGNED_DATA_ACCESS
255	#endif /ASM-NOINC/
256
257	//#define IEM_LOG_MEMORY_WRITES
258
259
260
261	#ifndef RT_IN_ASSEMBLER /* ASM-NOINC-START - the rest of the file */
262
263	# if !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
264	/** Instruction statistics. */
265	typedef struct IEMINSTRSTATS
266	{
267	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
268	# include "IEMInstructionStatisticsTmpl.h"
269	# undef IEM_DO_INSTR_STAT
270	} IEMINSTRSTATS;
271	#else
272	struct IEMINSTRSTATS;
273	typedef struct IEMINSTRSTATS IEMINSTRSTATS;
274	#endif
275	/** Pointer to IEM instruction statistics. */
276	typedef IEMINSTRSTATS *PIEMINSTRSTATS;
277
278
279	/** @name IEMTARGETCPU_EFL_BEHAVIOR_XXX - IEMCPU::aidxTargetCpuEflFlavour
280	* @{ */
281	#define IEMTARGETCPU_EFL_BEHAVIOR_NATIVE 0 /*< Native x86 EFLAGS result; Intel EFLAGS when on non-x86 hosts. /
282	#define IEMTARGETCPU_EFL_BEHAVIOR_INTEL 1 /*< Intel EFLAGS result. /
283	#define IEMTARGETCPU_EFL_BEHAVIOR_AMD 2 /*< AMD EFLAGS result /
284	#define IEMTARGETCPU_EFL_BEHAVIOR_RESERVED 3 /*< Reserved/dummy entry slot that's the same as 0. /
285	#define IEMTARGETCPU_EFL_BEHAVIOR_MASK 3 /*< For masking the index before use. /
286	/** Selects the right variant from a_aArray.
287	* pVCpu is implicit in the caller context. */
288	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT(a_aArray) \
289	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[1] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
290	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for when no native worker can
291	* be used because the host CPU does not support the operation. */
292	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_NON_NATIVE(a_aArray) \
293	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
294	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for a two dimentional
295	* array paralleling IEMCPU::aidxTargetCpuEflFlavour and a single bit index
296	* into the two.
297	* @sa IEM_SELECT_NATIVE_OR_FALLBACK */
298	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
299	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
300	(a_aaArray[a_fNative][pVCpu->iem.s.aidxTargetCpuEflFlavour[a_fNative] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
301	#else
302	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
303	(a_aaArray[0][pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
304	#endif
305	/** @} */
306
307	/**
308	* Picks @a a_pfnNative or @a a_pfnFallback according to the host CPU feature
309	* indicator given by @a a_fCpumFeatureMember (CPUMFEATURES member).
310	*
311	* On non-x86 hosts, this will shortcut to the fallback w/o checking the
312	* indicator.
313	*
314	* @sa IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX
315	*/
316	#if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
317	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) \
318	(g_CpumHostFeatures.s.a_fCpumFeatureMember ? a_pfnNative : a_pfnFallback)
319	#else
320	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) (a_pfnFallback)
321	#endif
322
323
324	/**
325	* Extended operand mode that includes a representation of 8-bit.
326	*
327	* This is used for packing down modes when invoking some C instruction
328	* implementations.
329	*/
330	typedef enum IEMMODEX
331	{
332	IEMMODEX_16BIT = IEMMODE_16BIT,
333	IEMMODEX_32BIT = IEMMODE_32BIT,
334	IEMMODEX_64BIT = IEMMODE_64BIT,
335	IEMMODEX_8BIT
336	} IEMMODEX;
337	AssertCompileSize(IEMMODEX, 4);
338
339
340	/**
341	* Branch types.
342	*/
343	typedef enum IEMBRANCH
344	{
345	IEMBRANCH_JUMP = 1,
346	IEMBRANCH_CALL,
347	IEMBRANCH_TRAP,
348	IEMBRANCH_SOFTWARE_INT,
349	IEMBRANCH_HARDWARE_INT
350	} IEMBRANCH;
351	AssertCompileSize(IEMBRANCH, 4);
352
353
354	/**
355	* INT instruction types.
356	*/
357	typedef enum IEMINT
358	{
359	/** INT n instruction (opcode 0xcd imm). */
360	IEMINT_INTN = 0,
361	/** Single byte INT3 instruction (opcode 0xcc). */
362	IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
363	/** Single byte INTO instruction (opcode 0xce). */
364	IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
365	/** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
366	IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
367	} IEMINT;
368	AssertCompileSize(IEMINT, 4);
369
370
371	/**
372	* A FPU result.
373	*/
374	typedef struct IEMFPURESULT
375	{
376	/** The output value. */
377	RTFLOAT80U r80Result;
378	/** The output status. */
379	uint16_t FSW;
380	} IEMFPURESULT;
381	AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
382	/** Pointer to a FPU result. */
383	typedef IEMFPURESULT *PIEMFPURESULT;
384	/** Pointer to a const FPU result. */
385	typedef IEMFPURESULT const *PCIEMFPURESULT;
386
387
388	/**
389	* A FPU result consisting of two output values and FSW.
390	*/
391	typedef struct IEMFPURESULTTWO
392	{
393	/** The first output value. */
394	RTFLOAT80U r80Result1;
395	/** The output status. */
396	uint16_t FSW;
397	/** The second output value. */
398	RTFLOAT80U r80Result2;
399	} IEMFPURESULTTWO;
400	AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
401	AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
402	/** Pointer to a FPU result consisting of two output values and FSW. */
403	typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
404	/** Pointer to a const FPU result consisting of two output values and FSW. */
405	typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
406
407
408	/**
409	* IEM TLB entry.
410	*
411	* Lookup assembly:
412	* @code{.asm}
413	; Calculate tag.
414	mov rax, [VA]
415	shl rax, 16
416	shr rax, 16 + X86_PAGE_SHIFT
417	or rax, [uTlbRevision]
418
419	; Do indexing.
420	movzx ecx, al
421	lea rcx, [pTlbEntries + rcx]
422
423	; Check tag.
424	cmp [rcx + IEMTLBENTRY.uTag], rax
425	jne .TlbMiss
426
427	; Check access.
428	mov rax, ACCESS_FLAGS \| MAPPING_R3_NOT_VALID \| 0xffffff00
429	and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
430	cmp rax, [uTlbPhysRev]
431	jne .TlbMiss
432
433	; Calc address and we're done.
434	mov eax, X86_PAGE_OFFSET_MASK
435	and eax, [VA]
436	or rax, [rcx + IEMTLBENTRY.pMappingR3]
437	%ifdef VBOX_WITH_STATISTICS
438	inc qword [cTlbHits]
439	%endif
440	jmp .Done
441
442	.TlbMiss:
443	mov r8d, ACCESS_FLAGS
444	mov rdx, [VA]
445	mov rcx, [pVCpu]
446	call iemTlbTypeMiss
447	.Done:
448
449	@endcode
450	*
451	*/
452	typedef struct IEMTLBENTRY
453	{
454	/** The TLB entry tag.
455	* Bits 35 thru 0 are made up of the virtual address shifted right 12 bits, this
456	* is ASSUMING a virtual address width of 48 bits.
457	*
458	* Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
459	*
460	* The TLB lookup code uses the current TLB revision, which won't ever be zero,
461	* enabling an extremely cheap TLB invalidation most of the time. When the TLB
462	* revision wraps around though, the tags needs to be zeroed.
463	*
464	* @note Try use SHRD instruction? After seeing
465	* https://gmplib.org/~tege/x86-timing.pdf, maybe not.
466	*
467	* @todo This will need to be reorganized for 57-bit wide virtual address and
468	* PCID (currently 12 bits) and ASID (currently 6 bits) support. We'll
469	* have to move the TLB entry versioning entirely to the
470	* fFlagsAndPhysRev member then, 57 bit wide VAs means we'll only have
471	* 19 bits left (64 - 57 + 12 = 19) and they'll almost entire be
472	* consumed by PCID and ASID (12 + 6 = 18).
473	*/
474	uint64_t uTag;
475	/** Access flags and physical TLB revision.
476	*
477	* - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
478	* - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
479	* - Bit 2 - page tables - not user (complemented X86_PTE_US).
480	* - Bit 3 - pgm phys/virt - not directly writable.
481	* - Bit 4 - pgm phys page - not directly readable.
482	* - Bit 5 - page tables - not accessed (complemented X86_PTE_A).
483	* - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
484	* - Bit 7 - tlb entry - pMappingR3 member not valid.
485	* - Bits 63 thru 8 are used for the physical TLB revision number.
486	*
487	* We're using complemented bit meanings here because it makes it easy to check
488	* whether special action is required. For instance a user mode write access
489	* would do a "TEST fFlags, (X86_PTE_RW \| X86_PTE_US \| X86_PTE_D)" and a
490	* non-zero result would mean special handling needed because either it wasn't
491	* writable, or it wasn't user, or the page wasn't dirty. A user mode read
492	* access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
493	* need to check any PTE flag.
494	*/
495	uint64_t fFlagsAndPhysRev;
496	/** The guest physical page address. */
497	uint64_t GCPhys;
498	/** Pointer to the ring-3 mapping. */
499	R3PTRTYPE(uint8_t *) pbMappingR3;
500	#if HC_ARCH_BITS == 32
501	uint32_t u32Padding1;
502	#endif
503	} IEMTLBENTRY;
504	AssertCompileSize(IEMTLBENTRY, 32);
505	/** Pointer to an IEM TLB entry. */
506	typedef IEMTLBENTRY *PIEMTLBENTRY;
507
508	/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
509	* @{ */
510	#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /*< Page tables: Not executable. /
511	#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /*< Page tables: Not writable. /
512	#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /*< Page tables: Not user accessible (supervisor only). /
513	#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /*< Phys page: Not writable (access handler, ROM, whatever). /
514	#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /*< Phys page: Not readable (MMIO / access handler, ROM) /
515	#define IEMTLBE_F_PT_NO_ACCESSED RT_BIT_64(5) /*< Phys tables: Not accessed (need to be marked accessed). /
516	#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /*< Page tables: Not dirty (needs to be made dirty on write). /
517	#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(7) /*< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. /
518	#define IEMTLBE_F_PG_UNASSIGNED RT_BIT_64(8) /*< Phys page: Unassigned memory (not RAM, ROM, MMIO2 or MMIO). /
519	#define IEMTLBE_F_PG_CODE_PAGE RT_BIT_64(9) /*< Phys page: Code page. /
520	#define IEMTLBE_F_PHYS_REV UINT64_C(0xfffffffffffffc00) /*< Physical revision mask. @sa IEMTLB_PHYS_REV_INCR /
521	/** @} */
522
523
524	/**
525	* An IEM TLB.
526	*
527	* We've got two of these, one for data and one for instructions.
528	*/
529	typedef struct IEMTLB
530	{
531	/** The TLB revision.
532	* This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
533	* by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
534	* the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
535	* (The revision zero indicates an invalid TLB entry.)
536	*
537	* The initial value is choosen to cause an early wraparound. */
538	uint64_t uTlbRevision;
539	/** The TLB physical address revision - shadow of PGM variable.
540	*
541	* This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
542	* incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
543	* a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
544	* as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
545	*
546	* The initial value is choosen to cause an early wraparound. */
547	uint64_t volatile uTlbPhysRev;
548
549	/* Statistics: */
550
551	/** TLB hits (VBOX_WITH_STATISTICS only). */
552	uint64_t cTlbHits;
553	/** TLB misses. */
554	uint32_t cTlbMisses;
555	/** Slow read path. */
556	uint32_t cTlbSlowReadPath;
557	/** Safe read path. */
558	uint32_t cTlbSafeReadPath;
559	/** Safe write path. */
560	uint32_t cTlbSafeWritePath;
561	#if 0
562	/** TLB misses because of tag mismatch. */
563	uint32_t cTlbMissesTag;
564	/** TLB misses because of virtual access violation. */
565	uint32_t cTlbMissesVirtAccess;
566	/** TLB misses because of dirty bit. */
567	uint32_t cTlbMissesDirty;
568	/** TLB misses because of MMIO */
569	uint32_t cTlbMissesMmio;
570	/** TLB misses because of write access handlers. */
571	uint32_t cTlbMissesWriteHandler;
572	/** TLB misses because no r3(/r0) mapping. */
573	uint32_t cTlbMissesMapping;
574	#endif
575	/** Alignment padding. */
576	uint32_t au32Padding[6];
577
578	/** The TLB entries.
579	* We've choosen 256 because that way we can obtain the result directly from a
580	* 8-bit register without an additional AND instruction. */
581	IEMTLBENTRY aEntries[256];
582	} IEMTLB;
583	AssertCompileSizeAlignment(IEMTLB, 64);
584	/** IEMTLB::uTlbRevision increment. */
585	#define IEMTLB_REVISION_INCR RT_BIT_64(36)
586	/** IEMTLB::uTlbRevision mask. */
587	#define IEMTLB_REVISION_MASK (~(RT_BIT_64(36) - 1))
588	/** IEMTLB::uTlbPhysRev increment.
589	* @sa IEMTLBE_F_PHYS_REV */
590	#define IEMTLB_PHYS_REV_INCR RT_BIT_64(10)
591	/**
592	* Calculates the TLB tag for a virtual address.
593	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
594	* @param a_pTlb The TLB.
595	* @param a_GCPtr The virtual address. Must be RTGCPTR or same size or
596	* the clearing of the top 16 bits won't work (if 32-bit
597	* we'll end up with mostly zeros).
598	*/
599	#define IEMTLB_CALC_TAG(a_pTlb, a_GCPtr) ( IEMTLB_CALC_TAG_NO_REV(a_GCPtr) \| (a_pTlb)->uTlbRevision )
600	/**
601	* Calculates the TLB tag for a virtual address but without TLB revision.
602	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
603	* @param a_GCPtr The virtual address. Must be RTGCPTR or same size or
604	* the clearing of the top 16 bits won't work (if 32-bit
605	* we'll end up with mostly zeros).
606	*/
607	#define IEMTLB_CALC_TAG_NO_REV(a_GCPtr) ( (((a_GCPtr) << 16) >> (GUEST_PAGE_SHIFT + 16)) )
608	/**
609	* Converts a TLB tag value into a TLB index.
610	* @returns Index into IEMTLB::aEntries.
611	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
612	*/
613	#define IEMTLB_TAG_TO_INDEX(a_uTag) ( (uint8_t)(a_uTag) )
614	/**
615	* Converts a TLB tag value into a TLB index.
616	* @returns Index into IEMTLB::aEntries.
617	* @param a_pTlb The TLB.
618	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
619	*/
620	#define IEMTLB_TAG_TO_ENTRY(a_pTlb, a_uTag) ( &(a_pTlb)->aEntries[IEMTLB_TAG_TO_INDEX(a_uTag)] )
621
622
623	/** @name IEM_MC_F_XXX - MC block flags/clues.
624	* @todo Merge with IEM_CIMPL_F_XXX
625	* @{ */
626	#define IEM_MC_F_ONLY_8086 RT_BIT_32(0)
627	#define IEM_MC_F_MIN_186 RT_BIT_32(1)
628	#define IEM_MC_F_MIN_286 RT_BIT_32(2)
629	#define IEM_MC_F_NOT_286_OR_OLDER IEM_MC_F_MIN_386
630	#define IEM_MC_F_MIN_386 RT_BIT_32(3)
631	#define IEM_MC_F_MIN_486 RT_BIT_32(4)
632	#define IEM_MC_F_MIN_PENTIUM RT_BIT_32(5)
633	#define IEM_MC_F_MIN_PENTIUM_II IEM_MC_F_MIN_PENTIUM
634	#define IEM_MC_F_MIN_CORE IEM_MC_F_MIN_PENTIUM
635	#define IEM_MC_F_64BIT RT_BIT_32(6)
636	#define IEM_MC_F_NOT_64BIT RT_BIT_32(7)
637	/** This is set by IEMAllN8vePython.py to indicate a variation without the
638	* flags-clearing-and-checking, when there is also a variation with that.
639	* @note Do not use this manully, it's only for python and for testing in
640	* the native recompiler! */
641	#define IEM_MC_F_WITHOUT_FLAGS RT_BIT_32(8)
642	/** @} */
643
644	/** @name IEM_CIMPL_F_XXX - State change clues for CIMPL calls.
645	*
646	* These clues are mainly for the recompiler, so that it can emit correct code.
647	*
648	* They are processed by the python script and which also automatically
649	* calculates flags for MC blocks based on the statements, extending the use of
650	* these flags to describe MC block behavior to the recompiler core. The python
651	* script pass the flags to the IEM_MC2_END_EMIT_CALLS macro, but mainly for
652	* error checking purposes. The script emits the necessary fEndTb = true and
653	* similar statements as this reduces compile time a tiny bit.
654	*
655	* @{ */
656	/** Flag set if direct branch, clear if absolute or indirect. */
657	#define IEM_CIMPL_F_BRANCH_DIRECT RT_BIT_32(0)
658	/** Flag set if indirect branch, clear if direct or relative.
659	* This is also used for all system control transfers (SYSCALL, SYSRET, INT, ++)
660	* as well as for return instructions (RET, IRET, RETF). */
661	#define IEM_CIMPL_F_BRANCH_INDIRECT RT_BIT_32(1)
662	/** Flag set if relative branch, clear if absolute or indirect. */
663	#define IEM_CIMPL_F_BRANCH_RELATIVE RT_BIT_32(2)
664	/** Flag set if conditional branch, clear if unconditional. */
665	#define IEM_CIMPL_F_BRANCH_CONDITIONAL RT_BIT_32(3)
666	/** Flag set if it's a far branch (changes CS). */
667	#define IEM_CIMPL_F_BRANCH_FAR RT_BIT_32(4)
668	/** Convenience: Testing any kind of branch. */
669	#define IEM_CIMPL_F_BRANCH_ANY (IEM_CIMPL_F_BRANCH_DIRECT \| IEM_CIMPL_F_BRANCH_INDIRECT \| IEM_CIMPL_F_BRANCH_RELATIVE)
670
671	/** Execution flags may change (IEMCPU::fExec). */
672	#define IEM_CIMPL_F_MODE RT_BIT_32(5)
673	/** May change significant portions of RFLAGS. */
674	#define IEM_CIMPL_F_RFLAGS RT_BIT_32(6)
675	/** May change the status bits (X86_EFL_STATUS_BITS) in RFLAGS. */
676	#define IEM_CIMPL_F_STATUS_FLAGS RT_BIT_32(7)
677	/** May trigger interrupt shadowing. */
678	#define IEM_CIMPL_F_INHIBIT_SHADOW RT_BIT_32(8)
679	/** May enable interrupts, so recheck IRQ immediately afterwards executing
680	* the instruction. */
681	#define IEM_CIMPL_F_CHECK_IRQ_AFTER RT_BIT_32(9)
682	/** May disable interrupts, so recheck IRQ immediately before executing the
683	* instruction. */
684	#define IEM_CIMPL_F_CHECK_IRQ_BEFORE RT_BIT_32(10)
685	/** Convenience: Check for IRQ both before and after an instruction. */
686	#define IEM_CIMPL_F_CHECK_IRQ_BEFORE_AND_AFTER (IEM_CIMPL_F_CHECK_IRQ_BEFORE \| IEM_CIMPL_F_CHECK_IRQ_AFTER)
687	/** May trigger a VM exit (treated like IEM_CIMPL_F_MODE atm). */
688	#define IEM_CIMPL_F_VMEXIT RT_BIT_32(11)
689	/** May modify FPU state.
690	* @todo Not sure if this is useful yet. */
691	#define IEM_CIMPL_F_FPU RT_BIT_32(12)
692	/** REP prefixed instruction which may yield before updating PC.
693	* @todo Not sure if this is useful, REP functions now return non-zero
694	* status if they don't update the PC. */
695	#define IEM_CIMPL_F_REP RT_BIT_32(13)
696	/** I/O instruction.
697	* @todo Not sure if this is useful yet. */
698	#define IEM_CIMPL_F_IO RT_BIT_32(14)
699	/** Force end of TB after the instruction. */
700	#define IEM_CIMPL_F_END_TB RT_BIT_32(15)
701	/** Flag set if a branch may also modify the stack (push/pop return address). */
702	#define IEM_CIMPL_F_BRANCH_STACK RT_BIT_32(16)
703	/** Flag set if a branch may also modify the stack (push/pop return address)
704	* and switch it (load/restore SS:RSP). */
705	#define IEM_CIMPL_F_BRANCH_STACK_FAR RT_BIT_32(17)
706	/** Convenience: Raise exception (technically unnecessary, since it shouldn't return VINF_SUCCESS). */
707	#define IEM_CIMPL_F_XCPT \
708	(IEM_CIMPL_F_BRANCH_INDIRECT \| IEM_CIMPL_F_BRANCH_FAR \| IEM_CIMPL_F_BRANCH_STACK_FAR \
709	\| IEM_CIMPL_F_MODE \| IEM_CIMPL_F_RFLAGS \| IEM_CIMPL_F_VMEXIT)
710
711	/** The block calls a C-implementation instruction function with two implicit arguments.
712	* Mutually exclusive with IEM_CIMPL_F_CALLS_AIMPL and
713	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
714	* @note The python scripts will add this if missing. */
715	#define IEM_CIMPL_F_CALLS_CIMPL RT_BIT_32(18)
716	/** The block calls an ASM-implementation instruction function.
717	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL and
718	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
719	* @note The python scripts will add this if missing. */
720	#define IEM_CIMPL_F_CALLS_AIMPL RT_BIT_32(19)
721	/** The block calls an ASM-implementation instruction function with an implicit
722	* X86FXSTATE pointer argument.
723	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL, IEM_CIMPL_F_CALLS_AIMPL and
724	* IEM_CIMPL_F_CALLS_AIMPL_WITH_XSTATE.
725	* @note The python scripts will add this if missing. */
726	#define IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE RT_BIT_32(20)
727	/** The block calls an ASM-implementation instruction function with an implicit
728	* X86XSAVEAREA pointer argument.
729	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL, IEM_CIMPL_F_CALLS_AIMPL and
730	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
731	* @note No different from IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE, so same value.
732	* @note The python scripts will add this if missing. */
733	#define IEM_CIMPL_F_CALLS_AIMPL_WITH_XSTATE IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE
734	/** @} */
735
736
737	/** @name IEM_F_XXX - Execution mode flags (IEMCPU::fExec, IEMTB::fFlags).
738	*
739	* These flags are set when entering IEM and adjusted as code is executed, such
740	* that they will always contain the current values as instructions are
741	* finished.
742	*
743	* In recompiled execution mode, (most of) these flags are included in the
744	* translation block selection key and stored in IEMTB::fFlags alongside the
745	* IEMTB_F_XXX flags. The latter flags uses bits 31 thru 24, which are all zero
746	* in IEMCPU::fExec.
747	*
748	* @{ */
749	/** Mode: The block target mode mask. */
750	#define IEM_F_MODE_MASK UINT32_C(0x0000001f)
751	/** Mode: The IEMMODE part of the IEMTB_F_MODE_MASK value. */
752	#define IEM_F_MODE_CPUMODE_MASK UINT32_C(0x00000003)
753	/** X86 Mode: Bit used to indicating pre-386 CPU in 16-bit mode (for eliminating
754	* conditional in EIP/IP updating), and flat wide open CS, SS, DS, and ES in
755	* 32-bit mode (for simplifying most memory accesses). */
756	#define IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK UINT32_C(0x00000004)
757	/** X86 Mode: Bit indicating protected mode, real mode (or SMM) when not set. */
758	#define IEM_F_MODE_X86_PROT_MASK UINT32_C(0x00000008)
759	/** X86 Mode: Bit used to indicate virtual 8086 mode (only 16-bit). */
760	#define IEM_F_MODE_X86_V86_MASK UINT32_C(0x00000010)
761
762	/** X86 Mode: 16-bit on 386 or later. */
763	#define IEM_F_MODE_X86_16BIT UINT32_C(0x00000000)
764	/** X86 Mode: 80286, 80186 and 8086/88 targetting blocks (EIP update opt). */
765	#define IEM_F_MODE_X86_16BIT_PRE_386 UINT32_C(0x00000004)
766	/** X86 Mode: 16-bit protected mode on 386 or later. */
767	#define IEM_F_MODE_X86_16BIT_PROT UINT32_C(0x00000008)
768	/** X86 Mode: 16-bit protected mode on 386 or later. */
769	#define IEM_F_MODE_X86_16BIT_PROT_PRE_386 UINT32_C(0x0000000c)
770	/** X86 Mode: 16-bit virtual 8086 protected mode (on 386 or later). */
771	#define IEM_F_MODE_X86_16BIT_PROT_V86 UINT32_C(0x00000018)
772
773	/** X86 Mode: 32-bit on 386 or later. */
774	#define IEM_F_MODE_X86_32BIT UINT32_C(0x00000001)
775	/** X86 Mode: 32-bit mode with wide open flat CS, SS, DS and ES. */
776	#define IEM_F_MODE_X86_32BIT_FLAT UINT32_C(0x00000005)
777	/** X86 Mode: 32-bit protected mode. */
778	#define IEM_F_MODE_X86_32BIT_PROT UINT32_C(0x00000009)
779	/** X86 Mode: 32-bit protected mode with wide open flat CS, SS, DS and ES. */
780	#define IEM_F_MODE_X86_32BIT_PROT_FLAT UINT32_C(0x0000000d)
781
782	/** X86 Mode: 64-bit (includes protected, but not the flat bit). */
783	#define IEM_F_MODE_X86_64BIT UINT32_C(0x0000000a)
784
785	/** X86 Mode: Checks if @a a_fExec represent a FLAT mode. */
786	#define IEM_F_MODE_X86_IS_FLAT(a_fExec) ( ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_64BIT \
787	\|\| ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_32BIT_PROT_FLAT \
788	\|\| ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_32BIT_FLAT)
789
790	/** Bypass access handlers when set. */
791	#define IEM_F_BYPASS_HANDLERS UINT32_C(0x00010000)
792	/** Have pending hardware instruction breakpoints. */
793	#define IEM_F_PENDING_BRK_INSTR UINT32_C(0x00020000)
794	/** Have pending hardware data breakpoints. */
795	#define IEM_F_PENDING_BRK_DATA UINT32_C(0x00040000)
796
797	/** X86: Have pending hardware I/O breakpoints. */
798	#define IEM_F_PENDING_BRK_X86_IO UINT32_C(0x00000400)
799	/** X86: Disregard the lock prefix (implied or not) when set. */
800	#define IEM_F_X86_DISREGARD_LOCK UINT32_C(0x00000800)
801
802	/** Pending breakpoint mask (what iemCalcExecDbgFlags works out). */
803	#define IEM_F_PENDING_BRK_MASK (IEM_F_PENDING_BRK_INSTR \| IEM_F_PENDING_BRK_DATA \| IEM_F_PENDING_BRK_X86_IO)
804
805	/** Caller configurable options. */
806	#define IEM_F_USER_OPTS (IEM_F_BYPASS_HANDLERS \| IEM_F_X86_DISREGARD_LOCK)
807
808	/** X86: The current protection level (CPL) shift factor. */
809	#define IEM_F_X86_CPL_SHIFT 8
810	/** X86: The current protection level (CPL) mask. */
811	#define IEM_F_X86_CPL_MASK UINT32_C(0x00000300)
812	/** X86: The current protection level (CPL) shifted mask. */
813	#define IEM_F_X86_CPL_SMASK UINT32_C(0x00000003)
814
815	/** X86 execution context.
816	* The IEM_F_X86_CTX_XXX values are individual flags that can be combined (with
817	* the exception of IEM_F_X86_CTX_NORMAL). This allows running VMs from SMM
818	* mode. */
819	#define IEM_F_X86_CTX_MASK UINT32_C(0x0000f000)
820	/** X86 context: Plain regular execution context. */
821	#define IEM_F_X86_CTX_NORMAL UINT32_C(0x00000000)
822	/** X86 context: VT-x enabled. */
823	#define IEM_F_X86_CTX_VMX UINT32_C(0x00001000)
824	/** X86 context: AMD-V enabled. */
825	#define IEM_F_X86_CTX_SVM UINT32_C(0x00002000)
826	/** X86 context: In AMD-V or VT-x guest mode. */
827	#define IEM_F_X86_CTX_IN_GUEST UINT32_C(0x00004000)
828	/** X86 context: System management mode (SMM). */
829	#define IEM_F_X86_CTX_SMM UINT32_C(0x00008000)
830
831	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
832	* iemRegFinishClearingRF() most for most situations (CPUMCTX_DBG_HIT_DRX_MASK
833	* and CPUMCTX_DBG_DBGF_MASK are covered by the IEM_F_PENDING_BRK_XXX bits
834	* alread). */
835
836	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
837	* iemRegFinishClearingRF() most for most situations
838	* (CPUMCTX_DBG_HIT_DRX_MASK and CPUMCTX_DBG_DBGF_MASK are covered by
839	* the IEM_F_PENDING_BRK_XXX bits alread). */
840
841	/** @} */
842
843
844	/** @name IEMTB_F_XXX - Translation block flags (IEMTB::fFlags).
845	*
846	* Extends the IEM_F_XXX flags (subject to IEMTB_F_IEM_F_MASK) to make up the
847	* translation block flags. The combined flag mask (subject to
848	* IEMTB_F_KEY_MASK) is used as part of the lookup key for translation blocks.
849	*
850	* @{ */
851	/** Mask of IEM_F_XXX flags included in IEMTB_F_XXX. */
852	#define IEMTB_F_IEM_F_MASK UINT32_C(0x00ffffff)
853
854	/** Type: The block type mask. */
855	#define IEMTB_F_TYPE_MASK UINT32_C(0x03000000)
856	/** Type: Purly threaded recompiler (via tables). */
857	#define IEMTB_F_TYPE_THREADED UINT32_C(0x01000000)
858	/** Type: Native recompilation. */
859	#define IEMTB_F_TYPE_NATIVE UINT32_C(0x02000000)
860
861	/** Set when we're starting the block in an "interrupt shadow".
862	* We don't need to distingish between the two types of this mask, thus the one.
863	* @see CPUMCTX_INHIBIT_SHADOW, CPUMIsInInterruptShadow() */
864	#define IEMTB_F_INHIBIT_SHADOW UINT32_C(0x04000000)
865	/** Set when we're currently inhibiting NMIs
866	* @see CPUMCTX_INHIBIT_NMI, CPUMAreInterruptsInhibitedByNmi() */
867	#define IEMTB_F_INHIBIT_NMI UINT32_C(0x08000000)
868
869	/** Checks that EIP/IP is wihin CS.LIM before each instruction. Used when
870	* we're close the limit before starting a TB, as determined by
871	* iemGetTbFlagsForCurrentPc(). */
872	#define IEMTB_F_CS_LIM_CHECKS UINT32_C(0x10000000)
873
874	/** Mask of the IEMTB_F_XXX flags that are part of the TB lookup key.
875	*
876	* @note We skip all of IEM_F_X86_CTX_MASK, with the exception of SMM (which we
877	* don't implement), because we don't currently generate any context
878	* specific code - that's all handled in CIMPL functions.
879	*
880	* For the threaded recompiler we don't generate any CPL specific code
881	* either, but the native recompiler does for memory access (saves getting
882	* the CPL from fExec and turning it into IEMTLBE_F_PT_NO_USER).
883	* Since most OSes will not share code between rings, this shouldn't
884	* have any real effect on TB/memory/recompiling load.
885	*/
886	#define IEMTB_F_KEY_MASK ((UINT32_MAX & ~(IEM_F_X86_CTX_MASK \| IEMTB_F_TYPE_MASK)) \| IEM_F_X86_CTX_SMM)
887	/** @} */
888
889	AssertCompile( (IEM_F_MODE_X86_16BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
890	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
891	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_PROT_MASK));
892	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_V86_MASK));
893	AssertCompile( (IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
894	AssertCompile( IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
895	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_PROT_MASK));
896	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
897	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
898	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
899	AssertCompile( IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
900	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_V86_MASK));
901	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
902	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
903	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_PROT_MASK);
904	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
905	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_PROT_MASK);
906	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
907	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_V86_MASK);
908
909	AssertCompile( (IEM_F_MODE_X86_32BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
910	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
911	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_PROT_MASK));
912	AssertCompile( (IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
913	AssertCompile( IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
914	AssertCompile(!(IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_PROT_MASK));
915	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
916	AssertCompile(!(IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
917	AssertCompile( IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
918	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
919	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
920	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_PROT_MASK);
921
922	AssertCompile( (IEM_F_MODE_X86_64BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_64BIT);
923	AssertCompile( IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_PROT_MASK);
924	AssertCompile(!(IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
925
926	/** Native instruction type for use with the native code generator.
927	* This is a byte (uint8_t) for x86 and amd64 and uint32_t for the other(s). */
928	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
929	typedef uint8_t IEMNATIVEINSTR;
930	#else
931	typedef uint32_t IEMNATIVEINSTR;
932	#endif
933	/** Pointer to a native instruction unit. */
934	typedef IEMNATIVEINSTR *PIEMNATIVEINSTR;
935	/** Pointer to a const native instruction unit. */
936	typedef IEMNATIVEINSTR const *PCIEMNATIVEINSTR;
937
938	/**
939	* A call for the threaded call table.
940	*/
941	typedef struct IEMTHRDEDCALLENTRY
942	{
943	/** The function to call (IEMTHREADEDFUNCS). */
944	uint16_t enmFunction;
945
946	/** Instruction number in the TB (for statistics). */
947	uint8_t idxInstr;
948	/** The opcode length. */
949	uint8_t cbOpcode;
950	/** Offset into IEMTB::pabOpcodes. */
951	uint16_t offOpcode;
952
953	/** TB lookup table index (7 bits) and large size (1 bits).
954	*
955	* The default size is 1 entry, but for indirect calls and returns we set the
956	* top bit and allocate 4 (IEM_TB_LOOKUP_TAB_LARGE_SIZE) entries. The large
957	* tables uses RIP for selecting the entry to use, as it is assumed a hash table
958	* lookup isn't that slow compared to sequentially trying out 4 TBs.
959	*
960	* By default lookup table entry 0 for a TB is reserved as a fallback for
961	* calltable entries w/o explicit entreis, so this member will be non-zero if
962	* there is a lookup entry associated with this call.
963	*
964	* @sa IEM_TB_LOOKUP_TAB_GET_SIZE, IEM_TB_LOOKUP_TAB_GET_IDX
965	*/
966	uint8_t uTbLookup;
967
968	/** Unused atm. */
969	uint8_t uUnused0;
970
971	/** Generic parameters. */
972	uint64_t auParams[3];
973	} IEMTHRDEDCALLENTRY;
974	AssertCompileSize(IEMTHRDEDCALLENTRY, sizeof(uint64_t) * 4);
975	/** Pointer to a threaded call entry. */
976	typedef struct IEMTHRDEDCALLENTRY *PIEMTHRDEDCALLENTRY;
977	/** Pointer to a const threaded call entry. */
978	typedef IEMTHRDEDCALLENTRY const *PCIEMTHRDEDCALLENTRY;
979
980	/** The number of TB lookup table entries for a large allocation
981	* (IEMTHRDEDCALLENTRY::uTbLookup bit 7 set). */
982	#define IEM_TB_LOOKUP_TAB_LARGE_SIZE 4
983	/** Get the lookup table size from IEMTHRDEDCALLENTRY::uTbLookup. */
984	#define IEM_TB_LOOKUP_TAB_GET_SIZE(a_uTbLookup) (!((a_uTbLookup) & 0x80) ? 1 : IEM_TB_LOOKUP_TAB_LARGE_SIZE)
985	/** Get the first lookup table index from IEMTHRDEDCALLENTRY::uTbLookup. */
986	#define IEM_TB_LOOKUP_TAB_GET_IDX(a_uTbLookup) ((a_uTbLookup) & 0x7f)
987	/** Get the lookup table index from IEMTHRDEDCALLENTRY::uTbLookup and RIP. */
988	#define IEM_TB_LOOKUP_TAB_GET_IDX_WITH_RIP(a_uTbLookup, a_Rip) \
989	(!((a_uTbLookup) & 0x80) ? (a_uTbLookup) & 0x7f : ((a_uTbLookup) & 0x7f) + ((a_Rip) & (IEM_TB_LOOKUP_TAB_LARGE_SIZE - 1)) )
990
991	/** Make a IEMTHRDEDCALLENTRY::uTbLookup value. */
992	#define IEM_TB_LOOKUP_TAB_MAKE(a_idxTable, a_fLarge) ((a_idxTable) \| ((a_fLarge) ? 0x80 : 0))
993
994	/**
995	* Native IEM TB 'function' typedef.
996	*
997	* This will throw/longjmp on occation.
998	*
999	* @note AMD64 doesn't have that many non-volatile registers and does sport
1000	* 32-bit address displacments, so we don't need pCtx.
1001	*
1002	* On ARM64 pCtx allows us to directly address the whole register
1003	* context without requiring a separate indexing register holding the
1004	* offset. This saves an instruction loading the offset for each guest
1005	* CPU context access, at the cost of a non-volatile register.
1006	* Fortunately, ARM64 has quite a lot more registers.
1007	*/
1008	typedef
1009	#ifdef RT_ARCH_AMD64
1010	int FNIEMTBNATIVE(PVMCPUCC pVCpu)
1011	#else
1012	int FNIEMTBNATIVE(PVMCPUCC pVCpu, PCPUMCTX pCtx)
1013	#endif
1014	#if RT_CPLUSPLUS_PREREQ(201700)
1015	IEM_NOEXCEPT_MAY_LONGJMP
1016	#endif
1017	;
1018	/** Pointer to a native IEM TB entry point function.
1019	* This will throw/longjmp on occation. */
1020	typedef FNIEMTBNATIVE *PFNIEMTBNATIVE;
1021
1022
1023	/**
1024	* Translation block debug info entry type.
1025	*/
1026	typedef enum IEMTBDBGENTRYTYPE
1027	{
1028	kIemTbDbgEntryType_Invalid = 0,
1029	/** The entry is for marking a native code position.
1030	* Entries following this all apply to this position. */
1031	kIemTbDbgEntryType_NativeOffset,
1032	/** The entry is for a new guest instruction. */
1033	kIemTbDbgEntryType_GuestInstruction,
1034	/** Marks the start of a threaded call. */
1035	kIemTbDbgEntryType_ThreadedCall,
1036	/** Marks the location of a label. */
1037	kIemTbDbgEntryType_Label,
1038	/** Info about a host register shadowing a guest register. */
1039	kIemTbDbgEntryType_GuestRegShadowing,
1040	#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
1041	/** Info about a host SIMD register shadowing a guest SIMD register. */
1042	kIemTbDbgEntryType_GuestSimdRegShadowing,
1043	#endif
1044	#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING
1045	/** Info about a delayed RIP update. */
1046	kIemTbDbgEntryType_DelayedPcUpdate,
1047	#endif
1048	#if defined(IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK) \|\| defined(IEMNATIVE_WITH_SIMD_REG_ALLOCATOR)
1049	/** Info about a shadowed guest register becoming dirty. */
1050	kIemTbDbgEntryType_GuestRegDirty,
1051	/** Info about register writeback/flush oepration. */
1052	kIemTbDbgEntryType_GuestRegWriteback,
1053	#endif
1054	kIemTbDbgEntryType_End
1055	} IEMTBDBGENTRYTYPE;
1056
1057	/**
1058	* Translation block debug info entry.
1059	*/
1060	typedef union IEMTBDBGENTRY
1061	{
1062	/** Plain 32-bit view. */
1063	uint32_t u;
1064
1065	/** Generic view for getting at the type field. */
1066	struct
1067	{
1068	/** IEMTBDBGENTRYTYPE */
1069	uint32_t uType : 4;
1070	uint32_t uTypeSpecific : 28;
1071	} Gen;
1072
1073	struct
1074	{
1075	/** kIemTbDbgEntryType_ThreadedCall1. */
1076	uint32_t uType : 4;
1077	/** Native code offset. */
1078	uint32_t offNative : 28;
1079	} NativeOffset;
1080
1081	struct
1082	{
1083	/** kIemTbDbgEntryType_GuestInstruction. */
1084	uint32_t uType : 4;
1085	uint32_t uUnused : 4;
1086	/** The IEM_F_XXX flags. */
1087	uint32_t fExec : 24;
1088	} GuestInstruction;
1089
1090	struct
1091	{
1092	/* kIemTbDbgEntryType_ThreadedCall. */
1093	uint32_t uType : 4;
1094	/** Set if the call was recompiled to native code, clear if just calling
1095	* threaded function. */
1096	uint32_t fRecompiled : 1;
1097	uint32_t uUnused : 11;
1098	/** The threaded call number (IEMTHREADEDFUNCS). */
1099	uint32_t enmCall : 16;
1100	} ThreadedCall;
1101
1102	struct
1103	{
1104	/* kIemTbDbgEntryType_Label. */
1105	uint32_t uType : 4;
1106	uint32_t uUnused : 4;
1107	/** The label type (IEMNATIVELABELTYPE). */
1108	uint32_t enmLabel : 8;
1109	/** The label data. */
1110	uint32_t uData : 16;
1111	} Label;
1112
1113	struct
1114	{
1115	/* kIemTbDbgEntryType_GuestRegShadowing. */
1116	uint32_t uType : 4;
1117	uint32_t uUnused : 4;
1118	/** The guest register being shadowed (IEMNATIVEGSTREG). */
1119	uint32_t idxGstReg : 8;
1120	/** The host new register number, UINT8_MAX if dropped. */
1121	uint32_t idxHstReg : 8;
1122	/** The previous host register number, UINT8_MAX if new. */
1123	uint32_t idxHstRegPrev : 8;
1124	} GuestRegShadowing;
1125
1126	#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
1127	struct
1128	{
1129	/* kIemTbDbgEntryType_GuestSimdRegShadowing. */
1130	uint32_t uType : 4;
1131	uint32_t uUnused : 4;
1132	/** The guest register being shadowed (IEMNATIVEGSTSIMDREG). */
1133	uint32_t idxGstSimdReg : 8;
1134	/** The host new register number, UINT8_MAX if dropped. */
1135	uint32_t idxHstSimdReg : 8;
1136	/** The previous host register number, UINT8_MAX if new. */
1137	uint32_t idxHstSimdRegPrev : 8;
1138	} GuestSimdRegShadowing;
1139	#endif
1140
1141	#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING
1142	struct
1143	{
1144	/* kIemTbDbgEntryType_DelayedPcUpdate. */
1145	uint32_t uType : 4;
1146	/* The instruction offset added to the program counter. */
1147	uint32_t offPc : 14;
1148	/** Number of instructions skipped. */
1149	uint32_t cInstrSkipped : 14;
1150	} DelayedPcUpdate;
1151	#endif
1152
1153	#if defined(IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK) \|\| defined(IEMNATIVE_WITH_SIMD_REG_ALLOCATOR)
1154	struct
1155	{
1156	/* kIemTbDbgEntryType_GuestRegDirty. */
1157	uint32_t uType : 4;
1158	uint32_t uUnused : 11;
1159	/** Flag whether this is about a SIMD (true) or general (false) register. */
1160	uint32_t fSimdReg : 1;
1161	/** The guest register index being marked as dirty. */
1162	uint32_t idxGstReg : 8;
1163	/** The host register number this register is shadowed in .*/
1164	uint32_t idxHstReg : 8;
1165	} GuestRegDirty;
1166
1167	struct
1168	{
1169	/* kIemTbDbgEntryType_GuestRegWriteback. */
1170	uint32_t uType : 4;
1171	/** Flag whether this is about a SIMD (true) or general (false) register flush. */
1172	uint32_t fSimdReg : 1;
1173	/** The mask shift. */
1174	uint32_t cShift : 2;
1175	/** The guest register mask being written back. */
1176	uint32_t fGstReg : 25;
1177	} GuestRegWriteback;
1178	#endif
1179
1180	} IEMTBDBGENTRY;
1181	AssertCompileSize(IEMTBDBGENTRY, sizeof(uint32_t));
1182	/** Pointer to a debug info entry. */
1183	typedef IEMTBDBGENTRY *PIEMTBDBGENTRY;
1184	/** Pointer to a const debug info entry. */
1185	typedef IEMTBDBGENTRY const *PCIEMTBDBGENTRY;
1186
1187	/**
1188	* Translation block debug info.
1189	*/
1190	typedef struct IEMTBDBG
1191	{
1192	/** Number of entries in aEntries. */
1193	uint32_t cEntries;
1194	/** The offset of the last kIemTbDbgEntryType_NativeOffset record. */
1195	uint32_t offNativeLast;
1196	/** Debug info entries. */
1197	RT_FLEXIBLE_ARRAY_EXTENSION
1198	IEMTBDBGENTRY aEntries[RT_FLEXIBLE_ARRAY];
1199	} IEMTBDBG;
1200	/** Pointer to TB debug info. */
1201	typedef IEMTBDBG *PIEMTBDBG;
1202	/** Pointer to const TB debug info. */
1203	typedef IEMTBDBG const *PCIEMTBDBG;
1204
1205
1206	/**
1207	* Translation block.
1208	*
1209	* The current plan is to just keep TBs and associated lookup hash table private
1210	* to each VCpu as that simplifies TB removal greatly (no races) and generally
1211	* avoids using expensive atomic primitives for updating lists and stuff.
1212	*/
1213	#pragma pack(2) /* to prevent the Thrd structure from being padded unnecessarily */
1214	typedef struct IEMTB
1215	{
1216	/** Next block with the same hash table entry. */
1217	struct IEMTB *pNext;
1218	/** Usage counter. */
1219	uint32_t cUsed;
1220	/** The IEMCPU::msRecompilerPollNow last time it was used. */
1221	uint32_t msLastUsed;
1222
1223	/** @name What uniquely identifies the block.
1224	* @{ */
1225	RTGCPHYS GCPhysPc;
1226	/** IEMTB_F_XXX (i.e. IEM_F_XXX ++). */
1227	uint32_t fFlags;
1228	union
1229	{
1230	struct
1231	{
1232	/*< Relevant CS X86DESCATTR_XXX bits. /
1233	uint16_t fAttr;
1234	} x86;
1235	};
1236	/** @} */
1237
1238	/** Number of opcode ranges. */
1239	uint8_t cRanges;
1240	/** Statistics: Number of instructions in the block. */
1241	uint8_t cInstructions;
1242
1243	/** Type specific info. */
1244	union
1245	{
1246	struct
1247	{
1248	/** The call sequence table. */
1249	PIEMTHRDEDCALLENTRY paCalls;
1250	/** Number of calls in paCalls. */
1251	uint16_t cCalls;
1252	/** Number of calls allocated. */
1253	uint16_t cAllocated;
1254	} Thrd;
1255	struct
1256	{
1257	/** The native instructions (PFNIEMTBNATIVE). */
1258	PIEMNATIVEINSTR paInstructions;
1259	/** Number of instructions pointed to by paInstructions. */
1260	uint32_t cInstructions;
1261	} Native;
1262	/** Generic view for zeroing when freeing. */
1263	struct
1264	{
1265	uintptr_t uPtr;
1266	uint32_t uData;
1267	} Gen;
1268	};
1269
1270	/** The allocation chunk this TB belongs to. */
1271	uint8_t idxAllocChunk;
1272	/** The number of entries in the lookup table.
1273	* Because we're out of space, the TB lookup table is located before the
1274	* opcodes pointed to by pabOpcodes. */
1275	uint8_t cTbLookupEntries;
1276
1277	/** Number of bytes of opcodes stored in pabOpcodes.
1278	* @todo this field isn't really needed, aRanges keeps the actual info. */
1279	uint16_t cbOpcodes;
1280	/** Pointer to the opcode bytes this block was recompiled from.
1281	* This also points to the TB lookup table, which starts cTbLookupEntries
1282	* entries before the opcodes (we don't have room atm for another point). */
1283	uint8_t *pabOpcodes;
1284
1285	/** Debug info if enabled.
1286	* This is only generated by the native recompiler. */
1287	PIEMTBDBG pDbgInfo;
1288
1289	/* --- 64 byte cache line end --- */
1290
1291	/** Opcode ranges.
1292	*
1293	* The opcode checkers and maybe TLB loading functions will use this to figure
1294	* out what to do. The parameter will specify an entry and the opcode offset to
1295	* start at and the minimum number of bytes to verify (instruction length).
1296	*
1297	* When VT-x and AMD-V looks up the opcode bytes for an exitting instruction,
1298	* they'll first translate RIP (+ cbInstr - 1) to a physical address using the
1299	* code TLB (must have a valid entry for that address) and scan the ranges to
1300	* locate the corresponding opcodes. Probably.
1301	*/
1302	struct IEMTBOPCODERANGE
1303	{
1304	/** Offset within pabOpcodes. */
1305	uint16_t offOpcodes;
1306	/** Number of bytes. */
1307	uint16_t cbOpcodes;
1308	/** The page offset. */
1309	RT_GCC_EXTENSION
1310	uint16_t offPhysPage : 12;
1311	/** Unused bits. */
1312	RT_GCC_EXTENSION
1313	uint16_t u2Unused : 2;
1314	/** Index into GCPhysPc + aGCPhysPages for the physical page address. */
1315	RT_GCC_EXTENSION
1316	uint16_t idxPhysPage : 2;
1317	} aRanges[8];
1318
1319	/** Physical pages that this TB covers.
1320	* The GCPhysPc w/o page offset is element zero, so starting here with 1. */
1321	RTGCPHYS aGCPhysPages[2];
1322	} IEMTB;
1323	#pragma pack()
1324	AssertCompileMemberAlignment(IEMTB, GCPhysPc, sizeof(RTGCPHYS));
1325	AssertCompileMemberAlignment(IEMTB, Thrd, sizeof(void *));
1326	AssertCompileMemberAlignment(IEMTB, pabOpcodes, sizeof(void *));
1327	AssertCompileMemberAlignment(IEMTB, pDbgInfo, sizeof(void *));
1328	AssertCompileMemberAlignment(IEMTB, aGCPhysPages, sizeof(RTGCPHYS));
1329	AssertCompileMemberOffset(IEMTB, aRanges, 64);
1330	AssertCompileMemberSize(IEMTB, aRanges[0], 6);
1331	#if 1
1332	AssertCompileSize(IEMTB, 128);
1333	# define IEMTB_SIZE_IS_POWER_OF_TWO /*< The IEMTB size is a power of two. /
1334	#else
1335	AssertCompileSize(IEMTB, 168);
1336	# undef IEMTB_SIZE_IS_POWER_OF_TWO
1337	#endif
1338
1339	/** Pointer to a translation block. */
1340	typedef IEMTB *PIEMTB;
1341	/** Pointer to a const translation block. */
1342	typedef IEMTB const *PCIEMTB;
1343
1344	/** Gets address of the given TB lookup table entry. */
1345	#define IEMTB_GET_TB_LOOKUP_TAB_ENTRY(a_pTb, a_idx) \
1346	((PIEMTB )&(a_pTb)->pabOpcodes[-(int)((a_pTb)->cTbLookupEntries - (a_idx)) sizeof(PIEMTB)])
1347
1348
1349	/**
1350	* A chunk of memory in the TB allocator.
1351	*/
1352	typedef struct IEMTBCHUNK
1353	{
1354	/** Pointer to the translation blocks in this chunk. */
1355	PIEMTB paTbs;
1356	#ifdef IN_RING0
1357	/** Allocation handle. */
1358	RTR0MEMOBJ hMemObj;
1359	#endif
1360	} IEMTBCHUNK;
1361
1362	/**
1363	* A per-CPU translation block allocator.
1364	*
1365	* Because of how the IEMTBCACHE uses the lower 6 bits of the TB address to keep
1366	* the length of the collision list, and of course also for cache line alignment
1367	* reasons, the TBs must be allocated with at least 64-byte alignment.
1368	* Memory is there therefore allocated using one of the page aligned allocators.
1369	*
1370	*
1371	* To avoid wasting too much memory, it is allocated piecemeal as needed,
1372	* in chunks (IEMTBCHUNK) of 2 MiB or more. The TB has an 8-bit chunk index
1373	* that enables us to quickly calculate the allocation bitmap position when
1374	* freeing the translation block.
1375	*/
1376	typedef struct IEMTBALLOCATOR
1377	{
1378	/** Magic value (IEMTBALLOCATOR_MAGIC). */
1379	uint32_t uMagic;
1380
1381	#ifdef IEMTB_SIZE_IS_POWER_OF_TWO
1382	/** Mask corresponding to cTbsPerChunk - 1. */
1383	uint32_t fChunkMask;
1384	/** Shift count corresponding to cTbsPerChunk. */
1385	uint8_t cChunkShift;
1386	#else
1387	uint32_t uUnused;
1388	uint8_t bUnused;
1389	#endif
1390	/** Number of chunks we're allowed to allocate. */
1391	uint8_t cMaxChunks;
1392	/** Number of chunks currently populated. */
1393	uint16_t cAllocatedChunks;
1394	/** Number of translation blocks per chunk. */
1395	uint32_t cTbsPerChunk;
1396	/** Chunk size. */
1397	uint32_t cbPerChunk;
1398
1399	/** The maximum number of TBs. */
1400	uint32_t cMaxTbs;
1401	/** Total number of TBs in the populated chunks.
1402	* (cAllocatedChunks * cTbsPerChunk) */
1403	uint32_t cTotalTbs;
1404	/** The current number of TBs in use.
1405	* The number of free TBs: cAllocatedTbs - cInUseTbs; */
1406	uint32_t cInUseTbs;
1407	/** Statistics: Number of the cInUseTbs that are native ones. */
1408	uint32_t cNativeTbs;
1409	/** Statistics: Number of the cInUseTbs that are threaded ones. */
1410	uint32_t cThreadedTbs;
1411
1412	/** Where to start pruning TBs from when we're out.
1413	* See iemTbAllocatorAllocSlow for details. */
1414	uint32_t iPruneFrom;
1415	/** Hint about which bit to start scanning the bitmap from. */
1416	uint32_t iStartHint;
1417	/** Where to start pruning native TBs from when we're out of executable memory.
1418	* See iemTbAllocatorFreeupNativeSpace for details. */
1419	uint32_t iPruneNativeFrom;
1420	uint32_t uPadding;
1421
1422	/** Statistics: Number of TB allocation calls. */
1423	STAMCOUNTER StatAllocs;
1424	/** Statistics: Number of TB free calls. */
1425	STAMCOUNTER StatFrees;
1426	/** Statistics: Time spend pruning. */
1427	STAMPROFILE StatPrune;
1428	/** Statistics: Time spend pruning native TBs. */
1429	STAMPROFILE StatPruneNative;
1430
1431	/** The delayed free list (see iemTbAlloctorScheduleForFree). */
1432	PIEMTB pDelayedFreeHead;
1433
1434	/** Allocation chunks. */
1435	IEMTBCHUNK aChunks[256];
1436
1437	/** Allocation bitmap for all possible chunk chunks. */
1438	RT_FLEXIBLE_ARRAY_EXTENSION
1439	uint64_t bmAllocated[RT_FLEXIBLE_ARRAY];
1440	} IEMTBALLOCATOR;
1441	/** Pointer to a TB allocator. */
1442	typedef struct IEMTBALLOCATOR *PIEMTBALLOCATOR;
1443
1444	/** Magic value for the TB allocator (Emmet Harley Cohen). */
1445	#define IEMTBALLOCATOR_MAGIC UINT32_C(0x19900525)
1446
1447
1448	/**
1449	* A per-CPU translation block cache (hash table).
1450	*
1451	* The hash table is allocated once during IEM initialization and size double
1452	* the max TB count, rounded up to the nearest power of two (so we can use and
1453	* AND mask rather than a rest division when hashing).
1454	*/
1455	typedef struct IEMTBCACHE
1456	{
1457	/** Magic value (IEMTBCACHE_MAGIC). */
1458	uint32_t uMagic;
1459	/** Size of the hash table. This is a power of two. */
1460	uint32_t cHash;
1461	/** The mask corresponding to cHash. */
1462	uint32_t uHashMask;
1463	uint32_t uPadding;
1464
1465	/** @name Statistics
1466	* @{ */
1467	/** Number of collisions ever. */
1468	STAMCOUNTER cCollisions;
1469
1470	/** Statistics: Number of TB lookup misses. */
1471	STAMCOUNTER cLookupMisses;
1472	/** Statistics: Number of TB lookup hits via hash table (debug only). */
1473	STAMCOUNTER cLookupHits;
1474	/** Statistics: Number of TB lookup hits via TB associated lookup table (debug only). */
1475	STAMCOUNTER cLookupHitsViaTbLookupTable;
1476	STAMCOUNTER auPadding2[2];
1477	/** Statistics: Collision list length pruning. */
1478	STAMPROFILE StatPrune;
1479	/** @} */
1480
1481	/** The hash table itself.
1482	* @note The lower 6 bits of the pointer is used for keeping the collision
1483	* list length, so we can take action when it grows too long.
1484	* This works because TBs are allocated using a 64 byte (or
1485	* higher) alignment from page aligned chunks of memory, so the lower
1486	* 6 bits of the address will always be zero.
1487	* See IEMTBCACHE_PTR_COUNT_MASK, IEMTBCACHE_PTR_MAKE and friends.
1488	*/
1489	RT_FLEXIBLE_ARRAY_EXTENSION
1490	PIEMTB apHash[RT_FLEXIBLE_ARRAY];
1491	} IEMTBCACHE;
1492	/** Pointer to a per-CPU translation block cahce. */
1493	typedef IEMTBCACHE *PIEMTBCACHE;
1494
1495	/** Magic value for IEMTBCACHE (Johnny O'Neal). */
1496	#define IEMTBCACHE_MAGIC UINT32_C(0x19561010)
1497
1498	/** The collision count mask for IEMTBCACHE::apHash entries. */
1499	#define IEMTBCACHE_PTR_COUNT_MASK ((uintptr_t)0x3f)
1500	/** The max collision count for IEMTBCACHE::apHash entries before pruning. */
1501	#define IEMTBCACHE_PTR_MAX_COUNT ((uintptr_t)0x30)
1502	/** Combine a TB pointer and a collision list length into a value for an
1503	* IEMTBCACHE::apHash entry. */
1504	#define IEMTBCACHE_PTR_MAKE(a_pTb, a_cCount) (PIEMTB)((uintptr_t)(a_pTb) \| (a_cCount))
1505	/** Combine a TB pointer and a collision list length into a value for an
1506	* IEMTBCACHE::apHash entry. */
1507	#define IEMTBCACHE_PTR_GET_TB(a_pHashEntry) (PIEMTB)((uintptr_t)(a_pHashEntry) & ~IEMTBCACHE_PTR_COUNT_MASK)
1508	/** Combine a TB pointer and a collision list length into a value for an
1509	* IEMTBCACHE::apHash entry. */
1510	#define IEMTBCACHE_PTR_GET_COUNT(a_pHashEntry) ((uintptr_t)(a_pHashEntry) & IEMTBCACHE_PTR_COUNT_MASK)
1511
1512	/**
1513	* Calculates the hash table slot for a TB from physical PC address and TB flags.
1514	*/
1515	#define IEMTBCACHE_HASH(a_paCache, a_fTbFlags, a_GCPhysPc) \
1516	IEMTBCACHE_HASH_NO_KEY_MASK(a_paCache, (a_fTbFlags) & IEMTB_F_KEY_MASK, a_GCPhysPc)
1517
1518	/**
1519	* Calculates the hash table slot for a TB from physical PC address and TB
1520	* flags, ASSUMING the caller has applied IEMTB_F_KEY_MASK to @a a_fTbFlags.
1521	*/
1522	#define IEMTBCACHE_HASH_NO_KEY_MASK(a_paCache, a_fTbFlags, a_GCPhysPc) \
1523	(((uint32_t)(a_GCPhysPc) ^ (a_fTbFlags)) & (a_paCache)->uHashMask)
1524
1525
1526	/** @name IEMBRANCHED_F_XXX - Branched indicator (IEMCPU::fTbBranched).
1527	*
1528	* These flags parallels the main IEM_CIMPL_F_BRANCH_XXX flags.
1529	*
1530	* @{ */
1531	/** Value if no branching happened recently. */
1532	#define IEMBRANCHED_F_NO UINT8_C(0x00)
1533	/** Flag set if direct branch, clear if absolute or indirect. */
1534	#define IEMBRANCHED_F_DIRECT UINT8_C(0x01)
1535	/** Flag set if indirect branch, clear if direct or relative. */
1536	#define IEMBRANCHED_F_INDIRECT UINT8_C(0x02)
1537	/** Flag set if relative branch, clear if absolute or indirect. */
1538	#define IEMBRANCHED_F_RELATIVE UINT8_C(0x04)
1539	/** Flag set if conditional branch, clear if unconditional. */
1540	#define IEMBRANCHED_F_CONDITIONAL UINT8_C(0x08)
1541	/** Flag set if it's a far branch. */
1542	#define IEMBRANCHED_F_FAR UINT8_C(0x10)
1543	/** Flag set if the stack pointer is modified. */
1544	#define IEMBRANCHED_F_STACK UINT8_C(0x20)
1545	/** Flag set if the stack pointer and (maybe) the stack segment are modified. */
1546	#define IEMBRANCHED_F_STACK_FAR UINT8_C(0x40)
1547	/** Flag set (by IEM_MC_REL_JMP_XXX) if it's a zero bytes relative jump. */
1548	#define IEMBRANCHED_F_ZERO UINT8_C(0x80)
1549	/** @} */
1550
1551
1552	/**
1553	* The per-CPU IEM state.
1554	*/
1555	typedef struct IEMCPU
1556	{
1557	/** Info status code that needs to be propagated to the IEM caller.
1558	* This cannot be passed internally, as it would complicate all success
1559	* checks within the interpreter making the code larger and almost impossible
1560	* to get right. Instead, we'll store status codes to pass on here. Each
1561	* source of these codes will perform appropriate sanity checks. */
1562	int32_t rcPassUp; /* 0x00 */
1563	/** Execution flag, IEM_F_XXX. */
1564	uint32_t fExec; /* 0x04 */
1565
1566	/** @name Decoder state.
1567	* @{ */
1568	#ifdef IEM_WITH_CODE_TLB
1569	/** The offset of the next instruction byte. */
1570	uint32_t offInstrNextByte; /* 0x08 */
1571	/** The number of bytes available at pbInstrBuf for the current instruction.
1572	* This takes the max opcode length into account so that doesn't need to be
1573	* checked separately. */
1574	uint32_t cbInstrBuf; /* 0x0c */
1575	/** Pointer to the page containing RIP, user specified buffer or abOpcode.
1576	* This can be NULL if the page isn't mappable for some reason, in which
1577	* case we'll do fallback stuff.
1578	*
1579	* If we're executing an instruction from a user specified buffer,
1580	* IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
1581	* aligned pointer but pointer to the user data.
1582	*
1583	* For instructions crossing pages, this will start on the first page and be
1584	* advanced to the next page by the time we've decoded the instruction. This
1585	* therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
1586	*/
1587	uint8_t const pbInstrBuf; / 0x10 */
1588	# if ARCH_BITS == 32
1589	uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
1590	# endif
1591	/** The program counter corresponding to pbInstrBuf.
1592	* This is set to a non-canonical address when we need to invalidate it. */
1593	uint64_t uInstrBufPc; /* 0x18 */
1594	/** The guest physical address corresponding to pbInstrBuf. */
1595	RTGCPHYS GCPhysInstrBuf; /* 0x20 */
1596	/** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
1597	* This takes the CS segment limit into account.
1598	* @note Set to zero when the code TLB is flushed to trigger TLB reload. */
1599	uint16_t cbInstrBufTotal; /* 0x28 */
1600	# ifndef IEM_WITH_OPAQUE_DECODER_STATE
1601	/** Offset into pbInstrBuf of the first byte of the current instruction.
1602	* Can be negative to efficiently handle cross page instructions. */
1603	int16_t offCurInstrStart; /* 0x2a */
1604
1605	/** The prefix mask (IEM_OP_PRF_XXX). */
1606	uint32_t fPrefixes; /* 0x2c */
1607	/** The extra REX ModR/M register field bit (REX.R << 3). */
1608	uint8_t uRexReg; /* 0x30 */
1609	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
1610	* (REX.B << 3). */
1611	uint8_t uRexB; /* 0x31 */
1612	/** The extra REX SIB index field bit (REX.X << 3). */
1613	uint8_t uRexIndex; /* 0x32 */
1614
1615	/** The effective segment register (X86_SREG_XXX). */
1616	uint8_t iEffSeg; /* 0x33 */
1617
1618	/** The offset of the ModR/M byte relative to the start of the instruction. */
1619	uint8_t offModRm; /* 0x34 */
1620
1621	# ifdef IEM_WITH_CODE_TLB_AND_OPCODE_BUF
1622	/** The current offset into abOpcode. */
1623	uint8_t offOpcode; /* 0x35 */
1624	# else
1625	uint8_t bUnused; /* 0x35 */
1626	# endif
1627	# else /* IEM_WITH_OPAQUE_DECODER_STATE */
1628	uint8_t abOpaqueDecoderPart1[0x36 - 0x2a];
1629	# endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1630
1631	#else /* !IEM_WITH_CODE_TLB */
1632	# ifndef IEM_WITH_OPAQUE_DECODER_STATE
1633	/** The size of what has currently been fetched into abOpcode. */
1634	uint8_t cbOpcode; /* 0x08 */
1635	/** The current offset into abOpcode. */
1636	uint8_t offOpcode; /* 0x09 */
1637	/** The offset of the ModR/M byte relative to the start of the instruction. */
1638	uint8_t offModRm; /* 0x0a */
1639
1640	/** The effective segment register (X86_SREG_XXX). */
1641	uint8_t iEffSeg; /* 0x0b */
1642
1643	/** The prefix mask (IEM_OP_PRF_XXX). */
1644	uint32_t fPrefixes; /* 0x0c */
1645	/** The extra REX ModR/M register field bit (REX.R << 3). */
1646	uint8_t uRexReg; /* 0x10 */
1647	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
1648	* (REX.B << 3). */
1649	uint8_t uRexB; /* 0x11 */
1650	/** The extra REX SIB index field bit (REX.X << 3). */
1651	uint8_t uRexIndex; /* 0x12 */
1652
1653	# else /* IEM_WITH_OPAQUE_DECODER_STATE */
1654	uint8_t abOpaqueDecoderPart1[0x13 - 0x08];
1655	# endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1656	#endif /* !IEM_WITH_CODE_TLB */
1657
1658	#ifndef IEM_WITH_OPAQUE_DECODER_STATE
1659	/** The effective operand mode. */
1660	IEMMODE enmEffOpSize; /* 0x36, 0x13 */
1661	/** The default addressing mode. */
1662	IEMMODE enmDefAddrMode; /* 0x37, 0x14 */
1663	/** The effective addressing mode. */
1664	IEMMODE enmEffAddrMode; /* 0x38, 0x15 */
1665	/** The default operand mode. */
1666	IEMMODE enmDefOpSize; /* 0x39, 0x16 */
1667
1668	/** Prefix index (VEX.pp) for two byte and three byte tables. */
1669	uint8_t idxPrefix; /* 0x3a, 0x17 */
1670	/** 3rd VEX/EVEX/XOP register.
1671	* Please use IEM_GET_EFFECTIVE_VVVV to access. */
1672	uint8_t uVex3rdReg; /* 0x3b, 0x18 */
1673	/** The VEX/EVEX/XOP length field. */
1674	uint8_t uVexLength; /* 0x3c, 0x19 */
1675	/** Additional EVEX stuff. */
1676	uint8_t fEvexStuff; /* 0x3d, 0x1a */
1677
1678	# ifndef IEM_WITH_CODE_TLB
1679	/** Explicit alignment padding. */
1680	uint8_t abAlignment2a[1]; /* 0x1b */
1681	# endif
1682	/** The FPU opcode (FOP). */
1683	uint16_t uFpuOpcode; /* 0x3e, 0x1c */
1684	# ifndef IEM_WITH_CODE_TLB
1685	/** Explicit alignment padding. */
1686	uint8_t abAlignment2b[2]; /* 0x1e */
1687	# endif
1688
1689	/** The opcode bytes. */
1690	uint8_t abOpcode[15]; /* 0x40, 0x20 */
1691	/** Explicit alignment padding. */
1692	# ifdef IEM_WITH_CODE_TLB
1693	//uint8_t abAlignment2c[0x4f - 0x4f]; /* 0x4f */
1694	# else
1695	uint8_t abAlignment2c[0x4f - 0x2f]; /* 0x2f */
1696	# endif
1697
1698	#else /* IEM_WITH_OPAQUE_DECODER_STATE */
1699	# ifdef IEM_WITH_CODE_TLB
1700	uint8_t abOpaqueDecoderPart2[0x4f - 0x36];
1701	# else
1702	uint8_t abOpaqueDecoderPart2[0x4f - 0x13];
1703	# endif
1704	#endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1705	/** @} */
1706
1707
1708	/** The number of active guest memory mappings. */
1709	uint8_t cActiveMappings; /* 0x4f, 0x4f */
1710
1711	/** Records for tracking guest memory mappings. */
1712	struct
1713	{
1714	/** The address of the mapped bytes. */
1715	R3R0PTRTYPE(void *) pv;
1716	/** The access flags (IEM_ACCESS_XXX).
1717	* IEM_ACCESS_INVALID if the entry is unused. */
1718	uint32_t fAccess;
1719	#if HC_ARCH_BITS == 64
1720	uint32_t u32Alignment4; /*< Alignment padding. /
1721	#endif
1722	} aMemMappings[3]; /* 0x50 LB 0x30 */
1723
1724	/** Locking records for the mapped memory. */
1725	union
1726	{
1727	PGMPAGEMAPLOCK Lock;
1728	uint64_t au64Padding[2];
1729	} aMemMappingLocks[3]; /* 0x80 LB 0x30 */
1730
1731	/** Bounce buffer info.
1732	* This runs in parallel to aMemMappings. */
1733	struct
1734	{
1735	/** The physical address of the first byte. */
1736	RTGCPHYS GCPhysFirst;
1737	/** The physical address of the second page. */
1738	RTGCPHYS GCPhysSecond;
1739	/** The number of bytes in the first page. */
1740	uint16_t cbFirst;
1741	/** The number of bytes in the second page. */
1742	uint16_t cbSecond;
1743	/** Whether it's unassigned memory. */
1744	bool fUnassigned;
1745	/** Explicit alignment padding. */
1746	bool afAlignment5[3];
1747	} aMemBbMappings[3]; /* 0xb0 LB 0x48 */
1748
1749	/** The flags of the current exception / interrupt. */
1750	uint32_t fCurXcpt; /* 0xf8 */
1751	/** The current exception / interrupt. */
1752	uint8_t uCurXcpt; /* 0xfc */
1753	/** Exception / interrupt recursion depth. */
1754	int8_t cXcptRecursions; /* 0xfb */
1755
1756	/** The next unused mapping index.
1757	* @todo try find room for this up with cActiveMappings. */
1758	uint8_t iNextMapping; /* 0xfd */
1759	uint8_t abAlignment7[1];
1760
1761	/** Bounce buffer storage.
1762	* This runs in parallel to aMemMappings and aMemBbMappings. */
1763	struct
1764	{
1765	uint8_t ab[512];
1766	} aBounceBuffers[3]; /* 0x100 LB 0x600 */
1767
1768
1769	/** Pointer set jump buffer - ring-3 context. */
1770	R3PTRTYPE(jmp_buf *) pJmpBufR3;
1771	/** Pointer set jump buffer - ring-0 context. */
1772	R0PTRTYPE(jmp_buf *) pJmpBufR0;
1773
1774	/** @todo Should move this near @a fCurXcpt later. */
1775	/** The CR2 for the current exception / interrupt. */
1776	uint64_t uCurXcptCr2;
1777	/** The error code for the current exception / interrupt. */
1778	uint32_t uCurXcptErr;
1779
1780	/** @name Statistics
1781	* @{ */
1782	/** The number of instructions we've executed. */
1783	uint32_t cInstructions;
1784	/** The number of potential exits. */
1785	uint32_t cPotentialExits;
1786	/** The number of bytes data or stack written (mostly for IEMExecOneEx).
1787	* This may contain uncommitted writes. */
1788	uint32_t cbWritten;
1789	/** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
1790	uint32_t cRetInstrNotImplemented;
1791	/** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
1792	uint32_t cRetAspectNotImplemented;
1793	/** Counts informational statuses returned (other than VINF_SUCCESS). */
1794	uint32_t cRetInfStatuses;
1795	/** Counts other error statuses returned. */
1796	uint32_t cRetErrStatuses;
1797	/** Number of times rcPassUp has been used. */
1798	uint32_t cRetPassUpStatus;
1799	/** Number of times RZ left with instruction commit pending for ring-3. */
1800	uint32_t cPendingCommit;
1801	/** Number of misaligned (host sense) atomic instruction accesses. */
1802	uint32_t cMisalignedAtomics;
1803	/** Number of long jumps. */
1804	uint32_t cLongJumps;
1805	/** @} */
1806
1807	/** @name Target CPU information.
1808	* @{ */
1809	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
1810	/** The target CPU. */
1811	uint8_t uTargetCpu;
1812	#else
1813	uint8_t bTargetCpuPadding;
1814	#endif
1815	/** For selecting assembly works matching the target CPU EFLAGS behaviour, see
1816	* IEMTARGETCPU_EFL_BEHAVIOR_XXX for values, with the 1st entry for when no
1817	* native host support and the 2nd for when there is.
1818	*
1819	* The two values are typically indexed by a g_CpumHostFeatures bit.
1820	*
1821	* This is for instance used for the BSF & BSR instructions where AMD and
1822	* Intel CPUs produce different EFLAGS. */
1823	uint8_t aidxTargetCpuEflFlavour[2];
1824
1825	/** The CPU vendor. */
1826	CPUMCPUVENDOR enmCpuVendor;
1827	/** @} */
1828
1829	/** @name Host CPU information.
1830	* @{ */
1831	/** The CPU vendor. */
1832	CPUMCPUVENDOR enmHostCpuVendor;
1833	/** @} */
1834
1835	/** Counts RDMSR \#GP(0) LogRel(). */
1836	uint8_t cLogRelRdMsr;
1837	/** Counts WRMSR \#GP(0) LogRel(). */
1838	uint8_t cLogRelWrMsr;
1839	/** Alignment padding. */
1840	uint8_t abAlignment9[42];
1841
1842	/** @name Recompilation
1843	* @{ */
1844	/** Pointer to the current translation block.
1845	* This can either be one being executed or one being compiled. */
1846	R3PTRTYPE(PIEMTB) pCurTbR3;
1847	#ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
1848	/** Frame pointer for the last native TB to execute. */
1849	R3PTRTYPE(void *) pvTbFramePointerR3;
1850	#else
1851	R3PTRTYPE(void *) pvUnusedR3;
1852	#endif
1853	/** Fixed TB used for threaded recompilation.
1854	* This is allocated once with maxed-out sizes and re-used afterwards. */
1855	R3PTRTYPE(PIEMTB) pThrdCompileTbR3;
1856	/** Pointer to the ring-3 TB cache for this EMT. */
1857	R3PTRTYPE(PIEMTBCACHE) pTbCacheR3;
1858	/** Pointer to the ring-3 TB lookup entry.
1859	* This either points to pTbLookupEntryDummyR3 or an actually lookuptable
1860	* entry, thus it can always safely be used w/o NULL checking. */
1861	R3PTRTYPE(PIEMTB *) ppTbLookupEntryR3;
1862	/** The PC (RIP) at the start of pCurTbR3/pCurTbR0.
1863	* The TBs are based on physical addresses, so this is needed to correleated
1864	* RIP to opcode bytes stored in the TB (AMD-V / VT-x). */
1865	uint64_t uCurTbStartPc;
1866	/** Number of threaded TBs executed. */
1867	uint64_t cTbExecThreaded;
1868	/** Number of native TBs executed. */
1869	uint64_t cTbExecNative;
1870	/** Whether we need to check the opcode bytes for the current instruction.
1871	* This is set by a previous instruction if it modified memory or similar. */
1872	bool fTbCheckOpcodes;
1873	/** Indicates whether and how we just branched - IEMBRANCHED_F_XXX. */
1874	uint8_t fTbBranched;
1875	/** Set when GCPhysInstrBuf is updated because of a page crossing. */
1876	bool fTbCrossedPage;
1877	/** Whether to end the current TB. */
1878	bool fEndTb;
1879	/** Number of instructions before we need emit an IRQ check call again.
1880	* This helps making sure we don't execute too long w/o checking for
1881	* interrupts and immediately following instructions that may enable
1882	* interrupts (e.g. POPF, IRET, STI). With STI an additional hack is
1883	* required to make sure we check following the next instruction as well, see
1884	* fTbCurInstrIsSti. */
1885	uint8_t cInstrTillIrqCheck;
1886	/** Indicates that the current instruction is an STI. This is set by the
1887	* iemCImpl_sti code and subsequently cleared by the recompiler. */
1888	bool fTbCurInstrIsSti;
1889	/** The size of the IEMTB::pabOpcodes allocation in pThrdCompileTbR3. */
1890	uint16_t cbOpcodesAllocated;
1891	/** The current instruction number in a native TB.
1892	* This is set by code that may trigger an unexpected TB exit (throw/longjmp)
1893	* and will be picked up by the TB execution loop. Only used when
1894	* IEMNATIVE_WITH_INSTRUCTION_COUNTING is defined. */
1895	uint8_t idxTbCurInstr;
1896	/** Spaced reserved for recompiler data / alignment. */
1897	bool afRecompilerStuff1[3];
1898	/** The virtual sync time at the last timer poll call. */
1899	uint32_t msRecompilerPollNow;
1900	/** The IEMTB::cUsed value when to attempt native recompilation of a TB. */
1901	uint32_t uTbNativeRecompileAtUsedCount;
1902	/** The IEM_CIMPL_F_XXX mask for the current instruction. */
1903	uint32_t fTbCurInstr;
1904	/** The IEM_CIMPL_F_XXX mask for the previous instruction. */
1905	uint32_t fTbPrevInstr;
1906	/** Strict: Tracking skipped EFLAGS calculations. Any bits set here are
1907	* currently not up to date in EFLAGS. */
1908	uint32_t fSkippingEFlags;
1909	/** Previous GCPhysInstrBuf value - only valid if fTbCrossedPage is set. */
1910	RTGCPHYS GCPhysInstrBufPrev;
1911	/** Pointer to the ring-3 TB allocator for this EMT. */
1912	R3PTRTYPE(PIEMTBALLOCATOR) pTbAllocatorR3;
1913	/** Pointer to the ring-3 executable memory allocator for this EMT. */
1914	R3PTRTYPE(struct IEMEXECMEMALLOCATOR *) pExecMemAllocatorR3;
1915	/** Pointer to the native recompiler state for ring-3. */
1916	R3PTRTYPE(struct IEMRECOMPILERSTATE *) pNativeRecompilerStateR3;
1917	/** Dummy entry for ppTbLookupEntryR3. */
1918	R3PTRTYPE(PIEMTB) pTbLookupEntryDummyR3;
1919
1920	/** Statistics: Times TB execution was broken off before reaching the end. */
1921	STAMCOUNTER StatTbExecBreaks;
1922	/** Statistics: Times BltIn_CheckIrq breaks out of the TB. */
1923	STAMCOUNTER StatCheckIrqBreaks;
1924	/** Statistics: Times BltIn_CheckMode breaks out of the TB. */
1925	STAMCOUNTER StatCheckModeBreaks;
1926	/** Threaded TB statistics: Times execution break on call with lookup entries. */
1927	STAMCOUNTER StatTbThreadedExecBreaksWithLookup;
1928	/** Threaded TB statistics: Times execution break on call without lookup entries. */
1929	STAMCOUNTER StatTbThreadedExecBreaksWithoutLookup;
1930	/** Statistics: Times a post jump target check missed and had to find new TB. */
1931	STAMCOUNTER StatCheckBranchMisses;
1932	/** Statistics: Times a jump or page crossing required a TB with CS.LIM checking. */
1933	STAMCOUNTER StatCheckNeedCsLimChecking;
1934	/** Statistics: Times a loop was detected within a TB.. */
1935	STAMCOUNTER StatTbLoopInTbDetected;
1936	/** Exec memory allocator statistics: Number of times allocaintg executable memory failed. */
1937	STAMCOUNTER StatNativeExecMemInstrBufAllocFailed;
1938	/** Native TB statistics: Number of fully recompiled TBs. */
1939	STAMCOUNTER StatNativeFullyRecompiledTbs;
1940	/** TB statistics: Number of instructions per TB. */
1941	STAMPROFILE StatTbInstr;
1942	/** TB statistics: Number of TB lookup table entries per TB. */
1943	STAMPROFILE StatTbLookupEntries;
1944	/** Threaded TB statistics: Number of calls per TB. */
1945	STAMPROFILE StatTbThreadedCalls;
1946	/** Native TB statistics: Native code size per TB. */
1947	STAMPROFILE StatTbNativeCode;
1948	/** Native TB statistics: Profiling native recompilation. */
1949	STAMPROFILE StatNativeRecompilation;
1950	/** Native TB statistics: Number of calls per TB that were recompiled properly. */
1951	STAMPROFILE StatNativeCallsRecompiled;
1952	/** Native TB statistics: Number of threaded calls per TB that weren't recompiled. */
1953	STAMPROFILE StatNativeCallsThreaded;
1954	/** Native recompiled execution: TLB hits for data fetches. */
1955	STAMCOUNTER StatNativeTlbHitsForFetch;
1956	/** Native recompiled execution: TLB hits for data stores. */
1957	STAMCOUNTER StatNativeTlbHitsForStore;
1958	/** Native recompiled execution: TLB hits for stack accesses. */
1959	STAMCOUNTER StatNativeTlbHitsForStack;
1960	/** Native recompiled execution: TLB hits for mapped accesses. */
1961	STAMCOUNTER StatNativeTlbHitsForMapped;
1962	/** Native recompiled execution: Code TLB misses for new page. */
1963	STAMCOUNTER StatNativeCodeTlbMissesNewPage;
1964	/** Native recompiled execution: Code TLB hits for new page. */
1965	STAMCOUNTER StatNativeCodeTlbHitsForNewPage;
1966	/** Native recompiled execution: Code TLB misses for new page with offset. */
1967	STAMCOUNTER StatNativeCodeTlbMissesNewPageWithOffset;
1968	/** Native recompiled execution: Code TLB hits for new page with offset. */
1969	STAMCOUNTER StatNativeCodeTlbHitsForNewPageWithOffset;
1970
1971	/** Native recompiler: Number of calls to iemNativeRegAllocFindFree. */
1972	STAMCOUNTER StatNativeRegFindFree;
1973	/** Native recompiler: Number of times iemNativeRegAllocFindFree needed
1974	* to free a variable. */
1975	STAMCOUNTER StatNativeRegFindFreeVar;
1976	/** Native recompiler: Number of times iemNativeRegAllocFindFree did
1977	* not need to free any variables. */
1978	STAMCOUNTER StatNativeRegFindFreeNoVar;
1979	/** Native recompiler: Liveness info freed shadowed guest registers in
1980	* iemNativeRegAllocFindFree. */
1981	STAMCOUNTER StatNativeRegFindFreeLivenessUnshadowed;
1982	/** Native recompiler: Liveness info helped with the allocation in
1983	* iemNativeRegAllocFindFree. */
1984	STAMCOUNTER StatNativeRegFindFreeLivenessHelped;
1985
1986	/** Native recompiler: Number of times status flags calc has been skipped. */
1987	STAMCOUNTER StatNativeEflSkippedArithmetic;
1988	/** Native recompiler: Number of times status flags calc has been skipped. */
1989	STAMCOUNTER StatNativeEflSkippedLogical;
1990
1991	/** Native recompiler: Number of opportunities to skip EFLAGS.CF updating. */
1992	STAMCOUNTER StatNativeLivenessEflCfSkippable;
1993	/** Native recompiler: Number of opportunities to skip EFLAGS.PF updating. */
1994	STAMCOUNTER StatNativeLivenessEflPfSkippable;
1995	/** Native recompiler: Number of opportunities to skip EFLAGS.AF updating. */
1996	STAMCOUNTER StatNativeLivenessEflAfSkippable;
1997	/** Native recompiler: Number of opportunities to skip EFLAGS.ZF updating. */
1998	STAMCOUNTER StatNativeLivenessEflZfSkippable;
1999	/** Native recompiler: Number of opportunities to skip EFLAGS.SF updating. */
2000	STAMCOUNTER StatNativeLivenessEflSfSkippable;
2001	/** Native recompiler: Number of opportunities to skip EFLAGS.OF updating. */
2002	STAMCOUNTER StatNativeLivenessEflOfSkippable;
2003	/** Native recompiler: Number of required EFLAGS.CF updates. */
2004	STAMCOUNTER StatNativeLivenessEflCfRequired;
2005	/** Native recompiler: Number of required EFLAGS.PF updates. */
2006	STAMCOUNTER StatNativeLivenessEflPfRequired;
2007	/** Native recompiler: Number of required EFLAGS.AF updates. */
2008	STAMCOUNTER StatNativeLivenessEflAfRequired;
2009	/** Native recompiler: Number of required EFLAGS.ZF updates. */
2010	STAMCOUNTER StatNativeLivenessEflZfRequired;
2011	/** Native recompiler: Number of required EFLAGS.SF updates. */
2012	STAMCOUNTER StatNativeLivenessEflSfRequired;
2013	/** Native recompiler: Number of required EFLAGS.OF updates. */
2014	STAMCOUNTER StatNativeLivenessEflOfRequired;
2015	/** Native recompiler: Number of potentially delayable EFLAGS.CF updates. */
2016	STAMCOUNTER StatNativeLivenessEflCfDelayable;
2017	/** Native recompiler: Number of potentially delayable EFLAGS.PF updates. */
2018	STAMCOUNTER StatNativeLivenessEflPfDelayable;
2019	/** Native recompiler: Number of potentially delayable EFLAGS.AF updates. */
2020	STAMCOUNTER StatNativeLivenessEflAfDelayable;
2021	/** Native recompiler: Number of potentially delayable EFLAGS.ZF updates. */
2022	STAMCOUNTER StatNativeLivenessEflZfDelayable;
2023	/** Native recompiler: Number of potentially delayable EFLAGS.SF updates. */
2024	STAMCOUNTER StatNativeLivenessEflSfDelayable;
2025	/** Native recompiler: Number of potentially delayable EFLAGS.OF updates. */
2026	STAMCOUNTER StatNativeLivenessEflOfDelayable;
2027
2028	/** Native recompiler: Number of potential PC updates in total. */
2029	STAMCOUNTER StatNativePcUpdateTotal;
2030	/** Native recompiler: Number of PC updates which could be delayed. */
2031	STAMCOUNTER StatNativePcUpdateDelayed;
2032
2033	//#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
2034	/** Native recompiler: Number of calls to iemNativeSimdRegAllocFindFree. */
2035	STAMCOUNTER StatNativeSimdRegFindFree;
2036	/** Native recompiler: Number of times iemNativeSimdRegAllocFindFree needed
2037	* to free a variable. */
2038	STAMCOUNTER StatNativeSimdRegFindFreeVar;
2039	/** Native recompiler: Number of times iemNativeSimdRegAllocFindFree did
2040	* not need to free any variables. */
2041	STAMCOUNTER StatNativeSimdRegFindFreeNoVar;
2042	/** Native recompiler: Liveness info freed shadowed guest registers in
2043	* iemNativeSimdRegAllocFindFree. */
2044	STAMCOUNTER StatNativeSimdRegFindFreeLivenessUnshadowed;
2045	/** Native recompiler: Liveness info helped with the allocation in
2046	* iemNativeSimdRegAllocFindFree. */
2047	STAMCOUNTER StatNativeSimdRegFindFreeLivenessHelped;
2048
2049	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() checks. */
2050	STAMCOUNTER StatNativeMaybeDeviceNotAvailXcptCheckPotential;
2051	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() checks. */
2052	STAMCOUNTER StatNativeMaybeWaitDeviceNotAvailXcptCheckPotential;
2053	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() checks. */
2054	STAMCOUNTER StatNativeMaybeSseXcptCheckPotential;
2055	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() checks. */
2056	STAMCOUNTER StatNativeMaybeAvxXcptCheckPotential;
2057
2058	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() checks omitted. */
2059	STAMCOUNTER StatNativeMaybeDeviceNotAvailXcptCheckOmitted;
2060	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() checks omitted. */
2061	STAMCOUNTER StatNativeMaybeWaitDeviceNotAvailXcptCheckOmitted;
2062	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() checks omitted. */
2063	STAMCOUNTER StatNativeMaybeSseXcptCheckOmitted;
2064	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() checks omitted. */
2065	STAMCOUNTER StatNativeMaybeAvxXcptCheckOmitted;
2066	//#endif
2067
2068	/** Native recompiler: The TB finished executing completely without jumping to a an exit label. */
2069	STAMCOUNTER StatNativeTbFinished;
2070	/** Native recompiler: The TB finished executing jumping to the ReturnBreak label. */
2071	STAMCOUNTER StatNativeTbExitReturnBreak;
2072	/** Native recompiler: The TB finished executing jumping to the ReturnWithFlags label. */
2073	STAMCOUNTER StatNativeTbExitReturnWithFlags;
2074
2075	/** Native recompiler: The TB finished executing jumping to the RaiseDe label. */
2076	STAMCOUNTER StatNativeTbExitRaiseDe;
2077	/** Native recompiler: The TB finished executing jumping to the RaiseUd label. */
2078	STAMCOUNTER StatNativeTbExitRaiseUd;
2079	/** Native recompiler: The TB finished executing jumping to the RaiseSseRelated label. */
2080	STAMCOUNTER StatNativeTbExitRaiseSseRelated;
2081	/** Native recompiler: The TB finished executing jumping to the RaiseAvxRelated label. */
2082	STAMCOUNTER StatNativeTbExitRaiseAvxRelated;
2083	/** Native recompiler: The TB finished executing jumping to the RaiseSseAvxFpRelated label. */
2084	STAMCOUNTER StatNativeTbExitRaiseSseAvxFpRelated;
2085	/** Native recompiler: The TB finished executing jumping to the RaiseNm label. */
2086	STAMCOUNTER StatNativeTbExitRaiseNm;
2087	/** Native recompiler: The TB finished executing jumping to the RaiseGp0 label. */
2088	STAMCOUNTER StatNativeTbExitRaiseGp0;
2089	/** Native recompiler: The TB finished executing jumping to the RaiseMf label. */
2090	STAMCOUNTER StatNativeTbExitRaiseMf;
2091	/** Native recompiler: The TB finished executing jumping to the RaiseXf label. */
2092	STAMCOUNTER StatNativeTbExitRaiseXf;
2093	/** Native recompiler: The TB finished executing jumping to the ObsoleteTb label. */
2094	STAMCOUNTER StatNativeTbExitObsoleteTb;
2095
2096	uint64_t au64Padding[4];
2097	/** @} */
2098
2099	/** Data TLB.
2100	* @remarks Must be 64-byte aligned. */
2101	IEMTLB DataTlb;
2102	/** Instruction TLB.
2103	* @remarks Must be 64-byte aligned. */
2104	IEMTLB CodeTlb;
2105
2106	/** Exception statistics. */
2107	STAMCOUNTER aStatXcpts[32];
2108	/** Interrupt statistics. */
2109	uint32_t aStatInts[256];
2110
2111	#if defined(VBOX_WITH_STATISTICS) && !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
2112	/** Instruction statistics for ring-0/raw-mode. */
2113	IEMINSTRSTATS StatsRZ;
2114	/** Instruction statistics for ring-3. */
2115	IEMINSTRSTATS StatsR3;
2116	# ifdef VBOX_WITH_IEM_RECOMPILER
2117	/** Statistics per threaded function call.
2118	* Updated by both the threaded and native recompilers. */
2119	uint32_t acThreadedFuncStats[0x6000 /24576/];
2120	# endif
2121	#endif
2122	} IEMCPU;
2123	AssertCompileMemberOffset(IEMCPU, cActiveMappings, 0x4f);
2124	AssertCompileMemberAlignment(IEMCPU, aMemMappings, 16);
2125	AssertCompileMemberAlignment(IEMCPU, aMemMappingLocks, 16);
2126	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 64);
2127	AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
2128	AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
2129
2130	/** Pointer to the per-CPU IEM state. */
2131	typedef IEMCPU *PIEMCPU;
2132	/** Pointer to the const per-CPU IEM state. */
2133	typedef IEMCPU const *PCIEMCPU;
2134
2135
2136	/** @def IEM_GET_CTX
2137	* Gets the guest CPU context for the calling EMT.
2138	* @returns PCPUMCTX
2139	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2140	*/
2141	#define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
2142
2143	/** @def IEM_CTX_ASSERT
2144	* Asserts that the @a a_fExtrnMbz is present in the CPU context.
2145	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2146	* @param a_fExtrnMbz The mask of CPUMCTX_EXTRN_XXX flags that must be zero.
2147	*/
2148	#define IEM_CTX_ASSERT(a_pVCpu, a_fExtrnMbz) \
2149	AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
2150	("fExtrn=%#RX64 & fExtrnMbz=%#RX64 -> %#RX64\n", \
2151	(a_pVCpu)->cpum.GstCtx.fExtrn, (a_fExtrnMbz), (a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz) ))
2152
2153	/** @def IEM_CTX_IMPORT_RET
2154	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
2155	*
2156	* Will call the keep to import the bits as needed.
2157	*
2158	* Returns on import failure.
2159	*
2160	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2161	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
2162	*/
2163	#define IEM_CTX_IMPORT_RET(a_pVCpu, a_fExtrnImport) \
2164	do { \
2165	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
2166	{ /* likely */ } \
2167	else \
2168	{ \
2169	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
2170	AssertRCReturn(rcCtxImport, rcCtxImport); \
2171	} \
2172	} while (0)
2173
2174	/** @def IEM_CTX_IMPORT_NORET
2175	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
2176	*
2177	* Will call the keep to import the bits as needed.
2178	*
2179	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2180	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
2181	*/
2182	#define IEM_CTX_IMPORT_NORET(a_pVCpu, a_fExtrnImport) \
2183	do { \
2184	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
2185	{ /* likely */ } \
2186	else \
2187	{ \
2188	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
2189	AssertLogRelRC(rcCtxImport); \
2190	} \
2191	} while (0)
2192
2193	/** @def IEM_CTX_IMPORT_JMP
2194	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
2195	*
2196	* Will call the keep to import the bits as needed.
2197	*
2198	* Jumps on import failure.
2199	*
2200	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2201	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
2202	*/
2203	#define IEM_CTX_IMPORT_JMP(a_pVCpu, a_fExtrnImport) \
2204	do { \
2205	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
2206	{ /* likely */ } \
2207	else \
2208	{ \
2209	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
2210	AssertRCStmt(rcCtxImport, IEM_DO_LONGJMP(pVCpu, rcCtxImport)); \
2211	} \
2212	} while (0)
2213
2214
2215
2216	/** @def IEM_GET_TARGET_CPU
2217	* Gets the current IEMTARGETCPU value.
2218	* @returns IEMTARGETCPU value.
2219	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2220	*/
2221	#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
2222	# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
2223	#else
2224	# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
2225	#endif
2226
2227	/** @def IEM_GET_INSTR_LEN
2228	* Gets the instruction length. */
2229	#ifdef IEM_WITH_CODE_TLB
2230	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
2231	#else
2232	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
2233	#endif
2234
2235	/** @def IEM_TRY_SETJMP
2236	* Wrapper around setjmp / try, hiding all the ugly differences.
2237	*
2238	* @note Use with extreme care as this is a fragile macro.
2239	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2240	* @param a_rcTarget The variable that should receive the status code in case
2241	* of a longjmp/throw.
2242	*/
2243	/** @def IEM_TRY_SETJMP_AGAIN
2244	* For when setjmp / try is used again in the same variable scope as a previous
2245	* IEM_TRY_SETJMP invocation.
2246	*/
2247	/** @def IEM_CATCH_LONGJMP_BEGIN
2248	* Start wrapper for catch / setjmp-else.
2249	*
2250	* This will set up a scope.
2251	*
2252	* @note Use with extreme care as this is a fragile macro.
2253	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2254	* @param a_rcTarget The variable that should receive the status code in case
2255	* of a longjmp/throw.
2256	*/
2257	/** @def IEM_CATCH_LONGJMP_END
2258	* End wrapper for catch / setjmp-else.
2259	*
2260	* This will close the scope set up by IEM_CATCH_LONGJMP_BEGIN and clean up the
2261	* state.
2262	*
2263	* @note Use with extreme care as this is a fragile macro.
2264	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2265	*/
2266	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
2267	# ifdef IEM_WITH_THROW_CATCH
2268	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
2269	a_rcTarget = VINF_SUCCESS; \
2270	try
2271	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
2272	IEM_TRY_SETJMP(a_pVCpu, a_rcTarget)
2273	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
2274	catch (int rcThrown) \
2275	{ \
2276	a_rcTarget = rcThrown
2277	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
2278	} \
2279	((void)0)
2280	# else /* !IEM_WITH_THROW_CATCH */
2281	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
2282	jmp_buf JmpBuf; \
2283	jmp_buf * volatile pSavedJmpBuf = (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf); \
2284	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
2285	if ((rcStrict = setjmp(JmpBuf)) == 0)
2286	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
2287	pSavedJmpBuf = (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf); \
2288	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
2289	if ((rcStrict = setjmp(JmpBuf)) == 0)
2290	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
2291	else \
2292	{ \
2293	((void)0)
2294	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
2295	} \
2296	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = pSavedJmpBuf
2297	# endif /* !IEM_WITH_THROW_CATCH */
2298	#endif /* IEM_WITH_SETJMP */
2299
2300
2301	/**
2302	* Shared per-VM IEM data.
2303	*/
2304	typedef struct IEM
2305	{
2306	/** The VMX APIC-access page handler type. */
2307	PGMPHYSHANDLERTYPE hVmxApicAccessPage;
2308	#ifndef VBOX_WITHOUT_CPUID_HOST_CALL
2309	/** Set if the CPUID host call functionality is enabled. */
2310	bool fCpuIdHostCall;
2311	#endif
2312	} IEM;
2313
2314
2315
2316	/** @name IEM_ACCESS_XXX - Access details.
2317	* @{ */
2318	#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
2319	#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
2320	#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
2321	#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
2322	#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
2323	#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
2324	#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
2325	#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
2326	#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
2327	#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
2328	/** The writes are partial, so if initialize the bounce buffer with the
2329	* orignal RAM content. */
2330	#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
2331	/** Used in aMemMappings to indicate that the entry is bounce buffered. */
2332	#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
2333	/** Bounce buffer with ring-3 write pending, first page. */
2334	#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
2335	/** Bounce buffer with ring-3 write pending, second page. */
2336	#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
2337	/** Not locked, accessed via the TLB. */
2338	#define IEM_ACCESS_NOT_LOCKED UINT32_C(0x00001000)
2339	/** Atomic access.
2340	* This enables special alignment checks and the VINF_EM_EMULATE_SPLIT_LOCK
2341	* fallback for misaligned stuff. See @bugref{10547}. */
2342	#define IEM_ACCESS_ATOMIC UINT32_C(0x00002000)
2343	/** Valid bit mask. */
2344	#define IEM_ACCESS_VALID_MASK UINT32_C(0x00003fff)
2345	/** Shift count for the TLB flags (upper word). */
2346	#define IEM_ACCESS_SHIFT_TLB_FLAGS 16
2347
2348	/** Atomic read+write data alias. */
2349	#define IEM_ACCESS_DATA_ATOMIC (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA \| IEM_ACCESS_ATOMIC)
2350	/** Read+write data alias. */
2351	#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
2352	/** Write data alias. */
2353	#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
2354	/** Read data alias. */
2355	#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_DATA)
2356	/** Instruction fetch alias. */
2357	#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_WHAT_CODE)
2358	/** Stack write alias. */
2359	#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
2360	/** Stack read alias. */
2361	#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_STACK)
2362	/** Stack read+write alias. */
2363	#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
2364	/** Read system table alias. */
2365	#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_SYS)
2366	/** Read+write system table alias. */
2367	#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_SYS)
2368	/** @} */
2369
2370	/** @name Prefix constants (IEMCPU::fPrefixes)
2371	* @{ */
2372	#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /*< CS segment prefix (0x2e). /
2373	#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /*< SS segment prefix (0x36). /
2374	#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /*< DS segment prefix (0x3e). /
2375	#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /*< ES segment prefix (0x26). /
2376	#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /*< FS segment prefix (0x64). /
2377	#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /*< GS segment prefix (0x65). /
2378	#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
2379
2380	#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /*< Operand size prefix (0x66). /
2381	#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /*< REX.W prefix (0x48-0x4f). /
2382	#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /*< Address size prefix (0x67). /
2383
2384	#define IEM_OP_PRF_LOCK RT_BIT_32(16) /*< Lock prefix (0xf0). /
2385	#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /*< Repeat-not-zero prefix (0xf2). /
2386	#define IEM_OP_PRF_REPZ RT_BIT_32(18) /*< Repeat-if-zero prefix (0xf3). /
2387
2388	#define IEM_OP_PRF_REX RT_BIT_32(24) /*< Any REX prefix (0x40-0x4f). /
2389	#define IEM_OP_PRF_REX_B RT_BIT_32(25) /*< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). /
2390	#define IEM_OP_PRF_REX_X RT_BIT_32(26) /*< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). /
2391	#define IEM_OP_PRF_REX_R RT_BIT_32(27) /*< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). /
2392	/** Mask with all the REX prefix flags.
2393	* This is generally for use when needing to undo the REX prefixes when they
2394	* are followed legacy prefixes and therefore does not immediately preceed
2395	* the first opcode byte.
2396	* For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
2397	#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX \| IEM_OP_PRF_REX_R \| IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X \| IEM_OP_PRF_SIZE_REX_W )
2398
2399	#define IEM_OP_PRF_VEX RT_BIT_32(28) /*< Indiciates VEX prefix. /
2400	#define IEM_OP_PRF_EVEX RT_BIT_32(29) /*< Indiciates EVEX prefix. /
2401	#define IEM_OP_PRF_XOP RT_BIT_32(30) /*< Indiciates XOP prefix. /
2402	/** @} */
2403
2404	/** @name IEMOPFORM_XXX - Opcode forms
2405	* @note These are ORed together with IEMOPHINT_XXX.
2406	* @{ */
2407	/** ModR/M: reg, r/m */
2408	#define IEMOPFORM_RM 0
2409	/** ModR/M: reg, r/m (register) */
2410	#define IEMOPFORM_RM_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
2411	/** ModR/M: reg, r/m (memory) */
2412	#define IEMOPFORM_RM_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
2413	/** ModR/M: reg, r/m, imm */
2414	#define IEMOPFORM_RMI 1
2415	/** ModR/M: reg, r/m (register), imm */
2416	#define IEMOPFORM_RMI_REG (IEMOPFORM_RMI \| IEMOPFORM_MOD3)
2417	/** ModR/M: reg, r/m (memory), imm */
2418	#define IEMOPFORM_RMI_MEM (IEMOPFORM_RMI \| IEMOPFORM_NOT_MOD3)
2419	/** ModR/M: reg, r/m, xmm0 */
2420	#define IEMOPFORM_RM0 2
2421	/** ModR/M: reg, r/m (register), xmm0 */
2422	#define IEMOPFORM_RM0_REG (IEMOPFORM_RM0 \| IEMOPFORM_MOD3)
2423	/** ModR/M: reg, r/m (memory), xmm0 */
2424	#define IEMOPFORM_RM0_MEM (IEMOPFORM_RM0 \| IEMOPFORM_NOT_MOD3)
2425	/** ModR/M: r/m, reg */
2426	#define IEMOPFORM_MR 3
2427	/** ModR/M: r/m (register), reg */
2428	#define IEMOPFORM_MR_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
2429	/** ModR/M: r/m (memory), reg */
2430	#define IEMOPFORM_MR_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
2431	/** ModR/M: r/m, reg, imm */
2432	#define IEMOPFORM_MRI 4
2433	/** ModR/M: r/m (register), reg, imm */
2434	#define IEMOPFORM_MRI_REG (IEMOPFORM_MRI \| IEMOPFORM_MOD3)
2435	/** ModR/M: r/m (memory), reg, imm */
2436	#define IEMOPFORM_MRI_MEM (IEMOPFORM_MRI \| IEMOPFORM_NOT_MOD3)
2437	/** ModR/M: r/m only */
2438	#define IEMOPFORM_M 5
2439	/** ModR/M: r/m only (register). */
2440	#define IEMOPFORM_M_REG (IEMOPFORM_M \| IEMOPFORM_MOD3)
2441	/** ModR/M: r/m only (memory). */
2442	#define IEMOPFORM_M_MEM (IEMOPFORM_M \| IEMOPFORM_NOT_MOD3)
2443	/** ModR/M: r/m, imm */
2444	#define IEMOPFORM_MI 6
2445	/** ModR/M: r/m (register), imm */
2446	#define IEMOPFORM_MI_REG (IEMOPFORM_MI \| IEMOPFORM_MOD3)
2447	/** ModR/M: r/m (memory), imm */
2448	#define IEMOPFORM_MI_MEM (IEMOPFORM_MI \| IEMOPFORM_NOT_MOD3)
2449	/** ModR/M: r/m, 1 (shift and rotate instructions) */
2450	#define IEMOPFORM_M1 7
2451	/** ModR/M: r/m (register), 1. */
2452	#define IEMOPFORM_M1_REG (IEMOPFORM_M1 \| IEMOPFORM_MOD3)
2453	/** ModR/M: r/m (memory), 1. */
2454	#define IEMOPFORM_M1_MEM (IEMOPFORM_M1 \| IEMOPFORM_NOT_MOD3)
2455	/** ModR/M: r/m, CL (shift and rotate instructions)
2456	* @todo This should just've been a generic fixed register. But the python
2457	* code doesn't needs more convincing. */
2458	#define IEMOPFORM_M_CL 8
2459	/** ModR/M: r/m (register), CL. */
2460	#define IEMOPFORM_M_CL_REG (IEMOPFORM_M_CL \| IEMOPFORM_MOD3)
2461	/** ModR/M: r/m (memory), CL. */
2462	#define IEMOPFORM_M_CL_MEM (IEMOPFORM_M_CL \| IEMOPFORM_NOT_MOD3)
2463	/** ModR/M: reg only */
2464	#define IEMOPFORM_R 9
2465
2466	/** VEX+ModR/M: reg, r/m */
2467	#define IEMOPFORM_VEX_RM 16
2468	/** VEX+ModR/M: reg, r/m (register) */
2469	#define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM \| IEMOPFORM_MOD3)
2470	/** VEX+ModR/M: reg, r/m (memory) */
2471	#define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM \| IEMOPFORM_NOT_MOD3)
2472	/** VEX+ModR/M: r/m, reg */
2473	#define IEMOPFORM_VEX_MR 17
2474	/** VEX+ModR/M: r/m (register), reg */
2475	#define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR \| IEMOPFORM_MOD3)
2476	/** VEX+ModR/M: r/m (memory), reg */
2477	#define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR \| IEMOPFORM_NOT_MOD3)
2478	/** VEX+ModR/M: r/m, reg, imm8 */
2479	#define IEMOPFORM_VEX_MRI 18
2480	/** VEX+ModR/M: r/m (register), reg, imm8 */
2481	#define IEMOPFORM_VEX_MRI_REG (IEMOPFORM_VEX_MRI \| IEMOPFORM_MOD3)
2482	/** VEX+ModR/M: r/m (memory), reg, imm8 */
2483	#define IEMOPFORM_VEX_MRI_MEM (IEMOPFORM_VEX_MRI \| IEMOPFORM_NOT_MOD3)
2484	/** VEX+ModR/M: r/m only */
2485	#define IEMOPFORM_VEX_M 19
2486	/** VEX+ModR/M: r/m only (register). */
2487	#define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M \| IEMOPFORM_MOD3)
2488	/** VEX+ModR/M: r/m only (memory). */
2489	#define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M \| IEMOPFORM_NOT_MOD3)
2490	/** VEX+ModR/M: reg only */
2491	#define IEMOPFORM_VEX_R 20
2492	/** VEX+ModR/M: reg, vvvv, r/m */
2493	#define IEMOPFORM_VEX_RVM 21
2494	/** VEX+ModR/M: reg, vvvv, r/m (register). */
2495	#define IEMOPFORM_VEX_RVM_REG (IEMOPFORM_VEX_RVM \| IEMOPFORM_MOD3)
2496	/** VEX+ModR/M: reg, vvvv, r/m (memory). */
2497	#define IEMOPFORM_VEX_RVM_MEM (IEMOPFORM_VEX_RVM \| IEMOPFORM_NOT_MOD3)
2498	/** VEX+ModR/M: reg, vvvv, r/m, imm */
2499	#define IEMOPFORM_VEX_RVMI 22
2500	/** VEX+ModR/M: reg, vvvv, r/m (register), imm. */
2501	#define IEMOPFORM_VEX_RVMI_REG (IEMOPFORM_VEX_RVMI \| IEMOPFORM_MOD3)
2502	/** VEX+ModR/M: reg, vvvv, r/m (memory), imm. */
2503	#define IEMOPFORM_VEX_RVMI_MEM (IEMOPFORM_VEX_RVMI \| IEMOPFORM_NOT_MOD3)
2504	/** VEX+ModR/M: reg, vvvv, r/m, imm(reg) */
2505	#define IEMOPFORM_VEX_RVMR 23
2506	/** VEX+ModR/M: reg, vvvv, r/m (register), imm(reg). */
2507	#define IEMOPFORM_VEX_RVMR_REG (IEMOPFORM_VEX_RVMI \| IEMOPFORM_MOD3)
2508	/** VEX+ModR/M: reg, vvvv, r/m (memory), imm(reg). */
2509	#define IEMOPFORM_VEX_RVMR_MEM (IEMOPFORM_VEX_RVMI \| IEMOPFORM_NOT_MOD3)
2510	/** VEX+ModR/M: reg, r/m, vvvv */
2511	#define IEMOPFORM_VEX_RMV 24
2512	/** VEX+ModR/M: reg, r/m, vvvv (register). */
2513	#define IEMOPFORM_VEX_RMV_REG (IEMOPFORM_VEX_RMV \| IEMOPFORM_MOD3)
2514	/** VEX+ModR/M: reg, r/m, vvvv (memory). */
2515	#define IEMOPFORM_VEX_RMV_MEM (IEMOPFORM_VEX_RMV \| IEMOPFORM_NOT_MOD3)
2516	/** VEX+ModR/M: reg, r/m, imm8 */
2517	#define IEMOPFORM_VEX_RMI 25
2518	/** VEX+ModR/M: reg, r/m, imm8 (register). */
2519	#define IEMOPFORM_VEX_RMI_REG (IEMOPFORM_VEX_RMI \| IEMOPFORM_MOD3)
2520	/** VEX+ModR/M: reg, r/m, imm8 (memory). */
2521	#define IEMOPFORM_VEX_RMI_MEM (IEMOPFORM_VEX_RMI \| IEMOPFORM_NOT_MOD3)
2522	/** VEX+ModR/M: r/m, vvvv, reg */
2523	#define IEMOPFORM_VEX_MVR 26
2524	/** VEX+ModR/M: r/m, vvvv, reg (register) */
2525	#define IEMOPFORM_VEX_MVR_REG (IEMOPFORM_VEX_MVR \| IEMOPFORM_MOD3)
2526	/** VEX+ModR/M: r/m, vvvv, reg (memory) */
2527	#define IEMOPFORM_VEX_MVR_MEM (IEMOPFORM_VEX_MVR \| IEMOPFORM_NOT_MOD3)
2528	/** VEX+ModR/M+/n: vvvv, r/m */
2529	#define IEMOPFORM_VEX_VM 27
2530	/** VEX+ModR/M+/n: vvvv, r/m (register) */
2531	#define IEMOPFORM_VEX_VM_REG (IEMOPFORM_VEX_VM \| IEMOPFORM_MOD3)
2532	/** VEX+ModR/M+/n: vvvv, r/m (memory) */
2533	#define IEMOPFORM_VEX_VM_MEM (IEMOPFORM_VEX_VM \| IEMOPFORM_NOT_MOD3)
2534	/** VEX+ModR/M+/n: vvvv, r/m, imm8 */
2535	#define IEMOPFORM_VEX_VMI 28
2536	/** VEX+ModR/M+/n: vvvv, r/m, imm8 (register) */
2537	#define IEMOPFORM_VEX_VMI_REG (IEMOPFORM_VEX_VMI \| IEMOPFORM_MOD3)
2538	/** VEX+ModR/M+/n: vvvv, r/m, imm8 (memory) */
2539	#define IEMOPFORM_VEX_VMI_MEM (IEMOPFORM_VEX_VMI \| IEMOPFORM_NOT_MOD3)
2540
2541	/** Fixed register instruction, no R/M. */
2542	#define IEMOPFORM_FIXED 32
2543
2544	/** The r/m is a register. */
2545	#define IEMOPFORM_MOD3 RT_BIT_32(8)
2546	/** The r/m is a memory access. */
2547	#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
2548	/** @} */
2549
2550	/** @name IEMOPHINT_XXX - Additional Opcode Hints
2551	* @note These are ORed together with IEMOPFORM_XXX.
2552	* @{ */
2553	/** Ignores the operand size prefix (66h). */
2554	#define IEMOPHINT_IGNORES_OZ_PFX RT_BIT_32(10)
2555	/** Ignores REX.W (aka WIG). */
2556	#define IEMOPHINT_IGNORES_REXW RT_BIT_32(11)
2557	/** Both the operand size prefixes (66h + REX.W) are ignored. */
2558	#define IEMOPHINT_IGNORES_OP_SIZES (IEMOPHINT_IGNORES_OZ_PFX \| IEMOPHINT_IGNORES_REXW)
2559	/** Allowed with the lock prefix. */
2560	#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
2561	/** The VEX.L value is ignored (aka LIG). */
2562	#define IEMOPHINT_VEX_L_IGNORED RT_BIT_32(12)
2563	/** The VEX.L value must be zero (i.e. 128-bit width only). */
2564	#define IEMOPHINT_VEX_L_ZERO RT_BIT_32(13)
2565	/** The VEX.L value must be one (i.e. 256-bit width only). */
2566	#define IEMOPHINT_VEX_L_ONE RT_BIT_32(14)
2567	/** The VEX.V value must be zero. */
2568	#define IEMOPHINT_VEX_V_ZERO RT_BIT_32(15)
2569	/** The REX.W/VEX.V value must be zero. */
2570	#define IEMOPHINT_REX_W_ZERO RT_BIT_32(16)
2571	#define IEMOPHINT_VEX_W_ZERO IEMOPHINT_REX_W_ZERO
2572	/** The REX.W/VEX.V value must be one. */
2573	#define IEMOPHINT_REX_W_ONE RT_BIT_32(17)
2574	#define IEMOPHINT_VEX_W_ONE IEMOPHINT_REX_W_ONE
2575
2576	/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
2577	#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
2578	/** @} */
2579
2580	/**
2581	* Possible hardware task switch sources.
2582	*/
2583	typedef enum IEMTASKSWITCH
2584	{
2585	/** Task switch caused by an interrupt/exception. */
2586	IEMTASKSWITCH_INT_XCPT = 1,
2587	/** Task switch caused by a far CALL. */
2588	IEMTASKSWITCH_CALL,
2589	/** Task switch caused by a far JMP. */
2590	IEMTASKSWITCH_JUMP,
2591	/** Task switch caused by an IRET. */
2592	IEMTASKSWITCH_IRET
2593	} IEMTASKSWITCH;
2594	AssertCompileSize(IEMTASKSWITCH, 4);
2595
2596	/**
2597	* Possible CrX load (write) sources.
2598	*/
2599	typedef enum IEMACCESSCRX
2600	{
2601	/** CrX access caused by 'mov crX' instruction. */
2602	IEMACCESSCRX_MOV_CRX,
2603	/** CrX (CR0) write caused by 'lmsw' instruction. */
2604	IEMACCESSCRX_LMSW,
2605	/** CrX (CR0) write caused by 'clts' instruction. */
2606	IEMACCESSCRX_CLTS,
2607	/** CrX (CR0) read caused by 'smsw' instruction. */
2608	IEMACCESSCRX_SMSW
2609	} IEMACCESSCRX;
2610
2611	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2612	/** @name IEM_SLAT_FAIL_XXX - Second-level address translation failure information.
2613	*
2614	* These flags provide further context to SLAT page-walk failures that could not be
2615	* determined by PGM (e.g, PGM is not privy to memory access permissions).
2616	*
2617	* @{
2618	*/
2619	/** Translating a nested-guest linear address failed accessing a nested-guest
2620	* physical address. */
2621	# define IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR RT_BIT_32(0)
2622	/** Translating a nested-guest linear address failed accessing a
2623	* paging-structure entry or updating accessed/dirty bits. */
2624	# define IEM_SLAT_FAIL_LINEAR_TO_PAGE_TABLE RT_BIT_32(1)
2625	/** @} */
2626
2627	DECLCALLBACK(FNPGMPHYSHANDLER) iemVmxApicAccessPageHandler;
2628	# ifndef IN_RING3
2629	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) iemVmxApicAccessPagePfHandler;
2630	# endif
2631	#endif
2632
2633	/**
2634	* Indicates to the verifier that the given flag set is undefined.
2635	*
2636	* Can be invoked again to add more flags.
2637	*
2638	* This is a NOOP if the verifier isn't compiled in.
2639	*
2640	* @note We're temporarily keeping this until code is converted to new
2641	* disassembler style opcode handling.
2642	*/
2643	#define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
2644
2645
2646	/** @def IEM_DECL_IMPL_TYPE
2647	* For typedef'ing an instruction implementation function.
2648	*
2649	* @param a_RetType The return type.
2650	* @param a_Name The name of the type.
2651	* @param a_ArgList The argument list enclosed in parentheses.
2652	*/
2653
2654	/** @def IEM_DECL_IMPL_DEF
2655	* For defining an instruction implementation function.
2656	*
2657	* @param a_RetType The return type.
2658	* @param a_Name The name of the type.
2659	* @param a_ArgList The argument list enclosed in parentheses.
2660	*/
2661
2662	#if defined(__GNUC__) && defined(RT_ARCH_X86)
2663	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2664	__attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
2665	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2666	__attribute__((__fastcall__, __nothrow__)) DECL_HIDDEN_ONLY(a_RetType) a_Name a_ArgList
2667	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2668	__attribute__((__fastcall__, __nothrow__)) DECL_HIDDEN_ONLY(a_RetType) a_Name a_ArgList
2669
2670	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
2671	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2672	a_RetType (__fastcall a_Name) a_ArgList
2673	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2674	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
2675	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2676	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
2677
2678	#elif __cplusplus >= 201700 /* P0012R1 support */
2679	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2680	a_RetType (VBOXCALL a_Name) a_ArgList RT_NOEXCEPT
2681	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2682	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList RT_NOEXCEPT
2683	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2684	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList RT_NOEXCEPT
2685
2686	#else
2687	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2688	a_RetType (VBOXCALL a_Name) a_ArgList
2689	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2690	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList
2691	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2692	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList
2693
2694	#endif
2695
2696	/** Defined in IEMAllAImplC.cpp but also used by IEMAllAImplA.asm. */
2697	RT_C_DECLS_BEGIN
2698	extern uint8_t const g_afParity[256];
2699	RT_C_DECLS_END
2700
2701
2702	/** @name Arithmetic assignment operations on bytes (binary).
2703	* @{ */
2704	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU8, (uint32_t fEFlagsIn, uint8_t *pu8Dst, uint8_t u8Src));
2705	typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
2706	FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
2707	FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
2708	FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
2709	FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
2710	FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
2711	FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
2712	FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
2713	/** @} */
2714
2715	/** @name Arithmetic assignment operations on words (binary).
2716	* @{ */
2717	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU16, (uint32_t fEFlagsIn, uint16_t *pu16Dst, uint16_t u16Src));
2718	typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
2719	FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
2720	FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
2721	FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
2722	FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
2723	FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
2724	FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
2725	FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
2726	/** @} */
2727
2728
2729	/** @name Arithmetic assignment operations on double words (binary).
2730	* @{ */
2731	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU32, (uint32_t fEFlagsIn, uint32_t *pu32Dst, uint32_t u32Src));
2732	typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
2733	FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
2734	FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
2735	FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
2736	FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
2737	FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
2738	FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
2739	FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
2740	FNIEMAIMPLBINU32 iemAImpl_blsi_u32, iemAImpl_blsi_u32_fallback;
2741	FNIEMAIMPLBINU32 iemAImpl_blsr_u32, iemAImpl_blsr_u32_fallback;
2742	FNIEMAIMPLBINU32 iemAImpl_blsmsk_u32, iemAImpl_blsmsk_u32_fallback;
2743	/** @} */
2744
2745	/** @name Arithmetic assignment operations on quad words (binary).
2746	* @{ */
2747	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU64, (uint32_t fEFlagsIn, uint64_t *pu64Dst, uint64_t u64Src));
2748	typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
2749	FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
2750	FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
2751	FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
2752	FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
2753	FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
2754	FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
2755	FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
2756	FNIEMAIMPLBINU64 iemAImpl_blsi_u64, iemAImpl_blsi_u64_fallback;
2757	FNIEMAIMPLBINU64 iemAImpl_blsr_u64, iemAImpl_blsr_u64_fallback;
2758	FNIEMAIMPLBINU64 iemAImpl_blsmsk_u64, iemAImpl_blsmsk_u64_fallback;
2759	/** @} */
2760
2761	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU8, (uint32_t fEFlagsIn, uint8_t const *pu8Dst, uint8_t u8Src));
2762	typedef FNIEMAIMPLBINROU8 *PFNIEMAIMPLBINROU8;
2763	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU16,(uint32_t fEFlagsIn, uint16_t const *pu16Dst, uint16_t u16Src));
2764	typedef FNIEMAIMPLBINROU16 *PFNIEMAIMPLBINROU16;
2765	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU32,(uint32_t fEFlagsIn, uint32_t const *pu32Dst, uint32_t u32Src));
2766	typedef FNIEMAIMPLBINROU32 *PFNIEMAIMPLBINROU32;
2767	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU64,(uint32_t fEFlagsIn, uint64_t const *pu64Dst, uint64_t u64Src));
2768	typedef FNIEMAIMPLBINROU64 *PFNIEMAIMPLBINROU64;
2769
2770	/** @name Compare operations (thrown in with the binary ops).
2771	* @{ */
2772	FNIEMAIMPLBINROU8 iemAImpl_cmp_u8;
2773	FNIEMAIMPLBINROU16 iemAImpl_cmp_u16;
2774	FNIEMAIMPLBINROU32 iemAImpl_cmp_u32;
2775	FNIEMAIMPLBINROU64 iemAImpl_cmp_u64;
2776	/** @} */
2777
2778	/** @name Test operations (thrown in with the binary ops).
2779	* @{ */
2780	FNIEMAIMPLBINROU8 iemAImpl_test_u8;
2781	FNIEMAIMPLBINROU16 iemAImpl_test_u16;
2782	FNIEMAIMPLBINROU32 iemAImpl_test_u32;
2783	FNIEMAIMPLBINROU64 iemAImpl_test_u64;
2784	/** @} */
2785
2786	/** @name Bit operations operations (thrown in with the binary ops).
2787	* @{ */
2788	FNIEMAIMPLBINROU16 iemAImpl_bt_u16;
2789	FNIEMAIMPLBINROU32 iemAImpl_bt_u32;
2790	FNIEMAIMPLBINROU64 iemAImpl_bt_u64;
2791	FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
2792	FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
2793	FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
2794	FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
2795	FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
2796	FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
2797	FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
2798	FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
2799	FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
2800	/** @} */
2801
2802	/** @name Arithmetic three operand operations on double words (binary).
2803	* @{ */
2804	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32, (uint32_t pu32Dst, uint32_t u32Src1, uint32_t u32Src2, uint32_t pEFlags));
2805	typedef FNIEMAIMPLBINVEXU32 *PFNIEMAIMPLBINVEXU32;
2806	FNIEMAIMPLBINVEXU32 iemAImpl_andn_u32, iemAImpl_andn_u32_fallback;
2807	FNIEMAIMPLBINVEXU32 iemAImpl_bextr_u32, iemAImpl_bextr_u32_fallback;
2808	FNIEMAIMPLBINVEXU32 iemAImpl_bzhi_u32, iemAImpl_bzhi_u32_fallback;
2809	/** @} */
2810
2811	/** @name Arithmetic three operand operations on quad words (binary).
2812	* @{ */
2813	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64, (uint64_t pu64Dst, uint64_t u64Src1, uint64_t u64Src2, uint32_t pEFlags));
2814	typedef FNIEMAIMPLBINVEXU64 *PFNIEMAIMPLBINVEXU64;
2815	FNIEMAIMPLBINVEXU64 iemAImpl_andn_u64, iemAImpl_andn_u64_fallback;
2816	FNIEMAIMPLBINVEXU64 iemAImpl_bextr_u64, iemAImpl_bextr_u64_fallback;
2817	FNIEMAIMPLBINVEXU64 iemAImpl_bzhi_u64, iemAImpl_bzhi_u64_fallback;
2818	/** @} */
2819
2820	/** @name Arithmetic three operand operations on double words w/o EFLAGS (binary).
2821	* @{ */
2822	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32NOEFL, (uint32_t *pu32Dst, uint32_t u32Src1, uint32_t u32Src2));
2823	typedef FNIEMAIMPLBINVEXU32NOEFL *PFNIEMAIMPLBINVEXU32NOEFL;
2824	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pdep_u32, iemAImpl_pdep_u32_fallback;
2825	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pext_u32, iemAImpl_pext_u32_fallback;
2826	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_sarx_u32, iemAImpl_sarx_u32_fallback;
2827	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shlx_u32, iemAImpl_shlx_u32_fallback;
2828	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shrx_u32, iemAImpl_shrx_u32_fallback;
2829	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_rorx_u32;
2830	/** @} */
2831
2832	/** @name Arithmetic three operand operations on quad words w/o EFLAGS (binary).
2833	* @{ */
2834	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64NOEFL, (uint64_t *pu64Dst, uint64_t u64Src1, uint64_t u64Src2));
2835	typedef FNIEMAIMPLBINVEXU64NOEFL *PFNIEMAIMPLBINVEXU64NOEFL;
2836	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pdep_u64, iemAImpl_pdep_u64_fallback;
2837	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pext_u64, iemAImpl_pext_u64_fallback;
2838	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_sarx_u64, iemAImpl_sarx_u64_fallback;
2839	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shlx_u64, iemAImpl_shlx_u64_fallback;
2840	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shrx_u64, iemAImpl_shrx_u64_fallback;
2841	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_rorx_u64;
2842	/** @} */
2843
2844	/** @name MULX 32-bit and 64-bit.
2845	* @{ */
2846	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU32, (uint32_t puDst1, uint32_t puDst2, uint32_t uSrc1, uint32_t uSrc2));
2847	typedef FNIEMAIMPLMULXVEXU32 *PFNIEMAIMPLMULXVEXU32;
2848	FNIEMAIMPLMULXVEXU32 iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback;
2849
2850	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU64, (uint64_t puDst1, uint64_t puDst2, uint64_t uSrc1, uint64_t uSrc2));
2851	typedef FNIEMAIMPLMULXVEXU64 *PFNIEMAIMPLMULXVEXU64;
2852	FNIEMAIMPLMULXVEXU64 iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback;
2853	/** @} */
2854
2855
2856	/** @name Exchange memory with register operations.
2857	* @{ */
2858	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_locked, (uint8_t pu8Mem, uint8_t pu8Reg));
2859	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_locked,(uint16_t pu16Mem, uint16_t pu16Reg));
2860	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_locked,(uint32_t pu32Mem, uint32_t pu32Reg));
2861	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_locked,(uint64_t pu64Mem, uint64_t pu64Reg));
2862	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_unlocked, (uint8_t pu8Mem, uint8_t pu8Reg));
2863	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_unlocked,(uint16_t pu16Mem, uint16_t pu16Reg));
2864	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_unlocked,(uint32_t pu32Mem, uint32_t pu32Reg));
2865	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_unlocked,(uint64_t pu64Mem, uint64_t pu64Reg));
2866	/** @} */
2867
2868	/** @name Exchange and add operations.
2869	* @{ */
2870	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
2871	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
2872	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
2873	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
2874	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
2875	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
2876	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
2877	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
2878	/** @} */
2879
2880	/** @name Compare and exchange.
2881	* @{ */
2882	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
2883	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
2884	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
2885	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
2886	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
2887	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
2888	#if ARCH_BITS == 32
2889	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
2890	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
2891	#else
2892	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
2893	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
2894	#endif
2895	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
2896	uint32_t *pEFlags));
2897	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
2898	uint32_t *pEFlags));
2899	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
2900	uint32_t *pEFlags));
2901	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
2902	uint32_t *pEFlags));
2903	#ifndef RT_ARCH_ARM64
2904	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
2905	PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
2906	#endif
2907	/** @} */
2908
2909	/** @name Memory ordering
2910	* @{ */
2911	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
2912	typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
2913	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
2914	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
2915	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
2916	#ifndef RT_ARCH_ARM64
2917	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
2918	#endif
2919	/** @} */
2920
2921	/** @name Double precision shifts
2922	* @{ */
2923	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t pEFlags));
2924	typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
2925	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t pEFlags));
2926	typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
2927	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t pEFlags));
2928	typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
2929	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16, iemAImpl_shld_u16_amd, iemAImpl_shld_u16_intel;
2930	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32, iemAImpl_shld_u32_amd, iemAImpl_shld_u32_intel;
2931	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64, iemAImpl_shld_u64_amd, iemAImpl_shld_u64_intel;
2932	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16, iemAImpl_shrd_u16_amd, iemAImpl_shrd_u16_intel;
2933	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32, iemAImpl_shrd_u32_amd, iemAImpl_shrd_u32_intel;
2934	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64, iemAImpl_shrd_u64_amd, iemAImpl_shrd_u64_intel;
2935	/** @} */
2936
2937
2938	/** @name Bit search operations (thrown in with the binary ops).
2939	* @{ */
2940	FNIEMAIMPLBINU16 iemAImpl_bsf_u16, iemAImpl_bsf_u16_amd, iemAImpl_bsf_u16_intel;
2941	FNIEMAIMPLBINU32 iemAImpl_bsf_u32, iemAImpl_bsf_u32_amd, iemAImpl_bsf_u32_intel;
2942	FNIEMAIMPLBINU64 iemAImpl_bsf_u64, iemAImpl_bsf_u64_amd, iemAImpl_bsf_u64_intel;
2943	FNIEMAIMPLBINU16 iemAImpl_bsr_u16, iemAImpl_bsr_u16_amd, iemAImpl_bsr_u16_intel;
2944	FNIEMAIMPLBINU32 iemAImpl_bsr_u32, iemAImpl_bsr_u32_amd, iemAImpl_bsr_u32_intel;
2945	FNIEMAIMPLBINU64 iemAImpl_bsr_u64, iemAImpl_bsr_u64_amd, iemAImpl_bsr_u64_intel;
2946	FNIEMAIMPLBINU16 iemAImpl_lzcnt_u16, iemAImpl_lzcnt_u16_amd, iemAImpl_lzcnt_u16_intel;
2947	FNIEMAIMPLBINU32 iemAImpl_lzcnt_u32, iemAImpl_lzcnt_u32_amd, iemAImpl_lzcnt_u32_intel;
2948	FNIEMAIMPLBINU64 iemAImpl_lzcnt_u64, iemAImpl_lzcnt_u64_amd, iemAImpl_lzcnt_u64_intel;
2949	FNIEMAIMPLBINU16 iemAImpl_tzcnt_u16, iemAImpl_tzcnt_u16_amd, iemAImpl_tzcnt_u16_intel;
2950	FNIEMAIMPLBINU32 iemAImpl_tzcnt_u32, iemAImpl_tzcnt_u32_amd, iemAImpl_tzcnt_u32_intel;
2951	FNIEMAIMPLBINU64 iemAImpl_tzcnt_u64, iemAImpl_tzcnt_u64_amd, iemAImpl_tzcnt_u64_intel;
2952	FNIEMAIMPLBINU16 iemAImpl_popcnt_u16, iemAImpl_popcnt_u16_fallback;
2953	FNIEMAIMPLBINU32 iemAImpl_popcnt_u32, iemAImpl_popcnt_u32_fallback;
2954	FNIEMAIMPLBINU64 iemAImpl_popcnt_u64, iemAImpl_popcnt_u64_fallback;
2955	/** @} */
2956
2957	/** @name Signed multiplication operations (thrown in with the binary ops).
2958	* @{ */
2959	FNIEMAIMPLBINU16 iemAImpl_imul_two_u16, iemAImpl_imul_two_u16_amd, iemAImpl_imul_two_u16_intel;
2960	FNIEMAIMPLBINU32 iemAImpl_imul_two_u32, iemAImpl_imul_two_u32_amd, iemAImpl_imul_two_u32_intel;
2961	FNIEMAIMPLBINU64 iemAImpl_imul_two_u64, iemAImpl_imul_two_u64_amd, iemAImpl_imul_two_u64_intel;
2962	/** @} */
2963
2964	/** @name Arithmetic assignment operations on bytes (unary).
2965	* @{ */
2966	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t pu8Dst, uint32_t pEFlags));
2967	typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
2968	FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
2969	FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
2970	FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
2971	FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
2972	/** @} */
2973
2974	/** @name Arithmetic assignment operations on words (unary).
2975	* @{ */
2976	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t pu16Dst, uint32_t pEFlags));
2977	typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
2978	FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
2979	FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
2980	FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
2981	FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
2982	/** @} */
2983
2984	/** @name Arithmetic assignment operations on double words (unary).
2985	* @{ */
2986	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t pu32Dst, uint32_t pEFlags));
2987	typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
2988	FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
2989	FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
2990	FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
2991	FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
2992	/** @} */
2993
2994	/** @name Arithmetic assignment operations on quad words (unary).
2995	* @{ */
2996	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t pu64Dst, uint32_t pEFlags));
2997	typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
2998	FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
2999	FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
3000	FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
3001	FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
3002	/** @} */
3003
3004
3005	/** @name Shift operations on bytes (Group 2).
3006	* @{ */
3007	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU8,(uint32_t fEFlagsIn, uint8_t *pu8Dst, uint8_t cShift));
3008	typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
3009	FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8, iemAImpl_rol_u8_amd, iemAImpl_rol_u8_intel;
3010	FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8, iemAImpl_ror_u8_amd, iemAImpl_ror_u8_intel;
3011	FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8, iemAImpl_rcl_u8_amd, iemAImpl_rcl_u8_intel;
3012	FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8, iemAImpl_rcr_u8_amd, iemAImpl_rcr_u8_intel;
3013	FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8, iemAImpl_shl_u8_amd, iemAImpl_shl_u8_intel;
3014	FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8, iemAImpl_shr_u8_amd, iemAImpl_shr_u8_intel;
3015	FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8, iemAImpl_sar_u8_amd, iemAImpl_sar_u8_intel;
3016	/** @} */
3017
3018	/** @name Shift operations on words (Group 2).
3019	* @{ */
3020	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU16,(uint32_t fEFlagsIn, uint16_t *pu16Dst, uint8_t cShift));
3021	typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
3022	FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16, iemAImpl_rol_u16_amd, iemAImpl_rol_u16_intel;
3023	FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16, iemAImpl_ror_u16_amd, iemAImpl_ror_u16_intel;
3024	FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16, iemAImpl_rcl_u16_amd, iemAImpl_rcl_u16_intel;
3025	FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16, iemAImpl_rcr_u16_amd, iemAImpl_rcr_u16_intel;
3026	FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16, iemAImpl_shl_u16_amd, iemAImpl_shl_u16_intel;
3027	FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16, iemAImpl_shr_u16_amd, iemAImpl_shr_u16_intel;
3028	FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16, iemAImpl_sar_u16_amd, iemAImpl_sar_u16_intel;
3029	/** @} */
3030
3031	/** @name Shift operations on double words (Group 2).
3032	* @{ */
3033	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU32,(uint32_t fEFlagsIn, uint32_t *pu32Dst, uint8_t cShift));
3034	typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
3035	FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32, iemAImpl_rol_u32_amd, iemAImpl_rol_u32_intel;
3036	FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32, iemAImpl_ror_u32_amd, iemAImpl_ror_u32_intel;
3037	FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32, iemAImpl_rcl_u32_amd, iemAImpl_rcl_u32_intel;
3038	FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32, iemAImpl_rcr_u32_amd, iemAImpl_rcr_u32_intel;
3039	FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32, iemAImpl_shl_u32_amd, iemAImpl_shl_u32_intel;
3040	FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32, iemAImpl_shr_u32_amd, iemAImpl_shr_u32_intel;
3041	FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32, iemAImpl_sar_u32_amd, iemAImpl_sar_u32_intel;
3042	/** @} */
3043
3044	/** @name Shift operations on words (Group 2).
3045	* @{ */
3046	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU64,(uint32_t fEFlagsIn, uint64_t *pu64Dst, uint8_t cShift));
3047	typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
3048	FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64, iemAImpl_rol_u64_amd, iemAImpl_rol_u64_intel;
3049	FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64, iemAImpl_ror_u64_amd, iemAImpl_ror_u64_intel;
3050	FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64, iemAImpl_rcl_u64_amd, iemAImpl_rcl_u64_intel;
3051	FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64, iemAImpl_rcr_u64_amd, iemAImpl_rcr_u64_intel;
3052	FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64, iemAImpl_shl_u64_amd, iemAImpl_shl_u64_intel;
3053	FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64, iemAImpl_shr_u64_amd, iemAImpl_shr_u64_intel;
3054	FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64, iemAImpl_sar_u64_amd, iemAImpl_sar_u64_intel;
3055	/** @} */
3056
3057	/** @name Multiplication and division operations.
3058	* @{ */
3059	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t pu16AX, uint8_t u8FactorDivisor, uint32_t pEFlags));
3060	typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
3061	FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_mul_u8_amd, iemAImpl_mul_u8_intel;
3062	FNIEMAIMPLMULDIVU8 iemAImpl_imul_u8, iemAImpl_imul_u8_amd, iemAImpl_imul_u8_intel;
3063	FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_div_u8_amd, iemAImpl_div_u8_intel;
3064	FNIEMAIMPLMULDIVU8 iemAImpl_idiv_u8, iemAImpl_idiv_u8_amd, iemAImpl_idiv_u8_intel;
3065
3066	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t pu16AX, uint16_t pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
3067	typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
3068	FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_mul_u16_amd, iemAImpl_mul_u16_intel;
3069	FNIEMAIMPLMULDIVU16 iemAImpl_imul_u16, iemAImpl_imul_u16_amd, iemAImpl_imul_u16_intel;
3070	FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_div_u16_amd, iemAImpl_div_u16_intel;
3071	FNIEMAIMPLMULDIVU16 iemAImpl_idiv_u16, iemAImpl_idiv_u16_amd, iemAImpl_idiv_u16_intel;
3072
3073	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t pu32EAX, uint32_t pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
3074	typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
3075	FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_mul_u32_amd, iemAImpl_mul_u32_intel;
3076	FNIEMAIMPLMULDIVU32 iemAImpl_imul_u32, iemAImpl_imul_u32_amd, iemAImpl_imul_u32_intel;
3077	FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_div_u32_amd, iemAImpl_div_u32_intel;
3078	FNIEMAIMPLMULDIVU32 iemAImpl_idiv_u32, iemAImpl_idiv_u32_amd, iemAImpl_idiv_u32_intel;
3079
3080	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t pu64RAX, uint64_t pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
3081	typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
3082	FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_mul_u64_amd, iemAImpl_mul_u64_intel;
3083	FNIEMAIMPLMULDIVU64 iemAImpl_imul_u64, iemAImpl_imul_u64_amd, iemAImpl_imul_u64_intel;
3084	FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_div_u64_amd, iemAImpl_div_u64_intel;
3085	FNIEMAIMPLMULDIVU64 iemAImpl_idiv_u64, iemAImpl_idiv_u64_amd, iemAImpl_idiv_u64_intel;
3086	/** @} */
3087
3088	/** @name Byte Swap.
3089	* @{ */
3090	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t pu32Dst)); / Yes, 32-bit register access. */
3091	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
3092	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
3093	/** @} */
3094
3095	/** @name Misc.
3096	* @{ */
3097	FNIEMAIMPLBINU16 iemAImpl_arpl;
3098	/** @} */
3099
3100	/** @name RDRAND and RDSEED
3101	* @{ */
3102	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU16,(uint16_t puDst, uint32_t pEFlags));
3103	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU32,(uint32_t puDst, uint32_t pEFlags));
3104	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU64,(uint64_t puDst, uint32_t pEFlags));
3105	typedef FNIEMAIMPLRDRANDSEEDU16 *PFNIEMAIMPLRDRANDSEEDU16;
3106	typedef FNIEMAIMPLRDRANDSEEDU32 *PFNIEMAIMPLRDRANDSEEDU32;
3107	typedef FNIEMAIMPLRDRANDSEEDU64 *PFNIEMAIMPLRDRANDSEEDU64;
3108
3109	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdrand_u16, iemAImpl_rdrand_u16_fallback;
3110	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdrand_u32, iemAImpl_rdrand_u32_fallback;
3111	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdrand_u64, iemAImpl_rdrand_u64_fallback;
3112	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdseed_u16, iemAImpl_rdseed_u16_fallback;
3113	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdseed_u32, iemAImpl_rdseed_u32_fallback;
3114	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdseed_u64, iemAImpl_rdseed_u64_fallback;
3115	/** @} */
3116
3117	/** @name ADOX and ADCX
3118	* @{ */
3119	FNIEMAIMPLBINU32 iemAImpl_adcx_u32, iemAImpl_adcx_u32_fallback;
3120	FNIEMAIMPLBINU64 iemAImpl_adcx_u64, iemAImpl_adcx_u64_fallback;
3121	FNIEMAIMPLBINU32 iemAImpl_adox_u32, iemAImpl_adox_u32_fallback;
3122	FNIEMAIMPLBINU64 iemAImpl_adox_u64, iemAImpl_adox_u64_fallback;
3123	/** @} */
3124
3125	/** @name FPU operations taking a 32-bit float argument
3126	* @{ */
3127	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3128	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
3129	typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
3130
3131	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3132	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
3133	typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
3134
3135	FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
3136	FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
3137	FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
3138	FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
3139	FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
3140	FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
3141	FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
3142
3143	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
3144	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3145	PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
3146	/** @} */
3147
3148	/** @name FPU operations taking a 64-bit float argument
3149	* @{ */
3150	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3151	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
3152	typedef FNIEMAIMPLFPUR64FSW *PFNIEMAIMPLFPUR64FSW;
3153
3154	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3155	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
3156	typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
3157
3158	FNIEMAIMPLFPUR64FSW iemAImpl_fcom_r80_by_r64;
3159	FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
3160	FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
3161	FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
3162	FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
3163	FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
3164	FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
3165
3166	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
3167	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3168	PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
3169	/** @} */
3170
3171	/** @name FPU operations taking a 80-bit float argument
3172	* @{ */
3173	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3174	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
3175	typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
3176	FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
3177	FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
3178	FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
3179	FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
3180	FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
3181	FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
3182	FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
3183	FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
3184	FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
3185
3186	FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80, iemAImpl_fpatan_r80_by_r80_amd, iemAImpl_fpatan_r80_by_r80_intel;
3187	FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80, iemAImpl_fyl2x_r80_by_r80_amd, iemAImpl_fyl2x_r80_by_r80_intel;
3188	FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80, iemAImpl_fyl2xp1_r80_by_r80_amd, iemAImpl_fyl2xp1_r80_by_r80_intel;
3189
3190	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3191	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
3192	typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
3193	FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
3194	FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
3195
3196	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
3197	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
3198	typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
3199	FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
3200	FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
3201
3202	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
3203	typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
3204	FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
3205	FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
3206	FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80, iemAImpl_f2xm1_r80_amd, iemAImpl_f2xm1_r80_intel;
3207	FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
3208	FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
3209	FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80, iemAImpl_fsin_r80_amd, iemAImpl_fsin_r80_intel;
3210	FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80, iemAImpl_fcos_r80_amd, iemAImpl_fcos_r80_intel;
3211
3212	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
3213	typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
3214	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
3215	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
3216
3217	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
3218	typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
3219	FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
3220	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
3221	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
3222	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
3223	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
3224	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
3225	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
3226
3227	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
3228	PCRTFLOAT80U pr80Val));
3229	typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
3230	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80, iemAImpl_fptan_r80_r80_amd, iemAImpl_fptan_r80_r80_intel;
3231	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
3232	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80, iemAImpl_fsincos_r80_r80_amd, iemAImpl_fsincos_r80_r80_intel;
3233
3234	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
3235	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3236	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
3237
3238	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_d80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTPBCD80U pd80Val));
3239	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_d80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3240	PRTPBCD80U pd80Dst, PCRTFLOAT80U pr80Src));
3241
3242	/** @} */
3243
3244	/** @name FPU operations taking a 16-bit signed integer argument
3245	* @{ */
3246	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3247	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
3248	typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
3249	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI16,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3250	int16_t *pi16Dst, PCRTFLOAT80U pr80Src));
3251	typedef FNIEMAIMPLFPUSTR80TOI16 *PFNIEMAIMPLFPUSTR80TOI16;
3252
3253	FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
3254	FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
3255	FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
3256	FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
3257	FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
3258	FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
3259
3260	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3261	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
3262	typedef FNIEMAIMPLFPUI16FSW *PFNIEMAIMPLFPUI16FSW;
3263	FNIEMAIMPLFPUI16FSW iemAImpl_ficom_r80_by_i16;
3264
3265	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
3266	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fist_r80_to_i16;
3267	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fistt_r80_to_i16, iemAImpl_fistt_r80_to_i16_amd, iemAImpl_fistt_r80_to_i16_intel;
3268	/** @} */
3269
3270	/** @name FPU operations taking a 32-bit signed integer argument
3271	* @{ */
3272	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3273	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
3274	typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
3275	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI32,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3276	int32_t *pi32Dst, PCRTFLOAT80U pr80Src));
3277	typedef FNIEMAIMPLFPUSTR80TOI32 *PFNIEMAIMPLFPUSTR80TOI32;
3278
3279	FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
3280	FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
3281	FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
3282	FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
3283	FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
3284	FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
3285
3286	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3287	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
3288	typedef FNIEMAIMPLFPUI32FSW *PFNIEMAIMPLFPUI32FSW;
3289	FNIEMAIMPLFPUI32FSW iemAImpl_ficom_r80_by_i32;
3290
3291	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
3292	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fist_r80_to_i32;
3293	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fistt_r80_to_i32;
3294	/** @} */
3295
3296	/** @name FPU operations taking a 64-bit signed integer argument
3297	* @{ */
3298	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI64,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3299	int64_t *pi64Dst, PCRTFLOAT80U pr80Src));
3300	typedef FNIEMAIMPLFPUSTR80TOI64 *PFNIEMAIMPLFPUSTR80TOI64;
3301
3302	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
3303	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fist_r80_to_i64;
3304	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fistt_r80_to_i64;
3305	/** @} */
3306
3307
3308	/** Temporary type representing a 256-bit vector register. */
3309	typedef struct { uint64_t au64[4]; } IEMVMM256;
3310	/** Temporary type pointing to a 256-bit vector register. */
3311	typedef IEMVMM256 *PIEMVMM256;
3312	/** Temporary type pointing to a const 256-bit vector register. */
3313	typedef IEMVMM256 *PCIEMVMM256;
3314
3315
3316	/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
3317	* @{ */
3318	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t puDst, uint64_t const puSrc));
3319	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
3320	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U128,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
3321	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
3322	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U128,(PX86XSAVEAREA pExtState, PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
3323	typedef FNIEMAIMPLMEDIAF3U128 *PFNIEMAIMPLMEDIAF3U128;
3324	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U256,(PX86XSAVEAREA pExtState, PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
3325	typedef FNIEMAIMPLMEDIAF3U256 *PFNIEMAIMPLMEDIAF3U256;
3326	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U64,(uint64_t puDst, uint64_t const puSrc));
3327	typedef FNIEMAIMPLMEDIAOPTF2U64 *PFNIEMAIMPLMEDIAOPTF2U64;
3328	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128,(PRTUINT128U puDst, PCRTUINT128U puSrc));
3329	typedef FNIEMAIMPLMEDIAOPTF2U128 *PFNIEMAIMPLMEDIAOPTF2U128;
3330	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
3331	typedef FNIEMAIMPLMEDIAOPTF3U128 *PFNIEMAIMPLMEDIAOPTF3U128;
3332	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
3333	typedef FNIEMAIMPLMEDIAOPTF3U256 *PFNIEMAIMPLMEDIAOPTF3U256;
3334	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256,(PRTUINT256U puDst, PCRTUINT256U puSrc));
3335	typedef FNIEMAIMPLMEDIAOPTF2U256 *PFNIEMAIMPLMEDIAOPTF2U256;
3336	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pshufb_u64, iemAImpl_pshufb_u64_fallback;
3337	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pand_u64, iemAImpl_pandn_u64, iemAImpl_por_u64, iemAImpl_pxor_u64;
3338	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
3339	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pcmpgtb_u64, iemAImpl_pcmpgtw_u64, iemAImpl_pcmpgtd_u64;
3340	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddb_u64, iemAImpl_paddsb_u64, iemAImpl_paddusb_u64;
3341	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddw_u64, iemAImpl_paddsw_u64, iemAImpl_paddusw_u64;
3342	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddd_u64;
3343	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddq_u64;
3344	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubb_u64, iemAImpl_psubsb_u64, iemAImpl_psubusb_u64;
3345	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubw_u64, iemAImpl_psubsw_u64, iemAImpl_psubusw_u64;
3346	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubd_u64;
3347	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubq_u64;
3348	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmaddwd_u64, iemAImpl_pmaddwd_u64_fallback;
3349	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmullw_u64, iemAImpl_pmulhw_u64;
3350	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pminub_u64, iemAImpl_pmaxub_u64;
3351	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pminsw_u64, iemAImpl_pmaxsw_u64;
3352	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pabsb_u64, iemAImpl_pabsb_u64_fallback;
3353	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pabsw_u64, iemAImpl_pabsw_u64_fallback;
3354	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pabsd_u64, iemAImpl_pabsd_u64_fallback;
3355	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psignb_u64, iemAImpl_psignb_u64_fallback;
3356	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psignw_u64, iemAImpl_psignw_u64_fallback;
3357	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psignd_u64, iemAImpl_psignd_u64_fallback;
3358	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phaddw_u64, iemAImpl_phaddw_u64_fallback;
3359	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phaddd_u64, iemAImpl_phaddd_u64_fallback;
3360	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phsubw_u64, iemAImpl_phsubw_u64_fallback;
3361	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phsubd_u64, iemAImpl_phsubd_u64_fallback;
3362	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phaddsw_u64, iemAImpl_phaddsw_u64_fallback;
3363	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phsubsw_u64, iemAImpl_phsubsw_u64_fallback;
3364	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmaddubsw_u64, iemAImpl_pmaddubsw_u64_fallback;
3365	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhrsw_u64, iemAImpl_pmulhrsw_u64_fallback;
3366	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmuludq_u64;
3367	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllw_u64, iemAImpl_psrlw_u64, iemAImpl_psraw_u64;
3368	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pslld_u64, iemAImpl_psrld_u64, iemAImpl_psrad_u64;
3369	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllq_u64, iemAImpl_psrlq_u64;
3370	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packsswb_u64, iemAImpl_packuswb_u64;
3371	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packssdw_u64;
3372	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhuw_u64;
3373	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pavgb_u64, iemAImpl_pavgw_u64;
3374	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psadbw_u64;
3375
3376	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pshufb_u128, iemAImpl_pshufb_u128_fallback;
3377	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pand_u128, iemAImpl_pandn_u128, iemAImpl_por_u128, iemAImpl_pxor_u128;
3378	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
3379	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpeqq_u128, iemAImpl_pcmpeqq_u128_fallback;
3380	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpgtb_u128, iemAImpl_pcmpgtw_u128, iemAImpl_pcmpgtd_u128;
3381	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpgtq_u128, iemAImpl_pcmpgtq_u128_fallback;
3382	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddb_u128, iemAImpl_paddsb_u128, iemAImpl_paddusb_u128;
3383	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddw_u128, iemAImpl_paddsw_u128, iemAImpl_paddusw_u128;
3384	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddd_u128;
3385	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddq_u128;
3386	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubb_u128, iemAImpl_psubsb_u128, iemAImpl_psubusb_u128;
3387	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubw_u128, iemAImpl_psubsw_u128, iemAImpl_psubusw_u128;
3388	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubd_u128;
3389	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubq_u128;
3390	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmullw_u128, iemAImpl_pmullw_u128_fallback;
3391	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhw_u128;
3392	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulld_u128, iemAImpl_pmulld_u128_fallback;
3393	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaddwd_u128, iemAImpl_pmaddwd_u128_fallback;
3394	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminub_u128;
3395	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminud_u128, iemAImpl_pminud_u128_fallback;
3396	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminuw_u128, iemAImpl_pminuw_u128_fallback;
3397	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminsb_u128, iemAImpl_pminsb_u128_fallback;
3398	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminsd_u128, iemAImpl_pminsd_u128_fallback;
3399	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminsw_u128, iemAImpl_pminsw_u128_fallback;
3400	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxub_u128;
3401	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxud_u128, iemAImpl_pmaxud_u128_fallback;
3402	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxuw_u128, iemAImpl_pmaxuw_u128_fallback;
3403	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxsb_u128, iemAImpl_pmaxsb_u128_fallback;
3404	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxsw_u128;
3405	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxsd_u128, iemAImpl_pmaxsd_u128_fallback;
3406	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pabsb_u128, iemAImpl_pabsb_u128_fallback;
3407	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pabsw_u128, iemAImpl_pabsw_u128_fallback;
3408	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pabsd_u128, iemAImpl_pabsd_u128_fallback;
3409	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psignb_u128, iemAImpl_psignb_u128_fallback;
3410	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psignw_u128, iemAImpl_psignw_u128_fallback;
3411	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psignd_u128, iemAImpl_psignd_u128_fallback;
3412	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phaddw_u128, iemAImpl_phaddw_u128_fallback;
3413	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phaddd_u128, iemAImpl_phaddd_u128_fallback;
3414	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phsubw_u128, iemAImpl_phsubw_u128_fallback;
3415	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phsubd_u128, iemAImpl_phsubd_u128_fallback;
3416	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phaddsw_u128, iemAImpl_phaddsw_u128_fallback;
3417	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phsubsw_u128, iemAImpl_phsubsw_u128_fallback;
3418	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaddubsw_u128, iemAImpl_pmaddubsw_u128_fallback;
3419	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhrsw_u128, iemAImpl_pmulhrsw_u128_fallback;
3420	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuludq_u128;
3421	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaddwd_u128, iemAImpl_pmaddwd_u128_fallback;
3422	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packsswb_u128, iemAImpl_packuswb_u128;
3423	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packssdw_u128, iemAImpl_packusdw_u128;
3424	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllw_u128, iemAImpl_psrlw_u128, iemAImpl_psraw_u128;
3425	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pslld_u128, iemAImpl_psrld_u128, iemAImpl_psrad_u128;
3426	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllq_u128, iemAImpl_psrlq_u128;
3427	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhuw_u128;
3428	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pavgb_u128, iemAImpl_pavgw_u128;
3429	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psadbw_u128;
3430	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuldq_u128, iemAImpl_pmuldq_u128_fallback;
3431	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpcklps_u128, iemAImpl_unpcklpd_u128;
3432	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpckhps_u128, iemAImpl_unpckhpd_u128;
3433	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phminposuw_u128, iemAImpl_phminposuw_u128_fallback;
3434
3435	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpshufb_u128, iemAImpl_vpshufb_u128_fallback;
3436	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpand_u128, iemAImpl_vpand_u128_fallback;
3437	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpandn_u128, iemAImpl_vpandn_u128_fallback;
3438	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpor_u128, iemAImpl_vpor_u128_fallback;
3439	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpxor_u128, iemAImpl_vpxor_u128_fallback;
3440	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqb_u128, iemAImpl_vpcmpeqb_u128_fallback;
3441	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqw_u128, iemAImpl_vpcmpeqw_u128_fallback;
3442	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqd_u128, iemAImpl_vpcmpeqd_u128_fallback;
3443	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqq_u128, iemAImpl_vpcmpeqq_u128_fallback;
3444	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtb_u128, iemAImpl_vpcmpgtb_u128_fallback;
3445	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtw_u128, iemAImpl_vpcmpgtw_u128_fallback;
3446	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtd_u128, iemAImpl_vpcmpgtd_u128_fallback;
3447	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtq_u128, iemAImpl_vpcmpgtq_u128_fallback;
3448	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddb_u128, iemAImpl_vpaddb_u128_fallback;
3449	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddw_u128, iemAImpl_vpaddw_u128_fallback;
3450	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddd_u128, iemAImpl_vpaddd_u128_fallback;
3451	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddq_u128, iemAImpl_vpaddq_u128_fallback;
3452	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubb_u128, iemAImpl_vpsubb_u128_fallback;
3453	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubw_u128, iemAImpl_vpsubw_u128_fallback;
3454	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubd_u128, iemAImpl_vpsubd_u128_fallback;
3455	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubq_u128, iemAImpl_vpsubq_u128_fallback;
3456	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminub_u128, iemAImpl_vpminub_u128_fallback;
3457	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminuw_u128, iemAImpl_vpminuw_u128_fallback;
3458	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminud_u128, iemAImpl_vpminud_u128_fallback;
3459	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminsb_u128, iemAImpl_vpminsb_u128_fallback;
3460	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminsw_u128, iemAImpl_vpminsw_u128_fallback;
3461	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminsd_u128, iemAImpl_vpminsd_u128_fallback;
3462	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxub_u128, iemAImpl_vpmaxub_u128_fallback;
3463	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxuw_u128, iemAImpl_vpmaxuw_u128_fallback;
3464	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxud_u128, iemAImpl_vpmaxud_u128_fallback;
3465	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxsb_u128, iemAImpl_vpmaxsb_u128_fallback;
3466	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxsw_u128, iemAImpl_vpmaxsw_u128_fallback;
3467	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxsd_u128, iemAImpl_vpmaxsd_u128_fallback;
3468	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpacksswb_u128, iemAImpl_vpacksswb_u128_fallback;
3469	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackssdw_u128, iemAImpl_vpackssdw_u128_fallback;
3470	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackuswb_u128, iemAImpl_vpackuswb_u128_fallback;
3471	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackusdw_u128, iemAImpl_vpackusdw_u128_fallback;
3472	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmullw_u128, iemAImpl_vpmullw_u128_fallback;
3473	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulld_u128, iemAImpl_vpmulld_u128_fallback;
3474	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhw_u128, iemAImpl_vpmulhw_u128_fallback;
3475	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhuw_u128, iemAImpl_vpmulhuw_u128_fallback;
3476	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgb_u128, iemAImpl_vpavgb_u128_fallback;
3477	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgw_u128, iemAImpl_vpavgw_u128_fallback;
3478	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignb_u128, iemAImpl_vpsignb_u128_fallback;
3479	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignw_u128, iemAImpl_vpsignw_u128_fallback;
3480	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignd_u128, iemAImpl_vpsignd_u128_fallback;
3481	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddw_u128, iemAImpl_vphaddw_u128_fallback;
3482	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddd_u128, iemAImpl_vphaddd_u128_fallback;
3483	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubw_u128, iemAImpl_vphsubw_u128_fallback;
3484	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubd_u128, iemAImpl_vphsubd_u128_fallback;
3485	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddsw_u128, iemAImpl_vphaddsw_u128_fallback;
3486	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubsw_u128, iemAImpl_vphsubsw_u128_fallback;
3487	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddubsw_u128, iemAImpl_vpmaddubsw_u128_fallback;
3488	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhrsw_u128, iemAImpl_vpmulhrsw_u128_fallback;
3489	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsadbw_u128, iemAImpl_vpsadbw_u128_fallback;
3490	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuldq_u128, iemAImpl_vpmuldq_u128_fallback;
3491	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuludq_u128, iemAImpl_vpmuludq_u128_fallback;
3492	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsb_u128, iemAImpl_vpsubsb_u128_fallback;
3493	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsw_u128, iemAImpl_vpsubsw_u128_fallback;
3494	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusb_u128, iemAImpl_vpsubusb_u128_fallback;
3495	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusw_u128, iemAImpl_vpsubusw_u128_fallback;
3496	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusb_u128, iemAImpl_vpaddusb_u128_fallback;
3497	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusw_u128, iemAImpl_vpaddusw_u128_fallback;
3498	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsb_u128, iemAImpl_vpaddsb_u128_fallback;
3499	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsw_u128, iemAImpl_vpaddsw_u128_fallback;
3500	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllw_u128, iemAImpl_vpsllw_u128_fallback;
3501	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpslld_u128, iemAImpl_vpslld_u128_fallback;
3502	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllq_u128, iemAImpl_vpsllq_u128_fallback;
3503	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsraw_u128, iemAImpl_vpsraw_u128_fallback;
3504	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrad_u128, iemAImpl_vpsrad_u128_fallback;
3505	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlw_u128, iemAImpl_vpsrlw_u128_fallback;
3506	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrld_u128, iemAImpl_vpsrld_u128_fallback;
3507	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlq_u128, iemAImpl_vpsrlq_u128_fallback;
3508	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddwd_u128, iemAImpl_vpmaddwd_u128_fallback;
3509
3510	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsb_u128, iemAImpl_vpabsb_u128_fallback;
3511	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsw_u128, iemAImpl_vpabsd_u128_fallback;
3512	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsd_u128, iemAImpl_vpabsw_u128_fallback;
3513	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vphminposuw_u128, iemAImpl_vphminposuw_u128_fallback;
3514
3515	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpshufb_u256, iemAImpl_vpshufb_u256_fallback;
3516	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpand_u256, iemAImpl_vpand_u256_fallback;
3517	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpandn_u256, iemAImpl_vpandn_u256_fallback;
3518	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpor_u256, iemAImpl_vpor_u256_fallback;
3519	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpxor_u256, iemAImpl_vpxor_u256_fallback;
3520	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqb_u256, iemAImpl_vpcmpeqb_u256_fallback;
3521	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqw_u256, iemAImpl_vpcmpeqw_u256_fallback;
3522	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqd_u256, iemAImpl_vpcmpeqd_u256_fallback;
3523	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqq_u256, iemAImpl_vpcmpeqq_u256_fallback;
3524	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtb_u256, iemAImpl_vpcmpgtb_u256_fallback;
3525	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtw_u256, iemAImpl_vpcmpgtw_u256_fallback;
3526	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtd_u256, iemAImpl_vpcmpgtd_u256_fallback;
3527	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtq_u256, iemAImpl_vpcmpgtq_u256_fallback;
3528	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddb_u256, iemAImpl_vpaddb_u256_fallback;
3529	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddw_u256, iemAImpl_vpaddw_u256_fallback;
3530	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddd_u256, iemAImpl_vpaddd_u256_fallback;
3531	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddq_u256, iemAImpl_vpaddq_u256_fallback;
3532	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubb_u256, iemAImpl_vpsubb_u256_fallback;
3533	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubw_u256, iemAImpl_vpsubw_u256_fallback;
3534	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubd_u256, iemAImpl_vpsubd_u256_fallback;
3535	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubq_u256, iemAImpl_vpsubq_u256_fallback;
3536	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminub_u256, iemAImpl_vpminub_u256_fallback;
3537	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminuw_u256, iemAImpl_vpminuw_u256_fallback;
3538	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminud_u256, iemAImpl_vpminud_u256_fallback;
3539	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminsb_u256, iemAImpl_vpminsb_u256_fallback;
3540	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminsw_u256, iemAImpl_vpminsw_u256_fallback;
3541	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminsd_u256, iemAImpl_vpminsd_u256_fallback;
3542	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxub_u256, iemAImpl_vpmaxub_u256_fallback;
3543	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxuw_u256, iemAImpl_vpmaxuw_u256_fallback;
3544	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxud_u256, iemAImpl_vpmaxud_u256_fallback;
3545	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxsb_u256, iemAImpl_vpmaxsb_u256_fallback;
3546	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxsw_u256, iemAImpl_vpmaxsw_u256_fallback;
3547	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxsd_u256, iemAImpl_vpmaxsd_u256_fallback;
3548	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpacksswb_u256, iemAImpl_vpacksswb_u256_fallback;
3549	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackssdw_u256, iemAImpl_vpackssdw_u256_fallback;
3550	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackuswb_u256, iemAImpl_vpackuswb_u256_fallback;
3551	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackusdw_u256, iemAImpl_vpackusdw_u256_fallback;
3552	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmullw_u256, iemAImpl_vpmullw_u256_fallback;
3553	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulld_u256, iemAImpl_vpmulld_u256_fallback;
3554	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhw_u256, iemAImpl_vpmulhw_u256_fallback;
3555	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhuw_u256, iemAImpl_vpmulhuw_u256_fallback;
3556	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgb_u256, iemAImpl_vpavgb_u256_fallback;
3557	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgw_u256, iemAImpl_vpavgw_u256_fallback;
3558	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignb_u256, iemAImpl_vpsignb_u256_fallback;
3559	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignw_u256, iemAImpl_vpsignw_u256_fallback;
3560	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignd_u256, iemAImpl_vpsignd_u256_fallback;
3561	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddw_u256, iemAImpl_vphaddw_u256_fallback;
3562	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddd_u256, iemAImpl_vphaddd_u256_fallback;
3563	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubw_u256, iemAImpl_vphsubw_u256_fallback;
3564	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubd_u256, iemAImpl_vphsubd_u256_fallback;
3565	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddsw_u256, iemAImpl_vphaddsw_u256_fallback;
3566	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubsw_u256, iemAImpl_vphsubsw_u256_fallback;
3567	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddubsw_u256, iemAImpl_vpmaddubsw_u256_fallback;
3568	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhrsw_u256, iemAImpl_vpmulhrsw_u256_fallback;
3569	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsadbw_u256, iemAImpl_vpsadbw_u256_fallback;
3570	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuldq_u256, iemAImpl_vpmuldq_u256_fallback;
3571	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuludq_u256, iemAImpl_vpmuludq_u256_fallback;
3572	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsb_u256, iemAImpl_vpsubsb_u256_fallback;
3573	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsw_u256, iemAImpl_vpsubsw_u256_fallback;
3574	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusb_u256, iemAImpl_vpsubusb_u256_fallback;
3575	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusw_u256, iemAImpl_vpsubusw_u256_fallback;
3576	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusb_u256, iemAImpl_vpaddusb_u256_fallback;
3577	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusw_u256, iemAImpl_vpaddusw_u256_fallback;
3578	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsb_u256, iemAImpl_vpaddsb_u256_fallback;
3579	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsw_u256, iemAImpl_vpaddsw_u256_fallback;
3580	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllw_u256, iemAImpl_vpsllw_u256_fallback;
3581	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpslld_u256, iemAImpl_vpslld_u256_fallback;
3582	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllq_u256, iemAImpl_vpsllq_u256_fallback;
3583	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsraw_u256, iemAImpl_vpsraw_u256_fallback;
3584	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrad_u256, iemAImpl_vpsrad_u256_fallback;
3585	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlw_u256, iemAImpl_vpsrlw_u256_fallback;
3586	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrld_u256, iemAImpl_vpsrld_u256_fallback;
3587	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlq_u256, iemAImpl_vpsrlq_u256_fallback;
3588	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddwd_u256, iemAImpl_vpmaddwd_u256_fallback;
3589
3590	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsb_u256, iemAImpl_vpabsb_u256_fallback;
3591	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsw_u256, iemAImpl_vpabsw_u256_fallback;
3592	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsd_u256, iemAImpl_vpabsd_u256_fallback;
3593	/** @} */
3594
3595	/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
3596	* @{ */
3597	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
3598	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
3599	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpcklbw_u128, iemAImpl_vpunpcklbw_u128_fallback,
3600	iemAImpl_vpunpcklwd_u128, iemAImpl_vpunpcklwd_u128_fallback,
3601	iemAImpl_vpunpckldq_u128, iemAImpl_vpunpckldq_u128_fallback,
3602	iemAImpl_vpunpcklqdq_u128, iemAImpl_vpunpcklqdq_u128_fallback,
3603	iemAImpl_vunpcklps_u128, iemAImpl_vunpcklps_u128_fallback,
3604	iemAImpl_vunpcklpd_u128, iemAImpl_vunpcklpd_u128_fallback,
3605	iemAImpl_vunpckhps_u128, iemAImpl_vunpckhps_u128_fallback,
3606	iemAImpl_vunpckhpd_u128, iemAImpl_vunpckhpd_u128_fallback;
3607
3608	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpcklbw_u256, iemAImpl_vpunpcklbw_u256_fallback,
3609	iemAImpl_vpunpcklwd_u256, iemAImpl_vpunpcklwd_u256_fallback,
3610	iemAImpl_vpunpckldq_u256, iemAImpl_vpunpckldq_u256_fallback,
3611	iemAImpl_vpunpcklqdq_u256, iemAImpl_vpunpcklqdq_u256_fallback,
3612	iemAImpl_vunpcklps_u256, iemAImpl_vunpcklps_u256_fallback,
3613	iemAImpl_vunpcklpd_u256, iemAImpl_vunpcklpd_u256_fallback,
3614	iemAImpl_vunpckhps_u256, iemAImpl_vunpckhps_u256_fallback,
3615	iemAImpl_vunpckhpd_u256, iemAImpl_vunpckhpd_u256_fallback;
3616	/** @} */
3617
3618	/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
3619	* @{ */
3620	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
3621	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
3622	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpckhbw_u128, iemAImpl_vpunpckhbw_u128_fallback,
3623	iemAImpl_vpunpckhwd_u128, iemAImpl_vpunpckhwd_u128_fallback,
3624	iemAImpl_vpunpckhdq_u128, iemAImpl_vpunpckhdq_u128_fallback,
3625	iemAImpl_vpunpckhqdq_u128, iemAImpl_vpunpckhqdq_u128_fallback;
3626	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpckhbw_u256, iemAImpl_vpunpckhbw_u256_fallback,
3627	iemAImpl_vpunpckhwd_u256, iemAImpl_vpunpckhwd_u256_fallback,
3628	iemAImpl_vpunpckhdq_u256, iemAImpl_vpunpckhdq_u256_fallback,
3629	iemAImpl_vpunpckhqdq_u256, iemAImpl_vpunpckhqdq_u256_fallback;
3630	/** @} */
3631
3632	/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
3633	* @{ */
3634	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3635	typedef FNIEMAIMPLMEDIAPSHUFU128 *PFNIEMAIMPLMEDIAPSHUFU128;
3636	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
3637	typedef FNIEMAIMPLMEDIAPSHUFU256 *PFNIEMAIMPLMEDIAPSHUFU256;
3638	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw_u64,(uint64_t puDst, uint64_t const puSrc, uint8_t bEvil));
3639	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_pshufhw_u128, iemAImpl_pshuflw_u128, iemAImpl_pshufd_u128;
3640	#ifndef IEM_WITHOUT_ASSEMBLY
3641	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256, iemAImpl_vpshuflw_u256, iemAImpl_vpshufd_u256;
3642	#endif
3643	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256_fallback, iemAImpl_vpshuflw_u256_fallback, iemAImpl_vpshufd_u256_fallback;
3644	/** @} */
3645
3646	/** @name Media (SSE/MMX/AVX) operation: Shift Immediate Stuff (evil)
3647	* @{ */
3648	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU64,(uint64_t *puDst, uint8_t bShift));
3649	typedef FNIEMAIMPLMEDIAPSHIFTU64 *PFNIEMAIMPLMEDIAPSHIFTU64;
3650	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU128,(PRTUINT128U puDst, uint8_t bShift));
3651	typedef FNIEMAIMPLMEDIAPSHIFTU128 *PFNIEMAIMPLMEDIAPSHIFTU128;
3652	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU256,(PRTUINT256U puDst, uint8_t bShift));
3653	typedef FNIEMAIMPLMEDIAPSHIFTU256 *PFNIEMAIMPLMEDIAPSHIFTU256;
3654	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psllw_imm_u64, iemAImpl_pslld_imm_u64, iemAImpl_psllq_imm_u64;
3655	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psrlw_imm_u64, iemAImpl_psrld_imm_u64, iemAImpl_psrlq_imm_u64;
3656	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psraw_imm_u64, iemAImpl_psrad_imm_u64;
3657	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psllw_imm_u128, iemAImpl_pslld_imm_u128, iemAImpl_psllq_imm_u128;
3658	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psrlw_imm_u128, iemAImpl_psrld_imm_u128, iemAImpl_psrlq_imm_u128;
3659	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psraw_imm_u128, iemAImpl_psrad_imm_u128;
3660	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_pslldq_imm_u128, iemAImpl_psrldq_imm_u128;
3661	/** @} */
3662
3663	/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
3664	* @{ */
3665	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(uint64_t pu64Dst, uint64_t const puSrc));
3666	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(uint64_t *pu64Dst, PCRTUINT128U puSrc));
3667	#ifndef IEM_WITHOUT_ASSEMBLY
3668	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
3669	#endif
3670	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256_fallback,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
3671	/** @} */
3672
3673	/** @name Media (SSE/MMX/AVX) operations: Variable Blend Packed Bytes/R32/R64.
3674	* @{ */
3675	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puMask));
3676	typedef FNIEMAIMPLBLENDU128 *PFNIEMAIMPLBLENDU128;
3677	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, PCRTUINT128U puMask));
3678	typedef FNIEMAIMPLAVXBLENDU128 *PFNIEMAIMPLAVXBLENDU128;
3679	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, PCRTUINT256U puMask));
3680	typedef FNIEMAIMPLAVXBLENDU256 *PFNIEMAIMPLAVXBLENDU256;
3681
3682	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128;
3683	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128_fallback;
3684	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128;
3685	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128_fallback;
3686	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256;
3687	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256_fallback;
3688
3689	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128;
3690	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128_fallback;
3691	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128;
3692	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128_fallback;
3693	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256;
3694	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256_fallback;
3695
3696	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128;
3697	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128_fallback;
3698	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128;
3699	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128_fallback;
3700	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256;
3701	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256_fallback;
3702	/** @} */
3703
3704
3705	/** @name Media (SSE/MMX/AVX) operation: Sort this later
3706	* @{ */
3707	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3708	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3709	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3710	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3711	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3712
3713	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3714	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3715	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3716	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3717	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3718
3719	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3720	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3721	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
3722	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3723	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3724
3725	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3726	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3727	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3728	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3729	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3730
3731	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3732	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3733	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3734	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3735	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3736
3737	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3738	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3739	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3740	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3741	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3742
3743	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3744	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3745	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3746	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3747	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3748
3749	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3750	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3751	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3752	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3753	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3754
3755	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3756	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3757	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
3758	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3759	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3760
3761	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3762	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3763	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3764	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3765	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3766
3767	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3768	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3769	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3770	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3771	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3772
3773	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3774	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3775	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3776	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3777	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3778
3779	IEM_DECL_IMPL_DEF(void, iemAImpl_shufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3780	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3781	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3782	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3783	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3784
3785	IEM_DECL_IMPL_DEF(void, iemAImpl_shufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3786	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3787	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3788	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3789	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3790
3791	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
3792	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64_fallback,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
3793
3794	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3795	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3796	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3797	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3798	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3799
3800	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3801	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3802	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3803	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3804	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3805
3806
3807	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3808	typedef FNIEMAIMPLMEDIAOPTF2U128IMM8 *PFNIEMAIMPLMEDIAOPTF2U128IMM8;
3809	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
3810	typedef FNIEMAIMPLMEDIAOPTF2U256IMM8 *PFNIEMAIMPLMEDIAOPTF2U256IMM8;
3811	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3812	typedef FNIEMAIMPLMEDIAOPTF3U128IMM8 *PFNIEMAIMPLMEDIAOPTF3U128IMM8;
3813	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3814	typedef FNIEMAIMPLMEDIAOPTF3U256IMM8 *PFNIEMAIMPLMEDIAOPTF3U256IMM8;
3815
3816	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_palignr_u128, iemAImpl_palignr_u128_fallback;
3817	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pblendw_u128, iemAImpl_pblendw_u128_fallback;
3818	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendps_u128, iemAImpl_blendps_u128_fallback;
3819	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendpd_u128, iemAImpl_blendpd_u128_fallback;
3820
3821	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpalignr_u128, iemAImpl_vpalignr_u128_fallback;
3822	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendw_u128, iemAImpl_vpblendw_u128_fallback;
3823	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendd_u128, iemAImpl_vpblendd_u128_fallback;
3824	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendps_u128, iemAImpl_vblendps_u128_fallback;
3825	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendpd_u128, iemAImpl_vblendpd_u128_fallback;
3826
3827	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpalignr_u256, iemAImpl_vpalignr_u256_fallback;
3828	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendw_u256, iemAImpl_vpblendw_u256_fallback;
3829	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendd_u256, iemAImpl_vpblendd_u256_fallback;
3830	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendps_u256, iemAImpl_vblendps_u256_fallback;
3831	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendpd_u256, iemAImpl_vblendpd_u256_fallback;
3832	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2i128_u256, iemAImpl_vperm2i128_u256_fallback;
3833	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2f128_u256, iemAImpl_vperm2f128_u256_fallback;
3834
3835	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesimc_u128, iemAImpl_aesimc_u128_fallback;
3836	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenc_u128, iemAImpl_aesenc_u128_fallback;
3837	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenclast_u128, iemAImpl_aesenclast_u128_fallback;
3838	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdec_u128, iemAImpl_aesdec_u128_fallback;
3839	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdeclast_u128, iemAImpl_aesdeclast_u128_fallback;
3840
3841	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesimc_u128, iemAImpl_vaesimc_u128_fallback;
3842	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenc_u128, iemAImpl_vaesenc_u128_fallback;
3843	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenclast_u128, iemAImpl_vaesenclast_u128_fallback;
3844	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdec_u128, iemAImpl_vaesdec_u128_fallback;
3845	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdeclast_u128, iemAImpl_vaesdeclast_u128_fallback;
3846
3847	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_aeskeygenassist_u128, iemAImpl_aeskeygenassist_u128_fallback;
3848
3849	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vaeskeygenassist_u128, iemAImpl_vaeskeygenassist_u128_fallback;
3850
3851	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1nexte_u128, iemAImpl_sha1nexte_u128_fallback;
3852	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg1_u128, iemAImpl_sha1msg1_u128_fallback;
3853	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg2_u128, iemAImpl_sha1msg2_u128_fallback;
3854	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg1_u128, iemAImpl_sha256msg1_u128_fallback;
3855	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg2_u128, iemAImpl_sha256msg2_u128_fallback;
3856	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_sha1rnds4_u128, iemAImpl_sha1rnds4_u128_fallback;
3857	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
3858	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
3859
3860	typedef struct IEMPCMPISTRXSRC
3861	{
3862	RTUINT128U uSrc1;
3863	RTUINT128U uSrc2;
3864	} IEMPCMPISTRXSRC;
3865	typedef IEMPCMPISTRXSRC *PIEMPCMPISTRXSRC;
3866	typedef const IEMPCMPISTRXSRC *PCIEMPCMPISTRXSRC;
3867
3868	typedef struct IEMPCMPESTRXSRC
3869	{
3870	RTUINT128U uSrc1;
3871	RTUINT128U uSrc2;
3872	uint64_t u64Rax;
3873	uint64_t u64Rdx;
3874	} IEMPCMPESTRXSRC;
3875	typedef IEMPCMPESTRXSRC *PIEMPCMPESTRXSRC;
3876	typedef const IEMPCMPESTRXSRC *PCIEMPCMPESTRXSRC;
3877
3878	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLPCMPISTRIU128IMM8,(uint32_t *pEFlags, PCRTUINT128U pSrc1, PCRTUINT128U pSrc2, uint8_t bEvil));
3879	typedef FNIEMAIMPLPCMPISTRIU128IMM8 *PFNIEMAIMPLPCMPISTRIU128IMM8;
3880	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRIU128IMM8,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
3881	typedef FNIEMAIMPLPCMPESTRIU128IMM8 *PFNIEMAIMPLPCMPESTRIU128IMM8;
3882
3883	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPISTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
3884	typedef FNIEMAIMPLPCMPISTRMU128IMM8 *PFNIEMAIMPLPCMPISTRMU128IMM8;
3885	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
3886	typedef FNIEMAIMPLPCMPESTRMU128IMM8 *PFNIEMAIMPLPCMPESTRMU128IMM8;
3887
3888	FNIEMAIMPLPCMPISTRIU128IMM8 iemAImpl_pcmpistri_u128, iemAImpl_pcmpistri_u128_fallback;
3889	FNIEMAIMPLPCMPESTRIU128IMM8 iemAImpl_pcmpestri_u128, iemAImpl_pcmpestri_u128_fallback;
3890	FNIEMAIMPLPCMPISTRMU128IMM8 iemAImpl_pcmpistrm_u128, iemAImpl_pcmpistrm_u128_fallback;
3891	FNIEMAIMPLPCMPESTRMU128IMM8 iemAImpl_pcmpestrm_u128, iemAImpl_pcmpestrm_u128_fallback;
3892
3893	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pclmulqdq_u128, iemAImpl_pclmulqdq_u128_fallback;
3894	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpclmulqdq_u128, iemAImpl_vpclmulqdq_u128_fallback;
3895
3896	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_mpsadbw_u128, iemAImpl_mpsadbw_u128_fallback;
3897	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vmpsadbw_u128, iemAImpl_vmpsadbw_u128_fallback;
3898	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vmpsadbw_u256, iemAImpl_vmpsadbw_u256_fallback;
3899
3900	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsllw_imm_u128, iemAImpl_vpsllw_imm_u128_fallback;
3901	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsllw_imm_u256, iemAImpl_vpsllw_imm_u256_fallback;
3902	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpslld_imm_u128, iemAImpl_vpslld_imm_u128_fallback;
3903	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpslld_imm_u256, iemAImpl_vpslld_imm_u256_fallback;
3904	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsllq_imm_u128, iemAImpl_vpsllq_imm_u128_fallback;
3905	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsllq_imm_u256, iemAImpl_vpsllq_imm_u256_fallback;
3906	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
3907	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
3908	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
3909	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
3910
3911	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsraw_imm_u128, iemAImpl_vpsraw_imm_u128_fallback;
3912	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsraw_imm_u256, iemAImpl_vpsraw_imm_u256_fallback;
3913	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrad_imm_u128, iemAImpl_vpsrad_imm_u128_fallback;
3914	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrad_imm_u256, iemAImpl_vpsrad_imm_u256_fallback;
3915
3916	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrlw_imm_u128, iemAImpl_vpsrlw_imm_u128_fallback;
3917	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrlw_imm_u256, iemAImpl_vpsrlw_imm_u256_fallback;
3918	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrld_imm_u128, iemAImpl_vpsrld_imm_u128_fallback;
3919	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrld_imm_u256, iemAImpl_vpsrld_imm_u256_fallback;
3920	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrlq_imm_u128, iemAImpl_vpsrlq_imm_u128_fallback;
3921	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrlq_imm_u256, iemAImpl_vpsrlq_imm_u256_fallback;
3922	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
3923	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
3924	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
3925	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
3926
3927	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpermilps_u128, iemAImpl_vpermilps_u128_fallback;
3928	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_vpermilps_imm_u128, iemAImpl_vpermilps_imm_u128_fallback;
3929	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpermilps_u256, iemAImpl_vpermilps_u256_fallback;
3930	FNIEMAIMPLMEDIAOPTF2U256IMM8 iemAImpl_vpermilps_imm_u256, iemAImpl_vpermilps_imm_u256_fallback;
3931
3932	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpermilpd_u128, iemAImpl_vpermilpd_u128_fallback;
3933	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_vpermilpd_imm_u128, iemAImpl_vpermilpd_imm_u128_fallback;
3934	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpermilpd_u256, iemAImpl_vpermilpd_u256_fallback;
3935	FNIEMAIMPLMEDIAOPTF2U256IMM8 iemAImpl_vpermilpd_imm_u256, iemAImpl_vpermilpd_imm_u256_fallback;
3936
3937	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllvd_u128, iemAImpl_vpsllvd_u128_fallback;
3938	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllvd_u256, iemAImpl_vpsllvd_u256_fallback;
3939	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllvq_u128, iemAImpl_vpsllvq_u128_fallback;
3940	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllvq_u256, iemAImpl_vpsllvq_u256_fallback;
3941	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsravd_u128, iemAImpl_vpsravd_u128_fallback;
3942	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsravd_u256, iemAImpl_vpsravd_u256_fallback;
3943	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlvd_u128, iemAImpl_vpsrlvd_u128_fallback;
3944	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlvd_u256, iemAImpl_vpsrlvd_u256_fallback;
3945	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlvq_u128, iemAImpl_vpsrlvq_u128_fallback;
3946	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlvq_u256, iemAImpl_vpsrlvq_u256_fallback;
3947	/** @} */
3948
3949	/** @name Media Odds and Ends
3950	* @{ */
3951	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U8,(uint32_t *puDst, uint8_t uSrc));
3952	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U16,(uint32_t *puDst, uint16_t uSrc));
3953	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U32,(uint32_t *puDst, uint32_t uSrc));
3954	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U64,(uint32_t *puDst, uint64_t uSrc));
3955	FNIEMAIMPLCR32U8 iemAImpl_crc32_u8, iemAImpl_crc32_u8_fallback;
3956	FNIEMAIMPLCR32U16 iemAImpl_crc32_u16, iemAImpl_crc32_u16_fallback;
3957	FNIEMAIMPLCR32U32 iemAImpl_crc32_u32, iemAImpl_crc32_u32_fallback;
3958	FNIEMAIMPLCR32U64 iemAImpl_crc32_u64, iemAImpl_crc32_u64_fallback;
3959
3960	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL128,(PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint32_t *pEFlags));
3961	typedef FNIEMAIMPLF2EFL128 *PFNIEMAIMPLF2EFL128;
3962	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL256,(PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint32_t *pEFlags));
3963	typedef FNIEMAIMPLF2EFL256 *PFNIEMAIMPLF2EFL256;
3964	FNIEMAIMPLF2EFL128 iemAImpl_ptest_u128;
3965	FNIEMAIMPLF2EFL256 iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback;
3966	FNIEMAIMPLF2EFL128 iemAImpl_vtestps_u128, iemAImpl_vtestps_u128_fallback;
3967	FNIEMAIMPLF2EFL256 iemAImpl_vtestps_u256, iemAImpl_vtestps_u256_fallback;
3968	FNIEMAIMPLF2EFL128 iemAImpl_vtestpd_u128, iemAImpl_vtestpd_u128_fallback;
3969	FNIEMAIMPLF2EFL256 iemAImpl_vtestpd_u256, iemAImpl_vtestpd_u256_fallback;
3970
3971	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I32U64,(uint32_t uMxCsrIn, int32_t pi32Dst, const uint64_t pu64Src)); /* pu64Src is a double precision floating point. */
3972	typedef FNIEMAIMPLSSEF2I32U64 *PFNIEMAIMPLSSEF2I32U64;
3973	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I64U64,(uint32_t uMxCsrIn, int64_t pi64Dst, const uint64_t pu64Src)); /* pu64Src is a double precision floating point. */
3974	typedef FNIEMAIMPLSSEF2I64U64 *PFNIEMAIMPLSSEF2I64U64;
3975	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I32U32,(uint32_t uMxCsrIn, int32_t pi32Dst, const uint32_t pu32Src)); /* pu32Src is a single precision floating point. */
3976	typedef FNIEMAIMPLSSEF2I32U32 *PFNIEMAIMPLSSEF2I32U32;
3977	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I64U32,(uint32_t uMxCsrIn, int64_t pi64Dst, const uint32_t pu32Src)); /* pu32Src is a single precision floating point. */
3978	typedef FNIEMAIMPLSSEF2I64U32 *PFNIEMAIMPLSSEF2I64U32;
3979
3980	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvttsd2si_i32_r64;
3981	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvtsd2si_i32_r64;
3982
3983	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvttsd2si_i64_r64;
3984	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvtsd2si_i64_r64;
3985
3986	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvttss2si_i32_r32;
3987	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvtss2si_i32_r32;
3988
3989	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvttss2si_i64_r32;
3990	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvtss2si_i64_r32;
3991
3992	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R32I32,(uint32_t uMxCsrIn, PRTFLOAT32U pr32Dst, const int32_t *pi32Src));
3993	typedef FNIEMAIMPLSSEF2R32I32 *PFNIEMAIMPLSSEF2R32I32;
3994	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R32I64,(uint32_t uMxCsrIn, PRTFLOAT32U pr32Dst, const int64_t *pi64Src));
3995	typedef FNIEMAIMPLSSEF2R32I64 *PFNIEMAIMPLSSEF2R32I64;
3996
3997	FNIEMAIMPLSSEF2R32I32 iemAImpl_cvtsi2ss_r32_i32;
3998	FNIEMAIMPLSSEF2R32I64 iemAImpl_cvtsi2ss_r32_i64;
3999
4000	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R64I32,(uint32_t uMxCsrIn, PRTFLOAT64U pr64Dst, const int32_t *pi32Src));
4001	typedef FNIEMAIMPLSSEF2R64I32 *PFNIEMAIMPLSSEF2R64I32;
4002	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R64I64,(uint32_t uMxCsrIn, PRTFLOAT64U pr64Dst, const int64_t *pi64Src));
4003	typedef FNIEMAIMPLSSEF2R64I64 *PFNIEMAIMPLSSEF2R64I64;
4004
4005	FNIEMAIMPLSSEF2R64I32 iemAImpl_cvtsi2sd_r64_i32;
4006	FNIEMAIMPLSSEF2R64I64 iemAImpl_cvtsi2sd_r64_i64;
4007
4008
4009	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLF2EFLMXCSRR32R32,(uint32_t uMxCsrIn, uint32_t *pfEFlags, RTFLOAT32U uSrc1, RTFLOAT32U uSrc2));
4010	typedef FNIEMAIMPLF2EFLMXCSRR32R32 *PFNIEMAIMPLF2EFLMXCSRR32R32;
4011
4012	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLF2EFLMXCSRR64R64,(uint32_t uMxCsrIn, uint32_t *pfEFlags, RTFLOAT64U uSrc1, RTFLOAT64U uSrc2));
4013	typedef FNIEMAIMPLF2EFLMXCSRR64R64 *PFNIEMAIMPLF2EFLMXCSRR64R64;
4014
4015	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_ucomiss_u128;
4016	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback;
4017
4018	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_ucomisd_u128;
4019	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback;
4020
4021	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_comiss_u128;
4022	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback;
4023
4024	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_comisd_u128;
4025	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback;
4026
4027
4028	typedef struct IEMMEDIAF2XMMSRC
4029	{
4030	X86XMMREG uSrc1;
4031	X86XMMREG uSrc2;
4032	} IEMMEDIAF2XMMSRC;
4033	typedef IEMMEDIAF2XMMSRC *PIEMMEDIAF2XMMSRC;
4034	typedef const IEMMEDIAF2XMMSRC *PCIEMMEDIAF2XMMSRC;
4035
4036	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRF2XMMIMM8,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCIEMMEDIAF2XMMSRC puSrc, uint8_t bEvil));
4037	typedef FNIEMAIMPLMXCSRF2XMMIMM8 *PFNIEMAIMPLMXCSRF2XMMIMM8;
4038
4039	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpps_u128;
4040	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmppd_u128;
4041	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpss_u128;
4042	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpsd_u128;
4043	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundss_u128;
4044	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundsd_u128;
4045
4046	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundps_u128, iemAImpl_roundps_u128_fallback;
4047	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundpd_u128, iemAImpl_roundpd_u128_fallback;
4048
4049	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_dpps_u128, iemAImpl_dpps_u128_fallback;
4050	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_dppd_u128, iemAImpl_dppd_u128_fallback;
4051
4052	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRU64U128,(uint32_t fMxCsrIn, uint64_t *pu64Dst, PCX86XMMREG pSrc));
4053	typedef FNIEMAIMPLMXCSRU64U128 *PFNIEMAIMPLMXCSRU64U128;
4054
4055	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvtpd2pi_u128;
4056	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvttpd2pi_u128;
4057
4058	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRU128U64,(uint32_t fMxCsrIn, PX86XMMREG pDst, uint64_t u64Src));
4059	typedef FNIEMAIMPLMXCSRU128U64 *PFNIEMAIMPLMXCSRU128U64;
4060
4061	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2ps_u128;
4062	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2pd_u128;
4063
4064	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRU64U64,(uint32_t fMxCsrIn, uint64_t *pu64Dst, uint64_t u64Src));
4065	typedef FNIEMAIMPLMXCSRU64U64 *PFNIEMAIMPLMXCSRU64U64;
4066
4067	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvtps2pi_u128;
4068	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvttps2pi_u128;
4069
4070	/** @} */
4071
4072
4073	/** @name Function tables.
4074	* @{
4075	*/
4076
4077	/**
4078	* Function table for a binary operator providing implementation based on
4079	* operand size.
4080	*/
4081	typedef struct IEMOPBINSIZES
4082	{
4083	PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
4084	PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
4085	PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
4086	PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
4087	} IEMOPBINSIZES;
4088	/** Pointer to a binary operator function table. */
4089	typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
4090
4091
4092	/**
4093	* Function table for a unary operator providing implementation based on
4094	* operand size.
4095	*/
4096	typedef struct IEMOPUNARYSIZES
4097	{
4098	PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
4099	PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
4100	PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
4101	PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
4102	} IEMOPUNARYSIZES;
4103	/** Pointer to a unary operator function table. */
4104	typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
4105
4106
4107	/**
4108	* Function table for a shift operator providing implementation based on
4109	* operand size.
4110	*/
4111	typedef struct IEMOPSHIFTSIZES
4112	{
4113	PFNIEMAIMPLSHIFTU8 pfnNormalU8;
4114	PFNIEMAIMPLSHIFTU16 pfnNormalU16;
4115	PFNIEMAIMPLSHIFTU32 pfnNormalU32;
4116	PFNIEMAIMPLSHIFTU64 pfnNormalU64;
4117	} IEMOPSHIFTSIZES;
4118	/** Pointer to a shift operator function table. */
4119	typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
4120
4121
4122	/**
4123	* Function table for a multiplication or division operation.
4124	*/
4125	typedef struct IEMOPMULDIVSIZES
4126	{
4127	PFNIEMAIMPLMULDIVU8 pfnU8;
4128	PFNIEMAIMPLMULDIVU16 pfnU16;
4129	PFNIEMAIMPLMULDIVU32 pfnU32;
4130	PFNIEMAIMPLMULDIVU64 pfnU64;
4131	} IEMOPMULDIVSIZES;
4132	/** Pointer to a multiplication or division operation function table. */
4133	typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
4134
4135
4136	/**
4137	* Function table for a double precision shift operator providing implementation
4138	* based on operand size.
4139	*/
4140	typedef struct IEMOPSHIFTDBLSIZES
4141	{
4142	PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
4143	PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
4144	PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
4145	} IEMOPSHIFTDBLSIZES;
4146	/** Pointer to a double precision shift function table. */
4147	typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
4148
4149
4150	/**
4151	* Function table for media instruction taking two full sized media source
4152	* registers and one full sized destination register (AVX).
4153	*/
4154	typedef struct IEMOPMEDIAF3
4155	{
4156	PFNIEMAIMPLMEDIAF3U128 pfnU128;
4157	PFNIEMAIMPLMEDIAF3U256 pfnU256;
4158	} IEMOPMEDIAF3;
4159	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
4160	typedef IEMOPMEDIAF3 const *PCIEMOPMEDIAF3;
4161
4162	/** @def IEMOPMEDIAF3_INIT_VARS_EX
4163	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4164	* given functions as initializers. For use in AVX functions where a pair of
4165	* functions are only used once and the function table need not be public. */
4166	#ifndef TST_IEM_CHECK_MC
4167	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4168	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4169	static IEMOPMEDIAF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4170	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4171	# else
4172	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4173	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4174	# endif
4175	#else
4176	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4177	#endif
4178	/** @def IEMOPMEDIAF3_INIT_VARS
4179	* Generate AVX function tables for the @a a_InstrNm instruction.
4180	* @sa IEMOPMEDIAF3_INIT_VARS_EX */
4181	#define IEMOPMEDIAF3_INIT_VARS(a_InstrNm) \
4182	IEMOPMEDIAF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4183	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4184
4185	/**
4186	* Function table for media instruction taking two full sized media source
4187	* registers and one full sized destination register, but no additional state
4188	* (AVX).
4189	*/
4190	typedef struct IEMOPMEDIAOPTF3
4191	{
4192	PFNIEMAIMPLMEDIAOPTF3U128 pfnU128;
4193	PFNIEMAIMPLMEDIAOPTF3U256 pfnU256;
4194	} IEMOPMEDIAOPTF3;
4195	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
4196	typedef IEMOPMEDIAOPTF3 const *PCIEMOPMEDIAOPTF3;
4197
4198	/** @def IEMOPMEDIAOPTF3_INIT_VARS_EX
4199	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4200	* given functions as initializers. For use in AVX functions where a pair of
4201	* functions are only used once and the function table need not be public. */
4202	#ifndef TST_IEM_CHECK_MC
4203	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4204	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4205	static IEMOPMEDIAOPTF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4206	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4207	# else
4208	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4209	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4210	# endif
4211	#else
4212	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4213	#endif
4214	/** @def IEMOPMEDIAOPTF3_INIT_VARS
4215	* Generate AVX function tables for the @a a_InstrNm instruction.
4216	* @sa IEMOPMEDIAOPTF3_INIT_VARS_EX */
4217	#define IEMOPMEDIAOPTF3_INIT_VARS(a_InstrNm) \
4218	IEMOPMEDIAOPTF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4219	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4220
4221	/**
4222	* Function table for media instruction taking one full sized media source
4223	* registers and one full sized destination register, but no additional state
4224	* (AVX).
4225	*/
4226	typedef struct IEMOPMEDIAOPTF2
4227	{
4228	PFNIEMAIMPLMEDIAOPTF2U128 pfnU128;
4229	PFNIEMAIMPLMEDIAOPTF2U256 pfnU256;
4230	} IEMOPMEDIAOPTF2;
4231	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
4232	typedef IEMOPMEDIAOPTF2 const *PCIEMOPMEDIAOPTF2;
4233
4234	/** @def IEMOPMEDIAOPTF2_INIT_VARS_EX
4235	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4236	* given functions as initializers. For use in AVX functions where a pair of
4237	* functions are only used once and the function table need not be public. */
4238	#ifndef TST_IEM_CHECK_MC
4239	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4240	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4241	static IEMOPMEDIAOPTF2 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4242	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4243	# else
4244	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4245	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4246	# endif
4247	#else
4248	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4249	#endif
4250	/** @def IEMOPMEDIAOPTF2_INIT_VARS
4251	* Generate AVX function tables for the @a a_InstrNm instruction.
4252	* @sa IEMOPMEDIAOPTF2_INIT_VARS_EX */
4253	#define IEMOPMEDIAOPTF2_INIT_VARS(a_InstrNm) \
4254	IEMOPMEDIAOPTF2_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4255	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4256
4257	/**
4258	* Function table for media instruction taking one full sized media source
4259	* register and one full sized destination register and an 8-bit immediate, but no additional state
4260	* (AVX).
4261	*/
4262	typedef struct IEMOPMEDIAOPTF2IMM8
4263	{
4264	PFNIEMAIMPLMEDIAOPTF2U128IMM8 pfnU128;
4265	PFNIEMAIMPLMEDIAOPTF2U256IMM8 pfnU256;
4266	} IEMOPMEDIAOPTF2IMM8;
4267	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
4268	typedef IEMOPMEDIAOPTF2IMM8 const *PCIEMOPMEDIAOPTF2IMM8;
4269
4270	/** @def IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX
4271	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4272	* given functions as initializers. For use in AVX functions where a pair of
4273	* functions are only used once and the function table need not be public. */
4274	#ifndef TST_IEM_CHECK_MC
4275	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4276	# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4277	static IEMOPMEDIAOPTF2IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4278	static IEMOPMEDIAOPTF2IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4279	# else
4280	# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4281	static IEMOPMEDIAOPTF2IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4282	# endif
4283	#else
4284	# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4285	#endif
4286	/** @def IEMOPMEDIAOPTF2IMM8_INIT_VARS
4287	* Generate AVX function tables for the @a a_InstrNm instruction.
4288	* @sa IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX */
4289	#define IEMOPMEDIAOPTF2IMM8_INIT_VARS(a_InstrNm) \
4290	IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u256),\
4291	RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u256_fallback))
4292
4293	/**
4294	* Function table for media instruction taking two full sized media source
4295	* registers and one full sized destination register and an 8-bit immediate, but no additional state
4296	* (AVX).
4297	*/
4298	typedef struct IEMOPMEDIAOPTF3IMM8
4299	{
4300	PFNIEMAIMPLMEDIAOPTF3U128IMM8 pfnU128;
4301	PFNIEMAIMPLMEDIAOPTF3U256IMM8 pfnU256;
4302	} IEMOPMEDIAOPTF3IMM8;
4303	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
4304	typedef IEMOPMEDIAOPTF3IMM8 const *PCIEMOPMEDIAOPTF3IMM8;
4305
4306	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX
4307	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4308	* given functions as initializers. For use in AVX functions where a pair of
4309	* functions are only used once and the function table need not be public. */
4310	#ifndef TST_IEM_CHECK_MC
4311	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4312	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4313	static IEMOPMEDIAOPTF3IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4314	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4315	# else
4316	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4317	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4318	# endif
4319	#else
4320	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4321	#endif
4322	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS
4323	* Generate AVX function tables for the @a a_InstrNm instruction.
4324	* @sa IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX */
4325	#define IEMOPMEDIAOPTF3IMM8_INIT_VARS(a_InstrNm) \
4326	IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4327	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4328	/** @} */
4329
4330
4331	/**
4332	* Function table for blend type instruction taking three full sized media source
4333	* registers and one full sized destination register, but no additional state
4334	* (AVX).
4335	*/
4336	typedef struct IEMOPBLENDOP
4337	{
4338	PFNIEMAIMPLAVXBLENDU128 pfnU128;
4339	PFNIEMAIMPLAVXBLENDU256 pfnU256;
4340	} IEMOPBLENDOP;
4341	/** Pointer to a media operation function table for 4 full sized ops (AVX). */
4342	typedef IEMOPBLENDOP const *PCIEMOPBLENDOP;
4343
4344	/** @def IEMOPBLENDOP_INIT_VARS_EX
4345	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4346	* given functions as initializers. For use in AVX functions where a pair of
4347	* functions are only used once and the function table need not be public. */
4348	#ifndef TST_IEM_CHECK_MC
4349	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4350	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4351	static IEMOPBLENDOP const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4352	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4353	# else
4354	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4355	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4356	# endif
4357	#else
4358	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4359	#endif
4360	/** @def IEMOPBLENDOP_INIT_VARS
4361	* Generate AVX function tables for the @a a_InstrNm instruction.
4362	* @sa IEMOPBLENDOP_INIT_VARS_EX */
4363	#define IEMOPBLENDOP_INIT_VARS(a_InstrNm) \
4364	IEMOPBLENDOP_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4365	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4366
4367
4368	/** @name SSE/AVX single/double precision floating point operations.
4369	* @{ */
4370	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
4371	typedef FNIEMAIMPLFPSSEF2U128 *PFNIEMAIMPLFPSSEF2U128;
4372	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128R32,(uint32_t uMxCsrIn, PX86XMMREG Result, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
4373	typedef FNIEMAIMPLFPSSEF2U128R32 *PFNIEMAIMPLFPSSEF2U128R32;
4374	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128R64,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
4375	typedef FNIEMAIMPLFPSSEF2U128R64 *PFNIEMAIMPLFPSSEF2U128R64;
4376
4377	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
4378	typedef FNIEMAIMPLFPAVXF3U128 *PFNIEMAIMPLFPAVXF3U128;
4379	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U128R32,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
4380	typedef FNIEMAIMPLFPAVXF3U128R32 *PFNIEMAIMPLFPAVXF3U128R32;
4381	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U128R64,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
4382	typedef FNIEMAIMPLFPAVXF3U128R64 *PFNIEMAIMPLFPAVXF3U128R64;
4383
4384	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U256,(uint32_t uMxCsrIn, PX86YMMREG pResult, PCX86YMMREG puSrc1, PCX86YMMREG puSrc2));
4385	typedef FNIEMAIMPLFPAVXF3U256 *PFNIEMAIMPLFPAVXF3U256;
4386
4387	FNIEMAIMPLFPSSEF2U128 iemAImpl_addps_u128;
4388	FNIEMAIMPLFPSSEF2U128 iemAImpl_addpd_u128;
4389	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulps_u128;
4390	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulpd_u128;
4391	FNIEMAIMPLFPSSEF2U128 iemAImpl_subps_u128;
4392	FNIEMAIMPLFPSSEF2U128 iemAImpl_subpd_u128;
4393	FNIEMAIMPLFPSSEF2U128 iemAImpl_minps_u128;
4394	FNIEMAIMPLFPSSEF2U128 iemAImpl_minpd_u128;
4395	FNIEMAIMPLFPSSEF2U128 iemAImpl_divps_u128;
4396	FNIEMAIMPLFPSSEF2U128 iemAImpl_divpd_u128;
4397	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxps_u128;
4398	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxpd_u128;
4399	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddps_u128;
4400	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddpd_u128;
4401	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubps_u128;
4402	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubpd_u128;
4403	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtps_u128;
4404	FNIEMAIMPLFPSSEF2U128 iemAImpl_rsqrtps_u128;
4405	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtpd_u128;
4406	FNIEMAIMPLFPSSEF2U128 iemAImpl_rcpps_u128;
4407	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubps_u128;
4408	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubpd_u128;
4409	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2ps_u128;
4410	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2pd_u128;
4411
4412	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2ps_u128;
4413	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2dq_u128;
4414	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttps2dq_u128;
4415	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttpd2dq_u128;
4416	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2pd_u128;
4417	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2dq_u128;
4418
4419	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_addss_u128_r32;
4420	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_addsd_u128_r64;
4421	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_mulss_u128_r32;
4422	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_mulsd_u128_r64;
4423	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_subss_u128_r32;
4424	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_subsd_u128_r64;
4425	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_minss_u128_r32;
4426	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_minsd_u128_r64;
4427	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_divss_u128_r32;
4428	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_divsd_u128_r64;
4429	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_maxss_u128_r32;
4430	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_maxsd_u128_r64;
4431	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_cvtss2sd_u128_r32;
4432	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_cvtsd2ss_u128_r64;
4433	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_sqrtss_u128_r32;
4434	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_sqrtsd_u128_r64;
4435	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_rsqrtss_u128_r32;
4436	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_rcpss_u128_r32;
4437
4438	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddps_u128, iemAImpl_vaddps_u128_fallback;
4439	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddpd_u128, iemAImpl_vaddpd_u128_fallback;
4440	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulps_u128, iemAImpl_vmulps_u128_fallback;
4441	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulpd_u128, iemAImpl_vmulpd_u128_fallback;
4442	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubps_u128, iemAImpl_vsubps_u128_fallback;
4443	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubpd_u128, iemAImpl_vsubpd_u128_fallback;
4444	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminps_u128, iemAImpl_vminps_u128_fallback;
4445	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminpd_u128, iemAImpl_vminpd_u128_fallback;
4446	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivps_u128, iemAImpl_vdivps_u128_fallback;
4447	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivpd_u128, iemAImpl_vdivpd_u128_fallback;
4448	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxps_u128, iemAImpl_vmaxps_u128_fallback;
4449	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxpd_u128, iemAImpl_vmaxpd_u128_fallback;
4450	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddps_u128, iemAImpl_vhaddps_u128_fallback;
4451	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddpd_u128, iemAImpl_vhaddpd_u128_fallback;
4452	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubps_u128, iemAImpl_vhsubps_u128_fallback;
4453	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubpd_u128, iemAImpl_vhsubpd_u128_fallback;
4454	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtps_u128, iemAImpl_vsqrtps_u128_fallback;
4455	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtpd_u128, iemAImpl_vsqrtpd_u128_fallback;
4456	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubps_u128, iemAImpl_vaddsubps_u128_fallback;
4457	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubpd_u128, iemAImpl_vaddsubpd_u128_fallback;
4458	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtpd2ps_u128, iemAImpl_vcvtpd2ps_u128_fallback;
4459	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtps2pd_u128, iemAImpl_vcvtps2pd_u128_fallback;
4460
4461	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vaddss_u128_r32, iemAImpl_vaddss_u128_r32_fallback;
4462	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vaddsd_u128_r64, iemAImpl_vaddsd_u128_r64_fallback;
4463	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmulss_u128_r32, iemAImpl_vmulss_u128_r32_fallback;
4464	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmulsd_u128_r64, iemAImpl_vmulsd_u128_r64_fallback;
4465	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsubss_u128_r32, iemAImpl_vsubss_u128_r32_fallback;
4466	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsubsd_u128_r64, iemAImpl_vsubsd_u128_r64_fallback;
4467	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vminss_u128_r32, iemAImpl_vminss_u128_r32_fallback;
4468	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vminsd_u128_r64, iemAImpl_vminsd_u128_r64_fallback;
4469	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vdivss_u128_r32, iemAImpl_vdivss_u128_r32_fallback;
4470	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vdivsd_u128_r64, iemAImpl_vdivsd_u128_r64_fallback;
4471	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmaxss_u128_r32, iemAImpl_vmaxss_u128_r32_fallback;
4472	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmaxsd_u128_r64, iemAImpl_vmaxsd_u128_r64_fallback;
4473	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsqrtss_u128_r32, iemAImpl_vsqrtss_u128_r32_fallback;
4474	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsqrtsd_u128_r64, iemAImpl_vsqrtsd_u128_r64_fallback;
4475
4476	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddps_u256, iemAImpl_vaddps_u256_fallback;
4477	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddpd_u256, iemAImpl_vaddpd_u256_fallback;
4478	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulps_u256, iemAImpl_vmulps_u256_fallback;
4479	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulpd_u256, iemAImpl_vmulpd_u256_fallback;
4480	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubps_u256, iemAImpl_vsubps_u256_fallback;
4481	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubpd_u256, iemAImpl_vsubpd_u256_fallback;
4482	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminps_u256, iemAImpl_vminps_u256_fallback;
4483	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminpd_u256, iemAImpl_vminpd_u256_fallback;
4484	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivps_u256, iemAImpl_vdivps_u256_fallback;
4485	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivpd_u256, iemAImpl_vdivpd_u256_fallback;
4486	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxps_u256, iemAImpl_vmaxps_u256_fallback;
4487	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxpd_u256, iemAImpl_vmaxpd_u256_fallback;
4488	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddps_u256, iemAImpl_vhaddps_u256_fallback;
4489	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddpd_u256, iemAImpl_vhaddpd_u256_fallback;
4490	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubps_u256, iemAImpl_vhsubps_u256_fallback;
4491	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubpd_u256, iemAImpl_vhsubpd_u256_fallback;
4492	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubps_u256, iemAImpl_vhaddsubps_u256_fallback;
4493	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubpd_u256, iemAImpl_vhaddsubpd_u256_fallback;
4494	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtpd2ps_u256, iemAImpl_vcvtpd2ps_u256_fallback;
4495	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtps2pd_u256, iemAImpl_vcvtps2pd_u256_fallback;
4496	/** @} */
4497
4498	/** @name C instruction implementations for anything slightly complicated.
4499	* @{ */
4500
4501	/**
4502	* For typedef'ing or declaring a C instruction implementation function taking
4503	* no extra arguments.
4504	*
4505	* @param a_Name The name of the type.
4506	*/
4507	# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
4508	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
4509	/**
4510	* For defining a C instruction implementation function taking no extra
4511	* arguments.
4512	*
4513	* @param a_Name The name of the function
4514	*/
4515	# define IEM_CIMPL_DEF_0(a_Name) \
4516	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
4517	/**
4518	* Prototype version of IEM_CIMPL_DEF_0.
4519	*/
4520	# define IEM_CIMPL_PROTO_0(a_Name) \
4521	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
4522	/**
4523	* For calling a C instruction implementation function taking no extra
4524	* arguments.
4525	*
4526	* This special call macro adds default arguments to the call and allow us to
4527	* change these later.
4528	*
4529	* @param a_fn The name of the function.
4530	*/
4531	# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
4532
4533	/** Type for a C instruction implementation function taking no extra
4534	* arguments. */
4535	typedef IEM_CIMPL_DECL_TYPE_0(FNIEMCIMPL0);
4536	/** Function pointer type for a C instruction implementation function taking
4537	* no extra arguments. */
4538	typedef FNIEMCIMPL0 *PFNIEMCIMPL0;
4539
4540	/**
4541	* For typedef'ing or declaring a C instruction implementation function taking
4542	* one extra argument.
4543	*
4544	* @param a_Name The name of the type.
4545	* @param a_Type0 The argument type.
4546	* @param a_Arg0 The argument name.
4547	*/
4548	# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
4549	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
4550	/**
4551	* For defining a C instruction implementation function taking one extra
4552	* argument.
4553	*
4554	* @param a_Name The name of the function
4555	* @param a_Type0 The argument type.
4556	* @param a_Arg0 The argument name.
4557	*/
4558	# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
4559	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
4560	/**
4561	* Prototype version of IEM_CIMPL_DEF_1.
4562	*/
4563	# define IEM_CIMPL_PROTO_1(a_Name, a_Type0, a_Arg0) \
4564	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
4565	/**
4566	* For calling a C instruction implementation function taking one extra
4567	* argument.
4568	*
4569	* This special call macro adds default arguments to the call and allow us to
4570	* change these later.
4571	*
4572	* @param a_fn The name of the function.
4573	* @param a0 The name of the 1st argument.
4574	*/
4575	# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
4576
4577	/**
4578	* For typedef'ing or declaring a C instruction implementation function taking
4579	* two extra arguments.
4580	*
4581	* @param a_Name The name of the type.
4582	* @param a_Type0 The type of the 1st argument
4583	* @param a_Arg0 The name of the 1st argument.
4584	* @param a_Type1 The type of the 2nd argument.
4585	* @param a_Arg1 The name of the 2nd argument.
4586	*/
4587	# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
4588	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
4589	/**
4590	* For defining a C instruction implementation function taking two extra
4591	* arguments.
4592	*
4593	* @param a_Name The name of the function.
4594	* @param a_Type0 The type of the 1st argument
4595	* @param a_Arg0 The name of the 1st argument.
4596	* @param a_Type1 The type of the 2nd argument.
4597	* @param a_Arg1 The name of the 2nd argument.
4598	*/
4599	# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
4600	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
4601	/**
4602	* Prototype version of IEM_CIMPL_DEF_2.
4603	*/
4604	# define IEM_CIMPL_PROTO_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
4605	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
4606	/**
4607	* For calling a C instruction implementation function taking two extra
4608	* arguments.
4609	*
4610	* This special call macro adds default arguments to the call and allow us to
4611	* change these later.
4612	*
4613	* @param a_fn The name of the function.
4614	* @param a0 The name of the 1st argument.
4615	* @param a1 The name of the 2nd argument.
4616	*/
4617	# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
4618
4619	/**
4620	* For typedef'ing or declaring a C instruction implementation function taking
4621	* three extra arguments.
4622	*
4623	* @param a_Name The name of the type.
4624	* @param a_Type0 The type of the 1st argument
4625	* @param a_Arg0 The name of the 1st argument.
4626	* @param a_Type1 The type of the 2nd argument.
4627	* @param a_Arg1 The name of the 2nd argument.
4628	* @param a_Type2 The type of the 3rd argument.
4629	* @param a_Arg2 The name of the 3rd argument.
4630	*/
4631	# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
4632	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
4633	/**
4634	* For defining a C instruction implementation function taking three extra
4635	* arguments.
4636	*
4637	* @param a_Name The name of the function.
4638	* @param a_Type0 The type of the 1st argument
4639	* @param a_Arg0 The name of the 1st argument.
4640	* @param a_Type1 The type of the 2nd argument.
4641	* @param a_Arg1 The name of the 2nd argument.
4642	* @param a_Type2 The type of the 3rd argument.
4643	* @param a_Arg2 The name of the 3rd argument.
4644	*/
4645	# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
4646	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
4647	/**
4648	* Prototype version of IEM_CIMPL_DEF_3.
4649	*/
4650	# define IEM_CIMPL_PROTO_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
4651	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
4652	/**
4653	* For calling a C instruction implementation function taking three extra
4654	* arguments.
4655	*
4656	* This special call macro adds default arguments to the call and allow us to
4657	* change these later.
4658	*
4659	* @param a_fn The name of the function.
4660	* @param a0 The name of the 1st argument.
4661	* @param a1 The name of the 2nd argument.
4662	* @param a2 The name of the 3rd argument.
4663	*/
4664	# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
4665
4666
4667	/**
4668	* For typedef'ing or declaring a C instruction implementation function taking
4669	* four extra arguments.
4670	*
4671	* @param a_Name The name of the type.
4672	* @param a_Type0 The type of the 1st argument
4673	* @param a_Arg0 The name of the 1st argument.
4674	* @param a_Type1 The type of the 2nd argument.
4675	* @param a_Arg1 The name of the 2nd argument.
4676	* @param a_Type2 The type of the 3rd argument.
4677	* @param a_Arg2 The name of the 3rd argument.
4678	* @param a_Type3 The type of the 4th argument.
4679	* @param a_Arg3 The name of the 4th argument.
4680	*/
4681	# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
4682	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
4683	/**
4684	* For defining a C instruction implementation function taking four extra
4685	* arguments.
4686	*
4687	* @param a_Name The name of the function.
4688	* @param a_Type0 The type of the 1st argument
4689	* @param a_Arg0 The name of the 1st argument.
4690	* @param a_Type1 The type of the 2nd argument.
4691	* @param a_Arg1 The name of the 2nd argument.
4692	* @param a_Type2 The type of the 3rd argument.
4693	* @param a_Arg2 The name of the 3rd argument.
4694	* @param a_Type3 The type of the 4th argument.
4695	* @param a_Arg3 The name of the 4th argument.
4696	*/
4697	# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
4698	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4699	a_Type2 a_Arg2, a_Type3 a_Arg3))
4700	/**
4701	* Prototype version of IEM_CIMPL_DEF_4.
4702	*/
4703	# define IEM_CIMPL_PROTO_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
4704	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4705	a_Type2 a_Arg2, a_Type3 a_Arg3))
4706	/**
4707	* For calling a C instruction implementation function taking four extra
4708	* arguments.
4709	*
4710	* This special call macro adds default arguments to the call and allow us to
4711	* change these later.
4712	*
4713	* @param a_fn The name of the function.
4714	* @param a0 The name of the 1st argument.
4715	* @param a1 The name of the 2nd argument.
4716	* @param a2 The name of the 3rd argument.
4717	* @param a3 The name of the 4th argument.
4718	*/
4719	# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
4720
4721
4722	/**
4723	* For typedef'ing or declaring a C instruction implementation function taking
4724	* five extra arguments.
4725	*
4726	* @param a_Name The name of the type.
4727	* @param a_Type0 The type of the 1st argument
4728	* @param a_Arg0 The name of the 1st argument.
4729	* @param a_Type1 The type of the 2nd argument.
4730	* @param a_Arg1 The name of the 2nd argument.
4731	* @param a_Type2 The type of the 3rd argument.
4732	* @param a_Arg2 The name of the 3rd argument.
4733	* @param a_Type3 The type of the 4th argument.
4734	* @param a_Arg3 The name of the 4th argument.
4735	* @param a_Type4 The type of the 5th argument.
4736	* @param a_Arg4 The name of the 5th argument.
4737	*/
4738	# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
4739	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, \
4740	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
4741	a_Type3 a_Arg3, a_Type4 a_Arg4))
4742	/**
4743	* For defining a C instruction implementation function taking five extra
4744	* arguments.
4745	*
4746	* @param a_Name The name of the function.
4747	* @param a_Type0 The type of the 1st argument
4748	* @param a_Arg0 The name of the 1st argument.
4749	* @param a_Type1 The type of the 2nd argument.
4750	* @param a_Arg1 The name of the 2nd argument.
4751	* @param a_Type2 The type of the 3rd argument.
4752	* @param a_Arg2 The name of the 3rd argument.
4753	* @param a_Type3 The type of the 4th argument.
4754	* @param a_Arg3 The name of the 4th argument.
4755	* @param a_Type4 The type of the 5th argument.
4756	* @param a_Arg4 The name of the 5th argument.
4757	*/
4758	# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
4759	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4760	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
4761	/**
4762	* Prototype version of IEM_CIMPL_DEF_5.
4763	*/
4764	# define IEM_CIMPL_PROTO_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
4765	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4766	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
4767	/**
4768	* For calling a C instruction implementation function taking five extra
4769	* arguments.
4770	*
4771	* This special call macro adds default arguments to the call and allow us to
4772	* change these later.
4773	*
4774	* @param a_fn The name of the function.
4775	* @param a0 The name of the 1st argument.
4776	* @param a1 The name of the 2nd argument.
4777	* @param a2 The name of the 3rd argument.
4778	* @param a3 The name of the 4th argument.
4779	* @param a4 The name of the 5th argument.
4780	*/
4781	# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
4782
4783	/** @} */
4784
4785
4786	/** @name Opcode Decoder Function Types.
4787	* @{ */
4788
4789	/** @typedef PFNIEMOP
4790	* Pointer to an opcode decoder function.
4791	*/
4792
4793	/** @def FNIEMOP_DEF
4794	* Define an opcode decoder function.
4795	*
4796	* We're using macors for this so that adding and removing parameters as well as
4797	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL
4798	*
4799	* @param a_Name The function name.
4800	*/
4801
4802	/** @typedef PFNIEMOPRM
4803	* Pointer to an opcode decoder function with RM byte.
4804	*/
4805
4806	/** @def FNIEMOPRM_DEF
4807	* Define an opcode decoder function with RM byte.
4808	*
4809	* We're using macors for this so that adding and removing parameters as well as
4810	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL_1
4811	*
4812	* @param a_Name The function name.
4813	*/
4814
4815	#if defined(__GNUC__) && defined(RT_ARCH_X86)
4816	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOP)(PVMCPUCC pVCpu);
4817	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4818	# define FNIEMOP_DEF(a_Name) \
4819	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu)
4820	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4821	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
4822	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4823	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
4824
4825	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
4826	typedef VBOXSTRICTRC (__fastcall * PFNIEMOP)(PVMCPUCC pVCpu);
4827	typedef VBOXSTRICTRC (__fastcall * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4828	# define FNIEMOP_DEF(a_Name) \
4829	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
4830	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4831	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
4832	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4833	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
4834
4835	#elif defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
4836	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
4837	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4838	# define FNIEMOP_DEF(a_Name) \
4839	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu)
4840	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4841	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
4842	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4843	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
4844
4845	#else
4846	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
4847	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4848	# define FNIEMOP_DEF(a_Name) \
4849	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
4850	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4851	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
4852	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4853	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
4854
4855	#endif
4856	#define FNIEMOPRM_DEF(a_Name) FNIEMOP_DEF_1(a_Name, uint8_t, bRm)
4857
4858	/**
4859	* Call an opcode decoder function.
4860	*
4861	* We're using macors for this so that adding and removing parameters can be
4862	* done as we please. See FNIEMOP_DEF.
4863	*/
4864	#define FNIEMOP_CALL(a_pfn) (a_pfn)(pVCpu)
4865
4866	/**
4867	* Call a common opcode decoder function taking one extra argument.
4868	*
4869	* We're using macors for this so that adding and removing parameters can be
4870	* done as we please. See FNIEMOP_DEF_1.
4871	*/
4872	#define FNIEMOP_CALL_1(a_pfn, a0) (a_pfn)(pVCpu, a0)
4873
4874	/**
4875	* Call a common opcode decoder function taking one extra argument.
4876	*
4877	* We're using macors for this so that adding and removing parameters can be
4878	* done as we please. See FNIEMOP_DEF_1.
4879	*/
4880	#define FNIEMOP_CALL_2(a_pfn, a0, a1) (a_pfn)(pVCpu, a0, a1)
4881	/** @} */
4882
4883
4884	/** @name Misc Helpers
4885	* @{ */
4886
4887	/** Used to shut up GCC warnings about variables that 'may be used uninitialized'
4888	* due to GCC lacking knowledge about the value range of a switch. */
4889	#if RT_CPLUSPLUS_PREREQ(202000)
4890	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: [[unlikely]] AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
4891	#else
4892	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
4893	#endif
4894
4895	/** Variant of IEM_NOT_REACHED_DEFAULT_CASE_RET that returns a custom value. */
4896	#if RT_CPLUSPLUS_PREREQ(202000)
4897	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: [[unlikely]] AssertFailedReturn(a_RetValue)
4898	#else
4899	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: AssertFailedReturn(a_RetValue)
4900	#endif
4901
4902	/**
4903	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
4904	* occation.
4905	*/
4906	#ifdef LOG_ENABLED
4907	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
4908	do { \
4909	/Log/ LogAlways(("%s: returning IEM_RETURN_ASPECT_NOT_IMPLEMENTED (line %d)\n", __FUNCTION__, __LINE__)); \
4910	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
4911	} while (0)
4912	#else
4913	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
4914	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
4915	#endif
4916
4917	/**
4918	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
4919	* occation using the supplied logger statement.
4920	*
4921	* @param a_LoggerArgs What to log on failure.
4922	*/
4923	#ifdef LOG_ENABLED
4924	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
4925	do { \
4926	LogAlways((LOG_FN_FMT ": ", __PRETTY_FUNCTION__)); LogAlways(a_LoggerArgs); \
4927	/LogFunc(a_LoggerArgs);/ \
4928	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
4929	} while (0)
4930	#else
4931	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
4932	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
4933	#endif
4934
4935	/**
4936	* Gets the CPU mode (from fExec) as a IEMMODE value.
4937	*
4938	* @returns IEMMODE
4939	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4940	*/
4941	#define IEM_GET_CPU_MODE(a_pVCpu) ((a_pVCpu)->iem.s.fExec & IEM_F_MODE_CPUMODE_MASK)
4942
4943	/**
4944	* Check if we're currently executing in real or virtual 8086 mode.
4945	*
4946	* @returns @c true if it is, @c false if not.
4947	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4948	*/
4949	#define IEM_IS_REAL_OR_V86_MODE(a_pVCpu) (( ((a_pVCpu)->iem.s.fExec ^ IEM_F_MODE_X86_PROT_MASK) \
4950	& (IEM_F_MODE_X86_V86_MASK \| IEM_F_MODE_X86_PROT_MASK)) != 0)
4951
4952	/**
4953	* Check if we're currently executing in virtual 8086 mode.
4954	*
4955	* @returns @c true if it is, @c false if not.
4956	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4957	*/
4958	#define IEM_IS_V86_MODE(a_pVCpu) (((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_V86_MASK) != 0)
4959
4960	/**
4961	* Check if we're currently executing in long mode.
4962	*
4963	* @returns @c true if it is, @c false if not.
4964	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4965	*/
4966	#define IEM_IS_LONG_MODE(a_pVCpu) (CPUMIsGuestInLongModeEx(IEM_GET_CTX(a_pVCpu)))
4967
4968	/**
4969	* Check if we're currently executing in a 16-bit code segment.
4970	*
4971	* @returns @c true if it is, @c false if not.
4972	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4973	*/
4974	#define IEM_IS_16BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_16BIT)
4975
4976	/**
4977	* Check if we're currently executing in a 32-bit code segment.
4978	*
4979	* @returns @c true if it is, @c false if not.
4980	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4981	*/
4982	#define IEM_IS_32BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_32BIT)
4983
4984	/**
4985	* Check if we're currently executing in a 64-bit code segment.
4986	*
4987	* @returns @c true if it is, @c false if not.
4988	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4989	*/
4990	#define IEM_IS_64BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_64BIT)
4991
4992	/**
4993	* Check if we're currently executing in real mode.
4994	*
4995	* @returns @c true if it is, @c false if not.
4996	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4997	*/
4998	#define IEM_IS_REAL_MODE(a_pVCpu) (!((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_PROT_MASK))
4999
5000	/**
5001	* Gets the current protection level (CPL).
5002	*
5003	* @returns 0..3
5004	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5005	*/
5006	#define IEM_GET_CPL(a_pVCpu) (((a_pVCpu)->iem.s.fExec >> IEM_F_X86_CPL_SHIFT) & IEM_F_X86_CPL_SMASK)
5007
5008	/**
5009	* Sets the current protection level (CPL).
5010	*
5011	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5012	*/
5013	#define IEM_SET_CPL(a_pVCpu, a_uCpl) \
5014	do { (a_pVCpu)->iem.s.fExec = ((a_pVCpu)->iem.s.fExec & ~IEM_F_X86_CPL_MASK) \| ((a_uCpl) << IEM_F_X86_CPL_SHIFT); } while (0)
5015
5016	/**
5017	* Returns a (const) pointer to the CPUMFEATURES for the guest CPU.
5018	* @returns PCCPUMFEATURES
5019	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5020	*/
5021	#define IEM_GET_GUEST_CPU_FEATURES(a_pVCpu) (&((a_pVCpu)->CTX_SUFF(pVM)->cpum.ro.GuestFeatures))
5022
5023	/**
5024	* Returns a (const) pointer to the CPUMFEATURES for the host CPU.
5025	* @returns PCCPUMFEATURES
5026	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5027	*/
5028	#define IEM_GET_HOST_CPU_FEATURES(a_pVCpu) (&g_CpumHostFeatures.s)
5029
5030	/**
5031	* Evaluates to true if we're presenting an Intel CPU to the guest.
5032	*/
5033	#define IEM_IS_GUEST_CPU_INTEL(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL )
5034
5035	/**
5036	* Evaluates to true if we're presenting an AMD CPU to the guest.
5037	*/
5038	#define IEM_IS_GUEST_CPU_AMD(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_AMD \|\| (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_HYGON )
5039
5040	/**
5041	* Check if the address is canonical.
5042	*/
5043	#define IEM_IS_CANONICAL(a_u64Addr) X86_IS_CANONICAL(a_u64Addr)
5044
5045	/** Checks if the ModR/M byte is in register mode or not. */
5046	#define IEM_IS_MODRM_REG_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT) )
5047	/** Checks if the ModR/M byte is in memory mode or not. */
5048	#define IEM_IS_MODRM_MEM_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT) )
5049
5050	/**
5051	* Gets the register (reg) part of a ModR/M encoding, with REX.R added in.
5052	*
5053	* For use during decoding.
5054	*/
5055	#define IEM_GET_MODRM_REG(a_pVCpu, a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| (a_pVCpu)->iem.s.uRexReg )
5056	/**
5057	* Gets the r/m part of a ModR/M encoding as a register index, with REX.B added in.
5058	*
5059	* For use during decoding.
5060	*/
5061	#define IEM_GET_MODRM_RM(a_pVCpu, a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) \| (a_pVCpu)->iem.s.uRexB )
5062
5063	/**
5064	* Gets the register (reg) part of a ModR/M encoding, without REX.R.
5065	*
5066	* For use during decoding.
5067	*/
5068	#define IEM_GET_MODRM_REG_8(a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) )
5069	/**
5070	* Gets the r/m part of a ModR/M encoding as a register index, without REX.B.
5071	*
5072	* For use during decoding.
5073	*/
5074	#define IEM_GET_MODRM_RM_8(a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) )
5075
5076	/**
5077	* Gets the register (reg) part of a ModR/M encoding as an extended 8-bit
5078	* register index, with REX.R added in.
5079	*
5080	* For use during decoding.
5081	*
5082	* @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
5083	*/
5084	#define IEM_GET_MODRM_REG_EX8(a_pVCpu, a_bRm) \
5085	( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
5086	\|\| !((a_bRm) & (4 << X86_MODRM_REG_SHIFT)) /* IEM_GET_MODRM_REG(pVCpu, a_bRm) < 4 */ \
5087	? IEM_GET_MODRM_REG(pVCpu, a_bRm) : (((a_bRm) >> X86_MODRM_REG_SHIFT) & 3) \| 16)
5088	/**
5089	* Gets the r/m part of a ModR/M encoding as an extended 8-bit register index,
5090	* with REX.B added in.
5091	*
5092	* For use during decoding.
5093	*
5094	* @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
5095	*/
5096	#define IEM_GET_MODRM_RM_EX8(a_pVCpu, a_bRm) \
5097	( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
5098	\|\| !((a_bRm) & 4) /* IEM_GET_MODRM_RM(pVCpu, a_bRm) < 4 */ \
5099	? IEM_GET_MODRM_RM(pVCpu, a_bRm) : ((a_bRm) & 3) \| 16)
5100
5101	/**
5102	* Combines the prefix REX and ModR/M byte for passing to
5103	* iemOpHlpCalcRmEffAddrThreadedAddr64().
5104	*
5105	* @returns The ModRM byte but with bit 3 set to REX.B and bit 4 to REX.X.
5106	* The two bits are part of the REG sub-field, which isn't needed in
5107	* iemOpHlpCalcRmEffAddrThreadedAddr64().
5108	*
5109	* For use during decoding/recompiling.
5110	*/
5111	#define IEM_GET_MODRM_EX(a_pVCpu, a_bRm) \
5112	( ((a_bRm) & ~X86_MODRM_REG_MASK) \
5113	\| (uint8_t)( (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X)) >> (25 - 3) ) )
5114	AssertCompile(IEM_OP_PRF_REX_B == RT_BIT_32(25));
5115	AssertCompile(IEM_OP_PRF_REX_X == RT_BIT_32(26));
5116
5117	/**
5118	* Gets the effective VEX.VVVV value.
5119	*
5120	* The 4th bit is ignored if not 64-bit code.
5121	* @returns effective V-register value.
5122	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5123	*/
5124	#define IEM_GET_EFFECTIVE_VVVV(a_pVCpu) \
5125	(IEM_IS_64BIT_CODE(a_pVCpu) ? (a_pVCpu)->iem.s.uVex3rdReg : (a_pVCpu)->iem.s.uVex3rdReg & 7)
5126
5127
5128	/**
5129	* Gets the register (reg) part of a the special 4th register byte used by
5130	* vblendvps and vblendvpd.
5131	*
5132	* For use during decoding.
5133	*/
5134	#define IEM_GET_IMM8_REG(a_pVCpu, a_bRegImm8) \
5135	(IEM_IS_64BIT_CODE(a_pVCpu) ? (a_bRegImm8) >> 4 : ((a_bRegImm8) >> 4) & 7)
5136
5137
5138	/**
5139	* Checks if we're executing inside an AMD-V or VT-x guest.
5140	*/
5141	#if defined(VBOX_WITH_NESTED_HWVIRT_VMX) \|\| defined(VBOX_WITH_NESTED_HWVIRT_SVM)
5142	# define IEM_IS_IN_GUEST(a_pVCpu) RT_BOOL((a_pVCpu)->iem.s.fExec & IEM_F_X86_CTX_IN_GUEST)
5143	#else
5144	# define IEM_IS_IN_GUEST(a_pVCpu) false
5145	#endif
5146
5147
5148	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5149
5150	/**
5151	* Check if the guest has entered VMX root operation.
5152	*/
5153	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxRootMode(IEM_GET_CTX(a_pVCpu)))
5154
5155	/**
5156	* Check if the guest has entered VMX non-root operation.
5157	*/
5158	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) ( ((a_pVCpu)->iem.s.fExec & (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST)) \
5159	== (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST) )
5160
5161	/**
5162	* Check if the nested-guest has the given Pin-based VM-execution control set.
5163	*/
5164	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_PinCtl) (CPUMIsGuestVmxPinCtlsSet(IEM_GET_CTX(a_pVCpu), (a_PinCtl)))
5165
5166	/**
5167	* Check if the nested-guest has the given Processor-based VM-execution control set.
5168	*/
5169	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_ProcCtl) (CPUMIsGuestVmxProcCtlsSet(IEM_GET_CTX(a_pVCpu), (a_ProcCtl)))
5170
5171	/**
5172	* Check if the nested-guest has the given Secondary Processor-based VM-execution
5173	* control set.
5174	*/
5175	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_ProcCtl2) (CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(a_pVCpu), (a_ProcCtl2)))
5176
5177	/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
5178	# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
5179
5180	/** Whether a shadow VMCS is present for the given VCPU. */
5181	# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
5182
5183	/** Gets the VMXON region pointer. */
5184	# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
5185
5186	/** Gets the guest-physical address of the current VMCS for the given VCPU. */
5187	# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
5188
5189	/** Whether a current VMCS is present for the given VCPU. */
5190	# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
5191
5192	/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
5193	# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
5194	do \
5195	{ \
5196	Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
5197	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
5198	} while (0)
5199
5200	/** Clears any current VMCS for the given VCPU. */
5201	# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
5202	do \
5203	{ \
5204	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
5205	} while (0)
5206
5207	/**
5208	* Invokes the VMX VM-exit handler for an instruction intercept.
5209	*/
5210	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) \
5211	do { return iemVmxVmexitInstr((a_pVCpu), (a_uExitReason), (a_cbInstr)); } while (0)
5212
5213	/**
5214	* Invokes the VMX VM-exit handler for an instruction intercept where the
5215	* instruction provides additional VM-exit information.
5216	*/
5217	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) \
5218	do { return iemVmxVmexitInstrNeedsInfo((a_pVCpu), (a_uExitReason), (a_uInstrId), (a_cbInstr)); } while (0)
5219
5220	/**
5221	* Invokes the VMX VM-exit handler for a task switch.
5222	*/
5223	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) \
5224	do { return iemVmxVmexitTaskSwitch((a_pVCpu), (a_enmTaskSwitch), (a_SelNewTss), (a_cbInstr)); } while (0)
5225
5226	/**
5227	* Invokes the VMX VM-exit handler for MWAIT.
5228	*/
5229	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) \
5230	do { return iemVmxVmexitInstrMwait((a_pVCpu), (a_fMonitorArmed), (a_cbInstr)); } while (0)
5231
5232	/**
5233	* Invokes the VMX VM-exit handler for EPT faults.
5234	*/
5235	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) \
5236	do { return iemVmxVmexitEpt(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr); } while (0)
5237
5238	/**
5239	* Invokes the VMX VM-exit handler.
5240	*/
5241	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) \
5242	do { return iemVmxVmexit((a_pVCpu), (a_uExitReason), (a_uExitQual)); } while (0)
5243
5244	#else
5245	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (false)
5246	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (false)
5247	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_cbInstr) (false)
5248	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_cbInstr) (false)
5249	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_cbInstr) (false)
5250	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5251	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5252	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5253	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5254	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5255	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) do { return VERR_VMX_IPE_1; } while (0)
5256
5257	#endif
5258
5259	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5260	/**
5261	* Checks if we're executing a guest using AMD-V.
5262	*/
5263	# define IEM_SVM_IS_IN_GUEST(a_pVCpu) ( (a_pVCpu->iem.s.fExec & (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST)) \
5264	== (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST))
5265	/**
5266	* Check if an SVM control/instruction intercept is set.
5267	*/
5268	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) \
5269	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmCtrlInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_Intercept)))
5270
5271	/**
5272	* Check if an SVM read CRx intercept is set.
5273	*/
5274	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
5275	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
5276
5277	/**
5278	* Check if an SVM write CRx intercept is set.
5279	*/
5280	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
5281	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
5282
5283	/**
5284	* Check if an SVM read DRx intercept is set.
5285	*/
5286	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
5287	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
5288
5289	/**
5290	* Check if an SVM write DRx intercept is set.
5291	*/
5292	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
5293	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
5294
5295	/**
5296	* Check if an SVM exception intercept is set.
5297	*/
5298	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) \
5299	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmXcptInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uVector)))
5300
5301	/**
5302	* Invokes the SVM \#VMEXIT handler for the nested-guest.
5303	*/
5304	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
5305	do { return iemSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2)); } while (0)
5306
5307	/**
5308	* Invokes the 'MOV CRx' SVM \#VMEXIT handler after constructing the
5309	* corresponding decode assist information.
5310	*/
5311	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) \
5312	do \
5313	{ \
5314	uint64_t uExitInfo1; \
5315	if ( IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmDecodeAssists \
5316	&& (a_enmAccessCrX) == IEMACCESSCRX_MOV_CRX) \
5317	uExitInfo1 = SVM_EXIT1_MOV_CRX_MASK \| ((a_iGReg) & 7); \
5318	else \
5319	uExitInfo1 = 0; \
5320	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, uExitInfo1, 0); \
5321	} while (0)
5322
5323	/** Check and handles SVM nested-guest instruction intercept and updates
5324	* NRIP if needed.
5325	*/
5326	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
5327	do \
5328	{ \
5329	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept)) \
5330	{ \
5331	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
5332	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2); \
5333	} \
5334	} while (0)
5335
5336	/** Checks and handles SVM nested-guest CR0 read intercept. */
5337	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
5338	do \
5339	{ \
5340	if (!IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, 0)) \
5341	{ /* probably likely */ } \
5342	else \
5343	{ \
5344	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
5345	IEM_SVM_VMEXIT_RET(a_pVCpu, SVM_EXIT_READ_CR0, a_uExitInfo1, a_uExitInfo2); \
5346	} \
5347	} while (0)
5348
5349	/**
5350	* Updates the NextRIP (NRI) field in the nested-guest VMCB.
5351	*/
5352	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) \
5353	do { \
5354	if (IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmNextRipSave) \
5355	CPUMGuestSvmUpdateNRip(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_cbInstr)); \
5356	} while (0)
5357
5358	#else
5359	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) (false)
5360	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
5361	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
5362	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
5363	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
5364	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) (false)
5365	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { return VERR_SVM_IPE_1; } while (0)
5366	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) do { return VERR_SVM_IPE_1; } while (0)
5367	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, \
5368	a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
5369	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
5370	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) do { } while (0)
5371
5372	#endif
5373
5374	/** @} */
5375
5376	uint32_t iemCalcExecDbgFlagsSlow(PVMCPUCC pVCpu);
5377	VBOXSTRICTRC iemExecInjectPendingTrap(PVMCPUCC pVCpu);
5378
5379
5380	/**
5381	* Selector descriptor table entry as fetched by iemMemFetchSelDesc.
5382	*/
5383	typedef union IEMSELDESC
5384	{
5385	/** The legacy view. */
5386	X86DESC Legacy;
5387	/** The long mode view. */
5388	X86DESC64 Long;
5389	} IEMSELDESC;
5390	/** Pointer to a selector descriptor table entry. */
5391	typedef IEMSELDESC *PIEMSELDESC;
5392
5393	/** @name Raising Exceptions.
5394	* @{ */
5395	VBOXSTRICTRC iemTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, uint32_t uNextEip, uint32_t fFlags,
5396	uint16_t uErr, uint64_t uCr2, RTSEL SelTSS, PIEMSELDESC pNewDescTSS) RT_NOEXCEPT;
5397
5398	VBOXSTRICTRC iemRaiseXcptOrInt(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags,
5399	uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
5400	#ifdef IEM_WITH_SETJMP
5401	DECL_NO_RETURN(void) iemRaiseXcptOrIntJmp(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector,
5402	uint32_t fFlags, uint16_t uErr, uint64_t uCr2) IEM_NOEXCEPT_MAY_LONGJMP;
5403	#endif
5404	VBOXSTRICTRC iemRaiseDivideError(PVMCPUCC pVCpu) RT_NOEXCEPT;
5405	#ifdef IEM_WITH_SETJMP
5406	DECL_NO_RETURN(void) iemRaiseDivideErrorJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5407	#endif
5408	VBOXSTRICTRC iemRaiseDebugException(PVMCPUCC pVCpu) RT_NOEXCEPT;
5409	VBOXSTRICTRC iemRaiseBoundRangeExceeded(PVMCPUCC pVCpu) RT_NOEXCEPT;
5410	VBOXSTRICTRC iemRaiseUndefinedOpcode(PVMCPUCC pVCpu) RT_NOEXCEPT;
5411	#ifdef IEM_WITH_SETJMP
5412	DECL_NO_RETURN(void) iemRaiseUndefinedOpcodeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5413	#endif
5414	VBOXSTRICTRC iemRaiseDeviceNotAvailable(PVMCPUCC pVCpu) RT_NOEXCEPT;
5415	#ifdef IEM_WITH_SETJMP
5416	DECL_NO_RETURN(void) iemRaiseDeviceNotAvailableJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5417	#endif
5418	VBOXSTRICTRC iemRaiseTaskSwitchFaultWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5419	VBOXSTRICTRC iemRaiseTaskSwitchFaultCurrentTSS(PVMCPUCC pVCpu) RT_NOEXCEPT;
5420	VBOXSTRICTRC iemRaiseTaskSwitchFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
5421	VBOXSTRICTRC iemRaiseTaskSwitchFaultBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5422	/VBOXSTRICTRC iemRaiseSelectorNotPresent(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;/
5423	VBOXSTRICTRC iemRaiseSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5424	VBOXSTRICTRC iemRaiseSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5425	VBOXSTRICTRC iemRaiseStackSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5426	VBOXSTRICTRC iemRaiseStackSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5427	VBOXSTRICTRC iemRaiseGeneralProtectionFault(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5428	VBOXSTRICTRC iemRaiseGeneralProtectionFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
5429	#ifdef IEM_WITH_SETJMP
5430	DECL_NO_RETURN(void) iemRaiseGeneralProtectionFault0Jmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5431	#endif
5432	VBOXSTRICTRC iemRaiseGeneralProtectionFaultBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
5433	VBOXSTRICTRC iemRaiseNotCanonical(PVMCPUCC pVCpu) RT_NOEXCEPT;
5434	VBOXSTRICTRC iemRaiseSelectorBounds(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
5435	#ifdef IEM_WITH_SETJMP
5436	DECL_NO_RETURN(void) iemRaiseSelectorBoundsJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
5437	#endif
5438	VBOXSTRICTRC iemRaiseSelectorBoundsBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
5439	#ifdef IEM_WITH_SETJMP
5440	DECL_NO_RETURN(void) iemRaiseSelectorBoundsBySelectorJmp(PVMCPUCC pVCpu, RTSEL Sel) IEM_NOEXCEPT_MAY_LONGJMP;
5441	#endif
5442	VBOXSTRICTRC iemRaiseSelectorInvalidAccess(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
5443	#ifdef IEM_WITH_SETJMP
5444	DECL_NO_RETURN(void) iemRaiseSelectorInvalidAccessJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
5445	#endif
5446	VBOXSTRICTRC iemRaisePageFault(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) RT_NOEXCEPT;
5447	#ifdef IEM_WITH_SETJMP
5448	DECL_NO_RETURN(void) iemRaisePageFaultJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) IEM_NOEXCEPT_MAY_LONGJMP;
5449	#endif
5450	VBOXSTRICTRC iemRaiseMathFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
5451	#ifdef IEM_WITH_SETJMP
5452	DECL_NO_RETURN(void) iemRaiseMathFaultJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5453	#endif
5454	VBOXSTRICTRC iemRaiseAlignmentCheckException(PVMCPUCC pVCpu) RT_NOEXCEPT;
5455	#ifdef IEM_WITH_SETJMP
5456	DECL_NO_RETURN(void) iemRaiseAlignmentCheckExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5457	#endif
5458	VBOXSTRICTRC iemRaiseSimdFpException(PVMCPUCC pVCpu) RT_NOEXCEPT;
5459	#ifdef IEM_WITH_SETJMP
5460	DECL_NO_RETURN(void) iemRaiseSimdFpExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5461	#endif
5462
5463	void iemLogSyscallRealModeInt(PVMCPUCC pVCpu, uint8_t u8Vector, uint8_t cbInstr);
5464	void iemLogSyscallProtModeInt(PVMCPUCC pVCpu, uint8_t u8Vector, uint8_t cbInstr);
5465
5466	IEM_CIMPL_DEF_0(iemCImplRaiseDivideError);
5467	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidLockPrefix);
5468	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidOpcode);
5469
5470	/**
5471	* Macro for calling iemCImplRaiseDivideError().
5472	*
5473	* This is for things that will _always_ decode to an \#DE, taking the
5474	* recompiler into consideration and everything.
5475	*
5476	* @return Strict VBox status code.
5477	*/
5478	#define IEMOP_RAISE_DIVIDE_ERROR_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseDivideError)
5479
5480	/**
5481	* Macro for calling iemCImplRaiseInvalidLockPrefix().
5482	*
5483	* This is for things that will _always_ decode to an \#UD, taking the
5484	* recompiler into consideration and everything.
5485	*
5486	* @return Strict VBox status code.
5487	*/
5488	#define IEMOP_RAISE_INVALID_LOCK_PREFIX_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidLockPrefix)
5489
5490	/**
5491	* Macro for calling iemCImplRaiseInvalidOpcode() for decode/static \#UDs.
5492	*
5493	* This is for things that will _always_ decode to an \#UD, taking the
5494	* recompiler into consideration and everything.
5495	*
5496	* @return Strict VBox status code.
5497	*/
5498	#define IEMOP_RAISE_INVALID_OPCODE_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidOpcode)
5499
5500	/**
5501	* Macro for calling iemCImplRaiseInvalidOpcode() for runtime-style \#UDs.
5502	*
5503	* Using this macro means you've got _buggy_ _code_ and are doing things that
5504	* belongs exclusively in IEMAllCImpl.cpp during decoding.
5505	*
5506	* @return Strict VBox status code.
5507	* @see IEMOP_RAISE_INVALID_OPCODE_RET
5508	*/
5509	#define IEMOP_RAISE_INVALID_OPCODE_RUNTIME_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidOpcode)
5510
5511	/** @} */
5512
5513	/** @name Register Access.
5514	* @{ */
5515	VBOXSTRICTRC iemRegRipRelativeJumpS8AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int8_t offNextInstr,
5516	IEMMODE enmEffOpSize) RT_NOEXCEPT;
5517	VBOXSTRICTRC iemRegRipRelativeJumpS16AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int16_t offNextInstr) RT_NOEXCEPT;
5518	VBOXSTRICTRC iemRegRipRelativeJumpS32AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int32_t offNextInstr,
5519	IEMMODE enmEffOpSize) RT_NOEXCEPT;
5520	/** @} */
5521
5522	/** @name FPU access and helpers.
5523	* @{ */
5524	void iemFpuPushResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
5525	void iemFpuPushResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5526	void iemFpuPushResultTwo(PVMCPUCC pVCpu, PIEMFPURESULTTWO pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
5527	void iemFpuStoreResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
5528	void iemFpuStoreResultThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
5529	void iemFpuStoreResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
5530	uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5531	void iemFpuStoreResultWithMemOpThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
5532	uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5533	void iemFpuUpdateOpcodeAndIp(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5534	void iemFpuUpdateFSW(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
5535	void iemFpuUpdateFSWThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
5536	void iemFpuUpdateFSWWithMemOp(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5537	void iemFpuUpdateFSWThenPopPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
5538	void iemFpuUpdateFSWWithMemOpThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5539	void iemFpuStackUnderflow(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
5540	void iemFpuStackUnderflowWithMemOp(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5541	void iemFpuStackUnderflowThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
5542	void iemFpuStackUnderflowWithMemOpThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5543	void iemFpuStackUnderflowThenPopPop(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5544	void iemFpuStackPushUnderflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5545	void iemFpuStackPushUnderflowTwo(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5546	void iemFpuStackPushOverflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5547	void iemFpuStackPushOverflowWithMemOp(PVMCPUCC pVCpu, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5548	/** @} */
5549
5550	/** @name SSE+AVX SIMD access and helpers.
5551	* @{ */
5552	void iemSseUpdateMxcsr(PVMCPUCC pVCpu, uint32_t fMxcsr) RT_NOEXCEPT;
5553	/** @} */
5554
5555	/** @name Memory access.
5556	* @{ */
5557
5558	/** Report a \#GP instead of \#AC and do not restrict to ring-3 */
5559	#define IEM_MEMMAP_F_ALIGN_GP RT_BIT_32(16)
5560	/** SSE access that should report a \#GP instead of \#AC, unless MXCSR.MM=1
5561	* when it works like normal \#AC. Always used with IEM_MEMMAP_F_ALIGN_GP. */
5562	#define IEM_MEMMAP_F_ALIGN_SSE RT_BIT_32(17)
5563	/** If \#AC is applicable, raise it. Always used with IEM_MEMMAP_F_ALIGN_GP.
5564	* Users include FXSAVE & FXRSTOR. */
5565	#define IEM_MEMMAP_F_ALIGN_GP_OR_AC RT_BIT_32(18)
5566
5567	VBOXSTRICTRC iemMemMap(PVMCPUCC pVCpu, void *ppvMem, uint8_t pbUnmapInfo, size_t cbMem, uint8_t iSegReg, RTGCPTR GCPtrMem,
5568	uint32_t fAccess, uint32_t uAlignCtl) RT_NOEXCEPT;
5569	VBOXSTRICTRC iemMemCommitAndUnmap(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5570	#ifndef IN_RING3
5571	VBOXSTRICTRC iemMemCommitAndUnmapPostponeTroubleToR3(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5572	#endif
5573	void iemMemRollbackAndUnmap(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5574	void iemMemRollback(PVMCPUCC pVCpu) RT_NOEXCEPT;
5575	VBOXSTRICTRC iemMemApplySegment(PVMCPUCC pVCpu, uint32_t fAccess, uint8_t iSegReg, size_t cbMem, PRTGCPTR pGCPtrMem) RT_NOEXCEPT;
5576	VBOXSTRICTRC iemMemMarkSelDescAccessed(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5577	VBOXSTRICTRC iemMemPageTranslateAndCheckAccess(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t cbAccess, uint32_t fAccess, PRTGCPHYS pGCPhysMem) RT_NOEXCEPT;
5578
5579	void iemOpcodeFlushLight(PVMCPUCC pVCpu, uint8_t cbInstr);
5580	void iemOpcodeFlushHeavy(PVMCPUCC pVCpu, uint8_t cbInstr);
5581	#ifdef IEM_WITH_CODE_TLB
5582	void iemOpcodeFetchBytesJmp(PVMCPUCC pVCpu, size_t cbDst, void *pvDst) IEM_NOEXCEPT_MAY_LONGJMP;
5583	#else
5584	VBOXSTRICTRC iemOpcodeFetchMoreBytes(PVMCPUCC pVCpu, size_t cbMin) RT_NOEXCEPT;
5585	#endif
5586	#ifdef IEM_WITH_SETJMP
5587	uint8_t iemOpcodeGetNextU8SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5588	uint16_t iemOpcodeGetNextU16SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5589	uint32_t iemOpcodeGetNextU32SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5590	uint64_t iemOpcodeGetNextU64SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5591	#else
5592	VBOXSTRICTRC iemOpcodeGetNextU8Slow(PVMCPUCC pVCpu, uint8_t *pb) RT_NOEXCEPT;
5593	VBOXSTRICTRC iemOpcodeGetNextS8SxU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
5594	VBOXSTRICTRC iemOpcodeGetNextS8SxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
5595	VBOXSTRICTRC iemOpcodeGetNextS8SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5596	VBOXSTRICTRC iemOpcodeGetNextU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
5597	VBOXSTRICTRC iemOpcodeGetNextU16ZxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
5598	VBOXSTRICTRC iemOpcodeGetNextU16ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5599	VBOXSTRICTRC iemOpcodeGetNextU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
5600	VBOXSTRICTRC iemOpcodeGetNextU32ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5601	VBOXSTRICTRC iemOpcodeGetNextS32SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5602	VBOXSTRICTRC iemOpcodeGetNextU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5603	#endif
5604
5605	VBOXSTRICTRC iemMemFetchDataU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5606	VBOXSTRICTRC iemMemFetchDataU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5607	VBOXSTRICTRC iemMemFetchDataU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5608	VBOXSTRICTRC iemMemFetchDataU32_ZX_U64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5609	VBOXSTRICTRC iemMemFetchDataU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5610	VBOXSTRICTRC iemMemFetchDataU64AlignedU128(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5611	VBOXSTRICTRC iemMemFetchDataR80(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5612	VBOXSTRICTRC iemMemFetchDataD80(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5613	VBOXSTRICTRC iemMemFetchDataU128(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5614	VBOXSTRICTRC iemMemFetchDataU128NoAc(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5615	VBOXSTRICTRC iemMemFetchDataU128AlignedSse(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5616	VBOXSTRICTRC iemMemFetchDataU256(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5617	VBOXSTRICTRC iemMemFetchDataU256NoAc(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5618	VBOXSTRICTRC iemMemFetchDataU256AlignedAvx(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5619	VBOXSTRICTRC iemMemFetchDataXdtr(PVMCPUCC pVCpu, uint16_t *pcbLimit, PRTGCPTR pGCPtrBase, uint8_t iSegReg,
5620	RTGCPTR GCPtrMem, IEMMODE enmOpSize) RT_NOEXCEPT;
5621	#ifdef IEM_WITH_SETJMP
5622	uint8_t iemMemFetchDataU8SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5623	uint16_t iemMemFetchDataU16SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5624	uint32_t iemMemFetchDataU32SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5625	uint32_t iemMemFlatFetchDataU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5626	uint64_t iemMemFetchDataU64SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5627	uint64_t iemMemFetchDataU64AlignedU128SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5628	void iemMemFetchDataR80SafeJmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5629	void iemMemFetchDataD80SafeJmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5630	void iemMemFetchDataU128SafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5631	void iemMemFetchDataU128NoAcSafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5632	void iemMemFetchDataU128AlignedSseSafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5633	void iemMemFetchDataU256SafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5634	void iemMemFetchDataU256NoAcSafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5635	void iemMemFetchDataU256AlignedAvxSafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5636	# if 0 /* these are inlined now */
5637	uint8_t iemMemFetchDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5638	uint16_t iemMemFetchDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5639	uint32_t iemMemFetchDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5640	uint32_t iemMemFlatFetchDataU32Jmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5641	uint64_t iemMemFetchDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5642	uint64_t iemMemFetchDataU64AlignedU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5643	void iemMemFetchDataR80Jmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5644	void iemMemFetchDataD80Jmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5645	void iemMemFetchDataU128Jmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5646	void iemMemFetchDataU128NoAcJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5647	void iemMemFetchDataU128AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5648	void iemMemFetchDataU256NoAcJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5649	void iemMemFetchDataU256AlignedAvxJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5650	# endif
5651	void iemMemFetchDataU256Jmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5652	#endif
5653
5654	VBOXSTRICTRC iemMemFetchSysU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5655	VBOXSTRICTRC iemMemFetchSysU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5656	VBOXSTRICTRC iemMemFetchSysU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5657	VBOXSTRICTRC iemMemFetchSysU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5658	VBOXSTRICTRC iemMemFetchSelDesc(PVMCPUCC pVCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt) RT_NOEXCEPT;
5659
5660	VBOXSTRICTRC iemMemStoreDataU8(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) RT_NOEXCEPT;
5661	VBOXSTRICTRC iemMemStoreDataU16(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) RT_NOEXCEPT;
5662	VBOXSTRICTRC iemMemStoreDataU32(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) RT_NOEXCEPT;
5663	VBOXSTRICTRC iemMemStoreDataU64(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) RT_NOEXCEPT;
5664	VBOXSTRICTRC iemMemStoreDataU128(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
5665	VBOXSTRICTRC iemMemStoreDataU128NoAc(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
5666	VBOXSTRICTRC iemMemStoreDataU128AlignedSse(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
5667	VBOXSTRICTRC iemMemStoreDataU256(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
5668	VBOXSTRICTRC iemMemStoreDataU256NoAc(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
5669	VBOXSTRICTRC iemMemStoreDataU256AlignedAvx(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
5670	VBOXSTRICTRC iemMemStoreDataXdtr(PVMCPUCC pVCpu, uint16_t cbLimit, RTGCPTR GCPtrBase, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5671	#ifdef IEM_WITH_SETJMP
5672	void iemMemStoreDataU8SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
5673	void iemMemStoreDataU16SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
5674	void iemMemStoreDataU32SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
5675	void iemMemStoreDataU64SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
5676	void iemMemStoreDataU128SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5677	void iemMemStoreDataU128NoAcSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT128U pu128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5678	void iemMemStoreDataU128AlignedSseSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT128U pu128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5679	void iemMemStoreDataU256SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5680	void iemMemStoreDataU256NoAcSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5681	void iemMemStoreDataU256AlignedAvxSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5682	void iemMemStoreDataR80SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTFLOAT80U pr80Value) IEM_NOEXCEPT_MAY_LONGJMP;
5683	void iemMemStoreDataD80SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTPBCD80U pd80Value) IEM_NOEXCEPT_MAY_LONGJMP;
5684	#if 0
5685	void iemMemStoreDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
5686	void iemMemStoreDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
5687	void iemMemStoreDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
5688	void iemMemStoreDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
5689	void iemMemStoreDataU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5690	void iemMemStoreDataNoAcU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5691	void iemMemStoreDataU256NoAcJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5692	void iemMemStoreDataU256AlignedAvxJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5693	#endif
5694	void iemMemStoreDataU128AlignedSseJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5695	void iemMemStoreDataU256Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5696	#endif
5697
5698	#ifdef IEM_WITH_SETJMP
5699	uint8_t iemMemMapDataU8RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5700	uint8_t iemMemMapDataU8AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5701	uint8_t iemMemMapDataU8WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5702	uint8_t const iemMemMapDataU8RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5703	uint16_t iemMemMapDataU16RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5704	uint16_t iemMemMapDataU16AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5705	uint16_t iemMemMapDataU16WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5706	uint16_t const iemMemMapDataU16RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5707	uint32_t iemMemMapDataU32RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5708	uint32_t iemMemMapDataU32AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5709	uint32_t iemMemMapDataU32WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5710	uint32_t const iemMemMapDataU32RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5711	uint64_t iemMemMapDataU64RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5712	uint64_t iemMemMapDataU64AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5713	uint64_t iemMemMapDataU64WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5714	uint64_t const iemMemMapDataU64RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5715	PRTFLOAT80U iemMemMapDataR80RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5716	PRTFLOAT80U iemMemMapDataR80WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5717	PCRTFLOAT80U iemMemMapDataR80RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5718	PRTPBCD80U iemMemMapDataD80RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5719	PRTPBCD80U iemMemMapDataD80WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5720	PCRTPBCD80U iemMemMapDataD80RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5721	PRTUINT128U iemMemMapDataU128RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5722	PRTUINT128U iemMemMapDataU128AtSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5723	PRTUINT128U iemMemMapDataU128WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5724	PCRTUINT128U iemMemMapDataU128RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5725
5726	void iemMemCommitAndUnmapJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5727	void iemMemCommitAndUnmapRwSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5728	void iemMemCommitAndUnmapAtSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5729	void iemMemCommitAndUnmapWoSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5730	void iemMemCommitAndUnmapRoSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5731	void iemMemRollbackAndUnmapWoSafe(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5732	#endif
5733
5734	VBOXSTRICTRC iemMemStackPushBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
5735	void *ppvMem, uint8_t pbUnmapInfo, uint64_t *puNewRsp) RT_NOEXCEPT;
5736	VBOXSTRICTRC iemMemStackPushCommitSpecial(PVMCPUCC pVCpu, uint8_t bUnmapInfo, uint64_t uNewRsp) RT_NOEXCEPT;
5737	VBOXSTRICTRC iemMemStackPushU16(PVMCPUCC pVCpu, uint16_t u16Value) RT_NOEXCEPT;
5738	VBOXSTRICTRC iemMemStackPushU32(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
5739	VBOXSTRICTRC iemMemStackPushU64(PVMCPUCC pVCpu, uint64_t u64Value) RT_NOEXCEPT;
5740	VBOXSTRICTRC iemMemStackPushU16Ex(PVMCPUCC pVCpu, uint16_t u16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5741	VBOXSTRICTRC iemMemStackPushU32Ex(PVMCPUCC pVCpu, uint32_t u32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5742	VBOXSTRICTRC iemMemStackPushU64Ex(PVMCPUCC pVCpu, uint64_t u64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5743	VBOXSTRICTRC iemMemStackPushU32SReg(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
5744	VBOXSTRICTRC iemMemStackPopBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
5745	void const *ppvMem, uint8_t pbUnmapInfo, uint64_t *puNewRsp) RT_NOEXCEPT;
5746	VBOXSTRICTRC iemMemStackPopContinueSpecial(PVMCPUCC pVCpu, size_t off, size_t cbMem,
5747	void const *ppvMem, uint8_t pbUnmapInfo, uint64_t uCurNewRsp) RT_NOEXCEPT;
5748	VBOXSTRICTRC iemMemStackPopDoneSpecial(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5749	VBOXSTRICTRC iemMemStackPopU16(PVMCPUCC pVCpu, uint16_t *pu16Value) RT_NOEXCEPT;
5750	VBOXSTRICTRC iemMemStackPopU32(PVMCPUCC pVCpu, uint32_t *pu32Value) RT_NOEXCEPT;
5751	VBOXSTRICTRC iemMemStackPopU64(PVMCPUCC pVCpu, uint64_t *pu64Value) RT_NOEXCEPT;
5752	VBOXSTRICTRC iemMemStackPopU16Ex(PVMCPUCC pVCpu, uint16_t *pu16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5753	VBOXSTRICTRC iemMemStackPopU32Ex(PVMCPUCC pVCpu, uint32_t *pu32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5754	VBOXSTRICTRC iemMemStackPopU64Ex(PVMCPUCC pVCpu, uint64_t *pu64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5755
5756	#ifdef IEM_WITH_SETJMP
5757	void iemMemStackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5758	void iemMemStackPushU32SafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5759	void iemMemStackPushU32SRegSafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5760	void iemMemStackPushU64SafeJmp(PVMCPUCC pVCpu, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5761	void iemMemStackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5762	void iemMemStackPopGRegU32SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5763	void iemMemStackPopGRegU64SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5764
5765	void iemMemFlat32StackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5766	void iemMemFlat32StackPushU32SafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5767	void iemMemFlat32StackPushU32SRegSafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5768	void iemMemFlat32StackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5769	void iemMemFlat32StackPopGRegU32SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5770
5771	void iemMemFlat64StackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5772	void iemMemFlat64StackPushU64SafeJmp(PVMCPUCC pVCpu, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5773	void iemMemFlat64StackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5774	void iemMemFlat64StackPopGRegU64SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5775
5776	void iemMemStoreStackU16SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5777	void iemMemStoreStackU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5778	void iemMemStoreStackU32SRegSafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5779	void iemMemStoreStackU64SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5780
5781	uint16_t iemMemFetchStackU16SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5782	uint32_t iemMemFetchStackU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5783	uint64_t iemMemFetchStackU64SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5784
5785	#endif
5786
5787	/** @} */
5788
5789	/** @name IEMAllCImpl.cpp
5790	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/'
5791	* @{ */
5792	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem16, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5793	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem32, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5794	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem64, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5795	IEM_CIMPL_PROTO_0(iemCImpl_popa_16);
5796	IEM_CIMPL_PROTO_0(iemCImpl_popa_32);
5797	IEM_CIMPL_PROTO_0(iemCImpl_pusha_16);
5798	IEM_CIMPL_PROTO_0(iemCImpl_pusha_32);
5799	IEM_CIMPL_PROTO_1(iemCImpl_pushf, IEMMODE, enmEffOpSize);
5800	IEM_CIMPL_PROTO_1(iemCImpl_popf, IEMMODE, enmEffOpSize);
5801	IEM_CIMPL_PROTO_1(iemCImpl_call_16, uint16_t, uNewPC);
5802	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_16, int16_t, offDisp);
5803	IEM_CIMPL_PROTO_1(iemCImpl_call_32, uint32_t, uNewPC);
5804	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_32, int32_t, offDisp);
5805	IEM_CIMPL_PROTO_1(iemCImpl_call_64, uint64_t, uNewPC);
5806	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_64, int64_t, offDisp);
5807	IEM_CIMPL_PROTO_3(iemCImpl_FarJmp, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
5808	IEM_CIMPL_PROTO_3(iemCImpl_callf, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
5809	typedef IEM_CIMPL_DECL_TYPE_3(FNIEMCIMPLFARBRANCH, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
5810	typedef FNIEMCIMPLFARBRANCH *PFNIEMCIMPLFARBRANCH;
5811	IEM_CIMPL_PROTO_2(iemCImpl_retf, IEMMODE, enmEffOpSize, uint16_t, cbPop);
5812	IEM_CIMPL_PROTO_0(iemCImpl_retn_16);
5813	IEM_CIMPL_PROTO_0(iemCImpl_retn_32);
5814	IEM_CIMPL_PROTO_0(iemCImpl_retn_64);
5815	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_16, uint16_t, cbPop);
5816	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_32, uint16_t, cbPop);
5817	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_64, uint16_t, cbPop);
5818	IEM_CIMPL_PROTO_3(iemCImpl_enter, IEMMODE, enmEffOpSize, uint16_t, cbFrame, uint8_t, cParameters);
5819	IEM_CIMPL_PROTO_1(iemCImpl_leave, IEMMODE, enmEffOpSize);
5820	IEM_CIMPL_PROTO_2(iemCImpl_int, uint8_t, u8Int, IEMINT, enmInt);
5821	IEM_CIMPL_PROTO_1(iemCImpl_iret_real_v8086, IEMMODE, enmEffOpSize);
5822	IEM_CIMPL_PROTO_4(iemCImpl_iret_prot_v8086, uint32_t, uNewEip, uint16_t, uNewCs, uint32_t, uNewFlags, uint64_t, uNewRsp);
5823	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot_NestedTask, IEMMODE, enmEffOpSize);
5824	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot, IEMMODE, enmEffOpSize);
5825	IEM_CIMPL_PROTO_1(iemCImpl_iret_64bit, IEMMODE, enmEffOpSize);
5826	IEM_CIMPL_PROTO_1(iemCImpl_iret, IEMMODE, enmEffOpSize);
5827	IEM_CIMPL_PROTO_0(iemCImpl_loadall286);
5828	IEM_CIMPL_PROTO_0(iemCImpl_syscall);
5829	IEM_CIMPL_PROTO_1(iemCImpl_sysret, IEMMODE, enmEffOpSize);
5830	IEM_CIMPL_PROTO_0(iemCImpl_sysenter);
5831	IEM_CIMPL_PROTO_1(iemCImpl_sysexit, IEMMODE, enmEffOpSize);
5832	IEM_CIMPL_PROTO_2(iemCImpl_LoadSReg, uint8_t, iSegReg, uint16_t, uSel);
5833	IEM_CIMPL_PROTO_2(iemCImpl_load_SReg, uint8_t, iSegReg, uint16_t, uSel);
5834	IEM_CIMPL_PROTO_2(iemCImpl_pop_Sreg, uint8_t, iSegReg, IEMMODE, enmEffOpSize);
5835	IEM_CIMPL_PROTO_5(iemCImpl_load_SReg_Greg, uint16_t, uSel, uint64_t, offSeg, uint8_t, iSegReg, uint8_t, iGReg, IEMMODE, enmEffOpSize);
5836	IEM_CIMPL_PROTO_2(iemCImpl_VerX, uint16_t, uSel, bool, fWrite);
5837	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u64, uint64_t *, pu64Dst, uint16_t, uSel, bool, fIsLar);
5838	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u16, uint16_t *, pu16Dst, uint16_t, uSel, bool, fIsLar);
5839	IEM_CIMPL_PROTO_3(iemCImpl_lgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
5840	IEM_CIMPL_PROTO_2(iemCImpl_sgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5841	IEM_CIMPL_PROTO_3(iemCImpl_lidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
5842	IEM_CIMPL_PROTO_2(iemCImpl_sidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5843	IEM_CIMPL_PROTO_1(iemCImpl_lldt, uint16_t, uNewLdt);
5844	IEM_CIMPL_PROTO_2(iemCImpl_sldt_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
5845	IEM_CIMPL_PROTO_2(iemCImpl_sldt_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5846	IEM_CIMPL_PROTO_1(iemCImpl_ltr, uint16_t, uNewTr);
5847	IEM_CIMPL_PROTO_2(iemCImpl_str_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
5848	IEM_CIMPL_PROTO_2(iemCImpl_str_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5849	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Cd, uint8_t, iGReg, uint8_t, iCrReg);
5850	IEM_CIMPL_PROTO_2(iemCImpl_smsw_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
5851	IEM_CIMPL_PROTO_2(iemCImpl_smsw_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5852	IEM_CIMPL_PROTO_4(iemCImpl_load_CrX, uint8_t, iCrReg, uint64_t, uNewCrX, IEMACCESSCRX, enmAccessCrX, uint8_t, iGReg);
5853	IEM_CIMPL_PROTO_2(iemCImpl_mov_Cd_Rd, uint8_t, iCrReg, uint8_t, iGReg);
5854	IEM_CIMPL_PROTO_2(iemCImpl_lmsw, uint16_t, u16NewMsw, RTGCPTR, GCPtrEffDst);
5855	IEM_CIMPL_PROTO_0(iemCImpl_clts);
5856	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Dd, uint8_t, iGReg, uint8_t, iDrReg);
5857	IEM_CIMPL_PROTO_2(iemCImpl_mov_Dd_Rd, uint8_t, iDrReg, uint8_t, iGReg);
5858	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Td, uint8_t, iGReg, uint8_t, iTrReg);
5859	IEM_CIMPL_PROTO_2(iemCImpl_mov_Td_Rd, uint8_t, iTrReg, uint8_t, iGReg);
5860	IEM_CIMPL_PROTO_1(iemCImpl_invlpg, RTGCPTR, GCPtrPage);
5861	IEM_CIMPL_PROTO_3(iemCImpl_invpcid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvpcidDesc, uint64_t, uInvpcidType);
5862	IEM_CIMPL_PROTO_0(iemCImpl_invd);
5863	IEM_CIMPL_PROTO_0(iemCImpl_wbinvd);
5864	IEM_CIMPL_PROTO_0(iemCImpl_rsm);
5865	IEM_CIMPL_PROTO_0(iemCImpl_rdtsc);
5866	IEM_CIMPL_PROTO_0(iemCImpl_rdtscp);
5867	IEM_CIMPL_PROTO_0(iemCImpl_rdpmc);
5868	IEM_CIMPL_PROTO_0(iemCImpl_rdmsr);
5869	IEM_CIMPL_PROTO_0(iemCImpl_wrmsr);
5870	IEM_CIMPL_PROTO_3(iemCImpl_in, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
5871	IEM_CIMPL_PROTO_2(iemCImpl_in_eAX_DX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
5872	IEM_CIMPL_PROTO_3(iemCImpl_out, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
5873	IEM_CIMPL_PROTO_2(iemCImpl_out_DX_eAX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
5874	IEM_CIMPL_PROTO_0(iemCImpl_cli);
5875	IEM_CIMPL_PROTO_0(iemCImpl_sti);
5876	IEM_CIMPL_PROTO_0(iemCImpl_hlt);
5877	IEM_CIMPL_PROTO_1(iemCImpl_monitor, uint8_t, iEffSeg);
5878	IEM_CIMPL_PROTO_0(iemCImpl_mwait);
5879	IEM_CIMPL_PROTO_0(iemCImpl_swapgs);
5880	IEM_CIMPL_PROTO_0(iemCImpl_cpuid);
5881	IEM_CIMPL_PROTO_1(iemCImpl_aad, uint8_t, bImm);
5882	IEM_CIMPL_PROTO_1(iemCImpl_aam, uint8_t, bImm);
5883	IEM_CIMPL_PROTO_0(iemCImpl_daa);
5884	IEM_CIMPL_PROTO_0(iemCImpl_das);
5885	IEM_CIMPL_PROTO_0(iemCImpl_aaa);
5886	IEM_CIMPL_PROTO_0(iemCImpl_aas);
5887	IEM_CIMPL_PROTO_3(iemCImpl_bound_16, int16_t, idxArray, int16_t, idxLowerBound, int16_t, idxUpperBound);
5888	IEM_CIMPL_PROTO_3(iemCImpl_bound_32, int32_t, idxArray, int32_t, idxLowerBound, int32_t, idxUpperBound);
5889	IEM_CIMPL_PROTO_0(iemCImpl_xgetbv);
5890	IEM_CIMPL_PROTO_0(iemCImpl_xsetbv);
5891	IEM_CIMPL_PROTO_5(iemCImpl_cmpxchg16b_fallback_rendezvous, PRTUINT128U, pu128Dst, PRTUINT128U, pu128RaxRdx,
5892	PRTUINT128U, pu128RbxRcx, uint32_t *, pEFlags, uint8_t, bUnmapInfo);
5893	IEM_CIMPL_PROTO_2(iemCImpl_clflush_clflushopt, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5894	IEM_CIMPL_PROTO_1(iemCImpl_finit, bool, fCheckXcpts);
5895	IEM_CIMPL_PROTO_3(iemCImpl_fxsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5896	IEM_CIMPL_PROTO_3(iemCImpl_fxrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5897	IEM_CIMPL_PROTO_3(iemCImpl_xsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5898	IEM_CIMPL_PROTO_3(iemCImpl_xrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5899	IEM_CIMPL_PROTO_2(iemCImpl_stmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5900	IEM_CIMPL_PROTO_2(iemCImpl_vstmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5901	IEM_CIMPL_PROTO_2(iemCImpl_ldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5902	IEM_CIMPL_PROTO_3(iemCImpl_fnstenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5903	IEM_CIMPL_PROTO_3(iemCImpl_fnsave, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5904	IEM_CIMPL_PROTO_3(iemCImpl_fldenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
5905	IEM_CIMPL_PROTO_3(iemCImpl_frstor, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
5906	IEM_CIMPL_PROTO_1(iemCImpl_fldcw, uint16_t, u16Fcw);
5907	IEM_CIMPL_PROTO_2(iemCImpl_fxch_underflow, uint8_t, iStReg, uint16_t, uFpuOpcode);
5908	IEM_CIMPL_PROTO_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, bool, fUCmp, uint32_t, uPopAndFpuOpcode);
5909	IEM_CIMPL_PROTO_2(iemCImpl_rdseed, uint8_t, iReg, IEMMODE, enmEffOpSize);
5910	IEM_CIMPL_PROTO_2(iemCImpl_rdrand, uint8_t, iReg, IEMMODE, enmEffOpSize);
5911	/** @} */
5912
5913	/** @name IEMAllCImplStrInstr.cpp.h
5914	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/' -e 's/RT_CONCAT4(//' \
5915	* -e 's/,ADDR_SIZE)/64/g' -e 's/,OP_SIZE,/64/g' -e 's/,OP_rAX,/rax/g' IEMAllCImplStrInstr.cpp.h
5916	* @{ */
5917	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr16, uint8_t, iEffSeg);
5918	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr16, uint8_t, iEffSeg);
5919	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m16);
5920	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m16);
5921	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr16, uint8_t, iEffSeg);
5922	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m16);
5923	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m16, int8_t, iEffSeg);
5924	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr16, bool, fIoChecked);
5925	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr16, bool, fIoChecked);
5926	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5927	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5928
5929	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr16, uint8_t, iEffSeg);
5930	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr16, uint8_t, iEffSeg);
5931	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m16);
5932	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m16);
5933	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr16, uint8_t, iEffSeg);
5934	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m16);
5935	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m16, int8_t, iEffSeg);
5936	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr16, bool, fIoChecked);
5937	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr16, bool, fIoChecked);
5938	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5939	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5940
5941	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr16, uint8_t, iEffSeg);
5942	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr16, uint8_t, iEffSeg);
5943	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m16);
5944	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m16);
5945	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr16, uint8_t, iEffSeg);
5946	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m16);
5947	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m16, int8_t, iEffSeg);
5948	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr16, bool, fIoChecked);
5949	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr16, bool, fIoChecked);
5950	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5951	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5952
5953
5954	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr32, uint8_t, iEffSeg);
5955	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr32, uint8_t, iEffSeg);
5956	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m32);
5957	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m32);
5958	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr32, uint8_t, iEffSeg);
5959	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m32);
5960	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m32, int8_t, iEffSeg);
5961	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr32, bool, fIoChecked);
5962	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr32, bool, fIoChecked);
5963	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5964	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5965
5966	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr32, uint8_t, iEffSeg);
5967	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr32, uint8_t, iEffSeg);
5968	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m32);
5969	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m32);
5970	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr32, uint8_t, iEffSeg);
5971	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m32);
5972	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m32, int8_t, iEffSeg);
5973	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr32, bool, fIoChecked);
5974	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr32, bool, fIoChecked);
5975	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5976	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5977
5978	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr32, uint8_t, iEffSeg);
5979	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr32, uint8_t, iEffSeg);
5980	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m32);
5981	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m32);
5982	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr32, uint8_t, iEffSeg);
5983	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m32);
5984	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m32, int8_t, iEffSeg);
5985	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr32, bool, fIoChecked);
5986	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr32, bool, fIoChecked);
5987	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5988	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5989
5990	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr32, uint8_t, iEffSeg);
5991	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr32, uint8_t, iEffSeg);
5992	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m32);
5993	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m32);
5994	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr32, uint8_t, iEffSeg);
5995	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m32);
5996	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m32, int8_t, iEffSeg);
5997	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr32, bool, fIoChecked);
5998	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr32, bool, fIoChecked);
5999	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6000	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6001
6002
6003	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr64, uint8_t, iEffSeg);
6004	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr64, uint8_t, iEffSeg);
6005	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m64);
6006	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m64);
6007	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr64, uint8_t, iEffSeg);
6008	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m64);
6009	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m64, int8_t, iEffSeg);
6010	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr64, bool, fIoChecked);
6011	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr64, bool, fIoChecked);
6012	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6013	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6014
6015	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr64, uint8_t, iEffSeg);
6016	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr64, uint8_t, iEffSeg);
6017	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m64);
6018	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m64);
6019	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr64, uint8_t, iEffSeg);
6020	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m64);
6021	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m64, int8_t, iEffSeg);
6022	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr64, bool, fIoChecked);
6023	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr64, bool, fIoChecked);
6024	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6025	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6026
6027	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr64, uint8_t, iEffSeg);
6028	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr64, uint8_t, iEffSeg);
6029	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m64);
6030	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m64);
6031	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr64, uint8_t, iEffSeg);
6032	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m64);
6033	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m64, int8_t, iEffSeg);
6034	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr64, bool, fIoChecked);
6035	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr64, bool, fIoChecked);
6036	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6037	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6038
6039	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr64, uint8_t, iEffSeg);
6040	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr64, uint8_t, iEffSeg);
6041	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m64);
6042	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m64);
6043	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr64, uint8_t, iEffSeg);
6044	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m64);
6045	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m64, int8_t, iEffSeg);
6046	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr64, bool, fIoChecked);
6047	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr64, bool, fIoChecked);
6048	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6049	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6050	/** @} */
6051
6052	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
6053	VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT;
6054	VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT;
6055	VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT;
6056	VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT;
6057	VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT;
6058	VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
6059	VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALK pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT;
6060	VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT;
6061	VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT;
6062	VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
6063	bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT;
6064	VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
6065	bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT;
6066	VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6067	VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6068	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6069	VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6070	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6071	VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6072	VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT;
6073	VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
6074	RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT;
6075	VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT;
6076	VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT;
6077	VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT;
6078	uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT;
6079	void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT;
6080	VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
6081	uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT;
6082	bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT;
6083	IEM_CIMPL_PROTO_0(iemCImpl_vmxoff);
6084	IEM_CIMPL_PROTO_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon);
6085	IEM_CIMPL_PROTO_0(iemCImpl_vmlaunch);
6086	IEM_CIMPL_PROTO_0(iemCImpl_vmresume);
6087	IEM_CIMPL_PROTO_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
6088	IEM_CIMPL_PROTO_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
6089	IEM_CIMPL_PROTO_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
6090	IEM_CIMPL_PROTO_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField);
6091	IEM_CIMPL_PROTO_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField);
6092	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField);
6093	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg32, uint64_t *, pu32Dst, uint32_t, u32VmcsField);
6094	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField);
6095	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField);
6096	IEM_CIMPL_PROTO_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType);
6097	IEM_CIMPL_PROTO_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType);
6098	IEM_CIMPL_PROTO_0(iemCImpl_vmx_pause);
6099	#endif
6100
6101	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
6102	VBOXSTRICTRC iemSvmVmexit(PVMCPUCC pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2) RT_NOEXCEPT;
6103	VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr, uint64_t uCr2) RT_NOEXCEPT;
6104	VBOXSTRICTRC iemSvmHandleIOIntercept(PVMCPUCC pVCpu, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
6105	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, uint8_t cbInstr) RT_NOEXCEPT;
6106	VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPUCC pVCpu, uint32_t idMsr, bool fWrite, uint8_t cbInstr) RT_NOEXCEPT;
6107	IEM_CIMPL_PROTO_0(iemCImpl_vmrun);
6108	IEM_CIMPL_PROTO_0(iemCImpl_vmload);
6109	IEM_CIMPL_PROTO_0(iemCImpl_vmsave);
6110	IEM_CIMPL_PROTO_0(iemCImpl_clgi);
6111	IEM_CIMPL_PROTO_0(iemCImpl_stgi);
6112	IEM_CIMPL_PROTO_0(iemCImpl_invlpga);
6113	IEM_CIMPL_PROTO_0(iemCImpl_skinit);
6114	IEM_CIMPL_PROTO_0(iemCImpl_svm_pause);
6115	#endif
6116
6117	IEM_CIMPL_PROTO_0(iemCImpl_vmcall); /* vmx */
6118	IEM_CIMPL_PROTO_0(iemCImpl_vmmcall); /* svm */
6119	IEM_CIMPL_PROTO_1(iemCImpl_Hypercall, uint16_t, uDisOpcode); /* both */
6120
6121	extern const PFNIEMOP g_apfnIemInterpretOnlyOneByteMap[256];
6122	extern const PFNIEMOP g_apfnIemInterpretOnlyTwoByteMap[1024];
6123	extern const PFNIEMOP g_apfnIemInterpretOnlyThreeByte0f3a[1024];
6124	extern const PFNIEMOP g_apfnIemInterpretOnlyThreeByte0f38[1024];
6125	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap1[1024];
6126	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap2[1024];
6127	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap3[1024];
6128
6129	/*
6130	* Recompiler related stuff.
6131	*/
6132	extern const PFNIEMOP g_apfnIemThreadedRecompilerOneByteMap[256];
6133	extern const PFNIEMOP g_apfnIemThreadedRecompilerTwoByteMap[1024];
6134	extern const PFNIEMOP g_apfnIemThreadedRecompilerThreeByte0f3a[1024];
6135	extern const PFNIEMOP g_apfnIemThreadedRecompilerThreeByte0f38[1024];
6136	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap1[1024];
6137	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap2[1024];
6138	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap3[1024];
6139
6140	DECLCALLBACK(int) iemTbInit(PVMCC pVM, uint32_t cInitialTbs, uint32_t cMaxTbs,
6141	uint64_t cbInitialExec, uint64_t cbMaxExec, uint32_t cbChunkExec);
6142	void iemThreadedTbObsolete(PVMCPUCC pVCpu, PIEMTB pTb, bool fSafeToFree);
6143	DECLHIDDEN(void) iemTbAllocatorFree(PVMCPUCC pVCpu, PIEMTB pTb);
6144	void iemTbAllocatorProcessDelayedFrees(PVMCPUCC pVCpu, PIEMTBALLOCATOR pTbAllocator);
6145	void iemTbAllocatorFreeupNativeSpace(PVMCPUCC pVCpu, uint32_t cNeededInstrs);
6146	DECLHIDDEN(const char ) iemTbFlagsToString(uint32_t fFlags, char pszBuf, size_t cbBuf) RT_NOEXCEPT;
6147	DECLHIDDEN(void) iemThreadedDisassembleTb(PCIEMTB pTb, PCDBGFINFOHLP pHlp) RT_NOEXCEPT;
6148
6149
6150	/** @todo FNIEMTHREADEDFUNC and friends may need more work... */
6151	#if defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
6152	typedef VBOXSTRICTRC /__attribute__((__nothrow__))/ FNIEMTHREADEDFUNC(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
6153	typedef FNIEMTHREADEDFUNC *PFNIEMTHREADEDFUNC;
6154	# define IEM_DECL_IEMTHREADEDFUNC_DEF(a_Name) \
6155	VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2)
6156	# define IEM_DECL_IEMTHREADEDFUNC_PROTO(a_Name) \
6157	VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2)
6158
6159	#else
6160	typedef VBOXSTRICTRC (FNIEMTHREADEDFUNC)(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
6161	typedef FNIEMTHREADEDFUNC *PFNIEMTHREADEDFUNC;
6162	# define IEM_DECL_IEMTHREADEDFUNC_DEF(a_Name) \
6163	VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2) IEM_NOEXCEPT_MAY_LONGJMP
6164	# define IEM_DECL_IEMTHREADEDFUNC_PROTO(a_Name) \
6165	VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2) IEM_NOEXCEPT_MAY_LONGJMP
6166	#endif
6167
6168
6169	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_Nop);
6170	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_LogCpuState);
6171
6172	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_DeferToCImpl0);
6173
6174	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckIrq);
6175	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckMode);
6176	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckHwInstrBps);
6177	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLim);
6178
6179	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodes);
6180	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodes);
6181	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesConsiderCsLim);
6182
6183	/* Branching: */
6184	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndPcAndOpcodes);
6185	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckPcAndOpcodes);
6186	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckPcAndOpcodesConsiderCsLim);
6187
6188	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesLoadingTlb);
6189	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesLoadingTlb);
6190	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesLoadingTlbConsiderCsLim);
6191
6192	/* Natural page crossing: */
6193	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesAcrossPageLoadingTlb);
6194	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesAcrossPageLoadingTlb);
6195	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesAcrossPageLoadingTlbConsiderCsLim);
6196
6197	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesOnNextPageLoadingTlb);
6198	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNextPageLoadingTlb);
6199	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNextPageLoadingTlbConsiderCsLim);
6200
6201	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesOnNewPageLoadingTlb);
6202	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNewPageLoadingTlb);
6203	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNewPageLoadingTlbConsiderCsLim);
6204
6205	bool iemThreadedCompileEmitIrqCheckBefore(PVMCPUCC pVCpu, PIEMTB pTb);
6206	bool iemThreadedCompileBeginEmitCallsComplications(PVMCPUCC pVCpu, PIEMTB pTb);
6207
6208	/* Native recompiler public bits: */
6209	DECLHIDDEN(PIEMTB) iemNativeRecompile(PVMCPUCC pVCpu, PIEMTB pTb) RT_NOEXCEPT;
6210	DECLHIDDEN(void) iemNativeDisassembleTb(PCIEMTB pTb, PCDBGFINFOHLP pHlp) RT_NOEXCEPT;
6211	int iemExecMemAllocatorInit(PVMCPU pVCpu, uint64_t cbMax, uint64_t cbInitial, uint32_t cbChunk) RT_NOEXCEPT;
6212	DECLHIDDEN(void *) iemExecMemAllocatorAlloc(PVMCPU pVCpu, uint32_t cbReq, PIEMTB pTb) RT_NOEXCEPT;
6213	DECLHIDDEN(void) iemExecMemAllocatorReadyForUse(PVMCPUCC pVCpu, void *pv, size_t cb) RT_NOEXCEPT;
6214	void iemExecMemAllocatorFree(PVMCPU pVCpu, void *pv, size_t cb) RT_NOEXCEPT;
6215	DECLASM(DECL_NO_RETURN(void)) iemNativeTbLongJmp(void *pvFramePointer, int rc) RT_NOEXCEPT;
6216
6217	#endif /* !RT_IN_ASSEMBLER - ASM-NOINC-END */
6218
6219
6220	/** @} */
6221
6222	RT_C_DECLS_END
6223
6224	/* ASM-INC: %include "IEMInternalStruct.mac" */
6225
6226	#endif /* !VMM_INCLUDED_SRC_include_IEMInternal_h */
6227

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source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h@ 104378

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