IEMInternal.h@ 104386

Last change on this file since 104386 was 104383, checked in by vboxsync, 8 months ago
VMM/IEM: Automtically convert IEMInternal.h & IEMN8veRecompiler.h into nasm/yasm include files so IEMAllN8veHlpA.asm can make use of some of the constants define in them for the prolog code. [doxygen] bugref:10653 bugref:10370
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 319.7 KB

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1	/* $Id: IEMInternal.h 104383 2024-04-19 20:00:51Z vboxsync $ */
2	/** @file
3	* IEM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2011-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_IEMInternal_h
29	#define VMM_INCLUDED_SRC_include_IEMInternal_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#ifndef RT_IN_ASSEMBLER
35	# include <VBox/vmm/cpum.h>
36	# include <VBox/vmm/iem.h>
37	# include <VBox/vmm/pgm.h>
38	# include <VBox/vmm/stam.h>
39	# include <VBox/param.h>
40
41	# include <iprt/setjmp-without-sigmask.h>
42	# include <iprt/list.h>
43	#endif /* !RT_IN_ASSEMBLER */
44
45
46	RT_C_DECLS_BEGIN
47
48
49	/** @defgroup grp_iem_int Internals
50	* @ingroup grp_iem
51	* @internal
52	* @{
53	*/
54
55	/* Make doxygen happy w/o overcomplicating the #if checks. */
56	#ifdef DOXYGEN_RUNNING
57	# define IEM_WITH_THROW_CATCH
58	# define VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
59	#endif
60
61	/** For expanding symbol in slickedit and other products tagging and
62	* crossreferencing IEM symbols. */
63	#ifndef IEM_STATIC
64	# define IEM_STATIC static
65	#endif
66
67	/** @def IEM_WITH_SETJMP
68	* Enables alternative status code handling using setjmps.
69	*
70	* This adds a bit of expense via the setjmp() call since it saves all the
71	* non-volatile registers. However, it eliminates return code checks and allows
72	* for more optimal return value passing (return regs instead of stack buffer).
73	*/
74	#if defined(DOXYGEN_RUNNING) \|\| defined(RT_OS_WINDOWS) \|\| 1
75	# define IEM_WITH_SETJMP
76	#endif
77
78	/** @def IEM_WITH_THROW_CATCH
79	* Enables using C++ throw/catch as an alternative to setjmp/longjmp in user
80	* mode code when IEM_WITH_SETJMP is in effect.
81	*
82	* With GCC 11.3.1 and code TLB on linux, using throw/catch instead of
83	* setjmp/long resulted in bs2-test-1 running 3.00% faster and all but on test
84	* result value improving by more than 1%. (Best out of three.)
85	*
86	* With Visual C++ 2019 and code TLB on windows, using throw/catch instead of
87	* setjmp/long resulted in bs2-test-1 running 3.68% faster and all but some of
88	* the MMIO and CPUID tests ran noticeably faster. Variation is greater than on
89	* Linux, but it should be quite a bit faster for normal code.
90	*/
91	#if defined(__cplusplus) && defined(IEM_WITH_SETJMP) && defined(IN_RING3) && (defined(__GNUC__) \|\| defined(_MSC_VER)) /* ASM-NOINC-START */
92	# define IEM_WITH_THROW_CATCH
93	#endif /ASM-NOINC-END/
94
95	/** @def IEMNATIVE_WITH_DELAYED_PC_UPDATING
96	* Enables the delayed PC updating optimization (see @bugref{10373}).
97	*/
98	#if defined(DOXYGEN_RUNNING) \|\| 1
99	# define IEMNATIVE_WITH_DELAYED_PC_UPDATING
100	#endif
101
102	/** Enables the SIMD register allocator @bugref{10614}. */
103	#if defined(DOXYGEN_RUNNING) \|\| 1
104	# define IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
105	#endif
106	/** Enables access to even callee saved registers. */
107	//# define IEMNATIVE_WITH_SIMD_REG_ACCESS_ALL_REGISTERS
108
109	#if defined(DOXYGEN_RUNNING) \|\| 1
110	/** @def IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
111	* Delay the writeback or dirty registers as long as possible. */
112	# define IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
113	#endif
114
115	/** @def VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
116	* Enables a quicker alternative to throw/longjmp for IEM_DO_LONGJMP when
117	* executing native translation blocks.
118	*
119	* This exploits the fact that we save all non-volatile registers in the TB
120	* prologue and thus just need to do the same as the TB epilogue to get the
121	* effect of a longjmp/throw. Since MSC marks XMM6 thru XMM15 as
122	* non-volatile (and does something even more crazy for ARM), this probably
123	* won't work reliably on Windows. */
124	#ifdef RT_ARCH_ARM64
125	# ifndef RT_OS_WINDOWS
126	# define VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
127	# endif
128	#endif
129	/* ASM-NOINC-START */
130	#ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
131	# if !defined(IN_RING3) \
132	\|\| !defined(VBOX_WITH_IEM_RECOMPILER) \
133	\|\| !defined(VBOX_WITH_IEM_NATIVE_RECOMPILER)
134	# undef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
135	# elif defined(RT_OS_WINDOWS)
136	# pragma message("VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP is not safe to use on windows")
137	# endif
138	#endif
139
140
141	/** @def IEM_DO_LONGJMP
142	*
143	* Wrapper around longjmp / throw.
144	*
145	* @param a_pVCpu The CPU handle.
146	* @param a_rc The status code jump back with / throw.
147	*/
148	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
149	# ifdef IEM_WITH_THROW_CATCH
150	# ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
151	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) do { \
152	if ((a_pVCpu)->iem.s.pvTbFramePointerR3) \
153	iemNativeTbLongJmp((a_pVCpu)->iem.s.pvTbFramePointerR3, (a_rc)); \
154	throw int(a_rc); \
155	} while (0)
156	# else
157	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) throw int(a_rc)
158	# endif
159	# else
160	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) longjmp(*(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf), (a_rc))
161	# endif
162	#endif
163
164	/** For use with IEM function that may do a longjmp (when enabled).
165	*
166	* Visual C++ has trouble longjmp'ing from/over functions with the noexcept
167	* attribute. So, we indicate that function that may be part of a longjmp may
168	* throw "exceptions" and that the compiler should definitely not generate and
169	* std::terminate calling unwind code.
170	*
171	* Here is one example of this ending in std::terminate:
172	* @code{.txt}
173	00 00000041`cadfda10 00007ffc`5d5a1f9f ucrtbase!abort+0x4e
174	01 00000041`cadfda40 00007ffc`57af229a ucrtbase!terminate+0x1f
175	02 00000041`cadfda70 00007ffb`eec91030 VCRUNTIME140!__std_terminate+0xa [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\ehhelpers.cpp @ 192]
176	03 00000041`cadfdaa0 00007ffb`eec92c6d VCRUNTIME140_1!_CallSettingFrame+0x20 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\handlers.asm @ 50]
177	04 00000041`cadfdad0 00007ffb`eec93ae5 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToState+0x241 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 1085]
178	05 00000041`cadfdc00 00007ffb`eec92258 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToEmptyState+0x2d [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 218]
179	06 00000041`cadfdc30 00007ffb`eec940e9 VCRUNTIME140_1!__InternalCxxFrameHandler<__FrameHandler4>+0x194 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 304]
180	07 00000041`cadfdcd0 00007ffc`5f9f249f VCRUNTIME140_1!__CxxFrameHandler4+0xa9 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 290]
181	08 00000041`cadfdd40 00007ffc`5f980939 ntdll!RtlpExecuteHandlerForUnwind+0xf
182	09 00000041`cadfdd70 00007ffc`5f9a0edd ntdll!RtlUnwindEx+0x339
183	0a 00000041`cadfe490 00007ffc`57aff976 ntdll!RtlUnwind+0xcd
184	0b 00000041`cadfea00 00007ffb`e1b5de01 VCRUNTIME140!__longjmp_internal+0xe6 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\longjmp.asm @ 140]
185	0c (Inline Function) --------`-------- VBoxVMM!iemOpcodeGetNextU8SlowJmp+0x95 [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 1155]
186	0d 00000041`cadfea50 00007ffb`e1b60f6b VBoxVMM!iemOpcodeGetNextU8Jmp+0xc1 [L:\vbox-intern\src\VBox\VMM\include\IEMInline.h @ 402]
187	0e 00000041`cadfea90 00007ffb`e1cc6201 VBoxVMM!IEMExecForExits+0xdb [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 10185]
188	0f 00000041`cadfec70 00007ffb`e1d0df8d VBoxVMM!EMHistoryExec+0x4f1 [L:\vbox-intern\src\VBox\VMM\VMMAll\EMAll.cpp @ 452]
189	10 00000041`cadfed60 00007ffb`e1d0d4c0 VBoxVMM!nemR3WinHandleExitCpuId+0x79d [L:\vbox-intern\src\VBox\VMM\VMMAll\NEMAllNativeTemplate-win.cpp.h @ 1829] @encode
190	@endcode
191	*
192	* @see https://developercommunity.visualstudio.com/t/fragile-behavior-of-longjmp-called-from-noexcept-f/1532859
193	*/
194	#if defined(IEM_WITH_SETJMP) && (defined(_MSC_VER) \|\| defined(IEM_WITH_THROW_CATCH))
195	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT_EX(false)
196	#else
197	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT
198	#endif
199	/* ASM-NOINC-END */
200
201	#define IEM_IMPLEMENTS_TASKSWITCH
202
203	/** @def IEM_WITH_3DNOW
204	* Includes the 3DNow decoding. */
205	#if !defined(IEM_WITH_3DNOW) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
206	# ifndef IEM_WITHOUT_3DNOW
207	# define IEM_WITH_3DNOW
208	# endif
209	#endif
210
211	/** @def IEM_WITH_THREE_0F_38
212	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
213	#if !defined(IEM_WITH_THREE_0F_38) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
214	# ifndef IEM_WITHOUT_THREE_0F_38
215	# define IEM_WITH_THREE_0F_38
216	# endif
217	#endif
218
219	/** @def IEM_WITH_THREE_0F_3A
220	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
221	#if !defined(IEM_WITH_THREE_0F_3A) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
222	# ifndef IEM_WITHOUT_THREE_0F_3A
223	# define IEM_WITH_THREE_0F_3A
224	# endif
225	#endif
226
227	/** @def IEM_WITH_VEX
228	* Includes the VEX decoding. */
229	#if !defined(IEM_WITH_VEX) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
230	# ifndef IEM_WITHOUT_VEX
231	# define IEM_WITH_VEX
232	# endif
233	#endif
234
235	/** @def IEM_CFG_TARGET_CPU
236	* The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
237	*
238	* By default we allow this to be configured by the user via the
239	* CPUM/GuestCpuName config string, but this comes at a slight cost during
240	* decoding. So, for applications of this code where there is no need to
241	* be dynamic wrt target CPU, just modify this define.
242	*/
243	#if !defined(IEM_CFG_TARGET_CPU) \|\| defined(DOXYGEN_RUNNING)
244	# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
245	#endif
246
247	//#define IEM_WITH_CODE_TLB // - work in progress
248	//#define IEM_WITH_DATA_TLB // - work in progress
249
250
251	/** @def IEM_USE_UNALIGNED_DATA_ACCESS
252	* Use unaligned accesses instead of elaborate byte assembly. */
253	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86) \|\| defined(DOXYGEN_RUNNING) /ASM-NOINC/
254	# define IEM_USE_UNALIGNED_DATA_ACCESS
255	#endif /ASM-NOINC/
256
257	//#define IEM_LOG_MEMORY_WRITES
258
259
260
261	#ifndef RT_IN_ASSEMBLER /* ASM-NOINC-START - the rest of the file */
262
263	# if !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
264	/** Instruction statistics. */
265	typedef struct IEMINSTRSTATS
266	{
267	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
268	# include "IEMInstructionStatisticsTmpl.h"
269	# undef IEM_DO_INSTR_STAT
270	} IEMINSTRSTATS;
271	#else
272	struct IEMINSTRSTATS;
273	typedef struct IEMINSTRSTATS IEMINSTRSTATS;
274	#endif
275	/** Pointer to IEM instruction statistics. */
276	typedef IEMINSTRSTATS *PIEMINSTRSTATS;
277
278
279	/** @name IEMTARGETCPU_EFL_BEHAVIOR_XXX - IEMCPU::aidxTargetCpuEflFlavour
280	* @{ */
281	#define IEMTARGETCPU_EFL_BEHAVIOR_NATIVE 0 /*< Native x86 EFLAGS result; Intel EFLAGS when on non-x86 hosts. /
282	#define IEMTARGETCPU_EFL_BEHAVIOR_INTEL 1 /*< Intel EFLAGS result. /
283	#define IEMTARGETCPU_EFL_BEHAVIOR_AMD 2 /*< AMD EFLAGS result /
284	#define IEMTARGETCPU_EFL_BEHAVIOR_RESERVED 3 /*< Reserved/dummy entry slot that's the same as 0. /
285	#define IEMTARGETCPU_EFL_BEHAVIOR_MASK 3 /*< For masking the index before use. /
286	/** Selects the right variant from a_aArray.
287	* pVCpu is implicit in the caller context. */
288	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT(a_aArray) \
289	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[1] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
290	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for when no native worker can
291	* be used because the host CPU does not support the operation. */
292	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_NON_NATIVE(a_aArray) \
293	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
294	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for a two dimentional
295	* array paralleling IEMCPU::aidxTargetCpuEflFlavour and a single bit index
296	* into the two.
297	* @sa IEM_SELECT_NATIVE_OR_FALLBACK */
298	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
299	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
300	(a_aaArray[a_fNative][pVCpu->iem.s.aidxTargetCpuEflFlavour[a_fNative] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
301	#else
302	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
303	(a_aaArray[0][pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
304	#endif
305	/** @} */
306
307	/**
308	* Picks @a a_pfnNative or @a a_pfnFallback according to the host CPU feature
309	* indicator given by @a a_fCpumFeatureMember (CPUMFEATURES member).
310	*
311	* On non-x86 hosts, this will shortcut to the fallback w/o checking the
312	* indicator.
313	*
314	* @sa IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX
315	*/
316	#if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
317	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) \
318	(g_CpumHostFeatures.s.a_fCpumFeatureMember ? a_pfnNative : a_pfnFallback)
319	#else
320	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) (a_pfnFallback)
321	#endif
322
323
324	/**
325	* Branch types.
326	*/
327	typedef enum IEMBRANCH
328	{
329	IEMBRANCH_JUMP = 1,
330	IEMBRANCH_CALL,
331	IEMBRANCH_TRAP,
332	IEMBRANCH_SOFTWARE_INT,
333	IEMBRANCH_HARDWARE_INT
334	} IEMBRANCH;
335	AssertCompileSize(IEMBRANCH, 4);
336
337
338	/**
339	* INT instruction types.
340	*/
341	typedef enum IEMINT
342	{
343	/** INT n instruction (opcode 0xcd imm). */
344	IEMINT_INTN = 0,
345	/** Single byte INT3 instruction (opcode 0xcc). */
346	IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
347	/** Single byte INTO instruction (opcode 0xce). */
348	IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
349	/** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
350	IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
351	} IEMINT;
352	AssertCompileSize(IEMINT, 4);
353
354
355	/**
356	* A FPU result.
357	*/
358	typedef struct IEMFPURESULT
359	{
360	/** The output value. */
361	RTFLOAT80U r80Result;
362	/** The output status. */
363	uint16_t FSW;
364	} IEMFPURESULT;
365	AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
366	/** Pointer to a FPU result. */
367	typedef IEMFPURESULT *PIEMFPURESULT;
368	/** Pointer to a const FPU result. */
369	typedef IEMFPURESULT const *PCIEMFPURESULT;
370
371
372	/**
373	* A FPU result consisting of two output values and FSW.
374	*/
375	typedef struct IEMFPURESULTTWO
376	{
377	/** The first output value. */
378	RTFLOAT80U r80Result1;
379	/** The output status. */
380	uint16_t FSW;
381	/** The second output value. */
382	RTFLOAT80U r80Result2;
383	} IEMFPURESULTTWO;
384	AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
385	AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
386	/** Pointer to a FPU result consisting of two output values and FSW. */
387	typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
388	/** Pointer to a const FPU result consisting of two output values and FSW. */
389	typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
390
391
392	/**
393	* IEM TLB entry.
394	*
395	* Lookup assembly:
396	* @code{.asm}
397	; Calculate tag.
398	mov rax, [VA]
399	shl rax, 16
400	shr rax, 16 + X86_PAGE_SHIFT
401	or rax, [uTlbRevision]
402
403	; Do indexing.
404	movzx ecx, al
405	lea rcx, [pTlbEntries + rcx]
406
407	; Check tag.
408	cmp [rcx + IEMTLBENTRY.uTag], rax
409	jne .TlbMiss
410
411	; Check access.
412	mov rax, ACCESS_FLAGS \| MAPPING_R3_NOT_VALID \| 0xffffff00
413	and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
414	cmp rax, [uTlbPhysRev]
415	jne .TlbMiss
416
417	; Calc address and we're done.
418	mov eax, X86_PAGE_OFFSET_MASK
419	and eax, [VA]
420	or rax, [rcx + IEMTLBENTRY.pMappingR3]
421	%ifdef VBOX_WITH_STATISTICS
422	inc qword [cTlbHits]
423	%endif
424	jmp .Done
425
426	.TlbMiss:
427	mov r8d, ACCESS_FLAGS
428	mov rdx, [VA]
429	mov rcx, [pVCpu]
430	call iemTlbTypeMiss
431	.Done:
432
433	@endcode
434	*
435	*/
436	typedef struct IEMTLBENTRY
437	{
438	/** The TLB entry tag.
439	* Bits 35 thru 0 are made up of the virtual address shifted right 12 bits, this
440	* is ASSUMING a virtual address width of 48 bits.
441	*
442	* Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
443	*
444	* The TLB lookup code uses the current TLB revision, which won't ever be zero,
445	* enabling an extremely cheap TLB invalidation most of the time. When the TLB
446	* revision wraps around though, the tags needs to be zeroed.
447	*
448	* @note Try use SHRD instruction? After seeing
449	* https://gmplib.org/~tege/x86-timing.pdf, maybe not.
450	*
451	* @todo This will need to be reorganized for 57-bit wide virtual address and
452	* PCID (currently 12 bits) and ASID (currently 6 bits) support. We'll
453	* have to move the TLB entry versioning entirely to the
454	* fFlagsAndPhysRev member then, 57 bit wide VAs means we'll only have
455	* 19 bits left (64 - 57 + 12 = 19) and they'll almost entire be
456	* consumed by PCID and ASID (12 + 6 = 18).
457	*/
458	uint64_t uTag;
459	/** Access flags and physical TLB revision.
460	*
461	* - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
462	* - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
463	* - Bit 2 - page tables - not user (complemented X86_PTE_US).
464	* - Bit 3 - pgm phys/virt - not directly writable.
465	* - Bit 4 - pgm phys page - not directly readable.
466	* - Bit 5 - page tables - not accessed (complemented X86_PTE_A).
467	* - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
468	* - Bit 7 - tlb entry - pMappingR3 member not valid.
469	* - Bits 63 thru 8 are used for the physical TLB revision number.
470	*
471	* We're using complemented bit meanings here because it makes it easy to check
472	* whether special action is required. For instance a user mode write access
473	* would do a "TEST fFlags, (X86_PTE_RW \| X86_PTE_US \| X86_PTE_D)" and a
474	* non-zero result would mean special handling needed because either it wasn't
475	* writable, or it wasn't user, or the page wasn't dirty. A user mode read
476	* access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
477	* need to check any PTE flag.
478	*/
479	uint64_t fFlagsAndPhysRev;
480	/** The guest physical page address. */
481	uint64_t GCPhys;
482	/** Pointer to the ring-3 mapping. */
483	R3PTRTYPE(uint8_t *) pbMappingR3;
484	#if HC_ARCH_BITS == 32
485	uint32_t u32Padding1;
486	#endif
487	} IEMTLBENTRY;
488	AssertCompileSize(IEMTLBENTRY, 32);
489	/** Pointer to an IEM TLB entry. */
490	typedef IEMTLBENTRY *PIEMTLBENTRY;
491
492	/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
493	* @{ */
494	#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /*< Page tables: Not executable. /
495	#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /*< Page tables: Not writable. /
496	#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /*< Page tables: Not user accessible (supervisor only). /
497	#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /*< Phys page: Not writable (access handler, ROM, whatever). /
498	#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /*< Phys page: Not readable (MMIO / access handler, ROM) /
499	#define IEMTLBE_F_PT_NO_ACCESSED RT_BIT_64(5) /*< Phys tables: Not accessed (need to be marked accessed). /
500	#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /*< Page tables: Not dirty (needs to be made dirty on write). /
501	#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(7) /*< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. /
502	#define IEMTLBE_F_PG_UNASSIGNED RT_BIT_64(8) /*< Phys page: Unassigned memory (not RAM, ROM, MMIO2 or MMIO). /
503	#define IEMTLBE_F_PG_CODE_PAGE RT_BIT_64(9) /*< Phys page: Code page. /
504	#define IEMTLBE_F_PHYS_REV UINT64_C(0xfffffffffffffc00) /*< Physical revision mask. @sa IEMTLB_PHYS_REV_INCR /
505	/** @} */
506
507
508	/**
509	* An IEM TLB.
510	*
511	* We've got two of these, one for data and one for instructions.
512	*/
513	typedef struct IEMTLB
514	{
515	/** The TLB revision.
516	* This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
517	* by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
518	* the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
519	* (The revision zero indicates an invalid TLB entry.)
520	*
521	* The initial value is choosen to cause an early wraparound. */
522	uint64_t uTlbRevision;
523	/** The TLB physical address revision - shadow of PGM variable.
524	*
525	* This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
526	* incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
527	* a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
528	* as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
529	*
530	* The initial value is choosen to cause an early wraparound. */
531	uint64_t volatile uTlbPhysRev;
532
533	/* Statistics: */
534
535	/** TLB hits (VBOX_WITH_STATISTICS only). */
536	uint64_t cTlbHits;
537	/** TLB misses. */
538	uint32_t cTlbMisses;
539	/** Slow read path. */
540	uint32_t cTlbSlowReadPath;
541	/** Safe read path. */
542	uint32_t cTlbSafeReadPath;
543	/** Safe write path. */
544	uint32_t cTlbSafeWritePath;
545	#if 0
546	/** TLB misses because of tag mismatch. */
547	uint32_t cTlbMissesTag;
548	/** TLB misses because of virtual access violation. */
549	uint32_t cTlbMissesVirtAccess;
550	/** TLB misses because of dirty bit. */
551	uint32_t cTlbMissesDirty;
552	/** TLB misses because of MMIO */
553	uint32_t cTlbMissesMmio;
554	/** TLB misses because of write access handlers. */
555	uint32_t cTlbMissesWriteHandler;
556	/** TLB misses because no r3(/r0) mapping. */
557	uint32_t cTlbMissesMapping;
558	#endif
559	/** Alignment padding. */
560	uint32_t au32Padding[6];
561
562	/** The TLB entries.
563	* We've choosen 256 because that way we can obtain the result directly from a
564	* 8-bit register without an additional AND instruction. */
565	IEMTLBENTRY aEntries[256];
566	} IEMTLB;
567	AssertCompileSizeAlignment(IEMTLB, 64);
568	/** IEMTLB::uTlbRevision increment. */
569	#define IEMTLB_REVISION_INCR RT_BIT_64(36)
570	/** IEMTLB::uTlbRevision mask. */
571	#define IEMTLB_REVISION_MASK (~(RT_BIT_64(36) - 1))
572	/** IEMTLB::uTlbPhysRev increment.
573	* @sa IEMTLBE_F_PHYS_REV */
574	#define IEMTLB_PHYS_REV_INCR RT_BIT_64(10)
575	/**
576	* Calculates the TLB tag for a virtual address.
577	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
578	* @param a_pTlb The TLB.
579	* @param a_GCPtr The virtual address. Must be RTGCPTR or same size or
580	* the clearing of the top 16 bits won't work (if 32-bit
581	* we'll end up with mostly zeros).
582	*/
583	#define IEMTLB_CALC_TAG(a_pTlb, a_GCPtr) ( IEMTLB_CALC_TAG_NO_REV(a_GCPtr) \| (a_pTlb)->uTlbRevision )
584	/**
585	* Calculates the TLB tag for a virtual address but without TLB revision.
586	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
587	* @param a_GCPtr The virtual address. Must be RTGCPTR or same size or
588	* the clearing of the top 16 bits won't work (if 32-bit
589	* we'll end up with mostly zeros).
590	*/
591	#define IEMTLB_CALC_TAG_NO_REV(a_GCPtr) ( (((a_GCPtr) << 16) >> (GUEST_PAGE_SHIFT + 16)) )
592	/**
593	* Converts a TLB tag value into a TLB index.
594	* @returns Index into IEMTLB::aEntries.
595	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
596	*/
597	#define IEMTLB_TAG_TO_INDEX(a_uTag) ( (uint8_t)(a_uTag) )
598	/**
599	* Converts a TLB tag value into a TLB index.
600	* @returns Index into IEMTLB::aEntries.
601	* @param a_pTlb The TLB.
602	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
603	*/
604	#define IEMTLB_TAG_TO_ENTRY(a_pTlb, a_uTag) ( &(a_pTlb)->aEntries[IEMTLB_TAG_TO_INDEX(a_uTag)] )
605
606
607	/** @name IEM_MC_F_XXX - MC block flags/clues.
608	* @todo Merge with IEM_CIMPL_F_XXX
609	* @{ */
610	#define IEM_MC_F_ONLY_8086 RT_BIT_32(0)
611	#define IEM_MC_F_MIN_186 RT_BIT_32(1)
612	#define IEM_MC_F_MIN_286 RT_BIT_32(2)
613	#define IEM_MC_F_NOT_286_OR_OLDER IEM_MC_F_MIN_386
614	#define IEM_MC_F_MIN_386 RT_BIT_32(3)
615	#define IEM_MC_F_MIN_486 RT_BIT_32(4)
616	#define IEM_MC_F_MIN_PENTIUM RT_BIT_32(5)
617	#define IEM_MC_F_MIN_PENTIUM_II IEM_MC_F_MIN_PENTIUM
618	#define IEM_MC_F_MIN_CORE IEM_MC_F_MIN_PENTIUM
619	#define IEM_MC_F_64BIT RT_BIT_32(6)
620	#define IEM_MC_F_NOT_64BIT RT_BIT_32(7)
621	/** This is set by IEMAllN8vePython.py to indicate a variation without the
622	* flags-clearing-and-checking, when there is also a variation with that.
623	* @note Do not use this manully, it's only for python and for testing in
624	* the native recompiler! */
625	#define IEM_MC_F_WITHOUT_FLAGS RT_BIT_32(8)
626	/** @} */
627
628	/** @name IEM_CIMPL_F_XXX - State change clues for CIMPL calls.
629	*
630	* These clues are mainly for the recompiler, so that it can emit correct code.
631	*
632	* They are processed by the python script and which also automatically
633	* calculates flags for MC blocks based on the statements, extending the use of
634	* these flags to describe MC block behavior to the recompiler core. The python
635	* script pass the flags to the IEM_MC2_END_EMIT_CALLS macro, but mainly for
636	* error checking purposes. The script emits the necessary fEndTb = true and
637	* similar statements as this reduces compile time a tiny bit.
638	*
639	* @{ */
640	/** Flag set if direct branch, clear if absolute or indirect. */
641	#define IEM_CIMPL_F_BRANCH_DIRECT RT_BIT_32(0)
642	/** Flag set if indirect branch, clear if direct or relative.
643	* This is also used for all system control transfers (SYSCALL, SYSRET, INT, ++)
644	* as well as for return instructions (RET, IRET, RETF). */
645	#define IEM_CIMPL_F_BRANCH_INDIRECT RT_BIT_32(1)
646	/** Flag set if relative branch, clear if absolute or indirect. */
647	#define IEM_CIMPL_F_BRANCH_RELATIVE RT_BIT_32(2)
648	/** Flag set if conditional branch, clear if unconditional. */
649	#define IEM_CIMPL_F_BRANCH_CONDITIONAL RT_BIT_32(3)
650	/** Flag set if it's a far branch (changes CS). */
651	#define IEM_CIMPL_F_BRANCH_FAR RT_BIT_32(4)
652	/** Convenience: Testing any kind of branch. */
653	#define IEM_CIMPL_F_BRANCH_ANY (IEM_CIMPL_F_BRANCH_DIRECT \| IEM_CIMPL_F_BRANCH_INDIRECT \| IEM_CIMPL_F_BRANCH_RELATIVE)
654
655	/** Execution flags may change (IEMCPU::fExec). */
656	#define IEM_CIMPL_F_MODE RT_BIT_32(5)
657	/** May change significant portions of RFLAGS. */
658	#define IEM_CIMPL_F_RFLAGS RT_BIT_32(6)
659	/** May change the status bits (X86_EFL_STATUS_BITS) in RFLAGS. */
660	#define IEM_CIMPL_F_STATUS_FLAGS RT_BIT_32(7)
661	/** May trigger interrupt shadowing. */
662	#define IEM_CIMPL_F_INHIBIT_SHADOW RT_BIT_32(8)
663	/** May enable interrupts, so recheck IRQ immediately afterwards executing
664	* the instruction. */
665	#define IEM_CIMPL_F_CHECK_IRQ_AFTER RT_BIT_32(9)
666	/** May disable interrupts, so recheck IRQ immediately before executing the
667	* instruction. */
668	#define IEM_CIMPL_F_CHECK_IRQ_BEFORE RT_BIT_32(10)
669	/** Convenience: Check for IRQ both before and after an instruction. */
670	#define IEM_CIMPL_F_CHECK_IRQ_BEFORE_AND_AFTER (IEM_CIMPL_F_CHECK_IRQ_BEFORE \| IEM_CIMPL_F_CHECK_IRQ_AFTER)
671	/** May trigger a VM exit (treated like IEM_CIMPL_F_MODE atm). */
672	#define IEM_CIMPL_F_VMEXIT RT_BIT_32(11)
673	/** May modify FPU state.
674	* @todo Not sure if this is useful yet. */
675	#define IEM_CIMPL_F_FPU RT_BIT_32(12)
676	/** REP prefixed instruction which may yield before updating PC.
677	* @todo Not sure if this is useful, REP functions now return non-zero
678	* status if they don't update the PC. */
679	#define IEM_CIMPL_F_REP RT_BIT_32(13)
680	/** I/O instruction.
681	* @todo Not sure if this is useful yet. */
682	#define IEM_CIMPL_F_IO RT_BIT_32(14)
683	/** Force end of TB after the instruction. */
684	#define IEM_CIMPL_F_END_TB RT_BIT_32(15)
685	/** Flag set if a branch may also modify the stack (push/pop return address). */
686	#define IEM_CIMPL_F_BRANCH_STACK RT_BIT_32(16)
687	/** Flag set if a branch may also modify the stack (push/pop return address)
688	* and switch it (load/restore SS:RSP). */
689	#define IEM_CIMPL_F_BRANCH_STACK_FAR RT_BIT_32(17)
690	/** Convenience: Raise exception (technically unnecessary, since it shouldn't return VINF_SUCCESS). */
691	#define IEM_CIMPL_F_XCPT \
692	(IEM_CIMPL_F_BRANCH_INDIRECT \| IEM_CIMPL_F_BRANCH_FAR \| IEM_CIMPL_F_BRANCH_STACK_FAR \
693	\| IEM_CIMPL_F_MODE \| IEM_CIMPL_F_RFLAGS \| IEM_CIMPL_F_VMEXIT)
694
695	/** The block calls a C-implementation instruction function with two implicit arguments.
696	* Mutually exclusive with IEM_CIMPL_F_CALLS_AIMPL and
697	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
698	* @note The python scripts will add this if missing. */
699	#define IEM_CIMPL_F_CALLS_CIMPL RT_BIT_32(18)
700	/** The block calls an ASM-implementation instruction function.
701	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL and
702	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
703	* @note The python scripts will add this if missing. */
704	#define IEM_CIMPL_F_CALLS_AIMPL RT_BIT_32(19)
705	/** The block calls an ASM-implementation instruction function with an implicit
706	* X86FXSTATE pointer argument.
707	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL, IEM_CIMPL_F_CALLS_AIMPL and
708	* IEM_CIMPL_F_CALLS_AIMPL_WITH_XSTATE.
709	* @note The python scripts will add this if missing. */
710	#define IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE RT_BIT_32(20)
711	/** The block calls an ASM-implementation instruction function with an implicit
712	* X86XSAVEAREA pointer argument.
713	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL, IEM_CIMPL_F_CALLS_AIMPL and
714	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
715	* @note No different from IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE, so same value.
716	* @note The python scripts will add this if missing. */
717	#define IEM_CIMPL_F_CALLS_AIMPL_WITH_XSTATE IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE
718	/** @} */
719
720
721	/** @name IEM_F_XXX - Execution mode flags (IEMCPU::fExec, IEMTB::fFlags).
722	*
723	* These flags are set when entering IEM and adjusted as code is executed, such
724	* that they will always contain the current values as instructions are
725	* finished.
726	*
727	* In recompiled execution mode, (most of) these flags are included in the
728	* translation block selection key and stored in IEMTB::fFlags alongside the
729	* IEMTB_F_XXX flags. The latter flags uses bits 31 thru 24, which are all zero
730	* in IEMCPU::fExec.
731	*
732	* @{ */
733	/** Mode: The block target mode mask. */
734	#define IEM_F_MODE_MASK UINT32_C(0x0000001f)
735	/** Mode: The IEMMODE part of the IEMTB_F_MODE_MASK value. */
736	#define IEM_F_MODE_CPUMODE_MASK UINT32_C(0x00000003)
737	/** X86 Mode: Bit used to indicating pre-386 CPU in 16-bit mode (for eliminating
738	* conditional in EIP/IP updating), and flat wide open CS, SS, DS, and ES in
739	* 32-bit mode (for simplifying most memory accesses). */
740	#define IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK UINT32_C(0x00000004)
741	/** X86 Mode: Bit indicating protected mode, real mode (or SMM) when not set. */
742	#define IEM_F_MODE_X86_PROT_MASK UINT32_C(0x00000008)
743	/** X86 Mode: Bit used to indicate virtual 8086 mode (only 16-bit). */
744	#define IEM_F_MODE_X86_V86_MASK UINT32_C(0x00000010)
745
746	/** X86 Mode: 16-bit on 386 or later. */
747	#define IEM_F_MODE_X86_16BIT UINT32_C(0x00000000)
748	/** X86 Mode: 80286, 80186 and 8086/88 targetting blocks (EIP update opt). */
749	#define IEM_F_MODE_X86_16BIT_PRE_386 UINT32_C(0x00000004)
750	/** X86 Mode: 16-bit protected mode on 386 or later. */
751	#define IEM_F_MODE_X86_16BIT_PROT UINT32_C(0x00000008)
752	/** X86 Mode: 16-bit protected mode on 386 or later. */
753	#define IEM_F_MODE_X86_16BIT_PROT_PRE_386 UINT32_C(0x0000000c)
754	/** X86 Mode: 16-bit virtual 8086 protected mode (on 386 or later). */
755	#define IEM_F_MODE_X86_16BIT_PROT_V86 UINT32_C(0x00000018)
756
757	/** X86 Mode: 32-bit on 386 or later. */
758	#define IEM_F_MODE_X86_32BIT UINT32_C(0x00000001)
759	/** X86 Mode: 32-bit mode with wide open flat CS, SS, DS and ES. */
760	#define IEM_F_MODE_X86_32BIT_FLAT UINT32_C(0x00000005)
761	/** X86 Mode: 32-bit protected mode. */
762	#define IEM_F_MODE_X86_32BIT_PROT UINT32_C(0x00000009)
763	/** X86 Mode: 32-bit protected mode with wide open flat CS, SS, DS and ES. */
764	#define IEM_F_MODE_X86_32BIT_PROT_FLAT UINT32_C(0x0000000d)
765
766	/** X86 Mode: 64-bit (includes protected, but not the flat bit). */
767	#define IEM_F_MODE_X86_64BIT UINT32_C(0x0000000a)
768
769	/** X86 Mode: Checks if @a a_fExec represent a FLAT mode. */
770	#define IEM_F_MODE_X86_IS_FLAT(a_fExec) ( ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_64BIT \
771	\|\| ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_32BIT_PROT_FLAT \
772	\|\| ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_32BIT_FLAT)
773
774	/** Bypass access handlers when set. */
775	#define IEM_F_BYPASS_HANDLERS UINT32_C(0x00010000)
776	/** Have pending hardware instruction breakpoints. */
777	#define IEM_F_PENDING_BRK_INSTR UINT32_C(0x00020000)
778	/** Have pending hardware data breakpoints. */
779	#define IEM_F_PENDING_BRK_DATA UINT32_C(0x00040000)
780
781	/** X86: Have pending hardware I/O breakpoints. */
782	#define IEM_F_PENDING_BRK_X86_IO UINT32_C(0x00000400)
783	/** X86: Disregard the lock prefix (implied or not) when set. */
784	#define IEM_F_X86_DISREGARD_LOCK UINT32_C(0x00000800)
785
786	/** Pending breakpoint mask (what iemCalcExecDbgFlags works out). */
787	#define IEM_F_PENDING_BRK_MASK (IEM_F_PENDING_BRK_INSTR \| IEM_F_PENDING_BRK_DATA \| IEM_F_PENDING_BRK_X86_IO)
788
789	/** Caller configurable options. */
790	#define IEM_F_USER_OPTS (IEM_F_BYPASS_HANDLERS \| IEM_F_X86_DISREGARD_LOCK)
791
792	/** X86: The current protection level (CPL) shift factor. */
793	#define IEM_F_X86_CPL_SHIFT 8
794	/** X86: The current protection level (CPL) mask. */
795	#define IEM_F_X86_CPL_MASK UINT32_C(0x00000300)
796	/** X86: The current protection level (CPL) shifted mask. */
797	#define IEM_F_X86_CPL_SMASK UINT32_C(0x00000003)
798
799	/** X86 execution context.
800	* The IEM_F_X86_CTX_XXX values are individual flags that can be combined (with
801	* the exception of IEM_F_X86_CTX_NORMAL). This allows running VMs from SMM
802	* mode. */
803	#define IEM_F_X86_CTX_MASK UINT32_C(0x0000f000)
804	/** X86 context: Plain regular execution context. */
805	#define IEM_F_X86_CTX_NORMAL UINT32_C(0x00000000)
806	/** X86 context: VT-x enabled. */
807	#define IEM_F_X86_CTX_VMX UINT32_C(0x00001000)
808	/** X86 context: AMD-V enabled. */
809	#define IEM_F_X86_CTX_SVM UINT32_C(0x00002000)
810	/** X86 context: In AMD-V or VT-x guest mode. */
811	#define IEM_F_X86_CTX_IN_GUEST UINT32_C(0x00004000)
812	/** X86 context: System management mode (SMM). */
813	#define IEM_F_X86_CTX_SMM UINT32_C(0x00008000)
814
815	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
816	* iemRegFinishClearingRF() most for most situations (CPUMCTX_DBG_HIT_DRX_MASK
817	* and CPUMCTX_DBG_DBGF_MASK are covered by the IEM_F_PENDING_BRK_XXX bits
818	* alread). */
819
820	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
821	* iemRegFinishClearingRF() most for most situations
822	* (CPUMCTX_DBG_HIT_DRX_MASK and CPUMCTX_DBG_DBGF_MASK are covered by
823	* the IEM_F_PENDING_BRK_XXX bits alread). */
824
825	/** @} */
826
827
828	/** @name IEMTB_F_XXX - Translation block flags (IEMTB::fFlags).
829	*
830	* Extends the IEM_F_XXX flags (subject to IEMTB_F_IEM_F_MASK) to make up the
831	* translation block flags. The combined flag mask (subject to
832	* IEMTB_F_KEY_MASK) is used as part of the lookup key for translation blocks.
833	*
834	* @{ */
835	/** Mask of IEM_F_XXX flags included in IEMTB_F_XXX. */
836	#define IEMTB_F_IEM_F_MASK UINT32_C(0x00ffffff)
837
838	/** Type: The block type mask. */
839	#define IEMTB_F_TYPE_MASK UINT32_C(0x03000000)
840	/** Type: Purly threaded recompiler (via tables). */
841	#define IEMTB_F_TYPE_THREADED UINT32_C(0x01000000)
842	/** Type: Native recompilation. */
843	#define IEMTB_F_TYPE_NATIVE UINT32_C(0x02000000)
844
845	/** Set when we're starting the block in an "interrupt shadow".
846	* We don't need to distingish between the two types of this mask, thus the one.
847	* @see CPUMCTX_INHIBIT_SHADOW, CPUMIsInInterruptShadow() */
848	#define IEMTB_F_INHIBIT_SHADOW UINT32_C(0x04000000)
849	/** Set when we're currently inhibiting NMIs
850	* @see CPUMCTX_INHIBIT_NMI, CPUMAreInterruptsInhibitedByNmi() */
851	#define IEMTB_F_INHIBIT_NMI UINT32_C(0x08000000)
852
853	/** Checks that EIP/IP is wihin CS.LIM before each instruction. Used when
854	* we're close the limit before starting a TB, as determined by
855	* iemGetTbFlagsForCurrentPc(). */
856	#define IEMTB_F_CS_LIM_CHECKS UINT32_C(0x10000000)
857
858	/** Mask of the IEMTB_F_XXX flags that are part of the TB lookup key.
859	*
860	* @note We skip all of IEM_F_X86_CTX_MASK, with the exception of SMM (which we
861	* don't implement), because we don't currently generate any context
862	* specific code - that's all handled in CIMPL functions.
863	*
864	* For the threaded recompiler we don't generate any CPL specific code
865	* either, but the native recompiler does for memory access (saves getting
866	* the CPL from fExec and turning it into IEMTLBE_F_PT_NO_USER).
867	* Since most OSes will not share code between rings, this shouldn't
868	* have any real effect on TB/memory/recompiling load.
869	*/
870	#define IEMTB_F_KEY_MASK ((UINT32_MAX & ~(IEM_F_X86_CTX_MASK \| IEMTB_F_TYPE_MASK)) \| IEM_F_X86_CTX_SMM)
871	/** @} */
872
873	AssertCompile( (IEM_F_MODE_X86_16BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
874	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
875	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_PROT_MASK));
876	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_V86_MASK));
877	AssertCompile( (IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
878	AssertCompile( IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
879	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_PROT_MASK));
880	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
881	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
882	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
883	AssertCompile( IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
884	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_V86_MASK));
885	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
886	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
887	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_PROT_MASK);
888	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
889	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_PROT_MASK);
890	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
891	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_V86_MASK);
892
893	AssertCompile( (IEM_F_MODE_X86_32BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
894	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
895	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_PROT_MASK));
896	AssertCompile( (IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
897	AssertCompile( IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
898	AssertCompile(!(IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_PROT_MASK));
899	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
900	AssertCompile(!(IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
901	AssertCompile( IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
902	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
903	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
904	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_PROT_MASK);
905
906	AssertCompile( (IEM_F_MODE_X86_64BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_64BIT);
907	AssertCompile( IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_PROT_MASK);
908	AssertCompile(!(IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
909
910	/** Native instruction type for use with the native code generator.
911	* This is a byte (uint8_t) for x86 and amd64 and uint32_t for the other(s). */
912	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
913	typedef uint8_t IEMNATIVEINSTR;
914	#else
915	typedef uint32_t IEMNATIVEINSTR;
916	#endif
917	/** Pointer to a native instruction unit. */
918	typedef IEMNATIVEINSTR *PIEMNATIVEINSTR;
919	/** Pointer to a const native instruction unit. */
920	typedef IEMNATIVEINSTR const *PCIEMNATIVEINSTR;
921
922	/**
923	* A call for the threaded call table.
924	*/
925	typedef struct IEMTHRDEDCALLENTRY
926	{
927	/** The function to call (IEMTHREADEDFUNCS). */
928	uint16_t enmFunction;
929
930	/** Instruction number in the TB (for statistics). */
931	uint8_t idxInstr;
932	/** The opcode length. */
933	uint8_t cbOpcode;
934	/** Offset into IEMTB::pabOpcodes. */
935	uint16_t offOpcode;
936
937	/** TB lookup table index (7 bits) and large size (1 bits).
938	*
939	* The default size is 1 entry, but for indirect calls and returns we set the
940	* top bit and allocate 4 (IEM_TB_LOOKUP_TAB_LARGE_SIZE) entries. The large
941	* tables uses RIP for selecting the entry to use, as it is assumed a hash table
942	* lookup isn't that slow compared to sequentially trying out 4 TBs.
943	*
944	* By default lookup table entry 0 for a TB is reserved as a fallback for
945	* calltable entries w/o explicit entreis, so this member will be non-zero if
946	* there is a lookup entry associated with this call.
947	*
948	* @sa IEM_TB_LOOKUP_TAB_GET_SIZE, IEM_TB_LOOKUP_TAB_GET_IDX
949	*/
950	uint8_t uTbLookup;
951
952	/** Unused atm. */
953	uint8_t uUnused0;
954
955	/** Generic parameters. */
956	uint64_t auParams[3];
957	} IEMTHRDEDCALLENTRY;
958	AssertCompileSize(IEMTHRDEDCALLENTRY, sizeof(uint64_t) * 4);
959	/** Pointer to a threaded call entry. */
960	typedef struct IEMTHRDEDCALLENTRY *PIEMTHRDEDCALLENTRY;
961	/** Pointer to a const threaded call entry. */
962	typedef IEMTHRDEDCALLENTRY const *PCIEMTHRDEDCALLENTRY;
963
964	/** The number of TB lookup table entries for a large allocation
965	* (IEMTHRDEDCALLENTRY::uTbLookup bit 7 set). */
966	#define IEM_TB_LOOKUP_TAB_LARGE_SIZE 4
967	/** Get the lookup table size from IEMTHRDEDCALLENTRY::uTbLookup. */
968	#define IEM_TB_LOOKUP_TAB_GET_SIZE(a_uTbLookup) (!((a_uTbLookup) & 0x80) ? 1 : IEM_TB_LOOKUP_TAB_LARGE_SIZE)
969	/** Get the first lookup table index from IEMTHRDEDCALLENTRY::uTbLookup. */
970	#define IEM_TB_LOOKUP_TAB_GET_IDX(a_uTbLookup) ((a_uTbLookup) & 0x7f)
971	/** Get the lookup table index from IEMTHRDEDCALLENTRY::uTbLookup and RIP. */
972	#define IEM_TB_LOOKUP_TAB_GET_IDX_WITH_RIP(a_uTbLookup, a_Rip) \
973	(!((a_uTbLookup) & 0x80) ? (a_uTbLookup) & 0x7f : ((a_uTbLookup) & 0x7f) + ((a_Rip) & (IEM_TB_LOOKUP_TAB_LARGE_SIZE - 1)) )
974
975	/** Make a IEMTHRDEDCALLENTRY::uTbLookup value. */
976	#define IEM_TB_LOOKUP_TAB_MAKE(a_idxTable, a_fLarge) ((a_idxTable) \| ((a_fLarge) ? 0x80 : 0))
977
978	/**
979	* Native IEM TB 'function' typedef.
980	*
981	* This will throw/longjmp on occation.
982	*
983	* @note AMD64 doesn't have that many non-volatile registers and does sport
984	* 32-bit address displacments, so we don't need pCtx.
985	*
986	* On ARM64 pCtx allows us to directly address the whole register
987	* context without requiring a separate indexing register holding the
988	* offset. This saves an instruction loading the offset for each guest
989	* CPU context access, at the cost of a non-volatile register.
990	* Fortunately, ARM64 has quite a lot more registers.
991	*/
992	typedef
993	#ifdef RT_ARCH_AMD64
994	int FNIEMTBNATIVE(PVMCPUCC pVCpu)
995	#else
996	int FNIEMTBNATIVE(PVMCPUCC pVCpu, PCPUMCTX pCtx)
997	#endif
998	#if RT_CPLUSPLUS_PREREQ(201700)
999	IEM_NOEXCEPT_MAY_LONGJMP
1000	#endif
1001	;
1002	/** Pointer to a native IEM TB entry point function.
1003	* This will throw/longjmp on occation. */
1004	typedef FNIEMTBNATIVE *PFNIEMTBNATIVE;
1005
1006
1007	/**
1008	* Translation block debug info entry type.
1009	*/
1010	typedef enum IEMTBDBGENTRYTYPE
1011	{
1012	kIemTbDbgEntryType_Invalid = 0,
1013	/** The entry is for marking a native code position.
1014	* Entries following this all apply to this position. */
1015	kIemTbDbgEntryType_NativeOffset,
1016	/** The entry is for a new guest instruction. */
1017	kIemTbDbgEntryType_GuestInstruction,
1018	/** Marks the start of a threaded call. */
1019	kIemTbDbgEntryType_ThreadedCall,
1020	/** Marks the location of a label. */
1021	kIemTbDbgEntryType_Label,
1022	/** Info about a host register shadowing a guest register. */
1023	kIemTbDbgEntryType_GuestRegShadowing,
1024	#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
1025	/** Info about a host SIMD register shadowing a guest SIMD register. */
1026	kIemTbDbgEntryType_GuestSimdRegShadowing,
1027	#endif
1028	#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING
1029	/** Info about a delayed RIP update. */
1030	kIemTbDbgEntryType_DelayedPcUpdate,
1031	#endif
1032	#if defined(IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK) \|\| defined(IEMNATIVE_WITH_SIMD_REG_ALLOCATOR)
1033	/** Info about a shadowed guest register becoming dirty. */
1034	kIemTbDbgEntryType_GuestRegDirty,
1035	/** Info about register writeback/flush oepration. */
1036	kIemTbDbgEntryType_GuestRegWriteback,
1037	#endif
1038	kIemTbDbgEntryType_End
1039	} IEMTBDBGENTRYTYPE;
1040
1041	/**
1042	* Translation block debug info entry.
1043	*/
1044	typedef union IEMTBDBGENTRY
1045	{
1046	/** Plain 32-bit view. */
1047	uint32_t u;
1048
1049	/** Generic view for getting at the type field. */
1050	struct
1051	{
1052	/** IEMTBDBGENTRYTYPE */
1053	uint32_t uType : 4;
1054	uint32_t uTypeSpecific : 28;
1055	} Gen;
1056
1057	struct
1058	{
1059	/** kIemTbDbgEntryType_ThreadedCall1. */
1060	uint32_t uType : 4;
1061	/** Native code offset. */
1062	uint32_t offNative : 28;
1063	} NativeOffset;
1064
1065	struct
1066	{
1067	/** kIemTbDbgEntryType_GuestInstruction. */
1068	uint32_t uType : 4;
1069	uint32_t uUnused : 4;
1070	/** The IEM_F_XXX flags. */
1071	uint32_t fExec : 24;
1072	} GuestInstruction;
1073
1074	struct
1075	{
1076	/* kIemTbDbgEntryType_ThreadedCall. */
1077	uint32_t uType : 4;
1078	/** Set if the call was recompiled to native code, clear if just calling
1079	* threaded function. */
1080	uint32_t fRecompiled : 1;
1081	uint32_t uUnused : 11;
1082	/** The threaded call number (IEMTHREADEDFUNCS). */
1083	uint32_t enmCall : 16;
1084	} ThreadedCall;
1085
1086	struct
1087	{
1088	/* kIemTbDbgEntryType_Label. */
1089	uint32_t uType : 4;
1090	uint32_t uUnused : 4;
1091	/** The label type (IEMNATIVELABELTYPE). */
1092	uint32_t enmLabel : 8;
1093	/** The label data. */
1094	uint32_t uData : 16;
1095	} Label;
1096
1097	struct
1098	{
1099	/* kIemTbDbgEntryType_GuestRegShadowing. */
1100	uint32_t uType : 4;
1101	uint32_t uUnused : 4;
1102	/** The guest register being shadowed (IEMNATIVEGSTREG). */
1103	uint32_t idxGstReg : 8;
1104	/** The host new register number, UINT8_MAX if dropped. */
1105	uint32_t idxHstReg : 8;
1106	/** The previous host register number, UINT8_MAX if new. */
1107	uint32_t idxHstRegPrev : 8;
1108	} GuestRegShadowing;
1109
1110	#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
1111	struct
1112	{
1113	/* kIemTbDbgEntryType_GuestSimdRegShadowing. */
1114	uint32_t uType : 4;
1115	uint32_t uUnused : 4;
1116	/** The guest register being shadowed (IEMNATIVEGSTSIMDREG). */
1117	uint32_t idxGstSimdReg : 8;
1118	/** The host new register number, UINT8_MAX if dropped. */
1119	uint32_t idxHstSimdReg : 8;
1120	/** The previous host register number, UINT8_MAX if new. */
1121	uint32_t idxHstSimdRegPrev : 8;
1122	} GuestSimdRegShadowing;
1123	#endif
1124
1125	#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING
1126	struct
1127	{
1128	/* kIemTbDbgEntryType_DelayedPcUpdate. */
1129	uint32_t uType : 4;
1130	/* The instruction offset added to the program counter. */
1131	uint32_t offPc : 14;
1132	/** Number of instructions skipped. */
1133	uint32_t cInstrSkipped : 14;
1134	} DelayedPcUpdate;
1135	#endif
1136
1137	#if defined(IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK) \|\| defined(IEMNATIVE_WITH_SIMD_REG_ALLOCATOR)
1138	struct
1139	{
1140	/* kIemTbDbgEntryType_GuestRegDirty. */
1141	uint32_t uType : 4;
1142	uint32_t uUnused : 11;
1143	/** Flag whether this is about a SIMD (true) or general (false) register. */
1144	uint32_t fSimdReg : 1;
1145	/** The guest register index being marked as dirty. */
1146	uint32_t idxGstReg : 8;
1147	/** The host register number this register is shadowed in .*/
1148	uint32_t idxHstReg : 8;
1149	} GuestRegDirty;
1150
1151	struct
1152	{
1153	/* kIemTbDbgEntryType_GuestRegWriteback. */
1154	uint32_t uType : 4;
1155	/** Flag whether this is about a SIMD (true) or general (false) register flush. */
1156	uint32_t fSimdReg : 1;
1157	/** The mask shift. */
1158	uint32_t cShift : 2;
1159	/** The guest register mask being written back. */
1160	uint32_t fGstReg : 25;
1161	} GuestRegWriteback;
1162	#endif
1163
1164	} IEMTBDBGENTRY;
1165	AssertCompileSize(IEMTBDBGENTRY, sizeof(uint32_t));
1166	/** Pointer to a debug info entry. */
1167	typedef IEMTBDBGENTRY *PIEMTBDBGENTRY;
1168	/** Pointer to a const debug info entry. */
1169	typedef IEMTBDBGENTRY const *PCIEMTBDBGENTRY;
1170
1171	/**
1172	* Translation block debug info.
1173	*/
1174	typedef struct IEMTBDBG
1175	{
1176	/** Number of entries in aEntries. */
1177	uint32_t cEntries;
1178	/** The offset of the last kIemTbDbgEntryType_NativeOffset record. */
1179	uint32_t offNativeLast;
1180	/** Debug info entries. */
1181	RT_FLEXIBLE_ARRAY_EXTENSION
1182	IEMTBDBGENTRY aEntries[RT_FLEXIBLE_ARRAY];
1183	} IEMTBDBG;
1184	/** Pointer to TB debug info. */
1185	typedef IEMTBDBG *PIEMTBDBG;
1186	/** Pointer to const TB debug info. */
1187	typedef IEMTBDBG const *PCIEMTBDBG;
1188
1189
1190	/**
1191	* Translation block.
1192	*
1193	* The current plan is to just keep TBs and associated lookup hash table private
1194	* to each VCpu as that simplifies TB removal greatly (no races) and generally
1195	* avoids using expensive atomic primitives for updating lists and stuff.
1196	*/
1197	#pragma pack(2) /* to prevent the Thrd structure from being padded unnecessarily */
1198	typedef struct IEMTB
1199	{
1200	/** Next block with the same hash table entry. */
1201	struct IEMTB *pNext;
1202	/** Usage counter. */
1203	uint32_t cUsed;
1204	/** The IEMCPU::msRecompilerPollNow last time it was used. */
1205	uint32_t msLastUsed;
1206
1207	/** @name What uniquely identifies the block.
1208	* @{ */
1209	RTGCPHYS GCPhysPc;
1210	/** IEMTB_F_XXX (i.e. IEM_F_XXX ++). */
1211	uint32_t fFlags;
1212	union
1213	{
1214	struct
1215	{
1216	/*< Relevant CS X86DESCATTR_XXX bits. /
1217	uint16_t fAttr;
1218	} x86;
1219	};
1220	/** @} */
1221
1222	/** Number of opcode ranges. */
1223	uint8_t cRanges;
1224	/** Statistics: Number of instructions in the block. */
1225	uint8_t cInstructions;
1226
1227	/** Type specific info. */
1228	union
1229	{
1230	struct
1231	{
1232	/** The call sequence table. */
1233	PIEMTHRDEDCALLENTRY paCalls;
1234	/** Number of calls in paCalls. */
1235	uint16_t cCalls;
1236	/** Number of calls allocated. */
1237	uint16_t cAllocated;
1238	} Thrd;
1239	struct
1240	{
1241	/** The native instructions (PFNIEMTBNATIVE). */
1242	PIEMNATIVEINSTR paInstructions;
1243	/** Number of instructions pointed to by paInstructions. */
1244	uint32_t cInstructions;
1245	} Native;
1246	/** Generic view for zeroing when freeing. */
1247	struct
1248	{
1249	uintptr_t uPtr;
1250	uint32_t uData;
1251	} Gen;
1252	};
1253
1254	/** The allocation chunk this TB belongs to. */
1255	uint8_t idxAllocChunk;
1256	/** The number of entries in the lookup table.
1257	* Because we're out of space, the TB lookup table is located before the
1258	* opcodes pointed to by pabOpcodes. */
1259	uint8_t cTbLookupEntries;
1260
1261	/** Number of bytes of opcodes stored in pabOpcodes.
1262	* @todo this field isn't really needed, aRanges keeps the actual info. */
1263	uint16_t cbOpcodes;
1264	/** Pointer to the opcode bytes this block was recompiled from.
1265	* This also points to the TB lookup table, which starts cTbLookupEntries
1266	* entries before the opcodes (we don't have room atm for another point). */
1267	uint8_t *pabOpcodes;
1268
1269	/** Debug info if enabled.
1270	* This is only generated by the native recompiler. */
1271	PIEMTBDBG pDbgInfo;
1272
1273	/* --- 64 byte cache line end --- */
1274
1275	/** Opcode ranges.
1276	*
1277	* The opcode checkers and maybe TLB loading functions will use this to figure
1278	* out what to do. The parameter will specify an entry and the opcode offset to
1279	* start at and the minimum number of bytes to verify (instruction length).
1280	*
1281	* When VT-x and AMD-V looks up the opcode bytes for an exitting instruction,
1282	* they'll first translate RIP (+ cbInstr - 1) to a physical address using the
1283	* code TLB (must have a valid entry for that address) and scan the ranges to
1284	* locate the corresponding opcodes. Probably.
1285	*/
1286	struct IEMTBOPCODERANGE
1287	{
1288	/** Offset within pabOpcodes. */
1289	uint16_t offOpcodes;
1290	/** Number of bytes. */
1291	uint16_t cbOpcodes;
1292	/** The page offset. */
1293	RT_GCC_EXTENSION
1294	uint16_t offPhysPage : 12;
1295	/** Unused bits. */
1296	RT_GCC_EXTENSION
1297	uint16_t u2Unused : 2;
1298	/** Index into GCPhysPc + aGCPhysPages for the physical page address. */
1299	RT_GCC_EXTENSION
1300	uint16_t idxPhysPage : 2;
1301	} aRanges[8];
1302
1303	/** Physical pages that this TB covers.
1304	* The GCPhysPc w/o page offset is element zero, so starting here with 1. */
1305	RTGCPHYS aGCPhysPages[2];
1306	} IEMTB;
1307	#pragma pack()
1308	AssertCompileMemberAlignment(IEMTB, GCPhysPc, sizeof(RTGCPHYS));
1309	AssertCompileMemberAlignment(IEMTB, Thrd, sizeof(void *));
1310	AssertCompileMemberAlignment(IEMTB, pabOpcodes, sizeof(void *));
1311	AssertCompileMemberAlignment(IEMTB, pDbgInfo, sizeof(void *));
1312	AssertCompileMemberAlignment(IEMTB, aGCPhysPages, sizeof(RTGCPHYS));
1313	AssertCompileMemberOffset(IEMTB, aRanges, 64);
1314	AssertCompileMemberSize(IEMTB, aRanges[0], 6);
1315	#if 1
1316	AssertCompileSize(IEMTB, 128);
1317	# define IEMTB_SIZE_IS_POWER_OF_TWO /*< The IEMTB size is a power of two. /
1318	#else
1319	AssertCompileSize(IEMTB, 168);
1320	# undef IEMTB_SIZE_IS_POWER_OF_TWO
1321	#endif
1322
1323	/** Pointer to a translation block. */
1324	typedef IEMTB *PIEMTB;
1325	/** Pointer to a const translation block. */
1326	typedef IEMTB const *PCIEMTB;
1327
1328	/** Gets address of the given TB lookup table entry. */
1329	#define IEMTB_GET_TB_LOOKUP_TAB_ENTRY(a_pTb, a_idx) \
1330	((PIEMTB )&(a_pTb)->pabOpcodes[-(int)((a_pTb)->cTbLookupEntries - (a_idx)) sizeof(PIEMTB)])
1331
1332
1333	/**
1334	* A chunk of memory in the TB allocator.
1335	*/
1336	typedef struct IEMTBCHUNK
1337	{
1338	/** Pointer to the translation blocks in this chunk. */
1339	PIEMTB paTbs;
1340	#ifdef IN_RING0
1341	/** Allocation handle. */
1342	RTR0MEMOBJ hMemObj;
1343	#endif
1344	} IEMTBCHUNK;
1345
1346	/**
1347	* A per-CPU translation block allocator.
1348	*
1349	* Because of how the IEMTBCACHE uses the lower 6 bits of the TB address to keep
1350	* the length of the collision list, and of course also for cache line alignment
1351	* reasons, the TBs must be allocated with at least 64-byte alignment.
1352	* Memory is there therefore allocated using one of the page aligned allocators.
1353	*
1354	*
1355	* To avoid wasting too much memory, it is allocated piecemeal as needed,
1356	* in chunks (IEMTBCHUNK) of 2 MiB or more. The TB has an 8-bit chunk index
1357	* that enables us to quickly calculate the allocation bitmap position when
1358	* freeing the translation block.
1359	*/
1360	typedef struct IEMTBALLOCATOR
1361	{
1362	/** Magic value (IEMTBALLOCATOR_MAGIC). */
1363	uint32_t uMagic;
1364
1365	#ifdef IEMTB_SIZE_IS_POWER_OF_TWO
1366	/** Mask corresponding to cTbsPerChunk - 1. */
1367	uint32_t fChunkMask;
1368	/** Shift count corresponding to cTbsPerChunk. */
1369	uint8_t cChunkShift;
1370	#else
1371	uint32_t uUnused;
1372	uint8_t bUnused;
1373	#endif
1374	/** Number of chunks we're allowed to allocate. */
1375	uint8_t cMaxChunks;
1376	/** Number of chunks currently populated. */
1377	uint16_t cAllocatedChunks;
1378	/** Number of translation blocks per chunk. */
1379	uint32_t cTbsPerChunk;
1380	/** Chunk size. */
1381	uint32_t cbPerChunk;
1382
1383	/** The maximum number of TBs. */
1384	uint32_t cMaxTbs;
1385	/** Total number of TBs in the populated chunks.
1386	* (cAllocatedChunks * cTbsPerChunk) */
1387	uint32_t cTotalTbs;
1388	/** The current number of TBs in use.
1389	* The number of free TBs: cAllocatedTbs - cInUseTbs; */
1390	uint32_t cInUseTbs;
1391	/** Statistics: Number of the cInUseTbs that are native ones. */
1392	uint32_t cNativeTbs;
1393	/** Statistics: Number of the cInUseTbs that are threaded ones. */
1394	uint32_t cThreadedTbs;
1395
1396	/** Where to start pruning TBs from when we're out.
1397	* See iemTbAllocatorAllocSlow for details. */
1398	uint32_t iPruneFrom;
1399	/** Hint about which bit to start scanning the bitmap from. */
1400	uint32_t iStartHint;
1401	/** Where to start pruning native TBs from when we're out of executable memory.
1402	* See iemTbAllocatorFreeupNativeSpace for details. */
1403	uint32_t iPruneNativeFrom;
1404	uint32_t uPadding;
1405
1406	/** Statistics: Number of TB allocation calls. */
1407	STAMCOUNTER StatAllocs;
1408	/** Statistics: Number of TB free calls. */
1409	STAMCOUNTER StatFrees;
1410	/** Statistics: Time spend pruning. */
1411	STAMPROFILE StatPrune;
1412	/** Statistics: Time spend pruning native TBs. */
1413	STAMPROFILE StatPruneNative;
1414
1415	/** The delayed free list (see iemTbAlloctorScheduleForFree). */
1416	PIEMTB pDelayedFreeHead;
1417
1418	/** Allocation chunks. */
1419	IEMTBCHUNK aChunks[256];
1420
1421	/** Allocation bitmap for all possible chunk chunks. */
1422	RT_FLEXIBLE_ARRAY_EXTENSION
1423	uint64_t bmAllocated[RT_FLEXIBLE_ARRAY];
1424	} IEMTBALLOCATOR;
1425	/** Pointer to a TB allocator. */
1426	typedef struct IEMTBALLOCATOR *PIEMTBALLOCATOR;
1427
1428	/** Magic value for the TB allocator (Emmet Harley Cohen). */
1429	#define IEMTBALLOCATOR_MAGIC UINT32_C(0x19900525)
1430
1431
1432	/**
1433	* A per-CPU translation block cache (hash table).
1434	*
1435	* The hash table is allocated once during IEM initialization and size double
1436	* the max TB count, rounded up to the nearest power of two (so we can use and
1437	* AND mask rather than a rest division when hashing).
1438	*/
1439	typedef struct IEMTBCACHE
1440	{
1441	/** Magic value (IEMTBCACHE_MAGIC). */
1442	uint32_t uMagic;
1443	/** Size of the hash table. This is a power of two. */
1444	uint32_t cHash;
1445	/** The mask corresponding to cHash. */
1446	uint32_t uHashMask;
1447	uint32_t uPadding;
1448
1449	/** @name Statistics
1450	* @{ */
1451	/** Number of collisions ever. */
1452	STAMCOUNTER cCollisions;
1453
1454	/** Statistics: Number of TB lookup misses. */
1455	STAMCOUNTER cLookupMisses;
1456	/** Statistics: Number of TB lookup hits via hash table (debug only). */
1457	STAMCOUNTER cLookupHits;
1458	/** Statistics: Number of TB lookup hits via TB associated lookup table (debug only). */
1459	STAMCOUNTER cLookupHitsViaTbLookupTable;
1460	STAMCOUNTER auPadding2[2];
1461	/** Statistics: Collision list length pruning. */
1462	STAMPROFILE StatPrune;
1463	/** @} */
1464
1465	/** The hash table itself.
1466	* @note The lower 6 bits of the pointer is used for keeping the collision
1467	* list length, so we can take action when it grows too long.
1468	* This works because TBs are allocated using a 64 byte (or
1469	* higher) alignment from page aligned chunks of memory, so the lower
1470	* 6 bits of the address will always be zero.
1471	* See IEMTBCACHE_PTR_COUNT_MASK, IEMTBCACHE_PTR_MAKE and friends.
1472	*/
1473	RT_FLEXIBLE_ARRAY_EXTENSION
1474	PIEMTB apHash[RT_FLEXIBLE_ARRAY];
1475	} IEMTBCACHE;
1476	/** Pointer to a per-CPU translation block cahce. */
1477	typedef IEMTBCACHE *PIEMTBCACHE;
1478
1479	/** Magic value for IEMTBCACHE (Johnny O'Neal). */
1480	#define IEMTBCACHE_MAGIC UINT32_C(0x19561010)
1481
1482	/** The collision count mask for IEMTBCACHE::apHash entries. */
1483	#define IEMTBCACHE_PTR_COUNT_MASK ((uintptr_t)0x3f)
1484	/** The max collision count for IEMTBCACHE::apHash entries before pruning. */
1485	#define IEMTBCACHE_PTR_MAX_COUNT ((uintptr_t)0x30)
1486	/** Combine a TB pointer and a collision list length into a value for an
1487	* IEMTBCACHE::apHash entry. */
1488	#define IEMTBCACHE_PTR_MAKE(a_pTb, a_cCount) (PIEMTB)((uintptr_t)(a_pTb) \| (a_cCount))
1489	/** Combine a TB pointer and a collision list length into a value for an
1490	* IEMTBCACHE::apHash entry. */
1491	#define IEMTBCACHE_PTR_GET_TB(a_pHashEntry) (PIEMTB)((uintptr_t)(a_pHashEntry) & ~IEMTBCACHE_PTR_COUNT_MASK)
1492	/** Combine a TB pointer and a collision list length into a value for an
1493	* IEMTBCACHE::apHash entry. */
1494	#define IEMTBCACHE_PTR_GET_COUNT(a_pHashEntry) ((uintptr_t)(a_pHashEntry) & IEMTBCACHE_PTR_COUNT_MASK)
1495
1496	/**
1497	* Calculates the hash table slot for a TB from physical PC address and TB flags.
1498	*/
1499	#define IEMTBCACHE_HASH(a_paCache, a_fTbFlags, a_GCPhysPc) \
1500	IEMTBCACHE_HASH_NO_KEY_MASK(a_paCache, (a_fTbFlags) & IEMTB_F_KEY_MASK, a_GCPhysPc)
1501
1502	/**
1503	* Calculates the hash table slot for a TB from physical PC address and TB
1504	* flags, ASSUMING the caller has applied IEMTB_F_KEY_MASK to @a a_fTbFlags.
1505	*/
1506	#define IEMTBCACHE_HASH_NO_KEY_MASK(a_paCache, a_fTbFlags, a_GCPhysPc) \
1507	(((uint32_t)(a_GCPhysPc) ^ (a_fTbFlags)) & (a_paCache)->uHashMask)
1508
1509
1510	/** @name IEMBRANCHED_F_XXX - Branched indicator (IEMCPU::fTbBranched).
1511	*
1512	* These flags parallels the main IEM_CIMPL_F_BRANCH_XXX flags.
1513	*
1514	* @{ */
1515	/** Value if no branching happened recently. */
1516	#define IEMBRANCHED_F_NO UINT8_C(0x00)
1517	/** Flag set if direct branch, clear if absolute or indirect. */
1518	#define IEMBRANCHED_F_DIRECT UINT8_C(0x01)
1519	/** Flag set if indirect branch, clear if direct or relative. */
1520	#define IEMBRANCHED_F_INDIRECT UINT8_C(0x02)
1521	/** Flag set if relative branch, clear if absolute or indirect. */
1522	#define IEMBRANCHED_F_RELATIVE UINT8_C(0x04)
1523	/** Flag set if conditional branch, clear if unconditional. */
1524	#define IEMBRANCHED_F_CONDITIONAL UINT8_C(0x08)
1525	/** Flag set if it's a far branch. */
1526	#define IEMBRANCHED_F_FAR UINT8_C(0x10)
1527	/** Flag set if the stack pointer is modified. */
1528	#define IEMBRANCHED_F_STACK UINT8_C(0x20)
1529	/** Flag set if the stack pointer and (maybe) the stack segment are modified. */
1530	#define IEMBRANCHED_F_STACK_FAR UINT8_C(0x40)
1531	/** Flag set (by IEM_MC_REL_JMP_XXX) if it's a zero bytes relative jump. */
1532	#define IEMBRANCHED_F_ZERO UINT8_C(0x80)
1533	/** @} */
1534
1535
1536	/**
1537	* The per-CPU IEM state.
1538	*/
1539	typedef struct IEMCPU
1540	{
1541	/** Info status code that needs to be propagated to the IEM caller.
1542	* This cannot be passed internally, as it would complicate all success
1543	* checks within the interpreter making the code larger and almost impossible
1544	* to get right. Instead, we'll store status codes to pass on here. Each
1545	* source of these codes will perform appropriate sanity checks. */
1546	int32_t rcPassUp; /* 0x00 */
1547	/** Execution flag, IEM_F_XXX. */
1548	uint32_t fExec; /* 0x04 */
1549
1550	/** @name Decoder state.
1551	* @{ */
1552	#ifdef IEM_WITH_CODE_TLB
1553	/** The offset of the next instruction byte. */
1554	uint32_t offInstrNextByte; /* 0x08 */
1555	/** The number of bytes available at pbInstrBuf for the current instruction.
1556	* This takes the max opcode length into account so that doesn't need to be
1557	* checked separately. */
1558	uint32_t cbInstrBuf; /* 0x0c */
1559	/** Pointer to the page containing RIP, user specified buffer or abOpcode.
1560	* This can be NULL if the page isn't mappable for some reason, in which
1561	* case we'll do fallback stuff.
1562	*
1563	* If we're executing an instruction from a user specified buffer,
1564	* IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
1565	* aligned pointer but pointer to the user data.
1566	*
1567	* For instructions crossing pages, this will start on the first page and be
1568	* advanced to the next page by the time we've decoded the instruction. This
1569	* therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
1570	*/
1571	uint8_t const pbInstrBuf; / 0x10 */
1572	# if ARCH_BITS == 32
1573	uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
1574	# endif
1575	/** The program counter corresponding to pbInstrBuf.
1576	* This is set to a non-canonical address when we need to invalidate it. */
1577	uint64_t uInstrBufPc; /* 0x18 */
1578	/** The guest physical address corresponding to pbInstrBuf. */
1579	RTGCPHYS GCPhysInstrBuf; /* 0x20 */
1580	/** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
1581	* This takes the CS segment limit into account.
1582	* @note Set to zero when the code TLB is flushed to trigger TLB reload. */
1583	uint16_t cbInstrBufTotal; /* 0x28 */
1584	# ifndef IEM_WITH_OPAQUE_DECODER_STATE
1585	/** Offset into pbInstrBuf of the first byte of the current instruction.
1586	* Can be negative to efficiently handle cross page instructions. */
1587	int16_t offCurInstrStart; /* 0x2a */
1588
1589	/** The prefix mask (IEM_OP_PRF_XXX). */
1590	uint32_t fPrefixes; /* 0x2c */
1591	/** The extra REX ModR/M register field bit (REX.R << 3). */
1592	uint8_t uRexReg; /* 0x30 */
1593	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
1594	* (REX.B << 3). */
1595	uint8_t uRexB; /* 0x31 */
1596	/** The extra REX SIB index field bit (REX.X << 3). */
1597	uint8_t uRexIndex; /* 0x32 */
1598
1599	/** The effective segment register (X86_SREG_XXX). */
1600	uint8_t iEffSeg; /* 0x33 */
1601
1602	/** The offset of the ModR/M byte relative to the start of the instruction. */
1603	uint8_t offModRm; /* 0x34 */
1604
1605	# ifdef IEM_WITH_CODE_TLB_AND_OPCODE_BUF
1606	/** The current offset into abOpcode. */
1607	uint8_t offOpcode; /* 0x35 */
1608	# else
1609	uint8_t bUnused; /* 0x35 */
1610	# endif
1611	# else /* IEM_WITH_OPAQUE_DECODER_STATE */
1612	uint8_t abOpaqueDecoderPart1[0x36 - 0x2a];
1613	# endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1614
1615	#else /* !IEM_WITH_CODE_TLB */
1616	# ifndef IEM_WITH_OPAQUE_DECODER_STATE
1617	/** The size of what has currently been fetched into abOpcode. */
1618	uint8_t cbOpcode; /* 0x08 */
1619	/** The current offset into abOpcode. */
1620	uint8_t offOpcode; /* 0x09 */
1621	/** The offset of the ModR/M byte relative to the start of the instruction. */
1622	uint8_t offModRm; /* 0x0a */
1623
1624	/** The effective segment register (X86_SREG_XXX). */
1625	uint8_t iEffSeg; /* 0x0b */
1626
1627	/** The prefix mask (IEM_OP_PRF_XXX). */
1628	uint32_t fPrefixes; /* 0x0c */
1629	/** The extra REX ModR/M register field bit (REX.R << 3). */
1630	uint8_t uRexReg; /* 0x10 */
1631	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
1632	* (REX.B << 3). */
1633	uint8_t uRexB; /* 0x11 */
1634	/** The extra REX SIB index field bit (REX.X << 3). */
1635	uint8_t uRexIndex; /* 0x12 */
1636
1637	# else /* IEM_WITH_OPAQUE_DECODER_STATE */
1638	uint8_t abOpaqueDecoderPart1[0x13 - 0x08];
1639	# endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1640	#endif /* !IEM_WITH_CODE_TLB */
1641
1642	#ifndef IEM_WITH_OPAQUE_DECODER_STATE
1643	/** The effective operand mode. */
1644	IEMMODE enmEffOpSize; /* 0x36, 0x13 */
1645	/** The default addressing mode. */
1646	IEMMODE enmDefAddrMode; /* 0x37, 0x14 */
1647	/** The effective addressing mode. */
1648	IEMMODE enmEffAddrMode; /* 0x38, 0x15 */
1649	/** The default operand mode. */
1650	IEMMODE enmDefOpSize; /* 0x39, 0x16 */
1651
1652	/** Prefix index (VEX.pp) for two byte and three byte tables. */
1653	uint8_t idxPrefix; /* 0x3a, 0x17 */
1654	/** 3rd VEX/EVEX/XOP register.
1655	* Please use IEM_GET_EFFECTIVE_VVVV to access. */
1656	uint8_t uVex3rdReg; /* 0x3b, 0x18 */
1657	/** The VEX/EVEX/XOP length field. */
1658	uint8_t uVexLength; /* 0x3c, 0x19 */
1659	/** Additional EVEX stuff. */
1660	uint8_t fEvexStuff; /* 0x3d, 0x1a */
1661
1662	# ifndef IEM_WITH_CODE_TLB
1663	/** Explicit alignment padding. */
1664	uint8_t abAlignment2a[1]; /* 0x1b */
1665	# endif
1666	/** The FPU opcode (FOP). */
1667	uint16_t uFpuOpcode; /* 0x3e, 0x1c */
1668	# ifndef IEM_WITH_CODE_TLB
1669	/** Explicit alignment padding. */
1670	uint8_t abAlignment2b[2]; /* 0x1e */
1671	# endif
1672
1673	/** The opcode bytes. */
1674	uint8_t abOpcode[15]; /* 0x40, 0x20 */
1675	/** Explicit alignment padding. */
1676	# ifdef IEM_WITH_CODE_TLB
1677	//uint8_t abAlignment2c[0x4f - 0x4f]; /* 0x4f */
1678	# else
1679	uint8_t abAlignment2c[0x4f - 0x2f]; /* 0x2f */
1680	# endif
1681
1682	#else /* IEM_WITH_OPAQUE_DECODER_STATE */
1683	# ifdef IEM_WITH_CODE_TLB
1684	uint8_t abOpaqueDecoderPart2[0x4f - 0x36];
1685	# else
1686	uint8_t abOpaqueDecoderPart2[0x4f - 0x13];
1687	# endif
1688	#endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1689	/** @} */
1690
1691
1692	/** The number of active guest memory mappings. */
1693	uint8_t cActiveMappings; /* 0x4f, 0x4f */
1694
1695	/** Records for tracking guest memory mappings. */
1696	struct
1697	{
1698	/** The address of the mapped bytes. */
1699	R3R0PTRTYPE(void *) pv;
1700	/** The access flags (IEM_ACCESS_XXX).
1701	* IEM_ACCESS_INVALID if the entry is unused. */
1702	uint32_t fAccess;
1703	#if HC_ARCH_BITS == 64
1704	uint32_t u32Alignment4; /*< Alignment padding. /
1705	#endif
1706	} aMemMappings[3]; /* 0x50 LB 0x30 */
1707
1708	/** Locking records for the mapped memory. */
1709	union
1710	{
1711	PGMPAGEMAPLOCK Lock;
1712	uint64_t au64Padding[2];
1713	} aMemMappingLocks[3]; /* 0x80 LB 0x30 */
1714
1715	/** Bounce buffer info.
1716	* This runs in parallel to aMemMappings. */
1717	struct
1718	{
1719	/** The physical address of the first byte. */
1720	RTGCPHYS GCPhysFirst;
1721	/** The physical address of the second page. */
1722	RTGCPHYS GCPhysSecond;
1723	/** The number of bytes in the first page. */
1724	uint16_t cbFirst;
1725	/** The number of bytes in the second page. */
1726	uint16_t cbSecond;
1727	/** Whether it's unassigned memory. */
1728	bool fUnassigned;
1729	/** Explicit alignment padding. */
1730	bool afAlignment5[3];
1731	} aMemBbMappings[3]; /* 0xb0 LB 0x48 */
1732
1733	/** The flags of the current exception / interrupt. */
1734	uint32_t fCurXcpt; /* 0xf8 */
1735	/** The current exception / interrupt. */
1736	uint8_t uCurXcpt; /* 0xfc */
1737	/** Exception / interrupt recursion depth. */
1738	int8_t cXcptRecursions; /* 0xfb */
1739
1740	/** The next unused mapping index.
1741	* @todo try find room for this up with cActiveMappings. */
1742	uint8_t iNextMapping; /* 0xfd */
1743	uint8_t abAlignment7[1];
1744
1745	/** Bounce buffer storage.
1746	* This runs in parallel to aMemMappings and aMemBbMappings. */
1747	struct
1748	{
1749	uint8_t ab[512];
1750	} aBounceBuffers[3]; /* 0x100 LB 0x600 */
1751
1752
1753	/** Pointer set jump buffer - ring-3 context. */
1754	R3PTRTYPE(jmp_buf *) pJmpBufR3;
1755	/** Pointer set jump buffer - ring-0 context. */
1756	R0PTRTYPE(jmp_buf *) pJmpBufR0;
1757
1758	/** @todo Should move this near @a fCurXcpt later. */
1759	/** The CR2 for the current exception / interrupt. */
1760	uint64_t uCurXcptCr2;
1761	/** The error code for the current exception / interrupt. */
1762	uint32_t uCurXcptErr;
1763
1764	/** @name Statistics
1765	* @{ */
1766	/** The number of instructions we've executed. */
1767	uint32_t cInstructions;
1768	/** The number of potential exits. */
1769	uint32_t cPotentialExits;
1770	/** The number of bytes data or stack written (mostly for IEMExecOneEx).
1771	* This may contain uncommitted writes. */
1772	uint32_t cbWritten;
1773	/** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
1774	uint32_t cRetInstrNotImplemented;
1775	/** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
1776	uint32_t cRetAspectNotImplemented;
1777	/** Counts informational statuses returned (other than VINF_SUCCESS). */
1778	uint32_t cRetInfStatuses;
1779	/** Counts other error statuses returned. */
1780	uint32_t cRetErrStatuses;
1781	/** Number of times rcPassUp has been used. */
1782	uint32_t cRetPassUpStatus;
1783	/** Number of times RZ left with instruction commit pending for ring-3. */
1784	uint32_t cPendingCommit;
1785	/** Number of misaligned (host sense) atomic instruction accesses. */
1786	uint32_t cMisalignedAtomics;
1787	/** Number of long jumps. */
1788	uint32_t cLongJumps;
1789	/** @} */
1790
1791	/** @name Target CPU information.
1792	* @{ */
1793	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
1794	/** The target CPU. */
1795	uint8_t uTargetCpu;
1796	#else
1797	uint8_t bTargetCpuPadding;
1798	#endif
1799	/** For selecting assembly works matching the target CPU EFLAGS behaviour, see
1800	* IEMTARGETCPU_EFL_BEHAVIOR_XXX for values, with the 1st entry for when no
1801	* native host support and the 2nd for when there is.
1802	*
1803	* The two values are typically indexed by a g_CpumHostFeatures bit.
1804	*
1805	* This is for instance used for the BSF & BSR instructions where AMD and
1806	* Intel CPUs produce different EFLAGS. */
1807	uint8_t aidxTargetCpuEflFlavour[2];
1808
1809	/** The CPU vendor. */
1810	CPUMCPUVENDOR enmCpuVendor;
1811	/** @} */
1812
1813	/** @name Host CPU information.
1814	* @{ */
1815	/** The CPU vendor. */
1816	CPUMCPUVENDOR enmHostCpuVendor;
1817	/** @} */
1818
1819	/** Counts RDMSR \#GP(0) LogRel(). */
1820	uint8_t cLogRelRdMsr;
1821	/** Counts WRMSR \#GP(0) LogRel(). */
1822	uint8_t cLogRelWrMsr;
1823	/** Alignment padding. */
1824	uint8_t abAlignment9[42];
1825
1826	/** @name Recompilation
1827	* @{ */
1828	/** Pointer to the current translation block.
1829	* This can either be one being executed or one being compiled. */
1830	R3PTRTYPE(PIEMTB) pCurTbR3;
1831	#ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
1832	/** Frame pointer for the last native TB to execute. */
1833	R3PTRTYPE(void *) pvTbFramePointerR3;
1834	#else
1835	R3PTRTYPE(void *) pvUnusedR3;
1836	#endif
1837	/** Fixed TB used for threaded recompilation.
1838	* This is allocated once with maxed-out sizes and re-used afterwards. */
1839	R3PTRTYPE(PIEMTB) pThrdCompileTbR3;
1840	/** Pointer to the ring-3 TB cache for this EMT. */
1841	R3PTRTYPE(PIEMTBCACHE) pTbCacheR3;
1842	/** Pointer to the ring-3 TB lookup entry.
1843	* This either points to pTbLookupEntryDummyR3 or an actually lookuptable
1844	* entry, thus it can always safely be used w/o NULL checking. */
1845	R3PTRTYPE(PIEMTB *) ppTbLookupEntryR3;
1846	/** The PC (RIP) at the start of pCurTbR3/pCurTbR0.
1847	* The TBs are based on physical addresses, so this is needed to correleated
1848	* RIP to opcode bytes stored in the TB (AMD-V / VT-x). */
1849	uint64_t uCurTbStartPc;
1850	/** Number of threaded TBs executed. */
1851	uint64_t cTbExecThreaded;
1852	/** Number of native TBs executed. */
1853	uint64_t cTbExecNative;
1854	/** Whether we need to check the opcode bytes for the current instruction.
1855	* This is set by a previous instruction if it modified memory or similar. */
1856	bool fTbCheckOpcodes;
1857	/** Indicates whether and how we just branched - IEMBRANCHED_F_XXX. */
1858	uint8_t fTbBranched;
1859	/** Set when GCPhysInstrBuf is updated because of a page crossing. */
1860	bool fTbCrossedPage;
1861	/** Whether to end the current TB. */
1862	bool fEndTb;
1863	/** Number of instructions before we need emit an IRQ check call again.
1864	* This helps making sure we don't execute too long w/o checking for
1865	* interrupts and immediately following instructions that may enable
1866	* interrupts (e.g. POPF, IRET, STI). With STI an additional hack is
1867	* required to make sure we check following the next instruction as well, see
1868	* fTbCurInstrIsSti. */
1869	uint8_t cInstrTillIrqCheck;
1870	/** Indicates that the current instruction is an STI. This is set by the
1871	* iemCImpl_sti code and subsequently cleared by the recompiler. */
1872	bool fTbCurInstrIsSti;
1873	/** The size of the IEMTB::pabOpcodes allocation in pThrdCompileTbR3. */
1874	uint16_t cbOpcodesAllocated;
1875	/** The current instruction number in a native TB.
1876	* This is set by code that may trigger an unexpected TB exit (throw/longjmp)
1877	* and will be picked up by the TB execution loop. Only used when
1878	* IEMNATIVE_WITH_INSTRUCTION_COUNTING is defined. */
1879	uint8_t idxTbCurInstr;
1880	/** Spaced reserved for recompiler data / alignment. */
1881	bool afRecompilerStuff1[3];
1882	/** The virtual sync time at the last timer poll call. */
1883	uint32_t msRecompilerPollNow;
1884	/** The IEMTB::cUsed value when to attempt native recompilation of a TB. */
1885	uint32_t uTbNativeRecompileAtUsedCount;
1886	/** The IEM_CIMPL_F_XXX mask for the current instruction. */
1887	uint32_t fTbCurInstr;
1888	/** The IEM_CIMPL_F_XXX mask for the previous instruction. */
1889	uint32_t fTbPrevInstr;
1890	/** Strict: Tracking skipped EFLAGS calculations. Any bits set here are
1891	* currently not up to date in EFLAGS. */
1892	uint32_t fSkippingEFlags;
1893	/** Previous GCPhysInstrBuf value - only valid if fTbCrossedPage is set. */
1894	RTGCPHYS GCPhysInstrBufPrev;
1895	/** Pointer to the ring-3 TB allocator for this EMT. */
1896	R3PTRTYPE(PIEMTBALLOCATOR) pTbAllocatorR3;
1897	/** Pointer to the ring-3 executable memory allocator for this EMT. */
1898	R3PTRTYPE(struct IEMEXECMEMALLOCATOR *) pExecMemAllocatorR3;
1899	/** Pointer to the native recompiler state for ring-3. */
1900	R3PTRTYPE(struct IEMRECOMPILERSTATE *) pNativeRecompilerStateR3;
1901	/** Dummy entry for ppTbLookupEntryR3. */
1902	R3PTRTYPE(PIEMTB) pTbLookupEntryDummyR3;
1903
1904	/** Statistics: Times TB execution was broken off before reaching the end. */
1905	STAMCOUNTER StatTbExecBreaks;
1906	/** Statistics: Times BltIn_CheckIrq breaks out of the TB. */
1907	STAMCOUNTER StatCheckIrqBreaks;
1908	/** Statistics: Times BltIn_CheckMode breaks out of the TB. */
1909	STAMCOUNTER StatCheckModeBreaks;
1910	/** Threaded TB statistics: Times execution break on call with lookup entries. */
1911	STAMCOUNTER StatTbThreadedExecBreaksWithLookup;
1912	/** Threaded TB statistics: Times execution break on call without lookup entries. */
1913	STAMCOUNTER StatTbThreadedExecBreaksWithoutLookup;
1914	/** Statistics: Times a post jump target check missed and had to find new TB. */
1915	STAMCOUNTER StatCheckBranchMisses;
1916	/** Statistics: Times a jump or page crossing required a TB with CS.LIM checking. */
1917	STAMCOUNTER StatCheckNeedCsLimChecking;
1918	/** Statistics: Times a loop was detected within a TB.. */
1919	STAMCOUNTER StatTbLoopInTbDetected;
1920	/** Exec memory allocator statistics: Number of times allocaintg executable memory failed. */
1921	STAMCOUNTER StatNativeExecMemInstrBufAllocFailed;
1922	/** Native TB statistics: Number of fully recompiled TBs. */
1923	STAMCOUNTER StatNativeFullyRecompiledTbs;
1924	/** TB statistics: Number of instructions per TB. */
1925	STAMPROFILE StatTbInstr;
1926	/** TB statistics: Number of TB lookup table entries per TB. */
1927	STAMPROFILE StatTbLookupEntries;
1928	/** Threaded TB statistics: Number of calls per TB. */
1929	STAMPROFILE StatTbThreadedCalls;
1930	/** Native TB statistics: Native code size per TB. */
1931	STAMPROFILE StatTbNativeCode;
1932	/** Native TB statistics: Profiling native recompilation. */
1933	STAMPROFILE StatNativeRecompilation;
1934	/** Native TB statistics: Number of calls per TB that were recompiled properly. */
1935	STAMPROFILE StatNativeCallsRecompiled;
1936	/** Native TB statistics: Number of threaded calls per TB that weren't recompiled. */
1937	STAMPROFILE StatNativeCallsThreaded;
1938	/** Native recompiled execution: TLB hits for data fetches. */
1939	STAMCOUNTER StatNativeTlbHitsForFetch;
1940	/** Native recompiled execution: TLB hits for data stores. */
1941	STAMCOUNTER StatNativeTlbHitsForStore;
1942	/** Native recompiled execution: TLB hits for stack accesses. */
1943	STAMCOUNTER StatNativeTlbHitsForStack;
1944	/** Native recompiled execution: TLB hits for mapped accesses. */
1945	STAMCOUNTER StatNativeTlbHitsForMapped;
1946	/** Native recompiled execution: Code TLB misses for new page. */
1947	STAMCOUNTER StatNativeCodeTlbMissesNewPage;
1948	/** Native recompiled execution: Code TLB hits for new page. */
1949	STAMCOUNTER StatNativeCodeTlbHitsForNewPage;
1950	/** Native recompiled execution: Code TLB misses for new page with offset. */
1951	STAMCOUNTER StatNativeCodeTlbMissesNewPageWithOffset;
1952	/** Native recompiled execution: Code TLB hits for new page with offset. */
1953	STAMCOUNTER StatNativeCodeTlbHitsForNewPageWithOffset;
1954
1955	/** Native recompiler: Number of calls to iemNativeRegAllocFindFree. */
1956	STAMCOUNTER StatNativeRegFindFree;
1957	/** Native recompiler: Number of times iemNativeRegAllocFindFree needed
1958	* to free a variable. */
1959	STAMCOUNTER StatNativeRegFindFreeVar;
1960	/** Native recompiler: Number of times iemNativeRegAllocFindFree did
1961	* not need to free any variables. */
1962	STAMCOUNTER StatNativeRegFindFreeNoVar;
1963	/** Native recompiler: Liveness info freed shadowed guest registers in
1964	* iemNativeRegAllocFindFree. */
1965	STAMCOUNTER StatNativeRegFindFreeLivenessUnshadowed;
1966	/** Native recompiler: Liveness info helped with the allocation in
1967	* iemNativeRegAllocFindFree. */
1968	STAMCOUNTER StatNativeRegFindFreeLivenessHelped;
1969
1970	/** Native recompiler: Number of times status flags calc has been skipped. */
1971	STAMCOUNTER StatNativeEflSkippedArithmetic;
1972	/** Native recompiler: Number of times status flags calc has been skipped. */
1973	STAMCOUNTER StatNativeEflSkippedLogical;
1974
1975	/** Native recompiler: Number of opportunities to skip EFLAGS.CF updating. */
1976	STAMCOUNTER StatNativeLivenessEflCfSkippable;
1977	/** Native recompiler: Number of opportunities to skip EFLAGS.PF updating. */
1978	STAMCOUNTER StatNativeLivenessEflPfSkippable;
1979	/** Native recompiler: Number of opportunities to skip EFLAGS.AF updating. */
1980	STAMCOUNTER StatNativeLivenessEflAfSkippable;
1981	/** Native recompiler: Number of opportunities to skip EFLAGS.ZF updating. */
1982	STAMCOUNTER StatNativeLivenessEflZfSkippable;
1983	/** Native recompiler: Number of opportunities to skip EFLAGS.SF updating. */
1984	STAMCOUNTER StatNativeLivenessEflSfSkippable;
1985	/** Native recompiler: Number of opportunities to skip EFLAGS.OF updating. */
1986	STAMCOUNTER StatNativeLivenessEflOfSkippable;
1987	/** Native recompiler: Number of required EFLAGS.CF updates. */
1988	STAMCOUNTER StatNativeLivenessEflCfRequired;
1989	/** Native recompiler: Number of required EFLAGS.PF updates. */
1990	STAMCOUNTER StatNativeLivenessEflPfRequired;
1991	/** Native recompiler: Number of required EFLAGS.AF updates. */
1992	STAMCOUNTER StatNativeLivenessEflAfRequired;
1993	/** Native recompiler: Number of required EFLAGS.ZF updates. */
1994	STAMCOUNTER StatNativeLivenessEflZfRequired;
1995	/** Native recompiler: Number of required EFLAGS.SF updates. */
1996	STAMCOUNTER StatNativeLivenessEflSfRequired;
1997	/** Native recompiler: Number of required EFLAGS.OF updates. */
1998	STAMCOUNTER StatNativeLivenessEflOfRequired;
1999	/** Native recompiler: Number of potentially delayable EFLAGS.CF updates. */
2000	STAMCOUNTER StatNativeLivenessEflCfDelayable;
2001	/** Native recompiler: Number of potentially delayable EFLAGS.PF updates. */
2002	STAMCOUNTER StatNativeLivenessEflPfDelayable;
2003	/** Native recompiler: Number of potentially delayable EFLAGS.AF updates. */
2004	STAMCOUNTER StatNativeLivenessEflAfDelayable;
2005	/** Native recompiler: Number of potentially delayable EFLAGS.ZF updates. */
2006	STAMCOUNTER StatNativeLivenessEflZfDelayable;
2007	/** Native recompiler: Number of potentially delayable EFLAGS.SF updates. */
2008	STAMCOUNTER StatNativeLivenessEflSfDelayable;
2009	/** Native recompiler: Number of potentially delayable EFLAGS.OF updates. */
2010	STAMCOUNTER StatNativeLivenessEflOfDelayable;
2011
2012	/** Native recompiler: Number of potential PC updates in total. */
2013	STAMCOUNTER StatNativePcUpdateTotal;
2014	/** Native recompiler: Number of PC updates which could be delayed. */
2015	STAMCOUNTER StatNativePcUpdateDelayed;
2016
2017	//#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
2018	/** Native recompiler: Number of calls to iemNativeSimdRegAllocFindFree. */
2019	STAMCOUNTER StatNativeSimdRegFindFree;
2020	/** Native recompiler: Number of times iemNativeSimdRegAllocFindFree needed
2021	* to free a variable. */
2022	STAMCOUNTER StatNativeSimdRegFindFreeVar;
2023	/** Native recompiler: Number of times iemNativeSimdRegAllocFindFree did
2024	* not need to free any variables. */
2025	STAMCOUNTER StatNativeSimdRegFindFreeNoVar;
2026	/** Native recompiler: Liveness info freed shadowed guest registers in
2027	* iemNativeSimdRegAllocFindFree. */
2028	STAMCOUNTER StatNativeSimdRegFindFreeLivenessUnshadowed;
2029	/** Native recompiler: Liveness info helped with the allocation in
2030	* iemNativeSimdRegAllocFindFree. */
2031	STAMCOUNTER StatNativeSimdRegFindFreeLivenessHelped;
2032
2033	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() checks. */
2034	STAMCOUNTER StatNativeMaybeDeviceNotAvailXcptCheckPotential;
2035	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() checks. */
2036	STAMCOUNTER StatNativeMaybeWaitDeviceNotAvailXcptCheckPotential;
2037	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() checks. */
2038	STAMCOUNTER StatNativeMaybeSseXcptCheckPotential;
2039	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() checks. */
2040	STAMCOUNTER StatNativeMaybeAvxXcptCheckPotential;
2041
2042	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() checks omitted. */
2043	STAMCOUNTER StatNativeMaybeDeviceNotAvailXcptCheckOmitted;
2044	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() checks omitted. */
2045	STAMCOUNTER StatNativeMaybeWaitDeviceNotAvailXcptCheckOmitted;
2046	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() checks omitted. */
2047	STAMCOUNTER StatNativeMaybeSseXcptCheckOmitted;
2048	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() checks omitted. */
2049	STAMCOUNTER StatNativeMaybeAvxXcptCheckOmitted;
2050	//#endif
2051
2052	/** Native recompiler: The TB finished executing completely without jumping to a an exit label. */
2053	STAMCOUNTER StatNativeTbFinished;
2054	/** Native recompiler: The TB finished executing jumping to the ReturnBreak label. */
2055	STAMCOUNTER StatNativeTbExitReturnBreak;
2056	/** Native recompiler: The TB finished executing jumping to the ReturnWithFlags label. */
2057	STAMCOUNTER StatNativeTbExitReturnWithFlags;
2058
2059	/** Native recompiler: The TB finished executing jumping to the RaiseDe label. */
2060	STAMCOUNTER StatNativeTbExitRaiseDe;
2061	/** Native recompiler: The TB finished executing jumping to the RaiseUd label. */
2062	STAMCOUNTER StatNativeTbExitRaiseUd;
2063	/** Native recompiler: The TB finished executing jumping to the RaiseSseRelated label. */
2064	STAMCOUNTER StatNativeTbExitRaiseSseRelated;
2065	/** Native recompiler: The TB finished executing jumping to the RaiseAvxRelated label. */
2066	STAMCOUNTER StatNativeTbExitRaiseAvxRelated;
2067	/** Native recompiler: The TB finished executing jumping to the RaiseSseAvxFpRelated label. */
2068	STAMCOUNTER StatNativeTbExitRaiseSseAvxFpRelated;
2069	/** Native recompiler: The TB finished executing jumping to the RaiseNm label. */
2070	STAMCOUNTER StatNativeTbExitRaiseNm;
2071	/** Native recompiler: The TB finished executing jumping to the RaiseGp0 label. */
2072	STAMCOUNTER StatNativeTbExitRaiseGp0;
2073	/** Native recompiler: The TB finished executing jumping to the RaiseMf label. */
2074	STAMCOUNTER StatNativeTbExitRaiseMf;
2075	/** Native recompiler: The TB finished executing jumping to the RaiseXf label. */
2076	STAMCOUNTER StatNativeTbExitRaiseXf;
2077	/** Native recompiler: The TB finished executing jumping to the ObsoleteTb label. */
2078	STAMCOUNTER StatNativeTbExitObsoleteTb;
2079
2080	uint64_t au64Padding[4];
2081	/** @} */
2082
2083	/** Data TLB.
2084	* @remarks Must be 64-byte aligned. */
2085	IEMTLB DataTlb;
2086	/** Instruction TLB.
2087	* @remarks Must be 64-byte aligned. */
2088	IEMTLB CodeTlb;
2089
2090	/** Exception statistics. */
2091	STAMCOUNTER aStatXcpts[32];
2092	/** Interrupt statistics. */
2093	uint32_t aStatInts[256];
2094
2095	#if defined(VBOX_WITH_STATISTICS) && !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
2096	/** Instruction statistics for ring-0/raw-mode. */
2097	IEMINSTRSTATS StatsRZ;
2098	/** Instruction statistics for ring-3. */
2099	IEMINSTRSTATS StatsR3;
2100	# ifdef VBOX_WITH_IEM_RECOMPILER
2101	/** Statistics per threaded function call.
2102	* Updated by both the threaded and native recompilers. */
2103	uint32_t acThreadedFuncStats[0x6000 /24576/];
2104	# endif
2105	#endif
2106	} IEMCPU;
2107	AssertCompileMemberOffset(IEMCPU, cActiveMappings, 0x4f);
2108	AssertCompileMemberAlignment(IEMCPU, aMemMappings, 16);
2109	AssertCompileMemberAlignment(IEMCPU, aMemMappingLocks, 16);
2110	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 64);
2111	AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
2112	AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
2113
2114	/** Pointer to the per-CPU IEM state. */
2115	typedef IEMCPU *PIEMCPU;
2116	/** Pointer to the const per-CPU IEM state. */
2117	typedef IEMCPU const *PCIEMCPU;
2118
2119
2120	/** @def IEM_GET_CTX
2121	* Gets the guest CPU context for the calling EMT.
2122	* @returns PCPUMCTX
2123	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2124	*/
2125	#define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
2126
2127	/** @def IEM_CTX_ASSERT
2128	* Asserts that the @a a_fExtrnMbz is present in the CPU context.
2129	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2130	* @param a_fExtrnMbz The mask of CPUMCTX_EXTRN_XXX flags that must be zero.
2131	*/
2132	#define IEM_CTX_ASSERT(a_pVCpu, a_fExtrnMbz) \
2133	AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
2134	("fExtrn=%#RX64 & fExtrnMbz=%#RX64 -> %#RX64\n", \
2135	(a_pVCpu)->cpum.GstCtx.fExtrn, (a_fExtrnMbz), (a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz) ))
2136
2137	/** @def IEM_CTX_IMPORT_RET
2138	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
2139	*
2140	* Will call the keep to import the bits as needed.
2141	*
2142	* Returns on import failure.
2143	*
2144	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2145	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
2146	*/
2147	#define IEM_CTX_IMPORT_RET(a_pVCpu, a_fExtrnImport) \
2148	do { \
2149	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
2150	{ /* likely */ } \
2151	else \
2152	{ \
2153	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
2154	AssertRCReturn(rcCtxImport, rcCtxImport); \
2155	} \
2156	} while (0)
2157
2158	/** @def IEM_CTX_IMPORT_NORET
2159	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
2160	*
2161	* Will call the keep to import the bits as needed.
2162	*
2163	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2164	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
2165	*/
2166	#define IEM_CTX_IMPORT_NORET(a_pVCpu, a_fExtrnImport) \
2167	do { \
2168	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
2169	{ /* likely */ } \
2170	else \
2171	{ \
2172	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
2173	AssertLogRelRC(rcCtxImport); \
2174	} \
2175	} while (0)
2176
2177	/** @def IEM_CTX_IMPORT_JMP
2178	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
2179	*
2180	* Will call the keep to import the bits as needed.
2181	*
2182	* Jumps on import failure.
2183	*
2184	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2185	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
2186	*/
2187	#define IEM_CTX_IMPORT_JMP(a_pVCpu, a_fExtrnImport) \
2188	do { \
2189	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
2190	{ /* likely */ } \
2191	else \
2192	{ \
2193	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
2194	AssertRCStmt(rcCtxImport, IEM_DO_LONGJMP(pVCpu, rcCtxImport)); \
2195	} \
2196	} while (0)
2197
2198
2199
2200	/** @def IEM_GET_TARGET_CPU
2201	* Gets the current IEMTARGETCPU value.
2202	* @returns IEMTARGETCPU value.
2203	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2204	*/
2205	#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
2206	# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
2207	#else
2208	# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
2209	#endif
2210
2211	/** @def IEM_GET_INSTR_LEN
2212	* Gets the instruction length. */
2213	#ifdef IEM_WITH_CODE_TLB
2214	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
2215	#else
2216	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
2217	#endif
2218
2219	/** @def IEM_TRY_SETJMP
2220	* Wrapper around setjmp / try, hiding all the ugly differences.
2221	*
2222	* @note Use with extreme care as this is a fragile macro.
2223	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2224	* @param a_rcTarget The variable that should receive the status code in case
2225	* of a longjmp/throw.
2226	*/
2227	/** @def IEM_TRY_SETJMP_AGAIN
2228	* For when setjmp / try is used again in the same variable scope as a previous
2229	* IEM_TRY_SETJMP invocation.
2230	*/
2231	/** @def IEM_CATCH_LONGJMP_BEGIN
2232	* Start wrapper for catch / setjmp-else.
2233	*
2234	* This will set up a scope.
2235	*
2236	* @note Use with extreme care as this is a fragile macro.
2237	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2238	* @param a_rcTarget The variable that should receive the status code in case
2239	* of a longjmp/throw.
2240	*/
2241	/** @def IEM_CATCH_LONGJMP_END
2242	* End wrapper for catch / setjmp-else.
2243	*
2244	* This will close the scope set up by IEM_CATCH_LONGJMP_BEGIN and clean up the
2245	* state.
2246	*
2247	* @note Use with extreme care as this is a fragile macro.
2248	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2249	*/
2250	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
2251	# ifdef IEM_WITH_THROW_CATCH
2252	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
2253	a_rcTarget = VINF_SUCCESS; \
2254	try
2255	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
2256	IEM_TRY_SETJMP(a_pVCpu, a_rcTarget)
2257	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
2258	catch (int rcThrown) \
2259	{ \
2260	a_rcTarget = rcThrown
2261	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
2262	} \
2263	((void)0)
2264	# else /* !IEM_WITH_THROW_CATCH */
2265	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
2266	jmp_buf JmpBuf; \
2267	jmp_buf * volatile pSavedJmpBuf = (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf); \
2268	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
2269	if ((rcStrict = setjmp(JmpBuf)) == 0)
2270	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
2271	pSavedJmpBuf = (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf); \
2272	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
2273	if ((rcStrict = setjmp(JmpBuf)) == 0)
2274	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
2275	else \
2276	{ \
2277	((void)0)
2278	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
2279	} \
2280	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = pSavedJmpBuf
2281	# endif /* !IEM_WITH_THROW_CATCH */
2282	#endif /* IEM_WITH_SETJMP */
2283
2284
2285	/**
2286	* Shared per-VM IEM data.
2287	*/
2288	typedef struct IEM
2289	{
2290	/** The VMX APIC-access page handler type. */
2291	PGMPHYSHANDLERTYPE hVmxApicAccessPage;
2292	#ifndef VBOX_WITHOUT_CPUID_HOST_CALL
2293	/** Set if the CPUID host call functionality is enabled. */
2294	bool fCpuIdHostCall;
2295	#endif
2296	} IEM;
2297
2298
2299
2300	/** @name IEM_ACCESS_XXX - Access details.
2301	* @{ */
2302	#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
2303	#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
2304	#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
2305	#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
2306	#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
2307	#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
2308	#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
2309	#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
2310	#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
2311	#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
2312	/** The writes are partial, so if initialize the bounce buffer with the
2313	* orignal RAM content. */
2314	#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
2315	/** Used in aMemMappings to indicate that the entry is bounce buffered. */
2316	#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
2317	/** Bounce buffer with ring-3 write pending, first page. */
2318	#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
2319	/** Bounce buffer with ring-3 write pending, second page. */
2320	#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
2321	/** Not locked, accessed via the TLB. */
2322	#define IEM_ACCESS_NOT_LOCKED UINT32_C(0x00001000)
2323	/** Atomic access.
2324	* This enables special alignment checks and the VINF_EM_EMULATE_SPLIT_LOCK
2325	* fallback for misaligned stuff. See @bugref{10547}. */
2326	#define IEM_ACCESS_ATOMIC UINT32_C(0x00002000)
2327	/** Valid bit mask. */
2328	#define IEM_ACCESS_VALID_MASK UINT32_C(0x00003fff)
2329	/** Shift count for the TLB flags (upper word). */
2330	#define IEM_ACCESS_SHIFT_TLB_FLAGS 16
2331
2332	/** Atomic read+write data alias. */
2333	#define IEM_ACCESS_DATA_ATOMIC (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA \| IEM_ACCESS_ATOMIC)
2334	/** Read+write data alias. */
2335	#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
2336	/** Write data alias. */
2337	#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
2338	/** Read data alias. */
2339	#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_DATA)
2340	/** Instruction fetch alias. */
2341	#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_WHAT_CODE)
2342	/** Stack write alias. */
2343	#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
2344	/** Stack read alias. */
2345	#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_STACK)
2346	/** Stack read+write alias. */
2347	#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
2348	/** Read system table alias. */
2349	#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_SYS)
2350	/** Read+write system table alias. */
2351	#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_SYS)
2352	/** @} */
2353
2354	/** @name Prefix constants (IEMCPU::fPrefixes)
2355	* @{ */
2356	#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /*< CS segment prefix (0x2e). /
2357	#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /*< SS segment prefix (0x36). /
2358	#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /*< DS segment prefix (0x3e). /
2359	#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /*< ES segment prefix (0x26). /
2360	#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /*< FS segment prefix (0x64). /
2361	#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /*< GS segment prefix (0x65). /
2362	#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
2363
2364	#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /*< Operand size prefix (0x66). /
2365	#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /*< REX.W prefix (0x48-0x4f). /
2366	#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /*< Address size prefix (0x67). /
2367
2368	#define IEM_OP_PRF_LOCK RT_BIT_32(16) /*< Lock prefix (0xf0). /
2369	#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /*< Repeat-not-zero prefix (0xf2). /
2370	#define IEM_OP_PRF_REPZ RT_BIT_32(18) /*< Repeat-if-zero prefix (0xf3). /
2371
2372	#define IEM_OP_PRF_REX RT_BIT_32(24) /*< Any REX prefix (0x40-0x4f). /
2373	#define IEM_OP_PRF_REX_B RT_BIT_32(25) /*< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). /
2374	#define IEM_OP_PRF_REX_X RT_BIT_32(26) /*< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). /
2375	#define IEM_OP_PRF_REX_R RT_BIT_32(27) /*< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). /
2376	/** Mask with all the REX prefix flags.
2377	* This is generally for use when needing to undo the REX prefixes when they
2378	* are followed legacy prefixes and therefore does not immediately preceed
2379	* the first opcode byte.
2380	* For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
2381	#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX \| IEM_OP_PRF_REX_R \| IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X \| IEM_OP_PRF_SIZE_REX_W )
2382
2383	#define IEM_OP_PRF_VEX RT_BIT_32(28) /*< Indiciates VEX prefix. /
2384	#define IEM_OP_PRF_EVEX RT_BIT_32(29) /*< Indiciates EVEX prefix. /
2385	#define IEM_OP_PRF_XOP RT_BIT_32(30) /*< Indiciates XOP prefix. /
2386	/** @} */
2387
2388	/** @name IEMOPFORM_XXX - Opcode forms
2389	* @note These are ORed together with IEMOPHINT_XXX.
2390	* @{ */
2391	/** ModR/M: reg, r/m */
2392	#define IEMOPFORM_RM 0
2393	/** ModR/M: reg, r/m (register) */
2394	#define IEMOPFORM_RM_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
2395	/** ModR/M: reg, r/m (memory) */
2396	#define IEMOPFORM_RM_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
2397	/** ModR/M: reg, r/m, imm */
2398	#define IEMOPFORM_RMI 1
2399	/** ModR/M: reg, r/m (register), imm */
2400	#define IEMOPFORM_RMI_REG (IEMOPFORM_RMI \| IEMOPFORM_MOD3)
2401	/** ModR/M: reg, r/m (memory), imm */
2402	#define IEMOPFORM_RMI_MEM (IEMOPFORM_RMI \| IEMOPFORM_NOT_MOD3)
2403	/** ModR/M: reg, r/m, xmm0 */
2404	#define IEMOPFORM_RM0 2
2405	/** ModR/M: reg, r/m (register), xmm0 */
2406	#define IEMOPFORM_RM0_REG (IEMOPFORM_RM0 \| IEMOPFORM_MOD3)
2407	/** ModR/M: reg, r/m (memory), xmm0 */
2408	#define IEMOPFORM_RM0_MEM (IEMOPFORM_RM0 \| IEMOPFORM_NOT_MOD3)
2409	/** ModR/M: r/m, reg */
2410	#define IEMOPFORM_MR 3
2411	/** ModR/M: r/m (register), reg */
2412	#define IEMOPFORM_MR_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
2413	/** ModR/M: r/m (memory), reg */
2414	#define IEMOPFORM_MR_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
2415	/** ModR/M: r/m, reg, imm */
2416	#define IEMOPFORM_MRI 4
2417	/** ModR/M: r/m (register), reg, imm */
2418	#define IEMOPFORM_MRI_REG (IEMOPFORM_MRI \| IEMOPFORM_MOD3)
2419	/** ModR/M: r/m (memory), reg, imm */
2420	#define IEMOPFORM_MRI_MEM (IEMOPFORM_MRI \| IEMOPFORM_NOT_MOD3)
2421	/** ModR/M: r/m only */
2422	#define IEMOPFORM_M 5
2423	/** ModR/M: r/m only (register). */
2424	#define IEMOPFORM_M_REG (IEMOPFORM_M \| IEMOPFORM_MOD3)
2425	/** ModR/M: r/m only (memory). */
2426	#define IEMOPFORM_M_MEM (IEMOPFORM_M \| IEMOPFORM_NOT_MOD3)
2427	/** ModR/M: r/m, imm */
2428	#define IEMOPFORM_MI 6
2429	/** ModR/M: r/m (register), imm */
2430	#define IEMOPFORM_MI_REG (IEMOPFORM_MI \| IEMOPFORM_MOD3)
2431	/** ModR/M: r/m (memory), imm */
2432	#define IEMOPFORM_MI_MEM (IEMOPFORM_MI \| IEMOPFORM_NOT_MOD3)
2433	/** ModR/M: r/m, 1 (shift and rotate instructions) */
2434	#define IEMOPFORM_M1 7
2435	/** ModR/M: r/m (register), 1. */
2436	#define IEMOPFORM_M1_REG (IEMOPFORM_M1 \| IEMOPFORM_MOD3)
2437	/** ModR/M: r/m (memory), 1. */
2438	#define IEMOPFORM_M1_MEM (IEMOPFORM_M1 \| IEMOPFORM_NOT_MOD3)
2439	/** ModR/M: r/m, CL (shift and rotate instructions)
2440	* @todo This should just've been a generic fixed register. But the python
2441	* code doesn't needs more convincing. */
2442	#define IEMOPFORM_M_CL 8
2443	/** ModR/M: r/m (register), CL. */
2444	#define IEMOPFORM_M_CL_REG (IEMOPFORM_M_CL \| IEMOPFORM_MOD3)
2445	/** ModR/M: r/m (memory), CL. */
2446	#define IEMOPFORM_M_CL_MEM (IEMOPFORM_M_CL \| IEMOPFORM_NOT_MOD3)
2447	/** ModR/M: reg only */
2448	#define IEMOPFORM_R 9
2449
2450	/** VEX+ModR/M: reg, r/m */
2451	#define IEMOPFORM_VEX_RM 16
2452	/** VEX+ModR/M: reg, r/m (register) */
2453	#define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM \| IEMOPFORM_MOD3)
2454	/** VEX+ModR/M: reg, r/m (memory) */
2455	#define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM \| IEMOPFORM_NOT_MOD3)
2456	/** VEX+ModR/M: r/m, reg */
2457	#define IEMOPFORM_VEX_MR 17
2458	/** VEX+ModR/M: r/m (register), reg */
2459	#define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR \| IEMOPFORM_MOD3)
2460	/** VEX+ModR/M: r/m (memory), reg */
2461	#define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR \| IEMOPFORM_NOT_MOD3)
2462	/** VEX+ModR/M: r/m, reg, imm8 */
2463	#define IEMOPFORM_VEX_MRI 18
2464	/** VEX+ModR/M: r/m (register), reg, imm8 */
2465	#define IEMOPFORM_VEX_MRI_REG (IEMOPFORM_VEX_MRI \| IEMOPFORM_MOD3)
2466	/** VEX+ModR/M: r/m (memory), reg, imm8 */
2467	#define IEMOPFORM_VEX_MRI_MEM (IEMOPFORM_VEX_MRI \| IEMOPFORM_NOT_MOD3)
2468	/** VEX+ModR/M: r/m only */
2469	#define IEMOPFORM_VEX_M 19
2470	/** VEX+ModR/M: r/m only (register). */
2471	#define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M \| IEMOPFORM_MOD3)
2472	/** VEX+ModR/M: r/m only (memory). */
2473	#define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M \| IEMOPFORM_NOT_MOD3)
2474	/** VEX+ModR/M: reg only */
2475	#define IEMOPFORM_VEX_R 20
2476	/** VEX+ModR/M: reg, vvvv, r/m */
2477	#define IEMOPFORM_VEX_RVM 21
2478	/** VEX+ModR/M: reg, vvvv, r/m (register). */
2479	#define IEMOPFORM_VEX_RVM_REG (IEMOPFORM_VEX_RVM \| IEMOPFORM_MOD3)
2480	/** VEX+ModR/M: reg, vvvv, r/m (memory). */
2481	#define IEMOPFORM_VEX_RVM_MEM (IEMOPFORM_VEX_RVM \| IEMOPFORM_NOT_MOD3)
2482	/** VEX+ModR/M: reg, vvvv, r/m, imm */
2483	#define IEMOPFORM_VEX_RVMI 22
2484	/** VEX+ModR/M: reg, vvvv, r/m (register), imm. */
2485	#define IEMOPFORM_VEX_RVMI_REG (IEMOPFORM_VEX_RVMI \| IEMOPFORM_MOD3)
2486	/** VEX+ModR/M: reg, vvvv, r/m (memory), imm. */
2487	#define IEMOPFORM_VEX_RVMI_MEM (IEMOPFORM_VEX_RVMI \| IEMOPFORM_NOT_MOD3)
2488	/** VEX+ModR/M: reg, vvvv, r/m, imm(reg) */
2489	#define IEMOPFORM_VEX_RVMR 23
2490	/** VEX+ModR/M: reg, vvvv, r/m (register), imm(reg). */
2491	#define IEMOPFORM_VEX_RVMR_REG (IEMOPFORM_VEX_RVMI \| IEMOPFORM_MOD3)
2492	/** VEX+ModR/M: reg, vvvv, r/m (memory), imm(reg). */
2493	#define IEMOPFORM_VEX_RVMR_MEM (IEMOPFORM_VEX_RVMI \| IEMOPFORM_NOT_MOD3)
2494	/** VEX+ModR/M: reg, r/m, vvvv */
2495	#define IEMOPFORM_VEX_RMV 24
2496	/** VEX+ModR/M: reg, r/m, vvvv (register). */
2497	#define IEMOPFORM_VEX_RMV_REG (IEMOPFORM_VEX_RMV \| IEMOPFORM_MOD3)
2498	/** VEX+ModR/M: reg, r/m, vvvv (memory). */
2499	#define IEMOPFORM_VEX_RMV_MEM (IEMOPFORM_VEX_RMV \| IEMOPFORM_NOT_MOD3)
2500	/** VEX+ModR/M: reg, r/m, imm8 */
2501	#define IEMOPFORM_VEX_RMI 25
2502	/** VEX+ModR/M: reg, r/m, imm8 (register). */
2503	#define IEMOPFORM_VEX_RMI_REG (IEMOPFORM_VEX_RMI \| IEMOPFORM_MOD3)
2504	/** VEX+ModR/M: reg, r/m, imm8 (memory). */
2505	#define IEMOPFORM_VEX_RMI_MEM (IEMOPFORM_VEX_RMI \| IEMOPFORM_NOT_MOD3)
2506	/** VEX+ModR/M: r/m, vvvv, reg */
2507	#define IEMOPFORM_VEX_MVR 26
2508	/** VEX+ModR/M: r/m, vvvv, reg (register) */
2509	#define IEMOPFORM_VEX_MVR_REG (IEMOPFORM_VEX_MVR \| IEMOPFORM_MOD3)
2510	/** VEX+ModR/M: r/m, vvvv, reg (memory) */
2511	#define IEMOPFORM_VEX_MVR_MEM (IEMOPFORM_VEX_MVR \| IEMOPFORM_NOT_MOD3)
2512	/** VEX+ModR/M+/n: vvvv, r/m */
2513	#define IEMOPFORM_VEX_VM 27
2514	/** VEX+ModR/M+/n: vvvv, r/m (register) */
2515	#define IEMOPFORM_VEX_VM_REG (IEMOPFORM_VEX_VM \| IEMOPFORM_MOD3)
2516	/** VEX+ModR/M+/n: vvvv, r/m (memory) */
2517	#define IEMOPFORM_VEX_VM_MEM (IEMOPFORM_VEX_VM \| IEMOPFORM_NOT_MOD3)
2518	/** VEX+ModR/M+/n: vvvv, r/m, imm8 */
2519	#define IEMOPFORM_VEX_VMI 28
2520	/** VEX+ModR/M+/n: vvvv, r/m, imm8 (register) */
2521	#define IEMOPFORM_VEX_VMI_REG (IEMOPFORM_VEX_VMI \| IEMOPFORM_MOD3)
2522	/** VEX+ModR/M+/n: vvvv, r/m, imm8 (memory) */
2523	#define IEMOPFORM_VEX_VMI_MEM (IEMOPFORM_VEX_VMI \| IEMOPFORM_NOT_MOD3)
2524
2525	/** Fixed register instruction, no R/M. */
2526	#define IEMOPFORM_FIXED 32
2527
2528	/** The r/m is a register. */
2529	#define IEMOPFORM_MOD3 RT_BIT_32(8)
2530	/** The r/m is a memory access. */
2531	#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
2532	/** @} */
2533
2534	/** @name IEMOPHINT_XXX - Additional Opcode Hints
2535	* @note These are ORed together with IEMOPFORM_XXX.
2536	* @{ */
2537	/** Ignores the operand size prefix (66h). */
2538	#define IEMOPHINT_IGNORES_OZ_PFX RT_BIT_32(10)
2539	/** Ignores REX.W (aka WIG). */
2540	#define IEMOPHINT_IGNORES_REXW RT_BIT_32(11)
2541	/** Both the operand size prefixes (66h + REX.W) are ignored. */
2542	#define IEMOPHINT_IGNORES_OP_SIZES (IEMOPHINT_IGNORES_OZ_PFX \| IEMOPHINT_IGNORES_REXW)
2543	/** Allowed with the lock prefix. */
2544	#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
2545	/** The VEX.L value is ignored (aka LIG). */
2546	#define IEMOPHINT_VEX_L_IGNORED RT_BIT_32(12)
2547	/** The VEX.L value must be zero (i.e. 128-bit width only). */
2548	#define IEMOPHINT_VEX_L_ZERO RT_BIT_32(13)
2549	/** The VEX.L value must be one (i.e. 256-bit width only). */
2550	#define IEMOPHINT_VEX_L_ONE RT_BIT_32(14)
2551	/** The VEX.V value must be zero. */
2552	#define IEMOPHINT_VEX_V_ZERO RT_BIT_32(15)
2553	/** The REX.W/VEX.V value must be zero. */
2554	#define IEMOPHINT_REX_W_ZERO RT_BIT_32(16)
2555	#define IEMOPHINT_VEX_W_ZERO IEMOPHINT_REX_W_ZERO
2556	/** The REX.W/VEX.V value must be one. */
2557	#define IEMOPHINT_REX_W_ONE RT_BIT_32(17)
2558	#define IEMOPHINT_VEX_W_ONE IEMOPHINT_REX_W_ONE
2559
2560	/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
2561	#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
2562	/** @} */
2563
2564	/**
2565	* Possible hardware task switch sources.
2566	*/
2567	typedef enum IEMTASKSWITCH
2568	{
2569	/** Task switch caused by an interrupt/exception. */
2570	IEMTASKSWITCH_INT_XCPT = 1,
2571	/** Task switch caused by a far CALL. */
2572	IEMTASKSWITCH_CALL,
2573	/** Task switch caused by a far JMP. */
2574	IEMTASKSWITCH_JUMP,
2575	/** Task switch caused by an IRET. */
2576	IEMTASKSWITCH_IRET
2577	} IEMTASKSWITCH;
2578	AssertCompileSize(IEMTASKSWITCH, 4);
2579
2580	/**
2581	* Possible CrX load (write) sources.
2582	*/
2583	typedef enum IEMACCESSCRX
2584	{
2585	/** CrX access caused by 'mov crX' instruction. */
2586	IEMACCESSCRX_MOV_CRX,
2587	/** CrX (CR0) write caused by 'lmsw' instruction. */
2588	IEMACCESSCRX_LMSW,
2589	/** CrX (CR0) write caused by 'clts' instruction. */
2590	IEMACCESSCRX_CLTS,
2591	/** CrX (CR0) read caused by 'smsw' instruction. */
2592	IEMACCESSCRX_SMSW
2593	} IEMACCESSCRX;
2594
2595	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2596	/** @name IEM_SLAT_FAIL_XXX - Second-level address translation failure information.
2597	*
2598	* These flags provide further context to SLAT page-walk failures that could not be
2599	* determined by PGM (e.g, PGM is not privy to memory access permissions).
2600	*
2601	* @{
2602	*/
2603	/** Translating a nested-guest linear address failed accessing a nested-guest
2604	* physical address. */
2605	# define IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR RT_BIT_32(0)
2606	/** Translating a nested-guest linear address failed accessing a
2607	* paging-structure entry or updating accessed/dirty bits. */
2608	# define IEM_SLAT_FAIL_LINEAR_TO_PAGE_TABLE RT_BIT_32(1)
2609	/** @} */
2610
2611	DECLCALLBACK(FNPGMPHYSHANDLER) iemVmxApicAccessPageHandler;
2612	# ifndef IN_RING3
2613	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) iemVmxApicAccessPagePfHandler;
2614	# endif
2615	#endif
2616
2617	/**
2618	* Indicates to the verifier that the given flag set is undefined.
2619	*
2620	* Can be invoked again to add more flags.
2621	*
2622	* This is a NOOP if the verifier isn't compiled in.
2623	*
2624	* @note We're temporarily keeping this until code is converted to new
2625	* disassembler style opcode handling.
2626	*/
2627	#define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
2628
2629
2630	/** @def IEM_DECL_IMPL_TYPE
2631	* For typedef'ing an instruction implementation function.
2632	*
2633	* @param a_RetType The return type.
2634	* @param a_Name The name of the type.
2635	* @param a_ArgList The argument list enclosed in parentheses.
2636	*/
2637
2638	/** @def IEM_DECL_IMPL_DEF
2639	* For defining an instruction implementation function.
2640	*
2641	* @param a_RetType The return type.
2642	* @param a_Name The name of the type.
2643	* @param a_ArgList The argument list enclosed in parentheses.
2644	*/
2645
2646	#if defined(__GNUC__) && defined(RT_ARCH_X86)
2647	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2648	__attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
2649	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2650	__attribute__((__fastcall__, __nothrow__)) DECL_HIDDEN_ONLY(a_RetType) a_Name a_ArgList
2651	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2652	__attribute__((__fastcall__, __nothrow__)) DECL_HIDDEN_ONLY(a_RetType) a_Name a_ArgList
2653
2654	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
2655	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2656	a_RetType (__fastcall a_Name) a_ArgList
2657	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2658	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
2659	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2660	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
2661
2662	#elif __cplusplus >= 201700 /* P0012R1 support */
2663	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2664	a_RetType (VBOXCALL a_Name) a_ArgList RT_NOEXCEPT
2665	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2666	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList RT_NOEXCEPT
2667	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2668	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList RT_NOEXCEPT
2669
2670	#else
2671	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2672	a_RetType (VBOXCALL a_Name) a_ArgList
2673	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2674	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList
2675	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2676	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList
2677
2678	#endif
2679
2680	/** Defined in IEMAllAImplC.cpp but also used by IEMAllAImplA.asm. */
2681	RT_C_DECLS_BEGIN
2682	extern uint8_t const g_afParity[256];
2683	RT_C_DECLS_END
2684
2685
2686	/** @name Arithmetic assignment operations on bytes (binary).
2687	* @{ */
2688	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU8, (uint32_t fEFlagsIn, uint8_t *pu8Dst, uint8_t u8Src));
2689	typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
2690	FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
2691	FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
2692	FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
2693	FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
2694	FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
2695	FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
2696	FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
2697	/** @} */
2698
2699	/** @name Arithmetic assignment operations on words (binary).
2700	* @{ */
2701	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU16, (uint32_t fEFlagsIn, uint16_t *pu16Dst, uint16_t u16Src));
2702	typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
2703	FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
2704	FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
2705	FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
2706	FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
2707	FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
2708	FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
2709	FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
2710	/** @} */
2711
2712
2713	/** @name Arithmetic assignment operations on double words (binary).
2714	* @{ */
2715	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU32, (uint32_t fEFlagsIn, uint32_t *pu32Dst, uint32_t u32Src));
2716	typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
2717	FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
2718	FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
2719	FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
2720	FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
2721	FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
2722	FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
2723	FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
2724	FNIEMAIMPLBINU32 iemAImpl_blsi_u32, iemAImpl_blsi_u32_fallback;
2725	FNIEMAIMPLBINU32 iemAImpl_blsr_u32, iemAImpl_blsr_u32_fallback;
2726	FNIEMAIMPLBINU32 iemAImpl_blsmsk_u32, iemAImpl_blsmsk_u32_fallback;
2727	/** @} */
2728
2729	/** @name Arithmetic assignment operations on quad words (binary).
2730	* @{ */
2731	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU64, (uint32_t fEFlagsIn, uint64_t *pu64Dst, uint64_t u64Src));
2732	typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
2733	FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
2734	FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
2735	FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
2736	FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
2737	FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
2738	FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
2739	FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
2740	FNIEMAIMPLBINU64 iemAImpl_blsi_u64, iemAImpl_blsi_u64_fallback;
2741	FNIEMAIMPLBINU64 iemAImpl_blsr_u64, iemAImpl_blsr_u64_fallback;
2742	FNIEMAIMPLBINU64 iemAImpl_blsmsk_u64, iemAImpl_blsmsk_u64_fallback;
2743	/** @} */
2744
2745	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU8, (uint32_t fEFlagsIn, uint8_t const *pu8Dst, uint8_t u8Src));
2746	typedef FNIEMAIMPLBINROU8 *PFNIEMAIMPLBINROU8;
2747	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU16,(uint32_t fEFlagsIn, uint16_t const *pu16Dst, uint16_t u16Src));
2748	typedef FNIEMAIMPLBINROU16 *PFNIEMAIMPLBINROU16;
2749	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU32,(uint32_t fEFlagsIn, uint32_t const *pu32Dst, uint32_t u32Src));
2750	typedef FNIEMAIMPLBINROU32 *PFNIEMAIMPLBINROU32;
2751	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU64,(uint32_t fEFlagsIn, uint64_t const *pu64Dst, uint64_t u64Src));
2752	typedef FNIEMAIMPLBINROU64 *PFNIEMAIMPLBINROU64;
2753
2754	/** @name Compare operations (thrown in with the binary ops).
2755	* @{ */
2756	FNIEMAIMPLBINROU8 iemAImpl_cmp_u8;
2757	FNIEMAIMPLBINROU16 iemAImpl_cmp_u16;
2758	FNIEMAIMPLBINROU32 iemAImpl_cmp_u32;
2759	FNIEMAIMPLBINROU64 iemAImpl_cmp_u64;
2760	/** @} */
2761
2762	/** @name Test operations (thrown in with the binary ops).
2763	* @{ */
2764	FNIEMAIMPLBINROU8 iemAImpl_test_u8;
2765	FNIEMAIMPLBINROU16 iemAImpl_test_u16;
2766	FNIEMAIMPLBINROU32 iemAImpl_test_u32;
2767	FNIEMAIMPLBINROU64 iemAImpl_test_u64;
2768	/** @} */
2769
2770	/** @name Bit operations operations (thrown in with the binary ops).
2771	* @{ */
2772	FNIEMAIMPLBINROU16 iemAImpl_bt_u16;
2773	FNIEMAIMPLBINROU32 iemAImpl_bt_u32;
2774	FNIEMAIMPLBINROU64 iemAImpl_bt_u64;
2775	FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
2776	FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
2777	FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
2778	FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
2779	FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
2780	FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
2781	FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
2782	FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
2783	FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
2784	/** @} */
2785
2786	/** @name Arithmetic three operand operations on double words (binary).
2787	* @{ */
2788	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32, (uint32_t pu32Dst, uint32_t u32Src1, uint32_t u32Src2, uint32_t pEFlags));
2789	typedef FNIEMAIMPLBINVEXU32 *PFNIEMAIMPLBINVEXU32;
2790	FNIEMAIMPLBINVEXU32 iemAImpl_andn_u32, iemAImpl_andn_u32_fallback;
2791	FNIEMAIMPLBINVEXU32 iemAImpl_bextr_u32, iemAImpl_bextr_u32_fallback;
2792	FNIEMAIMPLBINVEXU32 iemAImpl_bzhi_u32, iemAImpl_bzhi_u32_fallback;
2793	/** @} */
2794
2795	/** @name Arithmetic three operand operations on quad words (binary).
2796	* @{ */
2797	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64, (uint64_t pu64Dst, uint64_t u64Src1, uint64_t u64Src2, uint32_t pEFlags));
2798	typedef FNIEMAIMPLBINVEXU64 *PFNIEMAIMPLBINVEXU64;
2799	FNIEMAIMPLBINVEXU64 iemAImpl_andn_u64, iemAImpl_andn_u64_fallback;
2800	FNIEMAIMPLBINVEXU64 iemAImpl_bextr_u64, iemAImpl_bextr_u64_fallback;
2801	FNIEMAIMPLBINVEXU64 iemAImpl_bzhi_u64, iemAImpl_bzhi_u64_fallback;
2802	/** @} */
2803
2804	/** @name Arithmetic three operand operations on double words w/o EFLAGS (binary).
2805	* @{ */
2806	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32NOEFL, (uint32_t *pu32Dst, uint32_t u32Src1, uint32_t u32Src2));
2807	typedef FNIEMAIMPLBINVEXU32NOEFL *PFNIEMAIMPLBINVEXU32NOEFL;
2808	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pdep_u32, iemAImpl_pdep_u32_fallback;
2809	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pext_u32, iemAImpl_pext_u32_fallback;
2810	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_sarx_u32, iemAImpl_sarx_u32_fallback;
2811	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shlx_u32, iemAImpl_shlx_u32_fallback;
2812	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shrx_u32, iemAImpl_shrx_u32_fallback;
2813	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_rorx_u32;
2814	/** @} */
2815
2816	/** @name Arithmetic three operand operations on quad words w/o EFLAGS (binary).
2817	* @{ */
2818	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64NOEFL, (uint64_t *pu64Dst, uint64_t u64Src1, uint64_t u64Src2));
2819	typedef FNIEMAIMPLBINVEXU64NOEFL *PFNIEMAIMPLBINVEXU64NOEFL;
2820	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pdep_u64, iemAImpl_pdep_u64_fallback;
2821	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pext_u64, iemAImpl_pext_u64_fallback;
2822	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_sarx_u64, iemAImpl_sarx_u64_fallback;
2823	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shlx_u64, iemAImpl_shlx_u64_fallback;
2824	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shrx_u64, iemAImpl_shrx_u64_fallback;
2825	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_rorx_u64;
2826	/** @} */
2827
2828	/** @name MULX 32-bit and 64-bit.
2829	* @{ */
2830	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU32, (uint32_t puDst1, uint32_t puDst2, uint32_t uSrc1, uint32_t uSrc2));
2831	typedef FNIEMAIMPLMULXVEXU32 *PFNIEMAIMPLMULXVEXU32;
2832	FNIEMAIMPLMULXVEXU32 iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback;
2833
2834	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU64, (uint64_t puDst1, uint64_t puDst2, uint64_t uSrc1, uint64_t uSrc2));
2835	typedef FNIEMAIMPLMULXVEXU64 *PFNIEMAIMPLMULXVEXU64;
2836	FNIEMAIMPLMULXVEXU64 iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback;
2837	/** @} */
2838
2839
2840	/** @name Exchange memory with register operations.
2841	* @{ */
2842	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_locked, (uint8_t pu8Mem, uint8_t pu8Reg));
2843	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_locked,(uint16_t pu16Mem, uint16_t pu16Reg));
2844	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_locked,(uint32_t pu32Mem, uint32_t pu32Reg));
2845	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_locked,(uint64_t pu64Mem, uint64_t pu64Reg));
2846	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_unlocked, (uint8_t pu8Mem, uint8_t pu8Reg));
2847	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_unlocked,(uint16_t pu16Mem, uint16_t pu16Reg));
2848	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_unlocked,(uint32_t pu32Mem, uint32_t pu32Reg));
2849	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_unlocked,(uint64_t pu64Mem, uint64_t pu64Reg));
2850	/** @} */
2851
2852	/** @name Exchange and add operations.
2853	* @{ */
2854	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
2855	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
2856	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
2857	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
2858	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
2859	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
2860	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
2861	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
2862	/** @} */
2863
2864	/** @name Compare and exchange.
2865	* @{ */
2866	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
2867	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
2868	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
2869	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
2870	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
2871	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
2872	#if ARCH_BITS == 32
2873	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
2874	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
2875	#else
2876	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
2877	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
2878	#endif
2879	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
2880	uint32_t *pEFlags));
2881	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
2882	uint32_t *pEFlags));
2883	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
2884	uint32_t *pEFlags));
2885	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
2886	uint32_t *pEFlags));
2887	#ifndef RT_ARCH_ARM64
2888	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
2889	PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
2890	#endif
2891	/** @} */
2892
2893	/** @name Memory ordering
2894	* @{ */
2895	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
2896	typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
2897	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
2898	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
2899	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
2900	#ifndef RT_ARCH_ARM64
2901	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
2902	#endif
2903	/** @} */
2904
2905	/** @name Double precision shifts
2906	* @{ */
2907	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t pEFlags));
2908	typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
2909	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t pEFlags));
2910	typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
2911	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t pEFlags));
2912	typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
2913	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16, iemAImpl_shld_u16_amd, iemAImpl_shld_u16_intel;
2914	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32, iemAImpl_shld_u32_amd, iemAImpl_shld_u32_intel;
2915	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64, iemAImpl_shld_u64_amd, iemAImpl_shld_u64_intel;
2916	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16, iemAImpl_shrd_u16_amd, iemAImpl_shrd_u16_intel;
2917	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32, iemAImpl_shrd_u32_amd, iemAImpl_shrd_u32_intel;
2918	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64, iemAImpl_shrd_u64_amd, iemAImpl_shrd_u64_intel;
2919	/** @} */
2920
2921
2922	/** @name Bit search operations (thrown in with the binary ops).
2923	* @{ */
2924	FNIEMAIMPLBINU16 iemAImpl_bsf_u16, iemAImpl_bsf_u16_amd, iemAImpl_bsf_u16_intel;
2925	FNIEMAIMPLBINU32 iemAImpl_bsf_u32, iemAImpl_bsf_u32_amd, iemAImpl_bsf_u32_intel;
2926	FNIEMAIMPLBINU64 iemAImpl_bsf_u64, iemAImpl_bsf_u64_amd, iemAImpl_bsf_u64_intel;
2927	FNIEMAIMPLBINU16 iemAImpl_bsr_u16, iemAImpl_bsr_u16_amd, iemAImpl_bsr_u16_intel;
2928	FNIEMAIMPLBINU32 iemAImpl_bsr_u32, iemAImpl_bsr_u32_amd, iemAImpl_bsr_u32_intel;
2929	FNIEMAIMPLBINU64 iemAImpl_bsr_u64, iemAImpl_bsr_u64_amd, iemAImpl_bsr_u64_intel;
2930	FNIEMAIMPLBINU16 iemAImpl_lzcnt_u16, iemAImpl_lzcnt_u16_amd, iemAImpl_lzcnt_u16_intel;
2931	FNIEMAIMPLBINU32 iemAImpl_lzcnt_u32, iemAImpl_lzcnt_u32_amd, iemAImpl_lzcnt_u32_intel;
2932	FNIEMAIMPLBINU64 iemAImpl_lzcnt_u64, iemAImpl_lzcnt_u64_amd, iemAImpl_lzcnt_u64_intel;
2933	FNIEMAIMPLBINU16 iemAImpl_tzcnt_u16, iemAImpl_tzcnt_u16_amd, iemAImpl_tzcnt_u16_intel;
2934	FNIEMAIMPLBINU32 iemAImpl_tzcnt_u32, iemAImpl_tzcnt_u32_amd, iemAImpl_tzcnt_u32_intel;
2935	FNIEMAIMPLBINU64 iemAImpl_tzcnt_u64, iemAImpl_tzcnt_u64_amd, iemAImpl_tzcnt_u64_intel;
2936	FNIEMAIMPLBINU16 iemAImpl_popcnt_u16, iemAImpl_popcnt_u16_fallback;
2937	FNIEMAIMPLBINU32 iemAImpl_popcnt_u32, iemAImpl_popcnt_u32_fallback;
2938	FNIEMAIMPLBINU64 iemAImpl_popcnt_u64, iemAImpl_popcnt_u64_fallback;
2939	/** @} */
2940
2941	/** @name Signed multiplication operations (thrown in with the binary ops).
2942	* @{ */
2943	FNIEMAIMPLBINU16 iemAImpl_imul_two_u16, iemAImpl_imul_two_u16_amd, iemAImpl_imul_two_u16_intel;
2944	FNIEMAIMPLBINU32 iemAImpl_imul_two_u32, iemAImpl_imul_two_u32_amd, iemAImpl_imul_two_u32_intel;
2945	FNIEMAIMPLBINU64 iemAImpl_imul_two_u64, iemAImpl_imul_two_u64_amd, iemAImpl_imul_two_u64_intel;
2946	/** @} */
2947
2948	/** @name Arithmetic assignment operations on bytes (unary).
2949	* @{ */
2950	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t pu8Dst, uint32_t pEFlags));
2951	typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
2952	FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
2953	FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
2954	FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
2955	FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
2956	/** @} */
2957
2958	/** @name Arithmetic assignment operations on words (unary).
2959	* @{ */
2960	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t pu16Dst, uint32_t pEFlags));
2961	typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
2962	FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
2963	FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
2964	FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
2965	FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
2966	/** @} */
2967
2968	/** @name Arithmetic assignment operations on double words (unary).
2969	* @{ */
2970	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t pu32Dst, uint32_t pEFlags));
2971	typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
2972	FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
2973	FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
2974	FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
2975	FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
2976	/** @} */
2977
2978	/** @name Arithmetic assignment operations on quad words (unary).
2979	* @{ */
2980	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t pu64Dst, uint32_t pEFlags));
2981	typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
2982	FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
2983	FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
2984	FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
2985	FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
2986	/** @} */
2987
2988
2989	/** @name Shift operations on bytes (Group 2).
2990	* @{ */
2991	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU8,(uint32_t fEFlagsIn, uint8_t *pu8Dst, uint8_t cShift));
2992	typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
2993	FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8, iemAImpl_rol_u8_amd, iemAImpl_rol_u8_intel;
2994	FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8, iemAImpl_ror_u8_amd, iemAImpl_ror_u8_intel;
2995	FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8, iemAImpl_rcl_u8_amd, iemAImpl_rcl_u8_intel;
2996	FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8, iemAImpl_rcr_u8_amd, iemAImpl_rcr_u8_intel;
2997	FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8, iemAImpl_shl_u8_amd, iemAImpl_shl_u8_intel;
2998	FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8, iemAImpl_shr_u8_amd, iemAImpl_shr_u8_intel;
2999	FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8, iemAImpl_sar_u8_amd, iemAImpl_sar_u8_intel;
3000	/** @} */
3001
3002	/** @name Shift operations on words (Group 2).
3003	* @{ */
3004	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU16,(uint32_t fEFlagsIn, uint16_t *pu16Dst, uint8_t cShift));
3005	typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
3006	FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16, iemAImpl_rol_u16_amd, iemAImpl_rol_u16_intel;
3007	FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16, iemAImpl_ror_u16_amd, iemAImpl_ror_u16_intel;
3008	FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16, iemAImpl_rcl_u16_amd, iemAImpl_rcl_u16_intel;
3009	FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16, iemAImpl_rcr_u16_amd, iemAImpl_rcr_u16_intel;
3010	FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16, iemAImpl_shl_u16_amd, iemAImpl_shl_u16_intel;
3011	FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16, iemAImpl_shr_u16_amd, iemAImpl_shr_u16_intel;
3012	FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16, iemAImpl_sar_u16_amd, iemAImpl_sar_u16_intel;
3013	/** @} */
3014
3015	/** @name Shift operations on double words (Group 2).
3016	* @{ */
3017	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU32,(uint32_t fEFlagsIn, uint32_t *pu32Dst, uint8_t cShift));
3018	typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
3019	FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32, iemAImpl_rol_u32_amd, iemAImpl_rol_u32_intel;
3020	FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32, iemAImpl_ror_u32_amd, iemAImpl_ror_u32_intel;
3021	FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32, iemAImpl_rcl_u32_amd, iemAImpl_rcl_u32_intel;
3022	FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32, iemAImpl_rcr_u32_amd, iemAImpl_rcr_u32_intel;
3023	FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32, iemAImpl_shl_u32_amd, iemAImpl_shl_u32_intel;
3024	FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32, iemAImpl_shr_u32_amd, iemAImpl_shr_u32_intel;
3025	FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32, iemAImpl_sar_u32_amd, iemAImpl_sar_u32_intel;
3026	/** @} */
3027
3028	/** @name Shift operations on words (Group 2).
3029	* @{ */
3030	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU64,(uint32_t fEFlagsIn, uint64_t *pu64Dst, uint8_t cShift));
3031	typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
3032	FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64, iemAImpl_rol_u64_amd, iemAImpl_rol_u64_intel;
3033	FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64, iemAImpl_ror_u64_amd, iemAImpl_ror_u64_intel;
3034	FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64, iemAImpl_rcl_u64_amd, iemAImpl_rcl_u64_intel;
3035	FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64, iemAImpl_rcr_u64_amd, iemAImpl_rcr_u64_intel;
3036	FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64, iemAImpl_shl_u64_amd, iemAImpl_shl_u64_intel;
3037	FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64, iemAImpl_shr_u64_amd, iemAImpl_shr_u64_intel;
3038	FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64, iemAImpl_sar_u64_amd, iemAImpl_sar_u64_intel;
3039	/** @} */
3040
3041	/** @name Multiplication and division operations.
3042	* @{ */
3043	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t pu16AX, uint8_t u8FactorDivisor, uint32_t pEFlags));
3044	typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
3045	FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_mul_u8_amd, iemAImpl_mul_u8_intel;
3046	FNIEMAIMPLMULDIVU8 iemAImpl_imul_u8, iemAImpl_imul_u8_amd, iemAImpl_imul_u8_intel;
3047	FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_div_u8_amd, iemAImpl_div_u8_intel;
3048	FNIEMAIMPLMULDIVU8 iemAImpl_idiv_u8, iemAImpl_idiv_u8_amd, iemAImpl_idiv_u8_intel;
3049
3050	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t pu16AX, uint16_t pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
3051	typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
3052	FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_mul_u16_amd, iemAImpl_mul_u16_intel;
3053	FNIEMAIMPLMULDIVU16 iemAImpl_imul_u16, iemAImpl_imul_u16_amd, iemAImpl_imul_u16_intel;
3054	FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_div_u16_amd, iemAImpl_div_u16_intel;
3055	FNIEMAIMPLMULDIVU16 iemAImpl_idiv_u16, iemAImpl_idiv_u16_amd, iemAImpl_idiv_u16_intel;
3056
3057	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t pu32EAX, uint32_t pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
3058	typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
3059	FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_mul_u32_amd, iemAImpl_mul_u32_intel;
3060	FNIEMAIMPLMULDIVU32 iemAImpl_imul_u32, iemAImpl_imul_u32_amd, iemAImpl_imul_u32_intel;
3061	FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_div_u32_amd, iemAImpl_div_u32_intel;
3062	FNIEMAIMPLMULDIVU32 iemAImpl_idiv_u32, iemAImpl_idiv_u32_amd, iemAImpl_idiv_u32_intel;
3063
3064	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t pu64RAX, uint64_t pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
3065	typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
3066	FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_mul_u64_amd, iemAImpl_mul_u64_intel;
3067	FNIEMAIMPLMULDIVU64 iemAImpl_imul_u64, iemAImpl_imul_u64_amd, iemAImpl_imul_u64_intel;
3068	FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_div_u64_amd, iemAImpl_div_u64_intel;
3069	FNIEMAIMPLMULDIVU64 iemAImpl_idiv_u64, iemAImpl_idiv_u64_amd, iemAImpl_idiv_u64_intel;
3070	/** @} */
3071
3072	/** @name Byte Swap.
3073	* @{ */
3074	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t pu32Dst)); / Yes, 32-bit register access. */
3075	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
3076	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
3077	/** @} */
3078
3079	/** @name Misc.
3080	* @{ */
3081	FNIEMAIMPLBINU16 iemAImpl_arpl;
3082	/** @} */
3083
3084	/** @name RDRAND and RDSEED
3085	* @{ */
3086	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU16,(uint16_t puDst, uint32_t pEFlags));
3087	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU32,(uint32_t puDst, uint32_t pEFlags));
3088	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU64,(uint64_t puDst, uint32_t pEFlags));
3089	typedef FNIEMAIMPLRDRANDSEEDU16 *PFNIEMAIMPLRDRANDSEEDU16;
3090	typedef FNIEMAIMPLRDRANDSEEDU32 *PFNIEMAIMPLRDRANDSEEDU32;
3091	typedef FNIEMAIMPLRDRANDSEEDU64 *PFNIEMAIMPLRDRANDSEEDU64;
3092
3093	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdrand_u16, iemAImpl_rdrand_u16_fallback;
3094	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdrand_u32, iemAImpl_rdrand_u32_fallback;
3095	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdrand_u64, iemAImpl_rdrand_u64_fallback;
3096	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdseed_u16, iemAImpl_rdseed_u16_fallback;
3097	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdseed_u32, iemAImpl_rdseed_u32_fallback;
3098	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdseed_u64, iemAImpl_rdseed_u64_fallback;
3099	/** @} */
3100
3101	/** @name ADOX and ADCX
3102	* @{ */
3103	FNIEMAIMPLBINU32 iemAImpl_adcx_u32, iemAImpl_adcx_u32_fallback;
3104	FNIEMAIMPLBINU64 iemAImpl_adcx_u64, iemAImpl_adcx_u64_fallback;
3105	FNIEMAIMPLBINU32 iemAImpl_adox_u32, iemAImpl_adox_u32_fallback;
3106	FNIEMAIMPLBINU64 iemAImpl_adox_u64, iemAImpl_adox_u64_fallback;
3107	/** @} */
3108
3109	/** @name FPU operations taking a 32-bit float argument
3110	* @{ */
3111	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3112	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
3113	typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
3114
3115	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3116	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
3117	typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
3118
3119	FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
3120	FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
3121	FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
3122	FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
3123	FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
3124	FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
3125	FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
3126
3127	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
3128	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3129	PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
3130	/** @} */
3131
3132	/** @name FPU operations taking a 64-bit float argument
3133	* @{ */
3134	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3135	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
3136	typedef FNIEMAIMPLFPUR64FSW *PFNIEMAIMPLFPUR64FSW;
3137
3138	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3139	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
3140	typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
3141
3142	FNIEMAIMPLFPUR64FSW iemAImpl_fcom_r80_by_r64;
3143	FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
3144	FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
3145	FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
3146	FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
3147	FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
3148	FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
3149
3150	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
3151	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3152	PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
3153	/** @} */
3154
3155	/** @name FPU operations taking a 80-bit float argument
3156	* @{ */
3157	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3158	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
3159	typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
3160	FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
3161	FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
3162	FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
3163	FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
3164	FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
3165	FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
3166	FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
3167	FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
3168	FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
3169
3170	FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80, iemAImpl_fpatan_r80_by_r80_amd, iemAImpl_fpatan_r80_by_r80_intel;
3171	FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80, iemAImpl_fyl2x_r80_by_r80_amd, iemAImpl_fyl2x_r80_by_r80_intel;
3172	FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80, iemAImpl_fyl2xp1_r80_by_r80_amd, iemAImpl_fyl2xp1_r80_by_r80_intel;
3173
3174	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3175	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
3176	typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
3177	FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
3178	FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
3179
3180	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
3181	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
3182	typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
3183	FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
3184	FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
3185
3186	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
3187	typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
3188	FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
3189	FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
3190	FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80, iemAImpl_f2xm1_r80_amd, iemAImpl_f2xm1_r80_intel;
3191	FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
3192	FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
3193	FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80, iemAImpl_fsin_r80_amd, iemAImpl_fsin_r80_intel;
3194	FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80, iemAImpl_fcos_r80_amd, iemAImpl_fcos_r80_intel;
3195
3196	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
3197	typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
3198	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
3199	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
3200
3201	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
3202	typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
3203	FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
3204	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
3205	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
3206	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
3207	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
3208	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
3209	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
3210
3211	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
3212	PCRTFLOAT80U pr80Val));
3213	typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
3214	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80, iemAImpl_fptan_r80_r80_amd, iemAImpl_fptan_r80_r80_intel;
3215	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
3216	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80, iemAImpl_fsincos_r80_r80_amd, iemAImpl_fsincos_r80_r80_intel;
3217
3218	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
3219	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3220	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
3221
3222	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_d80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTPBCD80U pd80Val));
3223	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_d80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3224	PRTPBCD80U pd80Dst, PCRTFLOAT80U pr80Src));
3225
3226	/** @} */
3227
3228	/** @name FPU operations taking a 16-bit signed integer argument
3229	* @{ */
3230	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3231	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
3232	typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
3233	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI16,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3234	int16_t *pi16Dst, PCRTFLOAT80U pr80Src));
3235	typedef FNIEMAIMPLFPUSTR80TOI16 *PFNIEMAIMPLFPUSTR80TOI16;
3236
3237	FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
3238	FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
3239	FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
3240	FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
3241	FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
3242	FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
3243
3244	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3245	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
3246	typedef FNIEMAIMPLFPUI16FSW *PFNIEMAIMPLFPUI16FSW;
3247	FNIEMAIMPLFPUI16FSW iemAImpl_ficom_r80_by_i16;
3248
3249	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
3250	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fist_r80_to_i16;
3251	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fistt_r80_to_i16, iemAImpl_fistt_r80_to_i16_amd, iemAImpl_fistt_r80_to_i16_intel;
3252	/** @} */
3253
3254	/** @name FPU operations taking a 32-bit signed integer argument
3255	* @{ */
3256	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3257	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
3258	typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
3259	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI32,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3260	int32_t *pi32Dst, PCRTFLOAT80U pr80Src));
3261	typedef FNIEMAIMPLFPUSTR80TOI32 *PFNIEMAIMPLFPUSTR80TOI32;
3262
3263	FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
3264	FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
3265	FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
3266	FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
3267	FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
3268	FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
3269
3270	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3271	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
3272	typedef FNIEMAIMPLFPUI32FSW *PFNIEMAIMPLFPUI32FSW;
3273	FNIEMAIMPLFPUI32FSW iemAImpl_ficom_r80_by_i32;
3274
3275	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
3276	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fist_r80_to_i32;
3277	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fistt_r80_to_i32;
3278	/** @} */
3279
3280	/** @name FPU operations taking a 64-bit signed integer argument
3281	* @{ */
3282	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI64,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3283	int64_t *pi64Dst, PCRTFLOAT80U pr80Src));
3284	typedef FNIEMAIMPLFPUSTR80TOI64 *PFNIEMAIMPLFPUSTR80TOI64;
3285
3286	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
3287	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fist_r80_to_i64;
3288	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fistt_r80_to_i64;
3289	/** @} */
3290
3291
3292	/** Temporary type representing a 256-bit vector register. */
3293	typedef struct { uint64_t au64[4]; } IEMVMM256;
3294	/** Temporary type pointing to a 256-bit vector register. */
3295	typedef IEMVMM256 *PIEMVMM256;
3296	/** Temporary type pointing to a const 256-bit vector register. */
3297	typedef IEMVMM256 *PCIEMVMM256;
3298
3299
3300	/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
3301	* @{ */
3302	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t puDst, uint64_t const puSrc));
3303	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
3304	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U128,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
3305	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
3306	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U128,(PX86XSAVEAREA pExtState, PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
3307	typedef FNIEMAIMPLMEDIAF3U128 *PFNIEMAIMPLMEDIAF3U128;
3308	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U256,(PX86XSAVEAREA pExtState, PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
3309	typedef FNIEMAIMPLMEDIAF3U256 *PFNIEMAIMPLMEDIAF3U256;
3310	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U64,(uint64_t puDst, uint64_t const puSrc));
3311	typedef FNIEMAIMPLMEDIAOPTF2U64 *PFNIEMAIMPLMEDIAOPTF2U64;
3312	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128,(PRTUINT128U puDst, PCRTUINT128U puSrc));
3313	typedef FNIEMAIMPLMEDIAOPTF2U128 *PFNIEMAIMPLMEDIAOPTF2U128;
3314	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
3315	typedef FNIEMAIMPLMEDIAOPTF3U128 *PFNIEMAIMPLMEDIAOPTF3U128;
3316	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
3317	typedef FNIEMAIMPLMEDIAOPTF3U256 *PFNIEMAIMPLMEDIAOPTF3U256;
3318	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256,(PRTUINT256U puDst, PCRTUINT256U puSrc));
3319	typedef FNIEMAIMPLMEDIAOPTF2U256 *PFNIEMAIMPLMEDIAOPTF2U256;
3320	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pshufb_u64, iemAImpl_pshufb_u64_fallback;
3321	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pand_u64, iemAImpl_pandn_u64, iemAImpl_por_u64, iemAImpl_pxor_u64;
3322	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
3323	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pcmpgtb_u64, iemAImpl_pcmpgtw_u64, iemAImpl_pcmpgtd_u64;
3324	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddb_u64, iemAImpl_paddsb_u64, iemAImpl_paddusb_u64;
3325	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddw_u64, iemAImpl_paddsw_u64, iemAImpl_paddusw_u64;
3326	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddd_u64;
3327	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddq_u64;
3328	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubb_u64, iemAImpl_psubsb_u64, iemAImpl_psubusb_u64;
3329	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubw_u64, iemAImpl_psubsw_u64, iemAImpl_psubusw_u64;
3330	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubd_u64;
3331	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubq_u64;
3332	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmaddwd_u64, iemAImpl_pmaddwd_u64_fallback;
3333	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmullw_u64, iemAImpl_pmulhw_u64;
3334	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pminub_u64, iemAImpl_pmaxub_u64;
3335	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pminsw_u64, iemAImpl_pmaxsw_u64;
3336	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pabsb_u64, iemAImpl_pabsb_u64_fallback;
3337	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pabsw_u64, iemAImpl_pabsw_u64_fallback;
3338	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pabsd_u64, iemAImpl_pabsd_u64_fallback;
3339	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psignb_u64, iemAImpl_psignb_u64_fallback;
3340	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psignw_u64, iemAImpl_psignw_u64_fallback;
3341	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psignd_u64, iemAImpl_psignd_u64_fallback;
3342	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phaddw_u64, iemAImpl_phaddw_u64_fallback;
3343	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phaddd_u64, iemAImpl_phaddd_u64_fallback;
3344	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phsubw_u64, iemAImpl_phsubw_u64_fallback;
3345	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phsubd_u64, iemAImpl_phsubd_u64_fallback;
3346	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phaddsw_u64, iemAImpl_phaddsw_u64_fallback;
3347	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phsubsw_u64, iemAImpl_phsubsw_u64_fallback;
3348	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmaddubsw_u64, iemAImpl_pmaddubsw_u64_fallback;
3349	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhrsw_u64, iemAImpl_pmulhrsw_u64_fallback;
3350	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmuludq_u64;
3351	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllw_u64, iemAImpl_psrlw_u64, iemAImpl_psraw_u64;
3352	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pslld_u64, iemAImpl_psrld_u64, iemAImpl_psrad_u64;
3353	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllq_u64, iemAImpl_psrlq_u64;
3354	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packsswb_u64, iemAImpl_packuswb_u64;
3355	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packssdw_u64;
3356	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhuw_u64;
3357	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pavgb_u64, iemAImpl_pavgw_u64;
3358	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psadbw_u64;
3359
3360	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pshufb_u128, iemAImpl_pshufb_u128_fallback;
3361	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pand_u128, iemAImpl_pandn_u128, iemAImpl_por_u128, iemAImpl_pxor_u128;
3362	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
3363	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpeqq_u128, iemAImpl_pcmpeqq_u128_fallback;
3364	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpgtb_u128, iemAImpl_pcmpgtw_u128, iemAImpl_pcmpgtd_u128;
3365	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpgtq_u128, iemAImpl_pcmpgtq_u128_fallback;
3366	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddb_u128, iemAImpl_paddsb_u128, iemAImpl_paddusb_u128;
3367	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddw_u128, iemAImpl_paddsw_u128, iemAImpl_paddusw_u128;
3368	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddd_u128;
3369	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddq_u128;
3370	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubb_u128, iemAImpl_psubsb_u128, iemAImpl_psubusb_u128;
3371	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubw_u128, iemAImpl_psubsw_u128, iemAImpl_psubusw_u128;
3372	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubd_u128;
3373	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubq_u128;
3374	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmullw_u128, iemAImpl_pmullw_u128_fallback;
3375	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhw_u128;
3376	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulld_u128, iemAImpl_pmulld_u128_fallback;
3377	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaddwd_u128, iemAImpl_pmaddwd_u128_fallback;
3378	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminub_u128;
3379	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminud_u128, iemAImpl_pminud_u128_fallback;
3380	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminuw_u128, iemAImpl_pminuw_u128_fallback;
3381	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminsb_u128, iemAImpl_pminsb_u128_fallback;
3382	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminsd_u128, iemAImpl_pminsd_u128_fallback;
3383	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminsw_u128, iemAImpl_pminsw_u128_fallback;
3384	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxub_u128;
3385	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxud_u128, iemAImpl_pmaxud_u128_fallback;
3386	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxuw_u128, iemAImpl_pmaxuw_u128_fallback;
3387	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxsb_u128, iemAImpl_pmaxsb_u128_fallback;
3388	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxsw_u128;
3389	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxsd_u128, iemAImpl_pmaxsd_u128_fallback;
3390	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pabsb_u128, iemAImpl_pabsb_u128_fallback;
3391	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pabsw_u128, iemAImpl_pabsw_u128_fallback;
3392	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pabsd_u128, iemAImpl_pabsd_u128_fallback;
3393	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psignb_u128, iemAImpl_psignb_u128_fallback;
3394	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psignw_u128, iemAImpl_psignw_u128_fallback;
3395	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psignd_u128, iemAImpl_psignd_u128_fallback;
3396	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phaddw_u128, iemAImpl_phaddw_u128_fallback;
3397	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phaddd_u128, iemAImpl_phaddd_u128_fallback;
3398	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phsubw_u128, iemAImpl_phsubw_u128_fallback;
3399	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phsubd_u128, iemAImpl_phsubd_u128_fallback;
3400	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phaddsw_u128, iemAImpl_phaddsw_u128_fallback;
3401	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phsubsw_u128, iemAImpl_phsubsw_u128_fallback;
3402	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaddubsw_u128, iemAImpl_pmaddubsw_u128_fallback;
3403	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhrsw_u128, iemAImpl_pmulhrsw_u128_fallback;
3404	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuludq_u128;
3405	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaddwd_u128, iemAImpl_pmaddwd_u128_fallback;
3406	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packsswb_u128, iemAImpl_packuswb_u128;
3407	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packssdw_u128, iemAImpl_packusdw_u128;
3408	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllw_u128, iemAImpl_psrlw_u128, iemAImpl_psraw_u128;
3409	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pslld_u128, iemAImpl_psrld_u128, iemAImpl_psrad_u128;
3410	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllq_u128, iemAImpl_psrlq_u128;
3411	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhuw_u128;
3412	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pavgb_u128, iemAImpl_pavgw_u128;
3413	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psadbw_u128;
3414	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuldq_u128, iemAImpl_pmuldq_u128_fallback;
3415	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpcklps_u128, iemAImpl_unpcklpd_u128;
3416	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpckhps_u128, iemAImpl_unpckhpd_u128;
3417	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phminposuw_u128, iemAImpl_phminposuw_u128_fallback;
3418
3419	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpshufb_u128, iemAImpl_vpshufb_u128_fallback;
3420	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpand_u128, iemAImpl_vpand_u128_fallback;
3421	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpandn_u128, iemAImpl_vpandn_u128_fallback;
3422	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpor_u128, iemAImpl_vpor_u128_fallback;
3423	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpxor_u128, iemAImpl_vpxor_u128_fallback;
3424	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqb_u128, iemAImpl_vpcmpeqb_u128_fallback;
3425	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqw_u128, iemAImpl_vpcmpeqw_u128_fallback;
3426	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqd_u128, iemAImpl_vpcmpeqd_u128_fallback;
3427	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqq_u128, iemAImpl_vpcmpeqq_u128_fallback;
3428	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtb_u128, iemAImpl_vpcmpgtb_u128_fallback;
3429	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtw_u128, iemAImpl_vpcmpgtw_u128_fallback;
3430	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtd_u128, iemAImpl_vpcmpgtd_u128_fallback;
3431	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtq_u128, iemAImpl_vpcmpgtq_u128_fallback;
3432	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddb_u128, iemAImpl_vpaddb_u128_fallback;
3433	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddw_u128, iemAImpl_vpaddw_u128_fallback;
3434	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddd_u128, iemAImpl_vpaddd_u128_fallback;
3435	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddq_u128, iemAImpl_vpaddq_u128_fallback;
3436	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubb_u128, iemAImpl_vpsubb_u128_fallback;
3437	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubw_u128, iemAImpl_vpsubw_u128_fallback;
3438	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubd_u128, iemAImpl_vpsubd_u128_fallback;
3439	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubq_u128, iemAImpl_vpsubq_u128_fallback;
3440	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminub_u128, iemAImpl_vpminub_u128_fallback;
3441	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminuw_u128, iemAImpl_vpminuw_u128_fallback;
3442	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminud_u128, iemAImpl_vpminud_u128_fallback;
3443	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminsb_u128, iemAImpl_vpminsb_u128_fallback;
3444	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminsw_u128, iemAImpl_vpminsw_u128_fallback;
3445	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminsd_u128, iemAImpl_vpminsd_u128_fallback;
3446	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxub_u128, iemAImpl_vpmaxub_u128_fallback;
3447	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxuw_u128, iemAImpl_vpmaxuw_u128_fallback;
3448	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxud_u128, iemAImpl_vpmaxud_u128_fallback;
3449	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxsb_u128, iemAImpl_vpmaxsb_u128_fallback;
3450	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxsw_u128, iemAImpl_vpmaxsw_u128_fallback;
3451	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxsd_u128, iemAImpl_vpmaxsd_u128_fallback;
3452	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpacksswb_u128, iemAImpl_vpacksswb_u128_fallback;
3453	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackssdw_u128, iemAImpl_vpackssdw_u128_fallback;
3454	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackuswb_u128, iemAImpl_vpackuswb_u128_fallback;
3455	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackusdw_u128, iemAImpl_vpackusdw_u128_fallback;
3456	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmullw_u128, iemAImpl_vpmullw_u128_fallback;
3457	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulld_u128, iemAImpl_vpmulld_u128_fallback;
3458	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhw_u128, iemAImpl_vpmulhw_u128_fallback;
3459	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhuw_u128, iemAImpl_vpmulhuw_u128_fallback;
3460	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgb_u128, iemAImpl_vpavgb_u128_fallback;
3461	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgw_u128, iemAImpl_vpavgw_u128_fallback;
3462	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignb_u128, iemAImpl_vpsignb_u128_fallback;
3463	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignw_u128, iemAImpl_vpsignw_u128_fallback;
3464	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignd_u128, iemAImpl_vpsignd_u128_fallback;
3465	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddw_u128, iemAImpl_vphaddw_u128_fallback;
3466	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddd_u128, iemAImpl_vphaddd_u128_fallback;
3467	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubw_u128, iemAImpl_vphsubw_u128_fallback;
3468	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubd_u128, iemAImpl_vphsubd_u128_fallback;
3469	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddsw_u128, iemAImpl_vphaddsw_u128_fallback;
3470	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubsw_u128, iemAImpl_vphsubsw_u128_fallback;
3471	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddubsw_u128, iemAImpl_vpmaddubsw_u128_fallback;
3472	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhrsw_u128, iemAImpl_vpmulhrsw_u128_fallback;
3473	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsadbw_u128, iemAImpl_vpsadbw_u128_fallback;
3474	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuldq_u128, iemAImpl_vpmuldq_u128_fallback;
3475	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuludq_u128, iemAImpl_vpmuludq_u128_fallback;
3476	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsb_u128, iemAImpl_vpsubsb_u128_fallback;
3477	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsw_u128, iemAImpl_vpsubsw_u128_fallback;
3478	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusb_u128, iemAImpl_vpsubusb_u128_fallback;
3479	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusw_u128, iemAImpl_vpsubusw_u128_fallback;
3480	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusb_u128, iemAImpl_vpaddusb_u128_fallback;
3481	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusw_u128, iemAImpl_vpaddusw_u128_fallback;
3482	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsb_u128, iemAImpl_vpaddsb_u128_fallback;
3483	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsw_u128, iemAImpl_vpaddsw_u128_fallback;
3484	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllw_u128, iemAImpl_vpsllw_u128_fallback;
3485	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpslld_u128, iemAImpl_vpslld_u128_fallback;
3486	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllq_u128, iemAImpl_vpsllq_u128_fallback;
3487	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsraw_u128, iemAImpl_vpsraw_u128_fallback;
3488	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrad_u128, iemAImpl_vpsrad_u128_fallback;
3489	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlw_u128, iemAImpl_vpsrlw_u128_fallback;
3490	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrld_u128, iemAImpl_vpsrld_u128_fallback;
3491	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlq_u128, iemAImpl_vpsrlq_u128_fallback;
3492	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddwd_u128, iemAImpl_vpmaddwd_u128_fallback;
3493
3494	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsb_u128, iemAImpl_vpabsb_u128_fallback;
3495	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsw_u128, iemAImpl_vpabsd_u128_fallback;
3496	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsd_u128, iemAImpl_vpabsw_u128_fallback;
3497	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vphminposuw_u128, iemAImpl_vphminposuw_u128_fallback;
3498
3499	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpshufb_u256, iemAImpl_vpshufb_u256_fallback;
3500	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpand_u256, iemAImpl_vpand_u256_fallback;
3501	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpandn_u256, iemAImpl_vpandn_u256_fallback;
3502	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpor_u256, iemAImpl_vpor_u256_fallback;
3503	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpxor_u256, iemAImpl_vpxor_u256_fallback;
3504	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqb_u256, iemAImpl_vpcmpeqb_u256_fallback;
3505	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqw_u256, iemAImpl_vpcmpeqw_u256_fallback;
3506	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqd_u256, iemAImpl_vpcmpeqd_u256_fallback;
3507	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqq_u256, iemAImpl_vpcmpeqq_u256_fallback;
3508	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtb_u256, iemAImpl_vpcmpgtb_u256_fallback;
3509	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtw_u256, iemAImpl_vpcmpgtw_u256_fallback;
3510	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtd_u256, iemAImpl_vpcmpgtd_u256_fallback;
3511	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtq_u256, iemAImpl_vpcmpgtq_u256_fallback;
3512	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddb_u256, iemAImpl_vpaddb_u256_fallback;
3513	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddw_u256, iemAImpl_vpaddw_u256_fallback;
3514	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddd_u256, iemAImpl_vpaddd_u256_fallback;
3515	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddq_u256, iemAImpl_vpaddq_u256_fallback;
3516	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubb_u256, iemAImpl_vpsubb_u256_fallback;
3517	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubw_u256, iemAImpl_vpsubw_u256_fallback;
3518	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubd_u256, iemAImpl_vpsubd_u256_fallback;
3519	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubq_u256, iemAImpl_vpsubq_u256_fallback;
3520	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminub_u256, iemAImpl_vpminub_u256_fallback;
3521	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminuw_u256, iemAImpl_vpminuw_u256_fallback;
3522	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminud_u256, iemAImpl_vpminud_u256_fallback;
3523	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminsb_u256, iemAImpl_vpminsb_u256_fallback;
3524	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminsw_u256, iemAImpl_vpminsw_u256_fallback;
3525	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminsd_u256, iemAImpl_vpminsd_u256_fallback;
3526	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxub_u256, iemAImpl_vpmaxub_u256_fallback;
3527	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxuw_u256, iemAImpl_vpmaxuw_u256_fallback;
3528	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxud_u256, iemAImpl_vpmaxud_u256_fallback;
3529	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxsb_u256, iemAImpl_vpmaxsb_u256_fallback;
3530	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxsw_u256, iemAImpl_vpmaxsw_u256_fallback;
3531	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxsd_u256, iemAImpl_vpmaxsd_u256_fallback;
3532	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpacksswb_u256, iemAImpl_vpacksswb_u256_fallback;
3533	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackssdw_u256, iemAImpl_vpackssdw_u256_fallback;
3534	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackuswb_u256, iemAImpl_vpackuswb_u256_fallback;
3535	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackusdw_u256, iemAImpl_vpackusdw_u256_fallback;
3536	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmullw_u256, iemAImpl_vpmullw_u256_fallback;
3537	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulld_u256, iemAImpl_vpmulld_u256_fallback;
3538	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhw_u256, iemAImpl_vpmulhw_u256_fallback;
3539	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhuw_u256, iemAImpl_vpmulhuw_u256_fallback;
3540	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgb_u256, iemAImpl_vpavgb_u256_fallback;
3541	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgw_u256, iemAImpl_vpavgw_u256_fallback;
3542	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignb_u256, iemAImpl_vpsignb_u256_fallback;
3543	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignw_u256, iemAImpl_vpsignw_u256_fallback;
3544	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignd_u256, iemAImpl_vpsignd_u256_fallback;
3545	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddw_u256, iemAImpl_vphaddw_u256_fallback;
3546	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddd_u256, iemAImpl_vphaddd_u256_fallback;
3547	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubw_u256, iemAImpl_vphsubw_u256_fallback;
3548	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubd_u256, iemAImpl_vphsubd_u256_fallback;
3549	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddsw_u256, iemAImpl_vphaddsw_u256_fallback;
3550	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubsw_u256, iemAImpl_vphsubsw_u256_fallback;
3551	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddubsw_u256, iemAImpl_vpmaddubsw_u256_fallback;
3552	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhrsw_u256, iemAImpl_vpmulhrsw_u256_fallback;
3553	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsadbw_u256, iemAImpl_vpsadbw_u256_fallback;
3554	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuldq_u256, iemAImpl_vpmuldq_u256_fallback;
3555	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuludq_u256, iemAImpl_vpmuludq_u256_fallback;
3556	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsb_u256, iemAImpl_vpsubsb_u256_fallback;
3557	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsw_u256, iemAImpl_vpsubsw_u256_fallback;
3558	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusb_u256, iemAImpl_vpsubusb_u256_fallback;
3559	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusw_u256, iemAImpl_vpsubusw_u256_fallback;
3560	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusb_u256, iemAImpl_vpaddusb_u256_fallback;
3561	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusw_u256, iemAImpl_vpaddusw_u256_fallback;
3562	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsb_u256, iemAImpl_vpaddsb_u256_fallback;
3563	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsw_u256, iemAImpl_vpaddsw_u256_fallback;
3564	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllw_u256, iemAImpl_vpsllw_u256_fallback;
3565	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpslld_u256, iemAImpl_vpslld_u256_fallback;
3566	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllq_u256, iemAImpl_vpsllq_u256_fallback;
3567	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsraw_u256, iemAImpl_vpsraw_u256_fallback;
3568	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrad_u256, iemAImpl_vpsrad_u256_fallback;
3569	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlw_u256, iemAImpl_vpsrlw_u256_fallback;
3570	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrld_u256, iemAImpl_vpsrld_u256_fallback;
3571	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlq_u256, iemAImpl_vpsrlq_u256_fallback;
3572	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddwd_u256, iemAImpl_vpmaddwd_u256_fallback;
3573
3574	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsb_u256, iemAImpl_vpabsb_u256_fallback;
3575	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsw_u256, iemAImpl_vpabsw_u256_fallback;
3576	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsd_u256, iemAImpl_vpabsd_u256_fallback;
3577	/** @} */
3578
3579	/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
3580	* @{ */
3581	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
3582	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
3583	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpcklbw_u128, iemAImpl_vpunpcklbw_u128_fallback,
3584	iemAImpl_vpunpcklwd_u128, iemAImpl_vpunpcklwd_u128_fallback,
3585	iemAImpl_vpunpckldq_u128, iemAImpl_vpunpckldq_u128_fallback,
3586	iemAImpl_vpunpcklqdq_u128, iemAImpl_vpunpcklqdq_u128_fallback,
3587	iemAImpl_vunpcklps_u128, iemAImpl_vunpcklps_u128_fallback,
3588	iemAImpl_vunpcklpd_u128, iemAImpl_vunpcklpd_u128_fallback,
3589	iemAImpl_vunpckhps_u128, iemAImpl_vunpckhps_u128_fallback,
3590	iemAImpl_vunpckhpd_u128, iemAImpl_vunpckhpd_u128_fallback;
3591
3592	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpcklbw_u256, iemAImpl_vpunpcklbw_u256_fallback,
3593	iemAImpl_vpunpcklwd_u256, iemAImpl_vpunpcklwd_u256_fallback,
3594	iemAImpl_vpunpckldq_u256, iemAImpl_vpunpckldq_u256_fallback,
3595	iemAImpl_vpunpcklqdq_u256, iemAImpl_vpunpcklqdq_u256_fallback,
3596	iemAImpl_vunpcklps_u256, iemAImpl_vunpcklps_u256_fallback,
3597	iemAImpl_vunpcklpd_u256, iemAImpl_vunpcklpd_u256_fallback,
3598	iemAImpl_vunpckhps_u256, iemAImpl_vunpckhps_u256_fallback,
3599	iemAImpl_vunpckhpd_u256, iemAImpl_vunpckhpd_u256_fallback;
3600	/** @} */
3601
3602	/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
3603	* @{ */
3604	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
3605	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
3606	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpckhbw_u128, iemAImpl_vpunpckhbw_u128_fallback,
3607	iemAImpl_vpunpckhwd_u128, iemAImpl_vpunpckhwd_u128_fallback,
3608	iemAImpl_vpunpckhdq_u128, iemAImpl_vpunpckhdq_u128_fallback,
3609	iemAImpl_vpunpckhqdq_u128, iemAImpl_vpunpckhqdq_u128_fallback;
3610	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpckhbw_u256, iemAImpl_vpunpckhbw_u256_fallback,
3611	iemAImpl_vpunpckhwd_u256, iemAImpl_vpunpckhwd_u256_fallback,
3612	iemAImpl_vpunpckhdq_u256, iemAImpl_vpunpckhdq_u256_fallback,
3613	iemAImpl_vpunpckhqdq_u256, iemAImpl_vpunpckhqdq_u256_fallback;
3614	/** @} */
3615
3616	/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
3617	* @{ */
3618	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3619	typedef FNIEMAIMPLMEDIAPSHUFU128 *PFNIEMAIMPLMEDIAPSHUFU128;
3620	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
3621	typedef FNIEMAIMPLMEDIAPSHUFU256 *PFNIEMAIMPLMEDIAPSHUFU256;
3622	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw_u64,(uint64_t puDst, uint64_t const puSrc, uint8_t bEvil));
3623	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_pshufhw_u128, iemAImpl_pshuflw_u128, iemAImpl_pshufd_u128;
3624	#ifndef IEM_WITHOUT_ASSEMBLY
3625	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256, iemAImpl_vpshuflw_u256, iemAImpl_vpshufd_u256;
3626	#endif
3627	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256_fallback, iemAImpl_vpshuflw_u256_fallback, iemAImpl_vpshufd_u256_fallback;
3628	/** @} */
3629
3630	/** @name Media (SSE/MMX/AVX) operation: Shift Immediate Stuff (evil)
3631	* @{ */
3632	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU64,(uint64_t *puDst, uint8_t bShift));
3633	typedef FNIEMAIMPLMEDIAPSHIFTU64 *PFNIEMAIMPLMEDIAPSHIFTU64;
3634	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU128,(PRTUINT128U puDst, uint8_t bShift));
3635	typedef FNIEMAIMPLMEDIAPSHIFTU128 *PFNIEMAIMPLMEDIAPSHIFTU128;
3636	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU256,(PRTUINT256U puDst, uint8_t bShift));
3637	typedef FNIEMAIMPLMEDIAPSHIFTU256 *PFNIEMAIMPLMEDIAPSHIFTU256;
3638	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psllw_imm_u64, iemAImpl_pslld_imm_u64, iemAImpl_psllq_imm_u64;
3639	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psrlw_imm_u64, iemAImpl_psrld_imm_u64, iemAImpl_psrlq_imm_u64;
3640	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psraw_imm_u64, iemAImpl_psrad_imm_u64;
3641	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psllw_imm_u128, iemAImpl_pslld_imm_u128, iemAImpl_psllq_imm_u128;
3642	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psrlw_imm_u128, iemAImpl_psrld_imm_u128, iemAImpl_psrlq_imm_u128;
3643	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psraw_imm_u128, iemAImpl_psrad_imm_u128;
3644	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_pslldq_imm_u128, iemAImpl_psrldq_imm_u128;
3645	/** @} */
3646
3647	/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
3648	* @{ */
3649	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(uint64_t pu64Dst, uint64_t const puSrc));
3650	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(uint64_t *pu64Dst, PCRTUINT128U puSrc));
3651	#ifndef IEM_WITHOUT_ASSEMBLY
3652	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
3653	#endif
3654	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256_fallback,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
3655	/** @} */
3656
3657	/** @name Media (SSE/MMX/AVX) operations: Variable Blend Packed Bytes/R32/R64.
3658	* @{ */
3659	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puMask));
3660	typedef FNIEMAIMPLBLENDU128 *PFNIEMAIMPLBLENDU128;
3661	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, PCRTUINT128U puMask));
3662	typedef FNIEMAIMPLAVXBLENDU128 *PFNIEMAIMPLAVXBLENDU128;
3663	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, PCRTUINT256U puMask));
3664	typedef FNIEMAIMPLAVXBLENDU256 *PFNIEMAIMPLAVXBLENDU256;
3665
3666	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128;
3667	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128_fallback;
3668	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128;
3669	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128_fallback;
3670	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256;
3671	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256_fallback;
3672
3673	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128;
3674	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128_fallback;
3675	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128;
3676	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128_fallback;
3677	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256;
3678	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256_fallback;
3679
3680	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128;
3681	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128_fallback;
3682	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128;
3683	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128_fallback;
3684	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256;
3685	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256_fallback;
3686	/** @} */
3687
3688
3689	/** @name Media (SSE/MMX/AVX) operation: Sort this later
3690	* @{ */
3691	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3692	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3693	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3694	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3695	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3696
3697	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3698	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3699	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3700	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3701	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3702
3703	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3704	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3705	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
3706	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3707	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3708
3709	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3710	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3711	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3712	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3713	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3714
3715	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3716	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3717	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3718	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3719	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3720
3721	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3722	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3723	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3724	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3725	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3726
3727	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3728	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3729	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3730	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3731	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3732
3733	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3734	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3735	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3736	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3737	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3738
3739	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3740	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3741	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
3742	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3743	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3744
3745	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3746	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3747	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3748	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3749	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3750
3751	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3752	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3753	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3754	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3755	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3756
3757	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3758	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3759	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3760	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3761	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3762
3763	IEM_DECL_IMPL_DEF(void, iemAImpl_shufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3764	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3765	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3766	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3767	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3768
3769	IEM_DECL_IMPL_DEF(void, iemAImpl_shufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3770	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3771	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3772	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3773	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3774
3775	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
3776	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64_fallback,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
3777
3778	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3779	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3780	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3781	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3782	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3783
3784	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3785	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3786	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3787	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3788	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3789
3790
3791	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3792	typedef FNIEMAIMPLMEDIAOPTF2U128IMM8 *PFNIEMAIMPLMEDIAOPTF2U128IMM8;
3793	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
3794	typedef FNIEMAIMPLMEDIAOPTF2U256IMM8 *PFNIEMAIMPLMEDIAOPTF2U256IMM8;
3795	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3796	typedef FNIEMAIMPLMEDIAOPTF3U128IMM8 *PFNIEMAIMPLMEDIAOPTF3U128IMM8;
3797	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3798	typedef FNIEMAIMPLMEDIAOPTF3U256IMM8 *PFNIEMAIMPLMEDIAOPTF3U256IMM8;
3799
3800	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_palignr_u128, iemAImpl_palignr_u128_fallback;
3801	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pblendw_u128, iemAImpl_pblendw_u128_fallback;
3802	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendps_u128, iemAImpl_blendps_u128_fallback;
3803	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendpd_u128, iemAImpl_blendpd_u128_fallback;
3804
3805	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpalignr_u128, iemAImpl_vpalignr_u128_fallback;
3806	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendw_u128, iemAImpl_vpblendw_u128_fallback;
3807	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendd_u128, iemAImpl_vpblendd_u128_fallback;
3808	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendps_u128, iemAImpl_vblendps_u128_fallback;
3809	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendpd_u128, iemAImpl_vblendpd_u128_fallback;
3810
3811	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpalignr_u256, iemAImpl_vpalignr_u256_fallback;
3812	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendw_u256, iemAImpl_vpblendw_u256_fallback;
3813	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendd_u256, iemAImpl_vpblendd_u256_fallback;
3814	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendps_u256, iemAImpl_vblendps_u256_fallback;
3815	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendpd_u256, iemAImpl_vblendpd_u256_fallback;
3816	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2i128_u256, iemAImpl_vperm2i128_u256_fallback;
3817	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2f128_u256, iemAImpl_vperm2f128_u256_fallback;
3818
3819	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesimc_u128, iemAImpl_aesimc_u128_fallback;
3820	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenc_u128, iemAImpl_aesenc_u128_fallback;
3821	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenclast_u128, iemAImpl_aesenclast_u128_fallback;
3822	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdec_u128, iemAImpl_aesdec_u128_fallback;
3823	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdeclast_u128, iemAImpl_aesdeclast_u128_fallback;
3824
3825	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesimc_u128, iemAImpl_vaesimc_u128_fallback;
3826	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenc_u128, iemAImpl_vaesenc_u128_fallback;
3827	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenclast_u128, iemAImpl_vaesenclast_u128_fallback;
3828	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdec_u128, iemAImpl_vaesdec_u128_fallback;
3829	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdeclast_u128, iemAImpl_vaesdeclast_u128_fallback;
3830
3831	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_aeskeygenassist_u128, iemAImpl_aeskeygenassist_u128_fallback;
3832
3833	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vaeskeygenassist_u128, iemAImpl_vaeskeygenassist_u128_fallback;
3834
3835	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1nexte_u128, iemAImpl_sha1nexte_u128_fallback;
3836	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg1_u128, iemAImpl_sha1msg1_u128_fallback;
3837	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg2_u128, iemAImpl_sha1msg2_u128_fallback;
3838	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg1_u128, iemAImpl_sha256msg1_u128_fallback;
3839	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg2_u128, iemAImpl_sha256msg2_u128_fallback;
3840	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_sha1rnds4_u128, iemAImpl_sha1rnds4_u128_fallback;
3841	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
3842	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
3843
3844	typedef struct IEMPCMPISTRXSRC
3845	{
3846	RTUINT128U uSrc1;
3847	RTUINT128U uSrc2;
3848	} IEMPCMPISTRXSRC;
3849	typedef IEMPCMPISTRXSRC *PIEMPCMPISTRXSRC;
3850	typedef const IEMPCMPISTRXSRC *PCIEMPCMPISTRXSRC;
3851
3852	typedef struct IEMPCMPESTRXSRC
3853	{
3854	RTUINT128U uSrc1;
3855	RTUINT128U uSrc2;
3856	uint64_t u64Rax;
3857	uint64_t u64Rdx;
3858	} IEMPCMPESTRXSRC;
3859	typedef IEMPCMPESTRXSRC *PIEMPCMPESTRXSRC;
3860	typedef const IEMPCMPESTRXSRC *PCIEMPCMPESTRXSRC;
3861
3862	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLPCMPISTRIU128IMM8,(uint32_t *pEFlags, PCRTUINT128U pSrc1, PCRTUINT128U pSrc2, uint8_t bEvil));
3863	typedef FNIEMAIMPLPCMPISTRIU128IMM8 *PFNIEMAIMPLPCMPISTRIU128IMM8;
3864	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRIU128IMM8,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
3865	typedef FNIEMAIMPLPCMPESTRIU128IMM8 *PFNIEMAIMPLPCMPESTRIU128IMM8;
3866
3867	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPISTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
3868	typedef FNIEMAIMPLPCMPISTRMU128IMM8 *PFNIEMAIMPLPCMPISTRMU128IMM8;
3869	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
3870	typedef FNIEMAIMPLPCMPESTRMU128IMM8 *PFNIEMAIMPLPCMPESTRMU128IMM8;
3871
3872	FNIEMAIMPLPCMPISTRIU128IMM8 iemAImpl_pcmpistri_u128, iemAImpl_pcmpistri_u128_fallback;
3873	FNIEMAIMPLPCMPESTRIU128IMM8 iemAImpl_pcmpestri_u128, iemAImpl_pcmpestri_u128_fallback;
3874	FNIEMAIMPLPCMPISTRMU128IMM8 iemAImpl_pcmpistrm_u128, iemAImpl_pcmpistrm_u128_fallback;
3875	FNIEMAIMPLPCMPESTRMU128IMM8 iemAImpl_pcmpestrm_u128, iemAImpl_pcmpestrm_u128_fallback;
3876
3877	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pclmulqdq_u128, iemAImpl_pclmulqdq_u128_fallback;
3878	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpclmulqdq_u128, iemAImpl_vpclmulqdq_u128_fallback;
3879
3880	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_mpsadbw_u128, iemAImpl_mpsadbw_u128_fallback;
3881	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vmpsadbw_u128, iemAImpl_vmpsadbw_u128_fallback;
3882	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vmpsadbw_u256, iemAImpl_vmpsadbw_u256_fallback;
3883
3884	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsllw_imm_u128, iemAImpl_vpsllw_imm_u128_fallback;
3885	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsllw_imm_u256, iemAImpl_vpsllw_imm_u256_fallback;
3886	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpslld_imm_u128, iemAImpl_vpslld_imm_u128_fallback;
3887	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpslld_imm_u256, iemAImpl_vpslld_imm_u256_fallback;
3888	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsllq_imm_u128, iemAImpl_vpsllq_imm_u128_fallback;
3889	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsllq_imm_u256, iemAImpl_vpsllq_imm_u256_fallback;
3890	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
3891	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
3892	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
3893	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
3894
3895	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsraw_imm_u128, iemAImpl_vpsraw_imm_u128_fallback;
3896	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsraw_imm_u256, iemAImpl_vpsraw_imm_u256_fallback;
3897	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrad_imm_u128, iemAImpl_vpsrad_imm_u128_fallback;
3898	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrad_imm_u256, iemAImpl_vpsrad_imm_u256_fallback;
3899
3900	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrlw_imm_u128, iemAImpl_vpsrlw_imm_u128_fallback;
3901	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrlw_imm_u256, iemAImpl_vpsrlw_imm_u256_fallback;
3902	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrld_imm_u128, iemAImpl_vpsrld_imm_u128_fallback;
3903	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrld_imm_u256, iemAImpl_vpsrld_imm_u256_fallback;
3904	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrlq_imm_u128, iemAImpl_vpsrlq_imm_u128_fallback;
3905	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrlq_imm_u256, iemAImpl_vpsrlq_imm_u256_fallback;
3906	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
3907	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
3908	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
3909	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
3910
3911	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpermilps_u128, iemAImpl_vpermilps_u128_fallback;
3912	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_vpermilps_imm_u128, iemAImpl_vpermilps_imm_u128_fallback;
3913	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpermilps_u256, iemAImpl_vpermilps_u256_fallback;
3914	FNIEMAIMPLMEDIAOPTF2U256IMM8 iemAImpl_vpermilps_imm_u256, iemAImpl_vpermilps_imm_u256_fallback;
3915
3916	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpermilpd_u128, iemAImpl_vpermilpd_u128_fallback;
3917	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_vpermilpd_imm_u128, iemAImpl_vpermilpd_imm_u128_fallback;
3918	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpermilpd_u256, iemAImpl_vpermilpd_u256_fallback;
3919	FNIEMAIMPLMEDIAOPTF2U256IMM8 iemAImpl_vpermilpd_imm_u256, iemAImpl_vpermilpd_imm_u256_fallback;
3920
3921	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllvd_u128, iemAImpl_vpsllvd_u128_fallback;
3922	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllvd_u256, iemAImpl_vpsllvd_u256_fallback;
3923	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllvq_u128, iemAImpl_vpsllvq_u128_fallback;
3924	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllvq_u256, iemAImpl_vpsllvq_u256_fallback;
3925	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsravd_u128, iemAImpl_vpsravd_u128_fallback;
3926	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsravd_u256, iemAImpl_vpsravd_u256_fallback;
3927	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlvd_u128, iemAImpl_vpsrlvd_u128_fallback;
3928	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlvd_u256, iemAImpl_vpsrlvd_u256_fallback;
3929	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlvq_u128, iemAImpl_vpsrlvq_u128_fallback;
3930	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlvq_u256, iemAImpl_vpsrlvq_u256_fallback;
3931	/** @} */
3932
3933	/** @name Media Odds and Ends
3934	* @{ */
3935	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U8,(uint32_t *puDst, uint8_t uSrc));
3936	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U16,(uint32_t *puDst, uint16_t uSrc));
3937	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U32,(uint32_t *puDst, uint32_t uSrc));
3938	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U64,(uint32_t *puDst, uint64_t uSrc));
3939	FNIEMAIMPLCR32U8 iemAImpl_crc32_u8, iemAImpl_crc32_u8_fallback;
3940	FNIEMAIMPLCR32U16 iemAImpl_crc32_u16, iemAImpl_crc32_u16_fallback;
3941	FNIEMAIMPLCR32U32 iemAImpl_crc32_u32, iemAImpl_crc32_u32_fallback;
3942	FNIEMAIMPLCR32U64 iemAImpl_crc32_u64, iemAImpl_crc32_u64_fallback;
3943
3944	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL128,(PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint32_t *pEFlags));
3945	typedef FNIEMAIMPLF2EFL128 *PFNIEMAIMPLF2EFL128;
3946	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL256,(PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint32_t *pEFlags));
3947	typedef FNIEMAIMPLF2EFL256 *PFNIEMAIMPLF2EFL256;
3948	FNIEMAIMPLF2EFL128 iemAImpl_ptest_u128;
3949	FNIEMAIMPLF2EFL256 iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback;
3950	FNIEMAIMPLF2EFL128 iemAImpl_vtestps_u128, iemAImpl_vtestps_u128_fallback;
3951	FNIEMAIMPLF2EFL256 iemAImpl_vtestps_u256, iemAImpl_vtestps_u256_fallback;
3952	FNIEMAIMPLF2EFL128 iemAImpl_vtestpd_u128, iemAImpl_vtestpd_u128_fallback;
3953	FNIEMAIMPLF2EFL256 iemAImpl_vtestpd_u256, iemAImpl_vtestpd_u256_fallback;
3954
3955	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I32U64,(uint32_t uMxCsrIn, int32_t pi32Dst, const uint64_t pu64Src)); /* pu64Src is a double precision floating point. */
3956	typedef FNIEMAIMPLSSEF2I32U64 *PFNIEMAIMPLSSEF2I32U64;
3957	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I64U64,(uint32_t uMxCsrIn, int64_t pi64Dst, const uint64_t pu64Src)); /* pu64Src is a double precision floating point. */
3958	typedef FNIEMAIMPLSSEF2I64U64 *PFNIEMAIMPLSSEF2I64U64;
3959	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I32U32,(uint32_t uMxCsrIn, int32_t pi32Dst, const uint32_t pu32Src)); /* pu32Src is a single precision floating point. */
3960	typedef FNIEMAIMPLSSEF2I32U32 *PFNIEMAIMPLSSEF2I32U32;
3961	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I64U32,(uint32_t uMxCsrIn, int64_t pi64Dst, const uint32_t pu32Src)); /* pu32Src is a single precision floating point. */
3962	typedef FNIEMAIMPLSSEF2I64U32 *PFNIEMAIMPLSSEF2I64U32;
3963
3964	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvttsd2si_i32_r64;
3965	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvtsd2si_i32_r64;
3966
3967	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvttsd2si_i64_r64;
3968	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvtsd2si_i64_r64;
3969
3970	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvttss2si_i32_r32;
3971	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvtss2si_i32_r32;
3972
3973	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvttss2si_i64_r32;
3974	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvtss2si_i64_r32;
3975
3976	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R32I32,(uint32_t uMxCsrIn, PRTFLOAT32U pr32Dst, const int32_t *pi32Src));
3977	typedef FNIEMAIMPLSSEF2R32I32 *PFNIEMAIMPLSSEF2R32I32;
3978	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R32I64,(uint32_t uMxCsrIn, PRTFLOAT32U pr32Dst, const int64_t *pi64Src));
3979	typedef FNIEMAIMPLSSEF2R32I64 *PFNIEMAIMPLSSEF2R32I64;
3980
3981	FNIEMAIMPLSSEF2R32I32 iemAImpl_cvtsi2ss_r32_i32;
3982	FNIEMAIMPLSSEF2R32I64 iemAImpl_cvtsi2ss_r32_i64;
3983
3984	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R64I32,(uint32_t uMxCsrIn, PRTFLOAT64U pr64Dst, const int32_t *pi32Src));
3985	typedef FNIEMAIMPLSSEF2R64I32 *PFNIEMAIMPLSSEF2R64I32;
3986	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R64I64,(uint32_t uMxCsrIn, PRTFLOAT64U pr64Dst, const int64_t *pi64Src));
3987	typedef FNIEMAIMPLSSEF2R64I64 *PFNIEMAIMPLSSEF2R64I64;
3988
3989	FNIEMAIMPLSSEF2R64I32 iemAImpl_cvtsi2sd_r64_i32;
3990	FNIEMAIMPLSSEF2R64I64 iemAImpl_cvtsi2sd_r64_i64;
3991
3992
3993	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLF2EFLMXCSRR32R32,(uint32_t uMxCsrIn, uint32_t *pfEFlags, RTFLOAT32U uSrc1, RTFLOAT32U uSrc2));
3994	typedef FNIEMAIMPLF2EFLMXCSRR32R32 *PFNIEMAIMPLF2EFLMXCSRR32R32;
3995
3996	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLF2EFLMXCSRR64R64,(uint32_t uMxCsrIn, uint32_t *pfEFlags, RTFLOAT64U uSrc1, RTFLOAT64U uSrc2));
3997	typedef FNIEMAIMPLF2EFLMXCSRR64R64 *PFNIEMAIMPLF2EFLMXCSRR64R64;
3998
3999	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_ucomiss_u128;
4000	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback;
4001
4002	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_ucomisd_u128;
4003	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback;
4004
4005	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_comiss_u128;
4006	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback;
4007
4008	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_comisd_u128;
4009	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback;
4010
4011
4012	typedef struct IEMMEDIAF2XMMSRC
4013	{
4014	X86XMMREG uSrc1;
4015	X86XMMREG uSrc2;
4016	} IEMMEDIAF2XMMSRC;
4017	typedef IEMMEDIAF2XMMSRC *PIEMMEDIAF2XMMSRC;
4018	typedef const IEMMEDIAF2XMMSRC *PCIEMMEDIAF2XMMSRC;
4019
4020	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRF2XMMIMM8,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCIEMMEDIAF2XMMSRC puSrc, uint8_t bEvil));
4021	typedef FNIEMAIMPLMXCSRF2XMMIMM8 *PFNIEMAIMPLMXCSRF2XMMIMM8;
4022
4023	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpps_u128;
4024	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmppd_u128;
4025	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpss_u128;
4026	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpsd_u128;
4027	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundss_u128;
4028	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundsd_u128;
4029
4030	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundps_u128, iemAImpl_roundps_u128_fallback;
4031	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundpd_u128, iemAImpl_roundpd_u128_fallback;
4032
4033	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_dpps_u128, iemAImpl_dpps_u128_fallback;
4034	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_dppd_u128, iemAImpl_dppd_u128_fallback;
4035
4036	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRU64U128,(uint32_t fMxCsrIn, uint64_t *pu64Dst, PCX86XMMREG pSrc));
4037	typedef FNIEMAIMPLMXCSRU64U128 *PFNIEMAIMPLMXCSRU64U128;
4038
4039	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvtpd2pi_u128;
4040	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvttpd2pi_u128;
4041
4042	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRU128U64,(uint32_t fMxCsrIn, PX86XMMREG pDst, uint64_t u64Src));
4043	typedef FNIEMAIMPLMXCSRU128U64 *PFNIEMAIMPLMXCSRU128U64;
4044
4045	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2ps_u128;
4046	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2pd_u128;
4047
4048	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRU64U64,(uint32_t fMxCsrIn, uint64_t *pu64Dst, uint64_t u64Src));
4049	typedef FNIEMAIMPLMXCSRU64U64 *PFNIEMAIMPLMXCSRU64U64;
4050
4051	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvtps2pi_u128;
4052	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvttps2pi_u128;
4053
4054	/** @} */
4055
4056
4057	/** @name Function tables.
4058	* @{
4059	*/
4060
4061	/**
4062	* Function table for a binary operator providing implementation based on
4063	* operand size.
4064	*/
4065	typedef struct IEMOPBINSIZES
4066	{
4067	PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
4068	PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
4069	PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
4070	PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
4071	} IEMOPBINSIZES;
4072	/** Pointer to a binary operator function table. */
4073	typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
4074
4075
4076	/**
4077	* Function table for a unary operator providing implementation based on
4078	* operand size.
4079	*/
4080	typedef struct IEMOPUNARYSIZES
4081	{
4082	PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
4083	PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
4084	PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
4085	PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
4086	} IEMOPUNARYSIZES;
4087	/** Pointer to a unary operator function table. */
4088	typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
4089
4090
4091	/**
4092	* Function table for a shift operator providing implementation based on
4093	* operand size.
4094	*/
4095	typedef struct IEMOPSHIFTSIZES
4096	{
4097	PFNIEMAIMPLSHIFTU8 pfnNormalU8;
4098	PFNIEMAIMPLSHIFTU16 pfnNormalU16;
4099	PFNIEMAIMPLSHIFTU32 pfnNormalU32;
4100	PFNIEMAIMPLSHIFTU64 pfnNormalU64;
4101	} IEMOPSHIFTSIZES;
4102	/** Pointer to a shift operator function table. */
4103	typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
4104
4105
4106	/**
4107	* Function table for a multiplication or division operation.
4108	*/
4109	typedef struct IEMOPMULDIVSIZES
4110	{
4111	PFNIEMAIMPLMULDIVU8 pfnU8;
4112	PFNIEMAIMPLMULDIVU16 pfnU16;
4113	PFNIEMAIMPLMULDIVU32 pfnU32;
4114	PFNIEMAIMPLMULDIVU64 pfnU64;
4115	} IEMOPMULDIVSIZES;
4116	/** Pointer to a multiplication or division operation function table. */
4117	typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
4118
4119
4120	/**
4121	* Function table for a double precision shift operator providing implementation
4122	* based on operand size.
4123	*/
4124	typedef struct IEMOPSHIFTDBLSIZES
4125	{
4126	PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
4127	PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
4128	PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
4129	} IEMOPSHIFTDBLSIZES;
4130	/** Pointer to a double precision shift function table. */
4131	typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
4132
4133
4134	/**
4135	* Function table for media instruction taking two full sized media source
4136	* registers and one full sized destination register (AVX).
4137	*/
4138	typedef struct IEMOPMEDIAF3
4139	{
4140	PFNIEMAIMPLMEDIAF3U128 pfnU128;
4141	PFNIEMAIMPLMEDIAF3U256 pfnU256;
4142	} IEMOPMEDIAF3;
4143	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
4144	typedef IEMOPMEDIAF3 const *PCIEMOPMEDIAF3;
4145
4146	/** @def IEMOPMEDIAF3_INIT_VARS_EX
4147	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4148	* given functions as initializers. For use in AVX functions where a pair of
4149	* functions are only used once and the function table need not be public. */
4150	#ifndef TST_IEM_CHECK_MC
4151	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4152	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4153	static IEMOPMEDIAF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4154	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4155	# else
4156	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4157	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4158	# endif
4159	#else
4160	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4161	#endif
4162	/** @def IEMOPMEDIAF3_INIT_VARS
4163	* Generate AVX function tables for the @a a_InstrNm instruction.
4164	* @sa IEMOPMEDIAF3_INIT_VARS_EX */
4165	#define IEMOPMEDIAF3_INIT_VARS(a_InstrNm) \
4166	IEMOPMEDIAF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4167	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4168
4169	/**
4170	* Function table for media instruction taking two full sized media source
4171	* registers and one full sized destination register, but no additional state
4172	* (AVX).
4173	*/
4174	typedef struct IEMOPMEDIAOPTF3
4175	{
4176	PFNIEMAIMPLMEDIAOPTF3U128 pfnU128;
4177	PFNIEMAIMPLMEDIAOPTF3U256 pfnU256;
4178	} IEMOPMEDIAOPTF3;
4179	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
4180	typedef IEMOPMEDIAOPTF3 const *PCIEMOPMEDIAOPTF3;
4181
4182	/** @def IEMOPMEDIAOPTF3_INIT_VARS_EX
4183	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4184	* given functions as initializers. For use in AVX functions where a pair of
4185	* functions are only used once and the function table need not be public. */
4186	#ifndef TST_IEM_CHECK_MC
4187	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4188	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4189	static IEMOPMEDIAOPTF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4190	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4191	# else
4192	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4193	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4194	# endif
4195	#else
4196	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4197	#endif
4198	/** @def IEMOPMEDIAOPTF3_INIT_VARS
4199	* Generate AVX function tables for the @a a_InstrNm instruction.
4200	* @sa IEMOPMEDIAOPTF3_INIT_VARS_EX */
4201	#define IEMOPMEDIAOPTF3_INIT_VARS(a_InstrNm) \
4202	IEMOPMEDIAOPTF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4203	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4204
4205	/**
4206	* Function table for media instruction taking one full sized media source
4207	* registers and one full sized destination register, but no additional state
4208	* (AVX).
4209	*/
4210	typedef struct IEMOPMEDIAOPTF2
4211	{
4212	PFNIEMAIMPLMEDIAOPTF2U128 pfnU128;
4213	PFNIEMAIMPLMEDIAOPTF2U256 pfnU256;
4214	} IEMOPMEDIAOPTF2;
4215	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
4216	typedef IEMOPMEDIAOPTF2 const *PCIEMOPMEDIAOPTF2;
4217
4218	/** @def IEMOPMEDIAOPTF2_INIT_VARS_EX
4219	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4220	* given functions as initializers. For use in AVX functions where a pair of
4221	* functions are only used once and the function table need not be public. */
4222	#ifndef TST_IEM_CHECK_MC
4223	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4224	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4225	static IEMOPMEDIAOPTF2 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4226	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4227	# else
4228	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4229	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4230	# endif
4231	#else
4232	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4233	#endif
4234	/** @def IEMOPMEDIAOPTF2_INIT_VARS
4235	* Generate AVX function tables for the @a a_InstrNm instruction.
4236	* @sa IEMOPMEDIAOPTF2_INIT_VARS_EX */
4237	#define IEMOPMEDIAOPTF2_INIT_VARS(a_InstrNm) \
4238	IEMOPMEDIAOPTF2_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4239	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4240
4241	/**
4242	* Function table for media instruction taking one full sized media source
4243	* register and one full sized destination register and an 8-bit immediate, but no additional state
4244	* (AVX).
4245	*/
4246	typedef struct IEMOPMEDIAOPTF2IMM8
4247	{
4248	PFNIEMAIMPLMEDIAOPTF2U128IMM8 pfnU128;
4249	PFNIEMAIMPLMEDIAOPTF2U256IMM8 pfnU256;
4250	} IEMOPMEDIAOPTF2IMM8;
4251	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
4252	typedef IEMOPMEDIAOPTF2IMM8 const *PCIEMOPMEDIAOPTF2IMM8;
4253
4254	/** @def IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX
4255	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4256	* given functions as initializers. For use in AVX functions where a pair of
4257	* functions are only used once and the function table need not be public. */
4258	#ifndef TST_IEM_CHECK_MC
4259	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4260	# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4261	static IEMOPMEDIAOPTF2IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4262	static IEMOPMEDIAOPTF2IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4263	# else
4264	# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4265	static IEMOPMEDIAOPTF2IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4266	# endif
4267	#else
4268	# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4269	#endif
4270	/** @def IEMOPMEDIAOPTF2IMM8_INIT_VARS
4271	* Generate AVX function tables for the @a a_InstrNm instruction.
4272	* @sa IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX */
4273	#define IEMOPMEDIAOPTF2IMM8_INIT_VARS(a_InstrNm) \
4274	IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u256),\
4275	RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u256_fallback))
4276
4277	/**
4278	* Function table for media instruction taking two full sized media source
4279	* registers and one full sized destination register and an 8-bit immediate, but no additional state
4280	* (AVX).
4281	*/
4282	typedef struct IEMOPMEDIAOPTF3IMM8
4283	{
4284	PFNIEMAIMPLMEDIAOPTF3U128IMM8 pfnU128;
4285	PFNIEMAIMPLMEDIAOPTF3U256IMM8 pfnU256;
4286	} IEMOPMEDIAOPTF3IMM8;
4287	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
4288	typedef IEMOPMEDIAOPTF3IMM8 const *PCIEMOPMEDIAOPTF3IMM8;
4289
4290	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX
4291	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4292	* given functions as initializers. For use in AVX functions where a pair of
4293	* functions are only used once and the function table need not be public. */
4294	#ifndef TST_IEM_CHECK_MC
4295	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4296	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4297	static IEMOPMEDIAOPTF3IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4298	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4299	# else
4300	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4301	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4302	# endif
4303	#else
4304	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4305	#endif
4306	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS
4307	* Generate AVX function tables for the @a a_InstrNm instruction.
4308	* @sa IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX */
4309	#define IEMOPMEDIAOPTF3IMM8_INIT_VARS(a_InstrNm) \
4310	IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4311	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4312	/** @} */
4313
4314
4315	/**
4316	* Function table for blend type instruction taking three full sized media source
4317	* registers and one full sized destination register, but no additional state
4318	* (AVX).
4319	*/
4320	typedef struct IEMOPBLENDOP
4321	{
4322	PFNIEMAIMPLAVXBLENDU128 pfnU128;
4323	PFNIEMAIMPLAVXBLENDU256 pfnU256;
4324	} IEMOPBLENDOP;
4325	/** Pointer to a media operation function table for 4 full sized ops (AVX). */
4326	typedef IEMOPBLENDOP const *PCIEMOPBLENDOP;
4327
4328	/** @def IEMOPBLENDOP_INIT_VARS_EX
4329	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4330	* given functions as initializers. For use in AVX functions where a pair of
4331	* functions are only used once and the function table need not be public. */
4332	#ifndef TST_IEM_CHECK_MC
4333	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4334	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4335	static IEMOPBLENDOP const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4336	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4337	# else
4338	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4339	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4340	# endif
4341	#else
4342	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4343	#endif
4344	/** @def IEMOPBLENDOP_INIT_VARS
4345	* Generate AVX function tables for the @a a_InstrNm instruction.
4346	* @sa IEMOPBLENDOP_INIT_VARS_EX */
4347	#define IEMOPBLENDOP_INIT_VARS(a_InstrNm) \
4348	IEMOPBLENDOP_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4349	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4350
4351
4352	/** @name SSE/AVX single/double precision floating point operations.
4353	* @{ */
4354	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
4355	typedef FNIEMAIMPLFPSSEF2U128 *PFNIEMAIMPLFPSSEF2U128;
4356	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128R32,(uint32_t uMxCsrIn, PX86XMMREG Result, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
4357	typedef FNIEMAIMPLFPSSEF2U128R32 *PFNIEMAIMPLFPSSEF2U128R32;
4358	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128R64,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
4359	typedef FNIEMAIMPLFPSSEF2U128R64 *PFNIEMAIMPLFPSSEF2U128R64;
4360
4361	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
4362	typedef FNIEMAIMPLFPAVXF3U128 *PFNIEMAIMPLFPAVXF3U128;
4363	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U128R32,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
4364	typedef FNIEMAIMPLFPAVXF3U128R32 *PFNIEMAIMPLFPAVXF3U128R32;
4365	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U128R64,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
4366	typedef FNIEMAIMPLFPAVXF3U128R64 *PFNIEMAIMPLFPAVXF3U128R64;
4367
4368	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U256,(uint32_t uMxCsrIn, PX86YMMREG pResult, PCX86YMMREG puSrc1, PCX86YMMREG puSrc2));
4369	typedef FNIEMAIMPLFPAVXF3U256 *PFNIEMAIMPLFPAVXF3U256;
4370
4371	FNIEMAIMPLFPSSEF2U128 iemAImpl_addps_u128;
4372	FNIEMAIMPLFPSSEF2U128 iemAImpl_addpd_u128;
4373	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulps_u128;
4374	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulpd_u128;
4375	FNIEMAIMPLFPSSEF2U128 iemAImpl_subps_u128;
4376	FNIEMAIMPLFPSSEF2U128 iemAImpl_subpd_u128;
4377	FNIEMAIMPLFPSSEF2U128 iemAImpl_minps_u128;
4378	FNIEMAIMPLFPSSEF2U128 iemAImpl_minpd_u128;
4379	FNIEMAIMPLFPSSEF2U128 iemAImpl_divps_u128;
4380	FNIEMAIMPLFPSSEF2U128 iemAImpl_divpd_u128;
4381	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxps_u128;
4382	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxpd_u128;
4383	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddps_u128;
4384	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddpd_u128;
4385	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubps_u128;
4386	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubpd_u128;
4387	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtps_u128;
4388	FNIEMAIMPLFPSSEF2U128 iemAImpl_rsqrtps_u128;
4389	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtpd_u128;
4390	FNIEMAIMPLFPSSEF2U128 iemAImpl_rcpps_u128;
4391	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubps_u128;
4392	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubpd_u128;
4393	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2ps_u128;
4394	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2pd_u128;
4395
4396	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2ps_u128;
4397	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2dq_u128;
4398	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttps2dq_u128;
4399	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttpd2dq_u128;
4400	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2pd_u128;
4401	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2dq_u128;
4402
4403	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_addss_u128_r32;
4404	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_addsd_u128_r64;
4405	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_mulss_u128_r32;
4406	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_mulsd_u128_r64;
4407	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_subss_u128_r32;
4408	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_subsd_u128_r64;
4409	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_minss_u128_r32;
4410	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_minsd_u128_r64;
4411	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_divss_u128_r32;
4412	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_divsd_u128_r64;
4413	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_maxss_u128_r32;
4414	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_maxsd_u128_r64;
4415	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_cvtss2sd_u128_r32;
4416	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_cvtsd2ss_u128_r64;
4417	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_sqrtss_u128_r32;
4418	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_sqrtsd_u128_r64;
4419	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_rsqrtss_u128_r32;
4420	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_rcpss_u128_r32;
4421
4422	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddps_u128, iemAImpl_vaddps_u128_fallback;
4423	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddpd_u128, iemAImpl_vaddpd_u128_fallback;
4424	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulps_u128, iemAImpl_vmulps_u128_fallback;
4425	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulpd_u128, iemAImpl_vmulpd_u128_fallback;
4426	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubps_u128, iemAImpl_vsubps_u128_fallback;
4427	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubpd_u128, iemAImpl_vsubpd_u128_fallback;
4428	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminps_u128, iemAImpl_vminps_u128_fallback;
4429	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminpd_u128, iemAImpl_vminpd_u128_fallback;
4430	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivps_u128, iemAImpl_vdivps_u128_fallback;
4431	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivpd_u128, iemAImpl_vdivpd_u128_fallback;
4432	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxps_u128, iemAImpl_vmaxps_u128_fallback;
4433	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxpd_u128, iemAImpl_vmaxpd_u128_fallback;
4434	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddps_u128, iemAImpl_vhaddps_u128_fallback;
4435	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddpd_u128, iemAImpl_vhaddpd_u128_fallback;
4436	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubps_u128, iemAImpl_vhsubps_u128_fallback;
4437	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubpd_u128, iemAImpl_vhsubpd_u128_fallback;
4438	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtps_u128, iemAImpl_vsqrtps_u128_fallback;
4439	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtpd_u128, iemAImpl_vsqrtpd_u128_fallback;
4440	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubps_u128, iemAImpl_vaddsubps_u128_fallback;
4441	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubpd_u128, iemAImpl_vaddsubpd_u128_fallback;
4442	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtpd2ps_u128, iemAImpl_vcvtpd2ps_u128_fallback;
4443	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtps2pd_u128, iemAImpl_vcvtps2pd_u128_fallback;
4444
4445	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vaddss_u128_r32, iemAImpl_vaddss_u128_r32_fallback;
4446	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vaddsd_u128_r64, iemAImpl_vaddsd_u128_r64_fallback;
4447	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmulss_u128_r32, iemAImpl_vmulss_u128_r32_fallback;
4448	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmulsd_u128_r64, iemAImpl_vmulsd_u128_r64_fallback;
4449	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsubss_u128_r32, iemAImpl_vsubss_u128_r32_fallback;
4450	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsubsd_u128_r64, iemAImpl_vsubsd_u128_r64_fallback;
4451	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vminss_u128_r32, iemAImpl_vminss_u128_r32_fallback;
4452	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vminsd_u128_r64, iemAImpl_vminsd_u128_r64_fallback;
4453	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vdivss_u128_r32, iemAImpl_vdivss_u128_r32_fallback;
4454	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vdivsd_u128_r64, iemAImpl_vdivsd_u128_r64_fallback;
4455	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmaxss_u128_r32, iemAImpl_vmaxss_u128_r32_fallback;
4456	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmaxsd_u128_r64, iemAImpl_vmaxsd_u128_r64_fallback;
4457	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsqrtss_u128_r32, iemAImpl_vsqrtss_u128_r32_fallback;
4458	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsqrtsd_u128_r64, iemAImpl_vsqrtsd_u128_r64_fallback;
4459
4460	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddps_u256, iemAImpl_vaddps_u256_fallback;
4461	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddpd_u256, iemAImpl_vaddpd_u256_fallback;
4462	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulps_u256, iemAImpl_vmulps_u256_fallback;
4463	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulpd_u256, iemAImpl_vmulpd_u256_fallback;
4464	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubps_u256, iemAImpl_vsubps_u256_fallback;
4465	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubpd_u256, iemAImpl_vsubpd_u256_fallback;
4466	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminps_u256, iemAImpl_vminps_u256_fallback;
4467	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminpd_u256, iemAImpl_vminpd_u256_fallback;
4468	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivps_u256, iemAImpl_vdivps_u256_fallback;
4469	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivpd_u256, iemAImpl_vdivpd_u256_fallback;
4470	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxps_u256, iemAImpl_vmaxps_u256_fallback;
4471	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxpd_u256, iemAImpl_vmaxpd_u256_fallback;
4472	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddps_u256, iemAImpl_vhaddps_u256_fallback;
4473	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddpd_u256, iemAImpl_vhaddpd_u256_fallback;
4474	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubps_u256, iemAImpl_vhsubps_u256_fallback;
4475	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubpd_u256, iemAImpl_vhsubpd_u256_fallback;
4476	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubps_u256, iemAImpl_vhaddsubps_u256_fallback;
4477	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubpd_u256, iemAImpl_vhaddsubpd_u256_fallback;
4478	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtpd2ps_u256, iemAImpl_vcvtpd2ps_u256_fallback;
4479	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtps2pd_u256, iemAImpl_vcvtps2pd_u256_fallback;
4480	/** @} */
4481
4482	/** @name C instruction implementations for anything slightly complicated.
4483	* @{ */
4484
4485	/**
4486	* For typedef'ing or declaring a C instruction implementation function taking
4487	* no extra arguments.
4488	*
4489	* @param a_Name The name of the type.
4490	*/
4491	# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
4492	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
4493	/**
4494	* For defining a C instruction implementation function taking no extra
4495	* arguments.
4496	*
4497	* @param a_Name The name of the function
4498	*/
4499	# define IEM_CIMPL_DEF_0(a_Name) \
4500	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
4501	/**
4502	* Prototype version of IEM_CIMPL_DEF_0.
4503	*/
4504	# define IEM_CIMPL_PROTO_0(a_Name) \
4505	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
4506	/**
4507	* For calling a C instruction implementation function taking no extra
4508	* arguments.
4509	*
4510	* This special call macro adds default arguments to the call and allow us to
4511	* change these later.
4512	*
4513	* @param a_fn The name of the function.
4514	*/
4515	# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
4516
4517	/** Type for a C instruction implementation function taking no extra
4518	* arguments. */
4519	typedef IEM_CIMPL_DECL_TYPE_0(FNIEMCIMPL0);
4520	/** Function pointer type for a C instruction implementation function taking
4521	* no extra arguments. */
4522	typedef FNIEMCIMPL0 *PFNIEMCIMPL0;
4523
4524	/**
4525	* For typedef'ing or declaring a C instruction implementation function taking
4526	* one extra argument.
4527	*
4528	* @param a_Name The name of the type.
4529	* @param a_Type0 The argument type.
4530	* @param a_Arg0 The argument name.
4531	*/
4532	# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
4533	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
4534	/**
4535	* For defining a C instruction implementation function taking one extra
4536	* argument.
4537	*
4538	* @param a_Name The name of the function
4539	* @param a_Type0 The argument type.
4540	* @param a_Arg0 The argument name.
4541	*/
4542	# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
4543	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
4544	/**
4545	* Prototype version of IEM_CIMPL_DEF_1.
4546	*/
4547	# define IEM_CIMPL_PROTO_1(a_Name, a_Type0, a_Arg0) \
4548	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
4549	/**
4550	* For calling a C instruction implementation function taking one extra
4551	* argument.
4552	*
4553	* This special call macro adds default arguments to the call and allow us to
4554	* change these later.
4555	*
4556	* @param a_fn The name of the function.
4557	* @param a0 The name of the 1st argument.
4558	*/
4559	# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
4560
4561	/**
4562	* For typedef'ing or declaring a C instruction implementation function taking
4563	* two extra arguments.
4564	*
4565	* @param a_Name The name of the type.
4566	* @param a_Type0 The type of the 1st argument
4567	* @param a_Arg0 The name of the 1st argument.
4568	* @param a_Type1 The type of the 2nd argument.
4569	* @param a_Arg1 The name of the 2nd argument.
4570	*/
4571	# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
4572	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
4573	/**
4574	* For defining a C instruction implementation function taking two extra
4575	* arguments.
4576	*
4577	* @param a_Name The name of the function.
4578	* @param a_Type0 The type of the 1st argument
4579	* @param a_Arg0 The name of the 1st argument.
4580	* @param a_Type1 The type of the 2nd argument.
4581	* @param a_Arg1 The name of the 2nd argument.
4582	*/
4583	# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
4584	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
4585	/**
4586	* Prototype version of IEM_CIMPL_DEF_2.
4587	*/
4588	# define IEM_CIMPL_PROTO_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
4589	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
4590	/**
4591	* For calling a C instruction implementation function taking two extra
4592	* arguments.
4593	*
4594	* This special call macro adds default arguments to the call and allow us to
4595	* change these later.
4596	*
4597	* @param a_fn The name of the function.
4598	* @param a0 The name of the 1st argument.
4599	* @param a1 The name of the 2nd argument.
4600	*/
4601	# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
4602
4603	/**
4604	* For typedef'ing or declaring a C instruction implementation function taking
4605	* three extra arguments.
4606	*
4607	* @param a_Name The name of the type.
4608	* @param a_Type0 The type of the 1st argument
4609	* @param a_Arg0 The name of the 1st argument.
4610	* @param a_Type1 The type of the 2nd argument.
4611	* @param a_Arg1 The name of the 2nd argument.
4612	* @param a_Type2 The type of the 3rd argument.
4613	* @param a_Arg2 The name of the 3rd argument.
4614	*/
4615	# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
4616	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
4617	/**
4618	* For defining a C instruction implementation function taking three extra
4619	* arguments.
4620	*
4621	* @param a_Name The name of the function.
4622	* @param a_Type0 The type of the 1st argument
4623	* @param a_Arg0 The name of the 1st argument.
4624	* @param a_Type1 The type of the 2nd argument.
4625	* @param a_Arg1 The name of the 2nd argument.
4626	* @param a_Type2 The type of the 3rd argument.
4627	* @param a_Arg2 The name of the 3rd argument.
4628	*/
4629	# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
4630	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
4631	/**
4632	* Prototype version of IEM_CIMPL_DEF_3.
4633	*/
4634	# define IEM_CIMPL_PROTO_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
4635	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
4636	/**
4637	* For calling a C instruction implementation function taking three extra
4638	* arguments.
4639	*
4640	* This special call macro adds default arguments to the call and allow us to
4641	* change these later.
4642	*
4643	* @param a_fn The name of the function.
4644	* @param a0 The name of the 1st argument.
4645	* @param a1 The name of the 2nd argument.
4646	* @param a2 The name of the 3rd argument.
4647	*/
4648	# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
4649
4650
4651	/**
4652	* For typedef'ing or declaring a C instruction implementation function taking
4653	* four extra arguments.
4654	*
4655	* @param a_Name The name of the type.
4656	* @param a_Type0 The type of the 1st argument
4657	* @param a_Arg0 The name of the 1st argument.
4658	* @param a_Type1 The type of the 2nd argument.
4659	* @param a_Arg1 The name of the 2nd argument.
4660	* @param a_Type2 The type of the 3rd argument.
4661	* @param a_Arg2 The name of the 3rd argument.
4662	* @param a_Type3 The type of the 4th argument.
4663	* @param a_Arg3 The name of the 4th argument.
4664	*/
4665	# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
4666	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
4667	/**
4668	* For defining a C instruction implementation function taking four extra
4669	* arguments.
4670	*
4671	* @param a_Name The name of the function.
4672	* @param a_Type0 The type of the 1st argument
4673	* @param a_Arg0 The name of the 1st argument.
4674	* @param a_Type1 The type of the 2nd argument.
4675	* @param a_Arg1 The name of the 2nd argument.
4676	* @param a_Type2 The type of the 3rd argument.
4677	* @param a_Arg2 The name of the 3rd argument.
4678	* @param a_Type3 The type of the 4th argument.
4679	* @param a_Arg3 The name of the 4th argument.
4680	*/
4681	# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
4682	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4683	a_Type2 a_Arg2, a_Type3 a_Arg3))
4684	/**
4685	* Prototype version of IEM_CIMPL_DEF_4.
4686	*/
4687	# define IEM_CIMPL_PROTO_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
4688	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4689	a_Type2 a_Arg2, a_Type3 a_Arg3))
4690	/**
4691	* For calling a C instruction implementation function taking four extra
4692	* arguments.
4693	*
4694	* This special call macro adds default arguments to the call and allow us to
4695	* change these later.
4696	*
4697	* @param a_fn The name of the function.
4698	* @param a0 The name of the 1st argument.
4699	* @param a1 The name of the 2nd argument.
4700	* @param a2 The name of the 3rd argument.
4701	* @param a3 The name of the 4th argument.
4702	*/
4703	# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
4704
4705
4706	/**
4707	* For typedef'ing or declaring a C instruction implementation function taking
4708	* five extra arguments.
4709	*
4710	* @param a_Name The name of the type.
4711	* @param a_Type0 The type of the 1st argument
4712	* @param a_Arg0 The name of the 1st argument.
4713	* @param a_Type1 The type of the 2nd argument.
4714	* @param a_Arg1 The name of the 2nd argument.
4715	* @param a_Type2 The type of the 3rd argument.
4716	* @param a_Arg2 The name of the 3rd argument.
4717	* @param a_Type3 The type of the 4th argument.
4718	* @param a_Arg3 The name of the 4th argument.
4719	* @param a_Type4 The type of the 5th argument.
4720	* @param a_Arg4 The name of the 5th argument.
4721	*/
4722	# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
4723	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, \
4724	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
4725	a_Type3 a_Arg3, a_Type4 a_Arg4))
4726	/**
4727	* For defining a C instruction implementation function taking five extra
4728	* arguments.
4729	*
4730	* @param a_Name The name of the function.
4731	* @param a_Type0 The type of the 1st argument
4732	* @param a_Arg0 The name of the 1st argument.
4733	* @param a_Type1 The type of the 2nd argument.
4734	* @param a_Arg1 The name of the 2nd argument.
4735	* @param a_Type2 The type of the 3rd argument.
4736	* @param a_Arg2 The name of the 3rd argument.
4737	* @param a_Type3 The type of the 4th argument.
4738	* @param a_Arg3 The name of the 4th argument.
4739	* @param a_Type4 The type of the 5th argument.
4740	* @param a_Arg4 The name of the 5th argument.
4741	*/
4742	# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
4743	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4744	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
4745	/**
4746	* Prototype version of IEM_CIMPL_DEF_5.
4747	*/
4748	# define IEM_CIMPL_PROTO_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
4749	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4750	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
4751	/**
4752	* For calling a C instruction implementation function taking five extra
4753	* arguments.
4754	*
4755	* This special call macro adds default arguments to the call and allow us to
4756	* change these later.
4757	*
4758	* @param a_fn The name of the function.
4759	* @param a0 The name of the 1st argument.
4760	* @param a1 The name of the 2nd argument.
4761	* @param a2 The name of the 3rd argument.
4762	* @param a3 The name of the 4th argument.
4763	* @param a4 The name of the 5th argument.
4764	*/
4765	# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
4766
4767	/** @} */
4768
4769
4770	/** @name Opcode Decoder Function Types.
4771	* @{ */
4772
4773	/** @typedef PFNIEMOP
4774	* Pointer to an opcode decoder function.
4775	*/
4776
4777	/** @def FNIEMOP_DEF
4778	* Define an opcode decoder function.
4779	*
4780	* We're using macors for this so that adding and removing parameters as well as
4781	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL
4782	*
4783	* @param a_Name The function name.
4784	*/
4785
4786	/** @typedef PFNIEMOPRM
4787	* Pointer to an opcode decoder function with RM byte.
4788	*/
4789
4790	/** @def FNIEMOPRM_DEF
4791	* Define an opcode decoder function with RM byte.
4792	*
4793	* We're using macors for this so that adding and removing parameters as well as
4794	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL_1
4795	*
4796	* @param a_Name The function name.
4797	*/
4798
4799	#if defined(__GNUC__) && defined(RT_ARCH_X86)
4800	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOP)(PVMCPUCC pVCpu);
4801	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4802	# define FNIEMOP_DEF(a_Name) \
4803	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu)
4804	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4805	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
4806	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4807	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
4808
4809	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
4810	typedef VBOXSTRICTRC (__fastcall * PFNIEMOP)(PVMCPUCC pVCpu);
4811	typedef VBOXSTRICTRC (__fastcall * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4812	# define FNIEMOP_DEF(a_Name) \
4813	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
4814	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4815	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
4816	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4817	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
4818
4819	#elif defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
4820	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
4821	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4822	# define FNIEMOP_DEF(a_Name) \
4823	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu)
4824	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4825	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
4826	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4827	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
4828
4829	#else
4830	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
4831	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4832	# define FNIEMOP_DEF(a_Name) \
4833	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
4834	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4835	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
4836	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4837	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
4838
4839	#endif
4840	#define FNIEMOPRM_DEF(a_Name) FNIEMOP_DEF_1(a_Name, uint8_t, bRm)
4841
4842	/**
4843	* Call an opcode decoder function.
4844	*
4845	* We're using macors for this so that adding and removing parameters can be
4846	* done as we please. See FNIEMOP_DEF.
4847	*/
4848	#define FNIEMOP_CALL(a_pfn) (a_pfn)(pVCpu)
4849
4850	/**
4851	* Call a common opcode decoder function taking one extra argument.
4852	*
4853	* We're using macors for this so that adding and removing parameters can be
4854	* done as we please. See FNIEMOP_DEF_1.
4855	*/
4856	#define FNIEMOP_CALL_1(a_pfn, a0) (a_pfn)(pVCpu, a0)
4857
4858	/**
4859	* Call a common opcode decoder function taking one extra argument.
4860	*
4861	* We're using macors for this so that adding and removing parameters can be
4862	* done as we please. See FNIEMOP_DEF_1.
4863	*/
4864	#define FNIEMOP_CALL_2(a_pfn, a0, a1) (a_pfn)(pVCpu, a0, a1)
4865	/** @} */
4866
4867
4868	/** @name Misc Helpers
4869	* @{ */
4870
4871	/** Used to shut up GCC warnings about variables that 'may be used uninitialized'
4872	* due to GCC lacking knowledge about the value range of a switch. */
4873	#if RT_CPLUSPLUS_PREREQ(202000)
4874	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: [[unlikely]] AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
4875	#else
4876	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
4877	#endif
4878
4879	/** Variant of IEM_NOT_REACHED_DEFAULT_CASE_RET that returns a custom value. */
4880	#if RT_CPLUSPLUS_PREREQ(202000)
4881	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: [[unlikely]] AssertFailedReturn(a_RetValue)
4882	#else
4883	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: AssertFailedReturn(a_RetValue)
4884	#endif
4885
4886	/**
4887	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
4888	* occation.
4889	*/
4890	#ifdef LOG_ENABLED
4891	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
4892	do { \
4893	/Log/ LogAlways(("%s: returning IEM_RETURN_ASPECT_NOT_IMPLEMENTED (line %d)\n", __FUNCTION__, __LINE__)); \
4894	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
4895	} while (0)
4896	#else
4897	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
4898	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
4899	#endif
4900
4901	/**
4902	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
4903	* occation using the supplied logger statement.
4904	*
4905	* @param a_LoggerArgs What to log on failure.
4906	*/
4907	#ifdef LOG_ENABLED
4908	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
4909	do { \
4910	LogAlways((LOG_FN_FMT ": ", __PRETTY_FUNCTION__)); LogAlways(a_LoggerArgs); \
4911	/LogFunc(a_LoggerArgs);/ \
4912	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
4913	} while (0)
4914	#else
4915	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
4916	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
4917	#endif
4918
4919	/**
4920	* Gets the CPU mode (from fExec) as a IEMMODE value.
4921	*
4922	* @returns IEMMODE
4923	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4924	*/
4925	#define IEM_GET_CPU_MODE(a_pVCpu) ((a_pVCpu)->iem.s.fExec & IEM_F_MODE_CPUMODE_MASK)
4926
4927	/**
4928	* Check if we're currently executing in real or virtual 8086 mode.
4929	*
4930	* @returns @c true if it is, @c false if not.
4931	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4932	*/
4933	#define IEM_IS_REAL_OR_V86_MODE(a_pVCpu) (( ((a_pVCpu)->iem.s.fExec ^ IEM_F_MODE_X86_PROT_MASK) \
4934	& (IEM_F_MODE_X86_V86_MASK \| IEM_F_MODE_X86_PROT_MASK)) != 0)
4935
4936	/**
4937	* Check if we're currently executing in virtual 8086 mode.
4938	*
4939	* @returns @c true if it is, @c false if not.
4940	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4941	*/
4942	#define IEM_IS_V86_MODE(a_pVCpu) (((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_V86_MASK) != 0)
4943
4944	/**
4945	* Check if we're currently executing in long mode.
4946	*
4947	* @returns @c true if it is, @c false if not.
4948	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4949	*/
4950	#define IEM_IS_LONG_MODE(a_pVCpu) (CPUMIsGuestInLongModeEx(IEM_GET_CTX(a_pVCpu)))
4951
4952	/**
4953	* Check if we're currently executing in a 16-bit code segment.
4954	*
4955	* @returns @c true if it is, @c false if not.
4956	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4957	*/
4958	#define IEM_IS_16BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_16BIT)
4959
4960	/**
4961	* Check if we're currently executing in a 32-bit code segment.
4962	*
4963	* @returns @c true if it is, @c false if not.
4964	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4965	*/
4966	#define IEM_IS_32BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_32BIT)
4967
4968	/**
4969	* Check if we're currently executing in a 64-bit code segment.
4970	*
4971	* @returns @c true if it is, @c false if not.
4972	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4973	*/
4974	#define IEM_IS_64BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_64BIT)
4975
4976	/**
4977	* Check if we're currently executing in real mode.
4978	*
4979	* @returns @c true if it is, @c false if not.
4980	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4981	*/
4982	#define IEM_IS_REAL_MODE(a_pVCpu) (!((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_PROT_MASK))
4983
4984	/**
4985	* Gets the current protection level (CPL).
4986	*
4987	* @returns 0..3
4988	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4989	*/
4990	#define IEM_GET_CPL(a_pVCpu) (((a_pVCpu)->iem.s.fExec >> IEM_F_X86_CPL_SHIFT) & IEM_F_X86_CPL_SMASK)
4991
4992	/**
4993	* Sets the current protection level (CPL).
4994	*
4995	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
4996	*/
4997	#define IEM_SET_CPL(a_pVCpu, a_uCpl) \
4998	do { (a_pVCpu)->iem.s.fExec = ((a_pVCpu)->iem.s.fExec & ~IEM_F_X86_CPL_MASK) \| ((a_uCpl) << IEM_F_X86_CPL_SHIFT); } while (0)
4999
5000	/**
5001	* Returns a (const) pointer to the CPUMFEATURES for the guest CPU.
5002	* @returns PCCPUMFEATURES
5003	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5004	*/
5005	#define IEM_GET_GUEST_CPU_FEATURES(a_pVCpu) (&((a_pVCpu)->CTX_SUFF(pVM)->cpum.ro.GuestFeatures))
5006
5007	/**
5008	* Returns a (const) pointer to the CPUMFEATURES for the host CPU.
5009	* @returns PCCPUMFEATURES
5010	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5011	*/
5012	#define IEM_GET_HOST_CPU_FEATURES(a_pVCpu) (&g_CpumHostFeatures.s)
5013
5014	/**
5015	* Evaluates to true if we're presenting an Intel CPU to the guest.
5016	*/
5017	#define IEM_IS_GUEST_CPU_INTEL(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL )
5018
5019	/**
5020	* Evaluates to true if we're presenting an AMD CPU to the guest.
5021	*/
5022	#define IEM_IS_GUEST_CPU_AMD(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_AMD \|\| (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_HYGON )
5023
5024	/**
5025	* Check if the address is canonical.
5026	*/
5027	#define IEM_IS_CANONICAL(a_u64Addr) X86_IS_CANONICAL(a_u64Addr)
5028
5029	/** Checks if the ModR/M byte is in register mode or not. */
5030	#define IEM_IS_MODRM_REG_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT) )
5031	/** Checks if the ModR/M byte is in memory mode or not. */
5032	#define IEM_IS_MODRM_MEM_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT) )
5033
5034	/**
5035	* Gets the register (reg) part of a ModR/M encoding, with REX.R added in.
5036	*
5037	* For use during decoding.
5038	*/
5039	#define IEM_GET_MODRM_REG(a_pVCpu, a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| (a_pVCpu)->iem.s.uRexReg )
5040	/**
5041	* Gets the r/m part of a ModR/M encoding as a register index, with REX.B added in.
5042	*
5043	* For use during decoding.
5044	*/
5045	#define IEM_GET_MODRM_RM(a_pVCpu, a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) \| (a_pVCpu)->iem.s.uRexB )
5046
5047	/**
5048	* Gets the register (reg) part of a ModR/M encoding, without REX.R.
5049	*
5050	* For use during decoding.
5051	*/
5052	#define IEM_GET_MODRM_REG_8(a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) )
5053	/**
5054	* Gets the r/m part of a ModR/M encoding as a register index, without REX.B.
5055	*
5056	* For use during decoding.
5057	*/
5058	#define IEM_GET_MODRM_RM_8(a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) )
5059
5060	/**
5061	* Gets the register (reg) part of a ModR/M encoding as an extended 8-bit
5062	* register index, with REX.R added in.
5063	*
5064	* For use during decoding.
5065	*
5066	* @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
5067	*/
5068	#define IEM_GET_MODRM_REG_EX8(a_pVCpu, a_bRm) \
5069	( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
5070	\|\| !((a_bRm) & (4 << X86_MODRM_REG_SHIFT)) /* IEM_GET_MODRM_REG(pVCpu, a_bRm) < 4 */ \
5071	? IEM_GET_MODRM_REG(pVCpu, a_bRm) : (((a_bRm) >> X86_MODRM_REG_SHIFT) & 3) \| 16)
5072	/**
5073	* Gets the r/m part of a ModR/M encoding as an extended 8-bit register index,
5074	* with REX.B added in.
5075	*
5076	* For use during decoding.
5077	*
5078	* @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
5079	*/
5080	#define IEM_GET_MODRM_RM_EX8(a_pVCpu, a_bRm) \
5081	( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
5082	\|\| !((a_bRm) & 4) /* IEM_GET_MODRM_RM(pVCpu, a_bRm) < 4 */ \
5083	? IEM_GET_MODRM_RM(pVCpu, a_bRm) : ((a_bRm) & 3) \| 16)
5084
5085	/**
5086	* Combines the prefix REX and ModR/M byte for passing to
5087	* iemOpHlpCalcRmEffAddrThreadedAddr64().
5088	*
5089	* @returns The ModRM byte but with bit 3 set to REX.B and bit 4 to REX.X.
5090	* The two bits are part of the REG sub-field, which isn't needed in
5091	* iemOpHlpCalcRmEffAddrThreadedAddr64().
5092	*
5093	* For use during decoding/recompiling.
5094	*/
5095	#define IEM_GET_MODRM_EX(a_pVCpu, a_bRm) \
5096	( ((a_bRm) & ~X86_MODRM_REG_MASK) \
5097	\| (uint8_t)( (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X)) >> (25 - 3) ) )
5098	AssertCompile(IEM_OP_PRF_REX_B == RT_BIT_32(25));
5099	AssertCompile(IEM_OP_PRF_REX_X == RT_BIT_32(26));
5100
5101	/**
5102	* Gets the effective VEX.VVVV value.
5103	*
5104	* The 4th bit is ignored if not 64-bit code.
5105	* @returns effective V-register value.
5106	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5107	*/
5108	#define IEM_GET_EFFECTIVE_VVVV(a_pVCpu) \
5109	(IEM_IS_64BIT_CODE(a_pVCpu) ? (a_pVCpu)->iem.s.uVex3rdReg : (a_pVCpu)->iem.s.uVex3rdReg & 7)
5110
5111
5112	/**
5113	* Gets the register (reg) part of a the special 4th register byte used by
5114	* vblendvps and vblendvpd.
5115	*
5116	* For use during decoding.
5117	*/
5118	#define IEM_GET_IMM8_REG(a_pVCpu, a_bRegImm8) \
5119	(IEM_IS_64BIT_CODE(a_pVCpu) ? (a_bRegImm8) >> 4 : ((a_bRegImm8) >> 4) & 7)
5120
5121
5122	/**
5123	* Checks if we're executing inside an AMD-V or VT-x guest.
5124	*/
5125	#if defined(VBOX_WITH_NESTED_HWVIRT_VMX) \|\| defined(VBOX_WITH_NESTED_HWVIRT_SVM)
5126	# define IEM_IS_IN_GUEST(a_pVCpu) RT_BOOL((a_pVCpu)->iem.s.fExec & IEM_F_X86_CTX_IN_GUEST)
5127	#else
5128	# define IEM_IS_IN_GUEST(a_pVCpu) false
5129	#endif
5130
5131
5132	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5133
5134	/**
5135	* Check if the guest has entered VMX root operation.
5136	*/
5137	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxRootMode(IEM_GET_CTX(a_pVCpu)))
5138
5139	/**
5140	* Check if the guest has entered VMX non-root operation.
5141	*/
5142	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) ( ((a_pVCpu)->iem.s.fExec & (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST)) \
5143	== (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST) )
5144
5145	/**
5146	* Check if the nested-guest has the given Pin-based VM-execution control set.
5147	*/
5148	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_PinCtl) (CPUMIsGuestVmxPinCtlsSet(IEM_GET_CTX(a_pVCpu), (a_PinCtl)))
5149
5150	/**
5151	* Check if the nested-guest has the given Processor-based VM-execution control set.
5152	*/
5153	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_ProcCtl) (CPUMIsGuestVmxProcCtlsSet(IEM_GET_CTX(a_pVCpu), (a_ProcCtl)))
5154
5155	/**
5156	* Check if the nested-guest has the given Secondary Processor-based VM-execution
5157	* control set.
5158	*/
5159	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_ProcCtl2) (CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(a_pVCpu), (a_ProcCtl2)))
5160
5161	/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
5162	# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
5163
5164	/** Whether a shadow VMCS is present for the given VCPU. */
5165	# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
5166
5167	/** Gets the VMXON region pointer. */
5168	# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
5169
5170	/** Gets the guest-physical address of the current VMCS for the given VCPU. */
5171	# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
5172
5173	/** Whether a current VMCS is present for the given VCPU. */
5174	# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
5175
5176	/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
5177	# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
5178	do \
5179	{ \
5180	Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
5181	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
5182	} while (0)
5183
5184	/** Clears any current VMCS for the given VCPU. */
5185	# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
5186	do \
5187	{ \
5188	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
5189	} while (0)
5190
5191	/**
5192	* Invokes the VMX VM-exit handler for an instruction intercept.
5193	*/
5194	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) \
5195	do { return iemVmxVmexitInstr((a_pVCpu), (a_uExitReason), (a_cbInstr)); } while (0)
5196
5197	/**
5198	* Invokes the VMX VM-exit handler for an instruction intercept where the
5199	* instruction provides additional VM-exit information.
5200	*/
5201	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) \
5202	do { return iemVmxVmexitInstrNeedsInfo((a_pVCpu), (a_uExitReason), (a_uInstrId), (a_cbInstr)); } while (0)
5203
5204	/**
5205	* Invokes the VMX VM-exit handler for a task switch.
5206	*/
5207	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) \
5208	do { return iemVmxVmexitTaskSwitch((a_pVCpu), (a_enmTaskSwitch), (a_SelNewTss), (a_cbInstr)); } while (0)
5209
5210	/**
5211	* Invokes the VMX VM-exit handler for MWAIT.
5212	*/
5213	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) \
5214	do { return iemVmxVmexitInstrMwait((a_pVCpu), (a_fMonitorArmed), (a_cbInstr)); } while (0)
5215
5216	/**
5217	* Invokes the VMX VM-exit handler for EPT faults.
5218	*/
5219	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) \
5220	do { return iemVmxVmexitEpt(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr); } while (0)
5221
5222	/**
5223	* Invokes the VMX VM-exit handler.
5224	*/
5225	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) \
5226	do { return iemVmxVmexit((a_pVCpu), (a_uExitReason), (a_uExitQual)); } while (0)
5227
5228	#else
5229	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (false)
5230	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (false)
5231	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_cbInstr) (false)
5232	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_cbInstr) (false)
5233	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_cbInstr) (false)
5234	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5235	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5236	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5237	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5238	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5239	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) do { return VERR_VMX_IPE_1; } while (0)
5240
5241	#endif
5242
5243	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5244	/**
5245	* Checks if we're executing a guest using AMD-V.
5246	*/
5247	# define IEM_SVM_IS_IN_GUEST(a_pVCpu) ( (a_pVCpu->iem.s.fExec & (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST)) \
5248	== (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST))
5249	/**
5250	* Check if an SVM control/instruction intercept is set.
5251	*/
5252	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) \
5253	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmCtrlInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_Intercept)))
5254
5255	/**
5256	* Check if an SVM read CRx intercept is set.
5257	*/
5258	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
5259	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
5260
5261	/**
5262	* Check if an SVM write CRx intercept is set.
5263	*/
5264	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
5265	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
5266
5267	/**
5268	* Check if an SVM read DRx intercept is set.
5269	*/
5270	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
5271	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
5272
5273	/**
5274	* Check if an SVM write DRx intercept is set.
5275	*/
5276	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
5277	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
5278
5279	/**
5280	* Check if an SVM exception intercept is set.
5281	*/
5282	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) \
5283	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmXcptInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uVector)))
5284
5285	/**
5286	* Invokes the SVM \#VMEXIT handler for the nested-guest.
5287	*/
5288	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
5289	do { return iemSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2)); } while (0)
5290
5291	/**
5292	* Invokes the 'MOV CRx' SVM \#VMEXIT handler after constructing the
5293	* corresponding decode assist information.
5294	*/
5295	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) \
5296	do \
5297	{ \
5298	uint64_t uExitInfo1; \
5299	if ( IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmDecodeAssists \
5300	&& (a_enmAccessCrX) == IEMACCESSCRX_MOV_CRX) \
5301	uExitInfo1 = SVM_EXIT1_MOV_CRX_MASK \| ((a_iGReg) & 7); \
5302	else \
5303	uExitInfo1 = 0; \
5304	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, uExitInfo1, 0); \
5305	} while (0)
5306
5307	/** Check and handles SVM nested-guest instruction intercept and updates
5308	* NRIP if needed.
5309	*/
5310	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
5311	do \
5312	{ \
5313	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept)) \
5314	{ \
5315	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
5316	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2); \
5317	} \
5318	} while (0)
5319
5320	/** Checks and handles SVM nested-guest CR0 read intercept. */
5321	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
5322	do \
5323	{ \
5324	if (!IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, 0)) \
5325	{ /* probably likely */ } \
5326	else \
5327	{ \
5328	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
5329	IEM_SVM_VMEXIT_RET(a_pVCpu, SVM_EXIT_READ_CR0, a_uExitInfo1, a_uExitInfo2); \
5330	} \
5331	} while (0)
5332
5333	/**
5334	* Updates the NextRIP (NRI) field in the nested-guest VMCB.
5335	*/
5336	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) \
5337	do { \
5338	if (IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmNextRipSave) \
5339	CPUMGuestSvmUpdateNRip(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_cbInstr)); \
5340	} while (0)
5341
5342	#else
5343	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) (false)
5344	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
5345	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
5346	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
5347	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
5348	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) (false)
5349	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { return VERR_SVM_IPE_1; } while (0)
5350	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) do { return VERR_SVM_IPE_1; } while (0)
5351	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, \
5352	a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
5353	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
5354	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) do { } while (0)
5355
5356	#endif
5357
5358	/** @} */
5359
5360	uint32_t iemCalcExecDbgFlagsSlow(PVMCPUCC pVCpu);
5361	VBOXSTRICTRC iemExecInjectPendingTrap(PVMCPUCC pVCpu);
5362
5363
5364	/**
5365	* Selector descriptor table entry as fetched by iemMemFetchSelDesc.
5366	*/
5367	typedef union IEMSELDESC
5368	{
5369	/** The legacy view. */
5370	X86DESC Legacy;
5371	/** The long mode view. */
5372	X86DESC64 Long;
5373	} IEMSELDESC;
5374	/** Pointer to a selector descriptor table entry. */
5375	typedef IEMSELDESC *PIEMSELDESC;
5376
5377	/** @name Raising Exceptions.
5378	* @{ */
5379	VBOXSTRICTRC iemTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, uint32_t uNextEip, uint32_t fFlags,
5380	uint16_t uErr, uint64_t uCr2, RTSEL SelTSS, PIEMSELDESC pNewDescTSS) RT_NOEXCEPT;
5381
5382	VBOXSTRICTRC iemRaiseXcptOrInt(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags,
5383	uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
5384	#ifdef IEM_WITH_SETJMP
5385	DECL_NO_RETURN(void) iemRaiseXcptOrIntJmp(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector,
5386	uint32_t fFlags, uint16_t uErr, uint64_t uCr2) IEM_NOEXCEPT_MAY_LONGJMP;
5387	#endif
5388	VBOXSTRICTRC iemRaiseDivideError(PVMCPUCC pVCpu) RT_NOEXCEPT;
5389	#ifdef IEM_WITH_SETJMP
5390	DECL_NO_RETURN(void) iemRaiseDivideErrorJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5391	#endif
5392	VBOXSTRICTRC iemRaiseDebugException(PVMCPUCC pVCpu) RT_NOEXCEPT;
5393	VBOXSTRICTRC iemRaiseBoundRangeExceeded(PVMCPUCC pVCpu) RT_NOEXCEPT;
5394	VBOXSTRICTRC iemRaiseUndefinedOpcode(PVMCPUCC pVCpu) RT_NOEXCEPT;
5395	#ifdef IEM_WITH_SETJMP
5396	DECL_NO_RETURN(void) iemRaiseUndefinedOpcodeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5397	#endif
5398	VBOXSTRICTRC iemRaiseDeviceNotAvailable(PVMCPUCC pVCpu) RT_NOEXCEPT;
5399	#ifdef IEM_WITH_SETJMP
5400	DECL_NO_RETURN(void) iemRaiseDeviceNotAvailableJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5401	#endif
5402	VBOXSTRICTRC iemRaiseTaskSwitchFaultWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5403	VBOXSTRICTRC iemRaiseTaskSwitchFaultCurrentTSS(PVMCPUCC pVCpu) RT_NOEXCEPT;
5404	VBOXSTRICTRC iemRaiseTaskSwitchFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
5405	VBOXSTRICTRC iemRaiseTaskSwitchFaultBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5406	/VBOXSTRICTRC iemRaiseSelectorNotPresent(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;/
5407	VBOXSTRICTRC iemRaiseSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5408	VBOXSTRICTRC iemRaiseSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5409	VBOXSTRICTRC iemRaiseStackSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5410	VBOXSTRICTRC iemRaiseStackSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5411	VBOXSTRICTRC iemRaiseGeneralProtectionFault(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5412	VBOXSTRICTRC iemRaiseGeneralProtectionFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
5413	#ifdef IEM_WITH_SETJMP
5414	DECL_NO_RETURN(void) iemRaiseGeneralProtectionFault0Jmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5415	#endif
5416	VBOXSTRICTRC iemRaiseGeneralProtectionFaultBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
5417	VBOXSTRICTRC iemRaiseNotCanonical(PVMCPUCC pVCpu) RT_NOEXCEPT;
5418	VBOXSTRICTRC iemRaiseSelectorBounds(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
5419	#ifdef IEM_WITH_SETJMP
5420	DECL_NO_RETURN(void) iemRaiseSelectorBoundsJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
5421	#endif
5422	VBOXSTRICTRC iemRaiseSelectorBoundsBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
5423	#ifdef IEM_WITH_SETJMP
5424	DECL_NO_RETURN(void) iemRaiseSelectorBoundsBySelectorJmp(PVMCPUCC pVCpu, RTSEL Sel) IEM_NOEXCEPT_MAY_LONGJMP;
5425	#endif
5426	VBOXSTRICTRC iemRaiseSelectorInvalidAccess(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
5427	#ifdef IEM_WITH_SETJMP
5428	DECL_NO_RETURN(void) iemRaiseSelectorInvalidAccessJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
5429	#endif
5430	VBOXSTRICTRC iemRaisePageFault(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) RT_NOEXCEPT;
5431	#ifdef IEM_WITH_SETJMP
5432	DECL_NO_RETURN(void) iemRaisePageFaultJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) IEM_NOEXCEPT_MAY_LONGJMP;
5433	#endif
5434	VBOXSTRICTRC iemRaiseMathFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
5435	#ifdef IEM_WITH_SETJMP
5436	DECL_NO_RETURN(void) iemRaiseMathFaultJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5437	#endif
5438	VBOXSTRICTRC iemRaiseAlignmentCheckException(PVMCPUCC pVCpu) RT_NOEXCEPT;
5439	#ifdef IEM_WITH_SETJMP
5440	DECL_NO_RETURN(void) iemRaiseAlignmentCheckExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5441	#endif
5442	VBOXSTRICTRC iemRaiseSimdFpException(PVMCPUCC pVCpu) RT_NOEXCEPT;
5443	#ifdef IEM_WITH_SETJMP
5444	DECL_NO_RETURN(void) iemRaiseSimdFpExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5445	#endif
5446
5447	void iemLogSyscallRealModeInt(PVMCPUCC pVCpu, uint8_t u8Vector, uint8_t cbInstr);
5448	void iemLogSyscallProtModeInt(PVMCPUCC pVCpu, uint8_t u8Vector, uint8_t cbInstr);
5449
5450	IEM_CIMPL_DEF_0(iemCImplRaiseDivideError);
5451	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidLockPrefix);
5452	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidOpcode);
5453
5454	/**
5455	* Macro for calling iemCImplRaiseDivideError().
5456	*
5457	* This is for things that will _always_ decode to an \#DE, taking the
5458	* recompiler into consideration and everything.
5459	*
5460	* @return Strict VBox status code.
5461	*/
5462	#define IEMOP_RAISE_DIVIDE_ERROR_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseDivideError)
5463
5464	/**
5465	* Macro for calling iemCImplRaiseInvalidLockPrefix().
5466	*
5467	* This is for things that will _always_ decode to an \#UD, taking the
5468	* recompiler into consideration and everything.
5469	*
5470	* @return Strict VBox status code.
5471	*/
5472	#define IEMOP_RAISE_INVALID_LOCK_PREFIX_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidLockPrefix)
5473
5474	/**
5475	* Macro for calling iemCImplRaiseInvalidOpcode() for decode/static \#UDs.
5476	*
5477	* This is for things that will _always_ decode to an \#UD, taking the
5478	* recompiler into consideration and everything.
5479	*
5480	* @return Strict VBox status code.
5481	*/
5482	#define IEMOP_RAISE_INVALID_OPCODE_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidOpcode)
5483
5484	/**
5485	* Macro for calling iemCImplRaiseInvalidOpcode() for runtime-style \#UDs.
5486	*
5487	* Using this macro means you've got _buggy_ _code_ and are doing things that
5488	* belongs exclusively in IEMAllCImpl.cpp during decoding.
5489	*
5490	* @return Strict VBox status code.
5491	* @see IEMOP_RAISE_INVALID_OPCODE_RET
5492	*/
5493	#define IEMOP_RAISE_INVALID_OPCODE_RUNTIME_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidOpcode)
5494
5495	/** @} */
5496
5497	/** @name Register Access.
5498	* @{ */
5499	VBOXSTRICTRC iemRegRipRelativeJumpS8AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int8_t offNextInstr,
5500	IEMMODE enmEffOpSize) RT_NOEXCEPT;
5501	VBOXSTRICTRC iemRegRipRelativeJumpS16AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int16_t offNextInstr) RT_NOEXCEPT;
5502	VBOXSTRICTRC iemRegRipRelativeJumpS32AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int32_t offNextInstr,
5503	IEMMODE enmEffOpSize) RT_NOEXCEPT;
5504	/** @} */
5505
5506	/** @name FPU access and helpers.
5507	* @{ */
5508	void iemFpuPushResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
5509	void iemFpuPushResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5510	void iemFpuPushResultTwo(PVMCPUCC pVCpu, PIEMFPURESULTTWO pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
5511	void iemFpuStoreResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
5512	void iemFpuStoreResultThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
5513	void iemFpuStoreResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
5514	uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5515	void iemFpuStoreResultWithMemOpThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
5516	uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5517	void iemFpuUpdateOpcodeAndIp(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5518	void iemFpuUpdateFSW(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
5519	void iemFpuUpdateFSWThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
5520	void iemFpuUpdateFSWWithMemOp(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5521	void iemFpuUpdateFSWThenPopPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
5522	void iemFpuUpdateFSWWithMemOpThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5523	void iemFpuStackUnderflow(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
5524	void iemFpuStackUnderflowWithMemOp(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5525	void iemFpuStackUnderflowThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
5526	void iemFpuStackUnderflowWithMemOpThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5527	void iemFpuStackUnderflowThenPopPop(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5528	void iemFpuStackPushUnderflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5529	void iemFpuStackPushUnderflowTwo(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5530	void iemFpuStackPushOverflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5531	void iemFpuStackPushOverflowWithMemOp(PVMCPUCC pVCpu, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5532	/** @} */
5533
5534	/** @name SSE+AVX SIMD access and helpers.
5535	* @{ */
5536	void iemSseUpdateMxcsr(PVMCPUCC pVCpu, uint32_t fMxcsr) RT_NOEXCEPT;
5537	/** @} */
5538
5539	/** @name Memory access.
5540	* @{ */
5541
5542	/** Report a \#GP instead of \#AC and do not restrict to ring-3 */
5543	#define IEM_MEMMAP_F_ALIGN_GP RT_BIT_32(16)
5544	/** SSE access that should report a \#GP instead of \#AC, unless MXCSR.MM=1
5545	* when it works like normal \#AC. Always used with IEM_MEMMAP_F_ALIGN_GP. */
5546	#define IEM_MEMMAP_F_ALIGN_SSE RT_BIT_32(17)
5547	/** If \#AC is applicable, raise it. Always used with IEM_MEMMAP_F_ALIGN_GP.
5548	* Users include FXSAVE & FXRSTOR. */
5549	#define IEM_MEMMAP_F_ALIGN_GP_OR_AC RT_BIT_32(18)
5550
5551	VBOXSTRICTRC iemMemMap(PVMCPUCC pVCpu, void *ppvMem, uint8_t pbUnmapInfo, size_t cbMem, uint8_t iSegReg, RTGCPTR GCPtrMem,
5552	uint32_t fAccess, uint32_t uAlignCtl) RT_NOEXCEPT;
5553	VBOXSTRICTRC iemMemCommitAndUnmap(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5554	#ifndef IN_RING3
5555	VBOXSTRICTRC iemMemCommitAndUnmapPostponeTroubleToR3(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5556	#endif
5557	void iemMemRollbackAndUnmap(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5558	void iemMemRollback(PVMCPUCC pVCpu) RT_NOEXCEPT;
5559	VBOXSTRICTRC iemMemApplySegment(PVMCPUCC pVCpu, uint32_t fAccess, uint8_t iSegReg, size_t cbMem, PRTGCPTR pGCPtrMem) RT_NOEXCEPT;
5560	VBOXSTRICTRC iemMemMarkSelDescAccessed(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5561	VBOXSTRICTRC iemMemPageTranslateAndCheckAccess(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t cbAccess, uint32_t fAccess, PRTGCPHYS pGCPhysMem) RT_NOEXCEPT;
5562
5563	void iemOpcodeFlushLight(PVMCPUCC pVCpu, uint8_t cbInstr);
5564	void iemOpcodeFlushHeavy(PVMCPUCC pVCpu, uint8_t cbInstr);
5565	#ifdef IEM_WITH_CODE_TLB
5566	void iemOpcodeFetchBytesJmp(PVMCPUCC pVCpu, size_t cbDst, void *pvDst) IEM_NOEXCEPT_MAY_LONGJMP;
5567	#else
5568	VBOXSTRICTRC iemOpcodeFetchMoreBytes(PVMCPUCC pVCpu, size_t cbMin) RT_NOEXCEPT;
5569	#endif
5570	#ifdef IEM_WITH_SETJMP
5571	uint8_t iemOpcodeGetNextU8SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5572	uint16_t iemOpcodeGetNextU16SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5573	uint32_t iemOpcodeGetNextU32SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5574	uint64_t iemOpcodeGetNextU64SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5575	#else
5576	VBOXSTRICTRC iemOpcodeGetNextU8Slow(PVMCPUCC pVCpu, uint8_t *pb) RT_NOEXCEPT;
5577	VBOXSTRICTRC iemOpcodeGetNextS8SxU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
5578	VBOXSTRICTRC iemOpcodeGetNextS8SxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
5579	VBOXSTRICTRC iemOpcodeGetNextS8SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5580	VBOXSTRICTRC iemOpcodeGetNextU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
5581	VBOXSTRICTRC iemOpcodeGetNextU16ZxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
5582	VBOXSTRICTRC iemOpcodeGetNextU16ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5583	VBOXSTRICTRC iemOpcodeGetNextU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
5584	VBOXSTRICTRC iemOpcodeGetNextU32ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5585	VBOXSTRICTRC iemOpcodeGetNextS32SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5586	VBOXSTRICTRC iemOpcodeGetNextU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5587	#endif
5588
5589	VBOXSTRICTRC iemMemFetchDataU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5590	VBOXSTRICTRC iemMemFetchDataU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5591	VBOXSTRICTRC iemMemFetchDataU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5592	VBOXSTRICTRC iemMemFetchDataU32_ZX_U64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5593	VBOXSTRICTRC iemMemFetchDataU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5594	VBOXSTRICTRC iemMemFetchDataU64AlignedU128(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5595	VBOXSTRICTRC iemMemFetchDataR80(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5596	VBOXSTRICTRC iemMemFetchDataD80(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5597	VBOXSTRICTRC iemMemFetchDataU128(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5598	VBOXSTRICTRC iemMemFetchDataU128NoAc(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5599	VBOXSTRICTRC iemMemFetchDataU128AlignedSse(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5600	VBOXSTRICTRC iemMemFetchDataU256(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5601	VBOXSTRICTRC iemMemFetchDataU256NoAc(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5602	VBOXSTRICTRC iemMemFetchDataU256AlignedAvx(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5603	VBOXSTRICTRC iemMemFetchDataXdtr(PVMCPUCC pVCpu, uint16_t *pcbLimit, PRTGCPTR pGCPtrBase, uint8_t iSegReg,
5604	RTGCPTR GCPtrMem, IEMMODE enmOpSize) RT_NOEXCEPT;
5605	#ifdef IEM_WITH_SETJMP
5606	uint8_t iemMemFetchDataU8SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5607	uint16_t iemMemFetchDataU16SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5608	uint32_t iemMemFetchDataU32SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5609	uint32_t iemMemFlatFetchDataU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5610	uint64_t iemMemFetchDataU64SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5611	uint64_t iemMemFetchDataU64AlignedU128SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5612	void iemMemFetchDataR80SafeJmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5613	void iemMemFetchDataD80SafeJmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5614	void iemMemFetchDataU128SafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5615	void iemMemFetchDataU128NoAcSafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5616	void iemMemFetchDataU128AlignedSseSafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5617	void iemMemFetchDataU256SafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5618	void iemMemFetchDataU256NoAcSafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5619	void iemMemFetchDataU256AlignedAvxSafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5620	# if 0 /* these are inlined now */
5621	uint8_t iemMemFetchDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5622	uint16_t iemMemFetchDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5623	uint32_t iemMemFetchDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5624	uint32_t iemMemFlatFetchDataU32Jmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5625	uint64_t iemMemFetchDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5626	uint64_t iemMemFetchDataU64AlignedU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5627	void iemMemFetchDataR80Jmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5628	void iemMemFetchDataD80Jmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5629	void iemMemFetchDataU128Jmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5630	void iemMemFetchDataU128NoAcJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5631	void iemMemFetchDataU128AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5632	void iemMemFetchDataU256NoAcJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5633	void iemMemFetchDataU256AlignedAvxJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5634	# endif
5635	void iemMemFetchDataU256Jmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5636	#endif
5637
5638	VBOXSTRICTRC iemMemFetchSysU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5639	VBOXSTRICTRC iemMemFetchSysU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5640	VBOXSTRICTRC iemMemFetchSysU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5641	VBOXSTRICTRC iemMemFetchSysU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5642	VBOXSTRICTRC iemMemFetchSelDesc(PVMCPUCC pVCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt) RT_NOEXCEPT;
5643
5644	VBOXSTRICTRC iemMemStoreDataU8(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) RT_NOEXCEPT;
5645	VBOXSTRICTRC iemMemStoreDataU16(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) RT_NOEXCEPT;
5646	VBOXSTRICTRC iemMemStoreDataU32(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) RT_NOEXCEPT;
5647	VBOXSTRICTRC iemMemStoreDataU64(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) RT_NOEXCEPT;
5648	VBOXSTRICTRC iemMemStoreDataU128(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
5649	VBOXSTRICTRC iemMemStoreDataU128NoAc(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
5650	VBOXSTRICTRC iemMemStoreDataU128AlignedSse(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
5651	VBOXSTRICTRC iemMemStoreDataU256(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
5652	VBOXSTRICTRC iemMemStoreDataU256NoAc(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
5653	VBOXSTRICTRC iemMemStoreDataU256AlignedAvx(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
5654	VBOXSTRICTRC iemMemStoreDataXdtr(PVMCPUCC pVCpu, uint16_t cbLimit, RTGCPTR GCPtrBase, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5655	#ifdef IEM_WITH_SETJMP
5656	void iemMemStoreDataU8SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
5657	void iemMemStoreDataU16SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
5658	void iemMemStoreDataU32SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
5659	void iemMemStoreDataU64SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
5660	void iemMemStoreDataU128SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5661	void iemMemStoreDataU128NoAcSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT128U pu128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5662	void iemMemStoreDataU128AlignedSseSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT128U pu128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5663	void iemMemStoreDataU256SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5664	void iemMemStoreDataU256NoAcSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5665	void iemMemStoreDataU256AlignedAvxSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5666	void iemMemStoreDataR80SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTFLOAT80U pr80Value) IEM_NOEXCEPT_MAY_LONGJMP;
5667	void iemMemStoreDataD80SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTPBCD80U pd80Value) IEM_NOEXCEPT_MAY_LONGJMP;
5668	#if 0
5669	void iemMemStoreDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
5670	void iemMemStoreDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
5671	void iemMemStoreDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
5672	void iemMemStoreDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
5673	void iemMemStoreDataU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5674	void iemMemStoreDataNoAcU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5675	void iemMemStoreDataU256NoAcJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5676	void iemMemStoreDataU256AlignedAvxJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5677	#endif
5678	void iemMemStoreDataU128AlignedSseJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5679	void iemMemStoreDataU256Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5680	#endif
5681
5682	#ifdef IEM_WITH_SETJMP
5683	uint8_t iemMemMapDataU8RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5684	uint8_t iemMemMapDataU8AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5685	uint8_t iemMemMapDataU8WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5686	uint8_t const iemMemMapDataU8RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5687	uint16_t iemMemMapDataU16RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5688	uint16_t iemMemMapDataU16AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5689	uint16_t iemMemMapDataU16WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5690	uint16_t const iemMemMapDataU16RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5691	uint32_t iemMemMapDataU32RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5692	uint32_t iemMemMapDataU32AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5693	uint32_t iemMemMapDataU32WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5694	uint32_t const iemMemMapDataU32RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5695	uint64_t iemMemMapDataU64RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5696	uint64_t iemMemMapDataU64AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5697	uint64_t iemMemMapDataU64WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5698	uint64_t const iemMemMapDataU64RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5699	PRTFLOAT80U iemMemMapDataR80RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5700	PRTFLOAT80U iemMemMapDataR80WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5701	PCRTFLOAT80U iemMemMapDataR80RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5702	PRTPBCD80U iemMemMapDataD80RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5703	PRTPBCD80U iemMemMapDataD80WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5704	PCRTPBCD80U iemMemMapDataD80RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5705	PRTUINT128U iemMemMapDataU128RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5706	PRTUINT128U iemMemMapDataU128AtSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5707	PRTUINT128U iemMemMapDataU128WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5708	PCRTUINT128U iemMemMapDataU128RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5709
5710	void iemMemCommitAndUnmapJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5711	void iemMemCommitAndUnmapRwSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5712	void iemMemCommitAndUnmapAtSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5713	void iemMemCommitAndUnmapWoSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5714	void iemMemCommitAndUnmapRoSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5715	void iemMemRollbackAndUnmapWoSafe(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5716	#endif
5717
5718	VBOXSTRICTRC iemMemStackPushBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
5719	void *ppvMem, uint8_t pbUnmapInfo, uint64_t *puNewRsp) RT_NOEXCEPT;
5720	VBOXSTRICTRC iemMemStackPushCommitSpecial(PVMCPUCC pVCpu, uint8_t bUnmapInfo, uint64_t uNewRsp) RT_NOEXCEPT;
5721	VBOXSTRICTRC iemMemStackPushU16(PVMCPUCC pVCpu, uint16_t u16Value) RT_NOEXCEPT;
5722	VBOXSTRICTRC iemMemStackPushU32(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
5723	VBOXSTRICTRC iemMemStackPushU64(PVMCPUCC pVCpu, uint64_t u64Value) RT_NOEXCEPT;
5724	VBOXSTRICTRC iemMemStackPushU16Ex(PVMCPUCC pVCpu, uint16_t u16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5725	VBOXSTRICTRC iemMemStackPushU32Ex(PVMCPUCC pVCpu, uint32_t u32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5726	VBOXSTRICTRC iemMemStackPushU64Ex(PVMCPUCC pVCpu, uint64_t u64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5727	VBOXSTRICTRC iemMemStackPushU32SReg(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
5728	VBOXSTRICTRC iemMemStackPopBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
5729	void const *ppvMem, uint8_t pbUnmapInfo, uint64_t *puNewRsp) RT_NOEXCEPT;
5730	VBOXSTRICTRC iemMemStackPopContinueSpecial(PVMCPUCC pVCpu, size_t off, size_t cbMem,
5731	void const *ppvMem, uint8_t pbUnmapInfo, uint64_t uCurNewRsp) RT_NOEXCEPT;
5732	VBOXSTRICTRC iemMemStackPopDoneSpecial(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5733	VBOXSTRICTRC iemMemStackPopU16(PVMCPUCC pVCpu, uint16_t *pu16Value) RT_NOEXCEPT;
5734	VBOXSTRICTRC iemMemStackPopU32(PVMCPUCC pVCpu, uint32_t *pu32Value) RT_NOEXCEPT;
5735	VBOXSTRICTRC iemMemStackPopU64(PVMCPUCC pVCpu, uint64_t *pu64Value) RT_NOEXCEPT;
5736	VBOXSTRICTRC iemMemStackPopU16Ex(PVMCPUCC pVCpu, uint16_t *pu16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5737	VBOXSTRICTRC iemMemStackPopU32Ex(PVMCPUCC pVCpu, uint32_t *pu32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5738	VBOXSTRICTRC iemMemStackPopU64Ex(PVMCPUCC pVCpu, uint64_t *pu64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5739
5740	#ifdef IEM_WITH_SETJMP
5741	void iemMemStackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5742	void iemMemStackPushU32SafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5743	void iemMemStackPushU32SRegSafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5744	void iemMemStackPushU64SafeJmp(PVMCPUCC pVCpu, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5745	void iemMemStackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5746	void iemMemStackPopGRegU32SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5747	void iemMemStackPopGRegU64SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5748
5749	void iemMemFlat32StackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5750	void iemMemFlat32StackPushU32SafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5751	void iemMemFlat32StackPushU32SRegSafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5752	void iemMemFlat32StackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5753	void iemMemFlat32StackPopGRegU32SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5754
5755	void iemMemFlat64StackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5756	void iemMemFlat64StackPushU64SafeJmp(PVMCPUCC pVCpu, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5757	void iemMemFlat64StackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5758	void iemMemFlat64StackPopGRegU64SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5759
5760	void iemMemStoreStackU16SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5761	void iemMemStoreStackU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5762	void iemMemStoreStackU32SRegSafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5763	void iemMemStoreStackU64SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5764
5765	uint16_t iemMemFetchStackU16SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5766	uint32_t iemMemFetchStackU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5767	uint64_t iemMemFetchStackU64SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5768
5769	#endif
5770
5771	/** @} */
5772
5773	/** @name IEMAllCImpl.cpp
5774	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/'
5775	* @{ */
5776	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem16, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5777	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem32, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5778	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem64, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5779	IEM_CIMPL_PROTO_0(iemCImpl_popa_16);
5780	IEM_CIMPL_PROTO_0(iemCImpl_popa_32);
5781	IEM_CIMPL_PROTO_0(iemCImpl_pusha_16);
5782	IEM_CIMPL_PROTO_0(iemCImpl_pusha_32);
5783	IEM_CIMPL_PROTO_1(iemCImpl_pushf, IEMMODE, enmEffOpSize);
5784	IEM_CIMPL_PROTO_1(iemCImpl_popf, IEMMODE, enmEffOpSize);
5785	IEM_CIMPL_PROTO_1(iemCImpl_call_16, uint16_t, uNewPC);
5786	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_16, int16_t, offDisp);
5787	IEM_CIMPL_PROTO_1(iemCImpl_call_32, uint32_t, uNewPC);
5788	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_32, int32_t, offDisp);
5789	IEM_CIMPL_PROTO_1(iemCImpl_call_64, uint64_t, uNewPC);
5790	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_64, int64_t, offDisp);
5791	IEM_CIMPL_PROTO_3(iemCImpl_FarJmp, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
5792	IEM_CIMPL_PROTO_3(iemCImpl_callf, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
5793	typedef IEM_CIMPL_DECL_TYPE_3(FNIEMCIMPLFARBRANCH, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
5794	typedef FNIEMCIMPLFARBRANCH *PFNIEMCIMPLFARBRANCH;
5795	IEM_CIMPL_PROTO_2(iemCImpl_retf, IEMMODE, enmEffOpSize, uint16_t, cbPop);
5796	IEM_CIMPL_PROTO_0(iemCImpl_retn_16);
5797	IEM_CIMPL_PROTO_0(iemCImpl_retn_32);
5798	IEM_CIMPL_PROTO_0(iemCImpl_retn_64);
5799	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_16, uint16_t, cbPop);
5800	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_32, uint16_t, cbPop);
5801	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_64, uint16_t, cbPop);
5802	IEM_CIMPL_PROTO_3(iemCImpl_enter, IEMMODE, enmEffOpSize, uint16_t, cbFrame, uint8_t, cParameters);
5803	IEM_CIMPL_PROTO_1(iemCImpl_leave, IEMMODE, enmEffOpSize);
5804	IEM_CIMPL_PROTO_2(iemCImpl_int, uint8_t, u8Int, IEMINT, enmInt);
5805	IEM_CIMPL_PROTO_1(iemCImpl_iret_real_v8086, IEMMODE, enmEffOpSize);
5806	IEM_CIMPL_PROTO_4(iemCImpl_iret_prot_v8086, uint32_t, uNewEip, uint16_t, uNewCs, uint32_t, uNewFlags, uint64_t, uNewRsp);
5807	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot_NestedTask, IEMMODE, enmEffOpSize);
5808	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot, IEMMODE, enmEffOpSize);
5809	IEM_CIMPL_PROTO_1(iemCImpl_iret_64bit, IEMMODE, enmEffOpSize);
5810	IEM_CIMPL_PROTO_1(iemCImpl_iret, IEMMODE, enmEffOpSize);
5811	IEM_CIMPL_PROTO_0(iemCImpl_loadall286);
5812	IEM_CIMPL_PROTO_0(iemCImpl_syscall);
5813	IEM_CIMPL_PROTO_1(iemCImpl_sysret, IEMMODE, enmEffOpSize);
5814	IEM_CIMPL_PROTO_0(iemCImpl_sysenter);
5815	IEM_CIMPL_PROTO_1(iemCImpl_sysexit, IEMMODE, enmEffOpSize);
5816	IEM_CIMPL_PROTO_2(iemCImpl_LoadSReg, uint8_t, iSegReg, uint16_t, uSel);
5817	IEM_CIMPL_PROTO_2(iemCImpl_load_SReg, uint8_t, iSegReg, uint16_t, uSel);
5818	IEM_CIMPL_PROTO_2(iemCImpl_pop_Sreg, uint8_t, iSegReg, IEMMODE, enmEffOpSize);
5819	IEM_CIMPL_PROTO_5(iemCImpl_load_SReg_Greg, uint16_t, uSel, uint64_t, offSeg, uint8_t, iSegReg, uint8_t, iGReg, IEMMODE, enmEffOpSize);
5820	IEM_CIMPL_PROTO_2(iemCImpl_VerX, uint16_t, uSel, bool, fWrite);
5821	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u64, uint64_t *, pu64Dst, uint16_t, uSel, bool, fIsLar);
5822	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u16, uint16_t *, pu16Dst, uint16_t, uSel, bool, fIsLar);
5823	IEM_CIMPL_PROTO_3(iemCImpl_lgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
5824	IEM_CIMPL_PROTO_2(iemCImpl_sgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5825	IEM_CIMPL_PROTO_3(iemCImpl_lidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
5826	IEM_CIMPL_PROTO_2(iemCImpl_sidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5827	IEM_CIMPL_PROTO_1(iemCImpl_lldt, uint16_t, uNewLdt);
5828	IEM_CIMPL_PROTO_2(iemCImpl_sldt_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
5829	IEM_CIMPL_PROTO_2(iemCImpl_sldt_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5830	IEM_CIMPL_PROTO_1(iemCImpl_ltr, uint16_t, uNewTr);
5831	IEM_CIMPL_PROTO_2(iemCImpl_str_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
5832	IEM_CIMPL_PROTO_2(iemCImpl_str_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5833	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Cd, uint8_t, iGReg, uint8_t, iCrReg);
5834	IEM_CIMPL_PROTO_2(iemCImpl_smsw_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
5835	IEM_CIMPL_PROTO_2(iemCImpl_smsw_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5836	IEM_CIMPL_PROTO_4(iemCImpl_load_CrX, uint8_t, iCrReg, uint64_t, uNewCrX, IEMACCESSCRX, enmAccessCrX, uint8_t, iGReg);
5837	IEM_CIMPL_PROTO_2(iemCImpl_mov_Cd_Rd, uint8_t, iCrReg, uint8_t, iGReg);
5838	IEM_CIMPL_PROTO_2(iemCImpl_lmsw, uint16_t, u16NewMsw, RTGCPTR, GCPtrEffDst);
5839	IEM_CIMPL_PROTO_0(iemCImpl_clts);
5840	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Dd, uint8_t, iGReg, uint8_t, iDrReg);
5841	IEM_CIMPL_PROTO_2(iemCImpl_mov_Dd_Rd, uint8_t, iDrReg, uint8_t, iGReg);
5842	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Td, uint8_t, iGReg, uint8_t, iTrReg);
5843	IEM_CIMPL_PROTO_2(iemCImpl_mov_Td_Rd, uint8_t, iTrReg, uint8_t, iGReg);
5844	IEM_CIMPL_PROTO_1(iemCImpl_invlpg, RTGCPTR, GCPtrPage);
5845	IEM_CIMPL_PROTO_3(iemCImpl_invpcid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvpcidDesc, uint64_t, uInvpcidType);
5846	IEM_CIMPL_PROTO_0(iemCImpl_invd);
5847	IEM_CIMPL_PROTO_0(iemCImpl_wbinvd);
5848	IEM_CIMPL_PROTO_0(iemCImpl_rsm);
5849	IEM_CIMPL_PROTO_0(iemCImpl_rdtsc);
5850	IEM_CIMPL_PROTO_0(iemCImpl_rdtscp);
5851	IEM_CIMPL_PROTO_0(iemCImpl_rdpmc);
5852	IEM_CIMPL_PROTO_0(iemCImpl_rdmsr);
5853	IEM_CIMPL_PROTO_0(iemCImpl_wrmsr);
5854	IEM_CIMPL_PROTO_3(iemCImpl_in, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
5855	IEM_CIMPL_PROTO_2(iemCImpl_in_eAX_DX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
5856	IEM_CIMPL_PROTO_3(iemCImpl_out, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
5857	IEM_CIMPL_PROTO_2(iemCImpl_out_DX_eAX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
5858	IEM_CIMPL_PROTO_0(iemCImpl_cli);
5859	IEM_CIMPL_PROTO_0(iemCImpl_sti);
5860	IEM_CIMPL_PROTO_0(iemCImpl_hlt);
5861	IEM_CIMPL_PROTO_1(iemCImpl_monitor, uint8_t, iEffSeg);
5862	IEM_CIMPL_PROTO_0(iemCImpl_mwait);
5863	IEM_CIMPL_PROTO_0(iemCImpl_swapgs);
5864	IEM_CIMPL_PROTO_0(iemCImpl_cpuid);
5865	IEM_CIMPL_PROTO_1(iemCImpl_aad, uint8_t, bImm);
5866	IEM_CIMPL_PROTO_1(iemCImpl_aam, uint8_t, bImm);
5867	IEM_CIMPL_PROTO_0(iemCImpl_daa);
5868	IEM_CIMPL_PROTO_0(iemCImpl_das);
5869	IEM_CIMPL_PROTO_0(iemCImpl_aaa);
5870	IEM_CIMPL_PROTO_0(iemCImpl_aas);
5871	IEM_CIMPL_PROTO_3(iemCImpl_bound_16, int16_t, idxArray, int16_t, idxLowerBound, int16_t, idxUpperBound);
5872	IEM_CIMPL_PROTO_3(iemCImpl_bound_32, int32_t, idxArray, int32_t, idxLowerBound, int32_t, idxUpperBound);
5873	IEM_CIMPL_PROTO_0(iemCImpl_xgetbv);
5874	IEM_CIMPL_PROTO_0(iemCImpl_xsetbv);
5875	IEM_CIMPL_PROTO_5(iemCImpl_cmpxchg16b_fallback_rendezvous, PRTUINT128U, pu128Dst, PRTUINT128U, pu128RaxRdx,
5876	PRTUINT128U, pu128RbxRcx, uint32_t *, pEFlags, uint8_t, bUnmapInfo);
5877	IEM_CIMPL_PROTO_2(iemCImpl_clflush_clflushopt, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5878	IEM_CIMPL_PROTO_1(iemCImpl_finit, bool, fCheckXcpts);
5879	IEM_CIMPL_PROTO_3(iemCImpl_fxsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5880	IEM_CIMPL_PROTO_3(iemCImpl_fxrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5881	IEM_CIMPL_PROTO_3(iemCImpl_xsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5882	IEM_CIMPL_PROTO_3(iemCImpl_xrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5883	IEM_CIMPL_PROTO_2(iemCImpl_stmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5884	IEM_CIMPL_PROTO_2(iemCImpl_vstmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5885	IEM_CIMPL_PROTO_2(iemCImpl_ldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5886	IEM_CIMPL_PROTO_3(iemCImpl_fnstenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5887	IEM_CIMPL_PROTO_3(iemCImpl_fnsave, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5888	IEM_CIMPL_PROTO_3(iemCImpl_fldenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
5889	IEM_CIMPL_PROTO_3(iemCImpl_frstor, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
5890	IEM_CIMPL_PROTO_1(iemCImpl_fldcw, uint16_t, u16Fcw);
5891	IEM_CIMPL_PROTO_2(iemCImpl_fxch_underflow, uint8_t, iStReg, uint16_t, uFpuOpcode);
5892	IEM_CIMPL_PROTO_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, bool, fUCmp, uint32_t, uPopAndFpuOpcode);
5893	IEM_CIMPL_PROTO_2(iemCImpl_rdseed, uint8_t, iReg, IEMMODE, enmEffOpSize);
5894	IEM_CIMPL_PROTO_2(iemCImpl_rdrand, uint8_t, iReg, IEMMODE, enmEffOpSize);
5895	/** @} */
5896
5897	/** @name IEMAllCImplStrInstr.cpp.h
5898	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/' -e 's/RT_CONCAT4(//' \
5899	* -e 's/,ADDR_SIZE)/64/g' -e 's/,OP_SIZE,/64/g' -e 's/,OP_rAX,/rax/g' IEMAllCImplStrInstr.cpp.h
5900	* @{ */
5901	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr16, uint8_t, iEffSeg);
5902	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr16, uint8_t, iEffSeg);
5903	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m16);
5904	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m16);
5905	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr16, uint8_t, iEffSeg);
5906	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m16);
5907	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m16, int8_t, iEffSeg);
5908	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr16, bool, fIoChecked);
5909	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr16, bool, fIoChecked);
5910	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5911	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5912
5913	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr16, uint8_t, iEffSeg);
5914	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr16, uint8_t, iEffSeg);
5915	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m16);
5916	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m16);
5917	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr16, uint8_t, iEffSeg);
5918	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m16);
5919	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m16, int8_t, iEffSeg);
5920	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr16, bool, fIoChecked);
5921	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr16, bool, fIoChecked);
5922	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5923	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5924
5925	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr16, uint8_t, iEffSeg);
5926	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr16, uint8_t, iEffSeg);
5927	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m16);
5928	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m16);
5929	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr16, uint8_t, iEffSeg);
5930	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m16);
5931	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m16, int8_t, iEffSeg);
5932	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr16, bool, fIoChecked);
5933	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr16, bool, fIoChecked);
5934	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5935	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
5936
5937
5938	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr32, uint8_t, iEffSeg);
5939	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr32, uint8_t, iEffSeg);
5940	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m32);
5941	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m32);
5942	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr32, uint8_t, iEffSeg);
5943	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m32);
5944	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m32, int8_t, iEffSeg);
5945	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr32, bool, fIoChecked);
5946	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr32, bool, fIoChecked);
5947	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5948	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5949
5950	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr32, uint8_t, iEffSeg);
5951	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr32, uint8_t, iEffSeg);
5952	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m32);
5953	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m32);
5954	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr32, uint8_t, iEffSeg);
5955	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m32);
5956	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m32, int8_t, iEffSeg);
5957	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr32, bool, fIoChecked);
5958	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr32, bool, fIoChecked);
5959	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5960	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5961
5962	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr32, uint8_t, iEffSeg);
5963	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr32, uint8_t, iEffSeg);
5964	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m32);
5965	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m32);
5966	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr32, uint8_t, iEffSeg);
5967	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m32);
5968	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m32, int8_t, iEffSeg);
5969	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr32, bool, fIoChecked);
5970	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr32, bool, fIoChecked);
5971	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5972	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5973
5974	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr32, uint8_t, iEffSeg);
5975	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr32, uint8_t, iEffSeg);
5976	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m32);
5977	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m32);
5978	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr32, uint8_t, iEffSeg);
5979	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m32);
5980	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m32, int8_t, iEffSeg);
5981	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr32, bool, fIoChecked);
5982	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr32, bool, fIoChecked);
5983	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5984	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
5985
5986
5987	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr64, uint8_t, iEffSeg);
5988	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr64, uint8_t, iEffSeg);
5989	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m64);
5990	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m64);
5991	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr64, uint8_t, iEffSeg);
5992	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m64);
5993	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m64, int8_t, iEffSeg);
5994	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr64, bool, fIoChecked);
5995	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr64, bool, fIoChecked);
5996	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5997	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
5998
5999	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr64, uint8_t, iEffSeg);
6000	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr64, uint8_t, iEffSeg);
6001	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m64);
6002	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m64);
6003	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr64, uint8_t, iEffSeg);
6004	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m64);
6005	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m64, int8_t, iEffSeg);
6006	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr64, bool, fIoChecked);
6007	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr64, bool, fIoChecked);
6008	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6009	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6010
6011	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr64, uint8_t, iEffSeg);
6012	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr64, uint8_t, iEffSeg);
6013	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m64);
6014	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m64);
6015	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr64, uint8_t, iEffSeg);
6016	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m64);
6017	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m64, int8_t, iEffSeg);
6018	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr64, bool, fIoChecked);
6019	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr64, bool, fIoChecked);
6020	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6021	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6022
6023	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr64, uint8_t, iEffSeg);
6024	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr64, uint8_t, iEffSeg);
6025	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m64);
6026	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m64);
6027	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr64, uint8_t, iEffSeg);
6028	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m64);
6029	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m64, int8_t, iEffSeg);
6030	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr64, bool, fIoChecked);
6031	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr64, bool, fIoChecked);
6032	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6033	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6034	/** @} */
6035
6036	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
6037	VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT;
6038	VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT;
6039	VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT;
6040	VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT;
6041	VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT;
6042	VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
6043	VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALK pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT;
6044	VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT;
6045	VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT;
6046	VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
6047	bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT;
6048	VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
6049	bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT;
6050	VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6051	VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6052	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6053	VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6054	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6055	VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6056	VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT;
6057	VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
6058	RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT;
6059	VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT;
6060	VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT;
6061	VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT;
6062	uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT;
6063	void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT;
6064	VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
6065	uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT;
6066	bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT;
6067	IEM_CIMPL_PROTO_0(iemCImpl_vmxoff);
6068	IEM_CIMPL_PROTO_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon);
6069	IEM_CIMPL_PROTO_0(iemCImpl_vmlaunch);
6070	IEM_CIMPL_PROTO_0(iemCImpl_vmresume);
6071	IEM_CIMPL_PROTO_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
6072	IEM_CIMPL_PROTO_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
6073	IEM_CIMPL_PROTO_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
6074	IEM_CIMPL_PROTO_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField);
6075	IEM_CIMPL_PROTO_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField);
6076	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField);
6077	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg32, uint64_t *, pu32Dst, uint32_t, u32VmcsField);
6078	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField);
6079	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField);
6080	IEM_CIMPL_PROTO_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType);
6081	IEM_CIMPL_PROTO_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType);
6082	IEM_CIMPL_PROTO_0(iemCImpl_vmx_pause);
6083	#endif
6084
6085	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
6086	VBOXSTRICTRC iemSvmVmexit(PVMCPUCC pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2) RT_NOEXCEPT;
6087	VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr, uint64_t uCr2) RT_NOEXCEPT;
6088	VBOXSTRICTRC iemSvmHandleIOIntercept(PVMCPUCC pVCpu, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
6089	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, uint8_t cbInstr) RT_NOEXCEPT;
6090	VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPUCC pVCpu, uint32_t idMsr, bool fWrite, uint8_t cbInstr) RT_NOEXCEPT;
6091	IEM_CIMPL_PROTO_0(iemCImpl_vmrun);
6092	IEM_CIMPL_PROTO_0(iemCImpl_vmload);
6093	IEM_CIMPL_PROTO_0(iemCImpl_vmsave);
6094	IEM_CIMPL_PROTO_0(iemCImpl_clgi);
6095	IEM_CIMPL_PROTO_0(iemCImpl_stgi);
6096	IEM_CIMPL_PROTO_0(iemCImpl_invlpga);
6097	IEM_CIMPL_PROTO_0(iemCImpl_skinit);
6098	IEM_CIMPL_PROTO_0(iemCImpl_svm_pause);
6099	#endif
6100
6101	IEM_CIMPL_PROTO_0(iemCImpl_vmcall); /* vmx */
6102	IEM_CIMPL_PROTO_0(iemCImpl_vmmcall); /* svm */
6103	IEM_CIMPL_PROTO_1(iemCImpl_Hypercall, uint16_t, uDisOpcode); /* both */
6104
6105	extern const PFNIEMOP g_apfnIemInterpretOnlyOneByteMap[256];
6106	extern const PFNIEMOP g_apfnIemInterpretOnlyTwoByteMap[1024];
6107	extern const PFNIEMOP g_apfnIemInterpretOnlyThreeByte0f3a[1024];
6108	extern const PFNIEMOP g_apfnIemInterpretOnlyThreeByte0f38[1024];
6109	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap1[1024];
6110	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap2[1024];
6111	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap3[1024];
6112
6113	/*
6114	* Recompiler related stuff.
6115	*/
6116	extern const PFNIEMOP g_apfnIemThreadedRecompilerOneByteMap[256];
6117	extern const PFNIEMOP g_apfnIemThreadedRecompilerTwoByteMap[1024];
6118	extern const PFNIEMOP g_apfnIemThreadedRecompilerThreeByte0f3a[1024];
6119	extern const PFNIEMOP g_apfnIemThreadedRecompilerThreeByte0f38[1024];
6120	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap1[1024];
6121	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap2[1024];
6122	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap3[1024];
6123
6124	DECLCALLBACK(int) iemTbInit(PVMCC pVM, uint32_t cInitialTbs, uint32_t cMaxTbs,
6125	uint64_t cbInitialExec, uint64_t cbMaxExec, uint32_t cbChunkExec);
6126	void iemThreadedTbObsolete(PVMCPUCC pVCpu, PIEMTB pTb, bool fSafeToFree);
6127	DECLHIDDEN(void) iemTbAllocatorFree(PVMCPUCC pVCpu, PIEMTB pTb);
6128	void iemTbAllocatorProcessDelayedFrees(PVMCPUCC pVCpu, PIEMTBALLOCATOR pTbAllocator);
6129	void iemTbAllocatorFreeupNativeSpace(PVMCPUCC pVCpu, uint32_t cNeededInstrs);
6130	DECLHIDDEN(const char ) iemTbFlagsToString(uint32_t fFlags, char pszBuf, size_t cbBuf) RT_NOEXCEPT;
6131	DECLHIDDEN(void) iemThreadedDisassembleTb(PCIEMTB pTb, PCDBGFINFOHLP pHlp) RT_NOEXCEPT;
6132
6133
6134	/** @todo FNIEMTHREADEDFUNC and friends may need more work... */
6135	#if defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
6136	typedef VBOXSTRICTRC /__attribute__((__nothrow__))/ FNIEMTHREADEDFUNC(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
6137	typedef FNIEMTHREADEDFUNC *PFNIEMTHREADEDFUNC;
6138	# define IEM_DECL_IEMTHREADEDFUNC_DEF(a_Name) \
6139	VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2)
6140	# define IEM_DECL_IEMTHREADEDFUNC_PROTO(a_Name) \
6141	VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2)
6142
6143	#else
6144	typedef VBOXSTRICTRC (FNIEMTHREADEDFUNC)(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
6145	typedef FNIEMTHREADEDFUNC *PFNIEMTHREADEDFUNC;
6146	# define IEM_DECL_IEMTHREADEDFUNC_DEF(a_Name) \
6147	VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2) IEM_NOEXCEPT_MAY_LONGJMP
6148	# define IEM_DECL_IEMTHREADEDFUNC_PROTO(a_Name) \
6149	VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2) IEM_NOEXCEPT_MAY_LONGJMP
6150	#endif
6151
6152
6153	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_Nop);
6154	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_LogCpuState);
6155
6156	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_DeferToCImpl0);
6157
6158	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckIrq);
6159	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckMode);
6160	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckHwInstrBps);
6161	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLim);
6162
6163	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodes);
6164	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodes);
6165	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesConsiderCsLim);
6166
6167	/* Branching: */
6168	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndPcAndOpcodes);
6169	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckPcAndOpcodes);
6170	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckPcAndOpcodesConsiderCsLim);
6171
6172	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesLoadingTlb);
6173	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesLoadingTlb);
6174	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesLoadingTlbConsiderCsLim);
6175
6176	/* Natural page crossing: */
6177	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesAcrossPageLoadingTlb);
6178	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesAcrossPageLoadingTlb);
6179	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesAcrossPageLoadingTlbConsiderCsLim);
6180
6181	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesOnNextPageLoadingTlb);
6182	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNextPageLoadingTlb);
6183	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNextPageLoadingTlbConsiderCsLim);
6184
6185	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesOnNewPageLoadingTlb);
6186	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNewPageLoadingTlb);
6187	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNewPageLoadingTlbConsiderCsLim);
6188
6189	bool iemThreadedCompileEmitIrqCheckBefore(PVMCPUCC pVCpu, PIEMTB pTb);
6190	bool iemThreadedCompileBeginEmitCallsComplications(PVMCPUCC pVCpu, PIEMTB pTb);
6191
6192	/* Native recompiler public bits: */
6193	DECLHIDDEN(PIEMTB) iemNativeRecompile(PVMCPUCC pVCpu, PIEMTB pTb) RT_NOEXCEPT;
6194	DECLHIDDEN(void) iemNativeDisassembleTb(PCIEMTB pTb, PCDBGFINFOHLP pHlp) RT_NOEXCEPT;
6195	int iemExecMemAllocatorInit(PVMCPU pVCpu, uint64_t cbMax, uint64_t cbInitial, uint32_t cbChunk) RT_NOEXCEPT;
6196	DECLHIDDEN(void *) iemExecMemAllocatorAlloc(PVMCPU pVCpu, uint32_t cbReq, PIEMTB pTb) RT_NOEXCEPT;
6197	DECLHIDDEN(void) iemExecMemAllocatorReadyForUse(PVMCPUCC pVCpu, void *pv, size_t cb) RT_NOEXCEPT;
6198	void iemExecMemAllocatorFree(PVMCPU pVCpu, void *pv, size_t cb) RT_NOEXCEPT;
6199	DECLASM(DECL_NO_RETURN(void)) iemNativeTbLongJmp(void *pvFramePointer, int rc) RT_NOEXCEPT;
6200
6201	#endif /* !RT_IN_ASSEMBLER - ASM-NOINC-END */
6202
6203
6204	/** @} */
6205
6206	RT_C_DECLS_END
6207
6208	/* ASM-INC: %include "IEMInternalStruct.mac" */
6209
6210	#endif /* !VMM_INCLUDED_SRC_include_IEMInternal_h */
6211

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source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h@ 104386

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