IEMInternal.h@ 104956

Last change on this file since 104956 was 104956, checked in by vboxsync, 6 months ago
VMM/IEM: TLB statistics reorg. bugref:10687
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1	/* $Id: IEMInternal.h 104956 2024-06-18 11:44:59Z vboxsync $ */
2	/** @file
3	* IEM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2011-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_IEMInternal_h
29	#define VMM_INCLUDED_SRC_include_IEMInternal_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#ifndef RT_IN_ASSEMBLER
35	# include <VBox/vmm/cpum.h>
36	# include <VBox/vmm/iem.h>
37	# include <VBox/vmm/pgm.h>
38	# include <VBox/vmm/stam.h>
39	# include <VBox/param.h>
40
41	# include <iprt/setjmp-without-sigmask.h>
42	# include <iprt/list.h>
43	#endif /* !RT_IN_ASSEMBLER */
44
45
46	RT_C_DECLS_BEGIN
47
48
49	/** @defgroup grp_iem_int Internals
50	* @ingroup grp_iem
51	* @internal
52	* @{
53	*/
54
55	/* Make doxygen happy w/o overcomplicating the #if checks. */
56	#ifdef DOXYGEN_RUNNING
57	# define IEM_WITH_THROW_CATCH
58	# define VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
59	#endif
60
61	/** For expanding symbol in slickedit and other products tagging and
62	* crossreferencing IEM symbols. */
63	#ifndef IEM_STATIC
64	# define IEM_STATIC static
65	#endif
66
67	/** @def IEM_WITH_SETJMP
68	* Enables alternative status code handling using setjmps.
69	*
70	* This adds a bit of expense via the setjmp() call since it saves all the
71	* non-volatile registers. However, it eliminates return code checks and allows
72	* for more optimal return value passing (return regs instead of stack buffer).
73	*/
74	#if defined(DOXYGEN_RUNNING) \|\| defined(RT_OS_WINDOWS) \|\| 1
75	# define IEM_WITH_SETJMP
76	#endif
77
78	/** @def IEM_WITH_THROW_CATCH
79	* Enables using C++ throw/catch as an alternative to setjmp/longjmp in user
80	* mode code when IEM_WITH_SETJMP is in effect.
81	*
82	* With GCC 11.3.1 and code TLB on linux, using throw/catch instead of
83	* setjmp/long resulted in bs2-test-1 running 3.00% faster and all but on test
84	* result value improving by more than 1%. (Best out of three.)
85	*
86	* With Visual C++ 2019 and code TLB on windows, using throw/catch instead of
87	* setjmp/long resulted in bs2-test-1 running 3.68% faster and all but some of
88	* the MMIO and CPUID tests ran noticeably faster. Variation is greater than on
89	* Linux, but it should be quite a bit faster for normal code.
90	*/
91	#if defined(__cplusplus) && defined(IEM_WITH_SETJMP) && defined(IN_RING3) && (defined(__GNUC__) \|\| defined(_MSC_VER)) /* ASM-NOINC-START */
92	# define IEM_WITH_THROW_CATCH
93	#endif /ASM-NOINC-END/
94
95	/** @def IEMNATIVE_WITH_DELAYED_PC_UPDATING
96	* Enables the delayed PC updating optimization (see @bugref{10373}).
97	*/
98	#if defined(DOXYGEN_RUNNING) \|\| 1
99	# define IEMNATIVE_WITH_DELAYED_PC_UPDATING
100	#endif
101
102	/** Enables the SIMD register allocator @bugref{10614}. */
103	#if defined(DOXYGEN_RUNNING) \|\| 1
104	# define IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
105	#endif
106	/** Enables access to even callee saved registers. */
107	//# define IEMNATIVE_WITH_SIMD_REG_ACCESS_ALL_REGISTERS
108
109	#if defined(DOXYGEN_RUNNING) \|\| 1
110	/** @def IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
111	* Delay the writeback or dirty registers as long as possible. */
112	# define IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
113	#endif
114
115	/** @def IEM_WITH_TLB_STATISTICS
116	* Enables all TLB statistics. */
117	#if defined(VBOX_WITH_STATISTICS) \|\| defined(DOXYGEN_RUNNING)
118	# define IEM_WITH_TLB_STATISTICS
119	#endif
120
121	/** @def VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
122	* Enables a quicker alternative to throw/longjmp for IEM_DO_LONGJMP when
123	* executing native translation blocks.
124	*
125	* This exploits the fact that we save all non-volatile registers in the TB
126	* prologue and thus just need to do the same as the TB epilogue to get the
127	* effect of a longjmp/throw. Since MSC marks XMM6 thru XMM15 as
128	* non-volatile (and does something even more crazy for ARM), this probably
129	* won't work reliably on Windows. */
130	#ifdef RT_ARCH_ARM64
131	# ifndef RT_OS_WINDOWS
132	# define VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
133	# endif
134	#endif
135	/* ASM-NOINC-START */
136	#ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
137	# if !defined(IN_RING3) \
138	\|\| !defined(VBOX_WITH_IEM_RECOMPILER) \
139	\|\| !defined(VBOX_WITH_IEM_NATIVE_RECOMPILER)
140	# undef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
141	# elif defined(RT_OS_WINDOWS)
142	# pragma message("VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP is not safe to use on windows")
143	# endif
144	#endif
145
146
147	/** @def IEM_DO_LONGJMP
148	*
149	* Wrapper around longjmp / throw.
150	*
151	* @param a_pVCpu The CPU handle.
152	* @param a_rc The status code jump back with / throw.
153	*/
154	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
155	# ifdef IEM_WITH_THROW_CATCH
156	# ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
157	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) do { \
158	if ((a_pVCpu)->iem.s.pvTbFramePointerR3) \
159	iemNativeTbLongJmp((a_pVCpu)->iem.s.pvTbFramePointerR3, (a_rc)); \
160	throw int(a_rc); \
161	} while (0)
162	# else
163	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) throw int(a_rc)
164	# endif
165	# else
166	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) longjmp(*(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf), (a_rc))
167	# endif
168	#endif
169
170	/** For use with IEM function that may do a longjmp (when enabled).
171	*
172	* Visual C++ has trouble longjmp'ing from/over functions with the noexcept
173	* attribute. So, we indicate that function that may be part of a longjmp may
174	* throw "exceptions" and that the compiler should definitely not generate and
175	* std::terminate calling unwind code.
176	*
177	* Here is one example of this ending in std::terminate:
178	* @code{.txt}
179	00 00000041`cadfda10 00007ffc`5d5a1f9f ucrtbase!abort+0x4e
180	01 00000041`cadfda40 00007ffc`57af229a ucrtbase!terminate+0x1f
181	02 00000041`cadfda70 00007ffb`eec91030 VCRUNTIME140!__std_terminate+0xa [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\ehhelpers.cpp @ 192]
182	03 00000041`cadfdaa0 00007ffb`eec92c6d VCRUNTIME140_1!_CallSettingFrame+0x20 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\handlers.asm @ 50]
183	04 00000041`cadfdad0 00007ffb`eec93ae5 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToState+0x241 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 1085]
184	05 00000041`cadfdc00 00007ffb`eec92258 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToEmptyState+0x2d [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 218]
185	06 00000041`cadfdc30 00007ffb`eec940e9 VCRUNTIME140_1!__InternalCxxFrameHandler<__FrameHandler4>+0x194 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 304]
186	07 00000041`cadfdcd0 00007ffc`5f9f249f VCRUNTIME140_1!__CxxFrameHandler4+0xa9 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 290]
187	08 00000041`cadfdd40 00007ffc`5f980939 ntdll!RtlpExecuteHandlerForUnwind+0xf
188	09 00000041`cadfdd70 00007ffc`5f9a0edd ntdll!RtlUnwindEx+0x339
189	0a 00000041`cadfe490 00007ffc`57aff976 ntdll!RtlUnwind+0xcd
190	0b 00000041`cadfea00 00007ffb`e1b5de01 VCRUNTIME140!__longjmp_internal+0xe6 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\longjmp.asm @ 140]
191	0c (Inline Function) --------`-------- VBoxVMM!iemOpcodeGetNextU8SlowJmp+0x95 [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 1155]
192	0d 00000041`cadfea50 00007ffb`e1b60f6b VBoxVMM!iemOpcodeGetNextU8Jmp+0xc1 [L:\vbox-intern\src\VBox\VMM\include\IEMInline.h @ 402]
193	0e 00000041`cadfea90 00007ffb`e1cc6201 VBoxVMM!IEMExecForExits+0xdb [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 10185]
194	0f 00000041`cadfec70 00007ffb`e1d0df8d VBoxVMM!EMHistoryExec+0x4f1 [L:\vbox-intern\src\VBox\VMM\VMMAll\EMAll.cpp @ 452]
195	10 00000041`cadfed60 00007ffb`e1d0d4c0 VBoxVMM!nemR3WinHandleExitCpuId+0x79d [L:\vbox-intern\src\VBox\VMM\VMMAll\NEMAllNativeTemplate-win.cpp.h @ 1829] @encode
196	@endcode
197	*
198	* @see https://developercommunity.visualstudio.com/t/fragile-behavior-of-longjmp-called-from-noexcept-f/1532859
199	*/
200	#if defined(IEM_WITH_SETJMP) && (defined(_MSC_VER) \|\| defined(IEM_WITH_THROW_CATCH))
201	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT_EX(false)
202	#else
203	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT
204	#endif
205	/* ASM-NOINC-END */
206
207	#define IEM_IMPLEMENTS_TASKSWITCH
208
209	/** @def IEM_WITH_3DNOW
210	* Includes the 3DNow decoding. */
211	#if !defined(IEM_WITH_3DNOW) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
212	# ifndef IEM_WITHOUT_3DNOW
213	# define IEM_WITH_3DNOW
214	# endif
215	#endif
216
217	/** @def IEM_WITH_THREE_0F_38
218	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
219	#if !defined(IEM_WITH_THREE_0F_38) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
220	# ifndef IEM_WITHOUT_THREE_0F_38
221	# define IEM_WITH_THREE_0F_38
222	# endif
223	#endif
224
225	/** @def IEM_WITH_THREE_0F_3A
226	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
227	#if !defined(IEM_WITH_THREE_0F_3A) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
228	# ifndef IEM_WITHOUT_THREE_0F_3A
229	# define IEM_WITH_THREE_0F_3A
230	# endif
231	#endif
232
233	/** @def IEM_WITH_VEX
234	* Includes the VEX decoding. */
235	#if !defined(IEM_WITH_VEX) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
236	# ifndef IEM_WITHOUT_VEX
237	# define IEM_WITH_VEX
238	# endif
239	#endif
240
241	/** @def IEM_CFG_TARGET_CPU
242	* The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
243	*
244	* By default we allow this to be configured by the user via the
245	* CPUM/GuestCpuName config string, but this comes at a slight cost during
246	* decoding. So, for applications of this code where there is no need to
247	* be dynamic wrt target CPU, just modify this define.
248	*/
249	#if !defined(IEM_CFG_TARGET_CPU) \|\| defined(DOXYGEN_RUNNING)
250	# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
251	#endif
252
253	//#define IEM_WITH_CODE_TLB // - work in progress
254	//#define IEM_WITH_DATA_TLB // - work in progress
255
256
257	/** @def IEM_USE_UNALIGNED_DATA_ACCESS
258	* Use unaligned accesses instead of elaborate byte assembly. */
259	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86) \|\| defined(DOXYGEN_RUNNING) /ASM-NOINC/
260	# define IEM_USE_UNALIGNED_DATA_ACCESS
261	#endif /ASM-NOINC/
262
263	//#define IEM_LOG_MEMORY_WRITES
264
265
266
267	#ifndef RT_IN_ASSEMBLER /* ASM-NOINC-START - the rest of the file */
268
269	# if !defined(IEM_WITHOUT_INSTRUCTION_STATS) && !defined(DOXYGEN_RUNNING)
270	/** Instruction statistics. */
271	typedef struct IEMINSTRSTATS
272	{
273	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
274	# include "IEMInstructionStatisticsTmpl.h"
275	# undef IEM_DO_INSTR_STAT
276	} IEMINSTRSTATS;
277	#else
278	struct IEMINSTRSTATS;
279	typedef struct IEMINSTRSTATS IEMINSTRSTATS;
280	#endif
281	/** Pointer to IEM instruction statistics. */
282	typedef IEMINSTRSTATS *PIEMINSTRSTATS;
283
284
285	/** @name IEMTARGETCPU_EFL_BEHAVIOR_XXX - IEMCPU::aidxTargetCpuEflFlavour
286	* @{ */
287	#define IEMTARGETCPU_EFL_BEHAVIOR_NATIVE 0 /*< Native x86 EFLAGS result; Intel EFLAGS when on non-x86 hosts. /
288	#define IEMTARGETCPU_EFL_BEHAVIOR_INTEL 1 /*< Intel EFLAGS result. /
289	#define IEMTARGETCPU_EFL_BEHAVIOR_AMD 2 /*< AMD EFLAGS result /
290	#define IEMTARGETCPU_EFL_BEHAVIOR_RESERVED 3 /*< Reserved/dummy entry slot that's the same as 0. /
291	#define IEMTARGETCPU_EFL_BEHAVIOR_MASK 3 /*< For masking the index before use. /
292	/** Selects the right variant from a_aArray.
293	* pVCpu is implicit in the caller context. */
294	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT(a_aArray) \
295	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[1] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
296	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for when no native worker can
297	* be used because the host CPU does not support the operation. */
298	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_NON_NATIVE(a_aArray) \
299	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
300	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for a two dimentional
301	* array paralleling IEMCPU::aidxTargetCpuEflFlavour and a single bit index
302	* into the two.
303	* @sa IEM_SELECT_NATIVE_OR_FALLBACK */
304	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
305	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
306	(a_aaArray[a_fNative][pVCpu->iem.s.aidxTargetCpuEflFlavour[a_fNative] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
307	#else
308	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
309	(a_aaArray[0][pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
310	#endif
311	/** @} */
312
313	/**
314	* Picks @a a_pfnNative or @a a_pfnFallback according to the host CPU feature
315	* indicator given by @a a_fCpumFeatureMember (CPUMFEATURES member).
316	*
317	* On non-x86 hosts, this will shortcut to the fallback w/o checking the
318	* indicator.
319	*
320	* @sa IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX
321	*/
322	#if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
323	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) \
324	(g_CpumHostFeatures.s.a_fCpumFeatureMember ? a_pfnNative : a_pfnFallback)
325	#else
326	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) (a_pfnFallback)
327	#endif
328
329
330	/**
331	* Branch types.
332	*/
333	typedef enum IEMBRANCH
334	{
335	IEMBRANCH_JUMP = 1,
336	IEMBRANCH_CALL,
337	IEMBRANCH_TRAP,
338	IEMBRANCH_SOFTWARE_INT,
339	IEMBRANCH_HARDWARE_INT
340	} IEMBRANCH;
341	AssertCompileSize(IEMBRANCH, 4);
342
343
344	/**
345	* INT instruction types.
346	*/
347	typedef enum IEMINT
348	{
349	/** INT n instruction (opcode 0xcd imm). */
350	IEMINT_INTN = 0,
351	/** Single byte INT3 instruction (opcode 0xcc). */
352	IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
353	/** Single byte INTO instruction (opcode 0xce). */
354	IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
355	/** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
356	IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
357	} IEMINT;
358	AssertCompileSize(IEMINT, 4);
359
360
361	/**
362	* A FPU result.
363	*/
364	typedef struct IEMFPURESULT
365	{
366	/** The output value. */
367	RTFLOAT80U r80Result;
368	/** The output status. */
369	uint16_t FSW;
370	} IEMFPURESULT;
371	AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
372	/** Pointer to a FPU result. */
373	typedef IEMFPURESULT *PIEMFPURESULT;
374	/** Pointer to a const FPU result. */
375	typedef IEMFPURESULT const *PCIEMFPURESULT;
376
377
378	/**
379	* A FPU result consisting of two output values and FSW.
380	*/
381	typedef struct IEMFPURESULTTWO
382	{
383	/** The first output value. */
384	RTFLOAT80U r80Result1;
385	/** The output status. */
386	uint16_t FSW;
387	/** The second output value. */
388	RTFLOAT80U r80Result2;
389	} IEMFPURESULTTWO;
390	AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
391	AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
392	/** Pointer to a FPU result consisting of two output values and FSW. */
393	typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
394	/** Pointer to a const FPU result consisting of two output values and FSW. */
395	typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
396
397
398	/**
399	* IEM TLB entry.
400	*
401	* Lookup assembly:
402	* @code{.asm}
403	; Calculate tag.
404	mov rax, [VA]
405	shl rax, 16
406	shr rax, 16 + X86_PAGE_SHIFT
407	or rax, [uTlbRevision]
408
409	; Do indexing.
410	movzx ecx, al
411	lea rcx, [pTlbEntries + rcx]
412
413	; Check tag.
414	cmp [rcx + IEMTLBENTRY.uTag], rax
415	jne .TlbMiss
416
417	; Check access.
418	mov rax, ACCESS_FLAGS \| MAPPING_R3_NOT_VALID \| 0xffffff00
419	and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
420	cmp rax, [uTlbPhysRev]
421	jne .TlbMiss
422
423	; Calc address and we're done.
424	mov eax, X86_PAGE_OFFSET_MASK
425	and eax, [VA]
426	or rax, [rcx + IEMTLBENTRY.pMappingR3]
427	%ifdef VBOX_WITH_STATISTICS
428	inc qword [cTlbHits]
429	%endif
430	jmp .Done
431
432	.TlbMiss:
433	mov r8d, ACCESS_FLAGS
434	mov rdx, [VA]
435	mov rcx, [pVCpu]
436	call iemTlbTypeMiss
437	.Done:
438
439	@endcode
440	*
441	*/
442	typedef struct IEMTLBENTRY
443	{
444	/** The TLB entry tag.
445	* Bits 35 thru 0 are made up of the virtual address shifted right 12 bits, this
446	* is ASSUMING a virtual address width of 48 bits.
447	*
448	* Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
449	*
450	* The TLB lookup code uses the current TLB revision, which won't ever be zero,
451	* enabling an extremely cheap TLB invalidation most of the time. When the TLB
452	* revision wraps around though, the tags needs to be zeroed.
453	*
454	* @note Try use SHRD instruction? After seeing
455	* https://gmplib.org/~tege/x86-timing.pdf, maybe not.
456	*
457	* @todo This will need to be reorganized for 57-bit wide virtual address and
458	* PCID (currently 12 bits) and ASID (currently 6 bits) support. We'll
459	* have to move the TLB entry versioning entirely to the
460	* fFlagsAndPhysRev member then, 57 bit wide VAs means we'll only have
461	* 19 bits left (64 - 57 + 12 = 19) and they'll almost entire be
462	* consumed by PCID and ASID (12 + 6 = 18).
463	*/
464	uint64_t uTag;
465	/** Access flags and physical TLB revision.
466	*
467	* - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
468	* - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
469	* - Bit 2 - page tables - not user (complemented X86_PTE_US).
470	* - Bit 3 - pgm phys/virt - not directly writable.
471	* - Bit 4 - pgm phys page - not directly readable.
472	* - Bit 5 - page tables - not accessed (complemented X86_PTE_A).
473	* - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
474	* - Bit 7 - tlb entry - pMappingR3 member not valid.
475	* - Bits 63 thru 8 are used for the physical TLB revision number.
476	*
477	* We're using complemented bit meanings here because it makes it easy to check
478	* whether special action is required. For instance a user mode write access
479	* would do a "TEST fFlags, (X86_PTE_RW \| X86_PTE_US \| X86_PTE_D)" and a
480	* non-zero result would mean special handling needed because either it wasn't
481	* writable, or it wasn't user, or the page wasn't dirty. A user mode read
482	* access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
483	* need to check any PTE flag.
484	*/
485	uint64_t fFlagsAndPhysRev;
486	/** The guest physical page address. */
487	uint64_t GCPhys;
488	/** Pointer to the ring-3 mapping. */
489	R3PTRTYPE(uint8_t *) pbMappingR3;
490	#if HC_ARCH_BITS == 32
491	uint32_t u32Padding1;
492	#endif
493	} IEMTLBENTRY;
494	AssertCompileSize(IEMTLBENTRY, 32);
495	/** Pointer to an IEM TLB entry. */
496	typedef IEMTLBENTRY *PIEMTLBENTRY;
497
498	/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
499	* @{ */
500	#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /*< Page tables: Not executable. /
501	#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /*< Page tables: Not writable. /
502	#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /*< Page tables: Not user accessible (supervisor only). /
503	#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /*< Phys page: Not writable (access handler, ROM, whatever). /
504	#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /*< Phys page: Not readable (MMIO / access handler, ROM) /
505	#define IEMTLBE_F_PT_NO_ACCESSED RT_BIT_64(5) /*< Phys tables: Not accessed (need to be marked accessed). /
506	#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /*< Page tables: Not dirty (needs to be made dirty on write). /
507	#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(7) /*< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. /
508	#define IEMTLBE_F_PG_UNASSIGNED RT_BIT_64(8) /*< Phys page: Unassigned memory (not RAM, ROM, MMIO2 or MMIO). /
509	#define IEMTLBE_F_PG_CODE_PAGE RT_BIT_64(9) /*< Phys page: Code page. /
510	#define IEMTLBE_F_PHYS_REV UINT64_C(0xfffffffffffffc00) /*< Physical revision mask. @sa IEMTLB_PHYS_REV_INCR /
511	/** @} */
512	AssertCompile(PGMIEMGCPHYS2PTR_F_NO_WRITE == IEMTLBE_F_PG_NO_WRITE);
513	AssertCompile(PGMIEMGCPHYS2PTR_F_NO_READ == IEMTLBE_F_PG_NO_READ);
514	AssertCompile(PGMIEMGCPHYS2PTR_F_NO_MAPPINGR3 == IEMTLBE_F_NO_MAPPINGR3);
515	AssertCompile(PGMIEMGCPHYS2PTR_F_UNASSIGNED == IEMTLBE_F_PG_UNASSIGNED);
516	AssertCompile(PGMIEMGCPHYS2PTR_F_CODE_PAGE == IEMTLBE_F_PG_CODE_PAGE);
517	/** The bits set by PGMPhysIemGCPhys2PtrNoLock. */
518	#define IEMTLBE_GCPHYS2PTR_MASK ( PGMIEMGCPHYS2PTR_F_NO_WRITE \
519	\| PGMIEMGCPHYS2PTR_F_NO_READ \
520	\| PGMIEMGCPHYS2PTR_F_NO_MAPPINGR3 \
521	\| PGMIEMGCPHYS2PTR_F_UNASSIGNED \
522	\| PGMIEMGCPHYS2PTR_F_CODE_PAGE \
523	\| IEMTLBE_F_PHYS_REV )
524
525	/** The TLB size (power of two).
526	* We initially chose 256 because that way we can obtain the result directly
527	* from a 8-bit register without an additional AND instruction.
528	* See also @bugref{10687}. */
529	#define IEMTLB_ENTRY_COUNT 256
530	#define IEMTLB_ENTRY_COUNT_AS_POWER_OF_TWO 8
531	AssertCompile(RT_BIT_32(IEMTLB_ENTRY_COUNT_AS_POWER_OF_TWO) == IEMTLB_ENTRY_COUNT);
532
533	/**
534	* An IEM TLB.
535	*
536	* We've got two of these, one for data and one for instructions.
537	*/
538	typedef struct IEMTLB
539	{
540	/** The TLB revision.
541	* This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
542	* by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
543	* the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
544	* (The revision zero indicates an invalid TLB entry.)
545	*
546	* The initial value is choosen to cause an early wraparound. */
547	uint64_t uTlbRevision;
548	/** The TLB physical address revision - shadow of PGM variable.
549	*
550	* This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
551	* incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
552	* a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
553	* as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
554	*
555	* The initial value is choosen to cause an early wraparound. */
556	uint64_t volatile uTlbPhysRev;
557
558	/* Statistics: */
559
560	/** TLB hits in IEMAll.cpp code (IEM_WITH_TLB_STATISTICS only; both).
561	* @note For the data TLB this is only used in iemMemMap and and for direct (i.e.
562	* not via safe read/write path) calls to iemMemMapJmp. */
563	uint64_t cTlbCoreHits;
564	/** Safe read/write TLB hits in iemMemMapJmp (IEM_WITH_TLB_STATISTICS
565	* only; data tlb only). */
566	uint64_t cTlbSafeHits;
567	/** TLB hits in IEMAllMemRWTmplInline.cpp.h (data + IEM_WITH_TLB_STATISTICS only). */
568	uint64_t cTlbInlineCodeHits;
569
570	/** TLB misses in IEMAll.cpp code (both).
571	* @note For the data TLB this is only used in iemMemMap and for direct (i.e.
572	* not via safe read/write path) calls to iemMemMapJmp. So,
573	* for the data TLB this more like 'other misses', while for the code
574	* TLB is all misses. */
575	uint64_t cTlbCoreMisses;
576	/** Safe read/write TLB misses in iemMemMapJmp (so data only). */
577	uint64_t cTlbSafeMisses;
578	/** Safe read path taken (data only). */
579	uint64_t cTlbSafeReadPath;
580	/** Safe write path taken (data only). */
581	uint64_t cTlbSafeWritePath;
582
583	/** @name Details for native code TLB misses.
584	* @note These counts are included in the above counters (cTlbSafeReadPath,
585	* cTlbSafeWritePath, cTlbInlineCodeHits).
586	* @{ */
587	/** TLB misses in native code due to tag mismatch. */
588	STAMCOUNTER cTlbNativeMissTag;
589	/** TLB misses in native code due to flags or physical revision mismatch. */
590	STAMCOUNTER cTlbNativeMissFlagsAndPhysRev;
591	/** TLB misses in native code due to misaligned access. */
592	STAMCOUNTER cTlbNativeMissAlignment;
593	/** TLB misses in native code due to cross page access. */
594	uint32_t cTlbNativeMissCrossPage;
595	/** TLB misses in native code due to non-canonical address. */
596	uint32_t cTlbNativeMissNonCanonical;
597	/** @} */
598
599	/** Slow read path (code only). */
600	uint32_t cTlbSlowCodeReadPath;
601
602	/** Alignment padding. */
603	uint32_t au32Padding[5];
604
605	/** The TLB entries. */
606	IEMTLBENTRY aEntries[IEMTLB_ENTRY_COUNT];
607	} IEMTLB;
608	AssertCompileSizeAlignment(IEMTLB, 64);
609	/** IEMTLB::uTlbRevision increment. */
610	#define IEMTLB_REVISION_INCR RT_BIT_64(36)
611	/** IEMTLB::uTlbRevision mask. */
612	#define IEMTLB_REVISION_MASK (~(RT_BIT_64(36) - 1))
613	/** IEMTLB::uTlbPhysRev increment.
614	* @sa IEMTLBE_F_PHYS_REV */
615	#define IEMTLB_PHYS_REV_INCR RT_BIT_64(10)
616	/**
617	* Calculates the TLB tag for a virtual address.
618	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
619	* @param a_pTlb The TLB.
620	* @param a_GCPtr The virtual address. Must be RTGCPTR or same size or
621	* the clearing of the top 16 bits won't work (if 32-bit
622	* we'll end up with mostly zeros).
623	*/
624	#define IEMTLB_CALC_TAG(a_pTlb, a_GCPtr) ( IEMTLB_CALC_TAG_NO_REV(a_GCPtr) \| (a_pTlb)->uTlbRevision )
625	/**
626	* Calculates the TLB tag for a virtual address but without TLB revision.
627	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
628	* @param a_GCPtr The virtual address. Must be RTGCPTR or same size or
629	* the clearing of the top 16 bits won't work (if 32-bit
630	* we'll end up with mostly zeros).
631	*/
632	#define IEMTLB_CALC_TAG_NO_REV(a_GCPtr) ( (((a_GCPtr) << 16) >> (GUEST_PAGE_SHIFT + 16)) )
633	/**
634	* Converts a TLB tag value into a TLB index.
635	* @returns Index into IEMTLB::aEntries.
636	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
637	*/
638	#if IEMTLB_ENTRY_COUNT == 256
639	# define IEMTLB_TAG_TO_INDEX(a_uTag) ( (uint8_t)(a_uTag) )
640	#else
641	# define IEMTLB_TAG_TO_INDEX(a_uTag) ( (a_uTag) & (IEMTLB_ENTRY_COUNT - 1U) )
642	AssertCompile(RT_IS_POWER_OF_TWO(IEMTLB_ENTRY_COUNT));
643	#endif
644	/**
645	* Converts a TLB tag value into a TLB index.
646	* @returns Index into IEMTLB::aEntries.
647	* @param a_pTlb The TLB.
648	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
649	*/
650	#define IEMTLB_TAG_TO_ENTRY(a_pTlb, a_uTag) ( &(a_pTlb)->aEntries[IEMTLB_TAG_TO_INDEX(a_uTag)] )
651
652
653	/** @name IEM_MC_F_XXX - MC block flags/clues.
654	* @todo Merge with IEM_CIMPL_F_XXX
655	* @{ */
656	#define IEM_MC_F_ONLY_8086 RT_BIT_32(0)
657	#define IEM_MC_F_MIN_186 RT_BIT_32(1)
658	#define IEM_MC_F_MIN_286 RT_BIT_32(2)
659	#define IEM_MC_F_NOT_286_OR_OLDER IEM_MC_F_MIN_386
660	#define IEM_MC_F_MIN_386 RT_BIT_32(3)
661	#define IEM_MC_F_MIN_486 RT_BIT_32(4)
662	#define IEM_MC_F_MIN_PENTIUM RT_BIT_32(5)
663	#define IEM_MC_F_MIN_PENTIUM_II IEM_MC_F_MIN_PENTIUM
664	#define IEM_MC_F_MIN_CORE IEM_MC_F_MIN_PENTIUM
665	#define IEM_MC_F_64BIT RT_BIT_32(6)
666	#define IEM_MC_F_NOT_64BIT RT_BIT_32(7)
667	/** This is set by IEMAllN8vePython.py to indicate a variation without the
668	* flags-clearing-and-checking, when there is also a variation with that.
669	* @note Do not use this manully, it's only for python and for testing in
670	* the native recompiler! */
671	#define IEM_MC_F_WITHOUT_FLAGS RT_BIT_32(8)
672	/** @} */
673
674	/** @name IEM_CIMPL_F_XXX - State change clues for CIMPL calls.
675	*
676	* These clues are mainly for the recompiler, so that it can emit correct code.
677	*
678	* They are processed by the python script and which also automatically
679	* calculates flags for MC blocks based on the statements, extending the use of
680	* these flags to describe MC block behavior to the recompiler core. The python
681	* script pass the flags to the IEM_MC2_END_EMIT_CALLS macro, but mainly for
682	* error checking purposes. The script emits the necessary fEndTb = true and
683	* similar statements as this reduces compile time a tiny bit.
684	*
685	* @{ */
686	/** Flag set if direct branch, clear if absolute or indirect. */
687	#define IEM_CIMPL_F_BRANCH_DIRECT RT_BIT_32(0)
688	/** Flag set if indirect branch, clear if direct or relative.
689	* This is also used for all system control transfers (SYSCALL, SYSRET, INT, ++)
690	* as well as for return instructions (RET, IRET, RETF). */
691	#define IEM_CIMPL_F_BRANCH_INDIRECT RT_BIT_32(1)
692	/** Flag set if relative branch, clear if absolute or indirect. */
693	#define IEM_CIMPL_F_BRANCH_RELATIVE RT_BIT_32(2)
694	/** Flag set if conditional branch, clear if unconditional. */
695	#define IEM_CIMPL_F_BRANCH_CONDITIONAL RT_BIT_32(3)
696	/** Flag set if it's a far branch (changes CS). */
697	#define IEM_CIMPL_F_BRANCH_FAR RT_BIT_32(4)
698	/** Convenience: Testing any kind of branch. */
699	#define IEM_CIMPL_F_BRANCH_ANY (IEM_CIMPL_F_BRANCH_DIRECT \| IEM_CIMPL_F_BRANCH_INDIRECT \| IEM_CIMPL_F_BRANCH_RELATIVE)
700
701	/** Execution flags may change (IEMCPU::fExec). */
702	#define IEM_CIMPL_F_MODE RT_BIT_32(5)
703	/** May change significant portions of RFLAGS. */
704	#define IEM_CIMPL_F_RFLAGS RT_BIT_32(6)
705	/** May change the status bits (X86_EFL_STATUS_BITS) in RFLAGS. */
706	#define IEM_CIMPL_F_STATUS_FLAGS RT_BIT_32(7)
707	/** May trigger interrupt shadowing. */
708	#define IEM_CIMPL_F_INHIBIT_SHADOW RT_BIT_32(8)
709	/** May enable interrupts, so recheck IRQ immediately afterwards executing
710	* the instruction. */
711	#define IEM_CIMPL_F_CHECK_IRQ_AFTER RT_BIT_32(9)
712	/** May disable interrupts, so recheck IRQ immediately before executing the
713	* instruction. */
714	#define IEM_CIMPL_F_CHECK_IRQ_BEFORE RT_BIT_32(10)
715	/** Convenience: Check for IRQ both before and after an instruction. */
716	#define IEM_CIMPL_F_CHECK_IRQ_BEFORE_AND_AFTER (IEM_CIMPL_F_CHECK_IRQ_BEFORE \| IEM_CIMPL_F_CHECK_IRQ_AFTER)
717	/** May trigger a VM exit (treated like IEM_CIMPL_F_MODE atm). */
718	#define IEM_CIMPL_F_VMEXIT RT_BIT_32(11)
719	/** May modify FPU state.
720	* @todo Not sure if this is useful yet. */
721	#define IEM_CIMPL_F_FPU RT_BIT_32(12)
722	/** REP prefixed instruction which may yield before updating PC.
723	* @todo Not sure if this is useful, REP functions now return non-zero
724	* status if they don't update the PC. */
725	#define IEM_CIMPL_F_REP RT_BIT_32(13)
726	/** I/O instruction.
727	* @todo Not sure if this is useful yet. */
728	#define IEM_CIMPL_F_IO RT_BIT_32(14)
729	/** Force end of TB after the instruction. */
730	#define IEM_CIMPL_F_END_TB RT_BIT_32(15)
731	/** Flag set if a branch may also modify the stack (push/pop return address). */
732	#define IEM_CIMPL_F_BRANCH_STACK RT_BIT_32(16)
733	/** Flag set if a branch may also modify the stack (push/pop return address)
734	* and switch it (load/restore SS:RSP). */
735	#define IEM_CIMPL_F_BRANCH_STACK_FAR RT_BIT_32(17)
736	/** Convenience: Raise exception (technically unnecessary, since it shouldn't return VINF_SUCCESS). */
737	#define IEM_CIMPL_F_XCPT \
738	(IEM_CIMPL_F_BRANCH_INDIRECT \| IEM_CIMPL_F_BRANCH_FAR \| IEM_CIMPL_F_BRANCH_STACK_FAR \
739	\| IEM_CIMPL_F_MODE \| IEM_CIMPL_F_RFLAGS \| IEM_CIMPL_F_VMEXIT)
740
741	/** The block calls a C-implementation instruction function with two implicit arguments.
742	* Mutually exclusive with IEM_CIMPL_F_CALLS_AIMPL and
743	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
744	* @note The python scripts will add this if missing. */
745	#define IEM_CIMPL_F_CALLS_CIMPL RT_BIT_32(18)
746	/** The block calls an ASM-implementation instruction function.
747	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL and
748	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
749	* @note The python scripts will add this if missing. */
750	#define IEM_CIMPL_F_CALLS_AIMPL RT_BIT_32(19)
751	/** The block calls an ASM-implementation instruction function with an implicit
752	* X86FXSTATE pointer argument.
753	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL, IEM_CIMPL_F_CALLS_AIMPL and
754	* IEM_CIMPL_F_CALLS_AIMPL_WITH_XSTATE.
755	* @note The python scripts will add this if missing. */
756	#define IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE RT_BIT_32(20)
757	/** The block calls an ASM-implementation instruction function with an implicit
758	* X86XSAVEAREA pointer argument.
759	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL, IEM_CIMPL_F_CALLS_AIMPL and
760	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
761	* @note No different from IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE, so same value.
762	* @note The python scripts will add this if missing. */
763	#define IEM_CIMPL_F_CALLS_AIMPL_WITH_XSTATE IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE
764	/** @} */
765
766
767	/** @name IEM_F_XXX - Execution mode flags (IEMCPU::fExec, IEMTB::fFlags).
768	*
769	* These flags are set when entering IEM and adjusted as code is executed, such
770	* that they will always contain the current values as instructions are
771	* finished.
772	*
773	* In recompiled execution mode, (most of) these flags are included in the
774	* translation block selection key and stored in IEMTB::fFlags alongside the
775	* IEMTB_F_XXX flags. The latter flags uses bits 31 thru 24, which are all zero
776	* in IEMCPU::fExec.
777	*
778	* @{ */
779	/** Mode: The block target mode mask. */
780	#define IEM_F_MODE_MASK UINT32_C(0x0000001f)
781	/** Mode: The IEMMODE part of the IEMTB_F_MODE_MASK value. */
782	#define IEM_F_MODE_CPUMODE_MASK UINT32_C(0x00000003)
783	/** X86 Mode: Bit used to indicating pre-386 CPU in 16-bit mode (for eliminating
784	* conditional in EIP/IP updating), and flat wide open CS, SS, DS, and ES in
785	* 32-bit mode (for simplifying most memory accesses). */
786	#define IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK UINT32_C(0x00000004)
787	/** X86 Mode: Bit indicating protected mode, real mode (or SMM) when not set. */
788	#define IEM_F_MODE_X86_PROT_MASK UINT32_C(0x00000008)
789	/** X86 Mode: Bit used to indicate virtual 8086 mode (only 16-bit). */
790	#define IEM_F_MODE_X86_V86_MASK UINT32_C(0x00000010)
791
792	/** X86 Mode: 16-bit on 386 or later. */
793	#define IEM_F_MODE_X86_16BIT UINT32_C(0x00000000)
794	/** X86 Mode: 80286, 80186 and 8086/88 targetting blocks (EIP update opt). */
795	#define IEM_F_MODE_X86_16BIT_PRE_386 UINT32_C(0x00000004)
796	/** X86 Mode: 16-bit protected mode on 386 or later. */
797	#define IEM_F_MODE_X86_16BIT_PROT UINT32_C(0x00000008)
798	/** X86 Mode: 16-bit protected mode on 386 or later. */
799	#define IEM_F_MODE_X86_16BIT_PROT_PRE_386 UINT32_C(0x0000000c)
800	/** X86 Mode: 16-bit virtual 8086 protected mode (on 386 or later). */
801	#define IEM_F_MODE_X86_16BIT_PROT_V86 UINT32_C(0x00000018)
802
803	/** X86 Mode: 32-bit on 386 or later. */
804	#define IEM_F_MODE_X86_32BIT UINT32_C(0x00000001)
805	/** X86 Mode: 32-bit mode with wide open flat CS, SS, DS and ES. */
806	#define IEM_F_MODE_X86_32BIT_FLAT UINT32_C(0x00000005)
807	/** X86 Mode: 32-bit protected mode. */
808	#define IEM_F_MODE_X86_32BIT_PROT UINT32_C(0x00000009)
809	/** X86 Mode: 32-bit protected mode with wide open flat CS, SS, DS and ES. */
810	#define IEM_F_MODE_X86_32BIT_PROT_FLAT UINT32_C(0x0000000d)
811
812	/** X86 Mode: 64-bit (includes protected, but not the flat bit). */
813	#define IEM_F_MODE_X86_64BIT UINT32_C(0x0000000a)
814
815	/** X86 Mode: Checks if @a a_fExec represent a FLAT mode. */
816	#define IEM_F_MODE_X86_IS_FLAT(a_fExec) ( ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_64BIT \
817	\|\| ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_32BIT_PROT_FLAT \
818	\|\| ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_32BIT_FLAT)
819
820	/** Bypass access handlers when set. */
821	#define IEM_F_BYPASS_HANDLERS UINT32_C(0x00010000)
822	/** Have pending hardware instruction breakpoints. */
823	#define IEM_F_PENDING_BRK_INSTR UINT32_C(0x00020000)
824	/** Have pending hardware data breakpoints. */
825	#define IEM_F_PENDING_BRK_DATA UINT32_C(0x00040000)
826
827	/** X86: Have pending hardware I/O breakpoints. */
828	#define IEM_F_PENDING_BRK_X86_IO UINT32_C(0x00000400)
829	/** X86: Disregard the lock prefix (implied or not) when set. */
830	#define IEM_F_X86_DISREGARD_LOCK UINT32_C(0x00000800)
831
832	/** Pending breakpoint mask (what iemCalcExecDbgFlags works out). */
833	#define IEM_F_PENDING_BRK_MASK (IEM_F_PENDING_BRK_INSTR \| IEM_F_PENDING_BRK_DATA \| IEM_F_PENDING_BRK_X86_IO)
834
835	/** Caller configurable options. */
836	#define IEM_F_USER_OPTS (IEM_F_BYPASS_HANDLERS \| IEM_F_X86_DISREGARD_LOCK)
837
838	/** X86: The current protection level (CPL) shift factor. */
839	#define IEM_F_X86_CPL_SHIFT 8
840	/** X86: The current protection level (CPL) mask. */
841	#define IEM_F_X86_CPL_MASK UINT32_C(0x00000300)
842	/** X86: The current protection level (CPL) shifted mask. */
843	#define IEM_F_X86_CPL_SMASK UINT32_C(0x00000003)
844
845	/** X86 execution context.
846	* The IEM_F_X86_CTX_XXX values are individual flags that can be combined (with
847	* the exception of IEM_F_X86_CTX_NORMAL). This allows running VMs from SMM
848	* mode. */
849	#define IEM_F_X86_CTX_MASK UINT32_C(0x0000f000)
850	/** X86 context: Plain regular execution context. */
851	#define IEM_F_X86_CTX_NORMAL UINT32_C(0x00000000)
852	/** X86 context: VT-x enabled. */
853	#define IEM_F_X86_CTX_VMX UINT32_C(0x00001000)
854	/** X86 context: AMD-V enabled. */
855	#define IEM_F_X86_CTX_SVM UINT32_C(0x00002000)
856	/** X86 context: In AMD-V or VT-x guest mode. */
857	#define IEM_F_X86_CTX_IN_GUEST UINT32_C(0x00004000)
858	/** X86 context: System management mode (SMM). */
859	#define IEM_F_X86_CTX_SMM UINT32_C(0x00008000)
860
861	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
862	* iemRegFinishClearingRF() most for most situations (CPUMCTX_DBG_HIT_DRX_MASK
863	* and CPUMCTX_DBG_DBGF_MASK are covered by the IEM_F_PENDING_BRK_XXX bits
864	* alread). */
865
866	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
867	* iemRegFinishClearingRF() most for most situations
868	* (CPUMCTX_DBG_HIT_DRX_MASK and CPUMCTX_DBG_DBGF_MASK are covered by
869	* the IEM_F_PENDING_BRK_XXX bits alread). */
870
871	/** @} */
872
873
874	/** @name IEMTB_F_XXX - Translation block flags (IEMTB::fFlags).
875	*
876	* Extends the IEM_F_XXX flags (subject to IEMTB_F_IEM_F_MASK) to make up the
877	* translation block flags. The combined flag mask (subject to
878	* IEMTB_F_KEY_MASK) is used as part of the lookup key for translation blocks.
879	*
880	* @{ */
881	/** Mask of IEM_F_XXX flags included in IEMTB_F_XXX. */
882	#define IEMTB_F_IEM_F_MASK UINT32_C(0x00ffffff)
883
884	/** Type: The block type mask. */
885	#define IEMTB_F_TYPE_MASK UINT32_C(0x03000000)
886	/** Type: Purly threaded recompiler (via tables). */
887	#define IEMTB_F_TYPE_THREADED UINT32_C(0x01000000)
888	/** Type: Native recompilation. */
889	#define IEMTB_F_TYPE_NATIVE UINT32_C(0x02000000)
890
891	/** Set when we're starting the block in an "interrupt shadow".
892	* We don't need to distingish between the two types of this mask, thus the one.
893	* @see CPUMCTX_INHIBIT_SHADOW, CPUMIsInInterruptShadow() */
894	#define IEMTB_F_INHIBIT_SHADOW UINT32_C(0x04000000)
895	/** Set when we're currently inhibiting NMIs
896	* @see CPUMCTX_INHIBIT_NMI, CPUMAreInterruptsInhibitedByNmi() */
897	#define IEMTB_F_INHIBIT_NMI UINT32_C(0x08000000)
898
899	/** Checks that EIP/IP is wihin CS.LIM before each instruction. Used when
900	* we're close the limit before starting a TB, as determined by
901	* iemGetTbFlagsForCurrentPc(). */
902	#define IEMTB_F_CS_LIM_CHECKS UINT32_C(0x10000000)
903
904	/** Mask of the IEMTB_F_XXX flags that are part of the TB lookup key.
905	*
906	* @note We skip all of IEM_F_X86_CTX_MASK, with the exception of SMM (which we
907	* don't implement), because we don't currently generate any context
908	* specific code - that's all handled in CIMPL functions.
909	*
910	* For the threaded recompiler we don't generate any CPL specific code
911	* either, but the native recompiler does for memory access (saves getting
912	* the CPL from fExec and turning it into IEMTLBE_F_PT_NO_USER).
913	* Since most OSes will not share code between rings, this shouldn't
914	* have any real effect on TB/memory/recompiling load.
915	*/
916	#define IEMTB_F_KEY_MASK ((UINT32_MAX & ~(IEM_F_X86_CTX_MASK \| IEMTB_F_TYPE_MASK)) \| IEM_F_X86_CTX_SMM)
917	/** @} */
918
919	AssertCompile( (IEM_F_MODE_X86_16BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
920	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
921	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_PROT_MASK));
922	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_V86_MASK));
923	AssertCompile( (IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
924	AssertCompile( IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
925	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_PROT_MASK));
926	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
927	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
928	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
929	AssertCompile( IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
930	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_V86_MASK));
931	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
932	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
933	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_PROT_MASK);
934	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
935	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_PROT_MASK);
936	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
937	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_V86_MASK);
938
939	AssertCompile( (IEM_F_MODE_X86_32BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
940	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
941	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_PROT_MASK));
942	AssertCompile( (IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
943	AssertCompile( IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
944	AssertCompile(!(IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_PROT_MASK));
945	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
946	AssertCompile(!(IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
947	AssertCompile( IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
948	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
949	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
950	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_PROT_MASK);
951
952	AssertCompile( (IEM_F_MODE_X86_64BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_64BIT);
953	AssertCompile( IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_PROT_MASK);
954	AssertCompile(!(IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
955
956	/** Native instruction type for use with the native code generator.
957	* This is a byte (uint8_t) for x86 and amd64 and uint32_t for the other(s). */
958	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
959	typedef uint8_t IEMNATIVEINSTR;
960	#else
961	typedef uint32_t IEMNATIVEINSTR;
962	#endif
963	/** Pointer to a native instruction unit. */
964	typedef IEMNATIVEINSTR *PIEMNATIVEINSTR;
965	/** Pointer to a const native instruction unit. */
966	typedef IEMNATIVEINSTR const *PCIEMNATIVEINSTR;
967
968	/**
969	* A call for the threaded call table.
970	*/
971	typedef struct IEMTHRDEDCALLENTRY
972	{
973	/** The function to call (IEMTHREADEDFUNCS). */
974	uint16_t enmFunction;
975
976	/** Instruction number in the TB (for statistics). */
977	uint8_t idxInstr;
978	/** The opcode length. */
979	uint8_t cbOpcode;
980	/** Offset into IEMTB::pabOpcodes. */
981	uint16_t offOpcode;
982
983	/** TB lookup table index (7 bits) and large size (1 bits).
984	*
985	* The default size is 1 entry, but for indirect calls and returns we set the
986	* top bit and allocate 4 (IEM_TB_LOOKUP_TAB_LARGE_SIZE) entries. The large
987	* tables uses RIP for selecting the entry to use, as it is assumed a hash table
988	* lookup isn't that slow compared to sequentially trying out 4 TBs.
989	*
990	* By default lookup table entry 0 for a TB is reserved as a fallback for
991	* calltable entries w/o explicit entreis, so this member will be non-zero if
992	* there is a lookup entry associated with this call.
993	*
994	* @sa IEM_TB_LOOKUP_TAB_GET_SIZE, IEM_TB_LOOKUP_TAB_GET_IDX
995	*/
996	uint8_t uTbLookup;
997
998	/** Unused atm. */
999	uint8_t uUnused0;
1000
1001	/** Generic parameters. */
1002	uint64_t auParams[3];
1003	} IEMTHRDEDCALLENTRY;
1004	AssertCompileSize(IEMTHRDEDCALLENTRY, sizeof(uint64_t) * 4);
1005	/** Pointer to a threaded call entry. */
1006	typedef struct IEMTHRDEDCALLENTRY *PIEMTHRDEDCALLENTRY;
1007	/** Pointer to a const threaded call entry. */
1008	typedef IEMTHRDEDCALLENTRY const *PCIEMTHRDEDCALLENTRY;
1009
1010	/** The number of TB lookup table entries for a large allocation
1011	* (IEMTHRDEDCALLENTRY::uTbLookup bit 7 set). */
1012	#define IEM_TB_LOOKUP_TAB_LARGE_SIZE 4
1013	/** Get the lookup table size from IEMTHRDEDCALLENTRY::uTbLookup. */
1014	#define IEM_TB_LOOKUP_TAB_GET_SIZE(a_uTbLookup) (!((a_uTbLookup) & 0x80) ? 1 : IEM_TB_LOOKUP_TAB_LARGE_SIZE)
1015	/** Get the first lookup table index from IEMTHRDEDCALLENTRY::uTbLookup. */
1016	#define IEM_TB_LOOKUP_TAB_GET_IDX(a_uTbLookup) ((a_uTbLookup) & 0x7f)
1017	/** Get the lookup table index from IEMTHRDEDCALLENTRY::uTbLookup and RIP. */
1018	#define IEM_TB_LOOKUP_TAB_GET_IDX_WITH_RIP(a_uTbLookup, a_Rip) \
1019	(!((a_uTbLookup) & 0x80) ? (a_uTbLookup) & 0x7f : ((a_uTbLookup) & 0x7f) + ((a_Rip) & (IEM_TB_LOOKUP_TAB_LARGE_SIZE - 1)) )
1020
1021	/** Make a IEMTHRDEDCALLENTRY::uTbLookup value. */
1022	#define IEM_TB_LOOKUP_TAB_MAKE(a_idxTable, a_fLarge) ((a_idxTable) \| ((a_fLarge) ? 0x80 : 0))
1023
1024	/**
1025	* Native IEM TB 'function' typedef.
1026	*
1027	* This will throw/longjmp on occation.
1028	*
1029	* @note AMD64 doesn't have that many non-volatile registers and does sport
1030	* 32-bit address displacments, so we don't need pCtx.
1031	*
1032	* On ARM64 pCtx allows us to directly address the whole register
1033	* context without requiring a separate indexing register holding the
1034	* offset. This saves an instruction loading the offset for each guest
1035	* CPU context access, at the cost of a non-volatile register.
1036	* Fortunately, ARM64 has quite a lot more registers.
1037	*/
1038	typedef
1039	#ifdef RT_ARCH_AMD64
1040	int FNIEMTBNATIVE(PVMCPUCC pVCpu)
1041	#else
1042	int FNIEMTBNATIVE(PVMCPUCC pVCpu, PCPUMCTX pCtx)
1043	#endif
1044	#if RT_CPLUSPLUS_PREREQ(201700)
1045	IEM_NOEXCEPT_MAY_LONGJMP
1046	#endif
1047	;
1048	/** Pointer to a native IEM TB entry point function.
1049	* This will throw/longjmp on occation. */
1050	typedef FNIEMTBNATIVE *PFNIEMTBNATIVE;
1051
1052
1053	/**
1054	* Translation block debug info entry type.
1055	*/
1056	typedef enum IEMTBDBGENTRYTYPE
1057	{
1058	kIemTbDbgEntryType_Invalid = 0,
1059	/** The entry is for marking a native code position.
1060	* Entries following this all apply to this position. */
1061	kIemTbDbgEntryType_NativeOffset,
1062	/** The entry is for a new guest instruction. */
1063	kIemTbDbgEntryType_GuestInstruction,
1064	/** Marks the start of a threaded call. */
1065	kIemTbDbgEntryType_ThreadedCall,
1066	/** Marks the location of a label. */
1067	kIemTbDbgEntryType_Label,
1068	/** Info about a host register shadowing a guest register. */
1069	kIemTbDbgEntryType_GuestRegShadowing,
1070	#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
1071	/** Info about a host SIMD register shadowing a guest SIMD register. */
1072	kIemTbDbgEntryType_GuestSimdRegShadowing,
1073	#endif
1074	#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING
1075	/** Info about a delayed RIP update. */
1076	kIemTbDbgEntryType_DelayedPcUpdate,
1077	#endif
1078	#if defined(IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK) \|\| defined(IEMNATIVE_WITH_SIMD_REG_ALLOCATOR)
1079	/** Info about a shadowed guest register becoming dirty. */
1080	kIemTbDbgEntryType_GuestRegDirty,
1081	/** Info about register writeback/flush oepration. */
1082	kIemTbDbgEntryType_GuestRegWriteback,
1083	#endif
1084	kIemTbDbgEntryType_End
1085	} IEMTBDBGENTRYTYPE;
1086
1087	/**
1088	* Translation block debug info entry.
1089	*/
1090	typedef union IEMTBDBGENTRY
1091	{
1092	/** Plain 32-bit view. */
1093	uint32_t u;
1094
1095	/** Generic view for getting at the type field. */
1096	struct
1097	{
1098	/** IEMTBDBGENTRYTYPE */
1099	uint32_t uType : 4;
1100	uint32_t uTypeSpecific : 28;
1101	} Gen;
1102
1103	struct
1104	{
1105	/** kIemTbDbgEntryType_ThreadedCall1. */
1106	uint32_t uType : 4;
1107	/** Native code offset. */
1108	uint32_t offNative : 28;
1109	} NativeOffset;
1110
1111	struct
1112	{
1113	/** kIemTbDbgEntryType_GuestInstruction. */
1114	uint32_t uType : 4;
1115	uint32_t uUnused : 4;
1116	/** The IEM_F_XXX flags. */
1117	uint32_t fExec : 24;
1118	} GuestInstruction;
1119
1120	struct
1121	{
1122	/* kIemTbDbgEntryType_ThreadedCall. */
1123	uint32_t uType : 4;
1124	/** Set if the call was recompiled to native code, clear if just calling
1125	* threaded function. */
1126	uint32_t fRecompiled : 1;
1127	uint32_t uUnused : 11;
1128	/** The threaded call number (IEMTHREADEDFUNCS). */
1129	uint32_t enmCall : 16;
1130	} ThreadedCall;
1131
1132	struct
1133	{
1134	/* kIemTbDbgEntryType_Label. */
1135	uint32_t uType : 4;
1136	uint32_t uUnused : 4;
1137	/** The label type (IEMNATIVELABELTYPE). */
1138	uint32_t enmLabel : 8;
1139	/** The label data. */
1140	uint32_t uData : 16;
1141	} Label;
1142
1143	struct
1144	{
1145	/* kIemTbDbgEntryType_GuestRegShadowing. */
1146	uint32_t uType : 4;
1147	uint32_t uUnused : 4;
1148	/** The guest register being shadowed (IEMNATIVEGSTREG). */
1149	uint32_t idxGstReg : 8;
1150	/** The host new register number, UINT8_MAX if dropped. */
1151	uint32_t idxHstReg : 8;
1152	/** The previous host register number, UINT8_MAX if new. */
1153	uint32_t idxHstRegPrev : 8;
1154	} GuestRegShadowing;
1155
1156	#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
1157	struct
1158	{
1159	/* kIemTbDbgEntryType_GuestSimdRegShadowing. */
1160	uint32_t uType : 4;
1161	uint32_t uUnused : 4;
1162	/** The guest register being shadowed (IEMNATIVEGSTSIMDREG). */
1163	uint32_t idxGstSimdReg : 8;
1164	/** The host new register number, UINT8_MAX if dropped. */
1165	uint32_t idxHstSimdReg : 8;
1166	/** The previous host register number, UINT8_MAX if new. */
1167	uint32_t idxHstSimdRegPrev : 8;
1168	} GuestSimdRegShadowing;
1169	#endif
1170
1171	#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING
1172	struct
1173	{
1174	/* kIemTbDbgEntryType_DelayedPcUpdate. */
1175	uint32_t uType : 4;
1176	/* The instruction offset added to the program counter. */
1177	uint32_t offPc : 14;
1178	/** Number of instructions skipped. */
1179	uint32_t cInstrSkipped : 14;
1180	} DelayedPcUpdate;
1181	#endif
1182
1183	#if defined(IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK) \|\| defined(IEMNATIVE_WITH_SIMD_REG_ALLOCATOR)
1184	struct
1185	{
1186	/* kIemTbDbgEntryType_GuestRegDirty. */
1187	uint32_t uType : 4;
1188	uint32_t uUnused : 11;
1189	/** Flag whether this is about a SIMD (true) or general (false) register. */
1190	uint32_t fSimdReg : 1;
1191	/** The guest register index being marked as dirty. */
1192	uint32_t idxGstReg : 8;
1193	/** The host register number this register is shadowed in .*/
1194	uint32_t idxHstReg : 8;
1195	} GuestRegDirty;
1196
1197	struct
1198	{
1199	/* kIemTbDbgEntryType_GuestRegWriteback. */
1200	uint32_t uType : 4;
1201	/** Flag whether this is about a SIMD (true) or general (false) register flush. */
1202	uint32_t fSimdReg : 1;
1203	/** The mask shift. */
1204	uint32_t cShift : 2;
1205	/** The guest register mask being written back. */
1206	uint32_t fGstReg : 25;
1207	} GuestRegWriteback;
1208	#endif
1209
1210	} IEMTBDBGENTRY;
1211	AssertCompileSize(IEMTBDBGENTRY, sizeof(uint32_t));
1212	/** Pointer to a debug info entry. */
1213	typedef IEMTBDBGENTRY *PIEMTBDBGENTRY;
1214	/** Pointer to a const debug info entry. */
1215	typedef IEMTBDBGENTRY const *PCIEMTBDBGENTRY;
1216
1217	/**
1218	* Translation block debug info.
1219	*/
1220	typedef struct IEMTBDBG
1221	{
1222	/** Number of entries in aEntries. */
1223	uint32_t cEntries;
1224	/** The offset of the last kIemTbDbgEntryType_NativeOffset record. */
1225	uint32_t offNativeLast;
1226	/** Debug info entries. */
1227	RT_FLEXIBLE_ARRAY_EXTENSION
1228	IEMTBDBGENTRY aEntries[RT_FLEXIBLE_ARRAY];
1229	} IEMTBDBG;
1230	/** Pointer to TB debug info. */
1231	typedef IEMTBDBG *PIEMTBDBG;
1232	/** Pointer to const TB debug info. */
1233	typedef IEMTBDBG const *PCIEMTBDBG;
1234
1235
1236	/**
1237	* Translation block.
1238	*
1239	* The current plan is to just keep TBs and associated lookup hash table private
1240	* to each VCpu as that simplifies TB removal greatly (no races) and generally
1241	* avoids using expensive atomic primitives for updating lists and stuff.
1242	*/
1243	#pragma pack(2) /* to prevent the Thrd structure from being padded unnecessarily */
1244	typedef struct IEMTB
1245	{
1246	/** Next block with the same hash table entry. */
1247	struct IEMTB *pNext;
1248	/** Usage counter. */
1249	uint32_t cUsed;
1250	/** The IEMCPU::msRecompilerPollNow last time it was used. */
1251	uint32_t msLastUsed;
1252
1253	/** @name What uniquely identifies the block.
1254	* @{ */
1255	RTGCPHYS GCPhysPc;
1256	/** IEMTB_F_XXX (i.e. IEM_F_XXX ++). */
1257	uint32_t fFlags;
1258	union
1259	{
1260	struct
1261	{
1262	/*< Relevant CS X86DESCATTR_XXX bits. /
1263	uint16_t fAttr;
1264	} x86;
1265	};
1266	/** @} */
1267
1268	/** Number of opcode ranges. */
1269	uint8_t cRanges;
1270	/** Statistics: Number of instructions in the block. */
1271	uint8_t cInstructions;
1272
1273	/** Type specific info. */
1274	union
1275	{
1276	struct
1277	{
1278	/** The call sequence table. */
1279	PIEMTHRDEDCALLENTRY paCalls;
1280	/** Number of calls in paCalls. */
1281	uint16_t cCalls;
1282	/** Number of calls allocated. */
1283	uint16_t cAllocated;
1284	} Thrd;
1285	struct
1286	{
1287	/** The native instructions (PFNIEMTBNATIVE). */
1288	PIEMNATIVEINSTR paInstructions;
1289	/** Number of instructions pointed to by paInstructions. */
1290	uint32_t cInstructions;
1291	} Native;
1292	/** Generic view for zeroing when freeing. */
1293	struct
1294	{
1295	uintptr_t uPtr;
1296	uint32_t uData;
1297	} Gen;
1298	};
1299
1300	/** The allocation chunk this TB belongs to. */
1301	uint8_t idxAllocChunk;
1302	/** The number of entries in the lookup table.
1303	* Because we're out of space, the TB lookup table is located before the
1304	* opcodes pointed to by pabOpcodes. */
1305	uint8_t cTbLookupEntries;
1306
1307	/** Number of bytes of opcodes stored in pabOpcodes.
1308	* @todo this field isn't really needed, aRanges keeps the actual info. */
1309	uint16_t cbOpcodes;
1310	/** Pointer to the opcode bytes this block was recompiled from.
1311	* This also points to the TB lookup table, which starts cTbLookupEntries
1312	* entries before the opcodes (we don't have room atm for another point). */
1313	uint8_t *pabOpcodes;
1314
1315	/** Debug info if enabled.
1316	* This is only generated by the native recompiler. */
1317	PIEMTBDBG pDbgInfo;
1318
1319	/* --- 64 byte cache line end --- */
1320
1321	/** Opcode ranges.
1322	*
1323	* The opcode checkers and maybe TLB loading functions will use this to figure
1324	* out what to do. The parameter will specify an entry and the opcode offset to
1325	* start at and the minimum number of bytes to verify (instruction length).
1326	*
1327	* When VT-x and AMD-V looks up the opcode bytes for an exitting instruction,
1328	* they'll first translate RIP (+ cbInstr - 1) to a physical address using the
1329	* code TLB (must have a valid entry for that address) and scan the ranges to
1330	* locate the corresponding opcodes. Probably.
1331	*/
1332	struct IEMTBOPCODERANGE
1333	{
1334	/** Offset within pabOpcodes. */
1335	uint16_t offOpcodes;
1336	/** Number of bytes. */
1337	uint16_t cbOpcodes;
1338	/** The page offset. */
1339	RT_GCC_EXTENSION
1340	uint16_t offPhysPage : 12;
1341	/** Unused bits. */
1342	RT_GCC_EXTENSION
1343	uint16_t u2Unused : 2;
1344	/** Index into GCPhysPc + aGCPhysPages for the physical page address. */
1345	RT_GCC_EXTENSION
1346	uint16_t idxPhysPage : 2;
1347	} aRanges[8];
1348
1349	/** Physical pages that this TB covers.
1350	* The GCPhysPc w/o page offset is element zero, so starting here with 1. */
1351	RTGCPHYS aGCPhysPages[2];
1352	} IEMTB;
1353	#pragma pack()
1354	AssertCompileMemberAlignment(IEMTB, GCPhysPc, sizeof(RTGCPHYS));
1355	AssertCompileMemberAlignment(IEMTB, Thrd, sizeof(void *));
1356	AssertCompileMemberAlignment(IEMTB, pabOpcodes, sizeof(void *));
1357	AssertCompileMemberAlignment(IEMTB, pDbgInfo, sizeof(void *));
1358	AssertCompileMemberAlignment(IEMTB, aGCPhysPages, sizeof(RTGCPHYS));
1359	AssertCompileMemberOffset(IEMTB, aRanges, 64);
1360	AssertCompileMemberSize(IEMTB, aRanges[0], 6);
1361	#if 1
1362	AssertCompileSize(IEMTB, 128);
1363	# define IEMTB_SIZE_IS_POWER_OF_TWO /*< The IEMTB size is a power of two. /
1364	#else
1365	AssertCompileSize(IEMTB, 168);
1366	# undef IEMTB_SIZE_IS_POWER_OF_TWO
1367	#endif
1368
1369	/** Pointer to a translation block. */
1370	typedef IEMTB *PIEMTB;
1371	/** Pointer to a const translation block. */
1372	typedef IEMTB const *PCIEMTB;
1373
1374	/** Gets address of the given TB lookup table entry. */
1375	#define IEMTB_GET_TB_LOOKUP_TAB_ENTRY(a_pTb, a_idx) \
1376	((PIEMTB )&(a_pTb)->pabOpcodes[-(int)((a_pTb)->cTbLookupEntries - (a_idx)) sizeof(PIEMTB)])
1377
1378	/**
1379	* Gets the physical address for a TB opcode range.
1380	*/
1381	DECL_FORCE_INLINE(RTGCPHYS) iemTbGetRangePhysPageAddr(PCIEMTB pTb, uint8_t idxRange)
1382	{
1383	Assert(idxRange < RT_MIN(pTb->cRanges, RT_ELEMENTS(pTb->aRanges)));
1384	uint8_t const idxPage = pTb->aRanges[idxRange].idxPhysPage;
1385	Assert(idxPage <= RT_ELEMENTS(pTb->aGCPhysPages));
1386	if (idxPage == 0)
1387	return pTb->GCPhysPc & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
1388	Assert(!(pTb->aGCPhysPages[idxPage - 1] & GUEST_PAGE_OFFSET_MASK));
1389	return pTb->aGCPhysPages[idxPage - 1];
1390	}
1391
1392
1393	/**
1394	* A chunk of memory in the TB allocator.
1395	*/
1396	typedef struct IEMTBCHUNK
1397	{
1398	/** Pointer to the translation blocks in this chunk. */
1399	PIEMTB paTbs;
1400	#ifdef IN_RING0
1401	/** Allocation handle. */
1402	RTR0MEMOBJ hMemObj;
1403	#endif
1404	} IEMTBCHUNK;
1405
1406	/**
1407	* A per-CPU translation block allocator.
1408	*
1409	* Because of how the IEMTBCACHE uses the lower 6 bits of the TB address to keep
1410	* the length of the collision list, and of course also for cache line alignment
1411	* reasons, the TBs must be allocated with at least 64-byte alignment.
1412	* Memory is there therefore allocated using one of the page aligned allocators.
1413	*
1414	*
1415	* To avoid wasting too much memory, it is allocated piecemeal as needed,
1416	* in chunks (IEMTBCHUNK) of 2 MiB or more. The TB has an 8-bit chunk index
1417	* that enables us to quickly calculate the allocation bitmap position when
1418	* freeing the translation block.
1419	*/
1420	typedef struct IEMTBALLOCATOR
1421	{
1422	/** Magic value (IEMTBALLOCATOR_MAGIC). */
1423	uint32_t uMagic;
1424
1425	#ifdef IEMTB_SIZE_IS_POWER_OF_TWO
1426	/** Mask corresponding to cTbsPerChunk - 1. */
1427	uint32_t fChunkMask;
1428	/** Shift count corresponding to cTbsPerChunk. */
1429	uint8_t cChunkShift;
1430	#else
1431	uint32_t uUnused;
1432	uint8_t bUnused;
1433	#endif
1434	/** Number of chunks we're allowed to allocate. */
1435	uint8_t cMaxChunks;
1436	/** Number of chunks currently populated. */
1437	uint16_t cAllocatedChunks;
1438	/** Number of translation blocks per chunk. */
1439	uint32_t cTbsPerChunk;
1440	/** Chunk size. */
1441	uint32_t cbPerChunk;
1442
1443	/** The maximum number of TBs. */
1444	uint32_t cMaxTbs;
1445	/** Total number of TBs in the populated chunks.
1446	* (cAllocatedChunks * cTbsPerChunk) */
1447	uint32_t cTotalTbs;
1448	/** The current number of TBs in use.
1449	* The number of free TBs: cAllocatedTbs - cInUseTbs; */
1450	uint32_t cInUseTbs;
1451	/** Statistics: Number of the cInUseTbs that are native ones. */
1452	uint32_t cNativeTbs;
1453	/** Statistics: Number of the cInUseTbs that are threaded ones. */
1454	uint32_t cThreadedTbs;
1455
1456	/** Where to start pruning TBs from when we're out.
1457	* See iemTbAllocatorAllocSlow for details. */
1458	uint32_t iPruneFrom;
1459	/** Hint about which bit to start scanning the bitmap from. */
1460	uint32_t iStartHint;
1461	/** Where to start pruning native TBs from when we're out of executable memory.
1462	* See iemTbAllocatorFreeupNativeSpace for details. */
1463	uint32_t iPruneNativeFrom;
1464	uint32_t uPadding;
1465
1466	/** Statistics: Number of TB allocation calls. */
1467	STAMCOUNTER StatAllocs;
1468	/** Statistics: Number of TB free calls. */
1469	STAMCOUNTER StatFrees;
1470	/** Statistics: Time spend pruning. */
1471	STAMPROFILE StatPrune;
1472	/** Statistics: Time spend pruning native TBs. */
1473	STAMPROFILE StatPruneNative;
1474
1475	/** The delayed free list (see iemTbAlloctorScheduleForFree). */
1476	PIEMTB pDelayedFreeHead;
1477
1478	/** Allocation chunks. */
1479	IEMTBCHUNK aChunks[256];
1480
1481	/** Allocation bitmap for all possible chunk chunks. */
1482	RT_FLEXIBLE_ARRAY_EXTENSION
1483	uint64_t bmAllocated[RT_FLEXIBLE_ARRAY];
1484	} IEMTBALLOCATOR;
1485	/** Pointer to a TB allocator. */
1486	typedef struct IEMTBALLOCATOR *PIEMTBALLOCATOR;
1487
1488	/** Magic value for the TB allocator (Emmet Harley Cohen). */
1489	#define IEMTBALLOCATOR_MAGIC UINT32_C(0x19900525)
1490
1491
1492	/**
1493	* A per-CPU translation block cache (hash table).
1494	*
1495	* The hash table is allocated once during IEM initialization and size double
1496	* the max TB count, rounded up to the nearest power of two (so we can use and
1497	* AND mask rather than a rest division when hashing).
1498	*/
1499	typedef struct IEMTBCACHE
1500	{
1501	/** Magic value (IEMTBCACHE_MAGIC). */
1502	uint32_t uMagic;
1503	/** Size of the hash table. This is a power of two. */
1504	uint32_t cHash;
1505	/** The mask corresponding to cHash. */
1506	uint32_t uHashMask;
1507	uint32_t uPadding;
1508
1509	/** @name Statistics
1510	* @{ */
1511	/** Number of collisions ever. */
1512	STAMCOUNTER cCollisions;
1513
1514	/** Statistics: Number of TB lookup misses. */
1515	STAMCOUNTER cLookupMisses;
1516	/** Statistics: Number of TB lookup hits via hash table (debug only). */
1517	STAMCOUNTER cLookupHits;
1518	/** Statistics: Number of TB lookup hits via TB associated lookup table (debug only). */
1519	STAMCOUNTER cLookupHitsViaTbLookupTable;
1520	STAMCOUNTER auPadding2[2];
1521	/** Statistics: Collision list length pruning. */
1522	STAMPROFILE StatPrune;
1523	/** @} */
1524
1525	/** The hash table itself.
1526	* @note The lower 6 bits of the pointer is used for keeping the collision
1527	* list length, so we can take action when it grows too long.
1528	* This works because TBs are allocated using a 64 byte (or
1529	* higher) alignment from page aligned chunks of memory, so the lower
1530	* 6 bits of the address will always be zero.
1531	* See IEMTBCACHE_PTR_COUNT_MASK, IEMTBCACHE_PTR_MAKE and friends.
1532	*/
1533	RT_FLEXIBLE_ARRAY_EXTENSION
1534	PIEMTB apHash[RT_FLEXIBLE_ARRAY];
1535	} IEMTBCACHE;
1536	/** Pointer to a per-CPU translation block cahce. */
1537	typedef IEMTBCACHE *PIEMTBCACHE;
1538
1539	/** Magic value for IEMTBCACHE (Johnny O'Neal). */
1540	#define IEMTBCACHE_MAGIC UINT32_C(0x19561010)
1541
1542	/** The collision count mask for IEMTBCACHE::apHash entries. */
1543	#define IEMTBCACHE_PTR_COUNT_MASK ((uintptr_t)0x3f)
1544	/** The max collision count for IEMTBCACHE::apHash entries before pruning. */
1545	#define IEMTBCACHE_PTR_MAX_COUNT ((uintptr_t)0x30)
1546	/** Combine a TB pointer and a collision list length into a value for an
1547	* IEMTBCACHE::apHash entry. */
1548	#define IEMTBCACHE_PTR_MAKE(a_pTb, a_cCount) (PIEMTB)((uintptr_t)(a_pTb) \| (a_cCount))
1549	/** Combine a TB pointer and a collision list length into a value for an
1550	* IEMTBCACHE::apHash entry. */
1551	#define IEMTBCACHE_PTR_GET_TB(a_pHashEntry) (PIEMTB)((uintptr_t)(a_pHashEntry) & ~IEMTBCACHE_PTR_COUNT_MASK)
1552	/** Combine a TB pointer and a collision list length into a value for an
1553	* IEMTBCACHE::apHash entry. */
1554	#define IEMTBCACHE_PTR_GET_COUNT(a_pHashEntry) ((uintptr_t)(a_pHashEntry) & IEMTBCACHE_PTR_COUNT_MASK)
1555
1556	/**
1557	* Calculates the hash table slot for a TB from physical PC address and TB flags.
1558	*/
1559	#define IEMTBCACHE_HASH(a_paCache, a_fTbFlags, a_GCPhysPc) \
1560	IEMTBCACHE_HASH_NO_KEY_MASK(a_paCache, (a_fTbFlags) & IEMTB_F_KEY_MASK, a_GCPhysPc)
1561
1562	/**
1563	* Calculates the hash table slot for a TB from physical PC address and TB
1564	* flags, ASSUMING the caller has applied IEMTB_F_KEY_MASK to @a a_fTbFlags.
1565	*/
1566	#define IEMTBCACHE_HASH_NO_KEY_MASK(a_paCache, a_fTbFlags, a_GCPhysPc) \
1567	(((uint32_t)(a_GCPhysPc) ^ (a_fTbFlags)) & (a_paCache)->uHashMask)
1568
1569
1570	/** @name IEMBRANCHED_F_XXX - Branched indicator (IEMCPU::fTbBranched).
1571	*
1572	* These flags parallels the main IEM_CIMPL_F_BRANCH_XXX flags.
1573	*
1574	* @{ */
1575	/** Value if no branching happened recently. */
1576	#define IEMBRANCHED_F_NO UINT8_C(0x00)
1577	/** Flag set if direct branch, clear if absolute or indirect. */
1578	#define IEMBRANCHED_F_DIRECT UINT8_C(0x01)
1579	/** Flag set if indirect branch, clear if direct or relative. */
1580	#define IEMBRANCHED_F_INDIRECT UINT8_C(0x02)
1581	/** Flag set if relative branch, clear if absolute or indirect. */
1582	#define IEMBRANCHED_F_RELATIVE UINT8_C(0x04)
1583	/** Flag set if conditional branch, clear if unconditional. */
1584	#define IEMBRANCHED_F_CONDITIONAL UINT8_C(0x08)
1585	/** Flag set if it's a far branch. */
1586	#define IEMBRANCHED_F_FAR UINT8_C(0x10)
1587	/** Flag set if the stack pointer is modified. */
1588	#define IEMBRANCHED_F_STACK UINT8_C(0x20)
1589	/** Flag set if the stack pointer and (maybe) the stack segment are modified. */
1590	#define IEMBRANCHED_F_STACK_FAR UINT8_C(0x40)
1591	/** Flag set (by IEM_MC_REL_JMP_XXX) if it's a zero bytes relative jump. */
1592	#define IEMBRANCHED_F_ZERO UINT8_C(0x80)
1593	/** @} */
1594
1595
1596	/**
1597	* The per-CPU IEM state.
1598	*/
1599	typedef struct IEMCPU
1600	{
1601	/** Info status code that needs to be propagated to the IEM caller.
1602	* This cannot be passed internally, as it would complicate all success
1603	* checks within the interpreter making the code larger and almost impossible
1604	* to get right. Instead, we'll store status codes to pass on here. Each
1605	* source of these codes will perform appropriate sanity checks. */
1606	int32_t rcPassUp; /* 0x00 */
1607	/** Execution flag, IEM_F_XXX. */
1608	uint32_t fExec; /* 0x04 */
1609
1610	/** @name Decoder state.
1611	* @{ */
1612	#ifdef IEM_WITH_CODE_TLB
1613	/** The offset of the next instruction byte. */
1614	uint32_t offInstrNextByte; /* 0x08 */
1615	/** The number of bytes available at pbInstrBuf for the current instruction.
1616	* This takes the max opcode length into account so that doesn't need to be
1617	* checked separately. */
1618	uint32_t cbInstrBuf; /* 0x0c */
1619	/** Pointer to the page containing RIP, user specified buffer or abOpcode.
1620	* This can be NULL if the page isn't mappable for some reason, in which
1621	* case we'll do fallback stuff.
1622	*
1623	* If we're executing an instruction from a user specified buffer,
1624	* IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
1625	* aligned pointer but pointer to the user data.
1626	*
1627	* For instructions crossing pages, this will start on the first page and be
1628	* advanced to the next page by the time we've decoded the instruction. This
1629	* therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
1630	*/
1631	uint8_t const pbInstrBuf; / 0x10 */
1632	# if ARCH_BITS == 32
1633	uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
1634	# endif
1635	/** The program counter corresponding to pbInstrBuf.
1636	* This is set to a non-canonical address when we need to invalidate it. */
1637	uint64_t uInstrBufPc; /* 0x18 */
1638	/** The guest physical address corresponding to pbInstrBuf. */
1639	RTGCPHYS GCPhysInstrBuf; /* 0x20 */
1640	/** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
1641	* This takes the CS segment limit into account.
1642	* @note Set to zero when the code TLB is flushed to trigger TLB reload. */
1643	uint16_t cbInstrBufTotal; /* 0x28 */
1644	/** Offset into pbInstrBuf of the first byte of the current instruction.
1645	* Can be negative to efficiently handle cross page instructions. */
1646	int16_t offCurInstrStart; /* 0x2a */
1647
1648	# ifndef IEM_WITH_OPAQUE_DECODER_STATE
1649	/** The prefix mask (IEM_OP_PRF_XXX). */
1650	uint32_t fPrefixes; /* 0x2c */
1651	/** The extra REX ModR/M register field bit (REX.R << 3). */
1652	uint8_t uRexReg; /* 0x30 */
1653	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
1654	* (REX.B << 3). */
1655	uint8_t uRexB; /* 0x31 */
1656	/** The extra REX SIB index field bit (REX.X << 3). */
1657	uint8_t uRexIndex; /* 0x32 */
1658
1659	/** The effective segment register (X86_SREG_XXX). */
1660	uint8_t iEffSeg; /* 0x33 */
1661
1662	/** The offset of the ModR/M byte relative to the start of the instruction. */
1663	uint8_t offModRm; /* 0x34 */
1664
1665	# ifdef IEM_WITH_CODE_TLB_AND_OPCODE_BUF
1666	/** The current offset into abOpcode. */
1667	uint8_t offOpcode; /* 0x35 */
1668	# else
1669	uint8_t bUnused; /* 0x35 */
1670	# endif
1671	# else /* IEM_WITH_OPAQUE_DECODER_STATE */
1672	uint8_t abOpaqueDecoderPart1[0x36 - 0x2c];
1673	# endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1674
1675	#else /* !IEM_WITH_CODE_TLB */
1676	# ifndef IEM_WITH_OPAQUE_DECODER_STATE
1677	/** The size of what has currently been fetched into abOpcode. */
1678	uint8_t cbOpcode; /* 0x08 */
1679	/** The current offset into abOpcode. */
1680	uint8_t offOpcode; /* 0x09 */
1681	/** The offset of the ModR/M byte relative to the start of the instruction. */
1682	uint8_t offModRm; /* 0x0a */
1683
1684	/** The effective segment register (X86_SREG_XXX). */
1685	uint8_t iEffSeg; /* 0x0b */
1686
1687	/** The prefix mask (IEM_OP_PRF_XXX). */
1688	uint32_t fPrefixes; /* 0x0c */
1689	/** The extra REX ModR/M register field bit (REX.R << 3). */
1690	uint8_t uRexReg; /* 0x10 */
1691	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
1692	* (REX.B << 3). */
1693	uint8_t uRexB; /* 0x11 */
1694	/** The extra REX SIB index field bit (REX.X << 3). */
1695	uint8_t uRexIndex; /* 0x12 */
1696
1697	# else /* IEM_WITH_OPAQUE_DECODER_STATE */
1698	uint8_t abOpaqueDecoderPart1[0x13 - 0x08];
1699	# endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1700	#endif /* !IEM_WITH_CODE_TLB */
1701
1702	#ifndef IEM_WITH_OPAQUE_DECODER_STATE
1703	/** The effective operand mode. */
1704	IEMMODE enmEffOpSize; /* 0x36, 0x13 */
1705	/** The default addressing mode. */
1706	IEMMODE enmDefAddrMode; /* 0x37, 0x14 */
1707	/** The effective addressing mode. */
1708	IEMMODE enmEffAddrMode; /* 0x38, 0x15 */
1709	/** The default operand mode. */
1710	IEMMODE enmDefOpSize; /* 0x39, 0x16 */
1711
1712	/** Prefix index (VEX.pp) for two byte and three byte tables. */
1713	uint8_t idxPrefix; /* 0x3a, 0x17 */
1714	/** 3rd VEX/EVEX/XOP register.
1715	* Please use IEM_GET_EFFECTIVE_VVVV to access. */
1716	uint8_t uVex3rdReg; /* 0x3b, 0x18 */
1717	/** The VEX/EVEX/XOP length field. */
1718	uint8_t uVexLength; /* 0x3c, 0x19 */
1719	/** Additional EVEX stuff. */
1720	uint8_t fEvexStuff; /* 0x3d, 0x1a */
1721
1722	# ifndef IEM_WITH_CODE_TLB
1723	/** Explicit alignment padding. */
1724	uint8_t abAlignment2a[1]; /* 0x1b */
1725	# endif
1726	/** The FPU opcode (FOP). */
1727	uint16_t uFpuOpcode; /* 0x3e, 0x1c */
1728	# ifndef IEM_WITH_CODE_TLB
1729	/** Explicit alignment padding. */
1730	uint8_t abAlignment2b[2]; /* 0x1e */
1731	# endif
1732
1733	/** The opcode bytes. */
1734	uint8_t abOpcode[15]; /* 0x40, 0x20 */
1735	/** Explicit alignment padding. */
1736	# ifdef IEM_WITH_CODE_TLB
1737	//uint8_t abAlignment2c[0x4f - 0x4f]; /* 0x4f */
1738	# else
1739	uint8_t abAlignment2c[0x4f - 0x2f]; /* 0x2f */
1740	# endif
1741
1742	#else /* IEM_WITH_OPAQUE_DECODER_STATE */
1743	# ifdef IEM_WITH_CODE_TLB
1744	uint8_t abOpaqueDecoderPart2[0x4f - 0x36];
1745	# else
1746	uint8_t abOpaqueDecoderPart2[0x4f - 0x13];
1747	# endif
1748	#endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1749	/** @} */
1750
1751
1752	/** The number of active guest memory mappings. */
1753	uint8_t cActiveMappings; /* 0x4f, 0x4f */
1754
1755	/** Records for tracking guest memory mappings. */
1756	struct
1757	{
1758	/** The address of the mapped bytes. */
1759	R3R0PTRTYPE(void *) pv;
1760	/** The access flags (IEM_ACCESS_XXX).
1761	* IEM_ACCESS_INVALID if the entry is unused. */
1762	uint32_t fAccess;
1763	#if HC_ARCH_BITS == 64
1764	uint32_t u32Alignment4; /*< Alignment padding. /
1765	#endif
1766	} aMemMappings[3]; /* 0x50 LB 0x30 */
1767
1768	/** Locking records for the mapped memory. */
1769	union
1770	{
1771	PGMPAGEMAPLOCK Lock;
1772	uint64_t au64Padding[2];
1773	} aMemMappingLocks[3]; /* 0x80 LB 0x30 */
1774
1775	/** Bounce buffer info.
1776	* This runs in parallel to aMemMappings. */
1777	struct
1778	{
1779	/** The physical address of the first byte. */
1780	RTGCPHYS GCPhysFirst;
1781	/** The physical address of the second page. */
1782	RTGCPHYS GCPhysSecond;
1783	/** The number of bytes in the first page. */
1784	uint16_t cbFirst;
1785	/** The number of bytes in the second page. */
1786	uint16_t cbSecond;
1787	/** Whether it's unassigned memory. */
1788	bool fUnassigned;
1789	/** Explicit alignment padding. */
1790	bool afAlignment5[3];
1791	} aMemBbMappings[3]; /* 0xb0 LB 0x48 */
1792
1793	/** The flags of the current exception / interrupt. */
1794	uint32_t fCurXcpt; /* 0xf8 */
1795	/** The current exception / interrupt. */
1796	uint8_t uCurXcpt; /* 0xfc */
1797	/** Exception / interrupt recursion depth. */
1798	int8_t cXcptRecursions; /* 0xfb */
1799
1800	/** The next unused mapping index.
1801	* @todo try find room for this up with cActiveMappings. */
1802	uint8_t iNextMapping; /* 0xfd */
1803	uint8_t abAlignment7[1];
1804
1805	/** Bounce buffer storage.
1806	* This runs in parallel to aMemMappings and aMemBbMappings. */
1807	struct
1808	{
1809	uint8_t ab[512];
1810	} aBounceBuffers[3]; /* 0x100 LB 0x600 */
1811
1812
1813	/** Pointer set jump buffer - ring-3 context. */
1814	R3PTRTYPE(jmp_buf *) pJmpBufR3;
1815	/** Pointer set jump buffer - ring-0 context. */
1816	R0PTRTYPE(jmp_buf *) pJmpBufR0;
1817
1818	/** @todo Should move this near @a fCurXcpt later. */
1819	/** The CR2 for the current exception / interrupt. */
1820	uint64_t uCurXcptCr2;
1821	/** The error code for the current exception / interrupt. */
1822	uint32_t uCurXcptErr;
1823
1824	/** @name Statistics
1825	* @{ */
1826	/** The number of instructions we've executed. */
1827	uint32_t cInstructions;
1828	/** The number of potential exits. */
1829	uint32_t cPotentialExits;
1830	/** The number of bytes data or stack written (mostly for IEMExecOneEx).
1831	* This may contain uncommitted writes. */
1832	uint32_t cbWritten;
1833	/** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
1834	uint32_t cRetInstrNotImplemented;
1835	/** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
1836	uint32_t cRetAspectNotImplemented;
1837	/** Counts informational statuses returned (other than VINF_SUCCESS). */
1838	uint32_t cRetInfStatuses;
1839	/** Counts other error statuses returned. */
1840	uint32_t cRetErrStatuses;
1841	/** Number of times rcPassUp has been used. */
1842	uint32_t cRetPassUpStatus;
1843	/** Number of times RZ left with instruction commit pending for ring-3. */
1844	uint32_t cPendingCommit;
1845	/** Number of misaligned (host sense) atomic instruction accesses. */
1846	uint32_t cMisalignedAtomics;
1847	/** Number of long jumps. */
1848	uint32_t cLongJumps;
1849	/** @} */
1850
1851	/** @name Target CPU information.
1852	* @{ */
1853	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
1854	/** The target CPU. */
1855	uint8_t uTargetCpu;
1856	#else
1857	uint8_t bTargetCpuPadding;
1858	#endif
1859	/** For selecting assembly works matching the target CPU EFLAGS behaviour, see
1860	* IEMTARGETCPU_EFL_BEHAVIOR_XXX for values, with the 1st entry for when no
1861	* native host support and the 2nd for when there is.
1862	*
1863	* The two values are typically indexed by a g_CpumHostFeatures bit.
1864	*
1865	* This is for instance used for the BSF & BSR instructions where AMD and
1866	* Intel CPUs produce different EFLAGS. */
1867	uint8_t aidxTargetCpuEflFlavour[2];
1868
1869	/** The CPU vendor. */
1870	CPUMCPUVENDOR enmCpuVendor;
1871	/** @} */
1872
1873	/** @name Host CPU information.
1874	* @{ */
1875	/** The CPU vendor. */
1876	CPUMCPUVENDOR enmHostCpuVendor;
1877	/** @} */
1878
1879	/** Counts RDMSR \#GP(0) LogRel(). */
1880	uint8_t cLogRelRdMsr;
1881	/** Counts WRMSR \#GP(0) LogRel(). */
1882	uint8_t cLogRelWrMsr;
1883	/** Alignment padding. */
1884	uint8_t abAlignment9[42];
1885
1886	/** @name Recompilation
1887	* @{ */
1888	/** Pointer to the current translation block.
1889	* This can either be one being executed or one being compiled. */
1890	R3PTRTYPE(PIEMTB) pCurTbR3;
1891	#ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
1892	/** Frame pointer for the last native TB to execute. */
1893	R3PTRTYPE(void *) pvTbFramePointerR3;
1894	#else
1895	R3PTRTYPE(void *) pvUnusedR3;
1896	#endif
1897	/** Fixed TB used for threaded recompilation.
1898	* This is allocated once with maxed-out sizes and re-used afterwards. */
1899	R3PTRTYPE(PIEMTB) pThrdCompileTbR3;
1900	/** Pointer to the ring-3 TB cache for this EMT. */
1901	R3PTRTYPE(PIEMTBCACHE) pTbCacheR3;
1902	/** Pointer to the ring-3 TB lookup entry.
1903	* This either points to pTbLookupEntryDummyR3 or an actually lookuptable
1904	* entry, thus it can always safely be used w/o NULL checking. */
1905	R3PTRTYPE(PIEMTB *) ppTbLookupEntryR3;
1906	/** The PC (RIP) at the start of pCurTbR3/pCurTbR0.
1907	* The TBs are based on physical addresses, so this is needed to correleated
1908	* RIP to opcode bytes stored in the TB (AMD-V / VT-x). */
1909	uint64_t uCurTbStartPc;
1910	/** Number of threaded TBs executed. */
1911	uint64_t cTbExecThreaded;
1912	/** Number of native TBs executed. */
1913	uint64_t cTbExecNative;
1914	/** Whether we need to check the opcode bytes for the current instruction.
1915	* This is set by a previous instruction if it modified memory or similar. */
1916	bool fTbCheckOpcodes;
1917	/** Indicates whether and how we just branched - IEMBRANCHED_F_XXX. */
1918	uint8_t fTbBranched;
1919	/** Set when GCPhysInstrBuf is updated because of a page crossing. */
1920	bool fTbCrossedPage;
1921	/** Whether to end the current TB. */
1922	bool fEndTb;
1923	/** Number of instructions before we need emit an IRQ check call again.
1924	* This helps making sure we don't execute too long w/o checking for
1925	* interrupts and immediately following instructions that may enable
1926	* interrupts (e.g. POPF, IRET, STI). With STI an additional hack is
1927	* required to make sure we check following the next instruction as well, see
1928	* fTbCurInstrIsSti. */
1929	uint8_t cInstrTillIrqCheck;
1930	/** Indicates that the current instruction is an STI. This is set by the
1931	* iemCImpl_sti code and subsequently cleared by the recompiler. */
1932	bool fTbCurInstrIsSti;
1933	/** The size of the IEMTB::pabOpcodes allocation in pThrdCompileTbR3. */
1934	uint16_t cbOpcodesAllocated;
1935	/** The current instruction number in a native TB.
1936	* This is set by code that may trigger an unexpected TB exit (throw/longjmp)
1937	* and will be picked up by the TB execution loop. Only used when
1938	* IEMNATIVE_WITH_INSTRUCTION_COUNTING is defined. */
1939	uint8_t idxTbCurInstr;
1940	/** Spaced reserved for recompiler data / alignment. */
1941	bool afRecompilerStuff1[3];
1942	/** The virtual sync time at the last timer poll call. */
1943	uint32_t msRecompilerPollNow;
1944	/** The IEMTB::cUsed value when to attempt native recompilation of a TB. */
1945	uint32_t uTbNativeRecompileAtUsedCount;
1946	/** The IEM_CIMPL_F_XXX mask for the current instruction. */
1947	uint32_t fTbCurInstr;
1948	/** The IEM_CIMPL_F_XXX mask for the previous instruction. */
1949	uint32_t fTbPrevInstr;
1950	/** Strict: Tracking skipped EFLAGS calculations. Any bits set here are
1951	* currently not up to date in EFLAGS. */
1952	uint32_t fSkippingEFlags;
1953	/** Previous GCPhysInstrBuf value - only valid if fTbCrossedPage is set. */
1954	RTGCPHYS GCPhysInstrBufPrev;
1955	/** Pointer to the ring-3 TB allocator for this EMT. */
1956	R3PTRTYPE(PIEMTBALLOCATOR) pTbAllocatorR3;
1957	/** Pointer to the ring-3 executable memory allocator for this EMT. */
1958	R3PTRTYPE(struct IEMEXECMEMALLOCATOR *) pExecMemAllocatorR3;
1959	/** Pointer to the native recompiler state for ring-3. */
1960	R3PTRTYPE(struct IEMRECOMPILERSTATE *) pNativeRecompilerStateR3;
1961	/** Dummy entry for ppTbLookupEntryR3. */
1962	R3PTRTYPE(PIEMTB) pTbLookupEntryDummyR3;
1963
1964	/** Threaded TB statistics: Times TB execution was broken off before reaching the end. */
1965	STAMCOUNTER StatTbThreadedExecBreaks;
1966	/** Statistics: Times BltIn_CheckIrq breaks out of the TB. */
1967	STAMCOUNTER StatCheckIrqBreaks;
1968	/** Statistics: Times BltIn_CheckMode breaks out of the TB. */
1969	STAMCOUNTER StatCheckModeBreaks;
1970	/** Threaded TB statistics: Times execution break on call with lookup entries. */
1971	STAMCOUNTER StatTbThreadedExecBreaksWithLookup;
1972	/** Threaded TB statistics: Times execution break on call without lookup entries. */
1973	STAMCOUNTER StatTbThreadedExecBreaksWithoutLookup;
1974	/** Statistics: Times a post jump target check missed and had to find new TB. */
1975	STAMCOUNTER StatCheckBranchMisses;
1976	/** Statistics: Times a jump or page crossing required a TB with CS.LIM checking. */
1977	STAMCOUNTER StatCheckNeedCsLimChecking;
1978	/** Statistics: Times a loop was detected within a TB.. */
1979	STAMCOUNTER StatTbLoopInTbDetected;
1980	/** Exec memory allocator statistics: Number of times allocaintg executable memory failed. */
1981	STAMCOUNTER StatNativeExecMemInstrBufAllocFailed;
1982	/** Native TB statistics: Number of fully recompiled TBs. */
1983	STAMCOUNTER StatNativeFullyRecompiledTbs;
1984	/** TB statistics: Number of instructions per TB. */
1985	STAMPROFILE StatTbInstr;
1986	/** TB statistics: Number of TB lookup table entries per TB. */
1987	STAMPROFILE StatTbLookupEntries;
1988	/** Threaded TB statistics: Number of calls per TB. */
1989	STAMPROFILE StatTbThreadedCalls;
1990	/** Native TB statistics: Native code size per TB. */
1991	STAMPROFILE StatTbNativeCode;
1992	/** Native TB statistics: Profiling native recompilation. */
1993	STAMPROFILE StatNativeRecompilation;
1994	/** Native TB statistics: Number of calls per TB that were recompiled properly. */
1995	STAMPROFILE StatNativeCallsRecompiled;
1996	/** Native TB statistics: Number of threaded calls per TB that weren't recompiled. */
1997	STAMPROFILE StatNativeCallsThreaded;
1998	/** Native recompiled execution: TLB hits for data fetches. */
1999	STAMCOUNTER StatNativeTlbHitsForFetch;
2000	/** Native recompiled execution: TLB hits for data stores. */
2001	STAMCOUNTER StatNativeTlbHitsForStore;
2002	/** Native recompiled execution: TLB hits for stack accesses. */
2003	STAMCOUNTER StatNativeTlbHitsForStack;
2004	/** Native recompiled execution: TLB hits for mapped accesses. */
2005	STAMCOUNTER StatNativeTlbHitsForMapped;
2006	/** Native recompiled execution: Code TLB misses for new page. */
2007	STAMCOUNTER StatNativeCodeTlbMissesNewPage;
2008	/** Native recompiled execution: Code TLB hits for new page. */
2009	STAMCOUNTER StatNativeCodeTlbHitsForNewPage;
2010	/** Native recompiled execution: Code TLB misses for new page with offset. */
2011	STAMCOUNTER StatNativeCodeTlbMissesNewPageWithOffset;
2012	/** Native recompiled execution: Code TLB hits for new page with offset. */
2013	STAMCOUNTER StatNativeCodeTlbHitsForNewPageWithOffset;
2014
2015	/** Native recompiler: Number of calls to iemNativeRegAllocFindFree. */
2016	STAMCOUNTER StatNativeRegFindFree;
2017	/** Native recompiler: Number of times iemNativeRegAllocFindFree needed
2018	* to free a variable. */
2019	STAMCOUNTER StatNativeRegFindFreeVar;
2020	/** Native recompiler: Number of times iemNativeRegAllocFindFree did
2021	* not need to free any variables. */
2022	STAMCOUNTER StatNativeRegFindFreeNoVar;
2023	/** Native recompiler: Liveness info freed shadowed guest registers in
2024	* iemNativeRegAllocFindFree. */
2025	STAMCOUNTER StatNativeRegFindFreeLivenessUnshadowed;
2026	/** Native recompiler: Liveness info helped with the allocation in
2027	* iemNativeRegAllocFindFree. */
2028	STAMCOUNTER StatNativeRegFindFreeLivenessHelped;
2029
2030	/** Native recompiler: Number of times status flags calc has been skipped. */
2031	STAMCOUNTER StatNativeEflSkippedArithmetic;
2032	/** Native recompiler: Number of times status flags calc has been skipped. */
2033	STAMCOUNTER StatNativeEflSkippedLogical;
2034
2035	/** Native recompiler: Number of opportunities to skip EFLAGS.CF updating. */
2036	STAMCOUNTER StatNativeLivenessEflCfSkippable;
2037	/** Native recompiler: Number of opportunities to skip EFLAGS.PF updating. */
2038	STAMCOUNTER StatNativeLivenessEflPfSkippable;
2039	/** Native recompiler: Number of opportunities to skip EFLAGS.AF updating. */
2040	STAMCOUNTER StatNativeLivenessEflAfSkippable;
2041	/** Native recompiler: Number of opportunities to skip EFLAGS.ZF updating. */
2042	STAMCOUNTER StatNativeLivenessEflZfSkippable;
2043	/** Native recompiler: Number of opportunities to skip EFLAGS.SF updating. */
2044	STAMCOUNTER StatNativeLivenessEflSfSkippable;
2045	/** Native recompiler: Number of opportunities to skip EFLAGS.OF updating. */
2046	STAMCOUNTER StatNativeLivenessEflOfSkippable;
2047	/** Native recompiler: Number of required EFLAGS.CF updates. */
2048	STAMCOUNTER StatNativeLivenessEflCfRequired;
2049	/** Native recompiler: Number of required EFLAGS.PF updates. */
2050	STAMCOUNTER StatNativeLivenessEflPfRequired;
2051	/** Native recompiler: Number of required EFLAGS.AF updates. */
2052	STAMCOUNTER StatNativeLivenessEflAfRequired;
2053	/** Native recompiler: Number of required EFLAGS.ZF updates. */
2054	STAMCOUNTER StatNativeLivenessEflZfRequired;
2055	/** Native recompiler: Number of required EFLAGS.SF updates. */
2056	STAMCOUNTER StatNativeLivenessEflSfRequired;
2057	/** Native recompiler: Number of required EFLAGS.OF updates. */
2058	STAMCOUNTER StatNativeLivenessEflOfRequired;
2059	/** Native recompiler: Number of potentially delayable EFLAGS.CF updates. */
2060	STAMCOUNTER StatNativeLivenessEflCfDelayable;
2061	/** Native recompiler: Number of potentially delayable EFLAGS.PF updates. */
2062	STAMCOUNTER StatNativeLivenessEflPfDelayable;
2063	/** Native recompiler: Number of potentially delayable EFLAGS.AF updates. */
2064	STAMCOUNTER StatNativeLivenessEflAfDelayable;
2065	/** Native recompiler: Number of potentially delayable EFLAGS.ZF updates. */
2066	STAMCOUNTER StatNativeLivenessEflZfDelayable;
2067	/** Native recompiler: Number of potentially delayable EFLAGS.SF updates. */
2068	STAMCOUNTER StatNativeLivenessEflSfDelayable;
2069	/** Native recompiler: Number of potentially delayable EFLAGS.OF updates. */
2070	STAMCOUNTER StatNativeLivenessEflOfDelayable;
2071
2072	/** Native recompiler: Number of potential PC updates in total. */
2073	STAMCOUNTER StatNativePcUpdateTotal;
2074	/** Native recompiler: Number of PC updates which could be delayed. */
2075	STAMCOUNTER StatNativePcUpdateDelayed;
2076
2077	//#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
2078	/** Native recompiler: Number of calls to iemNativeSimdRegAllocFindFree. */
2079	STAMCOUNTER StatNativeSimdRegFindFree;
2080	/** Native recompiler: Number of times iemNativeSimdRegAllocFindFree needed
2081	* to free a variable. */
2082	STAMCOUNTER StatNativeSimdRegFindFreeVar;
2083	/** Native recompiler: Number of times iemNativeSimdRegAllocFindFree did
2084	* not need to free any variables. */
2085	STAMCOUNTER StatNativeSimdRegFindFreeNoVar;
2086	/** Native recompiler: Liveness info freed shadowed guest registers in
2087	* iemNativeSimdRegAllocFindFree. */
2088	STAMCOUNTER StatNativeSimdRegFindFreeLivenessUnshadowed;
2089	/** Native recompiler: Liveness info helped with the allocation in
2090	* iemNativeSimdRegAllocFindFree. */
2091	STAMCOUNTER StatNativeSimdRegFindFreeLivenessHelped;
2092
2093	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() checks. */
2094	STAMCOUNTER StatNativeMaybeDeviceNotAvailXcptCheckPotential;
2095	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() checks. */
2096	STAMCOUNTER StatNativeMaybeWaitDeviceNotAvailXcptCheckPotential;
2097	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() checks. */
2098	STAMCOUNTER StatNativeMaybeSseXcptCheckPotential;
2099	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() checks. */
2100	STAMCOUNTER StatNativeMaybeAvxXcptCheckPotential;
2101
2102	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() checks omitted. */
2103	STAMCOUNTER StatNativeMaybeDeviceNotAvailXcptCheckOmitted;
2104	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() checks omitted. */
2105	STAMCOUNTER StatNativeMaybeWaitDeviceNotAvailXcptCheckOmitted;
2106	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() checks omitted. */
2107	STAMCOUNTER StatNativeMaybeSseXcptCheckOmitted;
2108	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() checks omitted. */
2109	STAMCOUNTER StatNativeMaybeAvxXcptCheckOmitted;
2110	//#endif
2111
2112	/** Native recompiler: The TB finished executing completely without jumping to a an exit label.
2113	* Not availabe in release builds. */
2114	STAMCOUNTER StatNativeTbFinished;
2115	/** Native recompiler: The TB finished executing jumping to the ReturnBreak label. */
2116	STAMCOUNTER StatNativeTbExitReturnBreak;
2117	/** Native recompiler: The TB finished executing jumping to the ReturnBreakFF label. */
2118	STAMCOUNTER StatNativeTbExitReturnBreakFF;
2119	/** Native recompiler: The TB finished executing jumping to the ReturnWithFlags label. */
2120	STAMCOUNTER StatNativeTbExitReturnWithFlags;
2121	/** Native recompiler: The TB finished executing with other non-zero status. */
2122	STAMCOUNTER StatNativeTbExitReturnOtherStatus;
2123	/** Native recompiler: The TB finished executing via throw / long jump. */
2124	STAMCOUNTER StatNativeTbExitLongJump;
2125	/** Native recompiler: The TB finished executing jumping to the ReturnBreak
2126	* label, but directly jumped to the next TB, scenario \#1 w/o IRQ checks. */
2127	STAMCOUNTER StatNativeTbExitDirectLinking1NoIrq;
2128	/** Native recompiler: The TB finished executing jumping to the ReturnBreak
2129	* label, but directly jumped to the next TB, scenario \#1 with IRQ checks. */
2130	STAMCOUNTER StatNativeTbExitDirectLinking1Irq;
2131	/** Native recompiler: The TB finished executing jumping to the ReturnBreak
2132	* label, but directly jumped to the next TB, scenario \#1 w/o IRQ checks. */
2133	STAMCOUNTER StatNativeTbExitDirectLinking2NoIrq;
2134	/** Native recompiler: The TB finished executing jumping to the ReturnBreak
2135	* label, but directly jumped to the next TB, scenario \#2 with IRQ checks. */
2136	STAMCOUNTER StatNativeTbExitDirectLinking2Irq;
2137
2138	/** Native recompiler: The TB finished executing jumping to the RaiseDe label. */
2139	STAMCOUNTER StatNativeTbExitRaiseDe;
2140	/** Native recompiler: The TB finished executing jumping to the RaiseUd label. */
2141	STAMCOUNTER StatNativeTbExitRaiseUd;
2142	/** Native recompiler: The TB finished executing jumping to the RaiseSseRelated label. */
2143	STAMCOUNTER StatNativeTbExitRaiseSseRelated;
2144	/** Native recompiler: The TB finished executing jumping to the RaiseAvxRelated label. */
2145	STAMCOUNTER StatNativeTbExitRaiseAvxRelated;
2146	/** Native recompiler: The TB finished executing jumping to the RaiseSseAvxFpRelated label. */
2147	STAMCOUNTER StatNativeTbExitRaiseSseAvxFpRelated;
2148	/** Native recompiler: The TB finished executing jumping to the RaiseNm label. */
2149	STAMCOUNTER StatNativeTbExitRaiseNm;
2150	/** Native recompiler: The TB finished executing jumping to the RaiseGp0 label. */
2151	STAMCOUNTER StatNativeTbExitRaiseGp0;
2152	/** Native recompiler: The TB finished executing jumping to the RaiseMf label. */
2153	STAMCOUNTER StatNativeTbExitRaiseMf;
2154	/** Native recompiler: The TB finished executing jumping to the RaiseXf label. */
2155	STAMCOUNTER StatNativeTbExitRaiseXf;
2156	/** Native recompiler: The TB finished executing jumping to the ObsoleteTb label. */
2157	STAMCOUNTER StatNativeTbExitObsoleteTb;
2158
2159	/** Native recompiler: Failure situations with direct linking scenario \#1.
2160	* Counter with StatNativeTbExitReturnBreak. Not in release builds.
2161	* @{ */
2162	STAMCOUNTER StatNativeTbExitDirectLinking1NoTb;
2163	STAMCOUNTER StatNativeTbExitDirectLinking1MismatchGCPhysPc;
2164	STAMCOUNTER StatNativeTbExitDirectLinking1MismatchFlags;
2165	STAMCOUNTER StatNativeTbExitDirectLinking1PendingIrq;
2166	/** @} */
2167
2168	/** Native recompiler: Failure situations with direct linking scenario \#2.
2169	* Counter with StatNativeTbExitReturnBreak. Not in release builds.
2170	* @{ */
2171	STAMCOUNTER StatNativeTbExitDirectLinking2NoTb;
2172	STAMCOUNTER StatNativeTbExitDirectLinking2MismatchGCPhysPc;
2173	STAMCOUNTER StatNativeTbExitDirectLinking2MismatchFlags;
2174	STAMCOUNTER StatNativeTbExitDirectLinking2PendingIrq;
2175	/** @} */
2176
2177	/** iemMemMap and iemMemMapJmp statistics.
2178	* @{ */
2179	STAMCOUNTER StatMemMapJmp;
2180	STAMCOUNTER StatMemMapNoJmp;
2181	STAMCOUNTER StatMemBounceBufferCrossPage;
2182	STAMCOUNTER StatMemBounceBufferMapPhys;
2183	/** @} */
2184
2185	uint64_t au64Padding[1];
2186	/** @} */
2187
2188	/** Data TLB.
2189	* @remarks Must be 64-byte aligned. */
2190	IEMTLB DataTlb;
2191	/** Instruction TLB.
2192	* @remarks Must be 64-byte aligned. */
2193	IEMTLB CodeTlb;
2194
2195	/** Exception statistics. */
2196	STAMCOUNTER aStatXcpts[32];
2197	/** Interrupt statistics. */
2198	uint32_t aStatInts[256];
2199
2200	#if defined(VBOX_WITH_STATISTICS) && !defined(DOXYGEN_RUNNING) && !defined(IEM_WITHOUT_INSTRUCTION_STATS)
2201	/** Instruction statistics for ring-0/raw-mode. */
2202	IEMINSTRSTATS StatsRZ;
2203	/** Instruction statistics for ring-3. */
2204	IEMINSTRSTATS StatsR3;
2205	# ifdef VBOX_WITH_IEM_RECOMPILER
2206	/** Statistics per threaded function call.
2207	* Updated by both the threaded and native recompilers. */
2208	uint32_t acThreadedFuncStats[0x6000 /24576/];
2209	# endif
2210	#endif
2211	} IEMCPU;
2212	AssertCompileMemberOffset(IEMCPU, cActiveMappings, 0x4f);
2213	AssertCompileMemberAlignment(IEMCPU, aMemMappings, 16);
2214	AssertCompileMemberAlignment(IEMCPU, aMemMappingLocks, 16);
2215	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 64);
2216	AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
2217	AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
2218
2219	/** Pointer to the per-CPU IEM state. */
2220	typedef IEMCPU *PIEMCPU;
2221	/** Pointer to the const per-CPU IEM state. */
2222	typedef IEMCPU const *PCIEMCPU;
2223
2224
2225	/** @def IEM_GET_CTX
2226	* Gets the guest CPU context for the calling EMT.
2227	* @returns PCPUMCTX
2228	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2229	*/
2230	#define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
2231
2232	/** @def IEM_CTX_ASSERT
2233	* Asserts that the @a a_fExtrnMbz is present in the CPU context.
2234	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2235	* @param a_fExtrnMbz The mask of CPUMCTX_EXTRN_XXX flags that must be zero.
2236	*/
2237	#define IEM_CTX_ASSERT(a_pVCpu, a_fExtrnMbz) \
2238	AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
2239	("fExtrn=%#RX64 & fExtrnMbz=%#RX64 -> %#RX64\n", \
2240	(a_pVCpu)->cpum.GstCtx.fExtrn, (a_fExtrnMbz), (a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz) ))
2241
2242	/** @def IEM_CTX_IMPORT_RET
2243	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
2244	*
2245	* Will call the keep to import the bits as needed.
2246	*
2247	* Returns on import failure.
2248	*
2249	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2250	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
2251	*/
2252	#define IEM_CTX_IMPORT_RET(a_pVCpu, a_fExtrnImport) \
2253	do { \
2254	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
2255	{ /* likely */ } \
2256	else \
2257	{ \
2258	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
2259	AssertRCReturn(rcCtxImport, rcCtxImport); \
2260	} \
2261	} while (0)
2262
2263	/** @def IEM_CTX_IMPORT_NORET
2264	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
2265	*
2266	* Will call the keep to import the bits as needed.
2267	*
2268	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2269	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
2270	*/
2271	#define IEM_CTX_IMPORT_NORET(a_pVCpu, a_fExtrnImport) \
2272	do { \
2273	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
2274	{ /* likely */ } \
2275	else \
2276	{ \
2277	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
2278	AssertLogRelRC(rcCtxImport); \
2279	} \
2280	} while (0)
2281
2282	/** @def IEM_CTX_IMPORT_JMP
2283	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
2284	*
2285	* Will call the keep to import the bits as needed.
2286	*
2287	* Jumps on import failure.
2288	*
2289	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2290	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
2291	*/
2292	#define IEM_CTX_IMPORT_JMP(a_pVCpu, a_fExtrnImport) \
2293	do { \
2294	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
2295	{ /* likely */ } \
2296	else \
2297	{ \
2298	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
2299	AssertRCStmt(rcCtxImport, IEM_DO_LONGJMP(pVCpu, rcCtxImport)); \
2300	} \
2301	} while (0)
2302
2303
2304
2305	/** @def IEM_GET_TARGET_CPU
2306	* Gets the current IEMTARGETCPU value.
2307	* @returns IEMTARGETCPU value.
2308	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2309	*/
2310	#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
2311	# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
2312	#else
2313	# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
2314	#endif
2315
2316	/** @def IEM_GET_INSTR_LEN
2317	* Gets the instruction length. */
2318	#ifdef IEM_WITH_CODE_TLB
2319	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
2320	#else
2321	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
2322	#endif
2323
2324	/** @def IEM_TRY_SETJMP
2325	* Wrapper around setjmp / try, hiding all the ugly differences.
2326	*
2327	* @note Use with extreme care as this is a fragile macro.
2328	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2329	* @param a_rcTarget The variable that should receive the status code in case
2330	* of a longjmp/throw.
2331	*/
2332	/** @def IEM_TRY_SETJMP_AGAIN
2333	* For when setjmp / try is used again in the same variable scope as a previous
2334	* IEM_TRY_SETJMP invocation.
2335	*/
2336	/** @def IEM_CATCH_LONGJMP_BEGIN
2337	* Start wrapper for catch / setjmp-else.
2338	*
2339	* This will set up a scope.
2340	*
2341	* @note Use with extreme care as this is a fragile macro.
2342	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2343	* @param a_rcTarget The variable that should receive the status code in case
2344	* of a longjmp/throw.
2345	*/
2346	/** @def IEM_CATCH_LONGJMP_END
2347	* End wrapper for catch / setjmp-else.
2348	*
2349	* This will close the scope set up by IEM_CATCH_LONGJMP_BEGIN and clean up the
2350	* state.
2351	*
2352	* @note Use with extreme care as this is a fragile macro.
2353	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2354	*/
2355	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
2356	# ifdef IEM_WITH_THROW_CATCH
2357	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
2358	a_rcTarget = VINF_SUCCESS; \
2359	try
2360	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
2361	IEM_TRY_SETJMP(a_pVCpu, a_rcTarget)
2362	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
2363	catch (int rcThrown) \
2364	{ \
2365	a_rcTarget = rcThrown
2366	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
2367	} \
2368	((void)0)
2369	# else /* !IEM_WITH_THROW_CATCH */
2370	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
2371	jmp_buf JmpBuf; \
2372	jmp_buf * volatile pSavedJmpBuf = (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf); \
2373	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
2374	if ((rcStrict = setjmp(JmpBuf)) == 0)
2375	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
2376	pSavedJmpBuf = (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf); \
2377	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
2378	if ((rcStrict = setjmp(JmpBuf)) == 0)
2379	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
2380	else \
2381	{ \
2382	((void)0)
2383	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
2384	} \
2385	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = pSavedJmpBuf
2386	# endif /* !IEM_WITH_THROW_CATCH */
2387	#endif /* IEM_WITH_SETJMP */
2388
2389
2390	/**
2391	* Shared per-VM IEM data.
2392	*/
2393	typedef struct IEM
2394	{
2395	/** The VMX APIC-access page handler type. */
2396	PGMPHYSHANDLERTYPE hVmxApicAccessPage;
2397	#ifndef VBOX_WITHOUT_CPUID_HOST_CALL
2398	/** Set if the CPUID host call functionality is enabled. */
2399	bool fCpuIdHostCall;
2400	#endif
2401	} IEM;
2402
2403
2404
2405	/** @name IEM_ACCESS_XXX - Access details.
2406	* @{ */
2407	#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
2408	#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
2409	#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
2410	#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
2411	#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
2412	#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
2413	#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
2414	#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
2415	#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
2416	#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
2417	/** The writes are partial, so if initialize the bounce buffer with the
2418	* orignal RAM content. */
2419	#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
2420	/** Used in aMemMappings to indicate that the entry is bounce buffered. */
2421	#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
2422	/** Bounce buffer with ring-3 write pending, first page. */
2423	#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
2424	/** Bounce buffer with ring-3 write pending, second page. */
2425	#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
2426	/** Not locked, accessed via the TLB. */
2427	#define IEM_ACCESS_NOT_LOCKED UINT32_C(0x00001000)
2428	/** Atomic access.
2429	* This enables special alignment checks and the VINF_EM_EMULATE_SPLIT_LOCK
2430	* fallback for misaligned stuff. See @bugref{10547}. */
2431	#define IEM_ACCESS_ATOMIC UINT32_C(0x00002000)
2432	/** Valid bit mask. */
2433	#define IEM_ACCESS_VALID_MASK UINT32_C(0x00003fff)
2434	/** Shift count for the TLB flags (upper word). */
2435	#define IEM_ACCESS_SHIFT_TLB_FLAGS 16
2436
2437	/** Atomic read+write data alias. */
2438	#define IEM_ACCESS_DATA_ATOMIC (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA \| IEM_ACCESS_ATOMIC)
2439	/** Read+write data alias. */
2440	#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
2441	/** Write data alias. */
2442	#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
2443	/** Read data alias. */
2444	#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_DATA)
2445	/** Instruction fetch alias. */
2446	#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_WHAT_CODE)
2447	/** Stack write alias. */
2448	#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
2449	/** Stack read alias. */
2450	#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_STACK)
2451	/** Stack read+write alias. */
2452	#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
2453	/** Read system table alias. */
2454	#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_SYS)
2455	/** Read+write system table alias. */
2456	#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_SYS)
2457	/** @} */
2458
2459	/** @name Prefix constants (IEMCPU::fPrefixes)
2460	* @{ */
2461	#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /*< CS segment prefix (0x2e). /
2462	#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /*< SS segment prefix (0x36). /
2463	#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /*< DS segment prefix (0x3e). /
2464	#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /*< ES segment prefix (0x26). /
2465	#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /*< FS segment prefix (0x64). /
2466	#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /*< GS segment prefix (0x65). /
2467	#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
2468
2469	#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /*< Operand size prefix (0x66). /
2470	#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /*< REX.W prefix (0x48-0x4f). /
2471	#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /*< Address size prefix (0x67). /
2472
2473	#define IEM_OP_PRF_LOCK RT_BIT_32(16) /*< Lock prefix (0xf0). /
2474	#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /*< Repeat-not-zero prefix (0xf2). /
2475	#define IEM_OP_PRF_REPZ RT_BIT_32(18) /*< Repeat-if-zero prefix (0xf3). /
2476
2477	#define IEM_OP_PRF_REX RT_BIT_32(24) /*< Any REX prefix (0x40-0x4f). /
2478	#define IEM_OP_PRF_REX_B RT_BIT_32(25) /*< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). /
2479	#define IEM_OP_PRF_REX_X RT_BIT_32(26) /*< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). /
2480	#define IEM_OP_PRF_REX_R RT_BIT_32(27) /*< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). /
2481	/** Mask with all the REX prefix flags.
2482	* This is generally for use when needing to undo the REX prefixes when they
2483	* are followed legacy prefixes and therefore does not immediately preceed
2484	* the first opcode byte.
2485	* For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
2486	#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX \| IEM_OP_PRF_REX_R \| IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X \| IEM_OP_PRF_SIZE_REX_W )
2487
2488	#define IEM_OP_PRF_VEX RT_BIT_32(28) /*< Indiciates VEX prefix. /
2489	#define IEM_OP_PRF_EVEX RT_BIT_32(29) /*< Indiciates EVEX prefix. /
2490	#define IEM_OP_PRF_XOP RT_BIT_32(30) /*< Indiciates XOP prefix. /
2491	/** @} */
2492
2493	/** @name IEMOPFORM_XXX - Opcode forms
2494	* @note These are ORed together with IEMOPHINT_XXX.
2495	* @{ */
2496	/** ModR/M: reg, r/m */
2497	#define IEMOPFORM_RM 0
2498	/** ModR/M: reg, r/m (register) */
2499	#define IEMOPFORM_RM_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
2500	/** ModR/M: reg, r/m (memory) */
2501	#define IEMOPFORM_RM_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
2502	/** ModR/M: reg, r/m, imm */
2503	#define IEMOPFORM_RMI 1
2504	/** ModR/M: reg, r/m (register), imm */
2505	#define IEMOPFORM_RMI_REG (IEMOPFORM_RMI \| IEMOPFORM_MOD3)
2506	/** ModR/M: reg, r/m (memory), imm */
2507	#define IEMOPFORM_RMI_MEM (IEMOPFORM_RMI \| IEMOPFORM_NOT_MOD3)
2508	/** ModR/M: reg, r/m, xmm0 */
2509	#define IEMOPFORM_RM0 2
2510	/** ModR/M: reg, r/m (register), xmm0 */
2511	#define IEMOPFORM_RM0_REG (IEMOPFORM_RM0 \| IEMOPFORM_MOD3)
2512	/** ModR/M: reg, r/m (memory), xmm0 */
2513	#define IEMOPFORM_RM0_MEM (IEMOPFORM_RM0 \| IEMOPFORM_NOT_MOD3)
2514	/** ModR/M: r/m, reg */
2515	#define IEMOPFORM_MR 3
2516	/** ModR/M: r/m (register), reg */
2517	#define IEMOPFORM_MR_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
2518	/** ModR/M: r/m (memory), reg */
2519	#define IEMOPFORM_MR_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
2520	/** ModR/M: r/m, reg, imm */
2521	#define IEMOPFORM_MRI 4
2522	/** ModR/M: r/m (register), reg, imm */
2523	#define IEMOPFORM_MRI_REG (IEMOPFORM_MRI \| IEMOPFORM_MOD3)
2524	/** ModR/M: r/m (memory), reg, imm */
2525	#define IEMOPFORM_MRI_MEM (IEMOPFORM_MRI \| IEMOPFORM_NOT_MOD3)
2526	/** ModR/M: r/m only */
2527	#define IEMOPFORM_M 5
2528	/** ModR/M: r/m only (register). */
2529	#define IEMOPFORM_M_REG (IEMOPFORM_M \| IEMOPFORM_MOD3)
2530	/** ModR/M: r/m only (memory). */
2531	#define IEMOPFORM_M_MEM (IEMOPFORM_M \| IEMOPFORM_NOT_MOD3)
2532	/** ModR/M: r/m, imm */
2533	#define IEMOPFORM_MI 6
2534	/** ModR/M: r/m (register), imm */
2535	#define IEMOPFORM_MI_REG (IEMOPFORM_MI \| IEMOPFORM_MOD3)
2536	/** ModR/M: r/m (memory), imm */
2537	#define IEMOPFORM_MI_MEM (IEMOPFORM_MI \| IEMOPFORM_NOT_MOD3)
2538	/** ModR/M: r/m, 1 (shift and rotate instructions) */
2539	#define IEMOPFORM_M1 7
2540	/** ModR/M: r/m (register), 1. */
2541	#define IEMOPFORM_M1_REG (IEMOPFORM_M1 \| IEMOPFORM_MOD3)
2542	/** ModR/M: r/m (memory), 1. */
2543	#define IEMOPFORM_M1_MEM (IEMOPFORM_M1 \| IEMOPFORM_NOT_MOD3)
2544	/** ModR/M: r/m, CL (shift and rotate instructions)
2545	* @todo This should just've been a generic fixed register. But the python
2546	* code doesn't needs more convincing. */
2547	#define IEMOPFORM_M_CL 8
2548	/** ModR/M: r/m (register), CL. */
2549	#define IEMOPFORM_M_CL_REG (IEMOPFORM_M_CL \| IEMOPFORM_MOD3)
2550	/** ModR/M: r/m (memory), CL. */
2551	#define IEMOPFORM_M_CL_MEM (IEMOPFORM_M_CL \| IEMOPFORM_NOT_MOD3)
2552	/** ModR/M: reg only */
2553	#define IEMOPFORM_R 9
2554
2555	/** VEX+ModR/M: reg, r/m */
2556	#define IEMOPFORM_VEX_RM 16
2557	/** VEX+ModR/M: reg, r/m (register) */
2558	#define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM \| IEMOPFORM_MOD3)
2559	/** VEX+ModR/M: reg, r/m (memory) */
2560	#define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM \| IEMOPFORM_NOT_MOD3)
2561	/** VEX+ModR/M: r/m, reg */
2562	#define IEMOPFORM_VEX_MR 17
2563	/** VEX+ModR/M: r/m (register), reg */
2564	#define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR \| IEMOPFORM_MOD3)
2565	/** VEX+ModR/M: r/m (memory), reg */
2566	#define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR \| IEMOPFORM_NOT_MOD3)
2567	/** VEX+ModR/M: r/m, reg, imm8 */
2568	#define IEMOPFORM_VEX_MRI 18
2569	/** VEX+ModR/M: r/m (register), reg, imm8 */
2570	#define IEMOPFORM_VEX_MRI_REG (IEMOPFORM_VEX_MRI \| IEMOPFORM_MOD3)
2571	/** VEX+ModR/M: r/m (memory), reg, imm8 */
2572	#define IEMOPFORM_VEX_MRI_MEM (IEMOPFORM_VEX_MRI \| IEMOPFORM_NOT_MOD3)
2573	/** VEX+ModR/M: r/m only */
2574	#define IEMOPFORM_VEX_M 19
2575	/** VEX+ModR/M: r/m only (register). */
2576	#define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M \| IEMOPFORM_MOD3)
2577	/** VEX+ModR/M: r/m only (memory). */
2578	#define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M \| IEMOPFORM_NOT_MOD3)
2579	/** VEX+ModR/M: reg only */
2580	#define IEMOPFORM_VEX_R 20
2581	/** VEX+ModR/M: reg, vvvv, r/m */
2582	#define IEMOPFORM_VEX_RVM 21
2583	/** VEX+ModR/M: reg, vvvv, r/m (register). */
2584	#define IEMOPFORM_VEX_RVM_REG (IEMOPFORM_VEX_RVM \| IEMOPFORM_MOD3)
2585	/** VEX+ModR/M: reg, vvvv, r/m (memory). */
2586	#define IEMOPFORM_VEX_RVM_MEM (IEMOPFORM_VEX_RVM \| IEMOPFORM_NOT_MOD3)
2587	/** VEX+ModR/M: reg, vvvv, r/m, imm */
2588	#define IEMOPFORM_VEX_RVMI 22
2589	/** VEX+ModR/M: reg, vvvv, r/m (register), imm. */
2590	#define IEMOPFORM_VEX_RVMI_REG (IEMOPFORM_VEX_RVMI \| IEMOPFORM_MOD3)
2591	/** VEX+ModR/M: reg, vvvv, r/m (memory), imm. */
2592	#define IEMOPFORM_VEX_RVMI_MEM (IEMOPFORM_VEX_RVMI \| IEMOPFORM_NOT_MOD3)
2593	/** VEX+ModR/M: reg, vvvv, r/m, imm(reg) */
2594	#define IEMOPFORM_VEX_RVMR 23
2595	/** VEX+ModR/M: reg, vvvv, r/m (register), imm(reg). */
2596	#define IEMOPFORM_VEX_RVMR_REG (IEMOPFORM_VEX_RVMI \| IEMOPFORM_MOD3)
2597	/** VEX+ModR/M: reg, vvvv, r/m (memory), imm(reg). */
2598	#define IEMOPFORM_VEX_RVMR_MEM (IEMOPFORM_VEX_RVMI \| IEMOPFORM_NOT_MOD3)
2599	/** VEX+ModR/M: reg, r/m, vvvv */
2600	#define IEMOPFORM_VEX_RMV 24
2601	/** VEX+ModR/M: reg, r/m, vvvv (register). */
2602	#define IEMOPFORM_VEX_RMV_REG (IEMOPFORM_VEX_RMV \| IEMOPFORM_MOD3)
2603	/** VEX+ModR/M: reg, r/m, vvvv (memory). */
2604	#define IEMOPFORM_VEX_RMV_MEM (IEMOPFORM_VEX_RMV \| IEMOPFORM_NOT_MOD3)
2605	/** VEX+ModR/M: reg, r/m, imm8 */
2606	#define IEMOPFORM_VEX_RMI 25
2607	/** VEX+ModR/M: reg, r/m, imm8 (register). */
2608	#define IEMOPFORM_VEX_RMI_REG (IEMOPFORM_VEX_RMI \| IEMOPFORM_MOD3)
2609	/** VEX+ModR/M: reg, r/m, imm8 (memory). */
2610	#define IEMOPFORM_VEX_RMI_MEM (IEMOPFORM_VEX_RMI \| IEMOPFORM_NOT_MOD3)
2611	/** VEX+ModR/M: r/m, vvvv, reg */
2612	#define IEMOPFORM_VEX_MVR 26
2613	/** VEX+ModR/M: r/m, vvvv, reg (register) */
2614	#define IEMOPFORM_VEX_MVR_REG (IEMOPFORM_VEX_MVR \| IEMOPFORM_MOD3)
2615	/** VEX+ModR/M: r/m, vvvv, reg (memory) */
2616	#define IEMOPFORM_VEX_MVR_MEM (IEMOPFORM_VEX_MVR \| IEMOPFORM_NOT_MOD3)
2617	/** VEX+ModR/M+/n: vvvv, r/m */
2618	#define IEMOPFORM_VEX_VM 27
2619	/** VEX+ModR/M+/n: vvvv, r/m (register) */
2620	#define IEMOPFORM_VEX_VM_REG (IEMOPFORM_VEX_VM \| IEMOPFORM_MOD3)
2621	/** VEX+ModR/M+/n: vvvv, r/m (memory) */
2622	#define IEMOPFORM_VEX_VM_MEM (IEMOPFORM_VEX_VM \| IEMOPFORM_NOT_MOD3)
2623	/** VEX+ModR/M+/n: vvvv, r/m, imm8 */
2624	#define IEMOPFORM_VEX_VMI 28
2625	/** VEX+ModR/M+/n: vvvv, r/m, imm8 (register) */
2626	#define IEMOPFORM_VEX_VMI_REG (IEMOPFORM_VEX_VMI \| IEMOPFORM_MOD3)
2627	/** VEX+ModR/M+/n: vvvv, r/m, imm8 (memory) */
2628	#define IEMOPFORM_VEX_VMI_MEM (IEMOPFORM_VEX_VMI \| IEMOPFORM_NOT_MOD3)
2629
2630	/** Fixed register instruction, no R/M. */
2631	#define IEMOPFORM_FIXED 32
2632
2633	/** The r/m is a register. */
2634	#define IEMOPFORM_MOD3 RT_BIT_32(8)
2635	/** The r/m is a memory access. */
2636	#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
2637	/** @} */
2638
2639	/** @name IEMOPHINT_XXX - Additional Opcode Hints
2640	* @note These are ORed together with IEMOPFORM_XXX.
2641	* @{ */
2642	/** Ignores the operand size prefix (66h). */
2643	#define IEMOPHINT_IGNORES_OZ_PFX RT_BIT_32(10)
2644	/** Ignores REX.W (aka WIG). */
2645	#define IEMOPHINT_IGNORES_REXW RT_BIT_32(11)
2646	/** Both the operand size prefixes (66h + REX.W) are ignored. */
2647	#define IEMOPHINT_IGNORES_OP_SIZES (IEMOPHINT_IGNORES_OZ_PFX \| IEMOPHINT_IGNORES_REXW)
2648	/** Allowed with the lock prefix. */
2649	#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
2650	/** The VEX.L value is ignored (aka LIG). */
2651	#define IEMOPHINT_VEX_L_IGNORED RT_BIT_32(12)
2652	/** The VEX.L value must be zero (i.e. 128-bit width only). */
2653	#define IEMOPHINT_VEX_L_ZERO RT_BIT_32(13)
2654	/** The VEX.L value must be one (i.e. 256-bit width only). */
2655	#define IEMOPHINT_VEX_L_ONE RT_BIT_32(14)
2656	/** The VEX.V value must be zero. */
2657	#define IEMOPHINT_VEX_V_ZERO RT_BIT_32(15)
2658	/** The REX.W/VEX.V value must be zero. */
2659	#define IEMOPHINT_REX_W_ZERO RT_BIT_32(16)
2660	#define IEMOPHINT_VEX_W_ZERO IEMOPHINT_REX_W_ZERO
2661	/** The REX.W/VEX.V value must be one. */
2662	#define IEMOPHINT_REX_W_ONE RT_BIT_32(17)
2663	#define IEMOPHINT_VEX_W_ONE IEMOPHINT_REX_W_ONE
2664
2665	/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
2666	#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
2667	/** @} */
2668
2669	/**
2670	* Possible hardware task switch sources.
2671	*/
2672	typedef enum IEMTASKSWITCH
2673	{
2674	/** Task switch caused by an interrupt/exception. */
2675	IEMTASKSWITCH_INT_XCPT = 1,
2676	/** Task switch caused by a far CALL. */
2677	IEMTASKSWITCH_CALL,
2678	/** Task switch caused by a far JMP. */
2679	IEMTASKSWITCH_JUMP,
2680	/** Task switch caused by an IRET. */
2681	IEMTASKSWITCH_IRET
2682	} IEMTASKSWITCH;
2683	AssertCompileSize(IEMTASKSWITCH, 4);
2684
2685	/**
2686	* Possible CrX load (write) sources.
2687	*/
2688	typedef enum IEMACCESSCRX
2689	{
2690	/** CrX access caused by 'mov crX' instruction. */
2691	IEMACCESSCRX_MOV_CRX,
2692	/** CrX (CR0) write caused by 'lmsw' instruction. */
2693	IEMACCESSCRX_LMSW,
2694	/** CrX (CR0) write caused by 'clts' instruction. */
2695	IEMACCESSCRX_CLTS,
2696	/** CrX (CR0) read caused by 'smsw' instruction. */
2697	IEMACCESSCRX_SMSW
2698	} IEMACCESSCRX;
2699
2700	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2701	/** @name IEM_SLAT_FAIL_XXX - Second-level address translation failure information.
2702	*
2703	* These flags provide further context to SLAT page-walk failures that could not be
2704	* determined by PGM (e.g, PGM is not privy to memory access permissions).
2705	*
2706	* @{
2707	*/
2708	/** Translating a nested-guest linear address failed accessing a nested-guest
2709	* physical address. */
2710	# define IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR RT_BIT_32(0)
2711	/** Translating a nested-guest linear address failed accessing a
2712	* paging-structure entry or updating accessed/dirty bits. */
2713	# define IEM_SLAT_FAIL_LINEAR_TO_PAGE_TABLE RT_BIT_32(1)
2714	/** @} */
2715
2716	DECLCALLBACK(FNPGMPHYSHANDLER) iemVmxApicAccessPageHandler;
2717	# ifndef IN_RING3
2718	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) iemVmxApicAccessPagePfHandler;
2719	# endif
2720	#endif
2721
2722	/**
2723	* Indicates to the verifier that the given flag set is undefined.
2724	*
2725	* Can be invoked again to add more flags.
2726	*
2727	* This is a NOOP if the verifier isn't compiled in.
2728	*
2729	* @note We're temporarily keeping this until code is converted to new
2730	* disassembler style opcode handling.
2731	*/
2732	#define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
2733
2734
2735	/** @def IEM_DECL_IMPL_TYPE
2736	* For typedef'ing an instruction implementation function.
2737	*
2738	* @param a_RetType The return type.
2739	* @param a_Name The name of the type.
2740	* @param a_ArgList The argument list enclosed in parentheses.
2741	*/
2742
2743	/** @def IEM_DECL_IMPL_DEF
2744	* For defining an instruction implementation function.
2745	*
2746	* @param a_RetType The return type.
2747	* @param a_Name The name of the type.
2748	* @param a_ArgList The argument list enclosed in parentheses.
2749	*/
2750
2751	#if defined(__GNUC__) && defined(RT_ARCH_X86)
2752	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2753	__attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
2754	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2755	__attribute__((__fastcall__, __nothrow__)) DECL_HIDDEN_ONLY(a_RetType) a_Name a_ArgList
2756	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2757	__attribute__((__fastcall__, __nothrow__)) DECL_HIDDEN_ONLY(a_RetType) a_Name a_ArgList
2758
2759	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
2760	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2761	a_RetType (__fastcall a_Name) a_ArgList
2762	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2763	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
2764	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2765	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
2766
2767	#elif __cplusplus >= 201700 /* P0012R1 support */
2768	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2769	a_RetType (VBOXCALL a_Name) a_ArgList RT_NOEXCEPT
2770	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2771	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList RT_NOEXCEPT
2772	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2773	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList RT_NOEXCEPT
2774
2775	#else
2776	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2777	a_RetType (VBOXCALL a_Name) a_ArgList
2778	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2779	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList
2780	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2781	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList
2782
2783	#endif
2784
2785	/** Defined in IEMAllAImplC.cpp but also used by IEMAllAImplA.asm. */
2786	RT_C_DECLS_BEGIN
2787	extern uint8_t const g_afParity[256];
2788	RT_C_DECLS_END
2789
2790
2791	/** @name Arithmetic assignment operations on bytes (binary).
2792	* @{ */
2793	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU8, (uint32_t fEFlagsIn, uint8_t *pu8Dst, uint8_t u8Src));
2794	typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
2795	FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
2796	FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
2797	FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
2798	FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
2799	FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
2800	FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
2801	FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
2802	/** @} */
2803
2804	/** @name Arithmetic assignment operations on words (binary).
2805	* @{ */
2806	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU16, (uint32_t fEFlagsIn, uint16_t *pu16Dst, uint16_t u16Src));
2807	typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
2808	FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
2809	FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
2810	FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
2811	FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
2812	FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
2813	FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
2814	FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
2815	/** @} */
2816
2817
2818	/** @name Arithmetic assignment operations on double words (binary).
2819	* @{ */
2820	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU32, (uint32_t fEFlagsIn, uint32_t *pu32Dst, uint32_t u32Src));
2821	typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
2822	FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
2823	FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
2824	FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
2825	FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
2826	FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
2827	FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
2828	FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
2829	FNIEMAIMPLBINU32 iemAImpl_blsi_u32, iemAImpl_blsi_u32_fallback;
2830	FNIEMAIMPLBINU32 iemAImpl_blsr_u32, iemAImpl_blsr_u32_fallback;
2831	FNIEMAIMPLBINU32 iemAImpl_blsmsk_u32, iemAImpl_blsmsk_u32_fallback;
2832	/** @} */
2833
2834	/** @name Arithmetic assignment operations on quad words (binary).
2835	* @{ */
2836	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU64, (uint32_t fEFlagsIn, uint64_t *pu64Dst, uint64_t u64Src));
2837	typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
2838	FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
2839	FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
2840	FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
2841	FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
2842	FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
2843	FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
2844	FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
2845	FNIEMAIMPLBINU64 iemAImpl_blsi_u64, iemAImpl_blsi_u64_fallback;
2846	FNIEMAIMPLBINU64 iemAImpl_blsr_u64, iemAImpl_blsr_u64_fallback;
2847	FNIEMAIMPLBINU64 iemAImpl_blsmsk_u64, iemAImpl_blsmsk_u64_fallback;
2848	/** @} */
2849
2850	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU8, (uint32_t fEFlagsIn, uint8_t const *pu8Dst, uint8_t u8Src));
2851	typedef FNIEMAIMPLBINROU8 *PFNIEMAIMPLBINROU8;
2852	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU16,(uint32_t fEFlagsIn, uint16_t const *pu16Dst, uint16_t u16Src));
2853	typedef FNIEMAIMPLBINROU16 *PFNIEMAIMPLBINROU16;
2854	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU32,(uint32_t fEFlagsIn, uint32_t const *pu32Dst, uint32_t u32Src));
2855	typedef FNIEMAIMPLBINROU32 *PFNIEMAIMPLBINROU32;
2856	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU64,(uint32_t fEFlagsIn, uint64_t const *pu64Dst, uint64_t u64Src));
2857	typedef FNIEMAIMPLBINROU64 *PFNIEMAIMPLBINROU64;
2858
2859	/** @name Compare operations (thrown in with the binary ops).
2860	* @{ */
2861	FNIEMAIMPLBINROU8 iemAImpl_cmp_u8;
2862	FNIEMAIMPLBINROU16 iemAImpl_cmp_u16;
2863	FNIEMAIMPLBINROU32 iemAImpl_cmp_u32;
2864	FNIEMAIMPLBINROU64 iemAImpl_cmp_u64;
2865	/** @} */
2866
2867	/** @name Test operations (thrown in with the binary ops).
2868	* @{ */
2869	FNIEMAIMPLBINROU8 iemAImpl_test_u8;
2870	FNIEMAIMPLBINROU16 iemAImpl_test_u16;
2871	FNIEMAIMPLBINROU32 iemAImpl_test_u32;
2872	FNIEMAIMPLBINROU64 iemAImpl_test_u64;
2873	/** @} */
2874
2875	/** @name Bit operations operations (thrown in with the binary ops).
2876	* @{ */
2877	FNIEMAIMPLBINROU16 iemAImpl_bt_u16;
2878	FNIEMAIMPLBINROU32 iemAImpl_bt_u32;
2879	FNIEMAIMPLBINROU64 iemAImpl_bt_u64;
2880	FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
2881	FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
2882	FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
2883	FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
2884	FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
2885	FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
2886	FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
2887	FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
2888	FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
2889	/** @} */
2890
2891	/** @name Arithmetic three operand operations on double words (binary).
2892	* @{ */
2893	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32, (uint32_t pu32Dst, uint32_t u32Src1, uint32_t u32Src2, uint32_t pEFlags));
2894	typedef FNIEMAIMPLBINVEXU32 *PFNIEMAIMPLBINVEXU32;
2895	FNIEMAIMPLBINVEXU32 iemAImpl_andn_u32, iemAImpl_andn_u32_fallback;
2896	FNIEMAIMPLBINVEXU32 iemAImpl_bextr_u32, iemAImpl_bextr_u32_fallback;
2897	FNIEMAIMPLBINVEXU32 iemAImpl_bzhi_u32, iemAImpl_bzhi_u32_fallback;
2898	/** @} */
2899
2900	/** @name Arithmetic three operand operations on quad words (binary).
2901	* @{ */
2902	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64, (uint64_t pu64Dst, uint64_t u64Src1, uint64_t u64Src2, uint32_t pEFlags));
2903	typedef FNIEMAIMPLBINVEXU64 *PFNIEMAIMPLBINVEXU64;
2904	FNIEMAIMPLBINVEXU64 iemAImpl_andn_u64, iemAImpl_andn_u64_fallback;
2905	FNIEMAIMPLBINVEXU64 iemAImpl_bextr_u64, iemAImpl_bextr_u64_fallback;
2906	FNIEMAIMPLBINVEXU64 iemAImpl_bzhi_u64, iemAImpl_bzhi_u64_fallback;
2907	/** @} */
2908
2909	/** @name Arithmetic three operand operations on double words w/o EFLAGS (binary).
2910	* @{ */
2911	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32NOEFL, (uint32_t *pu32Dst, uint32_t u32Src1, uint32_t u32Src2));
2912	typedef FNIEMAIMPLBINVEXU32NOEFL *PFNIEMAIMPLBINVEXU32NOEFL;
2913	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pdep_u32, iemAImpl_pdep_u32_fallback;
2914	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pext_u32, iemAImpl_pext_u32_fallback;
2915	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_sarx_u32, iemAImpl_sarx_u32_fallback;
2916	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shlx_u32, iemAImpl_shlx_u32_fallback;
2917	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shrx_u32, iemAImpl_shrx_u32_fallback;
2918	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_rorx_u32;
2919	/** @} */
2920
2921	/** @name Arithmetic three operand operations on quad words w/o EFLAGS (binary).
2922	* @{ */
2923	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64NOEFL, (uint64_t *pu64Dst, uint64_t u64Src1, uint64_t u64Src2));
2924	typedef FNIEMAIMPLBINVEXU64NOEFL *PFNIEMAIMPLBINVEXU64NOEFL;
2925	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pdep_u64, iemAImpl_pdep_u64_fallback;
2926	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pext_u64, iemAImpl_pext_u64_fallback;
2927	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_sarx_u64, iemAImpl_sarx_u64_fallback;
2928	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shlx_u64, iemAImpl_shlx_u64_fallback;
2929	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shrx_u64, iemAImpl_shrx_u64_fallback;
2930	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_rorx_u64;
2931	/** @} */
2932
2933	/** @name MULX 32-bit and 64-bit.
2934	* @{ */
2935	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU32, (uint32_t puDst1, uint32_t puDst2, uint32_t uSrc1, uint32_t uSrc2));
2936	typedef FNIEMAIMPLMULXVEXU32 *PFNIEMAIMPLMULXVEXU32;
2937	FNIEMAIMPLMULXVEXU32 iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback;
2938
2939	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU64, (uint64_t puDst1, uint64_t puDst2, uint64_t uSrc1, uint64_t uSrc2));
2940	typedef FNIEMAIMPLMULXVEXU64 *PFNIEMAIMPLMULXVEXU64;
2941	FNIEMAIMPLMULXVEXU64 iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback;
2942	/** @} */
2943
2944
2945	/** @name Exchange memory with register operations.
2946	* @{ */
2947	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_locked, (uint8_t pu8Mem, uint8_t pu8Reg));
2948	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_locked,(uint16_t pu16Mem, uint16_t pu16Reg));
2949	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_locked,(uint32_t pu32Mem, uint32_t pu32Reg));
2950	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_locked,(uint64_t pu64Mem, uint64_t pu64Reg));
2951	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_unlocked, (uint8_t pu8Mem, uint8_t pu8Reg));
2952	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_unlocked,(uint16_t pu16Mem, uint16_t pu16Reg));
2953	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_unlocked,(uint32_t pu32Mem, uint32_t pu32Reg));
2954	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_unlocked,(uint64_t pu64Mem, uint64_t pu64Reg));
2955	/** @} */
2956
2957	/** @name Exchange and add operations.
2958	* @{ */
2959	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
2960	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
2961	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
2962	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
2963	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
2964	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
2965	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
2966	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
2967	/** @} */
2968
2969	/** @name Compare and exchange.
2970	* @{ */
2971	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
2972	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
2973	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
2974	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
2975	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
2976	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
2977	#if ARCH_BITS == 32
2978	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
2979	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
2980	#else
2981	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
2982	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
2983	#endif
2984	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
2985	uint32_t *pEFlags));
2986	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
2987	uint32_t *pEFlags));
2988	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
2989	uint32_t *pEFlags));
2990	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
2991	uint32_t *pEFlags));
2992	#ifndef RT_ARCH_ARM64
2993	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
2994	PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
2995	#endif
2996	/** @} */
2997
2998	/** @name Memory ordering
2999	* @{ */
3000	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
3001	typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
3002	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
3003	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
3004	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
3005	#ifndef RT_ARCH_ARM64
3006	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
3007	#endif
3008	/** @} */
3009
3010	/** @name Double precision shifts
3011	* @{ */
3012	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t pEFlags));
3013	typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
3014	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t pEFlags));
3015	typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
3016	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t pEFlags));
3017	typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
3018	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16, iemAImpl_shld_u16_amd, iemAImpl_shld_u16_intel;
3019	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32, iemAImpl_shld_u32_amd, iemAImpl_shld_u32_intel;
3020	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64, iemAImpl_shld_u64_amd, iemAImpl_shld_u64_intel;
3021	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16, iemAImpl_shrd_u16_amd, iemAImpl_shrd_u16_intel;
3022	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32, iemAImpl_shrd_u32_amd, iemAImpl_shrd_u32_intel;
3023	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64, iemAImpl_shrd_u64_amd, iemAImpl_shrd_u64_intel;
3024	/** @} */
3025
3026
3027	/** @name Bit search operations (thrown in with the binary ops).
3028	* @{ */
3029	FNIEMAIMPLBINU16 iemAImpl_bsf_u16, iemAImpl_bsf_u16_amd, iemAImpl_bsf_u16_intel;
3030	FNIEMAIMPLBINU32 iemAImpl_bsf_u32, iemAImpl_bsf_u32_amd, iemAImpl_bsf_u32_intel;
3031	FNIEMAIMPLBINU64 iemAImpl_bsf_u64, iemAImpl_bsf_u64_amd, iemAImpl_bsf_u64_intel;
3032	FNIEMAIMPLBINU16 iemAImpl_bsr_u16, iemAImpl_bsr_u16_amd, iemAImpl_bsr_u16_intel;
3033	FNIEMAIMPLBINU32 iemAImpl_bsr_u32, iemAImpl_bsr_u32_amd, iemAImpl_bsr_u32_intel;
3034	FNIEMAIMPLBINU64 iemAImpl_bsr_u64, iemAImpl_bsr_u64_amd, iemAImpl_bsr_u64_intel;
3035	FNIEMAIMPLBINU16 iemAImpl_lzcnt_u16, iemAImpl_lzcnt_u16_amd, iemAImpl_lzcnt_u16_intel;
3036	FNIEMAIMPLBINU32 iemAImpl_lzcnt_u32, iemAImpl_lzcnt_u32_amd, iemAImpl_lzcnt_u32_intel;
3037	FNIEMAIMPLBINU64 iemAImpl_lzcnt_u64, iemAImpl_lzcnt_u64_amd, iemAImpl_lzcnt_u64_intel;
3038	FNIEMAIMPLBINU16 iemAImpl_tzcnt_u16, iemAImpl_tzcnt_u16_amd, iemAImpl_tzcnt_u16_intel;
3039	FNIEMAIMPLBINU32 iemAImpl_tzcnt_u32, iemAImpl_tzcnt_u32_amd, iemAImpl_tzcnt_u32_intel;
3040	FNIEMAIMPLBINU64 iemAImpl_tzcnt_u64, iemAImpl_tzcnt_u64_amd, iemAImpl_tzcnt_u64_intel;
3041	FNIEMAIMPLBINU16 iemAImpl_popcnt_u16, iemAImpl_popcnt_u16_fallback;
3042	FNIEMAIMPLBINU32 iemAImpl_popcnt_u32, iemAImpl_popcnt_u32_fallback;
3043	FNIEMAIMPLBINU64 iemAImpl_popcnt_u64, iemAImpl_popcnt_u64_fallback;
3044	/** @} */
3045
3046	/** @name Signed multiplication operations (thrown in with the binary ops).
3047	* @{ */
3048	FNIEMAIMPLBINU16 iemAImpl_imul_two_u16, iemAImpl_imul_two_u16_amd, iemAImpl_imul_two_u16_intel;
3049	FNIEMAIMPLBINU32 iemAImpl_imul_two_u32, iemAImpl_imul_two_u32_amd, iemAImpl_imul_two_u32_intel;
3050	FNIEMAIMPLBINU64 iemAImpl_imul_two_u64, iemAImpl_imul_two_u64_amd, iemAImpl_imul_two_u64_intel;
3051	/** @} */
3052
3053	/** @name Arithmetic assignment operations on bytes (unary).
3054	* @{ */
3055	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t pu8Dst, uint32_t pEFlags));
3056	typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
3057	FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
3058	FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
3059	FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
3060	FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
3061	/** @} */
3062
3063	/** @name Arithmetic assignment operations on words (unary).
3064	* @{ */
3065	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t pu16Dst, uint32_t pEFlags));
3066	typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
3067	FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
3068	FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
3069	FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
3070	FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
3071	/** @} */
3072
3073	/** @name Arithmetic assignment operations on double words (unary).
3074	* @{ */
3075	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t pu32Dst, uint32_t pEFlags));
3076	typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
3077	FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
3078	FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
3079	FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
3080	FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
3081	/** @} */
3082
3083	/** @name Arithmetic assignment operations on quad words (unary).
3084	* @{ */
3085	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t pu64Dst, uint32_t pEFlags));
3086	typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
3087	FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
3088	FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
3089	FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
3090	FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
3091	/** @} */
3092
3093
3094	/** @name Shift operations on bytes (Group 2).
3095	* @{ */
3096	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU8,(uint32_t fEFlagsIn, uint8_t *pu8Dst, uint8_t cShift));
3097	typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
3098	FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8, iemAImpl_rol_u8_amd, iemAImpl_rol_u8_intel;
3099	FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8, iemAImpl_ror_u8_amd, iemAImpl_ror_u8_intel;
3100	FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8, iemAImpl_rcl_u8_amd, iemAImpl_rcl_u8_intel;
3101	FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8, iemAImpl_rcr_u8_amd, iemAImpl_rcr_u8_intel;
3102	FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8, iemAImpl_shl_u8_amd, iemAImpl_shl_u8_intel;
3103	FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8, iemAImpl_shr_u8_amd, iemAImpl_shr_u8_intel;
3104	FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8, iemAImpl_sar_u8_amd, iemAImpl_sar_u8_intel;
3105	/** @} */
3106
3107	/** @name Shift operations on words (Group 2).
3108	* @{ */
3109	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU16,(uint32_t fEFlagsIn, uint16_t *pu16Dst, uint8_t cShift));
3110	typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
3111	FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16, iemAImpl_rol_u16_amd, iemAImpl_rol_u16_intel;
3112	FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16, iemAImpl_ror_u16_amd, iemAImpl_ror_u16_intel;
3113	FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16, iemAImpl_rcl_u16_amd, iemAImpl_rcl_u16_intel;
3114	FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16, iemAImpl_rcr_u16_amd, iemAImpl_rcr_u16_intel;
3115	FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16, iemAImpl_shl_u16_amd, iemAImpl_shl_u16_intel;
3116	FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16, iemAImpl_shr_u16_amd, iemAImpl_shr_u16_intel;
3117	FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16, iemAImpl_sar_u16_amd, iemAImpl_sar_u16_intel;
3118	/** @} */
3119
3120	/** @name Shift operations on double words (Group 2).
3121	* @{ */
3122	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU32,(uint32_t fEFlagsIn, uint32_t *pu32Dst, uint8_t cShift));
3123	typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
3124	FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32, iemAImpl_rol_u32_amd, iemAImpl_rol_u32_intel;
3125	FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32, iemAImpl_ror_u32_amd, iemAImpl_ror_u32_intel;
3126	FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32, iemAImpl_rcl_u32_amd, iemAImpl_rcl_u32_intel;
3127	FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32, iemAImpl_rcr_u32_amd, iemAImpl_rcr_u32_intel;
3128	FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32, iemAImpl_shl_u32_amd, iemAImpl_shl_u32_intel;
3129	FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32, iemAImpl_shr_u32_amd, iemAImpl_shr_u32_intel;
3130	FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32, iemAImpl_sar_u32_amd, iemAImpl_sar_u32_intel;
3131	/** @} */
3132
3133	/** @name Shift operations on words (Group 2).
3134	* @{ */
3135	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU64,(uint32_t fEFlagsIn, uint64_t *pu64Dst, uint8_t cShift));
3136	typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
3137	FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64, iemAImpl_rol_u64_amd, iemAImpl_rol_u64_intel;
3138	FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64, iemAImpl_ror_u64_amd, iemAImpl_ror_u64_intel;
3139	FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64, iemAImpl_rcl_u64_amd, iemAImpl_rcl_u64_intel;
3140	FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64, iemAImpl_rcr_u64_amd, iemAImpl_rcr_u64_intel;
3141	FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64, iemAImpl_shl_u64_amd, iemAImpl_shl_u64_intel;
3142	FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64, iemAImpl_shr_u64_amd, iemAImpl_shr_u64_intel;
3143	FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64, iemAImpl_sar_u64_amd, iemAImpl_sar_u64_intel;
3144	/** @} */
3145
3146	/** @name Multiplication and division operations.
3147	* @{ */
3148	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t pu16AX, uint8_t u8FactorDivisor, uint32_t pEFlags));
3149	typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
3150	FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_mul_u8_amd, iemAImpl_mul_u8_intel;
3151	FNIEMAIMPLMULDIVU8 iemAImpl_imul_u8, iemAImpl_imul_u8_amd, iemAImpl_imul_u8_intel;
3152	FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_div_u8_amd, iemAImpl_div_u8_intel;
3153	FNIEMAIMPLMULDIVU8 iemAImpl_idiv_u8, iemAImpl_idiv_u8_amd, iemAImpl_idiv_u8_intel;
3154
3155	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t pu16AX, uint16_t pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
3156	typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
3157	FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_mul_u16_amd, iemAImpl_mul_u16_intel;
3158	FNIEMAIMPLMULDIVU16 iemAImpl_imul_u16, iemAImpl_imul_u16_amd, iemAImpl_imul_u16_intel;
3159	FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_div_u16_amd, iemAImpl_div_u16_intel;
3160	FNIEMAIMPLMULDIVU16 iemAImpl_idiv_u16, iemAImpl_idiv_u16_amd, iemAImpl_idiv_u16_intel;
3161
3162	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t pu32EAX, uint32_t pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
3163	typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
3164	FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_mul_u32_amd, iemAImpl_mul_u32_intel;
3165	FNIEMAIMPLMULDIVU32 iemAImpl_imul_u32, iemAImpl_imul_u32_amd, iemAImpl_imul_u32_intel;
3166	FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_div_u32_amd, iemAImpl_div_u32_intel;
3167	FNIEMAIMPLMULDIVU32 iemAImpl_idiv_u32, iemAImpl_idiv_u32_amd, iemAImpl_idiv_u32_intel;
3168
3169	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t pu64RAX, uint64_t pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
3170	typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
3171	FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_mul_u64_amd, iemAImpl_mul_u64_intel;
3172	FNIEMAIMPLMULDIVU64 iemAImpl_imul_u64, iemAImpl_imul_u64_amd, iemAImpl_imul_u64_intel;
3173	FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_div_u64_amd, iemAImpl_div_u64_intel;
3174	FNIEMAIMPLMULDIVU64 iemAImpl_idiv_u64, iemAImpl_idiv_u64_amd, iemAImpl_idiv_u64_intel;
3175	/** @} */
3176
3177	/** @name Byte Swap.
3178	* @{ */
3179	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t pu32Dst)); / Yes, 32-bit register access. */
3180	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
3181	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
3182	/** @} */
3183
3184	/** @name Misc.
3185	* @{ */
3186	FNIEMAIMPLBINU16 iemAImpl_arpl;
3187	/** @} */
3188
3189	/** @name RDRAND and RDSEED
3190	* @{ */
3191	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU16,(uint16_t puDst, uint32_t pEFlags));
3192	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU32,(uint32_t puDst, uint32_t pEFlags));
3193	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU64,(uint64_t puDst, uint32_t pEFlags));
3194	typedef FNIEMAIMPLRDRANDSEEDU16 *PFNIEMAIMPLRDRANDSEEDU16;
3195	typedef FNIEMAIMPLRDRANDSEEDU32 *PFNIEMAIMPLRDRANDSEEDU32;
3196	typedef FNIEMAIMPLRDRANDSEEDU64 *PFNIEMAIMPLRDRANDSEEDU64;
3197
3198	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdrand_u16, iemAImpl_rdrand_u16_fallback;
3199	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdrand_u32, iemAImpl_rdrand_u32_fallback;
3200	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdrand_u64, iemAImpl_rdrand_u64_fallback;
3201	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdseed_u16, iemAImpl_rdseed_u16_fallback;
3202	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdseed_u32, iemAImpl_rdseed_u32_fallback;
3203	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdseed_u64, iemAImpl_rdseed_u64_fallback;
3204	/** @} */
3205
3206	/** @name ADOX and ADCX
3207	* @{ */
3208	FNIEMAIMPLBINU32 iemAImpl_adcx_u32, iemAImpl_adcx_u32_fallback;
3209	FNIEMAIMPLBINU64 iemAImpl_adcx_u64, iemAImpl_adcx_u64_fallback;
3210	FNIEMAIMPLBINU32 iemAImpl_adox_u32, iemAImpl_adox_u32_fallback;
3211	FNIEMAIMPLBINU64 iemAImpl_adox_u64, iemAImpl_adox_u64_fallback;
3212	/** @} */
3213
3214	/** @name FPU operations taking a 32-bit float argument
3215	* @{ */
3216	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3217	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
3218	typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
3219
3220	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3221	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
3222	typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
3223
3224	FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
3225	FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
3226	FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
3227	FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
3228	FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
3229	FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
3230	FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
3231
3232	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
3233	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3234	PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
3235	/** @} */
3236
3237	/** @name FPU operations taking a 64-bit float argument
3238	* @{ */
3239	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3240	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
3241	typedef FNIEMAIMPLFPUR64FSW *PFNIEMAIMPLFPUR64FSW;
3242
3243	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3244	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
3245	typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
3246
3247	FNIEMAIMPLFPUR64FSW iemAImpl_fcom_r80_by_r64;
3248	FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
3249	FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
3250	FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
3251	FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
3252	FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
3253	FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
3254
3255	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
3256	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3257	PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
3258	/** @} */
3259
3260	/** @name FPU operations taking a 80-bit float argument
3261	* @{ */
3262	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3263	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
3264	typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
3265	FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
3266	FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
3267	FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
3268	FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
3269	FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
3270	FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
3271	FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
3272	FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
3273	FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
3274
3275	FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80, iemAImpl_fpatan_r80_by_r80_amd, iemAImpl_fpatan_r80_by_r80_intel;
3276	FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80, iemAImpl_fyl2x_r80_by_r80_amd, iemAImpl_fyl2x_r80_by_r80_intel;
3277	FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80, iemAImpl_fyl2xp1_r80_by_r80_amd, iemAImpl_fyl2xp1_r80_by_r80_intel;
3278
3279	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3280	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
3281	typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
3282	FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
3283	FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
3284
3285	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
3286	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
3287	typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
3288	FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
3289	FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
3290
3291	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
3292	typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
3293	FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
3294	FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
3295	FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80, iemAImpl_f2xm1_r80_amd, iemAImpl_f2xm1_r80_intel;
3296	FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
3297	FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
3298	FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80, iemAImpl_fsin_r80_amd, iemAImpl_fsin_r80_intel;
3299	FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80, iemAImpl_fcos_r80_amd, iemAImpl_fcos_r80_intel;
3300
3301	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
3302	typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
3303	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
3304	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
3305
3306	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
3307	typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
3308	FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
3309	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
3310	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
3311	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
3312	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
3313	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
3314	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
3315
3316	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
3317	PCRTFLOAT80U pr80Val));
3318	typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
3319	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80, iemAImpl_fptan_r80_r80_amd, iemAImpl_fptan_r80_r80_intel;
3320	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
3321	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80, iemAImpl_fsincos_r80_r80_amd, iemAImpl_fsincos_r80_r80_intel;
3322
3323	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
3324	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3325	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
3326
3327	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_d80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTPBCD80U pd80Val));
3328	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_d80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3329	PRTPBCD80U pd80Dst, PCRTFLOAT80U pr80Src));
3330
3331	/** @} */
3332
3333	/** @name FPU operations taking a 16-bit signed integer argument
3334	* @{ */
3335	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3336	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
3337	typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
3338	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI16,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3339	int16_t *pi16Dst, PCRTFLOAT80U pr80Src));
3340	typedef FNIEMAIMPLFPUSTR80TOI16 *PFNIEMAIMPLFPUSTR80TOI16;
3341
3342	FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
3343	FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
3344	FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
3345	FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
3346	FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
3347	FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
3348
3349	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3350	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
3351	typedef FNIEMAIMPLFPUI16FSW *PFNIEMAIMPLFPUI16FSW;
3352	FNIEMAIMPLFPUI16FSW iemAImpl_ficom_r80_by_i16;
3353
3354	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
3355	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fist_r80_to_i16;
3356	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fistt_r80_to_i16, iemAImpl_fistt_r80_to_i16_amd, iemAImpl_fistt_r80_to_i16_intel;
3357	/** @} */
3358
3359	/** @name FPU operations taking a 32-bit signed integer argument
3360	* @{ */
3361	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3362	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
3363	typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
3364	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI32,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3365	int32_t *pi32Dst, PCRTFLOAT80U pr80Src));
3366	typedef FNIEMAIMPLFPUSTR80TOI32 *PFNIEMAIMPLFPUSTR80TOI32;
3367
3368	FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
3369	FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
3370	FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
3371	FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
3372	FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
3373	FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
3374
3375	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3376	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
3377	typedef FNIEMAIMPLFPUI32FSW *PFNIEMAIMPLFPUI32FSW;
3378	FNIEMAIMPLFPUI32FSW iemAImpl_ficom_r80_by_i32;
3379
3380	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
3381	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fist_r80_to_i32;
3382	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fistt_r80_to_i32;
3383	/** @} */
3384
3385	/** @name FPU operations taking a 64-bit signed integer argument
3386	* @{ */
3387	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI64,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3388	int64_t *pi64Dst, PCRTFLOAT80U pr80Src));
3389	typedef FNIEMAIMPLFPUSTR80TOI64 *PFNIEMAIMPLFPUSTR80TOI64;
3390
3391	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
3392	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fist_r80_to_i64;
3393	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fistt_r80_to_i64;
3394	/** @} */
3395
3396
3397	/** Temporary type representing a 256-bit vector register. */
3398	typedef struct { uint64_t au64[4]; } IEMVMM256;
3399	/** Temporary type pointing to a 256-bit vector register. */
3400	typedef IEMVMM256 *PIEMVMM256;
3401	/** Temporary type pointing to a const 256-bit vector register. */
3402	typedef IEMVMM256 *PCIEMVMM256;
3403
3404
3405	/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
3406	* @{ */
3407	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t puDst, uint64_t const puSrc));
3408	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
3409	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U128,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
3410	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
3411	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U128,(PX86XSAVEAREA pExtState, PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
3412	typedef FNIEMAIMPLMEDIAF3U128 *PFNIEMAIMPLMEDIAF3U128;
3413	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U256,(PX86XSAVEAREA pExtState, PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
3414	typedef FNIEMAIMPLMEDIAF3U256 *PFNIEMAIMPLMEDIAF3U256;
3415	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U64,(uint64_t puDst, uint64_t const puSrc));
3416	typedef FNIEMAIMPLMEDIAOPTF2U64 *PFNIEMAIMPLMEDIAOPTF2U64;
3417	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128,(PRTUINT128U puDst, PCRTUINT128U puSrc));
3418	typedef FNIEMAIMPLMEDIAOPTF2U128 *PFNIEMAIMPLMEDIAOPTF2U128;
3419	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
3420	typedef FNIEMAIMPLMEDIAOPTF3U128 *PFNIEMAIMPLMEDIAOPTF3U128;
3421	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
3422	typedef FNIEMAIMPLMEDIAOPTF3U256 *PFNIEMAIMPLMEDIAOPTF3U256;
3423	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256,(PRTUINT256U puDst, PCRTUINT256U puSrc));
3424	typedef FNIEMAIMPLMEDIAOPTF2U256 *PFNIEMAIMPLMEDIAOPTF2U256;
3425	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pshufb_u64, iemAImpl_pshufb_u64_fallback;
3426	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pand_u64, iemAImpl_pandn_u64, iemAImpl_por_u64, iemAImpl_pxor_u64;
3427	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
3428	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pcmpgtb_u64, iemAImpl_pcmpgtw_u64, iemAImpl_pcmpgtd_u64;
3429	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddb_u64, iemAImpl_paddsb_u64, iemAImpl_paddusb_u64;
3430	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddw_u64, iemAImpl_paddsw_u64, iemAImpl_paddusw_u64;
3431	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddd_u64;
3432	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddq_u64;
3433	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubb_u64, iemAImpl_psubsb_u64, iemAImpl_psubusb_u64;
3434	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubw_u64, iemAImpl_psubsw_u64, iemAImpl_psubusw_u64;
3435	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubd_u64;
3436	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubq_u64;
3437	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmaddwd_u64, iemAImpl_pmaddwd_u64_fallback;
3438	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmullw_u64, iemAImpl_pmulhw_u64;
3439	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pminub_u64, iemAImpl_pmaxub_u64;
3440	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pminsw_u64, iemAImpl_pmaxsw_u64;
3441	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pabsb_u64, iemAImpl_pabsb_u64_fallback;
3442	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pabsw_u64, iemAImpl_pabsw_u64_fallback;
3443	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pabsd_u64, iemAImpl_pabsd_u64_fallback;
3444	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psignb_u64, iemAImpl_psignb_u64_fallback;
3445	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psignw_u64, iemAImpl_psignw_u64_fallback;
3446	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psignd_u64, iemAImpl_psignd_u64_fallback;
3447	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phaddw_u64, iemAImpl_phaddw_u64_fallback;
3448	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phaddd_u64, iemAImpl_phaddd_u64_fallback;
3449	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phsubw_u64, iemAImpl_phsubw_u64_fallback;
3450	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phsubd_u64, iemAImpl_phsubd_u64_fallback;
3451	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phaddsw_u64, iemAImpl_phaddsw_u64_fallback;
3452	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phsubsw_u64, iemAImpl_phsubsw_u64_fallback;
3453	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmaddubsw_u64, iemAImpl_pmaddubsw_u64_fallback;
3454	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhrsw_u64, iemAImpl_pmulhrsw_u64_fallback;
3455	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmuludq_u64;
3456	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllw_u64, iemAImpl_psrlw_u64, iemAImpl_psraw_u64;
3457	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pslld_u64, iemAImpl_psrld_u64, iemAImpl_psrad_u64;
3458	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllq_u64, iemAImpl_psrlq_u64;
3459	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packsswb_u64, iemAImpl_packuswb_u64;
3460	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packssdw_u64;
3461	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhuw_u64;
3462	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pavgb_u64, iemAImpl_pavgw_u64;
3463	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psadbw_u64;
3464
3465	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pshufb_u128, iemAImpl_pshufb_u128_fallback;
3466	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pand_u128, iemAImpl_pandn_u128, iemAImpl_por_u128, iemAImpl_pxor_u128;
3467	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
3468	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpeqq_u128, iemAImpl_pcmpeqq_u128_fallback;
3469	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpgtb_u128, iemAImpl_pcmpgtw_u128, iemAImpl_pcmpgtd_u128;
3470	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpgtq_u128, iemAImpl_pcmpgtq_u128_fallback;
3471	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddb_u128, iemAImpl_paddsb_u128, iemAImpl_paddusb_u128;
3472	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddw_u128, iemAImpl_paddsw_u128, iemAImpl_paddusw_u128;
3473	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddd_u128;
3474	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddq_u128;
3475	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubb_u128, iemAImpl_psubsb_u128, iemAImpl_psubusb_u128;
3476	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubw_u128, iemAImpl_psubsw_u128, iemAImpl_psubusw_u128;
3477	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubd_u128;
3478	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubq_u128;
3479	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmullw_u128, iemAImpl_pmullw_u128_fallback;
3480	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhw_u128;
3481	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulld_u128, iemAImpl_pmulld_u128_fallback;
3482	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaddwd_u128, iemAImpl_pmaddwd_u128_fallback;
3483	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminub_u128;
3484	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminud_u128, iemAImpl_pminud_u128_fallback;
3485	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminuw_u128, iemAImpl_pminuw_u128_fallback;
3486	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminsb_u128, iemAImpl_pminsb_u128_fallback;
3487	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminsd_u128, iemAImpl_pminsd_u128_fallback;
3488	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminsw_u128, iemAImpl_pminsw_u128_fallback;
3489	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxub_u128;
3490	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxud_u128, iemAImpl_pmaxud_u128_fallback;
3491	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxuw_u128, iemAImpl_pmaxuw_u128_fallback;
3492	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxsb_u128, iemAImpl_pmaxsb_u128_fallback;
3493	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxsw_u128;
3494	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxsd_u128, iemAImpl_pmaxsd_u128_fallback;
3495	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pabsb_u128, iemAImpl_pabsb_u128_fallback;
3496	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pabsw_u128, iemAImpl_pabsw_u128_fallback;
3497	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pabsd_u128, iemAImpl_pabsd_u128_fallback;
3498	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psignb_u128, iemAImpl_psignb_u128_fallback;
3499	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psignw_u128, iemAImpl_psignw_u128_fallback;
3500	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psignd_u128, iemAImpl_psignd_u128_fallback;
3501	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phaddw_u128, iemAImpl_phaddw_u128_fallback;
3502	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phaddd_u128, iemAImpl_phaddd_u128_fallback;
3503	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phsubw_u128, iemAImpl_phsubw_u128_fallback;
3504	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phsubd_u128, iemAImpl_phsubd_u128_fallback;
3505	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phaddsw_u128, iemAImpl_phaddsw_u128_fallback;
3506	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phsubsw_u128, iemAImpl_phsubsw_u128_fallback;
3507	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaddubsw_u128, iemAImpl_pmaddubsw_u128_fallback;
3508	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhrsw_u128, iemAImpl_pmulhrsw_u128_fallback;
3509	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuludq_u128;
3510	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaddwd_u128, iemAImpl_pmaddwd_u128_fallback;
3511	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packsswb_u128, iemAImpl_packuswb_u128;
3512	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packssdw_u128, iemAImpl_packusdw_u128;
3513	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllw_u128, iemAImpl_psrlw_u128, iemAImpl_psraw_u128;
3514	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pslld_u128, iemAImpl_psrld_u128, iemAImpl_psrad_u128;
3515	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllq_u128, iemAImpl_psrlq_u128;
3516	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhuw_u128;
3517	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pavgb_u128, iemAImpl_pavgw_u128;
3518	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psadbw_u128;
3519	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuldq_u128, iemAImpl_pmuldq_u128_fallback;
3520	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpcklps_u128, iemAImpl_unpcklpd_u128;
3521	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpckhps_u128, iemAImpl_unpckhpd_u128;
3522	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phminposuw_u128, iemAImpl_phminposuw_u128_fallback;
3523
3524	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpshufb_u128, iemAImpl_vpshufb_u128_fallback;
3525	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpand_u128, iemAImpl_vpand_u128_fallback;
3526	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpandn_u128, iemAImpl_vpandn_u128_fallback;
3527	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpor_u128, iemAImpl_vpor_u128_fallback;
3528	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpxor_u128, iemAImpl_vpxor_u128_fallback;
3529	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqb_u128, iemAImpl_vpcmpeqb_u128_fallback;
3530	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqw_u128, iemAImpl_vpcmpeqw_u128_fallback;
3531	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqd_u128, iemAImpl_vpcmpeqd_u128_fallback;
3532	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqq_u128, iemAImpl_vpcmpeqq_u128_fallback;
3533	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtb_u128, iemAImpl_vpcmpgtb_u128_fallback;
3534	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtw_u128, iemAImpl_vpcmpgtw_u128_fallback;
3535	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtd_u128, iemAImpl_vpcmpgtd_u128_fallback;
3536	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtq_u128, iemAImpl_vpcmpgtq_u128_fallback;
3537	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddb_u128, iemAImpl_vpaddb_u128_fallback;
3538	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddw_u128, iemAImpl_vpaddw_u128_fallback;
3539	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddd_u128, iemAImpl_vpaddd_u128_fallback;
3540	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddq_u128, iemAImpl_vpaddq_u128_fallback;
3541	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubb_u128, iemAImpl_vpsubb_u128_fallback;
3542	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubw_u128, iemAImpl_vpsubw_u128_fallback;
3543	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubd_u128, iemAImpl_vpsubd_u128_fallback;
3544	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubq_u128, iemAImpl_vpsubq_u128_fallback;
3545	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminub_u128, iemAImpl_vpminub_u128_fallback;
3546	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminuw_u128, iemAImpl_vpminuw_u128_fallback;
3547	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminud_u128, iemAImpl_vpminud_u128_fallback;
3548	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminsb_u128, iemAImpl_vpminsb_u128_fallback;
3549	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminsw_u128, iemAImpl_vpminsw_u128_fallback;
3550	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminsd_u128, iemAImpl_vpminsd_u128_fallback;
3551	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxub_u128, iemAImpl_vpmaxub_u128_fallback;
3552	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxuw_u128, iemAImpl_vpmaxuw_u128_fallback;
3553	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxud_u128, iemAImpl_vpmaxud_u128_fallback;
3554	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxsb_u128, iemAImpl_vpmaxsb_u128_fallback;
3555	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxsw_u128, iemAImpl_vpmaxsw_u128_fallback;
3556	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxsd_u128, iemAImpl_vpmaxsd_u128_fallback;
3557	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpacksswb_u128, iemAImpl_vpacksswb_u128_fallback;
3558	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackssdw_u128, iemAImpl_vpackssdw_u128_fallback;
3559	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackuswb_u128, iemAImpl_vpackuswb_u128_fallback;
3560	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackusdw_u128, iemAImpl_vpackusdw_u128_fallback;
3561	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmullw_u128, iemAImpl_vpmullw_u128_fallback;
3562	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulld_u128, iemAImpl_vpmulld_u128_fallback;
3563	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhw_u128, iemAImpl_vpmulhw_u128_fallback;
3564	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhuw_u128, iemAImpl_vpmulhuw_u128_fallback;
3565	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgb_u128, iemAImpl_vpavgb_u128_fallback;
3566	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgw_u128, iemAImpl_vpavgw_u128_fallback;
3567	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignb_u128, iemAImpl_vpsignb_u128_fallback;
3568	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignw_u128, iemAImpl_vpsignw_u128_fallback;
3569	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignd_u128, iemAImpl_vpsignd_u128_fallback;
3570	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddw_u128, iemAImpl_vphaddw_u128_fallback;
3571	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddd_u128, iemAImpl_vphaddd_u128_fallback;
3572	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubw_u128, iemAImpl_vphsubw_u128_fallback;
3573	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubd_u128, iemAImpl_vphsubd_u128_fallback;
3574	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddsw_u128, iemAImpl_vphaddsw_u128_fallback;
3575	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubsw_u128, iemAImpl_vphsubsw_u128_fallback;
3576	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddubsw_u128, iemAImpl_vpmaddubsw_u128_fallback;
3577	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhrsw_u128, iemAImpl_vpmulhrsw_u128_fallback;
3578	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsadbw_u128, iemAImpl_vpsadbw_u128_fallback;
3579	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuldq_u128, iemAImpl_vpmuldq_u128_fallback;
3580	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuludq_u128, iemAImpl_vpmuludq_u128_fallback;
3581	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsb_u128, iemAImpl_vpsubsb_u128_fallback;
3582	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsw_u128, iemAImpl_vpsubsw_u128_fallback;
3583	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusb_u128, iemAImpl_vpsubusb_u128_fallback;
3584	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusw_u128, iemAImpl_vpsubusw_u128_fallback;
3585	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusb_u128, iemAImpl_vpaddusb_u128_fallback;
3586	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusw_u128, iemAImpl_vpaddusw_u128_fallback;
3587	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsb_u128, iemAImpl_vpaddsb_u128_fallback;
3588	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsw_u128, iemAImpl_vpaddsw_u128_fallback;
3589	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllw_u128, iemAImpl_vpsllw_u128_fallback;
3590	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpslld_u128, iemAImpl_vpslld_u128_fallback;
3591	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllq_u128, iemAImpl_vpsllq_u128_fallback;
3592	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsraw_u128, iemAImpl_vpsraw_u128_fallback;
3593	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrad_u128, iemAImpl_vpsrad_u128_fallback;
3594	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlw_u128, iemAImpl_vpsrlw_u128_fallback;
3595	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrld_u128, iemAImpl_vpsrld_u128_fallback;
3596	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlq_u128, iemAImpl_vpsrlq_u128_fallback;
3597	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddwd_u128, iemAImpl_vpmaddwd_u128_fallback;
3598
3599	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsb_u128, iemAImpl_vpabsb_u128_fallback;
3600	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsw_u128, iemAImpl_vpabsd_u128_fallback;
3601	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsd_u128, iemAImpl_vpabsw_u128_fallback;
3602	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vphminposuw_u128, iemAImpl_vphminposuw_u128_fallback;
3603
3604	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpshufb_u256, iemAImpl_vpshufb_u256_fallback;
3605	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpand_u256, iemAImpl_vpand_u256_fallback;
3606	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpandn_u256, iemAImpl_vpandn_u256_fallback;
3607	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpor_u256, iemAImpl_vpor_u256_fallback;
3608	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpxor_u256, iemAImpl_vpxor_u256_fallback;
3609	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqb_u256, iemAImpl_vpcmpeqb_u256_fallback;
3610	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqw_u256, iemAImpl_vpcmpeqw_u256_fallback;
3611	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqd_u256, iemAImpl_vpcmpeqd_u256_fallback;
3612	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqq_u256, iemAImpl_vpcmpeqq_u256_fallback;
3613	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtb_u256, iemAImpl_vpcmpgtb_u256_fallback;
3614	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtw_u256, iemAImpl_vpcmpgtw_u256_fallback;
3615	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtd_u256, iemAImpl_vpcmpgtd_u256_fallback;
3616	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtq_u256, iemAImpl_vpcmpgtq_u256_fallback;
3617	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddb_u256, iemAImpl_vpaddb_u256_fallback;
3618	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddw_u256, iemAImpl_vpaddw_u256_fallback;
3619	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddd_u256, iemAImpl_vpaddd_u256_fallback;
3620	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddq_u256, iemAImpl_vpaddq_u256_fallback;
3621	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubb_u256, iemAImpl_vpsubb_u256_fallback;
3622	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubw_u256, iemAImpl_vpsubw_u256_fallback;
3623	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubd_u256, iemAImpl_vpsubd_u256_fallback;
3624	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubq_u256, iemAImpl_vpsubq_u256_fallback;
3625	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminub_u256, iemAImpl_vpminub_u256_fallback;
3626	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminuw_u256, iemAImpl_vpminuw_u256_fallback;
3627	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminud_u256, iemAImpl_vpminud_u256_fallback;
3628	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminsb_u256, iemAImpl_vpminsb_u256_fallback;
3629	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminsw_u256, iemAImpl_vpminsw_u256_fallback;
3630	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminsd_u256, iemAImpl_vpminsd_u256_fallback;
3631	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxub_u256, iemAImpl_vpmaxub_u256_fallback;
3632	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxuw_u256, iemAImpl_vpmaxuw_u256_fallback;
3633	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxud_u256, iemAImpl_vpmaxud_u256_fallback;
3634	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxsb_u256, iemAImpl_vpmaxsb_u256_fallback;
3635	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxsw_u256, iemAImpl_vpmaxsw_u256_fallback;
3636	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxsd_u256, iemAImpl_vpmaxsd_u256_fallback;
3637	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpacksswb_u256, iemAImpl_vpacksswb_u256_fallback;
3638	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackssdw_u256, iemAImpl_vpackssdw_u256_fallback;
3639	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackuswb_u256, iemAImpl_vpackuswb_u256_fallback;
3640	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackusdw_u256, iemAImpl_vpackusdw_u256_fallback;
3641	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmullw_u256, iemAImpl_vpmullw_u256_fallback;
3642	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulld_u256, iemAImpl_vpmulld_u256_fallback;
3643	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhw_u256, iemAImpl_vpmulhw_u256_fallback;
3644	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhuw_u256, iemAImpl_vpmulhuw_u256_fallback;
3645	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgb_u256, iemAImpl_vpavgb_u256_fallback;
3646	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgw_u256, iemAImpl_vpavgw_u256_fallback;
3647	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignb_u256, iemAImpl_vpsignb_u256_fallback;
3648	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignw_u256, iemAImpl_vpsignw_u256_fallback;
3649	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignd_u256, iemAImpl_vpsignd_u256_fallback;
3650	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddw_u256, iemAImpl_vphaddw_u256_fallback;
3651	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddd_u256, iemAImpl_vphaddd_u256_fallback;
3652	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubw_u256, iemAImpl_vphsubw_u256_fallback;
3653	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubd_u256, iemAImpl_vphsubd_u256_fallback;
3654	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddsw_u256, iemAImpl_vphaddsw_u256_fallback;
3655	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubsw_u256, iemAImpl_vphsubsw_u256_fallback;
3656	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddubsw_u256, iemAImpl_vpmaddubsw_u256_fallback;
3657	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhrsw_u256, iemAImpl_vpmulhrsw_u256_fallback;
3658	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsadbw_u256, iemAImpl_vpsadbw_u256_fallback;
3659	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuldq_u256, iemAImpl_vpmuldq_u256_fallback;
3660	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuludq_u256, iemAImpl_vpmuludq_u256_fallback;
3661	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsb_u256, iemAImpl_vpsubsb_u256_fallback;
3662	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsw_u256, iemAImpl_vpsubsw_u256_fallback;
3663	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusb_u256, iemAImpl_vpsubusb_u256_fallback;
3664	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusw_u256, iemAImpl_vpsubusw_u256_fallback;
3665	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusb_u256, iemAImpl_vpaddusb_u256_fallback;
3666	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusw_u256, iemAImpl_vpaddusw_u256_fallback;
3667	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsb_u256, iemAImpl_vpaddsb_u256_fallback;
3668	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsw_u256, iemAImpl_vpaddsw_u256_fallback;
3669	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllw_u256, iemAImpl_vpsllw_u256_fallback;
3670	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpslld_u256, iemAImpl_vpslld_u256_fallback;
3671	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllq_u256, iemAImpl_vpsllq_u256_fallback;
3672	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsraw_u256, iemAImpl_vpsraw_u256_fallback;
3673	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrad_u256, iemAImpl_vpsrad_u256_fallback;
3674	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlw_u256, iemAImpl_vpsrlw_u256_fallback;
3675	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrld_u256, iemAImpl_vpsrld_u256_fallback;
3676	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlq_u256, iemAImpl_vpsrlq_u256_fallback;
3677	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddwd_u256, iemAImpl_vpmaddwd_u256_fallback;
3678
3679	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsb_u256, iemAImpl_vpabsb_u256_fallback;
3680	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsw_u256, iemAImpl_vpabsw_u256_fallback;
3681	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsd_u256, iemAImpl_vpabsd_u256_fallback;
3682	/** @} */
3683
3684	/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
3685	* @{ */
3686	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
3687	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
3688	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpcklbw_u128, iemAImpl_vpunpcklbw_u128_fallback,
3689	iemAImpl_vpunpcklwd_u128, iemAImpl_vpunpcklwd_u128_fallback,
3690	iemAImpl_vpunpckldq_u128, iemAImpl_vpunpckldq_u128_fallback,
3691	iemAImpl_vpunpcklqdq_u128, iemAImpl_vpunpcklqdq_u128_fallback,
3692	iemAImpl_vunpcklps_u128, iemAImpl_vunpcklps_u128_fallback,
3693	iemAImpl_vunpcklpd_u128, iemAImpl_vunpcklpd_u128_fallback,
3694	iemAImpl_vunpckhps_u128, iemAImpl_vunpckhps_u128_fallback,
3695	iemAImpl_vunpckhpd_u128, iemAImpl_vunpckhpd_u128_fallback;
3696
3697	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpcklbw_u256, iemAImpl_vpunpcklbw_u256_fallback,
3698	iemAImpl_vpunpcklwd_u256, iemAImpl_vpunpcklwd_u256_fallback,
3699	iemAImpl_vpunpckldq_u256, iemAImpl_vpunpckldq_u256_fallback,
3700	iemAImpl_vpunpcklqdq_u256, iemAImpl_vpunpcklqdq_u256_fallback,
3701	iemAImpl_vunpcklps_u256, iemAImpl_vunpcklps_u256_fallback,
3702	iemAImpl_vunpcklpd_u256, iemAImpl_vunpcklpd_u256_fallback,
3703	iemAImpl_vunpckhps_u256, iemAImpl_vunpckhps_u256_fallback,
3704	iemAImpl_vunpckhpd_u256, iemAImpl_vunpckhpd_u256_fallback;
3705	/** @} */
3706
3707	/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
3708	* @{ */
3709	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
3710	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
3711	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpckhbw_u128, iemAImpl_vpunpckhbw_u128_fallback,
3712	iemAImpl_vpunpckhwd_u128, iemAImpl_vpunpckhwd_u128_fallback,
3713	iemAImpl_vpunpckhdq_u128, iemAImpl_vpunpckhdq_u128_fallback,
3714	iemAImpl_vpunpckhqdq_u128, iemAImpl_vpunpckhqdq_u128_fallback;
3715	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpckhbw_u256, iemAImpl_vpunpckhbw_u256_fallback,
3716	iemAImpl_vpunpckhwd_u256, iemAImpl_vpunpckhwd_u256_fallback,
3717	iemAImpl_vpunpckhdq_u256, iemAImpl_vpunpckhdq_u256_fallback,
3718	iemAImpl_vpunpckhqdq_u256, iemAImpl_vpunpckhqdq_u256_fallback;
3719	/** @} */
3720
3721	/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
3722	* @{ */
3723	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3724	typedef FNIEMAIMPLMEDIAPSHUFU128 *PFNIEMAIMPLMEDIAPSHUFU128;
3725	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
3726	typedef FNIEMAIMPLMEDIAPSHUFU256 *PFNIEMAIMPLMEDIAPSHUFU256;
3727	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw_u64,(uint64_t puDst, uint64_t const puSrc, uint8_t bEvil));
3728	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_pshufhw_u128, iemAImpl_pshuflw_u128, iemAImpl_pshufd_u128;
3729	#ifndef IEM_WITHOUT_ASSEMBLY
3730	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256, iemAImpl_vpshuflw_u256, iemAImpl_vpshufd_u256;
3731	#endif
3732	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256_fallback, iemAImpl_vpshuflw_u256_fallback, iemAImpl_vpshufd_u256_fallback;
3733	/** @} */
3734
3735	/** @name Media (SSE/MMX/AVX) operation: Shift Immediate Stuff (evil)
3736	* @{ */
3737	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU64,(uint64_t *puDst, uint8_t bShift));
3738	typedef FNIEMAIMPLMEDIAPSHIFTU64 *PFNIEMAIMPLMEDIAPSHIFTU64;
3739	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU128,(PRTUINT128U puDst, uint8_t bShift));
3740	typedef FNIEMAIMPLMEDIAPSHIFTU128 *PFNIEMAIMPLMEDIAPSHIFTU128;
3741	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU256,(PRTUINT256U puDst, uint8_t bShift));
3742	typedef FNIEMAIMPLMEDIAPSHIFTU256 *PFNIEMAIMPLMEDIAPSHIFTU256;
3743	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psllw_imm_u64, iemAImpl_pslld_imm_u64, iemAImpl_psllq_imm_u64;
3744	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psrlw_imm_u64, iemAImpl_psrld_imm_u64, iemAImpl_psrlq_imm_u64;
3745	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psraw_imm_u64, iemAImpl_psrad_imm_u64;
3746	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psllw_imm_u128, iemAImpl_pslld_imm_u128, iemAImpl_psllq_imm_u128;
3747	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psrlw_imm_u128, iemAImpl_psrld_imm_u128, iemAImpl_psrlq_imm_u128;
3748	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psraw_imm_u128, iemAImpl_psrad_imm_u128;
3749	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_pslldq_imm_u128, iemAImpl_psrldq_imm_u128;
3750	/** @} */
3751
3752	/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
3753	* @{ */
3754	IEM_DECL_IMPL_DEF(void, iemAImpl_maskmovq_u64,(uint64_t puMem, uint64_t const puSrc, uint64_t const *puMsk));
3755	IEM_DECL_IMPL_DEF(void, iemAImpl_maskmovdqu_u128,(PRTUINT128U puMem, PCRTUINT128U puSrc, PCRTUINT128U puMsk));
3756	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(uint64_t pu64Dst, uint64_t const puSrc));
3757	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(uint64_t *pu64Dst, PCRTUINT128U puSrc));
3758	#ifndef IEM_WITHOUT_ASSEMBLY
3759	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
3760	#endif
3761	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256_fallback,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
3762	/** @} */
3763
3764	/** @name Media (SSE/MMX/AVX) operations: Variable Blend Packed Bytes/R32/R64.
3765	* @{ */
3766	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puMask));
3767	typedef FNIEMAIMPLBLENDU128 *PFNIEMAIMPLBLENDU128;
3768	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, PCRTUINT128U puMask));
3769	typedef FNIEMAIMPLAVXBLENDU128 *PFNIEMAIMPLAVXBLENDU128;
3770	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, PCRTUINT256U puMask));
3771	typedef FNIEMAIMPLAVXBLENDU256 *PFNIEMAIMPLAVXBLENDU256;
3772
3773	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128;
3774	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128_fallback;
3775	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128;
3776	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128_fallback;
3777	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256;
3778	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256_fallback;
3779
3780	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128;
3781	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128_fallback;
3782	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128;
3783	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128_fallback;
3784	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256;
3785	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256_fallback;
3786
3787	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128;
3788	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128_fallback;
3789	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128;
3790	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128_fallback;
3791	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256;
3792	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256_fallback;
3793	/** @} */
3794
3795
3796	/** @name Media (SSE/MMX/AVX) operation: Sort this later
3797	* @{ */
3798	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3799	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3800	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3801	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3802	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3803
3804	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3805	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3806	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3807	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3808	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3809
3810	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3811	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3812	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
3813	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3814	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3815
3816	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3817	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3818	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3819	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3820	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3821
3822	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3823	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3824	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3825	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3826	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3827
3828	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3829	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3830	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3831	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3832	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3833
3834	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3835	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3836	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3837	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3838	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3839
3840	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3841	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3842	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3843	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3844	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3845
3846	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3847	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3848	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
3849	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3850	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3851
3852	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3853	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3854	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3855	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3856	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3857
3858	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3859	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3860	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3861	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3862	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3863
3864	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3865	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3866	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3867	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3868	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3869
3870	IEM_DECL_IMPL_DEF(void, iemAImpl_shufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3871	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3872	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3873	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3874	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3875
3876	IEM_DECL_IMPL_DEF(void, iemAImpl_shufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3877	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3878	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3879	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3880	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3881
3882	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
3883	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64_fallback,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
3884
3885	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3886	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3887	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3888	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3889	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3890
3891	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3892	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3893	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3894	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3895	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3896
3897
3898	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3899	typedef FNIEMAIMPLMEDIAOPTF2U128IMM8 *PFNIEMAIMPLMEDIAOPTF2U128IMM8;
3900	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
3901	typedef FNIEMAIMPLMEDIAOPTF2U256IMM8 *PFNIEMAIMPLMEDIAOPTF2U256IMM8;
3902	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3903	typedef FNIEMAIMPLMEDIAOPTF3U128IMM8 *PFNIEMAIMPLMEDIAOPTF3U128IMM8;
3904	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3905	typedef FNIEMAIMPLMEDIAOPTF3U256IMM8 *PFNIEMAIMPLMEDIAOPTF3U256IMM8;
3906
3907	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_palignr_u128, iemAImpl_palignr_u128_fallback;
3908	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pblendw_u128, iemAImpl_pblendw_u128_fallback;
3909	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendps_u128, iemAImpl_blendps_u128_fallback;
3910	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendpd_u128, iemAImpl_blendpd_u128_fallback;
3911
3912	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpalignr_u128, iemAImpl_vpalignr_u128_fallback;
3913	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendw_u128, iemAImpl_vpblendw_u128_fallback;
3914	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendd_u128, iemAImpl_vpblendd_u128_fallback;
3915	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendps_u128, iemAImpl_vblendps_u128_fallback;
3916	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendpd_u128, iemAImpl_vblendpd_u128_fallback;
3917
3918	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpalignr_u256, iemAImpl_vpalignr_u256_fallback;
3919	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendw_u256, iemAImpl_vpblendw_u256_fallback;
3920	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendd_u256, iemAImpl_vpblendd_u256_fallback;
3921	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendps_u256, iemAImpl_vblendps_u256_fallback;
3922	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendpd_u256, iemAImpl_vblendpd_u256_fallback;
3923	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2i128_u256, iemAImpl_vperm2i128_u256_fallback;
3924	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2f128_u256, iemAImpl_vperm2f128_u256_fallback;
3925
3926	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesimc_u128, iemAImpl_aesimc_u128_fallback;
3927	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenc_u128, iemAImpl_aesenc_u128_fallback;
3928	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenclast_u128, iemAImpl_aesenclast_u128_fallback;
3929	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdec_u128, iemAImpl_aesdec_u128_fallback;
3930	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdeclast_u128, iemAImpl_aesdeclast_u128_fallback;
3931
3932	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesimc_u128, iemAImpl_vaesimc_u128_fallback;
3933	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenc_u128, iemAImpl_vaesenc_u128_fallback;
3934	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenclast_u128, iemAImpl_vaesenclast_u128_fallback;
3935	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdec_u128, iemAImpl_vaesdec_u128_fallback;
3936	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdeclast_u128, iemAImpl_vaesdeclast_u128_fallback;
3937
3938	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_aeskeygenassist_u128, iemAImpl_aeskeygenassist_u128_fallback;
3939
3940	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vaeskeygenassist_u128, iemAImpl_vaeskeygenassist_u128_fallback;
3941
3942	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1nexte_u128, iemAImpl_sha1nexte_u128_fallback;
3943	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg1_u128, iemAImpl_sha1msg1_u128_fallback;
3944	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg2_u128, iemAImpl_sha1msg2_u128_fallback;
3945	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg1_u128, iemAImpl_sha256msg1_u128_fallback;
3946	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg2_u128, iemAImpl_sha256msg2_u128_fallback;
3947	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_sha1rnds4_u128, iemAImpl_sha1rnds4_u128_fallback;
3948	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
3949	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
3950
3951	typedef struct IEMPCMPISTRXSRC
3952	{
3953	RTUINT128U uSrc1;
3954	RTUINT128U uSrc2;
3955	} IEMPCMPISTRXSRC;
3956	typedef IEMPCMPISTRXSRC *PIEMPCMPISTRXSRC;
3957	typedef const IEMPCMPISTRXSRC *PCIEMPCMPISTRXSRC;
3958
3959	typedef struct IEMPCMPESTRXSRC
3960	{
3961	RTUINT128U uSrc1;
3962	RTUINT128U uSrc2;
3963	uint64_t u64Rax;
3964	uint64_t u64Rdx;
3965	} IEMPCMPESTRXSRC;
3966	typedef IEMPCMPESTRXSRC *PIEMPCMPESTRXSRC;
3967	typedef const IEMPCMPESTRXSRC *PCIEMPCMPESTRXSRC;
3968
3969	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLPCMPISTRIU128IMM8,(uint32_t *pEFlags, PCRTUINT128U pSrc1, PCRTUINT128U pSrc2, uint8_t bEvil));
3970	typedef FNIEMAIMPLPCMPISTRIU128IMM8 *PFNIEMAIMPLPCMPISTRIU128IMM8;
3971	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRIU128IMM8,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
3972	typedef FNIEMAIMPLPCMPESTRIU128IMM8 *PFNIEMAIMPLPCMPESTRIU128IMM8;
3973
3974	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPISTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
3975	typedef FNIEMAIMPLPCMPISTRMU128IMM8 *PFNIEMAIMPLPCMPISTRMU128IMM8;
3976	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
3977	typedef FNIEMAIMPLPCMPESTRMU128IMM8 *PFNIEMAIMPLPCMPESTRMU128IMM8;
3978
3979	FNIEMAIMPLPCMPISTRIU128IMM8 iemAImpl_pcmpistri_u128, iemAImpl_pcmpistri_u128_fallback;
3980	FNIEMAIMPLPCMPESTRIU128IMM8 iemAImpl_pcmpestri_u128, iemAImpl_pcmpestri_u128_fallback;
3981	FNIEMAIMPLPCMPISTRMU128IMM8 iemAImpl_pcmpistrm_u128, iemAImpl_pcmpistrm_u128_fallback;
3982	FNIEMAIMPLPCMPESTRMU128IMM8 iemAImpl_pcmpestrm_u128, iemAImpl_pcmpestrm_u128_fallback;
3983
3984	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pclmulqdq_u128, iemAImpl_pclmulqdq_u128_fallback;
3985	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpclmulqdq_u128, iemAImpl_vpclmulqdq_u128_fallback;
3986
3987	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_mpsadbw_u128, iemAImpl_mpsadbw_u128_fallback;
3988	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vmpsadbw_u128, iemAImpl_vmpsadbw_u128_fallback;
3989	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vmpsadbw_u256, iemAImpl_vmpsadbw_u256_fallback;
3990
3991	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsllw_imm_u128, iemAImpl_vpsllw_imm_u128_fallback;
3992	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsllw_imm_u256, iemAImpl_vpsllw_imm_u256_fallback;
3993	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpslld_imm_u128, iemAImpl_vpslld_imm_u128_fallback;
3994	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpslld_imm_u256, iemAImpl_vpslld_imm_u256_fallback;
3995	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsllq_imm_u128, iemAImpl_vpsllq_imm_u128_fallback;
3996	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsllq_imm_u256, iemAImpl_vpsllq_imm_u256_fallback;
3997	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
3998	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
3999	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
4000	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
4001
4002	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsraw_imm_u128, iemAImpl_vpsraw_imm_u128_fallback;
4003	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsraw_imm_u256, iemAImpl_vpsraw_imm_u256_fallback;
4004	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrad_imm_u128, iemAImpl_vpsrad_imm_u128_fallback;
4005	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrad_imm_u256, iemAImpl_vpsrad_imm_u256_fallback;
4006
4007	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrlw_imm_u128, iemAImpl_vpsrlw_imm_u128_fallback;
4008	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrlw_imm_u256, iemAImpl_vpsrlw_imm_u256_fallback;
4009	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrld_imm_u128, iemAImpl_vpsrld_imm_u128_fallback;
4010	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrld_imm_u256, iemAImpl_vpsrld_imm_u256_fallback;
4011	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrlq_imm_u128, iemAImpl_vpsrlq_imm_u128_fallback;
4012	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrlq_imm_u256, iemAImpl_vpsrlq_imm_u256_fallback;
4013	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
4014	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
4015	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
4016	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
4017
4018	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpermilps_u128, iemAImpl_vpermilps_u128_fallback;
4019	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_vpermilps_imm_u128, iemAImpl_vpermilps_imm_u128_fallback;
4020	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpermilps_u256, iemAImpl_vpermilps_u256_fallback;
4021	FNIEMAIMPLMEDIAOPTF2U256IMM8 iemAImpl_vpermilps_imm_u256, iemAImpl_vpermilps_imm_u256_fallback;
4022
4023	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpermilpd_u128, iemAImpl_vpermilpd_u128_fallback;
4024	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_vpermilpd_imm_u128, iemAImpl_vpermilpd_imm_u128_fallback;
4025	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpermilpd_u256, iemAImpl_vpermilpd_u256_fallback;
4026	FNIEMAIMPLMEDIAOPTF2U256IMM8 iemAImpl_vpermilpd_imm_u256, iemAImpl_vpermilpd_imm_u256_fallback;
4027
4028	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllvd_u128, iemAImpl_vpsllvd_u128_fallback;
4029	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllvd_u256, iemAImpl_vpsllvd_u256_fallback;
4030	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllvq_u128, iemAImpl_vpsllvq_u128_fallback;
4031	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllvq_u256, iemAImpl_vpsllvq_u256_fallback;
4032	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsravd_u128, iemAImpl_vpsravd_u128_fallback;
4033	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsravd_u256, iemAImpl_vpsravd_u256_fallback;
4034	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlvd_u128, iemAImpl_vpsrlvd_u128_fallback;
4035	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlvd_u256, iemAImpl_vpsrlvd_u256_fallback;
4036	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlvq_u128, iemAImpl_vpsrlvq_u128_fallback;
4037	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlvq_u256, iemAImpl_vpsrlvq_u256_fallback;
4038	/** @} */
4039
4040	/** @name Media Odds and Ends
4041	* @{ */
4042	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U8,(uint32_t *puDst, uint8_t uSrc));
4043	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U16,(uint32_t *puDst, uint16_t uSrc));
4044	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U32,(uint32_t *puDst, uint32_t uSrc));
4045	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U64,(uint32_t *puDst, uint64_t uSrc));
4046	FNIEMAIMPLCR32U8 iemAImpl_crc32_u8, iemAImpl_crc32_u8_fallback;
4047	FNIEMAIMPLCR32U16 iemAImpl_crc32_u16, iemAImpl_crc32_u16_fallback;
4048	FNIEMAIMPLCR32U32 iemAImpl_crc32_u32, iemAImpl_crc32_u32_fallback;
4049	FNIEMAIMPLCR32U64 iemAImpl_crc32_u64, iemAImpl_crc32_u64_fallback;
4050
4051	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL128,(PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint32_t *pEFlags));
4052	typedef FNIEMAIMPLF2EFL128 *PFNIEMAIMPLF2EFL128;
4053	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL256,(PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint32_t *pEFlags));
4054	typedef FNIEMAIMPLF2EFL256 *PFNIEMAIMPLF2EFL256;
4055	FNIEMAIMPLF2EFL128 iemAImpl_ptest_u128;
4056	FNIEMAIMPLF2EFL256 iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback;
4057	FNIEMAIMPLF2EFL128 iemAImpl_vtestps_u128, iemAImpl_vtestps_u128_fallback;
4058	FNIEMAIMPLF2EFL256 iemAImpl_vtestps_u256, iemAImpl_vtestps_u256_fallback;
4059	FNIEMAIMPLF2EFL128 iemAImpl_vtestpd_u128, iemAImpl_vtestpd_u128_fallback;
4060	FNIEMAIMPLF2EFL256 iemAImpl_vtestpd_u256, iemAImpl_vtestpd_u256_fallback;
4061
4062	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I32U64,(uint32_t uMxCsrIn, int32_t pi32Dst, const uint64_t pu64Src)); /* pu64Src is a double precision floating point. */
4063	typedef FNIEMAIMPLSSEF2I32U64 *PFNIEMAIMPLSSEF2I32U64;
4064	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I64U64,(uint32_t uMxCsrIn, int64_t pi64Dst, const uint64_t pu64Src)); /* pu64Src is a double precision floating point. */
4065	typedef FNIEMAIMPLSSEF2I64U64 *PFNIEMAIMPLSSEF2I64U64;
4066	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I32U32,(uint32_t uMxCsrIn, int32_t pi32Dst, const uint32_t pu32Src)); /* pu32Src is a single precision floating point. */
4067	typedef FNIEMAIMPLSSEF2I32U32 *PFNIEMAIMPLSSEF2I32U32;
4068	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I64U32,(uint32_t uMxCsrIn, int64_t pi64Dst, const uint32_t pu32Src)); /* pu32Src is a single precision floating point. */
4069	typedef FNIEMAIMPLSSEF2I64U32 *PFNIEMAIMPLSSEF2I64U32;
4070
4071	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvttsd2si_i32_r64;
4072	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvtsd2si_i32_r64;
4073
4074	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvttsd2si_i64_r64;
4075	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvtsd2si_i64_r64;
4076
4077	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvttss2si_i32_r32;
4078	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvtss2si_i32_r32;
4079
4080	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvttss2si_i64_r32;
4081	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvtss2si_i64_r32;
4082
4083	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R32I32,(uint32_t uMxCsrIn, PRTFLOAT32U pr32Dst, const int32_t *pi32Src));
4084	typedef FNIEMAIMPLSSEF2R32I32 *PFNIEMAIMPLSSEF2R32I32;
4085	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R32I64,(uint32_t uMxCsrIn, PRTFLOAT32U pr32Dst, const int64_t *pi64Src));
4086	typedef FNIEMAIMPLSSEF2R32I64 *PFNIEMAIMPLSSEF2R32I64;
4087
4088	FNIEMAIMPLSSEF2R32I32 iemAImpl_cvtsi2ss_r32_i32;
4089	FNIEMAIMPLSSEF2R32I64 iemAImpl_cvtsi2ss_r32_i64;
4090
4091	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R64I32,(uint32_t uMxCsrIn, PRTFLOAT64U pr64Dst, const int32_t *pi32Src));
4092	typedef FNIEMAIMPLSSEF2R64I32 *PFNIEMAIMPLSSEF2R64I32;
4093	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R64I64,(uint32_t uMxCsrIn, PRTFLOAT64U pr64Dst, const int64_t *pi64Src));
4094	typedef FNIEMAIMPLSSEF2R64I64 *PFNIEMAIMPLSSEF2R64I64;
4095
4096	FNIEMAIMPLSSEF2R64I32 iemAImpl_cvtsi2sd_r64_i32;
4097	FNIEMAIMPLSSEF2R64I64 iemAImpl_cvtsi2sd_r64_i64;
4098
4099
4100	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLF2EFLMXCSRR32R32,(uint32_t uMxCsrIn, uint32_t *pfEFlags, RTFLOAT32U uSrc1, RTFLOAT32U uSrc2));
4101	typedef FNIEMAIMPLF2EFLMXCSRR32R32 *PFNIEMAIMPLF2EFLMXCSRR32R32;
4102
4103	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLF2EFLMXCSRR64R64,(uint32_t uMxCsrIn, uint32_t *pfEFlags, RTFLOAT64U uSrc1, RTFLOAT64U uSrc2));
4104	typedef FNIEMAIMPLF2EFLMXCSRR64R64 *PFNIEMAIMPLF2EFLMXCSRR64R64;
4105
4106	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_ucomiss_u128;
4107	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback;
4108
4109	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_ucomisd_u128;
4110	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback;
4111
4112	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_comiss_u128;
4113	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback;
4114
4115	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_comisd_u128;
4116	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback;
4117
4118
4119	typedef struct IEMMEDIAF2XMMSRC
4120	{
4121	X86XMMREG uSrc1;
4122	X86XMMREG uSrc2;
4123	} IEMMEDIAF2XMMSRC;
4124	typedef IEMMEDIAF2XMMSRC *PIEMMEDIAF2XMMSRC;
4125	typedef const IEMMEDIAF2XMMSRC *PCIEMMEDIAF2XMMSRC;
4126
4127	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRF2XMMIMM8,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCIEMMEDIAF2XMMSRC puSrc, uint8_t bEvil));
4128	typedef FNIEMAIMPLMXCSRF2XMMIMM8 *PFNIEMAIMPLMXCSRF2XMMIMM8;
4129
4130	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpps_u128;
4131	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmppd_u128;
4132	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpss_u128;
4133	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpsd_u128;
4134	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundss_u128;
4135	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundsd_u128;
4136
4137	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundps_u128, iemAImpl_roundps_u128_fallback;
4138	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundpd_u128, iemAImpl_roundpd_u128_fallback;
4139
4140	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_dpps_u128, iemAImpl_dpps_u128_fallback;
4141	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_dppd_u128, iemAImpl_dppd_u128_fallback;
4142
4143	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRU64U128,(uint32_t fMxCsrIn, uint64_t *pu64Dst, PCX86XMMREG pSrc));
4144	typedef FNIEMAIMPLMXCSRU64U128 *PFNIEMAIMPLMXCSRU64U128;
4145
4146	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvtpd2pi_u128;
4147	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvttpd2pi_u128;
4148
4149	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRU128U64,(uint32_t fMxCsrIn, PX86XMMREG pDst, uint64_t u64Src));
4150	typedef FNIEMAIMPLMXCSRU128U64 *PFNIEMAIMPLMXCSRU128U64;
4151
4152	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2ps_u128;
4153	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2pd_u128;
4154
4155	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRU64U64,(uint32_t fMxCsrIn, uint64_t *pu64Dst, uint64_t u64Src));
4156	typedef FNIEMAIMPLMXCSRU64U64 *PFNIEMAIMPLMXCSRU64U64;
4157
4158	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvtps2pi_u128;
4159	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvttps2pi_u128;
4160
4161	/** @} */
4162
4163
4164	/** @name Function tables.
4165	* @{
4166	*/
4167
4168	/**
4169	* Function table for a binary operator providing implementation based on
4170	* operand size.
4171	*/
4172	typedef struct IEMOPBINSIZES
4173	{
4174	PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
4175	PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
4176	PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
4177	PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
4178	} IEMOPBINSIZES;
4179	/** Pointer to a binary operator function table. */
4180	typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
4181
4182
4183	/**
4184	* Function table for a unary operator providing implementation based on
4185	* operand size.
4186	*/
4187	typedef struct IEMOPUNARYSIZES
4188	{
4189	PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
4190	PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
4191	PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
4192	PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
4193	} IEMOPUNARYSIZES;
4194	/** Pointer to a unary operator function table. */
4195	typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
4196
4197
4198	/**
4199	* Function table for a shift operator providing implementation based on
4200	* operand size.
4201	*/
4202	typedef struct IEMOPSHIFTSIZES
4203	{
4204	PFNIEMAIMPLSHIFTU8 pfnNormalU8;
4205	PFNIEMAIMPLSHIFTU16 pfnNormalU16;
4206	PFNIEMAIMPLSHIFTU32 pfnNormalU32;
4207	PFNIEMAIMPLSHIFTU64 pfnNormalU64;
4208	} IEMOPSHIFTSIZES;
4209	/** Pointer to a shift operator function table. */
4210	typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
4211
4212
4213	/**
4214	* Function table for a multiplication or division operation.
4215	*/
4216	typedef struct IEMOPMULDIVSIZES
4217	{
4218	PFNIEMAIMPLMULDIVU8 pfnU8;
4219	PFNIEMAIMPLMULDIVU16 pfnU16;
4220	PFNIEMAIMPLMULDIVU32 pfnU32;
4221	PFNIEMAIMPLMULDIVU64 pfnU64;
4222	} IEMOPMULDIVSIZES;
4223	/** Pointer to a multiplication or division operation function table. */
4224	typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
4225
4226
4227	/**
4228	* Function table for a double precision shift operator providing implementation
4229	* based on operand size.
4230	*/
4231	typedef struct IEMOPSHIFTDBLSIZES
4232	{
4233	PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
4234	PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
4235	PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
4236	} IEMOPSHIFTDBLSIZES;
4237	/** Pointer to a double precision shift function table. */
4238	typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
4239
4240
4241	/**
4242	* Function table for media instruction taking two full sized media source
4243	* registers and one full sized destination register (AVX).
4244	*/
4245	typedef struct IEMOPMEDIAF3
4246	{
4247	PFNIEMAIMPLMEDIAF3U128 pfnU128;
4248	PFNIEMAIMPLMEDIAF3U256 pfnU256;
4249	} IEMOPMEDIAF3;
4250	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
4251	typedef IEMOPMEDIAF3 const *PCIEMOPMEDIAF3;
4252
4253	/** @def IEMOPMEDIAF3_INIT_VARS_EX
4254	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4255	* given functions as initializers. For use in AVX functions where a pair of
4256	* functions are only used once and the function table need not be public. */
4257	#ifndef TST_IEM_CHECK_MC
4258	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4259	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4260	static IEMOPMEDIAF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4261	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4262	# else
4263	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4264	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4265	# endif
4266	#else
4267	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4268	#endif
4269	/** @def IEMOPMEDIAF3_INIT_VARS
4270	* Generate AVX function tables for the @a a_InstrNm instruction.
4271	* @sa IEMOPMEDIAF3_INIT_VARS_EX */
4272	#define IEMOPMEDIAF3_INIT_VARS(a_InstrNm) \
4273	IEMOPMEDIAF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4274	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4275
4276	/**
4277	* Function table for media instruction taking two full sized media source
4278	* registers and one full sized destination register, but no additional state
4279	* (AVX).
4280	*/
4281	typedef struct IEMOPMEDIAOPTF3
4282	{
4283	PFNIEMAIMPLMEDIAOPTF3U128 pfnU128;
4284	PFNIEMAIMPLMEDIAOPTF3U256 pfnU256;
4285	} IEMOPMEDIAOPTF3;
4286	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
4287	typedef IEMOPMEDIAOPTF3 const *PCIEMOPMEDIAOPTF3;
4288
4289	/** @def IEMOPMEDIAOPTF3_INIT_VARS_EX
4290	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4291	* given functions as initializers. For use in AVX functions where a pair of
4292	* functions are only used once and the function table need not be public. */
4293	#ifndef TST_IEM_CHECK_MC
4294	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4295	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4296	static IEMOPMEDIAOPTF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4297	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4298	# else
4299	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4300	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4301	# endif
4302	#else
4303	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4304	#endif
4305	/** @def IEMOPMEDIAOPTF3_INIT_VARS
4306	* Generate AVX function tables for the @a a_InstrNm instruction.
4307	* @sa IEMOPMEDIAOPTF3_INIT_VARS_EX */
4308	#define IEMOPMEDIAOPTF3_INIT_VARS(a_InstrNm) \
4309	IEMOPMEDIAOPTF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4310	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4311
4312	/**
4313	* Function table for media instruction taking one full sized media source
4314	* registers and one full sized destination register, but no additional state
4315	* (AVX).
4316	*/
4317	typedef struct IEMOPMEDIAOPTF2
4318	{
4319	PFNIEMAIMPLMEDIAOPTF2U128 pfnU128;
4320	PFNIEMAIMPLMEDIAOPTF2U256 pfnU256;
4321	} IEMOPMEDIAOPTF2;
4322	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
4323	typedef IEMOPMEDIAOPTF2 const *PCIEMOPMEDIAOPTF2;
4324
4325	/** @def IEMOPMEDIAOPTF2_INIT_VARS_EX
4326	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4327	* given functions as initializers. For use in AVX functions where a pair of
4328	* functions are only used once and the function table need not be public. */
4329	#ifndef TST_IEM_CHECK_MC
4330	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4331	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4332	static IEMOPMEDIAOPTF2 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4333	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4334	# else
4335	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4336	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4337	# endif
4338	#else
4339	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4340	#endif
4341	/** @def IEMOPMEDIAOPTF2_INIT_VARS
4342	* Generate AVX function tables for the @a a_InstrNm instruction.
4343	* @sa IEMOPMEDIAOPTF2_INIT_VARS_EX */
4344	#define IEMOPMEDIAOPTF2_INIT_VARS(a_InstrNm) \
4345	IEMOPMEDIAOPTF2_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4346	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4347
4348	/**
4349	* Function table for media instruction taking one full sized media source
4350	* register and one full sized destination register and an 8-bit immediate, but no additional state
4351	* (AVX).
4352	*/
4353	typedef struct IEMOPMEDIAOPTF2IMM8
4354	{
4355	PFNIEMAIMPLMEDIAOPTF2U128IMM8 pfnU128;
4356	PFNIEMAIMPLMEDIAOPTF2U256IMM8 pfnU256;
4357	} IEMOPMEDIAOPTF2IMM8;
4358	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
4359	typedef IEMOPMEDIAOPTF2IMM8 const *PCIEMOPMEDIAOPTF2IMM8;
4360
4361	/** @def IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX
4362	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4363	* given functions as initializers. For use in AVX functions where a pair of
4364	* functions are only used once and the function table need not be public. */
4365	#ifndef TST_IEM_CHECK_MC
4366	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4367	# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4368	static IEMOPMEDIAOPTF2IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4369	static IEMOPMEDIAOPTF2IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4370	# else
4371	# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4372	static IEMOPMEDIAOPTF2IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4373	# endif
4374	#else
4375	# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4376	#endif
4377	/** @def IEMOPMEDIAOPTF2IMM8_INIT_VARS
4378	* Generate AVX function tables for the @a a_InstrNm instruction.
4379	* @sa IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX */
4380	#define IEMOPMEDIAOPTF2IMM8_INIT_VARS(a_InstrNm) \
4381	IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u256),\
4382	RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u256_fallback))
4383
4384	/**
4385	* Function table for media instruction taking two full sized media source
4386	* registers and one full sized destination register and an 8-bit immediate, but no additional state
4387	* (AVX).
4388	*/
4389	typedef struct IEMOPMEDIAOPTF3IMM8
4390	{
4391	PFNIEMAIMPLMEDIAOPTF3U128IMM8 pfnU128;
4392	PFNIEMAIMPLMEDIAOPTF3U256IMM8 pfnU256;
4393	} IEMOPMEDIAOPTF3IMM8;
4394	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
4395	typedef IEMOPMEDIAOPTF3IMM8 const *PCIEMOPMEDIAOPTF3IMM8;
4396
4397	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX
4398	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4399	* given functions as initializers. For use in AVX functions where a pair of
4400	* functions are only used once and the function table need not be public. */
4401	#ifndef TST_IEM_CHECK_MC
4402	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4403	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4404	static IEMOPMEDIAOPTF3IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4405	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4406	# else
4407	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4408	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4409	# endif
4410	#else
4411	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4412	#endif
4413	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS
4414	* Generate AVX function tables for the @a a_InstrNm instruction.
4415	* @sa IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX */
4416	#define IEMOPMEDIAOPTF3IMM8_INIT_VARS(a_InstrNm) \
4417	IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4418	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4419	/** @} */
4420
4421
4422	/**
4423	* Function table for blend type instruction taking three full sized media source
4424	* registers and one full sized destination register, but no additional state
4425	* (AVX).
4426	*/
4427	typedef struct IEMOPBLENDOP
4428	{
4429	PFNIEMAIMPLAVXBLENDU128 pfnU128;
4430	PFNIEMAIMPLAVXBLENDU256 pfnU256;
4431	} IEMOPBLENDOP;
4432	/** Pointer to a media operation function table for 4 full sized ops (AVX). */
4433	typedef IEMOPBLENDOP const *PCIEMOPBLENDOP;
4434
4435	/** @def IEMOPBLENDOP_INIT_VARS_EX
4436	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4437	* given functions as initializers. For use in AVX functions where a pair of
4438	* functions are only used once and the function table need not be public. */
4439	#ifndef TST_IEM_CHECK_MC
4440	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4441	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4442	static IEMOPBLENDOP const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4443	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4444	# else
4445	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4446	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4447	# endif
4448	#else
4449	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4450	#endif
4451	/** @def IEMOPBLENDOP_INIT_VARS
4452	* Generate AVX function tables for the @a a_InstrNm instruction.
4453	* @sa IEMOPBLENDOP_INIT_VARS_EX */
4454	#define IEMOPBLENDOP_INIT_VARS(a_InstrNm) \
4455	IEMOPBLENDOP_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4456	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4457
4458
4459	/** @name SSE/AVX single/double precision floating point operations.
4460	* @{ */
4461	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
4462	typedef FNIEMAIMPLFPSSEF2U128 *PFNIEMAIMPLFPSSEF2U128;
4463	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128R32,(uint32_t uMxCsrIn, PX86XMMREG Result, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
4464	typedef FNIEMAIMPLFPSSEF2U128R32 *PFNIEMAIMPLFPSSEF2U128R32;
4465	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128R64,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
4466	typedef FNIEMAIMPLFPSSEF2U128R64 *PFNIEMAIMPLFPSSEF2U128R64;
4467
4468	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
4469	typedef FNIEMAIMPLFPAVXF3U128 *PFNIEMAIMPLFPAVXF3U128;
4470	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U128R32,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
4471	typedef FNIEMAIMPLFPAVXF3U128R32 *PFNIEMAIMPLFPAVXF3U128R32;
4472	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U128R64,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
4473	typedef FNIEMAIMPLFPAVXF3U128R64 *PFNIEMAIMPLFPAVXF3U128R64;
4474
4475	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U256,(uint32_t uMxCsrIn, PX86YMMREG pResult, PCX86YMMREG puSrc1, PCX86YMMREG puSrc2));
4476	typedef FNIEMAIMPLFPAVXF3U256 *PFNIEMAIMPLFPAVXF3U256;
4477
4478	FNIEMAIMPLFPSSEF2U128 iemAImpl_addps_u128;
4479	FNIEMAIMPLFPSSEF2U128 iemAImpl_addpd_u128;
4480	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulps_u128;
4481	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulpd_u128;
4482	FNIEMAIMPLFPSSEF2U128 iemAImpl_subps_u128;
4483	FNIEMAIMPLFPSSEF2U128 iemAImpl_subpd_u128;
4484	FNIEMAIMPLFPSSEF2U128 iemAImpl_minps_u128;
4485	FNIEMAIMPLFPSSEF2U128 iemAImpl_minpd_u128;
4486	FNIEMAIMPLFPSSEF2U128 iemAImpl_divps_u128;
4487	FNIEMAIMPLFPSSEF2U128 iemAImpl_divpd_u128;
4488	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxps_u128;
4489	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxpd_u128;
4490	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddps_u128;
4491	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddpd_u128;
4492	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubps_u128;
4493	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubpd_u128;
4494	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtps_u128;
4495	FNIEMAIMPLFPSSEF2U128 iemAImpl_rsqrtps_u128;
4496	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtpd_u128;
4497	FNIEMAIMPLFPSSEF2U128 iemAImpl_rcpps_u128;
4498	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubps_u128;
4499	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubpd_u128;
4500
4501	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2ps_u128;
4502	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_cvtps2pd_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, uint64_t const *pu64Src));
4503
4504	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2ps_u128;
4505	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2dq_u128;
4506	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttps2dq_u128;
4507	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttpd2dq_u128;
4508	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2pd_u128;
4509	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2dq_u128;
4510
4511	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_addss_u128_r32;
4512	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_addsd_u128_r64;
4513	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_mulss_u128_r32;
4514	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_mulsd_u128_r64;
4515	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_subss_u128_r32;
4516	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_subsd_u128_r64;
4517	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_minss_u128_r32;
4518	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_minsd_u128_r64;
4519	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_divss_u128_r32;
4520	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_divsd_u128_r64;
4521	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_maxss_u128_r32;
4522	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_maxsd_u128_r64;
4523	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_cvtss2sd_u128_r32;
4524	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_cvtsd2ss_u128_r64;
4525	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_sqrtss_u128_r32;
4526	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_sqrtsd_u128_r64;
4527	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_rsqrtss_u128_r32;
4528	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_rcpss_u128_r32;
4529
4530	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddps_u128, iemAImpl_vaddps_u128_fallback;
4531	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddpd_u128, iemAImpl_vaddpd_u128_fallback;
4532	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulps_u128, iemAImpl_vmulps_u128_fallback;
4533	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulpd_u128, iemAImpl_vmulpd_u128_fallback;
4534	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubps_u128, iemAImpl_vsubps_u128_fallback;
4535	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubpd_u128, iemAImpl_vsubpd_u128_fallback;
4536	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminps_u128, iemAImpl_vminps_u128_fallback;
4537	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminpd_u128, iemAImpl_vminpd_u128_fallback;
4538	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivps_u128, iemAImpl_vdivps_u128_fallback;
4539	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivpd_u128, iemAImpl_vdivpd_u128_fallback;
4540	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxps_u128, iemAImpl_vmaxps_u128_fallback;
4541	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxpd_u128, iemAImpl_vmaxpd_u128_fallback;
4542	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddps_u128, iemAImpl_vhaddps_u128_fallback;
4543	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddpd_u128, iemAImpl_vhaddpd_u128_fallback;
4544	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubps_u128, iemAImpl_vhsubps_u128_fallback;
4545	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubpd_u128, iemAImpl_vhsubpd_u128_fallback;
4546	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtps_u128, iemAImpl_vsqrtps_u128_fallback;
4547	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtpd_u128, iemAImpl_vsqrtpd_u128_fallback;
4548	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubps_u128, iemAImpl_vaddsubps_u128_fallback;
4549	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubpd_u128, iemAImpl_vaddsubpd_u128_fallback;
4550	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtpd2ps_u128, iemAImpl_vcvtpd2ps_u128_fallback;
4551	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtps2pd_u128, iemAImpl_vcvtps2pd_u128_fallback;
4552
4553	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vaddss_u128_r32, iemAImpl_vaddss_u128_r32_fallback;
4554	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vaddsd_u128_r64, iemAImpl_vaddsd_u128_r64_fallback;
4555	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmulss_u128_r32, iemAImpl_vmulss_u128_r32_fallback;
4556	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmulsd_u128_r64, iemAImpl_vmulsd_u128_r64_fallback;
4557	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsubss_u128_r32, iemAImpl_vsubss_u128_r32_fallback;
4558	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsubsd_u128_r64, iemAImpl_vsubsd_u128_r64_fallback;
4559	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vminss_u128_r32, iemAImpl_vminss_u128_r32_fallback;
4560	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vminsd_u128_r64, iemAImpl_vminsd_u128_r64_fallback;
4561	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vdivss_u128_r32, iemAImpl_vdivss_u128_r32_fallback;
4562	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vdivsd_u128_r64, iemAImpl_vdivsd_u128_r64_fallback;
4563	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmaxss_u128_r32, iemAImpl_vmaxss_u128_r32_fallback;
4564	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmaxsd_u128_r64, iemAImpl_vmaxsd_u128_r64_fallback;
4565	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsqrtss_u128_r32, iemAImpl_vsqrtss_u128_r32_fallback;
4566	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsqrtsd_u128_r64, iemAImpl_vsqrtsd_u128_r64_fallback;
4567
4568	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddps_u256, iemAImpl_vaddps_u256_fallback;
4569	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddpd_u256, iemAImpl_vaddpd_u256_fallback;
4570	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulps_u256, iemAImpl_vmulps_u256_fallback;
4571	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulpd_u256, iemAImpl_vmulpd_u256_fallback;
4572	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubps_u256, iemAImpl_vsubps_u256_fallback;
4573	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubpd_u256, iemAImpl_vsubpd_u256_fallback;
4574	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminps_u256, iemAImpl_vminps_u256_fallback;
4575	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminpd_u256, iemAImpl_vminpd_u256_fallback;
4576	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivps_u256, iemAImpl_vdivps_u256_fallback;
4577	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivpd_u256, iemAImpl_vdivpd_u256_fallback;
4578	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxps_u256, iemAImpl_vmaxps_u256_fallback;
4579	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxpd_u256, iemAImpl_vmaxpd_u256_fallback;
4580	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddps_u256, iemAImpl_vhaddps_u256_fallback;
4581	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddpd_u256, iemAImpl_vhaddpd_u256_fallback;
4582	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubps_u256, iemAImpl_vhsubps_u256_fallback;
4583	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubpd_u256, iemAImpl_vhsubpd_u256_fallback;
4584	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubps_u256, iemAImpl_vhaddsubps_u256_fallback;
4585	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubpd_u256, iemAImpl_vhaddsubpd_u256_fallback;
4586	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtpd2ps_u256, iemAImpl_vcvtpd2ps_u256_fallback;
4587	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtps2pd_u256, iemAImpl_vcvtps2pd_u256_fallback;
4588	/** @} */
4589
4590	/** @name C instruction implementations for anything slightly complicated.
4591	* @{ */
4592
4593	/**
4594	* For typedef'ing or declaring a C instruction implementation function taking
4595	* no extra arguments.
4596	*
4597	* @param a_Name The name of the type.
4598	*/
4599	# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
4600	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
4601	/**
4602	* For defining a C instruction implementation function taking no extra
4603	* arguments.
4604	*
4605	* @param a_Name The name of the function
4606	*/
4607	# define IEM_CIMPL_DEF_0(a_Name) \
4608	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
4609	/**
4610	* Prototype version of IEM_CIMPL_DEF_0.
4611	*/
4612	# define IEM_CIMPL_PROTO_0(a_Name) \
4613	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
4614	/**
4615	* For calling a C instruction implementation function taking no extra
4616	* arguments.
4617	*
4618	* This special call macro adds default arguments to the call and allow us to
4619	* change these later.
4620	*
4621	* @param a_fn The name of the function.
4622	*/
4623	# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
4624
4625	/** Type for a C instruction implementation function taking no extra
4626	* arguments. */
4627	typedef IEM_CIMPL_DECL_TYPE_0(FNIEMCIMPL0);
4628	/** Function pointer type for a C instruction implementation function taking
4629	* no extra arguments. */
4630	typedef FNIEMCIMPL0 *PFNIEMCIMPL0;
4631
4632	/**
4633	* For typedef'ing or declaring a C instruction implementation function taking
4634	* one extra argument.
4635	*
4636	* @param a_Name The name of the type.
4637	* @param a_Type0 The argument type.
4638	* @param a_Arg0 The argument name.
4639	*/
4640	# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
4641	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
4642	/**
4643	* For defining a C instruction implementation function taking one extra
4644	* argument.
4645	*
4646	* @param a_Name The name of the function
4647	* @param a_Type0 The argument type.
4648	* @param a_Arg0 The argument name.
4649	*/
4650	# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
4651	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
4652	/**
4653	* Prototype version of IEM_CIMPL_DEF_1.
4654	*/
4655	# define IEM_CIMPL_PROTO_1(a_Name, a_Type0, a_Arg0) \
4656	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
4657	/**
4658	* For calling a C instruction implementation function taking one extra
4659	* argument.
4660	*
4661	* This special call macro adds default arguments to the call and allow us to
4662	* change these later.
4663	*
4664	* @param a_fn The name of the function.
4665	* @param a0 The name of the 1st argument.
4666	*/
4667	# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
4668
4669	/**
4670	* For typedef'ing or declaring a C instruction implementation function taking
4671	* two extra arguments.
4672	*
4673	* @param a_Name The name of the type.
4674	* @param a_Type0 The type of the 1st argument
4675	* @param a_Arg0 The name of the 1st argument.
4676	* @param a_Type1 The type of the 2nd argument.
4677	* @param a_Arg1 The name of the 2nd argument.
4678	*/
4679	# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
4680	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
4681	/**
4682	* For defining a C instruction implementation function taking two extra
4683	* arguments.
4684	*
4685	* @param a_Name The name of the function.
4686	* @param a_Type0 The type of the 1st argument
4687	* @param a_Arg0 The name of the 1st argument.
4688	* @param a_Type1 The type of the 2nd argument.
4689	* @param a_Arg1 The name of the 2nd argument.
4690	*/
4691	# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
4692	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
4693	/**
4694	* Prototype version of IEM_CIMPL_DEF_2.
4695	*/
4696	# define IEM_CIMPL_PROTO_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
4697	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
4698	/**
4699	* For calling a C instruction implementation function taking two extra
4700	* arguments.
4701	*
4702	* This special call macro adds default arguments to the call and allow us to
4703	* change these later.
4704	*
4705	* @param a_fn The name of the function.
4706	* @param a0 The name of the 1st argument.
4707	* @param a1 The name of the 2nd argument.
4708	*/
4709	# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
4710
4711	/**
4712	* For typedef'ing or declaring a C instruction implementation function taking
4713	* three extra arguments.
4714	*
4715	* @param a_Name The name of the type.
4716	* @param a_Type0 The type of the 1st argument
4717	* @param a_Arg0 The name of the 1st argument.
4718	* @param a_Type1 The type of the 2nd argument.
4719	* @param a_Arg1 The name of the 2nd argument.
4720	* @param a_Type2 The type of the 3rd argument.
4721	* @param a_Arg2 The name of the 3rd argument.
4722	*/
4723	# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
4724	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
4725	/**
4726	* For defining a C instruction implementation function taking three extra
4727	* arguments.
4728	*
4729	* @param a_Name The name of the function.
4730	* @param a_Type0 The type of the 1st argument
4731	* @param a_Arg0 The name of the 1st argument.
4732	* @param a_Type1 The type of the 2nd argument.
4733	* @param a_Arg1 The name of the 2nd argument.
4734	* @param a_Type2 The type of the 3rd argument.
4735	* @param a_Arg2 The name of the 3rd argument.
4736	*/
4737	# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
4738	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
4739	/**
4740	* Prototype version of IEM_CIMPL_DEF_3.
4741	*/
4742	# define IEM_CIMPL_PROTO_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
4743	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
4744	/**
4745	* For calling a C instruction implementation function taking three extra
4746	* arguments.
4747	*
4748	* This special call macro adds default arguments to the call and allow us to
4749	* change these later.
4750	*
4751	* @param a_fn The name of the function.
4752	* @param a0 The name of the 1st argument.
4753	* @param a1 The name of the 2nd argument.
4754	* @param a2 The name of the 3rd argument.
4755	*/
4756	# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
4757
4758
4759	/**
4760	* For typedef'ing or declaring a C instruction implementation function taking
4761	* four extra arguments.
4762	*
4763	* @param a_Name The name of the type.
4764	* @param a_Type0 The type of the 1st argument
4765	* @param a_Arg0 The name of the 1st argument.
4766	* @param a_Type1 The type of the 2nd argument.
4767	* @param a_Arg1 The name of the 2nd argument.
4768	* @param a_Type2 The type of the 3rd argument.
4769	* @param a_Arg2 The name of the 3rd argument.
4770	* @param a_Type3 The type of the 4th argument.
4771	* @param a_Arg3 The name of the 4th argument.
4772	*/
4773	# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
4774	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
4775	/**
4776	* For defining a C instruction implementation function taking four extra
4777	* arguments.
4778	*
4779	* @param a_Name The name of the function.
4780	* @param a_Type0 The type of the 1st argument
4781	* @param a_Arg0 The name of the 1st argument.
4782	* @param a_Type1 The type of the 2nd argument.
4783	* @param a_Arg1 The name of the 2nd argument.
4784	* @param a_Type2 The type of the 3rd argument.
4785	* @param a_Arg2 The name of the 3rd argument.
4786	* @param a_Type3 The type of the 4th argument.
4787	* @param a_Arg3 The name of the 4th argument.
4788	*/
4789	# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
4790	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4791	a_Type2 a_Arg2, a_Type3 a_Arg3))
4792	/**
4793	* Prototype version of IEM_CIMPL_DEF_4.
4794	*/
4795	# define IEM_CIMPL_PROTO_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
4796	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4797	a_Type2 a_Arg2, a_Type3 a_Arg3))
4798	/**
4799	* For calling a C instruction implementation function taking four extra
4800	* arguments.
4801	*
4802	* This special call macro adds default arguments to the call and allow us to
4803	* change these later.
4804	*
4805	* @param a_fn The name of the function.
4806	* @param a0 The name of the 1st argument.
4807	* @param a1 The name of the 2nd argument.
4808	* @param a2 The name of the 3rd argument.
4809	* @param a3 The name of the 4th argument.
4810	*/
4811	# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
4812
4813
4814	/**
4815	* For typedef'ing or declaring a C instruction implementation function taking
4816	* five extra arguments.
4817	*
4818	* @param a_Name The name of the type.
4819	* @param a_Type0 The type of the 1st argument
4820	* @param a_Arg0 The name of the 1st argument.
4821	* @param a_Type1 The type of the 2nd argument.
4822	* @param a_Arg1 The name of the 2nd argument.
4823	* @param a_Type2 The type of the 3rd argument.
4824	* @param a_Arg2 The name of the 3rd argument.
4825	* @param a_Type3 The type of the 4th argument.
4826	* @param a_Arg3 The name of the 4th argument.
4827	* @param a_Type4 The type of the 5th argument.
4828	* @param a_Arg4 The name of the 5th argument.
4829	*/
4830	# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
4831	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, \
4832	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
4833	a_Type3 a_Arg3, a_Type4 a_Arg4))
4834	/**
4835	* For defining a C instruction implementation function taking five extra
4836	* arguments.
4837	*
4838	* @param a_Name The name of the function.
4839	* @param a_Type0 The type of the 1st argument
4840	* @param a_Arg0 The name of the 1st argument.
4841	* @param a_Type1 The type of the 2nd argument.
4842	* @param a_Arg1 The name of the 2nd argument.
4843	* @param a_Type2 The type of the 3rd argument.
4844	* @param a_Arg2 The name of the 3rd argument.
4845	* @param a_Type3 The type of the 4th argument.
4846	* @param a_Arg3 The name of the 4th argument.
4847	* @param a_Type4 The type of the 5th argument.
4848	* @param a_Arg4 The name of the 5th argument.
4849	*/
4850	# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
4851	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4852	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
4853	/**
4854	* Prototype version of IEM_CIMPL_DEF_5.
4855	*/
4856	# define IEM_CIMPL_PROTO_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
4857	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4858	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
4859	/**
4860	* For calling a C instruction implementation function taking five extra
4861	* arguments.
4862	*
4863	* This special call macro adds default arguments to the call and allow us to
4864	* change these later.
4865	*
4866	* @param a_fn The name of the function.
4867	* @param a0 The name of the 1st argument.
4868	* @param a1 The name of the 2nd argument.
4869	* @param a2 The name of the 3rd argument.
4870	* @param a3 The name of the 4th argument.
4871	* @param a4 The name of the 5th argument.
4872	*/
4873	# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
4874
4875	/** @} */
4876
4877
4878	/** @name Opcode Decoder Function Types.
4879	* @{ */
4880
4881	/** @typedef PFNIEMOP
4882	* Pointer to an opcode decoder function.
4883	*/
4884
4885	/** @def FNIEMOP_DEF
4886	* Define an opcode decoder function.
4887	*
4888	* We're using macors for this so that adding and removing parameters as well as
4889	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL
4890	*
4891	* @param a_Name The function name.
4892	*/
4893
4894	/** @typedef PFNIEMOPRM
4895	* Pointer to an opcode decoder function with RM byte.
4896	*/
4897
4898	/** @def FNIEMOPRM_DEF
4899	* Define an opcode decoder function with RM byte.
4900	*
4901	* We're using macors for this so that adding and removing parameters as well as
4902	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL_1
4903	*
4904	* @param a_Name The function name.
4905	*/
4906
4907	#if defined(__GNUC__) && defined(RT_ARCH_X86)
4908	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOP)(PVMCPUCC pVCpu);
4909	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4910	# define FNIEMOP_DEF(a_Name) \
4911	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu)
4912	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4913	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
4914	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4915	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
4916
4917	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
4918	typedef VBOXSTRICTRC (__fastcall * PFNIEMOP)(PVMCPUCC pVCpu);
4919	typedef VBOXSTRICTRC (__fastcall * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4920	# define FNIEMOP_DEF(a_Name) \
4921	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
4922	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4923	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
4924	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4925	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
4926
4927	#elif defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
4928	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
4929	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4930	# define FNIEMOP_DEF(a_Name) \
4931	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu)
4932	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4933	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
4934	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4935	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
4936
4937	#else
4938	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
4939	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4940	# define FNIEMOP_DEF(a_Name) \
4941	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
4942	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4943	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
4944	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4945	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
4946
4947	#endif
4948	#define FNIEMOPRM_DEF(a_Name) FNIEMOP_DEF_1(a_Name, uint8_t, bRm)
4949
4950	/**
4951	* Call an opcode decoder function.
4952	*
4953	* We're using macors for this so that adding and removing parameters can be
4954	* done as we please. See FNIEMOP_DEF.
4955	*/
4956	#define FNIEMOP_CALL(a_pfn) (a_pfn)(pVCpu)
4957
4958	/**
4959	* Call a common opcode decoder function taking one extra argument.
4960	*
4961	* We're using macors for this so that adding and removing parameters can be
4962	* done as we please. See FNIEMOP_DEF_1.
4963	*/
4964	#define FNIEMOP_CALL_1(a_pfn, a0) (a_pfn)(pVCpu, a0)
4965
4966	/**
4967	* Call a common opcode decoder function taking one extra argument.
4968	*
4969	* We're using macors for this so that adding and removing parameters can be
4970	* done as we please. See FNIEMOP_DEF_1.
4971	*/
4972	#define FNIEMOP_CALL_2(a_pfn, a0, a1) (a_pfn)(pVCpu, a0, a1)
4973	/** @} */
4974
4975
4976	/** @name Misc Helpers
4977	* @{ */
4978
4979	/** Used to shut up GCC warnings about variables that 'may be used uninitialized'
4980	* due to GCC lacking knowledge about the value range of a switch. */
4981	#if RT_CPLUSPLUS_PREREQ(202000)
4982	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: [[unlikely]] AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
4983	#else
4984	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
4985	#endif
4986
4987	/** Variant of IEM_NOT_REACHED_DEFAULT_CASE_RET that returns a custom value. */
4988	#if RT_CPLUSPLUS_PREREQ(202000)
4989	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: [[unlikely]] AssertFailedReturn(a_RetValue)
4990	#else
4991	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: AssertFailedReturn(a_RetValue)
4992	#endif
4993
4994	/**
4995	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
4996	* occation.
4997	*/
4998	#ifdef LOG_ENABLED
4999	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
5000	do { \
5001	/Log/ LogAlways(("%s: returning IEM_RETURN_ASPECT_NOT_IMPLEMENTED (line %d)\n", __FUNCTION__, __LINE__)); \
5002	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
5003	} while (0)
5004	#else
5005	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
5006	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
5007	#endif
5008
5009	/**
5010	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
5011	* occation using the supplied logger statement.
5012	*
5013	* @param a_LoggerArgs What to log on failure.
5014	*/
5015	#ifdef LOG_ENABLED
5016	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
5017	do { \
5018	LogAlways((LOG_FN_FMT ": ", __PRETTY_FUNCTION__)); LogAlways(a_LoggerArgs); \
5019	/LogFunc(a_LoggerArgs);/ \
5020	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
5021	} while (0)
5022	#else
5023	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
5024	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
5025	#endif
5026
5027	/**
5028	* Gets the CPU mode (from fExec) as a IEMMODE value.
5029	*
5030	* @returns IEMMODE
5031	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5032	*/
5033	#define IEM_GET_CPU_MODE(a_pVCpu) ((a_pVCpu)->iem.s.fExec & IEM_F_MODE_CPUMODE_MASK)
5034
5035	/**
5036	* Check if we're currently executing in real or virtual 8086 mode.
5037	*
5038	* @returns @c true if it is, @c false if not.
5039	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5040	*/
5041	#define IEM_IS_REAL_OR_V86_MODE(a_pVCpu) (( ((a_pVCpu)->iem.s.fExec ^ IEM_F_MODE_X86_PROT_MASK) \
5042	& (IEM_F_MODE_X86_V86_MASK \| IEM_F_MODE_X86_PROT_MASK)) != 0)
5043
5044	/**
5045	* Check if we're currently executing in virtual 8086 mode.
5046	*
5047	* @returns @c true if it is, @c false if not.
5048	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5049	*/
5050	#define IEM_IS_V86_MODE(a_pVCpu) (((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_V86_MASK) != 0)
5051
5052	/**
5053	* Check if we're currently executing in long mode.
5054	*
5055	* @returns @c true if it is, @c false if not.
5056	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5057	*/
5058	#define IEM_IS_LONG_MODE(a_pVCpu) (CPUMIsGuestInLongModeEx(IEM_GET_CTX(a_pVCpu)))
5059
5060	/**
5061	* Check if we're currently executing in a 16-bit code segment.
5062	*
5063	* @returns @c true if it is, @c false if not.
5064	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5065	*/
5066	#define IEM_IS_16BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_16BIT)
5067
5068	/**
5069	* Check if we're currently executing in a 32-bit code segment.
5070	*
5071	* @returns @c true if it is, @c false if not.
5072	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5073	*/
5074	#define IEM_IS_32BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_32BIT)
5075
5076	/**
5077	* Check if we're currently executing in a 64-bit code segment.
5078	*
5079	* @returns @c true if it is, @c false if not.
5080	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5081	*/
5082	#define IEM_IS_64BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_64BIT)
5083
5084	/**
5085	* Check if we're currently executing in real mode.
5086	*
5087	* @returns @c true if it is, @c false if not.
5088	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5089	*/
5090	#define IEM_IS_REAL_MODE(a_pVCpu) (!((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_PROT_MASK))
5091
5092	/**
5093	* Gets the current protection level (CPL).
5094	*
5095	* @returns 0..3
5096	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5097	*/
5098	#define IEM_GET_CPL(a_pVCpu) (((a_pVCpu)->iem.s.fExec >> IEM_F_X86_CPL_SHIFT) & IEM_F_X86_CPL_SMASK)
5099
5100	/**
5101	* Sets the current protection level (CPL).
5102	*
5103	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5104	*/
5105	#define IEM_SET_CPL(a_pVCpu, a_uCpl) \
5106	do { (a_pVCpu)->iem.s.fExec = ((a_pVCpu)->iem.s.fExec & ~IEM_F_X86_CPL_MASK) \| ((a_uCpl) << IEM_F_X86_CPL_SHIFT); } while (0)
5107
5108	/**
5109	* Returns a (const) pointer to the CPUMFEATURES for the guest CPU.
5110	* @returns PCCPUMFEATURES
5111	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5112	*/
5113	#define IEM_GET_GUEST_CPU_FEATURES(a_pVCpu) (&((a_pVCpu)->CTX_SUFF(pVM)->cpum.ro.GuestFeatures))
5114
5115	/**
5116	* Returns a (const) pointer to the CPUMFEATURES for the host CPU.
5117	* @returns PCCPUMFEATURES
5118	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5119	*/
5120	#define IEM_GET_HOST_CPU_FEATURES(a_pVCpu) (&g_CpumHostFeatures.s)
5121
5122	/**
5123	* Evaluates to true if we're presenting an Intel CPU to the guest.
5124	*/
5125	#define IEM_IS_GUEST_CPU_INTEL(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL )
5126
5127	/**
5128	* Evaluates to true if we're presenting an AMD CPU to the guest.
5129	*/
5130	#define IEM_IS_GUEST_CPU_AMD(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_AMD \|\| (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_HYGON )
5131
5132	/**
5133	* Check if the address is canonical.
5134	*/
5135	#define IEM_IS_CANONICAL(a_u64Addr) X86_IS_CANONICAL(a_u64Addr)
5136
5137	/** Checks if the ModR/M byte is in register mode or not. */
5138	#define IEM_IS_MODRM_REG_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT) )
5139	/** Checks if the ModR/M byte is in memory mode or not. */
5140	#define IEM_IS_MODRM_MEM_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT) )
5141
5142	/**
5143	* Gets the register (reg) part of a ModR/M encoding, with REX.R added in.
5144	*
5145	* For use during decoding.
5146	*/
5147	#define IEM_GET_MODRM_REG(a_pVCpu, a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| (a_pVCpu)->iem.s.uRexReg )
5148	/**
5149	* Gets the r/m part of a ModR/M encoding as a register index, with REX.B added in.
5150	*
5151	* For use during decoding.
5152	*/
5153	#define IEM_GET_MODRM_RM(a_pVCpu, a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) \| (a_pVCpu)->iem.s.uRexB )
5154
5155	/**
5156	* Gets the register (reg) part of a ModR/M encoding, without REX.R.
5157	*
5158	* For use during decoding.
5159	*/
5160	#define IEM_GET_MODRM_REG_8(a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) )
5161	/**
5162	* Gets the r/m part of a ModR/M encoding as a register index, without REX.B.
5163	*
5164	* For use during decoding.
5165	*/
5166	#define IEM_GET_MODRM_RM_8(a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) )
5167
5168	/**
5169	* Gets the register (reg) part of a ModR/M encoding as an extended 8-bit
5170	* register index, with REX.R added in.
5171	*
5172	* For use during decoding.
5173	*
5174	* @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
5175	*/
5176	#define IEM_GET_MODRM_REG_EX8(a_pVCpu, a_bRm) \
5177	( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
5178	\|\| !((a_bRm) & (4 << X86_MODRM_REG_SHIFT)) /* IEM_GET_MODRM_REG(pVCpu, a_bRm) < 4 */ \
5179	? IEM_GET_MODRM_REG(pVCpu, a_bRm) : (((a_bRm) >> X86_MODRM_REG_SHIFT) & 3) \| 16)
5180	/**
5181	* Gets the r/m part of a ModR/M encoding as an extended 8-bit register index,
5182	* with REX.B added in.
5183	*
5184	* For use during decoding.
5185	*
5186	* @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
5187	*/
5188	#define IEM_GET_MODRM_RM_EX8(a_pVCpu, a_bRm) \
5189	( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
5190	\|\| !((a_bRm) & 4) /* IEM_GET_MODRM_RM(pVCpu, a_bRm) < 4 */ \
5191	? IEM_GET_MODRM_RM(pVCpu, a_bRm) : ((a_bRm) & 3) \| 16)
5192
5193	/**
5194	* Combines the prefix REX and ModR/M byte for passing to
5195	* iemOpHlpCalcRmEffAddrThreadedAddr64().
5196	*
5197	* @returns The ModRM byte but with bit 3 set to REX.B and bit 4 to REX.X.
5198	* The two bits are part of the REG sub-field, which isn't needed in
5199	* iemOpHlpCalcRmEffAddrThreadedAddr64().
5200	*
5201	* For use during decoding/recompiling.
5202	*/
5203	#define IEM_GET_MODRM_EX(a_pVCpu, a_bRm) \
5204	( ((a_bRm) & ~X86_MODRM_REG_MASK) \
5205	\| (uint8_t)( (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X)) >> (25 - 3) ) )
5206	AssertCompile(IEM_OP_PRF_REX_B == RT_BIT_32(25));
5207	AssertCompile(IEM_OP_PRF_REX_X == RT_BIT_32(26));
5208
5209	/**
5210	* Gets the effective VEX.VVVV value.
5211	*
5212	* The 4th bit is ignored if not 64-bit code.
5213	* @returns effective V-register value.
5214	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5215	*/
5216	#define IEM_GET_EFFECTIVE_VVVV(a_pVCpu) \
5217	(IEM_IS_64BIT_CODE(a_pVCpu) ? (a_pVCpu)->iem.s.uVex3rdReg : (a_pVCpu)->iem.s.uVex3rdReg & 7)
5218
5219
5220	/**
5221	* Gets the register (reg) part of a the special 4th register byte used by
5222	* vblendvps and vblendvpd.
5223	*
5224	* For use during decoding.
5225	*/
5226	#define IEM_GET_IMM8_REG(a_pVCpu, a_bRegImm8) \
5227	(IEM_IS_64BIT_CODE(a_pVCpu) ? (a_bRegImm8) >> 4 : ((a_bRegImm8) >> 4) & 7)
5228
5229
5230	/**
5231	* Checks if we're executing inside an AMD-V or VT-x guest.
5232	*/
5233	#if defined(VBOX_WITH_NESTED_HWVIRT_VMX) \|\| defined(VBOX_WITH_NESTED_HWVIRT_SVM)
5234	# define IEM_IS_IN_GUEST(a_pVCpu) RT_BOOL((a_pVCpu)->iem.s.fExec & IEM_F_X86_CTX_IN_GUEST)
5235	#else
5236	# define IEM_IS_IN_GUEST(a_pVCpu) false
5237	#endif
5238
5239
5240	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5241
5242	/**
5243	* Check if the guest has entered VMX root operation.
5244	*/
5245	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxRootMode(IEM_GET_CTX(a_pVCpu)))
5246
5247	/**
5248	* Check if the guest has entered VMX non-root operation.
5249	*/
5250	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) ( ((a_pVCpu)->iem.s.fExec & (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST)) \
5251	== (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST) )
5252
5253	/**
5254	* Check if the nested-guest has the given Pin-based VM-execution control set.
5255	*/
5256	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_PinCtl) (CPUMIsGuestVmxPinCtlsSet(IEM_GET_CTX(a_pVCpu), (a_PinCtl)))
5257
5258	/**
5259	* Check if the nested-guest has the given Processor-based VM-execution control set.
5260	*/
5261	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_ProcCtl) (CPUMIsGuestVmxProcCtlsSet(IEM_GET_CTX(a_pVCpu), (a_ProcCtl)))
5262
5263	/**
5264	* Check if the nested-guest has the given Secondary Processor-based VM-execution
5265	* control set.
5266	*/
5267	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_ProcCtl2) (CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(a_pVCpu), (a_ProcCtl2)))
5268
5269	/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
5270	# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
5271
5272	/** Whether a shadow VMCS is present for the given VCPU. */
5273	# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
5274
5275	/** Gets the VMXON region pointer. */
5276	# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
5277
5278	/** Gets the guest-physical address of the current VMCS for the given VCPU. */
5279	# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
5280
5281	/** Whether a current VMCS is present for the given VCPU. */
5282	# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
5283
5284	/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
5285	# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
5286	do \
5287	{ \
5288	Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
5289	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
5290	} while (0)
5291
5292	/** Clears any current VMCS for the given VCPU. */
5293	# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
5294	do \
5295	{ \
5296	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
5297	} while (0)
5298
5299	/**
5300	* Invokes the VMX VM-exit handler for an instruction intercept.
5301	*/
5302	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) \
5303	do { return iemVmxVmexitInstr((a_pVCpu), (a_uExitReason), (a_cbInstr)); } while (0)
5304
5305	/**
5306	* Invokes the VMX VM-exit handler for an instruction intercept where the
5307	* instruction provides additional VM-exit information.
5308	*/
5309	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) \
5310	do { return iemVmxVmexitInstrNeedsInfo((a_pVCpu), (a_uExitReason), (a_uInstrId), (a_cbInstr)); } while (0)
5311
5312	/**
5313	* Invokes the VMX VM-exit handler for a task switch.
5314	*/
5315	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) \
5316	do { return iemVmxVmexitTaskSwitch((a_pVCpu), (a_enmTaskSwitch), (a_SelNewTss), (a_cbInstr)); } while (0)
5317
5318	/**
5319	* Invokes the VMX VM-exit handler for MWAIT.
5320	*/
5321	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) \
5322	do { return iemVmxVmexitInstrMwait((a_pVCpu), (a_fMonitorArmed), (a_cbInstr)); } while (0)
5323
5324	/**
5325	* Invokes the VMX VM-exit handler for EPT faults.
5326	*/
5327	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) \
5328	do { return iemVmxVmexitEpt(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr); } while (0)
5329
5330	/**
5331	* Invokes the VMX VM-exit handler.
5332	*/
5333	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) \
5334	do { return iemVmxVmexit((a_pVCpu), (a_uExitReason), (a_uExitQual)); } while (0)
5335
5336	#else
5337	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (false)
5338	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (false)
5339	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_cbInstr) (false)
5340	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_cbInstr) (false)
5341	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_cbInstr) (false)
5342	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5343	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5344	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5345	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5346	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5347	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) do { return VERR_VMX_IPE_1; } while (0)
5348
5349	#endif
5350
5351	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5352	/**
5353	* Checks if we're executing a guest using AMD-V.
5354	*/
5355	# define IEM_SVM_IS_IN_GUEST(a_pVCpu) ( (a_pVCpu->iem.s.fExec & (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST)) \
5356	== (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST))
5357	/**
5358	* Check if an SVM control/instruction intercept is set.
5359	*/
5360	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) \
5361	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmCtrlInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_Intercept)))
5362
5363	/**
5364	* Check if an SVM read CRx intercept is set.
5365	*/
5366	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
5367	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
5368
5369	/**
5370	* Check if an SVM write CRx intercept is set.
5371	*/
5372	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
5373	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
5374
5375	/**
5376	* Check if an SVM read DRx intercept is set.
5377	*/
5378	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
5379	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
5380
5381	/**
5382	* Check if an SVM write DRx intercept is set.
5383	*/
5384	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
5385	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
5386
5387	/**
5388	* Check if an SVM exception intercept is set.
5389	*/
5390	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) \
5391	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmXcptInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uVector)))
5392
5393	/**
5394	* Invokes the SVM \#VMEXIT handler for the nested-guest.
5395	*/
5396	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
5397	do { return iemSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2)); } while (0)
5398
5399	/**
5400	* Invokes the 'MOV CRx' SVM \#VMEXIT handler after constructing the
5401	* corresponding decode assist information.
5402	*/
5403	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) \
5404	do \
5405	{ \
5406	uint64_t uExitInfo1; \
5407	if ( IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmDecodeAssists \
5408	&& (a_enmAccessCrX) == IEMACCESSCRX_MOV_CRX) \
5409	uExitInfo1 = SVM_EXIT1_MOV_CRX_MASK \| ((a_iGReg) & 7); \
5410	else \
5411	uExitInfo1 = 0; \
5412	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, uExitInfo1, 0); \
5413	} while (0)
5414
5415	/** Check and handles SVM nested-guest instruction intercept and updates
5416	* NRIP if needed.
5417	*/
5418	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
5419	do \
5420	{ \
5421	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept)) \
5422	{ \
5423	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
5424	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2); \
5425	} \
5426	} while (0)
5427
5428	/** Checks and handles SVM nested-guest CR0 read intercept. */
5429	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
5430	do \
5431	{ \
5432	if (!IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, 0)) \
5433	{ /* probably likely */ } \
5434	else \
5435	{ \
5436	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
5437	IEM_SVM_VMEXIT_RET(a_pVCpu, SVM_EXIT_READ_CR0, a_uExitInfo1, a_uExitInfo2); \
5438	} \
5439	} while (0)
5440
5441	/**
5442	* Updates the NextRIP (NRI) field in the nested-guest VMCB.
5443	*/
5444	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) \
5445	do { \
5446	if (IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmNextRipSave) \
5447	CPUMGuestSvmUpdateNRip(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_cbInstr)); \
5448	} while (0)
5449
5450	#else
5451	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) (false)
5452	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
5453	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
5454	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
5455	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
5456	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) (false)
5457	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { return VERR_SVM_IPE_1; } while (0)
5458	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) do { return VERR_SVM_IPE_1; } while (0)
5459	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, \
5460	a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
5461	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
5462	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) do { } while (0)
5463
5464	#endif
5465
5466	/** @} */
5467
5468	uint32_t iemCalcExecDbgFlagsSlow(PVMCPUCC pVCpu);
5469	VBOXSTRICTRC iemExecInjectPendingTrap(PVMCPUCC pVCpu);
5470
5471
5472	/**
5473	* Selector descriptor table entry as fetched by iemMemFetchSelDesc.
5474	*/
5475	typedef union IEMSELDESC
5476	{
5477	/** The legacy view. */
5478	X86DESC Legacy;
5479	/** The long mode view. */
5480	X86DESC64 Long;
5481	} IEMSELDESC;
5482	/** Pointer to a selector descriptor table entry. */
5483	typedef IEMSELDESC *PIEMSELDESC;
5484
5485	/** @name Raising Exceptions.
5486	* @{ */
5487	VBOXSTRICTRC iemTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, uint32_t uNextEip, uint32_t fFlags,
5488	uint16_t uErr, uint64_t uCr2, RTSEL SelTSS, PIEMSELDESC pNewDescTSS) RT_NOEXCEPT;
5489
5490	VBOXSTRICTRC iemRaiseXcptOrInt(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags,
5491	uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
5492	#ifdef IEM_WITH_SETJMP
5493	DECL_NO_RETURN(void) iemRaiseXcptOrIntJmp(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector,
5494	uint32_t fFlags, uint16_t uErr, uint64_t uCr2) IEM_NOEXCEPT_MAY_LONGJMP;
5495	#endif
5496	VBOXSTRICTRC iemRaiseDivideError(PVMCPUCC pVCpu) RT_NOEXCEPT;
5497	#ifdef IEM_WITH_SETJMP
5498	DECL_NO_RETURN(void) iemRaiseDivideErrorJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5499	#endif
5500	VBOXSTRICTRC iemRaiseDebugException(PVMCPUCC pVCpu) RT_NOEXCEPT;
5501	VBOXSTRICTRC iemRaiseBoundRangeExceeded(PVMCPUCC pVCpu) RT_NOEXCEPT;
5502	VBOXSTRICTRC iemRaiseUndefinedOpcode(PVMCPUCC pVCpu) RT_NOEXCEPT;
5503	#ifdef IEM_WITH_SETJMP
5504	DECL_NO_RETURN(void) iemRaiseUndefinedOpcodeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5505	#endif
5506	VBOXSTRICTRC iemRaiseDeviceNotAvailable(PVMCPUCC pVCpu) RT_NOEXCEPT;
5507	#ifdef IEM_WITH_SETJMP
5508	DECL_NO_RETURN(void) iemRaiseDeviceNotAvailableJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5509	#endif
5510	VBOXSTRICTRC iemRaiseTaskSwitchFaultWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5511	VBOXSTRICTRC iemRaiseTaskSwitchFaultCurrentTSS(PVMCPUCC pVCpu) RT_NOEXCEPT;
5512	VBOXSTRICTRC iemRaiseTaskSwitchFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
5513	VBOXSTRICTRC iemRaiseTaskSwitchFaultBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5514	/VBOXSTRICTRC iemRaiseSelectorNotPresent(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;/
5515	VBOXSTRICTRC iemRaiseSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5516	VBOXSTRICTRC iemRaiseSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5517	VBOXSTRICTRC iemRaiseStackSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5518	VBOXSTRICTRC iemRaiseStackSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5519	VBOXSTRICTRC iemRaiseGeneralProtectionFault(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5520	VBOXSTRICTRC iemRaiseGeneralProtectionFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
5521	#ifdef IEM_WITH_SETJMP
5522	DECL_NO_RETURN(void) iemRaiseGeneralProtectionFault0Jmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5523	#endif
5524	VBOXSTRICTRC iemRaiseGeneralProtectionFaultBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
5525	VBOXSTRICTRC iemRaiseNotCanonical(PVMCPUCC pVCpu) RT_NOEXCEPT;
5526	VBOXSTRICTRC iemRaiseSelectorBounds(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
5527	#ifdef IEM_WITH_SETJMP
5528	DECL_NO_RETURN(void) iemRaiseSelectorBoundsJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
5529	#endif
5530	VBOXSTRICTRC iemRaiseSelectorBoundsBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
5531	#ifdef IEM_WITH_SETJMP
5532	DECL_NO_RETURN(void) iemRaiseSelectorBoundsBySelectorJmp(PVMCPUCC pVCpu, RTSEL Sel) IEM_NOEXCEPT_MAY_LONGJMP;
5533	#endif
5534	VBOXSTRICTRC iemRaiseSelectorInvalidAccess(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
5535	#ifdef IEM_WITH_SETJMP
5536	DECL_NO_RETURN(void) iemRaiseSelectorInvalidAccessJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
5537	#endif
5538	VBOXSTRICTRC iemRaisePageFault(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) RT_NOEXCEPT;
5539	#ifdef IEM_WITH_SETJMP
5540	DECL_NO_RETURN(void) iemRaisePageFaultJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) IEM_NOEXCEPT_MAY_LONGJMP;
5541	#endif
5542	VBOXSTRICTRC iemRaiseMathFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
5543	#ifdef IEM_WITH_SETJMP
5544	DECL_NO_RETURN(void) iemRaiseMathFaultJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5545	#endif
5546	VBOXSTRICTRC iemRaiseAlignmentCheckException(PVMCPUCC pVCpu) RT_NOEXCEPT;
5547	#ifdef IEM_WITH_SETJMP
5548	DECL_NO_RETURN(void) iemRaiseAlignmentCheckExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5549	#endif
5550	VBOXSTRICTRC iemRaiseSimdFpException(PVMCPUCC pVCpu) RT_NOEXCEPT;
5551	#ifdef IEM_WITH_SETJMP
5552	DECL_NO_RETURN(void) iemRaiseSimdFpExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5553	#endif
5554
5555	void iemLogSyscallRealModeInt(PVMCPUCC pVCpu, uint8_t u8Vector, uint8_t cbInstr);
5556	void iemLogSyscallProtModeInt(PVMCPUCC pVCpu, uint8_t u8Vector, uint8_t cbInstr);
5557
5558	IEM_CIMPL_DEF_0(iemCImplRaiseDivideError);
5559	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidLockPrefix);
5560	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidOpcode);
5561
5562	/**
5563	* Macro for calling iemCImplRaiseDivideError().
5564	*
5565	* This is for things that will _always_ decode to an \#DE, taking the
5566	* recompiler into consideration and everything.
5567	*
5568	* @return Strict VBox status code.
5569	*/
5570	#define IEMOP_RAISE_DIVIDE_ERROR_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseDivideError)
5571
5572	/**
5573	* Macro for calling iemCImplRaiseInvalidLockPrefix().
5574	*
5575	* This is for things that will _always_ decode to an \#UD, taking the
5576	* recompiler into consideration and everything.
5577	*
5578	* @return Strict VBox status code.
5579	*/
5580	#define IEMOP_RAISE_INVALID_LOCK_PREFIX_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidLockPrefix)
5581
5582	/**
5583	* Macro for calling iemCImplRaiseInvalidOpcode() for decode/static \#UDs.
5584	*
5585	* This is for things that will _always_ decode to an \#UD, taking the
5586	* recompiler into consideration and everything.
5587	*
5588	* @return Strict VBox status code.
5589	*/
5590	#define IEMOP_RAISE_INVALID_OPCODE_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidOpcode)
5591
5592	/**
5593	* Macro for calling iemCImplRaiseInvalidOpcode() for runtime-style \#UDs.
5594	*
5595	* Using this macro means you've got _buggy_ _code_ and are doing things that
5596	* belongs exclusively in IEMAllCImpl.cpp during decoding.
5597	*
5598	* @return Strict VBox status code.
5599	* @see IEMOP_RAISE_INVALID_OPCODE_RET
5600	*/
5601	#define IEMOP_RAISE_INVALID_OPCODE_RUNTIME_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidOpcode)
5602
5603	/** @} */
5604
5605	/** @name Register Access.
5606	* @{ */
5607	VBOXSTRICTRC iemRegRipRelativeJumpS8AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int8_t offNextInstr,
5608	IEMMODE enmEffOpSize) RT_NOEXCEPT;
5609	VBOXSTRICTRC iemRegRipRelativeJumpS16AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int16_t offNextInstr) RT_NOEXCEPT;
5610	VBOXSTRICTRC iemRegRipRelativeJumpS32AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int32_t offNextInstr,
5611	IEMMODE enmEffOpSize) RT_NOEXCEPT;
5612	/** @} */
5613
5614	/** @name FPU access and helpers.
5615	* @{ */
5616	void iemFpuPushResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
5617	void iemFpuPushResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5618	void iemFpuPushResultTwo(PVMCPUCC pVCpu, PIEMFPURESULTTWO pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
5619	void iemFpuStoreResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
5620	void iemFpuStoreResultThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
5621	void iemFpuStoreResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
5622	uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5623	void iemFpuStoreResultWithMemOpThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
5624	uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5625	void iemFpuUpdateOpcodeAndIp(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5626	void iemFpuUpdateFSW(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
5627	void iemFpuUpdateFSWThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
5628	void iemFpuUpdateFSWWithMemOp(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5629	void iemFpuUpdateFSWThenPopPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
5630	void iemFpuUpdateFSWWithMemOpThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5631	void iemFpuStackUnderflow(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
5632	void iemFpuStackUnderflowWithMemOp(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5633	void iemFpuStackUnderflowThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
5634	void iemFpuStackUnderflowWithMemOpThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5635	void iemFpuStackUnderflowThenPopPop(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5636	void iemFpuStackPushUnderflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5637	void iemFpuStackPushUnderflowTwo(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5638	void iemFpuStackPushOverflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5639	void iemFpuStackPushOverflowWithMemOp(PVMCPUCC pVCpu, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5640	/** @} */
5641
5642	/** @name SSE+AVX SIMD access and helpers.
5643	* @{ */
5644	void iemSseUpdateMxcsr(PVMCPUCC pVCpu, uint32_t fMxcsr) RT_NOEXCEPT;
5645	/** @} */
5646
5647	/** @name Memory access.
5648	* @{ */
5649
5650	/** Report a \#GP instead of \#AC and do not restrict to ring-3 */
5651	#define IEM_MEMMAP_F_ALIGN_GP RT_BIT_32(16)
5652	/** SSE access that should report a \#GP instead of \#AC, unless MXCSR.MM=1
5653	* when it works like normal \#AC. Always used with IEM_MEMMAP_F_ALIGN_GP. */
5654	#define IEM_MEMMAP_F_ALIGN_SSE RT_BIT_32(17)
5655	/** If \#AC is applicable, raise it. Always used with IEM_MEMMAP_F_ALIGN_GP.
5656	* Users include FXSAVE & FXRSTOR. */
5657	#define IEM_MEMMAP_F_ALIGN_GP_OR_AC RT_BIT_32(18)
5658
5659	VBOXSTRICTRC iemMemMap(PVMCPUCC pVCpu, void *ppvMem, uint8_t pbUnmapInfo, size_t cbMem, uint8_t iSegReg, RTGCPTR GCPtrMem,
5660	uint32_t fAccess, uint32_t uAlignCtl) RT_NOEXCEPT;
5661	VBOXSTRICTRC iemMemCommitAndUnmap(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5662	#ifndef IN_RING3
5663	VBOXSTRICTRC iemMemCommitAndUnmapPostponeTroubleToR3(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5664	#endif
5665	void iemMemRollbackAndUnmap(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5666	void iemMemRollback(PVMCPUCC pVCpu) RT_NOEXCEPT;
5667	VBOXSTRICTRC iemMemApplySegment(PVMCPUCC pVCpu, uint32_t fAccess, uint8_t iSegReg, size_t cbMem, PRTGCPTR pGCPtrMem) RT_NOEXCEPT;
5668	VBOXSTRICTRC iemMemMarkSelDescAccessed(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5669	VBOXSTRICTRC iemMemPageTranslateAndCheckAccess(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t cbAccess, uint32_t fAccess, PRTGCPHYS pGCPhysMem) RT_NOEXCEPT;
5670
5671	void iemOpcodeFlushLight(PVMCPUCC pVCpu, uint8_t cbInstr);
5672	void iemOpcodeFlushHeavy(PVMCPUCC pVCpu, uint8_t cbInstr);
5673	#ifdef IEM_WITH_CODE_TLB
5674	void iemOpcodeFetchBytesJmp(PVMCPUCC pVCpu, size_t cbDst, void *pvDst) IEM_NOEXCEPT_MAY_LONGJMP;
5675	#else
5676	VBOXSTRICTRC iemOpcodeFetchMoreBytes(PVMCPUCC pVCpu, size_t cbMin) RT_NOEXCEPT;
5677	#endif
5678	#ifdef IEM_WITH_SETJMP
5679	uint8_t iemOpcodeGetNextU8SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5680	uint16_t iemOpcodeGetNextU16SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5681	uint32_t iemOpcodeGetNextU32SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5682	uint64_t iemOpcodeGetNextU64SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5683	#else
5684	VBOXSTRICTRC iemOpcodeGetNextU8Slow(PVMCPUCC pVCpu, uint8_t *pb) RT_NOEXCEPT;
5685	VBOXSTRICTRC iemOpcodeGetNextS8SxU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
5686	VBOXSTRICTRC iemOpcodeGetNextS8SxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
5687	VBOXSTRICTRC iemOpcodeGetNextS8SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5688	VBOXSTRICTRC iemOpcodeGetNextU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
5689	VBOXSTRICTRC iemOpcodeGetNextU16ZxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
5690	VBOXSTRICTRC iemOpcodeGetNextU16ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5691	VBOXSTRICTRC iemOpcodeGetNextU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
5692	VBOXSTRICTRC iemOpcodeGetNextU32ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5693	VBOXSTRICTRC iemOpcodeGetNextS32SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5694	VBOXSTRICTRC iemOpcodeGetNextU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5695	#endif
5696
5697	VBOXSTRICTRC iemMemFetchDataU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5698	VBOXSTRICTRC iemMemFetchDataU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5699	VBOXSTRICTRC iemMemFetchDataU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5700	VBOXSTRICTRC iemMemFetchDataU32_ZX_U64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5701	VBOXSTRICTRC iemMemFetchDataU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5702	VBOXSTRICTRC iemMemFetchDataU64AlignedU128(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5703	VBOXSTRICTRC iemMemFetchDataR80(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5704	VBOXSTRICTRC iemMemFetchDataD80(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5705	VBOXSTRICTRC iemMemFetchDataU128(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5706	VBOXSTRICTRC iemMemFetchDataU128NoAc(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5707	VBOXSTRICTRC iemMemFetchDataU128AlignedSse(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5708	VBOXSTRICTRC iemMemFetchDataU256(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5709	VBOXSTRICTRC iemMemFetchDataU256NoAc(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5710	VBOXSTRICTRC iemMemFetchDataU256AlignedAvx(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5711	VBOXSTRICTRC iemMemFetchDataXdtr(PVMCPUCC pVCpu, uint16_t *pcbLimit, PRTGCPTR pGCPtrBase, uint8_t iSegReg,
5712	RTGCPTR GCPtrMem, IEMMODE enmOpSize) RT_NOEXCEPT;
5713	#ifdef IEM_WITH_SETJMP
5714	uint8_t iemMemFetchDataU8SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5715	uint16_t iemMemFetchDataU16SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5716	uint32_t iemMemFetchDataU32SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5717	uint32_t iemMemFlatFetchDataU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5718	uint64_t iemMemFetchDataU64SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5719	uint64_t iemMemFetchDataU64AlignedU128SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5720	void iemMemFetchDataR80SafeJmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5721	void iemMemFetchDataD80SafeJmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5722	void iemMemFetchDataU128SafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5723	void iemMemFetchDataU128NoAcSafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5724	void iemMemFetchDataU128AlignedSseSafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5725	void iemMemFetchDataU256SafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5726	void iemMemFetchDataU256NoAcSafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5727	void iemMemFetchDataU256AlignedAvxSafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5728	# if 0 /* these are inlined now */
5729	uint8_t iemMemFetchDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5730	uint16_t iemMemFetchDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5731	uint32_t iemMemFetchDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5732	uint32_t iemMemFlatFetchDataU32Jmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5733	uint64_t iemMemFetchDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5734	uint64_t iemMemFetchDataU64AlignedU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5735	void iemMemFetchDataR80Jmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5736	void iemMemFetchDataD80Jmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5737	void iemMemFetchDataU128Jmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5738	void iemMemFetchDataU128NoAcJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5739	void iemMemFetchDataU128AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5740	void iemMemFetchDataU256NoAcJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5741	void iemMemFetchDataU256AlignedAvxJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5742	# endif
5743	void iemMemFetchDataU256Jmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5744	#endif
5745
5746	VBOXSTRICTRC iemMemFetchSysU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5747	VBOXSTRICTRC iemMemFetchSysU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5748	VBOXSTRICTRC iemMemFetchSysU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5749	VBOXSTRICTRC iemMemFetchSysU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5750	VBOXSTRICTRC iemMemFetchSelDesc(PVMCPUCC pVCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt) RT_NOEXCEPT;
5751
5752	VBOXSTRICTRC iemMemStoreDataU8(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) RT_NOEXCEPT;
5753	VBOXSTRICTRC iemMemStoreDataU16(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) RT_NOEXCEPT;
5754	VBOXSTRICTRC iemMemStoreDataU32(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) RT_NOEXCEPT;
5755	VBOXSTRICTRC iemMemStoreDataU64(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) RT_NOEXCEPT;
5756	VBOXSTRICTRC iemMemStoreDataU128(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
5757	VBOXSTRICTRC iemMemStoreDataU128NoAc(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
5758	VBOXSTRICTRC iemMemStoreDataU128AlignedSse(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
5759	VBOXSTRICTRC iemMemStoreDataU256(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
5760	VBOXSTRICTRC iemMemStoreDataU256NoAc(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
5761	VBOXSTRICTRC iemMemStoreDataU256AlignedAvx(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
5762	VBOXSTRICTRC iemMemStoreDataXdtr(PVMCPUCC pVCpu, uint16_t cbLimit, RTGCPTR GCPtrBase, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5763	#ifdef IEM_WITH_SETJMP
5764	void iemMemStoreDataU8SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
5765	void iemMemStoreDataU16SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
5766	void iemMemStoreDataU32SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
5767	void iemMemStoreDataU64SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
5768	void iemMemStoreDataU128SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5769	void iemMemStoreDataU128NoAcSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT128U pu128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5770	void iemMemStoreDataU128AlignedSseSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT128U pu128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5771	void iemMemStoreDataU256SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5772	void iemMemStoreDataU256NoAcSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5773	void iemMemStoreDataU256AlignedAvxSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5774	void iemMemStoreDataR80SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTFLOAT80U pr80Value) IEM_NOEXCEPT_MAY_LONGJMP;
5775	void iemMemStoreDataD80SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTPBCD80U pd80Value) IEM_NOEXCEPT_MAY_LONGJMP;
5776	#if 0
5777	void iemMemStoreDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
5778	void iemMemStoreDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
5779	void iemMemStoreDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
5780	void iemMemStoreDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
5781	void iemMemStoreDataU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5782	void iemMemStoreDataNoAcU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5783	void iemMemStoreDataU256NoAcJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5784	void iemMemStoreDataU256AlignedAvxJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5785	#endif
5786	void iemMemStoreDataU128AlignedSseJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5787	void iemMemStoreDataU256Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5788	#endif
5789
5790	#ifdef IEM_WITH_SETJMP
5791	uint8_t iemMemMapDataU8RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5792	uint8_t iemMemMapDataU8AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5793	uint8_t iemMemMapDataU8WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5794	uint8_t const iemMemMapDataU8RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5795	uint16_t iemMemMapDataU16RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5796	uint16_t iemMemMapDataU16AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5797	uint16_t iemMemMapDataU16WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5798	uint16_t const iemMemMapDataU16RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5799	uint32_t iemMemMapDataU32RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5800	uint32_t iemMemMapDataU32AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5801	uint32_t iemMemMapDataU32WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5802	uint32_t const iemMemMapDataU32RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5803	uint64_t iemMemMapDataU64RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5804	uint64_t iemMemMapDataU64AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5805	uint64_t iemMemMapDataU64WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5806	uint64_t const iemMemMapDataU64RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5807	PRTFLOAT80U iemMemMapDataR80RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5808	PRTFLOAT80U iemMemMapDataR80WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5809	PCRTFLOAT80U iemMemMapDataR80RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5810	PRTPBCD80U iemMemMapDataD80RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5811	PRTPBCD80U iemMemMapDataD80WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5812	PCRTPBCD80U iemMemMapDataD80RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5813	PRTUINT128U iemMemMapDataU128RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5814	PRTUINT128U iemMemMapDataU128AtSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5815	PRTUINT128U iemMemMapDataU128WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5816	PCRTUINT128U iemMemMapDataU128RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5817
5818	void iemMemCommitAndUnmapJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5819	void iemMemCommitAndUnmapRwSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5820	void iemMemCommitAndUnmapAtSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5821	void iemMemCommitAndUnmapWoSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5822	void iemMemCommitAndUnmapRoSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5823	void iemMemRollbackAndUnmapWoSafe(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5824	#endif
5825
5826	VBOXSTRICTRC iemMemStackPushBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
5827	void *ppvMem, uint8_t pbUnmapInfo, uint64_t *puNewRsp) RT_NOEXCEPT;
5828	VBOXSTRICTRC iemMemStackPushCommitSpecial(PVMCPUCC pVCpu, uint8_t bUnmapInfo, uint64_t uNewRsp) RT_NOEXCEPT;
5829	VBOXSTRICTRC iemMemStackPushU16(PVMCPUCC pVCpu, uint16_t u16Value) RT_NOEXCEPT;
5830	VBOXSTRICTRC iemMemStackPushU32(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
5831	VBOXSTRICTRC iemMemStackPushU64(PVMCPUCC pVCpu, uint64_t u64Value) RT_NOEXCEPT;
5832	VBOXSTRICTRC iemMemStackPushU16Ex(PVMCPUCC pVCpu, uint16_t u16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5833	VBOXSTRICTRC iemMemStackPushU32Ex(PVMCPUCC pVCpu, uint32_t u32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5834	VBOXSTRICTRC iemMemStackPushU64Ex(PVMCPUCC pVCpu, uint64_t u64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5835	VBOXSTRICTRC iemMemStackPushU32SReg(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
5836	VBOXSTRICTRC iemMemStackPopBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
5837	void const *ppvMem, uint8_t pbUnmapInfo, uint64_t *puNewRsp) RT_NOEXCEPT;
5838	VBOXSTRICTRC iemMemStackPopContinueSpecial(PVMCPUCC pVCpu, size_t off, size_t cbMem,
5839	void const *ppvMem, uint8_t pbUnmapInfo, uint64_t uCurNewRsp) RT_NOEXCEPT;
5840	VBOXSTRICTRC iemMemStackPopDoneSpecial(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5841	VBOXSTRICTRC iemMemStackPopU16(PVMCPUCC pVCpu, uint16_t *pu16Value) RT_NOEXCEPT;
5842	VBOXSTRICTRC iemMemStackPopU32(PVMCPUCC pVCpu, uint32_t *pu32Value) RT_NOEXCEPT;
5843	VBOXSTRICTRC iemMemStackPopU64(PVMCPUCC pVCpu, uint64_t *pu64Value) RT_NOEXCEPT;
5844	VBOXSTRICTRC iemMemStackPopU16Ex(PVMCPUCC pVCpu, uint16_t *pu16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5845	VBOXSTRICTRC iemMemStackPopU32Ex(PVMCPUCC pVCpu, uint32_t *pu32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5846	VBOXSTRICTRC iemMemStackPopU64Ex(PVMCPUCC pVCpu, uint64_t *pu64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5847
5848	#ifdef IEM_WITH_SETJMP
5849	void iemMemStackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5850	void iemMemStackPushU32SafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5851	void iemMemStackPushU32SRegSafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5852	void iemMemStackPushU64SafeJmp(PVMCPUCC pVCpu, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5853	void iemMemStackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5854	void iemMemStackPopGRegU32SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5855	void iemMemStackPopGRegU64SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5856
5857	void iemMemFlat32StackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5858	void iemMemFlat32StackPushU32SafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5859	void iemMemFlat32StackPushU32SRegSafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5860	void iemMemFlat32StackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5861	void iemMemFlat32StackPopGRegU32SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5862
5863	void iemMemFlat64StackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5864	void iemMemFlat64StackPushU64SafeJmp(PVMCPUCC pVCpu, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5865	void iemMemFlat64StackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5866	void iemMemFlat64StackPopGRegU64SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5867
5868	void iemMemStoreStackU16SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5869	void iemMemStoreStackU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5870	void iemMemStoreStackU32SRegSafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5871	void iemMemStoreStackU64SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5872
5873	uint16_t iemMemFetchStackU16SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5874	uint32_t iemMemFetchStackU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5875	uint64_t iemMemFetchStackU64SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5876
5877	#endif
5878
5879	/** @} */
5880
5881	/** @name IEMAllCImpl.cpp
5882	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/'
5883	* @{ */
5884	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem16, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5885	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem32, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5886	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem64, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5887	IEM_CIMPL_PROTO_0(iemCImpl_popa_16);
5888	IEM_CIMPL_PROTO_0(iemCImpl_popa_32);
5889	IEM_CIMPL_PROTO_0(iemCImpl_pusha_16);
5890	IEM_CIMPL_PROTO_0(iemCImpl_pusha_32);
5891	IEM_CIMPL_PROTO_1(iemCImpl_pushf, IEMMODE, enmEffOpSize);
5892	IEM_CIMPL_PROTO_1(iemCImpl_popf, IEMMODE, enmEffOpSize);
5893	IEM_CIMPL_PROTO_3(iemCImpl_FarJmp, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
5894	IEM_CIMPL_PROTO_3(iemCImpl_callf, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
5895	typedef IEM_CIMPL_DECL_TYPE_3(FNIEMCIMPLFARBRANCH, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
5896	typedef FNIEMCIMPLFARBRANCH *PFNIEMCIMPLFARBRANCH;
5897	IEM_CIMPL_PROTO_2(iemCImpl_retf, IEMMODE, enmEffOpSize, uint16_t, cbPop);
5898	IEM_CIMPL_PROTO_3(iemCImpl_enter, IEMMODE, enmEffOpSize, uint16_t, cbFrame, uint8_t, cParameters);
5899	IEM_CIMPL_PROTO_1(iemCImpl_leave, IEMMODE, enmEffOpSize);
5900	IEM_CIMPL_PROTO_2(iemCImpl_int, uint8_t, u8Int, IEMINT, enmInt);
5901	IEM_CIMPL_PROTO_1(iemCImpl_iret_real_v8086, IEMMODE, enmEffOpSize);
5902	IEM_CIMPL_PROTO_4(iemCImpl_iret_prot_v8086, uint32_t, uNewEip, uint16_t, uNewCs, uint32_t, uNewFlags, uint64_t, uNewRsp);
5903	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot_NestedTask, IEMMODE, enmEffOpSize);
5904	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot, IEMMODE, enmEffOpSize);
5905	IEM_CIMPL_PROTO_1(iemCImpl_iret_64bit, IEMMODE, enmEffOpSize);
5906	IEM_CIMPL_PROTO_1(iemCImpl_iret, IEMMODE, enmEffOpSize);
5907	IEM_CIMPL_PROTO_0(iemCImpl_loadall286);
5908	IEM_CIMPL_PROTO_0(iemCImpl_syscall);
5909	IEM_CIMPL_PROTO_1(iemCImpl_sysret, IEMMODE, enmEffOpSize);
5910	IEM_CIMPL_PROTO_0(iemCImpl_sysenter);
5911	IEM_CIMPL_PROTO_1(iemCImpl_sysexit, IEMMODE, enmEffOpSize);
5912	IEM_CIMPL_PROTO_2(iemCImpl_LoadSReg, uint8_t, iSegReg, uint16_t, uSel);
5913	IEM_CIMPL_PROTO_2(iemCImpl_load_SReg, uint8_t, iSegReg, uint16_t, uSel);
5914	IEM_CIMPL_PROTO_2(iemCImpl_pop_Sreg, uint8_t, iSegReg, IEMMODE, enmEffOpSize);
5915	IEM_CIMPL_PROTO_5(iemCImpl_load_SReg_Greg, uint16_t, uSel, uint64_t, offSeg, uint8_t, iSegReg, uint8_t, iGReg, IEMMODE, enmEffOpSize);
5916	IEM_CIMPL_PROTO_2(iemCImpl_VerX, uint16_t, uSel, bool, fWrite);
5917	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u64, uint64_t *, pu64Dst, uint16_t, uSel, bool, fIsLar);
5918	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u16, uint16_t *, pu16Dst, uint16_t, uSel, bool, fIsLar);
5919	IEM_CIMPL_PROTO_3(iemCImpl_lgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
5920	IEM_CIMPL_PROTO_2(iemCImpl_sgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5921	IEM_CIMPL_PROTO_3(iemCImpl_lidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
5922	IEM_CIMPL_PROTO_2(iemCImpl_sidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5923	IEM_CIMPL_PROTO_1(iemCImpl_lldt, uint16_t, uNewLdt);
5924	IEM_CIMPL_PROTO_2(iemCImpl_sldt_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
5925	IEM_CIMPL_PROTO_2(iemCImpl_sldt_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5926	IEM_CIMPL_PROTO_1(iemCImpl_ltr, uint16_t, uNewTr);
5927	IEM_CIMPL_PROTO_2(iemCImpl_str_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
5928	IEM_CIMPL_PROTO_2(iemCImpl_str_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5929	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Cd, uint8_t, iGReg, uint8_t, iCrReg);
5930	IEM_CIMPL_PROTO_2(iemCImpl_smsw_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
5931	IEM_CIMPL_PROTO_2(iemCImpl_smsw_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5932	IEM_CIMPL_PROTO_4(iemCImpl_load_CrX, uint8_t, iCrReg, uint64_t, uNewCrX, IEMACCESSCRX, enmAccessCrX, uint8_t, iGReg);
5933	IEM_CIMPL_PROTO_2(iemCImpl_mov_Cd_Rd, uint8_t, iCrReg, uint8_t, iGReg);
5934	IEM_CIMPL_PROTO_2(iemCImpl_lmsw, uint16_t, u16NewMsw, RTGCPTR, GCPtrEffDst);
5935	IEM_CIMPL_PROTO_0(iemCImpl_clts);
5936	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Dd, uint8_t, iGReg, uint8_t, iDrReg);
5937	IEM_CIMPL_PROTO_2(iemCImpl_mov_Dd_Rd, uint8_t, iDrReg, uint8_t, iGReg);
5938	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Td, uint8_t, iGReg, uint8_t, iTrReg);
5939	IEM_CIMPL_PROTO_2(iemCImpl_mov_Td_Rd, uint8_t, iTrReg, uint8_t, iGReg);
5940	IEM_CIMPL_PROTO_1(iemCImpl_invlpg, RTGCPTR, GCPtrPage);
5941	IEM_CIMPL_PROTO_3(iemCImpl_invpcid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvpcidDesc, uint64_t, uInvpcidType);
5942	IEM_CIMPL_PROTO_0(iemCImpl_invd);
5943	IEM_CIMPL_PROTO_0(iemCImpl_wbinvd);
5944	IEM_CIMPL_PROTO_0(iemCImpl_rsm);
5945	IEM_CIMPL_PROTO_0(iemCImpl_rdtsc);
5946	IEM_CIMPL_PROTO_0(iemCImpl_rdtscp);
5947	IEM_CIMPL_PROTO_0(iemCImpl_rdpmc);
5948	IEM_CIMPL_PROTO_0(iemCImpl_rdmsr);
5949	IEM_CIMPL_PROTO_0(iemCImpl_wrmsr);
5950	IEM_CIMPL_PROTO_3(iemCImpl_in, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
5951	IEM_CIMPL_PROTO_2(iemCImpl_in_eAX_DX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
5952	IEM_CIMPL_PROTO_3(iemCImpl_out, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
5953	IEM_CIMPL_PROTO_2(iemCImpl_out_DX_eAX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
5954	IEM_CIMPL_PROTO_0(iemCImpl_cli);
5955	IEM_CIMPL_PROTO_0(iemCImpl_sti);
5956	IEM_CIMPL_PROTO_0(iemCImpl_hlt);
5957	IEM_CIMPL_PROTO_1(iemCImpl_monitor, uint8_t, iEffSeg);
5958	IEM_CIMPL_PROTO_0(iemCImpl_mwait);
5959	IEM_CIMPL_PROTO_0(iemCImpl_swapgs);
5960	IEM_CIMPL_PROTO_0(iemCImpl_cpuid);
5961	IEM_CIMPL_PROTO_1(iemCImpl_aad, uint8_t, bImm);
5962	IEM_CIMPL_PROTO_1(iemCImpl_aam, uint8_t, bImm);
5963	IEM_CIMPL_PROTO_0(iemCImpl_daa);
5964	IEM_CIMPL_PROTO_0(iemCImpl_das);
5965	IEM_CIMPL_PROTO_0(iemCImpl_aaa);
5966	IEM_CIMPL_PROTO_0(iemCImpl_aas);
5967	IEM_CIMPL_PROTO_3(iemCImpl_bound_16, int16_t, idxArray, int16_t, idxLowerBound, int16_t, idxUpperBound);
5968	IEM_CIMPL_PROTO_3(iemCImpl_bound_32, int32_t, idxArray, int32_t, idxLowerBound, int32_t, idxUpperBound);
5969	IEM_CIMPL_PROTO_0(iemCImpl_xgetbv);
5970	IEM_CIMPL_PROTO_0(iemCImpl_xsetbv);
5971	IEM_CIMPL_PROTO_5(iemCImpl_cmpxchg16b_fallback_rendezvous, PRTUINT128U, pu128Dst, PRTUINT128U, pu128RaxRdx,
5972	PRTUINT128U, pu128RbxRcx, uint32_t *, pEFlags, uint8_t, bUnmapInfo);
5973	IEM_CIMPL_PROTO_2(iemCImpl_clflush_clflushopt, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5974	IEM_CIMPL_PROTO_1(iemCImpl_finit, bool, fCheckXcpts);
5975	IEM_CIMPL_PROTO_3(iemCImpl_fxsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5976	IEM_CIMPL_PROTO_3(iemCImpl_fxrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5977	IEM_CIMPL_PROTO_3(iemCImpl_xsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5978	IEM_CIMPL_PROTO_3(iemCImpl_xrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5979	IEM_CIMPL_PROTO_2(iemCImpl_stmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5980	IEM_CIMPL_PROTO_2(iemCImpl_vstmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5981	IEM_CIMPL_PROTO_2(iemCImpl_ldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5982	IEM_CIMPL_PROTO_3(iemCImpl_fnstenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5983	IEM_CIMPL_PROTO_3(iemCImpl_fnsave, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5984	IEM_CIMPL_PROTO_3(iemCImpl_fldenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
5985	IEM_CIMPL_PROTO_3(iemCImpl_frstor, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
5986	IEM_CIMPL_PROTO_1(iemCImpl_fldcw, uint16_t, u16Fcw);
5987	IEM_CIMPL_PROTO_2(iemCImpl_fxch_underflow, uint8_t, iStReg, uint16_t, uFpuOpcode);
5988	IEM_CIMPL_PROTO_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, bool, fUCmp, uint32_t, uPopAndFpuOpcode);
5989	IEM_CIMPL_PROTO_2(iemCImpl_rdseed, uint8_t, iReg, IEMMODE, enmEffOpSize);
5990	IEM_CIMPL_PROTO_2(iemCImpl_rdrand, uint8_t, iReg, IEMMODE, enmEffOpSize);
5991	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovps_load_u128, uint8_t, iXRegDst, uint8_t, iXRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
5992	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovps_load_u256, uint8_t, iYRegDst, uint8_t, iYRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
5993	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovps_store_u128, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iXRegMsk, uint8_t, iXRegSrc);
5994	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovps_store_u256, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iYRegMsk, uint8_t, iYRegSrc);
5995	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovd_load_u128, uint8_t, iXRegDst, uint8_t, iXRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
5996	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovd_load_u256, uint8_t, iYRegDst, uint8_t, iYRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
5997	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovd_store_u128, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iXRegMsk, uint8_t, iXRegSrc);
5998	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovd_store_u256, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iYRegMsk, uint8_t, iYRegSrc);
5999	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovpd_load_u128, uint8_t, iXRegDst, uint8_t, iXRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6000	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovpd_load_u256, uint8_t, iYRegDst, uint8_t, iYRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6001	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovpd_store_u128, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iXRegMsk, uint8_t, iXRegSrc);
6002	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovpd_store_u256, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iYRegMsk, uint8_t, iYRegSrc);
6003	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovq_load_u128, uint8_t, iXRegDst, uint8_t, iXRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6004	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovq_load_u256, uint8_t, iYRegDst, uint8_t, iYRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6005	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovq_store_u128, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iXRegMsk, uint8_t, iXRegSrc);
6006	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovq_store_u256, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iYRegMsk, uint8_t, iYRegSrc);
6007
6008	/** @} */
6009
6010	/** @name IEMAllCImplStrInstr.cpp.h
6011	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/' -e 's/RT_CONCAT4(//' \
6012	* -e 's/,ADDR_SIZE)/64/g' -e 's/,OP_SIZE,/64/g' -e 's/,OP_rAX,/rax/g' IEMAllCImplStrInstr.cpp.h
6013	* @{ */
6014	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr16, uint8_t, iEffSeg);
6015	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr16, uint8_t, iEffSeg);
6016	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m16);
6017	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m16);
6018	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr16, uint8_t, iEffSeg);
6019	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m16);
6020	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m16, int8_t, iEffSeg);
6021	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr16, bool, fIoChecked);
6022	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr16, bool, fIoChecked);
6023	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6024	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6025
6026	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr16, uint8_t, iEffSeg);
6027	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr16, uint8_t, iEffSeg);
6028	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m16);
6029	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m16);
6030	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr16, uint8_t, iEffSeg);
6031	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m16);
6032	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m16, int8_t, iEffSeg);
6033	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr16, bool, fIoChecked);
6034	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr16, bool, fIoChecked);
6035	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6036	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6037
6038	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr16, uint8_t, iEffSeg);
6039	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr16, uint8_t, iEffSeg);
6040	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m16);
6041	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m16);
6042	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr16, uint8_t, iEffSeg);
6043	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m16);
6044	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m16, int8_t, iEffSeg);
6045	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr16, bool, fIoChecked);
6046	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr16, bool, fIoChecked);
6047	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6048	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6049
6050
6051	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr32, uint8_t, iEffSeg);
6052	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr32, uint8_t, iEffSeg);
6053	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m32);
6054	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m32);
6055	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr32, uint8_t, iEffSeg);
6056	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m32);
6057	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m32, int8_t, iEffSeg);
6058	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr32, bool, fIoChecked);
6059	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr32, bool, fIoChecked);
6060	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6061	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6062
6063	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr32, uint8_t, iEffSeg);
6064	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr32, uint8_t, iEffSeg);
6065	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m32);
6066	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m32);
6067	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr32, uint8_t, iEffSeg);
6068	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m32);
6069	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m32, int8_t, iEffSeg);
6070	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr32, bool, fIoChecked);
6071	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr32, bool, fIoChecked);
6072	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6073	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6074
6075	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr32, uint8_t, iEffSeg);
6076	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr32, uint8_t, iEffSeg);
6077	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m32);
6078	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m32);
6079	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr32, uint8_t, iEffSeg);
6080	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m32);
6081	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m32, int8_t, iEffSeg);
6082	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr32, bool, fIoChecked);
6083	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr32, bool, fIoChecked);
6084	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6085	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6086
6087	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr32, uint8_t, iEffSeg);
6088	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr32, uint8_t, iEffSeg);
6089	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m32);
6090	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m32);
6091	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr32, uint8_t, iEffSeg);
6092	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m32);
6093	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m32, int8_t, iEffSeg);
6094	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr32, bool, fIoChecked);
6095	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr32, bool, fIoChecked);
6096	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6097	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6098
6099
6100	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr64, uint8_t, iEffSeg);
6101	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr64, uint8_t, iEffSeg);
6102	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m64);
6103	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m64);
6104	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr64, uint8_t, iEffSeg);
6105	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m64);
6106	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m64, int8_t, iEffSeg);
6107	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr64, bool, fIoChecked);
6108	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr64, bool, fIoChecked);
6109	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6110	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6111
6112	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr64, uint8_t, iEffSeg);
6113	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr64, uint8_t, iEffSeg);
6114	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m64);
6115	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m64);
6116	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr64, uint8_t, iEffSeg);
6117	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m64);
6118	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m64, int8_t, iEffSeg);
6119	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr64, bool, fIoChecked);
6120	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr64, bool, fIoChecked);
6121	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6122	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6123
6124	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr64, uint8_t, iEffSeg);
6125	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr64, uint8_t, iEffSeg);
6126	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m64);
6127	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m64);
6128	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr64, uint8_t, iEffSeg);
6129	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m64);
6130	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m64, int8_t, iEffSeg);
6131	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr64, bool, fIoChecked);
6132	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr64, bool, fIoChecked);
6133	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6134	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6135
6136	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr64, uint8_t, iEffSeg);
6137	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr64, uint8_t, iEffSeg);
6138	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m64);
6139	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m64);
6140	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr64, uint8_t, iEffSeg);
6141	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m64);
6142	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m64, int8_t, iEffSeg);
6143	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr64, bool, fIoChecked);
6144	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr64, bool, fIoChecked);
6145	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6146	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6147	/** @} */
6148
6149	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
6150	VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT;
6151	VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT;
6152	VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT;
6153	VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT;
6154	VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT;
6155	VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
6156	VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALKFAST pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT;
6157	VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT;
6158	VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT;
6159	VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
6160	bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT;
6161	VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
6162	bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT;
6163	VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6164	VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6165	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6166	VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6167	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6168	VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6169	VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT;
6170	VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
6171	RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT;
6172	VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT;
6173	VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT;
6174	VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT;
6175	uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT;
6176	void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT;
6177	VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
6178	uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT;
6179	bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT;
6180	IEM_CIMPL_PROTO_0(iemCImpl_vmxoff);
6181	IEM_CIMPL_PROTO_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon);
6182	IEM_CIMPL_PROTO_0(iemCImpl_vmlaunch);
6183	IEM_CIMPL_PROTO_0(iemCImpl_vmresume);
6184	IEM_CIMPL_PROTO_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
6185	IEM_CIMPL_PROTO_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
6186	IEM_CIMPL_PROTO_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
6187	IEM_CIMPL_PROTO_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField);
6188	IEM_CIMPL_PROTO_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField);
6189	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField);
6190	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg32, uint64_t *, pu32Dst, uint32_t, u32VmcsField);
6191	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField);
6192	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField);
6193	IEM_CIMPL_PROTO_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType);
6194	IEM_CIMPL_PROTO_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType);
6195	IEM_CIMPL_PROTO_0(iemCImpl_vmx_pause);
6196	#endif
6197
6198	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
6199	VBOXSTRICTRC iemSvmVmexit(PVMCPUCC pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2) RT_NOEXCEPT;
6200	VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr, uint64_t uCr2) RT_NOEXCEPT;
6201	VBOXSTRICTRC iemSvmHandleIOIntercept(PVMCPUCC pVCpu, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
6202	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, uint8_t cbInstr) RT_NOEXCEPT;
6203	VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPUCC pVCpu, uint32_t idMsr, bool fWrite, uint8_t cbInstr) RT_NOEXCEPT;
6204	IEM_CIMPL_PROTO_0(iemCImpl_vmrun);
6205	IEM_CIMPL_PROTO_0(iemCImpl_vmload);
6206	IEM_CIMPL_PROTO_0(iemCImpl_vmsave);
6207	IEM_CIMPL_PROTO_0(iemCImpl_clgi);
6208	IEM_CIMPL_PROTO_0(iemCImpl_stgi);
6209	IEM_CIMPL_PROTO_0(iemCImpl_invlpga);
6210	IEM_CIMPL_PROTO_0(iemCImpl_skinit);
6211	IEM_CIMPL_PROTO_0(iemCImpl_svm_pause);
6212	#endif
6213
6214	IEM_CIMPL_PROTO_0(iemCImpl_vmcall); /* vmx */
6215	IEM_CIMPL_PROTO_0(iemCImpl_vmmcall); /* svm */
6216	IEM_CIMPL_PROTO_1(iemCImpl_Hypercall, uint16_t, uDisOpcode); /* both */
6217
6218	extern const PFNIEMOP g_apfnIemInterpretOnlyOneByteMap[256];
6219	extern const PFNIEMOP g_apfnIemInterpretOnlyTwoByteMap[1024];
6220	extern const PFNIEMOP g_apfnIemInterpretOnlyThreeByte0f3a[1024];
6221	extern const PFNIEMOP g_apfnIemInterpretOnlyThreeByte0f38[1024];
6222	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap1[1024];
6223	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap2[1024];
6224	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap3[1024];
6225
6226	/*
6227	* Recompiler related stuff.
6228	*/
6229	extern const PFNIEMOP g_apfnIemThreadedRecompilerOneByteMap[256];
6230	extern const PFNIEMOP g_apfnIemThreadedRecompilerTwoByteMap[1024];
6231	extern const PFNIEMOP g_apfnIemThreadedRecompilerThreeByte0f3a[1024];
6232	extern const PFNIEMOP g_apfnIemThreadedRecompilerThreeByte0f38[1024];
6233	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap1[1024];
6234	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap2[1024];
6235	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap3[1024];
6236
6237	DECLCALLBACK(int) iemTbInit(PVMCC pVM, uint32_t cInitialTbs, uint32_t cMaxTbs,
6238	uint64_t cbInitialExec, uint64_t cbMaxExec, uint32_t cbChunkExec);
6239	void iemThreadedTbObsolete(PVMCPUCC pVCpu, PIEMTB pTb, bool fSafeToFree);
6240	DECLHIDDEN(void) iemTbAllocatorFree(PVMCPUCC pVCpu, PIEMTB pTb);
6241	void iemTbAllocatorProcessDelayedFrees(PVMCPUCC pVCpu, PIEMTBALLOCATOR pTbAllocator);
6242	void iemTbAllocatorFreeupNativeSpace(PVMCPUCC pVCpu, uint32_t cNeededInstrs);
6243	DECLHIDDEN(const char ) iemTbFlagsToString(uint32_t fFlags, char pszBuf, size_t cbBuf) RT_NOEXCEPT;
6244	DECLHIDDEN(void) iemThreadedDisassembleTb(PCIEMTB pTb, PCDBGFINFOHLP pHlp) RT_NOEXCEPT;
6245
6246
6247	/** @todo FNIEMTHREADEDFUNC and friends may need more work... */
6248	#if defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
6249	typedef VBOXSTRICTRC /__attribute__((__nothrow__))/ FNIEMTHREADEDFUNC(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
6250	typedef FNIEMTHREADEDFUNC *PFNIEMTHREADEDFUNC;
6251	# define IEM_DECL_IEMTHREADEDFUNC_DEF(a_Name) \
6252	VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2)
6253	# define IEM_DECL_IEMTHREADEDFUNC_PROTO(a_Name) \
6254	VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2)
6255
6256	#else
6257	typedef VBOXSTRICTRC (FNIEMTHREADEDFUNC)(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
6258	typedef FNIEMTHREADEDFUNC *PFNIEMTHREADEDFUNC;
6259	# define IEM_DECL_IEMTHREADEDFUNC_DEF(a_Name) \
6260	VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2) IEM_NOEXCEPT_MAY_LONGJMP
6261	# define IEM_DECL_IEMTHREADEDFUNC_PROTO(a_Name) \
6262	VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2) IEM_NOEXCEPT_MAY_LONGJMP
6263	#endif
6264
6265
6266	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_Nop);
6267	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_LogCpuState);
6268
6269	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_DeferToCImpl0);
6270
6271	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckIrq);
6272	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckMode);
6273	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckHwInstrBps);
6274	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLim);
6275
6276	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodes);
6277	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodes);
6278	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesConsiderCsLim);
6279
6280	/* Branching: */
6281	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndPcAndOpcodes);
6282	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckPcAndOpcodes);
6283	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckPcAndOpcodesConsiderCsLim);
6284
6285	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesLoadingTlb);
6286	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesLoadingTlb);
6287	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesLoadingTlbConsiderCsLim);
6288
6289	/* Natural page crossing: */
6290	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesAcrossPageLoadingTlb);
6291	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesAcrossPageLoadingTlb);
6292	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesAcrossPageLoadingTlbConsiderCsLim);
6293
6294	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesOnNextPageLoadingTlb);
6295	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNextPageLoadingTlb);
6296	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNextPageLoadingTlbConsiderCsLim);
6297
6298	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesOnNewPageLoadingTlb);
6299	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNewPageLoadingTlb);
6300	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNewPageLoadingTlbConsiderCsLim);
6301
6302	bool iemThreadedCompileEmitIrqCheckBefore(PVMCPUCC pVCpu, PIEMTB pTb);
6303	bool iemThreadedCompileBeginEmitCallsComplications(PVMCPUCC pVCpu, PIEMTB pTb);
6304
6305	/* Native recompiler public bits: */
6306	DECLHIDDEN(PIEMTB) iemNativeRecompile(PVMCPUCC pVCpu, PIEMTB pTb) RT_NOEXCEPT;
6307	DECLHIDDEN(void) iemNativeDisassembleTb(PCIEMTB pTb, PCDBGFINFOHLP pHlp) RT_NOEXCEPT;
6308	int iemExecMemAllocatorInit(PVMCPU pVCpu, uint64_t cbMax, uint64_t cbInitial, uint32_t cbChunk) RT_NOEXCEPT;
6309	DECLHIDDEN(void ) iemExecMemAllocatorAlloc(PVMCPU pVCpu, uint32_t cbReq, PIEMTB pTb, void *ppvExec) RT_NOEXCEPT;
6310	DECLHIDDEN(void) iemExecMemAllocatorReadyForUse(PVMCPUCC pVCpu, void *pv, size_t cb) RT_NOEXCEPT;
6311	void iemExecMemAllocatorFree(PVMCPU pVCpu, void *pv, size_t cb) RT_NOEXCEPT;
6312	DECLASM(DECL_NO_RETURN(void)) iemNativeTbLongJmp(void *pvFramePointer, int rc) RT_NOEXCEPT;
6313
6314	#endif /* !RT_IN_ASSEMBLER - ASM-NOINC-END */
6315
6316
6317	/** @} */
6318
6319	RT_C_DECLS_END
6320
6321	/* ASM-INC: %include "IEMInternalStruct.mac" */
6322
6323	#endif /* !VMM_INCLUDED_SRC_include_IEMInternal_h */
6324

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source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h@ 104956

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