IEMInternal.h@ 104984

Last change on this file since 104984 was 104984, checked in by vboxsync, 5 months ago
VMM/IEM: Relax alignment restrictions in native code TLB lookup, avoid the fallback/tlbmiss code path for most accesses as long as they're within the same page. bugref:10687
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 327.2 KB

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1	/* $Id: IEMInternal.h 104984 2024-06-20 14:07:04Z vboxsync $ */
2	/** @file
3	* IEM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2011-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_IEMInternal_h
29	#define VMM_INCLUDED_SRC_include_IEMInternal_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#ifndef RT_IN_ASSEMBLER
35	# include <VBox/vmm/cpum.h>
36	# include <VBox/vmm/iem.h>
37	# include <VBox/vmm/pgm.h>
38	# include <VBox/vmm/stam.h>
39	# include <VBox/param.h>
40
41	# include <iprt/setjmp-without-sigmask.h>
42	# include <iprt/list.h>
43	#endif /* !RT_IN_ASSEMBLER */
44
45
46	RT_C_DECLS_BEGIN
47
48
49	/** @defgroup grp_iem_int Internals
50	* @ingroup grp_iem
51	* @internal
52	* @{
53	*/
54
55	/* Make doxygen happy w/o overcomplicating the #if checks. */
56	#ifdef DOXYGEN_RUNNING
57	# define IEM_WITH_THROW_CATCH
58	# define VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
59	#endif
60
61	/** For expanding symbol in slickedit and other products tagging and
62	* crossreferencing IEM symbols. */
63	#ifndef IEM_STATIC
64	# define IEM_STATIC static
65	#endif
66
67	/** @def IEM_WITH_SETJMP
68	* Enables alternative status code handling using setjmps.
69	*
70	* This adds a bit of expense via the setjmp() call since it saves all the
71	* non-volatile registers. However, it eliminates return code checks and allows
72	* for more optimal return value passing (return regs instead of stack buffer).
73	*/
74	#if defined(DOXYGEN_RUNNING) \|\| defined(RT_OS_WINDOWS) \|\| 1
75	# define IEM_WITH_SETJMP
76	#endif
77
78	/** @def IEM_WITH_THROW_CATCH
79	* Enables using C++ throw/catch as an alternative to setjmp/longjmp in user
80	* mode code when IEM_WITH_SETJMP is in effect.
81	*
82	* With GCC 11.3.1 and code TLB on linux, using throw/catch instead of
83	* setjmp/long resulted in bs2-test-1 running 3.00% faster and all but on test
84	* result value improving by more than 1%. (Best out of three.)
85	*
86	* With Visual C++ 2019 and code TLB on windows, using throw/catch instead of
87	* setjmp/long resulted in bs2-test-1 running 3.68% faster and all but some of
88	* the MMIO and CPUID tests ran noticeably faster. Variation is greater than on
89	* Linux, but it should be quite a bit faster for normal code.
90	*/
91	#if defined(__cplusplus) && defined(IEM_WITH_SETJMP) && defined(IN_RING3) && (defined(__GNUC__) \|\| defined(_MSC_VER)) /* ASM-NOINC-START */
92	# define IEM_WITH_THROW_CATCH
93	#endif /ASM-NOINC-END/
94
95	/** @def IEMNATIVE_WITH_DELAYED_PC_UPDATING
96	* Enables the delayed PC updating optimization (see @bugref{10373}).
97	*/
98	#if defined(DOXYGEN_RUNNING) \|\| 1
99	# define IEMNATIVE_WITH_DELAYED_PC_UPDATING
100	#endif
101
102	/** Enables the SIMD register allocator @bugref{10614}. */
103	#if defined(DOXYGEN_RUNNING) \|\| 1
104	# define IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
105	#endif
106	/** Enables access to even callee saved registers. */
107	//# define IEMNATIVE_WITH_SIMD_REG_ACCESS_ALL_REGISTERS
108
109	#if defined(DOXYGEN_RUNNING) \|\| 1
110	/** @def IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
111	* Delay the writeback or dirty registers as long as possible. */
112	# define IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
113	#endif
114
115	/** @def IEM_WITH_TLB_STATISTICS
116	* Enables all TLB statistics. */
117	#if defined(VBOX_WITH_STATISTICS) \|\| defined(DOXYGEN_RUNNING)
118	# define IEM_WITH_TLB_STATISTICS
119	#endif
120
121	/** @def VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
122	* Enables a quicker alternative to throw/longjmp for IEM_DO_LONGJMP when
123	* executing native translation blocks.
124	*
125	* This exploits the fact that we save all non-volatile registers in the TB
126	* prologue and thus just need to do the same as the TB epilogue to get the
127	* effect of a longjmp/throw. Since MSC marks XMM6 thru XMM15 as
128	* non-volatile (and does something even more crazy for ARM), this probably
129	* won't work reliably on Windows. */
130	#ifdef RT_ARCH_ARM64
131	# ifndef RT_OS_WINDOWS
132	# define VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
133	# endif
134	#endif
135	/* ASM-NOINC-START */
136	#ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
137	# if !defined(IN_RING3) \
138	\|\| !defined(VBOX_WITH_IEM_RECOMPILER) \
139	\|\| !defined(VBOX_WITH_IEM_NATIVE_RECOMPILER)
140	# undef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
141	# elif defined(RT_OS_WINDOWS)
142	# pragma message("VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP is not safe to use on windows")
143	# endif
144	#endif
145
146
147	/** @def IEM_DO_LONGJMP
148	*
149	* Wrapper around longjmp / throw.
150	*
151	* @param a_pVCpu The CPU handle.
152	* @param a_rc The status code jump back with / throw.
153	*/
154	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
155	# ifdef IEM_WITH_THROW_CATCH
156	# ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
157	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) do { \
158	if ((a_pVCpu)->iem.s.pvTbFramePointerR3) \
159	iemNativeTbLongJmp((a_pVCpu)->iem.s.pvTbFramePointerR3, (a_rc)); \
160	throw int(a_rc); \
161	} while (0)
162	# else
163	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) throw int(a_rc)
164	# endif
165	# else
166	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) longjmp(*(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf), (a_rc))
167	# endif
168	#endif
169
170	/** For use with IEM function that may do a longjmp (when enabled).
171	*
172	* Visual C++ has trouble longjmp'ing from/over functions with the noexcept
173	* attribute. So, we indicate that function that may be part of a longjmp may
174	* throw "exceptions" and that the compiler should definitely not generate and
175	* std::terminate calling unwind code.
176	*
177	* Here is one example of this ending in std::terminate:
178	* @code{.txt}
179	00 00000041`cadfda10 00007ffc`5d5a1f9f ucrtbase!abort+0x4e
180	01 00000041`cadfda40 00007ffc`57af229a ucrtbase!terminate+0x1f
181	02 00000041`cadfda70 00007ffb`eec91030 VCRUNTIME140!__std_terminate+0xa [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\ehhelpers.cpp @ 192]
182	03 00000041`cadfdaa0 00007ffb`eec92c6d VCRUNTIME140_1!_CallSettingFrame+0x20 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\handlers.asm @ 50]
183	04 00000041`cadfdad0 00007ffb`eec93ae5 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToState+0x241 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 1085]
184	05 00000041`cadfdc00 00007ffb`eec92258 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToEmptyState+0x2d [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 218]
185	06 00000041`cadfdc30 00007ffb`eec940e9 VCRUNTIME140_1!__InternalCxxFrameHandler<__FrameHandler4>+0x194 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 304]
186	07 00000041`cadfdcd0 00007ffc`5f9f249f VCRUNTIME140_1!__CxxFrameHandler4+0xa9 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 290]
187	08 00000041`cadfdd40 00007ffc`5f980939 ntdll!RtlpExecuteHandlerForUnwind+0xf
188	09 00000041`cadfdd70 00007ffc`5f9a0edd ntdll!RtlUnwindEx+0x339
189	0a 00000041`cadfe490 00007ffc`57aff976 ntdll!RtlUnwind+0xcd
190	0b 00000041`cadfea00 00007ffb`e1b5de01 VCRUNTIME140!__longjmp_internal+0xe6 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\longjmp.asm @ 140]
191	0c (Inline Function) --------`-------- VBoxVMM!iemOpcodeGetNextU8SlowJmp+0x95 [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 1155]
192	0d 00000041`cadfea50 00007ffb`e1b60f6b VBoxVMM!iemOpcodeGetNextU8Jmp+0xc1 [L:\vbox-intern\src\VBox\VMM\include\IEMInline.h @ 402]
193	0e 00000041`cadfea90 00007ffb`e1cc6201 VBoxVMM!IEMExecForExits+0xdb [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 10185]
194	0f 00000041`cadfec70 00007ffb`e1d0df8d VBoxVMM!EMHistoryExec+0x4f1 [L:\vbox-intern\src\VBox\VMM\VMMAll\EMAll.cpp @ 452]
195	10 00000041`cadfed60 00007ffb`e1d0d4c0 VBoxVMM!nemR3WinHandleExitCpuId+0x79d [L:\vbox-intern\src\VBox\VMM\VMMAll\NEMAllNativeTemplate-win.cpp.h @ 1829] @encode
196	@endcode
197	*
198	* @see https://developercommunity.visualstudio.com/t/fragile-behavior-of-longjmp-called-from-noexcept-f/1532859
199	*/
200	#if defined(IEM_WITH_SETJMP) && (defined(_MSC_VER) \|\| defined(IEM_WITH_THROW_CATCH))
201	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT_EX(false)
202	#else
203	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT
204	#endif
205	/* ASM-NOINC-END */
206
207	#define IEM_IMPLEMENTS_TASKSWITCH
208
209	/** @def IEM_WITH_3DNOW
210	* Includes the 3DNow decoding. */
211	#if !defined(IEM_WITH_3DNOW) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
212	# ifndef IEM_WITHOUT_3DNOW
213	# define IEM_WITH_3DNOW
214	# endif
215	#endif
216
217	/** @def IEM_WITH_THREE_0F_38
218	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
219	#if !defined(IEM_WITH_THREE_0F_38) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
220	# ifndef IEM_WITHOUT_THREE_0F_38
221	# define IEM_WITH_THREE_0F_38
222	# endif
223	#endif
224
225	/** @def IEM_WITH_THREE_0F_3A
226	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
227	#if !defined(IEM_WITH_THREE_0F_3A) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
228	# ifndef IEM_WITHOUT_THREE_0F_3A
229	# define IEM_WITH_THREE_0F_3A
230	# endif
231	#endif
232
233	/** @def IEM_WITH_VEX
234	* Includes the VEX decoding. */
235	#if !defined(IEM_WITH_VEX) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
236	# ifndef IEM_WITHOUT_VEX
237	# define IEM_WITH_VEX
238	# endif
239	#endif
240
241	/** @def IEM_CFG_TARGET_CPU
242	* The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
243	*
244	* By default we allow this to be configured by the user via the
245	* CPUM/GuestCpuName config string, but this comes at a slight cost during
246	* decoding. So, for applications of this code where there is no need to
247	* be dynamic wrt target CPU, just modify this define.
248	*/
249	#if !defined(IEM_CFG_TARGET_CPU) \|\| defined(DOXYGEN_RUNNING)
250	# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
251	#endif
252
253	//#define IEM_WITH_CODE_TLB // - work in progress
254	//#define IEM_WITH_DATA_TLB // - work in progress
255
256
257	/** @def IEM_USE_UNALIGNED_DATA_ACCESS
258	* Use unaligned accesses instead of elaborate byte assembly. */
259	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86) \|\| defined(DOXYGEN_RUNNING) /ASM-NOINC/
260	# define IEM_USE_UNALIGNED_DATA_ACCESS
261	#endif /ASM-NOINC/
262
263	//#define IEM_LOG_MEMORY_WRITES
264
265
266
267	#ifndef RT_IN_ASSEMBLER /* ASM-NOINC-START - the rest of the file */
268
269	# if !defined(IEM_WITHOUT_INSTRUCTION_STATS) && !defined(DOXYGEN_RUNNING)
270	/** Instruction statistics. */
271	typedef struct IEMINSTRSTATS
272	{
273	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
274	# include "IEMInstructionStatisticsTmpl.h"
275	# undef IEM_DO_INSTR_STAT
276	} IEMINSTRSTATS;
277	#else
278	struct IEMINSTRSTATS;
279	typedef struct IEMINSTRSTATS IEMINSTRSTATS;
280	#endif
281	/** Pointer to IEM instruction statistics. */
282	typedef IEMINSTRSTATS *PIEMINSTRSTATS;
283
284
285	/** @name IEMTARGETCPU_EFL_BEHAVIOR_XXX - IEMCPU::aidxTargetCpuEflFlavour
286	* @{ */
287	#define IEMTARGETCPU_EFL_BEHAVIOR_NATIVE 0 /*< Native x86 EFLAGS result; Intel EFLAGS when on non-x86 hosts. /
288	#define IEMTARGETCPU_EFL_BEHAVIOR_INTEL 1 /*< Intel EFLAGS result. /
289	#define IEMTARGETCPU_EFL_BEHAVIOR_AMD 2 /*< AMD EFLAGS result /
290	#define IEMTARGETCPU_EFL_BEHAVIOR_RESERVED 3 /*< Reserved/dummy entry slot that's the same as 0. /
291	#define IEMTARGETCPU_EFL_BEHAVIOR_MASK 3 /*< For masking the index before use. /
292	/** Selects the right variant from a_aArray.
293	* pVCpu is implicit in the caller context. */
294	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT(a_aArray) \
295	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[1] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
296	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for when no native worker can
297	* be used because the host CPU does not support the operation. */
298	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_NON_NATIVE(a_aArray) \
299	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
300	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for a two dimentional
301	* array paralleling IEMCPU::aidxTargetCpuEflFlavour and a single bit index
302	* into the two.
303	* @sa IEM_SELECT_NATIVE_OR_FALLBACK */
304	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
305	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
306	(a_aaArray[a_fNative][pVCpu->iem.s.aidxTargetCpuEflFlavour[a_fNative] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
307	#else
308	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
309	(a_aaArray[0][pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
310	#endif
311	/** @} */
312
313	/**
314	* Picks @a a_pfnNative or @a a_pfnFallback according to the host CPU feature
315	* indicator given by @a a_fCpumFeatureMember (CPUMFEATURES member).
316	*
317	* On non-x86 hosts, this will shortcut to the fallback w/o checking the
318	* indicator.
319	*
320	* @sa IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX
321	*/
322	#if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
323	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) \
324	(g_CpumHostFeatures.s.a_fCpumFeatureMember ? a_pfnNative : a_pfnFallback)
325	#else
326	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) (a_pfnFallback)
327	#endif
328
329
330	/**
331	* Branch types.
332	*/
333	typedef enum IEMBRANCH
334	{
335	IEMBRANCH_JUMP = 1,
336	IEMBRANCH_CALL,
337	IEMBRANCH_TRAP,
338	IEMBRANCH_SOFTWARE_INT,
339	IEMBRANCH_HARDWARE_INT
340	} IEMBRANCH;
341	AssertCompileSize(IEMBRANCH, 4);
342
343
344	/**
345	* INT instruction types.
346	*/
347	typedef enum IEMINT
348	{
349	/** INT n instruction (opcode 0xcd imm). */
350	IEMINT_INTN = 0,
351	/** Single byte INT3 instruction (opcode 0xcc). */
352	IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
353	/** Single byte INTO instruction (opcode 0xce). */
354	IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
355	/** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
356	IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
357	} IEMINT;
358	AssertCompileSize(IEMINT, 4);
359
360
361	/**
362	* A FPU result.
363	*/
364	typedef struct IEMFPURESULT
365	{
366	/** The output value. */
367	RTFLOAT80U r80Result;
368	/** The output status. */
369	uint16_t FSW;
370	} IEMFPURESULT;
371	AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
372	/** Pointer to a FPU result. */
373	typedef IEMFPURESULT *PIEMFPURESULT;
374	/** Pointer to a const FPU result. */
375	typedef IEMFPURESULT const *PCIEMFPURESULT;
376
377
378	/**
379	* A FPU result consisting of two output values and FSW.
380	*/
381	typedef struct IEMFPURESULTTWO
382	{
383	/** The first output value. */
384	RTFLOAT80U r80Result1;
385	/** The output status. */
386	uint16_t FSW;
387	/** The second output value. */
388	RTFLOAT80U r80Result2;
389	} IEMFPURESULTTWO;
390	AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
391	AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
392	/** Pointer to a FPU result consisting of two output values and FSW. */
393	typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
394	/** Pointer to a const FPU result consisting of two output values and FSW. */
395	typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
396
397
398	/**
399	* IEM TLB entry.
400	*
401	* Lookup assembly:
402	* @code{.asm}
403	; Calculate tag.
404	mov rax, [VA]
405	shl rax, 16
406	shr rax, 16 + X86_PAGE_SHIFT
407	or rax, [uTlbRevision]
408
409	; Do indexing.
410	movzx ecx, al
411	lea rcx, [pTlbEntries + rcx]
412
413	; Check tag.
414	cmp [rcx + IEMTLBENTRY.uTag], rax
415	jne .TlbMiss
416
417	; Check access.
418	mov rax, ACCESS_FLAGS \| MAPPING_R3_NOT_VALID \| 0xffffff00
419	and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
420	cmp rax, [uTlbPhysRev]
421	jne .TlbMiss
422
423	; Calc address and we're done.
424	mov eax, X86_PAGE_OFFSET_MASK
425	and eax, [VA]
426	or rax, [rcx + IEMTLBENTRY.pMappingR3]
427	%ifdef VBOX_WITH_STATISTICS
428	inc qword [cTlbHits]
429	%endif
430	jmp .Done
431
432	.TlbMiss:
433	mov r8d, ACCESS_FLAGS
434	mov rdx, [VA]
435	mov rcx, [pVCpu]
436	call iemTlbTypeMiss
437	.Done:
438
439	@endcode
440	*
441	*/
442	typedef struct IEMTLBENTRY
443	{
444	/** The TLB entry tag.
445	* Bits 35 thru 0 are made up of the virtual address shifted right 12 bits, this
446	* is ASSUMING a virtual address width of 48 bits.
447	*
448	* Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
449	*
450	* The TLB lookup code uses the current TLB revision, which won't ever be zero,
451	* enabling an extremely cheap TLB invalidation most of the time. When the TLB
452	* revision wraps around though, the tags needs to be zeroed.
453	*
454	* @note Try use SHRD instruction? After seeing
455	* https://gmplib.org/~tege/x86-timing.pdf, maybe not.
456	*
457	* @todo This will need to be reorganized for 57-bit wide virtual address and
458	* PCID (currently 12 bits) and ASID (currently 6 bits) support. We'll
459	* have to move the TLB entry versioning entirely to the
460	* fFlagsAndPhysRev member then, 57 bit wide VAs means we'll only have
461	* 19 bits left (64 - 57 + 12 = 19) and they'll almost entire be
462	* consumed by PCID and ASID (12 + 6 = 18).
463	*/
464	uint64_t uTag;
465	/** Access flags and physical TLB revision.
466	*
467	* - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
468	* - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
469	* - Bit 2 - page tables - not user (complemented X86_PTE_US).
470	* - Bit 3 - pgm phys/virt - not directly writable.
471	* - Bit 4 - pgm phys page - not directly readable.
472	* - Bit 5 - page tables - not accessed (complemented X86_PTE_A).
473	* - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
474	* - Bit 7 - tlb entry - pMappingR3 member not valid.
475	* - Bits 63 thru 8 are used for the physical TLB revision number.
476	*
477	* We're using complemented bit meanings here because it makes it easy to check
478	* whether special action is required. For instance a user mode write access
479	* would do a "TEST fFlags, (X86_PTE_RW \| X86_PTE_US \| X86_PTE_D)" and a
480	* non-zero result would mean special handling needed because either it wasn't
481	* writable, or it wasn't user, or the page wasn't dirty. A user mode read
482	* access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
483	* need to check any PTE flag.
484	*/
485	uint64_t fFlagsAndPhysRev;
486	/** The guest physical page address. */
487	uint64_t GCPhys;
488	/** Pointer to the ring-3 mapping. */
489	R3PTRTYPE(uint8_t *) pbMappingR3;
490	#if HC_ARCH_BITS == 32
491	uint32_t u32Padding1;
492	#endif
493	} IEMTLBENTRY;
494	AssertCompileSize(IEMTLBENTRY, 32);
495	/** Pointer to an IEM TLB entry. */
496	typedef IEMTLBENTRY *PIEMTLBENTRY;
497
498	/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
499	* @{ */
500	#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /*< Page tables: Not executable. /
501	#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /*< Page tables: Not writable. /
502	#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /*< Page tables: Not user accessible (supervisor only). /
503	#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /*< Phys page: Not writable (access handler, ROM, whatever). /
504	#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /*< Phys page: Not readable (MMIO / access handler, ROM) /
505	#define IEMTLBE_F_PT_NO_ACCESSED RT_BIT_64(5) /*< Phys tables: Not accessed (need to be marked accessed). /
506	#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /*< Page tables: Not dirty (needs to be made dirty on write). /
507	#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(7) /*< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. /
508	#define IEMTLBE_F_PG_UNASSIGNED RT_BIT_64(8) /*< Phys page: Unassigned memory (not RAM, ROM, MMIO2 or MMIO). /
509	#define IEMTLBE_F_PG_CODE_PAGE RT_BIT_64(9) /*< Phys page: Code page. /
510	#define IEMTLBE_F_PHYS_REV UINT64_C(0xfffffffffffffc00) /*< Physical revision mask. @sa IEMTLB_PHYS_REV_INCR /
511	/** @} */
512	AssertCompile(PGMIEMGCPHYS2PTR_F_NO_WRITE == IEMTLBE_F_PG_NO_WRITE);
513	AssertCompile(PGMIEMGCPHYS2PTR_F_NO_READ == IEMTLBE_F_PG_NO_READ);
514	AssertCompile(PGMIEMGCPHYS2PTR_F_NO_MAPPINGR3 == IEMTLBE_F_NO_MAPPINGR3);
515	AssertCompile(PGMIEMGCPHYS2PTR_F_UNASSIGNED == IEMTLBE_F_PG_UNASSIGNED);
516	AssertCompile(PGMIEMGCPHYS2PTR_F_CODE_PAGE == IEMTLBE_F_PG_CODE_PAGE);
517	/** The bits set by PGMPhysIemGCPhys2PtrNoLock. */
518	#define IEMTLBE_GCPHYS2PTR_MASK ( PGMIEMGCPHYS2PTR_F_NO_WRITE \
519	\| PGMIEMGCPHYS2PTR_F_NO_READ \
520	\| PGMIEMGCPHYS2PTR_F_NO_MAPPINGR3 \
521	\| PGMIEMGCPHYS2PTR_F_UNASSIGNED \
522	\| PGMIEMGCPHYS2PTR_F_CODE_PAGE \
523	\| IEMTLBE_F_PHYS_REV )
524
525	/** The TLB size (power of two).
526	* We initially chose 256 because that way we can obtain the result directly
527	* from a 8-bit register without an additional AND instruction.
528	* See also @bugref{10687}. */
529	#define IEMTLB_ENTRY_COUNT 256
530	#define IEMTLB_ENTRY_COUNT_AS_POWER_OF_TWO 8
531	AssertCompile(RT_BIT_32(IEMTLB_ENTRY_COUNT_AS_POWER_OF_TWO) == IEMTLB_ENTRY_COUNT);
532
533	/**
534	* An IEM TLB.
535	*
536	* We've got two of these, one for data and one for instructions.
537	*/
538	typedef struct IEMTLB
539	{
540	/** The TLB revision.
541	* This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
542	* by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
543	* the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
544	* (The revision zero indicates an invalid TLB entry.)
545	*
546	* The initial value is choosen to cause an early wraparound. */
547	uint64_t uTlbRevision;
548	/** The TLB physical address revision - shadow of PGM variable.
549	*
550	* This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
551	* incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
552	* a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
553	* as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
554	*
555	* The initial value is choosen to cause an early wraparound. */
556	uint64_t volatile uTlbPhysRev;
557
558	/* Statistics: */
559
560	/** TLB hits in IEMAll.cpp code (IEM_WITH_TLB_STATISTICS only; both).
561	* @note For the data TLB this is only used in iemMemMap and and for direct (i.e.
562	* not via safe read/write path) calls to iemMemMapJmp. */
563	uint64_t cTlbCoreHits;
564	/** Safe read/write TLB hits in iemMemMapJmp (IEM_WITH_TLB_STATISTICS
565	* only; data tlb only). */
566	uint64_t cTlbSafeHits;
567	/** TLB hits in IEMAllMemRWTmplInline.cpp.h (data + IEM_WITH_TLB_STATISTICS only). */
568	uint64_t cTlbInlineCodeHits;
569
570	/** TLB misses in IEMAll.cpp code (both).
571	* @note For the data TLB this is only used in iemMemMap and for direct (i.e.
572	* not via safe read/write path) calls to iemMemMapJmp. So,
573	* for the data TLB this more like 'other misses', while for the code
574	* TLB is all misses. */
575	uint64_t cTlbCoreMisses;
576	/** Safe read/write TLB misses in iemMemMapJmp (so data only). */
577	uint64_t cTlbSafeMisses;
578	/** Safe read path taken (data only). */
579	uint64_t cTlbSafeReadPath;
580	/** Safe write path taken (data only). */
581	uint64_t cTlbSafeWritePath;
582
583	/** @name Details for native code TLB misses.
584	* @note These counts are included in the above counters (cTlbSafeReadPath,
585	* cTlbSafeWritePath, cTlbInlineCodeHits).
586	* @{ */
587	/** TLB misses in native code due to tag mismatch. */
588	STAMCOUNTER cTlbNativeMissTag;
589	/** TLB misses in native code due to flags or physical revision mismatch. */
590	STAMCOUNTER cTlbNativeMissFlagsAndPhysRev;
591	/** TLB misses in native code due to misaligned access. */
592	STAMCOUNTER cTlbNativeMissAlignment;
593	/** TLB misses in native code due to cross page access. */
594	uint32_t cTlbNativeMissCrossPage;
595	/** TLB misses in native code due to non-canonical address. */
596	uint32_t cTlbNativeMissNonCanonical;
597	/** @} */
598
599	/** Slow read path (code only). */
600	uint32_t cTlbSlowCodeReadPath;
601
602	/** Alignment padding. */
603	uint32_t au32Padding[5];
604
605	/** The TLB entries. */
606	IEMTLBENTRY aEntries[IEMTLB_ENTRY_COUNT];
607	} IEMTLB;
608	AssertCompileSizeAlignment(IEMTLB, 64);
609	/** IEMTLB::uTlbRevision increment. */
610	#define IEMTLB_REVISION_INCR RT_BIT_64(36)
611	/** IEMTLB::uTlbRevision mask. */
612	#define IEMTLB_REVISION_MASK (~(RT_BIT_64(36) - 1))
613	/** IEMTLB::uTlbPhysRev increment.
614	* @sa IEMTLBE_F_PHYS_REV */
615	#define IEMTLB_PHYS_REV_INCR RT_BIT_64(10)
616	/**
617	* Calculates the TLB tag for a virtual address.
618	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
619	* @param a_pTlb The TLB.
620	* @param a_GCPtr The virtual address. Must be RTGCPTR or same size or
621	* the clearing of the top 16 bits won't work (if 32-bit
622	* we'll end up with mostly zeros).
623	*/
624	#define IEMTLB_CALC_TAG(a_pTlb, a_GCPtr) ( IEMTLB_CALC_TAG_NO_REV(a_GCPtr) \| (a_pTlb)->uTlbRevision )
625	/**
626	* Calculates the TLB tag for a virtual address but without TLB revision.
627	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
628	* @param a_GCPtr The virtual address. Must be RTGCPTR or same size or
629	* the clearing of the top 16 bits won't work (if 32-bit
630	* we'll end up with mostly zeros).
631	*/
632	#define IEMTLB_CALC_TAG_NO_REV(a_GCPtr) ( (((a_GCPtr) << 16) >> (GUEST_PAGE_SHIFT + 16)) )
633	/**
634	* Converts a TLB tag value into a TLB index.
635	* @returns Index into IEMTLB::aEntries.
636	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
637	*/
638	#if IEMTLB_ENTRY_COUNT == 256
639	# define IEMTLB_TAG_TO_INDEX(a_uTag) ( (uint8_t)(a_uTag) )
640	#else
641	# define IEMTLB_TAG_TO_INDEX(a_uTag) ( (a_uTag) & (IEMTLB_ENTRY_COUNT - 1U) )
642	AssertCompile(RT_IS_POWER_OF_TWO(IEMTLB_ENTRY_COUNT));
643	#endif
644	/**
645	* Converts a TLB tag value into a TLB index.
646	* @returns Index into IEMTLB::aEntries.
647	* @param a_pTlb The TLB.
648	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
649	*/
650	#define IEMTLB_TAG_TO_ENTRY(a_pTlb, a_uTag) ( &(a_pTlb)->aEntries[IEMTLB_TAG_TO_INDEX(a_uTag)] )
651
652
653	/** @name IEM_MC_F_XXX - MC block flags/clues.
654	* @todo Merge with IEM_CIMPL_F_XXX
655	* @{ */
656	#define IEM_MC_F_ONLY_8086 RT_BIT_32(0)
657	#define IEM_MC_F_MIN_186 RT_BIT_32(1)
658	#define IEM_MC_F_MIN_286 RT_BIT_32(2)
659	#define IEM_MC_F_NOT_286_OR_OLDER IEM_MC_F_MIN_386
660	#define IEM_MC_F_MIN_386 RT_BIT_32(3)
661	#define IEM_MC_F_MIN_486 RT_BIT_32(4)
662	#define IEM_MC_F_MIN_PENTIUM RT_BIT_32(5)
663	#define IEM_MC_F_MIN_PENTIUM_II IEM_MC_F_MIN_PENTIUM
664	#define IEM_MC_F_MIN_CORE IEM_MC_F_MIN_PENTIUM
665	#define IEM_MC_F_64BIT RT_BIT_32(6)
666	#define IEM_MC_F_NOT_64BIT RT_BIT_32(7)
667	/** This is set by IEMAllN8vePython.py to indicate a variation without the
668	* flags-clearing-and-checking, when there is also a variation with that.
669	* @note Do not use this manully, it's only for python and for testing in
670	* the native recompiler! */
671	#define IEM_MC_F_WITHOUT_FLAGS RT_BIT_32(8)
672	/** @} */
673
674	/** @name IEM_CIMPL_F_XXX - State change clues for CIMPL calls.
675	*
676	* These clues are mainly for the recompiler, so that it can emit correct code.
677	*
678	* They are processed by the python script and which also automatically
679	* calculates flags for MC blocks based on the statements, extending the use of
680	* these flags to describe MC block behavior to the recompiler core. The python
681	* script pass the flags to the IEM_MC2_END_EMIT_CALLS macro, but mainly for
682	* error checking purposes. The script emits the necessary fEndTb = true and
683	* similar statements as this reduces compile time a tiny bit.
684	*
685	* @{ */
686	/** Flag set if direct branch, clear if absolute or indirect. */
687	#define IEM_CIMPL_F_BRANCH_DIRECT RT_BIT_32(0)
688	/** Flag set if indirect branch, clear if direct or relative.
689	* This is also used for all system control transfers (SYSCALL, SYSRET, INT, ++)
690	* as well as for return instructions (RET, IRET, RETF). */
691	#define IEM_CIMPL_F_BRANCH_INDIRECT RT_BIT_32(1)
692	/** Flag set if relative branch, clear if absolute or indirect. */
693	#define IEM_CIMPL_F_BRANCH_RELATIVE RT_BIT_32(2)
694	/** Flag set if conditional branch, clear if unconditional. */
695	#define IEM_CIMPL_F_BRANCH_CONDITIONAL RT_BIT_32(3)
696	/** Flag set if it's a far branch (changes CS). */
697	#define IEM_CIMPL_F_BRANCH_FAR RT_BIT_32(4)
698	/** Convenience: Testing any kind of branch. */
699	#define IEM_CIMPL_F_BRANCH_ANY (IEM_CIMPL_F_BRANCH_DIRECT \| IEM_CIMPL_F_BRANCH_INDIRECT \| IEM_CIMPL_F_BRANCH_RELATIVE)
700
701	/** Execution flags may change (IEMCPU::fExec). */
702	#define IEM_CIMPL_F_MODE RT_BIT_32(5)
703	/** May change significant portions of RFLAGS. */
704	#define IEM_CIMPL_F_RFLAGS RT_BIT_32(6)
705	/** May change the status bits (X86_EFL_STATUS_BITS) in RFLAGS. */
706	#define IEM_CIMPL_F_STATUS_FLAGS RT_BIT_32(7)
707	/** May trigger interrupt shadowing. */
708	#define IEM_CIMPL_F_INHIBIT_SHADOW RT_BIT_32(8)
709	/** May enable interrupts, so recheck IRQ immediately afterwards executing
710	* the instruction. */
711	#define IEM_CIMPL_F_CHECK_IRQ_AFTER RT_BIT_32(9)
712	/** May disable interrupts, so recheck IRQ immediately before executing the
713	* instruction. */
714	#define IEM_CIMPL_F_CHECK_IRQ_BEFORE RT_BIT_32(10)
715	/** Convenience: Check for IRQ both before and after an instruction. */
716	#define IEM_CIMPL_F_CHECK_IRQ_BEFORE_AND_AFTER (IEM_CIMPL_F_CHECK_IRQ_BEFORE \| IEM_CIMPL_F_CHECK_IRQ_AFTER)
717	/** May trigger a VM exit (treated like IEM_CIMPL_F_MODE atm). */
718	#define IEM_CIMPL_F_VMEXIT RT_BIT_32(11)
719	/** May modify FPU state.
720	* @todo Not sure if this is useful yet. */
721	#define IEM_CIMPL_F_FPU RT_BIT_32(12)
722	/** REP prefixed instruction which may yield before updating PC.
723	* @todo Not sure if this is useful, REP functions now return non-zero
724	* status if they don't update the PC. */
725	#define IEM_CIMPL_F_REP RT_BIT_32(13)
726	/** I/O instruction.
727	* @todo Not sure if this is useful yet. */
728	#define IEM_CIMPL_F_IO RT_BIT_32(14)
729	/** Force end of TB after the instruction. */
730	#define IEM_CIMPL_F_END_TB RT_BIT_32(15)
731	/** Flag set if a branch may also modify the stack (push/pop return address). */
732	#define IEM_CIMPL_F_BRANCH_STACK RT_BIT_32(16)
733	/** Flag set if a branch may also modify the stack (push/pop return address)
734	* and switch it (load/restore SS:RSP). */
735	#define IEM_CIMPL_F_BRANCH_STACK_FAR RT_BIT_32(17)
736	/** Convenience: Raise exception (technically unnecessary, since it shouldn't return VINF_SUCCESS). */
737	#define IEM_CIMPL_F_XCPT \
738	(IEM_CIMPL_F_BRANCH_INDIRECT \| IEM_CIMPL_F_BRANCH_FAR \| IEM_CIMPL_F_BRANCH_STACK_FAR \
739	\| IEM_CIMPL_F_MODE \| IEM_CIMPL_F_RFLAGS \| IEM_CIMPL_F_VMEXIT)
740
741	/** The block calls a C-implementation instruction function with two implicit arguments.
742	* Mutually exclusive with IEM_CIMPL_F_CALLS_AIMPL and
743	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
744	* @note The python scripts will add this if missing. */
745	#define IEM_CIMPL_F_CALLS_CIMPL RT_BIT_32(18)
746	/** The block calls an ASM-implementation instruction function.
747	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL and
748	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
749	* @note The python scripts will add this if missing. */
750	#define IEM_CIMPL_F_CALLS_AIMPL RT_BIT_32(19)
751	/** The block calls an ASM-implementation instruction function with an implicit
752	* X86FXSTATE pointer argument.
753	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL, IEM_CIMPL_F_CALLS_AIMPL and
754	* IEM_CIMPL_F_CALLS_AIMPL_WITH_XSTATE.
755	* @note The python scripts will add this if missing. */
756	#define IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE RT_BIT_32(20)
757	/** The block calls an ASM-implementation instruction function with an implicit
758	* X86XSAVEAREA pointer argument.
759	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL, IEM_CIMPL_F_CALLS_AIMPL and
760	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
761	* @note No different from IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE, so same value.
762	* @note The python scripts will add this if missing. */
763	#define IEM_CIMPL_F_CALLS_AIMPL_WITH_XSTATE IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE
764	/** @} */
765
766
767	/** @name IEM_F_XXX - Execution mode flags (IEMCPU::fExec, IEMTB::fFlags).
768	*
769	* These flags are set when entering IEM and adjusted as code is executed, such
770	* that they will always contain the current values as instructions are
771	* finished.
772	*
773	* In recompiled execution mode, (most of) these flags are included in the
774	* translation block selection key and stored in IEMTB::fFlags alongside the
775	* IEMTB_F_XXX flags. The latter flags uses bits 31 thru 24, which are all zero
776	* in IEMCPU::fExec.
777	*
778	* @{ */
779	/** Mode: The block target mode mask. */
780	#define IEM_F_MODE_MASK UINT32_C(0x0000001f)
781	/** Mode: The IEMMODE part of the IEMTB_F_MODE_MASK value. */
782	#define IEM_F_MODE_CPUMODE_MASK UINT32_C(0x00000003)
783	/** X86 Mode: Bit used to indicating pre-386 CPU in 16-bit mode (for eliminating
784	* conditional in EIP/IP updating), and flat wide open CS, SS, DS, and ES in
785	* 32-bit mode (for simplifying most memory accesses). */
786	#define IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK UINT32_C(0x00000004)
787	/** X86 Mode: Bit indicating protected mode, real mode (or SMM) when not set. */
788	#define IEM_F_MODE_X86_PROT_MASK UINT32_C(0x00000008)
789	/** X86 Mode: Bit used to indicate virtual 8086 mode (only 16-bit). */
790	#define IEM_F_MODE_X86_V86_MASK UINT32_C(0x00000010)
791
792	/** X86 Mode: 16-bit on 386 or later. */
793	#define IEM_F_MODE_X86_16BIT UINT32_C(0x00000000)
794	/** X86 Mode: 80286, 80186 and 8086/88 targetting blocks (EIP update opt). */
795	#define IEM_F_MODE_X86_16BIT_PRE_386 UINT32_C(0x00000004)
796	/** X86 Mode: 16-bit protected mode on 386 or later. */
797	#define IEM_F_MODE_X86_16BIT_PROT UINT32_C(0x00000008)
798	/** X86 Mode: 16-bit protected mode on 386 or later. */
799	#define IEM_F_MODE_X86_16BIT_PROT_PRE_386 UINT32_C(0x0000000c)
800	/** X86 Mode: 16-bit virtual 8086 protected mode (on 386 or later). */
801	#define IEM_F_MODE_X86_16BIT_PROT_V86 UINT32_C(0x00000018)
802
803	/** X86 Mode: 32-bit on 386 or later. */
804	#define IEM_F_MODE_X86_32BIT UINT32_C(0x00000001)
805	/** X86 Mode: 32-bit mode with wide open flat CS, SS, DS and ES. */
806	#define IEM_F_MODE_X86_32BIT_FLAT UINT32_C(0x00000005)
807	/** X86 Mode: 32-bit protected mode. */
808	#define IEM_F_MODE_X86_32BIT_PROT UINT32_C(0x00000009)
809	/** X86 Mode: 32-bit protected mode with wide open flat CS, SS, DS and ES. */
810	#define IEM_F_MODE_X86_32BIT_PROT_FLAT UINT32_C(0x0000000d)
811
812	/** X86 Mode: 64-bit (includes protected, but not the flat bit). */
813	#define IEM_F_MODE_X86_64BIT UINT32_C(0x0000000a)
814
815	/** X86 Mode: Checks if @a a_fExec represent a FLAT mode. */
816	#define IEM_F_MODE_X86_IS_FLAT(a_fExec) ( ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_64BIT \
817	\|\| ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_32BIT_PROT_FLAT \
818	\|\| ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_32BIT_FLAT)
819
820	/** Bypass access handlers when set. */
821	#define IEM_F_BYPASS_HANDLERS UINT32_C(0x00010000)
822	/** Have pending hardware instruction breakpoints. */
823	#define IEM_F_PENDING_BRK_INSTR UINT32_C(0x00020000)
824	/** Have pending hardware data breakpoints. */
825	#define IEM_F_PENDING_BRK_DATA UINT32_C(0x00040000)
826
827	/** X86: Have pending hardware I/O breakpoints. */
828	#define IEM_F_PENDING_BRK_X86_IO UINT32_C(0x00000400)
829	/** X86: Disregard the lock prefix (implied or not) when set. */
830	#define IEM_F_X86_DISREGARD_LOCK UINT32_C(0x00000800)
831
832	/** Pending breakpoint mask (what iemCalcExecDbgFlags works out). */
833	#define IEM_F_PENDING_BRK_MASK (IEM_F_PENDING_BRK_INSTR \| IEM_F_PENDING_BRK_DATA \| IEM_F_PENDING_BRK_X86_IO)
834
835	/** Caller configurable options. */
836	#define IEM_F_USER_OPTS (IEM_F_BYPASS_HANDLERS \| IEM_F_X86_DISREGARD_LOCK)
837
838	/** X86: The current protection level (CPL) shift factor. */
839	#define IEM_F_X86_CPL_SHIFT 8
840	/** X86: The current protection level (CPL) mask. */
841	#define IEM_F_X86_CPL_MASK UINT32_C(0x00000300)
842	/** X86: The current protection level (CPL) shifted mask. */
843	#define IEM_F_X86_CPL_SMASK UINT32_C(0x00000003)
844
845	/** X86: Alignment checks enabled (CR0.AM=1 & EFLAGS.AC=1). */
846	#define IEM_F_X86_AC UINT32_C(0x00080000)
847
848	/** X86 execution context.
849	* The IEM_F_X86_CTX_XXX values are individual flags that can be combined (with
850	* the exception of IEM_F_X86_CTX_NORMAL). This allows running VMs from SMM
851	* mode. */
852	#define IEM_F_X86_CTX_MASK UINT32_C(0x0000f000)
853	/** X86 context: Plain regular execution context. */
854	#define IEM_F_X86_CTX_NORMAL UINT32_C(0x00000000)
855	/** X86 context: VT-x enabled. */
856	#define IEM_F_X86_CTX_VMX UINT32_C(0x00001000)
857	/** X86 context: AMD-V enabled. */
858	#define IEM_F_X86_CTX_SVM UINT32_C(0x00002000)
859	/** X86 context: In AMD-V or VT-x guest mode. */
860	#define IEM_F_X86_CTX_IN_GUEST UINT32_C(0x00004000)
861	/** X86 context: System management mode (SMM). */
862	#define IEM_F_X86_CTX_SMM UINT32_C(0x00008000)
863
864	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
865	* iemRegFinishClearingRF() most for most situations (CPUMCTX_DBG_HIT_DRX_MASK
866	* and CPUMCTX_DBG_DBGF_MASK are covered by the IEM_F_PENDING_BRK_XXX bits
867	* alread). */
868
869	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
870	* iemRegFinishClearingRF() most for most situations
871	* (CPUMCTX_DBG_HIT_DRX_MASK and CPUMCTX_DBG_DBGF_MASK are covered by
872	* the IEM_F_PENDING_BRK_XXX bits alread). */
873
874	/** @} */
875
876
877	/** @name IEMTB_F_XXX - Translation block flags (IEMTB::fFlags).
878	*
879	* Extends the IEM_F_XXX flags (subject to IEMTB_F_IEM_F_MASK) to make up the
880	* translation block flags. The combined flag mask (subject to
881	* IEMTB_F_KEY_MASK) is used as part of the lookup key for translation blocks.
882	*
883	* @{ */
884	/** Mask of IEM_F_XXX flags included in IEMTB_F_XXX. */
885	#define IEMTB_F_IEM_F_MASK UINT32_C(0x00ffffff)
886
887	/** Type: The block type mask. */
888	#define IEMTB_F_TYPE_MASK UINT32_C(0x03000000)
889	/** Type: Purly threaded recompiler (via tables). */
890	#define IEMTB_F_TYPE_THREADED UINT32_C(0x01000000)
891	/** Type: Native recompilation. */
892	#define IEMTB_F_TYPE_NATIVE UINT32_C(0x02000000)
893
894	/** Set when we're starting the block in an "interrupt shadow".
895	* We don't need to distingish between the two types of this mask, thus the one.
896	* @see CPUMCTX_INHIBIT_SHADOW, CPUMIsInInterruptShadow() */
897	#define IEMTB_F_INHIBIT_SHADOW UINT32_C(0x04000000)
898	/** Set when we're currently inhibiting NMIs
899	* @see CPUMCTX_INHIBIT_NMI, CPUMAreInterruptsInhibitedByNmi() */
900	#define IEMTB_F_INHIBIT_NMI UINT32_C(0x08000000)
901
902	/** Checks that EIP/IP is wihin CS.LIM before each instruction. Used when
903	* we're close the limit before starting a TB, as determined by
904	* iemGetTbFlagsForCurrentPc(). */
905	#define IEMTB_F_CS_LIM_CHECKS UINT32_C(0x10000000)
906
907	/** Mask of the IEMTB_F_XXX flags that are part of the TB lookup key.
908	*
909	* @note We skip all of IEM_F_X86_CTX_MASK, with the exception of SMM (which we
910	* don't implement), because we don't currently generate any context
911	* specific code - that's all handled in CIMPL functions.
912	*
913	* For the threaded recompiler we don't generate any CPL specific code
914	* either, but the native recompiler does for memory access (saves getting
915	* the CPL from fExec and turning it into IEMTLBE_F_PT_NO_USER).
916	* Since most OSes will not share code between rings, this shouldn't
917	* have any real effect on TB/memory/recompiling load.
918	*/
919	#define IEMTB_F_KEY_MASK ((UINT32_MAX & ~(IEM_F_X86_CTX_MASK \| IEMTB_F_TYPE_MASK)) \| IEM_F_X86_CTX_SMM)
920	/** @} */
921
922	AssertCompile( (IEM_F_MODE_X86_16BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
923	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
924	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_PROT_MASK));
925	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_V86_MASK));
926	AssertCompile( (IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
927	AssertCompile( IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
928	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_PROT_MASK));
929	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
930	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
931	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
932	AssertCompile( IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
933	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_V86_MASK));
934	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
935	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
936	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_PROT_MASK);
937	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
938	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_PROT_MASK);
939	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
940	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_V86_MASK);
941
942	AssertCompile( (IEM_F_MODE_X86_32BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
943	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
944	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_PROT_MASK));
945	AssertCompile( (IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
946	AssertCompile( IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
947	AssertCompile(!(IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_PROT_MASK));
948	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
949	AssertCompile(!(IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
950	AssertCompile( IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
951	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
952	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
953	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_PROT_MASK);
954
955	AssertCompile( (IEM_F_MODE_X86_64BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_64BIT);
956	AssertCompile( IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_PROT_MASK);
957	AssertCompile(!(IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
958
959	/** Native instruction type for use with the native code generator.
960	* This is a byte (uint8_t) for x86 and amd64 and uint32_t for the other(s). */
961	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
962	typedef uint8_t IEMNATIVEINSTR;
963	#else
964	typedef uint32_t IEMNATIVEINSTR;
965	#endif
966	/** Pointer to a native instruction unit. */
967	typedef IEMNATIVEINSTR *PIEMNATIVEINSTR;
968	/** Pointer to a const native instruction unit. */
969	typedef IEMNATIVEINSTR const *PCIEMNATIVEINSTR;
970
971	/**
972	* A call for the threaded call table.
973	*/
974	typedef struct IEMTHRDEDCALLENTRY
975	{
976	/** The function to call (IEMTHREADEDFUNCS). */
977	uint16_t enmFunction;
978
979	/** Instruction number in the TB (for statistics). */
980	uint8_t idxInstr;
981	/** The opcode length. */
982	uint8_t cbOpcode;
983	/** Offset into IEMTB::pabOpcodes. */
984	uint16_t offOpcode;
985
986	/** TB lookup table index (7 bits) and large size (1 bits).
987	*
988	* The default size is 1 entry, but for indirect calls and returns we set the
989	* top bit and allocate 4 (IEM_TB_LOOKUP_TAB_LARGE_SIZE) entries. The large
990	* tables uses RIP for selecting the entry to use, as it is assumed a hash table
991	* lookup isn't that slow compared to sequentially trying out 4 TBs.
992	*
993	* By default lookup table entry 0 for a TB is reserved as a fallback for
994	* calltable entries w/o explicit entreis, so this member will be non-zero if
995	* there is a lookup entry associated with this call.
996	*
997	* @sa IEM_TB_LOOKUP_TAB_GET_SIZE, IEM_TB_LOOKUP_TAB_GET_IDX
998	*/
999	uint8_t uTbLookup;
1000
1001	/** Unused atm. */
1002	uint8_t uUnused0;
1003
1004	/** Generic parameters. */
1005	uint64_t auParams[3];
1006	} IEMTHRDEDCALLENTRY;
1007	AssertCompileSize(IEMTHRDEDCALLENTRY, sizeof(uint64_t) * 4);
1008	/** Pointer to a threaded call entry. */
1009	typedef struct IEMTHRDEDCALLENTRY *PIEMTHRDEDCALLENTRY;
1010	/** Pointer to a const threaded call entry. */
1011	typedef IEMTHRDEDCALLENTRY const *PCIEMTHRDEDCALLENTRY;
1012
1013	/** The number of TB lookup table entries for a large allocation
1014	* (IEMTHRDEDCALLENTRY::uTbLookup bit 7 set). */
1015	#define IEM_TB_LOOKUP_TAB_LARGE_SIZE 4
1016	/** Get the lookup table size from IEMTHRDEDCALLENTRY::uTbLookup. */
1017	#define IEM_TB_LOOKUP_TAB_GET_SIZE(a_uTbLookup) (!((a_uTbLookup) & 0x80) ? 1 : IEM_TB_LOOKUP_TAB_LARGE_SIZE)
1018	/** Get the first lookup table index from IEMTHRDEDCALLENTRY::uTbLookup. */
1019	#define IEM_TB_LOOKUP_TAB_GET_IDX(a_uTbLookup) ((a_uTbLookup) & 0x7f)
1020	/** Get the lookup table index from IEMTHRDEDCALLENTRY::uTbLookup and RIP. */
1021	#define IEM_TB_LOOKUP_TAB_GET_IDX_WITH_RIP(a_uTbLookup, a_Rip) \
1022	(!((a_uTbLookup) & 0x80) ? (a_uTbLookup) & 0x7f : ((a_uTbLookup) & 0x7f) + ((a_Rip) & (IEM_TB_LOOKUP_TAB_LARGE_SIZE - 1)) )
1023
1024	/** Make a IEMTHRDEDCALLENTRY::uTbLookup value. */
1025	#define IEM_TB_LOOKUP_TAB_MAKE(a_idxTable, a_fLarge) ((a_idxTable) \| ((a_fLarge) ? 0x80 : 0))
1026
1027	/**
1028	* Native IEM TB 'function' typedef.
1029	*
1030	* This will throw/longjmp on occation.
1031	*
1032	* @note AMD64 doesn't have that many non-volatile registers and does sport
1033	* 32-bit address displacments, so we don't need pCtx.
1034	*
1035	* On ARM64 pCtx allows us to directly address the whole register
1036	* context without requiring a separate indexing register holding the
1037	* offset. This saves an instruction loading the offset for each guest
1038	* CPU context access, at the cost of a non-volatile register.
1039	* Fortunately, ARM64 has quite a lot more registers.
1040	*/
1041	typedef
1042	#ifdef RT_ARCH_AMD64
1043	int FNIEMTBNATIVE(PVMCPUCC pVCpu)
1044	#else
1045	int FNIEMTBNATIVE(PVMCPUCC pVCpu, PCPUMCTX pCtx)
1046	#endif
1047	#if RT_CPLUSPLUS_PREREQ(201700)
1048	IEM_NOEXCEPT_MAY_LONGJMP
1049	#endif
1050	;
1051	/** Pointer to a native IEM TB entry point function.
1052	* This will throw/longjmp on occation. */
1053	typedef FNIEMTBNATIVE *PFNIEMTBNATIVE;
1054
1055
1056	/**
1057	* Translation block debug info entry type.
1058	*/
1059	typedef enum IEMTBDBGENTRYTYPE
1060	{
1061	kIemTbDbgEntryType_Invalid = 0,
1062	/** The entry is for marking a native code position.
1063	* Entries following this all apply to this position. */
1064	kIemTbDbgEntryType_NativeOffset,
1065	/** The entry is for a new guest instruction. */
1066	kIemTbDbgEntryType_GuestInstruction,
1067	/** Marks the start of a threaded call. */
1068	kIemTbDbgEntryType_ThreadedCall,
1069	/** Marks the location of a label. */
1070	kIemTbDbgEntryType_Label,
1071	/** Info about a host register shadowing a guest register. */
1072	kIemTbDbgEntryType_GuestRegShadowing,
1073	#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
1074	/** Info about a host SIMD register shadowing a guest SIMD register. */
1075	kIemTbDbgEntryType_GuestSimdRegShadowing,
1076	#endif
1077	#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING
1078	/** Info about a delayed RIP update. */
1079	kIemTbDbgEntryType_DelayedPcUpdate,
1080	#endif
1081	#if defined(IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK) \|\| defined(IEMNATIVE_WITH_SIMD_REG_ALLOCATOR)
1082	/** Info about a shadowed guest register becoming dirty. */
1083	kIemTbDbgEntryType_GuestRegDirty,
1084	/** Info about register writeback/flush oepration. */
1085	kIemTbDbgEntryType_GuestRegWriteback,
1086	#endif
1087	kIemTbDbgEntryType_End
1088	} IEMTBDBGENTRYTYPE;
1089
1090	/**
1091	* Translation block debug info entry.
1092	*/
1093	typedef union IEMTBDBGENTRY
1094	{
1095	/** Plain 32-bit view. */
1096	uint32_t u;
1097
1098	/** Generic view for getting at the type field. */
1099	struct
1100	{
1101	/** IEMTBDBGENTRYTYPE */
1102	uint32_t uType : 4;
1103	uint32_t uTypeSpecific : 28;
1104	} Gen;
1105
1106	struct
1107	{
1108	/** kIemTbDbgEntryType_ThreadedCall1. */
1109	uint32_t uType : 4;
1110	/** Native code offset. */
1111	uint32_t offNative : 28;
1112	} NativeOffset;
1113
1114	struct
1115	{
1116	/** kIemTbDbgEntryType_GuestInstruction. */
1117	uint32_t uType : 4;
1118	uint32_t uUnused : 4;
1119	/** The IEM_F_XXX flags. */
1120	uint32_t fExec : 24;
1121	} GuestInstruction;
1122
1123	struct
1124	{
1125	/* kIemTbDbgEntryType_ThreadedCall. */
1126	uint32_t uType : 4;
1127	/** Set if the call was recompiled to native code, clear if just calling
1128	* threaded function. */
1129	uint32_t fRecompiled : 1;
1130	uint32_t uUnused : 11;
1131	/** The threaded call number (IEMTHREADEDFUNCS). */
1132	uint32_t enmCall : 16;
1133	} ThreadedCall;
1134
1135	struct
1136	{
1137	/* kIemTbDbgEntryType_Label. */
1138	uint32_t uType : 4;
1139	uint32_t uUnused : 4;
1140	/** The label type (IEMNATIVELABELTYPE). */
1141	uint32_t enmLabel : 8;
1142	/** The label data. */
1143	uint32_t uData : 16;
1144	} Label;
1145
1146	struct
1147	{
1148	/* kIemTbDbgEntryType_GuestRegShadowing. */
1149	uint32_t uType : 4;
1150	uint32_t uUnused : 4;
1151	/** The guest register being shadowed (IEMNATIVEGSTREG). */
1152	uint32_t idxGstReg : 8;
1153	/** The host new register number, UINT8_MAX if dropped. */
1154	uint32_t idxHstReg : 8;
1155	/** The previous host register number, UINT8_MAX if new. */
1156	uint32_t idxHstRegPrev : 8;
1157	} GuestRegShadowing;
1158
1159	#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
1160	struct
1161	{
1162	/* kIemTbDbgEntryType_GuestSimdRegShadowing. */
1163	uint32_t uType : 4;
1164	uint32_t uUnused : 4;
1165	/** The guest register being shadowed (IEMNATIVEGSTSIMDREG). */
1166	uint32_t idxGstSimdReg : 8;
1167	/** The host new register number, UINT8_MAX if dropped. */
1168	uint32_t idxHstSimdReg : 8;
1169	/** The previous host register number, UINT8_MAX if new. */
1170	uint32_t idxHstSimdRegPrev : 8;
1171	} GuestSimdRegShadowing;
1172	#endif
1173
1174	#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING
1175	struct
1176	{
1177	/* kIemTbDbgEntryType_DelayedPcUpdate. */
1178	uint32_t uType : 4;
1179	/* The instruction offset added to the program counter. */
1180	uint32_t offPc : 14;
1181	/** Number of instructions skipped. */
1182	uint32_t cInstrSkipped : 14;
1183	} DelayedPcUpdate;
1184	#endif
1185
1186	#if defined(IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK) \|\| defined(IEMNATIVE_WITH_SIMD_REG_ALLOCATOR)
1187	struct
1188	{
1189	/* kIemTbDbgEntryType_GuestRegDirty. */
1190	uint32_t uType : 4;
1191	uint32_t uUnused : 11;
1192	/** Flag whether this is about a SIMD (true) or general (false) register. */
1193	uint32_t fSimdReg : 1;
1194	/** The guest register index being marked as dirty. */
1195	uint32_t idxGstReg : 8;
1196	/** The host register number this register is shadowed in .*/
1197	uint32_t idxHstReg : 8;
1198	} GuestRegDirty;
1199
1200	struct
1201	{
1202	/* kIemTbDbgEntryType_GuestRegWriteback. */
1203	uint32_t uType : 4;
1204	/** Flag whether this is about a SIMD (true) or general (false) register flush. */
1205	uint32_t fSimdReg : 1;
1206	/** The mask shift. */
1207	uint32_t cShift : 2;
1208	/** The guest register mask being written back. */
1209	uint32_t fGstReg : 25;
1210	} GuestRegWriteback;
1211	#endif
1212
1213	} IEMTBDBGENTRY;
1214	AssertCompileSize(IEMTBDBGENTRY, sizeof(uint32_t));
1215	/** Pointer to a debug info entry. */
1216	typedef IEMTBDBGENTRY *PIEMTBDBGENTRY;
1217	/** Pointer to a const debug info entry. */
1218	typedef IEMTBDBGENTRY const *PCIEMTBDBGENTRY;
1219
1220	/**
1221	* Translation block debug info.
1222	*/
1223	typedef struct IEMTBDBG
1224	{
1225	/** Number of entries in aEntries. */
1226	uint32_t cEntries;
1227	/** The offset of the last kIemTbDbgEntryType_NativeOffset record. */
1228	uint32_t offNativeLast;
1229	/** Debug info entries. */
1230	RT_FLEXIBLE_ARRAY_EXTENSION
1231	IEMTBDBGENTRY aEntries[RT_FLEXIBLE_ARRAY];
1232	} IEMTBDBG;
1233	/** Pointer to TB debug info. */
1234	typedef IEMTBDBG *PIEMTBDBG;
1235	/** Pointer to const TB debug info. */
1236	typedef IEMTBDBG const *PCIEMTBDBG;
1237
1238
1239	/**
1240	* Translation block.
1241	*
1242	* The current plan is to just keep TBs and associated lookup hash table private
1243	* to each VCpu as that simplifies TB removal greatly (no races) and generally
1244	* avoids using expensive atomic primitives for updating lists and stuff.
1245	*/
1246	#pragma pack(2) /* to prevent the Thrd structure from being padded unnecessarily */
1247	typedef struct IEMTB
1248	{
1249	/** Next block with the same hash table entry. */
1250	struct IEMTB *pNext;
1251	/** Usage counter. */
1252	uint32_t cUsed;
1253	/** The IEMCPU::msRecompilerPollNow last time it was used. */
1254	uint32_t msLastUsed;
1255
1256	/** @name What uniquely identifies the block.
1257	* @{ */
1258	RTGCPHYS GCPhysPc;
1259	/** IEMTB_F_XXX (i.e. IEM_F_XXX ++). */
1260	uint32_t fFlags;
1261	union
1262	{
1263	struct
1264	{
1265	/*< Relevant CS X86DESCATTR_XXX bits. /
1266	uint16_t fAttr;
1267	} x86;
1268	};
1269	/** @} */
1270
1271	/** Number of opcode ranges. */
1272	uint8_t cRanges;
1273	/** Statistics: Number of instructions in the block. */
1274	uint8_t cInstructions;
1275
1276	/** Type specific info. */
1277	union
1278	{
1279	struct
1280	{
1281	/** The call sequence table. */
1282	PIEMTHRDEDCALLENTRY paCalls;
1283	/** Number of calls in paCalls. */
1284	uint16_t cCalls;
1285	/** Number of calls allocated. */
1286	uint16_t cAllocated;
1287	} Thrd;
1288	struct
1289	{
1290	/** The native instructions (PFNIEMTBNATIVE). */
1291	PIEMNATIVEINSTR paInstructions;
1292	/** Number of instructions pointed to by paInstructions. */
1293	uint32_t cInstructions;
1294	} Native;
1295	/** Generic view for zeroing when freeing. */
1296	struct
1297	{
1298	uintptr_t uPtr;
1299	uint32_t uData;
1300	} Gen;
1301	};
1302
1303	/** The allocation chunk this TB belongs to. */
1304	uint8_t idxAllocChunk;
1305	/** The number of entries in the lookup table.
1306	* Because we're out of space, the TB lookup table is located before the
1307	* opcodes pointed to by pabOpcodes. */
1308	uint8_t cTbLookupEntries;
1309
1310	/** Number of bytes of opcodes stored in pabOpcodes.
1311	* @todo this field isn't really needed, aRanges keeps the actual info. */
1312	uint16_t cbOpcodes;
1313	/** Pointer to the opcode bytes this block was recompiled from.
1314	* This also points to the TB lookup table, which starts cTbLookupEntries
1315	* entries before the opcodes (we don't have room atm for another point). */
1316	uint8_t *pabOpcodes;
1317
1318	/** Debug info if enabled.
1319	* This is only generated by the native recompiler. */
1320	PIEMTBDBG pDbgInfo;
1321
1322	/* --- 64 byte cache line end --- */
1323
1324	/** Opcode ranges.
1325	*
1326	* The opcode checkers and maybe TLB loading functions will use this to figure
1327	* out what to do. The parameter will specify an entry and the opcode offset to
1328	* start at and the minimum number of bytes to verify (instruction length).
1329	*
1330	* When VT-x and AMD-V looks up the opcode bytes for an exitting instruction,
1331	* they'll first translate RIP (+ cbInstr - 1) to a physical address using the
1332	* code TLB (must have a valid entry for that address) and scan the ranges to
1333	* locate the corresponding opcodes. Probably.
1334	*/
1335	struct IEMTBOPCODERANGE
1336	{
1337	/** Offset within pabOpcodes. */
1338	uint16_t offOpcodes;
1339	/** Number of bytes. */
1340	uint16_t cbOpcodes;
1341	/** The page offset. */
1342	RT_GCC_EXTENSION
1343	uint16_t offPhysPage : 12;
1344	/** Unused bits. */
1345	RT_GCC_EXTENSION
1346	uint16_t u2Unused : 2;
1347	/** Index into GCPhysPc + aGCPhysPages for the physical page address. */
1348	RT_GCC_EXTENSION
1349	uint16_t idxPhysPage : 2;
1350	} aRanges[8];
1351
1352	/** Physical pages that this TB covers.
1353	* The GCPhysPc w/o page offset is element zero, so starting here with 1. */
1354	RTGCPHYS aGCPhysPages[2];
1355	} IEMTB;
1356	#pragma pack()
1357	AssertCompileMemberAlignment(IEMTB, GCPhysPc, sizeof(RTGCPHYS));
1358	AssertCompileMemberAlignment(IEMTB, Thrd, sizeof(void *));
1359	AssertCompileMemberAlignment(IEMTB, pabOpcodes, sizeof(void *));
1360	AssertCompileMemberAlignment(IEMTB, pDbgInfo, sizeof(void *));
1361	AssertCompileMemberAlignment(IEMTB, aGCPhysPages, sizeof(RTGCPHYS));
1362	AssertCompileMemberOffset(IEMTB, aRanges, 64);
1363	AssertCompileMemberSize(IEMTB, aRanges[0], 6);
1364	#if 1
1365	AssertCompileSize(IEMTB, 128);
1366	# define IEMTB_SIZE_IS_POWER_OF_TWO /*< The IEMTB size is a power of two. /
1367	#else
1368	AssertCompileSize(IEMTB, 168);
1369	# undef IEMTB_SIZE_IS_POWER_OF_TWO
1370	#endif
1371
1372	/** Pointer to a translation block. */
1373	typedef IEMTB *PIEMTB;
1374	/** Pointer to a const translation block. */
1375	typedef IEMTB const *PCIEMTB;
1376
1377	/** Gets address of the given TB lookup table entry. */
1378	#define IEMTB_GET_TB_LOOKUP_TAB_ENTRY(a_pTb, a_idx) \
1379	((PIEMTB )&(a_pTb)->pabOpcodes[-(int)((a_pTb)->cTbLookupEntries - (a_idx)) sizeof(PIEMTB)])
1380
1381	/**
1382	* Gets the physical address for a TB opcode range.
1383	*/
1384	DECL_FORCE_INLINE(RTGCPHYS) iemTbGetRangePhysPageAddr(PCIEMTB pTb, uint8_t idxRange)
1385	{
1386	Assert(idxRange < RT_MIN(pTb->cRanges, RT_ELEMENTS(pTb->aRanges)));
1387	uint8_t const idxPage = pTb->aRanges[idxRange].idxPhysPage;
1388	Assert(idxPage <= RT_ELEMENTS(pTb->aGCPhysPages));
1389	if (idxPage == 0)
1390	return pTb->GCPhysPc & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
1391	Assert(!(pTb->aGCPhysPages[idxPage - 1] & GUEST_PAGE_OFFSET_MASK));
1392	return pTb->aGCPhysPages[idxPage - 1];
1393	}
1394
1395
1396	/**
1397	* A chunk of memory in the TB allocator.
1398	*/
1399	typedef struct IEMTBCHUNK
1400	{
1401	/** Pointer to the translation blocks in this chunk. */
1402	PIEMTB paTbs;
1403	#ifdef IN_RING0
1404	/** Allocation handle. */
1405	RTR0MEMOBJ hMemObj;
1406	#endif
1407	} IEMTBCHUNK;
1408
1409	/**
1410	* A per-CPU translation block allocator.
1411	*
1412	* Because of how the IEMTBCACHE uses the lower 6 bits of the TB address to keep
1413	* the length of the collision list, and of course also for cache line alignment
1414	* reasons, the TBs must be allocated with at least 64-byte alignment.
1415	* Memory is there therefore allocated using one of the page aligned allocators.
1416	*
1417	*
1418	* To avoid wasting too much memory, it is allocated piecemeal as needed,
1419	* in chunks (IEMTBCHUNK) of 2 MiB or more. The TB has an 8-bit chunk index
1420	* that enables us to quickly calculate the allocation bitmap position when
1421	* freeing the translation block.
1422	*/
1423	typedef struct IEMTBALLOCATOR
1424	{
1425	/** Magic value (IEMTBALLOCATOR_MAGIC). */
1426	uint32_t uMagic;
1427
1428	#ifdef IEMTB_SIZE_IS_POWER_OF_TWO
1429	/** Mask corresponding to cTbsPerChunk - 1. */
1430	uint32_t fChunkMask;
1431	/** Shift count corresponding to cTbsPerChunk. */
1432	uint8_t cChunkShift;
1433	#else
1434	uint32_t uUnused;
1435	uint8_t bUnused;
1436	#endif
1437	/** Number of chunks we're allowed to allocate. */
1438	uint8_t cMaxChunks;
1439	/** Number of chunks currently populated. */
1440	uint16_t cAllocatedChunks;
1441	/** Number of translation blocks per chunk. */
1442	uint32_t cTbsPerChunk;
1443	/** Chunk size. */
1444	uint32_t cbPerChunk;
1445
1446	/** The maximum number of TBs. */
1447	uint32_t cMaxTbs;
1448	/** Total number of TBs in the populated chunks.
1449	* (cAllocatedChunks * cTbsPerChunk) */
1450	uint32_t cTotalTbs;
1451	/** The current number of TBs in use.
1452	* The number of free TBs: cAllocatedTbs - cInUseTbs; */
1453	uint32_t cInUseTbs;
1454	/** Statistics: Number of the cInUseTbs that are native ones. */
1455	uint32_t cNativeTbs;
1456	/** Statistics: Number of the cInUseTbs that are threaded ones. */
1457	uint32_t cThreadedTbs;
1458
1459	/** Where to start pruning TBs from when we're out.
1460	* See iemTbAllocatorAllocSlow for details. */
1461	uint32_t iPruneFrom;
1462	/** Hint about which bit to start scanning the bitmap from. */
1463	uint32_t iStartHint;
1464	/** Where to start pruning native TBs from when we're out of executable memory.
1465	* See iemTbAllocatorFreeupNativeSpace for details. */
1466	uint32_t iPruneNativeFrom;
1467	uint32_t uPadding;
1468
1469	/** Statistics: Number of TB allocation calls. */
1470	STAMCOUNTER StatAllocs;
1471	/** Statistics: Number of TB free calls. */
1472	STAMCOUNTER StatFrees;
1473	/** Statistics: Time spend pruning. */
1474	STAMPROFILE StatPrune;
1475	/** Statistics: Time spend pruning native TBs. */
1476	STAMPROFILE StatPruneNative;
1477
1478	/** The delayed free list (see iemTbAlloctorScheduleForFree). */
1479	PIEMTB pDelayedFreeHead;
1480
1481	/** Allocation chunks. */
1482	IEMTBCHUNK aChunks[256];
1483
1484	/** Allocation bitmap for all possible chunk chunks. */
1485	RT_FLEXIBLE_ARRAY_EXTENSION
1486	uint64_t bmAllocated[RT_FLEXIBLE_ARRAY];
1487	} IEMTBALLOCATOR;
1488	/** Pointer to a TB allocator. */
1489	typedef struct IEMTBALLOCATOR *PIEMTBALLOCATOR;
1490
1491	/** Magic value for the TB allocator (Emmet Harley Cohen). */
1492	#define IEMTBALLOCATOR_MAGIC UINT32_C(0x19900525)
1493
1494
1495	/**
1496	* A per-CPU translation block cache (hash table).
1497	*
1498	* The hash table is allocated once during IEM initialization and size double
1499	* the max TB count, rounded up to the nearest power of two (so we can use and
1500	* AND mask rather than a rest division when hashing).
1501	*/
1502	typedef struct IEMTBCACHE
1503	{
1504	/** Magic value (IEMTBCACHE_MAGIC). */
1505	uint32_t uMagic;
1506	/** Size of the hash table. This is a power of two. */
1507	uint32_t cHash;
1508	/** The mask corresponding to cHash. */
1509	uint32_t uHashMask;
1510	uint32_t uPadding;
1511
1512	/** @name Statistics
1513	* @{ */
1514	/** Number of collisions ever. */
1515	STAMCOUNTER cCollisions;
1516
1517	/** Statistics: Number of TB lookup misses. */
1518	STAMCOUNTER cLookupMisses;
1519	/** Statistics: Number of TB lookup hits via hash table (debug only). */
1520	STAMCOUNTER cLookupHits;
1521	/** Statistics: Number of TB lookup hits via TB associated lookup table (debug only). */
1522	STAMCOUNTER cLookupHitsViaTbLookupTable;
1523	STAMCOUNTER auPadding2[2];
1524	/** Statistics: Collision list length pruning. */
1525	STAMPROFILE StatPrune;
1526	/** @} */
1527
1528	/** The hash table itself.
1529	* @note The lower 6 bits of the pointer is used for keeping the collision
1530	* list length, so we can take action when it grows too long.
1531	* This works because TBs are allocated using a 64 byte (or
1532	* higher) alignment from page aligned chunks of memory, so the lower
1533	* 6 bits of the address will always be zero.
1534	* See IEMTBCACHE_PTR_COUNT_MASK, IEMTBCACHE_PTR_MAKE and friends.
1535	*/
1536	RT_FLEXIBLE_ARRAY_EXTENSION
1537	PIEMTB apHash[RT_FLEXIBLE_ARRAY];
1538	} IEMTBCACHE;
1539	/** Pointer to a per-CPU translation block cahce. */
1540	typedef IEMTBCACHE *PIEMTBCACHE;
1541
1542	/** Magic value for IEMTBCACHE (Johnny O'Neal). */
1543	#define IEMTBCACHE_MAGIC UINT32_C(0x19561010)
1544
1545	/** The collision count mask for IEMTBCACHE::apHash entries. */
1546	#define IEMTBCACHE_PTR_COUNT_MASK ((uintptr_t)0x3f)
1547	/** The max collision count for IEMTBCACHE::apHash entries before pruning. */
1548	#define IEMTBCACHE_PTR_MAX_COUNT ((uintptr_t)0x30)
1549	/** Combine a TB pointer and a collision list length into a value for an
1550	* IEMTBCACHE::apHash entry. */
1551	#define IEMTBCACHE_PTR_MAKE(a_pTb, a_cCount) (PIEMTB)((uintptr_t)(a_pTb) \| (a_cCount))
1552	/** Combine a TB pointer and a collision list length into a value for an
1553	* IEMTBCACHE::apHash entry. */
1554	#define IEMTBCACHE_PTR_GET_TB(a_pHashEntry) (PIEMTB)((uintptr_t)(a_pHashEntry) & ~IEMTBCACHE_PTR_COUNT_MASK)
1555	/** Combine a TB pointer and a collision list length into a value for an
1556	* IEMTBCACHE::apHash entry. */
1557	#define IEMTBCACHE_PTR_GET_COUNT(a_pHashEntry) ((uintptr_t)(a_pHashEntry) & IEMTBCACHE_PTR_COUNT_MASK)
1558
1559	/**
1560	* Calculates the hash table slot for a TB from physical PC address and TB flags.
1561	*/
1562	#define IEMTBCACHE_HASH(a_paCache, a_fTbFlags, a_GCPhysPc) \
1563	IEMTBCACHE_HASH_NO_KEY_MASK(a_paCache, (a_fTbFlags) & IEMTB_F_KEY_MASK, a_GCPhysPc)
1564
1565	/**
1566	* Calculates the hash table slot for a TB from physical PC address and TB
1567	* flags, ASSUMING the caller has applied IEMTB_F_KEY_MASK to @a a_fTbFlags.
1568	*/
1569	#define IEMTBCACHE_HASH_NO_KEY_MASK(a_paCache, a_fTbFlags, a_GCPhysPc) \
1570	(((uint32_t)(a_GCPhysPc) ^ (a_fTbFlags)) & (a_paCache)->uHashMask)
1571
1572
1573	/** @name IEMBRANCHED_F_XXX - Branched indicator (IEMCPU::fTbBranched).
1574	*
1575	* These flags parallels the main IEM_CIMPL_F_BRANCH_XXX flags.
1576	*
1577	* @{ */
1578	/** Value if no branching happened recently. */
1579	#define IEMBRANCHED_F_NO UINT8_C(0x00)
1580	/** Flag set if direct branch, clear if absolute or indirect. */
1581	#define IEMBRANCHED_F_DIRECT UINT8_C(0x01)
1582	/** Flag set if indirect branch, clear if direct or relative. */
1583	#define IEMBRANCHED_F_INDIRECT UINT8_C(0x02)
1584	/** Flag set if relative branch, clear if absolute or indirect. */
1585	#define IEMBRANCHED_F_RELATIVE UINT8_C(0x04)
1586	/** Flag set if conditional branch, clear if unconditional. */
1587	#define IEMBRANCHED_F_CONDITIONAL UINT8_C(0x08)
1588	/** Flag set if it's a far branch. */
1589	#define IEMBRANCHED_F_FAR UINT8_C(0x10)
1590	/** Flag set if the stack pointer is modified. */
1591	#define IEMBRANCHED_F_STACK UINT8_C(0x20)
1592	/** Flag set if the stack pointer and (maybe) the stack segment are modified. */
1593	#define IEMBRANCHED_F_STACK_FAR UINT8_C(0x40)
1594	/** Flag set (by IEM_MC_REL_JMP_XXX) if it's a zero bytes relative jump. */
1595	#define IEMBRANCHED_F_ZERO UINT8_C(0x80)
1596	/** @} */
1597
1598
1599	/**
1600	* The per-CPU IEM state.
1601	*/
1602	typedef struct IEMCPU
1603	{
1604	/** Info status code that needs to be propagated to the IEM caller.
1605	* This cannot be passed internally, as it would complicate all success
1606	* checks within the interpreter making the code larger and almost impossible
1607	* to get right. Instead, we'll store status codes to pass on here. Each
1608	* source of these codes will perform appropriate sanity checks. */
1609	int32_t rcPassUp; /* 0x00 */
1610	/** Execution flag, IEM_F_XXX. */
1611	uint32_t fExec; /* 0x04 */
1612
1613	/** @name Decoder state.
1614	* @{ */
1615	#ifdef IEM_WITH_CODE_TLB
1616	/** The offset of the next instruction byte. */
1617	uint32_t offInstrNextByte; /* 0x08 */
1618	/** The number of bytes available at pbInstrBuf for the current instruction.
1619	* This takes the max opcode length into account so that doesn't need to be
1620	* checked separately. */
1621	uint32_t cbInstrBuf; /* 0x0c */
1622	/** Pointer to the page containing RIP, user specified buffer or abOpcode.
1623	* This can be NULL if the page isn't mappable for some reason, in which
1624	* case we'll do fallback stuff.
1625	*
1626	* If we're executing an instruction from a user specified buffer,
1627	* IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
1628	* aligned pointer but pointer to the user data.
1629	*
1630	* For instructions crossing pages, this will start on the first page and be
1631	* advanced to the next page by the time we've decoded the instruction. This
1632	* therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
1633	*/
1634	uint8_t const pbInstrBuf; / 0x10 */
1635	# if ARCH_BITS == 32
1636	uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
1637	# endif
1638	/** The program counter corresponding to pbInstrBuf.
1639	* This is set to a non-canonical address when we need to invalidate it. */
1640	uint64_t uInstrBufPc; /* 0x18 */
1641	/** The guest physical address corresponding to pbInstrBuf. */
1642	RTGCPHYS GCPhysInstrBuf; /* 0x20 */
1643	/** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
1644	* This takes the CS segment limit into account.
1645	* @note Set to zero when the code TLB is flushed to trigger TLB reload. */
1646	uint16_t cbInstrBufTotal; /* 0x28 */
1647	/** Offset into pbInstrBuf of the first byte of the current instruction.
1648	* Can be negative to efficiently handle cross page instructions. */
1649	int16_t offCurInstrStart; /* 0x2a */
1650
1651	# ifndef IEM_WITH_OPAQUE_DECODER_STATE
1652	/** The prefix mask (IEM_OP_PRF_XXX). */
1653	uint32_t fPrefixes; /* 0x2c */
1654	/** The extra REX ModR/M register field bit (REX.R << 3). */
1655	uint8_t uRexReg; /* 0x30 */
1656	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
1657	* (REX.B << 3). */
1658	uint8_t uRexB; /* 0x31 */
1659	/** The extra REX SIB index field bit (REX.X << 3). */
1660	uint8_t uRexIndex; /* 0x32 */
1661
1662	/** The effective segment register (X86_SREG_XXX). */
1663	uint8_t iEffSeg; /* 0x33 */
1664
1665	/** The offset of the ModR/M byte relative to the start of the instruction. */
1666	uint8_t offModRm; /* 0x34 */
1667
1668	# ifdef IEM_WITH_CODE_TLB_AND_OPCODE_BUF
1669	/** The current offset into abOpcode. */
1670	uint8_t offOpcode; /* 0x35 */
1671	# else
1672	uint8_t bUnused; /* 0x35 */
1673	# endif
1674	# else /* IEM_WITH_OPAQUE_DECODER_STATE */
1675	uint8_t abOpaqueDecoderPart1[0x36 - 0x2c];
1676	# endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1677
1678	#else /* !IEM_WITH_CODE_TLB */
1679	# ifndef IEM_WITH_OPAQUE_DECODER_STATE
1680	/** The size of what has currently been fetched into abOpcode. */
1681	uint8_t cbOpcode; /* 0x08 */
1682	/** The current offset into abOpcode. */
1683	uint8_t offOpcode; /* 0x09 */
1684	/** The offset of the ModR/M byte relative to the start of the instruction. */
1685	uint8_t offModRm; /* 0x0a */
1686
1687	/** The effective segment register (X86_SREG_XXX). */
1688	uint8_t iEffSeg; /* 0x0b */
1689
1690	/** The prefix mask (IEM_OP_PRF_XXX). */
1691	uint32_t fPrefixes; /* 0x0c */
1692	/** The extra REX ModR/M register field bit (REX.R << 3). */
1693	uint8_t uRexReg; /* 0x10 */
1694	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
1695	* (REX.B << 3). */
1696	uint8_t uRexB; /* 0x11 */
1697	/** The extra REX SIB index field bit (REX.X << 3). */
1698	uint8_t uRexIndex; /* 0x12 */
1699
1700	# else /* IEM_WITH_OPAQUE_DECODER_STATE */
1701	uint8_t abOpaqueDecoderPart1[0x13 - 0x08];
1702	# endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1703	#endif /* !IEM_WITH_CODE_TLB */
1704
1705	#ifndef IEM_WITH_OPAQUE_DECODER_STATE
1706	/** The effective operand mode. */
1707	IEMMODE enmEffOpSize; /* 0x36, 0x13 */
1708	/** The default addressing mode. */
1709	IEMMODE enmDefAddrMode; /* 0x37, 0x14 */
1710	/** The effective addressing mode. */
1711	IEMMODE enmEffAddrMode; /* 0x38, 0x15 */
1712	/** The default operand mode. */
1713	IEMMODE enmDefOpSize; /* 0x39, 0x16 */
1714
1715	/** Prefix index (VEX.pp) for two byte and three byte tables. */
1716	uint8_t idxPrefix; /* 0x3a, 0x17 */
1717	/** 3rd VEX/EVEX/XOP register.
1718	* Please use IEM_GET_EFFECTIVE_VVVV to access. */
1719	uint8_t uVex3rdReg; /* 0x3b, 0x18 */
1720	/** The VEX/EVEX/XOP length field. */
1721	uint8_t uVexLength; /* 0x3c, 0x19 */
1722	/** Additional EVEX stuff. */
1723	uint8_t fEvexStuff; /* 0x3d, 0x1a */
1724
1725	# ifndef IEM_WITH_CODE_TLB
1726	/** Explicit alignment padding. */
1727	uint8_t abAlignment2a[1]; /* 0x1b */
1728	# endif
1729	/** The FPU opcode (FOP). */
1730	uint16_t uFpuOpcode; /* 0x3e, 0x1c */
1731	# ifndef IEM_WITH_CODE_TLB
1732	/** Explicit alignment padding. */
1733	uint8_t abAlignment2b[2]; /* 0x1e */
1734	# endif
1735
1736	/** The opcode bytes. */
1737	uint8_t abOpcode[15]; /* 0x40, 0x20 */
1738	/** Explicit alignment padding. */
1739	# ifdef IEM_WITH_CODE_TLB
1740	//uint8_t abAlignment2c[0x4f - 0x4f]; /* 0x4f */
1741	# else
1742	uint8_t abAlignment2c[0x4f - 0x2f]; /* 0x2f */
1743	# endif
1744
1745	#else /* IEM_WITH_OPAQUE_DECODER_STATE */
1746	# ifdef IEM_WITH_CODE_TLB
1747	uint8_t abOpaqueDecoderPart2[0x4f - 0x36];
1748	# else
1749	uint8_t abOpaqueDecoderPart2[0x4f - 0x13];
1750	# endif
1751	#endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1752	/** @} */
1753
1754
1755	/** The number of active guest memory mappings. */
1756	uint8_t cActiveMappings; /* 0x4f, 0x4f */
1757
1758	/** Records for tracking guest memory mappings. */
1759	struct
1760	{
1761	/** The address of the mapped bytes. */
1762	R3R0PTRTYPE(void *) pv;
1763	/** The access flags (IEM_ACCESS_XXX).
1764	* IEM_ACCESS_INVALID if the entry is unused. */
1765	uint32_t fAccess;
1766	#if HC_ARCH_BITS == 64
1767	uint32_t u32Alignment4; /*< Alignment padding. /
1768	#endif
1769	} aMemMappings[3]; /* 0x50 LB 0x30 */
1770
1771	/** Locking records for the mapped memory. */
1772	union
1773	{
1774	PGMPAGEMAPLOCK Lock;
1775	uint64_t au64Padding[2];
1776	} aMemMappingLocks[3]; /* 0x80 LB 0x30 */
1777
1778	/** Bounce buffer info.
1779	* This runs in parallel to aMemMappings. */
1780	struct
1781	{
1782	/** The physical address of the first byte. */
1783	RTGCPHYS GCPhysFirst;
1784	/** The physical address of the second page. */
1785	RTGCPHYS GCPhysSecond;
1786	/** The number of bytes in the first page. */
1787	uint16_t cbFirst;
1788	/** The number of bytes in the second page. */
1789	uint16_t cbSecond;
1790	/** Whether it's unassigned memory. */
1791	bool fUnassigned;
1792	/** Explicit alignment padding. */
1793	bool afAlignment5[3];
1794	} aMemBbMappings[3]; /* 0xb0 LB 0x48 */
1795
1796	/** The flags of the current exception / interrupt. */
1797	uint32_t fCurXcpt; /* 0xf8 */
1798	/** The current exception / interrupt. */
1799	uint8_t uCurXcpt; /* 0xfc */
1800	/** Exception / interrupt recursion depth. */
1801	int8_t cXcptRecursions; /* 0xfb */
1802
1803	/** The next unused mapping index.
1804	* @todo try find room for this up with cActiveMappings. */
1805	uint8_t iNextMapping; /* 0xfd */
1806	uint8_t abAlignment7[1];
1807
1808	/** Bounce buffer storage.
1809	* This runs in parallel to aMemMappings and aMemBbMappings. */
1810	struct
1811	{
1812	uint8_t ab[512];
1813	} aBounceBuffers[3]; /* 0x100 LB 0x600 */
1814
1815
1816	/** Pointer set jump buffer - ring-3 context. */
1817	R3PTRTYPE(jmp_buf *) pJmpBufR3;
1818	/** Pointer set jump buffer - ring-0 context. */
1819	R0PTRTYPE(jmp_buf *) pJmpBufR0;
1820
1821	/** @todo Should move this near @a fCurXcpt later. */
1822	/** The CR2 for the current exception / interrupt. */
1823	uint64_t uCurXcptCr2;
1824	/** The error code for the current exception / interrupt. */
1825	uint32_t uCurXcptErr;
1826
1827	/** @name Statistics
1828	* @{ */
1829	/** The number of instructions we've executed. */
1830	uint32_t cInstructions;
1831	/** The number of potential exits. */
1832	uint32_t cPotentialExits;
1833	/** The number of bytes data or stack written (mostly for IEMExecOneEx).
1834	* This may contain uncommitted writes. */
1835	uint32_t cbWritten;
1836	/** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
1837	uint32_t cRetInstrNotImplemented;
1838	/** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
1839	uint32_t cRetAspectNotImplemented;
1840	/** Counts informational statuses returned (other than VINF_SUCCESS). */
1841	uint32_t cRetInfStatuses;
1842	/** Counts other error statuses returned. */
1843	uint32_t cRetErrStatuses;
1844	/** Number of times rcPassUp has been used. */
1845	uint32_t cRetPassUpStatus;
1846	/** Number of times RZ left with instruction commit pending for ring-3. */
1847	uint32_t cPendingCommit;
1848	/** Number of misaligned (host sense) atomic instruction accesses. */
1849	uint32_t cMisalignedAtomics;
1850	/** Number of long jumps. */
1851	uint32_t cLongJumps;
1852	/** @} */
1853
1854	/** @name Target CPU information.
1855	* @{ */
1856	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
1857	/** The target CPU. */
1858	uint8_t uTargetCpu;
1859	#else
1860	uint8_t bTargetCpuPadding;
1861	#endif
1862	/** For selecting assembly works matching the target CPU EFLAGS behaviour, see
1863	* IEMTARGETCPU_EFL_BEHAVIOR_XXX for values, with the 1st entry for when no
1864	* native host support and the 2nd for when there is.
1865	*
1866	* The two values are typically indexed by a g_CpumHostFeatures bit.
1867	*
1868	* This is for instance used for the BSF & BSR instructions where AMD and
1869	* Intel CPUs produce different EFLAGS. */
1870	uint8_t aidxTargetCpuEflFlavour[2];
1871
1872	/** The CPU vendor. */
1873	CPUMCPUVENDOR enmCpuVendor;
1874	/** @} */
1875
1876	/** @name Host CPU information.
1877	* @{ */
1878	/** The CPU vendor. */
1879	CPUMCPUVENDOR enmHostCpuVendor;
1880	/** @} */
1881
1882	/** Counts RDMSR \#GP(0) LogRel(). */
1883	uint8_t cLogRelRdMsr;
1884	/** Counts WRMSR \#GP(0) LogRel(). */
1885	uint8_t cLogRelWrMsr;
1886	/** Alignment padding. */
1887	uint8_t abAlignment9[42];
1888
1889	/** @name Recompilation
1890	* @{ */
1891	/** Pointer to the current translation block.
1892	* This can either be one being executed or one being compiled. */
1893	R3PTRTYPE(PIEMTB) pCurTbR3;
1894	#ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
1895	/** Frame pointer for the last native TB to execute. */
1896	R3PTRTYPE(void *) pvTbFramePointerR3;
1897	#else
1898	R3PTRTYPE(void *) pvUnusedR3;
1899	#endif
1900	/** Fixed TB used for threaded recompilation.
1901	* This is allocated once with maxed-out sizes and re-used afterwards. */
1902	R3PTRTYPE(PIEMTB) pThrdCompileTbR3;
1903	/** Pointer to the ring-3 TB cache for this EMT. */
1904	R3PTRTYPE(PIEMTBCACHE) pTbCacheR3;
1905	/** Pointer to the ring-3 TB lookup entry.
1906	* This either points to pTbLookupEntryDummyR3 or an actually lookuptable
1907	* entry, thus it can always safely be used w/o NULL checking. */
1908	R3PTRTYPE(PIEMTB *) ppTbLookupEntryR3;
1909	/** The PC (RIP) at the start of pCurTbR3/pCurTbR0.
1910	* The TBs are based on physical addresses, so this is needed to correleated
1911	* RIP to opcode bytes stored in the TB (AMD-V / VT-x). */
1912	uint64_t uCurTbStartPc;
1913	/** Number of threaded TBs executed. */
1914	uint64_t cTbExecThreaded;
1915	/** Number of native TBs executed. */
1916	uint64_t cTbExecNative;
1917	/** Whether we need to check the opcode bytes for the current instruction.
1918	* This is set by a previous instruction if it modified memory or similar. */
1919	bool fTbCheckOpcodes;
1920	/** Indicates whether and how we just branched - IEMBRANCHED_F_XXX. */
1921	uint8_t fTbBranched;
1922	/** Set when GCPhysInstrBuf is updated because of a page crossing. */
1923	bool fTbCrossedPage;
1924	/** Whether to end the current TB. */
1925	bool fEndTb;
1926	/** Number of instructions before we need emit an IRQ check call again.
1927	* This helps making sure we don't execute too long w/o checking for
1928	* interrupts and immediately following instructions that may enable
1929	* interrupts (e.g. POPF, IRET, STI). With STI an additional hack is
1930	* required to make sure we check following the next instruction as well, see
1931	* fTbCurInstrIsSti. */
1932	uint8_t cInstrTillIrqCheck;
1933	/** Indicates that the current instruction is an STI. This is set by the
1934	* iemCImpl_sti code and subsequently cleared by the recompiler. */
1935	bool fTbCurInstrIsSti;
1936	/** The size of the IEMTB::pabOpcodes allocation in pThrdCompileTbR3. */
1937	uint16_t cbOpcodesAllocated;
1938	/** The current instruction number in a native TB.
1939	* This is set by code that may trigger an unexpected TB exit (throw/longjmp)
1940	* and will be picked up by the TB execution loop. Only used when
1941	* IEMNATIVE_WITH_INSTRUCTION_COUNTING is defined. */
1942	uint8_t idxTbCurInstr;
1943	/** Spaced reserved for recompiler data / alignment. */
1944	bool afRecompilerStuff1[3];
1945	/** The virtual sync time at the last timer poll call. */
1946	uint32_t msRecompilerPollNow;
1947	/** The IEMTB::cUsed value when to attempt native recompilation of a TB. */
1948	uint32_t uTbNativeRecompileAtUsedCount;
1949	/** The IEM_CIMPL_F_XXX mask for the current instruction. */
1950	uint32_t fTbCurInstr;
1951	/** The IEM_CIMPL_F_XXX mask for the previous instruction. */
1952	uint32_t fTbPrevInstr;
1953	/** Strict: Tracking skipped EFLAGS calculations. Any bits set here are
1954	* currently not up to date in EFLAGS. */
1955	uint32_t fSkippingEFlags;
1956	/** Previous GCPhysInstrBuf value - only valid if fTbCrossedPage is set. */
1957	RTGCPHYS GCPhysInstrBufPrev;
1958	/** Pointer to the ring-3 TB allocator for this EMT. */
1959	R3PTRTYPE(PIEMTBALLOCATOR) pTbAllocatorR3;
1960	/** Pointer to the ring-3 executable memory allocator for this EMT. */
1961	R3PTRTYPE(struct IEMEXECMEMALLOCATOR *) pExecMemAllocatorR3;
1962	/** Pointer to the native recompiler state for ring-3. */
1963	R3PTRTYPE(struct IEMRECOMPILERSTATE *) pNativeRecompilerStateR3;
1964	/** Dummy entry for ppTbLookupEntryR3. */
1965	R3PTRTYPE(PIEMTB) pTbLookupEntryDummyR3;
1966
1967	/** Threaded TB statistics: Times TB execution was broken off before reaching the end. */
1968	STAMCOUNTER StatTbThreadedExecBreaks;
1969	/** Statistics: Times BltIn_CheckIrq breaks out of the TB. */
1970	STAMCOUNTER StatCheckIrqBreaks;
1971	/** Statistics: Times BltIn_CheckMode breaks out of the TB. */
1972	STAMCOUNTER StatCheckModeBreaks;
1973	/** Threaded TB statistics: Times execution break on call with lookup entries. */
1974	STAMCOUNTER StatTbThreadedExecBreaksWithLookup;
1975	/** Threaded TB statistics: Times execution break on call without lookup entries. */
1976	STAMCOUNTER StatTbThreadedExecBreaksWithoutLookup;
1977	/** Statistics: Times a post jump target check missed and had to find new TB. */
1978	STAMCOUNTER StatCheckBranchMisses;
1979	/** Statistics: Times a jump or page crossing required a TB with CS.LIM checking. */
1980	STAMCOUNTER StatCheckNeedCsLimChecking;
1981	/** Statistics: Times a loop was detected within a TB.. */
1982	STAMCOUNTER StatTbLoopInTbDetected;
1983	/** Exec memory allocator statistics: Number of times allocaintg executable memory failed. */
1984	STAMCOUNTER StatNativeExecMemInstrBufAllocFailed;
1985	/** Native TB statistics: Number of fully recompiled TBs. */
1986	STAMCOUNTER StatNativeFullyRecompiledTbs;
1987	/** TB statistics: Number of instructions per TB. */
1988	STAMPROFILE StatTbInstr;
1989	/** TB statistics: Number of TB lookup table entries per TB. */
1990	STAMPROFILE StatTbLookupEntries;
1991	/** Threaded TB statistics: Number of calls per TB. */
1992	STAMPROFILE StatTbThreadedCalls;
1993	/** Native TB statistics: Native code size per TB. */
1994	STAMPROFILE StatTbNativeCode;
1995	/** Native TB statistics: Profiling native recompilation. */
1996	STAMPROFILE StatNativeRecompilation;
1997	/** Native TB statistics: Number of calls per TB that were recompiled properly. */
1998	STAMPROFILE StatNativeCallsRecompiled;
1999	/** Native TB statistics: Number of threaded calls per TB that weren't recompiled. */
2000	STAMPROFILE StatNativeCallsThreaded;
2001	/** Native recompiled execution: TLB hits for data fetches. */
2002	STAMCOUNTER StatNativeTlbHitsForFetch;
2003	/** Native recompiled execution: TLB hits for data stores. */
2004	STAMCOUNTER StatNativeTlbHitsForStore;
2005	/** Native recompiled execution: TLB hits for stack accesses. */
2006	STAMCOUNTER StatNativeTlbHitsForStack;
2007	/** Native recompiled execution: TLB hits for mapped accesses. */
2008	STAMCOUNTER StatNativeTlbHitsForMapped;
2009	/** Native recompiled execution: Code TLB misses for new page. */
2010	STAMCOUNTER StatNativeCodeTlbMissesNewPage;
2011	/** Native recompiled execution: Code TLB hits for new page. */
2012	STAMCOUNTER StatNativeCodeTlbHitsForNewPage;
2013	/** Native recompiled execution: Code TLB misses for new page with offset. */
2014	STAMCOUNTER StatNativeCodeTlbMissesNewPageWithOffset;
2015	/** Native recompiled execution: Code TLB hits for new page with offset. */
2016	STAMCOUNTER StatNativeCodeTlbHitsForNewPageWithOffset;
2017
2018	/** Native recompiler: Number of calls to iemNativeRegAllocFindFree. */
2019	STAMCOUNTER StatNativeRegFindFree;
2020	/** Native recompiler: Number of times iemNativeRegAllocFindFree needed
2021	* to free a variable. */
2022	STAMCOUNTER StatNativeRegFindFreeVar;
2023	/** Native recompiler: Number of times iemNativeRegAllocFindFree did
2024	* not need to free any variables. */
2025	STAMCOUNTER StatNativeRegFindFreeNoVar;
2026	/** Native recompiler: Liveness info freed shadowed guest registers in
2027	* iemNativeRegAllocFindFree. */
2028	STAMCOUNTER StatNativeRegFindFreeLivenessUnshadowed;
2029	/** Native recompiler: Liveness info helped with the allocation in
2030	* iemNativeRegAllocFindFree. */
2031	STAMCOUNTER StatNativeRegFindFreeLivenessHelped;
2032
2033	/** Native recompiler: Number of times status flags calc has been skipped. */
2034	STAMCOUNTER StatNativeEflSkippedArithmetic;
2035	/** Native recompiler: Number of times status flags calc has been skipped. */
2036	STAMCOUNTER StatNativeEflSkippedLogical;
2037
2038	/** Native recompiler: Number of opportunities to skip EFLAGS.CF updating. */
2039	STAMCOUNTER StatNativeLivenessEflCfSkippable;
2040	/** Native recompiler: Number of opportunities to skip EFLAGS.PF updating. */
2041	STAMCOUNTER StatNativeLivenessEflPfSkippable;
2042	/** Native recompiler: Number of opportunities to skip EFLAGS.AF updating. */
2043	STAMCOUNTER StatNativeLivenessEflAfSkippable;
2044	/** Native recompiler: Number of opportunities to skip EFLAGS.ZF updating. */
2045	STAMCOUNTER StatNativeLivenessEflZfSkippable;
2046	/** Native recompiler: Number of opportunities to skip EFLAGS.SF updating. */
2047	STAMCOUNTER StatNativeLivenessEflSfSkippable;
2048	/** Native recompiler: Number of opportunities to skip EFLAGS.OF updating. */
2049	STAMCOUNTER StatNativeLivenessEflOfSkippable;
2050	/** Native recompiler: Number of required EFLAGS.CF updates. */
2051	STAMCOUNTER StatNativeLivenessEflCfRequired;
2052	/** Native recompiler: Number of required EFLAGS.PF updates. */
2053	STAMCOUNTER StatNativeLivenessEflPfRequired;
2054	/** Native recompiler: Number of required EFLAGS.AF updates. */
2055	STAMCOUNTER StatNativeLivenessEflAfRequired;
2056	/** Native recompiler: Number of required EFLAGS.ZF updates. */
2057	STAMCOUNTER StatNativeLivenessEflZfRequired;
2058	/** Native recompiler: Number of required EFLAGS.SF updates. */
2059	STAMCOUNTER StatNativeLivenessEflSfRequired;
2060	/** Native recompiler: Number of required EFLAGS.OF updates. */
2061	STAMCOUNTER StatNativeLivenessEflOfRequired;
2062	/** Native recompiler: Number of potentially delayable EFLAGS.CF updates. */
2063	STAMCOUNTER StatNativeLivenessEflCfDelayable;
2064	/** Native recompiler: Number of potentially delayable EFLAGS.PF updates. */
2065	STAMCOUNTER StatNativeLivenessEflPfDelayable;
2066	/** Native recompiler: Number of potentially delayable EFLAGS.AF updates. */
2067	STAMCOUNTER StatNativeLivenessEflAfDelayable;
2068	/** Native recompiler: Number of potentially delayable EFLAGS.ZF updates. */
2069	STAMCOUNTER StatNativeLivenessEflZfDelayable;
2070	/** Native recompiler: Number of potentially delayable EFLAGS.SF updates. */
2071	STAMCOUNTER StatNativeLivenessEflSfDelayable;
2072	/** Native recompiler: Number of potentially delayable EFLAGS.OF updates. */
2073	STAMCOUNTER StatNativeLivenessEflOfDelayable;
2074
2075	/** Native recompiler: Number of potential PC updates in total. */
2076	STAMCOUNTER StatNativePcUpdateTotal;
2077	/** Native recompiler: Number of PC updates which could be delayed. */
2078	STAMCOUNTER StatNativePcUpdateDelayed;
2079
2080	//#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
2081	/** Native recompiler: Number of calls to iemNativeSimdRegAllocFindFree. */
2082	STAMCOUNTER StatNativeSimdRegFindFree;
2083	/** Native recompiler: Number of times iemNativeSimdRegAllocFindFree needed
2084	* to free a variable. */
2085	STAMCOUNTER StatNativeSimdRegFindFreeVar;
2086	/** Native recompiler: Number of times iemNativeSimdRegAllocFindFree did
2087	* not need to free any variables. */
2088	STAMCOUNTER StatNativeSimdRegFindFreeNoVar;
2089	/** Native recompiler: Liveness info freed shadowed guest registers in
2090	* iemNativeSimdRegAllocFindFree. */
2091	STAMCOUNTER StatNativeSimdRegFindFreeLivenessUnshadowed;
2092	/** Native recompiler: Liveness info helped with the allocation in
2093	* iemNativeSimdRegAllocFindFree. */
2094	STAMCOUNTER StatNativeSimdRegFindFreeLivenessHelped;
2095
2096	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() checks. */
2097	STAMCOUNTER StatNativeMaybeDeviceNotAvailXcptCheckPotential;
2098	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() checks. */
2099	STAMCOUNTER StatNativeMaybeWaitDeviceNotAvailXcptCheckPotential;
2100	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() checks. */
2101	STAMCOUNTER StatNativeMaybeSseXcptCheckPotential;
2102	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() checks. */
2103	STAMCOUNTER StatNativeMaybeAvxXcptCheckPotential;
2104
2105	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() checks omitted. */
2106	STAMCOUNTER StatNativeMaybeDeviceNotAvailXcptCheckOmitted;
2107	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() checks omitted. */
2108	STAMCOUNTER StatNativeMaybeWaitDeviceNotAvailXcptCheckOmitted;
2109	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() checks omitted. */
2110	STAMCOUNTER StatNativeMaybeSseXcptCheckOmitted;
2111	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() checks omitted. */
2112	STAMCOUNTER StatNativeMaybeAvxXcptCheckOmitted;
2113	//#endif
2114
2115	/** Native recompiler: The TB finished executing completely without jumping to a an exit label.
2116	* Not availabe in release builds. */
2117	STAMCOUNTER StatNativeTbFinished;
2118	/** Native recompiler: The TB finished executing jumping to the ReturnBreak label. */
2119	STAMCOUNTER StatNativeTbExitReturnBreak;
2120	/** Native recompiler: The TB finished executing jumping to the ReturnBreakFF label. */
2121	STAMCOUNTER StatNativeTbExitReturnBreakFF;
2122	/** Native recompiler: The TB finished executing jumping to the ReturnWithFlags label. */
2123	STAMCOUNTER StatNativeTbExitReturnWithFlags;
2124	/** Native recompiler: The TB finished executing with other non-zero status. */
2125	STAMCOUNTER StatNativeTbExitReturnOtherStatus;
2126	/** Native recompiler: The TB finished executing via throw / long jump. */
2127	STAMCOUNTER StatNativeTbExitLongJump;
2128	/** Native recompiler: The TB finished executing jumping to the ReturnBreak
2129	* label, but directly jumped to the next TB, scenario \#1 w/o IRQ checks. */
2130	STAMCOUNTER StatNativeTbExitDirectLinking1NoIrq;
2131	/** Native recompiler: The TB finished executing jumping to the ReturnBreak
2132	* label, but directly jumped to the next TB, scenario \#1 with IRQ checks. */
2133	STAMCOUNTER StatNativeTbExitDirectLinking1Irq;
2134	/** Native recompiler: The TB finished executing jumping to the ReturnBreak
2135	* label, but directly jumped to the next TB, scenario \#1 w/o IRQ checks. */
2136	STAMCOUNTER StatNativeTbExitDirectLinking2NoIrq;
2137	/** Native recompiler: The TB finished executing jumping to the ReturnBreak
2138	* label, but directly jumped to the next TB, scenario \#2 with IRQ checks. */
2139	STAMCOUNTER StatNativeTbExitDirectLinking2Irq;
2140
2141	/** Native recompiler: The TB finished executing jumping to the RaiseDe label. */
2142	STAMCOUNTER StatNativeTbExitRaiseDe;
2143	/** Native recompiler: The TB finished executing jumping to the RaiseUd label. */
2144	STAMCOUNTER StatNativeTbExitRaiseUd;
2145	/** Native recompiler: The TB finished executing jumping to the RaiseSseRelated label. */
2146	STAMCOUNTER StatNativeTbExitRaiseSseRelated;
2147	/** Native recompiler: The TB finished executing jumping to the RaiseAvxRelated label. */
2148	STAMCOUNTER StatNativeTbExitRaiseAvxRelated;
2149	/** Native recompiler: The TB finished executing jumping to the RaiseSseAvxFpRelated label. */
2150	STAMCOUNTER StatNativeTbExitRaiseSseAvxFpRelated;
2151	/** Native recompiler: The TB finished executing jumping to the RaiseNm label. */
2152	STAMCOUNTER StatNativeTbExitRaiseNm;
2153	/** Native recompiler: The TB finished executing jumping to the RaiseGp0 label. */
2154	STAMCOUNTER StatNativeTbExitRaiseGp0;
2155	/** Native recompiler: The TB finished executing jumping to the RaiseMf label. */
2156	STAMCOUNTER StatNativeTbExitRaiseMf;
2157	/** Native recompiler: The TB finished executing jumping to the RaiseXf label. */
2158	STAMCOUNTER StatNativeTbExitRaiseXf;
2159	/** Native recompiler: The TB finished executing jumping to the ObsoleteTb label. */
2160	STAMCOUNTER StatNativeTbExitObsoleteTb;
2161
2162	/** Native recompiler: Failure situations with direct linking scenario \#1.
2163	* Counter with StatNativeTbExitReturnBreak. Not in release builds.
2164	* @{ */
2165	STAMCOUNTER StatNativeTbExitDirectLinking1NoTb;
2166	STAMCOUNTER StatNativeTbExitDirectLinking1MismatchGCPhysPc;
2167	STAMCOUNTER StatNativeTbExitDirectLinking1MismatchFlags;
2168	STAMCOUNTER StatNativeTbExitDirectLinking1PendingIrq;
2169	/** @} */
2170
2171	/** Native recompiler: Failure situations with direct linking scenario \#2.
2172	* Counter with StatNativeTbExitReturnBreak. Not in release builds.
2173	* @{ */
2174	STAMCOUNTER StatNativeTbExitDirectLinking2NoTb;
2175	STAMCOUNTER StatNativeTbExitDirectLinking2MismatchGCPhysPc;
2176	STAMCOUNTER StatNativeTbExitDirectLinking2MismatchFlags;
2177	STAMCOUNTER StatNativeTbExitDirectLinking2PendingIrq;
2178	/** @} */
2179
2180	/** iemMemMap and iemMemMapJmp statistics.
2181	* @{ */
2182	STAMCOUNTER StatMemMapJmp;
2183	STAMCOUNTER StatMemMapNoJmp;
2184	STAMCOUNTER StatMemBounceBufferCrossPage;
2185	STAMCOUNTER StatMemBounceBufferMapPhys;
2186	/** @} */
2187
2188	uint64_t au64Padding[1];
2189	/** @} */
2190
2191	/** Data TLB.
2192	* @remarks Must be 64-byte aligned. */
2193	IEMTLB DataTlb;
2194	/** Instruction TLB.
2195	* @remarks Must be 64-byte aligned. */
2196	IEMTLB CodeTlb;
2197
2198	/** Exception statistics. */
2199	STAMCOUNTER aStatXcpts[32];
2200	/** Interrupt statistics. */
2201	uint32_t aStatInts[256];
2202
2203	#if defined(VBOX_WITH_STATISTICS) && !defined(DOXYGEN_RUNNING) && !defined(IEM_WITHOUT_INSTRUCTION_STATS)
2204	/** Instruction statistics for ring-0/raw-mode. */
2205	IEMINSTRSTATS StatsRZ;
2206	/** Instruction statistics for ring-3. */
2207	IEMINSTRSTATS StatsR3;
2208	# ifdef VBOX_WITH_IEM_RECOMPILER
2209	/** Statistics per threaded function call.
2210	* Updated by both the threaded and native recompilers. */
2211	uint32_t acThreadedFuncStats[0x6000 /24576/];
2212	# endif
2213	#endif
2214	} IEMCPU;
2215	AssertCompileMemberOffset(IEMCPU, cActiveMappings, 0x4f);
2216	AssertCompileMemberAlignment(IEMCPU, aMemMappings, 16);
2217	AssertCompileMemberAlignment(IEMCPU, aMemMappingLocks, 16);
2218	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 64);
2219	AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
2220	AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
2221
2222	/** Pointer to the per-CPU IEM state. */
2223	typedef IEMCPU *PIEMCPU;
2224	/** Pointer to the const per-CPU IEM state. */
2225	typedef IEMCPU const *PCIEMCPU;
2226
2227
2228	/** @def IEM_GET_CTX
2229	* Gets the guest CPU context for the calling EMT.
2230	* @returns PCPUMCTX
2231	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2232	*/
2233	#define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
2234
2235	/** @def IEM_CTX_ASSERT
2236	* Asserts that the @a a_fExtrnMbz is present in the CPU context.
2237	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2238	* @param a_fExtrnMbz The mask of CPUMCTX_EXTRN_XXX flags that must be zero.
2239	*/
2240	#define IEM_CTX_ASSERT(a_pVCpu, a_fExtrnMbz) \
2241	AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
2242	("fExtrn=%#RX64 & fExtrnMbz=%#RX64 -> %#RX64\n", \
2243	(a_pVCpu)->cpum.GstCtx.fExtrn, (a_fExtrnMbz), (a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz) ))
2244
2245	/** @def IEM_CTX_IMPORT_RET
2246	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
2247	*
2248	* Will call the keep to import the bits as needed.
2249	*
2250	* Returns on import failure.
2251	*
2252	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2253	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
2254	*/
2255	#define IEM_CTX_IMPORT_RET(a_pVCpu, a_fExtrnImport) \
2256	do { \
2257	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
2258	{ /* likely */ } \
2259	else \
2260	{ \
2261	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
2262	AssertRCReturn(rcCtxImport, rcCtxImport); \
2263	} \
2264	} while (0)
2265
2266	/** @def IEM_CTX_IMPORT_NORET
2267	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
2268	*
2269	* Will call the keep to import the bits as needed.
2270	*
2271	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2272	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
2273	*/
2274	#define IEM_CTX_IMPORT_NORET(a_pVCpu, a_fExtrnImport) \
2275	do { \
2276	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
2277	{ /* likely */ } \
2278	else \
2279	{ \
2280	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
2281	AssertLogRelRC(rcCtxImport); \
2282	} \
2283	} while (0)
2284
2285	/** @def IEM_CTX_IMPORT_JMP
2286	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
2287	*
2288	* Will call the keep to import the bits as needed.
2289	*
2290	* Jumps on import failure.
2291	*
2292	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2293	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
2294	*/
2295	#define IEM_CTX_IMPORT_JMP(a_pVCpu, a_fExtrnImport) \
2296	do { \
2297	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
2298	{ /* likely */ } \
2299	else \
2300	{ \
2301	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
2302	AssertRCStmt(rcCtxImport, IEM_DO_LONGJMP(pVCpu, rcCtxImport)); \
2303	} \
2304	} while (0)
2305
2306
2307
2308	/** @def IEM_GET_TARGET_CPU
2309	* Gets the current IEMTARGETCPU value.
2310	* @returns IEMTARGETCPU value.
2311	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2312	*/
2313	#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
2314	# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
2315	#else
2316	# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
2317	#endif
2318
2319	/** @def IEM_GET_INSTR_LEN
2320	* Gets the instruction length. */
2321	#ifdef IEM_WITH_CODE_TLB
2322	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
2323	#else
2324	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
2325	#endif
2326
2327	/** @def IEM_TRY_SETJMP
2328	* Wrapper around setjmp / try, hiding all the ugly differences.
2329	*
2330	* @note Use with extreme care as this is a fragile macro.
2331	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2332	* @param a_rcTarget The variable that should receive the status code in case
2333	* of a longjmp/throw.
2334	*/
2335	/** @def IEM_TRY_SETJMP_AGAIN
2336	* For when setjmp / try is used again in the same variable scope as a previous
2337	* IEM_TRY_SETJMP invocation.
2338	*/
2339	/** @def IEM_CATCH_LONGJMP_BEGIN
2340	* Start wrapper for catch / setjmp-else.
2341	*
2342	* This will set up a scope.
2343	*
2344	* @note Use with extreme care as this is a fragile macro.
2345	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2346	* @param a_rcTarget The variable that should receive the status code in case
2347	* of a longjmp/throw.
2348	*/
2349	/** @def IEM_CATCH_LONGJMP_END
2350	* End wrapper for catch / setjmp-else.
2351	*
2352	* This will close the scope set up by IEM_CATCH_LONGJMP_BEGIN and clean up the
2353	* state.
2354	*
2355	* @note Use with extreme care as this is a fragile macro.
2356	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2357	*/
2358	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
2359	# ifdef IEM_WITH_THROW_CATCH
2360	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
2361	a_rcTarget = VINF_SUCCESS; \
2362	try
2363	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
2364	IEM_TRY_SETJMP(a_pVCpu, a_rcTarget)
2365	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
2366	catch (int rcThrown) \
2367	{ \
2368	a_rcTarget = rcThrown
2369	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
2370	} \
2371	((void)0)
2372	# else /* !IEM_WITH_THROW_CATCH */
2373	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
2374	jmp_buf JmpBuf; \
2375	jmp_buf * volatile pSavedJmpBuf = (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf); \
2376	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
2377	if ((rcStrict = setjmp(JmpBuf)) == 0)
2378	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
2379	pSavedJmpBuf = (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf); \
2380	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
2381	if ((rcStrict = setjmp(JmpBuf)) == 0)
2382	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
2383	else \
2384	{ \
2385	((void)0)
2386	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
2387	} \
2388	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = pSavedJmpBuf
2389	# endif /* !IEM_WITH_THROW_CATCH */
2390	#endif /* IEM_WITH_SETJMP */
2391
2392
2393	/**
2394	* Shared per-VM IEM data.
2395	*/
2396	typedef struct IEM
2397	{
2398	/** The VMX APIC-access page handler type. */
2399	PGMPHYSHANDLERTYPE hVmxApicAccessPage;
2400	#ifndef VBOX_WITHOUT_CPUID_HOST_CALL
2401	/** Set if the CPUID host call functionality is enabled. */
2402	bool fCpuIdHostCall;
2403	#endif
2404	} IEM;
2405
2406
2407
2408	/** @name IEM_ACCESS_XXX - Access details.
2409	* @{ */
2410	#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
2411	#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
2412	#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
2413	#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
2414	#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
2415	#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
2416	#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
2417	#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
2418	#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
2419	#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
2420	/** The writes are partial, so if initialize the bounce buffer with the
2421	* orignal RAM content. */
2422	#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
2423	/** Used in aMemMappings to indicate that the entry is bounce buffered. */
2424	#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
2425	/** Bounce buffer with ring-3 write pending, first page. */
2426	#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
2427	/** Bounce buffer with ring-3 write pending, second page. */
2428	#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
2429	/** Not locked, accessed via the TLB. */
2430	#define IEM_ACCESS_NOT_LOCKED UINT32_C(0x00001000)
2431	/** Atomic access.
2432	* This enables special alignment checks and the VINF_EM_EMULATE_SPLIT_LOCK
2433	* fallback for misaligned stuff. See @bugref{10547}. */
2434	#define IEM_ACCESS_ATOMIC UINT32_C(0x00002000)
2435	/** Valid bit mask. */
2436	#define IEM_ACCESS_VALID_MASK UINT32_C(0x00003fff)
2437	/** Shift count for the TLB flags (upper word). */
2438	#define IEM_ACCESS_SHIFT_TLB_FLAGS 16
2439
2440	/** Atomic read+write data alias. */
2441	#define IEM_ACCESS_DATA_ATOMIC (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA \| IEM_ACCESS_ATOMIC)
2442	/** Read+write data alias. */
2443	#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
2444	/** Write data alias. */
2445	#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
2446	/** Read data alias. */
2447	#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_DATA)
2448	/** Instruction fetch alias. */
2449	#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_WHAT_CODE)
2450	/** Stack write alias. */
2451	#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
2452	/** Stack read alias. */
2453	#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_STACK)
2454	/** Stack read+write alias. */
2455	#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
2456	/** Read system table alias. */
2457	#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_SYS)
2458	/** Read+write system table alias. */
2459	#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_SYS)
2460	/** @} */
2461
2462	/** @name Prefix constants (IEMCPU::fPrefixes)
2463	* @{ */
2464	#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /*< CS segment prefix (0x2e). /
2465	#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /*< SS segment prefix (0x36). /
2466	#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /*< DS segment prefix (0x3e). /
2467	#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /*< ES segment prefix (0x26). /
2468	#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /*< FS segment prefix (0x64). /
2469	#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /*< GS segment prefix (0x65). /
2470	#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
2471
2472	#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /*< Operand size prefix (0x66). /
2473	#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /*< REX.W prefix (0x48-0x4f). /
2474	#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /*< Address size prefix (0x67). /
2475
2476	#define IEM_OP_PRF_LOCK RT_BIT_32(16) /*< Lock prefix (0xf0). /
2477	#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /*< Repeat-not-zero prefix (0xf2). /
2478	#define IEM_OP_PRF_REPZ RT_BIT_32(18) /*< Repeat-if-zero prefix (0xf3). /
2479
2480	#define IEM_OP_PRF_REX RT_BIT_32(24) /*< Any REX prefix (0x40-0x4f). /
2481	#define IEM_OP_PRF_REX_B RT_BIT_32(25) /*< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). /
2482	#define IEM_OP_PRF_REX_X RT_BIT_32(26) /*< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). /
2483	#define IEM_OP_PRF_REX_R RT_BIT_32(27) /*< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). /
2484	/** Mask with all the REX prefix flags.
2485	* This is generally for use when needing to undo the REX prefixes when they
2486	* are followed legacy prefixes and therefore does not immediately preceed
2487	* the first opcode byte.
2488	* For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
2489	#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX \| IEM_OP_PRF_REX_R \| IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X \| IEM_OP_PRF_SIZE_REX_W )
2490
2491	#define IEM_OP_PRF_VEX RT_BIT_32(28) /*< Indiciates VEX prefix. /
2492	#define IEM_OP_PRF_EVEX RT_BIT_32(29) /*< Indiciates EVEX prefix. /
2493	#define IEM_OP_PRF_XOP RT_BIT_32(30) /*< Indiciates XOP prefix. /
2494	/** @} */
2495
2496	/** @name IEMOPFORM_XXX - Opcode forms
2497	* @note These are ORed together with IEMOPHINT_XXX.
2498	* @{ */
2499	/** ModR/M: reg, r/m */
2500	#define IEMOPFORM_RM 0
2501	/** ModR/M: reg, r/m (register) */
2502	#define IEMOPFORM_RM_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
2503	/** ModR/M: reg, r/m (memory) */
2504	#define IEMOPFORM_RM_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
2505	/** ModR/M: reg, r/m, imm */
2506	#define IEMOPFORM_RMI 1
2507	/** ModR/M: reg, r/m (register), imm */
2508	#define IEMOPFORM_RMI_REG (IEMOPFORM_RMI \| IEMOPFORM_MOD3)
2509	/** ModR/M: reg, r/m (memory), imm */
2510	#define IEMOPFORM_RMI_MEM (IEMOPFORM_RMI \| IEMOPFORM_NOT_MOD3)
2511	/** ModR/M: reg, r/m, xmm0 */
2512	#define IEMOPFORM_RM0 2
2513	/** ModR/M: reg, r/m (register), xmm0 */
2514	#define IEMOPFORM_RM0_REG (IEMOPFORM_RM0 \| IEMOPFORM_MOD3)
2515	/** ModR/M: reg, r/m (memory), xmm0 */
2516	#define IEMOPFORM_RM0_MEM (IEMOPFORM_RM0 \| IEMOPFORM_NOT_MOD3)
2517	/** ModR/M: r/m, reg */
2518	#define IEMOPFORM_MR 3
2519	/** ModR/M: r/m (register), reg */
2520	#define IEMOPFORM_MR_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
2521	/** ModR/M: r/m (memory), reg */
2522	#define IEMOPFORM_MR_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
2523	/** ModR/M: r/m, reg, imm */
2524	#define IEMOPFORM_MRI 4
2525	/** ModR/M: r/m (register), reg, imm */
2526	#define IEMOPFORM_MRI_REG (IEMOPFORM_MRI \| IEMOPFORM_MOD3)
2527	/** ModR/M: r/m (memory), reg, imm */
2528	#define IEMOPFORM_MRI_MEM (IEMOPFORM_MRI \| IEMOPFORM_NOT_MOD3)
2529	/** ModR/M: r/m only */
2530	#define IEMOPFORM_M 5
2531	/** ModR/M: r/m only (register). */
2532	#define IEMOPFORM_M_REG (IEMOPFORM_M \| IEMOPFORM_MOD3)
2533	/** ModR/M: r/m only (memory). */
2534	#define IEMOPFORM_M_MEM (IEMOPFORM_M \| IEMOPFORM_NOT_MOD3)
2535	/** ModR/M: r/m, imm */
2536	#define IEMOPFORM_MI 6
2537	/** ModR/M: r/m (register), imm */
2538	#define IEMOPFORM_MI_REG (IEMOPFORM_MI \| IEMOPFORM_MOD3)
2539	/** ModR/M: r/m (memory), imm */
2540	#define IEMOPFORM_MI_MEM (IEMOPFORM_MI \| IEMOPFORM_NOT_MOD3)
2541	/** ModR/M: r/m, 1 (shift and rotate instructions) */
2542	#define IEMOPFORM_M1 7
2543	/** ModR/M: r/m (register), 1. */
2544	#define IEMOPFORM_M1_REG (IEMOPFORM_M1 \| IEMOPFORM_MOD3)
2545	/** ModR/M: r/m (memory), 1. */
2546	#define IEMOPFORM_M1_MEM (IEMOPFORM_M1 \| IEMOPFORM_NOT_MOD3)
2547	/** ModR/M: r/m, CL (shift and rotate instructions)
2548	* @todo This should just've been a generic fixed register. But the python
2549	* code doesn't needs more convincing. */
2550	#define IEMOPFORM_M_CL 8
2551	/** ModR/M: r/m (register), CL. */
2552	#define IEMOPFORM_M_CL_REG (IEMOPFORM_M_CL \| IEMOPFORM_MOD3)
2553	/** ModR/M: r/m (memory), CL. */
2554	#define IEMOPFORM_M_CL_MEM (IEMOPFORM_M_CL \| IEMOPFORM_NOT_MOD3)
2555	/** ModR/M: reg only */
2556	#define IEMOPFORM_R 9
2557
2558	/** VEX+ModR/M: reg, r/m */
2559	#define IEMOPFORM_VEX_RM 16
2560	/** VEX+ModR/M: reg, r/m (register) */
2561	#define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM \| IEMOPFORM_MOD3)
2562	/** VEX+ModR/M: reg, r/m (memory) */
2563	#define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM \| IEMOPFORM_NOT_MOD3)
2564	/** VEX+ModR/M: r/m, reg */
2565	#define IEMOPFORM_VEX_MR 17
2566	/** VEX+ModR/M: r/m (register), reg */
2567	#define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR \| IEMOPFORM_MOD3)
2568	/** VEX+ModR/M: r/m (memory), reg */
2569	#define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR \| IEMOPFORM_NOT_MOD3)
2570	/** VEX+ModR/M: r/m, reg, imm8 */
2571	#define IEMOPFORM_VEX_MRI 18
2572	/** VEX+ModR/M: r/m (register), reg, imm8 */
2573	#define IEMOPFORM_VEX_MRI_REG (IEMOPFORM_VEX_MRI \| IEMOPFORM_MOD3)
2574	/** VEX+ModR/M: r/m (memory), reg, imm8 */
2575	#define IEMOPFORM_VEX_MRI_MEM (IEMOPFORM_VEX_MRI \| IEMOPFORM_NOT_MOD3)
2576	/** VEX+ModR/M: r/m only */
2577	#define IEMOPFORM_VEX_M 19
2578	/** VEX+ModR/M: r/m only (register). */
2579	#define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M \| IEMOPFORM_MOD3)
2580	/** VEX+ModR/M: r/m only (memory). */
2581	#define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M \| IEMOPFORM_NOT_MOD3)
2582	/** VEX+ModR/M: reg only */
2583	#define IEMOPFORM_VEX_R 20
2584	/** VEX+ModR/M: reg, vvvv, r/m */
2585	#define IEMOPFORM_VEX_RVM 21
2586	/** VEX+ModR/M: reg, vvvv, r/m (register). */
2587	#define IEMOPFORM_VEX_RVM_REG (IEMOPFORM_VEX_RVM \| IEMOPFORM_MOD3)
2588	/** VEX+ModR/M: reg, vvvv, r/m (memory). */
2589	#define IEMOPFORM_VEX_RVM_MEM (IEMOPFORM_VEX_RVM \| IEMOPFORM_NOT_MOD3)
2590	/** VEX+ModR/M: reg, vvvv, r/m, imm */
2591	#define IEMOPFORM_VEX_RVMI 22
2592	/** VEX+ModR/M: reg, vvvv, r/m (register), imm. */
2593	#define IEMOPFORM_VEX_RVMI_REG (IEMOPFORM_VEX_RVMI \| IEMOPFORM_MOD3)
2594	/** VEX+ModR/M: reg, vvvv, r/m (memory), imm. */
2595	#define IEMOPFORM_VEX_RVMI_MEM (IEMOPFORM_VEX_RVMI \| IEMOPFORM_NOT_MOD3)
2596	/** VEX+ModR/M: reg, vvvv, r/m, imm(reg) */
2597	#define IEMOPFORM_VEX_RVMR 23
2598	/** VEX+ModR/M: reg, vvvv, r/m (register), imm(reg). */
2599	#define IEMOPFORM_VEX_RVMR_REG (IEMOPFORM_VEX_RVMI \| IEMOPFORM_MOD3)
2600	/** VEX+ModR/M: reg, vvvv, r/m (memory), imm(reg). */
2601	#define IEMOPFORM_VEX_RVMR_MEM (IEMOPFORM_VEX_RVMI \| IEMOPFORM_NOT_MOD3)
2602	/** VEX+ModR/M: reg, r/m, vvvv */
2603	#define IEMOPFORM_VEX_RMV 24
2604	/** VEX+ModR/M: reg, r/m, vvvv (register). */
2605	#define IEMOPFORM_VEX_RMV_REG (IEMOPFORM_VEX_RMV \| IEMOPFORM_MOD3)
2606	/** VEX+ModR/M: reg, r/m, vvvv (memory). */
2607	#define IEMOPFORM_VEX_RMV_MEM (IEMOPFORM_VEX_RMV \| IEMOPFORM_NOT_MOD3)
2608	/** VEX+ModR/M: reg, r/m, imm8 */
2609	#define IEMOPFORM_VEX_RMI 25
2610	/** VEX+ModR/M: reg, r/m, imm8 (register). */
2611	#define IEMOPFORM_VEX_RMI_REG (IEMOPFORM_VEX_RMI \| IEMOPFORM_MOD3)
2612	/** VEX+ModR/M: reg, r/m, imm8 (memory). */
2613	#define IEMOPFORM_VEX_RMI_MEM (IEMOPFORM_VEX_RMI \| IEMOPFORM_NOT_MOD3)
2614	/** VEX+ModR/M: r/m, vvvv, reg */
2615	#define IEMOPFORM_VEX_MVR 26
2616	/** VEX+ModR/M: r/m, vvvv, reg (register) */
2617	#define IEMOPFORM_VEX_MVR_REG (IEMOPFORM_VEX_MVR \| IEMOPFORM_MOD3)
2618	/** VEX+ModR/M: r/m, vvvv, reg (memory) */
2619	#define IEMOPFORM_VEX_MVR_MEM (IEMOPFORM_VEX_MVR \| IEMOPFORM_NOT_MOD3)
2620	/** VEX+ModR/M+/n: vvvv, r/m */
2621	#define IEMOPFORM_VEX_VM 27
2622	/** VEX+ModR/M+/n: vvvv, r/m (register) */
2623	#define IEMOPFORM_VEX_VM_REG (IEMOPFORM_VEX_VM \| IEMOPFORM_MOD3)
2624	/** VEX+ModR/M+/n: vvvv, r/m (memory) */
2625	#define IEMOPFORM_VEX_VM_MEM (IEMOPFORM_VEX_VM \| IEMOPFORM_NOT_MOD3)
2626	/** VEX+ModR/M+/n: vvvv, r/m, imm8 */
2627	#define IEMOPFORM_VEX_VMI 28
2628	/** VEX+ModR/M+/n: vvvv, r/m, imm8 (register) */
2629	#define IEMOPFORM_VEX_VMI_REG (IEMOPFORM_VEX_VMI \| IEMOPFORM_MOD3)
2630	/** VEX+ModR/M+/n: vvvv, r/m, imm8 (memory) */
2631	#define IEMOPFORM_VEX_VMI_MEM (IEMOPFORM_VEX_VMI \| IEMOPFORM_NOT_MOD3)
2632
2633	/** Fixed register instruction, no R/M. */
2634	#define IEMOPFORM_FIXED 32
2635
2636	/** The r/m is a register. */
2637	#define IEMOPFORM_MOD3 RT_BIT_32(8)
2638	/** The r/m is a memory access. */
2639	#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
2640	/** @} */
2641
2642	/** @name IEMOPHINT_XXX - Additional Opcode Hints
2643	* @note These are ORed together with IEMOPFORM_XXX.
2644	* @{ */
2645	/** Ignores the operand size prefix (66h). */
2646	#define IEMOPHINT_IGNORES_OZ_PFX RT_BIT_32(10)
2647	/** Ignores REX.W (aka WIG). */
2648	#define IEMOPHINT_IGNORES_REXW RT_BIT_32(11)
2649	/** Both the operand size prefixes (66h + REX.W) are ignored. */
2650	#define IEMOPHINT_IGNORES_OP_SIZES (IEMOPHINT_IGNORES_OZ_PFX \| IEMOPHINT_IGNORES_REXW)
2651	/** Allowed with the lock prefix. */
2652	#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
2653	/** The VEX.L value is ignored (aka LIG). */
2654	#define IEMOPHINT_VEX_L_IGNORED RT_BIT_32(12)
2655	/** The VEX.L value must be zero (i.e. 128-bit width only). */
2656	#define IEMOPHINT_VEX_L_ZERO RT_BIT_32(13)
2657	/** The VEX.L value must be one (i.e. 256-bit width only). */
2658	#define IEMOPHINT_VEX_L_ONE RT_BIT_32(14)
2659	/** The VEX.V value must be zero. */
2660	#define IEMOPHINT_VEX_V_ZERO RT_BIT_32(15)
2661	/** The REX.W/VEX.V value must be zero. */
2662	#define IEMOPHINT_REX_W_ZERO RT_BIT_32(16)
2663	#define IEMOPHINT_VEX_W_ZERO IEMOPHINT_REX_W_ZERO
2664	/** The REX.W/VEX.V value must be one. */
2665	#define IEMOPHINT_REX_W_ONE RT_BIT_32(17)
2666	#define IEMOPHINT_VEX_W_ONE IEMOPHINT_REX_W_ONE
2667
2668	/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
2669	#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
2670	/** @} */
2671
2672	/**
2673	* Possible hardware task switch sources.
2674	*/
2675	typedef enum IEMTASKSWITCH
2676	{
2677	/** Task switch caused by an interrupt/exception. */
2678	IEMTASKSWITCH_INT_XCPT = 1,
2679	/** Task switch caused by a far CALL. */
2680	IEMTASKSWITCH_CALL,
2681	/** Task switch caused by a far JMP. */
2682	IEMTASKSWITCH_JUMP,
2683	/** Task switch caused by an IRET. */
2684	IEMTASKSWITCH_IRET
2685	} IEMTASKSWITCH;
2686	AssertCompileSize(IEMTASKSWITCH, 4);
2687
2688	/**
2689	* Possible CrX load (write) sources.
2690	*/
2691	typedef enum IEMACCESSCRX
2692	{
2693	/** CrX access caused by 'mov crX' instruction. */
2694	IEMACCESSCRX_MOV_CRX,
2695	/** CrX (CR0) write caused by 'lmsw' instruction. */
2696	IEMACCESSCRX_LMSW,
2697	/** CrX (CR0) write caused by 'clts' instruction. */
2698	IEMACCESSCRX_CLTS,
2699	/** CrX (CR0) read caused by 'smsw' instruction. */
2700	IEMACCESSCRX_SMSW
2701	} IEMACCESSCRX;
2702
2703	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2704	/** @name IEM_SLAT_FAIL_XXX - Second-level address translation failure information.
2705	*
2706	* These flags provide further context to SLAT page-walk failures that could not be
2707	* determined by PGM (e.g, PGM is not privy to memory access permissions).
2708	*
2709	* @{
2710	*/
2711	/** Translating a nested-guest linear address failed accessing a nested-guest
2712	* physical address. */
2713	# define IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR RT_BIT_32(0)
2714	/** Translating a nested-guest linear address failed accessing a
2715	* paging-structure entry or updating accessed/dirty bits. */
2716	# define IEM_SLAT_FAIL_LINEAR_TO_PAGE_TABLE RT_BIT_32(1)
2717	/** @} */
2718
2719	DECLCALLBACK(FNPGMPHYSHANDLER) iemVmxApicAccessPageHandler;
2720	# ifndef IN_RING3
2721	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) iemVmxApicAccessPagePfHandler;
2722	# endif
2723	#endif
2724
2725	/**
2726	* Indicates to the verifier that the given flag set is undefined.
2727	*
2728	* Can be invoked again to add more flags.
2729	*
2730	* This is a NOOP if the verifier isn't compiled in.
2731	*
2732	* @note We're temporarily keeping this until code is converted to new
2733	* disassembler style opcode handling.
2734	*/
2735	#define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
2736
2737
2738	/** @def IEM_DECL_IMPL_TYPE
2739	* For typedef'ing an instruction implementation function.
2740	*
2741	* @param a_RetType The return type.
2742	* @param a_Name The name of the type.
2743	* @param a_ArgList The argument list enclosed in parentheses.
2744	*/
2745
2746	/** @def IEM_DECL_IMPL_DEF
2747	* For defining an instruction implementation function.
2748	*
2749	* @param a_RetType The return type.
2750	* @param a_Name The name of the type.
2751	* @param a_ArgList The argument list enclosed in parentheses.
2752	*/
2753
2754	#if defined(__GNUC__) && defined(RT_ARCH_X86)
2755	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2756	__attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
2757	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2758	__attribute__((__fastcall__, __nothrow__)) DECL_HIDDEN_ONLY(a_RetType) a_Name a_ArgList
2759	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2760	__attribute__((__fastcall__, __nothrow__)) DECL_HIDDEN_ONLY(a_RetType) a_Name a_ArgList
2761
2762	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
2763	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2764	a_RetType (__fastcall a_Name) a_ArgList
2765	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2766	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
2767	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2768	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
2769
2770	#elif __cplusplus >= 201700 /* P0012R1 support */
2771	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2772	a_RetType (VBOXCALL a_Name) a_ArgList RT_NOEXCEPT
2773	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2774	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList RT_NOEXCEPT
2775	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2776	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList RT_NOEXCEPT
2777
2778	#else
2779	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2780	a_RetType (VBOXCALL a_Name) a_ArgList
2781	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2782	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList
2783	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2784	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList
2785
2786	#endif
2787
2788	/** Defined in IEMAllAImplC.cpp but also used by IEMAllAImplA.asm. */
2789	RT_C_DECLS_BEGIN
2790	extern uint8_t const g_afParity[256];
2791	RT_C_DECLS_END
2792
2793
2794	/** @name Arithmetic assignment operations on bytes (binary).
2795	* @{ */
2796	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU8, (uint32_t fEFlagsIn, uint8_t *pu8Dst, uint8_t u8Src));
2797	typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
2798	FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
2799	FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
2800	FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
2801	FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
2802	FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
2803	FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
2804	FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
2805	/** @} */
2806
2807	/** @name Arithmetic assignment operations on words (binary).
2808	* @{ */
2809	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU16, (uint32_t fEFlagsIn, uint16_t *pu16Dst, uint16_t u16Src));
2810	typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
2811	FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
2812	FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
2813	FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
2814	FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
2815	FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
2816	FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
2817	FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
2818	/** @} */
2819
2820
2821	/** @name Arithmetic assignment operations on double words (binary).
2822	* @{ */
2823	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU32, (uint32_t fEFlagsIn, uint32_t *pu32Dst, uint32_t u32Src));
2824	typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
2825	FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
2826	FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
2827	FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
2828	FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
2829	FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
2830	FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
2831	FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
2832	FNIEMAIMPLBINU32 iemAImpl_blsi_u32, iemAImpl_blsi_u32_fallback;
2833	FNIEMAIMPLBINU32 iemAImpl_blsr_u32, iemAImpl_blsr_u32_fallback;
2834	FNIEMAIMPLBINU32 iemAImpl_blsmsk_u32, iemAImpl_blsmsk_u32_fallback;
2835	/** @} */
2836
2837	/** @name Arithmetic assignment operations on quad words (binary).
2838	* @{ */
2839	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU64, (uint32_t fEFlagsIn, uint64_t *pu64Dst, uint64_t u64Src));
2840	typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
2841	FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
2842	FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
2843	FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
2844	FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
2845	FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
2846	FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
2847	FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
2848	FNIEMAIMPLBINU64 iemAImpl_blsi_u64, iemAImpl_blsi_u64_fallback;
2849	FNIEMAIMPLBINU64 iemAImpl_blsr_u64, iemAImpl_blsr_u64_fallback;
2850	FNIEMAIMPLBINU64 iemAImpl_blsmsk_u64, iemAImpl_blsmsk_u64_fallback;
2851	/** @} */
2852
2853	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU8, (uint32_t fEFlagsIn, uint8_t const *pu8Dst, uint8_t u8Src));
2854	typedef FNIEMAIMPLBINROU8 *PFNIEMAIMPLBINROU8;
2855	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU16,(uint32_t fEFlagsIn, uint16_t const *pu16Dst, uint16_t u16Src));
2856	typedef FNIEMAIMPLBINROU16 *PFNIEMAIMPLBINROU16;
2857	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU32,(uint32_t fEFlagsIn, uint32_t const *pu32Dst, uint32_t u32Src));
2858	typedef FNIEMAIMPLBINROU32 *PFNIEMAIMPLBINROU32;
2859	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU64,(uint32_t fEFlagsIn, uint64_t const *pu64Dst, uint64_t u64Src));
2860	typedef FNIEMAIMPLBINROU64 *PFNIEMAIMPLBINROU64;
2861
2862	/** @name Compare operations (thrown in with the binary ops).
2863	* @{ */
2864	FNIEMAIMPLBINROU8 iemAImpl_cmp_u8;
2865	FNIEMAIMPLBINROU16 iemAImpl_cmp_u16;
2866	FNIEMAIMPLBINROU32 iemAImpl_cmp_u32;
2867	FNIEMAIMPLBINROU64 iemAImpl_cmp_u64;
2868	/** @} */
2869
2870	/** @name Test operations (thrown in with the binary ops).
2871	* @{ */
2872	FNIEMAIMPLBINROU8 iemAImpl_test_u8;
2873	FNIEMAIMPLBINROU16 iemAImpl_test_u16;
2874	FNIEMAIMPLBINROU32 iemAImpl_test_u32;
2875	FNIEMAIMPLBINROU64 iemAImpl_test_u64;
2876	/** @} */
2877
2878	/** @name Bit operations operations (thrown in with the binary ops).
2879	* @{ */
2880	FNIEMAIMPLBINROU16 iemAImpl_bt_u16;
2881	FNIEMAIMPLBINROU32 iemAImpl_bt_u32;
2882	FNIEMAIMPLBINROU64 iemAImpl_bt_u64;
2883	FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
2884	FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
2885	FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
2886	FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
2887	FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
2888	FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
2889	FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
2890	FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
2891	FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
2892	/** @} */
2893
2894	/** @name Arithmetic three operand operations on double words (binary).
2895	* @{ */
2896	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32, (uint32_t pu32Dst, uint32_t u32Src1, uint32_t u32Src2, uint32_t pEFlags));
2897	typedef FNIEMAIMPLBINVEXU32 *PFNIEMAIMPLBINVEXU32;
2898	FNIEMAIMPLBINVEXU32 iemAImpl_andn_u32, iemAImpl_andn_u32_fallback;
2899	FNIEMAIMPLBINVEXU32 iemAImpl_bextr_u32, iemAImpl_bextr_u32_fallback;
2900	FNIEMAIMPLBINVEXU32 iemAImpl_bzhi_u32, iemAImpl_bzhi_u32_fallback;
2901	/** @} */
2902
2903	/** @name Arithmetic three operand operations on quad words (binary).
2904	* @{ */
2905	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64, (uint64_t pu64Dst, uint64_t u64Src1, uint64_t u64Src2, uint32_t pEFlags));
2906	typedef FNIEMAIMPLBINVEXU64 *PFNIEMAIMPLBINVEXU64;
2907	FNIEMAIMPLBINVEXU64 iemAImpl_andn_u64, iemAImpl_andn_u64_fallback;
2908	FNIEMAIMPLBINVEXU64 iemAImpl_bextr_u64, iemAImpl_bextr_u64_fallback;
2909	FNIEMAIMPLBINVEXU64 iemAImpl_bzhi_u64, iemAImpl_bzhi_u64_fallback;
2910	/** @} */
2911
2912	/** @name Arithmetic three operand operations on double words w/o EFLAGS (binary).
2913	* @{ */
2914	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32NOEFL, (uint32_t *pu32Dst, uint32_t u32Src1, uint32_t u32Src2));
2915	typedef FNIEMAIMPLBINVEXU32NOEFL *PFNIEMAIMPLBINVEXU32NOEFL;
2916	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pdep_u32, iemAImpl_pdep_u32_fallback;
2917	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pext_u32, iemAImpl_pext_u32_fallback;
2918	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_sarx_u32, iemAImpl_sarx_u32_fallback;
2919	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shlx_u32, iemAImpl_shlx_u32_fallback;
2920	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shrx_u32, iemAImpl_shrx_u32_fallback;
2921	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_rorx_u32;
2922	/** @} */
2923
2924	/** @name Arithmetic three operand operations on quad words w/o EFLAGS (binary).
2925	* @{ */
2926	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64NOEFL, (uint64_t *pu64Dst, uint64_t u64Src1, uint64_t u64Src2));
2927	typedef FNIEMAIMPLBINVEXU64NOEFL *PFNIEMAIMPLBINVEXU64NOEFL;
2928	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pdep_u64, iemAImpl_pdep_u64_fallback;
2929	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pext_u64, iemAImpl_pext_u64_fallback;
2930	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_sarx_u64, iemAImpl_sarx_u64_fallback;
2931	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shlx_u64, iemAImpl_shlx_u64_fallback;
2932	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shrx_u64, iemAImpl_shrx_u64_fallback;
2933	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_rorx_u64;
2934	/** @} */
2935
2936	/** @name MULX 32-bit and 64-bit.
2937	* @{ */
2938	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU32, (uint32_t puDst1, uint32_t puDst2, uint32_t uSrc1, uint32_t uSrc2));
2939	typedef FNIEMAIMPLMULXVEXU32 *PFNIEMAIMPLMULXVEXU32;
2940	FNIEMAIMPLMULXVEXU32 iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback;
2941
2942	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU64, (uint64_t puDst1, uint64_t puDst2, uint64_t uSrc1, uint64_t uSrc2));
2943	typedef FNIEMAIMPLMULXVEXU64 *PFNIEMAIMPLMULXVEXU64;
2944	FNIEMAIMPLMULXVEXU64 iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback;
2945	/** @} */
2946
2947
2948	/** @name Exchange memory with register operations.
2949	* @{ */
2950	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_locked, (uint8_t pu8Mem, uint8_t pu8Reg));
2951	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_locked,(uint16_t pu16Mem, uint16_t pu16Reg));
2952	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_locked,(uint32_t pu32Mem, uint32_t pu32Reg));
2953	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_locked,(uint64_t pu64Mem, uint64_t pu64Reg));
2954	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_unlocked, (uint8_t pu8Mem, uint8_t pu8Reg));
2955	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_unlocked,(uint16_t pu16Mem, uint16_t pu16Reg));
2956	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_unlocked,(uint32_t pu32Mem, uint32_t pu32Reg));
2957	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_unlocked,(uint64_t pu64Mem, uint64_t pu64Reg));
2958	/** @} */
2959
2960	/** @name Exchange and add operations.
2961	* @{ */
2962	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
2963	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
2964	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
2965	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
2966	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
2967	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
2968	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
2969	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
2970	/** @} */
2971
2972	/** @name Compare and exchange.
2973	* @{ */
2974	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
2975	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
2976	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
2977	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
2978	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
2979	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
2980	#if ARCH_BITS == 32
2981	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
2982	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
2983	#else
2984	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
2985	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
2986	#endif
2987	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
2988	uint32_t *pEFlags));
2989	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
2990	uint32_t *pEFlags));
2991	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
2992	uint32_t *pEFlags));
2993	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
2994	uint32_t *pEFlags));
2995	#ifndef RT_ARCH_ARM64
2996	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
2997	PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
2998	#endif
2999	/** @} */
3000
3001	/** @name Memory ordering
3002	* @{ */
3003	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
3004	typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
3005	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
3006	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
3007	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
3008	#ifndef RT_ARCH_ARM64
3009	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
3010	#endif
3011	/** @} */
3012
3013	/** @name Double precision shifts
3014	* @{ */
3015	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t pEFlags));
3016	typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
3017	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t pEFlags));
3018	typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
3019	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t pEFlags));
3020	typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
3021	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16, iemAImpl_shld_u16_amd, iemAImpl_shld_u16_intel;
3022	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32, iemAImpl_shld_u32_amd, iemAImpl_shld_u32_intel;
3023	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64, iemAImpl_shld_u64_amd, iemAImpl_shld_u64_intel;
3024	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16, iemAImpl_shrd_u16_amd, iemAImpl_shrd_u16_intel;
3025	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32, iemAImpl_shrd_u32_amd, iemAImpl_shrd_u32_intel;
3026	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64, iemAImpl_shrd_u64_amd, iemAImpl_shrd_u64_intel;
3027	/** @} */
3028
3029
3030	/** @name Bit search operations (thrown in with the binary ops).
3031	* @{ */
3032	FNIEMAIMPLBINU16 iemAImpl_bsf_u16, iemAImpl_bsf_u16_amd, iemAImpl_bsf_u16_intel;
3033	FNIEMAIMPLBINU32 iemAImpl_bsf_u32, iemAImpl_bsf_u32_amd, iemAImpl_bsf_u32_intel;
3034	FNIEMAIMPLBINU64 iemAImpl_bsf_u64, iemAImpl_bsf_u64_amd, iemAImpl_bsf_u64_intel;
3035	FNIEMAIMPLBINU16 iemAImpl_bsr_u16, iemAImpl_bsr_u16_amd, iemAImpl_bsr_u16_intel;
3036	FNIEMAIMPLBINU32 iemAImpl_bsr_u32, iemAImpl_bsr_u32_amd, iemAImpl_bsr_u32_intel;
3037	FNIEMAIMPLBINU64 iemAImpl_bsr_u64, iemAImpl_bsr_u64_amd, iemAImpl_bsr_u64_intel;
3038	FNIEMAIMPLBINU16 iemAImpl_lzcnt_u16, iemAImpl_lzcnt_u16_amd, iemAImpl_lzcnt_u16_intel;
3039	FNIEMAIMPLBINU32 iemAImpl_lzcnt_u32, iemAImpl_lzcnt_u32_amd, iemAImpl_lzcnt_u32_intel;
3040	FNIEMAIMPLBINU64 iemAImpl_lzcnt_u64, iemAImpl_lzcnt_u64_amd, iemAImpl_lzcnt_u64_intel;
3041	FNIEMAIMPLBINU16 iemAImpl_tzcnt_u16, iemAImpl_tzcnt_u16_amd, iemAImpl_tzcnt_u16_intel;
3042	FNIEMAIMPLBINU32 iemAImpl_tzcnt_u32, iemAImpl_tzcnt_u32_amd, iemAImpl_tzcnt_u32_intel;
3043	FNIEMAIMPLBINU64 iemAImpl_tzcnt_u64, iemAImpl_tzcnt_u64_amd, iemAImpl_tzcnt_u64_intel;
3044	FNIEMAIMPLBINU16 iemAImpl_popcnt_u16, iemAImpl_popcnt_u16_fallback;
3045	FNIEMAIMPLBINU32 iemAImpl_popcnt_u32, iemAImpl_popcnt_u32_fallback;
3046	FNIEMAIMPLBINU64 iemAImpl_popcnt_u64, iemAImpl_popcnt_u64_fallback;
3047	/** @} */
3048
3049	/** @name Signed multiplication operations (thrown in with the binary ops).
3050	* @{ */
3051	FNIEMAIMPLBINU16 iemAImpl_imul_two_u16, iemAImpl_imul_two_u16_amd, iemAImpl_imul_two_u16_intel;
3052	FNIEMAIMPLBINU32 iemAImpl_imul_two_u32, iemAImpl_imul_two_u32_amd, iemAImpl_imul_two_u32_intel;
3053	FNIEMAIMPLBINU64 iemAImpl_imul_two_u64, iemAImpl_imul_two_u64_amd, iemAImpl_imul_two_u64_intel;
3054	/** @} */
3055
3056	/** @name Arithmetic assignment operations on bytes (unary).
3057	* @{ */
3058	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t pu8Dst, uint32_t pEFlags));
3059	typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
3060	FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
3061	FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
3062	FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
3063	FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
3064	/** @} */
3065
3066	/** @name Arithmetic assignment operations on words (unary).
3067	* @{ */
3068	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t pu16Dst, uint32_t pEFlags));
3069	typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
3070	FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
3071	FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
3072	FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
3073	FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
3074	/** @} */
3075
3076	/** @name Arithmetic assignment operations on double words (unary).
3077	* @{ */
3078	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t pu32Dst, uint32_t pEFlags));
3079	typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
3080	FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
3081	FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
3082	FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
3083	FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
3084	/** @} */
3085
3086	/** @name Arithmetic assignment operations on quad words (unary).
3087	* @{ */
3088	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t pu64Dst, uint32_t pEFlags));
3089	typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
3090	FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
3091	FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
3092	FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
3093	FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
3094	/** @} */
3095
3096
3097	/** @name Shift operations on bytes (Group 2).
3098	* @{ */
3099	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU8,(uint32_t fEFlagsIn, uint8_t *pu8Dst, uint8_t cShift));
3100	typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
3101	FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8, iemAImpl_rol_u8_amd, iemAImpl_rol_u8_intel;
3102	FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8, iemAImpl_ror_u8_amd, iemAImpl_ror_u8_intel;
3103	FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8, iemAImpl_rcl_u8_amd, iemAImpl_rcl_u8_intel;
3104	FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8, iemAImpl_rcr_u8_amd, iemAImpl_rcr_u8_intel;
3105	FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8, iemAImpl_shl_u8_amd, iemAImpl_shl_u8_intel;
3106	FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8, iemAImpl_shr_u8_amd, iemAImpl_shr_u8_intel;
3107	FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8, iemAImpl_sar_u8_amd, iemAImpl_sar_u8_intel;
3108	/** @} */
3109
3110	/** @name Shift operations on words (Group 2).
3111	* @{ */
3112	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU16,(uint32_t fEFlagsIn, uint16_t *pu16Dst, uint8_t cShift));
3113	typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
3114	FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16, iemAImpl_rol_u16_amd, iemAImpl_rol_u16_intel;
3115	FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16, iemAImpl_ror_u16_amd, iemAImpl_ror_u16_intel;
3116	FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16, iemAImpl_rcl_u16_amd, iemAImpl_rcl_u16_intel;
3117	FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16, iemAImpl_rcr_u16_amd, iemAImpl_rcr_u16_intel;
3118	FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16, iemAImpl_shl_u16_amd, iemAImpl_shl_u16_intel;
3119	FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16, iemAImpl_shr_u16_amd, iemAImpl_shr_u16_intel;
3120	FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16, iemAImpl_sar_u16_amd, iemAImpl_sar_u16_intel;
3121	/** @} */
3122
3123	/** @name Shift operations on double words (Group 2).
3124	* @{ */
3125	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU32,(uint32_t fEFlagsIn, uint32_t *pu32Dst, uint8_t cShift));
3126	typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
3127	FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32, iemAImpl_rol_u32_amd, iemAImpl_rol_u32_intel;
3128	FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32, iemAImpl_ror_u32_amd, iemAImpl_ror_u32_intel;
3129	FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32, iemAImpl_rcl_u32_amd, iemAImpl_rcl_u32_intel;
3130	FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32, iemAImpl_rcr_u32_amd, iemAImpl_rcr_u32_intel;
3131	FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32, iemAImpl_shl_u32_amd, iemAImpl_shl_u32_intel;
3132	FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32, iemAImpl_shr_u32_amd, iemAImpl_shr_u32_intel;
3133	FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32, iemAImpl_sar_u32_amd, iemAImpl_sar_u32_intel;
3134	/** @} */
3135
3136	/** @name Shift operations on words (Group 2).
3137	* @{ */
3138	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU64,(uint32_t fEFlagsIn, uint64_t *pu64Dst, uint8_t cShift));
3139	typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
3140	FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64, iemAImpl_rol_u64_amd, iemAImpl_rol_u64_intel;
3141	FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64, iemAImpl_ror_u64_amd, iemAImpl_ror_u64_intel;
3142	FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64, iemAImpl_rcl_u64_amd, iemAImpl_rcl_u64_intel;
3143	FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64, iemAImpl_rcr_u64_amd, iemAImpl_rcr_u64_intel;
3144	FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64, iemAImpl_shl_u64_amd, iemAImpl_shl_u64_intel;
3145	FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64, iemAImpl_shr_u64_amd, iemAImpl_shr_u64_intel;
3146	FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64, iemAImpl_sar_u64_amd, iemAImpl_sar_u64_intel;
3147	/** @} */
3148
3149	/** @name Multiplication and division operations.
3150	* @{ */
3151	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t pu16AX, uint8_t u8FactorDivisor, uint32_t pEFlags));
3152	typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
3153	FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_mul_u8_amd, iemAImpl_mul_u8_intel;
3154	FNIEMAIMPLMULDIVU8 iemAImpl_imul_u8, iemAImpl_imul_u8_amd, iemAImpl_imul_u8_intel;
3155	FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_div_u8_amd, iemAImpl_div_u8_intel;
3156	FNIEMAIMPLMULDIVU8 iemAImpl_idiv_u8, iemAImpl_idiv_u8_amd, iemAImpl_idiv_u8_intel;
3157
3158	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t pu16AX, uint16_t pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
3159	typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
3160	FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_mul_u16_amd, iemAImpl_mul_u16_intel;
3161	FNIEMAIMPLMULDIVU16 iemAImpl_imul_u16, iemAImpl_imul_u16_amd, iemAImpl_imul_u16_intel;
3162	FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_div_u16_amd, iemAImpl_div_u16_intel;
3163	FNIEMAIMPLMULDIVU16 iemAImpl_idiv_u16, iemAImpl_idiv_u16_amd, iemAImpl_idiv_u16_intel;
3164
3165	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t pu32EAX, uint32_t pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
3166	typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
3167	FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_mul_u32_amd, iemAImpl_mul_u32_intel;
3168	FNIEMAIMPLMULDIVU32 iemAImpl_imul_u32, iemAImpl_imul_u32_amd, iemAImpl_imul_u32_intel;
3169	FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_div_u32_amd, iemAImpl_div_u32_intel;
3170	FNIEMAIMPLMULDIVU32 iemAImpl_idiv_u32, iemAImpl_idiv_u32_amd, iemAImpl_idiv_u32_intel;
3171
3172	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t pu64RAX, uint64_t pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
3173	typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
3174	FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_mul_u64_amd, iemAImpl_mul_u64_intel;
3175	FNIEMAIMPLMULDIVU64 iemAImpl_imul_u64, iemAImpl_imul_u64_amd, iemAImpl_imul_u64_intel;
3176	FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_div_u64_amd, iemAImpl_div_u64_intel;
3177	FNIEMAIMPLMULDIVU64 iemAImpl_idiv_u64, iemAImpl_idiv_u64_amd, iemAImpl_idiv_u64_intel;
3178	/** @} */
3179
3180	/** @name Byte Swap.
3181	* @{ */
3182	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t pu32Dst)); / Yes, 32-bit register access. */
3183	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
3184	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
3185	/** @} */
3186
3187	/** @name Misc.
3188	* @{ */
3189	FNIEMAIMPLBINU16 iemAImpl_arpl;
3190	/** @} */
3191
3192	/** @name RDRAND and RDSEED
3193	* @{ */
3194	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU16,(uint16_t puDst, uint32_t pEFlags));
3195	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU32,(uint32_t puDst, uint32_t pEFlags));
3196	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU64,(uint64_t puDst, uint32_t pEFlags));
3197	typedef FNIEMAIMPLRDRANDSEEDU16 *PFNIEMAIMPLRDRANDSEEDU16;
3198	typedef FNIEMAIMPLRDRANDSEEDU32 *PFNIEMAIMPLRDRANDSEEDU32;
3199	typedef FNIEMAIMPLRDRANDSEEDU64 *PFNIEMAIMPLRDRANDSEEDU64;
3200
3201	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdrand_u16, iemAImpl_rdrand_u16_fallback;
3202	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdrand_u32, iemAImpl_rdrand_u32_fallback;
3203	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdrand_u64, iemAImpl_rdrand_u64_fallback;
3204	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdseed_u16, iemAImpl_rdseed_u16_fallback;
3205	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdseed_u32, iemAImpl_rdseed_u32_fallback;
3206	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdseed_u64, iemAImpl_rdseed_u64_fallback;
3207	/** @} */
3208
3209	/** @name ADOX and ADCX
3210	* @{ */
3211	FNIEMAIMPLBINU32 iemAImpl_adcx_u32, iemAImpl_adcx_u32_fallback;
3212	FNIEMAIMPLBINU64 iemAImpl_adcx_u64, iemAImpl_adcx_u64_fallback;
3213	FNIEMAIMPLBINU32 iemAImpl_adox_u32, iemAImpl_adox_u32_fallback;
3214	FNIEMAIMPLBINU64 iemAImpl_adox_u64, iemAImpl_adox_u64_fallback;
3215	/** @} */
3216
3217	/** @name FPU operations taking a 32-bit float argument
3218	* @{ */
3219	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3220	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
3221	typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
3222
3223	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3224	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
3225	typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
3226
3227	FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
3228	FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
3229	FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
3230	FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
3231	FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
3232	FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
3233	FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
3234
3235	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
3236	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3237	PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
3238	/** @} */
3239
3240	/** @name FPU operations taking a 64-bit float argument
3241	* @{ */
3242	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3243	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
3244	typedef FNIEMAIMPLFPUR64FSW *PFNIEMAIMPLFPUR64FSW;
3245
3246	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3247	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
3248	typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
3249
3250	FNIEMAIMPLFPUR64FSW iemAImpl_fcom_r80_by_r64;
3251	FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
3252	FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
3253	FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
3254	FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
3255	FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
3256	FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
3257
3258	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
3259	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3260	PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
3261	/** @} */
3262
3263	/** @name FPU operations taking a 80-bit float argument
3264	* @{ */
3265	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3266	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
3267	typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
3268	FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
3269	FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
3270	FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
3271	FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
3272	FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
3273	FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
3274	FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
3275	FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
3276	FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
3277
3278	FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80, iemAImpl_fpatan_r80_by_r80_amd, iemAImpl_fpatan_r80_by_r80_intel;
3279	FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80, iemAImpl_fyl2x_r80_by_r80_amd, iemAImpl_fyl2x_r80_by_r80_intel;
3280	FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80, iemAImpl_fyl2xp1_r80_by_r80_amd, iemAImpl_fyl2xp1_r80_by_r80_intel;
3281
3282	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3283	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
3284	typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
3285	FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
3286	FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
3287
3288	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
3289	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
3290	typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
3291	FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
3292	FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
3293
3294	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
3295	typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
3296	FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
3297	FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
3298	FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80, iemAImpl_f2xm1_r80_amd, iemAImpl_f2xm1_r80_intel;
3299	FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
3300	FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
3301	FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80, iemAImpl_fsin_r80_amd, iemAImpl_fsin_r80_intel;
3302	FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80, iemAImpl_fcos_r80_amd, iemAImpl_fcos_r80_intel;
3303
3304	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
3305	typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
3306	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
3307	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
3308
3309	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
3310	typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
3311	FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
3312	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
3313	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
3314	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
3315	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
3316	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
3317	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
3318
3319	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
3320	PCRTFLOAT80U pr80Val));
3321	typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
3322	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80, iemAImpl_fptan_r80_r80_amd, iemAImpl_fptan_r80_r80_intel;
3323	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
3324	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80, iemAImpl_fsincos_r80_r80_amd, iemAImpl_fsincos_r80_r80_intel;
3325
3326	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
3327	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3328	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
3329
3330	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_d80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTPBCD80U pd80Val));
3331	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_d80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3332	PRTPBCD80U pd80Dst, PCRTFLOAT80U pr80Src));
3333
3334	/** @} */
3335
3336	/** @name FPU operations taking a 16-bit signed integer argument
3337	* @{ */
3338	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3339	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
3340	typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
3341	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI16,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3342	int16_t *pi16Dst, PCRTFLOAT80U pr80Src));
3343	typedef FNIEMAIMPLFPUSTR80TOI16 *PFNIEMAIMPLFPUSTR80TOI16;
3344
3345	FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
3346	FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
3347	FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
3348	FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
3349	FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
3350	FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
3351
3352	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3353	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
3354	typedef FNIEMAIMPLFPUI16FSW *PFNIEMAIMPLFPUI16FSW;
3355	FNIEMAIMPLFPUI16FSW iemAImpl_ficom_r80_by_i16;
3356
3357	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
3358	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fist_r80_to_i16;
3359	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fistt_r80_to_i16, iemAImpl_fistt_r80_to_i16_amd, iemAImpl_fistt_r80_to_i16_intel;
3360	/** @} */
3361
3362	/** @name FPU operations taking a 32-bit signed integer argument
3363	* @{ */
3364	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3365	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
3366	typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
3367	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI32,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3368	int32_t *pi32Dst, PCRTFLOAT80U pr80Src));
3369	typedef FNIEMAIMPLFPUSTR80TOI32 *PFNIEMAIMPLFPUSTR80TOI32;
3370
3371	FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
3372	FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
3373	FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
3374	FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
3375	FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
3376	FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
3377
3378	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3379	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
3380	typedef FNIEMAIMPLFPUI32FSW *PFNIEMAIMPLFPUI32FSW;
3381	FNIEMAIMPLFPUI32FSW iemAImpl_ficom_r80_by_i32;
3382
3383	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
3384	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fist_r80_to_i32;
3385	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fistt_r80_to_i32;
3386	/** @} */
3387
3388	/** @name FPU operations taking a 64-bit signed integer argument
3389	* @{ */
3390	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI64,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3391	int64_t *pi64Dst, PCRTFLOAT80U pr80Src));
3392	typedef FNIEMAIMPLFPUSTR80TOI64 *PFNIEMAIMPLFPUSTR80TOI64;
3393
3394	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
3395	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fist_r80_to_i64;
3396	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fistt_r80_to_i64;
3397	/** @} */
3398
3399
3400	/** Temporary type representing a 256-bit vector register. */
3401	typedef struct { uint64_t au64[4]; } IEMVMM256;
3402	/** Temporary type pointing to a 256-bit vector register. */
3403	typedef IEMVMM256 *PIEMVMM256;
3404	/** Temporary type pointing to a const 256-bit vector register. */
3405	typedef IEMVMM256 *PCIEMVMM256;
3406
3407
3408	/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
3409	* @{ */
3410	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t puDst, uint64_t const puSrc));
3411	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
3412	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U128,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
3413	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
3414	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U128,(PX86XSAVEAREA pExtState, PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
3415	typedef FNIEMAIMPLMEDIAF3U128 *PFNIEMAIMPLMEDIAF3U128;
3416	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U256,(PX86XSAVEAREA pExtState, PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
3417	typedef FNIEMAIMPLMEDIAF3U256 *PFNIEMAIMPLMEDIAF3U256;
3418	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U64,(uint64_t puDst, uint64_t const puSrc));
3419	typedef FNIEMAIMPLMEDIAOPTF2U64 *PFNIEMAIMPLMEDIAOPTF2U64;
3420	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128,(PRTUINT128U puDst, PCRTUINT128U puSrc));
3421	typedef FNIEMAIMPLMEDIAOPTF2U128 *PFNIEMAIMPLMEDIAOPTF2U128;
3422	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
3423	typedef FNIEMAIMPLMEDIAOPTF3U128 *PFNIEMAIMPLMEDIAOPTF3U128;
3424	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
3425	typedef FNIEMAIMPLMEDIAOPTF3U256 *PFNIEMAIMPLMEDIAOPTF3U256;
3426	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256,(PRTUINT256U puDst, PCRTUINT256U puSrc));
3427	typedef FNIEMAIMPLMEDIAOPTF2U256 *PFNIEMAIMPLMEDIAOPTF2U256;
3428	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pshufb_u64, iemAImpl_pshufb_u64_fallback;
3429	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pand_u64, iemAImpl_pandn_u64, iemAImpl_por_u64, iemAImpl_pxor_u64;
3430	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
3431	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pcmpgtb_u64, iemAImpl_pcmpgtw_u64, iemAImpl_pcmpgtd_u64;
3432	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddb_u64, iemAImpl_paddsb_u64, iemAImpl_paddusb_u64;
3433	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddw_u64, iemAImpl_paddsw_u64, iemAImpl_paddusw_u64;
3434	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddd_u64;
3435	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddq_u64;
3436	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubb_u64, iemAImpl_psubsb_u64, iemAImpl_psubusb_u64;
3437	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubw_u64, iemAImpl_psubsw_u64, iemAImpl_psubusw_u64;
3438	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubd_u64;
3439	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubq_u64;
3440	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmaddwd_u64, iemAImpl_pmaddwd_u64_fallback;
3441	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmullw_u64, iemAImpl_pmulhw_u64;
3442	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pminub_u64, iemAImpl_pmaxub_u64;
3443	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pminsw_u64, iemAImpl_pmaxsw_u64;
3444	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pabsb_u64, iemAImpl_pabsb_u64_fallback;
3445	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pabsw_u64, iemAImpl_pabsw_u64_fallback;
3446	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pabsd_u64, iemAImpl_pabsd_u64_fallback;
3447	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psignb_u64, iemAImpl_psignb_u64_fallback;
3448	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psignw_u64, iemAImpl_psignw_u64_fallback;
3449	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psignd_u64, iemAImpl_psignd_u64_fallback;
3450	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phaddw_u64, iemAImpl_phaddw_u64_fallback;
3451	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phaddd_u64, iemAImpl_phaddd_u64_fallback;
3452	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phsubw_u64, iemAImpl_phsubw_u64_fallback;
3453	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phsubd_u64, iemAImpl_phsubd_u64_fallback;
3454	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phaddsw_u64, iemAImpl_phaddsw_u64_fallback;
3455	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phsubsw_u64, iemAImpl_phsubsw_u64_fallback;
3456	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmaddubsw_u64, iemAImpl_pmaddubsw_u64_fallback;
3457	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhrsw_u64, iemAImpl_pmulhrsw_u64_fallback;
3458	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmuludq_u64;
3459	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllw_u64, iemAImpl_psrlw_u64, iemAImpl_psraw_u64;
3460	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pslld_u64, iemAImpl_psrld_u64, iemAImpl_psrad_u64;
3461	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllq_u64, iemAImpl_psrlq_u64;
3462	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packsswb_u64, iemAImpl_packuswb_u64;
3463	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packssdw_u64;
3464	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhuw_u64;
3465	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pavgb_u64, iemAImpl_pavgw_u64;
3466	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psadbw_u64;
3467
3468	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pshufb_u128, iemAImpl_pshufb_u128_fallback;
3469	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pand_u128, iemAImpl_pandn_u128, iemAImpl_por_u128, iemAImpl_pxor_u128;
3470	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
3471	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpeqq_u128, iemAImpl_pcmpeqq_u128_fallback;
3472	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpgtb_u128, iemAImpl_pcmpgtw_u128, iemAImpl_pcmpgtd_u128;
3473	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpgtq_u128, iemAImpl_pcmpgtq_u128_fallback;
3474	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddb_u128, iemAImpl_paddsb_u128, iemAImpl_paddusb_u128;
3475	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddw_u128, iemAImpl_paddsw_u128, iemAImpl_paddusw_u128;
3476	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddd_u128;
3477	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddq_u128;
3478	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubb_u128, iemAImpl_psubsb_u128, iemAImpl_psubusb_u128;
3479	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubw_u128, iemAImpl_psubsw_u128, iemAImpl_psubusw_u128;
3480	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubd_u128;
3481	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubq_u128;
3482	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmullw_u128, iemAImpl_pmullw_u128_fallback;
3483	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhw_u128;
3484	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulld_u128, iemAImpl_pmulld_u128_fallback;
3485	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaddwd_u128, iemAImpl_pmaddwd_u128_fallback;
3486	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminub_u128;
3487	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminud_u128, iemAImpl_pminud_u128_fallback;
3488	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminuw_u128, iemAImpl_pminuw_u128_fallback;
3489	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminsb_u128, iemAImpl_pminsb_u128_fallback;
3490	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminsd_u128, iemAImpl_pminsd_u128_fallback;
3491	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminsw_u128, iemAImpl_pminsw_u128_fallback;
3492	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxub_u128;
3493	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxud_u128, iemAImpl_pmaxud_u128_fallback;
3494	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxuw_u128, iemAImpl_pmaxuw_u128_fallback;
3495	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxsb_u128, iemAImpl_pmaxsb_u128_fallback;
3496	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxsw_u128;
3497	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxsd_u128, iemAImpl_pmaxsd_u128_fallback;
3498	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pabsb_u128, iemAImpl_pabsb_u128_fallback;
3499	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pabsw_u128, iemAImpl_pabsw_u128_fallback;
3500	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pabsd_u128, iemAImpl_pabsd_u128_fallback;
3501	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psignb_u128, iemAImpl_psignb_u128_fallback;
3502	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psignw_u128, iemAImpl_psignw_u128_fallback;
3503	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psignd_u128, iemAImpl_psignd_u128_fallback;
3504	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phaddw_u128, iemAImpl_phaddw_u128_fallback;
3505	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phaddd_u128, iemAImpl_phaddd_u128_fallback;
3506	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phsubw_u128, iemAImpl_phsubw_u128_fallback;
3507	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phsubd_u128, iemAImpl_phsubd_u128_fallback;
3508	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phaddsw_u128, iemAImpl_phaddsw_u128_fallback;
3509	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phsubsw_u128, iemAImpl_phsubsw_u128_fallback;
3510	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaddubsw_u128, iemAImpl_pmaddubsw_u128_fallback;
3511	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhrsw_u128, iemAImpl_pmulhrsw_u128_fallback;
3512	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuludq_u128;
3513	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaddwd_u128, iemAImpl_pmaddwd_u128_fallback;
3514	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packsswb_u128, iemAImpl_packuswb_u128;
3515	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packssdw_u128, iemAImpl_packusdw_u128;
3516	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllw_u128, iemAImpl_psrlw_u128, iemAImpl_psraw_u128;
3517	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pslld_u128, iemAImpl_psrld_u128, iemAImpl_psrad_u128;
3518	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllq_u128, iemAImpl_psrlq_u128;
3519	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhuw_u128;
3520	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pavgb_u128, iemAImpl_pavgw_u128;
3521	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psadbw_u128;
3522	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuldq_u128, iemAImpl_pmuldq_u128_fallback;
3523	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpcklps_u128, iemAImpl_unpcklpd_u128;
3524	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpckhps_u128, iemAImpl_unpckhpd_u128;
3525	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phminposuw_u128, iemAImpl_phminposuw_u128_fallback;
3526
3527	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpshufb_u128, iemAImpl_vpshufb_u128_fallback;
3528	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpand_u128, iemAImpl_vpand_u128_fallback;
3529	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpandn_u128, iemAImpl_vpandn_u128_fallback;
3530	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpor_u128, iemAImpl_vpor_u128_fallback;
3531	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpxor_u128, iemAImpl_vpxor_u128_fallback;
3532	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqb_u128, iemAImpl_vpcmpeqb_u128_fallback;
3533	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqw_u128, iemAImpl_vpcmpeqw_u128_fallback;
3534	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqd_u128, iemAImpl_vpcmpeqd_u128_fallback;
3535	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqq_u128, iemAImpl_vpcmpeqq_u128_fallback;
3536	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtb_u128, iemAImpl_vpcmpgtb_u128_fallback;
3537	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtw_u128, iemAImpl_vpcmpgtw_u128_fallback;
3538	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtd_u128, iemAImpl_vpcmpgtd_u128_fallback;
3539	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtq_u128, iemAImpl_vpcmpgtq_u128_fallback;
3540	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddb_u128, iemAImpl_vpaddb_u128_fallback;
3541	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddw_u128, iemAImpl_vpaddw_u128_fallback;
3542	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddd_u128, iemAImpl_vpaddd_u128_fallback;
3543	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddq_u128, iemAImpl_vpaddq_u128_fallback;
3544	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubb_u128, iemAImpl_vpsubb_u128_fallback;
3545	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubw_u128, iemAImpl_vpsubw_u128_fallback;
3546	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubd_u128, iemAImpl_vpsubd_u128_fallback;
3547	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubq_u128, iemAImpl_vpsubq_u128_fallback;
3548	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminub_u128, iemAImpl_vpminub_u128_fallback;
3549	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminuw_u128, iemAImpl_vpminuw_u128_fallback;
3550	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminud_u128, iemAImpl_vpminud_u128_fallback;
3551	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminsb_u128, iemAImpl_vpminsb_u128_fallback;
3552	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminsw_u128, iemAImpl_vpminsw_u128_fallback;
3553	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminsd_u128, iemAImpl_vpminsd_u128_fallback;
3554	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxub_u128, iemAImpl_vpmaxub_u128_fallback;
3555	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxuw_u128, iemAImpl_vpmaxuw_u128_fallback;
3556	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxud_u128, iemAImpl_vpmaxud_u128_fallback;
3557	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxsb_u128, iemAImpl_vpmaxsb_u128_fallback;
3558	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxsw_u128, iemAImpl_vpmaxsw_u128_fallback;
3559	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxsd_u128, iemAImpl_vpmaxsd_u128_fallback;
3560	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpacksswb_u128, iemAImpl_vpacksswb_u128_fallback;
3561	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackssdw_u128, iemAImpl_vpackssdw_u128_fallback;
3562	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackuswb_u128, iemAImpl_vpackuswb_u128_fallback;
3563	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackusdw_u128, iemAImpl_vpackusdw_u128_fallback;
3564	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmullw_u128, iemAImpl_vpmullw_u128_fallback;
3565	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulld_u128, iemAImpl_vpmulld_u128_fallback;
3566	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhw_u128, iemAImpl_vpmulhw_u128_fallback;
3567	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhuw_u128, iemAImpl_vpmulhuw_u128_fallback;
3568	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgb_u128, iemAImpl_vpavgb_u128_fallback;
3569	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgw_u128, iemAImpl_vpavgw_u128_fallback;
3570	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignb_u128, iemAImpl_vpsignb_u128_fallback;
3571	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignw_u128, iemAImpl_vpsignw_u128_fallback;
3572	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignd_u128, iemAImpl_vpsignd_u128_fallback;
3573	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddw_u128, iemAImpl_vphaddw_u128_fallback;
3574	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddd_u128, iemAImpl_vphaddd_u128_fallback;
3575	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubw_u128, iemAImpl_vphsubw_u128_fallback;
3576	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubd_u128, iemAImpl_vphsubd_u128_fallback;
3577	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddsw_u128, iemAImpl_vphaddsw_u128_fallback;
3578	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubsw_u128, iemAImpl_vphsubsw_u128_fallback;
3579	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddubsw_u128, iemAImpl_vpmaddubsw_u128_fallback;
3580	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhrsw_u128, iemAImpl_vpmulhrsw_u128_fallback;
3581	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsadbw_u128, iemAImpl_vpsadbw_u128_fallback;
3582	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuldq_u128, iemAImpl_vpmuldq_u128_fallback;
3583	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuludq_u128, iemAImpl_vpmuludq_u128_fallback;
3584	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsb_u128, iemAImpl_vpsubsb_u128_fallback;
3585	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsw_u128, iemAImpl_vpsubsw_u128_fallback;
3586	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusb_u128, iemAImpl_vpsubusb_u128_fallback;
3587	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusw_u128, iemAImpl_vpsubusw_u128_fallback;
3588	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusb_u128, iemAImpl_vpaddusb_u128_fallback;
3589	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusw_u128, iemAImpl_vpaddusw_u128_fallback;
3590	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsb_u128, iemAImpl_vpaddsb_u128_fallback;
3591	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsw_u128, iemAImpl_vpaddsw_u128_fallback;
3592	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllw_u128, iemAImpl_vpsllw_u128_fallback;
3593	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpslld_u128, iemAImpl_vpslld_u128_fallback;
3594	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllq_u128, iemAImpl_vpsllq_u128_fallback;
3595	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsraw_u128, iemAImpl_vpsraw_u128_fallback;
3596	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrad_u128, iemAImpl_vpsrad_u128_fallback;
3597	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlw_u128, iemAImpl_vpsrlw_u128_fallback;
3598	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrld_u128, iemAImpl_vpsrld_u128_fallback;
3599	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlq_u128, iemAImpl_vpsrlq_u128_fallback;
3600	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddwd_u128, iemAImpl_vpmaddwd_u128_fallback;
3601
3602	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsb_u128, iemAImpl_vpabsb_u128_fallback;
3603	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsw_u128, iemAImpl_vpabsd_u128_fallback;
3604	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsd_u128, iemAImpl_vpabsw_u128_fallback;
3605	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vphminposuw_u128, iemAImpl_vphminposuw_u128_fallback;
3606
3607	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpshufb_u256, iemAImpl_vpshufb_u256_fallback;
3608	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpand_u256, iemAImpl_vpand_u256_fallback;
3609	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpandn_u256, iemAImpl_vpandn_u256_fallback;
3610	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpor_u256, iemAImpl_vpor_u256_fallback;
3611	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpxor_u256, iemAImpl_vpxor_u256_fallback;
3612	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqb_u256, iemAImpl_vpcmpeqb_u256_fallback;
3613	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqw_u256, iemAImpl_vpcmpeqw_u256_fallback;
3614	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqd_u256, iemAImpl_vpcmpeqd_u256_fallback;
3615	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqq_u256, iemAImpl_vpcmpeqq_u256_fallback;
3616	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtb_u256, iemAImpl_vpcmpgtb_u256_fallback;
3617	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtw_u256, iemAImpl_vpcmpgtw_u256_fallback;
3618	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtd_u256, iemAImpl_vpcmpgtd_u256_fallback;
3619	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtq_u256, iemAImpl_vpcmpgtq_u256_fallback;
3620	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddb_u256, iemAImpl_vpaddb_u256_fallback;
3621	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddw_u256, iemAImpl_vpaddw_u256_fallback;
3622	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddd_u256, iemAImpl_vpaddd_u256_fallback;
3623	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddq_u256, iemAImpl_vpaddq_u256_fallback;
3624	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubb_u256, iemAImpl_vpsubb_u256_fallback;
3625	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubw_u256, iemAImpl_vpsubw_u256_fallback;
3626	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubd_u256, iemAImpl_vpsubd_u256_fallback;
3627	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubq_u256, iemAImpl_vpsubq_u256_fallback;
3628	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminub_u256, iemAImpl_vpminub_u256_fallback;
3629	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminuw_u256, iemAImpl_vpminuw_u256_fallback;
3630	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminud_u256, iemAImpl_vpminud_u256_fallback;
3631	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminsb_u256, iemAImpl_vpminsb_u256_fallback;
3632	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminsw_u256, iemAImpl_vpminsw_u256_fallback;
3633	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminsd_u256, iemAImpl_vpminsd_u256_fallback;
3634	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxub_u256, iemAImpl_vpmaxub_u256_fallback;
3635	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxuw_u256, iemAImpl_vpmaxuw_u256_fallback;
3636	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxud_u256, iemAImpl_vpmaxud_u256_fallback;
3637	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxsb_u256, iemAImpl_vpmaxsb_u256_fallback;
3638	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxsw_u256, iemAImpl_vpmaxsw_u256_fallback;
3639	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxsd_u256, iemAImpl_vpmaxsd_u256_fallback;
3640	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpacksswb_u256, iemAImpl_vpacksswb_u256_fallback;
3641	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackssdw_u256, iemAImpl_vpackssdw_u256_fallback;
3642	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackuswb_u256, iemAImpl_vpackuswb_u256_fallback;
3643	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackusdw_u256, iemAImpl_vpackusdw_u256_fallback;
3644	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmullw_u256, iemAImpl_vpmullw_u256_fallback;
3645	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulld_u256, iemAImpl_vpmulld_u256_fallback;
3646	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhw_u256, iemAImpl_vpmulhw_u256_fallback;
3647	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhuw_u256, iemAImpl_vpmulhuw_u256_fallback;
3648	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgb_u256, iemAImpl_vpavgb_u256_fallback;
3649	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgw_u256, iemAImpl_vpavgw_u256_fallback;
3650	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignb_u256, iemAImpl_vpsignb_u256_fallback;
3651	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignw_u256, iemAImpl_vpsignw_u256_fallback;
3652	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignd_u256, iemAImpl_vpsignd_u256_fallback;
3653	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddw_u256, iemAImpl_vphaddw_u256_fallback;
3654	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddd_u256, iemAImpl_vphaddd_u256_fallback;
3655	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubw_u256, iemAImpl_vphsubw_u256_fallback;
3656	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubd_u256, iemAImpl_vphsubd_u256_fallback;
3657	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddsw_u256, iemAImpl_vphaddsw_u256_fallback;
3658	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubsw_u256, iemAImpl_vphsubsw_u256_fallback;
3659	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddubsw_u256, iemAImpl_vpmaddubsw_u256_fallback;
3660	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhrsw_u256, iemAImpl_vpmulhrsw_u256_fallback;
3661	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsadbw_u256, iemAImpl_vpsadbw_u256_fallback;
3662	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuldq_u256, iemAImpl_vpmuldq_u256_fallback;
3663	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuludq_u256, iemAImpl_vpmuludq_u256_fallback;
3664	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsb_u256, iemAImpl_vpsubsb_u256_fallback;
3665	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsw_u256, iemAImpl_vpsubsw_u256_fallback;
3666	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusb_u256, iemAImpl_vpsubusb_u256_fallback;
3667	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusw_u256, iemAImpl_vpsubusw_u256_fallback;
3668	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusb_u256, iemAImpl_vpaddusb_u256_fallback;
3669	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusw_u256, iemAImpl_vpaddusw_u256_fallback;
3670	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsb_u256, iemAImpl_vpaddsb_u256_fallback;
3671	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsw_u256, iemAImpl_vpaddsw_u256_fallback;
3672	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllw_u256, iemAImpl_vpsllw_u256_fallback;
3673	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpslld_u256, iemAImpl_vpslld_u256_fallback;
3674	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllq_u256, iemAImpl_vpsllq_u256_fallback;
3675	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsraw_u256, iemAImpl_vpsraw_u256_fallback;
3676	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrad_u256, iemAImpl_vpsrad_u256_fallback;
3677	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlw_u256, iemAImpl_vpsrlw_u256_fallback;
3678	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrld_u256, iemAImpl_vpsrld_u256_fallback;
3679	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlq_u256, iemAImpl_vpsrlq_u256_fallback;
3680	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddwd_u256, iemAImpl_vpmaddwd_u256_fallback;
3681
3682	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsb_u256, iemAImpl_vpabsb_u256_fallback;
3683	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsw_u256, iemAImpl_vpabsw_u256_fallback;
3684	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsd_u256, iemAImpl_vpabsd_u256_fallback;
3685	/** @} */
3686
3687	/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
3688	* @{ */
3689	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
3690	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
3691	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpcklbw_u128, iemAImpl_vpunpcklbw_u128_fallback,
3692	iemAImpl_vpunpcklwd_u128, iemAImpl_vpunpcklwd_u128_fallback,
3693	iemAImpl_vpunpckldq_u128, iemAImpl_vpunpckldq_u128_fallback,
3694	iemAImpl_vpunpcklqdq_u128, iemAImpl_vpunpcklqdq_u128_fallback,
3695	iemAImpl_vunpcklps_u128, iemAImpl_vunpcklps_u128_fallback,
3696	iemAImpl_vunpcklpd_u128, iemAImpl_vunpcklpd_u128_fallback,
3697	iemAImpl_vunpckhps_u128, iemAImpl_vunpckhps_u128_fallback,
3698	iemAImpl_vunpckhpd_u128, iemAImpl_vunpckhpd_u128_fallback;
3699
3700	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpcklbw_u256, iemAImpl_vpunpcklbw_u256_fallback,
3701	iemAImpl_vpunpcklwd_u256, iemAImpl_vpunpcklwd_u256_fallback,
3702	iemAImpl_vpunpckldq_u256, iemAImpl_vpunpckldq_u256_fallback,
3703	iemAImpl_vpunpcklqdq_u256, iemAImpl_vpunpcklqdq_u256_fallback,
3704	iemAImpl_vunpcklps_u256, iemAImpl_vunpcklps_u256_fallback,
3705	iemAImpl_vunpcklpd_u256, iemAImpl_vunpcklpd_u256_fallback,
3706	iemAImpl_vunpckhps_u256, iemAImpl_vunpckhps_u256_fallback,
3707	iemAImpl_vunpckhpd_u256, iemAImpl_vunpckhpd_u256_fallback;
3708	/** @} */
3709
3710	/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
3711	* @{ */
3712	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
3713	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
3714	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpckhbw_u128, iemAImpl_vpunpckhbw_u128_fallback,
3715	iemAImpl_vpunpckhwd_u128, iemAImpl_vpunpckhwd_u128_fallback,
3716	iemAImpl_vpunpckhdq_u128, iemAImpl_vpunpckhdq_u128_fallback,
3717	iemAImpl_vpunpckhqdq_u128, iemAImpl_vpunpckhqdq_u128_fallback;
3718	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpckhbw_u256, iemAImpl_vpunpckhbw_u256_fallback,
3719	iemAImpl_vpunpckhwd_u256, iemAImpl_vpunpckhwd_u256_fallback,
3720	iemAImpl_vpunpckhdq_u256, iemAImpl_vpunpckhdq_u256_fallback,
3721	iemAImpl_vpunpckhqdq_u256, iemAImpl_vpunpckhqdq_u256_fallback;
3722	/** @} */
3723
3724	/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
3725	* @{ */
3726	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3727	typedef FNIEMAIMPLMEDIAPSHUFU128 *PFNIEMAIMPLMEDIAPSHUFU128;
3728	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
3729	typedef FNIEMAIMPLMEDIAPSHUFU256 *PFNIEMAIMPLMEDIAPSHUFU256;
3730	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw_u64,(uint64_t puDst, uint64_t const puSrc, uint8_t bEvil));
3731	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_pshufhw_u128, iemAImpl_pshuflw_u128, iemAImpl_pshufd_u128;
3732	#ifndef IEM_WITHOUT_ASSEMBLY
3733	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256, iemAImpl_vpshuflw_u256, iemAImpl_vpshufd_u256;
3734	#endif
3735	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256_fallback, iemAImpl_vpshuflw_u256_fallback, iemAImpl_vpshufd_u256_fallback;
3736	/** @} */
3737
3738	/** @name Media (SSE/MMX/AVX) operation: Shift Immediate Stuff (evil)
3739	* @{ */
3740	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU64,(uint64_t *puDst, uint8_t bShift));
3741	typedef FNIEMAIMPLMEDIAPSHIFTU64 *PFNIEMAIMPLMEDIAPSHIFTU64;
3742	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU128,(PRTUINT128U puDst, uint8_t bShift));
3743	typedef FNIEMAIMPLMEDIAPSHIFTU128 *PFNIEMAIMPLMEDIAPSHIFTU128;
3744	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU256,(PRTUINT256U puDst, uint8_t bShift));
3745	typedef FNIEMAIMPLMEDIAPSHIFTU256 *PFNIEMAIMPLMEDIAPSHIFTU256;
3746	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psllw_imm_u64, iemAImpl_pslld_imm_u64, iemAImpl_psllq_imm_u64;
3747	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psrlw_imm_u64, iemAImpl_psrld_imm_u64, iemAImpl_psrlq_imm_u64;
3748	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psraw_imm_u64, iemAImpl_psrad_imm_u64;
3749	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psllw_imm_u128, iemAImpl_pslld_imm_u128, iemAImpl_psllq_imm_u128;
3750	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psrlw_imm_u128, iemAImpl_psrld_imm_u128, iemAImpl_psrlq_imm_u128;
3751	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psraw_imm_u128, iemAImpl_psrad_imm_u128;
3752	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_pslldq_imm_u128, iemAImpl_psrldq_imm_u128;
3753	/** @} */
3754
3755	/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
3756	* @{ */
3757	IEM_DECL_IMPL_DEF(void, iemAImpl_maskmovq_u64,(uint64_t puMem, uint64_t const puSrc, uint64_t const *puMsk));
3758	IEM_DECL_IMPL_DEF(void, iemAImpl_maskmovdqu_u128,(PRTUINT128U puMem, PCRTUINT128U puSrc, PCRTUINT128U puMsk));
3759	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(uint64_t pu64Dst, uint64_t const puSrc));
3760	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(uint64_t *pu64Dst, PCRTUINT128U puSrc));
3761	#ifndef IEM_WITHOUT_ASSEMBLY
3762	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
3763	#endif
3764	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256_fallback,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
3765	/** @} */
3766
3767	/** @name Media (SSE/MMX/AVX) operations: Variable Blend Packed Bytes/R32/R64.
3768	* @{ */
3769	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puMask));
3770	typedef FNIEMAIMPLBLENDU128 *PFNIEMAIMPLBLENDU128;
3771	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, PCRTUINT128U puMask));
3772	typedef FNIEMAIMPLAVXBLENDU128 *PFNIEMAIMPLAVXBLENDU128;
3773	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, PCRTUINT256U puMask));
3774	typedef FNIEMAIMPLAVXBLENDU256 *PFNIEMAIMPLAVXBLENDU256;
3775
3776	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128;
3777	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128_fallback;
3778	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128;
3779	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128_fallback;
3780	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256;
3781	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256_fallback;
3782
3783	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128;
3784	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128_fallback;
3785	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128;
3786	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128_fallback;
3787	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256;
3788	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256_fallback;
3789
3790	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128;
3791	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128_fallback;
3792	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128;
3793	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128_fallback;
3794	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256;
3795	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256_fallback;
3796	/** @} */
3797
3798
3799	/** @name Media (SSE/MMX/AVX) operation: Sort this later
3800	* @{ */
3801	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3802	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3803	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3804	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3805	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3806
3807	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3808	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3809	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3810	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3811	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3812
3813	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3814	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3815	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
3816	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3817	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3818
3819	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3820	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3821	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3822	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3823	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3824
3825	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3826	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3827	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3828	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3829	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3830
3831	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3832	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3833	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3834	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3835	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3836
3837	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3838	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3839	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3840	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3841	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3842
3843	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3844	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3845	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3846	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3847	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3848
3849	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3850	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3851	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
3852	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3853	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3854
3855	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3856	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3857	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3858	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3859	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3860
3861	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3862	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3863	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3864	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3865	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3866
3867	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3868	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3869	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3870	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3871	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3872
3873	IEM_DECL_IMPL_DEF(void, iemAImpl_shufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3874	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3875	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3876	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3877	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3878
3879	IEM_DECL_IMPL_DEF(void, iemAImpl_shufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3880	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3881	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3882	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3883	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3884
3885	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
3886	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64_fallback,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
3887
3888	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3889	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3890	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3891	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3892	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3893
3894	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3895	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3896	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3897	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3898	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3899
3900
3901	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3902	typedef FNIEMAIMPLMEDIAOPTF2U128IMM8 *PFNIEMAIMPLMEDIAOPTF2U128IMM8;
3903	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
3904	typedef FNIEMAIMPLMEDIAOPTF2U256IMM8 *PFNIEMAIMPLMEDIAOPTF2U256IMM8;
3905	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3906	typedef FNIEMAIMPLMEDIAOPTF3U128IMM8 *PFNIEMAIMPLMEDIAOPTF3U128IMM8;
3907	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3908	typedef FNIEMAIMPLMEDIAOPTF3U256IMM8 *PFNIEMAIMPLMEDIAOPTF3U256IMM8;
3909
3910	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_palignr_u128, iemAImpl_palignr_u128_fallback;
3911	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pblendw_u128, iemAImpl_pblendw_u128_fallback;
3912	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendps_u128, iemAImpl_blendps_u128_fallback;
3913	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendpd_u128, iemAImpl_blendpd_u128_fallback;
3914
3915	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpalignr_u128, iemAImpl_vpalignr_u128_fallback;
3916	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendw_u128, iemAImpl_vpblendw_u128_fallback;
3917	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendd_u128, iemAImpl_vpblendd_u128_fallback;
3918	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendps_u128, iemAImpl_vblendps_u128_fallback;
3919	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendpd_u128, iemAImpl_vblendpd_u128_fallback;
3920
3921	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpalignr_u256, iemAImpl_vpalignr_u256_fallback;
3922	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendw_u256, iemAImpl_vpblendw_u256_fallback;
3923	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendd_u256, iemAImpl_vpblendd_u256_fallback;
3924	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendps_u256, iemAImpl_vblendps_u256_fallback;
3925	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendpd_u256, iemAImpl_vblendpd_u256_fallback;
3926	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2i128_u256, iemAImpl_vperm2i128_u256_fallback;
3927	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2f128_u256, iemAImpl_vperm2f128_u256_fallback;
3928
3929	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesimc_u128, iemAImpl_aesimc_u128_fallback;
3930	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenc_u128, iemAImpl_aesenc_u128_fallback;
3931	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenclast_u128, iemAImpl_aesenclast_u128_fallback;
3932	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdec_u128, iemAImpl_aesdec_u128_fallback;
3933	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdeclast_u128, iemAImpl_aesdeclast_u128_fallback;
3934
3935	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesimc_u128, iemAImpl_vaesimc_u128_fallback;
3936	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenc_u128, iemAImpl_vaesenc_u128_fallback;
3937	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenclast_u128, iemAImpl_vaesenclast_u128_fallback;
3938	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdec_u128, iemAImpl_vaesdec_u128_fallback;
3939	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdeclast_u128, iemAImpl_vaesdeclast_u128_fallback;
3940
3941	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_aeskeygenassist_u128, iemAImpl_aeskeygenassist_u128_fallback;
3942
3943	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vaeskeygenassist_u128, iemAImpl_vaeskeygenassist_u128_fallback;
3944
3945	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1nexte_u128, iemAImpl_sha1nexte_u128_fallback;
3946	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg1_u128, iemAImpl_sha1msg1_u128_fallback;
3947	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg2_u128, iemAImpl_sha1msg2_u128_fallback;
3948	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg1_u128, iemAImpl_sha256msg1_u128_fallback;
3949	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg2_u128, iemAImpl_sha256msg2_u128_fallback;
3950	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_sha1rnds4_u128, iemAImpl_sha1rnds4_u128_fallback;
3951	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
3952	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
3953
3954	typedef struct IEMPCMPISTRXSRC
3955	{
3956	RTUINT128U uSrc1;
3957	RTUINT128U uSrc2;
3958	} IEMPCMPISTRXSRC;
3959	typedef IEMPCMPISTRXSRC *PIEMPCMPISTRXSRC;
3960	typedef const IEMPCMPISTRXSRC *PCIEMPCMPISTRXSRC;
3961
3962	typedef struct IEMPCMPESTRXSRC
3963	{
3964	RTUINT128U uSrc1;
3965	RTUINT128U uSrc2;
3966	uint64_t u64Rax;
3967	uint64_t u64Rdx;
3968	} IEMPCMPESTRXSRC;
3969	typedef IEMPCMPESTRXSRC *PIEMPCMPESTRXSRC;
3970	typedef const IEMPCMPESTRXSRC *PCIEMPCMPESTRXSRC;
3971
3972	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLPCMPISTRIU128IMM8,(uint32_t *pEFlags, PCRTUINT128U pSrc1, PCRTUINT128U pSrc2, uint8_t bEvil));
3973	typedef FNIEMAIMPLPCMPISTRIU128IMM8 *PFNIEMAIMPLPCMPISTRIU128IMM8;
3974	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRIU128IMM8,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
3975	typedef FNIEMAIMPLPCMPESTRIU128IMM8 *PFNIEMAIMPLPCMPESTRIU128IMM8;
3976
3977	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPISTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
3978	typedef FNIEMAIMPLPCMPISTRMU128IMM8 *PFNIEMAIMPLPCMPISTRMU128IMM8;
3979	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
3980	typedef FNIEMAIMPLPCMPESTRMU128IMM8 *PFNIEMAIMPLPCMPESTRMU128IMM8;
3981
3982	FNIEMAIMPLPCMPISTRIU128IMM8 iemAImpl_pcmpistri_u128, iemAImpl_pcmpistri_u128_fallback;
3983	FNIEMAIMPLPCMPESTRIU128IMM8 iemAImpl_pcmpestri_u128, iemAImpl_pcmpestri_u128_fallback;
3984	FNIEMAIMPLPCMPISTRMU128IMM8 iemAImpl_pcmpistrm_u128, iemAImpl_pcmpistrm_u128_fallback;
3985	FNIEMAIMPLPCMPESTRMU128IMM8 iemAImpl_pcmpestrm_u128, iemAImpl_pcmpestrm_u128_fallback;
3986
3987	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pclmulqdq_u128, iemAImpl_pclmulqdq_u128_fallback;
3988	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpclmulqdq_u128, iemAImpl_vpclmulqdq_u128_fallback;
3989
3990	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_mpsadbw_u128, iemAImpl_mpsadbw_u128_fallback;
3991	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vmpsadbw_u128, iemAImpl_vmpsadbw_u128_fallback;
3992	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vmpsadbw_u256, iemAImpl_vmpsadbw_u256_fallback;
3993
3994	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsllw_imm_u128, iemAImpl_vpsllw_imm_u128_fallback;
3995	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsllw_imm_u256, iemAImpl_vpsllw_imm_u256_fallback;
3996	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpslld_imm_u128, iemAImpl_vpslld_imm_u128_fallback;
3997	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpslld_imm_u256, iemAImpl_vpslld_imm_u256_fallback;
3998	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsllq_imm_u128, iemAImpl_vpsllq_imm_u128_fallback;
3999	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsllq_imm_u256, iemAImpl_vpsllq_imm_u256_fallback;
4000	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
4001	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
4002	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
4003	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
4004
4005	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsraw_imm_u128, iemAImpl_vpsraw_imm_u128_fallback;
4006	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsraw_imm_u256, iemAImpl_vpsraw_imm_u256_fallback;
4007	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrad_imm_u128, iemAImpl_vpsrad_imm_u128_fallback;
4008	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrad_imm_u256, iemAImpl_vpsrad_imm_u256_fallback;
4009
4010	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrlw_imm_u128, iemAImpl_vpsrlw_imm_u128_fallback;
4011	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrlw_imm_u256, iemAImpl_vpsrlw_imm_u256_fallback;
4012	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrld_imm_u128, iemAImpl_vpsrld_imm_u128_fallback;
4013	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrld_imm_u256, iemAImpl_vpsrld_imm_u256_fallback;
4014	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrlq_imm_u128, iemAImpl_vpsrlq_imm_u128_fallback;
4015	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrlq_imm_u256, iemAImpl_vpsrlq_imm_u256_fallback;
4016	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
4017	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
4018	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
4019	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
4020
4021	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpermilps_u128, iemAImpl_vpermilps_u128_fallback;
4022	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_vpermilps_imm_u128, iemAImpl_vpermilps_imm_u128_fallback;
4023	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpermilps_u256, iemAImpl_vpermilps_u256_fallback;
4024	FNIEMAIMPLMEDIAOPTF2U256IMM8 iemAImpl_vpermilps_imm_u256, iemAImpl_vpermilps_imm_u256_fallback;
4025
4026	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpermilpd_u128, iemAImpl_vpermilpd_u128_fallback;
4027	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_vpermilpd_imm_u128, iemAImpl_vpermilpd_imm_u128_fallback;
4028	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpermilpd_u256, iemAImpl_vpermilpd_u256_fallback;
4029	FNIEMAIMPLMEDIAOPTF2U256IMM8 iemAImpl_vpermilpd_imm_u256, iemAImpl_vpermilpd_imm_u256_fallback;
4030
4031	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllvd_u128, iemAImpl_vpsllvd_u128_fallback;
4032	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllvd_u256, iemAImpl_vpsllvd_u256_fallback;
4033	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllvq_u128, iemAImpl_vpsllvq_u128_fallback;
4034	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllvq_u256, iemAImpl_vpsllvq_u256_fallback;
4035	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsravd_u128, iemAImpl_vpsravd_u128_fallback;
4036	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsravd_u256, iemAImpl_vpsravd_u256_fallback;
4037	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlvd_u128, iemAImpl_vpsrlvd_u128_fallback;
4038	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlvd_u256, iemAImpl_vpsrlvd_u256_fallback;
4039	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlvq_u128, iemAImpl_vpsrlvq_u128_fallback;
4040	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlvq_u256, iemAImpl_vpsrlvq_u256_fallback;
4041	/** @} */
4042
4043	/** @name Media Odds and Ends
4044	* @{ */
4045	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U8,(uint32_t *puDst, uint8_t uSrc));
4046	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U16,(uint32_t *puDst, uint16_t uSrc));
4047	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U32,(uint32_t *puDst, uint32_t uSrc));
4048	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U64,(uint32_t *puDst, uint64_t uSrc));
4049	FNIEMAIMPLCR32U8 iemAImpl_crc32_u8, iemAImpl_crc32_u8_fallback;
4050	FNIEMAIMPLCR32U16 iemAImpl_crc32_u16, iemAImpl_crc32_u16_fallback;
4051	FNIEMAIMPLCR32U32 iemAImpl_crc32_u32, iemAImpl_crc32_u32_fallback;
4052	FNIEMAIMPLCR32U64 iemAImpl_crc32_u64, iemAImpl_crc32_u64_fallback;
4053
4054	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL128,(PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint32_t *pEFlags));
4055	typedef FNIEMAIMPLF2EFL128 *PFNIEMAIMPLF2EFL128;
4056	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL256,(PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint32_t *pEFlags));
4057	typedef FNIEMAIMPLF2EFL256 *PFNIEMAIMPLF2EFL256;
4058	FNIEMAIMPLF2EFL128 iemAImpl_ptest_u128;
4059	FNIEMAIMPLF2EFL256 iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback;
4060	FNIEMAIMPLF2EFL128 iemAImpl_vtestps_u128, iemAImpl_vtestps_u128_fallback;
4061	FNIEMAIMPLF2EFL256 iemAImpl_vtestps_u256, iemAImpl_vtestps_u256_fallback;
4062	FNIEMAIMPLF2EFL128 iemAImpl_vtestpd_u128, iemAImpl_vtestpd_u128_fallback;
4063	FNIEMAIMPLF2EFL256 iemAImpl_vtestpd_u256, iemAImpl_vtestpd_u256_fallback;
4064
4065	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I32U64,(uint32_t uMxCsrIn, int32_t pi32Dst, const uint64_t pu64Src)); /* pu64Src is a double precision floating point. */
4066	typedef FNIEMAIMPLSSEF2I32U64 *PFNIEMAIMPLSSEF2I32U64;
4067	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I64U64,(uint32_t uMxCsrIn, int64_t pi64Dst, const uint64_t pu64Src)); /* pu64Src is a double precision floating point. */
4068	typedef FNIEMAIMPLSSEF2I64U64 *PFNIEMAIMPLSSEF2I64U64;
4069	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I32U32,(uint32_t uMxCsrIn, int32_t pi32Dst, const uint32_t pu32Src)); /* pu32Src is a single precision floating point. */
4070	typedef FNIEMAIMPLSSEF2I32U32 *PFNIEMAIMPLSSEF2I32U32;
4071	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I64U32,(uint32_t uMxCsrIn, int64_t pi64Dst, const uint32_t pu32Src)); /* pu32Src is a single precision floating point. */
4072	typedef FNIEMAIMPLSSEF2I64U32 *PFNIEMAIMPLSSEF2I64U32;
4073
4074	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvttsd2si_i32_r64;
4075	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvtsd2si_i32_r64;
4076
4077	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvttsd2si_i64_r64;
4078	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvtsd2si_i64_r64;
4079
4080	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvttss2si_i32_r32;
4081	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvtss2si_i32_r32;
4082
4083	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvttss2si_i64_r32;
4084	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvtss2si_i64_r32;
4085
4086	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R32I32,(uint32_t uMxCsrIn, PRTFLOAT32U pr32Dst, const int32_t *pi32Src));
4087	typedef FNIEMAIMPLSSEF2R32I32 *PFNIEMAIMPLSSEF2R32I32;
4088	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R32I64,(uint32_t uMxCsrIn, PRTFLOAT32U pr32Dst, const int64_t *pi64Src));
4089	typedef FNIEMAIMPLSSEF2R32I64 *PFNIEMAIMPLSSEF2R32I64;
4090
4091	FNIEMAIMPLSSEF2R32I32 iemAImpl_cvtsi2ss_r32_i32;
4092	FNIEMAIMPLSSEF2R32I64 iemAImpl_cvtsi2ss_r32_i64;
4093
4094	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R64I32,(uint32_t uMxCsrIn, PRTFLOAT64U pr64Dst, const int32_t *pi32Src));
4095	typedef FNIEMAIMPLSSEF2R64I32 *PFNIEMAIMPLSSEF2R64I32;
4096	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R64I64,(uint32_t uMxCsrIn, PRTFLOAT64U pr64Dst, const int64_t *pi64Src));
4097	typedef FNIEMAIMPLSSEF2R64I64 *PFNIEMAIMPLSSEF2R64I64;
4098
4099	FNIEMAIMPLSSEF2R64I32 iemAImpl_cvtsi2sd_r64_i32;
4100	FNIEMAIMPLSSEF2R64I64 iemAImpl_cvtsi2sd_r64_i64;
4101
4102
4103	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLF2EFLMXCSRR32R32,(uint32_t uMxCsrIn, uint32_t *pfEFlags, RTFLOAT32U uSrc1, RTFLOAT32U uSrc2));
4104	typedef FNIEMAIMPLF2EFLMXCSRR32R32 *PFNIEMAIMPLF2EFLMXCSRR32R32;
4105
4106	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLF2EFLMXCSRR64R64,(uint32_t uMxCsrIn, uint32_t *pfEFlags, RTFLOAT64U uSrc1, RTFLOAT64U uSrc2));
4107	typedef FNIEMAIMPLF2EFLMXCSRR64R64 *PFNIEMAIMPLF2EFLMXCSRR64R64;
4108
4109	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_ucomiss_u128;
4110	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback;
4111
4112	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_ucomisd_u128;
4113	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback;
4114
4115	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_comiss_u128;
4116	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback;
4117
4118	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_comisd_u128;
4119	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback;
4120
4121
4122	typedef struct IEMMEDIAF2XMMSRC
4123	{
4124	X86XMMREG uSrc1;
4125	X86XMMREG uSrc2;
4126	} IEMMEDIAF2XMMSRC;
4127	typedef IEMMEDIAF2XMMSRC *PIEMMEDIAF2XMMSRC;
4128	typedef const IEMMEDIAF2XMMSRC *PCIEMMEDIAF2XMMSRC;
4129
4130	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRF2XMMIMM8,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCIEMMEDIAF2XMMSRC puSrc, uint8_t bEvil));
4131	typedef FNIEMAIMPLMXCSRF2XMMIMM8 *PFNIEMAIMPLMXCSRF2XMMIMM8;
4132
4133	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpps_u128;
4134	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmppd_u128;
4135	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpss_u128;
4136	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpsd_u128;
4137	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundss_u128;
4138	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundsd_u128;
4139
4140	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundps_u128, iemAImpl_roundps_u128_fallback;
4141	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundpd_u128, iemAImpl_roundpd_u128_fallback;
4142
4143	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_dpps_u128, iemAImpl_dpps_u128_fallback;
4144	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_dppd_u128, iemAImpl_dppd_u128_fallback;
4145
4146	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRU64U128,(uint32_t fMxCsrIn, uint64_t *pu64Dst, PCX86XMMREG pSrc));
4147	typedef FNIEMAIMPLMXCSRU64U128 *PFNIEMAIMPLMXCSRU64U128;
4148
4149	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvtpd2pi_u128;
4150	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvttpd2pi_u128;
4151
4152	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRU128U64,(uint32_t fMxCsrIn, PX86XMMREG pDst, uint64_t u64Src));
4153	typedef FNIEMAIMPLMXCSRU128U64 *PFNIEMAIMPLMXCSRU128U64;
4154
4155	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2ps_u128;
4156	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2pd_u128;
4157
4158	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRU64U64,(uint32_t fMxCsrIn, uint64_t *pu64Dst, uint64_t u64Src));
4159	typedef FNIEMAIMPLMXCSRU64U64 *PFNIEMAIMPLMXCSRU64U64;
4160
4161	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvtps2pi_u128;
4162	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvttps2pi_u128;
4163
4164	/** @} */
4165
4166
4167	/** @name Function tables.
4168	* @{
4169	*/
4170
4171	/**
4172	* Function table for a binary operator providing implementation based on
4173	* operand size.
4174	*/
4175	typedef struct IEMOPBINSIZES
4176	{
4177	PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
4178	PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
4179	PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
4180	PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
4181	} IEMOPBINSIZES;
4182	/** Pointer to a binary operator function table. */
4183	typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
4184
4185
4186	/**
4187	* Function table for a unary operator providing implementation based on
4188	* operand size.
4189	*/
4190	typedef struct IEMOPUNARYSIZES
4191	{
4192	PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
4193	PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
4194	PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
4195	PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
4196	} IEMOPUNARYSIZES;
4197	/** Pointer to a unary operator function table. */
4198	typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
4199
4200
4201	/**
4202	* Function table for a shift operator providing implementation based on
4203	* operand size.
4204	*/
4205	typedef struct IEMOPSHIFTSIZES
4206	{
4207	PFNIEMAIMPLSHIFTU8 pfnNormalU8;
4208	PFNIEMAIMPLSHIFTU16 pfnNormalU16;
4209	PFNIEMAIMPLSHIFTU32 pfnNormalU32;
4210	PFNIEMAIMPLSHIFTU64 pfnNormalU64;
4211	} IEMOPSHIFTSIZES;
4212	/** Pointer to a shift operator function table. */
4213	typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
4214
4215
4216	/**
4217	* Function table for a multiplication or division operation.
4218	*/
4219	typedef struct IEMOPMULDIVSIZES
4220	{
4221	PFNIEMAIMPLMULDIVU8 pfnU8;
4222	PFNIEMAIMPLMULDIVU16 pfnU16;
4223	PFNIEMAIMPLMULDIVU32 pfnU32;
4224	PFNIEMAIMPLMULDIVU64 pfnU64;
4225	} IEMOPMULDIVSIZES;
4226	/** Pointer to a multiplication or division operation function table. */
4227	typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
4228
4229
4230	/**
4231	* Function table for a double precision shift operator providing implementation
4232	* based on operand size.
4233	*/
4234	typedef struct IEMOPSHIFTDBLSIZES
4235	{
4236	PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
4237	PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
4238	PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
4239	} IEMOPSHIFTDBLSIZES;
4240	/** Pointer to a double precision shift function table. */
4241	typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
4242
4243
4244	/**
4245	* Function table for media instruction taking two full sized media source
4246	* registers and one full sized destination register (AVX).
4247	*/
4248	typedef struct IEMOPMEDIAF3
4249	{
4250	PFNIEMAIMPLMEDIAF3U128 pfnU128;
4251	PFNIEMAIMPLMEDIAF3U256 pfnU256;
4252	} IEMOPMEDIAF3;
4253	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
4254	typedef IEMOPMEDIAF3 const *PCIEMOPMEDIAF3;
4255
4256	/** @def IEMOPMEDIAF3_INIT_VARS_EX
4257	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4258	* given functions as initializers. For use in AVX functions where a pair of
4259	* functions are only used once and the function table need not be public. */
4260	#ifndef TST_IEM_CHECK_MC
4261	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4262	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4263	static IEMOPMEDIAF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4264	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4265	# else
4266	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4267	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4268	# endif
4269	#else
4270	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4271	#endif
4272	/** @def IEMOPMEDIAF3_INIT_VARS
4273	* Generate AVX function tables for the @a a_InstrNm instruction.
4274	* @sa IEMOPMEDIAF3_INIT_VARS_EX */
4275	#define IEMOPMEDIAF3_INIT_VARS(a_InstrNm) \
4276	IEMOPMEDIAF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4277	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4278
4279	/**
4280	* Function table for media instruction taking two full sized media source
4281	* registers and one full sized destination register, but no additional state
4282	* (AVX).
4283	*/
4284	typedef struct IEMOPMEDIAOPTF3
4285	{
4286	PFNIEMAIMPLMEDIAOPTF3U128 pfnU128;
4287	PFNIEMAIMPLMEDIAOPTF3U256 pfnU256;
4288	} IEMOPMEDIAOPTF3;
4289	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
4290	typedef IEMOPMEDIAOPTF3 const *PCIEMOPMEDIAOPTF3;
4291
4292	/** @def IEMOPMEDIAOPTF3_INIT_VARS_EX
4293	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4294	* given functions as initializers. For use in AVX functions where a pair of
4295	* functions are only used once and the function table need not be public. */
4296	#ifndef TST_IEM_CHECK_MC
4297	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4298	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4299	static IEMOPMEDIAOPTF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4300	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4301	# else
4302	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4303	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4304	# endif
4305	#else
4306	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4307	#endif
4308	/** @def IEMOPMEDIAOPTF3_INIT_VARS
4309	* Generate AVX function tables for the @a a_InstrNm instruction.
4310	* @sa IEMOPMEDIAOPTF3_INIT_VARS_EX */
4311	#define IEMOPMEDIAOPTF3_INIT_VARS(a_InstrNm) \
4312	IEMOPMEDIAOPTF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4313	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4314
4315	/**
4316	* Function table for media instruction taking one full sized media source
4317	* registers and one full sized destination register, but no additional state
4318	* (AVX).
4319	*/
4320	typedef struct IEMOPMEDIAOPTF2
4321	{
4322	PFNIEMAIMPLMEDIAOPTF2U128 pfnU128;
4323	PFNIEMAIMPLMEDIAOPTF2U256 pfnU256;
4324	} IEMOPMEDIAOPTF2;
4325	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
4326	typedef IEMOPMEDIAOPTF2 const *PCIEMOPMEDIAOPTF2;
4327
4328	/** @def IEMOPMEDIAOPTF2_INIT_VARS_EX
4329	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4330	* given functions as initializers. For use in AVX functions where a pair of
4331	* functions are only used once and the function table need not be public. */
4332	#ifndef TST_IEM_CHECK_MC
4333	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4334	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4335	static IEMOPMEDIAOPTF2 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4336	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4337	# else
4338	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4339	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4340	# endif
4341	#else
4342	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4343	#endif
4344	/** @def IEMOPMEDIAOPTF2_INIT_VARS
4345	* Generate AVX function tables for the @a a_InstrNm instruction.
4346	* @sa IEMOPMEDIAOPTF2_INIT_VARS_EX */
4347	#define IEMOPMEDIAOPTF2_INIT_VARS(a_InstrNm) \
4348	IEMOPMEDIAOPTF2_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4349	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4350
4351	/**
4352	* Function table for media instruction taking one full sized media source
4353	* register and one full sized destination register and an 8-bit immediate, but no additional state
4354	* (AVX).
4355	*/
4356	typedef struct IEMOPMEDIAOPTF2IMM8
4357	{
4358	PFNIEMAIMPLMEDIAOPTF2U128IMM8 pfnU128;
4359	PFNIEMAIMPLMEDIAOPTF2U256IMM8 pfnU256;
4360	} IEMOPMEDIAOPTF2IMM8;
4361	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
4362	typedef IEMOPMEDIAOPTF2IMM8 const *PCIEMOPMEDIAOPTF2IMM8;
4363
4364	/** @def IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX
4365	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4366	* given functions as initializers. For use in AVX functions where a pair of
4367	* functions are only used once and the function table need not be public. */
4368	#ifndef TST_IEM_CHECK_MC
4369	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4370	# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4371	static IEMOPMEDIAOPTF2IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4372	static IEMOPMEDIAOPTF2IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4373	# else
4374	# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4375	static IEMOPMEDIAOPTF2IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4376	# endif
4377	#else
4378	# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4379	#endif
4380	/** @def IEMOPMEDIAOPTF2IMM8_INIT_VARS
4381	* Generate AVX function tables for the @a a_InstrNm instruction.
4382	* @sa IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX */
4383	#define IEMOPMEDIAOPTF2IMM8_INIT_VARS(a_InstrNm) \
4384	IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u256),\
4385	RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u256_fallback))
4386
4387	/**
4388	* Function table for media instruction taking two full sized media source
4389	* registers and one full sized destination register and an 8-bit immediate, but no additional state
4390	* (AVX).
4391	*/
4392	typedef struct IEMOPMEDIAOPTF3IMM8
4393	{
4394	PFNIEMAIMPLMEDIAOPTF3U128IMM8 pfnU128;
4395	PFNIEMAIMPLMEDIAOPTF3U256IMM8 pfnU256;
4396	} IEMOPMEDIAOPTF3IMM8;
4397	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
4398	typedef IEMOPMEDIAOPTF3IMM8 const *PCIEMOPMEDIAOPTF3IMM8;
4399
4400	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX
4401	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4402	* given functions as initializers. For use in AVX functions where a pair of
4403	* functions are only used once and the function table need not be public. */
4404	#ifndef TST_IEM_CHECK_MC
4405	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4406	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4407	static IEMOPMEDIAOPTF3IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4408	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4409	# else
4410	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4411	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4412	# endif
4413	#else
4414	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4415	#endif
4416	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS
4417	* Generate AVX function tables for the @a a_InstrNm instruction.
4418	* @sa IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX */
4419	#define IEMOPMEDIAOPTF3IMM8_INIT_VARS(a_InstrNm) \
4420	IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4421	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4422	/** @} */
4423
4424
4425	/**
4426	* Function table for blend type instruction taking three full sized media source
4427	* registers and one full sized destination register, but no additional state
4428	* (AVX).
4429	*/
4430	typedef struct IEMOPBLENDOP
4431	{
4432	PFNIEMAIMPLAVXBLENDU128 pfnU128;
4433	PFNIEMAIMPLAVXBLENDU256 pfnU256;
4434	} IEMOPBLENDOP;
4435	/** Pointer to a media operation function table for 4 full sized ops (AVX). */
4436	typedef IEMOPBLENDOP const *PCIEMOPBLENDOP;
4437
4438	/** @def IEMOPBLENDOP_INIT_VARS_EX
4439	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4440	* given functions as initializers. For use in AVX functions where a pair of
4441	* functions are only used once and the function table need not be public. */
4442	#ifndef TST_IEM_CHECK_MC
4443	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4444	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4445	static IEMOPBLENDOP const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4446	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4447	# else
4448	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4449	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4450	# endif
4451	#else
4452	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4453	#endif
4454	/** @def IEMOPBLENDOP_INIT_VARS
4455	* Generate AVX function tables for the @a a_InstrNm instruction.
4456	* @sa IEMOPBLENDOP_INIT_VARS_EX */
4457	#define IEMOPBLENDOP_INIT_VARS(a_InstrNm) \
4458	IEMOPBLENDOP_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4459	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4460
4461
4462	/** @name SSE/AVX single/double precision floating point operations.
4463	* @{ */
4464	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
4465	typedef FNIEMAIMPLFPSSEF2U128 *PFNIEMAIMPLFPSSEF2U128;
4466	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128R32,(uint32_t uMxCsrIn, PX86XMMREG Result, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
4467	typedef FNIEMAIMPLFPSSEF2U128R32 *PFNIEMAIMPLFPSSEF2U128R32;
4468	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128R64,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
4469	typedef FNIEMAIMPLFPSSEF2U128R64 *PFNIEMAIMPLFPSSEF2U128R64;
4470
4471	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
4472	typedef FNIEMAIMPLFPAVXF3U128 *PFNIEMAIMPLFPAVXF3U128;
4473	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U128R32,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
4474	typedef FNIEMAIMPLFPAVXF3U128R32 *PFNIEMAIMPLFPAVXF3U128R32;
4475	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U128R64,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
4476	typedef FNIEMAIMPLFPAVXF3U128R64 *PFNIEMAIMPLFPAVXF3U128R64;
4477
4478	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U256,(uint32_t uMxCsrIn, PX86YMMREG pResult, PCX86YMMREG puSrc1, PCX86YMMREG puSrc2));
4479	typedef FNIEMAIMPLFPAVXF3U256 *PFNIEMAIMPLFPAVXF3U256;
4480
4481	FNIEMAIMPLFPSSEF2U128 iemAImpl_addps_u128;
4482	FNIEMAIMPLFPSSEF2U128 iemAImpl_addpd_u128;
4483	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulps_u128;
4484	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulpd_u128;
4485	FNIEMAIMPLFPSSEF2U128 iemAImpl_subps_u128;
4486	FNIEMAIMPLFPSSEF2U128 iemAImpl_subpd_u128;
4487	FNIEMAIMPLFPSSEF2U128 iemAImpl_minps_u128;
4488	FNIEMAIMPLFPSSEF2U128 iemAImpl_minpd_u128;
4489	FNIEMAIMPLFPSSEF2U128 iemAImpl_divps_u128;
4490	FNIEMAIMPLFPSSEF2U128 iemAImpl_divpd_u128;
4491	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxps_u128;
4492	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxpd_u128;
4493	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddps_u128;
4494	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddpd_u128;
4495	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubps_u128;
4496	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubpd_u128;
4497	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtps_u128;
4498	FNIEMAIMPLFPSSEF2U128 iemAImpl_rsqrtps_u128;
4499	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtpd_u128;
4500	FNIEMAIMPLFPSSEF2U128 iemAImpl_rcpps_u128;
4501	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubps_u128;
4502	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubpd_u128;
4503
4504	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2ps_u128;
4505	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_cvtps2pd_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, uint64_t const *pu64Src));
4506
4507	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2ps_u128;
4508	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2dq_u128;
4509	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttps2dq_u128;
4510	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttpd2dq_u128;
4511	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2pd_u128;
4512	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2dq_u128;
4513
4514	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_addss_u128_r32;
4515	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_addsd_u128_r64;
4516	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_mulss_u128_r32;
4517	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_mulsd_u128_r64;
4518	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_subss_u128_r32;
4519	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_subsd_u128_r64;
4520	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_minss_u128_r32;
4521	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_minsd_u128_r64;
4522	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_divss_u128_r32;
4523	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_divsd_u128_r64;
4524	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_maxss_u128_r32;
4525	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_maxsd_u128_r64;
4526	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_cvtss2sd_u128_r32;
4527	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_cvtsd2ss_u128_r64;
4528	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_sqrtss_u128_r32;
4529	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_sqrtsd_u128_r64;
4530	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_rsqrtss_u128_r32;
4531	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_rcpss_u128_r32;
4532
4533	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddps_u128, iemAImpl_vaddps_u128_fallback;
4534	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddpd_u128, iemAImpl_vaddpd_u128_fallback;
4535	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulps_u128, iemAImpl_vmulps_u128_fallback;
4536	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulpd_u128, iemAImpl_vmulpd_u128_fallback;
4537	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubps_u128, iemAImpl_vsubps_u128_fallback;
4538	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubpd_u128, iemAImpl_vsubpd_u128_fallback;
4539	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminps_u128, iemAImpl_vminps_u128_fallback;
4540	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminpd_u128, iemAImpl_vminpd_u128_fallback;
4541	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivps_u128, iemAImpl_vdivps_u128_fallback;
4542	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivpd_u128, iemAImpl_vdivpd_u128_fallback;
4543	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxps_u128, iemAImpl_vmaxps_u128_fallback;
4544	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxpd_u128, iemAImpl_vmaxpd_u128_fallback;
4545	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddps_u128, iemAImpl_vhaddps_u128_fallback;
4546	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddpd_u128, iemAImpl_vhaddpd_u128_fallback;
4547	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubps_u128, iemAImpl_vhsubps_u128_fallback;
4548	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubpd_u128, iemAImpl_vhsubpd_u128_fallback;
4549	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtps_u128, iemAImpl_vsqrtps_u128_fallback;
4550	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtpd_u128, iemAImpl_vsqrtpd_u128_fallback;
4551	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubps_u128, iemAImpl_vaddsubps_u128_fallback;
4552	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubpd_u128, iemAImpl_vaddsubpd_u128_fallback;
4553	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtpd2ps_u128, iemAImpl_vcvtpd2ps_u128_fallback;
4554	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtps2pd_u128, iemAImpl_vcvtps2pd_u128_fallback;
4555
4556	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vaddss_u128_r32, iemAImpl_vaddss_u128_r32_fallback;
4557	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vaddsd_u128_r64, iemAImpl_vaddsd_u128_r64_fallback;
4558	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmulss_u128_r32, iemAImpl_vmulss_u128_r32_fallback;
4559	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmulsd_u128_r64, iemAImpl_vmulsd_u128_r64_fallback;
4560	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsubss_u128_r32, iemAImpl_vsubss_u128_r32_fallback;
4561	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsubsd_u128_r64, iemAImpl_vsubsd_u128_r64_fallback;
4562	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vminss_u128_r32, iemAImpl_vminss_u128_r32_fallback;
4563	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vminsd_u128_r64, iemAImpl_vminsd_u128_r64_fallback;
4564	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vdivss_u128_r32, iemAImpl_vdivss_u128_r32_fallback;
4565	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vdivsd_u128_r64, iemAImpl_vdivsd_u128_r64_fallback;
4566	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmaxss_u128_r32, iemAImpl_vmaxss_u128_r32_fallback;
4567	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmaxsd_u128_r64, iemAImpl_vmaxsd_u128_r64_fallback;
4568	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsqrtss_u128_r32, iemAImpl_vsqrtss_u128_r32_fallback;
4569	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsqrtsd_u128_r64, iemAImpl_vsqrtsd_u128_r64_fallback;
4570
4571	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddps_u256, iemAImpl_vaddps_u256_fallback;
4572	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddpd_u256, iemAImpl_vaddpd_u256_fallback;
4573	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulps_u256, iemAImpl_vmulps_u256_fallback;
4574	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulpd_u256, iemAImpl_vmulpd_u256_fallback;
4575	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubps_u256, iemAImpl_vsubps_u256_fallback;
4576	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubpd_u256, iemAImpl_vsubpd_u256_fallback;
4577	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminps_u256, iemAImpl_vminps_u256_fallback;
4578	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminpd_u256, iemAImpl_vminpd_u256_fallback;
4579	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivps_u256, iemAImpl_vdivps_u256_fallback;
4580	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivpd_u256, iemAImpl_vdivpd_u256_fallback;
4581	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxps_u256, iemAImpl_vmaxps_u256_fallback;
4582	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxpd_u256, iemAImpl_vmaxpd_u256_fallback;
4583	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddps_u256, iemAImpl_vhaddps_u256_fallback;
4584	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddpd_u256, iemAImpl_vhaddpd_u256_fallback;
4585	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubps_u256, iemAImpl_vhsubps_u256_fallback;
4586	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubpd_u256, iemAImpl_vhsubpd_u256_fallback;
4587	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubps_u256, iemAImpl_vhaddsubps_u256_fallback;
4588	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubpd_u256, iemAImpl_vhaddsubpd_u256_fallback;
4589	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtpd2ps_u256, iemAImpl_vcvtpd2ps_u256_fallback;
4590	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtps2pd_u256, iemAImpl_vcvtps2pd_u256_fallback;
4591	/** @} */
4592
4593	/** @name C instruction implementations for anything slightly complicated.
4594	* @{ */
4595
4596	/**
4597	* For typedef'ing or declaring a C instruction implementation function taking
4598	* no extra arguments.
4599	*
4600	* @param a_Name The name of the type.
4601	*/
4602	# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
4603	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
4604	/**
4605	* For defining a C instruction implementation function taking no extra
4606	* arguments.
4607	*
4608	* @param a_Name The name of the function
4609	*/
4610	# define IEM_CIMPL_DEF_0(a_Name) \
4611	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
4612	/**
4613	* Prototype version of IEM_CIMPL_DEF_0.
4614	*/
4615	# define IEM_CIMPL_PROTO_0(a_Name) \
4616	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
4617	/**
4618	* For calling a C instruction implementation function taking no extra
4619	* arguments.
4620	*
4621	* This special call macro adds default arguments to the call and allow us to
4622	* change these later.
4623	*
4624	* @param a_fn The name of the function.
4625	*/
4626	# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
4627
4628	/** Type for a C instruction implementation function taking no extra
4629	* arguments. */
4630	typedef IEM_CIMPL_DECL_TYPE_0(FNIEMCIMPL0);
4631	/** Function pointer type for a C instruction implementation function taking
4632	* no extra arguments. */
4633	typedef FNIEMCIMPL0 *PFNIEMCIMPL0;
4634
4635	/**
4636	* For typedef'ing or declaring a C instruction implementation function taking
4637	* one extra argument.
4638	*
4639	* @param a_Name The name of the type.
4640	* @param a_Type0 The argument type.
4641	* @param a_Arg0 The argument name.
4642	*/
4643	# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
4644	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
4645	/**
4646	* For defining a C instruction implementation function taking one extra
4647	* argument.
4648	*
4649	* @param a_Name The name of the function
4650	* @param a_Type0 The argument type.
4651	* @param a_Arg0 The argument name.
4652	*/
4653	# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
4654	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
4655	/**
4656	* Prototype version of IEM_CIMPL_DEF_1.
4657	*/
4658	# define IEM_CIMPL_PROTO_1(a_Name, a_Type0, a_Arg0) \
4659	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
4660	/**
4661	* For calling a C instruction implementation function taking one extra
4662	* argument.
4663	*
4664	* This special call macro adds default arguments to the call and allow us to
4665	* change these later.
4666	*
4667	* @param a_fn The name of the function.
4668	* @param a0 The name of the 1st argument.
4669	*/
4670	# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
4671
4672	/**
4673	* For typedef'ing or declaring a C instruction implementation function taking
4674	* two extra arguments.
4675	*
4676	* @param a_Name The name of the type.
4677	* @param a_Type0 The type of the 1st argument
4678	* @param a_Arg0 The name of the 1st argument.
4679	* @param a_Type1 The type of the 2nd argument.
4680	* @param a_Arg1 The name of the 2nd argument.
4681	*/
4682	# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
4683	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
4684	/**
4685	* For defining a C instruction implementation function taking two extra
4686	* arguments.
4687	*
4688	* @param a_Name The name of the function.
4689	* @param a_Type0 The type of the 1st argument
4690	* @param a_Arg0 The name of the 1st argument.
4691	* @param a_Type1 The type of the 2nd argument.
4692	* @param a_Arg1 The name of the 2nd argument.
4693	*/
4694	# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
4695	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
4696	/**
4697	* Prototype version of IEM_CIMPL_DEF_2.
4698	*/
4699	# define IEM_CIMPL_PROTO_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
4700	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
4701	/**
4702	* For calling a C instruction implementation function taking two extra
4703	* arguments.
4704	*
4705	* This special call macro adds default arguments to the call and allow us to
4706	* change these later.
4707	*
4708	* @param a_fn The name of the function.
4709	* @param a0 The name of the 1st argument.
4710	* @param a1 The name of the 2nd argument.
4711	*/
4712	# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
4713
4714	/**
4715	* For typedef'ing or declaring a C instruction implementation function taking
4716	* three extra arguments.
4717	*
4718	* @param a_Name The name of the type.
4719	* @param a_Type0 The type of the 1st argument
4720	* @param a_Arg0 The name of the 1st argument.
4721	* @param a_Type1 The type of the 2nd argument.
4722	* @param a_Arg1 The name of the 2nd argument.
4723	* @param a_Type2 The type of the 3rd argument.
4724	* @param a_Arg2 The name of the 3rd argument.
4725	*/
4726	# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
4727	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
4728	/**
4729	* For defining a C instruction implementation function taking three extra
4730	* arguments.
4731	*
4732	* @param a_Name The name of the function.
4733	* @param a_Type0 The type of the 1st argument
4734	* @param a_Arg0 The name of the 1st argument.
4735	* @param a_Type1 The type of the 2nd argument.
4736	* @param a_Arg1 The name of the 2nd argument.
4737	* @param a_Type2 The type of the 3rd argument.
4738	* @param a_Arg2 The name of the 3rd argument.
4739	*/
4740	# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
4741	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
4742	/**
4743	* Prototype version of IEM_CIMPL_DEF_3.
4744	*/
4745	# define IEM_CIMPL_PROTO_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
4746	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
4747	/**
4748	* For calling a C instruction implementation function taking three extra
4749	* arguments.
4750	*
4751	* This special call macro adds default arguments to the call and allow us to
4752	* change these later.
4753	*
4754	* @param a_fn The name of the function.
4755	* @param a0 The name of the 1st argument.
4756	* @param a1 The name of the 2nd argument.
4757	* @param a2 The name of the 3rd argument.
4758	*/
4759	# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
4760
4761
4762	/**
4763	* For typedef'ing or declaring a C instruction implementation function taking
4764	* four extra arguments.
4765	*
4766	* @param a_Name The name of the type.
4767	* @param a_Type0 The type of the 1st argument
4768	* @param a_Arg0 The name of the 1st argument.
4769	* @param a_Type1 The type of the 2nd argument.
4770	* @param a_Arg1 The name of the 2nd argument.
4771	* @param a_Type2 The type of the 3rd argument.
4772	* @param a_Arg2 The name of the 3rd argument.
4773	* @param a_Type3 The type of the 4th argument.
4774	* @param a_Arg3 The name of the 4th argument.
4775	*/
4776	# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
4777	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
4778	/**
4779	* For defining a C instruction implementation function taking four extra
4780	* arguments.
4781	*
4782	* @param a_Name The name of the function.
4783	* @param a_Type0 The type of the 1st argument
4784	* @param a_Arg0 The name of the 1st argument.
4785	* @param a_Type1 The type of the 2nd argument.
4786	* @param a_Arg1 The name of the 2nd argument.
4787	* @param a_Type2 The type of the 3rd argument.
4788	* @param a_Arg2 The name of the 3rd argument.
4789	* @param a_Type3 The type of the 4th argument.
4790	* @param a_Arg3 The name of the 4th argument.
4791	*/
4792	# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
4793	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4794	a_Type2 a_Arg2, a_Type3 a_Arg3))
4795	/**
4796	* Prototype version of IEM_CIMPL_DEF_4.
4797	*/
4798	# define IEM_CIMPL_PROTO_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
4799	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4800	a_Type2 a_Arg2, a_Type3 a_Arg3))
4801	/**
4802	* For calling a C instruction implementation function taking four extra
4803	* arguments.
4804	*
4805	* This special call macro adds default arguments to the call and allow us to
4806	* change these later.
4807	*
4808	* @param a_fn The name of the function.
4809	* @param a0 The name of the 1st argument.
4810	* @param a1 The name of the 2nd argument.
4811	* @param a2 The name of the 3rd argument.
4812	* @param a3 The name of the 4th argument.
4813	*/
4814	# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
4815
4816
4817	/**
4818	* For typedef'ing or declaring a C instruction implementation function taking
4819	* five extra arguments.
4820	*
4821	* @param a_Name The name of the type.
4822	* @param a_Type0 The type of the 1st argument
4823	* @param a_Arg0 The name of the 1st argument.
4824	* @param a_Type1 The type of the 2nd argument.
4825	* @param a_Arg1 The name of the 2nd argument.
4826	* @param a_Type2 The type of the 3rd argument.
4827	* @param a_Arg2 The name of the 3rd argument.
4828	* @param a_Type3 The type of the 4th argument.
4829	* @param a_Arg3 The name of the 4th argument.
4830	* @param a_Type4 The type of the 5th argument.
4831	* @param a_Arg4 The name of the 5th argument.
4832	*/
4833	# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
4834	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, \
4835	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
4836	a_Type3 a_Arg3, a_Type4 a_Arg4))
4837	/**
4838	* For defining a C instruction implementation function taking five extra
4839	* arguments.
4840	*
4841	* @param a_Name The name of the function.
4842	* @param a_Type0 The type of the 1st argument
4843	* @param a_Arg0 The name of the 1st argument.
4844	* @param a_Type1 The type of the 2nd argument.
4845	* @param a_Arg1 The name of the 2nd argument.
4846	* @param a_Type2 The type of the 3rd argument.
4847	* @param a_Arg2 The name of the 3rd argument.
4848	* @param a_Type3 The type of the 4th argument.
4849	* @param a_Arg3 The name of the 4th argument.
4850	* @param a_Type4 The type of the 5th argument.
4851	* @param a_Arg4 The name of the 5th argument.
4852	*/
4853	# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
4854	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4855	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
4856	/**
4857	* Prototype version of IEM_CIMPL_DEF_5.
4858	*/
4859	# define IEM_CIMPL_PROTO_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
4860	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4861	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
4862	/**
4863	* For calling a C instruction implementation function taking five extra
4864	* arguments.
4865	*
4866	* This special call macro adds default arguments to the call and allow us to
4867	* change these later.
4868	*
4869	* @param a_fn The name of the function.
4870	* @param a0 The name of the 1st argument.
4871	* @param a1 The name of the 2nd argument.
4872	* @param a2 The name of the 3rd argument.
4873	* @param a3 The name of the 4th argument.
4874	* @param a4 The name of the 5th argument.
4875	*/
4876	# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
4877
4878	/** @} */
4879
4880
4881	/** @name Opcode Decoder Function Types.
4882	* @{ */
4883
4884	/** @typedef PFNIEMOP
4885	* Pointer to an opcode decoder function.
4886	*/
4887
4888	/** @def FNIEMOP_DEF
4889	* Define an opcode decoder function.
4890	*
4891	* We're using macors for this so that adding and removing parameters as well as
4892	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL
4893	*
4894	* @param a_Name The function name.
4895	*/
4896
4897	/** @typedef PFNIEMOPRM
4898	* Pointer to an opcode decoder function with RM byte.
4899	*/
4900
4901	/** @def FNIEMOPRM_DEF
4902	* Define an opcode decoder function with RM byte.
4903	*
4904	* We're using macors for this so that adding and removing parameters as well as
4905	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL_1
4906	*
4907	* @param a_Name The function name.
4908	*/
4909
4910	#if defined(__GNUC__) && defined(RT_ARCH_X86)
4911	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOP)(PVMCPUCC pVCpu);
4912	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4913	# define FNIEMOP_DEF(a_Name) \
4914	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu)
4915	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4916	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
4917	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4918	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
4919
4920	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
4921	typedef VBOXSTRICTRC (__fastcall * PFNIEMOP)(PVMCPUCC pVCpu);
4922	typedef VBOXSTRICTRC (__fastcall * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4923	# define FNIEMOP_DEF(a_Name) \
4924	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
4925	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4926	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
4927	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4928	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
4929
4930	#elif defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
4931	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
4932	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4933	# define FNIEMOP_DEF(a_Name) \
4934	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu)
4935	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4936	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
4937	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4938	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
4939
4940	#else
4941	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
4942	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4943	# define FNIEMOP_DEF(a_Name) \
4944	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
4945	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4946	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
4947	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4948	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
4949
4950	#endif
4951	#define FNIEMOPRM_DEF(a_Name) FNIEMOP_DEF_1(a_Name, uint8_t, bRm)
4952
4953	/**
4954	* Call an opcode decoder function.
4955	*
4956	* We're using macors for this so that adding and removing parameters can be
4957	* done as we please. See FNIEMOP_DEF.
4958	*/
4959	#define FNIEMOP_CALL(a_pfn) (a_pfn)(pVCpu)
4960
4961	/**
4962	* Call a common opcode decoder function taking one extra argument.
4963	*
4964	* We're using macors for this so that adding and removing parameters can be
4965	* done as we please. See FNIEMOP_DEF_1.
4966	*/
4967	#define FNIEMOP_CALL_1(a_pfn, a0) (a_pfn)(pVCpu, a0)
4968
4969	/**
4970	* Call a common opcode decoder function taking one extra argument.
4971	*
4972	* We're using macors for this so that adding and removing parameters can be
4973	* done as we please. See FNIEMOP_DEF_1.
4974	*/
4975	#define FNIEMOP_CALL_2(a_pfn, a0, a1) (a_pfn)(pVCpu, a0, a1)
4976	/** @} */
4977
4978
4979	/** @name Misc Helpers
4980	* @{ */
4981
4982	/** Used to shut up GCC warnings about variables that 'may be used uninitialized'
4983	* due to GCC lacking knowledge about the value range of a switch. */
4984	#if RT_CPLUSPLUS_PREREQ(202000)
4985	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: [[unlikely]] AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
4986	#else
4987	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
4988	#endif
4989
4990	/** Variant of IEM_NOT_REACHED_DEFAULT_CASE_RET that returns a custom value. */
4991	#if RT_CPLUSPLUS_PREREQ(202000)
4992	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: [[unlikely]] AssertFailedReturn(a_RetValue)
4993	#else
4994	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: AssertFailedReturn(a_RetValue)
4995	#endif
4996
4997	/**
4998	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
4999	* occation.
5000	*/
5001	#ifdef LOG_ENABLED
5002	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
5003	do { \
5004	/Log/ LogAlways(("%s: returning IEM_RETURN_ASPECT_NOT_IMPLEMENTED (line %d)\n", __FUNCTION__, __LINE__)); \
5005	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
5006	} while (0)
5007	#else
5008	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
5009	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
5010	#endif
5011
5012	/**
5013	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
5014	* occation using the supplied logger statement.
5015	*
5016	* @param a_LoggerArgs What to log on failure.
5017	*/
5018	#ifdef LOG_ENABLED
5019	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
5020	do { \
5021	LogAlways((LOG_FN_FMT ": ", __PRETTY_FUNCTION__)); LogAlways(a_LoggerArgs); \
5022	/LogFunc(a_LoggerArgs);/ \
5023	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
5024	} while (0)
5025	#else
5026	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
5027	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
5028	#endif
5029
5030	/**
5031	* Gets the CPU mode (from fExec) as a IEMMODE value.
5032	*
5033	* @returns IEMMODE
5034	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5035	*/
5036	#define IEM_GET_CPU_MODE(a_pVCpu) ((a_pVCpu)->iem.s.fExec & IEM_F_MODE_CPUMODE_MASK)
5037
5038	/**
5039	* Check if we're currently executing in real or virtual 8086 mode.
5040	*
5041	* @returns @c true if it is, @c false if not.
5042	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5043	*/
5044	#define IEM_IS_REAL_OR_V86_MODE(a_pVCpu) (( ((a_pVCpu)->iem.s.fExec ^ IEM_F_MODE_X86_PROT_MASK) \
5045	& (IEM_F_MODE_X86_V86_MASK \| IEM_F_MODE_X86_PROT_MASK)) != 0)
5046
5047	/**
5048	* Check if we're currently executing in virtual 8086 mode.
5049	*
5050	* @returns @c true if it is, @c false if not.
5051	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5052	*/
5053	#define IEM_IS_V86_MODE(a_pVCpu) (((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_V86_MASK) != 0)
5054
5055	/**
5056	* Check if we're currently executing in long mode.
5057	*
5058	* @returns @c true if it is, @c false if not.
5059	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5060	*/
5061	#define IEM_IS_LONG_MODE(a_pVCpu) (CPUMIsGuestInLongModeEx(IEM_GET_CTX(a_pVCpu)))
5062
5063	/**
5064	* Check if we're currently executing in a 16-bit code segment.
5065	*
5066	* @returns @c true if it is, @c false if not.
5067	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5068	*/
5069	#define IEM_IS_16BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_16BIT)
5070
5071	/**
5072	* Check if we're currently executing in a 32-bit code segment.
5073	*
5074	* @returns @c true if it is, @c false if not.
5075	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5076	*/
5077	#define IEM_IS_32BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_32BIT)
5078
5079	/**
5080	* Check if we're currently executing in a 64-bit code segment.
5081	*
5082	* @returns @c true if it is, @c false if not.
5083	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5084	*/
5085	#define IEM_IS_64BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_64BIT)
5086
5087	/**
5088	* Check if we're currently executing in real mode.
5089	*
5090	* @returns @c true if it is, @c false if not.
5091	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5092	*/
5093	#define IEM_IS_REAL_MODE(a_pVCpu) (!((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_PROT_MASK))
5094
5095	/**
5096	* Gets the current protection level (CPL).
5097	*
5098	* @returns 0..3
5099	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5100	*/
5101	#define IEM_GET_CPL(a_pVCpu) (((a_pVCpu)->iem.s.fExec >> IEM_F_X86_CPL_SHIFT) & IEM_F_X86_CPL_SMASK)
5102
5103	/**
5104	* Sets the current protection level (CPL).
5105	*
5106	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5107	*/
5108	#define IEM_SET_CPL(a_pVCpu, a_uCpl) \
5109	do { (a_pVCpu)->iem.s.fExec = ((a_pVCpu)->iem.s.fExec & ~IEM_F_X86_CPL_MASK) \| ((a_uCpl) << IEM_F_X86_CPL_SHIFT); } while (0)
5110
5111	/**
5112	* Returns a (const) pointer to the CPUMFEATURES for the guest CPU.
5113	* @returns PCCPUMFEATURES
5114	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5115	*/
5116	#define IEM_GET_GUEST_CPU_FEATURES(a_pVCpu) (&((a_pVCpu)->CTX_SUFF(pVM)->cpum.ro.GuestFeatures))
5117
5118	/**
5119	* Returns a (const) pointer to the CPUMFEATURES for the host CPU.
5120	* @returns PCCPUMFEATURES
5121	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5122	*/
5123	#define IEM_GET_HOST_CPU_FEATURES(a_pVCpu) (&g_CpumHostFeatures.s)
5124
5125	/**
5126	* Evaluates to true if we're presenting an Intel CPU to the guest.
5127	*/
5128	#define IEM_IS_GUEST_CPU_INTEL(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL )
5129
5130	/**
5131	* Evaluates to true if we're presenting an AMD CPU to the guest.
5132	*/
5133	#define IEM_IS_GUEST_CPU_AMD(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_AMD \|\| (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_HYGON )
5134
5135	/**
5136	* Check if the address is canonical.
5137	*/
5138	#define IEM_IS_CANONICAL(a_u64Addr) X86_IS_CANONICAL(a_u64Addr)
5139
5140	/** Checks if the ModR/M byte is in register mode or not. */
5141	#define IEM_IS_MODRM_REG_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT) )
5142	/** Checks if the ModR/M byte is in memory mode or not. */
5143	#define IEM_IS_MODRM_MEM_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT) )
5144
5145	/**
5146	* Gets the register (reg) part of a ModR/M encoding, with REX.R added in.
5147	*
5148	* For use during decoding.
5149	*/
5150	#define IEM_GET_MODRM_REG(a_pVCpu, a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| (a_pVCpu)->iem.s.uRexReg )
5151	/**
5152	* Gets the r/m part of a ModR/M encoding as a register index, with REX.B added in.
5153	*
5154	* For use during decoding.
5155	*/
5156	#define IEM_GET_MODRM_RM(a_pVCpu, a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) \| (a_pVCpu)->iem.s.uRexB )
5157
5158	/**
5159	* Gets the register (reg) part of a ModR/M encoding, without REX.R.
5160	*
5161	* For use during decoding.
5162	*/
5163	#define IEM_GET_MODRM_REG_8(a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) )
5164	/**
5165	* Gets the r/m part of a ModR/M encoding as a register index, without REX.B.
5166	*
5167	* For use during decoding.
5168	*/
5169	#define IEM_GET_MODRM_RM_8(a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) )
5170
5171	/**
5172	* Gets the register (reg) part of a ModR/M encoding as an extended 8-bit
5173	* register index, with REX.R added in.
5174	*
5175	* For use during decoding.
5176	*
5177	* @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
5178	*/
5179	#define IEM_GET_MODRM_REG_EX8(a_pVCpu, a_bRm) \
5180	( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
5181	\|\| !((a_bRm) & (4 << X86_MODRM_REG_SHIFT)) /* IEM_GET_MODRM_REG(pVCpu, a_bRm) < 4 */ \
5182	? IEM_GET_MODRM_REG(pVCpu, a_bRm) : (((a_bRm) >> X86_MODRM_REG_SHIFT) & 3) \| 16)
5183	/**
5184	* Gets the r/m part of a ModR/M encoding as an extended 8-bit register index,
5185	* with REX.B added in.
5186	*
5187	* For use during decoding.
5188	*
5189	* @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
5190	*/
5191	#define IEM_GET_MODRM_RM_EX8(a_pVCpu, a_bRm) \
5192	( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
5193	\|\| !((a_bRm) & 4) /* IEM_GET_MODRM_RM(pVCpu, a_bRm) < 4 */ \
5194	? IEM_GET_MODRM_RM(pVCpu, a_bRm) : ((a_bRm) & 3) \| 16)
5195
5196	/**
5197	* Combines the prefix REX and ModR/M byte for passing to
5198	* iemOpHlpCalcRmEffAddrThreadedAddr64().
5199	*
5200	* @returns The ModRM byte but with bit 3 set to REX.B and bit 4 to REX.X.
5201	* The two bits are part of the REG sub-field, which isn't needed in
5202	* iemOpHlpCalcRmEffAddrThreadedAddr64().
5203	*
5204	* For use during decoding/recompiling.
5205	*/
5206	#define IEM_GET_MODRM_EX(a_pVCpu, a_bRm) \
5207	( ((a_bRm) & ~X86_MODRM_REG_MASK) \
5208	\| (uint8_t)( (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X)) >> (25 - 3) ) )
5209	AssertCompile(IEM_OP_PRF_REX_B == RT_BIT_32(25));
5210	AssertCompile(IEM_OP_PRF_REX_X == RT_BIT_32(26));
5211
5212	/**
5213	* Gets the effective VEX.VVVV value.
5214	*
5215	* The 4th bit is ignored if not 64-bit code.
5216	* @returns effective V-register value.
5217	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5218	*/
5219	#define IEM_GET_EFFECTIVE_VVVV(a_pVCpu) \
5220	(IEM_IS_64BIT_CODE(a_pVCpu) ? (a_pVCpu)->iem.s.uVex3rdReg : (a_pVCpu)->iem.s.uVex3rdReg & 7)
5221
5222
5223	/**
5224	* Gets the register (reg) part of a the special 4th register byte used by
5225	* vblendvps and vblendvpd.
5226	*
5227	* For use during decoding.
5228	*/
5229	#define IEM_GET_IMM8_REG(a_pVCpu, a_bRegImm8) \
5230	(IEM_IS_64BIT_CODE(a_pVCpu) ? (a_bRegImm8) >> 4 : ((a_bRegImm8) >> 4) & 7)
5231
5232
5233	/**
5234	* Checks if we're executing inside an AMD-V or VT-x guest.
5235	*/
5236	#if defined(VBOX_WITH_NESTED_HWVIRT_VMX) \|\| defined(VBOX_WITH_NESTED_HWVIRT_SVM)
5237	# define IEM_IS_IN_GUEST(a_pVCpu) RT_BOOL((a_pVCpu)->iem.s.fExec & IEM_F_X86_CTX_IN_GUEST)
5238	#else
5239	# define IEM_IS_IN_GUEST(a_pVCpu) false
5240	#endif
5241
5242
5243	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5244
5245	/**
5246	* Check if the guest has entered VMX root operation.
5247	*/
5248	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxRootMode(IEM_GET_CTX(a_pVCpu)))
5249
5250	/**
5251	* Check if the guest has entered VMX non-root operation.
5252	*/
5253	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) ( ((a_pVCpu)->iem.s.fExec & (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST)) \
5254	== (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST) )
5255
5256	/**
5257	* Check if the nested-guest has the given Pin-based VM-execution control set.
5258	*/
5259	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_PinCtl) (CPUMIsGuestVmxPinCtlsSet(IEM_GET_CTX(a_pVCpu), (a_PinCtl)))
5260
5261	/**
5262	* Check if the nested-guest has the given Processor-based VM-execution control set.
5263	*/
5264	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_ProcCtl) (CPUMIsGuestVmxProcCtlsSet(IEM_GET_CTX(a_pVCpu), (a_ProcCtl)))
5265
5266	/**
5267	* Check if the nested-guest has the given Secondary Processor-based VM-execution
5268	* control set.
5269	*/
5270	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_ProcCtl2) (CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(a_pVCpu), (a_ProcCtl2)))
5271
5272	/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
5273	# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
5274
5275	/** Whether a shadow VMCS is present for the given VCPU. */
5276	# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
5277
5278	/** Gets the VMXON region pointer. */
5279	# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
5280
5281	/** Gets the guest-physical address of the current VMCS for the given VCPU. */
5282	# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
5283
5284	/** Whether a current VMCS is present for the given VCPU. */
5285	# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
5286
5287	/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
5288	# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
5289	do \
5290	{ \
5291	Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
5292	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
5293	} while (0)
5294
5295	/** Clears any current VMCS for the given VCPU. */
5296	# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
5297	do \
5298	{ \
5299	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
5300	} while (0)
5301
5302	/**
5303	* Invokes the VMX VM-exit handler for an instruction intercept.
5304	*/
5305	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) \
5306	do { return iemVmxVmexitInstr((a_pVCpu), (a_uExitReason), (a_cbInstr)); } while (0)
5307
5308	/**
5309	* Invokes the VMX VM-exit handler for an instruction intercept where the
5310	* instruction provides additional VM-exit information.
5311	*/
5312	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) \
5313	do { return iemVmxVmexitInstrNeedsInfo((a_pVCpu), (a_uExitReason), (a_uInstrId), (a_cbInstr)); } while (0)
5314
5315	/**
5316	* Invokes the VMX VM-exit handler for a task switch.
5317	*/
5318	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) \
5319	do { return iemVmxVmexitTaskSwitch((a_pVCpu), (a_enmTaskSwitch), (a_SelNewTss), (a_cbInstr)); } while (0)
5320
5321	/**
5322	* Invokes the VMX VM-exit handler for MWAIT.
5323	*/
5324	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) \
5325	do { return iemVmxVmexitInstrMwait((a_pVCpu), (a_fMonitorArmed), (a_cbInstr)); } while (0)
5326
5327	/**
5328	* Invokes the VMX VM-exit handler for EPT faults.
5329	*/
5330	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) \
5331	do { return iemVmxVmexitEpt(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr); } while (0)
5332
5333	/**
5334	* Invokes the VMX VM-exit handler.
5335	*/
5336	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) \
5337	do { return iemVmxVmexit((a_pVCpu), (a_uExitReason), (a_uExitQual)); } while (0)
5338
5339	#else
5340	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (false)
5341	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (false)
5342	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_cbInstr) (false)
5343	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_cbInstr) (false)
5344	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_cbInstr) (false)
5345	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5346	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5347	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5348	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5349	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5350	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) do { return VERR_VMX_IPE_1; } while (0)
5351
5352	#endif
5353
5354	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5355	/**
5356	* Checks if we're executing a guest using AMD-V.
5357	*/
5358	# define IEM_SVM_IS_IN_GUEST(a_pVCpu) ( (a_pVCpu->iem.s.fExec & (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST)) \
5359	== (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST))
5360	/**
5361	* Check if an SVM control/instruction intercept is set.
5362	*/
5363	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) \
5364	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmCtrlInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_Intercept)))
5365
5366	/**
5367	* Check if an SVM read CRx intercept is set.
5368	*/
5369	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
5370	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
5371
5372	/**
5373	* Check if an SVM write CRx intercept is set.
5374	*/
5375	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
5376	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
5377
5378	/**
5379	* Check if an SVM read DRx intercept is set.
5380	*/
5381	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
5382	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
5383
5384	/**
5385	* Check if an SVM write DRx intercept is set.
5386	*/
5387	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
5388	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
5389
5390	/**
5391	* Check if an SVM exception intercept is set.
5392	*/
5393	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) \
5394	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmXcptInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uVector)))
5395
5396	/**
5397	* Invokes the SVM \#VMEXIT handler for the nested-guest.
5398	*/
5399	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
5400	do { return iemSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2)); } while (0)
5401
5402	/**
5403	* Invokes the 'MOV CRx' SVM \#VMEXIT handler after constructing the
5404	* corresponding decode assist information.
5405	*/
5406	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) \
5407	do \
5408	{ \
5409	uint64_t uExitInfo1; \
5410	if ( IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmDecodeAssists \
5411	&& (a_enmAccessCrX) == IEMACCESSCRX_MOV_CRX) \
5412	uExitInfo1 = SVM_EXIT1_MOV_CRX_MASK \| ((a_iGReg) & 7); \
5413	else \
5414	uExitInfo1 = 0; \
5415	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, uExitInfo1, 0); \
5416	} while (0)
5417
5418	/** Check and handles SVM nested-guest instruction intercept and updates
5419	* NRIP if needed.
5420	*/
5421	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
5422	do \
5423	{ \
5424	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept)) \
5425	{ \
5426	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
5427	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2); \
5428	} \
5429	} while (0)
5430
5431	/** Checks and handles SVM nested-guest CR0 read intercept. */
5432	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
5433	do \
5434	{ \
5435	if (!IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, 0)) \
5436	{ /* probably likely */ } \
5437	else \
5438	{ \
5439	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
5440	IEM_SVM_VMEXIT_RET(a_pVCpu, SVM_EXIT_READ_CR0, a_uExitInfo1, a_uExitInfo2); \
5441	} \
5442	} while (0)
5443
5444	/**
5445	* Updates the NextRIP (NRI) field in the nested-guest VMCB.
5446	*/
5447	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) \
5448	do { \
5449	if (IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmNextRipSave) \
5450	CPUMGuestSvmUpdateNRip(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_cbInstr)); \
5451	} while (0)
5452
5453	#else
5454	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) (false)
5455	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
5456	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
5457	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
5458	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
5459	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) (false)
5460	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { return VERR_SVM_IPE_1; } while (0)
5461	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) do { return VERR_SVM_IPE_1; } while (0)
5462	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, \
5463	a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
5464	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
5465	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) do { } while (0)
5466
5467	#endif
5468
5469	/** @} */
5470
5471	uint32_t iemCalcExecDbgFlagsSlow(PVMCPUCC pVCpu);
5472	VBOXSTRICTRC iemExecInjectPendingTrap(PVMCPUCC pVCpu);
5473
5474
5475	/**
5476	* Selector descriptor table entry as fetched by iemMemFetchSelDesc.
5477	*/
5478	typedef union IEMSELDESC
5479	{
5480	/** The legacy view. */
5481	X86DESC Legacy;
5482	/** The long mode view. */
5483	X86DESC64 Long;
5484	} IEMSELDESC;
5485	/** Pointer to a selector descriptor table entry. */
5486	typedef IEMSELDESC *PIEMSELDESC;
5487
5488	/** @name Raising Exceptions.
5489	* @{ */
5490	VBOXSTRICTRC iemTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, uint32_t uNextEip, uint32_t fFlags,
5491	uint16_t uErr, uint64_t uCr2, RTSEL SelTSS, PIEMSELDESC pNewDescTSS) RT_NOEXCEPT;
5492
5493	VBOXSTRICTRC iemRaiseXcptOrInt(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags,
5494	uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
5495	#ifdef IEM_WITH_SETJMP
5496	DECL_NO_RETURN(void) iemRaiseXcptOrIntJmp(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector,
5497	uint32_t fFlags, uint16_t uErr, uint64_t uCr2) IEM_NOEXCEPT_MAY_LONGJMP;
5498	#endif
5499	VBOXSTRICTRC iemRaiseDivideError(PVMCPUCC pVCpu) RT_NOEXCEPT;
5500	#ifdef IEM_WITH_SETJMP
5501	DECL_NO_RETURN(void) iemRaiseDivideErrorJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5502	#endif
5503	VBOXSTRICTRC iemRaiseDebugException(PVMCPUCC pVCpu) RT_NOEXCEPT;
5504	VBOXSTRICTRC iemRaiseBoundRangeExceeded(PVMCPUCC pVCpu) RT_NOEXCEPT;
5505	VBOXSTRICTRC iemRaiseUndefinedOpcode(PVMCPUCC pVCpu) RT_NOEXCEPT;
5506	#ifdef IEM_WITH_SETJMP
5507	DECL_NO_RETURN(void) iemRaiseUndefinedOpcodeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5508	#endif
5509	VBOXSTRICTRC iemRaiseDeviceNotAvailable(PVMCPUCC pVCpu) RT_NOEXCEPT;
5510	#ifdef IEM_WITH_SETJMP
5511	DECL_NO_RETURN(void) iemRaiseDeviceNotAvailableJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5512	#endif
5513	VBOXSTRICTRC iemRaiseTaskSwitchFaultWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5514	VBOXSTRICTRC iemRaiseTaskSwitchFaultCurrentTSS(PVMCPUCC pVCpu) RT_NOEXCEPT;
5515	VBOXSTRICTRC iemRaiseTaskSwitchFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
5516	VBOXSTRICTRC iemRaiseTaskSwitchFaultBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5517	/VBOXSTRICTRC iemRaiseSelectorNotPresent(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;/
5518	VBOXSTRICTRC iemRaiseSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5519	VBOXSTRICTRC iemRaiseSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5520	VBOXSTRICTRC iemRaiseStackSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5521	VBOXSTRICTRC iemRaiseStackSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5522	VBOXSTRICTRC iemRaiseGeneralProtectionFault(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5523	VBOXSTRICTRC iemRaiseGeneralProtectionFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
5524	#ifdef IEM_WITH_SETJMP
5525	DECL_NO_RETURN(void) iemRaiseGeneralProtectionFault0Jmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5526	#endif
5527	VBOXSTRICTRC iemRaiseGeneralProtectionFaultBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
5528	VBOXSTRICTRC iemRaiseNotCanonical(PVMCPUCC pVCpu) RT_NOEXCEPT;
5529	VBOXSTRICTRC iemRaiseSelectorBounds(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
5530	#ifdef IEM_WITH_SETJMP
5531	DECL_NO_RETURN(void) iemRaiseSelectorBoundsJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
5532	#endif
5533	VBOXSTRICTRC iemRaiseSelectorBoundsBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
5534	#ifdef IEM_WITH_SETJMP
5535	DECL_NO_RETURN(void) iemRaiseSelectorBoundsBySelectorJmp(PVMCPUCC pVCpu, RTSEL Sel) IEM_NOEXCEPT_MAY_LONGJMP;
5536	#endif
5537	VBOXSTRICTRC iemRaiseSelectorInvalidAccess(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
5538	#ifdef IEM_WITH_SETJMP
5539	DECL_NO_RETURN(void) iemRaiseSelectorInvalidAccessJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
5540	#endif
5541	VBOXSTRICTRC iemRaisePageFault(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) RT_NOEXCEPT;
5542	#ifdef IEM_WITH_SETJMP
5543	DECL_NO_RETURN(void) iemRaisePageFaultJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) IEM_NOEXCEPT_MAY_LONGJMP;
5544	#endif
5545	VBOXSTRICTRC iemRaiseMathFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
5546	#ifdef IEM_WITH_SETJMP
5547	DECL_NO_RETURN(void) iemRaiseMathFaultJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5548	#endif
5549	VBOXSTRICTRC iemRaiseAlignmentCheckException(PVMCPUCC pVCpu) RT_NOEXCEPT;
5550	#ifdef IEM_WITH_SETJMP
5551	DECL_NO_RETURN(void) iemRaiseAlignmentCheckExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5552	#endif
5553	VBOXSTRICTRC iemRaiseSimdFpException(PVMCPUCC pVCpu) RT_NOEXCEPT;
5554	#ifdef IEM_WITH_SETJMP
5555	DECL_NO_RETURN(void) iemRaiseSimdFpExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5556	#endif
5557
5558	void iemLogSyscallRealModeInt(PVMCPUCC pVCpu, uint8_t u8Vector, uint8_t cbInstr);
5559	void iemLogSyscallProtModeInt(PVMCPUCC pVCpu, uint8_t u8Vector, uint8_t cbInstr);
5560
5561	IEM_CIMPL_DEF_0(iemCImplRaiseDivideError);
5562	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidLockPrefix);
5563	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidOpcode);
5564
5565	/**
5566	* Macro for calling iemCImplRaiseDivideError().
5567	*
5568	* This is for things that will _always_ decode to an \#DE, taking the
5569	* recompiler into consideration and everything.
5570	*
5571	* @return Strict VBox status code.
5572	*/
5573	#define IEMOP_RAISE_DIVIDE_ERROR_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseDivideError)
5574
5575	/**
5576	* Macro for calling iemCImplRaiseInvalidLockPrefix().
5577	*
5578	* This is for things that will _always_ decode to an \#UD, taking the
5579	* recompiler into consideration and everything.
5580	*
5581	* @return Strict VBox status code.
5582	*/
5583	#define IEMOP_RAISE_INVALID_LOCK_PREFIX_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidLockPrefix)
5584
5585	/**
5586	* Macro for calling iemCImplRaiseInvalidOpcode() for decode/static \#UDs.
5587	*
5588	* This is for things that will _always_ decode to an \#UD, taking the
5589	* recompiler into consideration and everything.
5590	*
5591	* @return Strict VBox status code.
5592	*/
5593	#define IEMOP_RAISE_INVALID_OPCODE_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidOpcode)
5594
5595	/**
5596	* Macro for calling iemCImplRaiseInvalidOpcode() for runtime-style \#UDs.
5597	*
5598	* Using this macro means you've got _buggy_ _code_ and are doing things that
5599	* belongs exclusively in IEMAllCImpl.cpp during decoding.
5600	*
5601	* @return Strict VBox status code.
5602	* @see IEMOP_RAISE_INVALID_OPCODE_RET
5603	*/
5604	#define IEMOP_RAISE_INVALID_OPCODE_RUNTIME_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidOpcode)
5605
5606	/** @} */
5607
5608	/** @name Register Access.
5609	* @{ */
5610	VBOXSTRICTRC iemRegRipRelativeJumpS8AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int8_t offNextInstr,
5611	IEMMODE enmEffOpSize) RT_NOEXCEPT;
5612	VBOXSTRICTRC iemRegRipRelativeJumpS16AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int16_t offNextInstr) RT_NOEXCEPT;
5613	VBOXSTRICTRC iemRegRipRelativeJumpS32AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int32_t offNextInstr,
5614	IEMMODE enmEffOpSize) RT_NOEXCEPT;
5615	/** @} */
5616
5617	/** @name FPU access and helpers.
5618	* @{ */
5619	void iemFpuPushResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
5620	void iemFpuPushResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5621	void iemFpuPushResultTwo(PVMCPUCC pVCpu, PIEMFPURESULTTWO pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
5622	void iemFpuStoreResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
5623	void iemFpuStoreResultThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
5624	void iemFpuStoreResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
5625	uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5626	void iemFpuStoreResultWithMemOpThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
5627	uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5628	void iemFpuUpdateOpcodeAndIp(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5629	void iemFpuUpdateFSW(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
5630	void iemFpuUpdateFSWThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
5631	void iemFpuUpdateFSWWithMemOp(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5632	void iemFpuUpdateFSWThenPopPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
5633	void iemFpuUpdateFSWWithMemOpThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5634	void iemFpuStackUnderflow(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
5635	void iemFpuStackUnderflowWithMemOp(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5636	void iemFpuStackUnderflowThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
5637	void iemFpuStackUnderflowWithMemOpThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5638	void iemFpuStackUnderflowThenPopPop(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5639	void iemFpuStackPushUnderflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5640	void iemFpuStackPushUnderflowTwo(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5641	void iemFpuStackPushOverflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5642	void iemFpuStackPushOverflowWithMemOp(PVMCPUCC pVCpu, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5643	/** @} */
5644
5645	/** @name SSE+AVX SIMD access and helpers.
5646	* @{ */
5647	void iemSseUpdateMxcsr(PVMCPUCC pVCpu, uint32_t fMxcsr) RT_NOEXCEPT;
5648	/** @} */
5649
5650	/** @name Memory access.
5651	* @{ */
5652
5653	/** Report a \#GP instead of \#AC and do not restrict to ring-3 */
5654	#define IEM_MEMMAP_F_ALIGN_GP RT_BIT_32(16)
5655	/** SSE access that should report a \#GP instead of \#AC, unless MXCSR.MM=1
5656	* when it works like normal \#AC. Always used with IEM_MEMMAP_F_ALIGN_GP. */
5657	#define IEM_MEMMAP_F_ALIGN_SSE RT_BIT_32(17)
5658	/** If \#AC is applicable, raise it. Always used with IEM_MEMMAP_F_ALIGN_GP.
5659	* Users include FXSAVE & FXRSTOR. */
5660	#define IEM_MEMMAP_F_ALIGN_GP_OR_AC RT_BIT_32(18)
5661
5662	VBOXSTRICTRC iemMemMap(PVMCPUCC pVCpu, void *ppvMem, uint8_t pbUnmapInfo, size_t cbMem, uint8_t iSegReg, RTGCPTR GCPtrMem,
5663	uint32_t fAccess, uint32_t uAlignCtl) RT_NOEXCEPT;
5664	VBOXSTRICTRC iemMemCommitAndUnmap(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5665	#ifndef IN_RING3
5666	VBOXSTRICTRC iemMemCommitAndUnmapPostponeTroubleToR3(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5667	#endif
5668	void iemMemRollbackAndUnmap(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5669	void iemMemRollback(PVMCPUCC pVCpu) RT_NOEXCEPT;
5670	VBOXSTRICTRC iemMemApplySegment(PVMCPUCC pVCpu, uint32_t fAccess, uint8_t iSegReg, size_t cbMem, PRTGCPTR pGCPtrMem) RT_NOEXCEPT;
5671	VBOXSTRICTRC iemMemMarkSelDescAccessed(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5672	VBOXSTRICTRC iemMemPageTranslateAndCheckAccess(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t cbAccess, uint32_t fAccess, PRTGCPHYS pGCPhysMem) RT_NOEXCEPT;
5673
5674	void iemOpcodeFlushLight(PVMCPUCC pVCpu, uint8_t cbInstr);
5675	void iemOpcodeFlushHeavy(PVMCPUCC pVCpu, uint8_t cbInstr);
5676	#ifdef IEM_WITH_CODE_TLB
5677	void iemOpcodeFetchBytesJmp(PVMCPUCC pVCpu, size_t cbDst, void *pvDst) IEM_NOEXCEPT_MAY_LONGJMP;
5678	#else
5679	VBOXSTRICTRC iemOpcodeFetchMoreBytes(PVMCPUCC pVCpu, size_t cbMin) RT_NOEXCEPT;
5680	#endif
5681	#ifdef IEM_WITH_SETJMP
5682	uint8_t iemOpcodeGetNextU8SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5683	uint16_t iemOpcodeGetNextU16SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5684	uint32_t iemOpcodeGetNextU32SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5685	uint64_t iemOpcodeGetNextU64SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5686	#else
5687	VBOXSTRICTRC iemOpcodeGetNextU8Slow(PVMCPUCC pVCpu, uint8_t *pb) RT_NOEXCEPT;
5688	VBOXSTRICTRC iemOpcodeGetNextS8SxU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
5689	VBOXSTRICTRC iemOpcodeGetNextS8SxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
5690	VBOXSTRICTRC iemOpcodeGetNextS8SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5691	VBOXSTRICTRC iemOpcodeGetNextU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
5692	VBOXSTRICTRC iemOpcodeGetNextU16ZxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
5693	VBOXSTRICTRC iemOpcodeGetNextU16ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5694	VBOXSTRICTRC iemOpcodeGetNextU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
5695	VBOXSTRICTRC iemOpcodeGetNextU32ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5696	VBOXSTRICTRC iemOpcodeGetNextS32SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5697	VBOXSTRICTRC iemOpcodeGetNextU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5698	#endif
5699
5700	VBOXSTRICTRC iemMemFetchDataU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5701	VBOXSTRICTRC iemMemFetchDataU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5702	VBOXSTRICTRC iemMemFetchDataU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5703	VBOXSTRICTRC iemMemFetchDataU32_ZX_U64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5704	VBOXSTRICTRC iemMemFetchDataU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5705	VBOXSTRICTRC iemMemFetchDataU64AlignedU128(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5706	VBOXSTRICTRC iemMemFetchDataR80(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5707	VBOXSTRICTRC iemMemFetchDataD80(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5708	VBOXSTRICTRC iemMemFetchDataU128(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5709	VBOXSTRICTRC iemMemFetchDataU128NoAc(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5710	VBOXSTRICTRC iemMemFetchDataU128AlignedSse(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5711	VBOXSTRICTRC iemMemFetchDataU256(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5712	VBOXSTRICTRC iemMemFetchDataU256NoAc(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5713	VBOXSTRICTRC iemMemFetchDataU256AlignedAvx(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5714	VBOXSTRICTRC iemMemFetchDataXdtr(PVMCPUCC pVCpu, uint16_t *pcbLimit, PRTGCPTR pGCPtrBase, uint8_t iSegReg,
5715	RTGCPTR GCPtrMem, IEMMODE enmOpSize) RT_NOEXCEPT;
5716	#ifdef IEM_WITH_SETJMP
5717	uint8_t iemMemFetchDataU8SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5718	uint16_t iemMemFetchDataU16SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5719	uint32_t iemMemFetchDataU32SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5720	uint32_t iemMemFlatFetchDataU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5721	uint64_t iemMemFetchDataU64SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5722	uint64_t iemMemFetchDataU64AlignedU128SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5723	void iemMemFetchDataR80SafeJmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5724	void iemMemFetchDataD80SafeJmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5725	void iemMemFetchDataU128SafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5726	void iemMemFetchDataU128NoAcSafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5727	void iemMemFetchDataU128AlignedSseSafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5728	void iemMemFetchDataU256SafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5729	void iemMemFetchDataU256NoAcSafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5730	void iemMemFetchDataU256AlignedAvxSafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5731	# if 0 /* these are inlined now */
5732	uint8_t iemMemFetchDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5733	uint16_t iemMemFetchDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5734	uint32_t iemMemFetchDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5735	uint32_t iemMemFlatFetchDataU32Jmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5736	uint64_t iemMemFetchDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5737	uint64_t iemMemFetchDataU64AlignedU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5738	void iemMemFetchDataR80Jmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5739	void iemMemFetchDataD80Jmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5740	void iemMemFetchDataU128Jmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5741	void iemMemFetchDataU128NoAcJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5742	void iemMemFetchDataU128AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5743	void iemMemFetchDataU256NoAcJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5744	void iemMemFetchDataU256AlignedAvxJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5745	# endif
5746	void iemMemFetchDataU256Jmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5747	#endif
5748
5749	VBOXSTRICTRC iemMemFetchSysU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5750	VBOXSTRICTRC iemMemFetchSysU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5751	VBOXSTRICTRC iemMemFetchSysU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5752	VBOXSTRICTRC iemMemFetchSysU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5753	VBOXSTRICTRC iemMemFetchSelDesc(PVMCPUCC pVCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt) RT_NOEXCEPT;
5754
5755	VBOXSTRICTRC iemMemStoreDataU8(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) RT_NOEXCEPT;
5756	VBOXSTRICTRC iemMemStoreDataU16(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) RT_NOEXCEPT;
5757	VBOXSTRICTRC iemMemStoreDataU32(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) RT_NOEXCEPT;
5758	VBOXSTRICTRC iemMemStoreDataU64(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) RT_NOEXCEPT;
5759	VBOXSTRICTRC iemMemStoreDataU128(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
5760	VBOXSTRICTRC iemMemStoreDataU128NoAc(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
5761	VBOXSTRICTRC iemMemStoreDataU128AlignedSse(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
5762	VBOXSTRICTRC iemMemStoreDataU256(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
5763	VBOXSTRICTRC iemMemStoreDataU256NoAc(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
5764	VBOXSTRICTRC iemMemStoreDataU256AlignedAvx(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
5765	VBOXSTRICTRC iemMemStoreDataXdtr(PVMCPUCC pVCpu, uint16_t cbLimit, RTGCPTR GCPtrBase, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5766	#ifdef IEM_WITH_SETJMP
5767	void iemMemStoreDataU8SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
5768	void iemMemStoreDataU16SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
5769	void iemMemStoreDataU32SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
5770	void iemMemStoreDataU64SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
5771	void iemMemStoreDataU128SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5772	void iemMemStoreDataU128NoAcSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT128U pu128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5773	void iemMemStoreDataU128AlignedSseSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT128U pu128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5774	void iemMemStoreDataU256SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5775	void iemMemStoreDataU256NoAcSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5776	void iemMemStoreDataU256AlignedAvxSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5777	void iemMemStoreDataR80SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTFLOAT80U pr80Value) IEM_NOEXCEPT_MAY_LONGJMP;
5778	void iemMemStoreDataD80SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTPBCD80U pd80Value) IEM_NOEXCEPT_MAY_LONGJMP;
5779	#if 0
5780	void iemMemStoreDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
5781	void iemMemStoreDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
5782	void iemMemStoreDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
5783	void iemMemStoreDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
5784	void iemMemStoreDataU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5785	void iemMemStoreDataNoAcU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5786	void iemMemStoreDataU256NoAcJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5787	void iemMemStoreDataU256AlignedAvxJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5788	#endif
5789	void iemMemStoreDataU128AlignedSseJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5790	void iemMemStoreDataU256Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5791	#endif
5792
5793	#ifdef IEM_WITH_SETJMP
5794	uint8_t iemMemMapDataU8RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5795	uint8_t iemMemMapDataU8AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5796	uint8_t iemMemMapDataU8WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5797	uint8_t const iemMemMapDataU8RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5798	uint16_t iemMemMapDataU16RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5799	uint16_t iemMemMapDataU16AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5800	uint16_t iemMemMapDataU16WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5801	uint16_t const iemMemMapDataU16RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5802	uint32_t iemMemMapDataU32RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5803	uint32_t iemMemMapDataU32AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5804	uint32_t iemMemMapDataU32WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5805	uint32_t const iemMemMapDataU32RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5806	uint64_t iemMemMapDataU64RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5807	uint64_t iemMemMapDataU64AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5808	uint64_t iemMemMapDataU64WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5809	uint64_t const iemMemMapDataU64RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5810	PRTFLOAT80U iemMemMapDataR80RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5811	PRTFLOAT80U iemMemMapDataR80WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5812	PCRTFLOAT80U iemMemMapDataR80RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5813	PRTPBCD80U iemMemMapDataD80RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5814	PRTPBCD80U iemMemMapDataD80WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5815	PCRTPBCD80U iemMemMapDataD80RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5816	PRTUINT128U iemMemMapDataU128RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5817	PRTUINT128U iemMemMapDataU128AtSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5818	PRTUINT128U iemMemMapDataU128WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5819	PCRTUINT128U iemMemMapDataU128RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5820
5821	void iemMemCommitAndUnmapJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5822	void iemMemCommitAndUnmapRwSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5823	void iemMemCommitAndUnmapAtSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5824	void iemMemCommitAndUnmapWoSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5825	void iemMemCommitAndUnmapRoSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5826	void iemMemRollbackAndUnmapWoSafe(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5827	#endif
5828
5829	VBOXSTRICTRC iemMemStackPushBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
5830	void *ppvMem, uint8_t pbUnmapInfo, uint64_t *puNewRsp) RT_NOEXCEPT;
5831	VBOXSTRICTRC iemMemStackPushCommitSpecial(PVMCPUCC pVCpu, uint8_t bUnmapInfo, uint64_t uNewRsp) RT_NOEXCEPT;
5832	VBOXSTRICTRC iemMemStackPushU16(PVMCPUCC pVCpu, uint16_t u16Value) RT_NOEXCEPT;
5833	VBOXSTRICTRC iemMemStackPushU32(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
5834	VBOXSTRICTRC iemMemStackPushU64(PVMCPUCC pVCpu, uint64_t u64Value) RT_NOEXCEPT;
5835	VBOXSTRICTRC iemMemStackPushU16Ex(PVMCPUCC pVCpu, uint16_t u16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5836	VBOXSTRICTRC iemMemStackPushU32Ex(PVMCPUCC pVCpu, uint32_t u32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5837	VBOXSTRICTRC iemMemStackPushU64Ex(PVMCPUCC pVCpu, uint64_t u64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5838	VBOXSTRICTRC iemMemStackPushU32SReg(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
5839	VBOXSTRICTRC iemMemStackPopBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
5840	void const *ppvMem, uint8_t pbUnmapInfo, uint64_t *puNewRsp) RT_NOEXCEPT;
5841	VBOXSTRICTRC iemMemStackPopContinueSpecial(PVMCPUCC pVCpu, size_t off, size_t cbMem,
5842	void const *ppvMem, uint8_t pbUnmapInfo, uint64_t uCurNewRsp) RT_NOEXCEPT;
5843	VBOXSTRICTRC iemMemStackPopDoneSpecial(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5844	VBOXSTRICTRC iemMemStackPopU16(PVMCPUCC pVCpu, uint16_t *pu16Value) RT_NOEXCEPT;
5845	VBOXSTRICTRC iemMemStackPopU32(PVMCPUCC pVCpu, uint32_t *pu32Value) RT_NOEXCEPT;
5846	VBOXSTRICTRC iemMemStackPopU64(PVMCPUCC pVCpu, uint64_t *pu64Value) RT_NOEXCEPT;
5847	VBOXSTRICTRC iemMemStackPopU16Ex(PVMCPUCC pVCpu, uint16_t *pu16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5848	VBOXSTRICTRC iemMemStackPopU32Ex(PVMCPUCC pVCpu, uint32_t *pu32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5849	VBOXSTRICTRC iemMemStackPopU64Ex(PVMCPUCC pVCpu, uint64_t *pu64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5850
5851	#ifdef IEM_WITH_SETJMP
5852	void iemMemStackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5853	void iemMemStackPushU32SafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5854	void iemMemStackPushU32SRegSafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5855	void iemMemStackPushU64SafeJmp(PVMCPUCC pVCpu, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5856	void iemMemStackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5857	void iemMemStackPopGRegU32SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5858	void iemMemStackPopGRegU64SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5859
5860	void iemMemFlat32StackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5861	void iemMemFlat32StackPushU32SafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5862	void iemMemFlat32StackPushU32SRegSafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5863	void iemMemFlat32StackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5864	void iemMemFlat32StackPopGRegU32SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5865
5866	void iemMemFlat64StackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5867	void iemMemFlat64StackPushU64SafeJmp(PVMCPUCC pVCpu, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5868	void iemMemFlat64StackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5869	void iemMemFlat64StackPopGRegU64SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5870
5871	void iemMemStoreStackU16SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5872	void iemMemStoreStackU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5873	void iemMemStoreStackU32SRegSafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5874	void iemMemStoreStackU64SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5875
5876	uint16_t iemMemFetchStackU16SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5877	uint32_t iemMemFetchStackU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5878	uint64_t iemMemFetchStackU64SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5879
5880	#endif
5881
5882	/** @} */
5883
5884	/** @name IEMAllCImpl.cpp
5885	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/'
5886	* @{ */
5887	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem16, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5888	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem32, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5889	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem64, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5890	IEM_CIMPL_PROTO_0(iemCImpl_popa_16);
5891	IEM_CIMPL_PROTO_0(iemCImpl_popa_32);
5892	IEM_CIMPL_PROTO_0(iemCImpl_pusha_16);
5893	IEM_CIMPL_PROTO_0(iemCImpl_pusha_32);
5894	IEM_CIMPL_PROTO_1(iemCImpl_pushf, IEMMODE, enmEffOpSize);
5895	IEM_CIMPL_PROTO_1(iemCImpl_popf, IEMMODE, enmEffOpSize);
5896	IEM_CIMPL_PROTO_3(iemCImpl_FarJmp, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
5897	IEM_CIMPL_PROTO_3(iemCImpl_callf, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
5898	typedef IEM_CIMPL_DECL_TYPE_3(FNIEMCIMPLFARBRANCH, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
5899	typedef FNIEMCIMPLFARBRANCH *PFNIEMCIMPLFARBRANCH;
5900	IEM_CIMPL_PROTO_2(iemCImpl_retf, IEMMODE, enmEffOpSize, uint16_t, cbPop);
5901	IEM_CIMPL_PROTO_3(iemCImpl_enter, IEMMODE, enmEffOpSize, uint16_t, cbFrame, uint8_t, cParameters);
5902	IEM_CIMPL_PROTO_1(iemCImpl_leave, IEMMODE, enmEffOpSize);
5903	IEM_CIMPL_PROTO_2(iemCImpl_int, uint8_t, u8Int, IEMINT, enmInt);
5904	IEM_CIMPL_PROTO_1(iemCImpl_iret_real_v8086, IEMMODE, enmEffOpSize);
5905	IEM_CIMPL_PROTO_4(iemCImpl_iret_prot_v8086, uint32_t, uNewEip, uint16_t, uNewCs, uint32_t, uNewFlags, uint64_t, uNewRsp);
5906	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot_NestedTask, IEMMODE, enmEffOpSize);
5907	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot, IEMMODE, enmEffOpSize);
5908	IEM_CIMPL_PROTO_1(iemCImpl_iret_64bit, IEMMODE, enmEffOpSize);
5909	IEM_CIMPL_PROTO_1(iemCImpl_iret, IEMMODE, enmEffOpSize);
5910	IEM_CIMPL_PROTO_0(iemCImpl_loadall286);
5911	IEM_CIMPL_PROTO_0(iemCImpl_syscall);
5912	IEM_CIMPL_PROTO_1(iemCImpl_sysret, IEMMODE, enmEffOpSize);
5913	IEM_CIMPL_PROTO_0(iemCImpl_sysenter);
5914	IEM_CIMPL_PROTO_1(iemCImpl_sysexit, IEMMODE, enmEffOpSize);
5915	IEM_CIMPL_PROTO_2(iemCImpl_LoadSReg, uint8_t, iSegReg, uint16_t, uSel);
5916	IEM_CIMPL_PROTO_2(iemCImpl_load_SReg, uint8_t, iSegReg, uint16_t, uSel);
5917	IEM_CIMPL_PROTO_2(iemCImpl_pop_Sreg, uint8_t, iSegReg, IEMMODE, enmEffOpSize);
5918	IEM_CIMPL_PROTO_5(iemCImpl_load_SReg_Greg, uint16_t, uSel, uint64_t, offSeg, uint8_t, iSegReg, uint8_t, iGReg, IEMMODE, enmEffOpSize);
5919	IEM_CIMPL_PROTO_2(iemCImpl_VerX, uint16_t, uSel, bool, fWrite);
5920	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u64, uint64_t *, pu64Dst, uint16_t, uSel, bool, fIsLar);
5921	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u16, uint16_t *, pu16Dst, uint16_t, uSel, bool, fIsLar);
5922	IEM_CIMPL_PROTO_3(iemCImpl_lgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
5923	IEM_CIMPL_PROTO_2(iemCImpl_sgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5924	IEM_CIMPL_PROTO_3(iemCImpl_lidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
5925	IEM_CIMPL_PROTO_2(iemCImpl_sidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5926	IEM_CIMPL_PROTO_1(iemCImpl_lldt, uint16_t, uNewLdt);
5927	IEM_CIMPL_PROTO_2(iemCImpl_sldt_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
5928	IEM_CIMPL_PROTO_2(iemCImpl_sldt_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5929	IEM_CIMPL_PROTO_1(iemCImpl_ltr, uint16_t, uNewTr);
5930	IEM_CIMPL_PROTO_2(iemCImpl_str_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
5931	IEM_CIMPL_PROTO_2(iemCImpl_str_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5932	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Cd, uint8_t, iGReg, uint8_t, iCrReg);
5933	IEM_CIMPL_PROTO_2(iemCImpl_smsw_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
5934	IEM_CIMPL_PROTO_2(iemCImpl_smsw_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5935	IEM_CIMPL_PROTO_4(iemCImpl_load_CrX, uint8_t, iCrReg, uint64_t, uNewCrX, IEMACCESSCRX, enmAccessCrX, uint8_t, iGReg);
5936	IEM_CIMPL_PROTO_2(iemCImpl_mov_Cd_Rd, uint8_t, iCrReg, uint8_t, iGReg);
5937	IEM_CIMPL_PROTO_2(iemCImpl_lmsw, uint16_t, u16NewMsw, RTGCPTR, GCPtrEffDst);
5938	IEM_CIMPL_PROTO_0(iemCImpl_clts);
5939	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Dd, uint8_t, iGReg, uint8_t, iDrReg);
5940	IEM_CIMPL_PROTO_2(iemCImpl_mov_Dd_Rd, uint8_t, iDrReg, uint8_t, iGReg);
5941	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Td, uint8_t, iGReg, uint8_t, iTrReg);
5942	IEM_CIMPL_PROTO_2(iemCImpl_mov_Td_Rd, uint8_t, iTrReg, uint8_t, iGReg);
5943	IEM_CIMPL_PROTO_1(iemCImpl_invlpg, RTGCPTR, GCPtrPage);
5944	IEM_CIMPL_PROTO_3(iemCImpl_invpcid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvpcidDesc, uint64_t, uInvpcidType);
5945	IEM_CIMPL_PROTO_0(iemCImpl_invd);
5946	IEM_CIMPL_PROTO_0(iemCImpl_wbinvd);
5947	IEM_CIMPL_PROTO_0(iemCImpl_rsm);
5948	IEM_CIMPL_PROTO_0(iemCImpl_rdtsc);
5949	IEM_CIMPL_PROTO_0(iemCImpl_rdtscp);
5950	IEM_CIMPL_PROTO_0(iemCImpl_rdpmc);
5951	IEM_CIMPL_PROTO_0(iemCImpl_rdmsr);
5952	IEM_CIMPL_PROTO_0(iemCImpl_wrmsr);
5953	IEM_CIMPL_PROTO_3(iemCImpl_in, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
5954	IEM_CIMPL_PROTO_2(iemCImpl_in_eAX_DX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
5955	IEM_CIMPL_PROTO_3(iemCImpl_out, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
5956	IEM_CIMPL_PROTO_2(iemCImpl_out_DX_eAX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
5957	IEM_CIMPL_PROTO_0(iemCImpl_cli);
5958	IEM_CIMPL_PROTO_0(iemCImpl_sti);
5959	IEM_CIMPL_PROTO_0(iemCImpl_hlt);
5960	IEM_CIMPL_PROTO_1(iemCImpl_monitor, uint8_t, iEffSeg);
5961	IEM_CIMPL_PROTO_0(iemCImpl_mwait);
5962	IEM_CIMPL_PROTO_0(iemCImpl_swapgs);
5963	IEM_CIMPL_PROTO_0(iemCImpl_cpuid);
5964	IEM_CIMPL_PROTO_1(iemCImpl_aad, uint8_t, bImm);
5965	IEM_CIMPL_PROTO_1(iemCImpl_aam, uint8_t, bImm);
5966	IEM_CIMPL_PROTO_0(iemCImpl_daa);
5967	IEM_CIMPL_PROTO_0(iemCImpl_das);
5968	IEM_CIMPL_PROTO_0(iemCImpl_aaa);
5969	IEM_CIMPL_PROTO_0(iemCImpl_aas);
5970	IEM_CIMPL_PROTO_3(iemCImpl_bound_16, int16_t, idxArray, int16_t, idxLowerBound, int16_t, idxUpperBound);
5971	IEM_CIMPL_PROTO_3(iemCImpl_bound_32, int32_t, idxArray, int32_t, idxLowerBound, int32_t, idxUpperBound);
5972	IEM_CIMPL_PROTO_0(iemCImpl_xgetbv);
5973	IEM_CIMPL_PROTO_0(iemCImpl_xsetbv);
5974	IEM_CIMPL_PROTO_5(iemCImpl_cmpxchg16b_fallback_rendezvous, PRTUINT128U, pu128Dst, PRTUINT128U, pu128RaxRdx,
5975	PRTUINT128U, pu128RbxRcx, uint32_t *, pEFlags, uint8_t, bUnmapInfo);
5976	IEM_CIMPL_PROTO_2(iemCImpl_clflush_clflushopt, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5977	IEM_CIMPL_PROTO_1(iemCImpl_finit, bool, fCheckXcpts);
5978	IEM_CIMPL_PROTO_3(iemCImpl_fxsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5979	IEM_CIMPL_PROTO_3(iemCImpl_fxrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5980	IEM_CIMPL_PROTO_3(iemCImpl_xsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5981	IEM_CIMPL_PROTO_3(iemCImpl_xrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5982	IEM_CIMPL_PROTO_2(iemCImpl_stmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5983	IEM_CIMPL_PROTO_2(iemCImpl_vstmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5984	IEM_CIMPL_PROTO_2(iemCImpl_ldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5985	IEM_CIMPL_PROTO_3(iemCImpl_fnstenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5986	IEM_CIMPL_PROTO_3(iemCImpl_fnsave, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5987	IEM_CIMPL_PROTO_3(iemCImpl_fldenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
5988	IEM_CIMPL_PROTO_3(iemCImpl_frstor, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
5989	IEM_CIMPL_PROTO_1(iemCImpl_fldcw, uint16_t, u16Fcw);
5990	IEM_CIMPL_PROTO_2(iemCImpl_fxch_underflow, uint8_t, iStReg, uint16_t, uFpuOpcode);
5991	IEM_CIMPL_PROTO_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, bool, fUCmp, uint32_t, uPopAndFpuOpcode);
5992	IEM_CIMPL_PROTO_2(iemCImpl_rdseed, uint8_t, iReg, IEMMODE, enmEffOpSize);
5993	IEM_CIMPL_PROTO_2(iemCImpl_rdrand, uint8_t, iReg, IEMMODE, enmEffOpSize);
5994	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovps_load_u128, uint8_t, iXRegDst, uint8_t, iXRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
5995	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovps_load_u256, uint8_t, iYRegDst, uint8_t, iYRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
5996	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovps_store_u128, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iXRegMsk, uint8_t, iXRegSrc);
5997	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovps_store_u256, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iYRegMsk, uint8_t, iYRegSrc);
5998	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovd_load_u128, uint8_t, iXRegDst, uint8_t, iXRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
5999	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovd_load_u256, uint8_t, iYRegDst, uint8_t, iYRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6000	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovd_store_u128, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iXRegMsk, uint8_t, iXRegSrc);
6001	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovd_store_u256, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iYRegMsk, uint8_t, iYRegSrc);
6002	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovpd_load_u128, uint8_t, iXRegDst, uint8_t, iXRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6003	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovpd_load_u256, uint8_t, iYRegDst, uint8_t, iYRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6004	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovpd_store_u128, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iXRegMsk, uint8_t, iXRegSrc);
6005	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovpd_store_u256, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iYRegMsk, uint8_t, iYRegSrc);
6006	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovq_load_u128, uint8_t, iXRegDst, uint8_t, iXRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6007	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovq_load_u256, uint8_t, iYRegDst, uint8_t, iYRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6008	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovq_store_u128, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iXRegMsk, uint8_t, iXRegSrc);
6009	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovq_store_u256, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iYRegMsk, uint8_t, iYRegSrc);
6010
6011	/** @} */
6012
6013	/** @name IEMAllCImplStrInstr.cpp.h
6014	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/' -e 's/RT_CONCAT4(//' \
6015	* -e 's/,ADDR_SIZE)/64/g' -e 's/,OP_SIZE,/64/g' -e 's/,OP_rAX,/rax/g' IEMAllCImplStrInstr.cpp.h
6016	* @{ */
6017	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr16, uint8_t, iEffSeg);
6018	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr16, uint8_t, iEffSeg);
6019	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m16);
6020	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m16);
6021	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr16, uint8_t, iEffSeg);
6022	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m16);
6023	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m16, int8_t, iEffSeg);
6024	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr16, bool, fIoChecked);
6025	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr16, bool, fIoChecked);
6026	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6027	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6028
6029	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr16, uint8_t, iEffSeg);
6030	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr16, uint8_t, iEffSeg);
6031	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m16);
6032	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m16);
6033	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr16, uint8_t, iEffSeg);
6034	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m16);
6035	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m16, int8_t, iEffSeg);
6036	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr16, bool, fIoChecked);
6037	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr16, bool, fIoChecked);
6038	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6039	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6040
6041	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr16, uint8_t, iEffSeg);
6042	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr16, uint8_t, iEffSeg);
6043	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m16);
6044	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m16);
6045	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr16, uint8_t, iEffSeg);
6046	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m16);
6047	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m16, int8_t, iEffSeg);
6048	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr16, bool, fIoChecked);
6049	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr16, bool, fIoChecked);
6050	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6051	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6052
6053
6054	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr32, uint8_t, iEffSeg);
6055	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr32, uint8_t, iEffSeg);
6056	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m32);
6057	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m32);
6058	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr32, uint8_t, iEffSeg);
6059	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m32);
6060	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m32, int8_t, iEffSeg);
6061	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr32, bool, fIoChecked);
6062	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr32, bool, fIoChecked);
6063	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6064	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6065
6066	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr32, uint8_t, iEffSeg);
6067	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr32, uint8_t, iEffSeg);
6068	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m32);
6069	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m32);
6070	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr32, uint8_t, iEffSeg);
6071	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m32);
6072	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m32, int8_t, iEffSeg);
6073	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr32, bool, fIoChecked);
6074	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr32, bool, fIoChecked);
6075	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6076	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6077
6078	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr32, uint8_t, iEffSeg);
6079	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr32, uint8_t, iEffSeg);
6080	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m32);
6081	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m32);
6082	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr32, uint8_t, iEffSeg);
6083	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m32);
6084	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m32, int8_t, iEffSeg);
6085	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr32, bool, fIoChecked);
6086	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr32, bool, fIoChecked);
6087	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6088	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6089
6090	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr32, uint8_t, iEffSeg);
6091	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr32, uint8_t, iEffSeg);
6092	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m32);
6093	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m32);
6094	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr32, uint8_t, iEffSeg);
6095	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m32);
6096	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m32, int8_t, iEffSeg);
6097	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr32, bool, fIoChecked);
6098	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr32, bool, fIoChecked);
6099	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6100	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6101
6102
6103	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr64, uint8_t, iEffSeg);
6104	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr64, uint8_t, iEffSeg);
6105	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m64);
6106	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m64);
6107	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr64, uint8_t, iEffSeg);
6108	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m64);
6109	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m64, int8_t, iEffSeg);
6110	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr64, bool, fIoChecked);
6111	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr64, bool, fIoChecked);
6112	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6113	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6114
6115	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr64, uint8_t, iEffSeg);
6116	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr64, uint8_t, iEffSeg);
6117	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m64);
6118	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m64);
6119	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr64, uint8_t, iEffSeg);
6120	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m64);
6121	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m64, int8_t, iEffSeg);
6122	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr64, bool, fIoChecked);
6123	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr64, bool, fIoChecked);
6124	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6125	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6126
6127	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr64, uint8_t, iEffSeg);
6128	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr64, uint8_t, iEffSeg);
6129	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m64);
6130	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m64);
6131	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr64, uint8_t, iEffSeg);
6132	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m64);
6133	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m64, int8_t, iEffSeg);
6134	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr64, bool, fIoChecked);
6135	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr64, bool, fIoChecked);
6136	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6137	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6138
6139	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr64, uint8_t, iEffSeg);
6140	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr64, uint8_t, iEffSeg);
6141	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m64);
6142	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m64);
6143	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr64, uint8_t, iEffSeg);
6144	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m64);
6145	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m64, int8_t, iEffSeg);
6146	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr64, bool, fIoChecked);
6147	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr64, bool, fIoChecked);
6148	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6149	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6150	/** @} */
6151
6152	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
6153	VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT;
6154	VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT;
6155	VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT;
6156	VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT;
6157	VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT;
6158	VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
6159	VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALKFAST pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT;
6160	VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT;
6161	VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT;
6162	VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
6163	bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT;
6164	VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
6165	bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT;
6166	VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6167	VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6168	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6169	VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6170	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6171	VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6172	VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT;
6173	VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
6174	RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT;
6175	VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT;
6176	VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT;
6177	VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT;
6178	uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT;
6179	void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT;
6180	VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
6181	uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT;
6182	bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT;
6183	IEM_CIMPL_PROTO_0(iemCImpl_vmxoff);
6184	IEM_CIMPL_PROTO_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon);
6185	IEM_CIMPL_PROTO_0(iemCImpl_vmlaunch);
6186	IEM_CIMPL_PROTO_0(iemCImpl_vmresume);
6187	IEM_CIMPL_PROTO_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
6188	IEM_CIMPL_PROTO_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
6189	IEM_CIMPL_PROTO_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
6190	IEM_CIMPL_PROTO_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField);
6191	IEM_CIMPL_PROTO_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField);
6192	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField);
6193	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg32, uint64_t *, pu32Dst, uint32_t, u32VmcsField);
6194	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField);
6195	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField);
6196	IEM_CIMPL_PROTO_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType);
6197	IEM_CIMPL_PROTO_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType);
6198	IEM_CIMPL_PROTO_0(iemCImpl_vmx_pause);
6199	#endif
6200
6201	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
6202	VBOXSTRICTRC iemSvmVmexit(PVMCPUCC pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2) RT_NOEXCEPT;
6203	VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr, uint64_t uCr2) RT_NOEXCEPT;
6204	VBOXSTRICTRC iemSvmHandleIOIntercept(PVMCPUCC pVCpu, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
6205	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, uint8_t cbInstr) RT_NOEXCEPT;
6206	VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPUCC pVCpu, uint32_t idMsr, bool fWrite, uint8_t cbInstr) RT_NOEXCEPT;
6207	IEM_CIMPL_PROTO_0(iemCImpl_vmrun);
6208	IEM_CIMPL_PROTO_0(iemCImpl_vmload);
6209	IEM_CIMPL_PROTO_0(iemCImpl_vmsave);
6210	IEM_CIMPL_PROTO_0(iemCImpl_clgi);
6211	IEM_CIMPL_PROTO_0(iemCImpl_stgi);
6212	IEM_CIMPL_PROTO_0(iemCImpl_invlpga);
6213	IEM_CIMPL_PROTO_0(iemCImpl_skinit);
6214	IEM_CIMPL_PROTO_0(iemCImpl_svm_pause);
6215	#endif
6216
6217	IEM_CIMPL_PROTO_0(iemCImpl_vmcall); /* vmx */
6218	IEM_CIMPL_PROTO_0(iemCImpl_vmmcall); /* svm */
6219	IEM_CIMPL_PROTO_1(iemCImpl_Hypercall, uint16_t, uDisOpcode); /* both */
6220
6221	extern const PFNIEMOP g_apfnIemInterpretOnlyOneByteMap[256];
6222	extern const PFNIEMOP g_apfnIemInterpretOnlyTwoByteMap[1024];
6223	extern const PFNIEMOP g_apfnIemInterpretOnlyThreeByte0f3a[1024];
6224	extern const PFNIEMOP g_apfnIemInterpretOnlyThreeByte0f38[1024];
6225	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap1[1024];
6226	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap2[1024];
6227	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap3[1024];
6228
6229	/*
6230	* Recompiler related stuff.
6231	*/
6232	extern const PFNIEMOP g_apfnIemThreadedRecompilerOneByteMap[256];
6233	extern const PFNIEMOP g_apfnIemThreadedRecompilerTwoByteMap[1024];
6234	extern const PFNIEMOP g_apfnIemThreadedRecompilerThreeByte0f3a[1024];
6235	extern const PFNIEMOP g_apfnIemThreadedRecompilerThreeByte0f38[1024];
6236	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap1[1024];
6237	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap2[1024];
6238	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap3[1024];
6239
6240	DECLCALLBACK(int) iemTbInit(PVMCC pVM, uint32_t cInitialTbs, uint32_t cMaxTbs,
6241	uint64_t cbInitialExec, uint64_t cbMaxExec, uint32_t cbChunkExec);
6242	void iemThreadedTbObsolete(PVMCPUCC pVCpu, PIEMTB pTb, bool fSafeToFree);
6243	DECLHIDDEN(void) iemTbAllocatorFree(PVMCPUCC pVCpu, PIEMTB pTb);
6244	void iemTbAllocatorProcessDelayedFrees(PVMCPUCC pVCpu, PIEMTBALLOCATOR pTbAllocator);
6245	void iemTbAllocatorFreeupNativeSpace(PVMCPUCC pVCpu, uint32_t cNeededInstrs);
6246	DECLHIDDEN(const char ) iemTbFlagsToString(uint32_t fFlags, char pszBuf, size_t cbBuf) RT_NOEXCEPT;
6247	DECLHIDDEN(void) iemThreadedDisassembleTb(PCIEMTB pTb, PCDBGFINFOHLP pHlp) RT_NOEXCEPT;
6248
6249
6250	/** @todo FNIEMTHREADEDFUNC and friends may need more work... */
6251	#if defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
6252	typedef VBOXSTRICTRC /__attribute__((__nothrow__))/ FNIEMTHREADEDFUNC(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
6253	typedef FNIEMTHREADEDFUNC *PFNIEMTHREADEDFUNC;
6254	# define IEM_DECL_IEMTHREADEDFUNC_DEF(a_Name) \
6255	VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2)
6256	# define IEM_DECL_IEMTHREADEDFUNC_PROTO(a_Name) \
6257	VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2)
6258
6259	#else
6260	typedef VBOXSTRICTRC (FNIEMTHREADEDFUNC)(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
6261	typedef FNIEMTHREADEDFUNC *PFNIEMTHREADEDFUNC;
6262	# define IEM_DECL_IEMTHREADEDFUNC_DEF(a_Name) \
6263	VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2) IEM_NOEXCEPT_MAY_LONGJMP
6264	# define IEM_DECL_IEMTHREADEDFUNC_PROTO(a_Name) \
6265	VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2) IEM_NOEXCEPT_MAY_LONGJMP
6266	#endif
6267
6268
6269	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_Nop);
6270	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_LogCpuState);
6271
6272	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_DeferToCImpl0);
6273
6274	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckIrq);
6275	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckMode);
6276	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckHwInstrBps);
6277	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLim);
6278
6279	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodes);
6280	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodes);
6281	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesConsiderCsLim);
6282
6283	/* Branching: */
6284	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndPcAndOpcodes);
6285	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckPcAndOpcodes);
6286	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckPcAndOpcodesConsiderCsLim);
6287
6288	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesLoadingTlb);
6289	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesLoadingTlb);
6290	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesLoadingTlbConsiderCsLim);
6291
6292	/* Natural page crossing: */
6293	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesAcrossPageLoadingTlb);
6294	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesAcrossPageLoadingTlb);
6295	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesAcrossPageLoadingTlbConsiderCsLim);
6296
6297	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesOnNextPageLoadingTlb);
6298	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNextPageLoadingTlb);
6299	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNextPageLoadingTlbConsiderCsLim);
6300
6301	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesOnNewPageLoadingTlb);
6302	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNewPageLoadingTlb);
6303	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNewPageLoadingTlbConsiderCsLim);
6304
6305	bool iemThreadedCompileEmitIrqCheckBefore(PVMCPUCC pVCpu, PIEMTB pTb);
6306	bool iemThreadedCompileBeginEmitCallsComplications(PVMCPUCC pVCpu, PIEMTB pTb);
6307
6308	/* Native recompiler public bits: */
6309	DECLHIDDEN(PIEMTB) iemNativeRecompile(PVMCPUCC pVCpu, PIEMTB pTb) RT_NOEXCEPT;
6310	DECLHIDDEN(void) iemNativeDisassembleTb(PCIEMTB pTb, PCDBGFINFOHLP pHlp) RT_NOEXCEPT;
6311	int iemExecMemAllocatorInit(PVMCPU pVCpu, uint64_t cbMax, uint64_t cbInitial, uint32_t cbChunk) RT_NOEXCEPT;
6312	DECLHIDDEN(void ) iemExecMemAllocatorAlloc(PVMCPU pVCpu, uint32_t cbReq, PIEMTB pTb, void *ppvExec) RT_NOEXCEPT;
6313	DECLHIDDEN(void) iemExecMemAllocatorReadyForUse(PVMCPUCC pVCpu, void *pv, size_t cb) RT_NOEXCEPT;
6314	void iemExecMemAllocatorFree(PVMCPU pVCpu, void *pv, size_t cb) RT_NOEXCEPT;
6315	DECLASM(DECL_NO_RETURN(void)) iemNativeTbLongJmp(void *pvFramePointer, int rc) RT_NOEXCEPT;
6316
6317	#endif /* !RT_IN_ASSEMBLER - ASM-NOINC-END */
6318
6319
6320	/** @} */
6321
6322	RT_C_DECLS_END
6323
6324	/* ASM-INC: %include "IEMInternalStruct.mac" */
6325
6326	#endif /* !VMM_INCLUDED_SRC_include_IEMInternal_h */
6327

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source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h@ 104984

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