IEMInternal.h@ 105076

Last change on this file since 105076 was 105076, checked in by vboxsync, 5 months ago
VMM/IEM: Increased the TLB size from 256 to 1024 entries. bugref:10687
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 328.1 KB

Line
1	/* $Id: IEMInternal.h 105076 2024-06-28 18:35:41Z vboxsync $ */
2	/** @file
3	* IEM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2011-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_IEMInternal_h
29	#define VMM_INCLUDED_SRC_include_IEMInternal_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#ifndef RT_IN_ASSEMBLER
35	# include <VBox/vmm/cpum.h>
36	# include <VBox/vmm/iem.h>
37	# include <VBox/vmm/pgm.h>
38	# include <VBox/vmm/stam.h>
39	# include <VBox/param.h>
40
41	# include <iprt/setjmp-without-sigmask.h>
42	# include <iprt/list.h>
43	#endif /* !RT_IN_ASSEMBLER */
44
45
46	RT_C_DECLS_BEGIN
47
48
49	/** @defgroup grp_iem_int Internals
50	* @ingroup grp_iem
51	* @internal
52	* @{
53	*/
54
55	/* Make doxygen happy w/o overcomplicating the #if checks. */
56	#ifdef DOXYGEN_RUNNING
57	# define IEM_WITH_THROW_CATCH
58	# define VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
59	#endif
60
61	/** For expanding symbol in slickedit and other products tagging and
62	* crossreferencing IEM symbols. */
63	#ifndef IEM_STATIC
64	# define IEM_STATIC static
65	#endif
66
67	/** @def IEM_WITH_SETJMP
68	* Enables alternative status code handling using setjmps.
69	*
70	* This adds a bit of expense via the setjmp() call since it saves all the
71	* non-volatile registers. However, it eliminates return code checks and allows
72	* for more optimal return value passing (return regs instead of stack buffer).
73	*/
74	#if defined(DOXYGEN_RUNNING) \|\| defined(RT_OS_WINDOWS) \|\| 1
75	# define IEM_WITH_SETJMP
76	#endif
77
78	/** @def IEM_WITH_THROW_CATCH
79	* Enables using C++ throw/catch as an alternative to setjmp/longjmp in user
80	* mode code when IEM_WITH_SETJMP is in effect.
81	*
82	* With GCC 11.3.1 and code TLB on linux, using throw/catch instead of
83	* setjmp/long resulted in bs2-test-1 running 3.00% faster and all but on test
84	* result value improving by more than 1%. (Best out of three.)
85	*
86	* With Visual C++ 2019 and code TLB on windows, using throw/catch instead of
87	* setjmp/long resulted in bs2-test-1 running 3.68% faster and all but some of
88	* the MMIO and CPUID tests ran noticeably faster. Variation is greater than on
89	* Linux, but it should be quite a bit faster for normal code.
90	*/
91	#if defined(__cplusplus) && defined(IEM_WITH_SETJMP) && defined(IN_RING3) && (defined(__GNUC__) \|\| defined(_MSC_VER)) /* ASM-NOINC-START */
92	# define IEM_WITH_THROW_CATCH
93	#endif /ASM-NOINC-END/
94
95	/** @def IEMNATIVE_WITH_DELAYED_PC_UPDATING
96	* Enables the delayed PC updating optimization (see @bugref{10373}).
97	*/
98	#if defined(DOXYGEN_RUNNING) \|\| 1
99	# define IEMNATIVE_WITH_DELAYED_PC_UPDATING
100	#endif
101
102	/** Enables the SIMD register allocator @bugref{10614}. */
103	#if defined(DOXYGEN_RUNNING) \|\| 1
104	# define IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
105	#endif
106	/** Enables access to even callee saved registers. */
107	//# define IEMNATIVE_WITH_SIMD_REG_ACCESS_ALL_REGISTERS
108
109	#if defined(DOXYGEN_RUNNING) \|\| 1
110	/** @def IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
111	* Delay the writeback or dirty registers as long as possible. */
112	# define IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
113	#endif
114
115	/** @def IEM_WITH_TLB_STATISTICS
116	* Enables all TLB statistics. */
117	#if defined(VBOX_WITH_STATISTICS) \|\| defined(DOXYGEN_RUNNING)
118	# define IEM_WITH_TLB_STATISTICS
119	#endif
120
121	/** @def VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
122	* Enables a quicker alternative to throw/longjmp for IEM_DO_LONGJMP when
123	* executing native translation blocks.
124	*
125	* This exploits the fact that we save all non-volatile registers in the TB
126	* prologue and thus just need to do the same as the TB epilogue to get the
127	* effect of a longjmp/throw. Since MSC marks XMM6 thru XMM15 as
128	* non-volatile (and does something even more crazy for ARM), this probably
129	* won't work reliably on Windows. */
130	#ifdef RT_ARCH_ARM64
131	# ifndef RT_OS_WINDOWS
132	# define VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
133	# endif
134	#endif
135	/* ASM-NOINC-START */
136	#ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
137	# if !defined(IN_RING3) \
138	\|\| !defined(VBOX_WITH_IEM_RECOMPILER) \
139	\|\| !defined(VBOX_WITH_IEM_NATIVE_RECOMPILER)
140	# undef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
141	# elif defined(RT_OS_WINDOWS)
142	# pragma message("VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP is not safe to use on windows")
143	# endif
144	#endif
145
146
147	/** @def IEM_DO_LONGJMP
148	*
149	* Wrapper around longjmp / throw.
150	*
151	* @param a_pVCpu The CPU handle.
152	* @param a_rc The status code jump back with / throw.
153	*/
154	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
155	# ifdef IEM_WITH_THROW_CATCH
156	# ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
157	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) do { \
158	if ((a_pVCpu)->iem.s.pvTbFramePointerR3) \
159	iemNativeTbLongJmp((a_pVCpu)->iem.s.pvTbFramePointerR3, (a_rc)); \
160	throw int(a_rc); \
161	} while (0)
162	# else
163	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) throw int(a_rc)
164	# endif
165	# else
166	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) longjmp(*(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf), (a_rc))
167	# endif
168	#endif
169
170	/** For use with IEM function that may do a longjmp (when enabled).
171	*
172	* Visual C++ has trouble longjmp'ing from/over functions with the noexcept
173	* attribute. So, we indicate that function that may be part of a longjmp may
174	* throw "exceptions" and that the compiler should definitely not generate and
175	* std::terminate calling unwind code.
176	*
177	* Here is one example of this ending in std::terminate:
178	* @code{.txt}
179	00 00000041`cadfda10 00007ffc`5d5a1f9f ucrtbase!abort+0x4e
180	01 00000041`cadfda40 00007ffc`57af229a ucrtbase!terminate+0x1f
181	02 00000041`cadfda70 00007ffb`eec91030 VCRUNTIME140!__std_terminate+0xa [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\ehhelpers.cpp @ 192]
182	03 00000041`cadfdaa0 00007ffb`eec92c6d VCRUNTIME140_1!_CallSettingFrame+0x20 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\handlers.asm @ 50]
183	04 00000041`cadfdad0 00007ffb`eec93ae5 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToState+0x241 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 1085]
184	05 00000041`cadfdc00 00007ffb`eec92258 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToEmptyState+0x2d [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 218]
185	06 00000041`cadfdc30 00007ffb`eec940e9 VCRUNTIME140_1!__InternalCxxFrameHandler<__FrameHandler4>+0x194 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 304]
186	07 00000041`cadfdcd0 00007ffc`5f9f249f VCRUNTIME140_1!__CxxFrameHandler4+0xa9 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 290]
187	08 00000041`cadfdd40 00007ffc`5f980939 ntdll!RtlpExecuteHandlerForUnwind+0xf
188	09 00000041`cadfdd70 00007ffc`5f9a0edd ntdll!RtlUnwindEx+0x339
189	0a 00000041`cadfe490 00007ffc`57aff976 ntdll!RtlUnwind+0xcd
190	0b 00000041`cadfea00 00007ffb`e1b5de01 VCRUNTIME140!__longjmp_internal+0xe6 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\longjmp.asm @ 140]
191	0c (Inline Function) --------`-------- VBoxVMM!iemOpcodeGetNextU8SlowJmp+0x95 [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 1155]
192	0d 00000041`cadfea50 00007ffb`e1b60f6b VBoxVMM!iemOpcodeGetNextU8Jmp+0xc1 [L:\vbox-intern\src\VBox\VMM\include\IEMInline.h @ 402]
193	0e 00000041`cadfea90 00007ffb`e1cc6201 VBoxVMM!IEMExecForExits+0xdb [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 10185]
194	0f 00000041`cadfec70 00007ffb`e1d0df8d VBoxVMM!EMHistoryExec+0x4f1 [L:\vbox-intern\src\VBox\VMM\VMMAll\EMAll.cpp @ 452]
195	10 00000041`cadfed60 00007ffb`e1d0d4c0 VBoxVMM!nemR3WinHandleExitCpuId+0x79d [L:\vbox-intern\src\VBox\VMM\VMMAll\NEMAllNativeTemplate-win.cpp.h @ 1829] @encode
196	@endcode
197	*
198	* @see https://developercommunity.visualstudio.com/t/fragile-behavior-of-longjmp-called-from-noexcept-f/1532859
199	*/
200	#if defined(IEM_WITH_SETJMP) && (defined(_MSC_VER) \|\| defined(IEM_WITH_THROW_CATCH))
201	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT_EX(false)
202	#else
203	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT
204	#endif
205	/* ASM-NOINC-END */
206
207	#define IEM_IMPLEMENTS_TASKSWITCH
208
209	/** @def IEM_WITH_3DNOW
210	* Includes the 3DNow decoding. */
211	#if !defined(IEM_WITH_3DNOW) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
212	# ifndef IEM_WITHOUT_3DNOW
213	# define IEM_WITH_3DNOW
214	# endif
215	#endif
216
217	/** @def IEM_WITH_THREE_0F_38
218	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
219	#if !defined(IEM_WITH_THREE_0F_38) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
220	# ifndef IEM_WITHOUT_THREE_0F_38
221	# define IEM_WITH_THREE_0F_38
222	# endif
223	#endif
224
225	/** @def IEM_WITH_THREE_0F_3A
226	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
227	#if !defined(IEM_WITH_THREE_0F_3A) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
228	# ifndef IEM_WITHOUT_THREE_0F_3A
229	# define IEM_WITH_THREE_0F_3A
230	# endif
231	#endif
232
233	/** @def IEM_WITH_VEX
234	* Includes the VEX decoding. */
235	#if !defined(IEM_WITH_VEX) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
236	# ifndef IEM_WITHOUT_VEX
237	# define IEM_WITH_VEX
238	# endif
239	#endif
240
241	/** @def IEM_CFG_TARGET_CPU
242	* The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
243	*
244	* By default we allow this to be configured by the user via the
245	* CPUM/GuestCpuName config string, but this comes at a slight cost during
246	* decoding. So, for applications of this code where there is no need to
247	* be dynamic wrt target CPU, just modify this define.
248	*/
249	#if !defined(IEM_CFG_TARGET_CPU) \|\| defined(DOXYGEN_RUNNING)
250	# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
251	#endif
252
253	//#define IEM_WITH_CODE_TLB // - work in progress
254	//#define IEM_WITH_DATA_TLB // - work in progress
255
256
257	/** @def IEM_USE_UNALIGNED_DATA_ACCESS
258	* Use unaligned accesses instead of elaborate byte assembly. */
259	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86) \|\| defined(DOXYGEN_RUNNING) /ASM-NOINC/
260	# define IEM_USE_UNALIGNED_DATA_ACCESS
261	#endif /ASM-NOINC/
262
263	//#define IEM_LOG_MEMORY_WRITES
264
265
266
267	#ifndef RT_IN_ASSEMBLER /* ASM-NOINC-START - the rest of the file */
268
269	# if !defined(IEM_WITHOUT_INSTRUCTION_STATS) && !defined(DOXYGEN_RUNNING)
270	/** Instruction statistics. */
271	typedef struct IEMINSTRSTATS
272	{
273	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
274	# include "IEMInstructionStatisticsTmpl.h"
275	# undef IEM_DO_INSTR_STAT
276	} IEMINSTRSTATS;
277	#else
278	struct IEMINSTRSTATS;
279	typedef struct IEMINSTRSTATS IEMINSTRSTATS;
280	#endif
281	/** Pointer to IEM instruction statistics. */
282	typedef IEMINSTRSTATS *PIEMINSTRSTATS;
283
284
285	/** @name IEMTARGETCPU_EFL_BEHAVIOR_XXX - IEMCPU::aidxTargetCpuEflFlavour
286	* @{ */
287	#define IEMTARGETCPU_EFL_BEHAVIOR_NATIVE 0 /*< Native x86 EFLAGS result; Intel EFLAGS when on non-x86 hosts. /
288	#define IEMTARGETCPU_EFL_BEHAVIOR_INTEL 1 /*< Intel EFLAGS result. /
289	#define IEMTARGETCPU_EFL_BEHAVIOR_AMD 2 /*< AMD EFLAGS result /
290	#define IEMTARGETCPU_EFL_BEHAVIOR_RESERVED 3 /*< Reserved/dummy entry slot that's the same as 0. /
291	#define IEMTARGETCPU_EFL_BEHAVIOR_MASK 3 /*< For masking the index before use. /
292	/** Selects the right variant from a_aArray.
293	* pVCpu is implicit in the caller context. */
294	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT(a_aArray) \
295	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[1] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
296	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for when no native worker can
297	* be used because the host CPU does not support the operation. */
298	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_NON_NATIVE(a_aArray) \
299	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
300	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for a two dimentional
301	* array paralleling IEMCPU::aidxTargetCpuEflFlavour and a single bit index
302	* into the two.
303	* @sa IEM_SELECT_NATIVE_OR_FALLBACK */
304	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
305	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
306	(a_aaArray[a_fNative][pVCpu->iem.s.aidxTargetCpuEflFlavour[a_fNative] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
307	#else
308	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
309	(a_aaArray[0][pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
310	#endif
311	/** @} */
312
313	/**
314	* Picks @a a_pfnNative or @a a_pfnFallback according to the host CPU feature
315	* indicator given by @a a_fCpumFeatureMember (CPUMFEATURES member).
316	*
317	* On non-x86 hosts, this will shortcut to the fallback w/o checking the
318	* indicator.
319	*
320	* @sa IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX
321	*/
322	#if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
323	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) \
324	(g_CpumHostFeatures.s.a_fCpumFeatureMember ? a_pfnNative : a_pfnFallback)
325	#else
326	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) (a_pfnFallback)
327	#endif
328
329
330	/**
331	* Branch types.
332	*/
333	typedef enum IEMBRANCH
334	{
335	IEMBRANCH_JUMP = 1,
336	IEMBRANCH_CALL,
337	IEMBRANCH_TRAP,
338	IEMBRANCH_SOFTWARE_INT,
339	IEMBRANCH_HARDWARE_INT
340	} IEMBRANCH;
341	AssertCompileSize(IEMBRANCH, 4);
342
343
344	/**
345	* INT instruction types.
346	*/
347	typedef enum IEMINT
348	{
349	/** INT n instruction (opcode 0xcd imm). */
350	IEMINT_INTN = 0,
351	/** Single byte INT3 instruction (opcode 0xcc). */
352	IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
353	/** Single byte INTO instruction (opcode 0xce). */
354	IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
355	/** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
356	IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
357	} IEMINT;
358	AssertCompileSize(IEMINT, 4);
359
360
361	/**
362	* A FPU result.
363	*/
364	typedef struct IEMFPURESULT
365	{
366	/** The output value. */
367	RTFLOAT80U r80Result;
368	/** The output status. */
369	uint16_t FSW;
370	} IEMFPURESULT;
371	AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
372	/** Pointer to a FPU result. */
373	typedef IEMFPURESULT *PIEMFPURESULT;
374	/** Pointer to a const FPU result. */
375	typedef IEMFPURESULT const *PCIEMFPURESULT;
376
377
378	/**
379	* A FPU result consisting of two output values and FSW.
380	*/
381	typedef struct IEMFPURESULTTWO
382	{
383	/** The first output value. */
384	RTFLOAT80U r80Result1;
385	/** The output status. */
386	uint16_t FSW;
387	/** The second output value. */
388	RTFLOAT80U r80Result2;
389	} IEMFPURESULTTWO;
390	AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
391	AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
392	/** Pointer to a FPU result consisting of two output values and FSW. */
393	typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
394	/** Pointer to a const FPU result consisting of two output values and FSW. */
395	typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
396
397
398	/**
399	* IEM TLB entry.
400	*
401	* Lookup assembly:
402	* @code{.asm}
403	; Calculate tag.
404	mov rax, [VA]
405	shl rax, 16
406	shr rax, 16 + X86_PAGE_SHIFT
407	or rax, [uTlbRevision]
408
409	; Do indexing.
410	movzx ecx, al
411	lea rcx, [pTlbEntries + rcx]
412
413	; Check tag.
414	cmp [rcx + IEMTLBENTRY.uTag], rax
415	jne .TlbMiss
416
417	; Check access.
418	mov rax, ACCESS_FLAGS \| MAPPING_R3_NOT_VALID \| 0xffffff00
419	and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
420	cmp rax, [uTlbPhysRev]
421	jne .TlbMiss
422
423	; Calc address and we're done.
424	mov eax, X86_PAGE_OFFSET_MASK
425	and eax, [VA]
426	or rax, [rcx + IEMTLBENTRY.pMappingR3]
427	%ifdef VBOX_WITH_STATISTICS
428	inc qword [cTlbHits]
429	%endif
430	jmp .Done
431
432	.TlbMiss:
433	mov r8d, ACCESS_FLAGS
434	mov rdx, [VA]
435	mov rcx, [pVCpu]
436	call iemTlbTypeMiss
437	.Done:
438
439	@endcode
440	*
441	*/
442	typedef struct IEMTLBENTRY
443	{
444	/** The TLB entry tag.
445	* Bits 35 thru 0 are made up of the virtual address shifted right 12 bits, this
446	* is ASSUMING a virtual address width of 48 bits.
447	*
448	* Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
449	*
450	* The TLB lookup code uses the current TLB revision, which won't ever be zero,
451	* enabling an extremely cheap TLB invalidation most of the time. When the TLB
452	* revision wraps around though, the tags needs to be zeroed.
453	*
454	* @note Try use SHRD instruction? After seeing
455	* https://gmplib.org/~tege/x86-timing.pdf, maybe not.
456	*
457	* @todo This will need to be reorganized for 57-bit wide virtual address and
458	* PCID (currently 12 bits) and ASID (currently 6 bits) support. We'll
459	* have to move the TLB entry versioning entirely to the
460	* fFlagsAndPhysRev member then, 57 bit wide VAs means we'll only have
461	* 19 bits left (64 - 57 + 12 = 19) and they'll almost entire be
462	* consumed by PCID and ASID (12 + 6 = 18).
463	*/
464	uint64_t uTag;
465	/** Access flags and physical TLB revision.
466	*
467	* - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
468	* - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
469	* - Bit 2 - page tables - not user (complemented X86_PTE_US).
470	* - Bit 3 - pgm phys/virt - not directly writable.
471	* - Bit 4 - pgm phys page - not directly readable.
472	* - Bit 5 - page tables - not accessed (complemented X86_PTE_A).
473	* - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
474	* - Bit 7 - tlb entry - pMappingR3 member not valid.
475	* - Bits 63 thru 8 are used for the physical TLB revision number.
476	*
477	* We're using complemented bit meanings here because it makes it easy to check
478	* whether special action is required. For instance a user mode write access
479	* would do a "TEST fFlags, (X86_PTE_RW \| X86_PTE_US \| X86_PTE_D)" and a
480	* non-zero result would mean special handling needed because either it wasn't
481	* writable, or it wasn't user, or the page wasn't dirty. A user mode read
482	* access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
483	* need to check any PTE flag.
484	*/
485	uint64_t fFlagsAndPhysRev;
486	/** The guest physical page address. */
487	uint64_t GCPhys;
488	/** Pointer to the ring-3 mapping. */
489	R3PTRTYPE(uint8_t *) pbMappingR3;
490	#if HC_ARCH_BITS == 32
491	uint32_t u32Padding1;
492	#endif
493	} IEMTLBENTRY;
494	AssertCompileSize(IEMTLBENTRY, 32);
495	/** Pointer to an IEM TLB entry. */
496	typedef IEMTLBENTRY *PIEMTLBENTRY;
497	/** Pointer to a const IEM TLB entry. */
498	typedef IEMTLBENTRY const *PCIEMTLBENTRY;
499
500	/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
501	* @{ */
502	#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /*< Page tables: Not executable. /
503	#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /*< Page tables: Not writable. /
504	#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /*< Page tables: Not user accessible (supervisor only). /
505	#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /*< Phys page: Not writable (access handler, ROM, whatever). /
506	#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /*< Phys page: Not readable (MMIO / access handler, ROM) /
507	#define IEMTLBE_F_PT_NO_ACCESSED RT_BIT_64(5) /*< Phys tables: Not accessed (need to be marked accessed). /
508	#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /*< Page tables: Not dirty (needs to be made dirty on write). /
509	#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(7) /*< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. /
510	#define IEMTLBE_F_PG_UNASSIGNED RT_BIT_64(8) /*< Phys page: Unassigned memory (not RAM, ROM, MMIO2 or MMIO). /
511	#define IEMTLBE_F_PG_CODE_PAGE RT_BIT_64(9) /*< Phys page: Code page. /
512	#define IEMTLBE_F_PHYS_REV UINT64_C(0xfffffffffffffc00) /*< Physical revision mask. @sa IEMTLB_PHYS_REV_INCR /
513	/** @} */
514	AssertCompile(PGMIEMGCPHYS2PTR_F_NO_WRITE == IEMTLBE_F_PG_NO_WRITE);
515	AssertCompile(PGMIEMGCPHYS2PTR_F_NO_READ == IEMTLBE_F_PG_NO_READ);
516	AssertCompile(PGMIEMGCPHYS2PTR_F_NO_MAPPINGR3 == IEMTLBE_F_NO_MAPPINGR3);
517	AssertCompile(PGMIEMGCPHYS2PTR_F_UNASSIGNED == IEMTLBE_F_PG_UNASSIGNED);
518	AssertCompile(PGMIEMGCPHYS2PTR_F_CODE_PAGE == IEMTLBE_F_PG_CODE_PAGE);
519	/** The bits set by PGMPhysIemGCPhys2PtrNoLock. */
520	#define IEMTLBE_GCPHYS2PTR_MASK ( PGMIEMGCPHYS2PTR_F_NO_WRITE \
521	\| PGMIEMGCPHYS2PTR_F_NO_READ \
522	\| PGMIEMGCPHYS2PTR_F_NO_MAPPINGR3 \
523	\| PGMIEMGCPHYS2PTR_F_UNASSIGNED \
524	\| PGMIEMGCPHYS2PTR_F_CODE_PAGE \
525	\| IEMTLBE_F_PHYS_REV )
526
527	/** The TLB size (power of two).
528	* We initially chose 256 because that way we can obtain the result directly
529	* from a 8-bit register without an additional AND instruction.
530	* See also @bugref{10687}. */
531	#define IEMTLB_ENTRY_COUNT 1024
532	#define IEMTLB_ENTRY_COUNT_AS_POWER_OF_TWO 10
533	AssertCompile(RT_BIT_32(IEMTLB_ENTRY_COUNT_AS_POWER_OF_TWO) == IEMTLB_ENTRY_COUNT);
534
535	/**
536	* An IEM TLB.
537	*
538	* We've got two of these, one for data and one for instructions.
539	*/
540	typedef struct IEMTLB
541	{
542	/** The non-global TLB revision.
543	* This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
544	* by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
545	* the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
546	* (The revision zero indicates an invalid TLB entry.)
547	*
548	* The initial value is choosen to cause an early wraparound. */
549	uint64_t uTlbRevision;
550	/** The TLB physical address revision - shadow of PGM variable.
551	*
552	* This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
553	* incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
554	* a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
555	* as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
556	*
557	* The initial value is choosen to cause an early wraparound.
558	*
559	* @note This is placed between the two TLB revisions because we
560	* load it in pair with one or the other on arm64. */
561	uint64_t volatile uTlbPhysRev;
562	/** The global TLB revision.
563	* Same as uTlbRevision, but only increased for global flushes. */
564	uint64_t uTlbRevisionGlobal;
565
566	/* Statistics: */
567
568	/** TLB hits in IEMAll.cpp code (IEM_WITH_TLB_STATISTICS only; both).
569	* @note For the data TLB this is only used in iemMemMap and and for direct (i.e.
570	* not via safe read/write path) calls to iemMemMapJmp. */
571	uint64_t cTlbCoreHits;
572	/** Safe read/write TLB hits in iemMemMapJmp (IEM_WITH_TLB_STATISTICS
573	* only; data tlb only). */
574	uint64_t cTlbSafeHits;
575	/** TLB hits in IEMAllMemRWTmplInline.cpp.h (data + IEM_WITH_TLB_STATISTICS only). */
576	uint64_t cTlbInlineCodeHits;
577
578	/** TLB misses in IEMAll.cpp code (both).
579	* @note For the data TLB this is only used in iemMemMap and for direct (i.e.
580	* not via safe read/write path) calls to iemMemMapJmp. So,
581	* for the data TLB this more like 'other misses', while for the code
582	* TLB is all misses. */
583	uint64_t cTlbCoreMisses;
584	/** Subset of cTlbCoreMisses that results in PTE.G=1 loads (odd entries). */
585	uint64_t cTlbCoreGlobalLoads;
586	/** Safe read/write TLB misses in iemMemMapJmp (so data only). */
587	uint64_t cTlbSafeMisses;
588	/** Subset of cTlbSafeMisses that results in PTE.G=1 loads (odd entries). */
589	uint64_t cTlbSafeGlobalLoads;
590	/** Safe read path taken (data only). */
591	uint64_t cTlbSafeReadPath;
592	/** Safe write path taken (data only). */
593	uint64_t cTlbSafeWritePath;
594
595	/** @name Details for native code TLB misses.
596	* @note These counts are included in the above counters (cTlbSafeReadPath,
597	* cTlbSafeWritePath, cTlbInlineCodeHits).
598	* @{ */
599	/** TLB misses in native code due to tag mismatch. */
600	STAMCOUNTER cTlbNativeMissTag;
601	/** TLB misses in native code due to flags or physical revision mismatch. */
602	STAMCOUNTER cTlbNativeMissFlagsAndPhysRev;
603	/** TLB misses in native code due to misaligned access. */
604	STAMCOUNTER cTlbNativeMissAlignment;
605	/** TLB misses in native code due to cross page access. */
606	uint32_t cTlbNativeMissCrossPage;
607	/** TLB misses in native code due to non-canonical address. */
608	uint32_t cTlbNativeMissNonCanonical;
609	/** @} */
610
611	/** Slow read path (code only). */
612	uint32_t cTlbSlowCodeReadPath;
613
614	/** Regular TLB flush count. */
615	uint32_t cTlsFlushes;
616	/** Global TLB flush count. */
617	uint32_t cTlsGlobalFlushes;
618	/** Revision rollovers. */
619	uint32_t cTlbRevisionRollovers;
620	/** Physical revision flushes. */
621	uint32_t cTlbPhysRevFlushes;
622	/** Physical revision rollovers. */
623	uint32_t cTlbPhysRevRollovers;
624
625	uint32_t au32Padding[10];
626
627	/** The TLB entries.
628	* Even entries are for PTE.G=0 and uses uTlbRevision.
629	* Odd entries are for PTE.G=1 and uses uTlbRevisionGlobal. */
630	IEMTLBENTRY aEntries[IEMTLB_ENTRY_COUNT * 2];
631	} IEMTLB;
632	AssertCompileSizeAlignment(IEMTLB, 64);
633	/** IEMTLB::uTlbRevision increment. */
634	#define IEMTLB_REVISION_INCR RT_BIT_64(36)
635	/** IEMTLB::uTlbRevision mask. */
636	#define IEMTLB_REVISION_MASK (~(RT_BIT_64(36) - 1))
637	/** IEMTLB::uTlbPhysRev increment.
638	* @sa IEMTLBE_F_PHYS_REV */
639	#define IEMTLB_PHYS_REV_INCR RT_BIT_64(10)
640	/**
641	* Calculates the TLB tag for a virtual address but without TLB revision.
642	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
643	* @param a_GCPtr The virtual address. Must be RTGCPTR or same size or
644	* the clearing of the top 16 bits won't work (if 32-bit
645	* we'll end up with mostly zeros).
646	*/
647	#define IEMTLB_CALC_TAG_NO_REV(a_GCPtr) ( (((a_GCPtr) << 16) >> (GUEST_PAGE_SHIFT + 16)) )
648	/**
649	* Converts a TLB tag value into a even TLB index.
650	* @returns Index into IEMTLB::aEntries.
651	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
652	*/
653	#if IEMTLB_ENTRY_COUNT == 256
654	# define IEMTLB_TAG_TO_EVEN_INDEX(a_uTag) ( (uint8_t)(a_uTag) * 2U )
655	#else
656	# define IEMTLB_TAG_TO_EVEN_INDEX(a_uTag) ( ((a_uTag) & (IEMTLB_ENTRY_COUNT - 1U)) * 2U )
657	AssertCompile(RT_IS_POWER_OF_TWO(IEMTLB_ENTRY_COUNT));
658	#endif
659	/**
660	* Converts a TLB tag value into an even TLB index.
661	* @returns Pointer into IEMTLB::aEntries corresponding to .
662	* @param a_pTlb The TLB.
663	* @param a_uTag Value returned by IEMTLB_CALC_TAG or
664	* IEMTLB_CALC_TAG_NO_REV.
665	*/
666	#define IEMTLB_TAG_TO_EVEN_ENTRY(a_pTlb, a_uTag) ( &(a_pTlb)->aEntries[IEMTLB_TAG_TO_EVEN_INDEX(a_uTag)] )
667
668
669	/** @name IEM_MC_F_XXX - MC block flags/clues.
670	* @todo Merge with IEM_CIMPL_F_XXX
671	* @{ */
672	#define IEM_MC_F_ONLY_8086 RT_BIT_32(0)
673	#define IEM_MC_F_MIN_186 RT_BIT_32(1)
674	#define IEM_MC_F_MIN_286 RT_BIT_32(2)
675	#define IEM_MC_F_NOT_286_OR_OLDER IEM_MC_F_MIN_386
676	#define IEM_MC_F_MIN_386 RT_BIT_32(3)
677	#define IEM_MC_F_MIN_486 RT_BIT_32(4)
678	#define IEM_MC_F_MIN_PENTIUM RT_BIT_32(5)
679	#define IEM_MC_F_MIN_PENTIUM_II IEM_MC_F_MIN_PENTIUM
680	#define IEM_MC_F_MIN_CORE IEM_MC_F_MIN_PENTIUM
681	#define IEM_MC_F_64BIT RT_BIT_32(6)
682	#define IEM_MC_F_NOT_64BIT RT_BIT_32(7)
683	/** This is set by IEMAllN8vePython.py to indicate a variation without the
684	* flags-clearing-and-checking, when there is also a variation with that.
685	* @note Do not use this manully, it's only for python and for testing in
686	* the native recompiler! */
687	#define IEM_MC_F_WITHOUT_FLAGS RT_BIT_32(8)
688	/** @} */
689
690	/** @name IEM_CIMPL_F_XXX - State change clues for CIMPL calls.
691	*
692	* These clues are mainly for the recompiler, so that it can emit correct code.
693	*
694	* They are processed by the python script and which also automatically
695	* calculates flags for MC blocks based on the statements, extending the use of
696	* these flags to describe MC block behavior to the recompiler core. The python
697	* script pass the flags to the IEM_MC2_END_EMIT_CALLS macro, but mainly for
698	* error checking purposes. The script emits the necessary fEndTb = true and
699	* similar statements as this reduces compile time a tiny bit.
700	*
701	* @{ */
702	/** Flag set if direct branch, clear if absolute or indirect. */
703	#define IEM_CIMPL_F_BRANCH_DIRECT RT_BIT_32(0)
704	/** Flag set if indirect branch, clear if direct or relative.
705	* This is also used for all system control transfers (SYSCALL, SYSRET, INT, ++)
706	* as well as for return instructions (RET, IRET, RETF). */
707	#define IEM_CIMPL_F_BRANCH_INDIRECT RT_BIT_32(1)
708	/** Flag set if relative branch, clear if absolute or indirect. */
709	#define IEM_CIMPL_F_BRANCH_RELATIVE RT_BIT_32(2)
710	/** Flag set if conditional branch, clear if unconditional. */
711	#define IEM_CIMPL_F_BRANCH_CONDITIONAL RT_BIT_32(3)
712	/** Flag set if it's a far branch (changes CS). */
713	#define IEM_CIMPL_F_BRANCH_FAR RT_BIT_32(4)
714	/** Convenience: Testing any kind of branch. */
715	#define IEM_CIMPL_F_BRANCH_ANY (IEM_CIMPL_F_BRANCH_DIRECT \| IEM_CIMPL_F_BRANCH_INDIRECT \| IEM_CIMPL_F_BRANCH_RELATIVE)
716
717	/** Execution flags may change (IEMCPU::fExec). */
718	#define IEM_CIMPL_F_MODE RT_BIT_32(5)
719	/** May change significant portions of RFLAGS. */
720	#define IEM_CIMPL_F_RFLAGS RT_BIT_32(6)
721	/** May change the status bits (X86_EFL_STATUS_BITS) in RFLAGS. */
722	#define IEM_CIMPL_F_STATUS_FLAGS RT_BIT_32(7)
723	/** May trigger interrupt shadowing. */
724	#define IEM_CIMPL_F_INHIBIT_SHADOW RT_BIT_32(8)
725	/** May enable interrupts, so recheck IRQ immediately afterwards executing
726	* the instruction. */
727	#define IEM_CIMPL_F_CHECK_IRQ_AFTER RT_BIT_32(9)
728	/** May disable interrupts, so recheck IRQ immediately before executing the
729	* instruction. */
730	#define IEM_CIMPL_F_CHECK_IRQ_BEFORE RT_BIT_32(10)
731	/** Convenience: Check for IRQ both before and after an instruction. */
732	#define IEM_CIMPL_F_CHECK_IRQ_BEFORE_AND_AFTER (IEM_CIMPL_F_CHECK_IRQ_BEFORE \| IEM_CIMPL_F_CHECK_IRQ_AFTER)
733	/** May trigger a VM exit (treated like IEM_CIMPL_F_MODE atm). */
734	#define IEM_CIMPL_F_VMEXIT RT_BIT_32(11)
735	/** May modify FPU state.
736	* @todo Not sure if this is useful yet. */
737	#define IEM_CIMPL_F_FPU RT_BIT_32(12)
738	/** REP prefixed instruction which may yield before updating PC.
739	* @todo Not sure if this is useful, REP functions now return non-zero
740	* status if they don't update the PC. */
741	#define IEM_CIMPL_F_REP RT_BIT_32(13)
742	/** I/O instruction.
743	* @todo Not sure if this is useful yet. */
744	#define IEM_CIMPL_F_IO RT_BIT_32(14)
745	/** Force end of TB after the instruction. */
746	#define IEM_CIMPL_F_END_TB RT_BIT_32(15)
747	/** Flag set if a branch may also modify the stack (push/pop return address). */
748	#define IEM_CIMPL_F_BRANCH_STACK RT_BIT_32(16)
749	/** Flag set if a branch may also modify the stack (push/pop return address)
750	* and switch it (load/restore SS:RSP). */
751	#define IEM_CIMPL_F_BRANCH_STACK_FAR RT_BIT_32(17)
752	/** Convenience: Raise exception (technically unnecessary, since it shouldn't return VINF_SUCCESS). */
753	#define IEM_CIMPL_F_XCPT \
754	(IEM_CIMPL_F_BRANCH_INDIRECT \| IEM_CIMPL_F_BRANCH_FAR \| IEM_CIMPL_F_BRANCH_STACK_FAR \
755	\| IEM_CIMPL_F_MODE \| IEM_CIMPL_F_RFLAGS \| IEM_CIMPL_F_VMEXIT)
756
757	/** The block calls a C-implementation instruction function with two implicit arguments.
758	* Mutually exclusive with IEM_CIMPL_F_CALLS_AIMPL and
759	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
760	* @note The python scripts will add this if missing. */
761	#define IEM_CIMPL_F_CALLS_CIMPL RT_BIT_32(18)
762	/** The block calls an ASM-implementation instruction function.
763	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL and
764	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
765	* @note The python scripts will add this if missing. */
766	#define IEM_CIMPL_F_CALLS_AIMPL RT_BIT_32(19)
767	/** The block calls an ASM-implementation instruction function with an implicit
768	* X86FXSTATE pointer argument.
769	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL, IEM_CIMPL_F_CALLS_AIMPL and
770	* IEM_CIMPL_F_CALLS_AIMPL_WITH_XSTATE.
771	* @note The python scripts will add this if missing. */
772	#define IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE RT_BIT_32(20)
773	/** The block calls an ASM-implementation instruction function with an implicit
774	* X86XSAVEAREA pointer argument.
775	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL, IEM_CIMPL_F_CALLS_AIMPL and
776	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
777	* @note No different from IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE, so same value.
778	* @note The python scripts will add this if missing. */
779	#define IEM_CIMPL_F_CALLS_AIMPL_WITH_XSTATE IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE
780	/** @} */
781
782
783	/** @name IEM_F_XXX - Execution mode flags (IEMCPU::fExec, IEMTB::fFlags).
784	*
785	* These flags are set when entering IEM and adjusted as code is executed, such
786	* that they will always contain the current values as instructions are
787	* finished.
788	*
789	* In recompiled execution mode, (most of) these flags are included in the
790	* translation block selection key and stored in IEMTB::fFlags alongside the
791	* IEMTB_F_XXX flags. The latter flags uses bits 31 thru 24, which are all zero
792	* in IEMCPU::fExec.
793	*
794	* @{ */
795	/** Mode: The block target mode mask. */
796	#define IEM_F_MODE_MASK UINT32_C(0x0000001f)
797	/** Mode: The IEMMODE part of the IEMTB_F_MODE_MASK value. */
798	#define IEM_F_MODE_CPUMODE_MASK UINT32_C(0x00000003)
799	/** X86 Mode: Bit used to indicating pre-386 CPU in 16-bit mode (for eliminating
800	* conditional in EIP/IP updating), and flat wide open CS, SS, DS, and ES in
801	* 32-bit mode (for simplifying most memory accesses). */
802	#define IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK UINT32_C(0x00000004)
803	/** X86 Mode: Bit indicating protected mode, real mode (or SMM) when not set. */
804	#define IEM_F_MODE_X86_PROT_MASK UINT32_C(0x00000008)
805	/** X86 Mode: Bit used to indicate virtual 8086 mode (only 16-bit). */
806	#define IEM_F_MODE_X86_V86_MASK UINT32_C(0x00000010)
807
808	/** X86 Mode: 16-bit on 386 or later. */
809	#define IEM_F_MODE_X86_16BIT UINT32_C(0x00000000)
810	/** X86 Mode: 80286, 80186 and 8086/88 targetting blocks (EIP update opt). */
811	#define IEM_F_MODE_X86_16BIT_PRE_386 UINT32_C(0x00000004)
812	/** X86 Mode: 16-bit protected mode on 386 or later. */
813	#define IEM_F_MODE_X86_16BIT_PROT UINT32_C(0x00000008)
814	/** X86 Mode: 16-bit protected mode on 386 or later. */
815	#define IEM_F_MODE_X86_16BIT_PROT_PRE_386 UINT32_C(0x0000000c)
816	/** X86 Mode: 16-bit virtual 8086 protected mode (on 386 or later). */
817	#define IEM_F_MODE_X86_16BIT_PROT_V86 UINT32_C(0x00000018)
818
819	/** X86 Mode: 32-bit on 386 or later. */
820	#define IEM_F_MODE_X86_32BIT UINT32_C(0x00000001)
821	/** X86 Mode: 32-bit mode with wide open flat CS, SS, DS and ES. */
822	#define IEM_F_MODE_X86_32BIT_FLAT UINT32_C(0x00000005)
823	/** X86 Mode: 32-bit protected mode. */
824	#define IEM_F_MODE_X86_32BIT_PROT UINT32_C(0x00000009)
825	/** X86 Mode: 32-bit protected mode with wide open flat CS, SS, DS and ES. */
826	#define IEM_F_MODE_X86_32BIT_PROT_FLAT UINT32_C(0x0000000d)
827
828	/** X86 Mode: 64-bit (includes protected, but not the flat bit). */
829	#define IEM_F_MODE_X86_64BIT UINT32_C(0x0000000a)
830
831	/** X86 Mode: Checks if @a a_fExec represent a FLAT mode. */
832	#define IEM_F_MODE_X86_IS_FLAT(a_fExec) ( ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_64BIT \
833	\|\| ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_32BIT_PROT_FLAT \
834	\|\| ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_32BIT_FLAT)
835
836	/** Bypass access handlers when set. */
837	#define IEM_F_BYPASS_HANDLERS UINT32_C(0x00010000)
838	/** Have pending hardware instruction breakpoints. */
839	#define IEM_F_PENDING_BRK_INSTR UINT32_C(0x00020000)
840	/** Have pending hardware data breakpoints. */
841	#define IEM_F_PENDING_BRK_DATA UINT32_C(0x00040000)
842
843	/** X86: Have pending hardware I/O breakpoints. */
844	#define IEM_F_PENDING_BRK_X86_IO UINT32_C(0x00000400)
845	/** X86: Disregard the lock prefix (implied or not) when set. */
846	#define IEM_F_X86_DISREGARD_LOCK UINT32_C(0x00000800)
847
848	/** Pending breakpoint mask (what iemCalcExecDbgFlags works out). */
849	#define IEM_F_PENDING_BRK_MASK (IEM_F_PENDING_BRK_INSTR \| IEM_F_PENDING_BRK_DATA \| IEM_F_PENDING_BRK_X86_IO)
850
851	/** Caller configurable options. */
852	#define IEM_F_USER_OPTS (IEM_F_BYPASS_HANDLERS \| IEM_F_X86_DISREGARD_LOCK)
853
854	/** X86: The current protection level (CPL) shift factor. */
855	#define IEM_F_X86_CPL_SHIFT 8
856	/** X86: The current protection level (CPL) mask. */
857	#define IEM_F_X86_CPL_MASK UINT32_C(0x00000300)
858	/** X86: The current protection level (CPL) shifted mask. */
859	#define IEM_F_X86_CPL_SMASK UINT32_C(0x00000003)
860
861	/** X86: Alignment checks enabled (CR0.AM=1 & EFLAGS.AC=1). */
862	#define IEM_F_X86_AC UINT32_C(0x00080000)
863
864	/** X86 execution context.
865	* The IEM_F_X86_CTX_XXX values are individual flags that can be combined (with
866	* the exception of IEM_F_X86_CTX_NORMAL). This allows running VMs from SMM
867	* mode. */
868	#define IEM_F_X86_CTX_MASK UINT32_C(0x0000f000)
869	/** X86 context: Plain regular execution context. */
870	#define IEM_F_X86_CTX_NORMAL UINT32_C(0x00000000)
871	/** X86 context: VT-x enabled. */
872	#define IEM_F_X86_CTX_VMX UINT32_C(0x00001000)
873	/** X86 context: AMD-V enabled. */
874	#define IEM_F_X86_CTX_SVM UINT32_C(0x00002000)
875	/** X86 context: In AMD-V or VT-x guest mode. */
876	#define IEM_F_X86_CTX_IN_GUEST UINT32_C(0x00004000)
877	/** X86 context: System management mode (SMM). */
878	#define IEM_F_X86_CTX_SMM UINT32_C(0x00008000)
879
880	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
881	* iemRegFinishClearingRF() most for most situations (CPUMCTX_DBG_HIT_DRX_MASK
882	* and CPUMCTX_DBG_DBGF_MASK are covered by the IEM_F_PENDING_BRK_XXX bits
883	* alread). */
884
885	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
886	* iemRegFinishClearingRF() most for most situations
887	* (CPUMCTX_DBG_HIT_DRX_MASK and CPUMCTX_DBG_DBGF_MASK are covered by
888	* the IEM_F_PENDING_BRK_XXX bits alread). */
889
890	/** @} */
891
892
893	/** @name IEMTB_F_XXX - Translation block flags (IEMTB::fFlags).
894	*
895	* Extends the IEM_F_XXX flags (subject to IEMTB_F_IEM_F_MASK) to make up the
896	* translation block flags. The combined flag mask (subject to
897	* IEMTB_F_KEY_MASK) is used as part of the lookup key for translation blocks.
898	*
899	* @{ */
900	/** Mask of IEM_F_XXX flags included in IEMTB_F_XXX. */
901	#define IEMTB_F_IEM_F_MASK UINT32_C(0x00ffffff)
902
903	/** Type: The block type mask. */
904	#define IEMTB_F_TYPE_MASK UINT32_C(0x03000000)
905	/** Type: Purly threaded recompiler (via tables). */
906	#define IEMTB_F_TYPE_THREADED UINT32_C(0x01000000)
907	/** Type: Native recompilation. */
908	#define IEMTB_F_TYPE_NATIVE UINT32_C(0x02000000)
909
910	/** Set when we're starting the block in an "interrupt shadow".
911	* We don't need to distingish between the two types of this mask, thus the one.
912	* @see CPUMCTX_INHIBIT_SHADOW, CPUMIsInInterruptShadow() */
913	#define IEMTB_F_INHIBIT_SHADOW UINT32_C(0x04000000)
914	/** Set when we're currently inhibiting NMIs
915	* @see CPUMCTX_INHIBIT_NMI, CPUMAreInterruptsInhibitedByNmi() */
916	#define IEMTB_F_INHIBIT_NMI UINT32_C(0x08000000)
917
918	/** Checks that EIP/IP is wihin CS.LIM before each instruction. Used when
919	* we're close the limit before starting a TB, as determined by
920	* iemGetTbFlagsForCurrentPc(). */
921	#define IEMTB_F_CS_LIM_CHECKS UINT32_C(0x10000000)
922
923	/** Mask of the IEMTB_F_XXX flags that are part of the TB lookup key.
924	*
925	* @note We skip all of IEM_F_X86_CTX_MASK, with the exception of SMM (which we
926	* don't implement), because we don't currently generate any context
927	* specific code - that's all handled in CIMPL functions.
928	*
929	* For the threaded recompiler we don't generate any CPL specific code
930	* either, but the native recompiler does for memory access (saves getting
931	* the CPL from fExec and turning it into IEMTLBE_F_PT_NO_USER).
932	* Since most OSes will not share code between rings, this shouldn't
933	* have any real effect on TB/memory/recompiling load.
934	*/
935	#define IEMTB_F_KEY_MASK ((UINT32_MAX & ~(IEM_F_X86_CTX_MASK \| IEMTB_F_TYPE_MASK)) \| IEM_F_X86_CTX_SMM)
936	/** @} */
937
938	AssertCompile( (IEM_F_MODE_X86_16BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
939	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
940	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_PROT_MASK));
941	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_V86_MASK));
942	AssertCompile( (IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
943	AssertCompile( IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
944	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_PROT_MASK));
945	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
946	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
947	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
948	AssertCompile( IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
949	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_V86_MASK));
950	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
951	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
952	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_PROT_MASK);
953	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
954	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_PROT_MASK);
955	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
956	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_V86_MASK);
957
958	AssertCompile( (IEM_F_MODE_X86_32BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
959	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
960	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_PROT_MASK));
961	AssertCompile( (IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
962	AssertCompile( IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
963	AssertCompile(!(IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_PROT_MASK));
964	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
965	AssertCompile(!(IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
966	AssertCompile( IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
967	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
968	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
969	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_PROT_MASK);
970
971	AssertCompile( (IEM_F_MODE_X86_64BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_64BIT);
972	AssertCompile( IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_PROT_MASK);
973	AssertCompile(!(IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
974
975	/** Native instruction type for use with the native code generator.
976	* This is a byte (uint8_t) for x86 and amd64 and uint32_t for the other(s). */
977	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
978	typedef uint8_t IEMNATIVEINSTR;
979	#else
980	typedef uint32_t IEMNATIVEINSTR;
981	#endif
982	/** Pointer to a native instruction unit. */
983	typedef IEMNATIVEINSTR *PIEMNATIVEINSTR;
984	/** Pointer to a const native instruction unit. */
985	typedef IEMNATIVEINSTR const *PCIEMNATIVEINSTR;
986
987	/**
988	* A call for the threaded call table.
989	*/
990	typedef struct IEMTHRDEDCALLENTRY
991	{
992	/** The function to call (IEMTHREADEDFUNCS). */
993	uint16_t enmFunction;
994
995	/** Instruction number in the TB (for statistics). */
996	uint8_t idxInstr;
997	/** The opcode length. */
998	uint8_t cbOpcode;
999	/** Offset into IEMTB::pabOpcodes. */
1000	uint16_t offOpcode;
1001
1002	/** TB lookup table index (7 bits) and large size (1 bits).
1003	*
1004	* The default size is 1 entry, but for indirect calls and returns we set the
1005	* top bit and allocate 4 (IEM_TB_LOOKUP_TAB_LARGE_SIZE) entries. The large
1006	* tables uses RIP for selecting the entry to use, as it is assumed a hash table
1007	* lookup isn't that slow compared to sequentially trying out 4 TBs.
1008	*
1009	* By default lookup table entry 0 for a TB is reserved as a fallback for
1010	* calltable entries w/o explicit entreis, so this member will be non-zero if
1011	* there is a lookup entry associated with this call.
1012	*
1013	* @sa IEM_TB_LOOKUP_TAB_GET_SIZE, IEM_TB_LOOKUP_TAB_GET_IDX
1014	*/
1015	uint8_t uTbLookup;
1016
1017	/** Unused atm. */
1018	uint8_t uUnused0;
1019
1020	/** Generic parameters. */
1021	uint64_t auParams[3];
1022	} IEMTHRDEDCALLENTRY;
1023	AssertCompileSize(IEMTHRDEDCALLENTRY, sizeof(uint64_t) * 4);
1024	/** Pointer to a threaded call entry. */
1025	typedef struct IEMTHRDEDCALLENTRY *PIEMTHRDEDCALLENTRY;
1026	/** Pointer to a const threaded call entry. */
1027	typedef IEMTHRDEDCALLENTRY const *PCIEMTHRDEDCALLENTRY;
1028
1029	/** The number of TB lookup table entries for a large allocation
1030	* (IEMTHRDEDCALLENTRY::uTbLookup bit 7 set). */
1031	#define IEM_TB_LOOKUP_TAB_LARGE_SIZE 4
1032	/** Get the lookup table size from IEMTHRDEDCALLENTRY::uTbLookup. */
1033	#define IEM_TB_LOOKUP_TAB_GET_SIZE(a_uTbLookup) (!((a_uTbLookup) & 0x80) ? 1 : IEM_TB_LOOKUP_TAB_LARGE_SIZE)
1034	/** Get the first lookup table index from IEMTHRDEDCALLENTRY::uTbLookup. */
1035	#define IEM_TB_LOOKUP_TAB_GET_IDX(a_uTbLookup) ((a_uTbLookup) & 0x7f)
1036	/** Get the lookup table index from IEMTHRDEDCALLENTRY::uTbLookup and RIP. */
1037	#define IEM_TB_LOOKUP_TAB_GET_IDX_WITH_RIP(a_uTbLookup, a_Rip) \
1038	(!((a_uTbLookup) & 0x80) ? (a_uTbLookup) & 0x7f : ((a_uTbLookup) & 0x7f) + ((a_Rip) & (IEM_TB_LOOKUP_TAB_LARGE_SIZE - 1)) )
1039
1040	/** Make a IEMTHRDEDCALLENTRY::uTbLookup value. */
1041	#define IEM_TB_LOOKUP_TAB_MAKE(a_idxTable, a_fLarge) ((a_idxTable) \| ((a_fLarge) ? 0x80 : 0))
1042
1043	/**
1044	* Native IEM TB 'function' typedef.
1045	*
1046	* This will throw/longjmp on occation.
1047	*
1048	* @note AMD64 doesn't have that many non-volatile registers and does sport
1049	* 32-bit address displacments, so we don't need pCtx.
1050	*
1051	* On ARM64 pCtx allows us to directly address the whole register
1052	* context without requiring a separate indexing register holding the
1053	* offset. This saves an instruction loading the offset for each guest
1054	* CPU context access, at the cost of a non-volatile register.
1055	* Fortunately, ARM64 has quite a lot more registers.
1056	*/
1057	typedef
1058	#ifdef RT_ARCH_AMD64
1059	int FNIEMTBNATIVE(PVMCPUCC pVCpu)
1060	#else
1061	int FNIEMTBNATIVE(PVMCPUCC pVCpu, PCPUMCTX pCtx)
1062	#endif
1063	#if RT_CPLUSPLUS_PREREQ(201700)
1064	IEM_NOEXCEPT_MAY_LONGJMP
1065	#endif
1066	;
1067	/** Pointer to a native IEM TB entry point function.
1068	* This will throw/longjmp on occation. */
1069	typedef FNIEMTBNATIVE *PFNIEMTBNATIVE;
1070
1071
1072	/**
1073	* Translation block debug info entry type.
1074	*/
1075	typedef enum IEMTBDBGENTRYTYPE
1076	{
1077	kIemTbDbgEntryType_Invalid = 0,
1078	/** The entry is for marking a native code position.
1079	* Entries following this all apply to this position. */
1080	kIemTbDbgEntryType_NativeOffset,
1081	/** The entry is for a new guest instruction. */
1082	kIemTbDbgEntryType_GuestInstruction,
1083	/** Marks the start of a threaded call. */
1084	kIemTbDbgEntryType_ThreadedCall,
1085	/** Marks the location of a label. */
1086	kIemTbDbgEntryType_Label,
1087	/** Info about a host register shadowing a guest register. */
1088	kIemTbDbgEntryType_GuestRegShadowing,
1089	#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
1090	/** Info about a host SIMD register shadowing a guest SIMD register. */
1091	kIemTbDbgEntryType_GuestSimdRegShadowing,
1092	#endif
1093	#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING
1094	/** Info about a delayed RIP update. */
1095	kIemTbDbgEntryType_DelayedPcUpdate,
1096	#endif
1097	#if defined(IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK) \|\| defined(IEMNATIVE_WITH_SIMD_REG_ALLOCATOR)
1098	/** Info about a shadowed guest register becoming dirty. */
1099	kIemTbDbgEntryType_GuestRegDirty,
1100	/** Info about register writeback/flush oepration. */
1101	kIemTbDbgEntryType_GuestRegWriteback,
1102	#endif
1103	kIemTbDbgEntryType_End
1104	} IEMTBDBGENTRYTYPE;
1105
1106	/**
1107	* Translation block debug info entry.
1108	*/
1109	typedef union IEMTBDBGENTRY
1110	{
1111	/** Plain 32-bit view. */
1112	uint32_t u;
1113
1114	/** Generic view for getting at the type field. */
1115	struct
1116	{
1117	/** IEMTBDBGENTRYTYPE */
1118	uint32_t uType : 4;
1119	uint32_t uTypeSpecific : 28;
1120	} Gen;
1121
1122	struct
1123	{
1124	/** kIemTbDbgEntryType_ThreadedCall1. */
1125	uint32_t uType : 4;
1126	/** Native code offset. */
1127	uint32_t offNative : 28;
1128	} NativeOffset;
1129
1130	struct
1131	{
1132	/** kIemTbDbgEntryType_GuestInstruction. */
1133	uint32_t uType : 4;
1134	uint32_t uUnused : 4;
1135	/** The IEM_F_XXX flags. */
1136	uint32_t fExec : 24;
1137	} GuestInstruction;
1138
1139	struct
1140	{
1141	/* kIemTbDbgEntryType_ThreadedCall. */
1142	uint32_t uType : 4;
1143	/** Set if the call was recompiled to native code, clear if just calling
1144	* threaded function. */
1145	uint32_t fRecompiled : 1;
1146	uint32_t uUnused : 11;
1147	/** The threaded call number (IEMTHREADEDFUNCS). */
1148	uint32_t enmCall : 16;
1149	} ThreadedCall;
1150
1151	struct
1152	{
1153	/* kIemTbDbgEntryType_Label. */
1154	uint32_t uType : 4;
1155	uint32_t uUnused : 4;
1156	/** The label type (IEMNATIVELABELTYPE). */
1157	uint32_t enmLabel : 8;
1158	/** The label data. */
1159	uint32_t uData : 16;
1160	} Label;
1161
1162	struct
1163	{
1164	/* kIemTbDbgEntryType_GuestRegShadowing. */
1165	uint32_t uType : 4;
1166	uint32_t uUnused : 4;
1167	/** The guest register being shadowed (IEMNATIVEGSTREG). */
1168	uint32_t idxGstReg : 8;
1169	/** The host new register number, UINT8_MAX if dropped. */
1170	uint32_t idxHstReg : 8;
1171	/** The previous host register number, UINT8_MAX if new. */
1172	uint32_t idxHstRegPrev : 8;
1173	} GuestRegShadowing;
1174
1175	#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
1176	struct
1177	{
1178	/* kIemTbDbgEntryType_GuestSimdRegShadowing. */
1179	uint32_t uType : 4;
1180	uint32_t uUnused : 4;
1181	/** The guest register being shadowed (IEMNATIVEGSTSIMDREG). */
1182	uint32_t idxGstSimdReg : 8;
1183	/** The host new register number, UINT8_MAX if dropped. */
1184	uint32_t idxHstSimdReg : 8;
1185	/** The previous host register number, UINT8_MAX if new. */
1186	uint32_t idxHstSimdRegPrev : 8;
1187	} GuestSimdRegShadowing;
1188	#endif
1189
1190	#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING
1191	struct
1192	{
1193	/* kIemTbDbgEntryType_DelayedPcUpdate. */
1194	uint32_t uType : 4;
1195	/* The instruction offset added to the program counter. */
1196	uint32_t offPc : 14;
1197	/** Number of instructions skipped. */
1198	uint32_t cInstrSkipped : 14;
1199	} DelayedPcUpdate;
1200	#endif
1201
1202	#if defined(IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK) \|\| defined(IEMNATIVE_WITH_SIMD_REG_ALLOCATOR)
1203	struct
1204	{
1205	/* kIemTbDbgEntryType_GuestRegDirty. */
1206	uint32_t uType : 4;
1207	uint32_t uUnused : 11;
1208	/** Flag whether this is about a SIMD (true) or general (false) register. */
1209	uint32_t fSimdReg : 1;
1210	/** The guest register index being marked as dirty. */
1211	uint32_t idxGstReg : 8;
1212	/** The host register number this register is shadowed in .*/
1213	uint32_t idxHstReg : 8;
1214	} GuestRegDirty;
1215
1216	struct
1217	{
1218	/* kIemTbDbgEntryType_GuestRegWriteback. */
1219	uint32_t uType : 4;
1220	/** Flag whether this is about a SIMD (true) or general (false) register flush. */
1221	uint32_t fSimdReg : 1;
1222	/** The mask shift. */
1223	uint32_t cShift : 2;
1224	/** The guest register mask being written back. */
1225	uint32_t fGstReg : 25;
1226	} GuestRegWriteback;
1227	#endif
1228
1229	} IEMTBDBGENTRY;
1230	AssertCompileSize(IEMTBDBGENTRY, sizeof(uint32_t));
1231	/** Pointer to a debug info entry. */
1232	typedef IEMTBDBGENTRY *PIEMTBDBGENTRY;
1233	/** Pointer to a const debug info entry. */
1234	typedef IEMTBDBGENTRY const *PCIEMTBDBGENTRY;
1235
1236	/**
1237	* Translation block debug info.
1238	*/
1239	typedef struct IEMTBDBG
1240	{
1241	/** Number of entries in aEntries. */
1242	uint32_t cEntries;
1243	/** The offset of the last kIemTbDbgEntryType_NativeOffset record. */
1244	uint32_t offNativeLast;
1245	/** Debug info entries. */
1246	RT_FLEXIBLE_ARRAY_EXTENSION
1247	IEMTBDBGENTRY aEntries[RT_FLEXIBLE_ARRAY];
1248	} IEMTBDBG;
1249	/** Pointer to TB debug info. */
1250	typedef IEMTBDBG *PIEMTBDBG;
1251	/** Pointer to const TB debug info. */
1252	typedef IEMTBDBG const *PCIEMTBDBG;
1253
1254
1255	/**
1256	* Translation block.
1257	*
1258	* The current plan is to just keep TBs and associated lookup hash table private
1259	* to each VCpu as that simplifies TB removal greatly (no races) and generally
1260	* avoids using expensive atomic primitives for updating lists and stuff.
1261	*/
1262	#pragma pack(2) /* to prevent the Thrd structure from being padded unnecessarily */
1263	typedef struct IEMTB
1264	{
1265	/** Next block with the same hash table entry. */
1266	struct IEMTB *pNext;
1267	/** Usage counter. */
1268	uint32_t cUsed;
1269	/** The IEMCPU::msRecompilerPollNow last time it was used. */
1270	uint32_t msLastUsed;
1271
1272	/** @name What uniquely identifies the block.
1273	* @{ */
1274	RTGCPHYS GCPhysPc;
1275	/** IEMTB_F_XXX (i.e. IEM_F_XXX ++). */
1276	uint32_t fFlags;
1277	union
1278	{
1279	struct
1280	{
1281	/*< Relevant CS X86DESCATTR_XXX bits. /
1282	uint16_t fAttr;
1283	} x86;
1284	};
1285	/** @} */
1286
1287	/** Number of opcode ranges. */
1288	uint8_t cRanges;
1289	/** Statistics: Number of instructions in the block. */
1290	uint8_t cInstructions;
1291
1292	/** Type specific info. */
1293	union
1294	{
1295	struct
1296	{
1297	/** The call sequence table. */
1298	PIEMTHRDEDCALLENTRY paCalls;
1299	/** Number of calls in paCalls. */
1300	uint16_t cCalls;
1301	/** Number of calls allocated. */
1302	uint16_t cAllocated;
1303	} Thrd;
1304	struct
1305	{
1306	/** The native instructions (PFNIEMTBNATIVE). */
1307	PIEMNATIVEINSTR paInstructions;
1308	/** Number of instructions pointed to by paInstructions. */
1309	uint32_t cInstructions;
1310	} Native;
1311	/** Generic view for zeroing when freeing. */
1312	struct
1313	{
1314	uintptr_t uPtr;
1315	uint32_t uData;
1316	} Gen;
1317	};
1318
1319	/** The allocation chunk this TB belongs to. */
1320	uint8_t idxAllocChunk;
1321	/** The number of entries in the lookup table.
1322	* Because we're out of space, the TB lookup table is located before the
1323	* opcodes pointed to by pabOpcodes. */
1324	uint8_t cTbLookupEntries;
1325
1326	/** Number of bytes of opcodes stored in pabOpcodes.
1327	* @todo this field isn't really needed, aRanges keeps the actual info. */
1328	uint16_t cbOpcodes;
1329	/** Pointer to the opcode bytes this block was recompiled from.
1330	* This also points to the TB lookup table, which starts cTbLookupEntries
1331	* entries before the opcodes (we don't have room atm for another point). */
1332	uint8_t *pabOpcodes;
1333
1334	/** Debug info if enabled.
1335	* This is only generated by the native recompiler. */
1336	PIEMTBDBG pDbgInfo;
1337
1338	/* --- 64 byte cache line end --- */
1339
1340	/** Opcode ranges.
1341	*
1342	* The opcode checkers and maybe TLB loading functions will use this to figure
1343	* out what to do. The parameter will specify an entry and the opcode offset to
1344	* start at and the minimum number of bytes to verify (instruction length).
1345	*
1346	* When VT-x and AMD-V looks up the opcode bytes for an exitting instruction,
1347	* they'll first translate RIP (+ cbInstr - 1) to a physical address using the
1348	* code TLB (must have a valid entry for that address) and scan the ranges to
1349	* locate the corresponding opcodes. Probably.
1350	*/
1351	struct IEMTBOPCODERANGE
1352	{
1353	/** Offset within pabOpcodes. */
1354	uint16_t offOpcodes;
1355	/** Number of bytes. */
1356	uint16_t cbOpcodes;
1357	/** The page offset. */
1358	RT_GCC_EXTENSION
1359	uint16_t offPhysPage : 12;
1360	/** Unused bits. */
1361	RT_GCC_EXTENSION
1362	uint16_t u2Unused : 2;
1363	/** Index into GCPhysPc + aGCPhysPages for the physical page address. */
1364	RT_GCC_EXTENSION
1365	uint16_t idxPhysPage : 2;
1366	} aRanges[8];
1367
1368	/** Physical pages that this TB covers.
1369	* The GCPhysPc w/o page offset is element zero, so starting here with 1. */
1370	RTGCPHYS aGCPhysPages[2];
1371	} IEMTB;
1372	#pragma pack()
1373	AssertCompileMemberAlignment(IEMTB, GCPhysPc, sizeof(RTGCPHYS));
1374	AssertCompileMemberAlignment(IEMTB, Thrd, sizeof(void *));
1375	AssertCompileMemberAlignment(IEMTB, pabOpcodes, sizeof(void *));
1376	AssertCompileMemberAlignment(IEMTB, pDbgInfo, sizeof(void *));
1377	AssertCompileMemberAlignment(IEMTB, aGCPhysPages, sizeof(RTGCPHYS));
1378	AssertCompileMemberOffset(IEMTB, aRanges, 64);
1379	AssertCompileMemberSize(IEMTB, aRanges[0], 6);
1380	#if 1
1381	AssertCompileSize(IEMTB, 128);
1382	# define IEMTB_SIZE_IS_POWER_OF_TWO /*< The IEMTB size is a power of two. /
1383	#else
1384	AssertCompileSize(IEMTB, 168);
1385	# undef IEMTB_SIZE_IS_POWER_OF_TWO
1386	#endif
1387
1388	/** Pointer to a translation block. */
1389	typedef IEMTB *PIEMTB;
1390	/** Pointer to a const translation block. */
1391	typedef IEMTB const *PCIEMTB;
1392
1393	/** Gets address of the given TB lookup table entry. */
1394	#define IEMTB_GET_TB_LOOKUP_TAB_ENTRY(a_pTb, a_idx) \
1395	((PIEMTB )&(a_pTb)->pabOpcodes[-(int)((a_pTb)->cTbLookupEntries - (a_idx)) sizeof(PIEMTB)])
1396
1397	/**
1398	* Gets the physical address for a TB opcode range.
1399	*/
1400	DECL_FORCE_INLINE(RTGCPHYS) iemTbGetRangePhysPageAddr(PCIEMTB pTb, uint8_t idxRange)
1401	{
1402	Assert(idxRange < RT_MIN(pTb->cRanges, RT_ELEMENTS(pTb->aRanges)));
1403	uint8_t const idxPage = pTb->aRanges[idxRange].idxPhysPage;
1404	Assert(idxPage <= RT_ELEMENTS(pTb->aGCPhysPages));
1405	if (idxPage == 0)
1406	return pTb->GCPhysPc & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
1407	Assert(!(pTb->aGCPhysPages[idxPage - 1] & GUEST_PAGE_OFFSET_MASK));
1408	return pTb->aGCPhysPages[idxPage - 1];
1409	}
1410
1411
1412	/**
1413	* A chunk of memory in the TB allocator.
1414	*/
1415	typedef struct IEMTBCHUNK
1416	{
1417	/** Pointer to the translation blocks in this chunk. */
1418	PIEMTB paTbs;
1419	#ifdef IN_RING0
1420	/** Allocation handle. */
1421	RTR0MEMOBJ hMemObj;
1422	#endif
1423	} IEMTBCHUNK;
1424
1425	/**
1426	* A per-CPU translation block allocator.
1427	*
1428	* Because of how the IEMTBCACHE uses the lower 6 bits of the TB address to keep
1429	* the length of the collision list, and of course also for cache line alignment
1430	* reasons, the TBs must be allocated with at least 64-byte alignment.
1431	* Memory is there therefore allocated using one of the page aligned allocators.
1432	*
1433	*
1434	* To avoid wasting too much memory, it is allocated piecemeal as needed,
1435	* in chunks (IEMTBCHUNK) of 2 MiB or more. The TB has an 8-bit chunk index
1436	* that enables us to quickly calculate the allocation bitmap position when
1437	* freeing the translation block.
1438	*/
1439	typedef struct IEMTBALLOCATOR
1440	{
1441	/** Magic value (IEMTBALLOCATOR_MAGIC). */
1442	uint32_t uMagic;
1443
1444	#ifdef IEMTB_SIZE_IS_POWER_OF_TWO
1445	/** Mask corresponding to cTbsPerChunk - 1. */
1446	uint32_t fChunkMask;
1447	/** Shift count corresponding to cTbsPerChunk. */
1448	uint8_t cChunkShift;
1449	#else
1450	uint32_t uUnused;
1451	uint8_t bUnused;
1452	#endif
1453	/** Number of chunks we're allowed to allocate. */
1454	uint8_t cMaxChunks;
1455	/** Number of chunks currently populated. */
1456	uint16_t cAllocatedChunks;
1457	/** Number of translation blocks per chunk. */
1458	uint32_t cTbsPerChunk;
1459	/** Chunk size. */
1460	uint32_t cbPerChunk;
1461
1462	/** The maximum number of TBs. */
1463	uint32_t cMaxTbs;
1464	/** Total number of TBs in the populated chunks.
1465	* (cAllocatedChunks * cTbsPerChunk) */
1466	uint32_t cTotalTbs;
1467	/** The current number of TBs in use.
1468	* The number of free TBs: cAllocatedTbs - cInUseTbs; */
1469	uint32_t cInUseTbs;
1470	/** Statistics: Number of the cInUseTbs that are native ones. */
1471	uint32_t cNativeTbs;
1472	/** Statistics: Number of the cInUseTbs that are threaded ones. */
1473	uint32_t cThreadedTbs;
1474
1475	/** Where to start pruning TBs from when we're out.
1476	* See iemTbAllocatorAllocSlow for details. */
1477	uint32_t iPruneFrom;
1478	/** Hint about which bit to start scanning the bitmap from. */
1479	uint32_t iStartHint;
1480	/** Where to start pruning native TBs from when we're out of executable memory.
1481	* See iemTbAllocatorFreeupNativeSpace for details. */
1482	uint32_t iPruneNativeFrom;
1483	uint32_t uPadding;
1484
1485	/** Statistics: Number of TB allocation calls. */
1486	STAMCOUNTER StatAllocs;
1487	/** Statistics: Number of TB free calls. */
1488	STAMCOUNTER StatFrees;
1489	/** Statistics: Time spend pruning. */
1490	STAMPROFILE StatPrune;
1491	/** Statistics: Time spend pruning native TBs. */
1492	STAMPROFILE StatPruneNative;
1493
1494	/** The delayed free list (see iemTbAlloctorScheduleForFree). */
1495	PIEMTB pDelayedFreeHead;
1496
1497	/** Allocation chunks. */
1498	IEMTBCHUNK aChunks[256];
1499
1500	/** Allocation bitmap for all possible chunk chunks. */
1501	RT_FLEXIBLE_ARRAY_EXTENSION
1502	uint64_t bmAllocated[RT_FLEXIBLE_ARRAY];
1503	} IEMTBALLOCATOR;
1504	/** Pointer to a TB allocator. */
1505	typedef struct IEMTBALLOCATOR *PIEMTBALLOCATOR;
1506
1507	/** Magic value for the TB allocator (Emmet Harley Cohen). */
1508	#define IEMTBALLOCATOR_MAGIC UINT32_C(0x19900525)
1509
1510
1511	/**
1512	* A per-CPU translation block cache (hash table).
1513	*
1514	* The hash table is allocated once during IEM initialization and size double
1515	* the max TB count, rounded up to the nearest power of two (so we can use and
1516	* AND mask rather than a rest division when hashing).
1517	*/
1518	typedef struct IEMTBCACHE
1519	{
1520	/** Magic value (IEMTBCACHE_MAGIC). */
1521	uint32_t uMagic;
1522	/** Size of the hash table. This is a power of two. */
1523	uint32_t cHash;
1524	/** The mask corresponding to cHash. */
1525	uint32_t uHashMask;
1526	uint32_t uPadding;
1527
1528	/** @name Statistics
1529	* @{ */
1530	/** Number of collisions ever. */
1531	STAMCOUNTER cCollisions;
1532
1533	/** Statistics: Number of TB lookup misses. */
1534	STAMCOUNTER cLookupMisses;
1535	/** Statistics: Number of TB lookup hits via hash table (debug only). */
1536	STAMCOUNTER cLookupHits;
1537	/** Statistics: Number of TB lookup hits via TB associated lookup table (debug only). */
1538	STAMCOUNTER cLookupHitsViaTbLookupTable;
1539	STAMCOUNTER auPadding2[2];
1540	/** Statistics: Collision list length pruning. */
1541	STAMPROFILE StatPrune;
1542	/** @} */
1543
1544	/** The hash table itself.
1545	* @note The lower 6 bits of the pointer is used for keeping the collision
1546	* list length, so we can take action when it grows too long.
1547	* This works because TBs are allocated using a 64 byte (or
1548	* higher) alignment from page aligned chunks of memory, so the lower
1549	* 6 bits of the address will always be zero.
1550	* See IEMTBCACHE_PTR_COUNT_MASK, IEMTBCACHE_PTR_MAKE and friends.
1551	*/
1552	RT_FLEXIBLE_ARRAY_EXTENSION
1553	PIEMTB apHash[RT_FLEXIBLE_ARRAY];
1554	} IEMTBCACHE;
1555	/** Pointer to a per-CPU translation block cahce. */
1556	typedef IEMTBCACHE *PIEMTBCACHE;
1557
1558	/** Magic value for IEMTBCACHE (Johnny O'Neal). */
1559	#define IEMTBCACHE_MAGIC UINT32_C(0x19561010)
1560
1561	/** The collision count mask for IEMTBCACHE::apHash entries. */
1562	#define IEMTBCACHE_PTR_COUNT_MASK ((uintptr_t)0x3f)
1563	/** The max collision count for IEMTBCACHE::apHash entries before pruning. */
1564	#define IEMTBCACHE_PTR_MAX_COUNT ((uintptr_t)0x30)
1565	/** Combine a TB pointer and a collision list length into a value for an
1566	* IEMTBCACHE::apHash entry. */
1567	#define IEMTBCACHE_PTR_MAKE(a_pTb, a_cCount) (PIEMTB)((uintptr_t)(a_pTb) \| (a_cCount))
1568	/** Combine a TB pointer and a collision list length into a value for an
1569	* IEMTBCACHE::apHash entry. */
1570	#define IEMTBCACHE_PTR_GET_TB(a_pHashEntry) (PIEMTB)((uintptr_t)(a_pHashEntry) & ~IEMTBCACHE_PTR_COUNT_MASK)
1571	/** Combine a TB pointer and a collision list length into a value for an
1572	* IEMTBCACHE::apHash entry. */
1573	#define IEMTBCACHE_PTR_GET_COUNT(a_pHashEntry) ((uintptr_t)(a_pHashEntry) & IEMTBCACHE_PTR_COUNT_MASK)
1574
1575	/**
1576	* Calculates the hash table slot for a TB from physical PC address and TB flags.
1577	*/
1578	#define IEMTBCACHE_HASH(a_paCache, a_fTbFlags, a_GCPhysPc) \
1579	IEMTBCACHE_HASH_NO_KEY_MASK(a_paCache, (a_fTbFlags) & IEMTB_F_KEY_MASK, a_GCPhysPc)
1580
1581	/**
1582	* Calculates the hash table slot for a TB from physical PC address and TB
1583	* flags, ASSUMING the caller has applied IEMTB_F_KEY_MASK to @a a_fTbFlags.
1584	*/
1585	#define IEMTBCACHE_HASH_NO_KEY_MASK(a_paCache, a_fTbFlags, a_GCPhysPc) \
1586	(((uint32_t)(a_GCPhysPc) ^ (a_fTbFlags)) & (a_paCache)->uHashMask)
1587
1588
1589	/** @name IEMBRANCHED_F_XXX - Branched indicator (IEMCPU::fTbBranched).
1590	*
1591	* These flags parallels the main IEM_CIMPL_F_BRANCH_XXX flags.
1592	*
1593	* @{ */
1594	/** Value if no branching happened recently. */
1595	#define IEMBRANCHED_F_NO UINT8_C(0x00)
1596	/** Flag set if direct branch, clear if absolute or indirect. */
1597	#define IEMBRANCHED_F_DIRECT UINT8_C(0x01)
1598	/** Flag set if indirect branch, clear if direct or relative. */
1599	#define IEMBRANCHED_F_INDIRECT UINT8_C(0x02)
1600	/** Flag set if relative branch, clear if absolute or indirect. */
1601	#define IEMBRANCHED_F_RELATIVE UINT8_C(0x04)
1602	/** Flag set if conditional branch, clear if unconditional. */
1603	#define IEMBRANCHED_F_CONDITIONAL UINT8_C(0x08)
1604	/** Flag set if it's a far branch. */
1605	#define IEMBRANCHED_F_FAR UINT8_C(0x10)
1606	/** Flag set if the stack pointer is modified. */
1607	#define IEMBRANCHED_F_STACK UINT8_C(0x20)
1608	/** Flag set if the stack pointer and (maybe) the stack segment are modified. */
1609	#define IEMBRANCHED_F_STACK_FAR UINT8_C(0x40)
1610	/** Flag set (by IEM_MC_REL_JMP_XXX) if it's a zero bytes relative jump. */
1611	#define IEMBRANCHED_F_ZERO UINT8_C(0x80)
1612	/** @} */
1613
1614
1615	/**
1616	* The per-CPU IEM state.
1617	*/
1618	typedef struct IEMCPU
1619	{
1620	/** Info status code that needs to be propagated to the IEM caller.
1621	* This cannot be passed internally, as it would complicate all success
1622	* checks within the interpreter making the code larger and almost impossible
1623	* to get right. Instead, we'll store status codes to pass on here. Each
1624	* source of these codes will perform appropriate sanity checks. */
1625	int32_t rcPassUp; /* 0x00 */
1626	/** Execution flag, IEM_F_XXX. */
1627	uint32_t fExec; /* 0x04 */
1628
1629	/** @name Decoder state.
1630	* @{ */
1631	#ifdef IEM_WITH_CODE_TLB
1632	/** The offset of the next instruction byte. */
1633	uint32_t offInstrNextByte; /* 0x08 */
1634	/** The number of bytes available at pbInstrBuf for the current instruction.
1635	* This takes the max opcode length into account so that doesn't need to be
1636	* checked separately. */
1637	uint32_t cbInstrBuf; /* 0x0c */
1638	/** Pointer to the page containing RIP, user specified buffer or abOpcode.
1639	* This can be NULL if the page isn't mappable for some reason, in which
1640	* case we'll do fallback stuff.
1641	*
1642	* If we're executing an instruction from a user specified buffer,
1643	* IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
1644	* aligned pointer but pointer to the user data.
1645	*
1646	* For instructions crossing pages, this will start on the first page and be
1647	* advanced to the next page by the time we've decoded the instruction. This
1648	* therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
1649	*/
1650	uint8_t const pbInstrBuf; / 0x10 */
1651	# if ARCH_BITS == 32
1652	uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
1653	# endif
1654	/** The program counter corresponding to pbInstrBuf.
1655	* This is set to a non-canonical address when we need to invalidate it. */
1656	uint64_t uInstrBufPc; /* 0x18 */
1657	/** The guest physical address corresponding to pbInstrBuf. */
1658	RTGCPHYS GCPhysInstrBuf; /* 0x20 */
1659	/** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
1660	* This takes the CS segment limit into account.
1661	* @note Set to zero when the code TLB is flushed to trigger TLB reload. */
1662	uint16_t cbInstrBufTotal; /* 0x28 */
1663	/** Offset into pbInstrBuf of the first byte of the current instruction.
1664	* Can be negative to efficiently handle cross page instructions. */
1665	int16_t offCurInstrStart; /* 0x2a */
1666
1667	# ifndef IEM_WITH_OPAQUE_DECODER_STATE
1668	/** The prefix mask (IEM_OP_PRF_XXX). */
1669	uint32_t fPrefixes; /* 0x2c */
1670	/** The extra REX ModR/M register field bit (REX.R << 3). */
1671	uint8_t uRexReg; /* 0x30 */
1672	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
1673	* (REX.B << 3). */
1674	uint8_t uRexB; /* 0x31 */
1675	/** The extra REX SIB index field bit (REX.X << 3). */
1676	uint8_t uRexIndex; /* 0x32 */
1677
1678	/** The effective segment register (X86_SREG_XXX). */
1679	uint8_t iEffSeg; /* 0x33 */
1680
1681	/** The offset of the ModR/M byte relative to the start of the instruction. */
1682	uint8_t offModRm; /* 0x34 */
1683
1684	# ifdef IEM_WITH_CODE_TLB_AND_OPCODE_BUF
1685	/** The current offset into abOpcode. */
1686	uint8_t offOpcode; /* 0x35 */
1687	# else
1688	uint8_t bUnused; /* 0x35 */
1689	# endif
1690	# else /* IEM_WITH_OPAQUE_DECODER_STATE */
1691	uint8_t abOpaqueDecoderPart1[0x36 - 0x2c];
1692	# endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1693
1694	#else /* !IEM_WITH_CODE_TLB */
1695	# ifndef IEM_WITH_OPAQUE_DECODER_STATE
1696	/** The size of what has currently been fetched into abOpcode. */
1697	uint8_t cbOpcode; /* 0x08 */
1698	/** The current offset into abOpcode. */
1699	uint8_t offOpcode; /* 0x09 */
1700	/** The offset of the ModR/M byte relative to the start of the instruction. */
1701	uint8_t offModRm; /* 0x0a */
1702
1703	/** The effective segment register (X86_SREG_XXX). */
1704	uint8_t iEffSeg; /* 0x0b */
1705
1706	/** The prefix mask (IEM_OP_PRF_XXX). */
1707	uint32_t fPrefixes; /* 0x0c */
1708	/** The extra REX ModR/M register field bit (REX.R << 3). */
1709	uint8_t uRexReg; /* 0x10 */
1710	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
1711	* (REX.B << 3). */
1712	uint8_t uRexB; /* 0x11 */
1713	/** The extra REX SIB index field bit (REX.X << 3). */
1714	uint8_t uRexIndex; /* 0x12 */
1715
1716	# else /* IEM_WITH_OPAQUE_DECODER_STATE */
1717	uint8_t abOpaqueDecoderPart1[0x13 - 0x08];
1718	# endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1719	#endif /* !IEM_WITH_CODE_TLB */
1720
1721	#ifndef IEM_WITH_OPAQUE_DECODER_STATE
1722	/** The effective operand mode. */
1723	IEMMODE enmEffOpSize; /* 0x36, 0x13 */
1724	/** The default addressing mode. */
1725	IEMMODE enmDefAddrMode; /* 0x37, 0x14 */
1726	/** The effective addressing mode. */
1727	IEMMODE enmEffAddrMode; /* 0x38, 0x15 */
1728	/** The default operand mode. */
1729	IEMMODE enmDefOpSize; /* 0x39, 0x16 */
1730
1731	/** Prefix index (VEX.pp) for two byte and three byte tables. */
1732	uint8_t idxPrefix; /* 0x3a, 0x17 */
1733	/** 3rd VEX/EVEX/XOP register.
1734	* Please use IEM_GET_EFFECTIVE_VVVV to access. */
1735	uint8_t uVex3rdReg; /* 0x3b, 0x18 */
1736	/** The VEX/EVEX/XOP length field. */
1737	uint8_t uVexLength; /* 0x3c, 0x19 */
1738	/** Additional EVEX stuff. */
1739	uint8_t fEvexStuff; /* 0x3d, 0x1a */
1740
1741	# ifndef IEM_WITH_CODE_TLB
1742	/** Explicit alignment padding. */
1743	uint8_t abAlignment2a[1]; /* 0x1b */
1744	# endif
1745	/** The FPU opcode (FOP). */
1746	uint16_t uFpuOpcode; /* 0x3e, 0x1c */
1747	# ifndef IEM_WITH_CODE_TLB
1748	/** Explicit alignment padding. */
1749	uint8_t abAlignment2b[2]; /* 0x1e */
1750	# endif
1751
1752	/** The opcode bytes. */
1753	uint8_t abOpcode[15]; /* 0x40, 0x20 */
1754	/** Explicit alignment padding. */
1755	# ifdef IEM_WITH_CODE_TLB
1756	//uint8_t abAlignment2c[0x4f - 0x4f]; /* 0x4f */
1757	# else
1758	uint8_t abAlignment2c[0x4f - 0x2f]; /* 0x2f */
1759	# endif
1760
1761	#else /* IEM_WITH_OPAQUE_DECODER_STATE */
1762	# ifdef IEM_WITH_CODE_TLB
1763	uint8_t abOpaqueDecoderPart2[0x4f - 0x36];
1764	# else
1765	uint8_t abOpaqueDecoderPart2[0x4f - 0x13];
1766	# endif
1767	#endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1768	/** @} */
1769
1770
1771	/** The number of active guest memory mappings. */
1772	uint8_t cActiveMappings; /* 0x4f, 0x4f */
1773
1774	/** Records for tracking guest memory mappings. */
1775	struct
1776	{
1777	/** The address of the mapped bytes. */
1778	R3R0PTRTYPE(void *) pv;
1779	/** The access flags (IEM_ACCESS_XXX).
1780	* IEM_ACCESS_INVALID if the entry is unused. */
1781	uint32_t fAccess;
1782	#if HC_ARCH_BITS == 64
1783	uint32_t u32Alignment4; /*< Alignment padding. /
1784	#endif
1785	} aMemMappings[3]; /* 0x50 LB 0x30 */
1786
1787	/** Locking records for the mapped memory. */
1788	union
1789	{
1790	PGMPAGEMAPLOCK Lock;
1791	uint64_t au64Padding[2];
1792	} aMemMappingLocks[3]; /* 0x80 LB 0x30 */
1793
1794	/** Bounce buffer info.
1795	* This runs in parallel to aMemMappings. */
1796	struct
1797	{
1798	/** The physical address of the first byte. */
1799	RTGCPHYS GCPhysFirst;
1800	/** The physical address of the second page. */
1801	RTGCPHYS GCPhysSecond;
1802	/** The number of bytes in the first page. */
1803	uint16_t cbFirst;
1804	/** The number of bytes in the second page. */
1805	uint16_t cbSecond;
1806	/** Whether it's unassigned memory. */
1807	bool fUnassigned;
1808	/** Explicit alignment padding. */
1809	bool afAlignment5[3];
1810	} aMemBbMappings[3]; /* 0xb0 LB 0x48 */
1811
1812	/** The flags of the current exception / interrupt. */
1813	uint32_t fCurXcpt; /* 0xf8 */
1814	/** The current exception / interrupt. */
1815	uint8_t uCurXcpt; /* 0xfc */
1816	/** Exception / interrupt recursion depth. */
1817	int8_t cXcptRecursions; /* 0xfb */
1818
1819	/** The next unused mapping index.
1820	* @todo try find room for this up with cActiveMappings. */
1821	uint8_t iNextMapping; /* 0xfd */
1822	uint8_t abAlignment7[1];
1823
1824	/** Bounce buffer storage.
1825	* This runs in parallel to aMemMappings and aMemBbMappings. */
1826	struct
1827	{
1828	uint8_t ab[512];
1829	} aBounceBuffers[3]; /* 0x100 LB 0x600 */
1830
1831
1832	/** Pointer set jump buffer - ring-3 context. */
1833	R3PTRTYPE(jmp_buf *) pJmpBufR3;
1834	/** Pointer set jump buffer - ring-0 context. */
1835	R0PTRTYPE(jmp_buf *) pJmpBufR0;
1836
1837	/** @todo Should move this near @a fCurXcpt later. */
1838	/** The CR2 for the current exception / interrupt. */
1839	uint64_t uCurXcptCr2;
1840	/** The error code for the current exception / interrupt. */
1841	uint32_t uCurXcptErr;
1842
1843	/** @name Statistics
1844	* @{ */
1845	/** The number of instructions we've executed. */
1846	uint32_t cInstructions;
1847	/** The number of potential exits. */
1848	uint32_t cPotentialExits;
1849	/** The number of bytes data or stack written (mostly for IEMExecOneEx).
1850	* This may contain uncommitted writes. */
1851	uint32_t cbWritten;
1852	/** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
1853	uint32_t cRetInstrNotImplemented;
1854	/** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
1855	uint32_t cRetAspectNotImplemented;
1856	/** Counts informational statuses returned (other than VINF_SUCCESS). */
1857	uint32_t cRetInfStatuses;
1858	/** Counts other error statuses returned. */
1859	uint32_t cRetErrStatuses;
1860	/** Number of times rcPassUp has been used. */
1861	uint32_t cRetPassUpStatus;
1862	/** Number of times RZ left with instruction commit pending for ring-3. */
1863	uint32_t cPendingCommit;
1864	/** Number of misaligned (host sense) atomic instruction accesses. */
1865	uint32_t cMisalignedAtomics;
1866	/** Number of long jumps. */
1867	uint32_t cLongJumps;
1868	/** @} */
1869
1870	/** @name Target CPU information.
1871	* @{ */
1872	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
1873	/** The target CPU. */
1874	uint8_t uTargetCpu;
1875	#else
1876	uint8_t bTargetCpuPadding;
1877	#endif
1878	/** For selecting assembly works matching the target CPU EFLAGS behaviour, see
1879	* IEMTARGETCPU_EFL_BEHAVIOR_XXX for values, with the 1st entry for when no
1880	* native host support and the 2nd for when there is.
1881	*
1882	* The two values are typically indexed by a g_CpumHostFeatures bit.
1883	*
1884	* This is for instance used for the BSF & BSR instructions where AMD and
1885	* Intel CPUs produce different EFLAGS. */
1886	uint8_t aidxTargetCpuEflFlavour[2];
1887
1888	/** The CPU vendor. */
1889	CPUMCPUVENDOR enmCpuVendor;
1890	/** @} */
1891
1892	/** @name Host CPU information.
1893	* @{ */
1894	/** The CPU vendor. */
1895	CPUMCPUVENDOR enmHostCpuVendor;
1896	/** @} */
1897
1898	/** Counts RDMSR \#GP(0) LogRel(). */
1899	uint8_t cLogRelRdMsr;
1900	/** Counts WRMSR \#GP(0) LogRel(). */
1901	uint8_t cLogRelWrMsr;
1902	/** Alignment padding. */
1903	uint8_t abAlignment9[42];
1904
1905	/** @name Recompilation
1906	* @{ */
1907	/** Pointer to the current translation block.
1908	* This can either be one being executed or one being compiled. */
1909	R3PTRTYPE(PIEMTB) pCurTbR3;
1910	#ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
1911	/** Frame pointer for the last native TB to execute. */
1912	R3PTRTYPE(void *) pvTbFramePointerR3;
1913	#else
1914	R3PTRTYPE(void *) pvUnusedR3;
1915	#endif
1916	/** Fixed TB used for threaded recompilation.
1917	* This is allocated once with maxed-out sizes and re-used afterwards. */
1918	R3PTRTYPE(PIEMTB) pThrdCompileTbR3;
1919	/** Pointer to the ring-3 TB cache for this EMT. */
1920	R3PTRTYPE(PIEMTBCACHE) pTbCacheR3;
1921	/** Pointer to the ring-3 TB lookup entry.
1922	* This either points to pTbLookupEntryDummyR3 or an actually lookuptable
1923	* entry, thus it can always safely be used w/o NULL checking. */
1924	R3PTRTYPE(PIEMTB *) ppTbLookupEntryR3;
1925	/** The PC (RIP) at the start of pCurTbR3/pCurTbR0.
1926	* The TBs are based on physical addresses, so this is needed to correleated
1927	* RIP to opcode bytes stored in the TB (AMD-V / VT-x). */
1928	uint64_t uCurTbStartPc;
1929	/** Number of threaded TBs executed. */
1930	uint64_t cTbExecThreaded;
1931	/** Number of native TBs executed. */
1932	uint64_t cTbExecNative;
1933	/** Whether we need to check the opcode bytes for the current instruction.
1934	* This is set by a previous instruction if it modified memory or similar. */
1935	bool fTbCheckOpcodes;
1936	/** Indicates whether and how we just branched - IEMBRANCHED_F_XXX. */
1937	uint8_t fTbBranched;
1938	/** Set when GCPhysInstrBuf is updated because of a page crossing. */
1939	bool fTbCrossedPage;
1940	/** Whether to end the current TB. */
1941	bool fEndTb;
1942	/** Number of instructions before we need emit an IRQ check call again.
1943	* This helps making sure we don't execute too long w/o checking for
1944	* interrupts and immediately following instructions that may enable
1945	* interrupts (e.g. POPF, IRET, STI). With STI an additional hack is
1946	* required to make sure we check following the next instruction as well, see
1947	* fTbCurInstrIsSti. */
1948	uint8_t cInstrTillIrqCheck;
1949	/** Indicates that the current instruction is an STI. This is set by the
1950	* iemCImpl_sti code and subsequently cleared by the recompiler. */
1951	bool fTbCurInstrIsSti;
1952	/** The size of the IEMTB::pabOpcodes allocation in pThrdCompileTbR3. */
1953	uint16_t cbOpcodesAllocated;
1954	/** The current instruction number in a native TB.
1955	* This is set by code that may trigger an unexpected TB exit (throw/longjmp)
1956	* and will be picked up by the TB execution loop. Only used when
1957	* IEMNATIVE_WITH_INSTRUCTION_COUNTING is defined. */
1958	uint8_t idxTbCurInstr;
1959	/** Spaced reserved for recompiler data / alignment. */
1960	bool afRecompilerStuff1[3];
1961	/** The virtual sync time at the last timer poll call. */
1962	uint32_t msRecompilerPollNow;
1963	/** The IEMTB::cUsed value when to attempt native recompilation of a TB. */
1964	uint32_t uTbNativeRecompileAtUsedCount;
1965	/** The IEM_CIMPL_F_XXX mask for the current instruction. */
1966	uint32_t fTbCurInstr;
1967	/** The IEM_CIMPL_F_XXX mask for the previous instruction. */
1968	uint32_t fTbPrevInstr;
1969	/** Strict: Tracking skipped EFLAGS calculations. Any bits set here are
1970	* currently not up to date in EFLAGS. */
1971	uint32_t fSkippingEFlags;
1972	/** Previous GCPhysInstrBuf value - only valid if fTbCrossedPage is set. */
1973	RTGCPHYS GCPhysInstrBufPrev;
1974	/** Pointer to the ring-3 TB allocator for this EMT. */
1975	R3PTRTYPE(PIEMTBALLOCATOR) pTbAllocatorR3;
1976	/** Pointer to the ring-3 executable memory allocator for this EMT. */
1977	R3PTRTYPE(struct IEMEXECMEMALLOCATOR *) pExecMemAllocatorR3;
1978	/** Pointer to the native recompiler state for ring-3. */
1979	R3PTRTYPE(struct IEMRECOMPILERSTATE *) pNativeRecompilerStateR3;
1980	/** Dummy entry for ppTbLookupEntryR3. */
1981	R3PTRTYPE(PIEMTB) pTbLookupEntryDummyR3;
1982
1983	/** Dummy TLB entry used for accesses to pages with databreakpoints. */
1984	IEMTLBENTRY DataBreakpointTlbe;
1985
1986	/** Threaded TB statistics: Times TB execution was broken off before reaching the end. */
1987	STAMCOUNTER StatTbThreadedExecBreaks;
1988	/** Statistics: Times BltIn_CheckIrq breaks out of the TB. */
1989	STAMCOUNTER StatCheckIrqBreaks;
1990	/** Statistics: Times BltIn_CheckMode breaks out of the TB. */
1991	STAMCOUNTER StatCheckModeBreaks;
1992	/** Threaded TB statistics: Times execution break on call with lookup entries. */
1993	STAMCOUNTER StatTbThreadedExecBreaksWithLookup;
1994	/** Threaded TB statistics: Times execution break on call without lookup entries. */
1995	STAMCOUNTER StatTbThreadedExecBreaksWithoutLookup;
1996	/** Statistics: Times a post jump target check missed and had to find new TB. */
1997	STAMCOUNTER StatCheckBranchMisses;
1998	/** Statistics: Times a jump or page crossing required a TB with CS.LIM checking. */
1999	STAMCOUNTER StatCheckNeedCsLimChecking;
2000	/** Statistics: Times a loop was detected within a TB.. */
2001	STAMCOUNTER StatTbLoopInTbDetected;
2002	/** Exec memory allocator statistics: Number of times allocaintg executable memory failed. */
2003	STAMCOUNTER StatNativeExecMemInstrBufAllocFailed;
2004	/** Native TB statistics: Number of fully recompiled TBs. */
2005	STAMCOUNTER StatNativeFullyRecompiledTbs;
2006	/** TB statistics: Number of instructions per TB. */
2007	STAMPROFILE StatTbInstr;
2008	/** TB statistics: Number of TB lookup table entries per TB. */
2009	STAMPROFILE StatTbLookupEntries;
2010	/** Threaded TB statistics: Number of calls per TB. */
2011	STAMPROFILE StatTbThreadedCalls;
2012	/** Native TB statistics: Native code size per TB. */
2013	STAMPROFILE StatTbNativeCode;
2014	/** Native TB statistics: Profiling native recompilation. */
2015	STAMPROFILE StatNativeRecompilation;
2016	/** Native TB statistics: Number of calls per TB that were recompiled properly. */
2017	STAMPROFILE StatNativeCallsRecompiled;
2018	/** Native TB statistics: Number of threaded calls per TB that weren't recompiled. */
2019	STAMPROFILE StatNativeCallsThreaded;
2020	/** Native recompiled execution: TLB hits for data fetches. */
2021	STAMCOUNTER StatNativeTlbHitsForFetch;
2022	/** Native recompiled execution: TLB hits for data stores. */
2023	STAMCOUNTER StatNativeTlbHitsForStore;
2024	/** Native recompiled execution: TLB hits for stack accesses. */
2025	STAMCOUNTER StatNativeTlbHitsForStack;
2026	/** Native recompiled execution: TLB hits for mapped accesses. */
2027	STAMCOUNTER StatNativeTlbHitsForMapped;
2028	/** Native recompiled execution: Code TLB misses for new page. */
2029	STAMCOUNTER StatNativeCodeTlbMissesNewPage;
2030	/** Native recompiled execution: Code TLB hits for new page. */
2031	STAMCOUNTER StatNativeCodeTlbHitsForNewPage;
2032	/** Native recompiled execution: Code TLB misses for new page with offset. */
2033	STAMCOUNTER StatNativeCodeTlbMissesNewPageWithOffset;
2034	/** Native recompiled execution: Code TLB hits for new page with offset. */
2035	STAMCOUNTER StatNativeCodeTlbHitsForNewPageWithOffset;
2036
2037	/** Native recompiler: Number of calls to iemNativeRegAllocFindFree. */
2038	STAMCOUNTER StatNativeRegFindFree;
2039	/** Native recompiler: Number of times iemNativeRegAllocFindFree needed
2040	* to free a variable. */
2041	STAMCOUNTER StatNativeRegFindFreeVar;
2042	/** Native recompiler: Number of times iemNativeRegAllocFindFree did
2043	* not need to free any variables. */
2044	STAMCOUNTER StatNativeRegFindFreeNoVar;
2045	/** Native recompiler: Liveness info freed shadowed guest registers in
2046	* iemNativeRegAllocFindFree. */
2047	STAMCOUNTER StatNativeRegFindFreeLivenessUnshadowed;
2048	/** Native recompiler: Liveness info helped with the allocation in
2049	* iemNativeRegAllocFindFree. */
2050	STAMCOUNTER StatNativeRegFindFreeLivenessHelped;
2051
2052	/** Native recompiler: Number of times status flags calc has been skipped. */
2053	STAMCOUNTER StatNativeEflSkippedArithmetic;
2054	/** Native recompiler: Number of times status flags calc has been skipped. */
2055	STAMCOUNTER StatNativeEflSkippedLogical;
2056
2057	/** Native recompiler: Number of opportunities to skip EFLAGS.CF updating. */
2058	STAMCOUNTER StatNativeLivenessEflCfSkippable;
2059	/** Native recompiler: Number of opportunities to skip EFLAGS.PF updating. */
2060	STAMCOUNTER StatNativeLivenessEflPfSkippable;
2061	/** Native recompiler: Number of opportunities to skip EFLAGS.AF updating. */
2062	STAMCOUNTER StatNativeLivenessEflAfSkippable;
2063	/** Native recompiler: Number of opportunities to skip EFLAGS.ZF updating. */
2064	STAMCOUNTER StatNativeLivenessEflZfSkippable;
2065	/** Native recompiler: Number of opportunities to skip EFLAGS.SF updating. */
2066	STAMCOUNTER StatNativeLivenessEflSfSkippable;
2067	/** Native recompiler: Number of opportunities to skip EFLAGS.OF updating. */
2068	STAMCOUNTER StatNativeLivenessEflOfSkippable;
2069	/** Native recompiler: Number of required EFLAGS.CF updates. */
2070	STAMCOUNTER StatNativeLivenessEflCfRequired;
2071	/** Native recompiler: Number of required EFLAGS.PF updates. */
2072	STAMCOUNTER StatNativeLivenessEflPfRequired;
2073	/** Native recompiler: Number of required EFLAGS.AF updates. */
2074	STAMCOUNTER StatNativeLivenessEflAfRequired;
2075	/** Native recompiler: Number of required EFLAGS.ZF updates. */
2076	STAMCOUNTER StatNativeLivenessEflZfRequired;
2077	/** Native recompiler: Number of required EFLAGS.SF updates. */
2078	STAMCOUNTER StatNativeLivenessEflSfRequired;
2079	/** Native recompiler: Number of required EFLAGS.OF updates. */
2080	STAMCOUNTER StatNativeLivenessEflOfRequired;
2081	/** Native recompiler: Number of potentially delayable EFLAGS.CF updates. */
2082	STAMCOUNTER StatNativeLivenessEflCfDelayable;
2083	/** Native recompiler: Number of potentially delayable EFLAGS.PF updates. */
2084	STAMCOUNTER StatNativeLivenessEflPfDelayable;
2085	/** Native recompiler: Number of potentially delayable EFLAGS.AF updates. */
2086	STAMCOUNTER StatNativeLivenessEflAfDelayable;
2087	/** Native recompiler: Number of potentially delayable EFLAGS.ZF updates. */
2088	STAMCOUNTER StatNativeLivenessEflZfDelayable;
2089	/** Native recompiler: Number of potentially delayable EFLAGS.SF updates. */
2090	STAMCOUNTER StatNativeLivenessEflSfDelayable;
2091	/** Native recompiler: Number of potentially delayable EFLAGS.OF updates. */
2092	STAMCOUNTER StatNativeLivenessEflOfDelayable;
2093
2094	/** Native recompiler: Number of potential PC updates in total. */
2095	STAMCOUNTER StatNativePcUpdateTotal;
2096	/** Native recompiler: Number of PC updates which could be delayed. */
2097	STAMCOUNTER StatNativePcUpdateDelayed;
2098
2099	//#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
2100	/** Native recompiler: Number of calls to iemNativeSimdRegAllocFindFree. */
2101	STAMCOUNTER StatNativeSimdRegFindFree;
2102	/** Native recompiler: Number of times iemNativeSimdRegAllocFindFree needed
2103	* to free a variable. */
2104	STAMCOUNTER StatNativeSimdRegFindFreeVar;
2105	/** Native recompiler: Number of times iemNativeSimdRegAllocFindFree did
2106	* not need to free any variables. */
2107	STAMCOUNTER StatNativeSimdRegFindFreeNoVar;
2108	/** Native recompiler: Liveness info freed shadowed guest registers in
2109	* iemNativeSimdRegAllocFindFree. */
2110	STAMCOUNTER StatNativeSimdRegFindFreeLivenessUnshadowed;
2111	/** Native recompiler: Liveness info helped with the allocation in
2112	* iemNativeSimdRegAllocFindFree. */
2113	STAMCOUNTER StatNativeSimdRegFindFreeLivenessHelped;
2114
2115	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() checks. */
2116	STAMCOUNTER StatNativeMaybeDeviceNotAvailXcptCheckPotential;
2117	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() checks. */
2118	STAMCOUNTER StatNativeMaybeWaitDeviceNotAvailXcptCheckPotential;
2119	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() checks. */
2120	STAMCOUNTER StatNativeMaybeSseXcptCheckPotential;
2121	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() checks. */
2122	STAMCOUNTER StatNativeMaybeAvxXcptCheckPotential;
2123
2124	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() checks omitted. */
2125	STAMCOUNTER StatNativeMaybeDeviceNotAvailXcptCheckOmitted;
2126	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() checks omitted. */
2127	STAMCOUNTER StatNativeMaybeWaitDeviceNotAvailXcptCheckOmitted;
2128	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() checks omitted. */
2129	STAMCOUNTER StatNativeMaybeSseXcptCheckOmitted;
2130	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() checks omitted. */
2131	STAMCOUNTER StatNativeMaybeAvxXcptCheckOmitted;
2132	//#endif
2133
2134	/** Native recompiler: The TB finished executing completely without jumping to a an exit label.
2135	* Not availabe in release builds. */
2136	STAMCOUNTER StatNativeTbFinished;
2137	/** Native recompiler: The TB finished executing jumping to the ReturnBreak label. */
2138	STAMCOUNTER StatNativeTbExitReturnBreak;
2139	/** Native recompiler: The TB finished executing jumping to the ReturnBreakFF label. */
2140	STAMCOUNTER StatNativeTbExitReturnBreakFF;
2141	/** Native recompiler: The TB finished executing jumping to the ReturnWithFlags label. */
2142	STAMCOUNTER StatNativeTbExitReturnWithFlags;
2143	/** Native recompiler: The TB finished executing with other non-zero status. */
2144	STAMCOUNTER StatNativeTbExitReturnOtherStatus;
2145	/** Native recompiler: The TB finished executing via throw / long jump. */
2146	STAMCOUNTER StatNativeTbExitLongJump;
2147	/** Native recompiler: The TB finished executing jumping to the ReturnBreak
2148	* label, but directly jumped to the next TB, scenario \#1 w/o IRQ checks. */
2149	STAMCOUNTER StatNativeTbExitDirectLinking1NoIrq;
2150	/** Native recompiler: The TB finished executing jumping to the ReturnBreak
2151	* label, but directly jumped to the next TB, scenario \#1 with IRQ checks. */
2152	STAMCOUNTER StatNativeTbExitDirectLinking1Irq;
2153	/** Native recompiler: The TB finished executing jumping to the ReturnBreak
2154	* label, but directly jumped to the next TB, scenario \#1 w/o IRQ checks. */
2155	STAMCOUNTER StatNativeTbExitDirectLinking2NoIrq;
2156	/** Native recompiler: The TB finished executing jumping to the ReturnBreak
2157	* label, but directly jumped to the next TB, scenario \#2 with IRQ checks. */
2158	STAMCOUNTER StatNativeTbExitDirectLinking2Irq;
2159
2160	/** Native recompiler: The TB finished executing jumping to the RaiseDe label. */
2161	STAMCOUNTER StatNativeTbExitRaiseDe;
2162	/** Native recompiler: The TB finished executing jumping to the RaiseUd label. */
2163	STAMCOUNTER StatNativeTbExitRaiseUd;
2164	/** Native recompiler: The TB finished executing jumping to the RaiseSseRelated label. */
2165	STAMCOUNTER StatNativeTbExitRaiseSseRelated;
2166	/** Native recompiler: The TB finished executing jumping to the RaiseAvxRelated label. */
2167	STAMCOUNTER StatNativeTbExitRaiseAvxRelated;
2168	/** Native recompiler: The TB finished executing jumping to the RaiseSseAvxFpRelated label. */
2169	STAMCOUNTER StatNativeTbExitRaiseSseAvxFpRelated;
2170	/** Native recompiler: The TB finished executing jumping to the RaiseNm label. */
2171	STAMCOUNTER StatNativeTbExitRaiseNm;
2172	/** Native recompiler: The TB finished executing jumping to the RaiseGp0 label. */
2173	STAMCOUNTER StatNativeTbExitRaiseGp0;
2174	/** Native recompiler: The TB finished executing jumping to the RaiseMf label. */
2175	STAMCOUNTER StatNativeTbExitRaiseMf;
2176	/** Native recompiler: The TB finished executing jumping to the RaiseXf label. */
2177	STAMCOUNTER StatNativeTbExitRaiseXf;
2178	/** Native recompiler: The TB finished executing jumping to the ObsoleteTb label. */
2179	STAMCOUNTER StatNativeTbExitObsoleteTb;
2180
2181	/** Native recompiler: Failure situations with direct linking scenario \#1.
2182	* Counter with StatNativeTbExitReturnBreak. Not in release builds.
2183	* @{ */
2184	STAMCOUNTER StatNativeTbExitDirectLinking1NoTb;
2185	STAMCOUNTER StatNativeTbExitDirectLinking1MismatchGCPhysPc;
2186	STAMCOUNTER StatNativeTbExitDirectLinking1MismatchFlags;
2187	STAMCOUNTER StatNativeTbExitDirectLinking1PendingIrq;
2188	/** @} */
2189
2190	/** Native recompiler: Failure situations with direct linking scenario \#2.
2191	* Counter with StatNativeTbExitReturnBreak. Not in release builds.
2192	* @{ */
2193	STAMCOUNTER StatNativeTbExitDirectLinking2NoTb;
2194	STAMCOUNTER StatNativeTbExitDirectLinking2MismatchGCPhysPc;
2195	STAMCOUNTER StatNativeTbExitDirectLinking2MismatchFlags;
2196	STAMCOUNTER StatNativeTbExitDirectLinking2PendingIrq;
2197	/** @} */
2198
2199	/** iemMemMap and iemMemMapJmp statistics.
2200	* @{ */
2201	STAMCOUNTER StatMemMapJmp;
2202	STAMCOUNTER StatMemMapNoJmp;
2203	STAMCOUNTER StatMemBounceBufferCrossPage;
2204	STAMCOUNTER StatMemBounceBufferMapPhys;
2205	/** @} */
2206
2207	uint64_t au64Padding[5];
2208	/** @} */
2209
2210	/** Data TLB.
2211	* @remarks Must be 64-byte aligned. */
2212	IEMTLB DataTlb;
2213	/** Instruction TLB.
2214	* @remarks Must be 64-byte aligned. */
2215	IEMTLB CodeTlb;
2216
2217	/** Exception statistics. */
2218	STAMCOUNTER aStatXcpts[32];
2219	/** Interrupt statistics. */
2220	uint32_t aStatInts[256];
2221
2222	#if defined(VBOX_WITH_STATISTICS) && !defined(DOXYGEN_RUNNING) && !defined(IEM_WITHOUT_INSTRUCTION_STATS)
2223	/** Instruction statistics for ring-0/raw-mode. */
2224	IEMINSTRSTATS StatsRZ;
2225	/** Instruction statistics for ring-3. */
2226	IEMINSTRSTATS StatsR3;
2227	# ifdef VBOX_WITH_IEM_RECOMPILER
2228	/** Statistics per threaded function call.
2229	* Updated by both the threaded and native recompilers. */
2230	uint32_t acThreadedFuncStats[0x6000 /24576/];
2231	# endif
2232	#endif
2233	} IEMCPU;
2234	AssertCompileMemberOffset(IEMCPU, cActiveMappings, 0x4f);
2235	AssertCompileMemberAlignment(IEMCPU, aMemMappings, 16);
2236	AssertCompileMemberAlignment(IEMCPU, aMemMappingLocks, 16);
2237	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 64);
2238	AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
2239	AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
2240
2241	/** Pointer to the per-CPU IEM state. */
2242	typedef IEMCPU *PIEMCPU;
2243	/** Pointer to the const per-CPU IEM state. */
2244	typedef IEMCPU const *PCIEMCPU;
2245
2246
2247	/** @def IEM_GET_CTX
2248	* Gets the guest CPU context for the calling EMT.
2249	* @returns PCPUMCTX
2250	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2251	*/
2252	#define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
2253
2254	/** @def IEM_CTX_ASSERT
2255	* Asserts that the @a a_fExtrnMbz is present in the CPU context.
2256	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2257	* @param a_fExtrnMbz The mask of CPUMCTX_EXTRN_XXX flags that must be zero.
2258	*/
2259	#define IEM_CTX_ASSERT(a_pVCpu, a_fExtrnMbz) \
2260	AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
2261	("fExtrn=%#RX64 & fExtrnMbz=%#RX64 -> %#RX64\n", \
2262	(a_pVCpu)->cpum.GstCtx.fExtrn, (a_fExtrnMbz), (a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz) ))
2263
2264	/** @def IEM_CTX_IMPORT_RET
2265	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
2266	*
2267	* Will call the keep to import the bits as needed.
2268	*
2269	* Returns on import failure.
2270	*
2271	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2272	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
2273	*/
2274	#define IEM_CTX_IMPORT_RET(a_pVCpu, a_fExtrnImport) \
2275	do { \
2276	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
2277	{ /* likely */ } \
2278	else \
2279	{ \
2280	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
2281	AssertRCReturn(rcCtxImport, rcCtxImport); \
2282	} \
2283	} while (0)
2284
2285	/** @def IEM_CTX_IMPORT_NORET
2286	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
2287	*
2288	* Will call the keep to import the bits as needed.
2289	*
2290	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2291	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
2292	*/
2293	#define IEM_CTX_IMPORT_NORET(a_pVCpu, a_fExtrnImport) \
2294	do { \
2295	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
2296	{ /* likely */ } \
2297	else \
2298	{ \
2299	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
2300	AssertLogRelRC(rcCtxImport); \
2301	} \
2302	} while (0)
2303
2304	/** @def IEM_CTX_IMPORT_JMP
2305	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
2306	*
2307	* Will call the keep to import the bits as needed.
2308	*
2309	* Jumps on import failure.
2310	*
2311	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2312	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
2313	*/
2314	#define IEM_CTX_IMPORT_JMP(a_pVCpu, a_fExtrnImport) \
2315	do { \
2316	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
2317	{ /* likely */ } \
2318	else \
2319	{ \
2320	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
2321	AssertRCStmt(rcCtxImport, IEM_DO_LONGJMP(pVCpu, rcCtxImport)); \
2322	} \
2323	} while (0)
2324
2325
2326
2327	/** @def IEM_GET_TARGET_CPU
2328	* Gets the current IEMTARGETCPU value.
2329	* @returns IEMTARGETCPU value.
2330	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2331	*/
2332	#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
2333	# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
2334	#else
2335	# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
2336	#endif
2337
2338	/** @def IEM_GET_INSTR_LEN
2339	* Gets the instruction length. */
2340	#ifdef IEM_WITH_CODE_TLB
2341	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
2342	#else
2343	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
2344	#endif
2345
2346	/** @def IEM_TRY_SETJMP
2347	* Wrapper around setjmp / try, hiding all the ugly differences.
2348	*
2349	* @note Use with extreme care as this is a fragile macro.
2350	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2351	* @param a_rcTarget The variable that should receive the status code in case
2352	* of a longjmp/throw.
2353	*/
2354	/** @def IEM_TRY_SETJMP_AGAIN
2355	* For when setjmp / try is used again in the same variable scope as a previous
2356	* IEM_TRY_SETJMP invocation.
2357	*/
2358	/** @def IEM_CATCH_LONGJMP_BEGIN
2359	* Start wrapper for catch / setjmp-else.
2360	*
2361	* This will set up a scope.
2362	*
2363	* @note Use with extreme care as this is a fragile macro.
2364	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2365	* @param a_rcTarget The variable that should receive the status code in case
2366	* of a longjmp/throw.
2367	*/
2368	/** @def IEM_CATCH_LONGJMP_END
2369	* End wrapper for catch / setjmp-else.
2370	*
2371	* This will close the scope set up by IEM_CATCH_LONGJMP_BEGIN and clean up the
2372	* state.
2373	*
2374	* @note Use with extreme care as this is a fragile macro.
2375	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2376	*/
2377	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
2378	# ifdef IEM_WITH_THROW_CATCH
2379	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
2380	a_rcTarget = VINF_SUCCESS; \
2381	try
2382	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
2383	IEM_TRY_SETJMP(a_pVCpu, a_rcTarget)
2384	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
2385	catch (int rcThrown) \
2386	{ \
2387	a_rcTarget = rcThrown
2388	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
2389	} \
2390	((void)0)
2391	# else /* !IEM_WITH_THROW_CATCH */
2392	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
2393	jmp_buf JmpBuf; \
2394	jmp_buf * volatile pSavedJmpBuf = (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf); \
2395	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
2396	if ((rcStrict = setjmp(JmpBuf)) == 0)
2397	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
2398	pSavedJmpBuf = (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf); \
2399	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
2400	if ((rcStrict = setjmp(JmpBuf)) == 0)
2401	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
2402	else \
2403	{ \
2404	((void)0)
2405	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
2406	} \
2407	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = pSavedJmpBuf
2408	# endif /* !IEM_WITH_THROW_CATCH */
2409	#endif /* IEM_WITH_SETJMP */
2410
2411
2412	/**
2413	* Shared per-VM IEM data.
2414	*/
2415	typedef struct IEM
2416	{
2417	/** The VMX APIC-access page handler type. */
2418	PGMPHYSHANDLERTYPE hVmxApicAccessPage;
2419	#ifndef VBOX_WITHOUT_CPUID_HOST_CALL
2420	/** Set if the CPUID host call functionality is enabled. */
2421	bool fCpuIdHostCall;
2422	#endif
2423	} IEM;
2424
2425
2426
2427	/** @name IEM_ACCESS_XXX - Access details.
2428	* @{ */
2429	#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
2430	#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
2431	#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
2432	#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
2433	#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
2434	#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
2435	#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
2436	#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
2437	#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
2438	#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
2439	/** The writes are partial, so if initialize the bounce buffer with the
2440	* orignal RAM content. */
2441	#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
2442	/** Used in aMemMappings to indicate that the entry is bounce buffered. */
2443	#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
2444	/** Bounce buffer with ring-3 write pending, first page. */
2445	#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
2446	/** Bounce buffer with ring-3 write pending, second page. */
2447	#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
2448	/** Not locked, accessed via the TLB. */
2449	#define IEM_ACCESS_NOT_LOCKED UINT32_C(0x00001000)
2450	/** Atomic access.
2451	* This enables special alignment checks and the VINF_EM_EMULATE_SPLIT_LOCK
2452	* fallback for misaligned stuff. See @bugref{10547}. */
2453	#define IEM_ACCESS_ATOMIC UINT32_C(0x00002000)
2454	/** Valid bit mask. */
2455	#define IEM_ACCESS_VALID_MASK UINT32_C(0x00003fff)
2456	/** Shift count for the TLB flags (upper word). */
2457	#define IEM_ACCESS_SHIFT_TLB_FLAGS 16
2458
2459	/** Atomic read+write data alias. */
2460	#define IEM_ACCESS_DATA_ATOMIC (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA \| IEM_ACCESS_ATOMIC)
2461	/** Read+write data alias. */
2462	#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
2463	/** Write data alias. */
2464	#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
2465	/** Read data alias. */
2466	#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_DATA)
2467	/** Instruction fetch alias. */
2468	#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_WHAT_CODE)
2469	/** Stack write alias. */
2470	#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
2471	/** Stack read alias. */
2472	#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_STACK)
2473	/** Stack read+write alias. */
2474	#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
2475	/** Read system table alias. */
2476	#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_SYS)
2477	/** Read+write system table alias. */
2478	#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_SYS)
2479	/** @} */
2480
2481	/** @name Prefix constants (IEMCPU::fPrefixes)
2482	* @{ */
2483	#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /*< CS segment prefix (0x2e). /
2484	#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /*< SS segment prefix (0x36). /
2485	#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /*< DS segment prefix (0x3e). /
2486	#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /*< ES segment prefix (0x26). /
2487	#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /*< FS segment prefix (0x64). /
2488	#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /*< GS segment prefix (0x65). /
2489	#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
2490
2491	#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /*< Operand size prefix (0x66). /
2492	#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /*< REX.W prefix (0x48-0x4f). /
2493	#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /*< Address size prefix (0x67). /
2494
2495	#define IEM_OP_PRF_LOCK RT_BIT_32(16) /*< Lock prefix (0xf0). /
2496	#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /*< Repeat-not-zero prefix (0xf2). /
2497	#define IEM_OP_PRF_REPZ RT_BIT_32(18) /*< Repeat-if-zero prefix (0xf3). /
2498
2499	#define IEM_OP_PRF_REX RT_BIT_32(24) /*< Any REX prefix (0x40-0x4f). /
2500	#define IEM_OP_PRF_REX_B RT_BIT_32(25) /*< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). /
2501	#define IEM_OP_PRF_REX_X RT_BIT_32(26) /*< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). /
2502	#define IEM_OP_PRF_REX_R RT_BIT_32(27) /*< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). /
2503	/** Mask with all the REX prefix flags.
2504	* This is generally for use when needing to undo the REX prefixes when they
2505	* are followed legacy prefixes and therefore does not immediately preceed
2506	* the first opcode byte.
2507	* For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
2508	#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX \| IEM_OP_PRF_REX_R \| IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X \| IEM_OP_PRF_SIZE_REX_W )
2509
2510	#define IEM_OP_PRF_VEX RT_BIT_32(28) /*< Indiciates VEX prefix. /
2511	#define IEM_OP_PRF_EVEX RT_BIT_32(29) /*< Indiciates EVEX prefix. /
2512	#define IEM_OP_PRF_XOP RT_BIT_32(30) /*< Indiciates XOP prefix. /
2513	/** @} */
2514
2515	/** @name IEMOPFORM_XXX - Opcode forms
2516	* @note These are ORed together with IEMOPHINT_XXX.
2517	* @{ */
2518	/** ModR/M: reg, r/m */
2519	#define IEMOPFORM_RM 0
2520	/** ModR/M: reg, r/m (register) */
2521	#define IEMOPFORM_RM_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
2522	/** ModR/M: reg, r/m (memory) */
2523	#define IEMOPFORM_RM_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
2524	/** ModR/M: reg, r/m, imm */
2525	#define IEMOPFORM_RMI 1
2526	/** ModR/M: reg, r/m (register), imm */
2527	#define IEMOPFORM_RMI_REG (IEMOPFORM_RMI \| IEMOPFORM_MOD3)
2528	/** ModR/M: reg, r/m (memory), imm */
2529	#define IEMOPFORM_RMI_MEM (IEMOPFORM_RMI \| IEMOPFORM_NOT_MOD3)
2530	/** ModR/M: reg, r/m, xmm0 */
2531	#define IEMOPFORM_RM0 2
2532	/** ModR/M: reg, r/m (register), xmm0 */
2533	#define IEMOPFORM_RM0_REG (IEMOPFORM_RM0 \| IEMOPFORM_MOD3)
2534	/** ModR/M: reg, r/m (memory), xmm0 */
2535	#define IEMOPFORM_RM0_MEM (IEMOPFORM_RM0 \| IEMOPFORM_NOT_MOD3)
2536	/** ModR/M: r/m, reg */
2537	#define IEMOPFORM_MR 3
2538	/** ModR/M: r/m (register), reg */
2539	#define IEMOPFORM_MR_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
2540	/** ModR/M: r/m (memory), reg */
2541	#define IEMOPFORM_MR_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
2542	/** ModR/M: r/m, reg, imm */
2543	#define IEMOPFORM_MRI 4
2544	/** ModR/M: r/m (register), reg, imm */
2545	#define IEMOPFORM_MRI_REG (IEMOPFORM_MRI \| IEMOPFORM_MOD3)
2546	/** ModR/M: r/m (memory), reg, imm */
2547	#define IEMOPFORM_MRI_MEM (IEMOPFORM_MRI \| IEMOPFORM_NOT_MOD3)
2548	/** ModR/M: r/m only */
2549	#define IEMOPFORM_M 5
2550	/** ModR/M: r/m only (register). */
2551	#define IEMOPFORM_M_REG (IEMOPFORM_M \| IEMOPFORM_MOD3)
2552	/** ModR/M: r/m only (memory). */
2553	#define IEMOPFORM_M_MEM (IEMOPFORM_M \| IEMOPFORM_NOT_MOD3)
2554	/** ModR/M: r/m, imm */
2555	#define IEMOPFORM_MI 6
2556	/** ModR/M: r/m (register), imm */
2557	#define IEMOPFORM_MI_REG (IEMOPFORM_MI \| IEMOPFORM_MOD3)
2558	/** ModR/M: r/m (memory), imm */
2559	#define IEMOPFORM_MI_MEM (IEMOPFORM_MI \| IEMOPFORM_NOT_MOD3)
2560	/** ModR/M: r/m, 1 (shift and rotate instructions) */
2561	#define IEMOPFORM_M1 7
2562	/** ModR/M: r/m (register), 1. */
2563	#define IEMOPFORM_M1_REG (IEMOPFORM_M1 \| IEMOPFORM_MOD3)
2564	/** ModR/M: r/m (memory), 1. */
2565	#define IEMOPFORM_M1_MEM (IEMOPFORM_M1 \| IEMOPFORM_NOT_MOD3)
2566	/** ModR/M: r/m, CL (shift and rotate instructions)
2567	* @todo This should just've been a generic fixed register. But the python
2568	* code doesn't needs more convincing. */
2569	#define IEMOPFORM_M_CL 8
2570	/** ModR/M: r/m (register), CL. */
2571	#define IEMOPFORM_M_CL_REG (IEMOPFORM_M_CL \| IEMOPFORM_MOD3)
2572	/** ModR/M: r/m (memory), CL. */
2573	#define IEMOPFORM_M_CL_MEM (IEMOPFORM_M_CL \| IEMOPFORM_NOT_MOD3)
2574	/** ModR/M: reg only */
2575	#define IEMOPFORM_R 9
2576
2577	/** VEX+ModR/M: reg, r/m */
2578	#define IEMOPFORM_VEX_RM 16
2579	/** VEX+ModR/M: reg, r/m (register) */
2580	#define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM \| IEMOPFORM_MOD3)
2581	/** VEX+ModR/M: reg, r/m (memory) */
2582	#define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM \| IEMOPFORM_NOT_MOD3)
2583	/** VEX+ModR/M: r/m, reg */
2584	#define IEMOPFORM_VEX_MR 17
2585	/** VEX+ModR/M: r/m (register), reg */
2586	#define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR \| IEMOPFORM_MOD3)
2587	/** VEX+ModR/M: r/m (memory), reg */
2588	#define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR \| IEMOPFORM_NOT_MOD3)
2589	/** VEX+ModR/M: r/m, reg, imm8 */
2590	#define IEMOPFORM_VEX_MRI 18
2591	/** VEX+ModR/M: r/m (register), reg, imm8 */
2592	#define IEMOPFORM_VEX_MRI_REG (IEMOPFORM_VEX_MRI \| IEMOPFORM_MOD3)
2593	/** VEX+ModR/M: r/m (memory), reg, imm8 */
2594	#define IEMOPFORM_VEX_MRI_MEM (IEMOPFORM_VEX_MRI \| IEMOPFORM_NOT_MOD3)
2595	/** VEX+ModR/M: r/m only */
2596	#define IEMOPFORM_VEX_M 19
2597	/** VEX+ModR/M: r/m only (register). */
2598	#define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M \| IEMOPFORM_MOD3)
2599	/** VEX+ModR/M: r/m only (memory). */
2600	#define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M \| IEMOPFORM_NOT_MOD3)
2601	/** VEX+ModR/M: reg only */
2602	#define IEMOPFORM_VEX_R 20
2603	/** VEX+ModR/M: reg, vvvv, r/m */
2604	#define IEMOPFORM_VEX_RVM 21
2605	/** VEX+ModR/M: reg, vvvv, r/m (register). */
2606	#define IEMOPFORM_VEX_RVM_REG (IEMOPFORM_VEX_RVM \| IEMOPFORM_MOD3)
2607	/** VEX+ModR/M: reg, vvvv, r/m (memory). */
2608	#define IEMOPFORM_VEX_RVM_MEM (IEMOPFORM_VEX_RVM \| IEMOPFORM_NOT_MOD3)
2609	/** VEX+ModR/M: reg, vvvv, r/m, imm */
2610	#define IEMOPFORM_VEX_RVMI 22
2611	/** VEX+ModR/M: reg, vvvv, r/m (register), imm. */
2612	#define IEMOPFORM_VEX_RVMI_REG (IEMOPFORM_VEX_RVMI \| IEMOPFORM_MOD3)
2613	/** VEX+ModR/M: reg, vvvv, r/m (memory), imm. */
2614	#define IEMOPFORM_VEX_RVMI_MEM (IEMOPFORM_VEX_RVMI \| IEMOPFORM_NOT_MOD3)
2615	/** VEX+ModR/M: reg, vvvv, r/m, imm(reg) */
2616	#define IEMOPFORM_VEX_RVMR 23
2617	/** VEX+ModR/M: reg, vvvv, r/m (register), imm(reg). */
2618	#define IEMOPFORM_VEX_RVMR_REG (IEMOPFORM_VEX_RVMI \| IEMOPFORM_MOD3)
2619	/** VEX+ModR/M: reg, vvvv, r/m (memory), imm(reg). */
2620	#define IEMOPFORM_VEX_RVMR_MEM (IEMOPFORM_VEX_RVMI \| IEMOPFORM_NOT_MOD3)
2621	/** VEX+ModR/M: reg, r/m, vvvv */
2622	#define IEMOPFORM_VEX_RMV 24
2623	/** VEX+ModR/M: reg, r/m, vvvv (register). */
2624	#define IEMOPFORM_VEX_RMV_REG (IEMOPFORM_VEX_RMV \| IEMOPFORM_MOD3)
2625	/** VEX+ModR/M: reg, r/m, vvvv (memory). */
2626	#define IEMOPFORM_VEX_RMV_MEM (IEMOPFORM_VEX_RMV \| IEMOPFORM_NOT_MOD3)
2627	/** VEX+ModR/M: reg, r/m, imm8 */
2628	#define IEMOPFORM_VEX_RMI 25
2629	/** VEX+ModR/M: reg, r/m, imm8 (register). */
2630	#define IEMOPFORM_VEX_RMI_REG (IEMOPFORM_VEX_RMI \| IEMOPFORM_MOD3)
2631	/** VEX+ModR/M: reg, r/m, imm8 (memory). */
2632	#define IEMOPFORM_VEX_RMI_MEM (IEMOPFORM_VEX_RMI \| IEMOPFORM_NOT_MOD3)
2633	/** VEX+ModR/M: r/m, vvvv, reg */
2634	#define IEMOPFORM_VEX_MVR 26
2635	/** VEX+ModR/M: r/m, vvvv, reg (register) */
2636	#define IEMOPFORM_VEX_MVR_REG (IEMOPFORM_VEX_MVR \| IEMOPFORM_MOD3)
2637	/** VEX+ModR/M: r/m, vvvv, reg (memory) */
2638	#define IEMOPFORM_VEX_MVR_MEM (IEMOPFORM_VEX_MVR \| IEMOPFORM_NOT_MOD3)
2639	/** VEX+ModR/M+/n: vvvv, r/m */
2640	#define IEMOPFORM_VEX_VM 27
2641	/** VEX+ModR/M+/n: vvvv, r/m (register) */
2642	#define IEMOPFORM_VEX_VM_REG (IEMOPFORM_VEX_VM \| IEMOPFORM_MOD3)
2643	/** VEX+ModR/M+/n: vvvv, r/m (memory) */
2644	#define IEMOPFORM_VEX_VM_MEM (IEMOPFORM_VEX_VM \| IEMOPFORM_NOT_MOD3)
2645	/** VEX+ModR/M+/n: vvvv, r/m, imm8 */
2646	#define IEMOPFORM_VEX_VMI 28
2647	/** VEX+ModR/M+/n: vvvv, r/m, imm8 (register) */
2648	#define IEMOPFORM_VEX_VMI_REG (IEMOPFORM_VEX_VMI \| IEMOPFORM_MOD3)
2649	/** VEX+ModR/M+/n: vvvv, r/m, imm8 (memory) */
2650	#define IEMOPFORM_VEX_VMI_MEM (IEMOPFORM_VEX_VMI \| IEMOPFORM_NOT_MOD3)
2651
2652	/** Fixed register instruction, no R/M. */
2653	#define IEMOPFORM_FIXED 32
2654
2655	/** The r/m is a register. */
2656	#define IEMOPFORM_MOD3 RT_BIT_32(8)
2657	/** The r/m is a memory access. */
2658	#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
2659	/** @} */
2660
2661	/** @name IEMOPHINT_XXX - Additional Opcode Hints
2662	* @note These are ORed together with IEMOPFORM_XXX.
2663	* @{ */
2664	/** Ignores the operand size prefix (66h). */
2665	#define IEMOPHINT_IGNORES_OZ_PFX RT_BIT_32(10)
2666	/** Ignores REX.W (aka WIG). */
2667	#define IEMOPHINT_IGNORES_REXW RT_BIT_32(11)
2668	/** Both the operand size prefixes (66h + REX.W) are ignored. */
2669	#define IEMOPHINT_IGNORES_OP_SIZES (IEMOPHINT_IGNORES_OZ_PFX \| IEMOPHINT_IGNORES_REXW)
2670	/** Allowed with the lock prefix. */
2671	#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
2672	/** The VEX.L value is ignored (aka LIG). */
2673	#define IEMOPHINT_VEX_L_IGNORED RT_BIT_32(12)
2674	/** The VEX.L value must be zero (i.e. 128-bit width only). */
2675	#define IEMOPHINT_VEX_L_ZERO RT_BIT_32(13)
2676	/** The VEX.L value must be one (i.e. 256-bit width only). */
2677	#define IEMOPHINT_VEX_L_ONE RT_BIT_32(14)
2678	/** The VEX.V value must be zero. */
2679	#define IEMOPHINT_VEX_V_ZERO RT_BIT_32(15)
2680	/** The REX.W/VEX.V value must be zero. */
2681	#define IEMOPHINT_REX_W_ZERO RT_BIT_32(16)
2682	#define IEMOPHINT_VEX_W_ZERO IEMOPHINT_REX_W_ZERO
2683	/** The REX.W/VEX.V value must be one. */
2684	#define IEMOPHINT_REX_W_ONE RT_BIT_32(17)
2685	#define IEMOPHINT_VEX_W_ONE IEMOPHINT_REX_W_ONE
2686
2687	/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
2688	#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
2689	/** @} */
2690
2691	/**
2692	* Possible hardware task switch sources.
2693	*/
2694	typedef enum IEMTASKSWITCH
2695	{
2696	/** Task switch caused by an interrupt/exception. */
2697	IEMTASKSWITCH_INT_XCPT = 1,
2698	/** Task switch caused by a far CALL. */
2699	IEMTASKSWITCH_CALL,
2700	/** Task switch caused by a far JMP. */
2701	IEMTASKSWITCH_JUMP,
2702	/** Task switch caused by an IRET. */
2703	IEMTASKSWITCH_IRET
2704	} IEMTASKSWITCH;
2705	AssertCompileSize(IEMTASKSWITCH, 4);
2706
2707	/**
2708	* Possible CrX load (write) sources.
2709	*/
2710	typedef enum IEMACCESSCRX
2711	{
2712	/** CrX access caused by 'mov crX' instruction. */
2713	IEMACCESSCRX_MOV_CRX,
2714	/** CrX (CR0) write caused by 'lmsw' instruction. */
2715	IEMACCESSCRX_LMSW,
2716	/** CrX (CR0) write caused by 'clts' instruction. */
2717	IEMACCESSCRX_CLTS,
2718	/** CrX (CR0) read caused by 'smsw' instruction. */
2719	IEMACCESSCRX_SMSW
2720	} IEMACCESSCRX;
2721
2722	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2723	/** @name IEM_SLAT_FAIL_XXX - Second-level address translation failure information.
2724	*
2725	* These flags provide further context to SLAT page-walk failures that could not be
2726	* determined by PGM (e.g, PGM is not privy to memory access permissions).
2727	*
2728	* @{
2729	*/
2730	/** Translating a nested-guest linear address failed accessing a nested-guest
2731	* physical address. */
2732	# define IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR RT_BIT_32(0)
2733	/** Translating a nested-guest linear address failed accessing a
2734	* paging-structure entry or updating accessed/dirty bits. */
2735	# define IEM_SLAT_FAIL_LINEAR_TO_PAGE_TABLE RT_BIT_32(1)
2736	/** @} */
2737
2738	DECLCALLBACK(FNPGMPHYSHANDLER) iemVmxApicAccessPageHandler;
2739	# ifndef IN_RING3
2740	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) iemVmxApicAccessPagePfHandler;
2741	# endif
2742	#endif
2743
2744	/**
2745	* Indicates to the verifier that the given flag set is undefined.
2746	*
2747	* Can be invoked again to add more flags.
2748	*
2749	* This is a NOOP if the verifier isn't compiled in.
2750	*
2751	* @note We're temporarily keeping this until code is converted to new
2752	* disassembler style opcode handling.
2753	*/
2754	#define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
2755
2756
2757	/** @def IEM_DECL_IMPL_TYPE
2758	* For typedef'ing an instruction implementation function.
2759	*
2760	* @param a_RetType The return type.
2761	* @param a_Name The name of the type.
2762	* @param a_ArgList The argument list enclosed in parentheses.
2763	*/
2764
2765	/** @def IEM_DECL_IMPL_DEF
2766	* For defining an instruction implementation function.
2767	*
2768	* @param a_RetType The return type.
2769	* @param a_Name The name of the type.
2770	* @param a_ArgList The argument list enclosed in parentheses.
2771	*/
2772
2773	#if defined(__GNUC__) && defined(RT_ARCH_X86)
2774	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2775	__attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
2776	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2777	__attribute__((__fastcall__, __nothrow__)) DECL_HIDDEN_ONLY(a_RetType) a_Name a_ArgList
2778	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2779	__attribute__((__fastcall__, __nothrow__)) DECL_HIDDEN_ONLY(a_RetType) a_Name a_ArgList
2780
2781	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
2782	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2783	a_RetType (__fastcall a_Name) a_ArgList
2784	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2785	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
2786	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2787	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
2788
2789	#elif __cplusplus >= 201700 /* P0012R1 support */
2790	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2791	a_RetType (VBOXCALL a_Name) a_ArgList RT_NOEXCEPT
2792	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2793	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList RT_NOEXCEPT
2794	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2795	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList RT_NOEXCEPT
2796
2797	#else
2798	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2799	a_RetType (VBOXCALL a_Name) a_ArgList
2800	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2801	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList
2802	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2803	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList
2804
2805	#endif
2806
2807	/** Defined in IEMAllAImplC.cpp but also used by IEMAllAImplA.asm. */
2808	RT_C_DECLS_BEGIN
2809	extern uint8_t const g_afParity[256];
2810	RT_C_DECLS_END
2811
2812
2813	/** @name Arithmetic assignment operations on bytes (binary).
2814	* @{ */
2815	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU8, (uint32_t fEFlagsIn, uint8_t *pu8Dst, uint8_t u8Src));
2816	typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
2817	FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
2818	FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
2819	FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
2820	FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
2821	FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
2822	FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
2823	FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
2824	/** @} */
2825
2826	/** @name Arithmetic assignment operations on words (binary).
2827	* @{ */
2828	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU16, (uint32_t fEFlagsIn, uint16_t *pu16Dst, uint16_t u16Src));
2829	typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
2830	FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
2831	FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
2832	FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
2833	FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
2834	FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
2835	FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
2836	FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
2837	/** @} */
2838
2839
2840	/** @name Arithmetic assignment operations on double words (binary).
2841	* @{ */
2842	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU32, (uint32_t fEFlagsIn, uint32_t *pu32Dst, uint32_t u32Src));
2843	typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
2844	FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
2845	FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
2846	FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
2847	FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
2848	FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
2849	FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
2850	FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
2851	FNIEMAIMPLBINU32 iemAImpl_blsi_u32, iemAImpl_blsi_u32_fallback;
2852	FNIEMAIMPLBINU32 iemAImpl_blsr_u32, iemAImpl_blsr_u32_fallback;
2853	FNIEMAIMPLBINU32 iemAImpl_blsmsk_u32, iemAImpl_blsmsk_u32_fallback;
2854	/** @} */
2855
2856	/** @name Arithmetic assignment operations on quad words (binary).
2857	* @{ */
2858	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU64, (uint32_t fEFlagsIn, uint64_t *pu64Dst, uint64_t u64Src));
2859	typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
2860	FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
2861	FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
2862	FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
2863	FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
2864	FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
2865	FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
2866	FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
2867	FNIEMAIMPLBINU64 iemAImpl_blsi_u64, iemAImpl_blsi_u64_fallback;
2868	FNIEMAIMPLBINU64 iemAImpl_blsr_u64, iemAImpl_blsr_u64_fallback;
2869	FNIEMAIMPLBINU64 iemAImpl_blsmsk_u64, iemAImpl_blsmsk_u64_fallback;
2870	/** @} */
2871
2872	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU8, (uint32_t fEFlagsIn, uint8_t const *pu8Dst, uint8_t u8Src));
2873	typedef FNIEMAIMPLBINROU8 *PFNIEMAIMPLBINROU8;
2874	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU16,(uint32_t fEFlagsIn, uint16_t const *pu16Dst, uint16_t u16Src));
2875	typedef FNIEMAIMPLBINROU16 *PFNIEMAIMPLBINROU16;
2876	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU32,(uint32_t fEFlagsIn, uint32_t const *pu32Dst, uint32_t u32Src));
2877	typedef FNIEMAIMPLBINROU32 *PFNIEMAIMPLBINROU32;
2878	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU64,(uint32_t fEFlagsIn, uint64_t const *pu64Dst, uint64_t u64Src));
2879	typedef FNIEMAIMPLBINROU64 *PFNIEMAIMPLBINROU64;
2880
2881	/** @name Compare operations (thrown in with the binary ops).
2882	* @{ */
2883	FNIEMAIMPLBINROU8 iemAImpl_cmp_u8;
2884	FNIEMAIMPLBINROU16 iemAImpl_cmp_u16;
2885	FNIEMAIMPLBINROU32 iemAImpl_cmp_u32;
2886	FNIEMAIMPLBINROU64 iemAImpl_cmp_u64;
2887	/** @} */
2888
2889	/** @name Test operations (thrown in with the binary ops).
2890	* @{ */
2891	FNIEMAIMPLBINROU8 iemAImpl_test_u8;
2892	FNIEMAIMPLBINROU16 iemAImpl_test_u16;
2893	FNIEMAIMPLBINROU32 iemAImpl_test_u32;
2894	FNIEMAIMPLBINROU64 iemAImpl_test_u64;
2895	/** @} */
2896
2897	/** @name Bit operations operations (thrown in with the binary ops).
2898	* @{ */
2899	FNIEMAIMPLBINROU16 iemAImpl_bt_u16;
2900	FNIEMAIMPLBINROU32 iemAImpl_bt_u32;
2901	FNIEMAIMPLBINROU64 iemAImpl_bt_u64;
2902	FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
2903	FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
2904	FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
2905	FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
2906	FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
2907	FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
2908	FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
2909	FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
2910	FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
2911	/** @} */
2912
2913	/** @name Arithmetic three operand operations on double words (binary).
2914	* @{ */
2915	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32, (uint32_t pu32Dst, uint32_t u32Src1, uint32_t u32Src2, uint32_t pEFlags));
2916	typedef FNIEMAIMPLBINVEXU32 *PFNIEMAIMPLBINVEXU32;
2917	FNIEMAIMPLBINVEXU32 iemAImpl_andn_u32, iemAImpl_andn_u32_fallback;
2918	FNIEMAIMPLBINVEXU32 iemAImpl_bextr_u32, iemAImpl_bextr_u32_fallback;
2919	FNIEMAIMPLBINVEXU32 iemAImpl_bzhi_u32, iemAImpl_bzhi_u32_fallback;
2920	/** @} */
2921
2922	/** @name Arithmetic three operand operations on quad words (binary).
2923	* @{ */
2924	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64, (uint64_t pu64Dst, uint64_t u64Src1, uint64_t u64Src2, uint32_t pEFlags));
2925	typedef FNIEMAIMPLBINVEXU64 *PFNIEMAIMPLBINVEXU64;
2926	FNIEMAIMPLBINVEXU64 iemAImpl_andn_u64, iemAImpl_andn_u64_fallback;
2927	FNIEMAIMPLBINVEXU64 iemAImpl_bextr_u64, iemAImpl_bextr_u64_fallback;
2928	FNIEMAIMPLBINVEXU64 iemAImpl_bzhi_u64, iemAImpl_bzhi_u64_fallback;
2929	/** @} */
2930
2931	/** @name Arithmetic three operand operations on double words w/o EFLAGS (binary).
2932	* @{ */
2933	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32NOEFL, (uint32_t *pu32Dst, uint32_t u32Src1, uint32_t u32Src2));
2934	typedef FNIEMAIMPLBINVEXU32NOEFL *PFNIEMAIMPLBINVEXU32NOEFL;
2935	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pdep_u32, iemAImpl_pdep_u32_fallback;
2936	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pext_u32, iemAImpl_pext_u32_fallback;
2937	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_sarx_u32, iemAImpl_sarx_u32_fallback;
2938	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shlx_u32, iemAImpl_shlx_u32_fallback;
2939	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shrx_u32, iemAImpl_shrx_u32_fallback;
2940	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_rorx_u32;
2941	/** @} */
2942
2943	/** @name Arithmetic three operand operations on quad words w/o EFLAGS (binary).
2944	* @{ */
2945	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64NOEFL, (uint64_t *pu64Dst, uint64_t u64Src1, uint64_t u64Src2));
2946	typedef FNIEMAIMPLBINVEXU64NOEFL *PFNIEMAIMPLBINVEXU64NOEFL;
2947	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pdep_u64, iemAImpl_pdep_u64_fallback;
2948	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pext_u64, iemAImpl_pext_u64_fallback;
2949	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_sarx_u64, iemAImpl_sarx_u64_fallback;
2950	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shlx_u64, iemAImpl_shlx_u64_fallback;
2951	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shrx_u64, iemAImpl_shrx_u64_fallback;
2952	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_rorx_u64;
2953	/** @} */
2954
2955	/** @name MULX 32-bit and 64-bit.
2956	* @{ */
2957	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU32, (uint32_t puDst1, uint32_t puDst2, uint32_t uSrc1, uint32_t uSrc2));
2958	typedef FNIEMAIMPLMULXVEXU32 *PFNIEMAIMPLMULXVEXU32;
2959	FNIEMAIMPLMULXVEXU32 iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback;
2960
2961	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU64, (uint64_t puDst1, uint64_t puDst2, uint64_t uSrc1, uint64_t uSrc2));
2962	typedef FNIEMAIMPLMULXVEXU64 *PFNIEMAIMPLMULXVEXU64;
2963	FNIEMAIMPLMULXVEXU64 iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback;
2964	/** @} */
2965
2966
2967	/** @name Exchange memory with register operations.
2968	* @{ */
2969	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_locked, (uint8_t pu8Mem, uint8_t pu8Reg));
2970	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_locked,(uint16_t pu16Mem, uint16_t pu16Reg));
2971	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_locked,(uint32_t pu32Mem, uint32_t pu32Reg));
2972	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_locked,(uint64_t pu64Mem, uint64_t pu64Reg));
2973	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_unlocked, (uint8_t pu8Mem, uint8_t pu8Reg));
2974	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_unlocked,(uint16_t pu16Mem, uint16_t pu16Reg));
2975	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_unlocked,(uint32_t pu32Mem, uint32_t pu32Reg));
2976	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_unlocked,(uint64_t pu64Mem, uint64_t pu64Reg));
2977	/** @} */
2978
2979	/** @name Exchange and add operations.
2980	* @{ */
2981	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
2982	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
2983	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
2984	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
2985	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
2986	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
2987	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
2988	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
2989	/** @} */
2990
2991	/** @name Compare and exchange.
2992	* @{ */
2993	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
2994	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
2995	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
2996	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
2997	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
2998	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
2999	#if ARCH_BITS == 32
3000	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
3001	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
3002	#else
3003	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
3004	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
3005	#endif
3006	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
3007	uint32_t *pEFlags));
3008	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
3009	uint32_t *pEFlags));
3010	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
3011	uint32_t *pEFlags));
3012	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
3013	uint32_t *pEFlags));
3014	#ifndef RT_ARCH_ARM64
3015	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
3016	PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
3017	#endif
3018	/** @} */
3019
3020	/** @name Memory ordering
3021	* @{ */
3022	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
3023	typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
3024	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
3025	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
3026	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
3027	#ifndef RT_ARCH_ARM64
3028	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
3029	#endif
3030	/** @} */
3031
3032	/** @name Double precision shifts
3033	* @{ */
3034	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t pEFlags));
3035	typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
3036	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t pEFlags));
3037	typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
3038	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t pEFlags));
3039	typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
3040	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16, iemAImpl_shld_u16_amd, iemAImpl_shld_u16_intel;
3041	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32, iemAImpl_shld_u32_amd, iemAImpl_shld_u32_intel;
3042	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64, iemAImpl_shld_u64_amd, iemAImpl_shld_u64_intel;
3043	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16, iemAImpl_shrd_u16_amd, iemAImpl_shrd_u16_intel;
3044	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32, iemAImpl_shrd_u32_amd, iemAImpl_shrd_u32_intel;
3045	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64, iemAImpl_shrd_u64_amd, iemAImpl_shrd_u64_intel;
3046	/** @} */
3047
3048
3049	/** @name Bit search operations (thrown in with the binary ops).
3050	* @{ */
3051	FNIEMAIMPLBINU16 iemAImpl_bsf_u16, iemAImpl_bsf_u16_amd, iemAImpl_bsf_u16_intel;
3052	FNIEMAIMPLBINU32 iemAImpl_bsf_u32, iemAImpl_bsf_u32_amd, iemAImpl_bsf_u32_intel;
3053	FNIEMAIMPLBINU64 iemAImpl_bsf_u64, iemAImpl_bsf_u64_amd, iemAImpl_bsf_u64_intel;
3054	FNIEMAIMPLBINU16 iemAImpl_bsr_u16, iemAImpl_bsr_u16_amd, iemAImpl_bsr_u16_intel;
3055	FNIEMAIMPLBINU32 iemAImpl_bsr_u32, iemAImpl_bsr_u32_amd, iemAImpl_bsr_u32_intel;
3056	FNIEMAIMPLBINU64 iemAImpl_bsr_u64, iemAImpl_bsr_u64_amd, iemAImpl_bsr_u64_intel;
3057	FNIEMAIMPLBINU16 iemAImpl_lzcnt_u16, iemAImpl_lzcnt_u16_amd, iemAImpl_lzcnt_u16_intel;
3058	FNIEMAIMPLBINU32 iemAImpl_lzcnt_u32, iemAImpl_lzcnt_u32_amd, iemAImpl_lzcnt_u32_intel;
3059	FNIEMAIMPLBINU64 iemAImpl_lzcnt_u64, iemAImpl_lzcnt_u64_amd, iemAImpl_lzcnt_u64_intel;
3060	FNIEMAIMPLBINU16 iemAImpl_tzcnt_u16, iemAImpl_tzcnt_u16_amd, iemAImpl_tzcnt_u16_intel;
3061	FNIEMAIMPLBINU32 iemAImpl_tzcnt_u32, iemAImpl_tzcnt_u32_amd, iemAImpl_tzcnt_u32_intel;
3062	FNIEMAIMPLBINU64 iemAImpl_tzcnt_u64, iemAImpl_tzcnt_u64_amd, iemAImpl_tzcnt_u64_intel;
3063	FNIEMAIMPLBINU16 iemAImpl_popcnt_u16, iemAImpl_popcnt_u16_fallback;
3064	FNIEMAIMPLBINU32 iemAImpl_popcnt_u32, iemAImpl_popcnt_u32_fallback;
3065	FNIEMAIMPLBINU64 iemAImpl_popcnt_u64, iemAImpl_popcnt_u64_fallback;
3066	/** @} */
3067
3068	/** @name Signed multiplication operations (thrown in with the binary ops).
3069	* @{ */
3070	FNIEMAIMPLBINU16 iemAImpl_imul_two_u16, iemAImpl_imul_two_u16_amd, iemAImpl_imul_two_u16_intel;
3071	FNIEMAIMPLBINU32 iemAImpl_imul_two_u32, iemAImpl_imul_two_u32_amd, iemAImpl_imul_two_u32_intel;
3072	FNIEMAIMPLBINU64 iemAImpl_imul_two_u64, iemAImpl_imul_two_u64_amd, iemAImpl_imul_two_u64_intel;
3073	/** @} */
3074
3075	/** @name Arithmetic assignment operations on bytes (unary).
3076	* @{ */
3077	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t pu8Dst, uint32_t pEFlags));
3078	typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
3079	FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
3080	FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
3081	FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
3082	FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
3083	/** @} */
3084
3085	/** @name Arithmetic assignment operations on words (unary).
3086	* @{ */
3087	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t pu16Dst, uint32_t pEFlags));
3088	typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
3089	FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
3090	FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
3091	FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
3092	FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
3093	/** @} */
3094
3095	/** @name Arithmetic assignment operations on double words (unary).
3096	* @{ */
3097	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t pu32Dst, uint32_t pEFlags));
3098	typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
3099	FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
3100	FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
3101	FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
3102	FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
3103	/** @} */
3104
3105	/** @name Arithmetic assignment operations on quad words (unary).
3106	* @{ */
3107	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t pu64Dst, uint32_t pEFlags));
3108	typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
3109	FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
3110	FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
3111	FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
3112	FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
3113	/** @} */
3114
3115
3116	/** @name Shift operations on bytes (Group 2).
3117	* @{ */
3118	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU8,(uint32_t fEFlagsIn, uint8_t *pu8Dst, uint8_t cShift));
3119	typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
3120	FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8, iemAImpl_rol_u8_amd, iemAImpl_rol_u8_intel;
3121	FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8, iemAImpl_ror_u8_amd, iemAImpl_ror_u8_intel;
3122	FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8, iemAImpl_rcl_u8_amd, iemAImpl_rcl_u8_intel;
3123	FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8, iemAImpl_rcr_u8_amd, iemAImpl_rcr_u8_intel;
3124	FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8, iemAImpl_shl_u8_amd, iemAImpl_shl_u8_intel;
3125	FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8, iemAImpl_shr_u8_amd, iemAImpl_shr_u8_intel;
3126	FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8, iemAImpl_sar_u8_amd, iemAImpl_sar_u8_intel;
3127	/** @} */
3128
3129	/** @name Shift operations on words (Group 2).
3130	* @{ */
3131	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU16,(uint32_t fEFlagsIn, uint16_t *pu16Dst, uint8_t cShift));
3132	typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
3133	FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16, iemAImpl_rol_u16_amd, iemAImpl_rol_u16_intel;
3134	FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16, iemAImpl_ror_u16_amd, iemAImpl_ror_u16_intel;
3135	FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16, iemAImpl_rcl_u16_amd, iemAImpl_rcl_u16_intel;
3136	FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16, iemAImpl_rcr_u16_amd, iemAImpl_rcr_u16_intel;
3137	FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16, iemAImpl_shl_u16_amd, iemAImpl_shl_u16_intel;
3138	FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16, iemAImpl_shr_u16_amd, iemAImpl_shr_u16_intel;
3139	FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16, iemAImpl_sar_u16_amd, iemAImpl_sar_u16_intel;
3140	/** @} */
3141
3142	/** @name Shift operations on double words (Group 2).
3143	* @{ */
3144	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU32,(uint32_t fEFlagsIn, uint32_t *pu32Dst, uint8_t cShift));
3145	typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
3146	FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32, iemAImpl_rol_u32_amd, iemAImpl_rol_u32_intel;
3147	FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32, iemAImpl_ror_u32_amd, iemAImpl_ror_u32_intel;
3148	FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32, iemAImpl_rcl_u32_amd, iemAImpl_rcl_u32_intel;
3149	FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32, iemAImpl_rcr_u32_amd, iemAImpl_rcr_u32_intel;
3150	FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32, iemAImpl_shl_u32_amd, iemAImpl_shl_u32_intel;
3151	FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32, iemAImpl_shr_u32_amd, iemAImpl_shr_u32_intel;
3152	FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32, iemAImpl_sar_u32_amd, iemAImpl_sar_u32_intel;
3153	/** @} */
3154
3155	/** @name Shift operations on words (Group 2).
3156	* @{ */
3157	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU64,(uint32_t fEFlagsIn, uint64_t *pu64Dst, uint8_t cShift));
3158	typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
3159	FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64, iemAImpl_rol_u64_amd, iemAImpl_rol_u64_intel;
3160	FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64, iemAImpl_ror_u64_amd, iemAImpl_ror_u64_intel;
3161	FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64, iemAImpl_rcl_u64_amd, iemAImpl_rcl_u64_intel;
3162	FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64, iemAImpl_rcr_u64_amd, iemAImpl_rcr_u64_intel;
3163	FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64, iemAImpl_shl_u64_amd, iemAImpl_shl_u64_intel;
3164	FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64, iemAImpl_shr_u64_amd, iemAImpl_shr_u64_intel;
3165	FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64, iemAImpl_sar_u64_amd, iemAImpl_sar_u64_intel;
3166	/** @} */
3167
3168	/** @name Multiplication and division operations.
3169	* @{ */
3170	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t pu16AX, uint8_t u8FactorDivisor, uint32_t pEFlags));
3171	typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
3172	FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_mul_u8_amd, iemAImpl_mul_u8_intel;
3173	FNIEMAIMPLMULDIVU8 iemAImpl_imul_u8, iemAImpl_imul_u8_amd, iemAImpl_imul_u8_intel;
3174	FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_div_u8_amd, iemAImpl_div_u8_intel;
3175	FNIEMAIMPLMULDIVU8 iemAImpl_idiv_u8, iemAImpl_idiv_u8_amd, iemAImpl_idiv_u8_intel;
3176
3177	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t pu16AX, uint16_t pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
3178	typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
3179	FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_mul_u16_amd, iemAImpl_mul_u16_intel;
3180	FNIEMAIMPLMULDIVU16 iemAImpl_imul_u16, iemAImpl_imul_u16_amd, iemAImpl_imul_u16_intel;
3181	FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_div_u16_amd, iemAImpl_div_u16_intel;
3182	FNIEMAIMPLMULDIVU16 iemAImpl_idiv_u16, iemAImpl_idiv_u16_amd, iemAImpl_idiv_u16_intel;
3183
3184	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t pu32EAX, uint32_t pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
3185	typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
3186	FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_mul_u32_amd, iemAImpl_mul_u32_intel;
3187	FNIEMAIMPLMULDIVU32 iemAImpl_imul_u32, iemAImpl_imul_u32_amd, iemAImpl_imul_u32_intel;
3188	FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_div_u32_amd, iemAImpl_div_u32_intel;
3189	FNIEMAIMPLMULDIVU32 iemAImpl_idiv_u32, iemAImpl_idiv_u32_amd, iemAImpl_idiv_u32_intel;
3190
3191	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t pu64RAX, uint64_t pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
3192	typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
3193	FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_mul_u64_amd, iemAImpl_mul_u64_intel;
3194	FNIEMAIMPLMULDIVU64 iemAImpl_imul_u64, iemAImpl_imul_u64_amd, iemAImpl_imul_u64_intel;
3195	FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_div_u64_amd, iemAImpl_div_u64_intel;
3196	FNIEMAIMPLMULDIVU64 iemAImpl_idiv_u64, iemAImpl_idiv_u64_amd, iemAImpl_idiv_u64_intel;
3197	/** @} */
3198
3199	/** @name Byte Swap.
3200	* @{ */
3201	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t pu32Dst)); / Yes, 32-bit register access. */
3202	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
3203	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
3204	/** @} */
3205
3206	/** @name Misc.
3207	* @{ */
3208	FNIEMAIMPLBINU16 iemAImpl_arpl;
3209	/** @} */
3210
3211	/** @name RDRAND and RDSEED
3212	* @{ */
3213	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU16,(uint16_t puDst, uint32_t pEFlags));
3214	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU32,(uint32_t puDst, uint32_t pEFlags));
3215	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU64,(uint64_t puDst, uint32_t pEFlags));
3216	typedef FNIEMAIMPLRDRANDSEEDU16 *PFNIEMAIMPLRDRANDSEEDU16;
3217	typedef FNIEMAIMPLRDRANDSEEDU32 *PFNIEMAIMPLRDRANDSEEDU32;
3218	typedef FNIEMAIMPLRDRANDSEEDU64 *PFNIEMAIMPLRDRANDSEEDU64;
3219
3220	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdrand_u16, iemAImpl_rdrand_u16_fallback;
3221	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdrand_u32, iemAImpl_rdrand_u32_fallback;
3222	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdrand_u64, iemAImpl_rdrand_u64_fallback;
3223	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdseed_u16, iemAImpl_rdseed_u16_fallback;
3224	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdseed_u32, iemAImpl_rdseed_u32_fallback;
3225	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdseed_u64, iemAImpl_rdseed_u64_fallback;
3226	/** @} */
3227
3228	/** @name ADOX and ADCX
3229	* @{ */
3230	FNIEMAIMPLBINU32 iemAImpl_adcx_u32, iemAImpl_adcx_u32_fallback;
3231	FNIEMAIMPLBINU64 iemAImpl_adcx_u64, iemAImpl_adcx_u64_fallback;
3232	FNIEMAIMPLBINU32 iemAImpl_adox_u32, iemAImpl_adox_u32_fallback;
3233	FNIEMAIMPLBINU64 iemAImpl_adox_u64, iemAImpl_adox_u64_fallback;
3234	/** @} */
3235
3236	/** @name FPU operations taking a 32-bit float argument
3237	* @{ */
3238	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3239	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
3240	typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
3241
3242	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3243	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
3244	typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
3245
3246	FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
3247	FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
3248	FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
3249	FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
3250	FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
3251	FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
3252	FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
3253
3254	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
3255	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3256	PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
3257	/** @} */
3258
3259	/** @name FPU operations taking a 64-bit float argument
3260	* @{ */
3261	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3262	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
3263	typedef FNIEMAIMPLFPUR64FSW *PFNIEMAIMPLFPUR64FSW;
3264
3265	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3266	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
3267	typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
3268
3269	FNIEMAIMPLFPUR64FSW iemAImpl_fcom_r80_by_r64;
3270	FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
3271	FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
3272	FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
3273	FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
3274	FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
3275	FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
3276
3277	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
3278	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3279	PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
3280	/** @} */
3281
3282	/** @name FPU operations taking a 80-bit float argument
3283	* @{ */
3284	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3285	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
3286	typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
3287	FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
3288	FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
3289	FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
3290	FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
3291	FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
3292	FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
3293	FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
3294	FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
3295	FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
3296
3297	FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80, iemAImpl_fpatan_r80_by_r80_amd, iemAImpl_fpatan_r80_by_r80_intel;
3298	FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80, iemAImpl_fyl2x_r80_by_r80_amd, iemAImpl_fyl2x_r80_by_r80_intel;
3299	FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80, iemAImpl_fyl2xp1_r80_by_r80_amd, iemAImpl_fyl2xp1_r80_by_r80_intel;
3300
3301	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3302	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
3303	typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
3304	FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
3305	FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
3306
3307	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
3308	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
3309	typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
3310	FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
3311	FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
3312
3313	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
3314	typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
3315	FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
3316	FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
3317	FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80, iemAImpl_f2xm1_r80_amd, iemAImpl_f2xm1_r80_intel;
3318	FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
3319	FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
3320	FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80, iemAImpl_fsin_r80_amd, iemAImpl_fsin_r80_intel;
3321	FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80, iemAImpl_fcos_r80_amd, iemAImpl_fcos_r80_intel;
3322
3323	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
3324	typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
3325	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
3326	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
3327
3328	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
3329	typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
3330	FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
3331	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
3332	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
3333	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
3334	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
3335	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
3336	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
3337
3338	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
3339	PCRTFLOAT80U pr80Val));
3340	typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
3341	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80, iemAImpl_fptan_r80_r80_amd, iemAImpl_fptan_r80_r80_intel;
3342	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
3343	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80, iemAImpl_fsincos_r80_r80_amd, iemAImpl_fsincos_r80_r80_intel;
3344
3345	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
3346	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3347	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
3348
3349	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_d80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTPBCD80U pd80Val));
3350	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_d80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3351	PRTPBCD80U pd80Dst, PCRTFLOAT80U pr80Src));
3352
3353	/** @} */
3354
3355	/** @name FPU operations taking a 16-bit signed integer argument
3356	* @{ */
3357	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3358	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
3359	typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
3360	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI16,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3361	int16_t *pi16Dst, PCRTFLOAT80U pr80Src));
3362	typedef FNIEMAIMPLFPUSTR80TOI16 *PFNIEMAIMPLFPUSTR80TOI16;
3363
3364	FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
3365	FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
3366	FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
3367	FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
3368	FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
3369	FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
3370
3371	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3372	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
3373	typedef FNIEMAIMPLFPUI16FSW *PFNIEMAIMPLFPUI16FSW;
3374	FNIEMAIMPLFPUI16FSW iemAImpl_ficom_r80_by_i16;
3375
3376	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
3377	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fist_r80_to_i16;
3378	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fistt_r80_to_i16, iemAImpl_fistt_r80_to_i16_amd, iemAImpl_fistt_r80_to_i16_intel;
3379	/** @} */
3380
3381	/** @name FPU operations taking a 32-bit signed integer argument
3382	* @{ */
3383	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3384	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
3385	typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
3386	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI32,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3387	int32_t *pi32Dst, PCRTFLOAT80U pr80Src));
3388	typedef FNIEMAIMPLFPUSTR80TOI32 *PFNIEMAIMPLFPUSTR80TOI32;
3389
3390	FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
3391	FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
3392	FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
3393	FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
3394	FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
3395	FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
3396
3397	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3398	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
3399	typedef FNIEMAIMPLFPUI32FSW *PFNIEMAIMPLFPUI32FSW;
3400	FNIEMAIMPLFPUI32FSW iemAImpl_ficom_r80_by_i32;
3401
3402	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
3403	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fist_r80_to_i32;
3404	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fistt_r80_to_i32;
3405	/** @} */
3406
3407	/** @name FPU operations taking a 64-bit signed integer argument
3408	* @{ */
3409	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI64,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3410	int64_t *pi64Dst, PCRTFLOAT80U pr80Src));
3411	typedef FNIEMAIMPLFPUSTR80TOI64 *PFNIEMAIMPLFPUSTR80TOI64;
3412
3413	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
3414	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fist_r80_to_i64;
3415	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fistt_r80_to_i64;
3416	/** @} */
3417
3418
3419	/** Temporary type representing a 256-bit vector register. */
3420	typedef struct { uint64_t au64[4]; } IEMVMM256;
3421	/** Temporary type pointing to a 256-bit vector register. */
3422	typedef IEMVMM256 *PIEMVMM256;
3423	/** Temporary type pointing to a const 256-bit vector register. */
3424	typedef IEMVMM256 *PCIEMVMM256;
3425
3426
3427	/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
3428	* @{ */
3429	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t puDst, uint64_t const puSrc));
3430	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
3431	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U128,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
3432	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
3433	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U128,(PX86XSAVEAREA pExtState, PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
3434	typedef FNIEMAIMPLMEDIAF3U128 *PFNIEMAIMPLMEDIAF3U128;
3435	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U256,(PX86XSAVEAREA pExtState, PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
3436	typedef FNIEMAIMPLMEDIAF3U256 *PFNIEMAIMPLMEDIAF3U256;
3437	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U64,(uint64_t puDst, uint64_t const puSrc));
3438	typedef FNIEMAIMPLMEDIAOPTF2U64 *PFNIEMAIMPLMEDIAOPTF2U64;
3439	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128,(PRTUINT128U puDst, PCRTUINT128U puSrc));
3440	typedef FNIEMAIMPLMEDIAOPTF2U128 *PFNIEMAIMPLMEDIAOPTF2U128;
3441	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
3442	typedef FNIEMAIMPLMEDIAOPTF3U128 *PFNIEMAIMPLMEDIAOPTF3U128;
3443	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
3444	typedef FNIEMAIMPLMEDIAOPTF3U256 *PFNIEMAIMPLMEDIAOPTF3U256;
3445	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256,(PRTUINT256U puDst, PCRTUINT256U puSrc));
3446	typedef FNIEMAIMPLMEDIAOPTF2U256 *PFNIEMAIMPLMEDIAOPTF2U256;
3447	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pshufb_u64, iemAImpl_pshufb_u64_fallback;
3448	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pand_u64, iemAImpl_pandn_u64, iemAImpl_por_u64, iemAImpl_pxor_u64;
3449	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
3450	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pcmpgtb_u64, iemAImpl_pcmpgtw_u64, iemAImpl_pcmpgtd_u64;
3451	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddb_u64, iemAImpl_paddsb_u64, iemAImpl_paddusb_u64;
3452	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddw_u64, iemAImpl_paddsw_u64, iemAImpl_paddusw_u64;
3453	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddd_u64;
3454	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddq_u64;
3455	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubb_u64, iemAImpl_psubsb_u64, iemAImpl_psubusb_u64;
3456	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubw_u64, iemAImpl_psubsw_u64, iemAImpl_psubusw_u64;
3457	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubd_u64;
3458	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubq_u64;
3459	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmaddwd_u64, iemAImpl_pmaddwd_u64_fallback;
3460	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmullw_u64, iemAImpl_pmulhw_u64;
3461	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pminub_u64, iemAImpl_pmaxub_u64;
3462	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pminsw_u64, iemAImpl_pmaxsw_u64;
3463	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pabsb_u64, iemAImpl_pabsb_u64_fallback;
3464	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pabsw_u64, iemAImpl_pabsw_u64_fallback;
3465	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pabsd_u64, iemAImpl_pabsd_u64_fallback;
3466	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psignb_u64, iemAImpl_psignb_u64_fallback;
3467	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psignw_u64, iemAImpl_psignw_u64_fallback;
3468	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psignd_u64, iemAImpl_psignd_u64_fallback;
3469	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phaddw_u64, iemAImpl_phaddw_u64_fallback;
3470	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phaddd_u64, iemAImpl_phaddd_u64_fallback;
3471	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phsubw_u64, iemAImpl_phsubw_u64_fallback;
3472	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phsubd_u64, iemAImpl_phsubd_u64_fallback;
3473	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phaddsw_u64, iemAImpl_phaddsw_u64_fallback;
3474	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phsubsw_u64, iemAImpl_phsubsw_u64_fallback;
3475	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmaddubsw_u64, iemAImpl_pmaddubsw_u64_fallback;
3476	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhrsw_u64, iemAImpl_pmulhrsw_u64_fallback;
3477	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmuludq_u64;
3478	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllw_u64, iemAImpl_psrlw_u64, iemAImpl_psraw_u64;
3479	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pslld_u64, iemAImpl_psrld_u64, iemAImpl_psrad_u64;
3480	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllq_u64, iemAImpl_psrlq_u64;
3481	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packsswb_u64, iemAImpl_packuswb_u64;
3482	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packssdw_u64;
3483	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhuw_u64;
3484	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pavgb_u64, iemAImpl_pavgw_u64;
3485	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psadbw_u64;
3486
3487	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pshufb_u128, iemAImpl_pshufb_u128_fallback;
3488	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pand_u128, iemAImpl_pandn_u128, iemAImpl_por_u128, iemAImpl_pxor_u128;
3489	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
3490	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpeqq_u128, iemAImpl_pcmpeqq_u128_fallback;
3491	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpgtb_u128, iemAImpl_pcmpgtw_u128, iemAImpl_pcmpgtd_u128;
3492	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpgtq_u128, iemAImpl_pcmpgtq_u128_fallback;
3493	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddb_u128, iemAImpl_paddsb_u128, iemAImpl_paddusb_u128;
3494	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddw_u128, iemAImpl_paddsw_u128, iemAImpl_paddusw_u128;
3495	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddd_u128;
3496	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddq_u128;
3497	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubb_u128, iemAImpl_psubsb_u128, iemAImpl_psubusb_u128;
3498	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubw_u128, iemAImpl_psubsw_u128, iemAImpl_psubusw_u128;
3499	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubd_u128;
3500	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubq_u128;
3501	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmullw_u128, iemAImpl_pmullw_u128_fallback;
3502	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhw_u128;
3503	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulld_u128, iemAImpl_pmulld_u128_fallback;
3504	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaddwd_u128, iemAImpl_pmaddwd_u128_fallback;
3505	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminub_u128;
3506	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminud_u128, iemAImpl_pminud_u128_fallback;
3507	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminuw_u128, iemAImpl_pminuw_u128_fallback;
3508	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminsb_u128, iemAImpl_pminsb_u128_fallback;
3509	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminsd_u128, iemAImpl_pminsd_u128_fallback;
3510	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminsw_u128, iemAImpl_pminsw_u128_fallback;
3511	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxub_u128;
3512	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxud_u128, iemAImpl_pmaxud_u128_fallback;
3513	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxuw_u128, iemAImpl_pmaxuw_u128_fallback;
3514	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxsb_u128, iemAImpl_pmaxsb_u128_fallback;
3515	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxsw_u128;
3516	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxsd_u128, iemAImpl_pmaxsd_u128_fallback;
3517	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pabsb_u128, iemAImpl_pabsb_u128_fallback;
3518	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pabsw_u128, iemAImpl_pabsw_u128_fallback;
3519	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pabsd_u128, iemAImpl_pabsd_u128_fallback;
3520	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psignb_u128, iemAImpl_psignb_u128_fallback;
3521	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psignw_u128, iemAImpl_psignw_u128_fallback;
3522	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psignd_u128, iemAImpl_psignd_u128_fallback;
3523	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phaddw_u128, iemAImpl_phaddw_u128_fallback;
3524	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phaddd_u128, iemAImpl_phaddd_u128_fallback;
3525	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phsubw_u128, iemAImpl_phsubw_u128_fallback;
3526	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phsubd_u128, iemAImpl_phsubd_u128_fallback;
3527	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phaddsw_u128, iemAImpl_phaddsw_u128_fallback;
3528	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phsubsw_u128, iemAImpl_phsubsw_u128_fallback;
3529	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaddubsw_u128, iemAImpl_pmaddubsw_u128_fallback;
3530	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhrsw_u128, iemAImpl_pmulhrsw_u128_fallback;
3531	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuludq_u128;
3532	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaddwd_u128, iemAImpl_pmaddwd_u128_fallback;
3533	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packsswb_u128, iemAImpl_packuswb_u128;
3534	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packssdw_u128, iemAImpl_packusdw_u128;
3535	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllw_u128, iemAImpl_psrlw_u128, iemAImpl_psraw_u128;
3536	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pslld_u128, iemAImpl_psrld_u128, iemAImpl_psrad_u128;
3537	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllq_u128, iemAImpl_psrlq_u128;
3538	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhuw_u128;
3539	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pavgb_u128, iemAImpl_pavgw_u128;
3540	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psadbw_u128;
3541	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuldq_u128, iemAImpl_pmuldq_u128_fallback;
3542	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpcklps_u128, iemAImpl_unpcklpd_u128;
3543	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpckhps_u128, iemAImpl_unpckhpd_u128;
3544	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phminposuw_u128, iemAImpl_phminposuw_u128_fallback;
3545
3546	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpshufb_u128, iemAImpl_vpshufb_u128_fallback;
3547	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpand_u128, iemAImpl_vpand_u128_fallback;
3548	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpandn_u128, iemAImpl_vpandn_u128_fallback;
3549	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpor_u128, iemAImpl_vpor_u128_fallback;
3550	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpxor_u128, iemAImpl_vpxor_u128_fallback;
3551	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqb_u128, iemAImpl_vpcmpeqb_u128_fallback;
3552	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqw_u128, iemAImpl_vpcmpeqw_u128_fallback;
3553	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqd_u128, iemAImpl_vpcmpeqd_u128_fallback;
3554	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqq_u128, iemAImpl_vpcmpeqq_u128_fallback;
3555	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtb_u128, iemAImpl_vpcmpgtb_u128_fallback;
3556	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtw_u128, iemAImpl_vpcmpgtw_u128_fallback;
3557	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtd_u128, iemAImpl_vpcmpgtd_u128_fallback;
3558	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtq_u128, iemAImpl_vpcmpgtq_u128_fallback;
3559	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddb_u128, iemAImpl_vpaddb_u128_fallback;
3560	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddw_u128, iemAImpl_vpaddw_u128_fallback;
3561	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddd_u128, iemAImpl_vpaddd_u128_fallback;
3562	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddq_u128, iemAImpl_vpaddq_u128_fallback;
3563	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubb_u128, iemAImpl_vpsubb_u128_fallback;
3564	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubw_u128, iemAImpl_vpsubw_u128_fallback;
3565	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubd_u128, iemAImpl_vpsubd_u128_fallback;
3566	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubq_u128, iemAImpl_vpsubq_u128_fallback;
3567	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminub_u128, iemAImpl_vpminub_u128_fallback;
3568	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminuw_u128, iemAImpl_vpminuw_u128_fallback;
3569	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminud_u128, iemAImpl_vpminud_u128_fallback;
3570	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminsb_u128, iemAImpl_vpminsb_u128_fallback;
3571	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminsw_u128, iemAImpl_vpminsw_u128_fallback;
3572	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminsd_u128, iemAImpl_vpminsd_u128_fallback;
3573	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxub_u128, iemAImpl_vpmaxub_u128_fallback;
3574	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxuw_u128, iemAImpl_vpmaxuw_u128_fallback;
3575	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxud_u128, iemAImpl_vpmaxud_u128_fallback;
3576	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxsb_u128, iemAImpl_vpmaxsb_u128_fallback;
3577	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxsw_u128, iemAImpl_vpmaxsw_u128_fallback;
3578	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxsd_u128, iemAImpl_vpmaxsd_u128_fallback;
3579	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpacksswb_u128, iemAImpl_vpacksswb_u128_fallback;
3580	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackssdw_u128, iemAImpl_vpackssdw_u128_fallback;
3581	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackuswb_u128, iemAImpl_vpackuswb_u128_fallback;
3582	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackusdw_u128, iemAImpl_vpackusdw_u128_fallback;
3583	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmullw_u128, iemAImpl_vpmullw_u128_fallback;
3584	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulld_u128, iemAImpl_vpmulld_u128_fallback;
3585	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhw_u128, iemAImpl_vpmulhw_u128_fallback;
3586	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhuw_u128, iemAImpl_vpmulhuw_u128_fallback;
3587	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgb_u128, iemAImpl_vpavgb_u128_fallback;
3588	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgw_u128, iemAImpl_vpavgw_u128_fallback;
3589	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignb_u128, iemAImpl_vpsignb_u128_fallback;
3590	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignw_u128, iemAImpl_vpsignw_u128_fallback;
3591	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignd_u128, iemAImpl_vpsignd_u128_fallback;
3592	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddw_u128, iemAImpl_vphaddw_u128_fallback;
3593	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddd_u128, iemAImpl_vphaddd_u128_fallback;
3594	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubw_u128, iemAImpl_vphsubw_u128_fallback;
3595	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubd_u128, iemAImpl_vphsubd_u128_fallback;
3596	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddsw_u128, iemAImpl_vphaddsw_u128_fallback;
3597	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubsw_u128, iemAImpl_vphsubsw_u128_fallback;
3598	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddubsw_u128, iemAImpl_vpmaddubsw_u128_fallback;
3599	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhrsw_u128, iemAImpl_vpmulhrsw_u128_fallback;
3600	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsadbw_u128, iemAImpl_vpsadbw_u128_fallback;
3601	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuldq_u128, iemAImpl_vpmuldq_u128_fallback;
3602	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuludq_u128, iemAImpl_vpmuludq_u128_fallback;
3603	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsb_u128, iemAImpl_vpsubsb_u128_fallback;
3604	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsw_u128, iemAImpl_vpsubsw_u128_fallback;
3605	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusb_u128, iemAImpl_vpsubusb_u128_fallback;
3606	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusw_u128, iemAImpl_vpsubusw_u128_fallback;
3607	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusb_u128, iemAImpl_vpaddusb_u128_fallback;
3608	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusw_u128, iemAImpl_vpaddusw_u128_fallback;
3609	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsb_u128, iemAImpl_vpaddsb_u128_fallback;
3610	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsw_u128, iemAImpl_vpaddsw_u128_fallback;
3611	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllw_u128, iemAImpl_vpsllw_u128_fallback;
3612	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpslld_u128, iemAImpl_vpslld_u128_fallback;
3613	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllq_u128, iemAImpl_vpsllq_u128_fallback;
3614	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsraw_u128, iemAImpl_vpsraw_u128_fallback;
3615	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrad_u128, iemAImpl_vpsrad_u128_fallback;
3616	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlw_u128, iemAImpl_vpsrlw_u128_fallback;
3617	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrld_u128, iemAImpl_vpsrld_u128_fallback;
3618	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlq_u128, iemAImpl_vpsrlq_u128_fallback;
3619	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddwd_u128, iemAImpl_vpmaddwd_u128_fallback;
3620
3621	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsb_u128, iemAImpl_vpabsb_u128_fallback;
3622	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsw_u128, iemAImpl_vpabsd_u128_fallback;
3623	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsd_u128, iemAImpl_vpabsw_u128_fallback;
3624	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vphminposuw_u128, iemAImpl_vphminposuw_u128_fallback;
3625
3626	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpshufb_u256, iemAImpl_vpshufb_u256_fallback;
3627	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpand_u256, iemAImpl_vpand_u256_fallback;
3628	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpandn_u256, iemAImpl_vpandn_u256_fallback;
3629	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpor_u256, iemAImpl_vpor_u256_fallback;
3630	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpxor_u256, iemAImpl_vpxor_u256_fallback;
3631	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqb_u256, iemAImpl_vpcmpeqb_u256_fallback;
3632	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqw_u256, iemAImpl_vpcmpeqw_u256_fallback;
3633	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqd_u256, iemAImpl_vpcmpeqd_u256_fallback;
3634	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqq_u256, iemAImpl_vpcmpeqq_u256_fallback;
3635	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtb_u256, iemAImpl_vpcmpgtb_u256_fallback;
3636	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtw_u256, iemAImpl_vpcmpgtw_u256_fallback;
3637	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtd_u256, iemAImpl_vpcmpgtd_u256_fallback;
3638	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtq_u256, iemAImpl_vpcmpgtq_u256_fallback;
3639	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddb_u256, iemAImpl_vpaddb_u256_fallback;
3640	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddw_u256, iemAImpl_vpaddw_u256_fallback;
3641	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddd_u256, iemAImpl_vpaddd_u256_fallback;
3642	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddq_u256, iemAImpl_vpaddq_u256_fallback;
3643	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubb_u256, iemAImpl_vpsubb_u256_fallback;
3644	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubw_u256, iemAImpl_vpsubw_u256_fallback;
3645	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubd_u256, iemAImpl_vpsubd_u256_fallback;
3646	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubq_u256, iemAImpl_vpsubq_u256_fallback;
3647	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminub_u256, iemAImpl_vpminub_u256_fallback;
3648	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminuw_u256, iemAImpl_vpminuw_u256_fallback;
3649	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminud_u256, iemAImpl_vpminud_u256_fallback;
3650	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminsb_u256, iemAImpl_vpminsb_u256_fallback;
3651	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminsw_u256, iemAImpl_vpminsw_u256_fallback;
3652	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminsd_u256, iemAImpl_vpminsd_u256_fallback;
3653	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxub_u256, iemAImpl_vpmaxub_u256_fallback;
3654	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxuw_u256, iemAImpl_vpmaxuw_u256_fallback;
3655	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxud_u256, iemAImpl_vpmaxud_u256_fallback;
3656	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxsb_u256, iemAImpl_vpmaxsb_u256_fallback;
3657	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxsw_u256, iemAImpl_vpmaxsw_u256_fallback;
3658	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxsd_u256, iemAImpl_vpmaxsd_u256_fallback;
3659	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpacksswb_u256, iemAImpl_vpacksswb_u256_fallback;
3660	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackssdw_u256, iemAImpl_vpackssdw_u256_fallback;
3661	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackuswb_u256, iemAImpl_vpackuswb_u256_fallback;
3662	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackusdw_u256, iemAImpl_vpackusdw_u256_fallback;
3663	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmullw_u256, iemAImpl_vpmullw_u256_fallback;
3664	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulld_u256, iemAImpl_vpmulld_u256_fallback;
3665	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhw_u256, iemAImpl_vpmulhw_u256_fallback;
3666	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhuw_u256, iemAImpl_vpmulhuw_u256_fallback;
3667	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgb_u256, iemAImpl_vpavgb_u256_fallback;
3668	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgw_u256, iemAImpl_vpavgw_u256_fallback;
3669	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignb_u256, iemAImpl_vpsignb_u256_fallback;
3670	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignw_u256, iemAImpl_vpsignw_u256_fallback;
3671	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignd_u256, iemAImpl_vpsignd_u256_fallback;
3672	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddw_u256, iemAImpl_vphaddw_u256_fallback;
3673	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddd_u256, iemAImpl_vphaddd_u256_fallback;
3674	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubw_u256, iemAImpl_vphsubw_u256_fallback;
3675	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubd_u256, iemAImpl_vphsubd_u256_fallback;
3676	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddsw_u256, iemAImpl_vphaddsw_u256_fallback;
3677	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubsw_u256, iemAImpl_vphsubsw_u256_fallback;
3678	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddubsw_u256, iemAImpl_vpmaddubsw_u256_fallback;
3679	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhrsw_u256, iemAImpl_vpmulhrsw_u256_fallback;
3680	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsadbw_u256, iemAImpl_vpsadbw_u256_fallback;
3681	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuldq_u256, iemAImpl_vpmuldq_u256_fallback;
3682	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuludq_u256, iemAImpl_vpmuludq_u256_fallback;
3683	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsb_u256, iemAImpl_vpsubsb_u256_fallback;
3684	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsw_u256, iemAImpl_vpsubsw_u256_fallback;
3685	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusb_u256, iemAImpl_vpsubusb_u256_fallback;
3686	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusw_u256, iemAImpl_vpsubusw_u256_fallback;
3687	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusb_u256, iemAImpl_vpaddusb_u256_fallback;
3688	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusw_u256, iemAImpl_vpaddusw_u256_fallback;
3689	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsb_u256, iemAImpl_vpaddsb_u256_fallback;
3690	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsw_u256, iemAImpl_vpaddsw_u256_fallback;
3691	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllw_u256, iemAImpl_vpsllw_u256_fallback;
3692	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpslld_u256, iemAImpl_vpslld_u256_fallback;
3693	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllq_u256, iemAImpl_vpsllq_u256_fallback;
3694	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsraw_u256, iemAImpl_vpsraw_u256_fallback;
3695	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrad_u256, iemAImpl_vpsrad_u256_fallback;
3696	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlw_u256, iemAImpl_vpsrlw_u256_fallback;
3697	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrld_u256, iemAImpl_vpsrld_u256_fallback;
3698	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlq_u256, iemAImpl_vpsrlq_u256_fallback;
3699	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddwd_u256, iemAImpl_vpmaddwd_u256_fallback;
3700
3701	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsb_u256, iemAImpl_vpabsb_u256_fallback;
3702	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsw_u256, iemAImpl_vpabsw_u256_fallback;
3703	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsd_u256, iemAImpl_vpabsd_u256_fallback;
3704	/** @} */
3705
3706	/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
3707	* @{ */
3708	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
3709	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
3710	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpcklbw_u128, iemAImpl_vpunpcklbw_u128_fallback,
3711	iemAImpl_vpunpcklwd_u128, iemAImpl_vpunpcklwd_u128_fallback,
3712	iemAImpl_vpunpckldq_u128, iemAImpl_vpunpckldq_u128_fallback,
3713	iemAImpl_vpunpcklqdq_u128, iemAImpl_vpunpcklqdq_u128_fallback,
3714	iemAImpl_vunpcklps_u128, iemAImpl_vunpcklps_u128_fallback,
3715	iemAImpl_vunpcklpd_u128, iemAImpl_vunpcklpd_u128_fallback,
3716	iemAImpl_vunpckhps_u128, iemAImpl_vunpckhps_u128_fallback,
3717	iemAImpl_vunpckhpd_u128, iemAImpl_vunpckhpd_u128_fallback;
3718
3719	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpcklbw_u256, iemAImpl_vpunpcklbw_u256_fallback,
3720	iemAImpl_vpunpcklwd_u256, iemAImpl_vpunpcklwd_u256_fallback,
3721	iemAImpl_vpunpckldq_u256, iemAImpl_vpunpckldq_u256_fallback,
3722	iemAImpl_vpunpcklqdq_u256, iemAImpl_vpunpcklqdq_u256_fallback,
3723	iemAImpl_vunpcklps_u256, iemAImpl_vunpcklps_u256_fallback,
3724	iemAImpl_vunpcklpd_u256, iemAImpl_vunpcklpd_u256_fallback,
3725	iemAImpl_vunpckhps_u256, iemAImpl_vunpckhps_u256_fallback,
3726	iemAImpl_vunpckhpd_u256, iemAImpl_vunpckhpd_u256_fallback;
3727	/** @} */
3728
3729	/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
3730	* @{ */
3731	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
3732	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
3733	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpckhbw_u128, iemAImpl_vpunpckhbw_u128_fallback,
3734	iemAImpl_vpunpckhwd_u128, iemAImpl_vpunpckhwd_u128_fallback,
3735	iemAImpl_vpunpckhdq_u128, iemAImpl_vpunpckhdq_u128_fallback,
3736	iemAImpl_vpunpckhqdq_u128, iemAImpl_vpunpckhqdq_u128_fallback;
3737	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpckhbw_u256, iemAImpl_vpunpckhbw_u256_fallback,
3738	iemAImpl_vpunpckhwd_u256, iemAImpl_vpunpckhwd_u256_fallback,
3739	iemAImpl_vpunpckhdq_u256, iemAImpl_vpunpckhdq_u256_fallback,
3740	iemAImpl_vpunpckhqdq_u256, iemAImpl_vpunpckhqdq_u256_fallback;
3741	/** @} */
3742
3743	/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
3744	* @{ */
3745	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3746	typedef FNIEMAIMPLMEDIAPSHUFU128 *PFNIEMAIMPLMEDIAPSHUFU128;
3747	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
3748	typedef FNIEMAIMPLMEDIAPSHUFU256 *PFNIEMAIMPLMEDIAPSHUFU256;
3749	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw_u64,(uint64_t puDst, uint64_t const puSrc, uint8_t bEvil));
3750	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_pshufhw_u128, iemAImpl_pshuflw_u128, iemAImpl_pshufd_u128;
3751	#ifndef IEM_WITHOUT_ASSEMBLY
3752	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256, iemAImpl_vpshuflw_u256, iemAImpl_vpshufd_u256;
3753	#endif
3754	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256_fallback, iemAImpl_vpshuflw_u256_fallback, iemAImpl_vpshufd_u256_fallback;
3755	/** @} */
3756
3757	/** @name Media (SSE/MMX/AVX) operation: Shift Immediate Stuff (evil)
3758	* @{ */
3759	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU64,(uint64_t *puDst, uint8_t bShift));
3760	typedef FNIEMAIMPLMEDIAPSHIFTU64 *PFNIEMAIMPLMEDIAPSHIFTU64;
3761	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU128,(PRTUINT128U puDst, uint8_t bShift));
3762	typedef FNIEMAIMPLMEDIAPSHIFTU128 *PFNIEMAIMPLMEDIAPSHIFTU128;
3763	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU256,(PRTUINT256U puDst, uint8_t bShift));
3764	typedef FNIEMAIMPLMEDIAPSHIFTU256 *PFNIEMAIMPLMEDIAPSHIFTU256;
3765	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psllw_imm_u64, iemAImpl_pslld_imm_u64, iemAImpl_psllq_imm_u64;
3766	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psrlw_imm_u64, iemAImpl_psrld_imm_u64, iemAImpl_psrlq_imm_u64;
3767	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psraw_imm_u64, iemAImpl_psrad_imm_u64;
3768	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psllw_imm_u128, iemAImpl_pslld_imm_u128, iemAImpl_psllq_imm_u128;
3769	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psrlw_imm_u128, iemAImpl_psrld_imm_u128, iemAImpl_psrlq_imm_u128;
3770	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psraw_imm_u128, iemAImpl_psrad_imm_u128;
3771	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_pslldq_imm_u128, iemAImpl_psrldq_imm_u128;
3772	/** @} */
3773
3774	/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
3775	* @{ */
3776	IEM_DECL_IMPL_DEF(void, iemAImpl_maskmovq_u64,(uint64_t puMem, uint64_t const puSrc, uint64_t const *puMsk));
3777	IEM_DECL_IMPL_DEF(void, iemAImpl_maskmovdqu_u128,(PRTUINT128U puMem, PCRTUINT128U puSrc, PCRTUINT128U puMsk));
3778	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(uint64_t pu64Dst, uint64_t const puSrc));
3779	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(uint64_t *pu64Dst, PCRTUINT128U puSrc));
3780	#ifndef IEM_WITHOUT_ASSEMBLY
3781	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
3782	#endif
3783	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256_fallback,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
3784	/** @} */
3785
3786	/** @name Media (SSE/MMX/AVX) operations: Variable Blend Packed Bytes/R32/R64.
3787	* @{ */
3788	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puMask));
3789	typedef FNIEMAIMPLBLENDU128 *PFNIEMAIMPLBLENDU128;
3790	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, PCRTUINT128U puMask));
3791	typedef FNIEMAIMPLAVXBLENDU128 *PFNIEMAIMPLAVXBLENDU128;
3792	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, PCRTUINT256U puMask));
3793	typedef FNIEMAIMPLAVXBLENDU256 *PFNIEMAIMPLAVXBLENDU256;
3794
3795	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128;
3796	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128_fallback;
3797	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128;
3798	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128_fallback;
3799	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256;
3800	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256_fallback;
3801
3802	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128;
3803	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128_fallback;
3804	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128;
3805	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128_fallback;
3806	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256;
3807	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256_fallback;
3808
3809	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128;
3810	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128_fallback;
3811	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128;
3812	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128_fallback;
3813	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256;
3814	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256_fallback;
3815	/** @} */
3816
3817
3818	/** @name Media (SSE/MMX/AVX) operation: Sort this later
3819	* @{ */
3820	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3821	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3822	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3823	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3824	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3825
3826	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3827	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3828	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3829	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3830	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3831
3832	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3833	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3834	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
3835	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3836	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3837
3838	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3839	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3840	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3841	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3842	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3843
3844	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3845	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3846	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3847	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3848	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3849
3850	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3851	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3852	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3853	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3854	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3855
3856	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3857	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3858	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3859	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3860	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3861
3862	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3863	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3864	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3865	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3866	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3867
3868	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3869	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3870	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
3871	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3872	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3873
3874	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3875	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3876	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3877	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3878	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3879
3880	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3881	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3882	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3883	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3884	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3885
3886	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3887	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3888	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3889	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3890	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3891
3892	IEM_DECL_IMPL_DEF(void, iemAImpl_shufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3893	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3894	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3895	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3896	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3897
3898	IEM_DECL_IMPL_DEF(void, iemAImpl_shufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3899	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3900	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3901	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3902	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3903
3904	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
3905	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64_fallback,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
3906
3907	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3908	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3909	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3910	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3911	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3912
3913	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3914	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3915	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3916	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3917	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3918
3919
3920	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3921	typedef FNIEMAIMPLMEDIAOPTF2U128IMM8 *PFNIEMAIMPLMEDIAOPTF2U128IMM8;
3922	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
3923	typedef FNIEMAIMPLMEDIAOPTF2U256IMM8 *PFNIEMAIMPLMEDIAOPTF2U256IMM8;
3924	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3925	typedef FNIEMAIMPLMEDIAOPTF3U128IMM8 *PFNIEMAIMPLMEDIAOPTF3U128IMM8;
3926	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3927	typedef FNIEMAIMPLMEDIAOPTF3U256IMM8 *PFNIEMAIMPLMEDIAOPTF3U256IMM8;
3928
3929	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_palignr_u128, iemAImpl_palignr_u128_fallback;
3930	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pblendw_u128, iemAImpl_pblendw_u128_fallback;
3931	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendps_u128, iemAImpl_blendps_u128_fallback;
3932	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendpd_u128, iemAImpl_blendpd_u128_fallback;
3933
3934	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpalignr_u128, iemAImpl_vpalignr_u128_fallback;
3935	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendw_u128, iemAImpl_vpblendw_u128_fallback;
3936	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendd_u128, iemAImpl_vpblendd_u128_fallback;
3937	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendps_u128, iemAImpl_vblendps_u128_fallback;
3938	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendpd_u128, iemAImpl_vblendpd_u128_fallback;
3939
3940	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpalignr_u256, iemAImpl_vpalignr_u256_fallback;
3941	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendw_u256, iemAImpl_vpblendw_u256_fallback;
3942	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendd_u256, iemAImpl_vpblendd_u256_fallback;
3943	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendps_u256, iemAImpl_vblendps_u256_fallback;
3944	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendpd_u256, iemAImpl_vblendpd_u256_fallback;
3945	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2i128_u256, iemAImpl_vperm2i128_u256_fallback;
3946	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2f128_u256, iemAImpl_vperm2f128_u256_fallback;
3947
3948	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesimc_u128, iemAImpl_aesimc_u128_fallback;
3949	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenc_u128, iemAImpl_aesenc_u128_fallback;
3950	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenclast_u128, iemAImpl_aesenclast_u128_fallback;
3951	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdec_u128, iemAImpl_aesdec_u128_fallback;
3952	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdeclast_u128, iemAImpl_aesdeclast_u128_fallback;
3953
3954	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesimc_u128, iemAImpl_vaesimc_u128_fallback;
3955	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenc_u128, iemAImpl_vaesenc_u128_fallback;
3956	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenclast_u128, iemAImpl_vaesenclast_u128_fallback;
3957	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdec_u128, iemAImpl_vaesdec_u128_fallback;
3958	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdeclast_u128, iemAImpl_vaesdeclast_u128_fallback;
3959
3960	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_aeskeygenassist_u128, iemAImpl_aeskeygenassist_u128_fallback;
3961
3962	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vaeskeygenassist_u128, iemAImpl_vaeskeygenassist_u128_fallback;
3963
3964	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1nexte_u128, iemAImpl_sha1nexte_u128_fallback;
3965	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg1_u128, iemAImpl_sha1msg1_u128_fallback;
3966	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg2_u128, iemAImpl_sha1msg2_u128_fallback;
3967	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg1_u128, iemAImpl_sha256msg1_u128_fallback;
3968	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg2_u128, iemAImpl_sha256msg2_u128_fallback;
3969	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_sha1rnds4_u128, iemAImpl_sha1rnds4_u128_fallback;
3970	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
3971	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
3972
3973	typedef struct IEMPCMPISTRXSRC
3974	{
3975	RTUINT128U uSrc1;
3976	RTUINT128U uSrc2;
3977	} IEMPCMPISTRXSRC;
3978	typedef IEMPCMPISTRXSRC *PIEMPCMPISTRXSRC;
3979	typedef const IEMPCMPISTRXSRC *PCIEMPCMPISTRXSRC;
3980
3981	typedef struct IEMPCMPESTRXSRC
3982	{
3983	RTUINT128U uSrc1;
3984	RTUINT128U uSrc2;
3985	uint64_t u64Rax;
3986	uint64_t u64Rdx;
3987	} IEMPCMPESTRXSRC;
3988	typedef IEMPCMPESTRXSRC *PIEMPCMPESTRXSRC;
3989	typedef const IEMPCMPESTRXSRC *PCIEMPCMPESTRXSRC;
3990
3991	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLPCMPISTRIU128IMM8,(uint32_t *pEFlags, PCRTUINT128U pSrc1, PCRTUINT128U pSrc2, uint8_t bEvil));
3992	typedef FNIEMAIMPLPCMPISTRIU128IMM8 *PFNIEMAIMPLPCMPISTRIU128IMM8;
3993	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRIU128IMM8,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
3994	typedef FNIEMAIMPLPCMPESTRIU128IMM8 *PFNIEMAIMPLPCMPESTRIU128IMM8;
3995
3996	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPISTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
3997	typedef FNIEMAIMPLPCMPISTRMU128IMM8 *PFNIEMAIMPLPCMPISTRMU128IMM8;
3998	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
3999	typedef FNIEMAIMPLPCMPESTRMU128IMM8 *PFNIEMAIMPLPCMPESTRMU128IMM8;
4000
4001	FNIEMAIMPLPCMPISTRIU128IMM8 iemAImpl_pcmpistri_u128, iemAImpl_pcmpistri_u128_fallback;
4002	FNIEMAIMPLPCMPESTRIU128IMM8 iemAImpl_pcmpestri_u128, iemAImpl_pcmpestri_u128_fallback;
4003	FNIEMAIMPLPCMPISTRMU128IMM8 iemAImpl_pcmpistrm_u128, iemAImpl_pcmpistrm_u128_fallback;
4004	FNIEMAIMPLPCMPESTRMU128IMM8 iemAImpl_pcmpestrm_u128, iemAImpl_pcmpestrm_u128_fallback;
4005
4006	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pclmulqdq_u128, iemAImpl_pclmulqdq_u128_fallback;
4007	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpclmulqdq_u128, iemAImpl_vpclmulqdq_u128_fallback;
4008
4009	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_mpsadbw_u128, iemAImpl_mpsadbw_u128_fallback;
4010	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vmpsadbw_u128, iemAImpl_vmpsadbw_u128_fallback;
4011	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vmpsadbw_u256, iemAImpl_vmpsadbw_u256_fallback;
4012
4013	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsllw_imm_u128, iemAImpl_vpsllw_imm_u128_fallback;
4014	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsllw_imm_u256, iemAImpl_vpsllw_imm_u256_fallback;
4015	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpslld_imm_u128, iemAImpl_vpslld_imm_u128_fallback;
4016	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpslld_imm_u256, iemAImpl_vpslld_imm_u256_fallback;
4017	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsllq_imm_u128, iemAImpl_vpsllq_imm_u128_fallback;
4018	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsllq_imm_u256, iemAImpl_vpsllq_imm_u256_fallback;
4019	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
4020	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
4021	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
4022	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
4023
4024	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsraw_imm_u128, iemAImpl_vpsraw_imm_u128_fallback;
4025	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsraw_imm_u256, iemAImpl_vpsraw_imm_u256_fallback;
4026	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrad_imm_u128, iemAImpl_vpsrad_imm_u128_fallback;
4027	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrad_imm_u256, iemAImpl_vpsrad_imm_u256_fallback;
4028
4029	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrlw_imm_u128, iemAImpl_vpsrlw_imm_u128_fallback;
4030	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrlw_imm_u256, iemAImpl_vpsrlw_imm_u256_fallback;
4031	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrld_imm_u128, iemAImpl_vpsrld_imm_u128_fallback;
4032	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrld_imm_u256, iemAImpl_vpsrld_imm_u256_fallback;
4033	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrlq_imm_u128, iemAImpl_vpsrlq_imm_u128_fallback;
4034	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrlq_imm_u256, iemAImpl_vpsrlq_imm_u256_fallback;
4035	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
4036	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
4037	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
4038	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
4039
4040	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpermilps_u128, iemAImpl_vpermilps_u128_fallback;
4041	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_vpermilps_imm_u128, iemAImpl_vpermilps_imm_u128_fallback;
4042	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpermilps_u256, iemAImpl_vpermilps_u256_fallback;
4043	FNIEMAIMPLMEDIAOPTF2U256IMM8 iemAImpl_vpermilps_imm_u256, iemAImpl_vpermilps_imm_u256_fallback;
4044
4045	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpermilpd_u128, iemAImpl_vpermilpd_u128_fallback;
4046	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_vpermilpd_imm_u128, iemAImpl_vpermilpd_imm_u128_fallback;
4047	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpermilpd_u256, iemAImpl_vpermilpd_u256_fallback;
4048	FNIEMAIMPLMEDIAOPTF2U256IMM8 iemAImpl_vpermilpd_imm_u256, iemAImpl_vpermilpd_imm_u256_fallback;
4049
4050	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllvd_u128, iemAImpl_vpsllvd_u128_fallback;
4051	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllvd_u256, iemAImpl_vpsllvd_u256_fallback;
4052	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllvq_u128, iemAImpl_vpsllvq_u128_fallback;
4053	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllvq_u256, iemAImpl_vpsllvq_u256_fallback;
4054	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsravd_u128, iemAImpl_vpsravd_u128_fallback;
4055	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsravd_u256, iemAImpl_vpsravd_u256_fallback;
4056	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlvd_u128, iemAImpl_vpsrlvd_u128_fallback;
4057	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlvd_u256, iemAImpl_vpsrlvd_u256_fallback;
4058	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlvq_u128, iemAImpl_vpsrlvq_u128_fallback;
4059	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlvq_u256, iemAImpl_vpsrlvq_u256_fallback;
4060	/** @} */
4061
4062	/** @name Media Odds and Ends
4063	* @{ */
4064	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U8,(uint32_t *puDst, uint8_t uSrc));
4065	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U16,(uint32_t *puDst, uint16_t uSrc));
4066	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U32,(uint32_t *puDst, uint32_t uSrc));
4067	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U64,(uint32_t *puDst, uint64_t uSrc));
4068	FNIEMAIMPLCR32U8 iemAImpl_crc32_u8, iemAImpl_crc32_u8_fallback;
4069	FNIEMAIMPLCR32U16 iemAImpl_crc32_u16, iemAImpl_crc32_u16_fallback;
4070	FNIEMAIMPLCR32U32 iemAImpl_crc32_u32, iemAImpl_crc32_u32_fallback;
4071	FNIEMAIMPLCR32U64 iemAImpl_crc32_u64, iemAImpl_crc32_u64_fallback;
4072
4073	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL128,(PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint32_t *pEFlags));
4074	typedef FNIEMAIMPLF2EFL128 *PFNIEMAIMPLF2EFL128;
4075	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL256,(PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint32_t *pEFlags));
4076	typedef FNIEMAIMPLF2EFL256 *PFNIEMAIMPLF2EFL256;
4077	FNIEMAIMPLF2EFL128 iemAImpl_ptest_u128;
4078	FNIEMAIMPLF2EFL256 iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback;
4079	FNIEMAIMPLF2EFL128 iemAImpl_vtestps_u128, iemAImpl_vtestps_u128_fallback;
4080	FNIEMAIMPLF2EFL256 iemAImpl_vtestps_u256, iemAImpl_vtestps_u256_fallback;
4081	FNIEMAIMPLF2EFL128 iemAImpl_vtestpd_u128, iemAImpl_vtestpd_u128_fallback;
4082	FNIEMAIMPLF2EFL256 iemAImpl_vtestpd_u256, iemAImpl_vtestpd_u256_fallback;
4083
4084	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I32U64,(uint32_t uMxCsrIn, int32_t pi32Dst, const uint64_t pu64Src)); /* pu64Src is a double precision floating point. */
4085	typedef FNIEMAIMPLSSEF2I32U64 *PFNIEMAIMPLSSEF2I32U64;
4086	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I64U64,(uint32_t uMxCsrIn, int64_t pi64Dst, const uint64_t pu64Src)); /* pu64Src is a double precision floating point. */
4087	typedef FNIEMAIMPLSSEF2I64U64 *PFNIEMAIMPLSSEF2I64U64;
4088	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I32U32,(uint32_t uMxCsrIn, int32_t pi32Dst, const uint32_t pu32Src)); /* pu32Src is a single precision floating point. */
4089	typedef FNIEMAIMPLSSEF2I32U32 *PFNIEMAIMPLSSEF2I32U32;
4090	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I64U32,(uint32_t uMxCsrIn, int64_t pi64Dst, const uint32_t pu32Src)); /* pu32Src is a single precision floating point. */
4091	typedef FNIEMAIMPLSSEF2I64U32 *PFNIEMAIMPLSSEF2I64U32;
4092
4093	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvttsd2si_i32_r64;
4094	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvtsd2si_i32_r64;
4095
4096	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvttsd2si_i64_r64;
4097	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvtsd2si_i64_r64;
4098
4099	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvttss2si_i32_r32;
4100	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvtss2si_i32_r32;
4101
4102	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvttss2si_i64_r32;
4103	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvtss2si_i64_r32;
4104
4105	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R32I32,(uint32_t uMxCsrIn, PRTFLOAT32U pr32Dst, const int32_t *pi32Src));
4106	typedef FNIEMAIMPLSSEF2R32I32 *PFNIEMAIMPLSSEF2R32I32;
4107	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R32I64,(uint32_t uMxCsrIn, PRTFLOAT32U pr32Dst, const int64_t *pi64Src));
4108	typedef FNIEMAIMPLSSEF2R32I64 *PFNIEMAIMPLSSEF2R32I64;
4109
4110	FNIEMAIMPLSSEF2R32I32 iemAImpl_cvtsi2ss_r32_i32;
4111	FNIEMAIMPLSSEF2R32I64 iemAImpl_cvtsi2ss_r32_i64;
4112
4113	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R64I32,(uint32_t uMxCsrIn, PRTFLOAT64U pr64Dst, const int32_t *pi32Src));
4114	typedef FNIEMAIMPLSSEF2R64I32 *PFNIEMAIMPLSSEF2R64I32;
4115	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R64I64,(uint32_t uMxCsrIn, PRTFLOAT64U pr64Dst, const int64_t *pi64Src));
4116	typedef FNIEMAIMPLSSEF2R64I64 *PFNIEMAIMPLSSEF2R64I64;
4117
4118	FNIEMAIMPLSSEF2R64I32 iemAImpl_cvtsi2sd_r64_i32;
4119	FNIEMAIMPLSSEF2R64I64 iemAImpl_cvtsi2sd_r64_i64;
4120
4121
4122	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLF2EFLMXCSRR32R32,(uint32_t uMxCsrIn, uint32_t *pfEFlags, RTFLOAT32U uSrc1, RTFLOAT32U uSrc2));
4123	typedef FNIEMAIMPLF2EFLMXCSRR32R32 *PFNIEMAIMPLF2EFLMXCSRR32R32;
4124
4125	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLF2EFLMXCSRR64R64,(uint32_t uMxCsrIn, uint32_t *pfEFlags, RTFLOAT64U uSrc1, RTFLOAT64U uSrc2));
4126	typedef FNIEMAIMPLF2EFLMXCSRR64R64 *PFNIEMAIMPLF2EFLMXCSRR64R64;
4127
4128	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_ucomiss_u128;
4129	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback;
4130
4131	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_ucomisd_u128;
4132	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback;
4133
4134	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_comiss_u128;
4135	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback;
4136
4137	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_comisd_u128;
4138	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback;
4139
4140
4141	typedef struct IEMMEDIAF2XMMSRC
4142	{
4143	X86XMMREG uSrc1;
4144	X86XMMREG uSrc2;
4145	} IEMMEDIAF2XMMSRC;
4146	typedef IEMMEDIAF2XMMSRC *PIEMMEDIAF2XMMSRC;
4147	typedef const IEMMEDIAF2XMMSRC *PCIEMMEDIAF2XMMSRC;
4148
4149	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRF2XMMIMM8,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCIEMMEDIAF2XMMSRC puSrc, uint8_t bEvil));
4150	typedef FNIEMAIMPLMXCSRF2XMMIMM8 *PFNIEMAIMPLMXCSRF2XMMIMM8;
4151
4152	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpps_u128;
4153	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmppd_u128;
4154	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpss_u128;
4155	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpsd_u128;
4156	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundss_u128;
4157	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundsd_u128;
4158
4159	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundps_u128, iemAImpl_roundps_u128_fallback;
4160	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundpd_u128, iemAImpl_roundpd_u128_fallback;
4161
4162	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_dpps_u128, iemAImpl_dpps_u128_fallback;
4163	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_dppd_u128, iemAImpl_dppd_u128_fallback;
4164
4165	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRU64U128,(uint32_t fMxCsrIn, uint64_t *pu64Dst, PCX86XMMREG pSrc));
4166	typedef FNIEMAIMPLMXCSRU64U128 *PFNIEMAIMPLMXCSRU64U128;
4167
4168	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvtpd2pi_u128;
4169	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvttpd2pi_u128;
4170
4171	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRU128U64,(uint32_t fMxCsrIn, PX86XMMREG pDst, uint64_t u64Src));
4172	typedef FNIEMAIMPLMXCSRU128U64 *PFNIEMAIMPLMXCSRU128U64;
4173
4174	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2ps_u128;
4175	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2pd_u128;
4176
4177	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRU64U64,(uint32_t fMxCsrIn, uint64_t *pu64Dst, uint64_t u64Src));
4178	typedef FNIEMAIMPLMXCSRU64U64 *PFNIEMAIMPLMXCSRU64U64;
4179
4180	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvtps2pi_u128;
4181	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvttps2pi_u128;
4182
4183	/** @} */
4184
4185
4186	/** @name Function tables.
4187	* @{
4188	*/
4189
4190	/**
4191	* Function table for a binary operator providing implementation based on
4192	* operand size.
4193	*/
4194	typedef struct IEMOPBINSIZES
4195	{
4196	PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
4197	PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
4198	PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
4199	PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
4200	} IEMOPBINSIZES;
4201	/** Pointer to a binary operator function table. */
4202	typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
4203
4204
4205	/**
4206	* Function table for a unary operator providing implementation based on
4207	* operand size.
4208	*/
4209	typedef struct IEMOPUNARYSIZES
4210	{
4211	PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
4212	PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
4213	PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
4214	PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
4215	} IEMOPUNARYSIZES;
4216	/** Pointer to a unary operator function table. */
4217	typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
4218
4219
4220	/**
4221	* Function table for a shift operator providing implementation based on
4222	* operand size.
4223	*/
4224	typedef struct IEMOPSHIFTSIZES
4225	{
4226	PFNIEMAIMPLSHIFTU8 pfnNormalU8;
4227	PFNIEMAIMPLSHIFTU16 pfnNormalU16;
4228	PFNIEMAIMPLSHIFTU32 pfnNormalU32;
4229	PFNIEMAIMPLSHIFTU64 pfnNormalU64;
4230	} IEMOPSHIFTSIZES;
4231	/** Pointer to a shift operator function table. */
4232	typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
4233
4234
4235	/**
4236	* Function table for a multiplication or division operation.
4237	*/
4238	typedef struct IEMOPMULDIVSIZES
4239	{
4240	PFNIEMAIMPLMULDIVU8 pfnU8;
4241	PFNIEMAIMPLMULDIVU16 pfnU16;
4242	PFNIEMAIMPLMULDIVU32 pfnU32;
4243	PFNIEMAIMPLMULDIVU64 pfnU64;
4244	} IEMOPMULDIVSIZES;
4245	/** Pointer to a multiplication or division operation function table. */
4246	typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
4247
4248
4249	/**
4250	* Function table for a double precision shift operator providing implementation
4251	* based on operand size.
4252	*/
4253	typedef struct IEMOPSHIFTDBLSIZES
4254	{
4255	PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
4256	PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
4257	PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
4258	} IEMOPSHIFTDBLSIZES;
4259	/** Pointer to a double precision shift function table. */
4260	typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
4261
4262
4263	/**
4264	* Function table for media instruction taking two full sized media source
4265	* registers and one full sized destination register (AVX).
4266	*/
4267	typedef struct IEMOPMEDIAF3
4268	{
4269	PFNIEMAIMPLMEDIAF3U128 pfnU128;
4270	PFNIEMAIMPLMEDIAF3U256 pfnU256;
4271	} IEMOPMEDIAF3;
4272	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
4273	typedef IEMOPMEDIAF3 const *PCIEMOPMEDIAF3;
4274
4275	/** @def IEMOPMEDIAF3_INIT_VARS_EX
4276	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4277	* given functions as initializers. For use in AVX functions where a pair of
4278	* functions are only used once and the function table need not be public. */
4279	#ifndef TST_IEM_CHECK_MC
4280	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4281	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4282	static IEMOPMEDIAF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4283	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4284	# else
4285	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4286	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4287	# endif
4288	#else
4289	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4290	#endif
4291	/** @def IEMOPMEDIAF3_INIT_VARS
4292	* Generate AVX function tables for the @a a_InstrNm instruction.
4293	* @sa IEMOPMEDIAF3_INIT_VARS_EX */
4294	#define IEMOPMEDIAF3_INIT_VARS(a_InstrNm) \
4295	IEMOPMEDIAF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4296	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4297
4298	/**
4299	* Function table for media instruction taking two full sized media source
4300	* registers and one full sized destination register, but no additional state
4301	* (AVX).
4302	*/
4303	typedef struct IEMOPMEDIAOPTF3
4304	{
4305	PFNIEMAIMPLMEDIAOPTF3U128 pfnU128;
4306	PFNIEMAIMPLMEDIAOPTF3U256 pfnU256;
4307	} IEMOPMEDIAOPTF3;
4308	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
4309	typedef IEMOPMEDIAOPTF3 const *PCIEMOPMEDIAOPTF3;
4310
4311	/** @def IEMOPMEDIAOPTF3_INIT_VARS_EX
4312	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4313	* given functions as initializers. For use in AVX functions where a pair of
4314	* functions are only used once and the function table need not be public. */
4315	#ifndef TST_IEM_CHECK_MC
4316	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4317	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4318	static IEMOPMEDIAOPTF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4319	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4320	# else
4321	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4322	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4323	# endif
4324	#else
4325	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4326	#endif
4327	/** @def IEMOPMEDIAOPTF3_INIT_VARS
4328	* Generate AVX function tables for the @a a_InstrNm instruction.
4329	* @sa IEMOPMEDIAOPTF3_INIT_VARS_EX */
4330	#define IEMOPMEDIAOPTF3_INIT_VARS(a_InstrNm) \
4331	IEMOPMEDIAOPTF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4332	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4333
4334	/**
4335	* Function table for media instruction taking one full sized media source
4336	* registers and one full sized destination register, but no additional state
4337	* (AVX).
4338	*/
4339	typedef struct IEMOPMEDIAOPTF2
4340	{
4341	PFNIEMAIMPLMEDIAOPTF2U128 pfnU128;
4342	PFNIEMAIMPLMEDIAOPTF2U256 pfnU256;
4343	} IEMOPMEDIAOPTF2;
4344	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
4345	typedef IEMOPMEDIAOPTF2 const *PCIEMOPMEDIAOPTF2;
4346
4347	/** @def IEMOPMEDIAOPTF2_INIT_VARS_EX
4348	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4349	* given functions as initializers. For use in AVX functions where a pair of
4350	* functions are only used once and the function table need not be public. */
4351	#ifndef TST_IEM_CHECK_MC
4352	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4353	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4354	static IEMOPMEDIAOPTF2 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4355	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4356	# else
4357	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4358	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4359	# endif
4360	#else
4361	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4362	#endif
4363	/** @def IEMOPMEDIAOPTF2_INIT_VARS
4364	* Generate AVX function tables for the @a a_InstrNm instruction.
4365	* @sa IEMOPMEDIAOPTF2_INIT_VARS_EX */
4366	#define IEMOPMEDIAOPTF2_INIT_VARS(a_InstrNm) \
4367	IEMOPMEDIAOPTF2_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4368	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4369
4370	/**
4371	* Function table for media instruction taking one full sized media source
4372	* register and one full sized destination register and an 8-bit immediate, but no additional state
4373	* (AVX).
4374	*/
4375	typedef struct IEMOPMEDIAOPTF2IMM8
4376	{
4377	PFNIEMAIMPLMEDIAOPTF2U128IMM8 pfnU128;
4378	PFNIEMAIMPLMEDIAOPTF2U256IMM8 pfnU256;
4379	} IEMOPMEDIAOPTF2IMM8;
4380	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
4381	typedef IEMOPMEDIAOPTF2IMM8 const *PCIEMOPMEDIAOPTF2IMM8;
4382
4383	/** @def IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX
4384	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4385	* given functions as initializers. For use in AVX functions where a pair of
4386	* functions are only used once and the function table need not be public. */
4387	#ifndef TST_IEM_CHECK_MC
4388	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4389	# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4390	static IEMOPMEDIAOPTF2IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4391	static IEMOPMEDIAOPTF2IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4392	# else
4393	# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4394	static IEMOPMEDIAOPTF2IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4395	# endif
4396	#else
4397	# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4398	#endif
4399	/** @def IEMOPMEDIAOPTF2IMM8_INIT_VARS
4400	* Generate AVX function tables for the @a a_InstrNm instruction.
4401	* @sa IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX */
4402	#define IEMOPMEDIAOPTF2IMM8_INIT_VARS(a_InstrNm) \
4403	IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u256),\
4404	RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u256_fallback))
4405
4406	/**
4407	* Function table for media instruction taking two full sized media source
4408	* registers and one full sized destination register and an 8-bit immediate, but no additional state
4409	* (AVX).
4410	*/
4411	typedef struct IEMOPMEDIAOPTF3IMM8
4412	{
4413	PFNIEMAIMPLMEDIAOPTF3U128IMM8 pfnU128;
4414	PFNIEMAIMPLMEDIAOPTF3U256IMM8 pfnU256;
4415	} IEMOPMEDIAOPTF3IMM8;
4416	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
4417	typedef IEMOPMEDIAOPTF3IMM8 const *PCIEMOPMEDIAOPTF3IMM8;
4418
4419	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX
4420	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4421	* given functions as initializers. For use in AVX functions where a pair of
4422	* functions are only used once and the function table need not be public. */
4423	#ifndef TST_IEM_CHECK_MC
4424	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4425	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4426	static IEMOPMEDIAOPTF3IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4427	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4428	# else
4429	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4430	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4431	# endif
4432	#else
4433	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4434	#endif
4435	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS
4436	* Generate AVX function tables for the @a a_InstrNm instruction.
4437	* @sa IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX */
4438	#define IEMOPMEDIAOPTF3IMM8_INIT_VARS(a_InstrNm) \
4439	IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4440	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4441	/** @} */
4442
4443
4444	/**
4445	* Function table for blend type instruction taking three full sized media source
4446	* registers and one full sized destination register, but no additional state
4447	* (AVX).
4448	*/
4449	typedef struct IEMOPBLENDOP
4450	{
4451	PFNIEMAIMPLAVXBLENDU128 pfnU128;
4452	PFNIEMAIMPLAVXBLENDU256 pfnU256;
4453	} IEMOPBLENDOP;
4454	/** Pointer to a media operation function table for 4 full sized ops (AVX). */
4455	typedef IEMOPBLENDOP const *PCIEMOPBLENDOP;
4456
4457	/** @def IEMOPBLENDOP_INIT_VARS_EX
4458	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4459	* given functions as initializers. For use in AVX functions where a pair of
4460	* functions are only used once and the function table need not be public. */
4461	#ifndef TST_IEM_CHECK_MC
4462	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4463	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4464	static IEMOPBLENDOP const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4465	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4466	# else
4467	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4468	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4469	# endif
4470	#else
4471	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4472	#endif
4473	/** @def IEMOPBLENDOP_INIT_VARS
4474	* Generate AVX function tables for the @a a_InstrNm instruction.
4475	* @sa IEMOPBLENDOP_INIT_VARS_EX */
4476	#define IEMOPBLENDOP_INIT_VARS(a_InstrNm) \
4477	IEMOPBLENDOP_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4478	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4479
4480
4481	/** @name SSE/AVX single/double precision floating point operations.
4482	* @{ */
4483	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
4484	typedef FNIEMAIMPLFPSSEF2U128 *PFNIEMAIMPLFPSSEF2U128;
4485	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128R32,(uint32_t uMxCsrIn, PX86XMMREG Result, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
4486	typedef FNIEMAIMPLFPSSEF2U128R32 *PFNIEMAIMPLFPSSEF2U128R32;
4487	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128R64,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
4488	typedef FNIEMAIMPLFPSSEF2U128R64 *PFNIEMAIMPLFPSSEF2U128R64;
4489
4490	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
4491	typedef FNIEMAIMPLFPAVXF3U128 *PFNIEMAIMPLFPAVXF3U128;
4492	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U128R32,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
4493	typedef FNIEMAIMPLFPAVXF3U128R32 *PFNIEMAIMPLFPAVXF3U128R32;
4494	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U128R64,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
4495	typedef FNIEMAIMPLFPAVXF3U128R64 *PFNIEMAIMPLFPAVXF3U128R64;
4496
4497	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U256,(uint32_t uMxCsrIn, PX86YMMREG pResult, PCX86YMMREG puSrc1, PCX86YMMREG puSrc2));
4498	typedef FNIEMAIMPLFPAVXF3U256 *PFNIEMAIMPLFPAVXF3U256;
4499
4500	FNIEMAIMPLFPSSEF2U128 iemAImpl_addps_u128;
4501	FNIEMAIMPLFPSSEF2U128 iemAImpl_addpd_u128;
4502	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulps_u128;
4503	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulpd_u128;
4504	FNIEMAIMPLFPSSEF2U128 iemAImpl_subps_u128;
4505	FNIEMAIMPLFPSSEF2U128 iemAImpl_subpd_u128;
4506	FNIEMAIMPLFPSSEF2U128 iemAImpl_minps_u128;
4507	FNIEMAIMPLFPSSEF2U128 iemAImpl_minpd_u128;
4508	FNIEMAIMPLFPSSEF2U128 iemAImpl_divps_u128;
4509	FNIEMAIMPLFPSSEF2U128 iemAImpl_divpd_u128;
4510	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxps_u128;
4511	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxpd_u128;
4512	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddps_u128;
4513	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddpd_u128;
4514	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubps_u128;
4515	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubpd_u128;
4516	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtps_u128;
4517	FNIEMAIMPLFPSSEF2U128 iemAImpl_rsqrtps_u128;
4518	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtpd_u128;
4519	FNIEMAIMPLFPSSEF2U128 iemAImpl_rcpps_u128;
4520	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubps_u128;
4521	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubpd_u128;
4522
4523	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2ps_u128;
4524	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_cvtps2pd_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, uint64_t const *pu64Src));
4525
4526	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2ps_u128;
4527	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2dq_u128;
4528	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttps2dq_u128;
4529	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttpd2dq_u128;
4530	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2pd_u128;
4531	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2dq_u128;
4532
4533	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_addss_u128_r32;
4534	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_addsd_u128_r64;
4535	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_mulss_u128_r32;
4536	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_mulsd_u128_r64;
4537	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_subss_u128_r32;
4538	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_subsd_u128_r64;
4539	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_minss_u128_r32;
4540	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_minsd_u128_r64;
4541	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_divss_u128_r32;
4542	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_divsd_u128_r64;
4543	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_maxss_u128_r32;
4544	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_maxsd_u128_r64;
4545	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_cvtss2sd_u128_r32;
4546	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_cvtsd2ss_u128_r64;
4547	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_sqrtss_u128_r32;
4548	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_sqrtsd_u128_r64;
4549	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_rsqrtss_u128_r32;
4550	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_rcpss_u128_r32;
4551
4552	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddps_u128, iemAImpl_vaddps_u128_fallback;
4553	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddpd_u128, iemAImpl_vaddpd_u128_fallback;
4554	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulps_u128, iemAImpl_vmulps_u128_fallback;
4555	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulpd_u128, iemAImpl_vmulpd_u128_fallback;
4556	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubps_u128, iemAImpl_vsubps_u128_fallback;
4557	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubpd_u128, iemAImpl_vsubpd_u128_fallback;
4558	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminps_u128, iemAImpl_vminps_u128_fallback;
4559	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminpd_u128, iemAImpl_vminpd_u128_fallback;
4560	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivps_u128, iemAImpl_vdivps_u128_fallback;
4561	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivpd_u128, iemAImpl_vdivpd_u128_fallback;
4562	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxps_u128, iemAImpl_vmaxps_u128_fallback;
4563	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxpd_u128, iemAImpl_vmaxpd_u128_fallback;
4564	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddps_u128, iemAImpl_vhaddps_u128_fallback;
4565	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddpd_u128, iemAImpl_vhaddpd_u128_fallback;
4566	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubps_u128, iemAImpl_vhsubps_u128_fallback;
4567	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubpd_u128, iemAImpl_vhsubpd_u128_fallback;
4568	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtps_u128, iemAImpl_vsqrtps_u128_fallback;
4569	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtpd_u128, iemAImpl_vsqrtpd_u128_fallback;
4570	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubps_u128, iemAImpl_vaddsubps_u128_fallback;
4571	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubpd_u128, iemAImpl_vaddsubpd_u128_fallback;
4572	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtpd2ps_u128, iemAImpl_vcvtpd2ps_u128_fallback;
4573	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtps2pd_u128, iemAImpl_vcvtps2pd_u128_fallback;
4574
4575	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vaddss_u128_r32, iemAImpl_vaddss_u128_r32_fallback;
4576	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vaddsd_u128_r64, iemAImpl_vaddsd_u128_r64_fallback;
4577	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmulss_u128_r32, iemAImpl_vmulss_u128_r32_fallback;
4578	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmulsd_u128_r64, iemAImpl_vmulsd_u128_r64_fallback;
4579	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsubss_u128_r32, iemAImpl_vsubss_u128_r32_fallback;
4580	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsubsd_u128_r64, iemAImpl_vsubsd_u128_r64_fallback;
4581	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vminss_u128_r32, iemAImpl_vminss_u128_r32_fallback;
4582	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vminsd_u128_r64, iemAImpl_vminsd_u128_r64_fallback;
4583	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vdivss_u128_r32, iemAImpl_vdivss_u128_r32_fallback;
4584	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vdivsd_u128_r64, iemAImpl_vdivsd_u128_r64_fallback;
4585	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmaxss_u128_r32, iemAImpl_vmaxss_u128_r32_fallback;
4586	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmaxsd_u128_r64, iemAImpl_vmaxsd_u128_r64_fallback;
4587	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsqrtss_u128_r32, iemAImpl_vsqrtss_u128_r32_fallback;
4588	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsqrtsd_u128_r64, iemAImpl_vsqrtsd_u128_r64_fallback;
4589
4590	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddps_u256, iemAImpl_vaddps_u256_fallback;
4591	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddpd_u256, iemAImpl_vaddpd_u256_fallback;
4592	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulps_u256, iemAImpl_vmulps_u256_fallback;
4593	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulpd_u256, iemAImpl_vmulpd_u256_fallback;
4594	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubps_u256, iemAImpl_vsubps_u256_fallback;
4595	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubpd_u256, iemAImpl_vsubpd_u256_fallback;
4596	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminps_u256, iemAImpl_vminps_u256_fallback;
4597	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminpd_u256, iemAImpl_vminpd_u256_fallback;
4598	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivps_u256, iemAImpl_vdivps_u256_fallback;
4599	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivpd_u256, iemAImpl_vdivpd_u256_fallback;
4600	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxps_u256, iemAImpl_vmaxps_u256_fallback;
4601	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxpd_u256, iemAImpl_vmaxpd_u256_fallback;
4602	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddps_u256, iemAImpl_vhaddps_u256_fallback;
4603	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddpd_u256, iemAImpl_vhaddpd_u256_fallback;
4604	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubps_u256, iemAImpl_vhsubps_u256_fallback;
4605	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubpd_u256, iemAImpl_vhsubpd_u256_fallback;
4606	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubps_u256, iemAImpl_vhaddsubps_u256_fallback;
4607	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubpd_u256, iemAImpl_vhaddsubpd_u256_fallback;
4608	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtpd2ps_u256, iemAImpl_vcvtpd2ps_u256_fallback;
4609	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtps2pd_u256, iemAImpl_vcvtps2pd_u256_fallback;
4610	/** @} */
4611
4612	/** @name C instruction implementations for anything slightly complicated.
4613	* @{ */
4614
4615	/**
4616	* For typedef'ing or declaring a C instruction implementation function taking
4617	* no extra arguments.
4618	*
4619	* @param a_Name The name of the type.
4620	*/
4621	# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
4622	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
4623	/**
4624	* For defining a C instruction implementation function taking no extra
4625	* arguments.
4626	*
4627	* @param a_Name The name of the function
4628	*/
4629	# define IEM_CIMPL_DEF_0(a_Name) \
4630	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
4631	/**
4632	* Prototype version of IEM_CIMPL_DEF_0.
4633	*/
4634	# define IEM_CIMPL_PROTO_0(a_Name) \
4635	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
4636	/**
4637	* For calling a C instruction implementation function taking no extra
4638	* arguments.
4639	*
4640	* This special call macro adds default arguments to the call and allow us to
4641	* change these later.
4642	*
4643	* @param a_fn The name of the function.
4644	*/
4645	# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
4646
4647	/** Type for a C instruction implementation function taking no extra
4648	* arguments. */
4649	typedef IEM_CIMPL_DECL_TYPE_0(FNIEMCIMPL0);
4650	/** Function pointer type for a C instruction implementation function taking
4651	* no extra arguments. */
4652	typedef FNIEMCIMPL0 *PFNIEMCIMPL0;
4653
4654	/**
4655	* For typedef'ing or declaring a C instruction implementation function taking
4656	* one extra argument.
4657	*
4658	* @param a_Name The name of the type.
4659	* @param a_Type0 The argument type.
4660	* @param a_Arg0 The argument name.
4661	*/
4662	# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
4663	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
4664	/**
4665	* For defining a C instruction implementation function taking one extra
4666	* argument.
4667	*
4668	* @param a_Name The name of the function
4669	* @param a_Type0 The argument type.
4670	* @param a_Arg0 The argument name.
4671	*/
4672	# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
4673	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
4674	/**
4675	* Prototype version of IEM_CIMPL_DEF_1.
4676	*/
4677	# define IEM_CIMPL_PROTO_1(a_Name, a_Type0, a_Arg0) \
4678	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
4679	/**
4680	* For calling a C instruction implementation function taking one extra
4681	* argument.
4682	*
4683	* This special call macro adds default arguments to the call and allow us to
4684	* change these later.
4685	*
4686	* @param a_fn The name of the function.
4687	* @param a0 The name of the 1st argument.
4688	*/
4689	# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
4690
4691	/**
4692	* For typedef'ing or declaring a C instruction implementation function taking
4693	* two extra arguments.
4694	*
4695	* @param a_Name The name of the type.
4696	* @param a_Type0 The type of the 1st argument
4697	* @param a_Arg0 The name of the 1st argument.
4698	* @param a_Type1 The type of the 2nd argument.
4699	* @param a_Arg1 The name of the 2nd argument.
4700	*/
4701	# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
4702	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
4703	/**
4704	* For defining a C instruction implementation function taking two extra
4705	* arguments.
4706	*
4707	* @param a_Name The name of the function.
4708	* @param a_Type0 The type of the 1st argument
4709	* @param a_Arg0 The name of the 1st argument.
4710	* @param a_Type1 The type of the 2nd argument.
4711	* @param a_Arg1 The name of the 2nd argument.
4712	*/
4713	# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
4714	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
4715	/**
4716	* Prototype version of IEM_CIMPL_DEF_2.
4717	*/
4718	# define IEM_CIMPL_PROTO_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
4719	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
4720	/**
4721	* For calling a C instruction implementation function taking two extra
4722	* arguments.
4723	*
4724	* This special call macro adds default arguments to the call and allow us to
4725	* change these later.
4726	*
4727	* @param a_fn The name of the function.
4728	* @param a0 The name of the 1st argument.
4729	* @param a1 The name of the 2nd argument.
4730	*/
4731	# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
4732
4733	/**
4734	* For typedef'ing or declaring a C instruction implementation function taking
4735	* three extra arguments.
4736	*
4737	* @param a_Name The name of the type.
4738	* @param a_Type0 The type of the 1st argument
4739	* @param a_Arg0 The name of the 1st argument.
4740	* @param a_Type1 The type of the 2nd argument.
4741	* @param a_Arg1 The name of the 2nd argument.
4742	* @param a_Type2 The type of the 3rd argument.
4743	* @param a_Arg2 The name of the 3rd argument.
4744	*/
4745	# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
4746	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
4747	/**
4748	* For defining a C instruction implementation function taking three extra
4749	* arguments.
4750	*
4751	* @param a_Name The name of the function.
4752	* @param a_Type0 The type of the 1st argument
4753	* @param a_Arg0 The name of the 1st argument.
4754	* @param a_Type1 The type of the 2nd argument.
4755	* @param a_Arg1 The name of the 2nd argument.
4756	* @param a_Type2 The type of the 3rd argument.
4757	* @param a_Arg2 The name of the 3rd argument.
4758	*/
4759	# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
4760	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
4761	/**
4762	* Prototype version of IEM_CIMPL_DEF_3.
4763	*/
4764	# define IEM_CIMPL_PROTO_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
4765	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
4766	/**
4767	* For calling a C instruction implementation function taking three extra
4768	* arguments.
4769	*
4770	* This special call macro adds default arguments to the call and allow us to
4771	* change these later.
4772	*
4773	* @param a_fn The name of the function.
4774	* @param a0 The name of the 1st argument.
4775	* @param a1 The name of the 2nd argument.
4776	* @param a2 The name of the 3rd argument.
4777	*/
4778	# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
4779
4780
4781	/**
4782	* For typedef'ing or declaring a C instruction implementation function taking
4783	* four extra arguments.
4784	*
4785	* @param a_Name The name of the type.
4786	* @param a_Type0 The type of the 1st argument
4787	* @param a_Arg0 The name of the 1st argument.
4788	* @param a_Type1 The type of the 2nd argument.
4789	* @param a_Arg1 The name of the 2nd argument.
4790	* @param a_Type2 The type of the 3rd argument.
4791	* @param a_Arg2 The name of the 3rd argument.
4792	* @param a_Type3 The type of the 4th argument.
4793	* @param a_Arg3 The name of the 4th argument.
4794	*/
4795	# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
4796	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
4797	/**
4798	* For defining a C instruction implementation function taking four extra
4799	* arguments.
4800	*
4801	* @param a_Name The name of the function.
4802	* @param a_Type0 The type of the 1st argument
4803	* @param a_Arg0 The name of the 1st argument.
4804	* @param a_Type1 The type of the 2nd argument.
4805	* @param a_Arg1 The name of the 2nd argument.
4806	* @param a_Type2 The type of the 3rd argument.
4807	* @param a_Arg2 The name of the 3rd argument.
4808	* @param a_Type3 The type of the 4th argument.
4809	* @param a_Arg3 The name of the 4th argument.
4810	*/
4811	# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
4812	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4813	a_Type2 a_Arg2, a_Type3 a_Arg3))
4814	/**
4815	* Prototype version of IEM_CIMPL_DEF_4.
4816	*/
4817	# define IEM_CIMPL_PROTO_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
4818	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4819	a_Type2 a_Arg2, a_Type3 a_Arg3))
4820	/**
4821	* For calling a C instruction implementation function taking four extra
4822	* arguments.
4823	*
4824	* This special call macro adds default arguments to the call and allow us to
4825	* change these later.
4826	*
4827	* @param a_fn The name of the function.
4828	* @param a0 The name of the 1st argument.
4829	* @param a1 The name of the 2nd argument.
4830	* @param a2 The name of the 3rd argument.
4831	* @param a3 The name of the 4th argument.
4832	*/
4833	# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
4834
4835
4836	/**
4837	* For typedef'ing or declaring a C instruction implementation function taking
4838	* five extra arguments.
4839	*
4840	* @param a_Name The name of the type.
4841	* @param a_Type0 The type of the 1st argument
4842	* @param a_Arg0 The name of the 1st argument.
4843	* @param a_Type1 The type of the 2nd argument.
4844	* @param a_Arg1 The name of the 2nd argument.
4845	* @param a_Type2 The type of the 3rd argument.
4846	* @param a_Arg2 The name of the 3rd argument.
4847	* @param a_Type3 The type of the 4th argument.
4848	* @param a_Arg3 The name of the 4th argument.
4849	* @param a_Type4 The type of the 5th argument.
4850	* @param a_Arg4 The name of the 5th argument.
4851	*/
4852	# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
4853	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, \
4854	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
4855	a_Type3 a_Arg3, a_Type4 a_Arg4))
4856	/**
4857	* For defining a C instruction implementation function taking five extra
4858	* arguments.
4859	*
4860	* @param a_Name The name of the function.
4861	* @param a_Type0 The type of the 1st argument
4862	* @param a_Arg0 The name of the 1st argument.
4863	* @param a_Type1 The type of the 2nd argument.
4864	* @param a_Arg1 The name of the 2nd argument.
4865	* @param a_Type2 The type of the 3rd argument.
4866	* @param a_Arg2 The name of the 3rd argument.
4867	* @param a_Type3 The type of the 4th argument.
4868	* @param a_Arg3 The name of the 4th argument.
4869	* @param a_Type4 The type of the 5th argument.
4870	* @param a_Arg4 The name of the 5th argument.
4871	*/
4872	# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
4873	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4874	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
4875	/**
4876	* Prototype version of IEM_CIMPL_DEF_5.
4877	*/
4878	# define IEM_CIMPL_PROTO_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
4879	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4880	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
4881	/**
4882	* For calling a C instruction implementation function taking five extra
4883	* arguments.
4884	*
4885	* This special call macro adds default arguments to the call and allow us to
4886	* change these later.
4887	*
4888	* @param a_fn The name of the function.
4889	* @param a0 The name of the 1st argument.
4890	* @param a1 The name of the 2nd argument.
4891	* @param a2 The name of the 3rd argument.
4892	* @param a3 The name of the 4th argument.
4893	* @param a4 The name of the 5th argument.
4894	*/
4895	# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
4896
4897	/** @} */
4898
4899
4900	/** @name Opcode Decoder Function Types.
4901	* @{ */
4902
4903	/** @typedef PFNIEMOP
4904	* Pointer to an opcode decoder function.
4905	*/
4906
4907	/** @def FNIEMOP_DEF
4908	* Define an opcode decoder function.
4909	*
4910	* We're using macors for this so that adding and removing parameters as well as
4911	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL
4912	*
4913	* @param a_Name The function name.
4914	*/
4915
4916	/** @typedef PFNIEMOPRM
4917	* Pointer to an opcode decoder function with RM byte.
4918	*/
4919
4920	/** @def FNIEMOPRM_DEF
4921	* Define an opcode decoder function with RM byte.
4922	*
4923	* We're using macors for this so that adding and removing parameters as well as
4924	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL_1
4925	*
4926	* @param a_Name The function name.
4927	*/
4928
4929	#if defined(__GNUC__) && defined(RT_ARCH_X86)
4930	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOP)(PVMCPUCC pVCpu);
4931	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4932	# define FNIEMOP_DEF(a_Name) \
4933	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu)
4934	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4935	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
4936	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4937	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
4938
4939	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
4940	typedef VBOXSTRICTRC (__fastcall * PFNIEMOP)(PVMCPUCC pVCpu);
4941	typedef VBOXSTRICTRC (__fastcall * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4942	# define FNIEMOP_DEF(a_Name) \
4943	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
4944	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4945	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
4946	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4947	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
4948
4949	#elif defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
4950	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
4951	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4952	# define FNIEMOP_DEF(a_Name) \
4953	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu)
4954	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4955	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
4956	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4957	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
4958
4959	#else
4960	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
4961	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4962	# define FNIEMOP_DEF(a_Name) \
4963	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
4964	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4965	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
4966	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4967	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
4968
4969	#endif
4970	#define FNIEMOPRM_DEF(a_Name) FNIEMOP_DEF_1(a_Name, uint8_t, bRm)
4971
4972	/**
4973	* Call an opcode decoder function.
4974	*
4975	* We're using macors for this so that adding and removing parameters can be
4976	* done as we please. See FNIEMOP_DEF.
4977	*/
4978	#define FNIEMOP_CALL(a_pfn) (a_pfn)(pVCpu)
4979
4980	/**
4981	* Call a common opcode decoder function taking one extra argument.
4982	*
4983	* We're using macors for this so that adding and removing parameters can be
4984	* done as we please. See FNIEMOP_DEF_1.
4985	*/
4986	#define FNIEMOP_CALL_1(a_pfn, a0) (a_pfn)(pVCpu, a0)
4987
4988	/**
4989	* Call a common opcode decoder function taking one extra argument.
4990	*
4991	* We're using macors for this so that adding and removing parameters can be
4992	* done as we please. See FNIEMOP_DEF_1.
4993	*/
4994	#define FNIEMOP_CALL_2(a_pfn, a0, a1) (a_pfn)(pVCpu, a0, a1)
4995	/** @} */
4996
4997
4998	/** @name Misc Helpers
4999	* @{ */
5000
5001	/** Used to shut up GCC warnings about variables that 'may be used uninitialized'
5002	* due to GCC lacking knowledge about the value range of a switch. */
5003	#if RT_CPLUSPLUS_PREREQ(202000)
5004	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: [[unlikely]] AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
5005	#else
5006	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
5007	#endif
5008
5009	/** Variant of IEM_NOT_REACHED_DEFAULT_CASE_RET that returns a custom value. */
5010	#if RT_CPLUSPLUS_PREREQ(202000)
5011	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: [[unlikely]] AssertFailedReturn(a_RetValue)
5012	#else
5013	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: AssertFailedReturn(a_RetValue)
5014	#endif
5015
5016	/**
5017	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
5018	* occation.
5019	*/
5020	#ifdef LOG_ENABLED
5021	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
5022	do { \
5023	/Log/ LogAlways(("%s: returning IEM_RETURN_ASPECT_NOT_IMPLEMENTED (line %d)\n", __FUNCTION__, __LINE__)); \
5024	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
5025	} while (0)
5026	#else
5027	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
5028	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
5029	#endif
5030
5031	/**
5032	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
5033	* occation using the supplied logger statement.
5034	*
5035	* @param a_LoggerArgs What to log on failure.
5036	*/
5037	#ifdef LOG_ENABLED
5038	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
5039	do { \
5040	LogAlways((LOG_FN_FMT ": ", __PRETTY_FUNCTION__)); LogAlways(a_LoggerArgs); \
5041	/LogFunc(a_LoggerArgs);/ \
5042	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
5043	} while (0)
5044	#else
5045	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
5046	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
5047	#endif
5048
5049	/**
5050	* Gets the CPU mode (from fExec) as a IEMMODE value.
5051	*
5052	* @returns IEMMODE
5053	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5054	*/
5055	#define IEM_GET_CPU_MODE(a_pVCpu) ((a_pVCpu)->iem.s.fExec & IEM_F_MODE_CPUMODE_MASK)
5056
5057	/**
5058	* Check if we're currently executing in real or virtual 8086 mode.
5059	*
5060	* @returns @c true if it is, @c false if not.
5061	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5062	*/
5063	#define IEM_IS_REAL_OR_V86_MODE(a_pVCpu) (( ((a_pVCpu)->iem.s.fExec ^ IEM_F_MODE_X86_PROT_MASK) \
5064	& (IEM_F_MODE_X86_V86_MASK \| IEM_F_MODE_X86_PROT_MASK)) != 0)
5065
5066	/**
5067	* Check if we're currently executing in virtual 8086 mode.
5068	*
5069	* @returns @c true if it is, @c false if not.
5070	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5071	*/
5072	#define IEM_IS_V86_MODE(a_pVCpu) (((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_V86_MASK) != 0)
5073
5074	/**
5075	* Check if we're currently executing in long mode.
5076	*
5077	* @returns @c true if it is, @c false if not.
5078	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5079	*/
5080	#define IEM_IS_LONG_MODE(a_pVCpu) (CPUMIsGuestInLongModeEx(IEM_GET_CTX(a_pVCpu)))
5081
5082	/**
5083	* Check if we're currently executing in a 16-bit code segment.
5084	*
5085	* @returns @c true if it is, @c false if not.
5086	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5087	*/
5088	#define IEM_IS_16BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_16BIT)
5089
5090	/**
5091	* Check if we're currently executing in a 32-bit code segment.
5092	*
5093	* @returns @c true if it is, @c false if not.
5094	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5095	*/
5096	#define IEM_IS_32BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_32BIT)
5097
5098	/**
5099	* Check if we're currently executing in a 64-bit code segment.
5100	*
5101	* @returns @c true if it is, @c false if not.
5102	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5103	*/
5104	#define IEM_IS_64BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_64BIT)
5105
5106	/**
5107	* Check if we're currently executing in real mode.
5108	*
5109	* @returns @c true if it is, @c false if not.
5110	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5111	*/
5112	#define IEM_IS_REAL_MODE(a_pVCpu) (!((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_PROT_MASK))
5113
5114	/**
5115	* Gets the current protection level (CPL).
5116	*
5117	* @returns 0..3
5118	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5119	*/
5120	#define IEM_GET_CPL(a_pVCpu) (((a_pVCpu)->iem.s.fExec >> IEM_F_X86_CPL_SHIFT) & IEM_F_X86_CPL_SMASK)
5121
5122	/**
5123	* Sets the current protection level (CPL).
5124	*
5125	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5126	*/
5127	#define IEM_SET_CPL(a_pVCpu, a_uCpl) \
5128	do { (a_pVCpu)->iem.s.fExec = ((a_pVCpu)->iem.s.fExec & ~IEM_F_X86_CPL_MASK) \| ((a_uCpl) << IEM_F_X86_CPL_SHIFT); } while (0)
5129
5130	/**
5131	* Returns a (const) pointer to the CPUMFEATURES for the guest CPU.
5132	* @returns PCCPUMFEATURES
5133	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5134	*/
5135	#define IEM_GET_GUEST_CPU_FEATURES(a_pVCpu) (&((a_pVCpu)->CTX_SUFF(pVM)->cpum.ro.GuestFeatures))
5136
5137	/**
5138	* Returns a (const) pointer to the CPUMFEATURES for the host CPU.
5139	* @returns PCCPUMFEATURES
5140	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5141	*/
5142	#define IEM_GET_HOST_CPU_FEATURES(a_pVCpu) (&g_CpumHostFeatures.s)
5143
5144	/**
5145	* Evaluates to true if we're presenting an Intel CPU to the guest.
5146	*/
5147	#define IEM_IS_GUEST_CPU_INTEL(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL )
5148
5149	/**
5150	* Evaluates to true if we're presenting an AMD CPU to the guest.
5151	*/
5152	#define IEM_IS_GUEST_CPU_AMD(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_AMD \|\| (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_HYGON )
5153
5154	/**
5155	* Check if the address is canonical.
5156	*/
5157	#define IEM_IS_CANONICAL(a_u64Addr) X86_IS_CANONICAL(a_u64Addr)
5158
5159	/** Checks if the ModR/M byte is in register mode or not. */
5160	#define IEM_IS_MODRM_REG_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT) )
5161	/** Checks if the ModR/M byte is in memory mode or not. */
5162	#define IEM_IS_MODRM_MEM_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT) )
5163
5164	/**
5165	* Gets the register (reg) part of a ModR/M encoding, with REX.R added in.
5166	*
5167	* For use during decoding.
5168	*/
5169	#define IEM_GET_MODRM_REG(a_pVCpu, a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| (a_pVCpu)->iem.s.uRexReg )
5170	/**
5171	* Gets the r/m part of a ModR/M encoding as a register index, with REX.B added in.
5172	*
5173	* For use during decoding.
5174	*/
5175	#define IEM_GET_MODRM_RM(a_pVCpu, a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) \| (a_pVCpu)->iem.s.uRexB )
5176
5177	/**
5178	* Gets the register (reg) part of a ModR/M encoding, without REX.R.
5179	*
5180	* For use during decoding.
5181	*/
5182	#define IEM_GET_MODRM_REG_8(a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) )
5183	/**
5184	* Gets the r/m part of a ModR/M encoding as a register index, without REX.B.
5185	*
5186	* For use during decoding.
5187	*/
5188	#define IEM_GET_MODRM_RM_8(a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) )
5189
5190	/**
5191	* Gets the register (reg) part of a ModR/M encoding as an extended 8-bit
5192	* register index, with REX.R added in.
5193	*
5194	* For use during decoding.
5195	*
5196	* @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
5197	*/
5198	#define IEM_GET_MODRM_REG_EX8(a_pVCpu, a_bRm) \
5199	( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
5200	\|\| !((a_bRm) & (4 << X86_MODRM_REG_SHIFT)) /* IEM_GET_MODRM_REG(pVCpu, a_bRm) < 4 */ \
5201	? IEM_GET_MODRM_REG(pVCpu, a_bRm) : (((a_bRm) >> X86_MODRM_REG_SHIFT) & 3) \| 16)
5202	/**
5203	* Gets the r/m part of a ModR/M encoding as an extended 8-bit register index,
5204	* with REX.B added in.
5205	*
5206	* For use during decoding.
5207	*
5208	* @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
5209	*/
5210	#define IEM_GET_MODRM_RM_EX8(a_pVCpu, a_bRm) \
5211	( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
5212	\|\| !((a_bRm) & 4) /* IEM_GET_MODRM_RM(pVCpu, a_bRm) < 4 */ \
5213	? IEM_GET_MODRM_RM(pVCpu, a_bRm) : ((a_bRm) & 3) \| 16)
5214
5215	/**
5216	* Combines the prefix REX and ModR/M byte for passing to
5217	* iemOpHlpCalcRmEffAddrThreadedAddr64().
5218	*
5219	* @returns The ModRM byte but with bit 3 set to REX.B and bit 4 to REX.X.
5220	* The two bits are part of the REG sub-field, which isn't needed in
5221	* iemOpHlpCalcRmEffAddrThreadedAddr64().
5222	*
5223	* For use during decoding/recompiling.
5224	*/
5225	#define IEM_GET_MODRM_EX(a_pVCpu, a_bRm) \
5226	( ((a_bRm) & ~X86_MODRM_REG_MASK) \
5227	\| (uint8_t)( (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X)) >> (25 - 3) ) )
5228	AssertCompile(IEM_OP_PRF_REX_B == RT_BIT_32(25));
5229	AssertCompile(IEM_OP_PRF_REX_X == RT_BIT_32(26));
5230
5231	/**
5232	* Gets the effective VEX.VVVV value.
5233	*
5234	* The 4th bit is ignored if not 64-bit code.
5235	* @returns effective V-register value.
5236	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5237	*/
5238	#define IEM_GET_EFFECTIVE_VVVV(a_pVCpu) \
5239	(IEM_IS_64BIT_CODE(a_pVCpu) ? (a_pVCpu)->iem.s.uVex3rdReg : (a_pVCpu)->iem.s.uVex3rdReg & 7)
5240
5241
5242	/**
5243	* Gets the register (reg) part of a the special 4th register byte used by
5244	* vblendvps and vblendvpd.
5245	*
5246	* For use during decoding.
5247	*/
5248	#define IEM_GET_IMM8_REG(a_pVCpu, a_bRegImm8) \
5249	(IEM_IS_64BIT_CODE(a_pVCpu) ? (a_bRegImm8) >> 4 : ((a_bRegImm8) >> 4) & 7)
5250
5251
5252	/**
5253	* Checks if we're executing inside an AMD-V or VT-x guest.
5254	*/
5255	#if defined(VBOX_WITH_NESTED_HWVIRT_VMX) \|\| defined(VBOX_WITH_NESTED_HWVIRT_SVM)
5256	# define IEM_IS_IN_GUEST(a_pVCpu) RT_BOOL((a_pVCpu)->iem.s.fExec & IEM_F_X86_CTX_IN_GUEST)
5257	#else
5258	# define IEM_IS_IN_GUEST(a_pVCpu) false
5259	#endif
5260
5261
5262	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5263
5264	/**
5265	* Check if the guest has entered VMX root operation.
5266	*/
5267	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxRootMode(IEM_GET_CTX(a_pVCpu)))
5268
5269	/**
5270	* Check if the guest has entered VMX non-root operation.
5271	*/
5272	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) ( ((a_pVCpu)->iem.s.fExec & (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST)) \
5273	== (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST) )
5274
5275	/**
5276	* Check if the nested-guest has the given Pin-based VM-execution control set.
5277	*/
5278	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_PinCtl) (CPUMIsGuestVmxPinCtlsSet(IEM_GET_CTX(a_pVCpu), (a_PinCtl)))
5279
5280	/**
5281	* Check if the nested-guest has the given Processor-based VM-execution control set.
5282	*/
5283	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_ProcCtl) (CPUMIsGuestVmxProcCtlsSet(IEM_GET_CTX(a_pVCpu), (a_ProcCtl)))
5284
5285	/**
5286	* Check if the nested-guest has the given Secondary Processor-based VM-execution
5287	* control set.
5288	*/
5289	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_ProcCtl2) (CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(a_pVCpu), (a_ProcCtl2)))
5290
5291	/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
5292	# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
5293
5294	/** Whether a shadow VMCS is present for the given VCPU. */
5295	# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
5296
5297	/** Gets the VMXON region pointer. */
5298	# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
5299
5300	/** Gets the guest-physical address of the current VMCS for the given VCPU. */
5301	# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
5302
5303	/** Whether a current VMCS is present for the given VCPU. */
5304	# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
5305
5306	/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
5307	# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
5308	do \
5309	{ \
5310	Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
5311	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
5312	} while (0)
5313
5314	/** Clears any current VMCS for the given VCPU. */
5315	# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
5316	do \
5317	{ \
5318	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
5319	} while (0)
5320
5321	/**
5322	* Invokes the VMX VM-exit handler for an instruction intercept.
5323	*/
5324	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) \
5325	do { return iemVmxVmexitInstr((a_pVCpu), (a_uExitReason), (a_cbInstr)); } while (0)
5326
5327	/**
5328	* Invokes the VMX VM-exit handler for an instruction intercept where the
5329	* instruction provides additional VM-exit information.
5330	*/
5331	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) \
5332	do { return iemVmxVmexitInstrNeedsInfo((a_pVCpu), (a_uExitReason), (a_uInstrId), (a_cbInstr)); } while (0)
5333
5334	/**
5335	* Invokes the VMX VM-exit handler for a task switch.
5336	*/
5337	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) \
5338	do { return iemVmxVmexitTaskSwitch((a_pVCpu), (a_enmTaskSwitch), (a_SelNewTss), (a_cbInstr)); } while (0)
5339
5340	/**
5341	* Invokes the VMX VM-exit handler for MWAIT.
5342	*/
5343	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) \
5344	do { return iemVmxVmexitInstrMwait((a_pVCpu), (a_fMonitorArmed), (a_cbInstr)); } while (0)
5345
5346	/**
5347	* Invokes the VMX VM-exit handler for EPT faults.
5348	*/
5349	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) \
5350	do { return iemVmxVmexitEpt(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr); } while (0)
5351
5352	/**
5353	* Invokes the VMX VM-exit handler.
5354	*/
5355	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) \
5356	do { return iemVmxVmexit((a_pVCpu), (a_uExitReason), (a_uExitQual)); } while (0)
5357
5358	#else
5359	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (false)
5360	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (false)
5361	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_cbInstr) (false)
5362	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_cbInstr) (false)
5363	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_cbInstr) (false)
5364	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5365	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5366	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5367	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5368	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5369	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) do { return VERR_VMX_IPE_1; } while (0)
5370
5371	#endif
5372
5373	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5374	/**
5375	* Checks if we're executing a guest using AMD-V.
5376	*/
5377	# define IEM_SVM_IS_IN_GUEST(a_pVCpu) ( (a_pVCpu->iem.s.fExec & (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST)) \
5378	== (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST))
5379	/**
5380	* Check if an SVM control/instruction intercept is set.
5381	*/
5382	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) \
5383	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmCtrlInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_Intercept)))
5384
5385	/**
5386	* Check if an SVM read CRx intercept is set.
5387	*/
5388	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
5389	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
5390
5391	/**
5392	* Check if an SVM write CRx intercept is set.
5393	*/
5394	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
5395	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
5396
5397	/**
5398	* Check if an SVM read DRx intercept is set.
5399	*/
5400	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
5401	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
5402
5403	/**
5404	* Check if an SVM write DRx intercept is set.
5405	*/
5406	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
5407	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
5408
5409	/**
5410	* Check if an SVM exception intercept is set.
5411	*/
5412	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) \
5413	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmXcptInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uVector)))
5414
5415	/**
5416	* Invokes the SVM \#VMEXIT handler for the nested-guest.
5417	*/
5418	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
5419	do { return iemSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2)); } while (0)
5420
5421	/**
5422	* Invokes the 'MOV CRx' SVM \#VMEXIT handler after constructing the
5423	* corresponding decode assist information.
5424	*/
5425	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) \
5426	do \
5427	{ \
5428	uint64_t uExitInfo1; \
5429	if ( IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmDecodeAssists \
5430	&& (a_enmAccessCrX) == IEMACCESSCRX_MOV_CRX) \
5431	uExitInfo1 = SVM_EXIT1_MOV_CRX_MASK \| ((a_iGReg) & 7); \
5432	else \
5433	uExitInfo1 = 0; \
5434	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, uExitInfo1, 0); \
5435	} while (0)
5436
5437	/** Check and handles SVM nested-guest instruction intercept and updates
5438	* NRIP if needed.
5439	*/
5440	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
5441	do \
5442	{ \
5443	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept)) \
5444	{ \
5445	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
5446	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2); \
5447	} \
5448	} while (0)
5449
5450	/** Checks and handles SVM nested-guest CR0 read intercept. */
5451	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
5452	do \
5453	{ \
5454	if (!IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, 0)) \
5455	{ /* probably likely */ } \
5456	else \
5457	{ \
5458	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
5459	IEM_SVM_VMEXIT_RET(a_pVCpu, SVM_EXIT_READ_CR0, a_uExitInfo1, a_uExitInfo2); \
5460	} \
5461	} while (0)
5462
5463	/**
5464	* Updates the NextRIP (NRI) field in the nested-guest VMCB.
5465	*/
5466	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) \
5467	do { \
5468	if (IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmNextRipSave) \
5469	CPUMGuestSvmUpdateNRip(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_cbInstr)); \
5470	} while (0)
5471
5472	#else
5473	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) (false)
5474	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
5475	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
5476	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
5477	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
5478	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) (false)
5479	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { return VERR_SVM_IPE_1; } while (0)
5480	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) do { return VERR_SVM_IPE_1; } while (0)
5481	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, \
5482	a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
5483	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
5484	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) do { } while (0)
5485
5486	#endif
5487
5488	/** @} */
5489
5490	uint32_t iemCalcExecDbgFlagsSlow(PVMCPUCC pVCpu);
5491	VBOXSTRICTRC iemExecInjectPendingTrap(PVMCPUCC pVCpu);
5492
5493
5494	/**
5495	* Selector descriptor table entry as fetched by iemMemFetchSelDesc.
5496	*/
5497	typedef union IEMSELDESC
5498	{
5499	/** The legacy view. */
5500	X86DESC Legacy;
5501	/** The long mode view. */
5502	X86DESC64 Long;
5503	} IEMSELDESC;
5504	/** Pointer to a selector descriptor table entry. */
5505	typedef IEMSELDESC *PIEMSELDESC;
5506
5507	/** @name Raising Exceptions.
5508	* @{ */
5509	VBOXSTRICTRC iemTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, uint32_t uNextEip, uint32_t fFlags,
5510	uint16_t uErr, uint64_t uCr2, RTSEL SelTSS, PIEMSELDESC pNewDescTSS) RT_NOEXCEPT;
5511
5512	VBOXSTRICTRC iemRaiseXcptOrInt(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags,
5513	uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
5514	#ifdef IEM_WITH_SETJMP
5515	DECL_NO_RETURN(void) iemRaiseXcptOrIntJmp(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector,
5516	uint32_t fFlags, uint16_t uErr, uint64_t uCr2) IEM_NOEXCEPT_MAY_LONGJMP;
5517	#endif
5518	VBOXSTRICTRC iemRaiseDivideError(PVMCPUCC pVCpu) RT_NOEXCEPT;
5519	#ifdef IEM_WITH_SETJMP
5520	DECL_NO_RETURN(void) iemRaiseDivideErrorJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5521	#endif
5522	VBOXSTRICTRC iemRaiseDebugException(PVMCPUCC pVCpu) RT_NOEXCEPT;
5523	VBOXSTRICTRC iemRaiseBoundRangeExceeded(PVMCPUCC pVCpu) RT_NOEXCEPT;
5524	VBOXSTRICTRC iemRaiseUndefinedOpcode(PVMCPUCC pVCpu) RT_NOEXCEPT;
5525	#ifdef IEM_WITH_SETJMP
5526	DECL_NO_RETURN(void) iemRaiseUndefinedOpcodeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5527	#endif
5528	VBOXSTRICTRC iemRaiseDeviceNotAvailable(PVMCPUCC pVCpu) RT_NOEXCEPT;
5529	#ifdef IEM_WITH_SETJMP
5530	DECL_NO_RETURN(void) iemRaiseDeviceNotAvailableJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5531	#endif
5532	VBOXSTRICTRC iemRaiseTaskSwitchFaultWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5533	VBOXSTRICTRC iemRaiseTaskSwitchFaultCurrentTSS(PVMCPUCC pVCpu) RT_NOEXCEPT;
5534	VBOXSTRICTRC iemRaiseTaskSwitchFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
5535	VBOXSTRICTRC iemRaiseTaskSwitchFaultBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5536	/VBOXSTRICTRC iemRaiseSelectorNotPresent(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;/
5537	VBOXSTRICTRC iemRaiseSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5538	VBOXSTRICTRC iemRaiseSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5539	VBOXSTRICTRC iemRaiseStackSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5540	VBOXSTRICTRC iemRaiseStackSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5541	VBOXSTRICTRC iemRaiseGeneralProtectionFault(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5542	VBOXSTRICTRC iemRaiseGeneralProtectionFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
5543	#ifdef IEM_WITH_SETJMP
5544	DECL_NO_RETURN(void) iemRaiseGeneralProtectionFault0Jmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5545	#endif
5546	VBOXSTRICTRC iemRaiseGeneralProtectionFaultBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
5547	VBOXSTRICTRC iemRaiseNotCanonical(PVMCPUCC pVCpu) RT_NOEXCEPT;
5548	VBOXSTRICTRC iemRaiseSelectorBounds(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
5549	#ifdef IEM_WITH_SETJMP
5550	DECL_NO_RETURN(void) iemRaiseSelectorBoundsJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
5551	#endif
5552	VBOXSTRICTRC iemRaiseSelectorBoundsBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
5553	#ifdef IEM_WITH_SETJMP
5554	DECL_NO_RETURN(void) iemRaiseSelectorBoundsBySelectorJmp(PVMCPUCC pVCpu, RTSEL Sel) IEM_NOEXCEPT_MAY_LONGJMP;
5555	#endif
5556	VBOXSTRICTRC iemRaiseSelectorInvalidAccess(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
5557	#ifdef IEM_WITH_SETJMP
5558	DECL_NO_RETURN(void) iemRaiseSelectorInvalidAccessJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
5559	#endif
5560	VBOXSTRICTRC iemRaisePageFault(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) RT_NOEXCEPT;
5561	#ifdef IEM_WITH_SETJMP
5562	DECL_NO_RETURN(void) iemRaisePageFaultJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) IEM_NOEXCEPT_MAY_LONGJMP;
5563	#endif
5564	VBOXSTRICTRC iemRaiseMathFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
5565	#ifdef IEM_WITH_SETJMP
5566	DECL_NO_RETURN(void) iemRaiseMathFaultJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5567	#endif
5568	VBOXSTRICTRC iemRaiseAlignmentCheckException(PVMCPUCC pVCpu) RT_NOEXCEPT;
5569	#ifdef IEM_WITH_SETJMP
5570	DECL_NO_RETURN(void) iemRaiseAlignmentCheckExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5571	#endif
5572	VBOXSTRICTRC iemRaiseSimdFpException(PVMCPUCC pVCpu) RT_NOEXCEPT;
5573	#ifdef IEM_WITH_SETJMP
5574	DECL_NO_RETURN(void) iemRaiseSimdFpExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5575	#endif
5576
5577	void iemLogSyscallRealModeInt(PVMCPUCC pVCpu, uint8_t u8Vector, uint8_t cbInstr);
5578	void iemLogSyscallProtModeInt(PVMCPUCC pVCpu, uint8_t u8Vector, uint8_t cbInstr);
5579
5580	IEM_CIMPL_DEF_0(iemCImplRaiseDivideError);
5581	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidLockPrefix);
5582	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidOpcode);
5583
5584	/**
5585	* Macro for calling iemCImplRaiseDivideError().
5586	*
5587	* This is for things that will _always_ decode to an \#DE, taking the
5588	* recompiler into consideration and everything.
5589	*
5590	* @return Strict VBox status code.
5591	*/
5592	#define IEMOP_RAISE_DIVIDE_ERROR_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseDivideError)
5593
5594	/**
5595	* Macro for calling iemCImplRaiseInvalidLockPrefix().
5596	*
5597	* This is for things that will _always_ decode to an \#UD, taking the
5598	* recompiler into consideration and everything.
5599	*
5600	* @return Strict VBox status code.
5601	*/
5602	#define IEMOP_RAISE_INVALID_LOCK_PREFIX_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidLockPrefix)
5603
5604	/**
5605	* Macro for calling iemCImplRaiseInvalidOpcode() for decode/static \#UDs.
5606	*
5607	* This is for things that will _always_ decode to an \#UD, taking the
5608	* recompiler into consideration and everything.
5609	*
5610	* @return Strict VBox status code.
5611	*/
5612	#define IEMOP_RAISE_INVALID_OPCODE_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidOpcode)
5613
5614	/**
5615	* Macro for calling iemCImplRaiseInvalidOpcode() for runtime-style \#UDs.
5616	*
5617	* Using this macro means you've got _buggy_ _code_ and are doing things that
5618	* belongs exclusively in IEMAllCImpl.cpp during decoding.
5619	*
5620	* @return Strict VBox status code.
5621	* @see IEMOP_RAISE_INVALID_OPCODE_RET
5622	*/
5623	#define IEMOP_RAISE_INVALID_OPCODE_RUNTIME_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidOpcode)
5624
5625	/** @} */
5626
5627	/** @name Register Access.
5628	* @{ */
5629	VBOXSTRICTRC iemRegRipRelativeJumpS8AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int8_t offNextInstr,
5630	IEMMODE enmEffOpSize) RT_NOEXCEPT;
5631	VBOXSTRICTRC iemRegRipRelativeJumpS16AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int16_t offNextInstr) RT_NOEXCEPT;
5632	VBOXSTRICTRC iemRegRipRelativeJumpS32AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int32_t offNextInstr,
5633	IEMMODE enmEffOpSize) RT_NOEXCEPT;
5634	/** @} */
5635
5636	/** @name FPU access and helpers.
5637	* @{ */
5638	void iemFpuPushResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
5639	void iemFpuPushResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5640	void iemFpuPushResultTwo(PVMCPUCC pVCpu, PIEMFPURESULTTWO pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
5641	void iemFpuStoreResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
5642	void iemFpuStoreResultThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
5643	void iemFpuStoreResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
5644	uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5645	void iemFpuStoreResultWithMemOpThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
5646	uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5647	void iemFpuUpdateOpcodeAndIp(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5648	void iemFpuUpdateFSW(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
5649	void iemFpuUpdateFSWThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
5650	void iemFpuUpdateFSWWithMemOp(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5651	void iemFpuUpdateFSWThenPopPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
5652	void iemFpuUpdateFSWWithMemOpThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5653	void iemFpuStackUnderflow(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
5654	void iemFpuStackUnderflowWithMemOp(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5655	void iemFpuStackUnderflowThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
5656	void iemFpuStackUnderflowWithMemOpThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5657	void iemFpuStackUnderflowThenPopPop(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5658	void iemFpuStackPushUnderflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5659	void iemFpuStackPushUnderflowTwo(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5660	void iemFpuStackPushOverflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5661	void iemFpuStackPushOverflowWithMemOp(PVMCPUCC pVCpu, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5662	/** @} */
5663
5664	/** @name SSE+AVX SIMD access and helpers.
5665	* @{ */
5666	void iemSseUpdateMxcsr(PVMCPUCC pVCpu, uint32_t fMxcsr) RT_NOEXCEPT;
5667	/** @} */
5668
5669	/** @name Memory access.
5670	* @{ */
5671
5672	/** Report a \#GP instead of \#AC and do not restrict to ring-3 */
5673	#define IEM_MEMMAP_F_ALIGN_GP RT_BIT_32(16)
5674	/** SSE access that should report a \#GP instead of \#AC, unless MXCSR.MM=1
5675	* when it works like normal \#AC. Always used with IEM_MEMMAP_F_ALIGN_GP. */
5676	#define IEM_MEMMAP_F_ALIGN_SSE RT_BIT_32(17)
5677	/** If \#AC is applicable, raise it. Always used with IEM_MEMMAP_F_ALIGN_GP.
5678	* Users include FXSAVE & FXRSTOR. */
5679	#define IEM_MEMMAP_F_ALIGN_GP_OR_AC RT_BIT_32(18)
5680
5681	VBOXSTRICTRC iemMemMap(PVMCPUCC pVCpu, void *ppvMem, uint8_t pbUnmapInfo, size_t cbMem, uint8_t iSegReg, RTGCPTR GCPtrMem,
5682	uint32_t fAccess, uint32_t uAlignCtl) RT_NOEXCEPT;
5683	VBOXSTRICTRC iemMemCommitAndUnmap(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5684	#ifndef IN_RING3
5685	VBOXSTRICTRC iemMemCommitAndUnmapPostponeTroubleToR3(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5686	#endif
5687	void iemMemRollbackAndUnmap(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5688	void iemMemRollback(PVMCPUCC pVCpu) RT_NOEXCEPT;
5689	VBOXSTRICTRC iemMemApplySegment(PVMCPUCC pVCpu, uint32_t fAccess, uint8_t iSegReg, size_t cbMem, PRTGCPTR pGCPtrMem) RT_NOEXCEPT;
5690	VBOXSTRICTRC iemMemMarkSelDescAccessed(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5691	VBOXSTRICTRC iemMemPageTranslateAndCheckAccess(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t cbAccess, uint32_t fAccess, PRTGCPHYS pGCPhysMem) RT_NOEXCEPT;
5692
5693	void iemOpcodeFlushLight(PVMCPUCC pVCpu, uint8_t cbInstr);
5694	void iemOpcodeFlushHeavy(PVMCPUCC pVCpu, uint8_t cbInstr);
5695	#ifdef IEM_WITH_CODE_TLB
5696	void iemOpcodeFetchBytesJmp(PVMCPUCC pVCpu, size_t cbDst, void *pvDst) IEM_NOEXCEPT_MAY_LONGJMP;
5697	#else
5698	VBOXSTRICTRC iemOpcodeFetchMoreBytes(PVMCPUCC pVCpu, size_t cbMin) RT_NOEXCEPT;
5699	#endif
5700	#ifdef IEM_WITH_SETJMP
5701	uint8_t iemOpcodeGetNextU8SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5702	uint16_t iemOpcodeGetNextU16SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5703	uint32_t iemOpcodeGetNextU32SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5704	uint64_t iemOpcodeGetNextU64SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5705	#else
5706	VBOXSTRICTRC iemOpcodeGetNextU8Slow(PVMCPUCC pVCpu, uint8_t *pb) RT_NOEXCEPT;
5707	VBOXSTRICTRC iemOpcodeGetNextS8SxU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
5708	VBOXSTRICTRC iemOpcodeGetNextS8SxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
5709	VBOXSTRICTRC iemOpcodeGetNextS8SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5710	VBOXSTRICTRC iemOpcodeGetNextU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
5711	VBOXSTRICTRC iemOpcodeGetNextU16ZxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
5712	VBOXSTRICTRC iemOpcodeGetNextU16ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5713	VBOXSTRICTRC iemOpcodeGetNextU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
5714	VBOXSTRICTRC iemOpcodeGetNextU32ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5715	VBOXSTRICTRC iemOpcodeGetNextS32SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5716	VBOXSTRICTRC iemOpcodeGetNextU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5717	#endif
5718
5719	VBOXSTRICTRC iemMemFetchDataU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5720	VBOXSTRICTRC iemMemFetchDataU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5721	VBOXSTRICTRC iemMemFetchDataU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5722	VBOXSTRICTRC iemMemFetchDataU32_ZX_U64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5723	VBOXSTRICTRC iemMemFetchDataU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5724	VBOXSTRICTRC iemMemFetchDataU64AlignedU128(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5725	VBOXSTRICTRC iemMemFetchDataR80(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5726	VBOXSTRICTRC iemMemFetchDataD80(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5727	VBOXSTRICTRC iemMemFetchDataU128(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5728	VBOXSTRICTRC iemMemFetchDataU128NoAc(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5729	VBOXSTRICTRC iemMemFetchDataU128AlignedSse(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5730	VBOXSTRICTRC iemMemFetchDataU256(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5731	VBOXSTRICTRC iemMemFetchDataU256NoAc(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5732	VBOXSTRICTRC iemMemFetchDataU256AlignedAvx(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5733	VBOXSTRICTRC iemMemFetchDataXdtr(PVMCPUCC pVCpu, uint16_t *pcbLimit, PRTGCPTR pGCPtrBase, uint8_t iSegReg,
5734	RTGCPTR GCPtrMem, IEMMODE enmOpSize) RT_NOEXCEPT;
5735	#ifdef IEM_WITH_SETJMP
5736	uint8_t iemMemFetchDataU8SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5737	uint16_t iemMemFetchDataU16SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5738	uint32_t iemMemFetchDataU32SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5739	uint32_t iemMemFlatFetchDataU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5740	uint64_t iemMemFetchDataU64SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5741	uint64_t iemMemFetchDataU64AlignedU128SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5742	void iemMemFetchDataR80SafeJmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5743	void iemMemFetchDataD80SafeJmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5744	void iemMemFetchDataU128SafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5745	void iemMemFetchDataU128NoAcSafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5746	void iemMemFetchDataU128AlignedSseSafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5747	void iemMemFetchDataU256SafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5748	void iemMemFetchDataU256NoAcSafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5749	void iemMemFetchDataU256AlignedAvxSafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5750	# if 0 /* these are inlined now */
5751	uint8_t iemMemFetchDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5752	uint16_t iemMemFetchDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5753	uint32_t iemMemFetchDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5754	uint32_t iemMemFlatFetchDataU32Jmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5755	uint64_t iemMemFetchDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5756	uint64_t iemMemFetchDataU64AlignedU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5757	void iemMemFetchDataR80Jmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5758	void iemMemFetchDataD80Jmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5759	void iemMemFetchDataU128Jmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5760	void iemMemFetchDataU128NoAcJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5761	void iemMemFetchDataU128AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5762	void iemMemFetchDataU256NoAcJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5763	void iemMemFetchDataU256AlignedAvxJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5764	# endif
5765	void iemMemFetchDataU256Jmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5766	#endif
5767
5768	VBOXSTRICTRC iemMemFetchSysU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5769	VBOXSTRICTRC iemMemFetchSysU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5770	VBOXSTRICTRC iemMemFetchSysU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5771	VBOXSTRICTRC iemMemFetchSysU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5772	VBOXSTRICTRC iemMemFetchSelDesc(PVMCPUCC pVCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt) RT_NOEXCEPT;
5773
5774	VBOXSTRICTRC iemMemStoreDataU8(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) RT_NOEXCEPT;
5775	VBOXSTRICTRC iemMemStoreDataU16(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) RT_NOEXCEPT;
5776	VBOXSTRICTRC iemMemStoreDataU32(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) RT_NOEXCEPT;
5777	VBOXSTRICTRC iemMemStoreDataU64(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) RT_NOEXCEPT;
5778	VBOXSTRICTRC iemMemStoreDataU128(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
5779	VBOXSTRICTRC iemMemStoreDataU128NoAc(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
5780	VBOXSTRICTRC iemMemStoreDataU128AlignedSse(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
5781	VBOXSTRICTRC iemMemStoreDataU256(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
5782	VBOXSTRICTRC iemMemStoreDataU256NoAc(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
5783	VBOXSTRICTRC iemMemStoreDataU256AlignedAvx(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
5784	VBOXSTRICTRC iemMemStoreDataXdtr(PVMCPUCC pVCpu, uint16_t cbLimit, RTGCPTR GCPtrBase, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5785	#ifdef IEM_WITH_SETJMP
5786	void iemMemStoreDataU8SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
5787	void iemMemStoreDataU16SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
5788	void iemMemStoreDataU32SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
5789	void iemMemStoreDataU64SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
5790	void iemMemStoreDataU128SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5791	void iemMemStoreDataU128NoAcSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT128U pu128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5792	void iemMemStoreDataU128AlignedSseSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT128U pu128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5793	void iemMemStoreDataU256SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5794	void iemMemStoreDataU256NoAcSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5795	void iemMemStoreDataU256AlignedAvxSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5796	void iemMemStoreDataR80SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTFLOAT80U pr80Value) IEM_NOEXCEPT_MAY_LONGJMP;
5797	void iemMemStoreDataD80SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTPBCD80U pd80Value) IEM_NOEXCEPT_MAY_LONGJMP;
5798	#if 0
5799	void iemMemStoreDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
5800	void iemMemStoreDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
5801	void iemMemStoreDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
5802	void iemMemStoreDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
5803	void iemMemStoreDataU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5804	void iemMemStoreDataNoAcU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5805	void iemMemStoreDataU256NoAcJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5806	void iemMemStoreDataU256AlignedAvxJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5807	#endif
5808	void iemMemStoreDataU128AlignedSseJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5809	void iemMemStoreDataU256Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5810	#endif
5811
5812	#ifdef IEM_WITH_SETJMP
5813	uint8_t iemMemMapDataU8RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5814	uint8_t iemMemMapDataU8AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5815	uint8_t iemMemMapDataU8WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5816	uint8_t const iemMemMapDataU8RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5817	uint16_t iemMemMapDataU16RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5818	uint16_t iemMemMapDataU16AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5819	uint16_t iemMemMapDataU16WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5820	uint16_t const iemMemMapDataU16RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5821	uint32_t iemMemMapDataU32RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5822	uint32_t iemMemMapDataU32AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5823	uint32_t iemMemMapDataU32WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5824	uint32_t const iemMemMapDataU32RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5825	uint64_t iemMemMapDataU64RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5826	uint64_t iemMemMapDataU64AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5827	uint64_t iemMemMapDataU64WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5828	uint64_t const iemMemMapDataU64RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5829	PRTFLOAT80U iemMemMapDataR80RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5830	PRTFLOAT80U iemMemMapDataR80WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5831	PCRTFLOAT80U iemMemMapDataR80RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5832	PRTPBCD80U iemMemMapDataD80RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5833	PRTPBCD80U iemMemMapDataD80WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5834	PCRTPBCD80U iemMemMapDataD80RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5835	PRTUINT128U iemMemMapDataU128RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5836	PRTUINT128U iemMemMapDataU128AtSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5837	PRTUINT128U iemMemMapDataU128WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5838	PCRTUINT128U iemMemMapDataU128RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5839
5840	void iemMemCommitAndUnmapJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5841	void iemMemCommitAndUnmapRwSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5842	void iemMemCommitAndUnmapAtSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5843	void iemMemCommitAndUnmapWoSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5844	void iemMemCommitAndUnmapRoSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5845	void iemMemRollbackAndUnmapWoSafe(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5846	#endif
5847
5848	VBOXSTRICTRC iemMemStackPushBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
5849	void *ppvMem, uint8_t pbUnmapInfo, uint64_t *puNewRsp) RT_NOEXCEPT;
5850	VBOXSTRICTRC iemMemStackPushCommitSpecial(PVMCPUCC pVCpu, uint8_t bUnmapInfo, uint64_t uNewRsp) RT_NOEXCEPT;
5851	VBOXSTRICTRC iemMemStackPushU16(PVMCPUCC pVCpu, uint16_t u16Value) RT_NOEXCEPT;
5852	VBOXSTRICTRC iemMemStackPushU32(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
5853	VBOXSTRICTRC iemMemStackPushU64(PVMCPUCC pVCpu, uint64_t u64Value) RT_NOEXCEPT;
5854	VBOXSTRICTRC iemMemStackPushU16Ex(PVMCPUCC pVCpu, uint16_t u16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5855	VBOXSTRICTRC iemMemStackPushU32Ex(PVMCPUCC pVCpu, uint32_t u32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5856	VBOXSTRICTRC iemMemStackPushU64Ex(PVMCPUCC pVCpu, uint64_t u64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5857	VBOXSTRICTRC iemMemStackPushU32SReg(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
5858	VBOXSTRICTRC iemMemStackPopBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
5859	void const *ppvMem, uint8_t pbUnmapInfo, uint64_t *puNewRsp) RT_NOEXCEPT;
5860	VBOXSTRICTRC iemMemStackPopContinueSpecial(PVMCPUCC pVCpu, size_t off, size_t cbMem,
5861	void const *ppvMem, uint8_t pbUnmapInfo, uint64_t uCurNewRsp) RT_NOEXCEPT;
5862	VBOXSTRICTRC iemMemStackPopDoneSpecial(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5863	VBOXSTRICTRC iemMemStackPopU16(PVMCPUCC pVCpu, uint16_t *pu16Value) RT_NOEXCEPT;
5864	VBOXSTRICTRC iemMemStackPopU32(PVMCPUCC pVCpu, uint32_t *pu32Value) RT_NOEXCEPT;
5865	VBOXSTRICTRC iemMemStackPopU64(PVMCPUCC pVCpu, uint64_t *pu64Value) RT_NOEXCEPT;
5866	VBOXSTRICTRC iemMemStackPopU16Ex(PVMCPUCC pVCpu, uint16_t *pu16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5867	VBOXSTRICTRC iemMemStackPopU32Ex(PVMCPUCC pVCpu, uint32_t *pu32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5868	VBOXSTRICTRC iemMemStackPopU64Ex(PVMCPUCC pVCpu, uint64_t *pu64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5869
5870	#ifdef IEM_WITH_SETJMP
5871	void iemMemStackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5872	void iemMemStackPushU32SafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5873	void iemMemStackPushU32SRegSafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5874	void iemMemStackPushU64SafeJmp(PVMCPUCC pVCpu, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5875	void iemMemStackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5876	void iemMemStackPopGRegU32SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5877	void iemMemStackPopGRegU64SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5878
5879	void iemMemFlat32StackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5880	void iemMemFlat32StackPushU32SafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5881	void iemMemFlat32StackPushU32SRegSafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5882	void iemMemFlat32StackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5883	void iemMemFlat32StackPopGRegU32SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5884
5885	void iemMemFlat64StackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5886	void iemMemFlat64StackPushU64SafeJmp(PVMCPUCC pVCpu, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5887	void iemMemFlat64StackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5888	void iemMemFlat64StackPopGRegU64SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5889
5890	void iemMemStoreStackU16SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5891	void iemMemStoreStackU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5892	void iemMemStoreStackU32SRegSafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5893	void iemMemStoreStackU64SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5894
5895	uint16_t iemMemFetchStackU16SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5896	uint32_t iemMemFetchStackU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5897	uint64_t iemMemFetchStackU64SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5898
5899	#endif
5900
5901	/** @} */
5902
5903	/** @name IEMAllCImpl.cpp
5904	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/'
5905	* @{ */
5906	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem16, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5907	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem32, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5908	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem64, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5909	IEM_CIMPL_PROTO_0(iemCImpl_popa_16);
5910	IEM_CIMPL_PROTO_0(iemCImpl_popa_32);
5911	IEM_CIMPL_PROTO_0(iemCImpl_pusha_16);
5912	IEM_CIMPL_PROTO_0(iemCImpl_pusha_32);
5913	IEM_CIMPL_PROTO_1(iemCImpl_pushf, IEMMODE, enmEffOpSize);
5914	IEM_CIMPL_PROTO_1(iemCImpl_popf, IEMMODE, enmEffOpSize);
5915	IEM_CIMPL_PROTO_3(iemCImpl_FarJmp, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
5916	IEM_CIMPL_PROTO_3(iemCImpl_callf, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
5917	typedef IEM_CIMPL_DECL_TYPE_3(FNIEMCIMPLFARBRANCH, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
5918	typedef FNIEMCIMPLFARBRANCH *PFNIEMCIMPLFARBRANCH;
5919	IEM_CIMPL_PROTO_2(iemCImpl_retf, IEMMODE, enmEffOpSize, uint16_t, cbPop);
5920	IEM_CIMPL_PROTO_3(iemCImpl_enter, IEMMODE, enmEffOpSize, uint16_t, cbFrame, uint8_t, cParameters);
5921	IEM_CIMPL_PROTO_1(iemCImpl_leave, IEMMODE, enmEffOpSize);
5922	IEM_CIMPL_PROTO_2(iemCImpl_int, uint8_t, u8Int, IEMINT, enmInt);
5923	IEM_CIMPL_PROTO_1(iemCImpl_iret_real_v8086, IEMMODE, enmEffOpSize);
5924	IEM_CIMPL_PROTO_4(iemCImpl_iret_prot_v8086, uint32_t, uNewEip, uint16_t, uNewCs, uint32_t, uNewFlags, uint64_t, uNewRsp);
5925	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot_NestedTask, IEMMODE, enmEffOpSize);
5926	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot, IEMMODE, enmEffOpSize);
5927	IEM_CIMPL_PROTO_1(iemCImpl_iret_64bit, IEMMODE, enmEffOpSize);
5928	IEM_CIMPL_PROTO_1(iemCImpl_iret, IEMMODE, enmEffOpSize);
5929	IEM_CIMPL_PROTO_0(iemCImpl_loadall286);
5930	IEM_CIMPL_PROTO_0(iemCImpl_syscall);
5931	IEM_CIMPL_PROTO_1(iemCImpl_sysret, IEMMODE, enmEffOpSize);
5932	IEM_CIMPL_PROTO_0(iemCImpl_sysenter);
5933	IEM_CIMPL_PROTO_1(iemCImpl_sysexit, IEMMODE, enmEffOpSize);
5934	IEM_CIMPL_PROTO_2(iemCImpl_LoadSReg, uint8_t, iSegReg, uint16_t, uSel);
5935	IEM_CIMPL_PROTO_2(iemCImpl_load_SReg, uint8_t, iSegReg, uint16_t, uSel);
5936	IEM_CIMPL_PROTO_2(iemCImpl_pop_Sreg, uint8_t, iSegReg, IEMMODE, enmEffOpSize);
5937	IEM_CIMPL_PROTO_5(iemCImpl_load_SReg_Greg, uint16_t, uSel, uint64_t, offSeg, uint8_t, iSegReg, uint8_t, iGReg, IEMMODE, enmEffOpSize);
5938	IEM_CIMPL_PROTO_2(iemCImpl_VerX, uint16_t, uSel, bool, fWrite);
5939	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u64, uint64_t *, pu64Dst, uint16_t, uSel, bool, fIsLar);
5940	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u16, uint16_t *, pu16Dst, uint16_t, uSel, bool, fIsLar);
5941	IEM_CIMPL_PROTO_3(iemCImpl_lgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
5942	IEM_CIMPL_PROTO_2(iemCImpl_sgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5943	IEM_CIMPL_PROTO_3(iemCImpl_lidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
5944	IEM_CIMPL_PROTO_2(iemCImpl_sidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5945	IEM_CIMPL_PROTO_1(iemCImpl_lldt, uint16_t, uNewLdt);
5946	IEM_CIMPL_PROTO_2(iemCImpl_sldt_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
5947	IEM_CIMPL_PROTO_2(iemCImpl_sldt_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5948	IEM_CIMPL_PROTO_1(iemCImpl_ltr, uint16_t, uNewTr);
5949	IEM_CIMPL_PROTO_2(iemCImpl_str_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
5950	IEM_CIMPL_PROTO_2(iemCImpl_str_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5951	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Cd, uint8_t, iGReg, uint8_t, iCrReg);
5952	IEM_CIMPL_PROTO_2(iemCImpl_smsw_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
5953	IEM_CIMPL_PROTO_2(iemCImpl_smsw_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5954	IEM_CIMPL_PROTO_4(iemCImpl_load_CrX, uint8_t, iCrReg, uint64_t, uNewCrX, IEMACCESSCRX, enmAccessCrX, uint8_t, iGReg);
5955	IEM_CIMPL_PROTO_2(iemCImpl_mov_Cd_Rd, uint8_t, iCrReg, uint8_t, iGReg);
5956	IEM_CIMPL_PROTO_2(iemCImpl_lmsw, uint16_t, u16NewMsw, RTGCPTR, GCPtrEffDst);
5957	IEM_CIMPL_PROTO_0(iemCImpl_clts);
5958	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Dd, uint8_t, iGReg, uint8_t, iDrReg);
5959	IEM_CIMPL_PROTO_2(iemCImpl_mov_Dd_Rd, uint8_t, iDrReg, uint8_t, iGReg);
5960	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Td, uint8_t, iGReg, uint8_t, iTrReg);
5961	IEM_CIMPL_PROTO_2(iemCImpl_mov_Td_Rd, uint8_t, iTrReg, uint8_t, iGReg);
5962	IEM_CIMPL_PROTO_1(iemCImpl_invlpg, RTGCPTR, GCPtrPage);
5963	IEM_CIMPL_PROTO_3(iemCImpl_invpcid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvpcidDesc, uint64_t, uInvpcidType);
5964	IEM_CIMPL_PROTO_0(iemCImpl_invd);
5965	IEM_CIMPL_PROTO_0(iemCImpl_wbinvd);
5966	IEM_CIMPL_PROTO_0(iemCImpl_rsm);
5967	IEM_CIMPL_PROTO_0(iemCImpl_rdtsc);
5968	IEM_CIMPL_PROTO_0(iemCImpl_rdtscp);
5969	IEM_CIMPL_PROTO_0(iemCImpl_rdpmc);
5970	IEM_CIMPL_PROTO_0(iemCImpl_rdmsr);
5971	IEM_CIMPL_PROTO_0(iemCImpl_wrmsr);
5972	IEM_CIMPL_PROTO_3(iemCImpl_in, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
5973	IEM_CIMPL_PROTO_2(iemCImpl_in_eAX_DX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
5974	IEM_CIMPL_PROTO_3(iemCImpl_out, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
5975	IEM_CIMPL_PROTO_2(iemCImpl_out_DX_eAX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
5976	IEM_CIMPL_PROTO_0(iemCImpl_cli);
5977	IEM_CIMPL_PROTO_0(iemCImpl_sti);
5978	IEM_CIMPL_PROTO_0(iemCImpl_hlt);
5979	IEM_CIMPL_PROTO_1(iemCImpl_monitor, uint8_t, iEffSeg);
5980	IEM_CIMPL_PROTO_0(iemCImpl_mwait);
5981	IEM_CIMPL_PROTO_0(iemCImpl_swapgs);
5982	IEM_CIMPL_PROTO_0(iemCImpl_cpuid);
5983	IEM_CIMPL_PROTO_1(iemCImpl_aad, uint8_t, bImm);
5984	IEM_CIMPL_PROTO_1(iemCImpl_aam, uint8_t, bImm);
5985	IEM_CIMPL_PROTO_0(iemCImpl_daa);
5986	IEM_CIMPL_PROTO_0(iemCImpl_das);
5987	IEM_CIMPL_PROTO_0(iemCImpl_aaa);
5988	IEM_CIMPL_PROTO_0(iemCImpl_aas);
5989	IEM_CIMPL_PROTO_3(iemCImpl_bound_16, int16_t, idxArray, int16_t, idxLowerBound, int16_t, idxUpperBound);
5990	IEM_CIMPL_PROTO_3(iemCImpl_bound_32, int32_t, idxArray, int32_t, idxLowerBound, int32_t, idxUpperBound);
5991	IEM_CIMPL_PROTO_0(iemCImpl_xgetbv);
5992	IEM_CIMPL_PROTO_0(iemCImpl_xsetbv);
5993	IEM_CIMPL_PROTO_5(iemCImpl_cmpxchg16b_fallback_rendezvous, PRTUINT128U, pu128Dst, PRTUINT128U, pu128RaxRdx,
5994	PRTUINT128U, pu128RbxRcx, uint32_t *, pEFlags, uint8_t, bUnmapInfo);
5995	IEM_CIMPL_PROTO_2(iemCImpl_clflush_clflushopt, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
5996	IEM_CIMPL_PROTO_1(iemCImpl_finit, bool, fCheckXcpts);
5997	IEM_CIMPL_PROTO_3(iemCImpl_fxsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5998	IEM_CIMPL_PROTO_3(iemCImpl_fxrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
5999	IEM_CIMPL_PROTO_3(iemCImpl_xsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
6000	IEM_CIMPL_PROTO_3(iemCImpl_xrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
6001	IEM_CIMPL_PROTO_2(iemCImpl_stmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
6002	IEM_CIMPL_PROTO_2(iemCImpl_vstmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
6003	IEM_CIMPL_PROTO_2(iemCImpl_ldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
6004	IEM_CIMPL_PROTO_3(iemCImpl_fnstenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6005	IEM_CIMPL_PROTO_3(iemCImpl_fnsave, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6006	IEM_CIMPL_PROTO_3(iemCImpl_fldenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6007	IEM_CIMPL_PROTO_3(iemCImpl_frstor, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6008	IEM_CIMPL_PROTO_1(iemCImpl_fldcw, uint16_t, u16Fcw);
6009	IEM_CIMPL_PROTO_2(iemCImpl_fxch_underflow, uint8_t, iStReg, uint16_t, uFpuOpcode);
6010	IEM_CIMPL_PROTO_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, bool, fUCmp, uint32_t, uPopAndFpuOpcode);
6011	IEM_CIMPL_PROTO_2(iemCImpl_rdseed, uint8_t, iReg, IEMMODE, enmEffOpSize);
6012	IEM_CIMPL_PROTO_2(iemCImpl_rdrand, uint8_t, iReg, IEMMODE, enmEffOpSize);
6013	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovps_load_u128, uint8_t, iXRegDst, uint8_t, iXRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6014	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovps_load_u256, uint8_t, iYRegDst, uint8_t, iYRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6015	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovps_store_u128, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iXRegMsk, uint8_t, iXRegSrc);
6016	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovps_store_u256, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iYRegMsk, uint8_t, iYRegSrc);
6017	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovd_load_u128, uint8_t, iXRegDst, uint8_t, iXRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6018	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovd_load_u256, uint8_t, iYRegDst, uint8_t, iYRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6019	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovd_store_u128, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iXRegMsk, uint8_t, iXRegSrc);
6020	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovd_store_u256, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iYRegMsk, uint8_t, iYRegSrc);
6021	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovpd_load_u128, uint8_t, iXRegDst, uint8_t, iXRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6022	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovpd_load_u256, uint8_t, iYRegDst, uint8_t, iYRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6023	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovpd_store_u128, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iXRegMsk, uint8_t, iXRegSrc);
6024	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovpd_store_u256, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iYRegMsk, uint8_t, iYRegSrc);
6025	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovq_load_u128, uint8_t, iXRegDst, uint8_t, iXRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6026	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovq_load_u256, uint8_t, iYRegDst, uint8_t, iYRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6027	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovq_store_u128, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iXRegMsk, uint8_t, iXRegSrc);
6028	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovq_store_u256, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iYRegMsk, uint8_t, iYRegSrc);
6029
6030	/** @} */
6031
6032	/** @name IEMAllCImplStrInstr.cpp.h
6033	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/' -e 's/RT_CONCAT4(//' \
6034	* -e 's/,ADDR_SIZE)/64/g' -e 's/,OP_SIZE,/64/g' -e 's/,OP_rAX,/rax/g' IEMAllCImplStrInstr.cpp.h
6035	* @{ */
6036	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr16, uint8_t, iEffSeg);
6037	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr16, uint8_t, iEffSeg);
6038	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m16);
6039	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m16);
6040	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr16, uint8_t, iEffSeg);
6041	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m16);
6042	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m16, int8_t, iEffSeg);
6043	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr16, bool, fIoChecked);
6044	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr16, bool, fIoChecked);
6045	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6046	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6047
6048	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr16, uint8_t, iEffSeg);
6049	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr16, uint8_t, iEffSeg);
6050	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m16);
6051	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m16);
6052	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr16, uint8_t, iEffSeg);
6053	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m16);
6054	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m16, int8_t, iEffSeg);
6055	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr16, bool, fIoChecked);
6056	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr16, bool, fIoChecked);
6057	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6058	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6059
6060	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr16, uint8_t, iEffSeg);
6061	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr16, uint8_t, iEffSeg);
6062	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m16);
6063	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m16);
6064	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr16, uint8_t, iEffSeg);
6065	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m16);
6066	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m16, int8_t, iEffSeg);
6067	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr16, bool, fIoChecked);
6068	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr16, bool, fIoChecked);
6069	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6070	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6071
6072
6073	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr32, uint8_t, iEffSeg);
6074	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr32, uint8_t, iEffSeg);
6075	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m32);
6076	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m32);
6077	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr32, uint8_t, iEffSeg);
6078	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m32);
6079	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m32, int8_t, iEffSeg);
6080	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr32, bool, fIoChecked);
6081	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr32, bool, fIoChecked);
6082	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6083	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6084
6085	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr32, uint8_t, iEffSeg);
6086	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr32, uint8_t, iEffSeg);
6087	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m32);
6088	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m32);
6089	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr32, uint8_t, iEffSeg);
6090	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m32);
6091	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m32, int8_t, iEffSeg);
6092	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr32, bool, fIoChecked);
6093	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr32, bool, fIoChecked);
6094	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6095	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6096
6097	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr32, uint8_t, iEffSeg);
6098	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr32, uint8_t, iEffSeg);
6099	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m32);
6100	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m32);
6101	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr32, uint8_t, iEffSeg);
6102	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m32);
6103	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m32, int8_t, iEffSeg);
6104	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr32, bool, fIoChecked);
6105	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr32, bool, fIoChecked);
6106	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6107	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6108
6109	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr32, uint8_t, iEffSeg);
6110	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr32, uint8_t, iEffSeg);
6111	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m32);
6112	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m32);
6113	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr32, uint8_t, iEffSeg);
6114	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m32);
6115	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m32, int8_t, iEffSeg);
6116	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr32, bool, fIoChecked);
6117	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr32, bool, fIoChecked);
6118	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6119	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6120
6121
6122	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr64, uint8_t, iEffSeg);
6123	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr64, uint8_t, iEffSeg);
6124	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m64);
6125	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m64);
6126	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr64, uint8_t, iEffSeg);
6127	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m64);
6128	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m64, int8_t, iEffSeg);
6129	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr64, bool, fIoChecked);
6130	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr64, bool, fIoChecked);
6131	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6132	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6133
6134	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr64, uint8_t, iEffSeg);
6135	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr64, uint8_t, iEffSeg);
6136	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m64);
6137	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m64);
6138	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr64, uint8_t, iEffSeg);
6139	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m64);
6140	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m64, int8_t, iEffSeg);
6141	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr64, bool, fIoChecked);
6142	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr64, bool, fIoChecked);
6143	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6144	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6145
6146	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr64, uint8_t, iEffSeg);
6147	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr64, uint8_t, iEffSeg);
6148	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m64);
6149	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m64);
6150	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr64, uint8_t, iEffSeg);
6151	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m64);
6152	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m64, int8_t, iEffSeg);
6153	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr64, bool, fIoChecked);
6154	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr64, bool, fIoChecked);
6155	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6156	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6157
6158	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr64, uint8_t, iEffSeg);
6159	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr64, uint8_t, iEffSeg);
6160	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m64);
6161	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m64);
6162	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr64, uint8_t, iEffSeg);
6163	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m64);
6164	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m64, int8_t, iEffSeg);
6165	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr64, bool, fIoChecked);
6166	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr64, bool, fIoChecked);
6167	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6168	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6169	/** @} */
6170
6171	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
6172	VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT;
6173	VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT;
6174	VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT;
6175	VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT;
6176	VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT;
6177	VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
6178	VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALKFAST pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT;
6179	VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT;
6180	VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT;
6181	VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
6182	bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT;
6183	VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
6184	bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT;
6185	VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6186	VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6187	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6188	VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6189	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6190	VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6191	VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT;
6192	VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
6193	RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT;
6194	VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT;
6195	VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT;
6196	VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT;
6197	uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT;
6198	void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT;
6199	VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
6200	uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT;
6201	bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT;
6202	IEM_CIMPL_PROTO_0(iemCImpl_vmxoff);
6203	IEM_CIMPL_PROTO_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon);
6204	IEM_CIMPL_PROTO_0(iemCImpl_vmlaunch);
6205	IEM_CIMPL_PROTO_0(iemCImpl_vmresume);
6206	IEM_CIMPL_PROTO_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
6207	IEM_CIMPL_PROTO_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
6208	IEM_CIMPL_PROTO_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
6209	IEM_CIMPL_PROTO_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField);
6210	IEM_CIMPL_PROTO_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField);
6211	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField);
6212	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg32, uint64_t *, pu32Dst, uint32_t, u32VmcsField);
6213	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField);
6214	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField);
6215	IEM_CIMPL_PROTO_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType);
6216	IEM_CIMPL_PROTO_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType);
6217	IEM_CIMPL_PROTO_0(iemCImpl_vmx_pause);
6218	#endif
6219
6220	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
6221	VBOXSTRICTRC iemSvmVmexit(PVMCPUCC pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2) RT_NOEXCEPT;
6222	VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr, uint64_t uCr2) RT_NOEXCEPT;
6223	VBOXSTRICTRC iemSvmHandleIOIntercept(PVMCPUCC pVCpu, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
6224	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, uint8_t cbInstr) RT_NOEXCEPT;
6225	VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPUCC pVCpu, uint32_t idMsr, bool fWrite, uint8_t cbInstr) RT_NOEXCEPT;
6226	IEM_CIMPL_PROTO_0(iemCImpl_vmrun);
6227	IEM_CIMPL_PROTO_0(iemCImpl_vmload);
6228	IEM_CIMPL_PROTO_0(iemCImpl_vmsave);
6229	IEM_CIMPL_PROTO_0(iemCImpl_clgi);
6230	IEM_CIMPL_PROTO_0(iemCImpl_stgi);
6231	IEM_CIMPL_PROTO_0(iemCImpl_invlpga);
6232	IEM_CIMPL_PROTO_0(iemCImpl_skinit);
6233	IEM_CIMPL_PROTO_0(iemCImpl_svm_pause);
6234	#endif
6235
6236	IEM_CIMPL_PROTO_0(iemCImpl_vmcall); /* vmx */
6237	IEM_CIMPL_PROTO_0(iemCImpl_vmmcall); /* svm */
6238	IEM_CIMPL_PROTO_1(iemCImpl_Hypercall, uint16_t, uDisOpcode); /* both */
6239
6240	extern const PFNIEMOP g_apfnIemInterpretOnlyOneByteMap[256];
6241	extern const PFNIEMOP g_apfnIemInterpretOnlyTwoByteMap[1024];
6242	extern const PFNIEMOP g_apfnIemInterpretOnlyThreeByte0f3a[1024];
6243	extern const PFNIEMOP g_apfnIemInterpretOnlyThreeByte0f38[1024];
6244	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap1[1024];
6245	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap2[1024];
6246	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap3[1024];
6247
6248	/*
6249	* Recompiler related stuff.
6250	*/
6251	extern const PFNIEMOP g_apfnIemThreadedRecompilerOneByteMap[256];
6252	extern const PFNIEMOP g_apfnIemThreadedRecompilerTwoByteMap[1024];
6253	extern const PFNIEMOP g_apfnIemThreadedRecompilerThreeByte0f3a[1024];
6254	extern const PFNIEMOP g_apfnIemThreadedRecompilerThreeByte0f38[1024];
6255	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap1[1024];
6256	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap2[1024];
6257	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap3[1024];
6258
6259	DECLCALLBACK(int) iemTbInit(PVMCC pVM, uint32_t cInitialTbs, uint32_t cMaxTbs,
6260	uint64_t cbInitialExec, uint64_t cbMaxExec, uint32_t cbChunkExec);
6261	void iemThreadedTbObsolete(PVMCPUCC pVCpu, PIEMTB pTb, bool fSafeToFree);
6262	DECLHIDDEN(void) iemTbAllocatorFree(PVMCPUCC pVCpu, PIEMTB pTb);
6263	void iemTbAllocatorProcessDelayedFrees(PVMCPUCC pVCpu, PIEMTBALLOCATOR pTbAllocator);
6264	void iemTbAllocatorFreeupNativeSpace(PVMCPUCC pVCpu, uint32_t cNeededInstrs);
6265	DECLHIDDEN(const char ) iemTbFlagsToString(uint32_t fFlags, char pszBuf, size_t cbBuf) RT_NOEXCEPT;
6266	DECLHIDDEN(void) iemThreadedDisassembleTb(PCIEMTB pTb, PCDBGFINFOHLP pHlp) RT_NOEXCEPT;
6267
6268
6269	/** @todo FNIEMTHREADEDFUNC and friends may need more work... */
6270	#if defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
6271	typedef VBOXSTRICTRC /__attribute__((__nothrow__))/ FNIEMTHREADEDFUNC(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
6272	typedef FNIEMTHREADEDFUNC *PFNIEMTHREADEDFUNC;
6273	# define IEM_DECL_IEMTHREADEDFUNC_DEF(a_Name) \
6274	VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2)
6275	# define IEM_DECL_IEMTHREADEDFUNC_PROTO(a_Name) \
6276	VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2)
6277
6278	#else
6279	typedef VBOXSTRICTRC (FNIEMTHREADEDFUNC)(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
6280	typedef FNIEMTHREADEDFUNC *PFNIEMTHREADEDFUNC;
6281	# define IEM_DECL_IEMTHREADEDFUNC_DEF(a_Name) \
6282	VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2) IEM_NOEXCEPT_MAY_LONGJMP
6283	# define IEM_DECL_IEMTHREADEDFUNC_PROTO(a_Name) \
6284	VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2) IEM_NOEXCEPT_MAY_LONGJMP
6285	#endif
6286
6287
6288	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_Nop);
6289	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_LogCpuState);
6290
6291	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_DeferToCImpl0);
6292
6293	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckIrq);
6294	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckMode);
6295	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckHwInstrBps);
6296	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLim);
6297
6298	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodes);
6299	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodes);
6300	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesConsiderCsLim);
6301
6302	/* Branching: */
6303	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndPcAndOpcodes);
6304	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckPcAndOpcodes);
6305	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckPcAndOpcodesConsiderCsLim);
6306
6307	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesLoadingTlb);
6308	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesLoadingTlb);
6309	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesLoadingTlbConsiderCsLim);
6310
6311	/* Natural page crossing: */
6312	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesAcrossPageLoadingTlb);
6313	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesAcrossPageLoadingTlb);
6314	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesAcrossPageLoadingTlbConsiderCsLim);
6315
6316	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesOnNextPageLoadingTlb);
6317	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNextPageLoadingTlb);
6318	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNextPageLoadingTlbConsiderCsLim);
6319
6320	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesOnNewPageLoadingTlb);
6321	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNewPageLoadingTlb);
6322	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNewPageLoadingTlbConsiderCsLim);
6323
6324	bool iemThreadedCompileEmitIrqCheckBefore(PVMCPUCC pVCpu, PIEMTB pTb);
6325	bool iemThreadedCompileBeginEmitCallsComplications(PVMCPUCC pVCpu, PIEMTB pTb);
6326
6327	/* Native recompiler public bits: */
6328	DECLHIDDEN(PIEMTB) iemNativeRecompile(PVMCPUCC pVCpu, PIEMTB pTb) RT_NOEXCEPT;
6329	DECLHIDDEN(void) iemNativeDisassembleTb(PCIEMTB pTb, PCDBGFINFOHLP pHlp) RT_NOEXCEPT;
6330	int iemExecMemAllocatorInit(PVMCPU pVCpu, uint64_t cbMax, uint64_t cbInitial, uint32_t cbChunk) RT_NOEXCEPT;
6331	DECLHIDDEN(void ) iemExecMemAllocatorAlloc(PVMCPU pVCpu, uint32_t cbReq, PIEMTB pTb, void *ppvExec) RT_NOEXCEPT;
6332	DECLHIDDEN(void) iemExecMemAllocatorReadyForUse(PVMCPUCC pVCpu, void *pv, size_t cb) RT_NOEXCEPT;
6333	void iemExecMemAllocatorFree(PVMCPU pVCpu, void *pv, size_t cb) RT_NOEXCEPT;
6334	DECLASM(DECL_NO_RETURN(void)) iemNativeTbLongJmp(void *pvFramePointer, int rc) RT_NOEXCEPT;
6335
6336	#endif /* !RT_IN_ASSEMBLER - ASM-NOINC-END */
6337
6338
6339	/** @} */
6340
6341	RT_C_DECLS_END
6342
6343	/* ASM-INC: %include "IEMInternalStruct.mac" */
6344
6345	#endif /* !VMM_INCLUDED_SRC_include_IEMInternal_h */
6346

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h@ 105076

Download in other formats: