IEMInternal.h@ 105184

Last change on this file since 105184 was 105184, checked in by vboxsync, 5 months ago
VMM/IEM: Implement vaddps instruction emulation, bugref:9898
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1	/* $Id: IEMInternal.h 105184 2024-07-08 12:27:15Z vboxsync $ */
2	/** @file
3	* IEM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2011-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_IEMInternal_h
29	#define VMM_INCLUDED_SRC_include_IEMInternal_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#ifndef RT_IN_ASSEMBLER
35	# include <VBox/vmm/cpum.h>
36	# include <VBox/vmm/iem.h>
37	# include <VBox/vmm/pgm.h>
38	# include <VBox/vmm/stam.h>
39	# include <VBox/param.h>
40
41	# include <iprt/setjmp-without-sigmask.h>
42	# include <iprt/list.h>
43	#endif /* !RT_IN_ASSEMBLER */
44
45
46	RT_C_DECLS_BEGIN
47
48
49	/** @defgroup grp_iem_int Internals
50	* @ingroup grp_iem
51	* @internal
52	* @{
53	*/
54
55	/* Make doxygen happy w/o overcomplicating the #if checks. */
56	#ifdef DOXYGEN_RUNNING
57	# define IEM_WITH_THROW_CATCH
58	# define VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
59	#endif
60
61	/** For expanding symbol in slickedit and other products tagging and
62	* crossreferencing IEM symbols. */
63	#ifndef IEM_STATIC
64	# define IEM_STATIC static
65	#endif
66
67	/** @def IEM_WITH_SETJMP
68	* Enables alternative status code handling using setjmps.
69	*
70	* This adds a bit of expense via the setjmp() call since it saves all the
71	* non-volatile registers. However, it eliminates return code checks and allows
72	* for more optimal return value passing (return regs instead of stack buffer).
73	*/
74	#if defined(DOXYGEN_RUNNING) \|\| defined(RT_OS_WINDOWS) \|\| 1
75	# define IEM_WITH_SETJMP
76	#endif
77
78	/** @def IEM_WITH_THROW_CATCH
79	* Enables using C++ throw/catch as an alternative to setjmp/longjmp in user
80	* mode code when IEM_WITH_SETJMP is in effect.
81	*
82	* With GCC 11.3.1 and code TLB on linux, using throw/catch instead of
83	* setjmp/long resulted in bs2-test-1 running 3.00% faster and all but on test
84	* result value improving by more than 1%. (Best out of three.)
85	*
86	* With Visual C++ 2019 and code TLB on windows, using throw/catch instead of
87	* setjmp/long resulted in bs2-test-1 running 3.68% faster and all but some of
88	* the MMIO and CPUID tests ran noticeably faster. Variation is greater than on
89	* Linux, but it should be quite a bit faster for normal code.
90	*/
91	#if defined(__cplusplus) && defined(IEM_WITH_SETJMP) && defined(IN_RING3) && (defined(__GNUC__) \|\| defined(_MSC_VER)) /* ASM-NOINC-START */
92	# define IEM_WITH_THROW_CATCH
93	#endif /ASM-NOINC-END/
94
95	/** @def IEMNATIVE_WITH_DELAYED_PC_UPDATING
96	* Enables the delayed PC updating optimization (see @bugref{10373}).
97	*/
98	#if defined(DOXYGEN_RUNNING) \|\| 1
99	# define IEMNATIVE_WITH_DELAYED_PC_UPDATING
100	#endif
101
102	/** Enables the SIMD register allocator @bugref{10614}. */
103	#if defined(DOXYGEN_RUNNING) \|\| 1
104	# define IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
105	#endif
106	/** Enables access to even callee saved registers. */
107	//# define IEMNATIVE_WITH_SIMD_REG_ACCESS_ALL_REGISTERS
108
109	#if defined(DOXYGEN_RUNNING) \|\| 1
110	/** @def IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
111	* Delay the writeback or dirty registers as long as possible. */
112	# define IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
113	#endif
114
115	/** @def IEM_WITH_TLB_STATISTICS
116	* Enables all TLB statistics. */
117	#if defined(VBOX_WITH_STATISTICS) \|\| defined(DOXYGEN_RUNNING)
118	# define IEM_WITH_TLB_STATISTICS
119	#endif
120
121	/** @def VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
122	* Enables a quicker alternative to throw/longjmp for IEM_DO_LONGJMP when
123	* executing native translation blocks.
124	*
125	* This exploits the fact that we save all non-volatile registers in the TB
126	* prologue and thus just need to do the same as the TB epilogue to get the
127	* effect of a longjmp/throw. Since MSC marks XMM6 thru XMM15 as
128	* non-volatile (and does something even more crazy for ARM), this probably
129	* won't work reliably on Windows. */
130	#ifdef RT_ARCH_ARM64
131	# ifndef RT_OS_WINDOWS
132	# define VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
133	# endif
134	#endif
135	/* ASM-NOINC-START */
136	#ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
137	# if !defined(IN_RING3) \
138	\|\| !defined(VBOX_WITH_IEM_RECOMPILER) \
139	\|\| !defined(VBOX_WITH_IEM_NATIVE_RECOMPILER)
140	# undef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
141	# elif defined(RT_OS_WINDOWS)
142	# pragma message("VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP is not safe to use on windows")
143	# endif
144	#endif
145
146
147	/** @def IEM_DO_LONGJMP
148	*
149	* Wrapper around longjmp / throw.
150	*
151	* @param a_pVCpu The CPU handle.
152	* @param a_rc The status code jump back with / throw.
153	*/
154	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
155	# ifdef IEM_WITH_THROW_CATCH
156	# ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
157	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) do { \
158	if ((a_pVCpu)->iem.s.pvTbFramePointerR3) \
159	iemNativeTbLongJmp((a_pVCpu)->iem.s.pvTbFramePointerR3, (a_rc)); \
160	throw int(a_rc); \
161	} while (0)
162	# else
163	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) throw int(a_rc)
164	# endif
165	# else
166	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) longjmp(*(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf), (a_rc))
167	# endif
168	#endif
169
170	/** For use with IEM function that may do a longjmp (when enabled).
171	*
172	* Visual C++ has trouble longjmp'ing from/over functions with the noexcept
173	* attribute. So, we indicate that function that may be part of a longjmp may
174	* throw "exceptions" and that the compiler should definitely not generate and
175	* std::terminate calling unwind code.
176	*
177	* Here is one example of this ending in std::terminate:
178	* @code{.txt}
179	00 00000041`cadfda10 00007ffc`5d5a1f9f ucrtbase!abort+0x4e
180	01 00000041`cadfda40 00007ffc`57af229a ucrtbase!terminate+0x1f
181	02 00000041`cadfda70 00007ffb`eec91030 VCRUNTIME140!__std_terminate+0xa [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\ehhelpers.cpp @ 192]
182	03 00000041`cadfdaa0 00007ffb`eec92c6d VCRUNTIME140_1!_CallSettingFrame+0x20 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\handlers.asm @ 50]
183	04 00000041`cadfdad0 00007ffb`eec93ae5 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToState+0x241 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 1085]
184	05 00000041`cadfdc00 00007ffb`eec92258 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToEmptyState+0x2d [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 218]
185	06 00000041`cadfdc30 00007ffb`eec940e9 VCRUNTIME140_1!__InternalCxxFrameHandler<__FrameHandler4>+0x194 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 304]
186	07 00000041`cadfdcd0 00007ffc`5f9f249f VCRUNTIME140_1!__CxxFrameHandler4+0xa9 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 290]
187	08 00000041`cadfdd40 00007ffc`5f980939 ntdll!RtlpExecuteHandlerForUnwind+0xf
188	09 00000041`cadfdd70 00007ffc`5f9a0edd ntdll!RtlUnwindEx+0x339
189	0a 00000041`cadfe490 00007ffc`57aff976 ntdll!RtlUnwind+0xcd
190	0b 00000041`cadfea00 00007ffb`e1b5de01 VCRUNTIME140!__longjmp_internal+0xe6 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\longjmp.asm @ 140]
191	0c (Inline Function) --------`-------- VBoxVMM!iemOpcodeGetNextU8SlowJmp+0x95 [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 1155]
192	0d 00000041`cadfea50 00007ffb`e1b60f6b VBoxVMM!iemOpcodeGetNextU8Jmp+0xc1 [L:\vbox-intern\src\VBox\VMM\include\IEMInline.h @ 402]
193	0e 00000041`cadfea90 00007ffb`e1cc6201 VBoxVMM!IEMExecForExits+0xdb [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 10185]
194	0f 00000041`cadfec70 00007ffb`e1d0df8d VBoxVMM!EMHistoryExec+0x4f1 [L:\vbox-intern\src\VBox\VMM\VMMAll\EMAll.cpp @ 452]
195	10 00000041`cadfed60 00007ffb`e1d0d4c0 VBoxVMM!nemR3WinHandleExitCpuId+0x79d [L:\vbox-intern\src\VBox\VMM\VMMAll\NEMAllNativeTemplate-win.cpp.h @ 1829] @encode
196	@endcode
197	*
198	* @see https://developercommunity.visualstudio.com/t/fragile-behavior-of-longjmp-called-from-noexcept-f/1532859
199	*/
200	#if defined(IEM_WITH_SETJMP) && (defined(_MSC_VER) \|\| defined(IEM_WITH_THROW_CATCH))
201	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT_EX(false)
202	#else
203	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT
204	#endif
205	/* ASM-NOINC-END */
206
207	#define IEM_IMPLEMENTS_TASKSWITCH
208
209	/** @def IEM_WITH_3DNOW
210	* Includes the 3DNow decoding. */
211	#if !defined(IEM_WITH_3DNOW) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
212	# ifndef IEM_WITHOUT_3DNOW
213	# define IEM_WITH_3DNOW
214	# endif
215	#endif
216
217	/** @def IEM_WITH_THREE_0F_38
218	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
219	#if !defined(IEM_WITH_THREE_0F_38) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
220	# ifndef IEM_WITHOUT_THREE_0F_38
221	# define IEM_WITH_THREE_0F_38
222	# endif
223	#endif
224
225	/** @def IEM_WITH_THREE_0F_3A
226	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
227	#if !defined(IEM_WITH_THREE_0F_3A) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
228	# ifndef IEM_WITHOUT_THREE_0F_3A
229	# define IEM_WITH_THREE_0F_3A
230	# endif
231	#endif
232
233	/** @def IEM_WITH_VEX
234	* Includes the VEX decoding. */
235	#if !defined(IEM_WITH_VEX) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
236	# ifndef IEM_WITHOUT_VEX
237	# define IEM_WITH_VEX
238	# endif
239	#endif
240
241	/** @def IEM_CFG_TARGET_CPU
242	* The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
243	*
244	* By default we allow this to be configured by the user via the
245	* CPUM/GuestCpuName config string, but this comes at a slight cost during
246	* decoding. So, for applications of this code where there is no need to
247	* be dynamic wrt target CPU, just modify this define.
248	*/
249	#if !defined(IEM_CFG_TARGET_CPU) \|\| defined(DOXYGEN_RUNNING)
250	# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
251	#endif
252
253	//#define IEM_WITH_CODE_TLB // - work in progress
254	//#define IEM_WITH_DATA_TLB // - work in progress
255
256
257	/** @def IEM_USE_UNALIGNED_DATA_ACCESS
258	* Use unaligned accesses instead of elaborate byte assembly. */
259	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86) \|\| defined(DOXYGEN_RUNNING) /ASM-NOINC/
260	# define IEM_USE_UNALIGNED_DATA_ACCESS
261	#endif /ASM-NOINC/
262
263	//#define IEM_LOG_MEMORY_WRITES
264
265
266
267	#ifndef RT_IN_ASSEMBLER /* ASM-NOINC-START - the rest of the file */
268
269	# if !defined(IEM_WITHOUT_INSTRUCTION_STATS) && !defined(DOXYGEN_RUNNING)
270	/** Instruction statistics. */
271	typedef struct IEMINSTRSTATS
272	{
273	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
274	# include "IEMInstructionStatisticsTmpl.h"
275	# undef IEM_DO_INSTR_STAT
276	} IEMINSTRSTATS;
277	#else
278	struct IEMINSTRSTATS;
279	typedef struct IEMINSTRSTATS IEMINSTRSTATS;
280	#endif
281	/** Pointer to IEM instruction statistics. */
282	typedef IEMINSTRSTATS *PIEMINSTRSTATS;
283
284
285	/** @name IEMTARGETCPU_EFL_BEHAVIOR_XXX - IEMCPU::aidxTargetCpuEflFlavour
286	* @{ */
287	#define IEMTARGETCPU_EFL_BEHAVIOR_NATIVE 0 /*< Native x86 EFLAGS result; Intel EFLAGS when on non-x86 hosts. /
288	#define IEMTARGETCPU_EFL_BEHAVIOR_INTEL 1 /*< Intel EFLAGS result. /
289	#define IEMTARGETCPU_EFL_BEHAVIOR_AMD 2 /*< AMD EFLAGS result /
290	#define IEMTARGETCPU_EFL_BEHAVIOR_RESERVED 3 /*< Reserved/dummy entry slot that's the same as 0. /
291	#define IEMTARGETCPU_EFL_BEHAVIOR_MASK 3 /*< For masking the index before use. /
292	/** Selects the right variant from a_aArray.
293	* pVCpu is implicit in the caller context. */
294	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT(a_aArray) \
295	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[1] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
296	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for when no native worker can
297	* be used because the host CPU does not support the operation. */
298	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_NON_NATIVE(a_aArray) \
299	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
300	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for a two dimentional
301	* array paralleling IEMCPU::aidxTargetCpuEflFlavour and a single bit index
302	* into the two.
303	* @sa IEM_SELECT_NATIVE_OR_FALLBACK */
304	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
305	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
306	(a_aaArray[a_fNative][pVCpu->iem.s.aidxTargetCpuEflFlavour[a_fNative] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
307	#else
308	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
309	(a_aaArray[0][pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
310	#endif
311	/** @} */
312
313	/**
314	* Picks @a a_pfnNative or @a a_pfnFallback according to the host CPU feature
315	* indicator given by @a a_fCpumFeatureMember (CPUMFEATURES member).
316	*
317	* On non-x86 hosts, this will shortcut to the fallback w/o checking the
318	* indicator.
319	*
320	* @sa IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX
321	*/
322	#if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
323	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) \
324	(g_CpumHostFeatures.s.a_fCpumFeatureMember ? a_pfnNative : a_pfnFallback)
325	#else
326	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) (a_pfnFallback)
327	#endif
328
329
330	/**
331	* Branch types.
332	*/
333	typedef enum IEMBRANCH
334	{
335	IEMBRANCH_JUMP = 1,
336	IEMBRANCH_CALL,
337	IEMBRANCH_TRAP,
338	IEMBRANCH_SOFTWARE_INT,
339	IEMBRANCH_HARDWARE_INT
340	} IEMBRANCH;
341	AssertCompileSize(IEMBRANCH, 4);
342
343
344	/**
345	* INT instruction types.
346	*/
347	typedef enum IEMINT
348	{
349	/** INT n instruction (opcode 0xcd imm). */
350	IEMINT_INTN = 0,
351	/** Single byte INT3 instruction (opcode 0xcc). */
352	IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
353	/** Single byte INTO instruction (opcode 0xce). */
354	IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
355	/** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
356	IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
357	} IEMINT;
358	AssertCompileSize(IEMINT, 4);
359
360
361	/**
362	* A FPU result.
363	*/
364	typedef struct IEMFPURESULT
365	{
366	/** The output value. */
367	RTFLOAT80U r80Result;
368	/** The output status. */
369	uint16_t FSW;
370	} IEMFPURESULT;
371	AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
372	/** Pointer to a FPU result. */
373	typedef IEMFPURESULT *PIEMFPURESULT;
374	/** Pointer to a const FPU result. */
375	typedef IEMFPURESULT const *PCIEMFPURESULT;
376
377
378	/**
379	* A FPU result consisting of two output values and FSW.
380	*/
381	typedef struct IEMFPURESULTTWO
382	{
383	/** The first output value. */
384	RTFLOAT80U r80Result1;
385	/** The output status. */
386	uint16_t FSW;
387	/** The second output value. */
388	RTFLOAT80U r80Result2;
389	} IEMFPURESULTTWO;
390	AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
391	AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
392	/** Pointer to a FPU result consisting of two output values and FSW. */
393	typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
394	/** Pointer to a const FPU result consisting of two output values and FSW. */
395	typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
396
397
398	/**
399	* IEM TLB entry.
400	*
401	* Lookup assembly:
402	* @code{.asm}
403	; Calculate tag.
404	mov rax, [VA]
405	shl rax, 16
406	shr rax, 16 + X86_PAGE_SHIFT
407	or rax, [uTlbRevision]
408
409	; Do indexing.
410	movzx ecx, al
411	lea rcx, [pTlbEntries + rcx]
412
413	; Check tag.
414	cmp [rcx + IEMTLBENTRY.uTag], rax
415	jne .TlbMiss
416
417	; Check access.
418	mov rax, ACCESS_FLAGS \| MAPPING_R3_NOT_VALID \| 0xffffff00
419	and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
420	cmp rax, [uTlbPhysRev]
421	jne .TlbMiss
422
423	; Calc address and we're done.
424	mov eax, X86_PAGE_OFFSET_MASK
425	and eax, [VA]
426	or rax, [rcx + IEMTLBENTRY.pMappingR3]
427	%ifdef VBOX_WITH_STATISTICS
428	inc qword [cTlbHits]
429	%endif
430	jmp .Done
431
432	.TlbMiss:
433	mov r8d, ACCESS_FLAGS
434	mov rdx, [VA]
435	mov rcx, [pVCpu]
436	call iemTlbTypeMiss
437	.Done:
438
439	@endcode
440	*
441	*/
442	typedef struct IEMTLBENTRY
443	{
444	/** The TLB entry tag.
445	* Bits 35 thru 0 are made up of the virtual address shifted right 12 bits, this
446	* is ASSUMING a virtual address width of 48 bits.
447	*
448	* Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
449	*
450	* The TLB lookup code uses the current TLB revision, which won't ever be zero,
451	* enabling an extremely cheap TLB invalidation most of the time. When the TLB
452	* revision wraps around though, the tags needs to be zeroed.
453	*
454	* @note Try use SHRD instruction? After seeing
455	* https://gmplib.org/~tege/x86-timing.pdf, maybe not.
456	*
457	* @todo This will need to be reorganized for 57-bit wide virtual address and
458	* PCID (currently 12 bits) and ASID (currently 6 bits) support. We'll
459	* have to move the TLB entry versioning entirely to the
460	* fFlagsAndPhysRev member then, 57 bit wide VAs means we'll only have
461	* 19 bits left (64 - 57 + 12 = 19) and they'll almost entire be
462	* consumed by PCID and ASID (12 + 6 = 18).
463	*/
464	uint64_t uTag;
465	/** Access flags and physical TLB revision.
466	*
467	* - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
468	* - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
469	* - Bit 2 - page tables - not user (complemented X86_PTE_US).
470	* - Bit 3 - pgm phys/virt - not directly writable.
471	* - Bit 4 - pgm phys page - not directly readable.
472	* - Bit 5 - page tables - not accessed (complemented X86_PTE_A).
473	* - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
474	* - Bit 7 - tlb entry - pMappingR3 member not valid.
475	* - Bits 63 thru 8 are used for the physical TLB revision number.
476	*
477	* We're using complemented bit meanings here because it makes it easy to check
478	* whether special action is required. For instance a user mode write access
479	* would do a "TEST fFlags, (X86_PTE_RW \| X86_PTE_US \| X86_PTE_D)" and a
480	* non-zero result would mean special handling needed because either it wasn't
481	* writable, or it wasn't user, or the page wasn't dirty. A user mode read
482	* access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
483	* need to check any PTE flag.
484	*/
485	uint64_t fFlagsAndPhysRev;
486	/** The guest physical page address. */
487	uint64_t GCPhys;
488	/** Pointer to the ring-3 mapping. */
489	R3PTRTYPE(uint8_t *) pbMappingR3;
490	#if HC_ARCH_BITS == 32
491	uint32_t u32Padding1;
492	#endif
493	} IEMTLBENTRY;
494	AssertCompileSize(IEMTLBENTRY, 32);
495	/** Pointer to an IEM TLB entry. */
496	typedef IEMTLBENTRY *PIEMTLBENTRY;
497	/** Pointer to a const IEM TLB entry. */
498	typedef IEMTLBENTRY const *PCIEMTLBENTRY;
499
500	/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
501	* @{ */
502	#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /*< Page tables: Not executable. /
503	#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /*< Page tables: Not writable. /
504	#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /*< Page tables: Not user accessible (supervisor only). /
505	#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /*< Phys page: Not writable (access handler, ROM, whatever). /
506	#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /*< Phys page: Not readable (MMIO / access handler, ROM) /
507	#define IEMTLBE_F_PT_NO_ACCESSED RT_BIT_64(5) /*< Phys tables: Not accessed (need to be marked accessed). /
508	#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /*< Page tables: Not dirty (needs to be made dirty on write). /
509	#define IEMTLBE_F_PT_LARGE_PAGE RT_BIT_64(7) /*< Page tables: Large 2 or 4 MiB page (for flushing). /
510	#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(8) /*< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. /
511	#define IEMTLBE_F_PG_UNASSIGNED RT_BIT_64(9) /*< Phys page: Unassigned memory (not RAM, ROM, MMIO2 or MMIO). /
512	#define IEMTLBE_F_PG_CODE_PAGE RT_BIT_64(10) /*< Phys page: Code page. /
513	#define IEMTLBE_F_PHYS_REV UINT64_C(0xfffffffffffff800) /*< Physical revision mask. @sa IEMTLB_PHYS_REV_INCR /
514	/** @} */
515	AssertCompile(PGMIEMGCPHYS2PTR_F_NO_WRITE == IEMTLBE_F_PG_NO_WRITE);
516	AssertCompile(PGMIEMGCPHYS2PTR_F_NO_READ == IEMTLBE_F_PG_NO_READ);
517	AssertCompile(PGMIEMGCPHYS2PTR_F_NO_MAPPINGR3 == IEMTLBE_F_NO_MAPPINGR3);
518	AssertCompile(PGMIEMGCPHYS2PTR_F_UNASSIGNED == IEMTLBE_F_PG_UNASSIGNED);
519	AssertCompile(PGMIEMGCPHYS2PTR_F_CODE_PAGE == IEMTLBE_F_PG_CODE_PAGE);
520	AssertCompile(PGM_WALKINFO_BIG_PAGE == IEMTLBE_F_PT_LARGE_PAGE);
521	/** The bits set by PGMPhysIemGCPhys2PtrNoLock. */
522	#define IEMTLBE_GCPHYS2PTR_MASK ( PGMIEMGCPHYS2PTR_F_NO_WRITE \
523	\| PGMIEMGCPHYS2PTR_F_NO_READ \
524	\| PGMIEMGCPHYS2PTR_F_NO_MAPPINGR3 \
525	\| PGMIEMGCPHYS2PTR_F_UNASSIGNED \
526	\| PGMIEMGCPHYS2PTR_F_CODE_PAGE \
527	\| IEMTLBE_F_PHYS_REV )
528
529	/** The TLB size (power of two).
530	* We initially chose 256 because that way we can obtain the result directly
531	* from a 8-bit register without an additional AND instruction.
532	* See also @bugref{10687}. */
533	#if defined(RT_ARCH_AMD64)
534	# define IEMTLB_ENTRY_COUNT 256
535	# define IEMTLB_ENTRY_COUNT_AS_POWER_OF_TWO 8
536	#else
537	# define IEMTLB_ENTRY_COUNT 8192
538	# define IEMTLB_ENTRY_COUNT_AS_POWER_OF_TWO 13
539	#endif
540	AssertCompile(RT_BIT_32(IEMTLB_ENTRY_COUNT_AS_POWER_OF_TWO) == IEMTLB_ENTRY_COUNT);
541
542	/**
543	* An IEM TLB.
544	*
545	* We've got two of these, one for data and one for instructions.
546	*/
547	typedef struct IEMTLB
548	{
549	/** The non-global TLB revision.
550	* This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
551	* by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
552	* the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
553	* (The revision zero indicates an invalid TLB entry.)
554	*
555	* The initial value is choosen to cause an early wraparound. */
556	uint64_t uTlbRevision;
557	/** The TLB physical address revision - shadow of PGM variable.
558	*
559	* This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
560	* incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
561	* a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
562	* as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
563	*
564	* The initial value is choosen to cause an early wraparound.
565	*
566	* @note This is placed between the two TLB revisions because we
567	* load it in pair with one or the other on arm64. */
568	uint64_t volatile uTlbPhysRev;
569	/** The global TLB revision.
570	* Same as uTlbRevision, but only increased for global flushes. */
571	uint64_t uTlbRevisionGlobal;
572
573	/* Statistics: */
574
575	/** TLB hits in IEMAll.cpp code (IEM_WITH_TLB_STATISTICS only; both).
576	* @note For the data TLB this is only used in iemMemMap and and for direct (i.e.
577	* not via safe read/write path) calls to iemMemMapJmp. */
578	uint64_t cTlbCoreHits;
579	/** Safe read/write TLB hits in iemMemMapJmp (IEM_WITH_TLB_STATISTICS
580	* only; data tlb only). */
581	uint64_t cTlbSafeHits;
582	/** TLB hits in IEMAllMemRWTmplInline.cpp.h (data + IEM_WITH_TLB_STATISTICS only). */
583	uint64_t cTlbInlineCodeHits;
584
585	/** TLB misses in IEMAll.cpp code (both).
586	* @note For the data TLB this is only used in iemMemMap and for direct (i.e.
587	* not via safe read/write path) calls to iemMemMapJmp. So,
588	* for the data TLB this more like 'other misses', while for the code
589	* TLB is all misses. */
590	uint64_t cTlbCoreMisses;
591	/** Subset of cTlbCoreMisses that results in PTE.G=1 loads (odd entries). */
592	uint64_t cTlbCoreGlobalLoads;
593	/** Safe read/write TLB misses in iemMemMapJmp (so data only). */
594	uint64_t cTlbSafeMisses;
595	/** Subset of cTlbSafeMisses that results in PTE.G=1 loads (odd entries). */
596	uint64_t cTlbSafeGlobalLoads;
597	/** Safe read path taken (data only). */
598	uint64_t cTlbSafeReadPath;
599	/** Safe write path taken (data only). */
600	uint64_t cTlbSafeWritePath;
601
602	/** @name Details for native code TLB misses.
603	* @note These counts are included in the above counters (cTlbSafeReadPath,
604	* cTlbSafeWritePath, cTlbInlineCodeHits).
605	* @{ */
606	/** TLB misses in native code due to tag mismatch. */
607	STAMCOUNTER cTlbNativeMissTag;
608	/** TLB misses in native code due to flags or physical revision mismatch. */
609	STAMCOUNTER cTlbNativeMissFlagsAndPhysRev;
610	/** TLB misses in native code due to misaligned access. */
611	STAMCOUNTER cTlbNativeMissAlignment;
612	/** TLB misses in native code due to cross page access. */
613	uint32_t cTlbNativeMissCrossPage;
614	/** TLB misses in native code due to non-canonical address. */
615	uint32_t cTlbNativeMissNonCanonical;
616	/** @} */
617
618	/** Slow read path (code only). */
619	uint32_t cTlbSlowCodeReadPath;
620
621	/** Regular TLB flush count. */
622	uint32_t cTlsFlushes;
623	/** Global TLB flush count. */
624	uint32_t cTlsGlobalFlushes;
625	/** Revision rollovers. */
626	uint32_t cTlbRevisionRollovers;
627	/** Physical revision flushes. */
628	uint32_t cTlbPhysRevFlushes;
629	/** Physical revision rollovers. */
630	uint32_t cTlbPhysRevRollovers;
631
632	uint32_t au32Padding[10];
633
634	/** The TLB entries.
635	* Even entries are for PTE.G=0 and uses uTlbRevision.
636	* Odd entries are for PTE.G=1 and uses uTlbRevisionGlobal. */
637	IEMTLBENTRY aEntries[IEMTLB_ENTRY_COUNT * 2];
638	} IEMTLB;
639	AssertCompileSizeAlignment(IEMTLB, 64);
640	/** IEMTLB::uTlbRevision increment. */
641	#define IEMTLB_REVISION_INCR RT_BIT_64(36)
642	/** IEMTLB::uTlbRevision mask. */
643	#define IEMTLB_REVISION_MASK (~(RT_BIT_64(36) - 1))
644	/** IEMTLB::uTlbPhysRev increment.
645	* @sa IEMTLBE_F_PHYS_REV */
646	#define IEMTLB_PHYS_REV_INCR RT_BIT_64(11)
647	AssertCompile(IEMTLBE_F_PHYS_REV == ~(IEMTLB_PHYS_REV_INCR - 1U));
648
649	/**
650	* Calculates the TLB tag for a virtual address but without TLB revision.
651	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
652	* @param a_GCPtr The virtual address. Must be RTGCPTR or same size or
653	* the clearing of the top 16 bits won't work (if 32-bit
654	* we'll end up with mostly zeros).
655	*/
656	#define IEMTLB_CALC_TAG_NO_REV(a_GCPtr) ( (((a_GCPtr) << 16) >> (GUEST_PAGE_SHIFT + 16)) )
657	/**
658	* Converts a TLB tag value into a even TLB index.
659	* @returns Index into IEMTLB::aEntries.
660	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
661	*/
662	#if IEMTLB_ENTRY_COUNT == 256
663	# define IEMTLB_TAG_TO_EVEN_INDEX(a_uTag) ( (uint8_t)(a_uTag) * 2U )
664	#else
665	# define IEMTLB_TAG_TO_EVEN_INDEX(a_uTag) ( ((a_uTag) & (IEMTLB_ENTRY_COUNT - 1U)) * 2U )
666	AssertCompile(RT_IS_POWER_OF_TWO(IEMTLB_ENTRY_COUNT));
667	#endif
668	/**
669	* Converts a TLB tag value into an even TLB index.
670	* @returns Pointer into IEMTLB::aEntries corresponding to .
671	* @param a_pTlb The TLB.
672	* @param a_uTag Value returned by IEMTLB_CALC_TAG or
673	* IEMTLB_CALC_TAG_NO_REV.
674	*/
675	#define IEMTLB_TAG_TO_EVEN_ENTRY(a_pTlb, a_uTag) ( &(a_pTlb)->aEntries[IEMTLB_TAG_TO_EVEN_INDEX(a_uTag)] )
676
677
678	/** @name IEM_MC_F_XXX - MC block flags/clues.
679	* @todo Merge with IEM_CIMPL_F_XXX
680	* @{ */
681	#define IEM_MC_F_ONLY_8086 RT_BIT_32(0)
682	#define IEM_MC_F_MIN_186 RT_BIT_32(1)
683	#define IEM_MC_F_MIN_286 RT_BIT_32(2)
684	#define IEM_MC_F_NOT_286_OR_OLDER IEM_MC_F_MIN_386
685	#define IEM_MC_F_MIN_386 RT_BIT_32(3)
686	#define IEM_MC_F_MIN_486 RT_BIT_32(4)
687	#define IEM_MC_F_MIN_PENTIUM RT_BIT_32(5)
688	#define IEM_MC_F_MIN_PENTIUM_II IEM_MC_F_MIN_PENTIUM
689	#define IEM_MC_F_MIN_CORE IEM_MC_F_MIN_PENTIUM
690	#define IEM_MC_F_64BIT RT_BIT_32(6)
691	#define IEM_MC_F_NOT_64BIT RT_BIT_32(7)
692	/** This is set by IEMAllN8vePython.py to indicate a variation without the
693	* flags-clearing-and-checking, when there is also a variation with that.
694	* @note Do not use this manully, it's only for python and for testing in
695	* the native recompiler! */
696	#define IEM_MC_F_WITHOUT_FLAGS RT_BIT_32(8)
697	/** @} */
698
699	/** @name IEM_CIMPL_F_XXX - State change clues for CIMPL calls.
700	*
701	* These clues are mainly for the recompiler, so that it can emit correct code.
702	*
703	* They are processed by the python script and which also automatically
704	* calculates flags for MC blocks based on the statements, extending the use of
705	* these flags to describe MC block behavior to the recompiler core. The python
706	* script pass the flags to the IEM_MC2_END_EMIT_CALLS macro, but mainly for
707	* error checking purposes. The script emits the necessary fEndTb = true and
708	* similar statements as this reduces compile time a tiny bit.
709	*
710	* @{ */
711	/** Flag set if direct branch, clear if absolute or indirect. */
712	#define IEM_CIMPL_F_BRANCH_DIRECT RT_BIT_32(0)
713	/** Flag set if indirect branch, clear if direct or relative.
714	* This is also used for all system control transfers (SYSCALL, SYSRET, INT, ++)
715	* as well as for return instructions (RET, IRET, RETF). */
716	#define IEM_CIMPL_F_BRANCH_INDIRECT RT_BIT_32(1)
717	/** Flag set if relative branch, clear if absolute or indirect. */
718	#define IEM_CIMPL_F_BRANCH_RELATIVE RT_BIT_32(2)
719	/** Flag set if conditional branch, clear if unconditional. */
720	#define IEM_CIMPL_F_BRANCH_CONDITIONAL RT_BIT_32(3)
721	/** Flag set if it's a far branch (changes CS). */
722	#define IEM_CIMPL_F_BRANCH_FAR RT_BIT_32(4)
723	/** Convenience: Testing any kind of branch. */
724	#define IEM_CIMPL_F_BRANCH_ANY (IEM_CIMPL_F_BRANCH_DIRECT \| IEM_CIMPL_F_BRANCH_INDIRECT \| IEM_CIMPL_F_BRANCH_RELATIVE)
725
726	/** Execution flags may change (IEMCPU::fExec). */
727	#define IEM_CIMPL_F_MODE RT_BIT_32(5)
728	/** May change significant portions of RFLAGS. */
729	#define IEM_CIMPL_F_RFLAGS RT_BIT_32(6)
730	/** May change the status bits (X86_EFL_STATUS_BITS) in RFLAGS. */
731	#define IEM_CIMPL_F_STATUS_FLAGS RT_BIT_32(7)
732	/** May trigger interrupt shadowing. */
733	#define IEM_CIMPL_F_INHIBIT_SHADOW RT_BIT_32(8)
734	/** May enable interrupts, so recheck IRQ immediately afterwards executing
735	* the instruction. */
736	#define IEM_CIMPL_F_CHECK_IRQ_AFTER RT_BIT_32(9)
737	/** May disable interrupts, so recheck IRQ immediately before executing the
738	* instruction. */
739	#define IEM_CIMPL_F_CHECK_IRQ_BEFORE RT_BIT_32(10)
740	/** Convenience: Check for IRQ both before and after an instruction. */
741	#define IEM_CIMPL_F_CHECK_IRQ_BEFORE_AND_AFTER (IEM_CIMPL_F_CHECK_IRQ_BEFORE \| IEM_CIMPL_F_CHECK_IRQ_AFTER)
742	/** May trigger a VM exit (treated like IEM_CIMPL_F_MODE atm). */
743	#define IEM_CIMPL_F_VMEXIT RT_BIT_32(11)
744	/** May modify FPU state.
745	* @todo Not sure if this is useful yet. */
746	#define IEM_CIMPL_F_FPU RT_BIT_32(12)
747	/** REP prefixed instruction which may yield before updating PC.
748	* @todo Not sure if this is useful, REP functions now return non-zero
749	* status if they don't update the PC. */
750	#define IEM_CIMPL_F_REP RT_BIT_32(13)
751	/** I/O instruction.
752	* @todo Not sure if this is useful yet. */
753	#define IEM_CIMPL_F_IO RT_BIT_32(14)
754	/** Force end of TB after the instruction. */
755	#define IEM_CIMPL_F_END_TB RT_BIT_32(15)
756	/** Flag set if a branch may also modify the stack (push/pop return address). */
757	#define IEM_CIMPL_F_BRANCH_STACK RT_BIT_32(16)
758	/** Flag set if a branch may also modify the stack (push/pop return address)
759	* and switch it (load/restore SS:RSP). */
760	#define IEM_CIMPL_F_BRANCH_STACK_FAR RT_BIT_32(17)
761	/** Convenience: Raise exception (technically unnecessary, since it shouldn't return VINF_SUCCESS). */
762	#define IEM_CIMPL_F_XCPT \
763	(IEM_CIMPL_F_BRANCH_INDIRECT \| IEM_CIMPL_F_BRANCH_FAR \| IEM_CIMPL_F_BRANCH_STACK_FAR \
764	\| IEM_CIMPL_F_MODE \| IEM_CIMPL_F_RFLAGS \| IEM_CIMPL_F_VMEXIT)
765
766	/** The block calls a C-implementation instruction function with two implicit arguments.
767	* Mutually exclusive with IEM_CIMPL_F_CALLS_AIMPL and
768	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
769	* @note The python scripts will add this if missing. */
770	#define IEM_CIMPL_F_CALLS_CIMPL RT_BIT_32(18)
771	/** The block calls an ASM-implementation instruction function.
772	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL and
773	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
774	* @note The python scripts will add this if missing. */
775	#define IEM_CIMPL_F_CALLS_AIMPL RT_BIT_32(19)
776	/** The block calls an ASM-implementation instruction function with an implicit
777	* X86FXSTATE pointer argument.
778	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL, IEM_CIMPL_F_CALLS_AIMPL and
779	* IEM_CIMPL_F_CALLS_AIMPL_WITH_XSTATE.
780	* @note The python scripts will add this if missing. */
781	#define IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE RT_BIT_32(20)
782	/** The block calls an ASM-implementation instruction function with an implicit
783	* X86XSAVEAREA pointer argument.
784	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL, IEM_CIMPL_F_CALLS_AIMPL and
785	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
786	* @note No different from IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE, so same value.
787	* @note The python scripts will add this if missing. */
788	#define IEM_CIMPL_F_CALLS_AIMPL_WITH_XSTATE IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE
789	/** @} */
790
791
792	/** @name IEM_F_XXX - Execution mode flags (IEMCPU::fExec, IEMTB::fFlags).
793	*
794	* These flags are set when entering IEM and adjusted as code is executed, such
795	* that they will always contain the current values as instructions are
796	* finished.
797	*
798	* In recompiled execution mode, (most of) these flags are included in the
799	* translation block selection key and stored in IEMTB::fFlags alongside the
800	* IEMTB_F_XXX flags. The latter flags uses bits 31 thru 24, which are all zero
801	* in IEMCPU::fExec.
802	*
803	* @{ */
804	/** Mode: The block target mode mask. */
805	#define IEM_F_MODE_MASK UINT32_C(0x0000001f)
806	/** Mode: The IEMMODE part of the IEMTB_F_MODE_MASK value. */
807	#define IEM_F_MODE_CPUMODE_MASK UINT32_C(0x00000003)
808	/** X86 Mode: Bit used to indicating pre-386 CPU in 16-bit mode (for eliminating
809	* conditional in EIP/IP updating), and flat wide open CS, SS, DS, and ES in
810	* 32-bit mode (for simplifying most memory accesses). */
811	#define IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK UINT32_C(0x00000004)
812	/** X86 Mode: Bit indicating protected mode, real mode (or SMM) when not set. */
813	#define IEM_F_MODE_X86_PROT_MASK UINT32_C(0x00000008)
814	/** X86 Mode: Bit used to indicate virtual 8086 mode (only 16-bit). */
815	#define IEM_F_MODE_X86_V86_MASK UINT32_C(0x00000010)
816
817	/** X86 Mode: 16-bit on 386 or later. */
818	#define IEM_F_MODE_X86_16BIT UINT32_C(0x00000000)
819	/** X86 Mode: 80286, 80186 and 8086/88 targetting blocks (EIP update opt). */
820	#define IEM_F_MODE_X86_16BIT_PRE_386 UINT32_C(0x00000004)
821	/** X86 Mode: 16-bit protected mode on 386 or later. */
822	#define IEM_F_MODE_X86_16BIT_PROT UINT32_C(0x00000008)
823	/** X86 Mode: 16-bit protected mode on 386 or later. */
824	#define IEM_F_MODE_X86_16BIT_PROT_PRE_386 UINT32_C(0x0000000c)
825	/** X86 Mode: 16-bit virtual 8086 protected mode (on 386 or later). */
826	#define IEM_F_MODE_X86_16BIT_PROT_V86 UINT32_C(0x00000018)
827
828	/** X86 Mode: 32-bit on 386 or later. */
829	#define IEM_F_MODE_X86_32BIT UINT32_C(0x00000001)
830	/** X86 Mode: 32-bit mode with wide open flat CS, SS, DS and ES. */
831	#define IEM_F_MODE_X86_32BIT_FLAT UINT32_C(0x00000005)
832	/** X86 Mode: 32-bit protected mode. */
833	#define IEM_F_MODE_X86_32BIT_PROT UINT32_C(0x00000009)
834	/** X86 Mode: 32-bit protected mode with wide open flat CS, SS, DS and ES. */
835	#define IEM_F_MODE_X86_32BIT_PROT_FLAT UINT32_C(0x0000000d)
836
837	/** X86 Mode: 64-bit (includes protected, but not the flat bit). */
838	#define IEM_F_MODE_X86_64BIT UINT32_C(0x0000000a)
839
840	/** X86 Mode: Checks if @a a_fExec represent a FLAT mode. */
841	#define IEM_F_MODE_X86_IS_FLAT(a_fExec) ( ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_64BIT \
842	\|\| ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_32BIT_PROT_FLAT \
843	\|\| ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_32BIT_FLAT)
844
845	/** Bypass access handlers when set. */
846	#define IEM_F_BYPASS_HANDLERS UINT32_C(0x00010000)
847	/** Have pending hardware instruction breakpoints. */
848	#define IEM_F_PENDING_BRK_INSTR UINT32_C(0x00020000)
849	/** Have pending hardware data breakpoints. */
850	#define IEM_F_PENDING_BRK_DATA UINT32_C(0x00040000)
851
852	/** X86: Have pending hardware I/O breakpoints. */
853	#define IEM_F_PENDING_BRK_X86_IO UINT32_C(0x00000400)
854	/** X86: Disregard the lock prefix (implied or not) when set. */
855	#define IEM_F_X86_DISREGARD_LOCK UINT32_C(0x00000800)
856
857	/** Pending breakpoint mask (what iemCalcExecDbgFlags works out). */
858	#define IEM_F_PENDING_BRK_MASK (IEM_F_PENDING_BRK_INSTR \| IEM_F_PENDING_BRK_DATA \| IEM_F_PENDING_BRK_X86_IO)
859
860	/** Caller configurable options. */
861	#define IEM_F_USER_OPTS (IEM_F_BYPASS_HANDLERS \| IEM_F_X86_DISREGARD_LOCK)
862
863	/** X86: The current protection level (CPL) shift factor. */
864	#define IEM_F_X86_CPL_SHIFT 8
865	/** X86: The current protection level (CPL) mask. */
866	#define IEM_F_X86_CPL_MASK UINT32_C(0x00000300)
867	/** X86: The current protection level (CPL) shifted mask. */
868	#define IEM_F_X86_CPL_SMASK UINT32_C(0x00000003)
869
870	/** X86: Alignment checks enabled (CR0.AM=1 & EFLAGS.AC=1). */
871	#define IEM_F_X86_AC UINT32_C(0x00080000)
872
873	/** X86 execution context.
874	* The IEM_F_X86_CTX_XXX values are individual flags that can be combined (with
875	* the exception of IEM_F_X86_CTX_NORMAL). This allows running VMs from SMM
876	* mode. */
877	#define IEM_F_X86_CTX_MASK UINT32_C(0x0000f000)
878	/** X86 context: Plain regular execution context. */
879	#define IEM_F_X86_CTX_NORMAL UINT32_C(0x00000000)
880	/** X86 context: VT-x enabled. */
881	#define IEM_F_X86_CTX_VMX UINT32_C(0x00001000)
882	/** X86 context: AMD-V enabled. */
883	#define IEM_F_X86_CTX_SVM UINT32_C(0x00002000)
884	/** X86 context: In AMD-V or VT-x guest mode. */
885	#define IEM_F_X86_CTX_IN_GUEST UINT32_C(0x00004000)
886	/** X86 context: System management mode (SMM). */
887	#define IEM_F_X86_CTX_SMM UINT32_C(0x00008000)
888
889	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
890	* iemRegFinishClearingRF() most for most situations (CPUMCTX_DBG_HIT_DRX_MASK
891	* and CPUMCTX_DBG_DBGF_MASK are covered by the IEM_F_PENDING_BRK_XXX bits
892	* alread). */
893
894	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
895	* iemRegFinishClearingRF() most for most situations
896	* (CPUMCTX_DBG_HIT_DRX_MASK and CPUMCTX_DBG_DBGF_MASK are covered by
897	* the IEM_F_PENDING_BRK_XXX bits alread). */
898
899	/** @} */
900
901
902	/** @name IEMTB_F_XXX - Translation block flags (IEMTB::fFlags).
903	*
904	* Extends the IEM_F_XXX flags (subject to IEMTB_F_IEM_F_MASK) to make up the
905	* translation block flags. The combined flag mask (subject to
906	* IEMTB_F_KEY_MASK) is used as part of the lookup key for translation blocks.
907	*
908	* @{ */
909	/** Mask of IEM_F_XXX flags included in IEMTB_F_XXX. */
910	#define IEMTB_F_IEM_F_MASK UINT32_C(0x00ffffff)
911
912	/** Type: The block type mask. */
913	#define IEMTB_F_TYPE_MASK UINT32_C(0x03000000)
914	/** Type: Purly threaded recompiler (via tables). */
915	#define IEMTB_F_TYPE_THREADED UINT32_C(0x01000000)
916	/** Type: Native recompilation. */
917	#define IEMTB_F_TYPE_NATIVE UINT32_C(0x02000000)
918
919	/** Set when we're starting the block in an "interrupt shadow".
920	* We don't need to distingish between the two types of this mask, thus the one.
921	* @see CPUMCTX_INHIBIT_SHADOW, CPUMIsInInterruptShadow() */
922	#define IEMTB_F_INHIBIT_SHADOW UINT32_C(0x04000000)
923	/** Set when we're currently inhibiting NMIs
924	* @see CPUMCTX_INHIBIT_NMI, CPUMAreInterruptsInhibitedByNmi() */
925	#define IEMTB_F_INHIBIT_NMI UINT32_C(0x08000000)
926
927	/** Checks that EIP/IP is wihin CS.LIM before each instruction. Used when
928	* we're close the limit before starting a TB, as determined by
929	* iemGetTbFlagsForCurrentPc(). */
930	#define IEMTB_F_CS_LIM_CHECKS UINT32_C(0x10000000)
931
932	/** Mask of the IEMTB_F_XXX flags that are part of the TB lookup key.
933	*
934	* @note We skip all of IEM_F_X86_CTX_MASK, with the exception of SMM (which we
935	* don't implement), because we don't currently generate any context
936	* specific code - that's all handled in CIMPL functions.
937	*
938	* For the threaded recompiler we don't generate any CPL specific code
939	* either, but the native recompiler does for memory access (saves getting
940	* the CPL from fExec and turning it into IEMTLBE_F_PT_NO_USER).
941	* Since most OSes will not share code between rings, this shouldn't
942	* have any real effect on TB/memory/recompiling load.
943	*/
944	#define IEMTB_F_KEY_MASK ((UINT32_MAX & ~(IEM_F_X86_CTX_MASK \| IEMTB_F_TYPE_MASK)) \| IEM_F_X86_CTX_SMM)
945	/** @} */
946
947	AssertCompile( (IEM_F_MODE_X86_16BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
948	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
949	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_PROT_MASK));
950	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_V86_MASK));
951	AssertCompile( (IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
952	AssertCompile( IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
953	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_PROT_MASK));
954	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
955	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
956	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
957	AssertCompile( IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
958	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_V86_MASK));
959	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
960	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
961	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_PROT_MASK);
962	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
963	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_PROT_MASK);
964	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
965	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_V86_MASK);
966
967	AssertCompile( (IEM_F_MODE_X86_32BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
968	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
969	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_PROT_MASK));
970	AssertCompile( (IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
971	AssertCompile( IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
972	AssertCompile(!(IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_PROT_MASK));
973	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
974	AssertCompile(!(IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
975	AssertCompile( IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
976	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
977	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
978	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_PROT_MASK);
979
980	AssertCompile( (IEM_F_MODE_X86_64BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_64BIT);
981	AssertCompile( IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_PROT_MASK);
982	AssertCompile(!(IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
983
984	/** Native instruction type for use with the native code generator.
985	* This is a byte (uint8_t) for x86 and amd64 and uint32_t for the other(s). */
986	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
987	typedef uint8_t IEMNATIVEINSTR;
988	#else
989	typedef uint32_t IEMNATIVEINSTR;
990	#endif
991	/** Pointer to a native instruction unit. */
992	typedef IEMNATIVEINSTR *PIEMNATIVEINSTR;
993	/** Pointer to a const native instruction unit. */
994	typedef IEMNATIVEINSTR const *PCIEMNATIVEINSTR;
995
996	/**
997	* A call for the threaded call table.
998	*/
999	typedef struct IEMTHRDEDCALLENTRY
1000	{
1001	/** The function to call (IEMTHREADEDFUNCS). */
1002	uint16_t enmFunction;
1003
1004	/** Instruction number in the TB (for statistics). */
1005	uint8_t idxInstr;
1006	/** The opcode length. */
1007	uint8_t cbOpcode;
1008	/** Offset into IEMTB::pabOpcodes. */
1009	uint16_t offOpcode;
1010
1011	/** TB lookup table index (7 bits) and large size (1 bits).
1012	*
1013	* The default size is 1 entry, but for indirect calls and returns we set the
1014	* top bit and allocate 4 (IEM_TB_LOOKUP_TAB_LARGE_SIZE) entries. The large
1015	* tables uses RIP for selecting the entry to use, as it is assumed a hash table
1016	* lookup isn't that slow compared to sequentially trying out 4 TBs.
1017	*
1018	* By default lookup table entry 0 for a TB is reserved as a fallback for
1019	* calltable entries w/o explicit entreis, so this member will be non-zero if
1020	* there is a lookup entry associated with this call.
1021	*
1022	* @sa IEM_TB_LOOKUP_TAB_GET_SIZE, IEM_TB_LOOKUP_TAB_GET_IDX
1023	*/
1024	uint8_t uTbLookup;
1025
1026	/** Unused atm. */
1027	uint8_t uUnused0;
1028
1029	/** Generic parameters. */
1030	uint64_t auParams[3];
1031	} IEMTHRDEDCALLENTRY;
1032	AssertCompileSize(IEMTHRDEDCALLENTRY, sizeof(uint64_t) * 4);
1033	/** Pointer to a threaded call entry. */
1034	typedef struct IEMTHRDEDCALLENTRY *PIEMTHRDEDCALLENTRY;
1035	/** Pointer to a const threaded call entry. */
1036	typedef IEMTHRDEDCALLENTRY const *PCIEMTHRDEDCALLENTRY;
1037
1038	/** The number of TB lookup table entries for a large allocation
1039	* (IEMTHRDEDCALLENTRY::uTbLookup bit 7 set). */
1040	#define IEM_TB_LOOKUP_TAB_LARGE_SIZE 4
1041	/** Get the lookup table size from IEMTHRDEDCALLENTRY::uTbLookup. */
1042	#define IEM_TB_LOOKUP_TAB_GET_SIZE(a_uTbLookup) (!((a_uTbLookup) & 0x80) ? 1 : IEM_TB_LOOKUP_TAB_LARGE_SIZE)
1043	/** Get the first lookup table index from IEMTHRDEDCALLENTRY::uTbLookup. */
1044	#define IEM_TB_LOOKUP_TAB_GET_IDX(a_uTbLookup) ((a_uTbLookup) & 0x7f)
1045	/** Get the lookup table index from IEMTHRDEDCALLENTRY::uTbLookup and RIP. */
1046	#define IEM_TB_LOOKUP_TAB_GET_IDX_WITH_RIP(a_uTbLookup, a_Rip) \
1047	(!((a_uTbLookup) & 0x80) ? (a_uTbLookup) & 0x7f : ((a_uTbLookup) & 0x7f) + ((a_Rip) & (IEM_TB_LOOKUP_TAB_LARGE_SIZE - 1)) )
1048
1049	/** Make a IEMTHRDEDCALLENTRY::uTbLookup value. */
1050	#define IEM_TB_LOOKUP_TAB_MAKE(a_idxTable, a_fLarge) ((a_idxTable) \| ((a_fLarge) ? 0x80 : 0))
1051
1052	/**
1053	* Native IEM TB 'function' typedef.
1054	*
1055	* This will throw/longjmp on occation.
1056	*
1057	* @note AMD64 doesn't have that many non-volatile registers and does sport
1058	* 32-bit address displacments, so we don't need pCtx.
1059	*
1060	* On ARM64 pCtx allows us to directly address the whole register
1061	* context without requiring a separate indexing register holding the
1062	* offset. This saves an instruction loading the offset for each guest
1063	* CPU context access, at the cost of a non-volatile register.
1064	* Fortunately, ARM64 has quite a lot more registers.
1065	*/
1066	typedef
1067	#ifdef RT_ARCH_AMD64
1068	int FNIEMTBNATIVE(PVMCPUCC pVCpu)
1069	#else
1070	int FNIEMTBNATIVE(PVMCPUCC pVCpu, PCPUMCTX pCtx)
1071	#endif
1072	#if RT_CPLUSPLUS_PREREQ(201700)
1073	IEM_NOEXCEPT_MAY_LONGJMP
1074	#endif
1075	;
1076	/** Pointer to a native IEM TB entry point function.
1077	* This will throw/longjmp on occation. */
1078	typedef FNIEMTBNATIVE *PFNIEMTBNATIVE;
1079
1080
1081	/**
1082	* Translation block debug info entry type.
1083	*/
1084	typedef enum IEMTBDBGENTRYTYPE
1085	{
1086	kIemTbDbgEntryType_Invalid = 0,
1087	/** The entry is for marking a native code position.
1088	* Entries following this all apply to this position. */
1089	kIemTbDbgEntryType_NativeOffset,
1090	/** The entry is for a new guest instruction. */
1091	kIemTbDbgEntryType_GuestInstruction,
1092	/** Marks the start of a threaded call. */
1093	kIemTbDbgEntryType_ThreadedCall,
1094	/** Marks the location of a label. */
1095	kIemTbDbgEntryType_Label,
1096	/** Info about a host register shadowing a guest register. */
1097	kIemTbDbgEntryType_GuestRegShadowing,
1098	#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
1099	/** Info about a host SIMD register shadowing a guest SIMD register. */
1100	kIemTbDbgEntryType_GuestSimdRegShadowing,
1101	#endif
1102	#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING
1103	/** Info about a delayed RIP update. */
1104	kIemTbDbgEntryType_DelayedPcUpdate,
1105	#endif
1106	#if defined(IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK) \|\| defined(IEMNATIVE_WITH_SIMD_REG_ALLOCATOR)
1107	/** Info about a shadowed guest register becoming dirty. */
1108	kIemTbDbgEntryType_GuestRegDirty,
1109	/** Info about register writeback/flush oepration. */
1110	kIemTbDbgEntryType_GuestRegWriteback,
1111	#endif
1112	kIemTbDbgEntryType_End
1113	} IEMTBDBGENTRYTYPE;
1114
1115	/**
1116	* Translation block debug info entry.
1117	*/
1118	typedef union IEMTBDBGENTRY
1119	{
1120	/** Plain 32-bit view. */
1121	uint32_t u;
1122
1123	/** Generic view for getting at the type field. */
1124	struct
1125	{
1126	/** IEMTBDBGENTRYTYPE */
1127	uint32_t uType : 4;
1128	uint32_t uTypeSpecific : 28;
1129	} Gen;
1130
1131	struct
1132	{
1133	/** kIemTbDbgEntryType_ThreadedCall1. */
1134	uint32_t uType : 4;
1135	/** Native code offset. */
1136	uint32_t offNative : 28;
1137	} NativeOffset;
1138
1139	struct
1140	{
1141	/** kIemTbDbgEntryType_GuestInstruction. */
1142	uint32_t uType : 4;
1143	uint32_t uUnused : 4;
1144	/** The IEM_F_XXX flags. */
1145	uint32_t fExec : 24;
1146	} GuestInstruction;
1147
1148	struct
1149	{
1150	/* kIemTbDbgEntryType_ThreadedCall. */
1151	uint32_t uType : 4;
1152	/** Set if the call was recompiled to native code, clear if just calling
1153	* threaded function. */
1154	uint32_t fRecompiled : 1;
1155	uint32_t uUnused : 11;
1156	/** The threaded call number (IEMTHREADEDFUNCS). */
1157	uint32_t enmCall : 16;
1158	} ThreadedCall;
1159
1160	struct
1161	{
1162	/* kIemTbDbgEntryType_Label. */
1163	uint32_t uType : 4;
1164	uint32_t uUnused : 4;
1165	/** The label type (IEMNATIVELABELTYPE). */
1166	uint32_t enmLabel : 8;
1167	/** The label data. */
1168	uint32_t uData : 16;
1169	} Label;
1170
1171	struct
1172	{
1173	/* kIemTbDbgEntryType_GuestRegShadowing. */
1174	uint32_t uType : 4;
1175	uint32_t uUnused : 4;
1176	/** The guest register being shadowed (IEMNATIVEGSTREG). */
1177	uint32_t idxGstReg : 8;
1178	/** The host new register number, UINT8_MAX if dropped. */
1179	uint32_t idxHstReg : 8;
1180	/** The previous host register number, UINT8_MAX if new. */
1181	uint32_t idxHstRegPrev : 8;
1182	} GuestRegShadowing;
1183
1184	#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
1185	struct
1186	{
1187	/* kIemTbDbgEntryType_GuestSimdRegShadowing. */
1188	uint32_t uType : 4;
1189	uint32_t uUnused : 4;
1190	/** The guest register being shadowed (IEMNATIVEGSTSIMDREG). */
1191	uint32_t idxGstSimdReg : 8;
1192	/** The host new register number, UINT8_MAX if dropped. */
1193	uint32_t idxHstSimdReg : 8;
1194	/** The previous host register number, UINT8_MAX if new. */
1195	uint32_t idxHstSimdRegPrev : 8;
1196	} GuestSimdRegShadowing;
1197	#endif
1198
1199	#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING
1200	struct
1201	{
1202	/* kIemTbDbgEntryType_DelayedPcUpdate. */
1203	uint32_t uType : 4;
1204	/* The instruction offset added to the program counter. */
1205	uint32_t offPc : 14;
1206	/** Number of instructions skipped. */
1207	uint32_t cInstrSkipped : 14;
1208	} DelayedPcUpdate;
1209	#endif
1210
1211	#if defined(IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK) \|\| defined(IEMNATIVE_WITH_SIMD_REG_ALLOCATOR)
1212	struct
1213	{
1214	/* kIemTbDbgEntryType_GuestRegDirty. */
1215	uint32_t uType : 4;
1216	uint32_t uUnused : 11;
1217	/** Flag whether this is about a SIMD (true) or general (false) register. */
1218	uint32_t fSimdReg : 1;
1219	/** The guest register index being marked as dirty. */
1220	uint32_t idxGstReg : 8;
1221	/** The host register number this register is shadowed in .*/
1222	uint32_t idxHstReg : 8;
1223	} GuestRegDirty;
1224
1225	struct
1226	{
1227	/* kIemTbDbgEntryType_GuestRegWriteback. */
1228	uint32_t uType : 4;
1229	/** Flag whether this is about a SIMD (true) or general (false) register flush. */
1230	uint32_t fSimdReg : 1;
1231	/** The mask shift. */
1232	uint32_t cShift : 2;
1233	/** The guest register mask being written back. */
1234	uint32_t fGstReg : 25;
1235	} GuestRegWriteback;
1236	#endif
1237
1238	} IEMTBDBGENTRY;
1239	AssertCompileSize(IEMTBDBGENTRY, sizeof(uint32_t));
1240	/** Pointer to a debug info entry. */
1241	typedef IEMTBDBGENTRY *PIEMTBDBGENTRY;
1242	/** Pointer to a const debug info entry. */
1243	typedef IEMTBDBGENTRY const *PCIEMTBDBGENTRY;
1244
1245	/**
1246	* Translation block debug info.
1247	*/
1248	typedef struct IEMTBDBG
1249	{
1250	/** Number of entries in aEntries. */
1251	uint32_t cEntries;
1252	/** The offset of the last kIemTbDbgEntryType_NativeOffset record. */
1253	uint32_t offNativeLast;
1254	/** Debug info entries. */
1255	RT_FLEXIBLE_ARRAY_EXTENSION
1256	IEMTBDBGENTRY aEntries[RT_FLEXIBLE_ARRAY];
1257	} IEMTBDBG;
1258	/** Pointer to TB debug info. */
1259	typedef IEMTBDBG *PIEMTBDBG;
1260	/** Pointer to const TB debug info. */
1261	typedef IEMTBDBG const *PCIEMTBDBG;
1262
1263
1264	/**
1265	* Translation block.
1266	*
1267	* The current plan is to just keep TBs and associated lookup hash table private
1268	* to each VCpu as that simplifies TB removal greatly (no races) and generally
1269	* avoids using expensive atomic primitives for updating lists and stuff.
1270	*/
1271	#pragma pack(2) /* to prevent the Thrd structure from being padded unnecessarily */
1272	typedef struct IEMTB
1273	{
1274	/** Next block with the same hash table entry. */
1275	struct IEMTB *pNext;
1276	/** Usage counter. */
1277	uint32_t cUsed;
1278	/** The IEMCPU::msRecompilerPollNow last time it was used. */
1279	uint32_t msLastUsed;
1280
1281	/** @name What uniquely identifies the block.
1282	* @{ */
1283	RTGCPHYS GCPhysPc;
1284	/** IEMTB_F_XXX (i.e. IEM_F_XXX ++). */
1285	uint32_t fFlags;
1286	union
1287	{
1288	struct
1289	{
1290	/*< Relevant CS X86DESCATTR_XXX bits. /
1291	uint16_t fAttr;
1292	} x86;
1293	};
1294	/** @} */
1295
1296	/** Number of opcode ranges. */
1297	uint8_t cRanges;
1298	/** Statistics: Number of instructions in the block. */
1299	uint8_t cInstructions;
1300
1301	/** Type specific info. */
1302	union
1303	{
1304	struct
1305	{
1306	/** The call sequence table. */
1307	PIEMTHRDEDCALLENTRY paCalls;
1308	/** Number of calls in paCalls. */
1309	uint16_t cCalls;
1310	/** Number of calls allocated. */
1311	uint16_t cAllocated;
1312	} Thrd;
1313	struct
1314	{
1315	/** The native instructions (PFNIEMTBNATIVE). */
1316	PIEMNATIVEINSTR paInstructions;
1317	/** Number of instructions pointed to by paInstructions. */
1318	uint32_t cInstructions;
1319	} Native;
1320	/** Generic view for zeroing when freeing. */
1321	struct
1322	{
1323	uintptr_t uPtr;
1324	uint32_t uData;
1325	} Gen;
1326	};
1327
1328	/** The allocation chunk this TB belongs to. */
1329	uint8_t idxAllocChunk;
1330	/** The number of entries in the lookup table.
1331	* Because we're out of space, the TB lookup table is located before the
1332	* opcodes pointed to by pabOpcodes. */
1333	uint8_t cTbLookupEntries;
1334
1335	/** Number of bytes of opcodes stored in pabOpcodes.
1336	* @todo this field isn't really needed, aRanges keeps the actual info. */
1337	uint16_t cbOpcodes;
1338	/** Pointer to the opcode bytes this block was recompiled from.
1339	* This also points to the TB lookup table, which starts cTbLookupEntries
1340	* entries before the opcodes (we don't have room atm for another point). */
1341	uint8_t *pabOpcodes;
1342
1343	/** Debug info if enabled.
1344	* This is only generated by the native recompiler. */
1345	PIEMTBDBG pDbgInfo;
1346
1347	/* --- 64 byte cache line end --- */
1348
1349	/** Opcode ranges.
1350	*
1351	* The opcode checkers and maybe TLB loading functions will use this to figure
1352	* out what to do. The parameter will specify an entry and the opcode offset to
1353	* start at and the minimum number of bytes to verify (instruction length).
1354	*
1355	* When VT-x and AMD-V looks up the opcode bytes for an exitting instruction,
1356	* they'll first translate RIP (+ cbInstr - 1) to a physical address using the
1357	* code TLB (must have a valid entry for that address) and scan the ranges to
1358	* locate the corresponding opcodes. Probably.
1359	*/
1360	struct IEMTBOPCODERANGE
1361	{
1362	/** Offset within pabOpcodes. */
1363	uint16_t offOpcodes;
1364	/** Number of bytes. */
1365	uint16_t cbOpcodes;
1366	/** The page offset. */
1367	RT_GCC_EXTENSION
1368	uint16_t offPhysPage : 12;
1369	/** Unused bits. */
1370	RT_GCC_EXTENSION
1371	uint16_t u2Unused : 2;
1372	/** Index into GCPhysPc + aGCPhysPages for the physical page address. */
1373	RT_GCC_EXTENSION
1374	uint16_t idxPhysPage : 2;
1375	} aRanges[8];
1376
1377	/** Physical pages that this TB covers.
1378	* The GCPhysPc w/o page offset is element zero, so starting here with 1. */
1379	RTGCPHYS aGCPhysPages[2];
1380	} IEMTB;
1381	#pragma pack()
1382	AssertCompileMemberAlignment(IEMTB, GCPhysPc, sizeof(RTGCPHYS));
1383	AssertCompileMemberAlignment(IEMTB, Thrd, sizeof(void *));
1384	AssertCompileMemberAlignment(IEMTB, pabOpcodes, sizeof(void *));
1385	AssertCompileMemberAlignment(IEMTB, pDbgInfo, sizeof(void *));
1386	AssertCompileMemberAlignment(IEMTB, aGCPhysPages, sizeof(RTGCPHYS));
1387	AssertCompileMemberOffset(IEMTB, aRanges, 64);
1388	AssertCompileMemberSize(IEMTB, aRanges[0], 6);
1389	#if 1
1390	AssertCompileSize(IEMTB, 128);
1391	# define IEMTB_SIZE_IS_POWER_OF_TWO /*< The IEMTB size is a power of two. /
1392	#else
1393	AssertCompileSize(IEMTB, 168);
1394	# undef IEMTB_SIZE_IS_POWER_OF_TWO
1395	#endif
1396
1397	/** Pointer to a translation block. */
1398	typedef IEMTB *PIEMTB;
1399	/** Pointer to a const translation block. */
1400	typedef IEMTB const *PCIEMTB;
1401
1402	/** Gets address of the given TB lookup table entry. */
1403	#define IEMTB_GET_TB_LOOKUP_TAB_ENTRY(a_pTb, a_idx) \
1404	((PIEMTB )&(a_pTb)->pabOpcodes[-(int)((a_pTb)->cTbLookupEntries - (a_idx)) sizeof(PIEMTB)])
1405
1406	/**
1407	* Gets the physical address for a TB opcode range.
1408	*/
1409	DECL_FORCE_INLINE(RTGCPHYS) iemTbGetRangePhysPageAddr(PCIEMTB pTb, uint8_t idxRange)
1410	{
1411	Assert(idxRange < RT_MIN(pTb->cRanges, RT_ELEMENTS(pTb->aRanges)));
1412	uint8_t const idxPage = pTb->aRanges[idxRange].idxPhysPage;
1413	Assert(idxPage <= RT_ELEMENTS(pTb->aGCPhysPages));
1414	if (idxPage == 0)
1415	return pTb->GCPhysPc & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
1416	Assert(!(pTb->aGCPhysPages[idxPage - 1] & GUEST_PAGE_OFFSET_MASK));
1417	return pTb->aGCPhysPages[idxPage - 1];
1418	}
1419
1420
1421	/**
1422	* A chunk of memory in the TB allocator.
1423	*/
1424	typedef struct IEMTBCHUNK
1425	{
1426	/** Pointer to the translation blocks in this chunk. */
1427	PIEMTB paTbs;
1428	#ifdef IN_RING0
1429	/** Allocation handle. */
1430	RTR0MEMOBJ hMemObj;
1431	#endif
1432	} IEMTBCHUNK;
1433
1434	/**
1435	* A per-CPU translation block allocator.
1436	*
1437	* Because of how the IEMTBCACHE uses the lower 6 bits of the TB address to keep
1438	* the length of the collision list, and of course also for cache line alignment
1439	* reasons, the TBs must be allocated with at least 64-byte alignment.
1440	* Memory is there therefore allocated using one of the page aligned allocators.
1441	*
1442	*
1443	* To avoid wasting too much memory, it is allocated piecemeal as needed,
1444	* in chunks (IEMTBCHUNK) of 2 MiB or more. The TB has an 8-bit chunk index
1445	* that enables us to quickly calculate the allocation bitmap position when
1446	* freeing the translation block.
1447	*/
1448	typedef struct IEMTBALLOCATOR
1449	{
1450	/** Magic value (IEMTBALLOCATOR_MAGIC). */
1451	uint32_t uMagic;
1452
1453	#ifdef IEMTB_SIZE_IS_POWER_OF_TWO
1454	/** Mask corresponding to cTbsPerChunk - 1. */
1455	uint32_t fChunkMask;
1456	/** Shift count corresponding to cTbsPerChunk. */
1457	uint8_t cChunkShift;
1458	#else
1459	uint32_t uUnused;
1460	uint8_t bUnused;
1461	#endif
1462	/** Number of chunks we're allowed to allocate. */
1463	uint8_t cMaxChunks;
1464	/** Number of chunks currently populated. */
1465	uint16_t cAllocatedChunks;
1466	/** Number of translation blocks per chunk. */
1467	uint32_t cTbsPerChunk;
1468	/** Chunk size. */
1469	uint32_t cbPerChunk;
1470
1471	/** The maximum number of TBs. */
1472	uint32_t cMaxTbs;
1473	/** Total number of TBs in the populated chunks.
1474	* (cAllocatedChunks * cTbsPerChunk) */
1475	uint32_t cTotalTbs;
1476	/** The current number of TBs in use.
1477	* The number of free TBs: cAllocatedTbs - cInUseTbs; */
1478	uint32_t cInUseTbs;
1479	/** Statistics: Number of the cInUseTbs that are native ones. */
1480	uint32_t cNativeTbs;
1481	/** Statistics: Number of the cInUseTbs that are threaded ones. */
1482	uint32_t cThreadedTbs;
1483
1484	/** Where to start pruning TBs from when we're out.
1485	* See iemTbAllocatorAllocSlow for details. */
1486	uint32_t iPruneFrom;
1487	/** Hint about which bit to start scanning the bitmap from. */
1488	uint32_t iStartHint;
1489	/** Where to start pruning native TBs from when we're out of executable memory.
1490	* See iemTbAllocatorFreeupNativeSpace for details. */
1491	uint32_t iPruneNativeFrom;
1492	/** Index into IEMTBALLOCATOR::apTbFreeCache were the next freed TB can be stored
1493	* (0 means the cache is empty, 32 the cache is full). */
1494	uint32_t idxTbCacheFree;
1495
1496	/** Statistics: Number of TB allocation calls. */
1497	STAMCOUNTER StatAllocs;
1498	/** Statistics: Number of TB free calls. */
1499	STAMCOUNTER StatFrees;
1500	/** Statistics: Time spend pruning. */
1501	STAMPROFILE StatPrune;
1502	/** Statistics: Time spend pruning native TBs. */
1503	STAMPROFILE StatPruneNative;
1504
1505	/** The delayed free list (see iemTbAlloctorScheduleForFree). */
1506	PIEMTB pDelayedFreeHead;
1507	/* Cache of recently freed TBs for immediate consumption by the allocator. */
1508	PIEMTB apTbFreeCache[32];
1509
1510	/** Allocation chunks. */
1511	IEMTBCHUNK aChunks[256];
1512
1513	/** Allocation bitmap for all possible chunk chunks. */
1514	RT_FLEXIBLE_ARRAY_EXTENSION
1515	uint64_t bmAllocated[RT_FLEXIBLE_ARRAY];
1516	} IEMTBALLOCATOR;
1517	/** Pointer to a TB allocator. */
1518	typedef struct IEMTBALLOCATOR *PIEMTBALLOCATOR;
1519
1520	/** Magic value for the TB allocator (Emmet Harley Cohen). */
1521	#define IEMTBALLOCATOR_MAGIC UINT32_C(0x19900525)
1522
1523
1524	/**
1525	* A per-CPU translation block cache (hash table).
1526	*
1527	* The hash table is allocated once during IEM initialization and size double
1528	* the max TB count, rounded up to the nearest power of two (so we can use and
1529	* AND mask rather than a rest division when hashing).
1530	*/
1531	typedef struct IEMTBCACHE
1532	{
1533	/** Magic value (IEMTBCACHE_MAGIC). */
1534	uint32_t uMagic;
1535	/** Size of the hash table. This is a power of two. */
1536	uint32_t cHash;
1537	/** The mask corresponding to cHash. */
1538	uint32_t uHashMask;
1539	uint32_t uPadding;
1540
1541	/** @name Statistics
1542	* @{ */
1543	/** Number of collisions ever. */
1544	STAMCOUNTER cCollisions;
1545
1546	/** Statistics: Number of TB lookup misses. */
1547	STAMCOUNTER cLookupMisses;
1548	/** Statistics: Number of TB lookup hits via hash table (debug only). */
1549	STAMCOUNTER cLookupHits;
1550	/** Statistics: Number of TB lookup hits via TB associated lookup table (debug only). */
1551	STAMCOUNTER cLookupHitsViaTbLookupTable;
1552	STAMCOUNTER auPadding2[2];
1553	/** Statistics: Collision list length pruning. */
1554	STAMPROFILE StatPrune;
1555	/** @} */
1556
1557	/** The hash table itself.
1558	* @note The lower 6 bits of the pointer is used for keeping the collision
1559	* list length, so we can take action when it grows too long.
1560	* This works because TBs are allocated using a 64 byte (or
1561	* higher) alignment from page aligned chunks of memory, so the lower
1562	* 6 bits of the address will always be zero.
1563	* See IEMTBCACHE_PTR_COUNT_MASK, IEMTBCACHE_PTR_MAKE and friends.
1564	*/
1565	RT_FLEXIBLE_ARRAY_EXTENSION
1566	PIEMTB apHash[RT_FLEXIBLE_ARRAY];
1567	} IEMTBCACHE;
1568	/** Pointer to a per-CPU translation block cahce. */
1569	typedef IEMTBCACHE *PIEMTBCACHE;
1570
1571	/** Magic value for IEMTBCACHE (Johnny O'Neal). */
1572	#define IEMTBCACHE_MAGIC UINT32_C(0x19561010)
1573
1574	/** The collision count mask for IEMTBCACHE::apHash entries. */
1575	#define IEMTBCACHE_PTR_COUNT_MASK ((uintptr_t)0x3f)
1576	/** The max collision count for IEMTBCACHE::apHash entries before pruning. */
1577	#define IEMTBCACHE_PTR_MAX_COUNT ((uintptr_t)0x30)
1578	/** Combine a TB pointer and a collision list length into a value for an
1579	* IEMTBCACHE::apHash entry. */
1580	#define IEMTBCACHE_PTR_MAKE(a_pTb, a_cCount) (PIEMTB)((uintptr_t)(a_pTb) \| (a_cCount))
1581	/** Combine a TB pointer and a collision list length into a value for an
1582	* IEMTBCACHE::apHash entry. */
1583	#define IEMTBCACHE_PTR_GET_TB(a_pHashEntry) (PIEMTB)((uintptr_t)(a_pHashEntry) & ~IEMTBCACHE_PTR_COUNT_MASK)
1584	/** Combine a TB pointer and a collision list length into a value for an
1585	* IEMTBCACHE::apHash entry. */
1586	#define IEMTBCACHE_PTR_GET_COUNT(a_pHashEntry) ((uintptr_t)(a_pHashEntry) & IEMTBCACHE_PTR_COUNT_MASK)
1587
1588	/**
1589	* Calculates the hash table slot for a TB from physical PC address and TB flags.
1590	*/
1591	#define IEMTBCACHE_HASH(a_paCache, a_fTbFlags, a_GCPhysPc) \
1592	IEMTBCACHE_HASH_NO_KEY_MASK(a_paCache, (a_fTbFlags) & IEMTB_F_KEY_MASK, a_GCPhysPc)
1593
1594	/**
1595	* Calculates the hash table slot for a TB from physical PC address and TB
1596	* flags, ASSUMING the caller has applied IEMTB_F_KEY_MASK to @a a_fTbFlags.
1597	*/
1598	#define IEMTBCACHE_HASH_NO_KEY_MASK(a_paCache, a_fTbFlags, a_GCPhysPc) \
1599	(((uint32_t)(a_GCPhysPc) ^ (a_fTbFlags)) & (a_paCache)->uHashMask)
1600
1601
1602	/** @name IEMBRANCHED_F_XXX - Branched indicator (IEMCPU::fTbBranched).
1603	*
1604	* These flags parallels the main IEM_CIMPL_F_BRANCH_XXX flags.
1605	*
1606	* @{ */
1607	/** Value if no branching happened recently. */
1608	#define IEMBRANCHED_F_NO UINT8_C(0x00)
1609	/** Flag set if direct branch, clear if absolute or indirect. */
1610	#define IEMBRANCHED_F_DIRECT UINT8_C(0x01)
1611	/** Flag set if indirect branch, clear if direct or relative. */
1612	#define IEMBRANCHED_F_INDIRECT UINT8_C(0x02)
1613	/** Flag set if relative branch, clear if absolute or indirect. */
1614	#define IEMBRANCHED_F_RELATIVE UINT8_C(0x04)
1615	/** Flag set if conditional branch, clear if unconditional. */
1616	#define IEMBRANCHED_F_CONDITIONAL UINT8_C(0x08)
1617	/** Flag set if it's a far branch. */
1618	#define IEMBRANCHED_F_FAR UINT8_C(0x10)
1619	/** Flag set if the stack pointer is modified. */
1620	#define IEMBRANCHED_F_STACK UINT8_C(0x20)
1621	/** Flag set if the stack pointer and (maybe) the stack segment are modified. */
1622	#define IEMBRANCHED_F_STACK_FAR UINT8_C(0x40)
1623	/** Flag set (by IEM_MC_REL_JMP_XXX) if it's a zero bytes relative jump. */
1624	#define IEMBRANCHED_F_ZERO UINT8_C(0x80)
1625	/** @} */
1626
1627
1628	/**
1629	* The per-CPU IEM state.
1630	*/
1631	typedef struct IEMCPU
1632	{
1633	/** Info status code that needs to be propagated to the IEM caller.
1634	* This cannot be passed internally, as it would complicate all success
1635	* checks within the interpreter making the code larger and almost impossible
1636	* to get right. Instead, we'll store status codes to pass on here. Each
1637	* source of these codes will perform appropriate sanity checks. */
1638	int32_t rcPassUp; /* 0x00 */
1639	/** Execution flag, IEM_F_XXX. */
1640	uint32_t fExec; /* 0x04 */
1641
1642	/** @name Decoder state.
1643	* @{ */
1644	#ifdef IEM_WITH_CODE_TLB
1645	/** The offset of the next instruction byte. */
1646	uint32_t offInstrNextByte; /* 0x08 */
1647	/** The number of bytes available at pbInstrBuf for the current instruction.
1648	* This takes the max opcode length into account so that doesn't need to be
1649	* checked separately. */
1650	uint32_t cbInstrBuf; /* 0x0c */
1651	/** Pointer to the page containing RIP, user specified buffer or abOpcode.
1652	* This can be NULL if the page isn't mappable for some reason, in which
1653	* case we'll do fallback stuff.
1654	*
1655	* If we're executing an instruction from a user specified buffer,
1656	* IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
1657	* aligned pointer but pointer to the user data.
1658	*
1659	* For instructions crossing pages, this will start on the first page and be
1660	* advanced to the next page by the time we've decoded the instruction. This
1661	* therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
1662	*/
1663	uint8_t const pbInstrBuf; / 0x10 */
1664	# if ARCH_BITS == 32
1665	uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
1666	# endif
1667	/** The program counter corresponding to pbInstrBuf.
1668	* This is set to a non-canonical address when we need to invalidate it. */
1669	uint64_t uInstrBufPc; /* 0x18 */
1670	/** The guest physical address corresponding to pbInstrBuf. */
1671	RTGCPHYS GCPhysInstrBuf; /* 0x20 */
1672	/** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
1673	* This takes the CS segment limit into account.
1674	* @note Set to zero when the code TLB is flushed to trigger TLB reload. */
1675	uint16_t cbInstrBufTotal; /* 0x28 */
1676	/** Offset into pbInstrBuf of the first byte of the current instruction.
1677	* Can be negative to efficiently handle cross page instructions. */
1678	int16_t offCurInstrStart; /* 0x2a */
1679
1680	# ifndef IEM_WITH_OPAQUE_DECODER_STATE
1681	/** The prefix mask (IEM_OP_PRF_XXX). */
1682	uint32_t fPrefixes; /* 0x2c */
1683	/** The extra REX ModR/M register field bit (REX.R << 3). */
1684	uint8_t uRexReg; /* 0x30 */
1685	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
1686	* (REX.B << 3). */
1687	uint8_t uRexB; /* 0x31 */
1688	/** The extra REX SIB index field bit (REX.X << 3). */
1689	uint8_t uRexIndex; /* 0x32 */
1690
1691	/** The effective segment register (X86_SREG_XXX). */
1692	uint8_t iEffSeg; /* 0x33 */
1693
1694	/** The offset of the ModR/M byte relative to the start of the instruction. */
1695	uint8_t offModRm; /* 0x34 */
1696
1697	# ifdef IEM_WITH_CODE_TLB_AND_OPCODE_BUF
1698	/** The current offset into abOpcode. */
1699	uint8_t offOpcode; /* 0x35 */
1700	# else
1701	uint8_t bUnused; /* 0x35 */
1702	# endif
1703	# else /* IEM_WITH_OPAQUE_DECODER_STATE */
1704	uint8_t abOpaqueDecoderPart1[0x36 - 0x2c];
1705	# endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1706
1707	#else /* !IEM_WITH_CODE_TLB */
1708	# ifndef IEM_WITH_OPAQUE_DECODER_STATE
1709	/** The size of what has currently been fetched into abOpcode. */
1710	uint8_t cbOpcode; /* 0x08 */
1711	/** The current offset into abOpcode. */
1712	uint8_t offOpcode; /* 0x09 */
1713	/** The offset of the ModR/M byte relative to the start of the instruction. */
1714	uint8_t offModRm; /* 0x0a */
1715
1716	/** The effective segment register (X86_SREG_XXX). */
1717	uint8_t iEffSeg; /* 0x0b */
1718
1719	/** The prefix mask (IEM_OP_PRF_XXX). */
1720	uint32_t fPrefixes; /* 0x0c */
1721	/** The extra REX ModR/M register field bit (REX.R << 3). */
1722	uint8_t uRexReg; /* 0x10 */
1723	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
1724	* (REX.B << 3). */
1725	uint8_t uRexB; /* 0x11 */
1726	/** The extra REX SIB index field bit (REX.X << 3). */
1727	uint8_t uRexIndex; /* 0x12 */
1728
1729	# else /* IEM_WITH_OPAQUE_DECODER_STATE */
1730	uint8_t abOpaqueDecoderPart1[0x13 - 0x08];
1731	# endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1732	#endif /* !IEM_WITH_CODE_TLB */
1733
1734	#ifndef IEM_WITH_OPAQUE_DECODER_STATE
1735	/** The effective operand mode. */
1736	IEMMODE enmEffOpSize; /* 0x36, 0x13 */
1737	/** The default addressing mode. */
1738	IEMMODE enmDefAddrMode; /* 0x37, 0x14 */
1739	/** The effective addressing mode. */
1740	IEMMODE enmEffAddrMode; /* 0x38, 0x15 */
1741	/** The default operand mode. */
1742	IEMMODE enmDefOpSize; /* 0x39, 0x16 */
1743
1744	/** Prefix index (VEX.pp) for two byte and three byte tables. */
1745	uint8_t idxPrefix; /* 0x3a, 0x17 */
1746	/** 3rd VEX/EVEX/XOP register.
1747	* Please use IEM_GET_EFFECTIVE_VVVV to access. */
1748	uint8_t uVex3rdReg; /* 0x3b, 0x18 */
1749	/** The VEX/EVEX/XOP length field. */
1750	uint8_t uVexLength; /* 0x3c, 0x19 */
1751	/** Additional EVEX stuff. */
1752	uint8_t fEvexStuff; /* 0x3d, 0x1a */
1753
1754	# ifndef IEM_WITH_CODE_TLB
1755	/** Explicit alignment padding. */
1756	uint8_t abAlignment2a[1]; /* 0x1b */
1757	# endif
1758	/** The FPU opcode (FOP). */
1759	uint16_t uFpuOpcode; /* 0x3e, 0x1c */
1760	# ifndef IEM_WITH_CODE_TLB
1761	/** Explicit alignment padding. */
1762	uint8_t abAlignment2b[2]; /* 0x1e */
1763	# endif
1764
1765	/** The opcode bytes. */
1766	uint8_t abOpcode[15]; /* 0x40, 0x20 */
1767	/** Explicit alignment padding. */
1768	# ifdef IEM_WITH_CODE_TLB
1769	//uint8_t abAlignment2c[0x4f - 0x4f]; /* 0x4f */
1770	# else
1771	uint8_t abAlignment2c[0x4f - 0x2f]; /* 0x2f */
1772	# endif
1773
1774	#else /* IEM_WITH_OPAQUE_DECODER_STATE */
1775	# ifdef IEM_WITH_CODE_TLB
1776	uint8_t abOpaqueDecoderPart2[0x4f - 0x36];
1777	# else
1778	uint8_t abOpaqueDecoderPart2[0x4f - 0x13];
1779	# endif
1780	#endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1781	/** @} */
1782
1783
1784	/** The number of active guest memory mappings. */
1785	uint8_t cActiveMappings; /* 0x4f, 0x4f */
1786
1787	/** Records for tracking guest memory mappings. */
1788	struct
1789	{
1790	/** The address of the mapped bytes. */
1791	R3R0PTRTYPE(void *) pv;
1792	/** The access flags (IEM_ACCESS_XXX).
1793	* IEM_ACCESS_INVALID if the entry is unused. */
1794	uint32_t fAccess;
1795	#if HC_ARCH_BITS == 64
1796	uint32_t u32Alignment4; /*< Alignment padding. /
1797	#endif
1798	} aMemMappings[3]; /* 0x50 LB 0x30 */
1799
1800	/** Locking records for the mapped memory. */
1801	union
1802	{
1803	PGMPAGEMAPLOCK Lock;
1804	uint64_t au64Padding[2];
1805	} aMemMappingLocks[3]; /* 0x80 LB 0x30 */
1806
1807	/** Bounce buffer info.
1808	* This runs in parallel to aMemMappings. */
1809	struct
1810	{
1811	/** The physical address of the first byte. */
1812	RTGCPHYS GCPhysFirst;
1813	/** The physical address of the second page. */
1814	RTGCPHYS GCPhysSecond;
1815	/** The number of bytes in the first page. */
1816	uint16_t cbFirst;
1817	/** The number of bytes in the second page. */
1818	uint16_t cbSecond;
1819	/** Whether it's unassigned memory. */
1820	bool fUnassigned;
1821	/** Explicit alignment padding. */
1822	bool afAlignment5[3];
1823	} aMemBbMappings[3]; /* 0xb0 LB 0x48 */
1824
1825	/** The flags of the current exception / interrupt. */
1826	uint32_t fCurXcpt; /* 0xf8 */
1827	/** The current exception / interrupt. */
1828	uint8_t uCurXcpt; /* 0xfc */
1829	/** Exception / interrupt recursion depth. */
1830	int8_t cXcptRecursions; /* 0xfb */
1831
1832	/** The next unused mapping index.
1833	* @todo try find room for this up with cActiveMappings. */
1834	uint8_t iNextMapping; /* 0xfd */
1835	uint8_t abAlignment7[1];
1836
1837	/** Bounce buffer storage.
1838	* This runs in parallel to aMemMappings and aMemBbMappings. */
1839	struct
1840	{
1841	uint8_t ab[512];
1842	} aBounceBuffers[3]; /* 0x100 LB 0x600 */
1843
1844
1845	/** Pointer set jump buffer - ring-3 context. */
1846	R3PTRTYPE(jmp_buf *) pJmpBufR3;
1847	/** Pointer set jump buffer - ring-0 context. */
1848	R0PTRTYPE(jmp_buf *) pJmpBufR0;
1849
1850	/** @todo Should move this near @a fCurXcpt later. */
1851	/** The CR2 for the current exception / interrupt. */
1852	uint64_t uCurXcptCr2;
1853	/** The error code for the current exception / interrupt. */
1854	uint32_t uCurXcptErr;
1855
1856	/** @name Statistics
1857	* @{ */
1858	/** The number of instructions we've executed. */
1859	uint32_t cInstructions;
1860	/** The number of potential exits. */
1861	uint32_t cPotentialExits;
1862	/** The number of bytes data or stack written (mostly for IEMExecOneEx).
1863	* This may contain uncommitted writes. */
1864	uint32_t cbWritten;
1865	/** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
1866	uint32_t cRetInstrNotImplemented;
1867	/** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
1868	uint32_t cRetAspectNotImplemented;
1869	/** Counts informational statuses returned (other than VINF_SUCCESS). */
1870	uint32_t cRetInfStatuses;
1871	/** Counts other error statuses returned. */
1872	uint32_t cRetErrStatuses;
1873	/** Number of times rcPassUp has been used. */
1874	uint32_t cRetPassUpStatus;
1875	/** Number of times RZ left with instruction commit pending for ring-3. */
1876	uint32_t cPendingCommit;
1877	/** Number of misaligned (host sense) atomic instruction accesses. */
1878	uint32_t cMisalignedAtomics;
1879	/** Number of long jumps. */
1880	uint32_t cLongJumps;
1881	/** @} */
1882
1883	/** @name Target CPU information.
1884	* @{ */
1885	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
1886	/** The target CPU. */
1887	uint8_t uTargetCpu;
1888	#else
1889	uint8_t bTargetCpuPadding;
1890	#endif
1891	/** For selecting assembly works matching the target CPU EFLAGS behaviour, see
1892	* IEMTARGETCPU_EFL_BEHAVIOR_XXX for values, with the 1st entry for when no
1893	* native host support and the 2nd for when there is.
1894	*
1895	* The two values are typically indexed by a g_CpumHostFeatures bit.
1896	*
1897	* This is for instance used for the BSF & BSR instructions where AMD and
1898	* Intel CPUs produce different EFLAGS. */
1899	uint8_t aidxTargetCpuEflFlavour[2];
1900
1901	/** The CPU vendor. */
1902	CPUMCPUVENDOR enmCpuVendor;
1903	/** @} */
1904
1905	/** @name Host CPU information.
1906	* @{ */
1907	/** The CPU vendor. */
1908	CPUMCPUVENDOR enmHostCpuVendor;
1909	/** @} */
1910
1911	/** Counts RDMSR \#GP(0) LogRel(). */
1912	uint8_t cLogRelRdMsr;
1913	/** Counts WRMSR \#GP(0) LogRel(). */
1914	uint8_t cLogRelWrMsr;
1915	/** Alignment padding. */
1916	uint8_t abAlignment9[42];
1917
1918	/** @name Recompilation
1919	* @{ */
1920	/** Pointer to the current translation block.
1921	* This can either be one being executed or one being compiled. */
1922	R3PTRTYPE(PIEMTB) pCurTbR3;
1923	#ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
1924	/** Frame pointer for the last native TB to execute. */
1925	R3PTRTYPE(void *) pvTbFramePointerR3;
1926	#else
1927	R3PTRTYPE(void *) pvUnusedR3;
1928	#endif
1929	/** Fixed TB used for threaded recompilation.
1930	* This is allocated once with maxed-out sizes and re-used afterwards. */
1931	R3PTRTYPE(PIEMTB) pThrdCompileTbR3;
1932	/** Pointer to the ring-3 TB cache for this EMT. */
1933	R3PTRTYPE(PIEMTBCACHE) pTbCacheR3;
1934	/** Pointer to the ring-3 TB lookup entry.
1935	* This either points to pTbLookupEntryDummyR3 or an actually lookuptable
1936	* entry, thus it can always safely be used w/o NULL checking. */
1937	R3PTRTYPE(PIEMTB *) ppTbLookupEntryR3;
1938	/** The PC (RIP) at the start of pCurTbR3/pCurTbR0.
1939	* The TBs are based on physical addresses, so this is needed to correleated
1940	* RIP to opcode bytes stored in the TB (AMD-V / VT-x). */
1941	uint64_t uCurTbStartPc;
1942	/** Number of threaded TBs executed. */
1943	uint64_t cTbExecThreaded;
1944	/** Number of native TBs executed. */
1945	uint64_t cTbExecNative;
1946	/** Whether we need to check the opcode bytes for the current instruction.
1947	* This is set by a previous instruction if it modified memory or similar. */
1948	bool fTbCheckOpcodes;
1949	/** Indicates whether and how we just branched - IEMBRANCHED_F_XXX. */
1950	uint8_t fTbBranched;
1951	/** Set when GCPhysInstrBuf is updated because of a page crossing. */
1952	bool fTbCrossedPage;
1953	/** Whether to end the current TB. */
1954	bool fEndTb;
1955	/** Number of instructions before we need emit an IRQ check call again.
1956	* This helps making sure we don't execute too long w/o checking for
1957	* interrupts and immediately following instructions that may enable
1958	* interrupts (e.g. POPF, IRET, STI). With STI an additional hack is
1959	* required to make sure we check following the next instruction as well, see
1960	* fTbCurInstrIsSti. */
1961	uint8_t cInstrTillIrqCheck;
1962	/** Indicates that the current instruction is an STI. This is set by the
1963	* iemCImpl_sti code and subsequently cleared by the recompiler. */
1964	bool fTbCurInstrIsSti;
1965	/** The size of the IEMTB::pabOpcodes allocation in pThrdCompileTbR3. */
1966	uint16_t cbOpcodesAllocated;
1967	/** The current instruction number in a native TB.
1968	* This is set by code that may trigger an unexpected TB exit (throw/longjmp)
1969	* and will be picked up by the TB execution loop. Only used when
1970	* IEMNATIVE_WITH_INSTRUCTION_COUNTING is defined. */
1971	uint8_t idxTbCurInstr;
1972	/** Spaced reserved for recompiler data / alignment. */
1973	bool afRecompilerStuff1[3];
1974	/** The virtual sync time at the last timer poll call. */
1975	uint32_t msRecompilerPollNow;
1976	/** The IEMTB::cUsed value when to attempt native recompilation of a TB. */
1977	uint32_t uTbNativeRecompileAtUsedCount;
1978	/** The IEM_CIMPL_F_XXX mask for the current instruction. */
1979	uint32_t fTbCurInstr;
1980	/** The IEM_CIMPL_F_XXX mask for the previous instruction. */
1981	uint32_t fTbPrevInstr;
1982	/** Strict: Tracking skipped EFLAGS calculations. Any bits set here are
1983	* currently not up to date in EFLAGS. */
1984	uint32_t fSkippingEFlags;
1985	/** Previous GCPhysInstrBuf value - only valid if fTbCrossedPage is set. */
1986	RTGCPHYS GCPhysInstrBufPrev;
1987	/** Pointer to the ring-3 TB allocator for this EMT. */
1988	R3PTRTYPE(PIEMTBALLOCATOR) pTbAllocatorR3;
1989	/** Pointer to the ring-3 executable memory allocator for this EMT. */
1990	R3PTRTYPE(struct IEMEXECMEMALLOCATOR *) pExecMemAllocatorR3;
1991	/** Pointer to the native recompiler state for ring-3. */
1992	R3PTRTYPE(struct IEMRECOMPILERSTATE *) pNativeRecompilerStateR3;
1993	/** Dummy entry for ppTbLookupEntryR3. */
1994	R3PTRTYPE(PIEMTB) pTbLookupEntryDummyR3;
1995
1996	/** Dummy TLB entry used for accesses to pages with databreakpoints. */
1997	IEMTLBENTRY DataBreakpointTlbe;
1998
1999	/** Threaded TB statistics: Times TB execution was broken off before reaching the end. */
2000	STAMCOUNTER StatTbThreadedExecBreaks;
2001	/** Statistics: Times BltIn_CheckIrq breaks out of the TB. */
2002	STAMCOUNTER StatCheckIrqBreaks;
2003	/** Statistics: Times BltIn_CheckMode breaks out of the TB. */
2004	STAMCOUNTER StatCheckModeBreaks;
2005	/** Threaded TB statistics: Times execution break on call with lookup entries. */
2006	STAMCOUNTER StatTbThreadedExecBreaksWithLookup;
2007	/** Threaded TB statistics: Times execution break on call without lookup entries. */
2008	STAMCOUNTER StatTbThreadedExecBreaksWithoutLookup;
2009	/** Statistics: Times a post jump target check missed and had to find new TB. */
2010	STAMCOUNTER StatCheckBranchMisses;
2011	/** Statistics: Times a jump or page crossing required a TB with CS.LIM checking. */
2012	STAMCOUNTER StatCheckNeedCsLimChecking;
2013	/** Statistics: Times a loop was detected within a TB.. */
2014	STAMCOUNTER StatTbLoopInTbDetected;
2015	/** Exec memory allocator statistics: Number of times allocaintg executable memory failed. */
2016	STAMCOUNTER StatNativeExecMemInstrBufAllocFailed;
2017	/** Native TB statistics: Number of fully recompiled TBs. */
2018	STAMCOUNTER StatNativeFullyRecompiledTbs;
2019	/** TB statistics: Number of instructions per TB. */
2020	STAMPROFILE StatTbInstr;
2021	/** TB statistics: Number of TB lookup table entries per TB. */
2022	STAMPROFILE StatTbLookupEntries;
2023	/** Threaded TB statistics: Number of calls per TB. */
2024	STAMPROFILE StatTbThreadedCalls;
2025	/** Native TB statistics: Native code size per TB. */
2026	STAMPROFILE StatTbNativeCode;
2027	/** Native TB statistics: Profiling native recompilation. */
2028	STAMPROFILE StatNativeRecompilation;
2029	/** Native TB statistics: Number of calls per TB that were recompiled properly. */
2030	STAMPROFILE StatNativeCallsRecompiled;
2031	/** Native TB statistics: Number of threaded calls per TB that weren't recompiled. */
2032	STAMPROFILE StatNativeCallsThreaded;
2033	/** Native recompiled execution: TLB hits for data fetches. */
2034	STAMCOUNTER StatNativeTlbHitsForFetch;
2035	/** Native recompiled execution: TLB hits for data stores. */
2036	STAMCOUNTER StatNativeTlbHitsForStore;
2037	/** Native recompiled execution: TLB hits for stack accesses. */
2038	STAMCOUNTER StatNativeTlbHitsForStack;
2039	/** Native recompiled execution: TLB hits for mapped accesses. */
2040	STAMCOUNTER StatNativeTlbHitsForMapped;
2041	/** Native recompiled execution: Code TLB misses for new page. */
2042	STAMCOUNTER StatNativeCodeTlbMissesNewPage;
2043	/** Native recompiled execution: Code TLB hits for new page. */
2044	STAMCOUNTER StatNativeCodeTlbHitsForNewPage;
2045	/** Native recompiled execution: Code TLB misses for new page with offset. */
2046	STAMCOUNTER StatNativeCodeTlbMissesNewPageWithOffset;
2047	/** Native recompiled execution: Code TLB hits for new page with offset. */
2048	STAMCOUNTER StatNativeCodeTlbHitsForNewPageWithOffset;
2049
2050	/** Native recompiler: Number of calls to iemNativeRegAllocFindFree. */
2051	STAMCOUNTER StatNativeRegFindFree;
2052	/** Native recompiler: Number of times iemNativeRegAllocFindFree needed
2053	* to free a variable. */
2054	STAMCOUNTER StatNativeRegFindFreeVar;
2055	/** Native recompiler: Number of times iemNativeRegAllocFindFree did
2056	* not need to free any variables. */
2057	STAMCOUNTER StatNativeRegFindFreeNoVar;
2058	/** Native recompiler: Liveness info freed shadowed guest registers in
2059	* iemNativeRegAllocFindFree. */
2060	STAMCOUNTER StatNativeRegFindFreeLivenessUnshadowed;
2061	/** Native recompiler: Liveness info helped with the allocation in
2062	* iemNativeRegAllocFindFree. */
2063	STAMCOUNTER StatNativeRegFindFreeLivenessHelped;
2064
2065	/** Native recompiler: Number of times status flags calc has been skipped. */
2066	STAMCOUNTER StatNativeEflSkippedArithmetic;
2067	/** Native recompiler: Number of times status flags calc has been skipped. */
2068	STAMCOUNTER StatNativeEflSkippedLogical;
2069
2070	/** Native recompiler: Number of opportunities to skip EFLAGS.CF updating. */
2071	STAMCOUNTER StatNativeLivenessEflCfSkippable;
2072	/** Native recompiler: Number of opportunities to skip EFLAGS.PF updating. */
2073	STAMCOUNTER StatNativeLivenessEflPfSkippable;
2074	/** Native recompiler: Number of opportunities to skip EFLAGS.AF updating. */
2075	STAMCOUNTER StatNativeLivenessEflAfSkippable;
2076	/** Native recompiler: Number of opportunities to skip EFLAGS.ZF updating. */
2077	STAMCOUNTER StatNativeLivenessEflZfSkippable;
2078	/** Native recompiler: Number of opportunities to skip EFLAGS.SF updating. */
2079	STAMCOUNTER StatNativeLivenessEflSfSkippable;
2080	/** Native recompiler: Number of opportunities to skip EFLAGS.OF updating. */
2081	STAMCOUNTER StatNativeLivenessEflOfSkippable;
2082	/** Native recompiler: Number of required EFLAGS.CF updates. */
2083	STAMCOUNTER StatNativeLivenessEflCfRequired;
2084	/** Native recompiler: Number of required EFLAGS.PF updates. */
2085	STAMCOUNTER StatNativeLivenessEflPfRequired;
2086	/** Native recompiler: Number of required EFLAGS.AF updates. */
2087	STAMCOUNTER StatNativeLivenessEflAfRequired;
2088	/** Native recompiler: Number of required EFLAGS.ZF updates. */
2089	STAMCOUNTER StatNativeLivenessEflZfRequired;
2090	/** Native recompiler: Number of required EFLAGS.SF updates. */
2091	STAMCOUNTER StatNativeLivenessEflSfRequired;
2092	/** Native recompiler: Number of required EFLAGS.OF updates. */
2093	STAMCOUNTER StatNativeLivenessEflOfRequired;
2094	/** Native recompiler: Number of potentially delayable EFLAGS.CF updates. */
2095	STAMCOUNTER StatNativeLivenessEflCfDelayable;
2096	/** Native recompiler: Number of potentially delayable EFLAGS.PF updates. */
2097	STAMCOUNTER StatNativeLivenessEflPfDelayable;
2098	/** Native recompiler: Number of potentially delayable EFLAGS.AF updates. */
2099	STAMCOUNTER StatNativeLivenessEflAfDelayable;
2100	/** Native recompiler: Number of potentially delayable EFLAGS.ZF updates. */
2101	STAMCOUNTER StatNativeLivenessEflZfDelayable;
2102	/** Native recompiler: Number of potentially delayable EFLAGS.SF updates. */
2103	STAMCOUNTER StatNativeLivenessEflSfDelayable;
2104	/** Native recompiler: Number of potentially delayable EFLAGS.OF updates. */
2105	STAMCOUNTER StatNativeLivenessEflOfDelayable;
2106
2107	/** Native recompiler: Number of potential PC updates in total. */
2108	STAMCOUNTER StatNativePcUpdateTotal;
2109	/** Native recompiler: Number of PC updates which could be delayed. */
2110	STAMCOUNTER StatNativePcUpdateDelayed;
2111
2112	//#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
2113	/** Native recompiler: Number of calls to iemNativeSimdRegAllocFindFree. */
2114	STAMCOUNTER StatNativeSimdRegFindFree;
2115	/** Native recompiler: Number of times iemNativeSimdRegAllocFindFree needed
2116	* to free a variable. */
2117	STAMCOUNTER StatNativeSimdRegFindFreeVar;
2118	/** Native recompiler: Number of times iemNativeSimdRegAllocFindFree did
2119	* not need to free any variables. */
2120	STAMCOUNTER StatNativeSimdRegFindFreeNoVar;
2121	/** Native recompiler: Liveness info freed shadowed guest registers in
2122	* iemNativeSimdRegAllocFindFree. */
2123	STAMCOUNTER StatNativeSimdRegFindFreeLivenessUnshadowed;
2124	/** Native recompiler: Liveness info helped with the allocation in
2125	* iemNativeSimdRegAllocFindFree. */
2126	STAMCOUNTER StatNativeSimdRegFindFreeLivenessHelped;
2127
2128	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() checks. */
2129	STAMCOUNTER StatNativeMaybeDeviceNotAvailXcptCheckPotential;
2130	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() checks. */
2131	STAMCOUNTER StatNativeMaybeWaitDeviceNotAvailXcptCheckPotential;
2132	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() checks. */
2133	STAMCOUNTER StatNativeMaybeSseXcptCheckPotential;
2134	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() checks. */
2135	STAMCOUNTER StatNativeMaybeAvxXcptCheckPotential;
2136
2137	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() checks omitted. */
2138	STAMCOUNTER StatNativeMaybeDeviceNotAvailXcptCheckOmitted;
2139	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() checks omitted. */
2140	STAMCOUNTER StatNativeMaybeWaitDeviceNotAvailXcptCheckOmitted;
2141	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() checks omitted. */
2142	STAMCOUNTER StatNativeMaybeSseXcptCheckOmitted;
2143	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() checks omitted. */
2144	STAMCOUNTER StatNativeMaybeAvxXcptCheckOmitted;
2145	//#endif
2146
2147	/** Native recompiler: The TB finished executing completely without jumping to a an exit label.
2148	* Not availabe in release builds. */
2149	STAMCOUNTER StatNativeTbFinished;
2150	/** Native recompiler: The TB finished executing jumping to the ReturnBreak label. */
2151	STAMCOUNTER StatNativeTbExitReturnBreak;
2152	/** Native recompiler: The TB finished executing jumping to the ReturnBreakFF label. */
2153	STAMCOUNTER StatNativeTbExitReturnBreakFF;
2154	/** Native recompiler: The TB finished executing jumping to the ReturnWithFlags label. */
2155	STAMCOUNTER StatNativeTbExitReturnWithFlags;
2156	/** Native recompiler: The TB finished executing with other non-zero status. */
2157	STAMCOUNTER StatNativeTbExitReturnOtherStatus;
2158	/** Native recompiler: The TB finished executing via throw / long jump. */
2159	STAMCOUNTER StatNativeTbExitLongJump;
2160	/** Native recompiler: The TB finished executing jumping to the ReturnBreak
2161	* label, but directly jumped to the next TB, scenario \#1 w/o IRQ checks. */
2162	STAMCOUNTER StatNativeTbExitDirectLinking1NoIrq;
2163	/** Native recompiler: The TB finished executing jumping to the ReturnBreak
2164	* label, but directly jumped to the next TB, scenario \#1 with IRQ checks. */
2165	STAMCOUNTER StatNativeTbExitDirectLinking1Irq;
2166	/** Native recompiler: The TB finished executing jumping to the ReturnBreak
2167	* label, but directly jumped to the next TB, scenario \#1 w/o IRQ checks. */
2168	STAMCOUNTER StatNativeTbExitDirectLinking2NoIrq;
2169	/** Native recompiler: The TB finished executing jumping to the ReturnBreak
2170	* label, but directly jumped to the next TB, scenario \#2 with IRQ checks. */
2171	STAMCOUNTER StatNativeTbExitDirectLinking2Irq;
2172
2173	/** Native recompiler: The TB finished executing jumping to the RaiseDe label. */
2174	STAMCOUNTER StatNativeTbExitRaiseDe;
2175	/** Native recompiler: The TB finished executing jumping to the RaiseUd label. */
2176	STAMCOUNTER StatNativeTbExitRaiseUd;
2177	/** Native recompiler: The TB finished executing jumping to the RaiseSseRelated label. */
2178	STAMCOUNTER StatNativeTbExitRaiseSseRelated;
2179	/** Native recompiler: The TB finished executing jumping to the RaiseAvxRelated label. */
2180	STAMCOUNTER StatNativeTbExitRaiseAvxRelated;
2181	/** Native recompiler: The TB finished executing jumping to the RaiseSseAvxFpRelated label. */
2182	STAMCOUNTER StatNativeTbExitRaiseSseAvxFpRelated;
2183	/** Native recompiler: The TB finished executing jumping to the RaiseNm label. */
2184	STAMCOUNTER StatNativeTbExitRaiseNm;
2185	/** Native recompiler: The TB finished executing jumping to the RaiseGp0 label. */
2186	STAMCOUNTER StatNativeTbExitRaiseGp0;
2187	/** Native recompiler: The TB finished executing jumping to the RaiseMf label. */
2188	STAMCOUNTER StatNativeTbExitRaiseMf;
2189	/** Native recompiler: The TB finished executing jumping to the RaiseXf label. */
2190	STAMCOUNTER StatNativeTbExitRaiseXf;
2191	/** Native recompiler: The TB finished executing jumping to the ObsoleteTb label. */
2192	STAMCOUNTER StatNativeTbExitObsoleteTb;
2193
2194	/** Native recompiler: Failure situations with direct linking scenario \#1.
2195	* Counter with StatNativeTbExitReturnBreak. Not in release builds.
2196	* @{ */
2197	STAMCOUNTER StatNativeTbExitDirectLinking1NoTb;
2198	STAMCOUNTER StatNativeTbExitDirectLinking1MismatchGCPhysPc;
2199	STAMCOUNTER StatNativeTbExitDirectLinking1MismatchFlags;
2200	STAMCOUNTER StatNativeTbExitDirectLinking1PendingIrq;
2201	/** @} */
2202
2203	/** Native recompiler: Failure situations with direct linking scenario \#2.
2204	* Counter with StatNativeTbExitReturnBreak. Not in release builds.
2205	* @{ */
2206	STAMCOUNTER StatNativeTbExitDirectLinking2NoTb;
2207	STAMCOUNTER StatNativeTbExitDirectLinking2MismatchGCPhysPc;
2208	STAMCOUNTER StatNativeTbExitDirectLinking2MismatchFlags;
2209	STAMCOUNTER StatNativeTbExitDirectLinking2PendingIrq;
2210	/** @} */
2211
2212	/** iemMemMap and iemMemMapJmp statistics.
2213	* @{ */
2214	STAMCOUNTER StatMemMapJmp;
2215	STAMCOUNTER StatMemMapNoJmp;
2216	STAMCOUNTER StatMemBounceBufferCrossPage;
2217	STAMCOUNTER StatMemBounceBufferMapPhys;
2218	/** @} */
2219
2220	uint64_t au64Padding[5];
2221	/** @} */
2222
2223	/** Data TLB.
2224	* @remarks Must be 64-byte aligned. */
2225	IEMTLB DataTlb;
2226	/** Instruction TLB.
2227	* @remarks Must be 64-byte aligned. */
2228	IEMTLB CodeTlb;
2229
2230	/** Exception statistics. */
2231	STAMCOUNTER aStatXcpts[32];
2232	/** Interrupt statistics. */
2233	uint32_t aStatInts[256];
2234
2235	#if defined(VBOX_WITH_STATISTICS) && !defined(DOXYGEN_RUNNING) && !defined(IEM_WITHOUT_INSTRUCTION_STATS)
2236	/** Instruction statistics for ring-0/raw-mode. */
2237	IEMINSTRSTATS StatsRZ;
2238	/** Instruction statistics for ring-3. */
2239	IEMINSTRSTATS StatsR3;
2240	# ifdef VBOX_WITH_IEM_RECOMPILER
2241	/** Statistics per threaded function call.
2242	* Updated by both the threaded and native recompilers. */
2243	uint32_t acThreadedFuncStats[0x6000 /24576/];
2244	# endif
2245	#endif
2246	} IEMCPU;
2247	AssertCompileMemberOffset(IEMCPU, cActiveMappings, 0x4f);
2248	AssertCompileMemberAlignment(IEMCPU, aMemMappings, 16);
2249	AssertCompileMemberAlignment(IEMCPU, aMemMappingLocks, 16);
2250	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 64);
2251	AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
2252	AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
2253
2254	/** Pointer to the per-CPU IEM state. */
2255	typedef IEMCPU *PIEMCPU;
2256	/** Pointer to the const per-CPU IEM state. */
2257	typedef IEMCPU const *PCIEMCPU;
2258
2259
2260	/** @def IEM_GET_CTX
2261	* Gets the guest CPU context for the calling EMT.
2262	* @returns PCPUMCTX
2263	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2264	*/
2265	#define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
2266
2267	/** @def IEM_CTX_ASSERT
2268	* Asserts that the @a a_fExtrnMbz is present in the CPU context.
2269	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2270	* @param a_fExtrnMbz The mask of CPUMCTX_EXTRN_XXX flags that must be zero.
2271	*/
2272	#define IEM_CTX_ASSERT(a_pVCpu, a_fExtrnMbz) \
2273	AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
2274	("fExtrn=%#RX64 & fExtrnMbz=%#RX64 -> %#RX64\n", \
2275	(a_pVCpu)->cpum.GstCtx.fExtrn, (a_fExtrnMbz), (a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz) ))
2276
2277	/** @def IEM_CTX_IMPORT_RET
2278	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
2279	*
2280	* Will call the keep to import the bits as needed.
2281	*
2282	* Returns on import failure.
2283	*
2284	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2285	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
2286	*/
2287	#define IEM_CTX_IMPORT_RET(a_pVCpu, a_fExtrnImport) \
2288	do { \
2289	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
2290	{ /* likely */ } \
2291	else \
2292	{ \
2293	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
2294	AssertRCReturn(rcCtxImport, rcCtxImport); \
2295	} \
2296	} while (0)
2297
2298	/** @def IEM_CTX_IMPORT_NORET
2299	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
2300	*
2301	* Will call the keep to import the bits as needed.
2302	*
2303	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2304	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
2305	*/
2306	#define IEM_CTX_IMPORT_NORET(a_pVCpu, a_fExtrnImport) \
2307	do { \
2308	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
2309	{ /* likely */ } \
2310	else \
2311	{ \
2312	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
2313	AssertLogRelRC(rcCtxImport); \
2314	} \
2315	} while (0)
2316
2317	/** @def IEM_CTX_IMPORT_JMP
2318	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
2319	*
2320	* Will call the keep to import the bits as needed.
2321	*
2322	* Jumps on import failure.
2323	*
2324	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2325	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
2326	*/
2327	#define IEM_CTX_IMPORT_JMP(a_pVCpu, a_fExtrnImport) \
2328	do { \
2329	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
2330	{ /* likely */ } \
2331	else \
2332	{ \
2333	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
2334	AssertRCStmt(rcCtxImport, IEM_DO_LONGJMP(pVCpu, rcCtxImport)); \
2335	} \
2336	} while (0)
2337
2338
2339
2340	/** @def IEM_GET_TARGET_CPU
2341	* Gets the current IEMTARGETCPU value.
2342	* @returns IEMTARGETCPU value.
2343	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2344	*/
2345	#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
2346	# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
2347	#else
2348	# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
2349	#endif
2350
2351	/** @def IEM_GET_INSTR_LEN
2352	* Gets the instruction length. */
2353	#ifdef IEM_WITH_CODE_TLB
2354	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
2355	#else
2356	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
2357	#endif
2358
2359	/** @def IEM_TRY_SETJMP
2360	* Wrapper around setjmp / try, hiding all the ugly differences.
2361	*
2362	* @note Use with extreme care as this is a fragile macro.
2363	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2364	* @param a_rcTarget The variable that should receive the status code in case
2365	* of a longjmp/throw.
2366	*/
2367	/** @def IEM_TRY_SETJMP_AGAIN
2368	* For when setjmp / try is used again in the same variable scope as a previous
2369	* IEM_TRY_SETJMP invocation.
2370	*/
2371	/** @def IEM_CATCH_LONGJMP_BEGIN
2372	* Start wrapper for catch / setjmp-else.
2373	*
2374	* This will set up a scope.
2375	*
2376	* @note Use with extreme care as this is a fragile macro.
2377	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2378	* @param a_rcTarget The variable that should receive the status code in case
2379	* of a longjmp/throw.
2380	*/
2381	/** @def IEM_CATCH_LONGJMP_END
2382	* End wrapper for catch / setjmp-else.
2383	*
2384	* This will close the scope set up by IEM_CATCH_LONGJMP_BEGIN and clean up the
2385	* state.
2386	*
2387	* @note Use with extreme care as this is a fragile macro.
2388	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2389	*/
2390	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
2391	# ifdef IEM_WITH_THROW_CATCH
2392	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
2393	a_rcTarget = VINF_SUCCESS; \
2394	try
2395	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
2396	IEM_TRY_SETJMP(a_pVCpu, a_rcTarget)
2397	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
2398	catch (int rcThrown) \
2399	{ \
2400	a_rcTarget = rcThrown
2401	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
2402	} \
2403	((void)0)
2404	# else /* !IEM_WITH_THROW_CATCH */
2405	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
2406	jmp_buf JmpBuf; \
2407	jmp_buf * volatile pSavedJmpBuf = (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf); \
2408	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
2409	if ((rcStrict = setjmp(JmpBuf)) == 0)
2410	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
2411	pSavedJmpBuf = (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf); \
2412	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
2413	if ((rcStrict = setjmp(JmpBuf)) == 0)
2414	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
2415	else \
2416	{ \
2417	((void)0)
2418	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
2419	} \
2420	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = pSavedJmpBuf
2421	# endif /* !IEM_WITH_THROW_CATCH */
2422	#endif /* IEM_WITH_SETJMP */
2423
2424
2425	/**
2426	* Shared per-VM IEM data.
2427	*/
2428	typedef struct IEM
2429	{
2430	/** The VMX APIC-access page handler type. */
2431	PGMPHYSHANDLERTYPE hVmxApicAccessPage;
2432	#ifndef VBOX_WITHOUT_CPUID_HOST_CALL
2433	/** Set if the CPUID host call functionality is enabled. */
2434	bool fCpuIdHostCall;
2435	#endif
2436	} IEM;
2437
2438
2439
2440	/** @name IEM_ACCESS_XXX - Access details.
2441	* @{ */
2442	#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
2443	#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
2444	#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
2445	#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
2446	#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
2447	#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
2448	#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
2449	#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
2450	#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
2451	#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
2452	/** The writes are partial, so if initialize the bounce buffer with the
2453	* orignal RAM content. */
2454	#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
2455	/** Used in aMemMappings to indicate that the entry is bounce buffered. */
2456	#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
2457	/** Bounce buffer with ring-3 write pending, first page. */
2458	#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
2459	/** Bounce buffer with ring-3 write pending, second page. */
2460	#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
2461	/** Not locked, accessed via the TLB. */
2462	#define IEM_ACCESS_NOT_LOCKED UINT32_C(0x00001000)
2463	/** Atomic access.
2464	* This enables special alignment checks and the VINF_EM_EMULATE_SPLIT_LOCK
2465	* fallback for misaligned stuff. See @bugref{10547}. */
2466	#define IEM_ACCESS_ATOMIC UINT32_C(0x00002000)
2467	/** Valid bit mask. */
2468	#define IEM_ACCESS_VALID_MASK UINT32_C(0x00003fff)
2469	/** Shift count for the TLB flags (upper word). */
2470	#define IEM_ACCESS_SHIFT_TLB_FLAGS 16
2471
2472	/** Atomic read+write data alias. */
2473	#define IEM_ACCESS_DATA_ATOMIC (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA \| IEM_ACCESS_ATOMIC)
2474	/** Read+write data alias. */
2475	#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
2476	/** Write data alias. */
2477	#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
2478	/** Read data alias. */
2479	#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_DATA)
2480	/** Instruction fetch alias. */
2481	#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_WHAT_CODE)
2482	/** Stack write alias. */
2483	#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
2484	/** Stack read alias. */
2485	#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_STACK)
2486	/** Stack read+write alias. */
2487	#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
2488	/** Read system table alias. */
2489	#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_SYS)
2490	/** Read+write system table alias. */
2491	#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_SYS)
2492	/** @} */
2493
2494	/** @name Prefix constants (IEMCPU::fPrefixes)
2495	* @{ */
2496	#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /*< CS segment prefix (0x2e). /
2497	#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /*< SS segment prefix (0x36). /
2498	#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /*< DS segment prefix (0x3e). /
2499	#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /*< ES segment prefix (0x26). /
2500	#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /*< FS segment prefix (0x64). /
2501	#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /*< GS segment prefix (0x65). /
2502	#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
2503
2504	#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /*< Operand size prefix (0x66). /
2505	#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /*< REX.W prefix (0x48-0x4f). /
2506	#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /*< Address size prefix (0x67). /
2507
2508	#define IEM_OP_PRF_LOCK RT_BIT_32(16) /*< Lock prefix (0xf0). /
2509	#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /*< Repeat-not-zero prefix (0xf2). /
2510	#define IEM_OP_PRF_REPZ RT_BIT_32(18) /*< Repeat-if-zero prefix (0xf3). /
2511
2512	#define IEM_OP_PRF_REX RT_BIT_32(24) /*< Any REX prefix (0x40-0x4f). /
2513	#define IEM_OP_PRF_REX_B RT_BIT_32(25) /*< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). /
2514	#define IEM_OP_PRF_REX_X RT_BIT_32(26) /*< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). /
2515	#define IEM_OP_PRF_REX_R RT_BIT_32(27) /*< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). /
2516	/** Mask with all the REX prefix flags.
2517	* This is generally for use when needing to undo the REX prefixes when they
2518	* are followed legacy prefixes and therefore does not immediately preceed
2519	* the first opcode byte.
2520	* For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
2521	#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX \| IEM_OP_PRF_REX_R \| IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X \| IEM_OP_PRF_SIZE_REX_W )
2522
2523	#define IEM_OP_PRF_VEX RT_BIT_32(28) /*< Indiciates VEX prefix. /
2524	#define IEM_OP_PRF_EVEX RT_BIT_32(29) /*< Indiciates EVEX prefix. /
2525	#define IEM_OP_PRF_XOP RT_BIT_32(30) /*< Indiciates XOP prefix. /
2526	/** @} */
2527
2528	/** @name IEMOPFORM_XXX - Opcode forms
2529	* @note These are ORed together with IEMOPHINT_XXX.
2530	* @{ */
2531	/** ModR/M: reg, r/m */
2532	#define IEMOPFORM_RM 0
2533	/** ModR/M: reg, r/m (register) */
2534	#define IEMOPFORM_RM_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
2535	/** ModR/M: reg, r/m (memory) */
2536	#define IEMOPFORM_RM_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
2537	/** ModR/M: reg, r/m, imm */
2538	#define IEMOPFORM_RMI 1
2539	/** ModR/M: reg, r/m (register), imm */
2540	#define IEMOPFORM_RMI_REG (IEMOPFORM_RMI \| IEMOPFORM_MOD3)
2541	/** ModR/M: reg, r/m (memory), imm */
2542	#define IEMOPFORM_RMI_MEM (IEMOPFORM_RMI \| IEMOPFORM_NOT_MOD3)
2543	/** ModR/M: reg, r/m, xmm0 */
2544	#define IEMOPFORM_RM0 2
2545	/** ModR/M: reg, r/m (register), xmm0 */
2546	#define IEMOPFORM_RM0_REG (IEMOPFORM_RM0 \| IEMOPFORM_MOD3)
2547	/** ModR/M: reg, r/m (memory), xmm0 */
2548	#define IEMOPFORM_RM0_MEM (IEMOPFORM_RM0 \| IEMOPFORM_NOT_MOD3)
2549	/** ModR/M: r/m, reg */
2550	#define IEMOPFORM_MR 3
2551	/** ModR/M: r/m (register), reg */
2552	#define IEMOPFORM_MR_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
2553	/** ModR/M: r/m (memory), reg */
2554	#define IEMOPFORM_MR_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
2555	/** ModR/M: r/m, reg, imm */
2556	#define IEMOPFORM_MRI 4
2557	/** ModR/M: r/m (register), reg, imm */
2558	#define IEMOPFORM_MRI_REG (IEMOPFORM_MRI \| IEMOPFORM_MOD3)
2559	/** ModR/M: r/m (memory), reg, imm */
2560	#define IEMOPFORM_MRI_MEM (IEMOPFORM_MRI \| IEMOPFORM_NOT_MOD3)
2561	/** ModR/M: r/m only */
2562	#define IEMOPFORM_M 5
2563	/** ModR/M: r/m only (register). */
2564	#define IEMOPFORM_M_REG (IEMOPFORM_M \| IEMOPFORM_MOD3)
2565	/** ModR/M: r/m only (memory). */
2566	#define IEMOPFORM_M_MEM (IEMOPFORM_M \| IEMOPFORM_NOT_MOD3)
2567	/** ModR/M: r/m, imm */
2568	#define IEMOPFORM_MI 6
2569	/** ModR/M: r/m (register), imm */
2570	#define IEMOPFORM_MI_REG (IEMOPFORM_MI \| IEMOPFORM_MOD3)
2571	/** ModR/M: r/m (memory), imm */
2572	#define IEMOPFORM_MI_MEM (IEMOPFORM_MI \| IEMOPFORM_NOT_MOD3)
2573	/** ModR/M: r/m, 1 (shift and rotate instructions) */
2574	#define IEMOPFORM_M1 7
2575	/** ModR/M: r/m (register), 1. */
2576	#define IEMOPFORM_M1_REG (IEMOPFORM_M1 \| IEMOPFORM_MOD3)
2577	/** ModR/M: r/m (memory), 1. */
2578	#define IEMOPFORM_M1_MEM (IEMOPFORM_M1 \| IEMOPFORM_NOT_MOD3)
2579	/** ModR/M: r/m, CL (shift and rotate instructions)
2580	* @todo This should just've been a generic fixed register. But the python
2581	* code doesn't needs more convincing. */
2582	#define IEMOPFORM_M_CL 8
2583	/** ModR/M: r/m (register), CL. */
2584	#define IEMOPFORM_M_CL_REG (IEMOPFORM_M_CL \| IEMOPFORM_MOD3)
2585	/** ModR/M: r/m (memory), CL. */
2586	#define IEMOPFORM_M_CL_MEM (IEMOPFORM_M_CL \| IEMOPFORM_NOT_MOD3)
2587	/** ModR/M: reg only */
2588	#define IEMOPFORM_R 9
2589
2590	/** VEX+ModR/M: reg, r/m */
2591	#define IEMOPFORM_VEX_RM 16
2592	/** VEX+ModR/M: reg, r/m (register) */
2593	#define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM \| IEMOPFORM_MOD3)
2594	/** VEX+ModR/M: reg, r/m (memory) */
2595	#define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM \| IEMOPFORM_NOT_MOD3)
2596	/** VEX+ModR/M: r/m, reg */
2597	#define IEMOPFORM_VEX_MR 17
2598	/** VEX+ModR/M: r/m (register), reg */
2599	#define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR \| IEMOPFORM_MOD3)
2600	/** VEX+ModR/M: r/m (memory), reg */
2601	#define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR \| IEMOPFORM_NOT_MOD3)
2602	/** VEX+ModR/M: r/m, reg, imm8 */
2603	#define IEMOPFORM_VEX_MRI 18
2604	/** VEX+ModR/M: r/m (register), reg, imm8 */
2605	#define IEMOPFORM_VEX_MRI_REG (IEMOPFORM_VEX_MRI \| IEMOPFORM_MOD3)
2606	/** VEX+ModR/M: r/m (memory), reg, imm8 */
2607	#define IEMOPFORM_VEX_MRI_MEM (IEMOPFORM_VEX_MRI \| IEMOPFORM_NOT_MOD3)
2608	/** VEX+ModR/M: r/m only */
2609	#define IEMOPFORM_VEX_M 19
2610	/** VEX+ModR/M: r/m only (register). */
2611	#define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M \| IEMOPFORM_MOD3)
2612	/** VEX+ModR/M: r/m only (memory). */
2613	#define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M \| IEMOPFORM_NOT_MOD3)
2614	/** VEX+ModR/M: reg only */
2615	#define IEMOPFORM_VEX_R 20
2616	/** VEX+ModR/M: reg, vvvv, r/m */
2617	#define IEMOPFORM_VEX_RVM 21
2618	/** VEX+ModR/M: reg, vvvv, r/m (register). */
2619	#define IEMOPFORM_VEX_RVM_REG (IEMOPFORM_VEX_RVM \| IEMOPFORM_MOD3)
2620	/** VEX+ModR/M: reg, vvvv, r/m (memory). */
2621	#define IEMOPFORM_VEX_RVM_MEM (IEMOPFORM_VEX_RVM \| IEMOPFORM_NOT_MOD3)
2622	/** VEX+ModR/M: reg, vvvv, r/m, imm */
2623	#define IEMOPFORM_VEX_RVMI 22
2624	/** VEX+ModR/M: reg, vvvv, r/m (register), imm. */
2625	#define IEMOPFORM_VEX_RVMI_REG (IEMOPFORM_VEX_RVMI \| IEMOPFORM_MOD3)
2626	/** VEX+ModR/M: reg, vvvv, r/m (memory), imm. */
2627	#define IEMOPFORM_VEX_RVMI_MEM (IEMOPFORM_VEX_RVMI \| IEMOPFORM_NOT_MOD3)
2628	/** VEX+ModR/M: reg, vvvv, r/m, imm(reg) */
2629	#define IEMOPFORM_VEX_RVMR 23
2630	/** VEX+ModR/M: reg, vvvv, r/m (register), imm(reg). */
2631	#define IEMOPFORM_VEX_RVMR_REG (IEMOPFORM_VEX_RVMI \| IEMOPFORM_MOD3)
2632	/** VEX+ModR/M: reg, vvvv, r/m (memory), imm(reg). */
2633	#define IEMOPFORM_VEX_RVMR_MEM (IEMOPFORM_VEX_RVMI \| IEMOPFORM_NOT_MOD3)
2634	/** VEX+ModR/M: reg, r/m, vvvv */
2635	#define IEMOPFORM_VEX_RMV 24
2636	/** VEX+ModR/M: reg, r/m, vvvv (register). */
2637	#define IEMOPFORM_VEX_RMV_REG (IEMOPFORM_VEX_RMV \| IEMOPFORM_MOD3)
2638	/** VEX+ModR/M: reg, r/m, vvvv (memory). */
2639	#define IEMOPFORM_VEX_RMV_MEM (IEMOPFORM_VEX_RMV \| IEMOPFORM_NOT_MOD3)
2640	/** VEX+ModR/M: reg, r/m, imm8 */
2641	#define IEMOPFORM_VEX_RMI 25
2642	/** VEX+ModR/M: reg, r/m, imm8 (register). */
2643	#define IEMOPFORM_VEX_RMI_REG (IEMOPFORM_VEX_RMI \| IEMOPFORM_MOD3)
2644	/** VEX+ModR/M: reg, r/m, imm8 (memory). */
2645	#define IEMOPFORM_VEX_RMI_MEM (IEMOPFORM_VEX_RMI \| IEMOPFORM_NOT_MOD3)
2646	/** VEX+ModR/M: r/m, vvvv, reg */
2647	#define IEMOPFORM_VEX_MVR 26
2648	/** VEX+ModR/M: r/m, vvvv, reg (register) */
2649	#define IEMOPFORM_VEX_MVR_REG (IEMOPFORM_VEX_MVR \| IEMOPFORM_MOD3)
2650	/** VEX+ModR/M: r/m, vvvv, reg (memory) */
2651	#define IEMOPFORM_VEX_MVR_MEM (IEMOPFORM_VEX_MVR \| IEMOPFORM_NOT_MOD3)
2652	/** VEX+ModR/M+/n: vvvv, r/m */
2653	#define IEMOPFORM_VEX_VM 27
2654	/** VEX+ModR/M+/n: vvvv, r/m (register) */
2655	#define IEMOPFORM_VEX_VM_REG (IEMOPFORM_VEX_VM \| IEMOPFORM_MOD3)
2656	/** VEX+ModR/M+/n: vvvv, r/m (memory) */
2657	#define IEMOPFORM_VEX_VM_MEM (IEMOPFORM_VEX_VM \| IEMOPFORM_NOT_MOD3)
2658	/** VEX+ModR/M+/n: vvvv, r/m, imm8 */
2659	#define IEMOPFORM_VEX_VMI 28
2660	/** VEX+ModR/M+/n: vvvv, r/m, imm8 (register) */
2661	#define IEMOPFORM_VEX_VMI_REG (IEMOPFORM_VEX_VMI \| IEMOPFORM_MOD3)
2662	/** VEX+ModR/M+/n: vvvv, r/m, imm8 (memory) */
2663	#define IEMOPFORM_VEX_VMI_MEM (IEMOPFORM_VEX_VMI \| IEMOPFORM_NOT_MOD3)
2664
2665	/** Fixed register instruction, no R/M. */
2666	#define IEMOPFORM_FIXED 32
2667
2668	/** The r/m is a register. */
2669	#define IEMOPFORM_MOD3 RT_BIT_32(8)
2670	/** The r/m is a memory access. */
2671	#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
2672	/** @} */
2673
2674	/** @name IEMOPHINT_XXX - Additional Opcode Hints
2675	* @note These are ORed together with IEMOPFORM_XXX.
2676	* @{ */
2677	/** Ignores the operand size prefix (66h). */
2678	#define IEMOPHINT_IGNORES_OZ_PFX RT_BIT_32(10)
2679	/** Ignores REX.W (aka WIG). */
2680	#define IEMOPHINT_IGNORES_REXW RT_BIT_32(11)
2681	/** Both the operand size prefixes (66h + REX.W) are ignored. */
2682	#define IEMOPHINT_IGNORES_OP_SIZES (IEMOPHINT_IGNORES_OZ_PFX \| IEMOPHINT_IGNORES_REXW)
2683	/** Allowed with the lock prefix. */
2684	#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
2685	/** The VEX.L value is ignored (aka LIG). */
2686	#define IEMOPHINT_VEX_L_IGNORED RT_BIT_32(12)
2687	/** The VEX.L value must be zero (i.e. 128-bit width only). */
2688	#define IEMOPHINT_VEX_L_ZERO RT_BIT_32(13)
2689	/** The VEX.L value must be one (i.e. 256-bit width only). */
2690	#define IEMOPHINT_VEX_L_ONE RT_BIT_32(14)
2691	/** The VEX.V value must be zero. */
2692	#define IEMOPHINT_VEX_V_ZERO RT_BIT_32(15)
2693	/** The REX.W/VEX.V value must be zero. */
2694	#define IEMOPHINT_REX_W_ZERO RT_BIT_32(16)
2695	#define IEMOPHINT_VEX_W_ZERO IEMOPHINT_REX_W_ZERO
2696	/** The REX.W/VEX.V value must be one. */
2697	#define IEMOPHINT_REX_W_ONE RT_BIT_32(17)
2698	#define IEMOPHINT_VEX_W_ONE IEMOPHINT_REX_W_ONE
2699
2700	/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
2701	#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
2702	/** @} */
2703
2704	/**
2705	* Possible hardware task switch sources.
2706	*/
2707	typedef enum IEMTASKSWITCH
2708	{
2709	/** Task switch caused by an interrupt/exception. */
2710	IEMTASKSWITCH_INT_XCPT = 1,
2711	/** Task switch caused by a far CALL. */
2712	IEMTASKSWITCH_CALL,
2713	/** Task switch caused by a far JMP. */
2714	IEMTASKSWITCH_JUMP,
2715	/** Task switch caused by an IRET. */
2716	IEMTASKSWITCH_IRET
2717	} IEMTASKSWITCH;
2718	AssertCompileSize(IEMTASKSWITCH, 4);
2719
2720	/**
2721	* Possible CrX load (write) sources.
2722	*/
2723	typedef enum IEMACCESSCRX
2724	{
2725	/** CrX access caused by 'mov crX' instruction. */
2726	IEMACCESSCRX_MOV_CRX,
2727	/** CrX (CR0) write caused by 'lmsw' instruction. */
2728	IEMACCESSCRX_LMSW,
2729	/** CrX (CR0) write caused by 'clts' instruction. */
2730	IEMACCESSCRX_CLTS,
2731	/** CrX (CR0) read caused by 'smsw' instruction. */
2732	IEMACCESSCRX_SMSW
2733	} IEMACCESSCRX;
2734
2735	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2736	/** @name IEM_SLAT_FAIL_XXX - Second-level address translation failure information.
2737	*
2738	* These flags provide further context to SLAT page-walk failures that could not be
2739	* determined by PGM (e.g, PGM is not privy to memory access permissions).
2740	*
2741	* @{
2742	*/
2743	/** Translating a nested-guest linear address failed accessing a nested-guest
2744	* physical address. */
2745	# define IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR RT_BIT_32(0)
2746	/** Translating a nested-guest linear address failed accessing a
2747	* paging-structure entry or updating accessed/dirty bits. */
2748	# define IEM_SLAT_FAIL_LINEAR_TO_PAGE_TABLE RT_BIT_32(1)
2749	/** @} */
2750
2751	DECLCALLBACK(FNPGMPHYSHANDLER) iemVmxApicAccessPageHandler;
2752	# ifndef IN_RING3
2753	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) iemVmxApicAccessPagePfHandler;
2754	# endif
2755	#endif
2756
2757	/**
2758	* Indicates to the verifier that the given flag set is undefined.
2759	*
2760	* Can be invoked again to add more flags.
2761	*
2762	* This is a NOOP if the verifier isn't compiled in.
2763	*
2764	* @note We're temporarily keeping this until code is converted to new
2765	* disassembler style opcode handling.
2766	*/
2767	#define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
2768
2769
2770	/** @def IEM_DECL_IMPL_TYPE
2771	* For typedef'ing an instruction implementation function.
2772	*
2773	* @param a_RetType The return type.
2774	* @param a_Name The name of the type.
2775	* @param a_ArgList The argument list enclosed in parentheses.
2776	*/
2777
2778	/** @def IEM_DECL_IMPL_DEF
2779	* For defining an instruction implementation function.
2780	*
2781	* @param a_RetType The return type.
2782	* @param a_Name The name of the type.
2783	* @param a_ArgList The argument list enclosed in parentheses.
2784	*/
2785
2786	#if defined(__GNUC__) && defined(RT_ARCH_X86)
2787	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2788	__attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
2789	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2790	__attribute__((__fastcall__, __nothrow__)) DECL_HIDDEN_ONLY(a_RetType) a_Name a_ArgList
2791	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2792	__attribute__((__fastcall__, __nothrow__)) DECL_HIDDEN_ONLY(a_RetType) a_Name a_ArgList
2793
2794	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
2795	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2796	a_RetType (__fastcall a_Name) a_ArgList
2797	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2798	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
2799	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2800	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
2801
2802	#elif __cplusplus >= 201700 /* P0012R1 support */
2803	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2804	a_RetType (VBOXCALL a_Name) a_ArgList RT_NOEXCEPT
2805	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2806	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList RT_NOEXCEPT
2807	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2808	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList RT_NOEXCEPT
2809
2810	#else
2811	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2812	a_RetType (VBOXCALL a_Name) a_ArgList
2813	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2814	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList
2815	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2816	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList
2817
2818	#endif
2819
2820	/** Defined in IEMAllAImplC.cpp but also used by IEMAllAImplA.asm. */
2821	RT_C_DECLS_BEGIN
2822	extern uint8_t const g_afParity[256];
2823	RT_C_DECLS_END
2824
2825
2826	/** @name Arithmetic assignment operations on bytes (binary).
2827	* @{ */
2828	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU8, (uint32_t fEFlagsIn, uint8_t *pu8Dst, uint8_t u8Src));
2829	typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
2830	FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
2831	FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
2832	FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
2833	FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
2834	FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
2835	FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
2836	FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
2837	/** @} */
2838
2839	/** @name Arithmetic assignment operations on words (binary).
2840	* @{ */
2841	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU16, (uint32_t fEFlagsIn, uint16_t *pu16Dst, uint16_t u16Src));
2842	typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
2843	FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
2844	FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
2845	FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
2846	FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
2847	FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
2848	FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
2849	FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
2850	/** @} */
2851
2852
2853	/** @name Arithmetic assignment operations on double words (binary).
2854	* @{ */
2855	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU32, (uint32_t fEFlagsIn, uint32_t *pu32Dst, uint32_t u32Src));
2856	typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
2857	FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
2858	FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
2859	FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
2860	FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
2861	FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
2862	FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
2863	FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
2864	FNIEMAIMPLBINU32 iemAImpl_blsi_u32, iemAImpl_blsi_u32_fallback;
2865	FNIEMAIMPLBINU32 iemAImpl_blsr_u32, iemAImpl_blsr_u32_fallback;
2866	FNIEMAIMPLBINU32 iemAImpl_blsmsk_u32, iemAImpl_blsmsk_u32_fallback;
2867	/** @} */
2868
2869	/** @name Arithmetic assignment operations on quad words (binary).
2870	* @{ */
2871	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU64, (uint32_t fEFlagsIn, uint64_t *pu64Dst, uint64_t u64Src));
2872	typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
2873	FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
2874	FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
2875	FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
2876	FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
2877	FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
2878	FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
2879	FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
2880	FNIEMAIMPLBINU64 iemAImpl_blsi_u64, iemAImpl_blsi_u64_fallback;
2881	FNIEMAIMPLBINU64 iemAImpl_blsr_u64, iemAImpl_blsr_u64_fallback;
2882	FNIEMAIMPLBINU64 iemAImpl_blsmsk_u64, iemAImpl_blsmsk_u64_fallback;
2883	/** @} */
2884
2885	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU8, (uint32_t fEFlagsIn, uint8_t const *pu8Dst, uint8_t u8Src));
2886	typedef FNIEMAIMPLBINROU8 *PFNIEMAIMPLBINROU8;
2887	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU16,(uint32_t fEFlagsIn, uint16_t const *pu16Dst, uint16_t u16Src));
2888	typedef FNIEMAIMPLBINROU16 *PFNIEMAIMPLBINROU16;
2889	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU32,(uint32_t fEFlagsIn, uint32_t const *pu32Dst, uint32_t u32Src));
2890	typedef FNIEMAIMPLBINROU32 *PFNIEMAIMPLBINROU32;
2891	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU64,(uint32_t fEFlagsIn, uint64_t const *pu64Dst, uint64_t u64Src));
2892	typedef FNIEMAIMPLBINROU64 *PFNIEMAIMPLBINROU64;
2893
2894	/** @name Compare operations (thrown in with the binary ops).
2895	* @{ */
2896	FNIEMAIMPLBINROU8 iemAImpl_cmp_u8;
2897	FNIEMAIMPLBINROU16 iemAImpl_cmp_u16;
2898	FNIEMAIMPLBINROU32 iemAImpl_cmp_u32;
2899	FNIEMAIMPLBINROU64 iemAImpl_cmp_u64;
2900	/** @} */
2901
2902	/** @name Test operations (thrown in with the binary ops).
2903	* @{ */
2904	FNIEMAIMPLBINROU8 iemAImpl_test_u8;
2905	FNIEMAIMPLBINROU16 iemAImpl_test_u16;
2906	FNIEMAIMPLBINROU32 iemAImpl_test_u32;
2907	FNIEMAIMPLBINROU64 iemAImpl_test_u64;
2908	/** @} */
2909
2910	/** @name Bit operations operations (thrown in with the binary ops).
2911	* @{ */
2912	FNIEMAIMPLBINROU16 iemAImpl_bt_u16;
2913	FNIEMAIMPLBINROU32 iemAImpl_bt_u32;
2914	FNIEMAIMPLBINROU64 iemAImpl_bt_u64;
2915	FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
2916	FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
2917	FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
2918	FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
2919	FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
2920	FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
2921	FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
2922	FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
2923	FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
2924	/** @} */
2925
2926	/** @name Arithmetic three operand operations on double words (binary).
2927	* @{ */
2928	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32, (uint32_t pu32Dst, uint32_t u32Src1, uint32_t u32Src2, uint32_t pEFlags));
2929	typedef FNIEMAIMPLBINVEXU32 *PFNIEMAIMPLBINVEXU32;
2930	FNIEMAIMPLBINVEXU32 iemAImpl_andn_u32, iemAImpl_andn_u32_fallback;
2931	FNIEMAIMPLBINVEXU32 iemAImpl_bextr_u32, iemAImpl_bextr_u32_fallback;
2932	FNIEMAIMPLBINVEXU32 iemAImpl_bzhi_u32, iemAImpl_bzhi_u32_fallback;
2933	/** @} */
2934
2935	/** @name Arithmetic three operand operations on quad words (binary).
2936	* @{ */
2937	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64, (uint64_t pu64Dst, uint64_t u64Src1, uint64_t u64Src2, uint32_t pEFlags));
2938	typedef FNIEMAIMPLBINVEXU64 *PFNIEMAIMPLBINVEXU64;
2939	FNIEMAIMPLBINVEXU64 iemAImpl_andn_u64, iemAImpl_andn_u64_fallback;
2940	FNIEMAIMPLBINVEXU64 iemAImpl_bextr_u64, iemAImpl_bextr_u64_fallback;
2941	FNIEMAIMPLBINVEXU64 iemAImpl_bzhi_u64, iemAImpl_bzhi_u64_fallback;
2942	/** @} */
2943
2944	/** @name Arithmetic three operand operations on double words w/o EFLAGS (binary).
2945	* @{ */
2946	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32NOEFL, (uint32_t *pu32Dst, uint32_t u32Src1, uint32_t u32Src2));
2947	typedef FNIEMAIMPLBINVEXU32NOEFL *PFNIEMAIMPLBINVEXU32NOEFL;
2948	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pdep_u32, iemAImpl_pdep_u32_fallback;
2949	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pext_u32, iemAImpl_pext_u32_fallback;
2950	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_sarx_u32, iemAImpl_sarx_u32_fallback;
2951	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shlx_u32, iemAImpl_shlx_u32_fallback;
2952	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shrx_u32, iemAImpl_shrx_u32_fallback;
2953	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_rorx_u32;
2954	/** @} */
2955
2956	/** @name Arithmetic three operand operations on quad words w/o EFLAGS (binary).
2957	* @{ */
2958	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64NOEFL, (uint64_t *pu64Dst, uint64_t u64Src1, uint64_t u64Src2));
2959	typedef FNIEMAIMPLBINVEXU64NOEFL *PFNIEMAIMPLBINVEXU64NOEFL;
2960	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pdep_u64, iemAImpl_pdep_u64_fallback;
2961	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pext_u64, iemAImpl_pext_u64_fallback;
2962	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_sarx_u64, iemAImpl_sarx_u64_fallback;
2963	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shlx_u64, iemAImpl_shlx_u64_fallback;
2964	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shrx_u64, iemAImpl_shrx_u64_fallback;
2965	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_rorx_u64;
2966	/** @} */
2967
2968	/** @name MULX 32-bit and 64-bit.
2969	* @{ */
2970	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU32, (uint32_t puDst1, uint32_t puDst2, uint32_t uSrc1, uint32_t uSrc2));
2971	typedef FNIEMAIMPLMULXVEXU32 *PFNIEMAIMPLMULXVEXU32;
2972	FNIEMAIMPLMULXVEXU32 iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback;
2973
2974	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU64, (uint64_t puDst1, uint64_t puDst2, uint64_t uSrc1, uint64_t uSrc2));
2975	typedef FNIEMAIMPLMULXVEXU64 *PFNIEMAIMPLMULXVEXU64;
2976	FNIEMAIMPLMULXVEXU64 iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback;
2977	/** @} */
2978
2979
2980	/** @name Exchange memory with register operations.
2981	* @{ */
2982	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_locked, (uint8_t pu8Mem, uint8_t pu8Reg));
2983	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_locked,(uint16_t pu16Mem, uint16_t pu16Reg));
2984	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_locked,(uint32_t pu32Mem, uint32_t pu32Reg));
2985	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_locked,(uint64_t pu64Mem, uint64_t pu64Reg));
2986	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_unlocked, (uint8_t pu8Mem, uint8_t pu8Reg));
2987	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_unlocked,(uint16_t pu16Mem, uint16_t pu16Reg));
2988	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_unlocked,(uint32_t pu32Mem, uint32_t pu32Reg));
2989	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_unlocked,(uint64_t pu64Mem, uint64_t pu64Reg));
2990	/** @} */
2991
2992	/** @name Exchange and add operations.
2993	* @{ */
2994	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
2995	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
2996	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
2997	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
2998	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
2999	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
3000	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
3001	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
3002	/** @} */
3003
3004	/** @name Compare and exchange.
3005	* @{ */
3006	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
3007	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
3008	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
3009	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
3010	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
3011	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
3012	#if ARCH_BITS == 32
3013	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
3014	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
3015	#else
3016	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
3017	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
3018	#endif
3019	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
3020	uint32_t *pEFlags));
3021	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
3022	uint32_t *pEFlags));
3023	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
3024	uint32_t *pEFlags));
3025	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
3026	uint32_t *pEFlags));
3027	#ifndef RT_ARCH_ARM64
3028	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
3029	PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
3030	#endif
3031	/** @} */
3032
3033	/** @name Memory ordering
3034	* @{ */
3035	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
3036	typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
3037	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
3038	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
3039	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
3040	#ifndef RT_ARCH_ARM64
3041	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
3042	#endif
3043	/** @} */
3044
3045	/** @name Double precision shifts
3046	* @{ */
3047	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t pEFlags));
3048	typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
3049	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t pEFlags));
3050	typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
3051	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t pEFlags));
3052	typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
3053	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16, iemAImpl_shld_u16_amd, iemAImpl_shld_u16_intel;
3054	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32, iemAImpl_shld_u32_amd, iemAImpl_shld_u32_intel;
3055	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64, iemAImpl_shld_u64_amd, iemAImpl_shld_u64_intel;
3056	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16, iemAImpl_shrd_u16_amd, iemAImpl_shrd_u16_intel;
3057	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32, iemAImpl_shrd_u32_amd, iemAImpl_shrd_u32_intel;
3058	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64, iemAImpl_shrd_u64_amd, iemAImpl_shrd_u64_intel;
3059	/** @} */
3060
3061
3062	/** @name Bit search operations (thrown in with the binary ops).
3063	* @{ */
3064	FNIEMAIMPLBINU16 iemAImpl_bsf_u16, iemAImpl_bsf_u16_amd, iemAImpl_bsf_u16_intel;
3065	FNIEMAIMPLBINU32 iemAImpl_bsf_u32, iemAImpl_bsf_u32_amd, iemAImpl_bsf_u32_intel;
3066	FNIEMAIMPLBINU64 iemAImpl_bsf_u64, iemAImpl_bsf_u64_amd, iemAImpl_bsf_u64_intel;
3067	FNIEMAIMPLBINU16 iemAImpl_bsr_u16, iemAImpl_bsr_u16_amd, iemAImpl_bsr_u16_intel;
3068	FNIEMAIMPLBINU32 iemAImpl_bsr_u32, iemAImpl_bsr_u32_amd, iemAImpl_bsr_u32_intel;
3069	FNIEMAIMPLBINU64 iemAImpl_bsr_u64, iemAImpl_bsr_u64_amd, iemAImpl_bsr_u64_intel;
3070	FNIEMAIMPLBINU16 iemAImpl_lzcnt_u16, iemAImpl_lzcnt_u16_amd, iemAImpl_lzcnt_u16_intel;
3071	FNIEMAIMPLBINU32 iemAImpl_lzcnt_u32, iemAImpl_lzcnt_u32_amd, iemAImpl_lzcnt_u32_intel;
3072	FNIEMAIMPLBINU64 iemAImpl_lzcnt_u64, iemAImpl_lzcnt_u64_amd, iemAImpl_lzcnt_u64_intel;
3073	FNIEMAIMPLBINU16 iemAImpl_tzcnt_u16, iemAImpl_tzcnt_u16_amd, iemAImpl_tzcnt_u16_intel;
3074	FNIEMAIMPLBINU32 iemAImpl_tzcnt_u32, iemAImpl_tzcnt_u32_amd, iemAImpl_tzcnt_u32_intel;
3075	FNIEMAIMPLBINU64 iemAImpl_tzcnt_u64, iemAImpl_tzcnt_u64_amd, iemAImpl_tzcnt_u64_intel;
3076	FNIEMAIMPLBINU16 iemAImpl_popcnt_u16, iemAImpl_popcnt_u16_fallback;
3077	FNIEMAIMPLBINU32 iemAImpl_popcnt_u32, iemAImpl_popcnt_u32_fallback;
3078	FNIEMAIMPLBINU64 iemAImpl_popcnt_u64, iemAImpl_popcnt_u64_fallback;
3079	/** @} */
3080
3081	/** @name Signed multiplication operations (thrown in with the binary ops).
3082	* @{ */
3083	FNIEMAIMPLBINU16 iemAImpl_imul_two_u16, iemAImpl_imul_two_u16_amd, iemAImpl_imul_two_u16_intel;
3084	FNIEMAIMPLBINU32 iemAImpl_imul_two_u32, iemAImpl_imul_two_u32_amd, iemAImpl_imul_two_u32_intel;
3085	FNIEMAIMPLBINU64 iemAImpl_imul_two_u64, iemAImpl_imul_two_u64_amd, iemAImpl_imul_two_u64_intel;
3086	/** @} */
3087
3088	/** @name Arithmetic assignment operations on bytes (unary).
3089	* @{ */
3090	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t pu8Dst, uint32_t pEFlags));
3091	typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
3092	FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
3093	FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
3094	FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
3095	FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
3096	/** @} */
3097
3098	/** @name Arithmetic assignment operations on words (unary).
3099	* @{ */
3100	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t pu16Dst, uint32_t pEFlags));
3101	typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
3102	FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
3103	FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
3104	FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
3105	FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
3106	/** @} */
3107
3108	/** @name Arithmetic assignment operations on double words (unary).
3109	* @{ */
3110	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t pu32Dst, uint32_t pEFlags));
3111	typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
3112	FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
3113	FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
3114	FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
3115	FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
3116	/** @} */
3117
3118	/** @name Arithmetic assignment operations on quad words (unary).
3119	* @{ */
3120	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t pu64Dst, uint32_t pEFlags));
3121	typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
3122	FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
3123	FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
3124	FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
3125	FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
3126	/** @} */
3127
3128
3129	/** @name Shift operations on bytes (Group 2).
3130	* @{ */
3131	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU8,(uint32_t fEFlagsIn, uint8_t *pu8Dst, uint8_t cShift));
3132	typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
3133	FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8, iemAImpl_rol_u8_amd, iemAImpl_rol_u8_intel;
3134	FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8, iemAImpl_ror_u8_amd, iemAImpl_ror_u8_intel;
3135	FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8, iemAImpl_rcl_u8_amd, iemAImpl_rcl_u8_intel;
3136	FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8, iemAImpl_rcr_u8_amd, iemAImpl_rcr_u8_intel;
3137	FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8, iemAImpl_shl_u8_amd, iemAImpl_shl_u8_intel;
3138	FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8, iemAImpl_shr_u8_amd, iemAImpl_shr_u8_intel;
3139	FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8, iemAImpl_sar_u8_amd, iemAImpl_sar_u8_intel;
3140	/** @} */
3141
3142	/** @name Shift operations on words (Group 2).
3143	* @{ */
3144	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU16,(uint32_t fEFlagsIn, uint16_t *pu16Dst, uint8_t cShift));
3145	typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
3146	FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16, iemAImpl_rol_u16_amd, iemAImpl_rol_u16_intel;
3147	FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16, iemAImpl_ror_u16_amd, iemAImpl_ror_u16_intel;
3148	FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16, iemAImpl_rcl_u16_amd, iemAImpl_rcl_u16_intel;
3149	FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16, iemAImpl_rcr_u16_amd, iemAImpl_rcr_u16_intel;
3150	FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16, iemAImpl_shl_u16_amd, iemAImpl_shl_u16_intel;
3151	FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16, iemAImpl_shr_u16_amd, iemAImpl_shr_u16_intel;
3152	FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16, iemAImpl_sar_u16_amd, iemAImpl_sar_u16_intel;
3153	/** @} */
3154
3155	/** @name Shift operations on double words (Group 2).
3156	* @{ */
3157	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU32,(uint32_t fEFlagsIn, uint32_t *pu32Dst, uint8_t cShift));
3158	typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
3159	FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32, iemAImpl_rol_u32_amd, iemAImpl_rol_u32_intel;
3160	FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32, iemAImpl_ror_u32_amd, iemAImpl_ror_u32_intel;
3161	FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32, iemAImpl_rcl_u32_amd, iemAImpl_rcl_u32_intel;
3162	FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32, iemAImpl_rcr_u32_amd, iemAImpl_rcr_u32_intel;
3163	FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32, iemAImpl_shl_u32_amd, iemAImpl_shl_u32_intel;
3164	FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32, iemAImpl_shr_u32_amd, iemAImpl_shr_u32_intel;
3165	FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32, iemAImpl_sar_u32_amd, iemAImpl_sar_u32_intel;
3166	/** @} */
3167
3168	/** @name Shift operations on words (Group 2).
3169	* @{ */
3170	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU64,(uint32_t fEFlagsIn, uint64_t *pu64Dst, uint8_t cShift));
3171	typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
3172	FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64, iemAImpl_rol_u64_amd, iemAImpl_rol_u64_intel;
3173	FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64, iemAImpl_ror_u64_amd, iemAImpl_ror_u64_intel;
3174	FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64, iemAImpl_rcl_u64_amd, iemAImpl_rcl_u64_intel;
3175	FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64, iemAImpl_rcr_u64_amd, iemAImpl_rcr_u64_intel;
3176	FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64, iemAImpl_shl_u64_amd, iemAImpl_shl_u64_intel;
3177	FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64, iemAImpl_shr_u64_amd, iemAImpl_shr_u64_intel;
3178	FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64, iemAImpl_sar_u64_amd, iemAImpl_sar_u64_intel;
3179	/** @} */
3180
3181	/** @name Multiplication and division operations.
3182	* @{ */
3183	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t pu16AX, uint8_t u8FactorDivisor, uint32_t pEFlags));
3184	typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
3185	FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_mul_u8_amd, iemAImpl_mul_u8_intel;
3186	FNIEMAIMPLMULDIVU8 iemAImpl_imul_u8, iemAImpl_imul_u8_amd, iemAImpl_imul_u8_intel;
3187	FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_div_u8_amd, iemAImpl_div_u8_intel;
3188	FNIEMAIMPLMULDIVU8 iemAImpl_idiv_u8, iemAImpl_idiv_u8_amd, iemAImpl_idiv_u8_intel;
3189
3190	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t pu16AX, uint16_t pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
3191	typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
3192	FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_mul_u16_amd, iemAImpl_mul_u16_intel;
3193	FNIEMAIMPLMULDIVU16 iemAImpl_imul_u16, iemAImpl_imul_u16_amd, iemAImpl_imul_u16_intel;
3194	FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_div_u16_amd, iemAImpl_div_u16_intel;
3195	FNIEMAIMPLMULDIVU16 iemAImpl_idiv_u16, iemAImpl_idiv_u16_amd, iemAImpl_idiv_u16_intel;
3196
3197	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t pu32EAX, uint32_t pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
3198	typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
3199	FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_mul_u32_amd, iemAImpl_mul_u32_intel;
3200	FNIEMAIMPLMULDIVU32 iemAImpl_imul_u32, iemAImpl_imul_u32_amd, iemAImpl_imul_u32_intel;
3201	FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_div_u32_amd, iemAImpl_div_u32_intel;
3202	FNIEMAIMPLMULDIVU32 iemAImpl_idiv_u32, iemAImpl_idiv_u32_amd, iemAImpl_idiv_u32_intel;
3203
3204	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t pu64RAX, uint64_t pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
3205	typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
3206	FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_mul_u64_amd, iemAImpl_mul_u64_intel;
3207	FNIEMAIMPLMULDIVU64 iemAImpl_imul_u64, iemAImpl_imul_u64_amd, iemAImpl_imul_u64_intel;
3208	FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_div_u64_amd, iemAImpl_div_u64_intel;
3209	FNIEMAIMPLMULDIVU64 iemAImpl_idiv_u64, iemAImpl_idiv_u64_amd, iemAImpl_idiv_u64_intel;
3210	/** @} */
3211
3212	/** @name Byte Swap.
3213	* @{ */
3214	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t pu32Dst)); / Yes, 32-bit register access. */
3215	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
3216	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
3217	/** @} */
3218
3219	/** @name Misc.
3220	* @{ */
3221	FNIEMAIMPLBINU16 iemAImpl_arpl;
3222	/** @} */
3223
3224	/** @name RDRAND and RDSEED
3225	* @{ */
3226	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU16,(uint16_t puDst, uint32_t pEFlags));
3227	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU32,(uint32_t puDst, uint32_t pEFlags));
3228	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU64,(uint64_t puDst, uint32_t pEFlags));
3229	typedef FNIEMAIMPLRDRANDSEEDU16 *PFNIEMAIMPLRDRANDSEEDU16;
3230	typedef FNIEMAIMPLRDRANDSEEDU32 *PFNIEMAIMPLRDRANDSEEDU32;
3231	typedef FNIEMAIMPLRDRANDSEEDU64 *PFNIEMAIMPLRDRANDSEEDU64;
3232
3233	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdrand_u16, iemAImpl_rdrand_u16_fallback;
3234	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdrand_u32, iemAImpl_rdrand_u32_fallback;
3235	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdrand_u64, iemAImpl_rdrand_u64_fallback;
3236	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdseed_u16, iemAImpl_rdseed_u16_fallback;
3237	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdseed_u32, iemAImpl_rdseed_u32_fallback;
3238	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdseed_u64, iemAImpl_rdseed_u64_fallback;
3239	/** @} */
3240
3241	/** @name ADOX and ADCX
3242	* @{ */
3243	FNIEMAIMPLBINU32 iemAImpl_adcx_u32, iemAImpl_adcx_u32_fallback;
3244	FNIEMAIMPLBINU64 iemAImpl_adcx_u64, iemAImpl_adcx_u64_fallback;
3245	FNIEMAIMPLBINU32 iemAImpl_adox_u32, iemAImpl_adox_u32_fallback;
3246	FNIEMAIMPLBINU64 iemAImpl_adox_u64, iemAImpl_adox_u64_fallback;
3247	/** @} */
3248
3249	/** @name FPU operations taking a 32-bit float argument
3250	* @{ */
3251	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3252	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
3253	typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
3254
3255	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3256	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
3257	typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
3258
3259	FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
3260	FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
3261	FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
3262	FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
3263	FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
3264	FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
3265	FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
3266
3267	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
3268	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3269	PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
3270	/** @} */
3271
3272	/** @name FPU operations taking a 64-bit float argument
3273	* @{ */
3274	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3275	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
3276	typedef FNIEMAIMPLFPUR64FSW *PFNIEMAIMPLFPUR64FSW;
3277
3278	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3279	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
3280	typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
3281
3282	FNIEMAIMPLFPUR64FSW iemAImpl_fcom_r80_by_r64;
3283	FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
3284	FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
3285	FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
3286	FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
3287	FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
3288	FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
3289
3290	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
3291	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3292	PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
3293	/** @} */
3294
3295	/** @name FPU operations taking a 80-bit float argument
3296	* @{ */
3297	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3298	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
3299	typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
3300	FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
3301	FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
3302	FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
3303	FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
3304	FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
3305	FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
3306	FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
3307	FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
3308	FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
3309
3310	FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80, iemAImpl_fpatan_r80_by_r80_amd, iemAImpl_fpatan_r80_by_r80_intel;
3311	FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80, iemAImpl_fyl2x_r80_by_r80_amd, iemAImpl_fyl2x_r80_by_r80_intel;
3312	FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80, iemAImpl_fyl2xp1_r80_by_r80_amd, iemAImpl_fyl2xp1_r80_by_r80_intel;
3313
3314	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3315	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
3316	typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
3317	FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
3318	FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
3319
3320	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
3321	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
3322	typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
3323	FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
3324	FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
3325
3326	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
3327	typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
3328	FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
3329	FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
3330	FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80, iemAImpl_f2xm1_r80_amd, iemAImpl_f2xm1_r80_intel;
3331	FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
3332	FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
3333	FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80, iemAImpl_fsin_r80_amd, iemAImpl_fsin_r80_intel;
3334	FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80, iemAImpl_fcos_r80_amd, iemAImpl_fcos_r80_intel;
3335
3336	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
3337	typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
3338	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
3339	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
3340
3341	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
3342	typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
3343	FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
3344	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
3345	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
3346	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
3347	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
3348	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
3349	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
3350
3351	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
3352	PCRTFLOAT80U pr80Val));
3353	typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
3354	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80, iemAImpl_fptan_r80_r80_amd, iemAImpl_fptan_r80_r80_intel;
3355	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
3356	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80, iemAImpl_fsincos_r80_r80_amd, iemAImpl_fsincos_r80_r80_intel;
3357
3358	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
3359	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3360	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
3361
3362	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_d80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTPBCD80U pd80Val));
3363	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_d80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3364	PRTPBCD80U pd80Dst, PCRTFLOAT80U pr80Src));
3365
3366	/** @} */
3367
3368	/** @name FPU operations taking a 16-bit signed integer argument
3369	* @{ */
3370	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3371	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
3372	typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
3373	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI16,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3374	int16_t *pi16Dst, PCRTFLOAT80U pr80Src));
3375	typedef FNIEMAIMPLFPUSTR80TOI16 *PFNIEMAIMPLFPUSTR80TOI16;
3376
3377	FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
3378	FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
3379	FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
3380	FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
3381	FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
3382	FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
3383
3384	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3385	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
3386	typedef FNIEMAIMPLFPUI16FSW *PFNIEMAIMPLFPUI16FSW;
3387	FNIEMAIMPLFPUI16FSW iemAImpl_ficom_r80_by_i16;
3388
3389	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
3390	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fist_r80_to_i16;
3391	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fistt_r80_to_i16, iemAImpl_fistt_r80_to_i16_amd, iemAImpl_fistt_r80_to_i16_intel;
3392	/** @} */
3393
3394	/** @name FPU operations taking a 32-bit signed integer argument
3395	* @{ */
3396	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3397	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
3398	typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
3399	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI32,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3400	int32_t *pi32Dst, PCRTFLOAT80U pr80Src));
3401	typedef FNIEMAIMPLFPUSTR80TOI32 *PFNIEMAIMPLFPUSTR80TOI32;
3402
3403	FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
3404	FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
3405	FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
3406	FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
3407	FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
3408	FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
3409
3410	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3411	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
3412	typedef FNIEMAIMPLFPUI32FSW *PFNIEMAIMPLFPUI32FSW;
3413	FNIEMAIMPLFPUI32FSW iemAImpl_ficom_r80_by_i32;
3414
3415	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
3416	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fist_r80_to_i32;
3417	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fistt_r80_to_i32;
3418	/** @} */
3419
3420	/** @name FPU operations taking a 64-bit signed integer argument
3421	* @{ */
3422	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI64,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3423	int64_t *pi64Dst, PCRTFLOAT80U pr80Src));
3424	typedef FNIEMAIMPLFPUSTR80TOI64 *PFNIEMAIMPLFPUSTR80TOI64;
3425
3426	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
3427	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fist_r80_to_i64;
3428	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fistt_r80_to_i64;
3429	/** @} */
3430
3431
3432	/** Temporary type representing a 256-bit vector register. */
3433	typedef struct { uint64_t au64[4]; } IEMVMM256;
3434	/** Temporary type pointing to a 256-bit vector register. */
3435	typedef IEMVMM256 *PIEMVMM256;
3436	/** Temporary type pointing to a const 256-bit vector register. */
3437	typedef IEMVMM256 *PCIEMVMM256;
3438
3439
3440	/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
3441	* @{ */
3442	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t puDst, uint64_t const puSrc));
3443	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
3444	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U128,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
3445	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
3446	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF3U128,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
3447	typedef FNIEMAIMPLMEDIAF3U128 *PFNIEMAIMPLMEDIAF3U128;
3448	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF3U256,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86YMMREG puSrc1, PCX86YMMREG puSrc2));
3449	typedef FNIEMAIMPLMEDIAF3U256 *PFNIEMAIMPLMEDIAF3U256;
3450	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U64,(uint64_t puDst, uint64_t const puSrc));
3451	typedef FNIEMAIMPLMEDIAOPTF2U64 *PFNIEMAIMPLMEDIAOPTF2U64;
3452	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128,(PRTUINT128U puDst, PCRTUINT128U puSrc));
3453	typedef FNIEMAIMPLMEDIAOPTF2U128 *PFNIEMAIMPLMEDIAOPTF2U128;
3454	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
3455	typedef FNIEMAIMPLMEDIAOPTF3U128 *PFNIEMAIMPLMEDIAOPTF3U128;
3456	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
3457	typedef FNIEMAIMPLMEDIAOPTF3U256 *PFNIEMAIMPLMEDIAOPTF3U256;
3458	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256,(PRTUINT256U puDst, PCRTUINT256U puSrc));
3459	typedef FNIEMAIMPLMEDIAOPTF2U256 *PFNIEMAIMPLMEDIAOPTF2U256;
3460	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pshufb_u64, iemAImpl_pshufb_u64_fallback;
3461	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pand_u64, iemAImpl_pandn_u64, iemAImpl_por_u64, iemAImpl_pxor_u64;
3462	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
3463	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pcmpgtb_u64, iemAImpl_pcmpgtw_u64, iemAImpl_pcmpgtd_u64;
3464	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddb_u64, iemAImpl_paddsb_u64, iemAImpl_paddusb_u64;
3465	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddw_u64, iemAImpl_paddsw_u64, iemAImpl_paddusw_u64;
3466	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddd_u64;
3467	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddq_u64;
3468	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubb_u64, iemAImpl_psubsb_u64, iemAImpl_psubusb_u64;
3469	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubw_u64, iemAImpl_psubsw_u64, iemAImpl_psubusw_u64;
3470	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubd_u64;
3471	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubq_u64;
3472	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmaddwd_u64, iemAImpl_pmaddwd_u64_fallback;
3473	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmullw_u64, iemAImpl_pmulhw_u64;
3474	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pminub_u64, iemAImpl_pmaxub_u64;
3475	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pminsw_u64, iemAImpl_pmaxsw_u64;
3476	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pabsb_u64, iemAImpl_pabsb_u64_fallback;
3477	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pabsw_u64, iemAImpl_pabsw_u64_fallback;
3478	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pabsd_u64, iemAImpl_pabsd_u64_fallback;
3479	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psignb_u64, iemAImpl_psignb_u64_fallback;
3480	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psignw_u64, iemAImpl_psignw_u64_fallback;
3481	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psignd_u64, iemAImpl_psignd_u64_fallback;
3482	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phaddw_u64, iemAImpl_phaddw_u64_fallback;
3483	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phaddd_u64, iemAImpl_phaddd_u64_fallback;
3484	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phsubw_u64, iemAImpl_phsubw_u64_fallback;
3485	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phsubd_u64, iemAImpl_phsubd_u64_fallback;
3486	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phaddsw_u64, iemAImpl_phaddsw_u64_fallback;
3487	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phsubsw_u64, iemAImpl_phsubsw_u64_fallback;
3488	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmaddubsw_u64, iemAImpl_pmaddubsw_u64_fallback;
3489	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhrsw_u64, iemAImpl_pmulhrsw_u64_fallback;
3490	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmuludq_u64;
3491	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllw_u64, iemAImpl_psrlw_u64, iemAImpl_psraw_u64;
3492	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pslld_u64, iemAImpl_psrld_u64, iemAImpl_psrad_u64;
3493	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllq_u64, iemAImpl_psrlq_u64;
3494	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packsswb_u64, iemAImpl_packuswb_u64;
3495	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packssdw_u64;
3496	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhuw_u64;
3497	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pavgb_u64, iemAImpl_pavgw_u64;
3498	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psadbw_u64;
3499
3500	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pshufb_u128, iemAImpl_pshufb_u128_fallback;
3501	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pand_u128, iemAImpl_pandn_u128, iemAImpl_por_u128, iemAImpl_pxor_u128;
3502	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
3503	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpeqq_u128, iemAImpl_pcmpeqq_u128_fallback;
3504	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpgtb_u128, iemAImpl_pcmpgtw_u128, iemAImpl_pcmpgtd_u128;
3505	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpgtq_u128, iemAImpl_pcmpgtq_u128_fallback;
3506	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddb_u128, iemAImpl_paddsb_u128, iemAImpl_paddusb_u128;
3507	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddw_u128, iemAImpl_paddsw_u128, iemAImpl_paddusw_u128;
3508	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddd_u128;
3509	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddq_u128;
3510	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubb_u128, iemAImpl_psubsb_u128, iemAImpl_psubusb_u128;
3511	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubw_u128, iemAImpl_psubsw_u128, iemAImpl_psubusw_u128;
3512	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubd_u128;
3513	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubq_u128;
3514	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmullw_u128, iemAImpl_pmullw_u128_fallback;
3515	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhw_u128;
3516	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulld_u128, iemAImpl_pmulld_u128_fallback;
3517	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaddwd_u128, iemAImpl_pmaddwd_u128_fallback;
3518	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminub_u128;
3519	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminud_u128, iemAImpl_pminud_u128_fallback;
3520	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminuw_u128, iemAImpl_pminuw_u128_fallback;
3521	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminsb_u128, iemAImpl_pminsb_u128_fallback;
3522	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminsd_u128, iemAImpl_pminsd_u128_fallback;
3523	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminsw_u128, iemAImpl_pminsw_u128_fallback;
3524	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxub_u128;
3525	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxud_u128, iemAImpl_pmaxud_u128_fallback;
3526	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxuw_u128, iemAImpl_pmaxuw_u128_fallback;
3527	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxsb_u128, iemAImpl_pmaxsb_u128_fallback;
3528	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxsw_u128;
3529	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxsd_u128, iemAImpl_pmaxsd_u128_fallback;
3530	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pabsb_u128, iemAImpl_pabsb_u128_fallback;
3531	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pabsw_u128, iemAImpl_pabsw_u128_fallback;
3532	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pabsd_u128, iemAImpl_pabsd_u128_fallback;
3533	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psignb_u128, iemAImpl_psignb_u128_fallback;
3534	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psignw_u128, iemAImpl_psignw_u128_fallback;
3535	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psignd_u128, iemAImpl_psignd_u128_fallback;
3536	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phaddw_u128, iemAImpl_phaddw_u128_fallback;
3537	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phaddd_u128, iemAImpl_phaddd_u128_fallback;
3538	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phsubw_u128, iemAImpl_phsubw_u128_fallback;
3539	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phsubd_u128, iemAImpl_phsubd_u128_fallback;
3540	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phaddsw_u128, iemAImpl_phaddsw_u128_fallback;
3541	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phsubsw_u128, iemAImpl_phsubsw_u128_fallback;
3542	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaddubsw_u128, iemAImpl_pmaddubsw_u128_fallback;
3543	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhrsw_u128, iemAImpl_pmulhrsw_u128_fallback;
3544	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuludq_u128;
3545	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaddwd_u128, iemAImpl_pmaddwd_u128_fallback;
3546	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packsswb_u128, iemAImpl_packuswb_u128;
3547	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packssdw_u128, iemAImpl_packusdw_u128;
3548	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllw_u128, iemAImpl_psrlw_u128, iemAImpl_psraw_u128;
3549	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pslld_u128, iemAImpl_psrld_u128, iemAImpl_psrad_u128;
3550	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllq_u128, iemAImpl_psrlq_u128;
3551	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhuw_u128;
3552	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pavgb_u128, iemAImpl_pavgw_u128;
3553	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psadbw_u128;
3554	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuldq_u128, iemAImpl_pmuldq_u128_fallback;
3555	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpcklps_u128, iemAImpl_unpcklpd_u128;
3556	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpckhps_u128, iemAImpl_unpckhpd_u128;
3557	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phminposuw_u128, iemAImpl_phminposuw_u128_fallback;
3558
3559	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpshufb_u128, iemAImpl_vpshufb_u128_fallback;
3560	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpand_u128, iemAImpl_vpand_u128_fallback;
3561	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpandn_u128, iemAImpl_vpandn_u128_fallback;
3562	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpor_u128, iemAImpl_vpor_u128_fallback;
3563	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpxor_u128, iemAImpl_vpxor_u128_fallback;
3564	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqb_u128, iemAImpl_vpcmpeqb_u128_fallback;
3565	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqw_u128, iemAImpl_vpcmpeqw_u128_fallback;
3566	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqd_u128, iemAImpl_vpcmpeqd_u128_fallback;
3567	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqq_u128, iemAImpl_vpcmpeqq_u128_fallback;
3568	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtb_u128, iemAImpl_vpcmpgtb_u128_fallback;
3569	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtw_u128, iemAImpl_vpcmpgtw_u128_fallback;
3570	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtd_u128, iemAImpl_vpcmpgtd_u128_fallback;
3571	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtq_u128, iemAImpl_vpcmpgtq_u128_fallback;
3572	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddb_u128, iemAImpl_vpaddb_u128_fallback;
3573	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddw_u128, iemAImpl_vpaddw_u128_fallback;
3574	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddd_u128, iemAImpl_vpaddd_u128_fallback;
3575	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddq_u128, iemAImpl_vpaddq_u128_fallback;
3576	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubb_u128, iemAImpl_vpsubb_u128_fallback;
3577	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubw_u128, iemAImpl_vpsubw_u128_fallback;
3578	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubd_u128, iemAImpl_vpsubd_u128_fallback;
3579	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubq_u128, iemAImpl_vpsubq_u128_fallback;
3580	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminub_u128, iemAImpl_vpminub_u128_fallback;
3581	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminuw_u128, iemAImpl_vpminuw_u128_fallback;
3582	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminud_u128, iemAImpl_vpminud_u128_fallback;
3583	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminsb_u128, iemAImpl_vpminsb_u128_fallback;
3584	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminsw_u128, iemAImpl_vpminsw_u128_fallback;
3585	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminsd_u128, iemAImpl_vpminsd_u128_fallback;
3586	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxub_u128, iemAImpl_vpmaxub_u128_fallback;
3587	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxuw_u128, iemAImpl_vpmaxuw_u128_fallback;
3588	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxud_u128, iemAImpl_vpmaxud_u128_fallback;
3589	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxsb_u128, iemAImpl_vpmaxsb_u128_fallback;
3590	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxsw_u128, iemAImpl_vpmaxsw_u128_fallback;
3591	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxsd_u128, iemAImpl_vpmaxsd_u128_fallback;
3592	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpacksswb_u128, iemAImpl_vpacksswb_u128_fallback;
3593	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackssdw_u128, iemAImpl_vpackssdw_u128_fallback;
3594	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackuswb_u128, iemAImpl_vpackuswb_u128_fallback;
3595	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackusdw_u128, iemAImpl_vpackusdw_u128_fallback;
3596	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmullw_u128, iemAImpl_vpmullw_u128_fallback;
3597	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulld_u128, iemAImpl_vpmulld_u128_fallback;
3598	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhw_u128, iemAImpl_vpmulhw_u128_fallback;
3599	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhuw_u128, iemAImpl_vpmulhuw_u128_fallback;
3600	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgb_u128, iemAImpl_vpavgb_u128_fallback;
3601	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgw_u128, iemAImpl_vpavgw_u128_fallback;
3602	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignb_u128, iemAImpl_vpsignb_u128_fallback;
3603	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignw_u128, iemAImpl_vpsignw_u128_fallback;
3604	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignd_u128, iemAImpl_vpsignd_u128_fallback;
3605	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddw_u128, iemAImpl_vphaddw_u128_fallback;
3606	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddd_u128, iemAImpl_vphaddd_u128_fallback;
3607	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubw_u128, iemAImpl_vphsubw_u128_fallback;
3608	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubd_u128, iemAImpl_vphsubd_u128_fallback;
3609	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddsw_u128, iemAImpl_vphaddsw_u128_fallback;
3610	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubsw_u128, iemAImpl_vphsubsw_u128_fallback;
3611	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddubsw_u128, iemAImpl_vpmaddubsw_u128_fallback;
3612	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhrsw_u128, iemAImpl_vpmulhrsw_u128_fallback;
3613	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsadbw_u128, iemAImpl_vpsadbw_u128_fallback;
3614	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuldq_u128, iemAImpl_vpmuldq_u128_fallback;
3615	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuludq_u128, iemAImpl_vpmuludq_u128_fallback;
3616	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsb_u128, iemAImpl_vpsubsb_u128_fallback;
3617	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsw_u128, iemAImpl_vpsubsw_u128_fallback;
3618	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusb_u128, iemAImpl_vpsubusb_u128_fallback;
3619	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusw_u128, iemAImpl_vpsubusw_u128_fallback;
3620	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusb_u128, iemAImpl_vpaddusb_u128_fallback;
3621	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusw_u128, iemAImpl_vpaddusw_u128_fallback;
3622	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsb_u128, iemAImpl_vpaddsb_u128_fallback;
3623	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsw_u128, iemAImpl_vpaddsw_u128_fallback;
3624	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllw_u128, iemAImpl_vpsllw_u128_fallback;
3625	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpslld_u128, iemAImpl_vpslld_u128_fallback;
3626	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllq_u128, iemAImpl_vpsllq_u128_fallback;
3627	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsraw_u128, iemAImpl_vpsraw_u128_fallback;
3628	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrad_u128, iemAImpl_vpsrad_u128_fallback;
3629	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlw_u128, iemAImpl_vpsrlw_u128_fallback;
3630	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrld_u128, iemAImpl_vpsrld_u128_fallback;
3631	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlq_u128, iemAImpl_vpsrlq_u128_fallback;
3632	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddwd_u128, iemAImpl_vpmaddwd_u128_fallback;
3633
3634	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsb_u128, iemAImpl_vpabsb_u128_fallback;
3635	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsw_u128, iemAImpl_vpabsd_u128_fallback;
3636	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsd_u128, iemAImpl_vpabsw_u128_fallback;
3637	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vphminposuw_u128, iemAImpl_vphminposuw_u128_fallback;
3638
3639	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpshufb_u256, iemAImpl_vpshufb_u256_fallback;
3640	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpand_u256, iemAImpl_vpand_u256_fallback;
3641	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpandn_u256, iemAImpl_vpandn_u256_fallback;
3642	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpor_u256, iemAImpl_vpor_u256_fallback;
3643	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpxor_u256, iemAImpl_vpxor_u256_fallback;
3644	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqb_u256, iemAImpl_vpcmpeqb_u256_fallback;
3645	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqw_u256, iemAImpl_vpcmpeqw_u256_fallback;
3646	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqd_u256, iemAImpl_vpcmpeqd_u256_fallback;
3647	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqq_u256, iemAImpl_vpcmpeqq_u256_fallback;
3648	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtb_u256, iemAImpl_vpcmpgtb_u256_fallback;
3649	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtw_u256, iemAImpl_vpcmpgtw_u256_fallback;
3650	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtd_u256, iemAImpl_vpcmpgtd_u256_fallback;
3651	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtq_u256, iemAImpl_vpcmpgtq_u256_fallback;
3652	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddb_u256, iemAImpl_vpaddb_u256_fallback;
3653	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddw_u256, iemAImpl_vpaddw_u256_fallback;
3654	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddd_u256, iemAImpl_vpaddd_u256_fallback;
3655	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddq_u256, iemAImpl_vpaddq_u256_fallback;
3656	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubb_u256, iemAImpl_vpsubb_u256_fallback;
3657	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubw_u256, iemAImpl_vpsubw_u256_fallback;
3658	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubd_u256, iemAImpl_vpsubd_u256_fallback;
3659	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubq_u256, iemAImpl_vpsubq_u256_fallback;
3660	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminub_u256, iemAImpl_vpminub_u256_fallback;
3661	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminuw_u256, iemAImpl_vpminuw_u256_fallback;
3662	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminud_u256, iemAImpl_vpminud_u256_fallback;
3663	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminsb_u256, iemAImpl_vpminsb_u256_fallback;
3664	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminsw_u256, iemAImpl_vpminsw_u256_fallback;
3665	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminsd_u256, iemAImpl_vpminsd_u256_fallback;
3666	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxub_u256, iemAImpl_vpmaxub_u256_fallback;
3667	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxuw_u256, iemAImpl_vpmaxuw_u256_fallback;
3668	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxud_u256, iemAImpl_vpmaxud_u256_fallback;
3669	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxsb_u256, iemAImpl_vpmaxsb_u256_fallback;
3670	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxsw_u256, iemAImpl_vpmaxsw_u256_fallback;
3671	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxsd_u256, iemAImpl_vpmaxsd_u256_fallback;
3672	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpacksswb_u256, iemAImpl_vpacksswb_u256_fallback;
3673	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackssdw_u256, iemAImpl_vpackssdw_u256_fallback;
3674	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackuswb_u256, iemAImpl_vpackuswb_u256_fallback;
3675	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackusdw_u256, iemAImpl_vpackusdw_u256_fallback;
3676	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmullw_u256, iemAImpl_vpmullw_u256_fallback;
3677	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulld_u256, iemAImpl_vpmulld_u256_fallback;
3678	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhw_u256, iemAImpl_vpmulhw_u256_fallback;
3679	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhuw_u256, iemAImpl_vpmulhuw_u256_fallback;
3680	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgb_u256, iemAImpl_vpavgb_u256_fallback;
3681	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgw_u256, iemAImpl_vpavgw_u256_fallback;
3682	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignb_u256, iemAImpl_vpsignb_u256_fallback;
3683	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignw_u256, iemAImpl_vpsignw_u256_fallback;
3684	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignd_u256, iemAImpl_vpsignd_u256_fallback;
3685	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddw_u256, iemAImpl_vphaddw_u256_fallback;
3686	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddd_u256, iemAImpl_vphaddd_u256_fallback;
3687	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubw_u256, iemAImpl_vphsubw_u256_fallback;
3688	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubd_u256, iemAImpl_vphsubd_u256_fallback;
3689	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddsw_u256, iemAImpl_vphaddsw_u256_fallback;
3690	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubsw_u256, iemAImpl_vphsubsw_u256_fallback;
3691	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddubsw_u256, iemAImpl_vpmaddubsw_u256_fallback;
3692	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhrsw_u256, iemAImpl_vpmulhrsw_u256_fallback;
3693	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsadbw_u256, iemAImpl_vpsadbw_u256_fallback;
3694	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuldq_u256, iemAImpl_vpmuldq_u256_fallback;
3695	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuludq_u256, iemAImpl_vpmuludq_u256_fallback;
3696	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsb_u256, iemAImpl_vpsubsb_u256_fallback;
3697	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsw_u256, iemAImpl_vpsubsw_u256_fallback;
3698	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusb_u256, iemAImpl_vpsubusb_u256_fallback;
3699	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusw_u256, iemAImpl_vpsubusw_u256_fallback;
3700	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusb_u256, iemAImpl_vpaddusb_u256_fallback;
3701	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusw_u256, iemAImpl_vpaddusw_u256_fallback;
3702	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsb_u256, iemAImpl_vpaddsb_u256_fallback;
3703	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsw_u256, iemAImpl_vpaddsw_u256_fallback;
3704	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllw_u256, iemAImpl_vpsllw_u256_fallback;
3705	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpslld_u256, iemAImpl_vpslld_u256_fallback;
3706	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllq_u256, iemAImpl_vpsllq_u256_fallback;
3707	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsraw_u256, iemAImpl_vpsraw_u256_fallback;
3708	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrad_u256, iemAImpl_vpsrad_u256_fallback;
3709	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlw_u256, iemAImpl_vpsrlw_u256_fallback;
3710	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrld_u256, iemAImpl_vpsrld_u256_fallback;
3711	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlq_u256, iemAImpl_vpsrlq_u256_fallback;
3712	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddwd_u256, iemAImpl_vpmaddwd_u256_fallback;
3713
3714	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsb_u256, iemAImpl_vpabsb_u256_fallback;
3715	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsw_u256, iemAImpl_vpabsw_u256_fallback;
3716	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsd_u256, iemAImpl_vpabsd_u256_fallback;
3717	/** @} */
3718
3719	/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
3720	* @{ */
3721	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
3722	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
3723	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpcklbw_u128, iemAImpl_vpunpcklbw_u128_fallback,
3724	iemAImpl_vpunpcklwd_u128, iemAImpl_vpunpcklwd_u128_fallback,
3725	iemAImpl_vpunpckldq_u128, iemAImpl_vpunpckldq_u128_fallback,
3726	iemAImpl_vpunpcklqdq_u128, iemAImpl_vpunpcklqdq_u128_fallback,
3727	iemAImpl_vunpcklps_u128, iemAImpl_vunpcklps_u128_fallback,
3728	iemAImpl_vunpcklpd_u128, iemAImpl_vunpcklpd_u128_fallback,
3729	iemAImpl_vunpckhps_u128, iemAImpl_vunpckhps_u128_fallback,
3730	iemAImpl_vunpckhpd_u128, iemAImpl_vunpckhpd_u128_fallback;
3731
3732	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpcklbw_u256, iemAImpl_vpunpcklbw_u256_fallback,
3733	iemAImpl_vpunpcklwd_u256, iemAImpl_vpunpcklwd_u256_fallback,
3734	iemAImpl_vpunpckldq_u256, iemAImpl_vpunpckldq_u256_fallback,
3735	iemAImpl_vpunpcklqdq_u256, iemAImpl_vpunpcklqdq_u256_fallback,
3736	iemAImpl_vunpcklps_u256, iemAImpl_vunpcklps_u256_fallback,
3737	iemAImpl_vunpcklpd_u256, iemAImpl_vunpcklpd_u256_fallback,
3738	iemAImpl_vunpckhps_u256, iemAImpl_vunpckhps_u256_fallback,
3739	iemAImpl_vunpckhpd_u256, iemAImpl_vunpckhpd_u256_fallback;
3740	/** @} */
3741
3742	/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
3743	* @{ */
3744	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
3745	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
3746	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpckhbw_u128, iemAImpl_vpunpckhbw_u128_fallback,
3747	iemAImpl_vpunpckhwd_u128, iemAImpl_vpunpckhwd_u128_fallback,
3748	iemAImpl_vpunpckhdq_u128, iemAImpl_vpunpckhdq_u128_fallback,
3749	iemAImpl_vpunpckhqdq_u128, iemAImpl_vpunpckhqdq_u128_fallback;
3750	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpckhbw_u256, iemAImpl_vpunpckhbw_u256_fallback,
3751	iemAImpl_vpunpckhwd_u256, iemAImpl_vpunpckhwd_u256_fallback,
3752	iemAImpl_vpunpckhdq_u256, iemAImpl_vpunpckhdq_u256_fallback,
3753	iemAImpl_vpunpckhqdq_u256, iemAImpl_vpunpckhqdq_u256_fallback;
3754	/** @} */
3755
3756	/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
3757	* @{ */
3758	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3759	typedef FNIEMAIMPLMEDIAPSHUFU128 *PFNIEMAIMPLMEDIAPSHUFU128;
3760	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
3761	typedef FNIEMAIMPLMEDIAPSHUFU256 *PFNIEMAIMPLMEDIAPSHUFU256;
3762	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw_u64,(uint64_t puDst, uint64_t const puSrc, uint8_t bEvil));
3763	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_pshufhw_u128, iemAImpl_pshuflw_u128, iemAImpl_pshufd_u128;
3764	#ifndef IEM_WITHOUT_ASSEMBLY
3765	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256, iemAImpl_vpshuflw_u256, iemAImpl_vpshufd_u256;
3766	#endif
3767	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256_fallback, iemAImpl_vpshuflw_u256_fallback, iemAImpl_vpshufd_u256_fallback;
3768	/** @} */
3769
3770	/** @name Media (SSE/MMX/AVX) operation: Shift Immediate Stuff (evil)
3771	* @{ */
3772	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU64,(uint64_t *puDst, uint8_t bShift));
3773	typedef FNIEMAIMPLMEDIAPSHIFTU64 *PFNIEMAIMPLMEDIAPSHIFTU64;
3774	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU128,(PRTUINT128U puDst, uint8_t bShift));
3775	typedef FNIEMAIMPLMEDIAPSHIFTU128 *PFNIEMAIMPLMEDIAPSHIFTU128;
3776	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU256,(PRTUINT256U puDst, uint8_t bShift));
3777	typedef FNIEMAIMPLMEDIAPSHIFTU256 *PFNIEMAIMPLMEDIAPSHIFTU256;
3778	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psllw_imm_u64, iemAImpl_pslld_imm_u64, iemAImpl_psllq_imm_u64;
3779	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psrlw_imm_u64, iemAImpl_psrld_imm_u64, iemAImpl_psrlq_imm_u64;
3780	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psraw_imm_u64, iemAImpl_psrad_imm_u64;
3781	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psllw_imm_u128, iemAImpl_pslld_imm_u128, iemAImpl_psllq_imm_u128;
3782	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psrlw_imm_u128, iemAImpl_psrld_imm_u128, iemAImpl_psrlq_imm_u128;
3783	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psraw_imm_u128, iemAImpl_psrad_imm_u128;
3784	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_pslldq_imm_u128, iemAImpl_psrldq_imm_u128;
3785	/** @} */
3786
3787	/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
3788	* @{ */
3789	IEM_DECL_IMPL_DEF(void, iemAImpl_maskmovq_u64,(uint64_t puMem, uint64_t const puSrc, uint64_t const *puMsk));
3790	IEM_DECL_IMPL_DEF(void, iemAImpl_maskmovdqu_u128,(PRTUINT128U puMem, PCRTUINT128U puSrc, PCRTUINT128U puMsk));
3791	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(uint64_t pu64Dst, uint64_t const puSrc));
3792	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(uint64_t *pu64Dst, PCRTUINT128U puSrc));
3793	#ifndef IEM_WITHOUT_ASSEMBLY
3794	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
3795	#endif
3796	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256_fallback,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
3797	/** @} */
3798
3799	/** @name Media (SSE/MMX/AVX) operations: Variable Blend Packed Bytes/R32/R64.
3800	* @{ */
3801	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puMask));
3802	typedef FNIEMAIMPLBLENDU128 *PFNIEMAIMPLBLENDU128;
3803	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, PCRTUINT128U puMask));
3804	typedef FNIEMAIMPLAVXBLENDU128 *PFNIEMAIMPLAVXBLENDU128;
3805	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, PCRTUINT256U puMask));
3806	typedef FNIEMAIMPLAVXBLENDU256 *PFNIEMAIMPLAVXBLENDU256;
3807
3808	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128;
3809	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128_fallback;
3810	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128;
3811	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128_fallback;
3812	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256;
3813	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256_fallback;
3814
3815	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128;
3816	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128_fallback;
3817	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128;
3818	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128_fallback;
3819	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256;
3820	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256_fallback;
3821
3822	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128;
3823	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128_fallback;
3824	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128;
3825	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128_fallback;
3826	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256;
3827	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256_fallback;
3828	/** @} */
3829
3830
3831	/** @name Media (SSE/MMX/AVX) operation: Sort this later
3832	* @{ */
3833	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3834	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3835	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3836	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3837	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3838
3839	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3840	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3841	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3842	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3843	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3844
3845	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3846	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3847	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
3848	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3849	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3850
3851	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3852	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3853	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3854	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3855	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3856
3857	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3858	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3859	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3860	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3861	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3862
3863	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3864	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3865	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3866	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3867	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3868
3869	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3870	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3871	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3872	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3873	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3874
3875	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3876	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3877	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3878	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3879	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3880
3881	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3882	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3883	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
3884	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3885	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3886
3887	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3888	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3889	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3890	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3891	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3892
3893	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3894	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3895	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3896	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3897	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3898
3899	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3900	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3901	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3902	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3903	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3904
3905	IEM_DECL_IMPL_DEF(void, iemAImpl_shufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3906	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3907	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3908	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3909	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3910
3911	IEM_DECL_IMPL_DEF(void, iemAImpl_shufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3912	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3913	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3914	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3915	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3916
3917	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
3918	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64_fallback,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
3919
3920	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3921	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3922	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3923	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3924	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3925
3926	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3927	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3928	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3929	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3930	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3931
3932
3933	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3934	typedef FNIEMAIMPLMEDIAOPTF2U128IMM8 *PFNIEMAIMPLMEDIAOPTF2U128IMM8;
3935	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
3936	typedef FNIEMAIMPLMEDIAOPTF2U256IMM8 *PFNIEMAIMPLMEDIAOPTF2U256IMM8;
3937	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3938	typedef FNIEMAIMPLMEDIAOPTF3U128IMM8 *PFNIEMAIMPLMEDIAOPTF3U128IMM8;
3939	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3940	typedef FNIEMAIMPLMEDIAOPTF3U256IMM8 *PFNIEMAIMPLMEDIAOPTF3U256IMM8;
3941
3942	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_palignr_u128, iemAImpl_palignr_u128_fallback;
3943	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pblendw_u128, iemAImpl_pblendw_u128_fallback;
3944	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendps_u128, iemAImpl_blendps_u128_fallback;
3945	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendpd_u128, iemAImpl_blendpd_u128_fallback;
3946
3947	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpalignr_u128, iemAImpl_vpalignr_u128_fallback;
3948	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendw_u128, iemAImpl_vpblendw_u128_fallback;
3949	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendd_u128, iemAImpl_vpblendd_u128_fallback;
3950	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendps_u128, iemAImpl_vblendps_u128_fallback;
3951	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendpd_u128, iemAImpl_vblendpd_u128_fallback;
3952
3953	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpalignr_u256, iemAImpl_vpalignr_u256_fallback;
3954	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendw_u256, iemAImpl_vpblendw_u256_fallback;
3955	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendd_u256, iemAImpl_vpblendd_u256_fallback;
3956	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendps_u256, iemAImpl_vblendps_u256_fallback;
3957	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendpd_u256, iemAImpl_vblendpd_u256_fallback;
3958	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2i128_u256, iemAImpl_vperm2i128_u256_fallback;
3959	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2f128_u256, iemAImpl_vperm2f128_u256_fallback;
3960
3961	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesimc_u128, iemAImpl_aesimc_u128_fallback;
3962	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenc_u128, iemAImpl_aesenc_u128_fallback;
3963	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenclast_u128, iemAImpl_aesenclast_u128_fallback;
3964	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdec_u128, iemAImpl_aesdec_u128_fallback;
3965	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdeclast_u128, iemAImpl_aesdeclast_u128_fallback;
3966
3967	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesimc_u128, iemAImpl_vaesimc_u128_fallback;
3968	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenc_u128, iemAImpl_vaesenc_u128_fallback;
3969	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenclast_u128, iemAImpl_vaesenclast_u128_fallback;
3970	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdec_u128, iemAImpl_vaesdec_u128_fallback;
3971	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdeclast_u128, iemAImpl_vaesdeclast_u128_fallback;
3972
3973	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_aeskeygenassist_u128, iemAImpl_aeskeygenassist_u128_fallback;
3974
3975	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vaeskeygenassist_u128, iemAImpl_vaeskeygenassist_u128_fallback;
3976
3977	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1nexte_u128, iemAImpl_sha1nexte_u128_fallback;
3978	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg1_u128, iemAImpl_sha1msg1_u128_fallback;
3979	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg2_u128, iemAImpl_sha1msg2_u128_fallback;
3980	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg1_u128, iemAImpl_sha256msg1_u128_fallback;
3981	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg2_u128, iemAImpl_sha256msg2_u128_fallback;
3982	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_sha1rnds4_u128, iemAImpl_sha1rnds4_u128_fallback;
3983	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
3984	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
3985
3986	typedef struct IEMPCMPISTRXSRC
3987	{
3988	RTUINT128U uSrc1;
3989	RTUINT128U uSrc2;
3990	} IEMPCMPISTRXSRC;
3991	typedef IEMPCMPISTRXSRC *PIEMPCMPISTRXSRC;
3992	typedef const IEMPCMPISTRXSRC *PCIEMPCMPISTRXSRC;
3993
3994	typedef struct IEMPCMPESTRXSRC
3995	{
3996	RTUINT128U uSrc1;
3997	RTUINT128U uSrc2;
3998	uint64_t u64Rax;
3999	uint64_t u64Rdx;
4000	} IEMPCMPESTRXSRC;
4001	typedef IEMPCMPESTRXSRC *PIEMPCMPESTRXSRC;
4002	typedef const IEMPCMPESTRXSRC *PCIEMPCMPESTRXSRC;
4003
4004	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLPCMPISTRIU128IMM8,(uint32_t *pEFlags, PCRTUINT128U pSrc1, PCRTUINT128U pSrc2, uint8_t bEvil));
4005	typedef FNIEMAIMPLPCMPISTRIU128IMM8 *PFNIEMAIMPLPCMPISTRIU128IMM8;
4006	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRIU128IMM8,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
4007	typedef FNIEMAIMPLPCMPESTRIU128IMM8 *PFNIEMAIMPLPCMPESTRIU128IMM8;
4008
4009	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPISTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
4010	typedef FNIEMAIMPLPCMPISTRMU128IMM8 *PFNIEMAIMPLPCMPISTRMU128IMM8;
4011	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
4012	typedef FNIEMAIMPLPCMPESTRMU128IMM8 *PFNIEMAIMPLPCMPESTRMU128IMM8;
4013
4014	FNIEMAIMPLPCMPISTRIU128IMM8 iemAImpl_pcmpistri_u128, iemAImpl_pcmpistri_u128_fallback;
4015	FNIEMAIMPLPCMPESTRIU128IMM8 iemAImpl_pcmpestri_u128, iemAImpl_pcmpestri_u128_fallback;
4016	FNIEMAIMPLPCMPISTRMU128IMM8 iemAImpl_pcmpistrm_u128, iemAImpl_pcmpistrm_u128_fallback;
4017	FNIEMAIMPLPCMPESTRMU128IMM8 iemAImpl_pcmpestrm_u128, iemAImpl_pcmpestrm_u128_fallback;
4018
4019	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pclmulqdq_u128, iemAImpl_pclmulqdq_u128_fallback;
4020	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpclmulqdq_u128, iemAImpl_vpclmulqdq_u128_fallback;
4021
4022	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_mpsadbw_u128, iemAImpl_mpsadbw_u128_fallback;
4023	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vmpsadbw_u128, iemAImpl_vmpsadbw_u128_fallback;
4024	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vmpsadbw_u256, iemAImpl_vmpsadbw_u256_fallback;
4025
4026	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsllw_imm_u128, iemAImpl_vpsllw_imm_u128_fallback;
4027	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsllw_imm_u256, iemAImpl_vpsllw_imm_u256_fallback;
4028	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpslld_imm_u128, iemAImpl_vpslld_imm_u128_fallback;
4029	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpslld_imm_u256, iemAImpl_vpslld_imm_u256_fallback;
4030	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsllq_imm_u128, iemAImpl_vpsllq_imm_u128_fallback;
4031	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsllq_imm_u256, iemAImpl_vpsllq_imm_u256_fallback;
4032	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
4033	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
4034	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
4035	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
4036
4037	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsraw_imm_u128, iemAImpl_vpsraw_imm_u128_fallback;
4038	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsraw_imm_u256, iemAImpl_vpsraw_imm_u256_fallback;
4039	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrad_imm_u128, iemAImpl_vpsrad_imm_u128_fallback;
4040	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrad_imm_u256, iemAImpl_vpsrad_imm_u256_fallback;
4041
4042	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrlw_imm_u128, iemAImpl_vpsrlw_imm_u128_fallback;
4043	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrlw_imm_u256, iemAImpl_vpsrlw_imm_u256_fallback;
4044	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrld_imm_u128, iemAImpl_vpsrld_imm_u128_fallback;
4045	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrld_imm_u256, iemAImpl_vpsrld_imm_u256_fallback;
4046	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrlq_imm_u128, iemAImpl_vpsrlq_imm_u128_fallback;
4047	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrlq_imm_u256, iemAImpl_vpsrlq_imm_u256_fallback;
4048	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
4049	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
4050	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
4051	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
4052
4053	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpermilps_u128, iemAImpl_vpermilps_u128_fallback;
4054	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_vpermilps_imm_u128, iemAImpl_vpermilps_imm_u128_fallback;
4055	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpermilps_u256, iemAImpl_vpermilps_u256_fallback;
4056	FNIEMAIMPLMEDIAOPTF2U256IMM8 iemAImpl_vpermilps_imm_u256, iemAImpl_vpermilps_imm_u256_fallback;
4057
4058	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpermilpd_u128, iemAImpl_vpermilpd_u128_fallback;
4059	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_vpermilpd_imm_u128, iemAImpl_vpermilpd_imm_u128_fallback;
4060	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpermilpd_u256, iemAImpl_vpermilpd_u256_fallback;
4061	FNIEMAIMPLMEDIAOPTF2U256IMM8 iemAImpl_vpermilpd_imm_u256, iemAImpl_vpermilpd_imm_u256_fallback;
4062
4063	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllvd_u128, iemAImpl_vpsllvd_u128_fallback;
4064	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllvd_u256, iemAImpl_vpsllvd_u256_fallback;
4065	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllvq_u128, iemAImpl_vpsllvq_u128_fallback;
4066	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllvq_u256, iemAImpl_vpsllvq_u256_fallback;
4067	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsravd_u128, iemAImpl_vpsravd_u128_fallback;
4068	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsravd_u256, iemAImpl_vpsravd_u256_fallback;
4069	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlvd_u128, iemAImpl_vpsrlvd_u128_fallback;
4070	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlvd_u256, iemAImpl_vpsrlvd_u256_fallback;
4071	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlvq_u128, iemAImpl_vpsrlvq_u128_fallback;
4072	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlvq_u256, iemAImpl_vpsrlvq_u256_fallback;
4073	/** @} */
4074
4075	/** @name Media Odds and Ends
4076	* @{ */
4077	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U8,(uint32_t *puDst, uint8_t uSrc));
4078	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U16,(uint32_t *puDst, uint16_t uSrc));
4079	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U32,(uint32_t *puDst, uint32_t uSrc));
4080	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U64,(uint32_t *puDst, uint64_t uSrc));
4081	FNIEMAIMPLCR32U8 iemAImpl_crc32_u8, iemAImpl_crc32_u8_fallback;
4082	FNIEMAIMPLCR32U16 iemAImpl_crc32_u16, iemAImpl_crc32_u16_fallback;
4083	FNIEMAIMPLCR32U32 iemAImpl_crc32_u32, iemAImpl_crc32_u32_fallback;
4084	FNIEMAIMPLCR32U64 iemAImpl_crc32_u64, iemAImpl_crc32_u64_fallback;
4085
4086	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL128,(PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint32_t *pEFlags));
4087	typedef FNIEMAIMPLF2EFL128 *PFNIEMAIMPLF2EFL128;
4088	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL256,(PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint32_t *pEFlags));
4089	typedef FNIEMAIMPLF2EFL256 *PFNIEMAIMPLF2EFL256;
4090	FNIEMAIMPLF2EFL128 iemAImpl_ptest_u128;
4091	FNIEMAIMPLF2EFL256 iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback;
4092	FNIEMAIMPLF2EFL128 iemAImpl_vtestps_u128, iemAImpl_vtestps_u128_fallback;
4093	FNIEMAIMPLF2EFL256 iemAImpl_vtestps_u256, iemAImpl_vtestps_u256_fallback;
4094	FNIEMAIMPLF2EFL128 iemAImpl_vtestpd_u128, iemAImpl_vtestpd_u128_fallback;
4095	FNIEMAIMPLF2EFL256 iemAImpl_vtestpd_u256, iemAImpl_vtestpd_u256_fallback;
4096
4097	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I32U64,(uint32_t uMxCsrIn, int32_t pi32Dst, const uint64_t pu64Src)); /* pu64Src is a double precision floating point. */
4098	typedef FNIEMAIMPLSSEF2I32U64 *PFNIEMAIMPLSSEF2I32U64;
4099	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I64U64,(uint32_t uMxCsrIn, int64_t pi64Dst, const uint64_t pu64Src)); /* pu64Src is a double precision floating point. */
4100	typedef FNIEMAIMPLSSEF2I64U64 *PFNIEMAIMPLSSEF2I64U64;
4101	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I32U32,(uint32_t uMxCsrIn, int32_t pi32Dst, const uint32_t pu32Src)); /* pu32Src is a single precision floating point. */
4102	typedef FNIEMAIMPLSSEF2I32U32 *PFNIEMAIMPLSSEF2I32U32;
4103	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I64U32,(uint32_t uMxCsrIn, int64_t pi64Dst, const uint32_t pu32Src)); /* pu32Src is a single precision floating point. */
4104	typedef FNIEMAIMPLSSEF2I64U32 *PFNIEMAIMPLSSEF2I64U32;
4105
4106	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvttsd2si_i32_r64;
4107	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvtsd2si_i32_r64;
4108
4109	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvttsd2si_i64_r64;
4110	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvtsd2si_i64_r64;
4111
4112	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvttss2si_i32_r32;
4113	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvtss2si_i32_r32;
4114
4115	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvttss2si_i64_r32;
4116	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvtss2si_i64_r32;
4117
4118	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R32I32,(uint32_t uMxCsrIn, PRTFLOAT32U pr32Dst, const int32_t *pi32Src));
4119	typedef FNIEMAIMPLSSEF2R32I32 *PFNIEMAIMPLSSEF2R32I32;
4120	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R32I64,(uint32_t uMxCsrIn, PRTFLOAT32U pr32Dst, const int64_t *pi64Src));
4121	typedef FNIEMAIMPLSSEF2R32I64 *PFNIEMAIMPLSSEF2R32I64;
4122
4123	FNIEMAIMPLSSEF2R32I32 iemAImpl_cvtsi2ss_r32_i32;
4124	FNIEMAIMPLSSEF2R32I64 iemAImpl_cvtsi2ss_r32_i64;
4125
4126	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R64I32,(uint32_t uMxCsrIn, PRTFLOAT64U pr64Dst, const int32_t *pi32Src));
4127	typedef FNIEMAIMPLSSEF2R64I32 *PFNIEMAIMPLSSEF2R64I32;
4128	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R64I64,(uint32_t uMxCsrIn, PRTFLOAT64U pr64Dst, const int64_t *pi64Src));
4129	typedef FNIEMAIMPLSSEF2R64I64 *PFNIEMAIMPLSSEF2R64I64;
4130
4131	FNIEMAIMPLSSEF2R64I32 iemAImpl_cvtsi2sd_r64_i32;
4132	FNIEMAIMPLSSEF2R64I64 iemAImpl_cvtsi2sd_r64_i64;
4133
4134
4135	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLF2EFLMXCSRR32R32,(uint32_t uMxCsrIn, uint32_t *pfEFlags, RTFLOAT32U uSrc1, RTFLOAT32U uSrc2));
4136	typedef FNIEMAIMPLF2EFLMXCSRR32R32 *PFNIEMAIMPLF2EFLMXCSRR32R32;
4137
4138	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLF2EFLMXCSRR64R64,(uint32_t uMxCsrIn, uint32_t *pfEFlags, RTFLOAT64U uSrc1, RTFLOAT64U uSrc2));
4139	typedef FNIEMAIMPLF2EFLMXCSRR64R64 *PFNIEMAIMPLF2EFLMXCSRR64R64;
4140
4141	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_ucomiss_u128;
4142	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback;
4143
4144	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_ucomisd_u128;
4145	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback;
4146
4147	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_comiss_u128;
4148	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback;
4149
4150	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_comisd_u128;
4151	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback;
4152
4153
4154	typedef struct IEMMEDIAF2XMMSRC
4155	{
4156	X86XMMREG uSrc1;
4157	X86XMMREG uSrc2;
4158	} IEMMEDIAF2XMMSRC;
4159	typedef IEMMEDIAF2XMMSRC *PIEMMEDIAF2XMMSRC;
4160	typedef const IEMMEDIAF2XMMSRC *PCIEMMEDIAF2XMMSRC;
4161
4162	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRF2XMMIMM8,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCIEMMEDIAF2XMMSRC puSrc, uint8_t bEvil));
4163	typedef FNIEMAIMPLMXCSRF2XMMIMM8 *PFNIEMAIMPLMXCSRF2XMMIMM8;
4164
4165	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpps_u128;
4166	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmppd_u128;
4167	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpss_u128;
4168	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpsd_u128;
4169	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundss_u128;
4170	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundsd_u128;
4171
4172	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundps_u128, iemAImpl_roundps_u128_fallback;
4173	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundpd_u128, iemAImpl_roundpd_u128_fallback;
4174
4175	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_dpps_u128, iemAImpl_dpps_u128_fallback;
4176	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_dppd_u128, iemAImpl_dppd_u128_fallback;
4177
4178	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRU64U128,(uint32_t fMxCsrIn, uint64_t *pu64Dst, PCX86XMMREG pSrc));
4179	typedef FNIEMAIMPLMXCSRU64U128 *PFNIEMAIMPLMXCSRU64U128;
4180
4181	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvtpd2pi_u128;
4182	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvttpd2pi_u128;
4183
4184	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRU128U64,(uint32_t fMxCsrIn, PX86XMMREG pDst, uint64_t u64Src));
4185	typedef FNIEMAIMPLMXCSRU128U64 *PFNIEMAIMPLMXCSRU128U64;
4186
4187	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2ps_u128;
4188	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2pd_u128;
4189
4190	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRU64U64,(uint32_t fMxCsrIn, uint64_t *pu64Dst, uint64_t u64Src));
4191	typedef FNIEMAIMPLMXCSRU64U64 *PFNIEMAIMPLMXCSRU64U64;
4192
4193	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvtps2pi_u128;
4194	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvttps2pi_u128;
4195
4196	/** @} */
4197
4198
4199	/** @name Function tables.
4200	* @{
4201	*/
4202
4203	/**
4204	* Function table for a binary operator providing implementation based on
4205	* operand size.
4206	*/
4207	typedef struct IEMOPBINSIZES
4208	{
4209	PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
4210	PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
4211	PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
4212	PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
4213	} IEMOPBINSIZES;
4214	/** Pointer to a binary operator function table. */
4215	typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
4216
4217
4218	/**
4219	* Function table for a unary operator providing implementation based on
4220	* operand size.
4221	*/
4222	typedef struct IEMOPUNARYSIZES
4223	{
4224	PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
4225	PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
4226	PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
4227	PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
4228	} IEMOPUNARYSIZES;
4229	/** Pointer to a unary operator function table. */
4230	typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
4231
4232
4233	/**
4234	* Function table for a shift operator providing implementation based on
4235	* operand size.
4236	*/
4237	typedef struct IEMOPSHIFTSIZES
4238	{
4239	PFNIEMAIMPLSHIFTU8 pfnNormalU8;
4240	PFNIEMAIMPLSHIFTU16 pfnNormalU16;
4241	PFNIEMAIMPLSHIFTU32 pfnNormalU32;
4242	PFNIEMAIMPLSHIFTU64 pfnNormalU64;
4243	} IEMOPSHIFTSIZES;
4244	/** Pointer to a shift operator function table. */
4245	typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
4246
4247
4248	/**
4249	* Function table for a multiplication or division operation.
4250	*/
4251	typedef struct IEMOPMULDIVSIZES
4252	{
4253	PFNIEMAIMPLMULDIVU8 pfnU8;
4254	PFNIEMAIMPLMULDIVU16 pfnU16;
4255	PFNIEMAIMPLMULDIVU32 pfnU32;
4256	PFNIEMAIMPLMULDIVU64 pfnU64;
4257	} IEMOPMULDIVSIZES;
4258	/** Pointer to a multiplication or division operation function table. */
4259	typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
4260
4261
4262	/**
4263	* Function table for a double precision shift operator providing implementation
4264	* based on operand size.
4265	*/
4266	typedef struct IEMOPSHIFTDBLSIZES
4267	{
4268	PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
4269	PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
4270	PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
4271	} IEMOPSHIFTDBLSIZES;
4272	/** Pointer to a double precision shift function table. */
4273	typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
4274
4275
4276	/**
4277	* Function table for media instruction taking two full sized media source
4278	* registers and one full sized destination register (AVX).
4279	*/
4280	typedef struct IEMOPMEDIAF3
4281	{
4282	PFNIEMAIMPLMEDIAF3U128 pfnU128;
4283	PFNIEMAIMPLMEDIAF3U256 pfnU256;
4284	} IEMOPMEDIAF3;
4285	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
4286	typedef IEMOPMEDIAF3 const *PCIEMOPMEDIAF3;
4287
4288	/** @def IEMOPMEDIAF3_INIT_VARS_EX
4289	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4290	* given functions as initializers. For use in AVX functions where a pair of
4291	* functions are only used once and the function table need not be public. */
4292	#ifndef TST_IEM_CHECK_MC
4293	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4294	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4295	static IEMOPMEDIAF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4296	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4297	# else
4298	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4299	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4300	# endif
4301	#else
4302	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4303	#endif
4304	/** @def IEMOPMEDIAF3_INIT_VARS
4305	* Generate AVX function tables for the @a a_InstrNm instruction.
4306	* @sa IEMOPMEDIAF3_INIT_VARS_EX */
4307	#define IEMOPMEDIAF3_INIT_VARS(a_InstrNm) \
4308	IEMOPMEDIAF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4309	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4310
4311	/**
4312	* Function table for media instruction taking two full sized media source
4313	* registers and one full sized destination register, but no additional state
4314	* (AVX).
4315	*/
4316	typedef struct IEMOPMEDIAOPTF3
4317	{
4318	PFNIEMAIMPLMEDIAOPTF3U128 pfnU128;
4319	PFNIEMAIMPLMEDIAOPTF3U256 pfnU256;
4320	} IEMOPMEDIAOPTF3;
4321	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
4322	typedef IEMOPMEDIAOPTF3 const *PCIEMOPMEDIAOPTF3;
4323
4324	/** @def IEMOPMEDIAOPTF3_INIT_VARS_EX
4325	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4326	* given functions as initializers. For use in AVX functions where a pair of
4327	* functions are only used once and the function table need not be public. */
4328	#ifndef TST_IEM_CHECK_MC
4329	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4330	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4331	static IEMOPMEDIAOPTF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4332	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4333	# else
4334	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4335	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4336	# endif
4337	#else
4338	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4339	#endif
4340	/** @def IEMOPMEDIAOPTF3_INIT_VARS
4341	* Generate AVX function tables for the @a a_InstrNm instruction.
4342	* @sa IEMOPMEDIAOPTF3_INIT_VARS_EX */
4343	#define IEMOPMEDIAOPTF3_INIT_VARS(a_InstrNm) \
4344	IEMOPMEDIAOPTF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4345	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4346
4347	/**
4348	* Function table for media instruction taking one full sized media source
4349	* registers and one full sized destination register, but no additional state
4350	* (AVX).
4351	*/
4352	typedef struct IEMOPMEDIAOPTF2
4353	{
4354	PFNIEMAIMPLMEDIAOPTF2U128 pfnU128;
4355	PFNIEMAIMPLMEDIAOPTF2U256 pfnU256;
4356	} IEMOPMEDIAOPTF2;
4357	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
4358	typedef IEMOPMEDIAOPTF2 const *PCIEMOPMEDIAOPTF2;
4359
4360	/** @def IEMOPMEDIAOPTF2_INIT_VARS_EX
4361	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4362	* given functions as initializers. For use in AVX functions where a pair of
4363	* functions are only used once and the function table need not be public. */
4364	#ifndef TST_IEM_CHECK_MC
4365	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4366	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4367	static IEMOPMEDIAOPTF2 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4368	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4369	# else
4370	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4371	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4372	# endif
4373	#else
4374	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4375	#endif
4376	/** @def IEMOPMEDIAOPTF2_INIT_VARS
4377	* Generate AVX function tables for the @a a_InstrNm instruction.
4378	* @sa IEMOPMEDIAOPTF2_INIT_VARS_EX */
4379	#define IEMOPMEDIAOPTF2_INIT_VARS(a_InstrNm) \
4380	IEMOPMEDIAOPTF2_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4381	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4382
4383	/**
4384	* Function table for media instruction taking one full sized media source
4385	* register and one full sized destination register and an 8-bit immediate, but no additional state
4386	* (AVX).
4387	*/
4388	typedef struct IEMOPMEDIAOPTF2IMM8
4389	{
4390	PFNIEMAIMPLMEDIAOPTF2U128IMM8 pfnU128;
4391	PFNIEMAIMPLMEDIAOPTF2U256IMM8 pfnU256;
4392	} IEMOPMEDIAOPTF2IMM8;
4393	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
4394	typedef IEMOPMEDIAOPTF2IMM8 const *PCIEMOPMEDIAOPTF2IMM8;
4395
4396	/** @def IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX
4397	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4398	* given functions as initializers. For use in AVX functions where a pair of
4399	* functions are only used once and the function table need not be public. */
4400	#ifndef TST_IEM_CHECK_MC
4401	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4402	# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4403	static IEMOPMEDIAOPTF2IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4404	static IEMOPMEDIAOPTF2IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4405	# else
4406	# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4407	static IEMOPMEDIAOPTF2IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4408	# endif
4409	#else
4410	# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4411	#endif
4412	/** @def IEMOPMEDIAOPTF2IMM8_INIT_VARS
4413	* Generate AVX function tables for the @a a_InstrNm instruction.
4414	* @sa IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX */
4415	#define IEMOPMEDIAOPTF2IMM8_INIT_VARS(a_InstrNm) \
4416	IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u256),\
4417	RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u256_fallback))
4418
4419	/**
4420	* Function table for media instruction taking two full sized media source
4421	* registers and one full sized destination register and an 8-bit immediate, but no additional state
4422	* (AVX).
4423	*/
4424	typedef struct IEMOPMEDIAOPTF3IMM8
4425	{
4426	PFNIEMAIMPLMEDIAOPTF3U128IMM8 pfnU128;
4427	PFNIEMAIMPLMEDIAOPTF3U256IMM8 pfnU256;
4428	} IEMOPMEDIAOPTF3IMM8;
4429	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
4430	typedef IEMOPMEDIAOPTF3IMM8 const *PCIEMOPMEDIAOPTF3IMM8;
4431
4432	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX
4433	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4434	* given functions as initializers. For use in AVX functions where a pair of
4435	* functions are only used once and the function table need not be public. */
4436	#ifndef TST_IEM_CHECK_MC
4437	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4438	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4439	static IEMOPMEDIAOPTF3IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4440	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4441	# else
4442	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4443	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4444	# endif
4445	#else
4446	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4447	#endif
4448	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS
4449	* Generate AVX function tables for the @a a_InstrNm instruction.
4450	* @sa IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX */
4451	#define IEMOPMEDIAOPTF3IMM8_INIT_VARS(a_InstrNm) \
4452	IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4453	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4454	/** @} */
4455
4456
4457	/**
4458	* Function table for blend type instruction taking three full sized media source
4459	* registers and one full sized destination register, but no additional state
4460	* (AVX).
4461	*/
4462	typedef struct IEMOPBLENDOP
4463	{
4464	PFNIEMAIMPLAVXBLENDU128 pfnU128;
4465	PFNIEMAIMPLAVXBLENDU256 pfnU256;
4466	} IEMOPBLENDOP;
4467	/** Pointer to a media operation function table for 4 full sized ops (AVX). */
4468	typedef IEMOPBLENDOP const *PCIEMOPBLENDOP;
4469
4470	/** @def IEMOPBLENDOP_INIT_VARS_EX
4471	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4472	* given functions as initializers. For use in AVX functions where a pair of
4473	* functions are only used once and the function table need not be public. */
4474	#ifndef TST_IEM_CHECK_MC
4475	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4476	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4477	static IEMOPBLENDOP const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4478	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4479	# else
4480	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4481	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4482	# endif
4483	#else
4484	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4485	#endif
4486	/** @def IEMOPBLENDOP_INIT_VARS
4487	* Generate AVX function tables for the @a a_InstrNm instruction.
4488	* @sa IEMOPBLENDOP_INIT_VARS_EX */
4489	#define IEMOPBLENDOP_INIT_VARS(a_InstrNm) \
4490	IEMOPBLENDOP_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4491	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4492
4493
4494	/** @name SSE/AVX single/double precision floating point operations.
4495	* @{ */
4496	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
4497	typedef FNIEMAIMPLFPSSEF2U128 *PFNIEMAIMPLFPSSEF2U128;
4498	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128R32,(uint32_t uMxCsrIn, PX86XMMREG Result, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
4499	typedef FNIEMAIMPLFPSSEF2U128R32 *PFNIEMAIMPLFPSSEF2U128R32;
4500	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128R64,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
4501	typedef FNIEMAIMPLFPSSEF2U128R64 *PFNIEMAIMPLFPSSEF2U128R64;
4502
4503	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
4504	typedef FNIEMAIMPLFPAVXF3U128 *PFNIEMAIMPLFPAVXF3U128;
4505	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U128R32,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
4506	typedef FNIEMAIMPLFPAVXF3U128R32 *PFNIEMAIMPLFPAVXF3U128R32;
4507	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U128R64,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
4508	typedef FNIEMAIMPLFPAVXF3U128R64 *PFNIEMAIMPLFPAVXF3U128R64;
4509
4510	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U256,(uint32_t uMxCsrIn, PX86YMMREG pResult, PCX86YMMREG puSrc1, PCX86YMMREG puSrc2));
4511	typedef FNIEMAIMPLFPAVXF3U256 *PFNIEMAIMPLFPAVXF3U256;
4512
4513	FNIEMAIMPLFPSSEF2U128 iemAImpl_addps_u128;
4514	FNIEMAIMPLFPSSEF2U128 iemAImpl_addpd_u128;
4515	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulps_u128;
4516	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulpd_u128;
4517	FNIEMAIMPLFPSSEF2U128 iemAImpl_subps_u128;
4518	FNIEMAIMPLFPSSEF2U128 iemAImpl_subpd_u128;
4519	FNIEMAIMPLFPSSEF2U128 iemAImpl_minps_u128;
4520	FNIEMAIMPLFPSSEF2U128 iemAImpl_minpd_u128;
4521	FNIEMAIMPLFPSSEF2U128 iemAImpl_divps_u128;
4522	FNIEMAIMPLFPSSEF2U128 iemAImpl_divpd_u128;
4523	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxps_u128;
4524	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxpd_u128;
4525	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddps_u128;
4526	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddpd_u128;
4527	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubps_u128;
4528	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubpd_u128;
4529	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtps_u128;
4530	FNIEMAIMPLFPSSEF2U128 iemAImpl_rsqrtps_u128;
4531	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtpd_u128;
4532	FNIEMAIMPLFPSSEF2U128 iemAImpl_rcpps_u128;
4533	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubps_u128;
4534	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubpd_u128;
4535
4536	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2ps_u128;
4537	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_cvtps2pd_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, uint64_t const *pu64Src));
4538
4539	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2ps_u128;
4540	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2dq_u128;
4541	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttps2dq_u128;
4542	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttpd2dq_u128;
4543	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2pd_u128;
4544	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2dq_u128;
4545
4546	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_addss_u128_r32;
4547	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_addsd_u128_r64;
4548	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_mulss_u128_r32;
4549	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_mulsd_u128_r64;
4550	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_subss_u128_r32;
4551	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_subsd_u128_r64;
4552	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_minss_u128_r32;
4553	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_minsd_u128_r64;
4554	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_divss_u128_r32;
4555	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_divsd_u128_r64;
4556	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_maxss_u128_r32;
4557	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_maxsd_u128_r64;
4558	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_cvtss2sd_u128_r32;
4559	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_cvtsd2ss_u128_r64;
4560	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_sqrtss_u128_r32;
4561	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_sqrtsd_u128_r64;
4562	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_rsqrtss_u128_r32;
4563	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_rcpss_u128_r32;
4564
4565	FNIEMAIMPLMEDIAF3U128 iemAImpl_vaddps_u128, iemAImpl_vaddps_u128_fallback;
4566	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddpd_u128, iemAImpl_vaddpd_u128_fallback;
4567	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulps_u128, iemAImpl_vmulps_u128_fallback;
4568	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulpd_u128, iemAImpl_vmulpd_u128_fallback;
4569	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubps_u128, iemAImpl_vsubps_u128_fallback;
4570	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubpd_u128, iemAImpl_vsubpd_u128_fallback;
4571	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminps_u128, iemAImpl_vminps_u128_fallback;
4572	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminpd_u128, iemAImpl_vminpd_u128_fallback;
4573	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivps_u128, iemAImpl_vdivps_u128_fallback;
4574	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivpd_u128, iemAImpl_vdivpd_u128_fallback;
4575	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxps_u128, iemAImpl_vmaxps_u128_fallback;
4576	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxpd_u128, iemAImpl_vmaxpd_u128_fallback;
4577	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddps_u128, iemAImpl_vhaddps_u128_fallback;
4578	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddpd_u128, iemAImpl_vhaddpd_u128_fallback;
4579	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubps_u128, iemAImpl_vhsubps_u128_fallback;
4580	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubpd_u128, iemAImpl_vhsubpd_u128_fallback;
4581	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtps_u128, iemAImpl_vsqrtps_u128_fallback;
4582	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtpd_u128, iemAImpl_vsqrtpd_u128_fallback;
4583	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubps_u128, iemAImpl_vaddsubps_u128_fallback;
4584	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubpd_u128, iemAImpl_vaddsubpd_u128_fallback;
4585	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtpd2ps_u128, iemAImpl_vcvtpd2ps_u128_fallback;
4586	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtps2pd_u128, iemAImpl_vcvtps2pd_u128_fallback;
4587
4588	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vaddss_u128_r32, iemAImpl_vaddss_u128_r32_fallback;
4589	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vaddsd_u128_r64, iemAImpl_vaddsd_u128_r64_fallback;
4590	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmulss_u128_r32, iemAImpl_vmulss_u128_r32_fallback;
4591	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmulsd_u128_r64, iemAImpl_vmulsd_u128_r64_fallback;
4592	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsubss_u128_r32, iemAImpl_vsubss_u128_r32_fallback;
4593	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsubsd_u128_r64, iemAImpl_vsubsd_u128_r64_fallback;
4594	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vminss_u128_r32, iemAImpl_vminss_u128_r32_fallback;
4595	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vminsd_u128_r64, iemAImpl_vminsd_u128_r64_fallback;
4596	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vdivss_u128_r32, iemAImpl_vdivss_u128_r32_fallback;
4597	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vdivsd_u128_r64, iemAImpl_vdivsd_u128_r64_fallback;
4598	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmaxss_u128_r32, iemAImpl_vmaxss_u128_r32_fallback;
4599	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmaxsd_u128_r64, iemAImpl_vmaxsd_u128_r64_fallback;
4600	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsqrtss_u128_r32, iemAImpl_vsqrtss_u128_r32_fallback;
4601	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsqrtsd_u128_r64, iemAImpl_vsqrtsd_u128_r64_fallback;
4602
4603	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddps_u256, iemAImpl_vaddps_u256_fallback;
4604	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddpd_u256, iemAImpl_vaddpd_u256_fallback;
4605	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulps_u256, iemAImpl_vmulps_u256_fallback;
4606	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulpd_u256, iemAImpl_vmulpd_u256_fallback;
4607	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubps_u256, iemAImpl_vsubps_u256_fallback;
4608	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubpd_u256, iemAImpl_vsubpd_u256_fallback;
4609	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminps_u256, iemAImpl_vminps_u256_fallback;
4610	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminpd_u256, iemAImpl_vminpd_u256_fallback;
4611	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivps_u256, iemAImpl_vdivps_u256_fallback;
4612	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivpd_u256, iemAImpl_vdivpd_u256_fallback;
4613	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxps_u256, iemAImpl_vmaxps_u256_fallback;
4614	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxpd_u256, iemAImpl_vmaxpd_u256_fallback;
4615	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddps_u256, iemAImpl_vhaddps_u256_fallback;
4616	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddpd_u256, iemAImpl_vhaddpd_u256_fallback;
4617	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubps_u256, iemAImpl_vhsubps_u256_fallback;
4618	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubpd_u256, iemAImpl_vhsubpd_u256_fallback;
4619	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubps_u256, iemAImpl_vhaddsubps_u256_fallback;
4620	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubpd_u256, iemAImpl_vhaddsubpd_u256_fallback;
4621	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtpd2ps_u256, iemAImpl_vcvtpd2ps_u256_fallback;
4622	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtps2pd_u256, iemAImpl_vcvtps2pd_u256_fallback;
4623	/** @} */
4624
4625	/** @name C instruction implementations for anything slightly complicated.
4626	* @{ */
4627
4628	/**
4629	* For typedef'ing or declaring a C instruction implementation function taking
4630	* no extra arguments.
4631	*
4632	* @param a_Name The name of the type.
4633	*/
4634	# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
4635	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
4636	/**
4637	* For defining a C instruction implementation function taking no extra
4638	* arguments.
4639	*
4640	* @param a_Name The name of the function
4641	*/
4642	# define IEM_CIMPL_DEF_0(a_Name) \
4643	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
4644	/**
4645	* Prototype version of IEM_CIMPL_DEF_0.
4646	*/
4647	# define IEM_CIMPL_PROTO_0(a_Name) \
4648	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
4649	/**
4650	* For calling a C instruction implementation function taking no extra
4651	* arguments.
4652	*
4653	* This special call macro adds default arguments to the call and allow us to
4654	* change these later.
4655	*
4656	* @param a_fn The name of the function.
4657	*/
4658	# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
4659
4660	/** Type for a C instruction implementation function taking no extra
4661	* arguments. */
4662	typedef IEM_CIMPL_DECL_TYPE_0(FNIEMCIMPL0);
4663	/** Function pointer type for a C instruction implementation function taking
4664	* no extra arguments. */
4665	typedef FNIEMCIMPL0 *PFNIEMCIMPL0;
4666
4667	/**
4668	* For typedef'ing or declaring a C instruction implementation function taking
4669	* one extra argument.
4670	*
4671	* @param a_Name The name of the type.
4672	* @param a_Type0 The argument type.
4673	* @param a_Arg0 The argument name.
4674	*/
4675	# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
4676	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
4677	/**
4678	* For defining a C instruction implementation function taking one extra
4679	* argument.
4680	*
4681	* @param a_Name The name of the function
4682	* @param a_Type0 The argument type.
4683	* @param a_Arg0 The argument name.
4684	*/
4685	# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
4686	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
4687	/**
4688	* Prototype version of IEM_CIMPL_DEF_1.
4689	*/
4690	# define IEM_CIMPL_PROTO_1(a_Name, a_Type0, a_Arg0) \
4691	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
4692	/**
4693	* For calling a C instruction implementation function taking one extra
4694	* argument.
4695	*
4696	* This special call macro adds default arguments to the call and allow us to
4697	* change these later.
4698	*
4699	* @param a_fn The name of the function.
4700	* @param a0 The name of the 1st argument.
4701	*/
4702	# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
4703
4704	/**
4705	* For typedef'ing or declaring a C instruction implementation function taking
4706	* two extra arguments.
4707	*
4708	* @param a_Name The name of the type.
4709	* @param a_Type0 The type of the 1st argument
4710	* @param a_Arg0 The name of the 1st argument.
4711	* @param a_Type1 The type of the 2nd argument.
4712	* @param a_Arg1 The name of the 2nd argument.
4713	*/
4714	# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
4715	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
4716	/**
4717	* For defining a C instruction implementation function taking two extra
4718	* arguments.
4719	*
4720	* @param a_Name The name of the function.
4721	* @param a_Type0 The type of the 1st argument
4722	* @param a_Arg0 The name of the 1st argument.
4723	* @param a_Type1 The type of the 2nd argument.
4724	* @param a_Arg1 The name of the 2nd argument.
4725	*/
4726	# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
4727	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
4728	/**
4729	* Prototype version of IEM_CIMPL_DEF_2.
4730	*/
4731	# define IEM_CIMPL_PROTO_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
4732	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
4733	/**
4734	* For calling a C instruction implementation function taking two extra
4735	* arguments.
4736	*
4737	* This special call macro adds default arguments to the call and allow us to
4738	* change these later.
4739	*
4740	* @param a_fn The name of the function.
4741	* @param a0 The name of the 1st argument.
4742	* @param a1 The name of the 2nd argument.
4743	*/
4744	# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
4745
4746	/**
4747	* For typedef'ing or declaring a C instruction implementation function taking
4748	* three extra arguments.
4749	*
4750	* @param a_Name The name of the type.
4751	* @param a_Type0 The type of the 1st argument
4752	* @param a_Arg0 The name of the 1st argument.
4753	* @param a_Type1 The type of the 2nd argument.
4754	* @param a_Arg1 The name of the 2nd argument.
4755	* @param a_Type2 The type of the 3rd argument.
4756	* @param a_Arg2 The name of the 3rd argument.
4757	*/
4758	# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
4759	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
4760	/**
4761	* For defining a C instruction implementation function taking three extra
4762	* arguments.
4763	*
4764	* @param a_Name The name of the function.
4765	* @param a_Type0 The type of the 1st argument
4766	* @param a_Arg0 The name of the 1st argument.
4767	* @param a_Type1 The type of the 2nd argument.
4768	* @param a_Arg1 The name of the 2nd argument.
4769	* @param a_Type2 The type of the 3rd argument.
4770	* @param a_Arg2 The name of the 3rd argument.
4771	*/
4772	# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
4773	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
4774	/**
4775	* Prototype version of IEM_CIMPL_DEF_3.
4776	*/
4777	# define IEM_CIMPL_PROTO_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
4778	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
4779	/**
4780	* For calling a C instruction implementation function taking three extra
4781	* arguments.
4782	*
4783	* This special call macro adds default arguments to the call and allow us to
4784	* change these later.
4785	*
4786	* @param a_fn The name of the function.
4787	* @param a0 The name of the 1st argument.
4788	* @param a1 The name of the 2nd argument.
4789	* @param a2 The name of the 3rd argument.
4790	*/
4791	# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
4792
4793
4794	/**
4795	* For typedef'ing or declaring a C instruction implementation function taking
4796	* four extra arguments.
4797	*
4798	* @param a_Name The name of the type.
4799	* @param a_Type0 The type of the 1st argument
4800	* @param a_Arg0 The name of the 1st argument.
4801	* @param a_Type1 The type of the 2nd argument.
4802	* @param a_Arg1 The name of the 2nd argument.
4803	* @param a_Type2 The type of the 3rd argument.
4804	* @param a_Arg2 The name of the 3rd argument.
4805	* @param a_Type3 The type of the 4th argument.
4806	* @param a_Arg3 The name of the 4th argument.
4807	*/
4808	# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
4809	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
4810	/**
4811	* For defining a C instruction implementation function taking four extra
4812	* arguments.
4813	*
4814	* @param a_Name The name of the function.
4815	* @param a_Type0 The type of the 1st argument
4816	* @param a_Arg0 The name of the 1st argument.
4817	* @param a_Type1 The type of the 2nd argument.
4818	* @param a_Arg1 The name of the 2nd argument.
4819	* @param a_Type2 The type of the 3rd argument.
4820	* @param a_Arg2 The name of the 3rd argument.
4821	* @param a_Type3 The type of the 4th argument.
4822	* @param a_Arg3 The name of the 4th argument.
4823	*/
4824	# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
4825	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4826	a_Type2 a_Arg2, a_Type3 a_Arg3))
4827	/**
4828	* Prototype version of IEM_CIMPL_DEF_4.
4829	*/
4830	# define IEM_CIMPL_PROTO_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
4831	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4832	a_Type2 a_Arg2, a_Type3 a_Arg3))
4833	/**
4834	* For calling a C instruction implementation function taking four extra
4835	* arguments.
4836	*
4837	* This special call macro adds default arguments to the call and allow us to
4838	* change these later.
4839	*
4840	* @param a_fn The name of the function.
4841	* @param a0 The name of the 1st argument.
4842	* @param a1 The name of the 2nd argument.
4843	* @param a2 The name of the 3rd argument.
4844	* @param a3 The name of the 4th argument.
4845	*/
4846	# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
4847
4848
4849	/**
4850	* For typedef'ing or declaring a C instruction implementation function taking
4851	* five extra arguments.
4852	*
4853	* @param a_Name The name of the type.
4854	* @param a_Type0 The type of the 1st argument
4855	* @param a_Arg0 The name of the 1st argument.
4856	* @param a_Type1 The type of the 2nd argument.
4857	* @param a_Arg1 The name of the 2nd argument.
4858	* @param a_Type2 The type of the 3rd argument.
4859	* @param a_Arg2 The name of the 3rd argument.
4860	* @param a_Type3 The type of the 4th argument.
4861	* @param a_Arg3 The name of the 4th argument.
4862	* @param a_Type4 The type of the 5th argument.
4863	* @param a_Arg4 The name of the 5th argument.
4864	*/
4865	# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
4866	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, \
4867	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
4868	a_Type3 a_Arg3, a_Type4 a_Arg4))
4869	/**
4870	* For defining a C instruction implementation function taking five extra
4871	* arguments.
4872	*
4873	* @param a_Name The name of the function.
4874	* @param a_Type0 The type of the 1st argument
4875	* @param a_Arg0 The name of the 1st argument.
4876	* @param a_Type1 The type of the 2nd argument.
4877	* @param a_Arg1 The name of the 2nd argument.
4878	* @param a_Type2 The type of the 3rd argument.
4879	* @param a_Arg2 The name of the 3rd argument.
4880	* @param a_Type3 The type of the 4th argument.
4881	* @param a_Arg3 The name of the 4th argument.
4882	* @param a_Type4 The type of the 5th argument.
4883	* @param a_Arg4 The name of the 5th argument.
4884	*/
4885	# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
4886	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4887	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
4888	/**
4889	* Prototype version of IEM_CIMPL_DEF_5.
4890	*/
4891	# define IEM_CIMPL_PROTO_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
4892	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4893	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
4894	/**
4895	* For calling a C instruction implementation function taking five extra
4896	* arguments.
4897	*
4898	* This special call macro adds default arguments to the call and allow us to
4899	* change these later.
4900	*
4901	* @param a_fn The name of the function.
4902	* @param a0 The name of the 1st argument.
4903	* @param a1 The name of the 2nd argument.
4904	* @param a2 The name of the 3rd argument.
4905	* @param a3 The name of the 4th argument.
4906	* @param a4 The name of the 5th argument.
4907	*/
4908	# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
4909
4910	/** @} */
4911
4912
4913	/** @name Opcode Decoder Function Types.
4914	* @{ */
4915
4916	/** @typedef PFNIEMOP
4917	* Pointer to an opcode decoder function.
4918	*/
4919
4920	/** @def FNIEMOP_DEF
4921	* Define an opcode decoder function.
4922	*
4923	* We're using macors for this so that adding and removing parameters as well as
4924	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL
4925	*
4926	* @param a_Name The function name.
4927	*/
4928
4929	/** @typedef PFNIEMOPRM
4930	* Pointer to an opcode decoder function with RM byte.
4931	*/
4932
4933	/** @def FNIEMOPRM_DEF
4934	* Define an opcode decoder function with RM byte.
4935	*
4936	* We're using macors for this so that adding and removing parameters as well as
4937	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL_1
4938	*
4939	* @param a_Name The function name.
4940	*/
4941
4942	#if defined(__GNUC__) && defined(RT_ARCH_X86)
4943	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOP)(PVMCPUCC pVCpu);
4944	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4945	# define FNIEMOP_DEF(a_Name) \
4946	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu)
4947	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4948	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
4949	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4950	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
4951
4952	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
4953	typedef VBOXSTRICTRC (__fastcall * PFNIEMOP)(PVMCPUCC pVCpu);
4954	typedef VBOXSTRICTRC (__fastcall * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4955	# define FNIEMOP_DEF(a_Name) \
4956	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
4957	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4958	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
4959	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4960	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
4961
4962	#elif defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
4963	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
4964	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4965	# define FNIEMOP_DEF(a_Name) \
4966	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu)
4967	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4968	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
4969	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4970	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
4971
4972	#else
4973	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
4974	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4975	# define FNIEMOP_DEF(a_Name) \
4976	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
4977	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4978	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
4979	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4980	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
4981
4982	#endif
4983	#define FNIEMOPRM_DEF(a_Name) FNIEMOP_DEF_1(a_Name, uint8_t, bRm)
4984
4985	/**
4986	* Call an opcode decoder function.
4987	*
4988	* We're using macors for this so that adding and removing parameters can be
4989	* done as we please. See FNIEMOP_DEF.
4990	*/
4991	#define FNIEMOP_CALL(a_pfn) (a_pfn)(pVCpu)
4992
4993	/**
4994	* Call a common opcode decoder function taking one extra argument.
4995	*
4996	* We're using macors for this so that adding and removing parameters can be
4997	* done as we please. See FNIEMOP_DEF_1.
4998	*/
4999	#define FNIEMOP_CALL_1(a_pfn, a0) (a_pfn)(pVCpu, a0)
5000
5001	/**
5002	* Call a common opcode decoder function taking one extra argument.
5003	*
5004	* We're using macors for this so that adding and removing parameters can be
5005	* done as we please. See FNIEMOP_DEF_1.
5006	*/
5007	#define FNIEMOP_CALL_2(a_pfn, a0, a1) (a_pfn)(pVCpu, a0, a1)
5008	/** @} */
5009
5010
5011	/** @name Misc Helpers
5012	* @{ */
5013
5014	/** Used to shut up GCC warnings about variables that 'may be used uninitialized'
5015	* due to GCC lacking knowledge about the value range of a switch. */
5016	#if RT_CPLUSPLUS_PREREQ(202000)
5017	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: [[unlikely]] AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
5018	#else
5019	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
5020	#endif
5021
5022	/** Variant of IEM_NOT_REACHED_DEFAULT_CASE_RET that returns a custom value. */
5023	#if RT_CPLUSPLUS_PREREQ(202000)
5024	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: [[unlikely]] AssertFailedReturn(a_RetValue)
5025	#else
5026	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: AssertFailedReturn(a_RetValue)
5027	#endif
5028
5029	/**
5030	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
5031	* occation.
5032	*/
5033	#ifdef LOG_ENABLED
5034	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
5035	do { \
5036	/Log/ LogAlways(("%s: returning IEM_RETURN_ASPECT_NOT_IMPLEMENTED (line %d)\n", __FUNCTION__, __LINE__)); \
5037	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
5038	} while (0)
5039	#else
5040	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
5041	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
5042	#endif
5043
5044	/**
5045	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
5046	* occation using the supplied logger statement.
5047	*
5048	* @param a_LoggerArgs What to log on failure.
5049	*/
5050	#ifdef LOG_ENABLED
5051	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
5052	do { \
5053	LogAlways((LOG_FN_FMT ": ", __PRETTY_FUNCTION__)); LogAlways(a_LoggerArgs); \
5054	/LogFunc(a_LoggerArgs);/ \
5055	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
5056	} while (0)
5057	#else
5058	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
5059	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
5060	#endif
5061
5062	/**
5063	* Gets the CPU mode (from fExec) as a IEMMODE value.
5064	*
5065	* @returns IEMMODE
5066	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5067	*/
5068	#define IEM_GET_CPU_MODE(a_pVCpu) ((a_pVCpu)->iem.s.fExec & IEM_F_MODE_CPUMODE_MASK)
5069
5070	/**
5071	* Check if we're currently executing in real or virtual 8086 mode.
5072	*
5073	* @returns @c true if it is, @c false if not.
5074	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5075	*/
5076	#define IEM_IS_REAL_OR_V86_MODE(a_pVCpu) (( ((a_pVCpu)->iem.s.fExec ^ IEM_F_MODE_X86_PROT_MASK) \
5077	& (IEM_F_MODE_X86_V86_MASK \| IEM_F_MODE_X86_PROT_MASK)) != 0)
5078
5079	/**
5080	* Check if we're currently executing in virtual 8086 mode.
5081	*
5082	* @returns @c true if it is, @c false if not.
5083	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5084	*/
5085	#define IEM_IS_V86_MODE(a_pVCpu) (((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_V86_MASK) != 0)
5086
5087	/**
5088	* Check if we're currently executing in long mode.
5089	*
5090	* @returns @c true if it is, @c false if not.
5091	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5092	*/
5093	#define IEM_IS_LONG_MODE(a_pVCpu) (CPUMIsGuestInLongModeEx(IEM_GET_CTX(a_pVCpu)))
5094
5095	/**
5096	* Check if we're currently executing in a 16-bit code segment.
5097	*
5098	* @returns @c true if it is, @c false if not.
5099	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5100	*/
5101	#define IEM_IS_16BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_16BIT)
5102
5103	/**
5104	* Check if we're currently executing in a 32-bit code segment.
5105	*
5106	* @returns @c true if it is, @c false if not.
5107	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5108	*/
5109	#define IEM_IS_32BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_32BIT)
5110
5111	/**
5112	* Check if we're currently executing in a 64-bit code segment.
5113	*
5114	* @returns @c true if it is, @c false if not.
5115	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5116	*/
5117	#define IEM_IS_64BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_64BIT)
5118
5119	/**
5120	* Check if we're currently executing in real mode.
5121	*
5122	* @returns @c true if it is, @c false if not.
5123	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5124	*/
5125	#define IEM_IS_REAL_MODE(a_pVCpu) (!((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_PROT_MASK))
5126
5127	/**
5128	* Gets the current protection level (CPL).
5129	*
5130	* @returns 0..3
5131	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5132	*/
5133	#define IEM_GET_CPL(a_pVCpu) (((a_pVCpu)->iem.s.fExec >> IEM_F_X86_CPL_SHIFT) & IEM_F_X86_CPL_SMASK)
5134
5135	/**
5136	* Sets the current protection level (CPL).
5137	*
5138	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5139	*/
5140	#define IEM_SET_CPL(a_pVCpu, a_uCpl) \
5141	do { (a_pVCpu)->iem.s.fExec = ((a_pVCpu)->iem.s.fExec & ~IEM_F_X86_CPL_MASK) \| ((a_uCpl) << IEM_F_X86_CPL_SHIFT); } while (0)
5142
5143	/**
5144	* Returns a (const) pointer to the CPUMFEATURES for the guest CPU.
5145	* @returns PCCPUMFEATURES
5146	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5147	*/
5148	#define IEM_GET_GUEST_CPU_FEATURES(a_pVCpu) (&((a_pVCpu)->CTX_SUFF(pVM)->cpum.ro.GuestFeatures))
5149
5150	/**
5151	* Returns a (const) pointer to the CPUMFEATURES for the host CPU.
5152	* @returns PCCPUMFEATURES
5153	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5154	*/
5155	#define IEM_GET_HOST_CPU_FEATURES(a_pVCpu) (&g_CpumHostFeatures.s)
5156
5157	/**
5158	* Evaluates to true if we're presenting an Intel CPU to the guest.
5159	*/
5160	#define IEM_IS_GUEST_CPU_INTEL(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL )
5161
5162	/**
5163	* Evaluates to true if we're presenting an AMD CPU to the guest.
5164	*/
5165	#define IEM_IS_GUEST_CPU_AMD(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_AMD \|\| (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_HYGON )
5166
5167	/**
5168	* Check if the address is canonical.
5169	*/
5170	#define IEM_IS_CANONICAL(a_u64Addr) X86_IS_CANONICAL(a_u64Addr)
5171
5172	/** Checks if the ModR/M byte is in register mode or not. */
5173	#define IEM_IS_MODRM_REG_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT) )
5174	/** Checks if the ModR/M byte is in memory mode or not. */
5175	#define IEM_IS_MODRM_MEM_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT) )
5176
5177	/**
5178	* Gets the register (reg) part of a ModR/M encoding, with REX.R added in.
5179	*
5180	* For use during decoding.
5181	*/
5182	#define IEM_GET_MODRM_REG(a_pVCpu, a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| (a_pVCpu)->iem.s.uRexReg )
5183	/**
5184	* Gets the r/m part of a ModR/M encoding as a register index, with REX.B added in.
5185	*
5186	* For use during decoding.
5187	*/
5188	#define IEM_GET_MODRM_RM(a_pVCpu, a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) \| (a_pVCpu)->iem.s.uRexB )
5189
5190	/**
5191	* Gets the register (reg) part of a ModR/M encoding, without REX.R.
5192	*
5193	* For use during decoding.
5194	*/
5195	#define IEM_GET_MODRM_REG_8(a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) )
5196	/**
5197	* Gets the r/m part of a ModR/M encoding as a register index, without REX.B.
5198	*
5199	* For use during decoding.
5200	*/
5201	#define IEM_GET_MODRM_RM_8(a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) )
5202
5203	/**
5204	* Gets the register (reg) part of a ModR/M encoding as an extended 8-bit
5205	* register index, with REX.R added in.
5206	*
5207	* For use during decoding.
5208	*
5209	* @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
5210	*/
5211	#define IEM_GET_MODRM_REG_EX8(a_pVCpu, a_bRm) \
5212	( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
5213	\|\| !((a_bRm) & (4 << X86_MODRM_REG_SHIFT)) /* IEM_GET_MODRM_REG(pVCpu, a_bRm) < 4 */ \
5214	? IEM_GET_MODRM_REG(pVCpu, a_bRm) : (((a_bRm) >> X86_MODRM_REG_SHIFT) & 3) \| 16)
5215	/**
5216	* Gets the r/m part of a ModR/M encoding as an extended 8-bit register index,
5217	* with REX.B added in.
5218	*
5219	* For use during decoding.
5220	*
5221	* @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
5222	*/
5223	#define IEM_GET_MODRM_RM_EX8(a_pVCpu, a_bRm) \
5224	( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
5225	\|\| !((a_bRm) & 4) /* IEM_GET_MODRM_RM(pVCpu, a_bRm) < 4 */ \
5226	? IEM_GET_MODRM_RM(pVCpu, a_bRm) : ((a_bRm) & 3) \| 16)
5227
5228	/**
5229	* Combines the prefix REX and ModR/M byte for passing to
5230	* iemOpHlpCalcRmEffAddrThreadedAddr64().
5231	*
5232	* @returns The ModRM byte but with bit 3 set to REX.B and bit 4 to REX.X.
5233	* The two bits are part of the REG sub-field, which isn't needed in
5234	* iemOpHlpCalcRmEffAddrThreadedAddr64().
5235	*
5236	* For use during decoding/recompiling.
5237	*/
5238	#define IEM_GET_MODRM_EX(a_pVCpu, a_bRm) \
5239	( ((a_bRm) & ~X86_MODRM_REG_MASK) \
5240	\| (uint8_t)( (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X)) >> (25 - 3) ) )
5241	AssertCompile(IEM_OP_PRF_REX_B == RT_BIT_32(25));
5242	AssertCompile(IEM_OP_PRF_REX_X == RT_BIT_32(26));
5243
5244	/**
5245	* Gets the effective VEX.VVVV value.
5246	*
5247	* The 4th bit is ignored if not 64-bit code.
5248	* @returns effective V-register value.
5249	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5250	*/
5251	#define IEM_GET_EFFECTIVE_VVVV(a_pVCpu) \
5252	(IEM_IS_64BIT_CODE(a_pVCpu) ? (a_pVCpu)->iem.s.uVex3rdReg : (a_pVCpu)->iem.s.uVex3rdReg & 7)
5253
5254
5255	/**
5256	* Gets the register (reg) part of a the special 4th register byte used by
5257	* vblendvps and vblendvpd.
5258	*
5259	* For use during decoding.
5260	*/
5261	#define IEM_GET_IMM8_REG(a_pVCpu, a_bRegImm8) \
5262	(IEM_IS_64BIT_CODE(a_pVCpu) ? (a_bRegImm8) >> 4 : ((a_bRegImm8) >> 4) & 7)
5263
5264
5265	/**
5266	* Checks if we're executing inside an AMD-V or VT-x guest.
5267	*/
5268	#if defined(VBOX_WITH_NESTED_HWVIRT_VMX) \|\| defined(VBOX_WITH_NESTED_HWVIRT_SVM)
5269	# define IEM_IS_IN_GUEST(a_pVCpu) RT_BOOL((a_pVCpu)->iem.s.fExec & IEM_F_X86_CTX_IN_GUEST)
5270	#else
5271	# define IEM_IS_IN_GUEST(a_pVCpu) false
5272	#endif
5273
5274
5275	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5276
5277	/**
5278	* Check if the guest has entered VMX root operation.
5279	*/
5280	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxRootMode(IEM_GET_CTX(a_pVCpu)))
5281
5282	/**
5283	* Check if the guest has entered VMX non-root operation.
5284	*/
5285	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) ( ((a_pVCpu)->iem.s.fExec & (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST)) \
5286	== (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST) )
5287
5288	/**
5289	* Check if the nested-guest has the given Pin-based VM-execution control set.
5290	*/
5291	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_PinCtl) (CPUMIsGuestVmxPinCtlsSet(IEM_GET_CTX(a_pVCpu), (a_PinCtl)))
5292
5293	/**
5294	* Check if the nested-guest has the given Processor-based VM-execution control set.
5295	*/
5296	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_ProcCtl) (CPUMIsGuestVmxProcCtlsSet(IEM_GET_CTX(a_pVCpu), (a_ProcCtl)))
5297
5298	/**
5299	* Check if the nested-guest has the given Secondary Processor-based VM-execution
5300	* control set.
5301	*/
5302	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_ProcCtl2) (CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(a_pVCpu), (a_ProcCtl2)))
5303
5304	/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
5305	# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
5306
5307	/** Whether a shadow VMCS is present for the given VCPU. */
5308	# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
5309
5310	/** Gets the VMXON region pointer. */
5311	# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
5312
5313	/** Gets the guest-physical address of the current VMCS for the given VCPU. */
5314	# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
5315
5316	/** Whether a current VMCS is present for the given VCPU. */
5317	# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
5318
5319	/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
5320	# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
5321	do \
5322	{ \
5323	Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
5324	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
5325	} while (0)
5326
5327	/** Clears any current VMCS for the given VCPU. */
5328	# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
5329	do \
5330	{ \
5331	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
5332	} while (0)
5333
5334	/**
5335	* Invokes the VMX VM-exit handler for an instruction intercept.
5336	*/
5337	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) \
5338	do { return iemVmxVmexitInstr((a_pVCpu), (a_uExitReason), (a_cbInstr)); } while (0)
5339
5340	/**
5341	* Invokes the VMX VM-exit handler for an instruction intercept where the
5342	* instruction provides additional VM-exit information.
5343	*/
5344	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) \
5345	do { return iemVmxVmexitInstrNeedsInfo((a_pVCpu), (a_uExitReason), (a_uInstrId), (a_cbInstr)); } while (0)
5346
5347	/**
5348	* Invokes the VMX VM-exit handler for a task switch.
5349	*/
5350	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) \
5351	do { return iemVmxVmexitTaskSwitch((a_pVCpu), (a_enmTaskSwitch), (a_SelNewTss), (a_cbInstr)); } while (0)
5352
5353	/**
5354	* Invokes the VMX VM-exit handler for MWAIT.
5355	*/
5356	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) \
5357	do { return iemVmxVmexitInstrMwait((a_pVCpu), (a_fMonitorArmed), (a_cbInstr)); } while (0)
5358
5359	/**
5360	* Invokes the VMX VM-exit handler for EPT faults.
5361	*/
5362	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) \
5363	do { return iemVmxVmexitEpt(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr); } while (0)
5364
5365	/**
5366	* Invokes the VMX VM-exit handler.
5367	*/
5368	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) \
5369	do { return iemVmxVmexit((a_pVCpu), (a_uExitReason), (a_uExitQual)); } while (0)
5370
5371	#else
5372	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (false)
5373	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (false)
5374	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_cbInstr) (false)
5375	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_cbInstr) (false)
5376	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_cbInstr) (false)
5377	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5378	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5379	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5380	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5381	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5382	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) do { return VERR_VMX_IPE_1; } while (0)
5383
5384	#endif
5385
5386	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5387	/**
5388	* Checks if we're executing a guest using AMD-V.
5389	*/
5390	# define IEM_SVM_IS_IN_GUEST(a_pVCpu) ( (a_pVCpu->iem.s.fExec & (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST)) \
5391	== (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST))
5392	/**
5393	* Check if an SVM control/instruction intercept is set.
5394	*/
5395	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) \
5396	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmCtrlInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_Intercept)))
5397
5398	/**
5399	* Check if an SVM read CRx intercept is set.
5400	*/
5401	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
5402	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
5403
5404	/**
5405	* Check if an SVM write CRx intercept is set.
5406	*/
5407	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
5408	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
5409
5410	/**
5411	* Check if an SVM read DRx intercept is set.
5412	*/
5413	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
5414	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
5415
5416	/**
5417	* Check if an SVM write DRx intercept is set.
5418	*/
5419	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
5420	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
5421
5422	/**
5423	* Check if an SVM exception intercept is set.
5424	*/
5425	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) \
5426	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmXcptInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uVector)))
5427
5428	/**
5429	* Invokes the SVM \#VMEXIT handler for the nested-guest.
5430	*/
5431	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
5432	do { return iemSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2)); } while (0)
5433
5434	/**
5435	* Invokes the 'MOV CRx' SVM \#VMEXIT handler after constructing the
5436	* corresponding decode assist information.
5437	*/
5438	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) \
5439	do \
5440	{ \
5441	uint64_t uExitInfo1; \
5442	if ( IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmDecodeAssists \
5443	&& (a_enmAccessCrX) == IEMACCESSCRX_MOV_CRX) \
5444	uExitInfo1 = SVM_EXIT1_MOV_CRX_MASK \| ((a_iGReg) & 7); \
5445	else \
5446	uExitInfo1 = 0; \
5447	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, uExitInfo1, 0); \
5448	} while (0)
5449
5450	/** Check and handles SVM nested-guest instruction intercept and updates
5451	* NRIP if needed.
5452	*/
5453	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
5454	do \
5455	{ \
5456	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept)) \
5457	{ \
5458	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
5459	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2); \
5460	} \
5461	} while (0)
5462
5463	/** Checks and handles SVM nested-guest CR0 read intercept. */
5464	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
5465	do \
5466	{ \
5467	if (!IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, 0)) \
5468	{ /* probably likely */ } \
5469	else \
5470	{ \
5471	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
5472	IEM_SVM_VMEXIT_RET(a_pVCpu, SVM_EXIT_READ_CR0, a_uExitInfo1, a_uExitInfo2); \
5473	} \
5474	} while (0)
5475
5476	/**
5477	* Updates the NextRIP (NRI) field in the nested-guest VMCB.
5478	*/
5479	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) \
5480	do { \
5481	if (IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmNextRipSave) \
5482	CPUMGuestSvmUpdateNRip(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_cbInstr)); \
5483	} while (0)
5484
5485	#else
5486	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) (false)
5487	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
5488	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
5489	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
5490	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
5491	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) (false)
5492	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { return VERR_SVM_IPE_1; } while (0)
5493	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) do { return VERR_SVM_IPE_1; } while (0)
5494	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, \
5495	a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
5496	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
5497	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) do { } while (0)
5498
5499	#endif
5500
5501	/** @} */
5502
5503	uint32_t iemCalcExecDbgFlagsSlow(PVMCPUCC pVCpu);
5504	VBOXSTRICTRC iemExecInjectPendingTrap(PVMCPUCC pVCpu);
5505
5506
5507	/**
5508	* Selector descriptor table entry as fetched by iemMemFetchSelDesc.
5509	*/
5510	typedef union IEMSELDESC
5511	{
5512	/** The legacy view. */
5513	X86DESC Legacy;
5514	/** The long mode view. */
5515	X86DESC64 Long;
5516	} IEMSELDESC;
5517	/** Pointer to a selector descriptor table entry. */
5518	typedef IEMSELDESC *PIEMSELDESC;
5519
5520	/** @name Raising Exceptions.
5521	* @{ */
5522	VBOXSTRICTRC iemTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, uint32_t uNextEip, uint32_t fFlags,
5523	uint16_t uErr, uint64_t uCr2, RTSEL SelTSS, PIEMSELDESC pNewDescTSS) RT_NOEXCEPT;
5524
5525	VBOXSTRICTRC iemRaiseXcptOrInt(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags,
5526	uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
5527	#ifdef IEM_WITH_SETJMP
5528	DECL_NO_RETURN(void) iemRaiseXcptOrIntJmp(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector,
5529	uint32_t fFlags, uint16_t uErr, uint64_t uCr2) IEM_NOEXCEPT_MAY_LONGJMP;
5530	#endif
5531	VBOXSTRICTRC iemRaiseDivideError(PVMCPUCC pVCpu) RT_NOEXCEPT;
5532	#ifdef IEM_WITH_SETJMP
5533	DECL_NO_RETURN(void) iemRaiseDivideErrorJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5534	#endif
5535	VBOXSTRICTRC iemRaiseDebugException(PVMCPUCC pVCpu) RT_NOEXCEPT;
5536	VBOXSTRICTRC iemRaiseBoundRangeExceeded(PVMCPUCC pVCpu) RT_NOEXCEPT;
5537	VBOXSTRICTRC iemRaiseUndefinedOpcode(PVMCPUCC pVCpu) RT_NOEXCEPT;
5538	#ifdef IEM_WITH_SETJMP
5539	DECL_NO_RETURN(void) iemRaiseUndefinedOpcodeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5540	#endif
5541	VBOXSTRICTRC iemRaiseDeviceNotAvailable(PVMCPUCC pVCpu) RT_NOEXCEPT;
5542	#ifdef IEM_WITH_SETJMP
5543	DECL_NO_RETURN(void) iemRaiseDeviceNotAvailableJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5544	#endif
5545	VBOXSTRICTRC iemRaiseTaskSwitchFaultWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5546	VBOXSTRICTRC iemRaiseTaskSwitchFaultCurrentTSS(PVMCPUCC pVCpu) RT_NOEXCEPT;
5547	VBOXSTRICTRC iemRaiseTaskSwitchFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
5548	VBOXSTRICTRC iemRaiseTaskSwitchFaultBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5549	/VBOXSTRICTRC iemRaiseSelectorNotPresent(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;/
5550	VBOXSTRICTRC iemRaiseSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5551	VBOXSTRICTRC iemRaiseSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5552	VBOXSTRICTRC iemRaiseStackSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5553	VBOXSTRICTRC iemRaiseStackSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5554	VBOXSTRICTRC iemRaiseGeneralProtectionFault(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5555	VBOXSTRICTRC iemRaiseGeneralProtectionFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
5556	#ifdef IEM_WITH_SETJMP
5557	DECL_NO_RETURN(void) iemRaiseGeneralProtectionFault0Jmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5558	#endif
5559	VBOXSTRICTRC iemRaiseGeneralProtectionFaultBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
5560	VBOXSTRICTRC iemRaiseNotCanonical(PVMCPUCC pVCpu) RT_NOEXCEPT;
5561	VBOXSTRICTRC iemRaiseSelectorBounds(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
5562	#ifdef IEM_WITH_SETJMP
5563	DECL_NO_RETURN(void) iemRaiseSelectorBoundsJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
5564	#endif
5565	VBOXSTRICTRC iemRaiseSelectorBoundsBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
5566	#ifdef IEM_WITH_SETJMP
5567	DECL_NO_RETURN(void) iemRaiseSelectorBoundsBySelectorJmp(PVMCPUCC pVCpu, RTSEL Sel) IEM_NOEXCEPT_MAY_LONGJMP;
5568	#endif
5569	VBOXSTRICTRC iemRaiseSelectorInvalidAccess(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
5570	#ifdef IEM_WITH_SETJMP
5571	DECL_NO_RETURN(void) iemRaiseSelectorInvalidAccessJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
5572	#endif
5573	VBOXSTRICTRC iemRaisePageFault(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) RT_NOEXCEPT;
5574	#ifdef IEM_WITH_SETJMP
5575	DECL_NO_RETURN(void) iemRaisePageFaultJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) IEM_NOEXCEPT_MAY_LONGJMP;
5576	#endif
5577	VBOXSTRICTRC iemRaiseMathFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
5578	#ifdef IEM_WITH_SETJMP
5579	DECL_NO_RETURN(void) iemRaiseMathFaultJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5580	#endif
5581	VBOXSTRICTRC iemRaiseAlignmentCheckException(PVMCPUCC pVCpu) RT_NOEXCEPT;
5582	#ifdef IEM_WITH_SETJMP
5583	DECL_NO_RETURN(void) iemRaiseAlignmentCheckExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5584	#endif
5585	VBOXSTRICTRC iemRaiseSimdFpException(PVMCPUCC pVCpu) RT_NOEXCEPT;
5586	#ifdef IEM_WITH_SETJMP
5587	DECL_NO_RETURN(void) iemRaiseSimdFpExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5588	#endif
5589
5590	void iemLogSyscallRealModeInt(PVMCPUCC pVCpu, uint8_t u8Vector, uint8_t cbInstr);
5591	void iemLogSyscallProtModeInt(PVMCPUCC pVCpu, uint8_t u8Vector, uint8_t cbInstr);
5592
5593	IEM_CIMPL_DEF_0(iemCImplRaiseDivideError);
5594	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidLockPrefix);
5595	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidOpcode);
5596
5597	/**
5598	* Macro for calling iemCImplRaiseDivideError().
5599	*
5600	* This is for things that will _always_ decode to an \#DE, taking the
5601	* recompiler into consideration and everything.
5602	*
5603	* @return Strict VBox status code.
5604	*/
5605	#define IEMOP_RAISE_DIVIDE_ERROR_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseDivideError)
5606
5607	/**
5608	* Macro for calling iemCImplRaiseInvalidLockPrefix().
5609	*
5610	* This is for things that will _always_ decode to an \#UD, taking the
5611	* recompiler into consideration and everything.
5612	*
5613	* @return Strict VBox status code.
5614	*/
5615	#define IEMOP_RAISE_INVALID_LOCK_PREFIX_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidLockPrefix)
5616
5617	/**
5618	* Macro for calling iemCImplRaiseInvalidOpcode() for decode/static \#UDs.
5619	*
5620	* This is for things that will _always_ decode to an \#UD, taking the
5621	* recompiler into consideration and everything.
5622	*
5623	* @return Strict VBox status code.
5624	*/
5625	#define IEMOP_RAISE_INVALID_OPCODE_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidOpcode)
5626
5627	/**
5628	* Macro for calling iemCImplRaiseInvalidOpcode() for runtime-style \#UDs.
5629	*
5630	* Using this macro means you've got _buggy_ _code_ and are doing things that
5631	* belongs exclusively in IEMAllCImpl.cpp during decoding.
5632	*
5633	* @return Strict VBox status code.
5634	* @see IEMOP_RAISE_INVALID_OPCODE_RET
5635	*/
5636	#define IEMOP_RAISE_INVALID_OPCODE_RUNTIME_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidOpcode)
5637
5638	/** @} */
5639
5640	/** @name Register Access.
5641	* @{ */
5642	VBOXSTRICTRC iemRegRipRelativeJumpS8AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int8_t offNextInstr,
5643	IEMMODE enmEffOpSize) RT_NOEXCEPT;
5644	VBOXSTRICTRC iemRegRipRelativeJumpS16AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int16_t offNextInstr) RT_NOEXCEPT;
5645	VBOXSTRICTRC iemRegRipRelativeJumpS32AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int32_t offNextInstr,
5646	IEMMODE enmEffOpSize) RT_NOEXCEPT;
5647	/** @} */
5648
5649	/** @name FPU access and helpers.
5650	* @{ */
5651	void iemFpuPushResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
5652	void iemFpuPushResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5653	void iemFpuPushResultTwo(PVMCPUCC pVCpu, PIEMFPURESULTTWO pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
5654	void iemFpuStoreResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
5655	void iemFpuStoreResultThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
5656	void iemFpuStoreResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
5657	uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5658	void iemFpuStoreResultWithMemOpThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
5659	uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5660	void iemFpuUpdateOpcodeAndIp(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5661	void iemFpuUpdateFSW(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
5662	void iemFpuUpdateFSWThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
5663	void iemFpuUpdateFSWWithMemOp(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5664	void iemFpuUpdateFSWThenPopPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
5665	void iemFpuUpdateFSWWithMemOpThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5666	void iemFpuStackUnderflow(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
5667	void iemFpuStackUnderflowWithMemOp(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5668	void iemFpuStackUnderflowThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
5669	void iemFpuStackUnderflowWithMemOpThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5670	void iemFpuStackUnderflowThenPopPop(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5671	void iemFpuStackPushUnderflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5672	void iemFpuStackPushUnderflowTwo(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5673	void iemFpuStackPushOverflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5674	void iemFpuStackPushOverflowWithMemOp(PVMCPUCC pVCpu, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5675	/** @} */
5676
5677	/** @name SSE+AVX SIMD access and helpers.
5678	* @{ */
5679	void iemSseUpdateMxcsr(PVMCPUCC pVCpu, uint32_t fMxcsr) RT_NOEXCEPT;
5680	/** @} */
5681
5682	/** @name Memory access.
5683	* @{ */
5684
5685	/** Report a \#GP instead of \#AC and do not restrict to ring-3 */
5686	#define IEM_MEMMAP_F_ALIGN_GP RT_BIT_32(16)
5687	/** SSE access that should report a \#GP instead of \#AC, unless MXCSR.MM=1
5688	* when it works like normal \#AC. Always used with IEM_MEMMAP_F_ALIGN_GP. */
5689	#define IEM_MEMMAP_F_ALIGN_SSE RT_BIT_32(17)
5690	/** If \#AC is applicable, raise it. Always used with IEM_MEMMAP_F_ALIGN_GP.
5691	* Users include FXSAVE & FXRSTOR. */
5692	#define IEM_MEMMAP_F_ALIGN_GP_OR_AC RT_BIT_32(18)
5693
5694	VBOXSTRICTRC iemMemMap(PVMCPUCC pVCpu, void *ppvMem, uint8_t pbUnmapInfo, size_t cbMem, uint8_t iSegReg, RTGCPTR GCPtrMem,
5695	uint32_t fAccess, uint32_t uAlignCtl) RT_NOEXCEPT;
5696	VBOXSTRICTRC iemMemCommitAndUnmap(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5697	#ifndef IN_RING3
5698	VBOXSTRICTRC iemMemCommitAndUnmapPostponeTroubleToR3(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5699	#endif
5700	void iemMemRollbackAndUnmap(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5701	void iemMemRollback(PVMCPUCC pVCpu) RT_NOEXCEPT;
5702	VBOXSTRICTRC iemMemApplySegment(PVMCPUCC pVCpu, uint32_t fAccess, uint8_t iSegReg, size_t cbMem, PRTGCPTR pGCPtrMem) RT_NOEXCEPT;
5703	VBOXSTRICTRC iemMemMarkSelDescAccessed(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5704	VBOXSTRICTRC iemMemPageTranslateAndCheckAccess(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t cbAccess, uint32_t fAccess, PRTGCPHYS pGCPhysMem) RT_NOEXCEPT;
5705
5706	void iemOpcodeFlushLight(PVMCPUCC pVCpu, uint8_t cbInstr);
5707	void iemOpcodeFlushHeavy(PVMCPUCC pVCpu, uint8_t cbInstr);
5708	#ifdef IEM_WITH_CODE_TLB
5709	void iemOpcodeFetchBytesJmp(PVMCPUCC pVCpu, size_t cbDst, void *pvDst) IEM_NOEXCEPT_MAY_LONGJMP;
5710	#else
5711	VBOXSTRICTRC iemOpcodeFetchMoreBytes(PVMCPUCC pVCpu, size_t cbMin) RT_NOEXCEPT;
5712	#endif
5713	#ifdef IEM_WITH_SETJMP
5714	uint8_t iemOpcodeGetNextU8SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5715	uint16_t iemOpcodeGetNextU16SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5716	uint32_t iemOpcodeGetNextU32SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5717	uint64_t iemOpcodeGetNextU64SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5718	#else
5719	VBOXSTRICTRC iemOpcodeGetNextU8Slow(PVMCPUCC pVCpu, uint8_t *pb) RT_NOEXCEPT;
5720	VBOXSTRICTRC iemOpcodeGetNextS8SxU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
5721	VBOXSTRICTRC iemOpcodeGetNextS8SxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
5722	VBOXSTRICTRC iemOpcodeGetNextS8SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5723	VBOXSTRICTRC iemOpcodeGetNextU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
5724	VBOXSTRICTRC iemOpcodeGetNextU16ZxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
5725	VBOXSTRICTRC iemOpcodeGetNextU16ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5726	VBOXSTRICTRC iemOpcodeGetNextU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
5727	VBOXSTRICTRC iemOpcodeGetNextU32ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5728	VBOXSTRICTRC iemOpcodeGetNextS32SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5729	VBOXSTRICTRC iemOpcodeGetNextU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5730	#endif
5731
5732	VBOXSTRICTRC iemMemFetchDataU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5733	VBOXSTRICTRC iemMemFetchDataU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5734	VBOXSTRICTRC iemMemFetchDataU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5735	VBOXSTRICTRC iemMemFetchDataU32_ZX_U64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5736	VBOXSTRICTRC iemMemFetchDataU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5737	VBOXSTRICTRC iemMemFetchDataU64AlignedU128(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5738	VBOXSTRICTRC iemMemFetchDataR80(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5739	VBOXSTRICTRC iemMemFetchDataD80(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5740	VBOXSTRICTRC iemMemFetchDataU128(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5741	VBOXSTRICTRC iemMemFetchDataU128NoAc(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5742	VBOXSTRICTRC iemMemFetchDataU128AlignedSse(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5743	VBOXSTRICTRC iemMemFetchDataU256(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5744	VBOXSTRICTRC iemMemFetchDataU256NoAc(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5745	VBOXSTRICTRC iemMemFetchDataU256AlignedAvx(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5746	VBOXSTRICTRC iemMemFetchDataXdtr(PVMCPUCC pVCpu, uint16_t *pcbLimit, PRTGCPTR pGCPtrBase, uint8_t iSegReg,
5747	RTGCPTR GCPtrMem, IEMMODE enmOpSize) RT_NOEXCEPT;
5748	#ifdef IEM_WITH_SETJMP
5749	uint8_t iemMemFetchDataU8SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5750	uint16_t iemMemFetchDataU16SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5751	uint32_t iemMemFetchDataU32SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5752	uint32_t iemMemFlatFetchDataU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5753	uint64_t iemMemFetchDataU64SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5754	uint64_t iemMemFetchDataU64AlignedU128SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5755	void iemMemFetchDataR80SafeJmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5756	void iemMemFetchDataD80SafeJmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5757	void iemMemFetchDataU128SafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5758	void iemMemFetchDataU128NoAcSafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5759	void iemMemFetchDataU128AlignedSseSafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5760	void iemMemFetchDataU256SafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5761	void iemMemFetchDataU256NoAcSafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5762	void iemMemFetchDataU256AlignedAvxSafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5763	# if 0 /* these are inlined now */
5764	uint8_t iemMemFetchDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5765	uint16_t iemMemFetchDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5766	uint32_t iemMemFetchDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5767	uint32_t iemMemFlatFetchDataU32Jmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5768	uint64_t iemMemFetchDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5769	uint64_t iemMemFetchDataU64AlignedU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5770	void iemMemFetchDataR80Jmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5771	void iemMemFetchDataD80Jmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5772	void iemMemFetchDataU128Jmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5773	void iemMemFetchDataU128NoAcJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5774	void iemMemFetchDataU128AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5775	void iemMemFetchDataU256NoAcJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5776	void iemMemFetchDataU256AlignedAvxJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5777	# endif
5778	void iemMemFetchDataU256Jmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5779	#endif
5780
5781	VBOXSTRICTRC iemMemFetchSysU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5782	VBOXSTRICTRC iemMemFetchSysU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5783	VBOXSTRICTRC iemMemFetchSysU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5784	VBOXSTRICTRC iemMemFetchSysU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5785	VBOXSTRICTRC iemMemFetchSelDesc(PVMCPUCC pVCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt) RT_NOEXCEPT;
5786
5787	VBOXSTRICTRC iemMemStoreDataU8(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) RT_NOEXCEPT;
5788	VBOXSTRICTRC iemMemStoreDataU16(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) RT_NOEXCEPT;
5789	VBOXSTRICTRC iemMemStoreDataU32(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) RT_NOEXCEPT;
5790	VBOXSTRICTRC iemMemStoreDataU64(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) RT_NOEXCEPT;
5791	VBOXSTRICTRC iemMemStoreDataU128(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
5792	VBOXSTRICTRC iemMemStoreDataU128NoAc(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
5793	VBOXSTRICTRC iemMemStoreDataU128AlignedSse(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
5794	VBOXSTRICTRC iemMemStoreDataU256(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
5795	VBOXSTRICTRC iemMemStoreDataU256NoAc(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
5796	VBOXSTRICTRC iemMemStoreDataU256AlignedAvx(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
5797	VBOXSTRICTRC iemMemStoreDataXdtr(PVMCPUCC pVCpu, uint16_t cbLimit, RTGCPTR GCPtrBase, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5798	#ifdef IEM_WITH_SETJMP
5799	void iemMemStoreDataU8SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
5800	void iemMemStoreDataU16SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
5801	void iemMemStoreDataU32SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
5802	void iemMemStoreDataU64SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
5803	void iemMemStoreDataU128SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5804	void iemMemStoreDataU128NoAcSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT128U pu128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5805	void iemMemStoreDataU128AlignedSseSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT128U pu128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5806	void iemMemStoreDataU256SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5807	void iemMemStoreDataU256NoAcSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5808	void iemMemStoreDataU256AlignedAvxSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5809	void iemMemStoreDataR80SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTFLOAT80U pr80Value) IEM_NOEXCEPT_MAY_LONGJMP;
5810	void iemMemStoreDataD80SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTPBCD80U pd80Value) IEM_NOEXCEPT_MAY_LONGJMP;
5811	#if 0
5812	void iemMemStoreDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
5813	void iemMemStoreDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
5814	void iemMemStoreDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
5815	void iemMemStoreDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
5816	void iemMemStoreDataU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5817	void iemMemStoreDataNoAcU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5818	void iemMemStoreDataU256NoAcJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5819	void iemMemStoreDataU256AlignedAvxJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5820	#endif
5821	void iemMemStoreDataU128AlignedSseJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5822	void iemMemStoreDataU256Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5823	#endif
5824
5825	#ifdef IEM_WITH_SETJMP
5826	uint8_t iemMemMapDataU8RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5827	uint8_t iemMemMapDataU8AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5828	uint8_t iemMemMapDataU8WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5829	uint8_t const iemMemMapDataU8RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5830	uint16_t iemMemMapDataU16RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5831	uint16_t iemMemMapDataU16AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5832	uint16_t iemMemMapDataU16WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5833	uint16_t const iemMemMapDataU16RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5834	uint32_t iemMemMapDataU32RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5835	uint32_t iemMemMapDataU32AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5836	uint32_t iemMemMapDataU32WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5837	uint32_t const iemMemMapDataU32RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5838	uint64_t iemMemMapDataU64RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5839	uint64_t iemMemMapDataU64AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5840	uint64_t iemMemMapDataU64WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5841	uint64_t const iemMemMapDataU64RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5842	PRTFLOAT80U iemMemMapDataR80RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5843	PRTFLOAT80U iemMemMapDataR80WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5844	PCRTFLOAT80U iemMemMapDataR80RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5845	PRTPBCD80U iemMemMapDataD80RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5846	PRTPBCD80U iemMemMapDataD80WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5847	PCRTPBCD80U iemMemMapDataD80RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5848	PRTUINT128U iemMemMapDataU128RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5849	PRTUINT128U iemMemMapDataU128AtSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5850	PRTUINT128U iemMemMapDataU128WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5851	PCRTUINT128U iemMemMapDataU128RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5852
5853	void iemMemCommitAndUnmapJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5854	void iemMemCommitAndUnmapRwSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5855	void iemMemCommitAndUnmapAtSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5856	void iemMemCommitAndUnmapWoSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5857	void iemMemCommitAndUnmapRoSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5858	void iemMemRollbackAndUnmapWoSafe(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5859	#endif
5860
5861	VBOXSTRICTRC iemMemStackPushBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
5862	void *ppvMem, uint8_t pbUnmapInfo, uint64_t *puNewRsp) RT_NOEXCEPT;
5863	VBOXSTRICTRC iemMemStackPushCommitSpecial(PVMCPUCC pVCpu, uint8_t bUnmapInfo, uint64_t uNewRsp) RT_NOEXCEPT;
5864	VBOXSTRICTRC iemMemStackPushU16(PVMCPUCC pVCpu, uint16_t u16Value) RT_NOEXCEPT;
5865	VBOXSTRICTRC iemMemStackPushU32(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
5866	VBOXSTRICTRC iemMemStackPushU64(PVMCPUCC pVCpu, uint64_t u64Value) RT_NOEXCEPT;
5867	VBOXSTRICTRC iemMemStackPushU16Ex(PVMCPUCC pVCpu, uint16_t u16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5868	VBOXSTRICTRC iemMemStackPushU32Ex(PVMCPUCC pVCpu, uint32_t u32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5869	VBOXSTRICTRC iemMemStackPushU64Ex(PVMCPUCC pVCpu, uint64_t u64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5870	VBOXSTRICTRC iemMemStackPushU32SReg(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
5871	VBOXSTRICTRC iemMemStackPopBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
5872	void const *ppvMem, uint8_t pbUnmapInfo, uint64_t *puNewRsp) RT_NOEXCEPT;
5873	VBOXSTRICTRC iemMemStackPopContinueSpecial(PVMCPUCC pVCpu, size_t off, size_t cbMem,
5874	void const *ppvMem, uint8_t pbUnmapInfo, uint64_t uCurNewRsp) RT_NOEXCEPT;
5875	VBOXSTRICTRC iemMemStackPopDoneSpecial(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5876	VBOXSTRICTRC iemMemStackPopU16(PVMCPUCC pVCpu, uint16_t *pu16Value) RT_NOEXCEPT;
5877	VBOXSTRICTRC iemMemStackPopU32(PVMCPUCC pVCpu, uint32_t *pu32Value) RT_NOEXCEPT;
5878	VBOXSTRICTRC iemMemStackPopU64(PVMCPUCC pVCpu, uint64_t *pu64Value) RT_NOEXCEPT;
5879	VBOXSTRICTRC iemMemStackPopU16Ex(PVMCPUCC pVCpu, uint16_t *pu16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5880	VBOXSTRICTRC iemMemStackPopU32Ex(PVMCPUCC pVCpu, uint32_t *pu32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5881	VBOXSTRICTRC iemMemStackPopU64Ex(PVMCPUCC pVCpu, uint64_t *pu64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5882
5883	#ifdef IEM_WITH_SETJMP
5884	void iemMemStackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5885	void iemMemStackPushU32SafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5886	void iemMemStackPushU32SRegSafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5887	void iemMemStackPushU64SafeJmp(PVMCPUCC pVCpu, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5888	void iemMemStackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5889	void iemMemStackPopGRegU32SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5890	void iemMemStackPopGRegU64SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5891
5892	void iemMemFlat32StackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5893	void iemMemFlat32StackPushU32SafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5894	void iemMemFlat32StackPushU32SRegSafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5895	void iemMemFlat32StackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5896	void iemMemFlat32StackPopGRegU32SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5897
5898	void iemMemFlat64StackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5899	void iemMemFlat64StackPushU64SafeJmp(PVMCPUCC pVCpu, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5900	void iemMemFlat64StackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5901	void iemMemFlat64StackPopGRegU64SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5902
5903	void iemMemStoreStackU16SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5904	void iemMemStoreStackU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5905	void iemMemStoreStackU32SRegSafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5906	void iemMemStoreStackU64SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5907
5908	uint16_t iemMemFetchStackU16SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5909	uint32_t iemMemFetchStackU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5910	uint64_t iemMemFetchStackU64SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5911
5912	#endif
5913
5914	/** @} */
5915
5916	/** @name IEMAllCImpl.cpp
5917	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/'
5918	* @{ */
5919	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem16, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5920	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem32, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5921	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem64, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5922	IEM_CIMPL_PROTO_0(iemCImpl_popa_16);
5923	IEM_CIMPL_PROTO_0(iemCImpl_popa_32);
5924	IEM_CIMPL_PROTO_0(iemCImpl_pusha_16);
5925	IEM_CIMPL_PROTO_0(iemCImpl_pusha_32);
5926	IEM_CIMPL_PROTO_1(iemCImpl_pushf, IEMMODE, enmEffOpSize);
5927	IEM_CIMPL_PROTO_1(iemCImpl_popf, IEMMODE, enmEffOpSize);
5928	IEM_CIMPL_PROTO_3(iemCImpl_FarJmp, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
5929	IEM_CIMPL_PROTO_3(iemCImpl_callf, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
5930	typedef IEM_CIMPL_DECL_TYPE_3(FNIEMCIMPLFARBRANCH, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
5931	typedef FNIEMCIMPLFARBRANCH *PFNIEMCIMPLFARBRANCH;
5932	IEM_CIMPL_PROTO_2(iemCImpl_retf, IEMMODE, enmEffOpSize, uint16_t, cbPop);
5933	IEM_CIMPL_PROTO_3(iemCImpl_enter, IEMMODE, enmEffOpSize, uint16_t, cbFrame, uint8_t, cParameters);
5934	IEM_CIMPL_PROTO_1(iemCImpl_leave, IEMMODE, enmEffOpSize);
5935	IEM_CIMPL_PROTO_2(iemCImpl_int, uint8_t, u8Int, IEMINT, enmInt);
5936	IEM_CIMPL_PROTO_1(iemCImpl_iret_real_v8086, IEMMODE, enmEffOpSize);
5937	IEM_CIMPL_PROTO_4(iemCImpl_iret_prot_v8086, uint32_t, uNewEip, uint16_t, uNewCs, uint32_t, uNewFlags, uint64_t, uNewRsp);
5938	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot_NestedTask, IEMMODE, enmEffOpSize);
5939	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot, IEMMODE, enmEffOpSize);
5940	IEM_CIMPL_PROTO_1(iemCImpl_iret_64bit, IEMMODE, enmEffOpSize);
5941	IEM_CIMPL_PROTO_1(iemCImpl_iret, IEMMODE, enmEffOpSize);
5942	IEM_CIMPL_PROTO_0(iemCImpl_loadall286);
5943	IEM_CIMPL_PROTO_0(iemCImpl_syscall);
5944	IEM_CIMPL_PROTO_1(iemCImpl_sysret, IEMMODE, enmEffOpSize);
5945	IEM_CIMPL_PROTO_0(iemCImpl_sysenter);
5946	IEM_CIMPL_PROTO_1(iemCImpl_sysexit, IEMMODE, enmEffOpSize);
5947	IEM_CIMPL_PROTO_2(iemCImpl_LoadSReg, uint8_t, iSegReg, uint16_t, uSel);
5948	IEM_CIMPL_PROTO_2(iemCImpl_load_SReg, uint8_t, iSegReg, uint16_t, uSel);
5949	IEM_CIMPL_PROTO_2(iemCImpl_pop_Sreg, uint8_t, iSegReg, IEMMODE, enmEffOpSize);
5950	IEM_CIMPL_PROTO_5(iemCImpl_load_SReg_Greg, uint16_t, uSel, uint64_t, offSeg, uint8_t, iSegReg, uint8_t, iGReg, IEMMODE, enmEffOpSize);
5951	IEM_CIMPL_PROTO_2(iemCImpl_VerX, uint16_t, uSel, bool, fWrite);
5952	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u64, uint64_t *, pu64Dst, uint16_t, uSel, bool, fIsLar);
5953	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u16, uint16_t *, pu16Dst, uint16_t, uSel, bool, fIsLar);
5954	IEM_CIMPL_PROTO_3(iemCImpl_lgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
5955	IEM_CIMPL_PROTO_2(iemCImpl_sgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5956	IEM_CIMPL_PROTO_3(iemCImpl_lidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
5957	IEM_CIMPL_PROTO_2(iemCImpl_sidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5958	IEM_CIMPL_PROTO_1(iemCImpl_lldt, uint16_t, uNewLdt);
5959	IEM_CIMPL_PROTO_2(iemCImpl_sldt_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
5960	IEM_CIMPL_PROTO_2(iemCImpl_sldt_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5961	IEM_CIMPL_PROTO_1(iemCImpl_ltr, uint16_t, uNewTr);
5962	IEM_CIMPL_PROTO_2(iemCImpl_str_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
5963	IEM_CIMPL_PROTO_2(iemCImpl_str_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5964	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Cd, uint8_t, iGReg, uint8_t, iCrReg);
5965	IEM_CIMPL_PROTO_2(iemCImpl_smsw_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
5966	IEM_CIMPL_PROTO_2(iemCImpl_smsw_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5967	IEM_CIMPL_PROTO_4(iemCImpl_load_CrX, uint8_t, iCrReg, uint64_t, uNewCrX, IEMACCESSCRX, enmAccessCrX, uint8_t, iGReg);
5968	IEM_CIMPL_PROTO_2(iemCImpl_mov_Cd_Rd, uint8_t, iCrReg, uint8_t, iGReg);
5969	IEM_CIMPL_PROTO_2(iemCImpl_lmsw, uint16_t, u16NewMsw, RTGCPTR, GCPtrEffDst);
5970	IEM_CIMPL_PROTO_0(iemCImpl_clts);
5971	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Dd, uint8_t, iGReg, uint8_t, iDrReg);
5972	IEM_CIMPL_PROTO_2(iemCImpl_mov_Dd_Rd, uint8_t, iDrReg, uint8_t, iGReg);
5973	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Td, uint8_t, iGReg, uint8_t, iTrReg);
5974	IEM_CIMPL_PROTO_2(iemCImpl_mov_Td_Rd, uint8_t, iTrReg, uint8_t, iGReg);
5975	IEM_CIMPL_PROTO_1(iemCImpl_invlpg, RTGCPTR, GCPtrPage);
5976	IEM_CIMPL_PROTO_3(iemCImpl_invpcid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvpcidDesc, uint64_t, uInvpcidType);
5977	IEM_CIMPL_PROTO_0(iemCImpl_invd);
5978	IEM_CIMPL_PROTO_0(iemCImpl_wbinvd);
5979	IEM_CIMPL_PROTO_0(iemCImpl_rsm);
5980	IEM_CIMPL_PROTO_0(iemCImpl_rdtsc);
5981	IEM_CIMPL_PROTO_0(iemCImpl_rdtscp);
5982	IEM_CIMPL_PROTO_0(iemCImpl_rdpmc);
5983	IEM_CIMPL_PROTO_0(iemCImpl_rdmsr);
5984	IEM_CIMPL_PROTO_0(iemCImpl_wrmsr);
5985	IEM_CIMPL_PROTO_3(iemCImpl_in, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
5986	IEM_CIMPL_PROTO_2(iemCImpl_in_eAX_DX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
5987	IEM_CIMPL_PROTO_3(iemCImpl_out, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
5988	IEM_CIMPL_PROTO_2(iemCImpl_out_DX_eAX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
5989	IEM_CIMPL_PROTO_0(iemCImpl_cli);
5990	IEM_CIMPL_PROTO_0(iemCImpl_sti);
5991	IEM_CIMPL_PROTO_0(iemCImpl_hlt);
5992	IEM_CIMPL_PROTO_1(iemCImpl_monitor, uint8_t, iEffSeg);
5993	IEM_CIMPL_PROTO_0(iemCImpl_mwait);
5994	IEM_CIMPL_PROTO_0(iemCImpl_swapgs);
5995	IEM_CIMPL_PROTO_0(iemCImpl_cpuid);
5996	IEM_CIMPL_PROTO_1(iemCImpl_aad, uint8_t, bImm);
5997	IEM_CIMPL_PROTO_1(iemCImpl_aam, uint8_t, bImm);
5998	IEM_CIMPL_PROTO_0(iemCImpl_daa);
5999	IEM_CIMPL_PROTO_0(iemCImpl_das);
6000	IEM_CIMPL_PROTO_0(iemCImpl_aaa);
6001	IEM_CIMPL_PROTO_0(iemCImpl_aas);
6002	IEM_CIMPL_PROTO_3(iemCImpl_bound_16, int16_t, idxArray, int16_t, idxLowerBound, int16_t, idxUpperBound);
6003	IEM_CIMPL_PROTO_3(iemCImpl_bound_32, int32_t, idxArray, int32_t, idxLowerBound, int32_t, idxUpperBound);
6004	IEM_CIMPL_PROTO_0(iemCImpl_xgetbv);
6005	IEM_CIMPL_PROTO_0(iemCImpl_xsetbv);
6006	IEM_CIMPL_PROTO_5(iemCImpl_cmpxchg16b_fallback_rendezvous, PRTUINT128U, pu128Dst, PRTUINT128U, pu128RaxRdx,
6007	PRTUINT128U, pu128RbxRcx, uint32_t *, pEFlags, uint8_t, bUnmapInfo);
6008	IEM_CIMPL_PROTO_2(iemCImpl_clflush_clflushopt, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
6009	IEM_CIMPL_PROTO_1(iemCImpl_finit, bool, fCheckXcpts);
6010	IEM_CIMPL_PROTO_3(iemCImpl_fxsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
6011	IEM_CIMPL_PROTO_3(iemCImpl_fxrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
6012	IEM_CIMPL_PROTO_3(iemCImpl_xsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
6013	IEM_CIMPL_PROTO_3(iemCImpl_xrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
6014	IEM_CIMPL_PROTO_2(iemCImpl_stmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
6015	IEM_CIMPL_PROTO_2(iemCImpl_vstmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
6016	IEM_CIMPL_PROTO_2(iemCImpl_ldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
6017	IEM_CIMPL_PROTO_3(iemCImpl_fnstenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6018	IEM_CIMPL_PROTO_3(iemCImpl_fnsave, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6019	IEM_CIMPL_PROTO_3(iemCImpl_fldenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6020	IEM_CIMPL_PROTO_3(iemCImpl_frstor, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6021	IEM_CIMPL_PROTO_1(iemCImpl_fldcw, uint16_t, u16Fcw);
6022	IEM_CIMPL_PROTO_2(iemCImpl_fxch_underflow, uint8_t, iStReg, uint16_t, uFpuOpcode);
6023	IEM_CIMPL_PROTO_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, bool, fUCmp, uint32_t, uPopAndFpuOpcode);
6024	IEM_CIMPL_PROTO_2(iemCImpl_rdseed, uint8_t, iReg, IEMMODE, enmEffOpSize);
6025	IEM_CIMPL_PROTO_2(iemCImpl_rdrand, uint8_t, iReg, IEMMODE, enmEffOpSize);
6026	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovps_load_u128, uint8_t, iXRegDst, uint8_t, iXRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6027	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovps_load_u256, uint8_t, iYRegDst, uint8_t, iYRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6028	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovps_store_u128, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iXRegMsk, uint8_t, iXRegSrc);
6029	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovps_store_u256, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iYRegMsk, uint8_t, iYRegSrc);
6030	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovd_load_u128, uint8_t, iXRegDst, uint8_t, iXRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6031	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovd_load_u256, uint8_t, iYRegDst, uint8_t, iYRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6032	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovd_store_u128, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iXRegMsk, uint8_t, iXRegSrc);
6033	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovd_store_u256, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iYRegMsk, uint8_t, iYRegSrc);
6034	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovpd_load_u128, uint8_t, iXRegDst, uint8_t, iXRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6035	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovpd_load_u256, uint8_t, iYRegDst, uint8_t, iYRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6036	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovpd_store_u128, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iXRegMsk, uint8_t, iXRegSrc);
6037	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovpd_store_u256, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iYRegMsk, uint8_t, iYRegSrc);
6038	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovq_load_u128, uint8_t, iXRegDst, uint8_t, iXRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6039	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovq_load_u256, uint8_t, iYRegDst, uint8_t, iYRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6040	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovq_store_u128, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iXRegMsk, uint8_t, iXRegSrc);
6041	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovq_store_u256, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iYRegMsk, uint8_t, iYRegSrc);
6042
6043	/** @} */
6044
6045	/** @name IEMAllCImplStrInstr.cpp.h
6046	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/' -e 's/RT_CONCAT4(//' \
6047	* -e 's/,ADDR_SIZE)/64/g' -e 's/,OP_SIZE,/64/g' -e 's/,OP_rAX,/rax/g' IEMAllCImplStrInstr.cpp.h
6048	* @{ */
6049	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr16, uint8_t, iEffSeg);
6050	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr16, uint8_t, iEffSeg);
6051	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m16);
6052	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m16);
6053	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr16, uint8_t, iEffSeg);
6054	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m16);
6055	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m16, int8_t, iEffSeg);
6056	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr16, bool, fIoChecked);
6057	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr16, bool, fIoChecked);
6058	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6059	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6060
6061	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr16, uint8_t, iEffSeg);
6062	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr16, uint8_t, iEffSeg);
6063	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m16);
6064	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m16);
6065	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr16, uint8_t, iEffSeg);
6066	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m16);
6067	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m16, int8_t, iEffSeg);
6068	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr16, bool, fIoChecked);
6069	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr16, bool, fIoChecked);
6070	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6071	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6072
6073	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr16, uint8_t, iEffSeg);
6074	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr16, uint8_t, iEffSeg);
6075	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m16);
6076	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m16);
6077	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr16, uint8_t, iEffSeg);
6078	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m16);
6079	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m16, int8_t, iEffSeg);
6080	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr16, bool, fIoChecked);
6081	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr16, bool, fIoChecked);
6082	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6083	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6084
6085
6086	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr32, uint8_t, iEffSeg);
6087	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr32, uint8_t, iEffSeg);
6088	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m32);
6089	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m32);
6090	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr32, uint8_t, iEffSeg);
6091	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m32);
6092	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m32, int8_t, iEffSeg);
6093	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr32, bool, fIoChecked);
6094	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr32, bool, fIoChecked);
6095	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6096	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6097
6098	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr32, uint8_t, iEffSeg);
6099	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr32, uint8_t, iEffSeg);
6100	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m32);
6101	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m32);
6102	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr32, uint8_t, iEffSeg);
6103	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m32);
6104	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m32, int8_t, iEffSeg);
6105	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr32, bool, fIoChecked);
6106	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr32, bool, fIoChecked);
6107	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6108	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6109
6110	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr32, uint8_t, iEffSeg);
6111	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr32, uint8_t, iEffSeg);
6112	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m32);
6113	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m32);
6114	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr32, uint8_t, iEffSeg);
6115	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m32);
6116	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m32, int8_t, iEffSeg);
6117	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr32, bool, fIoChecked);
6118	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr32, bool, fIoChecked);
6119	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6120	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6121
6122	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr32, uint8_t, iEffSeg);
6123	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr32, uint8_t, iEffSeg);
6124	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m32);
6125	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m32);
6126	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr32, uint8_t, iEffSeg);
6127	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m32);
6128	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m32, int8_t, iEffSeg);
6129	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr32, bool, fIoChecked);
6130	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr32, bool, fIoChecked);
6131	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6132	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6133
6134
6135	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr64, uint8_t, iEffSeg);
6136	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr64, uint8_t, iEffSeg);
6137	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m64);
6138	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m64);
6139	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr64, uint8_t, iEffSeg);
6140	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m64);
6141	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m64, int8_t, iEffSeg);
6142	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr64, bool, fIoChecked);
6143	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr64, bool, fIoChecked);
6144	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6145	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6146
6147	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr64, uint8_t, iEffSeg);
6148	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr64, uint8_t, iEffSeg);
6149	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m64);
6150	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m64);
6151	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr64, uint8_t, iEffSeg);
6152	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m64);
6153	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m64, int8_t, iEffSeg);
6154	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr64, bool, fIoChecked);
6155	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr64, bool, fIoChecked);
6156	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6157	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6158
6159	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr64, uint8_t, iEffSeg);
6160	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr64, uint8_t, iEffSeg);
6161	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m64);
6162	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m64);
6163	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr64, uint8_t, iEffSeg);
6164	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m64);
6165	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m64, int8_t, iEffSeg);
6166	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr64, bool, fIoChecked);
6167	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr64, bool, fIoChecked);
6168	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6169	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6170
6171	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr64, uint8_t, iEffSeg);
6172	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr64, uint8_t, iEffSeg);
6173	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m64);
6174	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m64);
6175	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr64, uint8_t, iEffSeg);
6176	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m64);
6177	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m64, int8_t, iEffSeg);
6178	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr64, bool, fIoChecked);
6179	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr64, bool, fIoChecked);
6180	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6181	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6182	/** @} */
6183
6184	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
6185	VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT;
6186	VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT;
6187	VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT;
6188	VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT;
6189	VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT;
6190	VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
6191	VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALKFAST pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT;
6192	VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT;
6193	VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT;
6194	VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
6195	bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT;
6196	VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
6197	bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT;
6198	VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6199	VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6200	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6201	VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6202	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6203	VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6204	VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT;
6205	VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
6206	RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT;
6207	VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT;
6208	VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT;
6209	VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT;
6210	uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT;
6211	void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT;
6212	VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
6213	uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT;
6214	bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT;
6215	IEM_CIMPL_PROTO_0(iemCImpl_vmxoff);
6216	IEM_CIMPL_PROTO_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon);
6217	IEM_CIMPL_PROTO_0(iemCImpl_vmlaunch);
6218	IEM_CIMPL_PROTO_0(iemCImpl_vmresume);
6219	IEM_CIMPL_PROTO_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
6220	IEM_CIMPL_PROTO_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
6221	IEM_CIMPL_PROTO_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
6222	IEM_CIMPL_PROTO_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField);
6223	IEM_CIMPL_PROTO_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField);
6224	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField);
6225	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg32, uint64_t *, pu32Dst, uint32_t, u32VmcsField);
6226	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField);
6227	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField);
6228	IEM_CIMPL_PROTO_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType);
6229	IEM_CIMPL_PROTO_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType);
6230	IEM_CIMPL_PROTO_0(iemCImpl_vmx_pause);
6231	#endif
6232
6233	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
6234	VBOXSTRICTRC iemSvmVmexit(PVMCPUCC pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2) RT_NOEXCEPT;
6235	VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr, uint64_t uCr2) RT_NOEXCEPT;
6236	VBOXSTRICTRC iemSvmHandleIOIntercept(PVMCPUCC pVCpu, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
6237	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, uint8_t cbInstr) RT_NOEXCEPT;
6238	VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPUCC pVCpu, uint32_t idMsr, bool fWrite, uint8_t cbInstr) RT_NOEXCEPT;
6239	IEM_CIMPL_PROTO_0(iemCImpl_vmrun);
6240	IEM_CIMPL_PROTO_0(iemCImpl_vmload);
6241	IEM_CIMPL_PROTO_0(iemCImpl_vmsave);
6242	IEM_CIMPL_PROTO_0(iemCImpl_clgi);
6243	IEM_CIMPL_PROTO_0(iemCImpl_stgi);
6244	IEM_CIMPL_PROTO_0(iemCImpl_invlpga);
6245	IEM_CIMPL_PROTO_0(iemCImpl_skinit);
6246	IEM_CIMPL_PROTO_0(iemCImpl_svm_pause);
6247	#endif
6248
6249	IEM_CIMPL_PROTO_0(iemCImpl_vmcall); /* vmx */
6250	IEM_CIMPL_PROTO_0(iemCImpl_vmmcall); /* svm */
6251	IEM_CIMPL_PROTO_1(iemCImpl_Hypercall, uint16_t, uDisOpcode); /* both */
6252
6253	extern const PFNIEMOP g_apfnIemInterpretOnlyOneByteMap[256];
6254	extern const PFNIEMOP g_apfnIemInterpretOnlyTwoByteMap[1024];
6255	extern const PFNIEMOP g_apfnIemInterpretOnlyThreeByte0f3a[1024];
6256	extern const PFNIEMOP g_apfnIemInterpretOnlyThreeByte0f38[1024];
6257	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap1[1024];
6258	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap2[1024];
6259	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap3[1024];
6260
6261	/*
6262	* Recompiler related stuff.
6263	*/
6264	extern const PFNIEMOP g_apfnIemThreadedRecompilerOneByteMap[256];
6265	extern const PFNIEMOP g_apfnIemThreadedRecompilerTwoByteMap[1024];
6266	extern const PFNIEMOP g_apfnIemThreadedRecompilerThreeByte0f3a[1024];
6267	extern const PFNIEMOP g_apfnIemThreadedRecompilerThreeByte0f38[1024];
6268	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap1[1024];
6269	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap2[1024];
6270	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap3[1024];
6271
6272	DECLCALLBACK(int) iemTbInit(PVMCC pVM, uint32_t cInitialTbs, uint32_t cMaxTbs,
6273	uint64_t cbInitialExec, uint64_t cbMaxExec, uint32_t cbChunkExec);
6274	void iemThreadedTbObsolete(PVMCPUCC pVCpu, PIEMTB pTb, bool fSafeToFree);
6275	DECLHIDDEN(void) iemTbAllocatorFree(PVMCPUCC pVCpu, PIEMTB pTb);
6276	void iemTbAllocatorProcessDelayedFrees(PVMCPUCC pVCpu, PIEMTBALLOCATOR pTbAllocator);
6277	void iemTbAllocatorFreeupNativeSpace(PVMCPUCC pVCpu, uint32_t cNeededInstrs);
6278	DECLHIDDEN(const char ) iemTbFlagsToString(uint32_t fFlags, char pszBuf, size_t cbBuf) RT_NOEXCEPT;
6279	DECLHIDDEN(void) iemThreadedDisassembleTb(PCIEMTB pTb, PCDBGFINFOHLP pHlp) RT_NOEXCEPT;
6280
6281
6282	/** @todo FNIEMTHREADEDFUNC and friends may need more work... */
6283	#if defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
6284	typedef VBOXSTRICTRC /__attribute__((__nothrow__))/ FNIEMTHREADEDFUNC(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
6285	typedef FNIEMTHREADEDFUNC *PFNIEMTHREADEDFUNC;
6286	# define IEM_DECL_IEMTHREADEDFUNC_DEF(a_Name) \
6287	VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2)
6288	# define IEM_DECL_IEMTHREADEDFUNC_PROTO(a_Name) \
6289	VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2)
6290
6291	#else
6292	typedef VBOXSTRICTRC (FNIEMTHREADEDFUNC)(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
6293	typedef FNIEMTHREADEDFUNC *PFNIEMTHREADEDFUNC;
6294	# define IEM_DECL_IEMTHREADEDFUNC_DEF(a_Name) \
6295	VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2) IEM_NOEXCEPT_MAY_LONGJMP
6296	# define IEM_DECL_IEMTHREADEDFUNC_PROTO(a_Name) \
6297	VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2) IEM_NOEXCEPT_MAY_LONGJMP
6298	#endif
6299
6300
6301	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_Nop);
6302	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_LogCpuState);
6303
6304	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_DeferToCImpl0);
6305
6306	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckIrq);
6307	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckMode);
6308	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckHwInstrBps);
6309	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLim);
6310
6311	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodes);
6312	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodes);
6313	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesConsiderCsLim);
6314
6315	/* Branching: */
6316	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndPcAndOpcodes);
6317	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckPcAndOpcodes);
6318	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckPcAndOpcodesConsiderCsLim);
6319
6320	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesLoadingTlb);
6321	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesLoadingTlb);
6322	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesLoadingTlbConsiderCsLim);
6323
6324	/* Natural page crossing: */
6325	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesAcrossPageLoadingTlb);
6326	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesAcrossPageLoadingTlb);
6327	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesAcrossPageLoadingTlbConsiderCsLim);
6328
6329	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesOnNextPageLoadingTlb);
6330	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNextPageLoadingTlb);
6331	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNextPageLoadingTlbConsiderCsLim);
6332
6333	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesOnNewPageLoadingTlb);
6334	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNewPageLoadingTlb);
6335	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNewPageLoadingTlbConsiderCsLim);
6336
6337	bool iemThreadedCompileEmitIrqCheckBefore(PVMCPUCC pVCpu, PIEMTB pTb);
6338	bool iemThreadedCompileBeginEmitCallsComplications(PVMCPUCC pVCpu, PIEMTB pTb);
6339
6340	/* Native recompiler public bits: */
6341	DECLHIDDEN(PIEMTB) iemNativeRecompile(PVMCPUCC pVCpu, PIEMTB pTb) RT_NOEXCEPT;
6342	DECLHIDDEN(void) iemNativeDisassembleTb(PCIEMTB pTb, PCDBGFINFOHLP pHlp) RT_NOEXCEPT;
6343	int iemExecMemAllocatorInit(PVMCPU pVCpu, uint64_t cbMax, uint64_t cbInitial, uint32_t cbChunk) RT_NOEXCEPT;
6344	DECLHIDDEN(void ) iemExecMemAllocatorAlloc(PVMCPU pVCpu, uint32_t cbReq, PIEMTB pTb, void *ppvExec) RT_NOEXCEPT;
6345	DECLHIDDEN(void) iemExecMemAllocatorReadyForUse(PVMCPUCC pVCpu, void *pv, size_t cb) RT_NOEXCEPT;
6346	void iemExecMemAllocatorFree(PVMCPU pVCpu, void *pv, size_t cb) RT_NOEXCEPT;
6347	DECLASM(DECL_NO_RETURN(void)) iemNativeTbLongJmp(void *pvFramePointer, int rc) RT_NOEXCEPT;
6348
6349	#endif /* !RT_IN_ASSEMBLER - ASM-NOINC-END */
6350
6351
6352	/** @} */
6353
6354	RT_C_DECLS_END
6355
6356	/* ASM-INC: %include "IEMInternalStruct.mac" */
6357
6358	#endif /* !VMM_INCLUDED_SRC_include_IEMInternal_h */
6359

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source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h@ 105184

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