IEMInternal.h@ 105231

Last change on this file since 105231 was 105231, checked in by vboxsync, 5 months ago
VMM/IEM: Implement vhaddpd instruction emulation, bugref:9898
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1	/* $Id: IEMInternal.h 105231 2024-07-09 10:39:41Z vboxsync $ */
2	/** @file
3	* IEM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2011-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_IEMInternal_h
29	#define VMM_INCLUDED_SRC_include_IEMInternal_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#ifndef RT_IN_ASSEMBLER
35	# include <VBox/vmm/cpum.h>
36	# include <VBox/vmm/iem.h>
37	# include <VBox/vmm/pgm.h>
38	# include <VBox/vmm/stam.h>
39	# include <VBox/param.h>
40
41	# include <iprt/setjmp-without-sigmask.h>
42	# include <iprt/list.h>
43	#endif /* !RT_IN_ASSEMBLER */
44
45
46	RT_C_DECLS_BEGIN
47
48
49	/** @defgroup grp_iem_int Internals
50	* @ingroup grp_iem
51	* @internal
52	* @{
53	*/
54
55	/* Make doxygen happy w/o overcomplicating the #if checks. */
56	#ifdef DOXYGEN_RUNNING
57	# define IEM_WITH_THROW_CATCH
58	# define VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
59	#endif
60
61	/** For expanding symbol in slickedit and other products tagging and
62	* crossreferencing IEM symbols. */
63	#ifndef IEM_STATIC
64	# define IEM_STATIC static
65	#endif
66
67	/** @def IEM_WITH_SETJMP
68	* Enables alternative status code handling using setjmps.
69	*
70	* This adds a bit of expense via the setjmp() call since it saves all the
71	* non-volatile registers. However, it eliminates return code checks and allows
72	* for more optimal return value passing (return regs instead of stack buffer).
73	*/
74	#if defined(DOXYGEN_RUNNING) \|\| defined(RT_OS_WINDOWS) \|\| 1
75	# define IEM_WITH_SETJMP
76	#endif
77
78	/** @def IEM_WITH_THROW_CATCH
79	* Enables using C++ throw/catch as an alternative to setjmp/longjmp in user
80	* mode code when IEM_WITH_SETJMP is in effect.
81	*
82	* With GCC 11.3.1 and code TLB on linux, using throw/catch instead of
83	* setjmp/long resulted in bs2-test-1 running 3.00% faster and all but on test
84	* result value improving by more than 1%. (Best out of three.)
85	*
86	* With Visual C++ 2019 and code TLB on windows, using throw/catch instead of
87	* setjmp/long resulted in bs2-test-1 running 3.68% faster and all but some of
88	* the MMIO and CPUID tests ran noticeably faster. Variation is greater than on
89	* Linux, but it should be quite a bit faster for normal code.
90	*/
91	#if defined(__cplusplus) && defined(IEM_WITH_SETJMP) && defined(IN_RING3) && (defined(__GNUC__) \|\| defined(_MSC_VER)) /* ASM-NOINC-START */
92	# define IEM_WITH_THROW_CATCH
93	#endif /ASM-NOINC-END/
94
95	/** @def IEMNATIVE_WITH_DELAYED_PC_UPDATING
96	* Enables the delayed PC updating optimization (see @bugref{10373}).
97	*/
98	#if defined(DOXYGEN_RUNNING) \|\| 1
99	# define IEMNATIVE_WITH_DELAYED_PC_UPDATING
100	#endif
101
102	/** Enables the SIMD register allocator @bugref{10614}. */
103	#if defined(DOXYGEN_RUNNING) \|\| 1
104	# define IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
105	#endif
106	/** Enables access to even callee saved registers. */
107	//# define IEMNATIVE_WITH_SIMD_REG_ACCESS_ALL_REGISTERS
108
109	#if defined(DOXYGEN_RUNNING) \|\| 1
110	/** @def IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
111	* Delay the writeback or dirty registers as long as possible. */
112	# define IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
113	#endif
114
115	/** @def IEM_WITH_TLB_STATISTICS
116	* Enables all TLB statistics. */
117	#if defined(VBOX_WITH_STATISTICS) \|\| defined(DOXYGEN_RUNNING)
118	# define IEM_WITH_TLB_STATISTICS
119	#endif
120
121	/** @def VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
122	* Enables a quicker alternative to throw/longjmp for IEM_DO_LONGJMP when
123	* executing native translation blocks.
124	*
125	* This exploits the fact that we save all non-volatile registers in the TB
126	* prologue and thus just need to do the same as the TB epilogue to get the
127	* effect of a longjmp/throw. Since MSC marks XMM6 thru XMM15 as
128	* non-volatile (and does something even more crazy for ARM), this probably
129	* won't work reliably on Windows. */
130	#ifdef RT_ARCH_ARM64
131	# ifndef RT_OS_WINDOWS
132	# define VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
133	# endif
134	#endif
135	/* ASM-NOINC-START */
136	#ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
137	# if !defined(IN_RING3) \
138	\|\| !defined(VBOX_WITH_IEM_RECOMPILER) \
139	\|\| !defined(VBOX_WITH_IEM_NATIVE_RECOMPILER)
140	# undef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
141	# elif defined(RT_OS_WINDOWS)
142	# pragma message("VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP is not safe to use on windows")
143	# endif
144	#endif
145
146
147	/** @def IEM_DO_LONGJMP
148	*
149	* Wrapper around longjmp / throw.
150	*
151	* @param a_pVCpu The CPU handle.
152	* @param a_rc The status code jump back with / throw.
153	*/
154	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
155	# ifdef IEM_WITH_THROW_CATCH
156	# ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
157	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) do { \
158	if ((a_pVCpu)->iem.s.pvTbFramePointerR3) \
159	iemNativeTbLongJmp((a_pVCpu)->iem.s.pvTbFramePointerR3, (a_rc)); \
160	throw int(a_rc); \
161	} while (0)
162	# else
163	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) throw int(a_rc)
164	# endif
165	# else
166	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) longjmp(*(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf), (a_rc))
167	# endif
168	#endif
169
170	/** For use with IEM function that may do a longjmp (when enabled).
171	*
172	* Visual C++ has trouble longjmp'ing from/over functions with the noexcept
173	* attribute. So, we indicate that function that may be part of a longjmp may
174	* throw "exceptions" and that the compiler should definitely not generate and
175	* std::terminate calling unwind code.
176	*
177	* Here is one example of this ending in std::terminate:
178	* @code{.txt}
179	00 00000041`cadfda10 00007ffc`5d5a1f9f ucrtbase!abort+0x4e
180	01 00000041`cadfda40 00007ffc`57af229a ucrtbase!terminate+0x1f
181	02 00000041`cadfda70 00007ffb`eec91030 VCRUNTIME140!__std_terminate+0xa [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\ehhelpers.cpp @ 192]
182	03 00000041`cadfdaa0 00007ffb`eec92c6d VCRUNTIME140_1!_CallSettingFrame+0x20 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\handlers.asm @ 50]
183	04 00000041`cadfdad0 00007ffb`eec93ae5 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToState+0x241 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 1085]
184	05 00000041`cadfdc00 00007ffb`eec92258 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToEmptyState+0x2d [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 218]
185	06 00000041`cadfdc30 00007ffb`eec940e9 VCRUNTIME140_1!__InternalCxxFrameHandler<__FrameHandler4>+0x194 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 304]
186	07 00000041`cadfdcd0 00007ffc`5f9f249f VCRUNTIME140_1!__CxxFrameHandler4+0xa9 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 290]
187	08 00000041`cadfdd40 00007ffc`5f980939 ntdll!RtlpExecuteHandlerForUnwind+0xf
188	09 00000041`cadfdd70 00007ffc`5f9a0edd ntdll!RtlUnwindEx+0x339
189	0a 00000041`cadfe490 00007ffc`57aff976 ntdll!RtlUnwind+0xcd
190	0b 00000041`cadfea00 00007ffb`e1b5de01 VCRUNTIME140!__longjmp_internal+0xe6 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\longjmp.asm @ 140]
191	0c (Inline Function) --------`-------- VBoxVMM!iemOpcodeGetNextU8SlowJmp+0x95 [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 1155]
192	0d 00000041`cadfea50 00007ffb`e1b60f6b VBoxVMM!iemOpcodeGetNextU8Jmp+0xc1 [L:\vbox-intern\src\VBox\VMM\include\IEMInline.h @ 402]
193	0e 00000041`cadfea90 00007ffb`e1cc6201 VBoxVMM!IEMExecForExits+0xdb [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 10185]
194	0f 00000041`cadfec70 00007ffb`e1d0df8d VBoxVMM!EMHistoryExec+0x4f1 [L:\vbox-intern\src\VBox\VMM\VMMAll\EMAll.cpp @ 452]
195	10 00000041`cadfed60 00007ffb`e1d0d4c0 VBoxVMM!nemR3WinHandleExitCpuId+0x79d [L:\vbox-intern\src\VBox\VMM\VMMAll\NEMAllNativeTemplate-win.cpp.h @ 1829] @encode
196	@endcode
197	*
198	* @see https://developercommunity.visualstudio.com/t/fragile-behavior-of-longjmp-called-from-noexcept-f/1532859
199	*/
200	#if defined(IEM_WITH_SETJMP) && (defined(_MSC_VER) \|\| defined(IEM_WITH_THROW_CATCH))
201	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT_EX(false)
202	#else
203	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT
204	#endif
205	/* ASM-NOINC-END */
206
207	#define IEM_IMPLEMENTS_TASKSWITCH
208
209	/** @def IEM_WITH_3DNOW
210	* Includes the 3DNow decoding. */
211	#if !defined(IEM_WITH_3DNOW) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
212	# ifndef IEM_WITHOUT_3DNOW
213	# define IEM_WITH_3DNOW
214	# endif
215	#endif
216
217	/** @def IEM_WITH_THREE_0F_38
218	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
219	#if !defined(IEM_WITH_THREE_0F_38) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
220	# ifndef IEM_WITHOUT_THREE_0F_38
221	# define IEM_WITH_THREE_0F_38
222	# endif
223	#endif
224
225	/** @def IEM_WITH_THREE_0F_3A
226	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
227	#if !defined(IEM_WITH_THREE_0F_3A) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
228	# ifndef IEM_WITHOUT_THREE_0F_3A
229	# define IEM_WITH_THREE_0F_3A
230	# endif
231	#endif
232
233	/** @def IEM_WITH_VEX
234	* Includes the VEX decoding. */
235	#if !defined(IEM_WITH_VEX) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
236	# ifndef IEM_WITHOUT_VEX
237	# define IEM_WITH_VEX
238	# endif
239	#endif
240
241	/** @def IEM_CFG_TARGET_CPU
242	* The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
243	*
244	* By default we allow this to be configured by the user via the
245	* CPUM/GuestCpuName config string, but this comes at a slight cost during
246	* decoding. So, for applications of this code where there is no need to
247	* be dynamic wrt target CPU, just modify this define.
248	*/
249	#if !defined(IEM_CFG_TARGET_CPU) \|\| defined(DOXYGEN_RUNNING)
250	# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
251	#endif
252
253	//#define IEM_WITH_CODE_TLB // - work in progress
254	//#define IEM_WITH_DATA_TLB // - work in progress
255
256
257	/** @def IEM_USE_UNALIGNED_DATA_ACCESS
258	* Use unaligned accesses instead of elaborate byte assembly. */
259	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86) \|\| defined(DOXYGEN_RUNNING) /ASM-NOINC/
260	# define IEM_USE_UNALIGNED_DATA_ACCESS
261	#endif /ASM-NOINC/
262
263	//#define IEM_LOG_MEMORY_WRITES
264
265
266
267	#ifndef RT_IN_ASSEMBLER /* ASM-NOINC-START - the rest of the file */
268
269	# if !defined(IEM_WITHOUT_INSTRUCTION_STATS) && !defined(DOXYGEN_RUNNING)
270	/** Instruction statistics. */
271	typedef struct IEMINSTRSTATS
272	{
273	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
274	# include "IEMInstructionStatisticsTmpl.h"
275	# undef IEM_DO_INSTR_STAT
276	} IEMINSTRSTATS;
277	#else
278	struct IEMINSTRSTATS;
279	typedef struct IEMINSTRSTATS IEMINSTRSTATS;
280	#endif
281	/** Pointer to IEM instruction statistics. */
282	typedef IEMINSTRSTATS *PIEMINSTRSTATS;
283
284
285	/** @name IEMTARGETCPU_EFL_BEHAVIOR_XXX - IEMCPU::aidxTargetCpuEflFlavour
286	* @{ */
287	#define IEMTARGETCPU_EFL_BEHAVIOR_NATIVE 0 /*< Native x86 EFLAGS result; Intel EFLAGS when on non-x86 hosts. /
288	#define IEMTARGETCPU_EFL_BEHAVIOR_INTEL 1 /*< Intel EFLAGS result. /
289	#define IEMTARGETCPU_EFL_BEHAVIOR_AMD 2 /*< AMD EFLAGS result /
290	#define IEMTARGETCPU_EFL_BEHAVIOR_RESERVED 3 /*< Reserved/dummy entry slot that's the same as 0. /
291	#define IEMTARGETCPU_EFL_BEHAVIOR_MASK 3 /*< For masking the index before use. /
292	/** Selects the right variant from a_aArray.
293	* pVCpu is implicit in the caller context. */
294	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT(a_aArray) \
295	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[1] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
296	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for when no native worker can
297	* be used because the host CPU does not support the operation. */
298	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_NON_NATIVE(a_aArray) \
299	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
300	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for a two dimentional
301	* array paralleling IEMCPU::aidxTargetCpuEflFlavour and a single bit index
302	* into the two.
303	* @sa IEM_SELECT_NATIVE_OR_FALLBACK */
304	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
305	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
306	(a_aaArray[a_fNative][pVCpu->iem.s.aidxTargetCpuEflFlavour[a_fNative] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
307	#else
308	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
309	(a_aaArray[0][pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
310	#endif
311	/** @} */
312
313	/**
314	* Picks @a a_pfnNative or @a a_pfnFallback according to the host CPU feature
315	* indicator given by @a a_fCpumFeatureMember (CPUMFEATURES member).
316	*
317	* On non-x86 hosts, this will shortcut to the fallback w/o checking the
318	* indicator.
319	*
320	* @sa IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX
321	*/
322	#if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
323	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) \
324	(g_CpumHostFeatures.s.a_fCpumFeatureMember ? a_pfnNative : a_pfnFallback)
325	#else
326	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) (a_pfnFallback)
327	#endif
328
329
330	/**
331	* Branch types.
332	*/
333	typedef enum IEMBRANCH
334	{
335	IEMBRANCH_JUMP = 1,
336	IEMBRANCH_CALL,
337	IEMBRANCH_TRAP,
338	IEMBRANCH_SOFTWARE_INT,
339	IEMBRANCH_HARDWARE_INT
340	} IEMBRANCH;
341	AssertCompileSize(IEMBRANCH, 4);
342
343
344	/**
345	* INT instruction types.
346	*/
347	typedef enum IEMINT
348	{
349	/** INT n instruction (opcode 0xcd imm). */
350	IEMINT_INTN = 0,
351	/** Single byte INT3 instruction (opcode 0xcc). */
352	IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
353	/** Single byte INTO instruction (opcode 0xce). */
354	IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
355	/** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
356	IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
357	} IEMINT;
358	AssertCompileSize(IEMINT, 4);
359
360
361	/**
362	* A FPU result.
363	*/
364	typedef struct IEMFPURESULT
365	{
366	/** The output value. */
367	RTFLOAT80U r80Result;
368	/** The output status. */
369	uint16_t FSW;
370	} IEMFPURESULT;
371	AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
372	/** Pointer to a FPU result. */
373	typedef IEMFPURESULT *PIEMFPURESULT;
374	/** Pointer to a const FPU result. */
375	typedef IEMFPURESULT const *PCIEMFPURESULT;
376
377
378	/**
379	* A FPU result consisting of two output values and FSW.
380	*/
381	typedef struct IEMFPURESULTTWO
382	{
383	/** The first output value. */
384	RTFLOAT80U r80Result1;
385	/** The output status. */
386	uint16_t FSW;
387	/** The second output value. */
388	RTFLOAT80U r80Result2;
389	} IEMFPURESULTTWO;
390	AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
391	AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
392	/** Pointer to a FPU result consisting of two output values and FSW. */
393	typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
394	/** Pointer to a const FPU result consisting of two output values and FSW. */
395	typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
396
397
398	/**
399	* IEM TLB entry.
400	*
401	* Lookup assembly:
402	* @code{.asm}
403	; Calculate tag.
404	mov rax, [VA]
405	shl rax, 16
406	shr rax, 16 + X86_PAGE_SHIFT
407	or rax, [uTlbRevision]
408
409	; Do indexing.
410	movzx ecx, al
411	lea rcx, [pTlbEntries + rcx]
412
413	; Check tag.
414	cmp [rcx + IEMTLBENTRY.uTag], rax
415	jne .TlbMiss
416
417	; Check access.
418	mov rax, ACCESS_FLAGS \| MAPPING_R3_NOT_VALID \| 0xffffff00
419	and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
420	cmp rax, [uTlbPhysRev]
421	jne .TlbMiss
422
423	; Calc address and we're done.
424	mov eax, X86_PAGE_OFFSET_MASK
425	and eax, [VA]
426	or rax, [rcx + IEMTLBENTRY.pMappingR3]
427	%ifdef VBOX_WITH_STATISTICS
428	inc qword [cTlbHits]
429	%endif
430	jmp .Done
431
432	.TlbMiss:
433	mov r8d, ACCESS_FLAGS
434	mov rdx, [VA]
435	mov rcx, [pVCpu]
436	call iemTlbTypeMiss
437	.Done:
438
439	@endcode
440	*
441	*/
442	typedef struct IEMTLBENTRY
443	{
444	/** The TLB entry tag.
445	* Bits 35 thru 0 are made up of the virtual address shifted right 12 bits, this
446	* is ASSUMING a virtual address width of 48 bits.
447	*
448	* Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
449	*
450	* The TLB lookup code uses the current TLB revision, which won't ever be zero,
451	* enabling an extremely cheap TLB invalidation most of the time. When the TLB
452	* revision wraps around though, the tags needs to be zeroed.
453	*
454	* @note Try use SHRD instruction? After seeing
455	* https://gmplib.org/~tege/x86-timing.pdf, maybe not.
456	*
457	* @todo This will need to be reorganized for 57-bit wide virtual address and
458	* PCID (currently 12 bits) and ASID (currently 6 bits) support. We'll
459	* have to move the TLB entry versioning entirely to the
460	* fFlagsAndPhysRev member then, 57 bit wide VAs means we'll only have
461	* 19 bits left (64 - 57 + 12 = 19) and they'll almost entire be
462	* consumed by PCID and ASID (12 + 6 = 18).
463	*/
464	uint64_t uTag;
465	/** Access flags and physical TLB revision.
466	*
467	* - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
468	* - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
469	* - Bit 2 - page tables - not user (complemented X86_PTE_US).
470	* - Bit 3 - pgm phys/virt - not directly writable.
471	* - Bit 4 - pgm phys page - not directly readable.
472	* - Bit 5 - page tables - not accessed (complemented X86_PTE_A).
473	* - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
474	* - Bit 7 - tlb entry - pMappingR3 member not valid.
475	* - Bits 63 thru 8 are used for the physical TLB revision number.
476	*
477	* We're using complemented bit meanings here because it makes it easy to check
478	* whether special action is required. For instance a user mode write access
479	* would do a "TEST fFlags, (X86_PTE_RW \| X86_PTE_US \| X86_PTE_D)" and a
480	* non-zero result would mean special handling needed because either it wasn't
481	* writable, or it wasn't user, or the page wasn't dirty. A user mode read
482	* access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
483	* need to check any PTE flag.
484	*/
485	uint64_t fFlagsAndPhysRev;
486	/** The guest physical page address. */
487	uint64_t GCPhys;
488	/** Pointer to the ring-3 mapping. */
489	R3PTRTYPE(uint8_t *) pbMappingR3;
490	#if HC_ARCH_BITS == 32
491	uint32_t u32Padding1;
492	#endif
493	} IEMTLBENTRY;
494	AssertCompileSize(IEMTLBENTRY, 32);
495	/** Pointer to an IEM TLB entry. */
496	typedef IEMTLBENTRY *PIEMTLBENTRY;
497	/** Pointer to a const IEM TLB entry. */
498	typedef IEMTLBENTRY const *PCIEMTLBENTRY;
499
500	/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
501	* @{ */
502	#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /*< Page tables: Not executable. /
503	#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /*< Page tables: Not writable. /
504	#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /*< Page tables: Not user accessible (supervisor only). /
505	#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /*< Phys page: Not writable (access handler, ROM, whatever). /
506	#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /*< Phys page: Not readable (MMIO / access handler, ROM) /
507	#define IEMTLBE_F_PT_NO_ACCESSED RT_BIT_64(5) /*< Phys tables: Not accessed (need to be marked accessed). /
508	#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /*< Page tables: Not dirty (needs to be made dirty on write). /
509	#define IEMTLBE_F_PT_LARGE_PAGE RT_BIT_64(7) /*< Page tables: Large 2 or 4 MiB page (for flushing). /
510	#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(8) /*< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. /
511	#define IEMTLBE_F_PG_UNASSIGNED RT_BIT_64(9) /*< Phys page: Unassigned memory (not RAM, ROM, MMIO2 or MMIO). /
512	#define IEMTLBE_F_PG_CODE_PAGE RT_BIT_64(10) /*< Phys page: Code page. /
513	#define IEMTLBE_F_PHYS_REV UINT64_C(0xfffffffffffff800) /*< Physical revision mask. @sa IEMTLB_PHYS_REV_INCR /
514	/** @} */
515	AssertCompile(PGMIEMGCPHYS2PTR_F_NO_WRITE == IEMTLBE_F_PG_NO_WRITE);
516	AssertCompile(PGMIEMGCPHYS2PTR_F_NO_READ == IEMTLBE_F_PG_NO_READ);
517	AssertCompile(PGMIEMGCPHYS2PTR_F_NO_MAPPINGR3 == IEMTLBE_F_NO_MAPPINGR3);
518	AssertCompile(PGMIEMGCPHYS2PTR_F_UNASSIGNED == IEMTLBE_F_PG_UNASSIGNED);
519	AssertCompile(PGMIEMGCPHYS2PTR_F_CODE_PAGE == IEMTLBE_F_PG_CODE_PAGE);
520	AssertCompile(PGM_WALKINFO_BIG_PAGE == IEMTLBE_F_PT_LARGE_PAGE);
521	/** The bits set by PGMPhysIemGCPhys2PtrNoLock. */
522	#define IEMTLBE_GCPHYS2PTR_MASK ( PGMIEMGCPHYS2PTR_F_NO_WRITE \
523	\| PGMIEMGCPHYS2PTR_F_NO_READ \
524	\| PGMIEMGCPHYS2PTR_F_NO_MAPPINGR3 \
525	\| PGMIEMGCPHYS2PTR_F_UNASSIGNED \
526	\| PGMIEMGCPHYS2PTR_F_CODE_PAGE \
527	\| IEMTLBE_F_PHYS_REV )
528
529	/** The TLB size (power of two).
530	* We initially chose 256 because that way we can obtain the result directly
531	* from a 8-bit register without an additional AND instruction.
532	* See also @bugref{10687}. */
533	#if defined(RT_ARCH_AMD64)
534	# define IEMTLB_ENTRY_COUNT 256
535	# define IEMTLB_ENTRY_COUNT_AS_POWER_OF_TWO 8
536	#else
537	# define IEMTLB_ENTRY_COUNT 8192
538	# define IEMTLB_ENTRY_COUNT_AS_POWER_OF_TWO 13
539	#endif
540	AssertCompile(RT_BIT_32(IEMTLB_ENTRY_COUNT_AS_POWER_OF_TWO) == IEMTLB_ENTRY_COUNT);
541
542	/**
543	* An IEM TLB.
544	*
545	* We've got two of these, one for data and one for instructions.
546	*/
547	typedef struct IEMTLB
548	{
549	/** The non-global TLB revision.
550	* This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
551	* by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
552	* the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
553	* (The revision zero indicates an invalid TLB entry.)
554	*
555	* The initial value is choosen to cause an early wraparound. */
556	uint64_t uTlbRevision;
557	/** The TLB physical address revision - shadow of PGM variable.
558	*
559	* This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
560	* incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
561	* a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
562	* as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
563	*
564	* The initial value is choosen to cause an early wraparound.
565	*
566	* @note This is placed between the two TLB revisions because we
567	* load it in pair with one or the other on arm64. */
568	uint64_t volatile uTlbPhysRev;
569	/** The global TLB revision.
570	* Same as uTlbRevision, but only increased for global flushes. */
571	uint64_t uTlbRevisionGlobal;
572
573	/* Statistics: */
574
575	/** TLB hits in IEMAll.cpp code (IEM_WITH_TLB_STATISTICS only; both).
576	* @note For the data TLB this is only used in iemMemMap and and for direct (i.e.
577	* not via safe read/write path) calls to iemMemMapJmp. */
578	uint64_t cTlbCoreHits;
579	/** Safe read/write TLB hits in iemMemMapJmp (IEM_WITH_TLB_STATISTICS
580	* only; data tlb only). */
581	uint64_t cTlbSafeHits;
582	/** TLB hits in IEMAllMemRWTmplInline.cpp.h (data + IEM_WITH_TLB_STATISTICS only). */
583	uint64_t cTlbInlineCodeHits;
584
585	/** TLB misses in IEMAll.cpp code (both).
586	* @note For the data TLB this is only used in iemMemMap and for direct (i.e.
587	* not via safe read/write path) calls to iemMemMapJmp. So,
588	* for the data TLB this more like 'other misses', while for the code
589	* TLB is all misses. */
590	uint64_t cTlbCoreMisses;
591	/** Subset of cTlbCoreMisses that results in PTE.G=1 loads (odd entries). */
592	uint64_t cTlbCoreGlobalLoads;
593	/** Safe read/write TLB misses in iemMemMapJmp (so data only). */
594	uint64_t cTlbSafeMisses;
595	/** Subset of cTlbSafeMisses that results in PTE.G=1 loads (odd entries). */
596	uint64_t cTlbSafeGlobalLoads;
597	/** Safe read path taken (data only). */
598	uint64_t cTlbSafeReadPath;
599	/** Safe write path taken (data only). */
600	uint64_t cTlbSafeWritePath;
601
602	/** @name Details for native code TLB misses.
603	* @note These counts are included in the above counters (cTlbSafeReadPath,
604	* cTlbSafeWritePath, cTlbInlineCodeHits).
605	* @{ */
606	/** TLB misses in native code due to tag mismatch. */
607	STAMCOUNTER cTlbNativeMissTag;
608	/** TLB misses in native code due to flags or physical revision mismatch. */
609	STAMCOUNTER cTlbNativeMissFlagsAndPhysRev;
610	/** TLB misses in native code due to misaligned access. */
611	STAMCOUNTER cTlbNativeMissAlignment;
612	/** TLB misses in native code due to cross page access. */
613	uint32_t cTlbNativeMissCrossPage;
614	/** TLB misses in native code due to non-canonical address. */
615	uint32_t cTlbNativeMissNonCanonical;
616	/** @} */
617
618	/** Slow read path (code only). */
619	uint32_t cTlbSlowCodeReadPath;
620
621	/** Regular TLB flush count. */
622	uint32_t cTlsFlushes;
623	/** Global TLB flush count. */
624	uint32_t cTlsGlobalFlushes;
625	/** Revision rollovers. */
626	uint32_t cTlbRevisionRollovers;
627	/** Physical revision flushes. */
628	uint32_t cTlbPhysRevFlushes;
629	/** Physical revision rollovers. */
630	uint32_t cTlbPhysRevRollovers;
631
632	uint32_t au32Padding[10];
633
634	/** The TLB entries.
635	* Even entries are for PTE.G=0 and uses uTlbRevision.
636	* Odd entries are for PTE.G=1 and uses uTlbRevisionGlobal. */
637	IEMTLBENTRY aEntries[IEMTLB_ENTRY_COUNT * 2];
638	} IEMTLB;
639	AssertCompileSizeAlignment(IEMTLB, 64);
640	/** IEMTLB::uTlbRevision increment. */
641	#define IEMTLB_REVISION_INCR RT_BIT_64(36)
642	/** IEMTLB::uTlbRevision mask. */
643	#define IEMTLB_REVISION_MASK (~(RT_BIT_64(36) - 1))
644	/** IEMTLB::uTlbPhysRev increment.
645	* @sa IEMTLBE_F_PHYS_REV */
646	#define IEMTLB_PHYS_REV_INCR RT_BIT_64(11)
647	AssertCompile(IEMTLBE_F_PHYS_REV == ~(IEMTLB_PHYS_REV_INCR - 1U));
648
649	/**
650	* Calculates the TLB tag for a virtual address but without TLB revision.
651	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
652	* @param a_GCPtr The virtual address. Must be RTGCPTR or same size or
653	* the clearing of the top 16 bits won't work (if 32-bit
654	* we'll end up with mostly zeros).
655	*/
656	#define IEMTLB_CALC_TAG_NO_REV(a_GCPtr) ( (((a_GCPtr) << 16) >> (GUEST_PAGE_SHIFT + 16)) )
657	/**
658	* Converts a TLB tag value into a even TLB index.
659	* @returns Index into IEMTLB::aEntries.
660	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
661	*/
662	#if IEMTLB_ENTRY_COUNT == 256
663	# define IEMTLB_TAG_TO_EVEN_INDEX(a_uTag) ( (uint8_t)(a_uTag) * 2U )
664	#else
665	# define IEMTLB_TAG_TO_EVEN_INDEX(a_uTag) ( ((a_uTag) & (IEMTLB_ENTRY_COUNT - 1U)) * 2U )
666	AssertCompile(RT_IS_POWER_OF_TWO(IEMTLB_ENTRY_COUNT));
667	#endif
668	/**
669	* Converts a TLB tag value into an even TLB index.
670	* @returns Pointer into IEMTLB::aEntries corresponding to .
671	* @param a_pTlb The TLB.
672	* @param a_uTag Value returned by IEMTLB_CALC_TAG or
673	* IEMTLB_CALC_TAG_NO_REV.
674	*/
675	#define IEMTLB_TAG_TO_EVEN_ENTRY(a_pTlb, a_uTag) ( &(a_pTlb)->aEntries[IEMTLB_TAG_TO_EVEN_INDEX(a_uTag)] )
676
677
678	/** @name IEM_MC_F_XXX - MC block flags/clues.
679	* @todo Merge with IEM_CIMPL_F_XXX
680	* @{ */
681	#define IEM_MC_F_ONLY_8086 RT_BIT_32(0)
682	#define IEM_MC_F_MIN_186 RT_BIT_32(1)
683	#define IEM_MC_F_MIN_286 RT_BIT_32(2)
684	#define IEM_MC_F_NOT_286_OR_OLDER IEM_MC_F_MIN_386
685	#define IEM_MC_F_MIN_386 RT_BIT_32(3)
686	#define IEM_MC_F_MIN_486 RT_BIT_32(4)
687	#define IEM_MC_F_MIN_PENTIUM RT_BIT_32(5)
688	#define IEM_MC_F_MIN_PENTIUM_II IEM_MC_F_MIN_PENTIUM
689	#define IEM_MC_F_MIN_CORE IEM_MC_F_MIN_PENTIUM
690	#define IEM_MC_F_64BIT RT_BIT_32(6)
691	#define IEM_MC_F_NOT_64BIT RT_BIT_32(7)
692	/** This is set by IEMAllN8vePython.py to indicate a variation without the
693	* flags-clearing-and-checking, when there is also a variation with that.
694	* @note Do not use this manully, it's only for python and for testing in
695	* the native recompiler! */
696	#define IEM_MC_F_WITHOUT_FLAGS RT_BIT_32(8)
697	/** @} */
698
699	/** @name IEM_CIMPL_F_XXX - State change clues for CIMPL calls.
700	*
701	* These clues are mainly for the recompiler, so that it can emit correct code.
702	*
703	* They are processed by the python script and which also automatically
704	* calculates flags for MC blocks based on the statements, extending the use of
705	* these flags to describe MC block behavior to the recompiler core. The python
706	* script pass the flags to the IEM_MC2_END_EMIT_CALLS macro, but mainly for
707	* error checking purposes. The script emits the necessary fEndTb = true and
708	* similar statements as this reduces compile time a tiny bit.
709	*
710	* @{ */
711	/** Flag set if direct branch, clear if absolute or indirect. */
712	#define IEM_CIMPL_F_BRANCH_DIRECT RT_BIT_32(0)
713	/** Flag set if indirect branch, clear if direct or relative.
714	* This is also used for all system control transfers (SYSCALL, SYSRET, INT, ++)
715	* as well as for return instructions (RET, IRET, RETF). */
716	#define IEM_CIMPL_F_BRANCH_INDIRECT RT_BIT_32(1)
717	/** Flag set if relative branch, clear if absolute or indirect. */
718	#define IEM_CIMPL_F_BRANCH_RELATIVE RT_BIT_32(2)
719	/** Flag set if conditional branch, clear if unconditional. */
720	#define IEM_CIMPL_F_BRANCH_CONDITIONAL RT_BIT_32(3)
721	/** Flag set if it's a far branch (changes CS). */
722	#define IEM_CIMPL_F_BRANCH_FAR RT_BIT_32(4)
723	/** Convenience: Testing any kind of branch. */
724	#define IEM_CIMPL_F_BRANCH_ANY (IEM_CIMPL_F_BRANCH_DIRECT \| IEM_CIMPL_F_BRANCH_INDIRECT \| IEM_CIMPL_F_BRANCH_RELATIVE)
725
726	/** Execution flags may change (IEMCPU::fExec). */
727	#define IEM_CIMPL_F_MODE RT_BIT_32(5)
728	/** May change significant portions of RFLAGS. */
729	#define IEM_CIMPL_F_RFLAGS RT_BIT_32(6)
730	/** May change the status bits (X86_EFL_STATUS_BITS) in RFLAGS. */
731	#define IEM_CIMPL_F_STATUS_FLAGS RT_BIT_32(7)
732	/** May trigger interrupt shadowing. */
733	#define IEM_CIMPL_F_INHIBIT_SHADOW RT_BIT_32(8)
734	/** May enable interrupts, so recheck IRQ immediately afterwards executing
735	* the instruction. */
736	#define IEM_CIMPL_F_CHECK_IRQ_AFTER RT_BIT_32(9)
737	/** May disable interrupts, so recheck IRQ immediately before executing the
738	* instruction. */
739	#define IEM_CIMPL_F_CHECK_IRQ_BEFORE RT_BIT_32(10)
740	/** Convenience: Check for IRQ both before and after an instruction. */
741	#define IEM_CIMPL_F_CHECK_IRQ_BEFORE_AND_AFTER (IEM_CIMPL_F_CHECK_IRQ_BEFORE \| IEM_CIMPL_F_CHECK_IRQ_AFTER)
742	/** May trigger a VM exit (treated like IEM_CIMPL_F_MODE atm). */
743	#define IEM_CIMPL_F_VMEXIT RT_BIT_32(11)
744	/** May modify FPU state.
745	* @todo Not sure if this is useful yet. */
746	#define IEM_CIMPL_F_FPU RT_BIT_32(12)
747	/** REP prefixed instruction which may yield before updating PC.
748	* @todo Not sure if this is useful, REP functions now return non-zero
749	* status if they don't update the PC. */
750	#define IEM_CIMPL_F_REP RT_BIT_32(13)
751	/** I/O instruction.
752	* @todo Not sure if this is useful yet. */
753	#define IEM_CIMPL_F_IO RT_BIT_32(14)
754	/** Force end of TB after the instruction. */
755	#define IEM_CIMPL_F_END_TB RT_BIT_32(15)
756	/** Flag set if a branch may also modify the stack (push/pop return address). */
757	#define IEM_CIMPL_F_BRANCH_STACK RT_BIT_32(16)
758	/** Flag set if a branch may also modify the stack (push/pop return address)
759	* and switch it (load/restore SS:RSP). */
760	#define IEM_CIMPL_F_BRANCH_STACK_FAR RT_BIT_32(17)
761	/** Convenience: Raise exception (technically unnecessary, since it shouldn't return VINF_SUCCESS). */
762	#define IEM_CIMPL_F_XCPT \
763	(IEM_CIMPL_F_BRANCH_INDIRECT \| IEM_CIMPL_F_BRANCH_FAR \| IEM_CIMPL_F_BRANCH_STACK_FAR \
764	\| IEM_CIMPL_F_MODE \| IEM_CIMPL_F_RFLAGS \| IEM_CIMPL_F_VMEXIT)
765
766	/** The block calls a C-implementation instruction function with two implicit arguments.
767	* Mutually exclusive with IEM_CIMPL_F_CALLS_AIMPL and
768	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
769	* @note The python scripts will add this if missing. */
770	#define IEM_CIMPL_F_CALLS_CIMPL RT_BIT_32(18)
771	/** The block calls an ASM-implementation instruction function.
772	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL and
773	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
774	* @note The python scripts will add this if missing. */
775	#define IEM_CIMPL_F_CALLS_AIMPL RT_BIT_32(19)
776	/** The block calls an ASM-implementation instruction function with an implicit
777	* X86FXSTATE pointer argument.
778	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL, IEM_CIMPL_F_CALLS_AIMPL and
779	* IEM_CIMPL_F_CALLS_AIMPL_WITH_XSTATE.
780	* @note The python scripts will add this if missing. */
781	#define IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE RT_BIT_32(20)
782	/** The block calls an ASM-implementation instruction function with an implicit
783	* X86XSAVEAREA pointer argument.
784	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL, IEM_CIMPL_F_CALLS_AIMPL and
785	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
786	* @note No different from IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE, so same value.
787	* @note The python scripts will add this if missing. */
788	#define IEM_CIMPL_F_CALLS_AIMPL_WITH_XSTATE IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE
789	/** @} */
790
791
792	/** @name IEM_F_XXX - Execution mode flags (IEMCPU::fExec, IEMTB::fFlags).
793	*
794	* These flags are set when entering IEM and adjusted as code is executed, such
795	* that they will always contain the current values as instructions are
796	* finished.
797	*
798	* In recompiled execution mode, (most of) these flags are included in the
799	* translation block selection key and stored in IEMTB::fFlags alongside the
800	* IEMTB_F_XXX flags. The latter flags uses bits 31 thru 24, which are all zero
801	* in IEMCPU::fExec.
802	*
803	* @{ */
804	/** Mode: The block target mode mask. */
805	#define IEM_F_MODE_MASK UINT32_C(0x0000001f)
806	/** Mode: The IEMMODE part of the IEMTB_F_MODE_MASK value. */
807	#define IEM_F_MODE_CPUMODE_MASK UINT32_C(0x00000003)
808	/** X86 Mode: Bit used to indicating pre-386 CPU in 16-bit mode (for eliminating
809	* conditional in EIP/IP updating), and flat wide open CS, SS, DS, and ES in
810	* 32-bit mode (for simplifying most memory accesses). */
811	#define IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK UINT32_C(0x00000004)
812	/** X86 Mode: Bit indicating protected mode, real mode (or SMM) when not set. */
813	#define IEM_F_MODE_X86_PROT_MASK UINT32_C(0x00000008)
814	/** X86 Mode: Bit used to indicate virtual 8086 mode (only 16-bit). */
815	#define IEM_F_MODE_X86_V86_MASK UINT32_C(0x00000010)
816
817	/** X86 Mode: 16-bit on 386 or later. */
818	#define IEM_F_MODE_X86_16BIT UINT32_C(0x00000000)
819	/** X86 Mode: 80286, 80186 and 8086/88 targetting blocks (EIP update opt). */
820	#define IEM_F_MODE_X86_16BIT_PRE_386 UINT32_C(0x00000004)
821	/** X86 Mode: 16-bit protected mode on 386 or later. */
822	#define IEM_F_MODE_X86_16BIT_PROT UINT32_C(0x00000008)
823	/** X86 Mode: 16-bit protected mode on 386 or later. */
824	#define IEM_F_MODE_X86_16BIT_PROT_PRE_386 UINT32_C(0x0000000c)
825	/** X86 Mode: 16-bit virtual 8086 protected mode (on 386 or later). */
826	#define IEM_F_MODE_X86_16BIT_PROT_V86 UINT32_C(0x00000018)
827
828	/** X86 Mode: 32-bit on 386 or later. */
829	#define IEM_F_MODE_X86_32BIT UINT32_C(0x00000001)
830	/** X86 Mode: 32-bit mode with wide open flat CS, SS, DS and ES. */
831	#define IEM_F_MODE_X86_32BIT_FLAT UINT32_C(0x00000005)
832	/** X86 Mode: 32-bit protected mode. */
833	#define IEM_F_MODE_X86_32BIT_PROT UINT32_C(0x00000009)
834	/** X86 Mode: 32-bit protected mode with wide open flat CS, SS, DS and ES. */
835	#define IEM_F_MODE_X86_32BIT_PROT_FLAT UINT32_C(0x0000000d)
836
837	/** X86 Mode: 64-bit (includes protected, but not the flat bit). */
838	#define IEM_F_MODE_X86_64BIT UINT32_C(0x0000000a)
839
840	/** X86 Mode: Checks if @a a_fExec represent a FLAT mode. */
841	#define IEM_F_MODE_X86_IS_FLAT(a_fExec) ( ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_64BIT \
842	\|\| ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_32BIT_PROT_FLAT \
843	\|\| ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_32BIT_FLAT)
844
845	/** Bypass access handlers when set. */
846	#define IEM_F_BYPASS_HANDLERS UINT32_C(0x00010000)
847	/** Have pending hardware instruction breakpoints. */
848	#define IEM_F_PENDING_BRK_INSTR UINT32_C(0x00020000)
849	/** Have pending hardware data breakpoints. */
850	#define IEM_F_PENDING_BRK_DATA UINT32_C(0x00040000)
851
852	/** X86: Have pending hardware I/O breakpoints. */
853	#define IEM_F_PENDING_BRK_X86_IO UINT32_C(0x00000400)
854	/** X86: Disregard the lock prefix (implied or not) when set. */
855	#define IEM_F_X86_DISREGARD_LOCK UINT32_C(0x00000800)
856
857	/** Pending breakpoint mask (what iemCalcExecDbgFlags works out). */
858	#define IEM_F_PENDING_BRK_MASK (IEM_F_PENDING_BRK_INSTR \| IEM_F_PENDING_BRK_DATA \| IEM_F_PENDING_BRK_X86_IO)
859
860	/** Caller configurable options. */
861	#define IEM_F_USER_OPTS (IEM_F_BYPASS_HANDLERS \| IEM_F_X86_DISREGARD_LOCK)
862
863	/** X86: The current protection level (CPL) shift factor. */
864	#define IEM_F_X86_CPL_SHIFT 8
865	/** X86: The current protection level (CPL) mask. */
866	#define IEM_F_X86_CPL_MASK UINT32_C(0x00000300)
867	/** X86: The current protection level (CPL) shifted mask. */
868	#define IEM_F_X86_CPL_SMASK UINT32_C(0x00000003)
869
870	/** X86: Alignment checks enabled (CR0.AM=1 & EFLAGS.AC=1). */
871	#define IEM_F_X86_AC UINT32_C(0x00080000)
872
873	/** X86 execution context.
874	* The IEM_F_X86_CTX_XXX values are individual flags that can be combined (with
875	* the exception of IEM_F_X86_CTX_NORMAL). This allows running VMs from SMM
876	* mode. */
877	#define IEM_F_X86_CTX_MASK UINT32_C(0x0000f000)
878	/** X86 context: Plain regular execution context. */
879	#define IEM_F_X86_CTX_NORMAL UINT32_C(0x00000000)
880	/** X86 context: VT-x enabled. */
881	#define IEM_F_X86_CTX_VMX UINT32_C(0x00001000)
882	/** X86 context: AMD-V enabled. */
883	#define IEM_F_X86_CTX_SVM UINT32_C(0x00002000)
884	/** X86 context: In AMD-V or VT-x guest mode. */
885	#define IEM_F_X86_CTX_IN_GUEST UINT32_C(0x00004000)
886	/** X86 context: System management mode (SMM). */
887	#define IEM_F_X86_CTX_SMM UINT32_C(0x00008000)
888
889	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
890	* iemRegFinishClearingRF() most for most situations (CPUMCTX_DBG_HIT_DRX_MASK
891	* and CPUMCTX_DBG_DBGF_MASK are covered by the IEM_F_PENDING_BRK_XXX bits
892	* alread). */
893
894	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
895	* iemRegFinishClearingRF() most for most situations
896	* (CPUMCTX_DBG_HIT_DRX_MASK and CPUMCTX_DBG_DBGF_MASK are covered by
897	* the IEM_F_PENDING_BRK_XXX bits alread). */
898
899	/** @} */
900
901
902	/** @name IEMTB_F_XXX - Translation block flags (IEMTB::fFlags).
903	*
904	* Extends the IEM_F_XXX flags (subject to IEMTB_F_IEM_F_MASK) to make up the
905	* translation block flags. The combined flag mask (subject to
906	* IEMTB_F_KEY_MASK) is used as part of the lookup key for translation blocks.
907	*
908	* @{ */
909	/** Mask of IEM_F_XXX flags included in IEMTB_F_XXX. */
910	#define IEMTB_F_IEM_F_MASK UINT32_C(0x00ffffff)
911
912	/** Type: The block type mask. */
913	#define IEMTB_F_TYPE_MASK UINT32_C(0x03000000)
914	/** Type: Purly threaded recompiler (via tables). */
915	#define IEMTB_F_TYPE_THREADED UINT32_C(0x01000000)
916	/** Type: Native recompilation. */
917	#define IEMTB_F_TYPE_NATIVE UINT32_C(0x02000000)
918
919	/** Set when we're starting the block in an "interrupt shadow".
920	* We don't need to distingish between the two types of this mask, thus the one.
921	* @see CPUMCTX_INHIBIT_SHADOW, CPUMIsInInterruptShadow() */
922	#define IEMTB_F_INHIBIT_SHADOW UINT32_C(0x04000000)
923	/** Set when we're currently inhibiting NMIs
924	* @see CPUMCTX_INHIBIT_NMI, CPUMAreInterruptsInhibitedByNmi() */
925	#define IEMTB_F_INHIBIT_NMI UINT32_C(0x08000000)
926
927	/** Checks that EIP/IP is wihin CS.LIM before each instruction. Used when
928	* we're close the limit before starting a TB, as determined by
929	* iemGetTbFlagsForCurrentPc(). */
930	#define IEMTB_F_CS_LIM_CHECKS UINT32_C(0x10000000)
931
932	/** Mask of the IEMTB_F_XXX flags that are part of the TB lookup key.
933	*
934	* @note We skip all of IEM_F_X86_CTX_MASK, with the exception of SMM (which we
935	* don't implement), because we don't currently generate any context
936	* specific code - that's all handled in CIMPL functions.
937	*
938	* For the threaded recompiler we don't generate any CPL specific code
939	* either, but the native recompiler does for memory access (saves getting
940	* the CPL from fExec and turning it into IEMTLBE_F_PT_NO_USER).
941	* Since most OSes will not share code between rings, this shouldn't
942	* have any real effect on TB/memory/recompiling load.
943	*/
944	#define IEMTB_F_KEY_MASK ((UINT32_MAX & ~(IEM_F_X86_CTX_MASK \| IEMTB_F_TYPE_MASK)) \| IEM_F_X86_CTX_SMM)
945	/** @} */
946
947	AssertCompile( (IEM_F_MODE_X86_16BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
948	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
949	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_PROT_MASK));
950	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_V86_MASK));
951	AssertCompile( (IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
952	AssertCompile( IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
953	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_PROT_MASK));
954	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
955	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
956	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
957	AssertCompile( IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
958	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_V86_MASK));
959	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
960	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
961	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_PROT_MASK);
962	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
963	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_PROT_MASK);
964	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
965	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_V86_MASK);
966
967	AssertCompile( (IEM_F_MODE_X86_32BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
968	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
969	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_PROT_MASK));
970	AssertCompile( (IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
971	AssertCompile( IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
972	AssertCompile(!(IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_PROT_MASK));
973	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
974	AssertCompile(!(IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
975	AssertCompile( IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
976	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
977	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
978	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_PROT_MASK);
979
980	AssertCompile( (IEM_F_MODE_X86_64BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_64BIT);
981	AssertCompile( IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_PROT_MASK);
982	AssertCompile(!(IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
983
984	/** Native instruction type for use with the native code generator.
985	* This is a byte (uint8_t) for x86 and amd64 and uint32_t for the other(s). */
986	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
987	typedef uint8_t IEMNATIVEINSTR;
988	#else
989	typedef uint32_t IEMNATIVEINSTR;
990	#endif
991	/** Pointer to a native instruction unit. */
992	typedef IEMNATIVEINSTR *PIEMNATIVEINSTR;
993	/** Pointer to a const native instruction unit. */
994	typedef IEMNATIVEINSTR const *PCIEMNATIVEINSTR;
995
996	/**
997	* A call for the threaded call table.
998	*/
999	typedef struct IEMTHRDEDCALLENTRY
1000	{
1001	/** The function to call (IEMTHREADEDFUNCS). */
1002	uint16_t enmFunction;
1003
1004	/** Instruction number in the TB (for statistics). */
1005	uint8_t idxInstr;
1006	/** The opcode length. */
1007	uint8_t cbOpcode;
1008	/** Offset into IEMTB::pabOpcodes. */
1009	uint16_t offOpcode;
1010
1011	/** TB lookup table index (7 bits) and large size (1 bits).
1012	*
1013	* The default size is 1 entry, but for indirect calls and returns we set the
1014	* top bit and allocate 4 (IEM_TB_LOOKUP_TAB_LARGE_SIZE) entries. The large
1015	* tables uses RIP for selecting the entry to use, as it is assumed a hash table
1016	* lookup isn't that slow compared to sequentially trying out 4 TBs.
1017	*
1018	* By default lookup table entry 0 for a TB is reserved as a fallback for
1019	* calltable entries w/o explicit entreis, so this member will be non-zero if
1020	* there is a lookup entry associated with this call.
1021	*
1022	* @sa IEM_TB_LOOKUP_TAB_GET_SIZE, IEM_TB_LOOKUP_TAB_GET_IDX
1023	*/
1024	uint8_t uTbLookup;
1025
1026	/** Unused atm. */
1027	uint8_t uUnused0;
1028
1029	/** Generic parameters. */
1030	uint64_t auParams[3];
1031	} IEMTHRDEDCALLENTRY;
1032	AssertCompileSize(IEMTHRDEDCALLENTRY, sizeof(uint64_t) * 4);
1033	/** Pointer to a threaded call entry. */
1034	typedef struct IEMTHRDEDCALLENTRY *PIEMTHRDEDCALLENTRY;
1035	/** Pointer to a const threaded call entry. */
1036	typedef IEMTHRDEDCALLENTRY const *PCIEMTHRDEDCALLENTRY;
1037
1038	/** The number of TB lookup table entries for a large allocation
1039	* (IEMTHRDEDCALLENTRY::uTbLookup bit 7 set). */
1040	#define IEM_TB_LOOKUP_TAB_LARGE_SIZE 4
1041	/** Get the lookup table size from IEMTHRDEDCALLENTRY::uTbLookup. */
1042	#define IEM_TB_LOOKUP_TAB_GET_SIZE(a_uTbLookup) (!((a_uTbLookup) & 0x80) ? 1 : IEM_TB_LOOKUP_TAB_LARGE_SIZE)
1043	/** Get the first lookup table index from IEMTHRDEDCALLENTRY::uTbLookup. */
1044	#define IEM_TB_LOOKUP_TAB_GET_IDX(a_uTbLookup) ((a_uTbLookup) & 0x7f)
1045	/** Get the lookup table index from IEMTHRDEDCALLENTRY::uTbLookup and RIP. */
1046	#define IEM_TB_LOOKUP_TAB_GET_IDX_WITH_RIP(a_uTbLookup, a_Rip) \
1047	(!((a_uTbLookup) & 0x80) ? (a_uTbLookup) & 0x7f : ((a_uTbLookup) & 0x7f) + ((a_Rip) & (IEM_TB_LOOKUP_TAB_LARGE_SIZE - 1)) )
1048
1049	/** Make a IEMTHRDEDCALLENTRY::uTbLookup value. */
1050	#define IEM_TB_LOOKUP_TAB_MAKE(a_idxTable, a_fLarge) ((a_idxTable) \| ((a_fLarge) ? 0x80 : 0))
1051
1052	/**
1053	* Native IEM TB 'function' typedef.
1054	*
1055	* This will throw/longjmp on occation.
1056	*
1057	* @note AMD64 doesn't have that many non-volatile registers and does sport
1058	* 32-bit address displacments, so we don't need pCtx.
1059	*
1060	* On ARM64 pCtx allows us to directly address the whole register
1061	* context without requiring a separate indexing register holding the
1062	* offset. This saves an instruction loading the offset for each guest
1063	* CPU context access, at the cost of a non-volatile register.
1064	* Fortunately, ARM64 has quite a lot more registers.
1065	*/
1066	typedef
1067	#ifdef RT_ARCH_AMD64
1068	int FNIEMTBNATIVE(PVMCPUCC pVCpu)
1069	#else
1070	int FNIEMTBNATIVE(PVMCPUCC pVCpu, PCPUMCTX pCtx)
1071	#endif
1072	#if RT_CPLUSPLUS_PREREQ(201700)
1073	IEM_NOEXCEPT_MAY_LONGJMP
1074	#endif
1075	;
1076	/** Pointer to a native IEM TB entry point function.
1077	* This will throw/longjmp on occation. */
1078	typedef FNIEMTBNATIVE *PFNIEMTBNATIVE;
1079
1080
1081	/**
1082	* Translation block debug info entry type.
1083	*/
1084	typedef enum IEMTBDBGENTRYTYPE
1085	{
1086	kIemTbDbgEntryType_Invalid = 0,
1087	/** The entry is for marking a native code position.
1088	* Entries following this all apply to this position. */
1089	kIemTbDbgEntryType_NativeOffset,
1090	/** The entry is for a new guest instruction. */
1091	kIemTbDbgEntryType_GuestInstruction,
1092	/** Marks the start of a threaded call. */
1093	kIemTbDbgEntryType_ThreadedCall,
1094	/** Marks the location of a label. */
1095	kIemTbDbgEntryType_Label,
1096	/** Info about a host register shadowing a guest register. */
1097	kIemTbDbgEntryType_GuestRegShadowing,
1098	#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
1099	/** Info about a host SIMD register shadowing a guest SIMD register. */
1100	kIemTbDbgEntryType_GuestSimdRegShadowing,
1101	#endif
1102	#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING
1103	/** Info about a delayed RIP update. */
1104	kIemTbDbgEntryType_DelayedPcUpdate,
1105	#endif
1106	#if defined(IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK) \|\| defined(IEMNATIVE_WITH_SIMD_REG_ALLOCATOR)
1107	/** Info about a shadowed guest register becoming dirty. */
1108	kIemTbDbgEntryType_GuestRegDirty,
1109	/** Info about register writeback/flush oepration. */
1110	kIemTbDbgEntryType_GuestRegWriteback,
1111	#endif
1112	kIemTbDbgEntryType_End
1113	} IEMTBDBGENTRYTYPE;
1114
1115	/**
1116	* Translation block debug info entry.
1117	*/
1118	typedef union IEMTBDBGENTRY
1119	{
1120	/** Plain 32-bit view. */
1121	uint32_t u;
1122
1123	/** Generic view for getting at the type field. */
1124	struct
1125	{
1126	/** IEMTBDBGENTRYTYPE */
1127	uint32_t uType : 4;
1128	uint32_t uTypeSpecific : 28;
1129	} Gen;
1130
1131	struct
1132	{
1133	/** kIemTbDbgEntryType_ThreadedCall1. */
1134	uint32_t uType : 4;
1135	/** Native code offset. */
1136	uint32_t offNative : 28;
1137	} NativeOffset;
1138
1139	struct
1140	{
1141	/** kIemTbDbgEntryType_GuestInstruction. */
1142	uint32_t uType : 4;
1143	uint32_t uUnused : 4;
1144	/** The IEM_F_XXX flags. */
1145	uint32_t fExec : 24;
1146	} GuestInstruction;
1147
1148	struct
1149	{
1150	/* kIemTbDbgEntryType_ThreadedCall. */
1151	uint32_t uType : 4;
1152	/** Set if the call was recompiled to native code, clear if just calling
1153	* threaded function. */
1154	uint32_t fRecompiled : 1;
1155	uint32_t uUnused : 11;
1156	/** The threaded call number (IEMTHREADEDFUNCS). */
1157	uint32_t enmCall : 16;
1158	} ThreadedCall;
1159
1160	struct
1161	{
1162	/* kIemTbDbgEntryType_Label. */
1163	uint32_t uType : 4;
1164	uint32_t uUnused : 4;
1165	/** The label type (IEMNATIVELABELTYPE). */
1166	uint32_t enmLabel : 8;
1167	/** The label data. */
1168	uint32_t uData : 16;
1169	} Label;
1170
1171	struct
1172	{
1173	/* kIemTbDbgEntryType_GuestRegShadowing. */
1174	uint32_t uType : 4;
1175	uint32_t uUnused : 4;
1176	/** The guest register being shadowed (IEMNATIVEGSTREG). */
1177	uint32_t idxGstReg : 8;
1178	/** The host new register number, UINT8_MAX if dropped. */
1179	uint32_t idxHstReg : 8;
1180	/** The previous host register number, UINT8_MAX if new. */
1181	uint32_t idxHstRegPrev : 8;
1182	} GuestRegShadowing;
1183
1184	#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
1185	struct
1186	{
1187	/* kIemTbDbgEntryType_GuestSimdRegShadowing. */
1188	uint32_t uType : 4;
1189	uint32_t uUnused : 4;
1190	/** The guest register being shadowed (IEMNATIVEGSTSIMDREG). */
1191	uint32_t idxGstSimdReg : 8;
1192	/** The host new register number, UINT8_MAX if dropped. */
1193	uint32_t idxHstSimdReg : 8;
1194	/** The previous host register number, UINT8_MAX if new. */
1195	uint32_t idxHstSimdRegPrev : 8;
1196	} GuestSimdRegShadowing;
1197	#endif
1198
1199	#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING
1200	struct
1201	{
1202	/* kIemTbDbgEntryType_DelayedPcUpdate. */
1203	uint32_t uType : 4;
1204	/* The instruction offset added to the program counter. */
1205	uint32_t offPc : 14;
1206	/** Number of instructions skipped. */
1207	uint32_t cInstrSkipped : 14;
1208	} DelayedPcUpdate;
1209	#endif
1210
1211	#if defined(IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK) \|\| defined(IEMNATIVE_WITH_SIMD_REG_ALLOCATOR)
1212	struct
1213	{
1214	/* kIemTbDbgEntryType_GuestRegDirty. */
1215	uint32_t uType : 4;
1216	uint32_t uUnused : 11;
1217	/** Flag whether this is about a SIMD (true) or general (false) register. */
1218	uint32_t fSimdReg : 1;
1219	/** The guest register index being marked as dirty. */
1220	uint32_t idxGstReg : 8;
1221	/** The host register number this register is shadowed in .*/
1222	uint32_t idxHstReg : 8;
1223	} GuestRegDirty;
1224
1225	struct
1226	{
1227	/* kIemTbDbgEntryType_GuestRegWriteback. */
1228	uint32_t uType : 4;
1229	/** Flag whether this is about a SIMD (true) or general (false) register flush. */
1230	uint32_t fSimdReg : 1;
1231	/** The mask shift. */
1232	uint32_t cShift : 2;
1233	/** The guest register mask being written back. */
1234	uint32_t fGstReg : 25;
1235	} GuestRegWriteback;
1236	#endif
1237
1238	} IEMTBDBGENTRY;
1239	AssertCompileSize(IEMTBDBGENTRY, sizeof(uint32_t));
1240	/** Pointer to a debug info entry. */
1241	typedef IEMTBDBGENTRY *PIEMTBDBGENTRY;
1242	/** Pointer to a const debug info entry. */
1243	typedef IEMTBDBGENTRY const *PCIEMTBDBGENTRY;
1244
1245	/**
1246	* Translation block debug info.
1247	*/
1248	typedef struct IEMTBDBG
1249	{
1250	/** Number of entries in aEntries. */
1251	uint32_t cEntries;
1252	/** The offset of the last kIemTbDbgEntryType_NativeOffset record. */
1253	uint32_t offNativeLast;
1254	/** Debug info entries. */
1255	RT_FLEXIBLE_ARRAY_EXTENSION
1256	IEMTBDBGENTRY aEntries[RT_FLEXIBLE_ARRAY];
1257	} IEMTBDBG;
1258	/** Pointer to TB debug info. */
1259	typedef IEMTBDBG *PIEMTBDBG;
1260	/** Pointer to const TB debug info. */
1261	typedef IEMTBDBG const *PCIEMTBDBG;
1262
1263
1264	/**
1265	* Translation block.
1266	*
1267	* The current plan is to just keep TBs and associated lookup hash table private
1268	* to each VCpu as that simplifies TB removal greatly (no races) and generally
1269	* avoids using expensive atomic primitives for updating lists and stuff.
1270	*/
1271	#pragma pack(2) /* to prevent the Thrd structure from being padded unnecessarily */
1272	typedef struct IEMTB
1273	{
1274	/** Next block with the same hash table entry. */
1275	struct IEMTB *pNext;
1276	/** Usage counter. */
1277	uint32_t cUsed;
1278	/** The IEMCPU::msRecompilerPollNow last time it was used. */
1279	uint32_t msLastUsed;
1280
1281	/** @name What uniquely identifies the block.
1282	* @{ */
1283	RTGCPHYS GCPhysPc;
1284	/** IEMTB_F_XXX (i.e. IEM_F_XXX ++). */
1285	uint32_t fFlags;
1286	union
1287	{
1288	struct
1289	{
1290	/*< Relevant CS X86DESCATTR_XXX bits. /
1291	uint16_t fAttr;
1292	} x86;
1293	};
1294	/** @} */
1295
1296	/** Number of opcode ranges. */
1297	uint8_t cRanges;
1298	/** Statistics: Number of instructions in the block. */
1299	uint8_t cInstructions;
1300
1301	/** Type specific info. */
1302	union
1303	{
1304	struct
1305	{
1306	/** The call sequence table. */
1307	PIEMTHRDEDCALLENTRY paCalls;
1308	/** Number of calls in paCalls. */
1309	uint16_t cCalls;
1310	/** Number of calls allocated. */
1311	uint16_t cAllocated;
1312	} Thrd;
1313	struct
1314	{
1315	/** The native instructions (PFNIEMTBNATIVE). */
1316	PIEMNATIVEINSTR paInstructions;
1317	/** Number of instructions pointed to by paInstructions. */
1318	uint32_t cInstructions;
1319	} Native;
1320	/** Generic view for zeroing when freeing. */
1321	struct
1322	{
1323	uintptr_t uPtr;
1324	uint32_t uData;
1325	} Gen;
1326	};
1327
1328	/** The allocation chunk this TB belongs to. */
1329	uint8_t idxAllocChunk;
1330	/** The number of entries in the lookup table.
1331	* Because we're out of space, the TB lookup table is located before the
1332	* opcodes pointed to by pabOpcodes. */
1333	uint8_t cTbLookupEntries;
1334
1335	/** Number of bytes of opcodes stored in pabOpcodes.
1336	* @todo this field isn't really needed, aRanges keeps the actual info. */
1337	uint16_t cbOpcodes;
1338	/** Pointer to the opcode bytes this block was recompiled from.
1339	* This also points to the TB lookup table, which starts cTbLookupEntries
1340	* entries before the opcodes (we don't have room atm for another point). */
1341	uint8_t *pabOpcodes;
1342
1343	/** Debug info if enabled.
1344	* This is only generated by the native recompiler. */
1345	PIEMTBDBG pDbgInfo;
1346
1347	/* --- 64 byte cache line end --- */
1348
1349	/** Opcode ranges.
1350	*
1351	* The opcode checkers and maybe TLB loading functions will use this to figure
1352	* out what to do. The parameter will specify an entry and the opcode offset to
1353	* start at and the minimum number of bytes to verify (instruction length).
1354	*
1355	* When VT-x and AMD-V looks up the opcode bytes for an exitting instruction,
1356	* they'll first translate RIP (+ cbInstr - 1) to a physical address using the
1357	* code TLB (must have a valid entry for that address) and scan the ranges to
1358	* locate the corresponding opcodes. Probably.
1359	*/
1360	struct IEMTBOPCODERANGE
1361	{
1362	/** Offset within pabOpcodes. */
1363	uint16_t offOpcodes;
1364	/** Number of bytes. */
1365	uint16_t cbOpcodes;
1366	/** The page offset. */
1367	RT_GCC_EXTENSION
1368	uint16_t offPhysPage : 12;
1369	/** Unused bits. */
1370	RT_GCC_EXTENSION
1371	uint16_t u2Unused : 2;
1372	/** Index into GCPhysPc + aGCPhysPages for the physical page address. */
1373	RT_GCC_EXTENSION
1374	uint16_t idxPhysPage : 2;
1375	} aRanges[8];
1376
1377	/** Physical pages that this TB covers.
1378	* The GCPhysPc w/o page offset is element zero, so starting here with 1. */
1379	RTGCPHYS aGCPhysPages[2];
1380	} IEMTB;
1381	#pragma pack()
1382	AssertCompileMemberAlignment(IEMTB, GCPhysPc, sizeof(RTGCPHYS));
1383	AssertCompileMemberAlignment(IEMTB, Thrd, sizeof(void *));
1384	AssertCompileMemberAlignment(IEMTB, pabOpcodes, sizeof(void *));
1385	AssertCompileMemberAlignment(IEMTB, pDbgInfo, sizeof(void *));
1386	AssertCompileMemberAlignment(IEMTB, aGCPhysPages, sizeof(RTGCPHYS));
1387	AssertCompileMemberOffset(IEMTB, aRanges, 64);
1388	AssertCompileMemberSize(IEMTB, aRanges[0], 6);
1389	#if 1
1390	AssertCompileSize(IEMTB, 128);
1391	# define IEMTB_SIZE_IS_POWER_OF_TWO /*< The IEMTB size is a power of two. /
1392	#else
1393	AssertCompileSize(IEMTB, 168);
1394	# undef IEMTB_SIZE_IS_POWER_OF_TWO
1395	#endif
1396
1397	/** Pointer to a translation block. */
1398	typedef IEMTB *PIEMTB;
1399	/** Pointer to a const translation block. */
1400	typedef IEMTB const *PCIEMTB;
1401
1402	/** Gets address of the given TB lookup table entry. */
1403	#define IEMTB_GET_TB_LOOKUP_TAB_ENTRY(a_pTb, a_idx) \
1404	((PIEMTB )&(a_pTb)->pabOpcodes[-(int)((a_pTb)->cTbLookupEntries - (a_idx)) sizeof(PIEMTB)])
1405
1406	/**
1407	* Gets the physical address for a TB opcode range.
1408	*/
1409	DECL_FORCE_INLINE(RTGCPHYS) iemTbGetRangePhysPageAddr(PCIEMTB pTb, uint8_t idxRange)
1410	{
1411	Assert(idxRange < RT_MIN(pTb->cRanges, RT_ELEMENTS(pTb->aRanges)));
1412	uint8_t const idxPage = pTb->aRanges[idxRange].idxPhysPage;
1413	Assert(idxPage <= RT_ELEMENTS(pTb->aGCPhysPages));
1414	if (idxPage == 0)
1415	return pTb->GCPhysPc & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
1416	Assert(!(pTb->aGCPhysPages[idxPage - 1] & GUEST_PAGE_OFFSET_MASK));
1417	return pTb->aGCPhysPages[idxPage - 1];
1418	}
1419
1420
1421	/**
1422	* A chunk of memory in the TB allocator.
1423	*/
1424	typedef struct IEMTBCHUNK
1425	{
1426	/** Pointer to the translation blocks in this chunk. */
1427	PIEMTB paTbs;
1428	#ifdef IN_RING0
1429	/** Allocation handle. */
1430	RTR0MEMOBJ hMemObj;
1431	#endif
1432	} IEMTBCHUNK;
1433
1434	/**
1435	* A per-CPU translation block allocator.
1436	*
1437	* Because of how the IEMTBCACHE uses the lower 6 bits of the TB address to keep
1438	* the length of the collision list, and of course also for cache line alignment
1439	* reasons, the TBs must be allocated with at least 64-byte alignment.
1440	* Memory is there therefore allocated using one of the page aligned allocators.
1441	*
1442	*
1443	* To avoid wasting too much memory, it is allocated piecemeal as needed,
1444	* in chunks (IEMTBCHUNK) of 2 MiB or more. The TB has an 8-bit chunk index
1445	* that enables us to quickly calculate the allocation bitmap position when
1446	* freeing the translation block.
1447	*/
1448	typedef struct IEMTBALLOCATOR
1449	{
1450	/** Magic value (IEMTBALLOCATOR_MAGIC). */
1451	uint32_t uMagic;
1452
1453	#ifdef IEMTB_SIZE_IS_POWER_OF_TWO
1454	/** Mask corresponding to cTbsPerChunk - 1. */
1455	uint32_t fChunkMask;
1456	/** Shift count corresponding to cTbsPerChunk. */
1457	uint8_t cChunkShift;
1458	#else
1459	uint32_t uUnused;
1460	uint8_t bUnused;
1461	#endif
1462	/** Number of chunks we're allowed to allocate. */
1463	uint8_t cMaxChunks;
1464	/** Number of chunks currently populated. */
1465	uint16_t cAllocatedChunks;
1466	/** Number of translation blocks per chunk. */
1467	uint32_t cTbsPerChunk;
1468	/** Chunk size. */
1469	uint32_t cbPerChunk;
1470
1471	/** The maximum number of TBs. */
1472	uint32_t cMaxTbs;
1473	/** Total number of TBs in the populated chunks.
1474	* (cAllocatedChunks * cTbsPerChunk) */
1475	uint32_t cTotalTbs;
1476	/** The current number of TBs in use.
1477	* The number of free TBs: cAllocatedTbs - cInUseTbs; */
1478	uint32_t cInUseTbs;
1479	/** Statistics: Number of the cInUseTbs that are native ones. */
1480	uint32_t cNativeTbs;
1481	/** Statistics: Number of the cInUseTbs that are threaded ones. */
1482	uint32_t cThreadedTbs;
1483
1484	/** Where to start pruning TBs from when we're out.
1485	* See iemTbAllocatorAllocSlow for details. */
1486	uint32_t iPruneFrom;
1487	/** Where to start pruning native TBs from when we're out of executable memory.
1488	* See iemTbAllocatorFreeupNativeSpace for details. */
1489	uint32_t iPruneNativeFrom;
1490	uint64_t u64Padding;
1491
1492	/** Statistics: Number of TB allocation calls. */
1493	STAMCOUNTER StatAllocs;
1494	/** Statistics: Number of TB free calls. */
1495	STAMCOUNTER StatFrees;
1496	/** Statistics: Time spend pruning. */
1497	STAMPROFILE StatPrune;
1498	/** Statistics: Time spend pruning native TBs. */
1499	STAMPROFILE StatPruneNative;
1500
1501	/** The delayed free list (see iemTbAlloctorScheduleForFree). */
1502	PIEMTB pDelayedFreeHead;
1503	/* Head of the list of free TBs. */
1504	PIEMTB pTbsFreeHead;
1505
1506	/** Allocation chunks. */
1507	IEMTBCHUNK aChunks[256];
1508	} IEMTBALLOCATOR;
1509	/** Pointer to a TB allocator. */
1510	typedef struct IEMTBALLOCATOR *PIEMTBALLOCATOR;
1511
1512	/** Magic value for the TB allocator (Emmet Harley Cohen). */
1513	#define IEMTBALLOCATOR_MAGIC UINT32_C(0x19900525)
1514
1515
1516	/**
1517	* A per-CPU translation block cache (hash table).
1518	*
1519	* The hash table is allocated once during IEM initialization and size double
1520	* the max TB count, rounded up to the nearest power of two (so we can use and
1521	* AND mask rather than a rest division when hashing).
1522	*/
1523	typedef struct IEMTBCACHE
1524	{
1525	/** Magic value (IEMTBCACHE_MAGIC). */
1526	uint32_t uMagic;
1527	/** Size of the hash table. This is a power of two. */
1528	uint32_t cHash;
1529	/** The mask corresponding to cHash. */
1530	uint32_t uHashMask;
1531	uint32_t uPadding;
1532
1533	/** @name Statistics
1534	* @{ */
1535	/** Number of collisions ever. */
1536	STAMCOUNTER cCollisions;
1537
1538	/** Statistics: Number of TB lookup misses. */
1539	STAMCOUNTER cLookupMisses;
1540	/** Statistics: Number of TB lookup hits via hash table (debug only). */
1541	STAMCOUNTER cLookupHits;
1542	/** Statistics: Number of TB lookup hits via TB associated lookup table (debug only). */
1543	STAMCOUNTER cLookupHitsViaTbLookupTable;
1544	STAMCOUNTER auPadding2[2];
1545	/** Statistics: Collision list length pruning. */
1546	STAMPROFILE StatPrune;
1547	/** @} */
1548
1549	/** The hash table itself.
1550	* @note The lower 6 bits of the pointer is used for keeping the collision
1551	* list length, so we can take action when it grows too long.
1552	* This works because TBs are allocated using a 64 byte (or
1553	* higher) alignment from page aligned chunks of memory, so the lower
1554	* 6 bits of the address will always be zero.
1555	* See IEMTBCACHE_PTR_COUNT_MASK, IEMTBCACHE_PTR_MAKE and friends.
1556	*/
1557	RT_FLEXIBLE_ARRAY_EXTENSION
1558	PIEMTB apHash[RT_FLEXIBLE_ARRAY];
1559	} IEMTBCACHE;
1560	/** Pointer to a per-CPU translation block cahce. */
1561	typedef IEMTBCACHE *PIEMTBCACHE;
1562
1563	/** Magic value for IEMTBCACHE (Johnny O'Neal). */
1564	#define IEMTBCACHE_MAGIC UINT32_C(0x19561010)
1565
1566	/** The collision count mask for IEMTBCACHE::apHash entries. */
1567	#define IEMTBCACHE_PTR_COUNT_MASK ((uintptr_t)0x3f)
1568	/** The max collision count for IEMTBCACHE::apHash entries before pruning. */
1569	#define IEMTBCACHE_PTR_MAX_COUNT ((uintptr_t)0x30)
1570	/** Combine a TB pointer and a collision list length into a value for an
1571	* IEMTBCACHE::apHash entry. */
1572	#define IEMTBCACHE_PTR_MAKE(a_pTb, a_cCount) (PIEMTB)((uintptr_t)(a_pTb) \| (a_cCount))
1573	/** Combine a TB pointer and a collision list length into a value for an
1574	* IEMTBCACHE::apHash entry. */
1575	#define IEMTBCACHE_PTR_GET_TB(a_pHashEntry) (PIEMTB)((uintptr_t)(a_pHashEntry) & ~IEMTBCACHE_PTR_COUNT_MASK)
1576	/** Combine a TB pointer and a collision list length into a value for an
1577	* IEMTBCACHE::apHash entry. */
1578	#define IEMTBCACHE_PTR_GET_COUNT(a_pHashEntry) ((uintptr_t)(a_pHashEntry) & IEMTBCACHE_PTR_COUNT_MASK)
1579
1580	/**
1581	* Calculates the hash table slot for a TB from physical PC address and TB flags.
1582	*/
1583	#define IEMTBCACHE_HASH(a_paCache, a_fTbFlags, a_GCPhysPc) \
1584	IEMTBCACHE_HASH_NO_KEY_MASK(a_paCache, (a_fTbFlags) & IEMTB_F_KEY_MASK, a_GCPhysPc)
1585
1586	/**
1587	* Calculates the hash table slot for a TB from physical PC address and TB
1588	* flags, ASSUMING the caller has applied IEMTB_F_KEY_MASK to @a a_fTbFlags.
1589	*/
1590	#define IEMTBCACHE_HASH_NO_KEY_MASK(a_paCache, a_fTbFlags, a_GCPhysPc) \
1591	(((uint32_t)(a_GCPhysPc) ^ (a_fTbFlags)) & (a_paCache)->uHashMask)
1592
1593
1594	/** @name IEMBRANCHED_F_XXX - Branched indicator (IEMCPU::fTbBranched).
1595	*
1596	* These flags parallels the main IEM_CIMPL_F_BRANCH_XXX flags.
1597	*
1598	* @{ */
1599	/** Value if no branching happened recently. */
1600	#define IEMBRANCHED_F_NO UINT8_C(0x00)
1601	/** Flag set if direct branch, clear if absolute or indirect. */
1602	#define IEMBRANCHED_F_DIRECT UINT8_C(0x01)
1603	/** Flag set if indirect branch, clear if direct or relative. */
1604	#define IEMBRANCHED_F_INDIRECT UINT8_C(0x02)
1605	/** Flag set if relative branch, clear if absolute or indirect. */
1606	#define IEMBRANCHED_F_RELATIVE UINT8_C(0x04)
1607	/** Flag set if conditional branch, clear if unconditional. */
1608	#define IEMBRANCHED_F_CONDITIONAL UINT8_C(0x08)
1609	/** Flag set if it's a far branch. */
1610	#define IEMBRANCHED_F_FAR UINT8_C(0x10)
1611	/** Flag set if the stack pointer is modified. */
1612	#define IEMBRANCHED_F_STACK UINT8_C(0x20)
1613	/** Flag set if the stack pointer and (maybe) the stack segment are modified. */
1614	#define IEMBRANCHED_F_STACK_FAR UINT8_C(0x40)
1615	/** Flag set (by IEM_MC_REL_JMP_XXX) if it's a zero bytes relative jump. */
1616	#define IEMBRANCHED_F_ZERO UINT8_C(0x80)
1617	/** @} */
1618
1619
1620	/**
1621	* The per-CPU IEM state.
1622	*/
1623	typedef struct IEMCPU
1624	{
1625	/** Info status code that needs to be propagated to the IEM caller.
1626	* This cannot be passed internally, as it would complicate all success
1627	* checks within the interpreter making the code larger and almost impossible
1628	* to get right. Instead, we'll store status codes to pass on here. Each
1629	* source of these codes will perform appropriate sanity checks. */
1630	int32_t rcPassUp; /* 0x00 */
1631	/** Execution flag, IEM_F_XXX. */
1632	uint32_t fExec; /* 0x04 */
1633
1634	/** @name Decoder state.
1635	* @{ */
1636	#ifdef IEM_WITH_CODE_TLB
1637	/** The offset of the next instruction byte. */
1638	uint32_t offInstrNextByte; /* 0x08 */
1639	/** The number of bytes available at pbInstrBuf for the current instruction.
1640	* This takes the max opcode length into account so that doesn't need to be
1641	* checked separately. */
1642	uint32_t cbInstrBuf; /* 0x0c */
1643	/** Pointer to the page containing RIP, user specified buffer or abOpcode.
1644	* This can be NULL if the page isn't mappable for some reason, in which
1645	* case we'll do fallback stuff.
1646	*
1647	* If we're executing an instruction from a user specified buffer,
1648	* IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
1649	* aligned pointer but pointer to the user data.
1650	*
1651	* For instructions crossing pages, this will start on the first page and be
1652	* advanced to the next page by the time we've decoded the instruction. This
1653	* therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
1654	*/
1655	uint8_t const pbInstrBuf; / 0x10 */
1656	# if ARCH_BITS == 32
1657	uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
1658	# endif
1659	/** The program counter corresponding to pbInstrBuf.
1660	* This is set to a non-canonical address when we need to invalidate it. */
1661	uint64_t uInstrBufPc; /* 0x18 */
1662	/** The guest physical address corresponding to pbInstrBuf. */
1663	RTGCPHYS GCPhysInstrBuf; /* 0x20 */
1664	/** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
1665	* This takes the CS segment limit into account.
1666	* @note Set to zero when the code TLB is flushed to trigger TLB reload. */
1667	uint16_t cbInstrBufTotal; /* 0x28 */
1668	/** Offset into pbInstrBuf of the first byte of the current instruction.
1669	* Can be negative to efficiently handle cross page instructions. */
1670	int16_t offCurInstrStart; /* 0x2a */
1671
1672	# ifndef IEM_WITH_OPAQUE_DECODER_STATE
1673	/** The prefix mask (IEM_OP_PRF_XXX). */
1674	uint32_t fPrefixes; /* 0x2c */
1675	/** The extra REX ModR/M register field bit (REX.R << 3). */
1676	uint8_t uRexReg; /* 0x30 */
1677	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
1678	* (REX.B << 3). */
1679	uint8_t uRexB; /* 0x31 */
1680	/** The extra REX SIB index field bit (REX.X << 3). */
1681	uint8_t uRexIndex; /* 0x32 */
1682
1683	/** The effective segment register (X86_SREG_XXX). */
1684	uint8_t iEffSeg; /* 0x33 */
1685
1686	/** The offset of the ModR/M byte relative to the start of the instruction. */
1687	uint8_t offModRm; /* 0x34 */
1688
1689	# ifdef IEM_WITH_CODE_TLB_AND_OPCODE_BUF
1690	/** The current offset into abOpcode. */
1691	uint8_t offOpcode; /* 0x35 */
1692	# else
1693	uint8_t bUnused; /* 0x35 */
1694	# endif
1695	# else /* IEM_WITH_OPAQUE_DECODER_STATE */
1696	uint8_t abOpaqueDecoderPart1[0x36 - 0x2c];
1697	# endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1698
1699	#else /* !IEM_WITH_CODE_TLB */
1700	# ifndef IEM_WITH_OPAQUE_DECODER_STATE
1701	/** The size of what has currently been fetched into abOpcode. */
1702	uint8_t cbOpcode; /* 0x08 */
1703	/** The current offset into abOpcode. */
1704	uint8_t offOpcode; /* 0x09 */
1705	/** The offset of the ModR/M byte relative to the start of the instruction. */
1706	uint8_t offModRm; /* 0x0a */
1707
1708	/** The effective segment register (X86_SREG_XXX). */
1709	uint8_t iEffSeg; /* 0x0b */
1710
1711	/** The prefix mask (IEM_OP_PRF_XXX). */
1712	uint32_t fPrefixes; /* 0x0c */
1713	/** The extra REX ModR/M register field bit (REX.R << 3). */
1714	uint8_t uRexReg; /* 0x10 */
1715	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
1716	* (REX.B << 3). */
1717	uint8_t uRexB; /* 0x11 */
1718	/** The extra REX SIB index field bit (REX.X << 3). */
1719	uint8_t uRexIndex; /* 0x12 */
1720
1721	# else /* IEM_WITH_OPAQUE_DECODER_STATE */
1722	uint8_t abOpaqueDecoderPart1[0x13 - 0x08];
1723	# endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1724	#endif /* !IEM_WITH_CODE_TLB */
1725
1726	#ifndef IEM_WITH_OPAQUE_DECODER_STATE
1727	/** The effective operand mode. */
1728	IEMMODE enmEffOpSize; /* 0x36, 0x13 */
1729	/** The default addressing mode. */
1730	IEMMODE enmDefAddrMode; /* 0x37, 0x14 */
1731	/** The effective addressing mode. */
1732	IEMMODE enmEffAddrMode; /* 0x38, 0x15 */
1733	/** The default operand mode. */
1734	IEMMODE enmDefOpSize; /* 0x39, 0x16 */
1735
1736	/** Prefix index (VEX.pp) for two byte and three byte tables. */
1737	uint8_t idxPrefix; /* 0x3a, 0x17 */
1738	/** 3rd VEX/EVEX/XOP register.
1739	* Please use IEM_GET_EFFECTIVE_VVVV to access. */
1740	uint8_t uVex3rdReg; /* 0x3b, 0x18 */
1741	/** The VEX/EVEX/XOP length field. */
1742	uint8_t uVexLength; /* 0x3c, 0x19 */
1743	/** Additional EVEX stuff. */
1744	uint8_t fEvexStuff; /* 0x3d, 0x1a */
1745
1746	# ifndef IEM_WITH_CODE_TLB
1747	/** Explicit alignment padding. */
1748	uint8_t abAlignment2a[1]; /* 0x1b */
1749	# endif
1750	/** The FPU opcode (FOP). */
1751	uint16_t uFpuOpcode; /* 0x3e, 0x1c */
1752	# ifndef IEM_WITH_CODE_TLB
1753	/** Explicit alignment padding. */
1754	uint8_t abAlignment2b[2]; /* 0x1e */
1755	# endif
1756
1757	/** The opcode bytes. */
1758	uint8_t abOpcode[15]; /* 0x40, 0x20 */
1759	/** Explicit alignment padding. */
1760	# ifdef IEM_WITH_CODE_TLB
1761	//uint8_t abAlignment2c[0x4f - 0x4f]; /* 0x4f */
1762	# else
1763	uint8_t abAlignment2c[0x4f - 0x2f]; /* 0x2f */
1764	# endif
1765
1766	#else /* IEM_WITH_OPAQUE_DECODER_STATE */
1767	# ifdef IEM_WITH_CODE_TLB
1768	uint8_t abOpaqueDecoderPart2[0x4f - 0x36];
1769	# else
1770	uint8_t abOpaqueDecoderPart2[0x4f - 0x13];
1771	# endif
1772	#endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1773	/** @} */
1774
1775
1776	/** The number of active guest memory mappings. */
1777	uint8_t cActiveMappings; /* 0x4f, 0x4f */
1778
1779	/** Records for tracking guest memory mappings. */
1780	struct
1781	{
1782	/** The address of the mapped bytes. */
1783	R3R0PTRTYPE(void *) pv;
1784	/** The access flags (IEM_ACCESS_XXX).
1785	* IEM_ACCESS_INVALID if the entry is unused. */
1786	uint32_t fAccess;
1787	#if HC_ARCH_BITS == 64
1788	uint32_t u32Alignment4; /*< Alignment padding. /
1789	#endif
1790	} aMemMappings[3]; /* 0x50 LB 0x30 */
1791
1792	/** Locking records for the mapped memory. */
1793	union
1794	{
1795	PGMPAGEMAPLOCK Lock;
1796	uint64_t au64Padding[2];
1797	} aMemMappingLocks[3]; /* 0x80 LB 0x30 */
1798
1799	/** Bounce buffer info.
1800	* This runs in parallel to aMemMappings. */
1801	struct
1802	{
1803	/** The physical address of the first byte. */
1804	RTGCPHYS GCPhysFirst;
1805	/** The physical address of the second page. */
1806	RTGCPHYS GCPhysSecond;
1807	/** The number of bytes in the first page. */
1808	uint16_t cbFirst;
1809	/** The number of bytes in the second page. */
1810	uint16_t cbSecond;
1811	/** Whether it's unassigned memory. */
1812	bool fUnassigned;
1813	/** Explicit alignment padding. */
1814	bool afAlignment5[3];
1815	} aMemBbMappings[3]; /* 0xb0 LB 0x48 */
1816
1817	/** The flags of the current exception / interrupt. */
1818	uint32_t fCurXcpt; /* 0xf8 */
1819	/** The current exception / interrupt. */
1820	uint8_t uCurXcpt; /* 0xfc */
1821	/** Exception / interrupt recursion depth. */
1822	int8_t cXcptRecursions; /* 0xfb */
1823
1824	/** The next unused mapping index.
1825	* @todo try find room for this up with cActiveMappings. */
1826	uint8_t iNextMapping; /* 0xfd */
1827	uint8_t abAlignment7[1];
1828
1829	/** Bounce buffer storage.
1830	* This runs in parallel to aMemMappings and aMemBbMappings. */
1831	struct
1832	{
1833	uint8_t ab[512];
1834	} aBounceBuffers[3]; /* 0x100 LB 0x600 */
1835
1836
1837	/** Pointer set jump buffer - ring-3 context. */
1838	R3PTRTYPE(jmp_buf *) pJmpBufR3;
1839	/** Pointer set jump buffer - ring-0 context. */
1840	R0PTRTYPE(jmp_buf *) pJmpBufR0;
1841
1842	/** @todo Should move this near @a fCurXcpt later. */
1843	/** The CR2 for the current exception / interrupt. */
1844	uint64_t uCurXcptCr2;
1845	/** The error code for the current exception / interrupt. */
1846	uint32_t uCurXcptErr;
1847
1848	/** @name Statistics
1849	* @{ */
1850	/** The number of instructions we've executed. */
1851	uint32_t cInstructions;
1852	/** The number of potential exits. */
1853	uint32_t cPotentialExits;
1854	/** The number of bytes data or stack written (mostly for IEMExecOneEx).
1855	* This may contain uncommitted writes. */
1856	uint32_t cbWritten;
1857	/** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
1858	uint32_t cRetInstrNotImplemented;
1859	/** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
1860	uint32_t cRetAspectNotImplemented;
1861	/** Counts informational statuses returned (other than VINF_SUCCESS). */
1862	uint32_t cRetInfStatuses;
1863	/** Counts other error statuses returned. */
1864	uint32_t cRetErrStatuses;
1865	/** Number of times rcPassUp has been used. */
1866	uint32_t cRetPassUpStatus;
1867	/** Number of times RZ left with instruction commit pending for ring-3. */
1868	uint32_t cPendingCommit;
1869	/** Number of misaligned (host sense) atomic instruction accesses. */
1870	uint32_t cMisalignedAtomics;
1871	/** Number of long jumps. */
1872	uint32_t cLongJumps;
1873	/** @} */
1874
1875	/** @name Target CPU information.
1876	* @{ */
1877	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
1878	/** The target CPU. */
1879	uint8_t uTargetCpu;
1880	#else
1881	uint8_t bTargetCpuPadding;
1882	#endif
1883	/** For selecting assembly works matching the target CPU EFLAGS behaviour, see
1884	* IEMTARGETCPU_EFL_BEHAVIOR_XXX for values, with the 1st entry for when no
1885	* native host support and the 2nd for when there is.
1886	*
1887	* The two values are typically indexed by a g_CpumHostFeatures bit.
1888	*
1889	* This is for instance used for the BSF & BSR instructions where AMD and
1890	* Intel CPUs produce different EFLAGS. */
1891	uint8_t aidxTargetCpuEflFlavour[2];
1892
1893	/** The CPU vendor. */
1894	CPUMCPUVENDOR enmCpuVendor;
1895	/** @} */
1896
1897	/** @name Host CPU information.
1898	* @{ */
1899	/** The CPU vendor. */
1900	CPUMCPUVENDOR enmHostCpuVendor;
1901	/** @} */
1902
1903	/** Counts RDMSR \#GP(0) LogRel(). */
1904	uint8_t cLogRelRdMsr;
1905	/** Counts WRMSR \#GP(0) LogRel(). */
1906	uint8_t cLogRelWrMsr;
1907	/** Alignment padding. */
1908	uint8_t abAlignment9[42];
1909
1910	/** @name Recompilation
1911	* @{ */
1912	/** Pointer to the current translation block.
1913	* This can either be one being executed or one being compiled. */
1914	R3PTRTYPE(PIEMTB) pCurTbR3;
1915	#ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
1916	/** Frame pointer for the last native TB to execute. */
1917	R3PTRTYPE(void *) pvTbFramePointerR3;
1918	#else
1919	R3PTRTYPE(void *) pvUnusedR3;
1920	#endif
1921	/** Fixed TB used for threaded recompilation.
1922	* This is allocated once with maxed-out sizes and re-used afterwards. */
1923	R3PTRTYPE(PIEMTB) pThrdCompileTbR3;
1924	/** Pointer to the ring-3 TB cache for this EMT. */
1925	R3PTRTYPE(PIEMTBCACHE) pTbCacheR3;
1926	/** Pointer to the ring-3 TB lookup entry.
1927	* This either points to pTbLookupEntryDummyR3 or an actually lookuptable
1928	* entry, thus it can always safely be used w/o NULL checking. */
1929	R3PTRTYPE(PIEMTB *) ppTbLookupEntryR3;
1930	/** The PC (RIP) at the start of pCurTbR3/pCurTbR0.
1931	* The TBs are based on physical addresses, so this is needed to correleated
1932	* RIP to opcode bytes stored in the TB (AMD-V / VT-x). */
1933	uint64_t uCurTbStartPc;
1934	/** Number of threaded TBs executed. */
1935	uint64_t cTbExecThreaded;
1936	/** Number of native TBs executed. */
1937	uint64_t cTbExecNative;
1938	/** Whether we need to check the opcode bytes for the current instruction.
1939	* This is set by a previous instruction if it modified memory or similar. */
1940	bool fTbCheckOpcodes;
1941	/** Indicates whether and how we just branched - IEMBRANCHED_F_XXX. */
1942	uint8_t fTbBranched;
1943	/** Set when GCPhysInstrBuf is updated because of a page crossing. */
1944	bool fTbCrossedPage;
1945	/** Whether to end the current TB. */
1946	bool fEndTb;
1947	/** Number of instructions before we need emit an IRQ check call again.
1948	* This helps making sure we don't execute too long w/o checking for
1949	* interrupts and immediately following instructions that may enable
1950	* interrupts (e.g. POPF, IRET, STI). With STI an additional hack is
1951	* required to make sure we check following the next instruction as well, see
1952	* fTbCurInstrIsSti. */
1953	uint8_t cInstrTillIrqCheck;
1954	/** Indicates that the current instruction is an STI. This is set by the
1955	* iemCImpl_sti code and subsequently cleared by the recompiler. */
1956	bool fTbCurInstrIsSti;
1957	/** The size of the IEMTB::pabOpcodes allocation in pThrdCompileTbR3. */
1958	uint16_t cbOpcodesAllocated;
1959	/** The current instruction number in a native TB.
1960	* This is set by code that may trigger an unexpected TB exit (throw/longjmp)
1961	* and will be picked up by the TB execution loop. Only used when
1962	* IEMNATIVE_WITH_INSTRUCTION_COUNTING is defined. */
1963	uint8_t idxTbCurInstr;
1964	/** Spaced reserved for recompiler data / alignment. */
1965	bool afRecompilerStuff1[3];
1966	/** The virtual sync time at the last timer poll call. */
1967	uint32_t msRecompilerPollNow;
1968	/** The IEMTB::cUsed value when to attempt native recompilation of a TB. */
1969	uint32_t uTbNativeRecompileAtUsedCount;
1970	/** The IEM_CIMPL_F_XXX mask for the current instruction. */
1971	uint32_t fTbCurInstr;
1972	/** The IEM_CIMPL_F_XXX mask for the previous instruction. */
1973	uint32_t fTbPrevInstr;
1974	/** Strict: Tracking skipped EFLAGS calculations. Any bits set here are
1975	* currently not up to date in EFLAGS. */
1976	uint32_t fSkippingEFlags;
1977	/** Previous GCPhysInstrBuf value - only valid if fTbCrossedPage is set. */
1978	RTGCPHYS GCPhysInstrBufPrev;
1979	/** Pointer to the ring-3 TB allocator for this EMT. */
1980	R3PTRTYPE(PIEMTBALLOCATOR) pTbAllocatorR3;
1981	/** Pointer to the ring-3 executable memory allocator for this EMT. */
1982	R3PTRTYPE(struct IEMEXECMEMALLOCATOR *) pExecMemAllocatorR3;
1983	/** Pointer to the native recompiler state for ring-3. */
1984	R3PTRTYPE(struct IEMRECOMPILERSTATE *) pNativeRecompilerStateR3;
1985	/** Dummy entry for ppTbLookupEntryR3. */
1986	R3PTRTYPE(PIEMTB) pTbLookupEntryDummyR3;
1987
1988	/** Dummy TLB entry used for accesses to pages with databreakpoints. */
1989	IEMTLBENTRY DataBreakpointTlbe;
1990
1991	/** Threaded TB statistics: Times TB execution was broken off before reaching the end. */
1992	STAMCOUNTER StatTbThreadedExecBreaks;
1993	/** Statistics: Times BltIn_CheckIrq breaks out of the TB. */
1994	STAMCOUNTER StatCheckIrqBreaks;
1995	/** Statistics: Times BltIn_CheckMode breaks out of the TB. */
1996	STAMCOUNTER StatCheckModeBreaks;
1997	/** Threaded TB statistics: Times execution break on call with lookup entries. */
1998	STAMCOUNTER StatTbThreadedExecBreaksWithLookup;
1999	/** Threaded TB statistics: Times execution break on call without lookup entries. */
2000	STAMCOUNTER StatTbThreadedExecBreaksWithoutLookup;
2001	/** Statistics: Times a post jump target check missed and had to find new TB. */
2002	STAMCOUNTER StatCheckBranchMisses;
2003	/** Statistics: Times a jump or page crossing required a TB with CS.LIM checking. */
2004	STAMCOUNTER StatCheckNeedCsLimChecking;
2005	/** Statistics: Times a loop was detected within a TB.. */
2006	STAMCOUNTER StatTbLoopInTbDetected;
2007	/** Exec memory allocator statistics: Number of times allocaintg executable memory failed. */
2008	STAMCOUNTER StatNativeExecMemInstrBufAllocFailed;
2009	/** Native TB statistics: Number of fully recompiled TBs. */
2010	STAMCOUNTER StatNativeFullyRecompiledTbs;
2011	/** TB statistics: Number of instructions per TB. */
2012	STAMPROFILE StatTbInstr;
2013	/** TB statistics: Number of TB lookup table entries per TB. */
2014	STAMPROFILE StatTbLookupEntries;
2015	/** Threaded TB statistics: Number of calls per TB. */
2016	STAMPROFILE StatTbThreadedCalls;
2017	/** Native TB statistics: Native code size per TB. */
2018	STAMPROFILE StatTbNativeCode;
2019	/** Native TB statistics: Profiling native recompilation. */
2020	STAMPROFILE StatNativeRecompilation;
2021	/** Native TB statistics: Number of calls per TB that were recompiled properly. */
2022	STAMPROFILE StatNativeCallsRecompiled;
2023	/** Native TB statistics: Number of threaded calls per TB that weren't recompiled. */
2024	STAMPROFILE StatNativeCallsThreaded;
2025	/** Native recompiled execution: TLB hits for data fetches. */
2026	STAMCOUNTER StatNativeTlbHitsForFetch;
2027	/** Native recompiled execution: TLB hits for data stores. */
2028	STAMCOUNTER StatNativeTlbHitsForStore;
2029	/** Native recompiled execution: TLB hits for stack accesses. */
2030	STAMCOUNTER StatNativeTlbHitsForStack;
2031	/** Native recompiled execution: TLB hits for mapped accesses. */
2032	STAMCOUNTER StatNativeTlbHitsForMapped;
2033	/** Native recompiled execution: Code TLB misses for new page. */
2034	STAMCOUNTER StatNativeCodeTlbMissesNewPage;
2035	/** Native recompiled execution: Code TLB hits for new page. */
2036	STAMCOUNTER StatNativeCodeTlbHitsForNewPage;
2037	/** Native recompiled execution: Code TLB misses for new page with offset. */
2038	STAMCOUNTER StatNativeCodeTlbMissesNewPageWithOffset;
2039	/** Native recompiled execution: Code TLB hits for new page with offset. */
2040	STAMCOUNTER StatNativeCodeTlbHitsForNewPageWithOffset;
2041
2042	/** Native recompiler: Number of calls to iemNativeRegAllocFindFree. */
2043	STAMCOUNTER StatNativeRegFindFree;
2044	/** Native recompiler: Number of times iemNativeRegAllocFindFree needed
2045	* to free a variable. */
2046	STAMCOUNTER StatNativeRegFindFreeVar;
2047	/** Native recompiler: Number of times iemNativeRegAllocFindFree did
2048	* not need to free any variables. */
2049	STAMCOUNTER StatNativeRegFindFreeNoVar;
2050	/** Native recompiler: Liveness info freed shadowed guest registers in
2051	* iemNativeRegAllocFindFree. */
2052	STAMCOUNTER StatNativeRegFindFreeLivenessUnshadowed;
2053	/** Native recompiler: Liveness info helped with the allocation in
2054	* iemNativeRegAllocFindFree. */
2055	STAMCOUNTER StatNativeRegFindFreeLivenessHelped;
2056
2057	/** Native recompiler: Number of times status flags calc has been skipped. */
2058	STAMCOUNTER StatNativeEflSkippedArithmetic;
2059	/** Native recompiler: Number of times status flags calc has been skipped. */
2060	STAMCOUNTER StatNativeEflSkippedLogical;
2061
2062	/** Native recompiler: Number of opportunities to skip EFLAGS.CF updating. */
2063	STAMCOUNTER StatNativeLivenessEflCfSkippable;
2064	/** Native recompiler: Number of opportunities to skip EFLAGS.PF updating. */
2065	STAMCOUNTER StatNativeLivenessEflPfSkippable;
2066	/** Native recompiler: Number of opportunities to skip EFLAGS.AF updating. */
2067	STAMCOUNTER StatNativeLivenessEflAfSkippable;
2068	/** Native recompiler: Number of opportunities to skip EFLAGS.ZF updating. */
2069	STAMCOUNTER StatNativeLivenessEflZfSkippable;
2070	/** Native recompiler: Number of opportunities to skip EFLAGS.SF updating. */
2071	STAMCOUNTER StatNativeLivenessEflSfSkippable;
2072	/** Native recompiler: Number of opportunities to skip EFLAGS.OF updating. */
2073	STAMCOUNTER StatNativeLivenessEflOfSkippable;
2074	/** Native recompiler: Number of required EFLAGS.CF updates. */
2075	STAMCOUNTER StatNativeLivenessEflCfRequired;
2076	/** Native recompiler: Number of required EFLAGS.PF updates. */
2077	STAMCOUNTER StatNativeLivenessEflPfRequired;
2078	/** Native recompiler: Number of required EFLAGS.AF updates. */
2079	STAMCOUNTER StatNativeLivenessEflAfRequired;
2080	/** Native recompiler: Number of required EFLAGS.ZF updates. */
2081	STAMCOUNTER StatNativeLivenessEflZfRequired;
2082	/** Native recompiler: Number of required EFLAGS.SF updates. */
2083	STAMCOUNTER StatNativeLivenessEflSfRequired;
2084	/** Native recompiler: Number of required EFLAGS.OF updates. */
2085	STAMCOUNTER StatNativeLivenessEflOfRequired;
2086	/** Native recompiler: Number of potentially delayable EFLAGS.CF updates. */
2087	STAMCOUNTER StatNativeLivenessEflCfDelayable;
2088	/** Native recompiler: Number of potentially delayable EFLAGS.PF updates. */
2089	STAMCOUNTER StatNativeLivenessEflPfDelayable;
2090	/** Native recompiler: Number of potentially delayable EFLAGS.AF updates. */
2091	STAMCOUNTER StatNativeLivenessEflAfDelayable;
2092	/** Native recompiler: Number of potentially delayable EFLAGS.ZF updates. */
2093	STAMCOUNTER StatNativeLivenessEflZfDelayable;
2094	/** Native recompiler: Number of potentially delayable EFLAGS.SF updates. */
2095	STAMCOUNTER StatNativeLivenessEflSfDelayable;
2096	/** Native recompiler: Number of potentially delayable EFLAGS.OF updates. */
2097	STAMCOUNTER StatNativeLivenessEflOfDelayable;
2098
2099	/** Native recompiler: Number of potential PC updates in total. */
2100	STAMCOUNTER StatNativePcUpdateTotal;
2101	/** Native recompiler: Number of PC updates which could be delayed. */
2102	STAMCOUNTER StatNativePcUpdateDelayed;
2103
2104	//#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
2105	/** Native recompiler: Number of calls to iemNativeSimdRegAllocFindFree. */
2106	STAMCOUNTER StatNativeSimdRegFindFree;
2107	/** Native recompiler: Number of times iemNativeSimdRegAllocFindFree needed
2108	* to free a variable. */
2109	STAMCOUNTER StatNativeSimdRegFindFreeVar;
2110	/** Native recompiler: Number of times iemNativeSimdRegAllocFindFree did
2111	* not need to free any variables. */
2112	STAMCOUNTER StatNativeSimdRegFindFreeNoVar;
2113	/** Native recompiler: Liveness info freed shadowed guest registers in
2114	* iemNativeSimdRegAllocFindFree. */
2115	STAMCOUNTER StatNativeSimdRegFindFreeLivenessUnshadowed;
2116	/** Native recompiler: Liveness info helped with the allocation in
2117	* iemNativeSimdRegAllocFindFree. */
2118	STAMCOUNTER StatNativeSimdRegFindFreeLivenessHelped;
2119
2120	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() checks. */
2121	STAMCOUNTER StatNativeMaybeDeviceNotAvailXcptCheckPotential;
2122	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() checks. */
2123	STAMCOUNTER StatNativeMaybeWaitDeviceNotAvailXcptCheckPotential;
2124	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() checks. */
2125	STAMCOUNTER StatNativeMaybeSseXcptCheckPotential;
2126	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() checks. */
2127	STAMCOUNTER StatNativeMaybeAvxXcptCheckPotential;
2128
2129	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() checks omitted. */
2130	STAMCOUNTER StatNativeMaybeDeviceNotAvailXcptCheckOmitted;
2131	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() checks omitted. */
2132	STAMCOUNTER StatNativeMaybeWaitDeviceNotAvailXcptCheckOmitted;
2133	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() checks omitted. */
2134	STAMCOUNTER StatNativeMaybeSseXcptCheckOmitted;
2135	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() checks omitted. */
2136	STAMCOUNTER StatNativeMaybeAvxXcptCheckOmitted;
2137	//#endif
2138
2139	/** Native recompiler: The TB finished executing completely without jumping to a an exit label.
2140	* Not availabe in release builds. */
2141	STAMCOUNTER StatNativeTbFinished;
2142	/** Native recompiler: The TB finished executing jumping to the ReturnBreak label. */
2143	STAMCOUNTER StatNativeTbExitReturnBreak;
2144	/** Native recompiler: The TB finished executing jumping to the ReturnBreakFF label. */
2145	STAMCOUNTER StatNativeTbExitReturnBreakFF;
2146	/** Native recompiler: The TB finished executing jumping to the ReturnWithFlags label. */
2147	STAMCOUNTER StatNativeTbExitReturnWithFlags;
2148	/** Native recompiler: The TB finished executing with other non-zero status. */
2149	STAMCOUNTER StatNativeTbExitReturnOtherStatus;
2150	/** Native recompiler: The TB finished executing via throw / long jump. */
2151	STAMCOUNTER StatNativeTbExitLongJump;
2152	/** Native recompiler: The TB finished executing jumping to the ReturnBreak
2153	* label, but directly jumped to the next TB, scenario \#1 w/o IRQ checks. */
2154	STAMCOUNTER StatNativeTbExitDirectLinking1NoIrq;
2155	/** Native recompiler: The TB finished executing jumping to the ReturnBreak
2156	* label, but directly jumped to the next TB, scenario \#1 with IRQ checks. */
2157	STAMCOUNTER StatNativeTbExitDirectLinking1Irq;
2158	/** Native recompiler: The TB finished executing jumping to the ReturnBreak
2159	* label, but directly jumped to the next TB, scenario \#1 w/o IRQ checks. */
2160	STAMCOUNTER StatNativeTbExitDirectLinking2NoIrq;
2161	/** Native recompiler: The TB finished executing jumping to the ReturnBreak
2162	* label, but directly jumped to the next TB, scenario \#2 with IRQ checks. */
2163	STAMCOUNTER StatNativeTbExitDirectLinking2Irq;
2164
2165	/** Native recompiler: The TB finished executing jumping to the RaiseDe label. */
2166	STAMCOUNTER StatNativeTbExitRaiseDe;
2167	/** Native recompiler: The TB finished executing jumping to the RaiseUd label. */
2168	STAMCOUNTER StatNativeTbExitRaiseUd;
2169	/** Native recompiler: The TB finished executing jumping to the RaiseSseRelated label. */
2170	STAMCOUNTER StatNativeTbExitRaiseSseRelated;
2171	/** Native recompiler: The TB finished executing jumping to the RaiseAvxRelated label. */
2172	STAMCOUNTER StatNativeTbExitRaiseAvxRelated;
2173	/** Native recompiler: The TB finished executing jumping to the RaiseSseAvxFpRelated label. */
2174	STAMCOUNTER StatNativeTbExitRaiseSseAvxFpRelated;
2175	/** Native recompiler: The TB finished executing jumping to the RaiseNm label. */
2176	STAMCOUNTER StatNativeTbExitRaiseNm;
2177	/** Native recompiler: The TB finished executing jumping to the RaiseGp0 label. */
2178	STAMCOUNTER StatNativeTbExitRaiseGp0;
2179	/** Native recompiler: The TB finished executing jumping to the RaiseMf label. */
2180	STAMCOUNTER StatNativeTbExitRaiseMf;
2181	/** Native recompiler: The TB finished executing jumping to the RaiseXf label. */
2182	STAMCOUNTER StatNativeTbExitRaiseXf;
2183	/** Native recompiler: The TB finished executing jumping to the ObsoleteTb label. */
2184	STAMCOUNTER StatNativeTbExitObsoleteTb;
2185
2186	/** Native recompiler: Failure situations with direct linking scenario \#1.
2187	* Counter with StatNativeTbExitReturnBreak. Not in release builds.
2188	* @{ */
2189	STAMCOUNTER StatNativeTbExitDirectLinking1NoTb;
2190	STAMCOUNTER StatNativeTbExitDirectLinking1MismatchGCPhysPc;
2191	STAMCOUNTER StatNativeTbExitDirectLinking1MismatchFlags;
2192	STAMCOUNTER StatNativeTbExitDirectLinking1PendingIrq;
2193	/** @} */
2194
2195	/** Native recompiler: Failure situations with direct linking scenario \#2.
2196	* Counter with StatNativeTbExitReturnBreak. Not in release builds.
2197	* @{ */
2198	STAMCOUNTER StatNativeTbExitDirectLinking2NoTb;
2199	STAMCOUNTER StatNativeTbExitDirectLinking2MismatchGCPhysPc;
2200	STAMCOUNTER StatNativeTbExitDirectLinking2MismatchFlags;
2201	STAMCOUNTER StatNativeTbExitDirectLinking2PendingIrq;
2202	/** @} */
2203
2204	/** iemMemMap and iemMemMapJmp statistics.
2205	* @{ */
2206	STAMCOUNTER StatMemMapJmp;
2207	STAMCOUNTER StatMemMapNoJmp;
2208	STAMCOUNTER StatMemBounceBufferCrossPage;
2209	STAMCOUNTER StatMemBounceBufferMapPhys;
2210	/** @} */
2211
2212	uint64_t au64Padding[5];
2213	/** @} */
2214
2215	/** Data TLB.
2216	* @remarks Must be 64-byte aligned. */
2217	IEMTLB DataTlb;
2218	/** Instruction TLB.
2219	* @remarks Must be 64-byte aligned. */
2220	IEMTLB CodeTlb;
2221
2222	/** Exception statistics. */
2223	STAMCOUNTER aStatXcpts[32];
2224	/** Interrupt statistics. */
2225	uint32_t aStatInts[256];
2226
2227	#if defined(VBOX_WITH_STATISTICS) && !defined(DOXYGEN_RUNNING) && !defined(IEM_WITHOUT_INSTRUCTION_STATS)
2228	/** Instruction statistics for ring-0/raw-mode. */
2229	IEMINSTRSTATS StatsRZ;
2230	/** Instruction statistics for ring-3. */
2231	IEMINSTRSTATS StatsR3;
2232	# ifdef VBOX_WITH_IEM_RECOMPILER
2233	/** Statistics per threaded function call.
2234	* Updated by both the threaded and native recompilers. */
2235	uint32_t acThreadedFuncStats[0x6000 /24576/];
2236	# endif
2237	#endif
2238	} IEMCPU;
2239	AssertCompileMemberOffset(IEMCPU, cActiveMappings, 0x4f);
2240	AssertCompileMemberAlignment(IEMCPU, aMemMappings, 16);
2241	AssertCompileMemberAlignment(IEMCPU, aMemMappingLocks, 16);
2242	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 64);
2243	AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
2244	AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
2245
2246	/** Pointer to the per-CPU IEM state. */
2247	typedef IEMCPU *PIEMCPU;
2248	/** Pointer to the const per-CPU IEM state. */
2249	typedef IEMCPU const *PCIEMCPU;
2250
2251
2252	/** @def IEM_GET_CTX
2253	* Gets the guest CPU context for the calling EMT.
2254	* @returns PCPUMCTX
2255	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2256	*/
2257	#define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
2258
2259	/** @def IEM_CTX_ASSERT
2260	* Asserts that the @a a_fExtrnMbz is present in the CPU context.
2261	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2262	* @param a_fExtrnMbz The mask of CPUMCTX_EXTRN_XXX flags that must be zero.
2263	*/
2264	#define IEM_CTX_ASSERT(a_pVCpu, a_fExtrnMbz) \
2265	AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
2266	("fExtrn=%#RX64 & fExtrnMbz=%#RX64 -> %#RX64\n", \
2267	(a_pVCpu)->cpum.GstCtx.fExtrn, (a_fExtrnMbz), (a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz) ))
2268
2269	/** @def IEM_CTX_IMPORT_RET
2270	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
2271	*
2272	* Will call the keep to import the bits as needed.
2273	*
2274	* Returns on import failure.
2275	*
2276	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2277	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
2278	*/
2279	#define IEM_CTX_IMPORT_RET(a_pVCpu, a_fExtrnImport) \
2280	do { \
2281	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
2282	{ /* likely */ } \
2283	else \
2284	{ \
2285	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
2286	AssertRCReturn(rcCtxImport, rcCtxImport); \
2287	} \
2288	} while (0)
2289
2290	/** @def IEM_CTX_IMPORT_NORET
2291	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
2292	*
2293	* Will call the keep to import the bits as needed.
2294	*
2295	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2296	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
2297	*/
2298	#define IEM_CTX_IMPORT_NORET(a_pVCpu, a_fExtrnImport) \
2299	do { \
2300	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
2301	{ /* likely */ } \
2302	else \
2303	{ \
2304	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
2305	AssertLogRelRC(rcCtxImport); \
2306	} \
2307	} while (0)
2308
2309	/** @def IEM_CTX_IMPORT_JMP
2310	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
2311	*
2312	* Will call the keep to import the bits as needed.
2313	*
2314	* Jumps on import failure.
2315	*
2316	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2317	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
2318	*/
2319	#define IEM_CTX_IMPORT_JMP(a_pVCpu, a_fExtrnImport) \
2320	do { \
2321	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
2322	{ /* likely */ } \
2323	else \
2324	{ \
2325	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
2326	AssertRCStmt(rcCtxImport, IEM_DO_LONGJMP(pVCpu, rcCtxImport)); \
2327	} \
2328	} while (0)
2329
2330
2331
2332	/** @def IEM_GET_TARGET_CPU
2333	* Gets the current IEMTARGETCPU value.
2334	* @returns IEMTARGETCPU value.
2335	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2336	*/
2337	#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
2338	# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
2339	#else
2340	# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
2341	#endif
2342
2343	/** @def IEM_GET_INSTR_LEN
2344	* Gets the instruction length. */
2345	#ifdef IEM_WITH_CODE_TLB
2346	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
2347	#else
2348	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
2349	#endif
2350
2351	/** @def IEM_TRY_SETJMP
2352	* Wrapper around setjmp / try, hiding all the ugly differences.
2353	*
2354	* @note Use with extreme care as this is a fragile macro.
2355	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2356	* @param a_rcTarget The variable that should receive the status code in case
2357	* of a longjmp/throw.
2358	*/
2359	/** @def IEM_TRY_SETJMP_AGAIN
2360	* For when setjmp / try is used again in the same variable scope as a previous
2361	* IEM_TRY_SETJMP invocation.
2362	*/
2363	/** @def IEM_CATCH_LONGJMP_BEGIN
2364	* Start wrapper for catch / setjmp-else.
2365	*
2366	* This will set up a scope.
2367	*
2368	* @note Use with extreme care as this is a fragile macro.
2369	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2370	* @param a_rcTarget The variable that should receive the status code in case
2371	* of a longjmp/throw.
2372	*/
2373	/** @def IEM_CATCH_LONGJMP_END
2374	* End wrapper for catch / setjmp-else.
2375	*
2376	* This will close the scope set up by IEM_CATCH_LONGJMP_BEGIN and clean up the
2377	* state.
2378	*
2379	* @note Use with extreme care as this is a fragile macro.
2380	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2381	*/
2382	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
2383	# ifdef IEM_WITH_THROW_CATCH
2384	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
2385	a_rcTarget = VINF_SUCCESS; \
2386	try
2387	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
2388	IEM_TRY_SETJMP(a_pVCpu, a_rcTarget)
2389	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
2390	catch (int rcThrown) \
2391	{ \
2392	a_rcTarget = rcThrown
2393	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
2394	} \
2395	((void)0)
2396	# else /* !IEM_WITH_THROW_CATCH */
2397	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
2398	jmp_buf JmpBuf; \
2399	jmp_buf * volatile pSavedJmpBuf = (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf); \
2400	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
2401	if ((rcStrict = setjmp(JmpBuf)) == 0)
2402	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
2403	pSavedJmpBuf = (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf); \
2404	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
2405	if ((rcStrict = setjmp(JmpBuf)) == 0)
2406	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
2407	else \
2408	{ \
2409	((void)0)
2410	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
2411	} \
2412	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = pSavedJmpBuf
2413	# endif /* !IEM_WITH_THROW_CATCH */
2414	#endif /* IEM_WITH_SETJMP */
2415
2416
2417	/**
2418	* Shared per-VM IEM data.
2419	*/
2420	typedef struct IEM
2421	{
2422	/** The VMX APIC-access page handler type. */
2423	PGMPHYSHANDLERTYPE hVmxApicAccessPage;
2424	#ifndef VBOX_WITHOUT_CPUID_HOST_CALL
2425	/** Set if the CPUID host call functionality is enabled. */
2426	bool fCpuIdHostCall;
2427	#endif
2428	} IEM;
2429
2430
2431
2432	/** @name IEM_ACCESS_XXX - Access details.
2433	* @{ */
2434	#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
2435	#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
2436	#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
2437	#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
2438	#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
2439	#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
2440	#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
2441	#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
2442	#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
2443	#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
2444	/** The writes are partial, so if initialize the bounce buffer with the
2445	* orignal RAM content. */
2446	#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
2447	/** Used in aMemMappings to indicate that the entry is bounce buffered. */
2448	#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
2449	/** Bounce buffer with ring-3 write pending, first page. */
2450	#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
2451	/** Bounce buffer with ring-3 write pending, second page. */
2452	#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
2453	/** Not locked, accessed via the TLB. */
2454	#define IEM_ACCESS_NOT_LOCKED UINT32_C(0x00001000)
2455	/** Atomic access.
2456	* This enables special alignment checks and the VINF_EM_EMULATE_SPLIT_LOCK
2457	* fallback for misaligned stuff. See @bugref{10547}. */
2458	#define IEM_ACCESS_ATOMIC UINT32_C(0x00002000)
2459	/** Valid bit mask. */
2460	#define IEM_ACCESS_VALID_MASK UINT32_C(0x00003fff)
2461	/** Shift count for the TLB flags (upper word). */
2462	#define IEM_ACCESS_SHIFT_TLB_FLAGS 16
2463
2464	/** Atomic read+write data alias. */
2465	#define IEM_ACCESS_DATA_ATOMIC (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA \| IEM_ACCESS_ATOMIC)
2466	/** Read+write data alias. */
2467	#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
2468	/** Write data alias. */
2469	#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
2470	/** Read data alias. */
2471	#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_DATA)
2472	/** Instruction fetch alias. */
2473	#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_WHAT_CODE)
2474	/** Stack write alias. */
2475	#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
2476	/** Stack read alias. */
2477	#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_STACK)
2478	/** Stack read+write alias. */
2479	#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
2480	/** Read system table alias. */
2481	#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_SYS)
2482	/** Read+write system table alias. */
2483	#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_SYS)
2484	/** @} */
2485
2486	/** @name Prefix constants (IEMCPU::fPrefixes)
2487	* @{ */
2488	#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /*< CS segment prefix (0x2e). /
2489	#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /*< SS segment prefix (0x36). /
2490	#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /*< DS segment prefix (0x3e). /
2491	#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /*< ES segment prefix (0x26). /
2492	#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /*< FS segment prefix (0x64). /
2493	#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /*< GS segment prefix (0x65). /
2494	#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
2495
2496	#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /*< Operand size prefix (0x66). /
2497	#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /*< REX.W prefix (0x48-0x4f). /
2498	#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /*< Address size prefix (0x67). /
2499
2500	#define IEM_OP_PRF_LOCK RT_BIT_32(16) /*< Lock prefix (0xf0). /
2501	#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /*< Repeat-not-zero prefix (0xf2). /
2502	#define IEM_OP_PRF_REPZ RT_BIT_32(18) /*< Repeat-if-zero prefix (0xf3). /
2503
2504	#define IEM_OP_PRF_REX RT_BIT_32(24) /*< Any REX prefix (0x40-0x4f). /
2505	#define IEM_OP_PRF_REX_B RT_BIT_32(25) /*< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). /
2506	#define IEM_OP_PRF_REX_X RT_BIT_32(26) /*< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). /
2507	#define IEM_OP_PRF_REX_R RT_BIT_32(27) /*< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). /
2508	/** Mask with all the REX prefix flags.
2509	* This is generally for use when needing to undo the REX prefixes when they
2510	* are followed legacy prefixes and therefore does not immediately preceed
2511	* the first opcode byte.
2512	* For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
2513	#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX \| IEM_OP_PRF_REX_R \| IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X \| IEM_OP_PRF_SIZE_REX_W )
2514
2515	#define IEM_OP_PRF_VEX RT_BIT_32(28) /*< Indiciates VEX prefix. /
2516	#define IEM_OP_PRF_EVEX RT_BIT_32(29) /*< Indiciates EVEX prefix. /
2517	#define IEM_OP_PRF_XOP RT_BIT_32(30) /*< Indiciates XOP prefix. /
2518	/** @} */
2519
2520	/** @name IEMOPFORM_XXX - Opcode forms
2521	* @note These are ORed together with IEMOPHINT_XXX.
2522	* @{ */
2523	/** ModR/M: reg, r/m */
2524	#define IEMOPFORM_RM 0
2525	/** ModR/M: reg, r/m (register) */
2526	#define IEMOPFORM_RM_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
2527	/** ModR/M: reg, r/m (memory) */
2528	#define IEMOPFORM_RM_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
2529	/** ModR/M: reg, r/m, imm */
2530	#define IEMOPFORM_RMI 1
2531	/** ModR/M: reg, r/m (register), imm */
2532	#define IEMOPFORM_RMI_REG (IEMOPFORM_RMI \| IEMOPFORM_MOD3)
2533	/** ModR/M: reg, r/m (memory), imm */
2534	#define IEMOPFORM_RMI_MEM (IEMOPFORM_RMI \| IEMOPFORM_NOT_MOD3)
2535	/** ModR/M: reg, r/m, xmm0 */
2536	#define IEMOPFORM_RM0 2
2537	/** ModR/M: reg, r/m (register), xmm0 */
2538	#define IEMOPFORM_RM0_REG (IEMOPFORM_RM0 \| IEMOPFORM_MOD3)
2539	/** ModR/M: reg, r/m (memory), xmm0 */
2540	#define IEMOPFORM_RM0_MEM (IEMOPFORM_RM0 \| IEMOPFORM_NOT_MOD3)
2541	/** ModR/M: r/m, reg */
2542	#define IEMOPFORM_MR 3
2543	/** ModR/M: r/m (register), reg */
2544	#define IEMOPFORM_MR_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
2545	/** ModR/M: r/m (memory), reg */
2546	#define IEMOPFORM_MR_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
2547	/** ModR/M: r/m, reg, imm */
2548	#define IEMOPFORM_MRI 4
2549	/** ModR/M: r/m (register), reg, imm */
2550	#define IEMOPFORM_MRI_REG (IEMOPFORM_MRI \| IEMOPFORM_MOD3)
2551	/** ModR/M: r/m (memory), reg, imm */
2552	#define IEMOPFORM_MRI_MEM (IEMOPFORM_MRI \| IEMOPFORM_NOT_MOD3)
2553	/** ModR/M: r/m only */
2554	#define IEMOPFORM_M 5
2555	/** ModR/M: r/m only (register). */
2556	#define IEMOPFORM_M_REG (IEMOPFORM_M \| IEMOPFORM_MOD3)
2557	/** ModR/M: r/m only (memory). */
2558	#define IEMOPFORM_M_MEM (IEMOPFORM_M \| IEMOPFORM_NOT_MOD3)
2559	/** ModR/M: r/m, imm */
2560	#define IEMOPFORM_MI 6
2561	/** ModR/M: r/m (register), imm */
2562	#define IEMOPFORM_MI_REG (IEMOPFORM_MI \| IEMOPFORM_MOD3)
2563	/** ModR/M: r/m (memory), imm */
2564	#define IEMOPFORM_MI_MEM (IEMOPFORM_MI \| IEMOPFORM_NOT_MOD3)
2565	/** ModR/M: r/m, 1 (shift and rotate instructions) */
2566	#define IEMOPFORM_M1 7
2567	/** ModR/M: r/m (register), 1. */
2568	#define IEMOPFORM_M1_REG (IEMOPFORM_M1 \| IEMOPFORM_MOD3)
2569	/** ModR/M: r/m (memory), 1. */
2570	#define IEMOPFORM_M1_MEM (IEMOPFORM_M1 \| IEMOPFORM_NOT_MOD3)
2571	/** ModR/M: r/m, CL (shift and rotate instructions)
2572	* @todo This should just've been a generic fixed register. But the python
2573	* code doesn't needs more convincing. */
2574	#define IEMOPFORM_M_CL 8
2575	/** ModR/M: r/m (register), CL. */
2576	#define IEMOPFORM_M_CL_REG (IEMOPFORM_M_CL \| IEMOPFORM_MOD3)
2577	/** ModR/M: r/m (memory), CL. */
2578	#define IEMOPFORM_M_CL_MEM (IEMOPFORM_M_CL \| IEMOPFORM_NOT_MOD3)
2579	/** ModR/M: reg only */
2580	#define IEMOPFORM_R 9
2581
2582	/** VEX+ModR/M: reg, r/m */
2583	#define IEMOPFORM_VEX_RM 16
2584	/** VEX+ModR/M: reg, r/m (register) */
2585	#define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM \| IEMOPFORM_MOD3)
2586	/** VEX+ModR/M: reg, r/m (memory) */
2587	#define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM \| IEMOPFORM_NOT_MOD3)
2588	/** VEX+ModR/M: r/m, reg */
2589	#define IEMOPFORM_VEX_MR 17
2590	/** VEX+ModR/M: r/m (register), reg */
2591	#define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR \| IEMOPFORM_MOD3)
2592	/** VEX+ModR/M: r/m (memory), reg */
2593	#define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR \| IEMOPFORM_NOT_MOD3)
2594	/** VEX+ModR/M: r/m, reg, imm8 */
2595	#define IEMOPFORM_VEX_MRI 18
2596	/** VEX+ModR/M: r/m (register), reg, imm8 */
2597	#define IEMOPFORM_VEX_MRI_REG (IEMOPFORM_VEX_MRI \| IEMOPFORM_MOD3)
2598	/** VEX+ModR/M: r/m (memory), reg, imm8 */
2599	#define IEMOPFORM_VEX_MRI_MEM (IEMOPFORM_VEX_MRI \| IEMOPFORM_NOT_MOD3)
2600	/** VEX+ModR/M: r/m only */
2601	#define IEMOPFORM_VEX_M 19
2602	/** VEX+ModR/M: r/m only (register). */
2603	#define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M \| IEMOPFORM_MOD3)
2604	/** VEX+ModR/M: r/m only (memory). */
2605	#define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M \| IEMOPFORM_NOT_MOD3)
2606	/** VEX+ModR/M: reg only */
2607	#define IEMOPFORM_VEX_R 20
2608	/** VEX+ModR/M: reg, vvvv, r/m */
2609	#define IEMOPFORM_VEX_RVM 21
2610	/** VEX+ModR/M: reg, vvvv, r/m (register). */
2611	#define IEMOPFORM_VEX_RVM_REG (IEMOPFORM_VEX_RVM \| IEMOPFORM_MOD3)
2612	/** VEX+ModR/M: reg, vvvv, r/m (memory). */
2613	#define IEMOPFORM_VEX_RVM_MEM (IEMOPFORM_VEX_RVM \| IEMOPFORM_NOT_MOD3)
2614	/** VEX+ModR/M: reg, vvvv, r/m, imm */
2615	#define IEMOPFORM_VEX_RVMI 22
2616	/** VEX+ModR/M: reg, vvvv, r/m (register), imm. */
2617	#define IEMOPFORM_VEX_RVMI_REG (IEMOPFORM_VEX_RVMI \| IEMOPFORM_MOD3)
2618	/** VEX+ModR/M: reg, vvvv, r/m (memory), imm. */
2619	#define IEMOPFORM_VEX_RVMI_MEM (IEMOPFORM_VEX_RVMI \| IEMOPFORM_NOT_MOD3)
2620	/** VEX+ModR/M: reg, vvvv, r/m, imm(reg) */
2621	#define IEMOPFORM_VEX_RVMR 23
2622	/** VEX+ModR/M: reg, vvvv, r/m (register), imm(reg). */
2623	#define IEMOPFORM_VEX_RVMR_REG (IEMOPFORM_VEX_RVMI \| IEMOPFORM_MOD3)
2624	/** VEX+ModR/M: reg, vvvv, r/m (memory), imm(reg). */
2625	#define IEMOPFORM_VEX_RVMR_MEM (IEMOPFORM_VEX_RVMI \| IEMOPFORM_NOT_MOD3)
2626	/** VEX+ModR/M: reg, r/m, vvvv */
2627	#define IEMOPFORM_VEX_RMV 24
2628	/** VEX+ModR/M: reg, r/m, vvvv (register). */
2629	#define IEMOPFORM_VEX_RMV_REG (IEMOPFORM_VEX_RMV \| IEMOPFORM_MOD3)
2630	/** VEX+ModR/M: reg, r/m, vvvv (memory). */
2631	#define IEMOPFORM_VEX_RMV_MEM (IEMOPFORM_VEX_RMV \| IEMOPFORM_NOT_MOD3)
2632	/** VEX+ModR/M: reg, r/m, imm8 */
2633	#define IEMOPFORM_VEX_RMI 25
2634	/** VEX+ModR/M: reg, r/m, imm8 (register). */
2635	#define IEMOPFORM_VEX_RMI_REG (IEMOPFORM_VEX_RMI \| IEMOPFORM_MOD3)
2636	/** VEX+ModR/M: reg, r/m, imm8 (memory). */
2637	#define IEMOPFORM_VEX_RMI_MEM (IEMOPFORM_VEX_RMI \| IEMOPFORM_NOT_MOD3)
2638	/** VEX+ModR/M: r/m, vvvv, reg */
2639	#define IEMOPFORM_VEX_MVR 26
2640	/** VEX+ModR/M: r/m, vvvv, reg (register) */
2641	#define IEMOPFORM_VEX_MVR_REG (IEMOPFORM_VEX_MVR \| IEMOPFORM_MOD3)
2642	/** VEX+ModR/M: r/m, vvvv, reg (memory) */
2643	#define IEMOPFORM_VEX_MVR_MEM (IEMOPFORM_VEX_MVR \| IEMOPFORM_NOT_MOD3)
2644	/** VEX+ModR/M+/n: vvvv, r/m */
2645	#define IEMOPFORM_VEX_VM 27
2646	/** VEX+ModR/M+/n: vvvv, r/m (register) */
2647	#define IEMOPFORM_VEX_VM_REG (IEMOPFORM_VEX_VM \| IEMOPFORM_MOD3)
2648	/** VEX+ModR/M+/n: vvvv, r/m (memory) */
2649	#define IEMOPFORM_VEX_VM_MEM (IEMOPFORM_VEX_VM \| IEMOPFORM_NOT_MOD3)
2650	/** VEX+ModR/M+/n: vvvv, r/m, imm8 */
2651	#define IEMOPFORM_VEX_VMI 28
2652	/** VEX+ModR/M+/n: vvvv, r/m, imm8 (register) */
2653	#define IEMOPFORM_VEX_VMI_REG (IEMOPFORM_VEX_VMI \| IEMOPFORM_MOD3)
2654	/** VEX+ModR/M+/n: vvvv, r/m, imm8 (memory) */
2655	#define IEMOPFORM_VEX_VMI_MEM (IEMOPFORM_VEX_VMI \| IEMOPFORM_NOT_MOD3)
2656
2657	/** Fixed register instruction, no R/M. */
2658	#define IEMOPFORM_FIXED 32
2659
2660	/** The r/m is a register. */
2661	#define IEMOPFORM_MOD3 RT_BIT_32(8)
2662	/** The r/m is a memory access. */
2663	#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
2664	/** @} */
2665
2666	/** @name IEMOPHINT_XXX - Additional Opcode Hints
2667	* @note These are ORed together with IEMOPFORM_XXX.
2668	* @{ */
2669	/** Ignores the operand size prefix (66h). */
2670	#define IEMOPHINT_IGNORES_OZ_PFX RT_BIT_32(10)
2671	/** Ignores REX.W (aka WIG). */
2672	#define IEMOPHINT_IGNORES_REXW RT_BIT_32(11)
2673	/** Both the operand size prefixes (66h + REX.W) are ignored. */
2674	#define IEMOPHINT_IGNORES_OP_SIZES (IEMOPHINT_IGNORES_OZ_PFX \| IEMOPHINT_IGNORES_REXW)
2675	/** Allowed with the lock prefix. */
2676	#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
2677	/** The VEX.L value is ignored (aka LIG). */
2678	#define IEMOPHINT_VEX_L_IGNORED RT_BIT_32(12)
2679	/** The VEX.L value must be zero (i.e. 128-bit width only). */
2680	#define IEMOPHINT_VEX_L_ZERO RT_BIT_32(13)
2681	/** The VEX.L value must be one (i.e. 256-bit width only). */
2682	#define IEMOPHINT_VEX_L_ONE RT_BIT_32(14)
2683	/** The VEX.V value must be zero. */
2684	#define IEMOPHINT_VEX_V_ZERO RT_BIT_32(15)
2685	/** The REX.W/VEX.V value must be zero. */
2686	#define IEMOPHINT_REX_W_ZERO RT_BIT_32(16)
2687	#define IEMOPHINT_VEX_W_ZERO IEMOPHINT_REX_W_ZERO
2688	/** The REX.W/VEX.V value must be one. */
2689	#define IEMOPHINT_REX_W_ONE RT_BIT_32(17)
2690	#define IEMOPHINT_VEX_W_ONE IEMOPHINT_REX_W_ONE
2691
2692	/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
2693	#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
2694	/** @} */
2695
2696	/**
2697	* Possible hardware task switch sources.
2698	*/
2699	typedef enum IEMTASKSWITCH
2700	{
2701	/** Task switch caused by an interrupt/exception. */
2702	IEMTASKSWITCH_INT_XCPT = 1,
2703	/** Task switch caused by a far CALL. */
2704	IEMTASKSWITCH_CALL,
2705	/** Task switch caused by a far JMP. */
2706	IEMTASKSWITCH_JUMP,
2707	/** Task switch caused by an IRET. */
2708	IEMTASKSWITCH_IRET
2709	} IEMTASKSWITCH;
2710	AssertCompileSize(IEMTASKSWITCH, 4);
2711
2712	/**
2713	* Possible CrX load (write) sources.
2714	*/
2715	typedef enum IEMACCESSCRX
2716	{
2717	/** CrX access caused by 'mov crX' instruction. */
2718	IEMACCESSCRX_MOV_CRX,
2719	/** CrX (CR0) write caused by 'lmsw' instruction. */
2720	IEMACCESSCRX_LMSW,
2721	/** CrX (CR0) write caused by 'clts' instruction. */
2722	IEMACCESSCRX_CLTS,
2723	/** CrX (CR0) read caused by 'smsw' instruction. */
2724	IEMACCESSCRX_SMSW
2725	} IEMACCESSCRX;
2726
2727	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2728	/** @name IEM_SLAT_FAIL_XXX - Second-level address translation failure information.
2729	*
2730	* These flags provide further context to SLAT page-walk failures that could not be
2731	* determined by PGM (e.g, PGM is not privy to memory access permissions).
2732	*
2733	* @{
2734	*/
2735	/** Translating a nested-guest linear address failed accessing a nested-guest
2736	* physical address. */
2737	# define IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR RT_BIT_32(0)
2738	/** Translating a nested-guest linear address failed accessing a
2739	* paging-structure entry or updating accessed/dirty bits. */
2740	# define IEM_SLAT_FAIL_LINEAR_TO_PAGE_TABLE RT_BIT_32(1)
2741	/** @} */
2742
2743	DECLCALLBACK(FNPGMPHYSHANDLER) iemVmxApicAccessPageHandler;
2744	# ifndef IN_RING3
2745	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) iemVmxApicAccessPagePfHandler;
2746	# endif
2747	#endif
2748
2749	/**
2750	* Indicates to the verifier that the given flag set is undefined.
2751	*
2752	* Can be invoked again to add more flags.
2753	*
2754	* This is a NOOP if the verifier isn't compiled in.
2755	*
2756	* @note We're temporarily keeping this until code is converted to new
2757	* disassembler style opcode handling.
2758	*/
2759	#define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
2760
2761
2762	/** @def IEM_DECL_IMPL_TYPE
2763	* For typedef'ing an instruction implementation function.
2764	*
2765	* @param a_RetType The return type.
2766	* @param a_Name The name of the type.
2767	* @param a_ArgList The argument list enclosed in parentheses.
2768	*/
2769
2770	/** @def IEM_DECL_IMPL_DEF
2771	* For defining an instruction implementation function.
2772	*
2773	* @param a_RetType The return type.
2774	* @param a_Name The name of the type.
2775	* @param a_ArgList The argument list enclosed in parentheses.
2776	*/
2777
2778	#if defined(__GNUC__) && defined(RT_ARCH_X86)
2779	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2780	__attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
2781	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2782	__attribute__((__fastcall__, __nothrow__)) DECL_HIDDEN_ONLY(a_RetType) a_Name a_ArgList
2783	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2784	__attribute__((__fastcall__, __nothrow__)) DECL_HIDDEN_ONLY(a_RetType) a_Name a_ArgList
2785
2786	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
2787	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2788	a_RetType (__fastcall a_Name) a_ArgList
2789	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2790	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
2791	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2792	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
2793
2794	#elif __cplusplus >= 201700 /* P0012R1 support */
2795	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2796	a_RetType (VBOXCALL a_Name) a_ArgList RT_NOEXCEPT
2797	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2798	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList RT_NOEXCEPT
2799	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2800	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList RT_NOEXCEPT
2801
2802	#else
2803	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2804	a_RetType (VBOXCALL a_Name) a_ArgList
2805	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2806	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList
2807	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2808	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList
2809
2810	#endif
2811
2812	/** Defined in IEMAllAImplC.cpp but also used by IEMAllAImplA.asm. */
2813	RT_C_DECLS_BEGIN
2814	extern uint8_t const g_afParity[256];
2815	RT_C_DECLS_END
2816
2817
2818	/** @name Arithmetic assignment operations on bytes (binary).
2819	* @{ */
2820	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU8, (uint32_t fEFlagsIn, uint8_t *pu8Dst, uint8_t u8Src));
2821	typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
2822	FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
2823	FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
2824	FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
2825	FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
2826	FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
2827	FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
2828	FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
2829	/** @} */
2830
2831	/** @name Arithmetic assignment operations on words (binary).
2832	* @{ */
2833	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU16, (uint32_t fEFlagsIn, uint16_t *pu16Dst, uint16_t u16Src));
2834	typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
2835	FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
2836	FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
2837	FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
2838	FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
2839	FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
2840	FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
2841	FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
2842	/** @} */
2843
2844
2845	/** @name Arithmetic assignment operations on double words (binary).
2846	* @{ */
2847	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU32, (uint32_t fEFlagsIn, uint32_t *pu32Dst, uint32_t u32Src));
2848	typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
2849	FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
2850	FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
2851	FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
2852	FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
2853	FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
2854	FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
2855	FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
2856	FNIEMAIMPLBINU32 iemAImpl_blsi_u32, iemAImpl_blsi_u32_fallback;
2857	FNIEMAIMPLBINU32 iemAImpl_blsr_u32, iemAImpl_blsr_u32_fallback;
2858	FNIEMAIMPLBINU32 iemAImpl_blsmsk_u32, iemAImpl_blsmsk_u32_fallback;
2859	/** @} */
2860
2861	/** @name Arithmetic assignment operations on quad words (binary).
2862	* @{ */
2863	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU64, (uint32_t fEFlagsIn, uint64_t *pu64Dst, uint64_t u64Src));
2864	typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
2865	FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
2866	FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
2867	FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
2868	FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
2869	FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
2870	FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
2871	FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
2872	FNIEMAIMPLBINU64 iemAImpl_blsi_u64, iemAImpl_blsi_u64_fallback;
2873	FNIEMAIMPLBINU64 iemAImpl_blsr_u64, iemAImpl_blsr_u64_fallback;
2874	FNIEMAIMPLBINU64 iemAImpl_blsmsk_u64, iemAImpl_blsmsk_u64_fallback;
2875	/** @} */
2876
2877	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU8, (uint32_t fEFlagsIn, uint8_t const *pu8Dst, uint8_t u8Src));
2878	typedef FNIEMAIMPLBINROU8 *PFNIEMAIMPLBINROU8;
2879	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU16,(uint32_t fEFlagsIn, uint16_t const *pu16Dst, uint16_t u16Src));
2880	typedef FNIEMAIMPLBINROU16 *PFNIEMAIMPLBINROU16;
2881	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU32,(uint32_t fEFlagsIn, uint32_t const *pu32Dst, uint32_t u32Src));
2882	typedef FNIEMAIMPLBINROU32 *PFNIEMAIMPLBINROU32;
2883	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU64,(uint32_t fEFlagsIn, uint64_t const *pu64Dst, uint64_t u64Src));
2884	typedef FNIEMAIMPLBINROU64 *PFNIEMAIMPLBINROU64;
2885
2886	/** @name Compare operations (thrown in with the binary ops).
2887	* @{ */
2888	FNIEMAIMPLBINROU8 iemAImpl_cmp_u8;
2889	FNIEMAIMPLBINROU16 iemAImpl_cmp_u16;
2890	FNIEMAIMPLBINROU32 iemAImpl_cmp_u32;
2891	FNIEMAIMPLBINROU64 iemAImpl_cmp_u64;
2892	/** @} */
2893
2894	/** @name Test operations (thrown in with the binary ops).
2895	* @{ */
2896	FNIEMAIMPLBINROU8 iemAImpl_test_u8;
2897	FNIEMAIMPLBINROU16 iemAImpl_test_u16;
2898	FNIEMAIMPLBINROU32 iemAImpl_test_u32;
2899	FNIEMAIMPLBINROU64 iemAImpl_test_u64;
2900	/** @} */
2901
2902	/** @name Bit operations operations (thrown in with the binary ops).
2903	* @{ */
2904	FNIEMAIMPLBINROU16 iemAImpl_bt_u16;
2905	FNIEMAIMPLBINROU32 iemAImpl_bt_u32;
2906	FNIEMAIMPLBINROU64 iemAImpl_bt_u64;
2907	FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
2908	FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
2909	FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
2910	FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
2911	FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
2912	FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
2913	FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
2914	FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
2915	FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
2916	/** @} */
2917
2918	/** @name Arithmetic three operand operations on double words (binary).
2919	* @{ */
2920	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32, (uint32_t pu32Dst, uint32_t u32Src1, uint32_t u32Src2, uint32_t pEFlags));
2921	typedef FNIEMAIMPLBINVEXU32 *PFNIEMAIMPLBINVEXU32;
2922	FNIEMAIMPLBINVEXU32 iemAImpl_andn_u32, iemAImpl_andn_u32_fallback;
2923	FNIEMAIMPLBINVEXU32 iemAImpl_bextr_u32, iemAImpl_bextr_u32_fallback;
2924	FNIEMAIMPLBINVEXU32 iemAImpl_bzhi_u32, iemAImpl_bzhi_u32_fallback;
2925	/** @} */
2926
2927	/** @name Arithmetic three operand operations on quad words (binary).
2928	* @{ */
2929	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64, (uint64_t pu64Dst, uint64_t u64Src1, uint64_t u64Src2, uint32_t pEFlags));
2930	typedef FNIEMAIMPLBINVEXU64 *PFNIEMAIMPLBINVEXU64;
2931	FNIEMAIMPLBINVEXU64 iemAImpl_andn_u64, iemAImpl_andn_u64_fallback;
2932	FNIEMAIMPLBINVEXU64 iemAImpl_bextr_u64, iemAImpl_bextr_u64_fallback;
2933	FNIEMAIMPLBINVEXU64 iemAImpl_bzhi_u64, iemAImpl_bzhi_u64_fallback;
2934	/** @} */
2935
2936	/** @name Arithmetic three operand operations on double words w/o EFLAGS (binary).
2937	* @{ */
2938	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32NOEFL, (uint32_t *pu32Dst, uint32_t u32Src1, uint32_t u32Src2));
2939	typedef FNIEMAIMPLBINVEXU32NOEFL *PFNIEMAIMPLBINVEXU32NOEFL;
2940	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pdep_u32, iemAImpl_pdep_u32_fallback;
2941	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pext_u32, iemAImpl_pext_u32_fallback;
2942	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_sarx_u32, iemAImpl_sarx_u32_fallback;
2943	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shlx_u32, iemAImpl_shlx_u32_fallback;
2944	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shrx_u32, iemAImpl_shrx_u32_fallback;
2945	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_rorx_u32;
2946	/** @} */
2947
2948	/** @name Arithmetic three operand operations on quad words w/o EFLAGS (binary).
2949	* @{ */
2950	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64NOEFL, (uint64_t *pu64Dst, uint64_t u64Src1, uint64_t u64Src2));
2951	typedef FNIEMAIMPLBINVEXU64NOEFL *PFNIEMAIMPLBINVEXU64NOEFL;
2952	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pdep_u64, iemAImpl_pdep_u64_fallback;
2953	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pext_u64, iemAImpl_pext_u64_fallback;
2954	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_sarx_u64, iemAImpl_sarx_u64_fallback;
2955	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shlx_u64, iemAImpl_shlx_u64_fallback;
2956	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shrx_u64, iemAImpl_shrx_u64_fallback;
2957	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_rorx_u64;
2958	/** @} */
2959
2960	/** @name MULX 32-bit and 64-bit.
2961	* @{ */
2962	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU32, (uint32_t puDst1, uint32_t puDst2, uint32_t uSrc1, uint32_t uSrc2));
2963	typedef FNIEMAIMPLMULXVEXU32 *PFNIEMAIMPLMULXVEXU32;
2964	FNIEMAIMPLMULXVEXU32 iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback;
2965
2966	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU64, (uint64_t puDst1, uint64_t puDst2, uint64_t uSrc1, uint64_t uSrc2));
2967	typedef FNIEMAIMPLMULXVEXU64 *PFNIEMAIMPLMULXVEXU64;
2968	FNIEMAIMPLMULXVEXU64 iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback;
2969	/** @} */
2970
2971
2972	/** @name Exchange memory with register operations.
2973	* @{ */
2974	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_locked, (uint8_t pu8Mem, uint8_t pu8Reg));
2975	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_locked,(uint16_t pu16Mem, uint16_t pu16Reg));
2976	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_locked,(uint32_t pu32Mem, uint32_t pu32Reg));
2977	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_locked,(uint64_t pu64Mem, uint64_t pu64Reg));
2978	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_unlocked, (uint8_t pu8Mem, uint8_t pu8Reg));
2979	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_unlocked,(uint16_t pu16Mem, uint16_t pu16Reg));
2980	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_unlocked,(uint32_t pu32Mem, uint32_t pu32Reg));
2981	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_unlocked,(uint64_t pu64Mem, uint64_t pu64Reg));
2982	/** @} */
2983
2984	/** @name Exchange and add operations.
2985	* @{ */
2986	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
2987	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
2988	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
2989	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
2990	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
2991	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
2992	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
2993	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
2994	/** @} */
2995
2996	/** @name Compare and exchange.
2997	* @{ */
2998	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
2999	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
3000	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
3001	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
3002	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
3003	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
3004	#if ARCH_BITS == 32
3005	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
3006	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
3007	#else
3008	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
3009	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
3010	#endif
3011	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
3012	uint32_t *pEFlags));
3013	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
3014	uint32_t *pEFlags));
3015	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
3016	uint32_t *pEFlags));
3017	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
3018	uint32_t *pEFlags));
3019	#ifndef RT_ARCH_ARM64
3020	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
3021	PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
3022	#endif
3023	/** @} */
3024
3025	/** @name Memory ordering
3026	* @{ */
3027	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
3028	typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
3029	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
3030	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
3031	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
3032	#ifndef RT_ARCH_ARM64
3033	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
3034	#endif
3035	/** @} */
3036
3037	/** @name Double precision shifts
3038	* @{ */
3039	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t pEFlags));
3040	typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
3041	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t pEFlags));
3042	typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
3043	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t pEFlags));
3044	typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
3045	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16, iemAImpl_shld_u16_amd, iemAImpl_shld_u16_intel;
3046	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32, iemAImpl_shld_u32_amd, iemAImpl_shld_u32_intel;
3047	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64, iemAImpl_shld_u64_amd, iemAImpl_shld_u64_intel;
3048	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16, iemAImpl_shrd_u16_amd, iemAImpl_shrd_u16_intel;
3049	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32, iemAImpl_shrd_u32_amd, iemAImpl_shrd_u32_intel;
3050	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64, iemAImpl_shrd_u64_amd, iemAImpl_shrd_u64_intel;
3051	/** @} */
3052
3053
3054	/** @name Bit search operations (thrown in with the binary ops).
3055	* @{ */
3056	FNIEMAIMPLBINU16 iemAImpl_bsf_u16, iemAImpl_bsf_u16_amd, iemAImpl_bsf_u16_intel;
3057	FNIEMAIMPLBINU32 iemAImpl_bsf_u32, iemAImpl_bsf_u32_amd, iemAImpl_bsf_u32_intel;
3058	FNIEMAIMPLBINU64 iemAImpl_bsf_u64, iemAImpl_bsf_u64_amd, iemAImpl_bsf_u64_intel;
3059	FNIEMAIMPLBINU16 iemAImpl_bsr_u16, iemAImpl_bsr_u16_amd, iemAImpl_bsr_u16_intel;
3060	FNIEMAIMPLBINU32 iemAImpl_bsr_u32, iemAImpl_bsr_u32_amd, iemAImpl_bsr_u32_intel;
3061	FNIEMAIMPLBINU64 iemAImpl_bsr_u64, iemAImpl_bsr_u64_amd, iemAImpl_bsr_u64_intel;
3062	FNIEMAIMPLBINU16 iemAImpl_lzcnt_u16, iemAImpl_lzcnt_u16_amd, iemAImpl_lzcnt_u16_intel;
3063	FNIEMAIMPLBINU32 iemAImpl_lzcnt_u32, iemAImpl_lzcnt_u32_amd, iemAImpl_lzcnt_u32_intel;
3064	FNIEMAIMPLBINU64 iemAImpl_lzcnt_u64, iemAImpl_lzcnt_u64_amd, iemAImpl_lzcnt_u64_intel;
3065	FNIEMAIMPLBINU16 iemAImpl_tzcnt_u16, iemAImpl_tzcnt_u16_amd, iemAImpl_tzcnt_u16_intel;
3066	FNIEMAIMPLBINU32 iemAImpl_tzcnt_u32, iemAImpl_tzcnt_u32_amd, iemAImpl_tzcnt_u32_intel;
3067	FNIEMAIMPLBINU64 iemAImpl_tzcnt_u64, iemAImpl_tzcnt_u64_amd, iemAImpl_tzcnt_u64_intel;
3068	FNIEMAIMPLBINU16 iemAImpl_popcnt_u16, iemAImpl_popcnt_u16_fallback;
3069	FNIEMAIMPLBINU32 iemAImpl_popcnt_u32, iemAImpl_popcnt_u32_fallback;
3070	FNIEMAIMPLBINU64 iemAImpl_popcnt_u64, iemAImpl_popcnt_u64_fallback;
3071	/** @} */
3072
3073	/** @name Signed multiplication operations (thrown in with the binary ops).
3074	* @{ */
3075	FNIEMAIMPLBINU16 iemAImpl_imul_two_u16, iemAImpl_imul_two_u16_amd, iemAImpl_imul_two_u16_intel;
3076	FNIEMAIMPLBINU32 iemAImpl_imul_two_u32, iemAImpl_imul_two_u32_amd, iemAImpl_imul_two_u32_intel;
3077	FNIEMAIMPLBINU64 iemAImpl_imul_two_u64, iemAImpl_imul_two_u64_amd, iemAImpl_imul_two_u64_intel;
3078	/** @} */
3079
3080	/** @name Arithmetic assignment operations on bytes (unary).
3081	* @{ */
3082	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t pu8Dst, uint32_t pEFlags));
3083	typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
3084	FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
3085	FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
3086	FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
3087	FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
3088	/** @} */
3089
3090	/** @name Arithmetic assignment operations on words (unary).
3091	* @{ */
3092	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t pu16Dst, uint32_t pEFlags));
3093	typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
3094	FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
3095	FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
3096	FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
3097	FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
3098	/** @} */
3099
3100	/** @name Arithmetic assignment operations on double words (unary).
3101	* @{ */
3102	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t pu32Dst, uint32_t pEFlags));
3103	typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
3104	FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
3105	FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
3106	FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
3107	FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
3108	/** @} */
3109
3110	/** @name Arithmetic assignment operations on quad words (unary).
3111	* @{ */
3112	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t pu64Dst, uint32_t pEFlags));
3113	typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
3114	FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
3115	FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
3116	FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
3117	FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
3118	/** @} */
3119
3120
3121	/** @name Shift operations on bytes (Group 2).
3122	* @{ */
3123	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU8,(uint32_t fEFlagsIn, uint8_t *pu8Dst, uint8_t cShift));
3124	typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
3125	FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8, iemAImpl_rol_u8_amd, iemAImpl_rol_u8_intel;
3126	FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8, iemAImpl_ror_u8_amd, iemAImpl_ror_u8_intel;
3127	FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8, iemAImpl_rcl_u8_amd, iemAImpl_rcl_u8_intel;
3128	FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8, iemAImpl_rcr_u8_amd, iemAImpl_rcr_u8_intel;
3129	FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8, iemAImpl_shl_u8_amd, iemAImpl_shl_u8_intel;
3130	FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8, iemAImpl_shr_u8_amd, iemAImpl_shr_u8_intel;
3131	FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8, iemAImpl_sar_u8_amd, iemAImpl_sar_u8_intel;
3132	/** @} */
3133
3134	/** @name Shift operations on words (Group 2).
3135	* @{ */
3136	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU16,(uint32_t fEFlagsIn, uint16_t *pu16Dst, uint8_t cShift));
3137	typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
3138	FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16, iemAImpl_rol_u16_amd, iemAImpl_rol_u16_intel;
3139	FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16, iemAImpl_ror_u16_amd, iemAImpl_ror_u16_intel;
3140	FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16, iemAImpl_rcl_u16_amd, iemAImpl_rcl_u16_intel;
3141	FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16, iemAImpl_rcr_u16_amd, iemAImpl_rcr_u16_intel;
3142	FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16, iemAImpl_shl_u16_amd, iemAImpl_shl_u16_intel;
3143	FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16, iemAImpl_shr_u16_amd, iemAImpl_shr_u16_intel;
3144	FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16, iemAImpl_sar_u16_amd, iemAImpl_sar_u16_intel;
3145	/** @} */
3146
3147	/** @name Shift operations on double words (Group 2).
3148	* @{ */
3149	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU32,(uint32_t fEFlagsIn, uint32_t *pu32Dst, uint8_t cShift));
3150	typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
3151	FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32, iemAImpl_rol_u32_amd, iemAImpl_rol_u32_intel;
3152	FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32, iemAImpl_ror_u32_amd, iemAImpl_ror_u32_intel;
3153	FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32, iemAImpl_rcl_u32_amd, iemAImpl_rcl_u32_intel;
3154	FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32, iemAImpl_rcr_u32_amd, iemAImpl_rcr_u32_intel;
3155	FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32, iemAImpl_shl_u32_amd, iemAImpl_shl_u32_intel;
3156	FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32, iemAImpl_shr_u32_amd, iemAImpl_shr_u32_intel;
3157	FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32, iemAImpl_sar_u32_amd, iemAImpl_sar_u32_intel;
3158	/** @} */
3159
3160	/** @name Shift operations on words (Group 2).
3161	* @{ */
3162	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU64,(uint32_t fEFlagsIn, uint64_t *pu64Dst, uint8_t cShift));
3163	typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
3164	FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64, iemAImpl_rol_u64_amd, iemAImpl_rol_u64_intel;
3165	FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64, iemAImpl_ror_u64_amd, iemAImpl_ror_u64_intel;
3166	FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64, iemAImpl_rcl_u64_amd, iemAImpl_rcl_u64_intel;
3167	FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64, iemAImpl_rcr_u64_amd, iemAImpl_rcr_u64_intel;
3168	FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64, iemAImpl_shl_u64_amd, iemAImpl_shl_u64_intel;
3169	FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64, iemAImpl_shr_u64_amd, iemAImpl_shr_u64_intel;
3170	FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64, iemAImpl_sar_u64_amd, iemAImpl_sar_u64_intel;
3171	/** @} */
3172
3173	/** @name Multiplication and division operations.
3174	* @{ */
3175	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t pu16AX, uint8_t u8FactorDivisor, uint32_t pEFlags));
3176	typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
3177	FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_mul_u8_amd, iemAImpl_mul_u8_intel;
3178	FNIEMAIMPLMULDIVU8 iemAImpl_imul_u8, iemAImpl_imul_u8_amd, iemAImpl_imul_u8_intel;
3179	FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_div_u8_amd, iemAImpl_div_u8_intel;
3180	FNIEMAIMPLMULDIVU8 iemAImpl_idiv_u8, iemAImpl_idiv_u8_amd, iemAImpl_idiv_u8_intel;
3181
3182	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t pu16AX, uint16_t pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
3183	typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
3184	FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_mul_u16_amd, iemAImpl_mul_u16_intel;
3185	FNIEMAIMPLMULDIVU16 iemAImpl_imul_u16, iemAImpl_imul_u16_amd, iemAImpl_imul_u16_intel;
3186	FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_div_u16_amd, iemAImpl_div_u16_intel;
3187	FNIEMAIMPLMULDIVU16 iemAImpl_idiv_u16, iemAImpl_idiv_u16_amd, iemAImpl_idiv_u16_intel;
3188
3189	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t pu32EAX, uint32_t pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
3190	typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
3191	FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_mul_u32_amd, iemAImpl_mul_u32_intel;
3192	FNIEMAIMPLMULDIVU32 iemAImpl_imul_u32, iemAImpl_imul_u32_amd, iemAImpl_imul_u32_intel;
3193	FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_div_u32_amd, iemAImpl_div_u32_intel;
3194	FNIEMAIMPLMULDIVU32 iemAImpl_idiv_u32, iemAImpl_idiv_u32_amd, iemAImpl_idiv_u32_intel;
3195
3196	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t pu64RAX, uint64_t pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
3197	typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
3198	FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_mul_u64_amd, iemAImpl_mul_u64_intel;
3199	FNIEMAIMPLMULDIVU64 iemAImpl_imul_u64, iemAImpl_imul_u64_amd, iemAImpl_imul_u64_intel;
3200	FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_div_u64_amd, iemAImpl_div_u64_intel;
3201	FNIEMAIMPLMULDIVU64 iemAImpl_idiv_u64, iemAImpl_idiv_u64_amd, iemAImpl_idiv_u64_intel;
3202	/** @} */
3203
3204	/** @name Byte Swap.
3205	* @{ */
3206	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t pu32Dst)); / Yes, 32-bit register access. */
3207	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
3208	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
3209	/** @} */
3210
3211	/** @name Misc.
3212	* @{ */
3213	FNIEMAIMPLBINU16 iemAImpl_arpl;
3214	/** @} */
3215
3216	/** @name RDRAND and RDSEED
3217	* @{ */
3218	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU16,(uint16_t puDst, uint32_t pEFlags));
3219	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU32,(uint32_t puDst, uint32_t pEFlags));
3220	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU64,(uint64_t puDst, uint32_t pEFlags));
3221	typedef FNIEMAIMPLRDRANDSEEDU16 *PFNIEMAIMPLRDRANDSEEDU16;
3222	typedef FNIEMAIMPLRDRANDSEEDU32 *PFNIEMAIMPLRDRANDSEEDU32;
3223	typedef FNIEMAIMPLRDRANDSEEDU64 *PFNIEMAIMPLRDRANDSEEDU64;
3224
3225	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdrand_u16, iemAImpl_rdrand_u16_fallback;
3226	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdrand_u32, iemAImpl_rdrand_u32_fallback;
3227	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdrand_u64, iemAImpl_rdrand_u64_fallback;
3228	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdseed_u16, iemAImpl_rdseed_u16_fallback;
3229	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdseed_u32, iemAImpl_rdseed_u32_fallback;
3230	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdseed_u64, iemAImpl_rdseed_u64_fallback;
3231	/** @} */
3232
3233	/** @name ADOX and ADCX
3234	* @{ */
3235	FNIEMAIMPLBINU32 iemAImpl_adcx_u32, iemAImpl_adcx_u32_fallback;
3236	FNIEMAIMPLBINU64 iemAImpl_adcx_u64, iemAImpl_adcx_u64_fallback;
3237	FNIEMAIMPLBINU32 iemAImpl_adox_u32, iemAImpl_adox_u32_fallback;
3238	FNIEMAIMPLBINU64 iemAImpl_adox_u64, iemAImpl_adox_u64_fallback;
3239	/** @} */
3240
3241	/** @name FPU operations taking a 32-bit float argument
3242	* @{ */
3243	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3244	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
3245	typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
3246
3247	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3248	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
3249	typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
3250
3251	FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
3252	FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
3253	FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
3254	FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
3255	FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
3256	FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
3257	FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
3258
3259	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
3260	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3261	PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
3262	/** @} */
3263
3264	/** @name FPU operations taking a 64-bit float argument
3265	* @{ */
3266	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3267	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
3268	typedef FNIEMAIMPLFPUR64FSW *PFNIEMAIMPLFPUR64FSW;
3269
3270	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3271	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
3272	typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
3273
3274	FNIEMAIMPLFPUR64FSW iemAImpl_fcom_r80_by_r64;
3275	FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
3276	FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
3277	FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
3278	FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
3279	FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
3280	FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
3281
3282	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
3283	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3284	PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
3285	/** @} */
3286
3287	/** @name FPU operations taking a 80-bit float argument
3288	* @{ */
3289	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3290	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
3291	typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
3292	FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
3293	FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
3294	FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
3295	FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
3296	FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
3297	FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
3298	FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
3299	FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
3300	FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
3301
3302	FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80, iemAImpl_fpatan_r80_by_r80_amd, iemAImpl_fpatan_r80_by_r80_intel;
3303	FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80, iemAImpl_fyl2x_r80_by_r80_amd, iemAImpl_fyl2x_r80_by_r80_intel;
3304	FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80, iemAImpl_fyl2xp1_r80_by_r80_amd, iemAImpl_fyl2xp1_r80_by_r80_intel;
3305
3306	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3307	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
3308	typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
3309	FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
3310	FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
3311
3312	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
3313	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
3314	typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
3315	FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
3316	FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
3317
3318	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
3319	typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
3320	FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
3321	FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
3322	FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80, iemAImpl_f2xm1_r80_amd, iemAImpl_f2xm1_r80_intel;
3323	FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
3324	FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
3325	FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80, iemAImpl_fsin_r80_amd, iemAImpl_fsin_r80_intel;
3326	FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80, iemAImpl_fcos_r80_amd, iemAImpl_fcos_r80_intel;
3327
3328	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
3329	typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
3330	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
3331	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
3332
3333	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
3334	typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
3335	FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
3336	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
3337	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
3338	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
3339	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
3340	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
3341	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
3342
3343	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
3344	PCRTFLOAT80U pr80Val));
3345	typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
3346	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80, iemAImpl_fptan_r80_r80_amd, iemAImpl_fptan_r80_r80_intel;
3347	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
3348	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80, iemAImpl_fsincos_r80_r80_amd, iemAImpl_fsincos_r80_r80_intel;
3349
3350	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
3351	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3352	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
3353
3354	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_d80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTPBCD80U pd80Val));
3355	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_d80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3356	PRTPBCD80U pd80Dst, PCRTFLOAT80U pr80Src));
3357
3358	/** @} */
3359
3360	/** @name FPU operations taking a 16-bit signed integer argument
3361	* @{ */
3362	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3363	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
3364	typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
3365	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI16,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3366	int16_t *pi16Dst, PCRTFLOAT80U pr80Src));
3367	typedef FNIEMAIMPLFPUSTR80TOI16 *PFNIEMAIMPLFPUSTR80TOI16;
3368
3369	FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
3370	FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
3371	FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
3372	FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
3373	FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
3374	FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
3375
3376	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3377	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
3378	typedef FNIEMAIMPLFPUI16FSW *PFNIEMAIMPLFPUI16FSW;
3379	FNIEMAIMPLFPUI16FSW iemAImpl_ficom_r80_by_i16;
3380
3381	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
3382	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fist_r80_to_i16;
3383	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fistt_r80_to_i16, iemAImpl_fistt_r80_to_i16_amd, iemAImpl_fistt_r80_to_i16_intel;
3384	/** @} */
3385
3386	/** @name FPU operations taking a 32-bit signed integer argument
3387	* @{ */
3388	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3389	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
3390	typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
3391	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI32,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3392	int32_t *pi32Dst, PCRTFLOAT80U pr80Src));
3393	typedef FNIEMAIMPLFPUSTR80TOI32 *PFNIEMAIMPLFPUSTR80TOI32;
3394
3395	FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
3396	FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
3397	FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
3398	FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
3399	FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
3400	FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
3401
3402	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3403	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
3404	typedef FNIEMAIMPLFPUI32FSW *PFNIEMAIMPLFPUI32FSW;
3405	FNIEMAIMPLFPUI32FSW iemAImpl_ficom_r80_by_i32;
3406
3407	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
3408	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fist_r80_to_i32;
3409	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fistt_r80_to_i32;
3410	/** @} */
3411
3412	/** @name FPU operations taking a 64-bit signed integer argument
3413	* @{ */
3414	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI64,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3415	int64_t *pi64Dst, PCRTFLOAT80U pr80Src));
3416	typedef FNIEMAIMPLFPUSTR80TOI64 *PFNIEMAIMPLFPUSTR80TOI64;
3417
3418	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
3419	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fist_r80_to_i64;
3420	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fistt_r80_to_i64;
3421	/** @} */
3422
3423
3424	/** Temporary type representing a 256-bit vector register. */
3425	typedef struct { uint64_t au64[4]; } IEMVMM256;
3426	/** Temporary type pointing to a 256-bit vector register. */
3427	typedef IEMVMM256 *PIEMVMM256;
3428	/** Temporary type pointing to a const 256-bit vector register. */
3429	typedef IEMVMM256 *PCIEMVMM256;
3430
3431
3432	/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
3433	* @{ */
3434	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t puDst, uint64_t const puSrc));
3435	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
3436	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U128,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
3437	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
3438	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF3U128,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
3439	typedef FNIEMAIMPLMEDIAF3U128 *PFNIEMAIMPLMEDIAF3U128;
3440	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF3U256,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86YMMREG puSrc1, PCX86YMMREG puSrc2));
3441	typedef FNIEMAIMPLMEDIAF3U256 *PFNIEMAIMPLMEDIAF3U256;
3442	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U64,(uint64_t puDst, uint64_t const puSrc));
3443	typedef FNIEMAIMPLMEDIAOPTF2U64 *PFNIEMAIMPLMEDIAOPTF2U64;
3444	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128,(PRTUINT128U puDst, PCRTUINT128U puSrc));
3445	typedef FNIEMAIMPLMEDIAOPTF2U128 *PFNIEMAIMPLMEDIAOPTF2U128;
3446	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
3447	typedef FNIEMAIMPLMEDIAOPTF3U128 *PFNIEMAIMPLMEDIAOPTF3U128;
3448	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
3449	typedef FNIEMAIMPLMEDIAOPTF3U256 *PFNIEMAIMPLMEDIAOPTF3U256;
3450	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256,(PRTUINT256U puDst, PCRTUINT256U puSrc));
3451	typedef FNIEMAIMPLMEDIAOPTF2U256 *PFNIEMAIMPLMEDIAOPTF2U256;
3452	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pshufb_u64, iemAImpl_pshufb_u64_fallback;
3453	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pand_u64, iemAImpl_pandn_u64, iemAImpl_por_u64, iemAImpl_pxor_u64;
3454	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
3455	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pcmpgtb_u64, iemAImpl_pcmpgtw_u64, iemAImpl_pcmpgtd_u64;
3456	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddb_u64, iemAImpl_paddsb_u64, iemAImpl_paddusb_u64;
3457	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddw_u64, iemAImpl_paddsw_u64, iemAImpl_paddusw_u64;
3458	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddd_u64;
3459	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddq_u64;
3460	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubb_u64, iemAImpl_psubsb_u64, iemAImpl_psubusb_u64;
3461	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubw_u64, iemAImpl_psubsw_u64, iemAImpl_psubusw_u64;
3462	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubd_u64;
3463	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubq_u64;
3464	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmaddwd_u64, iemAImpl_pmaddwd_u64_fallback;
3465	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmullw_u64, iemAImpl_pmulhw_u64;
3466	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pminub_u64, iemAImpl_pmaxub_u64;
3467	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pminsw_u64, iemAImpl_pmaxsw_u64;
3468	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pabsb_u64, iemAImpl_pabsb_u64_fallback;
3469	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pabsw_u64, iemAImpl_pabsw_u64_fallback;
3470	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pabsd_u64, iemAImpl_pabsd_u64_fallback;
3471	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psignb_u64, iemAImpl_psignb_u64_fallback;
3472	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psignw_u64, iemAImpl_psignw_u64_fallback;
3473	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psignd_u64, iemAImpl_psignd_u64_fallback;
3474	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phaddw_u64, iemAImpl_phaddw_u64_fallback;
3475	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phaddd_u64, iemAImpl_phaddd_u64_fallback;
3476	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phsubw_u64, iemAImpl_phsubw_u64_fallback;
3477	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phsubd_u64, iemAImpl_phsubd_u64_fallback;
3478	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phaddsw_u64, iemAImpl_phaddsw_u64_fallback;
3479	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phsubsw_u64, iemAImpl_phsubsw_u64_fallback;
3480	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmaddubsw_u64, iemAImpl_pmaddubsw_u64_fallback;
3481	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhrsw_u64, iemAImpl_pmulhrsw_u64_fallback;
3482	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmuludq_u64;
3483	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllw_u64, iemAImpl_psrlw_u64, iemAImpl_psraw_u64;
3484	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pslld_u64, iemAImpl_psrld_u64, iemAImpl_psrad_u64;
3485	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllq_u64, iemAImpl_psrlq_u64;
3486	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packsswb_u64, iemAImpl_packuswb_u64;
3487	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packssdw_u64;
3488	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhuw_u64;
3489	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pavgb_u64, iemAImpl_pavgw_u64;
3490	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psadbw_u64;
3491
3492	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pshufb_u128, iemAImpl_pshufb_u128_fallback;
3493	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pand_u128, iemAImpl_pandn_u128, iemAImpl_por_u128, iemAImpl_pxor_u128;
3494	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
3495	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpeqq_u128, iemAImpl_pcmpeqq_u128_fallback;
3496	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpgtb_u128, iemAImpl_pcmpgtw_u128, iemAImpl_pcmpgtd_u128;
3497	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpgtq_u128, iemAImpl_pcmpgtq_u128_fallback;
3498	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddb_u128, iemAImpl_paddsb_u128, iemAImpl_paddusb_u128;
3499	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddw_u128, iemAImpl_paddsw_u128, iemAImpl_paddusw_u128;
3500	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddd_u128;
3501	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddq_u128;
3502	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubb_u128, iemAImpl_psubsb_u128, iemAImpl_psubusb_u128;
3503	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubw_u128, iemAImpl_psubsw_u128, iemAImpl_psubusw_u128;
3504	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubd_u128;
3505	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubq_u128;
3506	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmullw_u128, iemAImpl_pmullw_u128_fallback;
3507	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhw_u128;
3508	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulld_u128, iemAImpl_pmulld_u128_fallback;
3509	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaddwd_u128, iemAImpl_pmaddwd_u128_fallback;
3510	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminub_u128;
3511	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminud_u128, iemAImpl_pminud_u128_fallback;
3512	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminuw_u128, iemAImpl_pminuw_u128_fallback;
3513	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminsb_u128, iemAImpl_pminsb_u128_fallback;
3514	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminsd_u128, iemAImpl_pminsd_u128_fallback;
3515	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminsw_u128, iemAImpl_pminsw_u128_fallback;
3516	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxub_u128;
3517	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxud_u128, iemAImpl_pmaxud_u128_fallback;
3518	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxuw_u128, iemAImpl_pmaxuw_u128_fallback;
3519	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxsb_u128, iemAImpl_pmaxsb_u128_fallback;
3520	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxsw_u128;
3521	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxsd_u128, iemAImpl_pmaxsd_u128_fallback;
3522	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pabsb_u128, iemAImpl_pabsb_u128_fallback;
3523	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pabsw_u128, iemAImpl_pabsw_u128_fallback;
3524	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pabsd_u128, iemAImpl_pabsd_u128_fallback;
3525	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psignb_u128, iemAImpl_psignb_u128_fallback;
3526	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psignw_u128, iemAImpl_psignw_u128_fallback;
3527	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psignd_u128, iemAImpl_psignd_u128_fallback;
3528	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phaddw_u128, iemAImpl_phaddw_u128_fallback;
3529	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phaddd_u128, iemAImpl_phaddd_u128_fallback;
3530	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phsubw_u128, iemAImpl_phsubw_u128_fallback;
3531	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phsubd_u128, iemAImpl_phsubd_u128_fallback;
3532	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phaddsw_u128, iemAImpl_phaddsw_u128_fallback;
3533	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phsubsw_u128, iemAImpl_phsubsw_u128_fallback;
3534	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaddubsw_u128, iemAImpl_pmaddubsw_u128_fallback;
3535	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhrsw_u128, iemAImpl_pmulhrsw_u128_fallback;
3536	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuludq_u128;
3537	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaddwd_u128, iemAImpl_pmaddwd_u128_fallback;
3538	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packsswb_u128, iemAImpl_packuswb_u128;
3539	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packssdw_u128, iemAImpl_packusdw_u128;
3540	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllw_u128, iemAImpl_psrlw_u128, iemAImpl_psraw_u128;
3541	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pslld_u128, iemAImpl_psrld_u128, iemAImpl_psrad_u128;
3542	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllq_u128, iemAImpl_psrlq_u128;
3543	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhuw_u128;
3544	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pavgb_u128, iemAImpl_pavgw_u128;
3545	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psadbw_u128;
3546	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuldq_u128, iemAImpl_pmuldq_u128_fallback;
3547	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpcklps_u128, iemAImpl_unpcklpd_u128;
3548	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpckhps_u128, iemAImpl_unpckhpd_u128;
3549	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phminposuw_u128, iemAImpl_phminposuw_u128_fallback;
3550
3551	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpshufb_u128, iemAImpl_vpshufb_u128_fallback;
3552	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpand_u128, iemAImpl_vpand_u128_fallback;
3553	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpandn_u128, iemAImpl_vpandn_u128_fallback;
3554	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpor_u128, iemAImpl_vpor_u128_fallback;
3555	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpxor_u128, iemAImpl_vpxor_u128_fallback;
3556	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqb_u128, iemAImpl_vpcmpeqb_u128_fallback;
3557	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqw_u128, iemAImpl_vpcmpeqw_u128_fallback;
3558	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqd_u128, iemAImpl_vpcmpeqd_u128_fallback;
3559	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqq_u128, iemAImpl_vpcmpeqq_u128_fallback;
3560	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtb_u128, iemAImpl_vpcmpgtb_u128_fallback;
3561	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtw_u128, iemAImpl_vpcmpgtw_u128_fallback;
3562	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtd_u128, iemAImpl_vpcmpgtd_u128_fallback;
3563	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtq_u128, iemAImpl_vpcmpgtq_u128_fallback;
3564	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddb_u128, iemAImpl_vpaddb_u128_fallback;
3565	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddw_u128, iemAImpl_vpaddw_u128_fallback;
3566	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddd_u128, iemAImpl_vpaddd_u128_fallback;
3567	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddq_u128, iemAImpl_vpaddq_u128_fallback;
3568	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubb_u128, iemAImpl_vpsubb_u128_fallback;
3569	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubw_u128, iemAImpl_vpsubw_u128_fallback;
3570	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubd_u128, iemAImpl_vpsubd_u128_fallback;
3571	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubq_u128, iemAImpl_vpsubq_u128_fallback;
3572	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminub_u128, iemAImpl_vpminub_u128_fallback;
3573	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminuw_u128, iemAImpl_vpminuw_u128_fallback;
3574	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminud_u128, iemAImpl_vpminud_u128_fallback;
3575	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminsb_u128, iemAImpl_vpminsb_u128_fallback;
3576	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminsw_u128, iemAImpl_vpminsw_u128_fallback;
3577	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminsd_u128, iemAImpl_vpminsd_u128_fallback;
3578	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxub_u128, iemAImpl_vpmaxub_u128_fallback;
3579	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxuw_u128, iemAImpl_vpmaxuw_u128_fallback;
3580	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxud_u128, iemAImpl_vpmaxud_u128_fallback;
3581	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxsb_u128, iemAImpl_vpmaxsb_u128_fallback;
3582	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxsw_u128, iemAImpl_vpmaxsw_u128_fallback;
3583	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxsd_u128, iemAImpl_vpmaxsd_u128_fallback;
3584	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpacksswb_u128, iemAImpl_vpacksswb_u128_fallback;
3585	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackssdw_u128, iemAImpl_vpackssdw_u128_fallback;
3586	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackuswb_u128, iemAImpl_vpackuswb_u128_fallback;
3587	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackusdw_u128, iemAImpl_vpackusdw_u128_fallback;
3588	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmullw_u128, iemAImpl_vpmullw_u128_fallback;
3589	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulld_u128, iemAImpl_vpmulld_u128_fallback;
3590	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhw_u128, iemAImpl_vpmulhw_u128_fallback;
3591	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhuw_u128, iemAImpl_vpmulhuw_u128_fallback;
3592	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgb_u128, iemAImpl_vpavgb_u128_fallback;
3593	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgw_u128, iemAImpl_vpavgw_u128_fallback;
3594	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignb_u128, iemAImpl_vpsignb_u128_fallback;
3595	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignw_u128, iemAImpl_vpsignw_u128_fallback;
3596	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignd_u128, iemAImpl_vpsignd_u128_fallback;
3597	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddw_u128, iemAImpl_vphaddw_u128_fallback;
3598	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddd_u128, iemAImpl_vphaddd_u128_fallback;
3599	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubw_u128, iemAImpl_vphsubw_u128_fallback;
3600	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubd_u128, iemAImpl_vphsubd_u128_fallback;
3601	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddsw_u128, iemAImpl_vphaddsw_u128_fallback;
3602	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubsw_u128, iemAImpl_vphsubsw_u128_fallback;
3603	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddubsw_u128, iemAImpl_vpmaddubsw_u128_fallback;
3604	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhrsw_u128, iemAImpl_vpmulhrsw_u128_fallback;
3605	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsadbw_u128, iemAImpl_vpsadbw_u128_fallback;
3606	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuldq_u128, iemAImpl_vpmuldq_u128_fallback;
3607	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuludq_u128, iemAImpl_vpmuludq_u128_fallback;
3608	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsb_u128, iemAImpl_vpsubsb_u128_fallback;
3609	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsw_u128, iemAImpl_vpsubsw_u128_fallback;
3610	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusb_u128, iemAImpl_vpsubusb_u128_fallback;
3611	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusw_u128, iemAImpl_vpsubusw_u128_fallback;
3612	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusb_u128, iemAImpl_vpaddusb_u128_fallback;
3613	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusw_u128, iemAImpl_vpaddusw_u128_fallback;
3614	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsb_u128, iemAImpl_vpaddsb_u128_fallback;
3615	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsw_u128, iemAImpl_vpaddsw_u128_fallback;
3616	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllw_u128, iemAImpl_vpsllw_u128_fallback;
3617	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpslld_u128, iemAImpl_vpslld_u128_fallback;
3618	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllq_u128, iemAImpl_vpsllq_u128_fallback;
3619	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsraw_u128, iemAImpl_vpsraw_u128_fallback;
3620	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrad_u128, iemAImpl_vpsrad_u128_fallback;
3621	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlw_u128, iemAImpl_vpsrlw_u128_fallback;
3622	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrld_u128, iemAImpl_vpsrld_u128_fallback;
3623	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlq_u128, iemAImpl_vpsrlq_u128_fallback;
3624	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddwd_u128, iemAImpl_vpmaddwd_u128_fallback;
3625
3626	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsb_u128, iemAImpl_vpabsb_u128_fallback;
3627	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsw_u128, iemAImpl_vpabsd_u128_fallback;
3628	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsd_u128, iemAImpl_vpabsw_u128_fallback;
3629	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vphminposuw_u128, iemAImpl_vphminposuw_u128_fallback;
3630
3631	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpshufb_u256, iemAImpl_vpshufb_u256_fallback;
3632	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpand_u256, iemAImpl_vpand_u256_fallback;
3633	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpandn_u256, iemAImpl_vpandn_u256_fallback;
3634	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpor_u256, iemAImpl_vpor_u256_fallback;
3635	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpxor_u256, iemAImpl_vpxor_u256_fallback;
3636	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqb_u256, iemAImpl_vpcmpeqb_u256_fallback;
3637	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqw_u256, iemAImpl_vpcmpeqw_u256_fallback;
3638	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqd_u256, iemAImpl_vpcmpeqd_u256_fallback;
3639	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqq_u256, iemAImpl_vpcmpeqq_u256_fallback;
3640	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtb_u256, iemAImpl_vpcmpgtb_u256_fallback;
3641	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtw_u256, iemAImpl_vpcmpgtw_u256_fallback;
3642	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtd_u256, iemAImpl_vpcmpgtd_u256_fallback;
3643	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtq_u256, iemAImpl_vpcmpgtq_u256_fallback;
3644	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddb_u256, iemAImpl_vpaddb_u256_fallback;
3645	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddw_u256, iemAImpl_vpaddw_u256_fallback;
3646	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddd_u256, iemAImpl_vpaddd_u256_fallback;
3647	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddq_u256, iemAImpl_vpaddq_u256_fallback;
3648	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubb_u256, iemAImpl_vpsubb_u256_fallback;
3649	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubw_u256, iemAImpl_vpsubw_u256_fallback;
3650	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubd_u256, iemAImpl_vpsubd_u256_fallback;
3651	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubq_u256, iemAImpl_vpsubq_u256_fallback;
3652	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminub_u256, iemAImpl_vpminub_u256_fallback;
3653	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminuw_u256, iemAImpl_vpminuw_u256_fallback;
3654	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminud_u256, iemAImpl_vpminud_u256_fallback;
3655	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminsb_u256, iemAImpl_vpminsb_u256_fallback;
3656	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminsw_u256, iemAImpl_vpminsw_u256_fallback;
3657	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminsd_u256, iemAImpl_vpminsd_u256_fallback;
3658	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxub_u256, iemAImpl_vpmaxub_u256_fallback;
3659	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxuw_u256, iemAImpl_vpmaxuw_u256_fallback;
3660	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxud_u256, iemAImpl_vpmaxud_u256_fallback;
3661	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxsb_u256, iemAImpl_vpmaxsb_u256_fallback;
3662	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxsw_u256, iemAImpl_vpmaxsw_u256_fallback;
3663	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxsd_u256, iemAImpl_vpmaxsd_u256_fallback;
3664	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpacksswb_u256, iemAImpl_vpacksswb_u256_fallback;
3665	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackssdw_u256, iemAImpl_vpackssdw_u256_fallback;
3666	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackuswb_u256, iemAImpl_vpackuswb_u256_fallback;
3667	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackusdw_u256, iemAImpl_vpackusdw_u256_fallback;
3668	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmullw_u256, iemAImpl_vpmullw_u256_fallback;
3669	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulld_u256, iemAImpl_vpmulld_u256_fallback;
3670	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhw_u256, iemAImpl_vpmulhw_u256_fallback;
3671	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhuw_u256, iemAImpl_vpmulhuw_u256_fallback;
3672	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgb_u256, iemAImpl_vpavgb_u256_fallback;
3673	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgw_u256, iemAImpl_vpavgw_u256_fallback;
3674	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignb_u256, iemAImpl_vpsignb_u256_fallback;
3675	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignw_u256, iemAImpl_vpsignw_u256_fallback;
3676	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignd_u256, iemAImpl_vpsignd_u256_fallback;
3677	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddw_u256, iemAImpl_vphaddw_u256_fallback;
3678	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddd_u256, iemAImpl_vphaddd_u256_fallback;
3679	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubw_u256, iemAImpl_vphsubw_u256_fallback;
3680	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubd_u256, iemAImpl_vphsubd_u256_fallback;
3681	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddsw_u256, iemAImpl_vphaddsw_u256_fallback;
3682	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubsw_u256, iemAImpl_vphsubsw_u256_fallback;
3683	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddubsw_u256, iemAImpl_vpmaddubsw_u256_fallback;
3684	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhrsw_u256, iemAImpl_vpmulhrsw_u256_fallback;
3685	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsadbw_u256, iemAImpl_vpsadbw_u256_fallback;
3686	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuldq_u256, iemAImpl_vpmuldq_u256_fallback;
3687	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuludq_u256, iemAImpl_vpmuludq_u256_fallback;
3688	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsb_u256, iemAImpl_vpsubsb_u256_fallback;
3689	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsw_u256, iemAImpl_vpsubsw_u256_fallback;
3690	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusb_u256, iemAImpl_vpsubusb_u256_fallback;
3691	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusw_u256, iemAImpl_vpsubusw_u256_fallback;
3692	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusb_u256, iemAImpl_vpaddusb_u256_fallback;
3693	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusw_u256, iemAImpl_vpaddusw_u256_fallback;
3694	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsb_u256, iemAImpl_vpaddsb_u256_fallback;
3695	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsw_u256, iemAImpl_vpaddsw_u256_fallback;
3696	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllw_u256, iemAImpl_vpsllw_u256_fallback;
3697	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpslld_u256, iemAImpl_vpslld_u256_fallback;
3698	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllq_u256, iemAImpl_vpsllq_u256_fallback;
3699	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsraw_u256, iemAImpl_vpsraw_u256_fallback;
3700	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrad_u256, iemAImpl_vpsrad_u256_fallback;
3701	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlw_u256, iemAImpl_vpsrlw_u256_fallback;
3702	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrld_u256, iemAImpl_vpsrld_u256_fallback;
3703	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlq_u256, iemAImpl_vpsrlq_u256_fallback;
3704	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddwd_u256, iemAImpl_vpmaddwd_u256_fallback;
3705
3706	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsb_u256, iemAImpl_vpabsb_u256_fallback;
3707	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsw_u256, iemAImpl_vpabsw_u256_fallback;
3708	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsd_u256, iemAImpl_vpabsd_u256_fallback;
3709	/** @} */
3710
3711	/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
3712	* @{ */
3713	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
3714	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
3715	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpcklbw_u128, iemAImpl_vpunpcklbw_u128_fallback,
3716	iemAImpl_vpunpcklwd_u128, iemAImpl_vpunpcklwd_u128_fallback,
3717	iemAImpl_vpunpckldq_u128, iemAImpl_vpunpckldq_u128_fallback,
3718	iemAImpl_vpunpcklqdq_u128, iemAImpl_vpunpcklqdq_u128_fallback,
3719	iemAImpl_vunpcklps_u128, iemAImpl_vunpcklps_u128_fallback,
3720	iemAImpl_vunpcklpd_u128, iemAImpl_vunpcklpd_u128_fallback,
3721	iemAImpl_vunpckhps_u128, iemAImpl_vunpckhps_u128_fallback,
3722	iemAImpl_vunpckhpd_u128, iemAImpl_vunpckhpd_u128_fallback;
3723
3724	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpcklbw_u256, iemAImpl_vpunpcklbw_u256_fallback,
3725	iemAImpl_vpunpcklwd_u256, iemAImpl_vpunpcklwd_u256_fallback,
3726	iemAImpl_vpunpckldq_u256, iemAImpl_vpunpckldq_u256_fallback,
3727	iemAImpl_vpunpcklqdq_u256, iemAImpl_vpunpcklqdq_u256_fallback,
3728	iemAImpl_vunpcklps_u256, iemAImpl_vunpcklps_u256_fallback,
3729	iemAImpl_vunpcklpd_u256, iemAImpl_vunpcklpd_u256_fallback,
3730	iemAImpl_vunpckhps_u256, iemAImpl_vunpckhps_u256_fallback,
3731	iemAImpl_vunpckhpd_u256, iemAImpl_vunpckhpd_u256_fallback;
3732	/** @} */
3733
3734	/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
3735	* @{ */
3736	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
3737	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
3738	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpckhbw_u128, iemAImpl_vpunpckhbw_u128_fallback,
3739	iemAImpl_vpunpckhwd_u128, iemAImpl_vpunpckhwd_u128_fallback,
3740	iemAImpl_vpunpckhdq_u128, iemAImpl_vpunpckhdq_u128_fallback,
3741	iemAImpl_vpunpckhqdq_u128, iemAImpl_vpunpckhqdq_u128_fallback;
3742	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpckhbw_u256, iemAImpl_vpunpckhbw_u256_fallback,
3743	iemAImpl_vpunpckhwd_u256, iemAImpl_vpunpckhwd_u256_fallback,
3744	iemAImpl_vpunpckhdq_u256, iemAImpl_vpunpckhdq_u256_fallback,
3745	iemAImpl_vpunpckhqdq_u256, iemAImpl_vpunpckhqdq_u256_fallback;
3746	/** @} */
3747
3748	/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
3749	* @{ */
3750	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3751	typedef FNIEMAIMPLMEDIAPSHUFU128 *PFNIEMAIMPLMEDIAPSHUFU128;
3752	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
3753	typedef FNIEMAIMPLMEDIAPSHUFU256 *PFNIEMAIMPLMEDIAPSHUFU256;
3754	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw_u64,(uint64_t puDst, uint64_t const puSrc, uint8_t bEvil));
3755	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_pshufhw_u128, iemAImpl_pshuflw_u128, iemAImpl_pshufd_u128;
3756	#ifndef IEM_WITHOUT_ASSEMBLY
3757	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256, iemAImpl_vpshuflw_u256, iemAImpl_vpshufd_u256;
3758	#endif
3759	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256_fallback, iemAImpl_vpshuflw_u256_fallback, iemAImpl_vpshufd_u256_fallback;
3760	/** @} */
3761
3762	/** @name Media (SSE/MMX/AVX) operation: Shift Immediate Stuff (evil)
3763	* @{ */
3764	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU64,(uint64_t *puDst, uint8_t bShift));
3765	typedef FNIEMAIMPLMEDIAPSHIFTU64 *PFNIEMAIMPLMEDIAPSHIFTU64;
3766	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU128,(PRTUINT128U puDst, uint8_t bShift));
3767	typedef FNIEMAIMPLMEDIAPSHIFTU128 *PFNIEMAIMPLMEDIAPSHIFTU128;
3768	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU256,(PRTUINT256U puDst, uint8_t bShift));
3769	typedef FNIEMAIMPLMEDIAPSHIFTU256 *PFNIEMAIMPLMEDIAPSHIFTU256;
3770	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psllw_imm_u64, iemAImpl_pslld_imm_u64, iemAImpl_psllq_imm_u64;
3771	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psrlw_imm_u64, iemAImpl_psrld_imm_u64, iemAImpl_psrlq_imm_u64;
3772	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psraw_imm_u64, iemAImpl_psrad_imm_u64;
3773	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psllw_imm_u128, iemAImpl_pslld_imm_u128, iemAImpl_psllq_imm_u128;
3774	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psrlw_imm_u128, iemAImpl_psrld_imm_u128, iemAImpl_psrlq_imm_u128;
3775	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psraw_imm_u128, iemAImpl_psrad_imm_u128;
3776	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_pslldq_imm_u128, iemAImpl_psrldq_imm_u128;
3777	/** @} */
3778
3779	/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
3780	* @{ */
3781	IEM_DECL_IMPL_DEF(void, iemAImpl_maskmovq_u64,(uint64_t puMem, uint64_t const puSrc, uint64_t const *puMsk));
3782	IEM_DECL_IMPL_DEF(void, iemAImpl_maskmovdqu_u128,(PRTUINT128U puMem, PCRTUINT128U puSrc, PCRTUINT128U puMsk));
3783	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(uint64_t pu64Dst, uint64_t const puSrc));
3784	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(uint64_t *pu64Dst, PCRTUINT128U puSrc));
3785	#ifndef IEM_WITHOUT_ASSEMBLY
3786	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
3787	#endif
3788	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256_fallback,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
3789	/** @} */
3790
3791	/** @name Media (SSE/MMX/AVX) operations: Variable Blend Packed Bytes/R32/R64.
3792	* @{ */
3793	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puMask));
3794	typedef FNIEMAIMPLBLENDU128 *PFNIEMAIMPLBLENDU128;
3795	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, PCRTUINT128U puMask));
3796	typedef FNIEMAIMPLAVXBLENDU128 *PFNIEMAIMPLAVXBLENDU128;
3797	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, PCRTUINT256U puMask));
3798	typedef FNIEMAIMPLAVXBLENDU256 *PFNIEMAIMPLAVXBLENDU256;
3799
3800	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128;
3801	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128_fallback;
3802	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128;
3803	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128_fallback;
3804	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256;
3805	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256_fallback;
3806
3807	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128;
3808	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128_fallback;
3809	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128;
3810	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128_fallback;
3811	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256;
3812	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256_fallback;
3813
3814	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128;
3815	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128_fallback;
3816	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128;
3817	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128_fallback;
3818	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256;
3819	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256_fallback;
3820	/** @} */
3821
3822
3823	/** @name Media (SSE/MMX/AVX) operation: Sort this later
3824	* @{ */
3825	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3826	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3827	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3828	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3829	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3830
3831	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3832	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3833	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3834	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3835	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3836
3837	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3838	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3839	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
3840	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3841	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3842
3843	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3844	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3845	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3846	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3847	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3848
3849	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3850	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3851	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3852	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3853	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3854
3855	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3856	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3857	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3858	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3859	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3860
3861	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3862	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3863	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3864	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3865	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3866
3867	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3868	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3869	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3870	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3871	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3872
3873	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3874	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3875	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
3876	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3877	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3878
3879	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3880	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3881	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3882	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3883	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3884
3885	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3886	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3887	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3888	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3889	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3890
3891	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3892	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3893	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3894	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3895	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3896
3897	IEM_DECL_IMPL_DEF(void, iemAImpl_shufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3898	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3899	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3900	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3901	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3902
3903	IEM_DECL_IMPL_DEF(void, iemAImpl_shufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3904	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3905	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3906	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3907	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3908
3909	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
3910	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64_fallback,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
3911
3912	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3913	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3914	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3915	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3916	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3917
3918	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3919	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3920	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3921	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3922	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3923
3924
3925	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3926	typedef FNIEMAIMPLMEDIAOPTF2U128IMM8 *PFNIEMAIMPLMEDIAOPTF2U128IMM8;
3927	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
3928	typedef FNIEMAIMPLMEDIAOPTF2U256IMM8 *PFNIEMAIMPLMEDIAOPTF2U256IMM8;
3929	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3930	typedef FNIEMAIMPLMEDIAOPTF3U128IMM8 *PFNIEMAIMPLMEDIAOPTF3U128IMM8;
3931	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3932	typedef FNIEMAIMPLMEDIAOPTF3U256IMM8 *PFNIEMAIMPLMEDIAOPTF3U256IMM8;
3933
3934	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_palignr_u128, iemAImpl_palignr_u128_fallback;
3935	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pblendw_u128, iemAImpl_pblendw_u128_fallback;
3936	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendps_u128, iemAImpl_blendps_u128_fallback;
3937	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendpd_u128, iemAImpl_blendpd_u128_fallback;
3938
3939	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpalignr_u128, iemAImpl_vpalignr_u128_fallback;
3940	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendw_u128, iemAImpl_vpblendw_u128_fallback;
3941	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendd_u128, iemAImpl_vpblendd_u128_fallback;
3942	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendps_u128, iemAImpl_vblendps_u128_fallback;
3943	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendpd_u128, iemAImpl_vblendpd_u128_fallback;
3944
3945	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpalignr_u256, iemAImpl_vpalignr_u256_fallback;
3946	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendw_u256, iemAImpl_vpblendw_u256_fallback;
3947	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendd_u256, iemAImpl_vpblendd_u256_fallback;
3948	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendps_u256, iemAImpl_vblendps_u256_fallback;
3949	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendpd_u256, iemAImpl_vblendpd_u256_fallback;
3950	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2i128_u256, iemAImpl_vperm2i128_u256_fallback;
3951	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2f128_u256, iemAImpl_vperm2f128_u256_fallback;
3952
3953	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesimc_u128, iemAImpl_aesimc_u128_fallback;
3954	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenc_u128, iemAImpl_aesenc_u128_fallback;
3955	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenclast_u128, iemAImpl_aesenclast_u128_fallback;
3956	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdec_u128, iemAImpl_aesdec_u128_fallback;
3957	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdeclast_u128, iemAImpl_aesdeclast_u128_fallback;
3958
3959	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesimc_u128, iemAImpl_vaesimc_u128_fallback;
3960	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenc_u128, iemAImpl_vaesenc_u128_fallback;
3961	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenclast_u128, iemAImpl_vaesenclast_u128_fallback;
3962	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdec_u128, iemAImpl_vaesdec_u128_fallback;
3963	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdeclast_u128, iemAImpl_vaesdeclast_u128_fallback;
3964
3965	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_aeskeygenassist_u128, iemAImpl_aeskeygenassist_u128_fallback;
3966
3967	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vaeskeygenassist_u128, iemAImpl_vaeskeygenassist_u128_fallback;
3968
3969	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1nexte_u128, iemAImpl_sha1nexte_u128_fallback;
3970	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg1_u128, iemAImpl_sha1msg1_u128_fallback;
3971	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg2_u128, iemAImpl_sha1msg2_u128_fallback;
3972	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg1_u128, iemAImpl_sha256msg1_u128_fallback;
3973	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg2_u128, iemAImpl_sha256msg2_u128_fallback;
3974	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_sha1rnds4_u128, iemAImpl_sha1rnds4_u128_fallback;
3975	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
3976	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
3977
3978	typedef struct IEMPCMPISTRXSRC
3979	{
3980	RTUINT128U uSrc1;
3981	RTUINT128U uSrc2;
3982	} IEMPCMPISTRXSRC;
3983	typedef IEMPCMPISTRXSRC *PIEMPCMPISTRXSRC;
3984	typedef const IEMPCMPISTRXSRC *PCIEMPCMPISTRXSRC;
3985
3986	typedef struct IEMPCMPESTRXSRC
3987	{
3988	RTUINT128U uSrc1;
3989	RTUINT128U uSrc2;
3990	uint64_t u64Rax;
3991	uint64_t u64Rdx;
3992	} IEMPCMPESTRXSRC;
3993	typedef IEMPCMPESTRXSRC *PIEMPCMPESTRXSRC;
3994	typedef const IEMPCMPESTRXSRC *PCIEMPCMPESTRXSRC;
3995
3996	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLPCMPISTRIU128IMM8,(uint32_t *pEFlags, PCRTUINT128U pSrc1, PCRTUINT128U pSrc2, uint8_t bEvil));
3997	typedef FNIEMAIMPLPCMPISTRIU128IMM8 *PFNIEMAIMPLPCMPISTRIU128IMM8;
3998	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRIU128IMM8,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
3999	typedef FNIEMAIMPLPCMPESTRIU128IMM8 *PFNIEMAIMPLPCMPESTRIU128IMM8;
4000
4001	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPISTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
4002	typedef FNIEMAIMPLPCMPISTRMU128IMM8 *PFNIEMAIMPLPCMPISTRMU128IMM8;
4003	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
4004	typedef FNIEMAIMPLPCMPESTRMU128IMM8 *PFNIEMAIMPLPCMPESTRMU128IMM8;
4005
4006	FNIEMAIMPLPCMPISTRIU128IMM8 iemAImpl_pcmpistri_u128, iemAImpl_pcmpistri_u128_fallback;
4007	FNIEMAIMPLPCMPESTRIU128IMM8 iemAImpl_pcmpestri_u128, iemAImpl_pcmpestri_u128_fallback;
4008	FNIEMAIMPLPCMPISTRMU128IMM8 iemAImpl_pcmpistrm_u128, iemAImpl_pcmpistrm_u128_fallback;
4009	FNIEMAIMPLPCMPESTRMU128IMM8 iemAImpl_pcmpestrm_u128, iemAImpl_pcmpestrm_u128_fallback;
4010
4011	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pclmulqdq_u128, iemAImpl_pclmulqdq_u128_fallback;
4012	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpclmulqdq_u128, iemAImpl_vpclmulqdq_u128_fallback;
4013
4014	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_mpsadbw_u128, iemAImpl_mpsadbw_u128_fallback;
4015	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vmpsadbw_u128, iemAImpl_vmpsadbw_u128_fallback;
4016	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vmpsadbw_u256, iemAImpl_vmpsadbw_u256_fallback;
4017
4018	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsllw_imm_u128, iemAImpl_vpsllw_imm_u128_fallback;
4019	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsllw_imm_u256, iemAImpl_vpsllw_imm_u256_fallback;
4020	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpslld_imm_u128, iemAImpl_vpslld_imm_u128_fallback;
4021	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpslld_imm_u256, iemAImpl_vpslld_imm_u256_fallback;
4022	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsllq_imm_u128, iemAImpl_vpsllq_imm_u128_fallback;
4023	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsllq_imm_u256, iemAImpl_vpsllq_imm_u256_fallback;
4024	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
4025	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
4026	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
4027	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
4028
4029	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsraw_imm_u128, iemAImpl_vpsraw_imm_u128_fallback;
4030	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsraw_imm_u256, iemAImpl_vpsraw_imm_u256_fallback;
4031	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrad_imm_u128, iemAImpl_vpsrad_imm_u128_fallback;
4032	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrad_imm_u256, iemAImpl_vpsrad_imm_u256_fallback;
4033
4034	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrlw_imm_u128, iemAImpl_vpsrlw_imm_u128_fallback;
4035	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrlw_imm_u256, iemAImpl_vpsrlw_imm_u256_fallback;
4036	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrld_imm_u128, iemAImpl_vpsrld_imm_u128_fallback;
4037	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrld_imm_u256, iemAImpl_vpsrld_imm_u256_fallback;
4038	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrlq_imm_u128, iemAImpl_vpsrlq_imm_u128_fallback;
4039	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrlq_imm_u256, iemAImpl_vpsrlq_imm_u256_fallback;
4040	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
4041	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
4042	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
4043	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
4044
4045	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpermilps_u128, iemAImpl_vpermilps_u128_fallback;
4046	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_vpermilps_imm_u128, iemAImpl_vpermilps_imm_u128_fallback;
4047	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpermilps_u256, iemAImpl_vpermilps_u256_fallback;
4048	FNIEMAIMPLMEDIAOPTF2U256IMM8 iemAImpl_vpermilps_imm_u256, iemAImpl_vpermilps_imm_u256_fallback;
4049
4050	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpermilpd_u128, iemAImpl_vpermilpd_u128_fallback;
4051	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_vpermilpd_imm_u128, iemAImpl_vpermilpd_imm_u128_fallback;
4052	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpermilpd_u256, iemAImpl_vpermilpd_u256_fallback;
4053	FNIEMAIMPLMEDIAOPTF2U256IMM8 iemAImpl_vpermilpd_imm_u256, iemAImpl_vpermilpd_imm_u256_fallback;
4054
4055	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllvd_u128, iemAImpl_vpsllvd_u128_fallback;
4056	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllvd_u256, iemAImpl_vpsllvd_u256_fallback;
4057	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllvq_u128, iemAImpl_vpsllvq_u128_fallback;
4058	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllvq_u256, iemAImpl_vpsllvq_u256_fallback;
4059	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsravd_u128, iemAImpl_vpsravd_u128_fallback;
4060	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsravd_u256, iemAImpl_vpsravd_u256_fallback;
4061	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlvd_u128, iemAImpl_vpsrlvd_u128_fallback;
4062	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlvd_u256, iemAImpl_vpsrlvd_u256_fallback;
4063	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlvq_u128, iemAImpl_vpsrlvq_u128_fallback;
4064	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlvq_u256, iemAImpl_vpsrlvq_u256_fallback;
4065	/** @} */
4066
4067	/** @name Media Odds and Ends
4068	* @{ */
4069	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U8,(uint32_t *puDst, uint8_t uSrc));
4070	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U16,(uint32_t *puDst, uint16_t uSrc));
4071	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U32,(uint32_t *puDst, uint32_t uSrc));
4072	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U64,(uint32_t *puDst, uint64_t uSrc));
4073	FNIEMAIMPLCR32U8 iemAImpl_crc32_u8, iemAImpl_crc32_u8_fallback;
4074	FNIEMAIMPLCR32U16 iemAImpl_crc32_u16, iemAImpl_crc32_u16_fallback;
4075	FNIEMAIMPLCR32U32 iemAImpl_crc32_u32, iemAImpl_crc32_u32_fallback;
4076	FNIEMAIMPLCR32U64 iemAImpl_crc32_u64, iemAImpl_crc32_u64_fallback;
4077
4078	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL128,(PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint32_t *pEFlags));
4079	typedef FNIEMAIMPLF2EFL128 *PFNIEMAIMPLF2EFL128;
4080	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL256,(PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint32_t *pEFlags));
4081	typedef FNIEMAIMPLF2EFL256 *PFNIEMAIMPLF2EFL256;
4082	FNIEMAIMPLF2EFL128 iemAImpl_ptest_u128;
4083	FNIEMAIMPLF2EFL256 iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback;
4084	FNIEMAIMPLF2EFL128 iemAImpl_vtestps_u128, iemAImpl_vtestps_u128_fallback;
4085	FNIEMAIMPLF2EFL256 iemAImpl_vtestps_u256, iemAImpl_vtestps_u256_fallback;
4086	FNIEMAIMPLF2EFL128 iemAImpl_vtestpd_u128, iemAImpl_vtestpd_u128_fallback;
4087	FNIEMAIMPLF2EFL256 iemAImpl_vtestpd_u256, iemAImpl_vtestpd_u256_fallback;
4088
4089	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I32U64,(uint32_t uMxCsrIn, int32_t pi32Dst, const uint64_t pu64Src)); /* pu64Src is a double precision floating point. */
4090	typedef FNIEMAIMPLSSEF2I32U64 *PFNIEMAIMPLSSEF2I32U64;
4091	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I64U64,(uint32_t uMxCsrIn, int64_t pi64Dst, const uint64_t pu64Src)); /* pu64Src is a double precision floating point. */
4092	typedef FNIEMAIMPLSSEF2I64U64 *PFNIEMAIMPLSSEF2I64U64;
4093	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I32U32,(uint32_t uMxCsrIn, int32_t pi32Dst, const uint32_t pu32Src)); /* pu32Src is a single precision floating point. */
4094	typedef FNIEMAIMPLSSEF2I32U32 *PFNIEMAIMPLSSEF2I32U32;
4095	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I64U32,(uint32_t uMxCsrIn, int64_t pi64Dst, const uint32_t pu32Src)); /* pu32Src is a single precision floating point. */
4096	typedef FNIEMAIMPLSSEF2I64U32 *PFNIEMAIMPLSSEF2I64U32;
4097
4098	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvttsd2si_i32_r64;
4099	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvtsd2si_i32_r64;
4100
4101	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvttsd2si_i64_r64;
4102	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvtsd2si_i64_r64;
4103
4104	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvttss2si_i32_r32;
4105	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvtss2si_i32_r32;
4106
4107	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvttss2si_i64_r32;
4108	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvtss2si_i64_r32;
4109
4110	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R32I32,(uint32_t uMxCsrIn, PRTFLOAT32U pr32Dst, const int32_t *pi32Src));
4111	typedef FNIEMAIMPLSSEF2R32I32 *PFNIEMAIMPLSSEF2R32I32;
4112	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R32I64,(uint32_t uMxCsrIn, PRTFLOAT32U pr32Dst, const int64_t *pi64Src));
4113	typedef FNIEMAIMPLSSEF2R32I64 *PFNIEMAIMPLSSEF2R32I64;
4114
4115	FNIEMAIMPLSSEF2R32I32 iemAImpl_cvtsi2ss_r32_i32;
4116	FNIEMAIMPLSSEF2R32I64 iemAImpl_cvtsi2ss_r32_i64;
4117
4118	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R64I32,(uint32_t uMxCsrIn, PRTFLOAT64U pr64Dst, const int32_t *pi32Src));
4119	typedef FNIEMAIMPLSSEF2R64I32 *PFNIEMAIMPLSSEF2R64I32;
4120	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R64I64,(uint32_t uMxCsrIn, PRTFLOAT64U pr64Dst, const int64_t *pi64Src));
4121	typedef FNIEMAIMPLSSEF2R64I64 *PFNIEMAIMPLSSEF2R64I64;
4122
4123	FNIEMAIMPLSSEF2R64I32 iemAImpl_cvtsi2sd_r64_i32;
4124	FNIEMAIMPLSSEF2R64I64 iemAImpl_cvtsi2sd_r64_i64;
4125
4126
4127	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLF2EFLMXCSRR32R32,(uint32_t uMxCsrIn, uint32_t *pfEFlags, RTFLOAT32U uSrc1, RTFLOAT32U uSrc2));
4128	typedef FNIEMAIMPLF2EFLMXCSRR32R32 *PFNIEMAIMPLF2EFLMXCSRR32R32;
4129
4130	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLF2EFLMXCSRR64R64,(uint32_t uMxCsrIn, uint32_t *pfEFlags, RTFLOAT64U uSrc1, RTFLOAT64U uSrc2));
4131	typedef FNIEMAIMPLF2EFLMXCSRR64R64 *PFNIEMAIMPLF2EFLMXCSRR64R64;
4132
4133	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_ucomiss_u128;
4134	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback;
4135
4136	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_ucomisd_u128;
4137	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback;
4138
4139	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_comiss_u128;
4140	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback;
4141
4142	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_comisd_u128;
4143	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback;
4144
4145
4146	typedef struct IEMMEDIAF2XMMSRC
4147	{
4148	X86XMMREG uSrc1;
4149	X86XMMREG uSrc2;
4150	} IEMMEDIAF2XMMSRC;
4151	typedef IEMMEDIAF2XMMSRC *PIEMMEDIAF2XMMSRC;
4152	typedef const IEMMEDIAF2XMMSRC *PCIEMMEDIAF2XMMSRC;
4153
4154	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRF2XMMIMM8,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCIEMMEDIAF2XMMSRC puSrc, uint8_t bEvil));
4155	typedef FNIEMAIMPLMXCSRF2XMMIMM8 *PFNIEMAIMPLMXCSRF2XMMIMM8;
4156
4157	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpps_u128;
4158	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmppd_u128;
4159	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpss_u128;
4160	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpsd_u128;
4161	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundss_u128;
4162	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundsd_u128;
4163
4164	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundps_u128, iemAImpl_roundps_u128_fallback;
4165	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundpd_u128, iemAImpl_roundpd_u128_fallback;
4166
4167	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_dpps_u128, iemAImpl_dpps_u128_fallback;
4168	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_dppd_u128, iemAImpl_dppd_u128_fallback;
4169
4170	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRU64U128,(uint32_t fMxCsrIn, uint64_t *pu64Dst, PCX86XMMREG pSrc));
4171	typedef FNIEMAIMPLMXCSRU64U128 *PFNIEMAIMPLMXCSRU64U128;
4172
4173	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvtpd2pi_u128;
4174	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvttpd2pi_u128;
4175
4176	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRU128U64,(uint32_t fMxCsrIn, PX86XMMREG pDst, uint64_t u64Src));
4177	typedef FNIEMAIMPLMXCSRU128U64 *PFNIEMAIMPLMXCSRU128U64;
4178
4179	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2ps_u128;
4180	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2pd_u128;
4181
4182	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRU64U64,(uint32_t fMxCsrIn, uint64_t *pu64Dst, uint64_t u64Src));
4183	typedef FNIEMAIMPLMXCSRU64U64 *PFNIEMAIMPLMXCSRU64U64;
4184
4185	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvtps2pi_u128;
4186	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvttps2pi_u128;
4187
4188	/** @} */
4189
4190
4191	/** @name Function tables.
4192	* @{
4193	*/
4194
4195	/**
4196	* Function table for a binary operator providing implementation based on
4197	* operand size.
4198	*/
4199	typedef struct IEMOPBINSIZES
4200	{
4201	PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
4202	PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
4203	PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
4204	PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
4205	} IEMOPBINSIZES;
4206	/** Pointer to a binary operator function table. */
4207	typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
4208
4209
4210	/**
4211	* Function table for a unary operator providing implementation based on
4212	* operand size.
4213	*/
4214	typedef struct IEMOPUNARYSIZES
4215	{
4216	PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
4217	PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
4218	PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
4219	PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
4220	} IEMOPUNARYSIZES;
4221	/** Pointer to a unary operator function table. */
4222	typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
4223
4224
4225	/**
4226	* Function table for a shift operator providing implementation based on
4227	* operand size.
4228	*/
4229	typedef struct IEMOPSHIFTSIZES
4230	{
4231	PFNIEMAIMPLSHIFTU8 pfnNormalU8;
4232	PFNIEMAIMPLSHIFTU16 pfnNormalU16;
4233	PFNIEMAIMPLSHIFTU32 pfnNormalU32;
4234	PFNIEMAIMPLSHIFTU64 pfnNormalU64;
4235	} IEMOPSHIFTSIZES;
4236	/** Pointer to a shift operator function table. */
4237	typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
4238
4239
4240	/**
4241	* Function table for a multiplication or division operation.
4242	*/
4243	typedef struct IEMOPMULDIVSIZES
4244	{
4245	PFNIEMAIMPLMULDIVU8 pfnU8;
4246	PFNIEMAIMPLMULDIVU16 pfnU16;
4247	PFNIEMAIMPLMULDIVU32 pfnU32;
4248	PFNIEMAIMPLMULDIVU64 pfnU64;
4249	} IEMOPMULDIVSIZES;
4250	/** Pointer to a multiplication or division operation function table. */
4251	typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
4252
4253
4254	/**
4255	* Function table for a double precision shift operator providing implementation
4256	* based on operand size.
4257	*/
4258	typedef struct IEMOPSHIFTDBLSIZES
4259	{
4260	PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
4261	PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
4262	PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
4263	} IEMOPSHIFTDBLSIZES;
4264	/** Pointer to a double precision shift function table. */
4265	typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
4266
4267
4268	/**
4269	* Function table for media instruction taking two full sized media source
4270	* registers and one full sized destination register (AVX).
4271	*/
4272	typedef struct IEMOPMEDIAF3
4273	{
4274	PFNIEMAIMPLMEDIAF3U128 pfnU128;
4275	PFNIEMAIMPLMEDIAF3U256 pfnU256;
4276	} IEMOPMEDIAF3;
4277	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
4278	typedef IEMOPMEDIAF3 const *PCIEMOPMEDIAF3;
4279
4280	/** @def IEMOPMEDIAF3_INIT_VARS_EX
4281	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4282	* given functions as initializers. For use in AVX functions where a pair of
4283	* functions are only used once and the function table need not be public. */
4284	#ifndef TST_IEM_CHECK_MC
4285	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4286	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4287	static IEMOPMEDIAF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4288	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4289	# else
4290	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4291	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4292	# endif
4293	#else
4294	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4295	#endif
4296	/** @def IEMOPMEDIAF3_INIT_VARS
4297	* Generate AVX function tables for the @a a_InstrNm instruction.
4298	* @sa IEMOPMEDIAF3_INIT_VARS_EX */
4299	#define IEMOPMEDIAF3_INIT_VARS(a_InstrNm) \
4300	IEMOPMEDIAF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4301	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4302
4303	/**
4304	* Function table for media instruction taking two full sized media source
4305	* registers and one full sized destination register, but no additional state
4306	* (AVX).
4307	*/
4308	typedef struct IEMOPMEDIAOPTF3
4309	{
4310	PFNIEMAIMPLMEDIAOPTF3U128 pfnU128;
4311	PFNIEMAIMPLMEDIAOPTF3U256 pfnU256;
4312	} IEMOPMEDIAOPTF3;
4313	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
4314	typedef IEMOPMEDIAOPTF3 const *PCIEMOPMEDIAOPTF3;
4315
4316	/** @def IEMOPMEDIAOPTF3_INIT_VARS_EX
4317	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4318	* given functions as initializers. For use in AVX functions where a pair of
4319	* functions are only used once and the function table need not be public. */
4320	#ifndef TST_IEM_CHECK_MC
4321	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4322	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4323	static IEMOPMEDIAOPTF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4324	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4325	# else
4326	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4327	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4328	# endif
4329	#else
4330	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4331	#endif
4332	/** @def IEMOPMEDIAOPTF3_INIT_VARS
4333	* Generate AVX function tables for the @a a_InstrNm instruction.
4334	* @sa IEMOPMEDIAOPTF3_INIT_VARS_EX */
4335	#define IEMOPMEDIAOPTF3_INIT_VARS(a_InstrNm) \
4336	IEMOPMEDIAOPTF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4337	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4338
4339	/**
4340	* Function table for media instruction taking one full sized media source
4341	* registers and one full sized destination register, but no additional state
4342	* (AVX).
4343	*/
4344	typedef struct IEMOPMEDIAOPTF2
4345	{
4346	PFNIEMAIMPLMEDIAOPTF2U128 pfnU128;
4347	PFNIEMAIMPLMEDIAOPTF2U256 pfnU256;
4348	} IEMOPMEDIAOPTF2;
4349	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
4350	typedef IEMOPMEDIAOPTF2 const *PCIEMOPMEDIAOPTF2;
4351
4352	/** @def IEMOPMEDIAOPTF2_INIT_VARS_EX
4353	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4354	* given functions as initializers. For use in AVX functions where a pair of
4355	* functions are only used once and the function table need not be public. */
4356	#ifndef TST_IEM_CHECK_MC
4357	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4358	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4359	static IEMOPMEDIAOPTF2 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4360	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4361	# else
4362	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4363	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4364	# endif
4365	#else
4366	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4367	#endif
4368	/** @def IEMOPMEDIAOPTF2_INIT_VARS
4369	* Generate AVX function tables for the @a a_InstrNm instruction.
4370	* @sa IEMOPMEDIAOPTF2_INIT_VARS_EX */
4371	#define IEMOPMEDIAOPTF2_INIT_VARS(a_InstrNm) \
4372	IEMOPMEDIAOPTF2_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4373	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4374
4375	/**
4376	* Function table for media instruction taking one full sized media source
4377	* register and one full sized destination register and an 8-bit immediate, but no additional state
4378	* (AVX).
4379	*/
4380	typedef struct IEMOPMEDIAOPTF2IMM8
4381	{
4382	PFNIEMAIMPLMEDIAOPTF2U128IMM8 pfnU128;
4383	PFNIEMAIMPLMEDIAOPTF2U256IMM8 pfnU256;
4384	} IEMOPMEDIAOPTF2IMM8;
4385	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
4386	typedef IEMOPMEDIAOPTF2IMM8 const *PCIEMOPMEDIAOPTF2IMM8;
4387
4388	/** @def IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX
4389	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4390	* given functions as initializers. For use in AVX functions where a pair of
4391	* functions are only used once and the function table need not be public. */
4392	#ifndef TST_IEM_CHECK_MC
4393	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4394	# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4395	static IEMOPMEDIAOPTF2IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4396	static IEMOPMEDIAOPTF2IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4397	# else
4398	# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4399	static IEMOPMEDIAOPTF2IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4400	# endif
4401	#else
4402	# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4403	#endif
4404	/** @def IEMOPMEDIAOPTF2IMM8_INIT_VARS
4405	* Generate AVX function tables for the @a a_InstrNm instruction.
4406	* @sa IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX */
4407	#define IEMOPMEDIAOPTF2IMM8_INIT_VARS(a_InstrNm) \
4408	IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u256),\
4409	RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u256_fallback))
4410
4411	/**
4412	* Function table for media instruction taking two full sized media source
4413	* registers and one full sized destination register and an 8-bit immediate, but no additional state
4414	* (AVX).
4415	*/
4416	typedef struct IEMOPMEDIAOPTF3IMM8
4417	{
4418	PFNIEMAIMPLMEDIAOPTF3U128IMM8 pfnU128;
4419	PFNIEMAIMPLMEDIAOPTF3U256IMM8 pfnU256;
4420	} IEMOPMEDIAOPTF3IMM8;
4421	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
4422	typedef IEMOPMEDIAOPTF3IMM8 const *PCIEMOPMEDIAOPTF3IMM8;
4423
4424	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX
4425	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4426	* given functions as initializers. For use in AVX functions where a pair of
4427	* functions are only used once and the function table need not be public. */
4428	#ifndef TST_IEM_CHECK_MC
4429	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4430	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4431	static IEMOPMEDIAOPTF3IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4432	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4433	# else
4434	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4435	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4436	# endif
4437	#else
4438	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4439	#endif
4440	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS
4441	* Generate AVX function tables for the @a a_InstrNm instruction.
4442	* @sa IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX */
4443	#define IEMOPMEDIAOPTF3IMM8_INIT_VARS(a_InstrNm) \
4444	IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4445	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4446	/** @} */
4447
4448
4449	/**
4450	* Function table for blend type instruction taking three full sized media source
4451	* registers and one full sized destination register, but no additional state
4452	* (AVX).
4453	*/
4454	typedef struct IEMOPBLENDOP
4455	{
4456	PFNIEMAIMPLAVXBLENDU128 pfnU128;
4457	PFNIEMAIMPLAVXBLENDU256 pfnU256;
4458	} IEMOPBLENDOP;
4459	/** Pointer to a media operation function table for 4 full sized ops (AVX). */
4460	typedef IEMOPBLENDOP const *PCIEMOPBLENDOP;
4461
4462	/** @def IEMOPBLENDOP_INIT_VARS_EX
4463	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4464	* given functions as initializers. For use in AVX functions where a pair of
4465	* functions are only used once and the function table need not be public. */
4466	#ifndef TST_IEM_CHECK_MC
4467	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4468	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4469	static IEMOPBLENDOP const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4470	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4471	# else
4472	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4473	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4474	# endif
4475	#else
4476	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4477	#endif
4478	/** @def IEMOPBLENDOP_INIT_VARS
4479	* Generate AVX function tables for the @a a_InstrNm instruction.
4480	* @sa IEMOPBLENDOP_INIT_VARS_EX */
4481	#define IEMOPBLENDOP_INIT_VARS(a_InstrNm) \
4482	IEMOPBLENDOP_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4483	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4484
4485
4486	/** @name SSE/AVX single/double precision floating point operations.
4487	* @{ */
4488	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
4489	typedef FNIEMAIMPLFPSSEF2U128 *PFNIEMAIMPLFPSSEF2U128;
4490	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128R32,(uint32_t uMxCsrIn, PX86XMMREG Result, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
4491	typedef FNIEMAIMPLFPSSEF2U128R32 *PFNIEMAIMPLFPSSEF2U128R32;
4492	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128R64,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
4493	typedef FNIEMAIMPLFPSSEF2U128R64 *PFNIEMAIMPLFPSSEF2U128R64;
4494
4495	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
4496	typedef FNIEMAIMPLFPAVXF3U128 *PFNIEMAIMPLFPAVXF3U128;
4497	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U128R32,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
4498	typedef FNIEMAIMPLFPAVXF3U128R32 *PFNIEMAIMPLFPAVXF3U128R32;
4499	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U128R64,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
4500	typedef FNIEMAIMPLFPAVXF3U128R64 *PFNIEMAIMPLFPAVXF3U128R64;
4501
4502	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U256,(uint32_t uMxCsrIn, PX86YMMREG pResult, PCX86YMMREG puSrc1, PCX86YMMREG puSrc2));
4503	typedef FNIEMAIMPLFPAVXF3U256 *PFNIEMAIMPLFPAVXF3U256;
4504
4505	FNIEMAIMPLFPSSEF2U128 iemAImpl_addps_u128;
4506	FNIEMAIMPLFPSSEF2U128 iemAImpl_addpd_u128;
4507	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulps_u128;
4508	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulpd_u128;
4509	FNIEMAIMPLFPSSEF2U128 iemAImpl_subps_u128;
4510	FNIEMAIMPLFPSSEF2U128 iemAImpl_subpd_u128;
4511	FNIEMAIMPLFPSSEF2U128 iemAImpl_minps_u128;
4512	FNIEMAIMPLFPSSEF2U128 iemAImpl_minpd_u128;
4513	FNIEMAIMPLFPSSEF2U128 iemAImpl_divps_u128;
4514	FNIEMAIMPLFPSSEF2U128 iemAImpl_divpd_u128;
4515	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxps_u128;
4516	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxpd_u128;
4517	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddps_u128;
4518	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddpd_u128;
4519	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubps_u128;
4520	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubpd_u128;
4521	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtps_u128;
4522	FNIEMAIMPLFPSSEF2U128 iemAImpl_rsqrtps_u128;
4523	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtpd_u128;
4524	FNIEMAIMPLFPSSEF2U128 iemAImpl_rcpps_u128;
4525	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubps_u128;
4526	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubpd_u128;
4527
4528	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2ps_u128;
4529	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_cvtps2pd_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, uint64_t const *pu64Src));
4530
4531	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2ps_u128;
4532	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2dq_u128;
4533	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttps2dq_u128;
4534	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttpd2dq_u128;
4535	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2pd_u128;
4536	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2dq_u128;
4537
4538	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_addss_u128_r32;
4539	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_addsd_u128_r64;
4540	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_mulss_u128_r32;
4541	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_mulsd_u128_r64;
4542	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_subss_u128_r32;
4543	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_subsd_u128_r64;
4544	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_minss_u128_r32;
4545	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_minsd_u128_r64;
4546	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_divss_u128_r32;
4547	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_divsd_u128_r64;
4548	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_maxss_u128_r32;
4549	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_maxsd_u128_r64;
4550	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_cvtss2sd_u128_r32;
4551	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_cvtsd2ss_u128_r64;
4552	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_sqrtss_u128_r32;
4553	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_sqrtsd_u128_r64;
4554	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_rsqrtss_u128_r32;
4555	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_rcpss_u128_r32;
4556
4557	FNIEMAIMPLMEDIAF3U128 iemAImpl_vaddps_u128, iemAImpl_vaddps_u128_fallback;
4558	FNIEMAIMPLMEDIAF3U128 iemAImpl_vaddpd_u128, iemAImpl_vaddpd_u128_fallback;
4559	FNIEMAIMPLMEDIAF3U128 iemAImpl_vmulps_u128, iemAImpl_vmulps_u128_fallback;
4560	FNIEMAIMPLMEDIAF3U128 iemAImpl_vmulpd_u128, iemAImpl_vmulpd_u128_fallback;
4561	FNIEMAIMPLMEDIAF3U128 iemAImpl_vsubps_u128, iemAImpl_vsubps_u128_fallback;
4562	FNIEMAIMPLMEDIAF3U128 iemAImpl_vsubpd_u128, iemAImpl_vsubpd_u128_fallback;
4563	FNIEMAIMPLMEDIAF3U128 iemAImpl_vminps_u128, iemAImpl_vminps_u128_fallback;
4564	FNIEMAIMPLMEDIAF3U128 iemAImpl_vminpd_u128, iemAImpl_vminpd_u128_fallback;
4565	FNIEMAIMPLMEDIAF3U128 iemAImpl_vdivps_u128, iemAImpl_vdivps_u128_fallback;
4566	FNIEMAIMPLMEDIAF3U128 iemAImpl_vdivpd_u128, iemAImpl_vdivpd_u128_fallback;
4567	FNIEMAIMPLMEDIAF3U128 iemAImpl_vmaxps_u128, iemAImpl_vmaxps_u128_fallback;
4568	FNIEMAIMPLMEDIAF3U128 iemAImpl_vmaxpd_u128, iemAImpl_vmaxpd_u128_fallback;
4569	FNIEMAIMPLMEDIAF3U128 iemAImpl_vhaddps_u128, iemAImpl_vhaddps_u128_fallback;
4570	FNIEMAIMPLMEDIAF3U128 iemAImpl_vhaddpd_u128, iemAImpl_vhaddpd_u128_fallback;
4571	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubps_u128, iemAImpl_vhsubps_u128_fallback;
4572	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubpd_u128, iemAImpl_vhsubpd_u128_fallback;
4573	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtps_u128, iemAImpl_vsqrtps_u128_fallback;
4574	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtpd_u128, iemAImpl_vsqrtpd_u128_fallback;
4575	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubps_u128, iemAImpl_vaddsubps_u128_fallback;
4576	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubpd_u128, iemAImpl_vaddsubpd_u128_fallback;
4577	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtpd2ps_u128, iemAImpl_vcvtpd2ps_u128_fallback;
4578	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtps2pd_u128, iemAImpl_vcvtps2pd_u128_fallback;
4579
4580	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vaddss_u128_r32, iemAImpl_vaddss_u128_r32_fallback;
4581	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vaddsd_u128_r64, iemAImpl_vaddsd_u128_r64_fallback;
4582	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmulss_u128_r32, iemAImpl_vmulss_u128_r32_fallback;
4583	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmulsd_u128_r64, iemAImpl_vmulsd_u128_r64_fallback;
4584	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsubss_u128_r32, iemAImpl_vsubss_u128_r32_fallback;
4585	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsubsd_u128_r64, iemAImpl_vsubsd_u128_r64_fallback;
4586	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vminss_u128_r32, iemAImpl_vminss_u128_r32_fallback;
4587	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vminsd_u128_r64, iemAImpl_vminsd_u128_r64_fallback;
4588	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vdivss_u128_r32, iemAImpl_vdivss_u128_r32_fallback;
4589	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vdivsd_u128_r64, iemAImpl_vdivsd_u128_r64_fallback;
4590	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmaxss_u128_r32, iemAImpl_vmaxss_u128_r32_fallback;
4591	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmaxsd_u128_r64, iemAImpl_vmaxsd_u128_r64_fallback;
4592	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsqrtss_u128_r32, iemAImpl_vsqrtss_u128_r32_fallback;
4593	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsqrtsd_u128_r64, iemAImpl_vsqrtsd_u128_r64_fallback;
4594
4595	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddps_u256, iemAImpl_vaddps_u256_fallback;
4596	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddpd_u256, iemAImpl_vaddpd_u256_fallback;
4597	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulps_u256, iemAImpl_vmulps_u256_fallback;
4598	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulpd_u256, iemAImpl_vmulpd_u256_fallback;
4599	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubps_u256, iemAImpl_vsubps_u256_fallback;
4600	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubpd_u256, iemAImpl_vsubpd_u256_fallback;
4601	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminps_u256, iemAImpl_vminps_u256_fallback;
4602	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminpd_u256, iemAImpl_vminpd_u256_fallback;
4603	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivps_u256, iemAImpl_vdivps_u256_fallback;
4604	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivpd_u256, iemAImpl_vdivpd_u256_fallback;
4605	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxps_u256, iemAImpl_vmaxps_u256_fallback;
4606	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxpd_u256, iemAImpl_vmaxpd_u256_fallback;
4607	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddps_u256, iemAImpl_vhaddps_u256_fallback;
4608	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddpd_u256, iemAImpl_vhaddpd_u256_fallback;
4609	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubps_u256, iemAImpl_vhsubps_u256_fallback;
4610	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubpd_u256, iemAImpl_vhsubpd_u256_fallback;
4611	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubps_u256, iemAImpl_vhaddsubps_u256_fallback;
4612	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubpd_u256, iemAImpl_vhaddsubpd_u256_fallback;
4613	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtpd2ps_u256, iemAImpl_vcvtpd2ps_u256_fallback;
4614	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtps2pd_u256, iemAImpl_vcvtps2pd_u256_fallback;
4615	/** @} */
4616
4617	/** @name C instruction implementations for anything slightly complicated.
4618	* @{ */
4619
4620	/**
4621	* For typedef'ing or declaring a C instruction implementation function taking
4622	* no extra arguments.
4623	*
4624	* @param a_Name The name of the type.
4625	*/
4626	# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
4627	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
4628	/**
4629	* For defining a C instruction implementation function taking no extra
4630	* arguments.
4631	*
4632	* @param a_Name The name of the function
4633	*/
4634	# define IEM_CIMPL_DEF_0(a_Name) \
4635	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
4636	/**
4637	* Prototype version of IEM_CIMPL_DEF_0.
4638	*/
4639	# define IEM_CIMPL_PROTO_0(a_Name) \
4640	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
4641	/**
4642	* For calling a C instruction implementation function taking no extra
4643	* arguments.
4644	*
4645	* This special call macro adds default arguments to the call and allow us to
4646	* change these later.
4647	*
4648	* @param a_fn The name of the function.
4649	*/
4650	# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
4651
4652	/** Type for a C instruction implementation function taking no extra
4653	* arguments. */
4654	typedef IEM_CIMPL_DECL_TYPE_0(FNIEMCIMPL0);
4655	/** Function pointer type for a C instruction implementation function taking
4656	* no extra arguments. */
4657	typedef FNIEMCIMPL0 *PFNIEMCIMPL0;
4658
4659	/**
4660	* For typedef'ing or declaring a C instruction implementation function taking
4661	* one extra argument.
4662	*
4663	* @param a_Name The name of the type.
4664	* @param a_Type0 The argument type.
4665	* @param a_Arg0 The argument name.
4666	*/
4667	# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
4668	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
4669	/**
4670	* For defining a C instruction implementation function taking one extra
4671	* argument.
4672	*
4673	* @param a_Name The name of the function
4674	* @param a_Type0 The argument type.
4675	* @param a_Arg0 The argument name.
4676	*/
4677	# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
4678	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
4679	/**
4680	* Prototype version of IEM_CIMPL_DEF_1.
4681	*/
4682	# define IEM_CIMPL_PROTO_1(a_Name, a_Type0, a_Arg0) \
4683	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
4684	/**
4685	* For calling a C instruction implementation function taking one extra
4686	* argument.
4687	*
4688	* This special call macro adds default arguments to the call and allow us to
4689	* change these later.
4690	*
4691	* @param a_fn The name of the function.
4692	* @param a0 The name of the 1st argument.
4693	*/
4694	# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
4695
4696	/**
4697	* For typedef'ing or declaring a C instruction implementation function taking
4698	* two extra arguments.
4699	*
4700	* @param a_Name The name of the type.
4701	* @param a_Type0 The type of the 1st argument
4702	* @param a_Arg0 The name of the 1st argument.
4703	* @param a_Type1 The type of the 2nd argument.
4704	* @param a_Arg1 The name of the 2nd argument.
4705	*/
4706	# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
4707	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
4708	/**
4709	* For defining a C instruction implementation function taking two extra
4710	* arguments.
4711	*
4712	* @param a_Name The name of the function.
4713	* @param a_Type0 The type of the 1st argument
4714	* @param a_Arg0 The name of the 1st argument.
4715	* @param a_Type1 The type of the 2nd argument.
4716	* @param a_Arg1 The name of the 2nd argument.
4717	*/
4718	# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
4719	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
4720	/**
4721	* Prototype version of IEM_CIMPL_DEF_2.
4722	*/
4723	# define IEM_CIMPL_PROTO_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
4724	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
4725	/**
4726	* For calling a C instruction implementation function taking two extra
4727	* arguments.
4728	*
4729	* This special call macro adds default arguments to the call and allow us to
4730	* change these later.
4731	*
4732	* @param a_fn The name of the function.
4733	* @param a0 The name of the 1st argument.
4734	* @param a1 The name of the 2nd argument.
4735	*/
4736	# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
4737
4738	/**
4739	* For typedef'ing or declaring a C instruction implementation function taking
4740	* three extra arguments.
4741	*
4742	* @param a_Name The name of the type.
4743	* @param a_Type0 The type of the 1st argument
4744	* @param a_Arg0 The name of the 1st argument.
4745	* @param a_Type1 The type of the 2nd argument.
4746	* @param a_Arg1 The name of the 2nd argument.
4747	* @param a_Type2 The type of the 3rd argument.
4748	* @param a_Arg2 The name of the 3rd argument.
4749	*/
4750	# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
4751	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
4752	/**
4753	* For defining a C instruction implementation function taking three extra
4754	* arguments.
4755	*
4756	* @param a_Name The name of the function.
4757	* @param a_Type0 The type of the 1st argument
4758	* @param a_Arg0 The name of the 1st argument.
4759	* @param a_Type1 The type of the 2nd argument.
4760	* @param a_Arg1 The name of the 2nd argument.
4761	* @param a_Type2 The type of the 3rd argument.
4762	* @param a_Arg2 The name of the 3rd argument.
4763	*/
4764	# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
4765	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
4766	/**
4767	* Prototype version of IEM_CIMPL_DEF_3.
4768	*/
4769	# define IEM_CIMPL_PROTO_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
4770	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
4771	/**
4772	* For calling a C instruction implementation function taking three extra
4773	* arguments.
4774	*
4775	* This special call macro adds default arguments to the call and allow us to
4776	* change these later.
4777	*
4778	* @param a_fn The name of the function.
4779	* @param a0 The name of the 1st argument.
4780	* @param a1 The name of the 2nd argument.
4781	* @param a2 The name of the 3rd argument.
4782	*/
4783	# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
4784
4785
4786	/**
4787	* For typedef'ing or declaring a C instruction implementation function taking
4788	* four extra arguments.
4789	*
4790	* @param a_Name The name of the type.
4791	* @param a_Type0 The type of the 1st argument
4792	* @param a_Arg0 The name of the 1st argument.
4793	* @param a_Type1 The type of the 2nd argument.
4794	* @param a_Arg1 The name of the 2nd argument.
4795	* @param a_Type2 The type of the 3rd argument.
4796	* @param a_Arg2 The name of the 3rd argument.
4797	* @param a_Type3 The type of the 4th argument.
4798	* @param a_Arg3 The name of the 4th argument.
4799	*/
4800	# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
4801	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
4802	/**
4803	* For defining a C instruction implementation function taking four extra
4804	* arguments.
4805	*
4806	* @param a_Name The name of the function.
4807	* @param a_Type0 The type of the 1st argument
4808	* @param a_Arg0 The name of the 1st argument.
4809	* @param a_Type1 The type of the 2nd argument.
4810	* @param a_Arg1 The name of the 2nd argument.
4811	* @param a_Type2 The type of the 3rd argument.
4812	* @param a_Arg2 The name of the 3rd argument.
4813	* @param a_Type3 The type of the 4th argument.
4814	* @param a_Arg3 The name of the 4th argument.
4815	*/
4816	# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
4817	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4818	a_Type2 a_Arg2, a_Type3 a_Arg3))
4819	/**
4820	* Prototype version of IEM_CIMPL_DEF_4.
4821	*/
4822	# define IEM_CIMPL_PROTO_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
4823	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4824	a_Type2 a_Arg2, a_Type3 a_Arg3))
4825	/**
4826	* For calling a C instruction implementation function taking four extra
4827	* arguments.
4828	*
4829	* This special call macro adds default arguments to the call and allow us to
4830	* change these later.
4831	*
4832	* @param a_fn The name of the function.
4833	* @param a0 The name of the 1st argument.
4834	* @param a1 The name of the 2nd argument.
4835	* @param a2 The name of the 3rd argument.
4836	* @param a3 The name of the 4th argument.
4837	*/
4838	# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
4839
4840
4841	/**
4842	* For typedef'ing or declaring a C instruction implementation function taking
4843	* five extra arguments.
4844	*
4845	* @param a_Name The name of the type.
4846	* @param a_Type0 The type of the 1st argument
4847	* @param a_Arg0 The name of the 1st argument.
4848	* @param a_Type1 The type of the 2nd argument.
4849	* @param a_Arg1 The name of the 2nd argument.
4850	* @param a_Type2 The type of the 3rd argument.
4851	* @param a_Arg2 The name of the 3rd argument.
4852	* @param a_Type3 The type of the 4th argument.
4853	* @param a_Arg3 The name of the 4th argument.
4854	* @param a_Type4 The type of the 5th argument.
4855	* @param a_Arg4 The name of the 5th argument.
4856	*/
4857	# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
4858	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, \
4859	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
4860	a_Type3 a_Arg3, a_Type4 a_Arg4))
4861	/**
4862	* For defining a C instruction implementation function taking five extra
4863	* arguments.
4864	*
4865	* @param a_Name The name of the function.
4866	* @param a_Type0 The type of the 1st argument
4867	* @param a_Arg0 The name of the 1st argument.
4868	* @param a_Type1 The type of the 2nd argument.
4869	* @param a_Arg1 The name of the 2nd argument.
4870	* @param a_Type2 The type of the 3rd argument.
4871	* @param a_Arg2 The name of the 3rd argument.
4872	* @param a_Type3 The type of the 4th argument.
4873	* @param a_Arg3 The name of the 4th argument.
4874	* @param a_Type4 The type of the 5th argument.
4875	* @param a_Arg4 The name of the 5th argument.
4876	*/
4877	# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
4878	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4879	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
4880	/**
4881	* Prototype version of IEM_CIMPL_DEF_5.
4882	*/
4883	# define IEM_CIMPL_PROTO_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
4884	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4885	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
4886	/**
4887	* For calling a C instruction implementation function taking five extra
4888	* arguments.
4889	*
4890	* This special call macro adds default arguments to the call and allow us to
4891	* change these later.
4892	*
4893	* @param a_fn The name of the function.
4894	* @param a0 The name of the 1st argument.
4895	* @param a1 The name of the 2nd argument.
4896	* @param a2 The name of the 3rd argument.
4897	* @param a3 The name of the 4th argument.
4898	* @param a4 The name of the 5th argument.
4899	*/
4900	# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
4901
4902	/** @} */
4903
4904
4905	/** @name Opcode Decoder Function Types.
4906	* @{ */
4907
4908	/** @typedef PFNIEMOP
4909	* Pointer to an opcode decoder function.
4910	*/
4911
4912	/** @def FNIEMOP_DEF
4913	* Define an opcode decoder function.
4914	*
4915	* We're using macors for this so that adding and removing parameters as well as
4916	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL
4917	*
4918	* @param a_Name The function name.
4919	*/
4920
4921	/** @typedef PFNIEMOPRM
4922	* Pointer to an opcode decoder function with RM byte.
4923	*/
4924
4925	/** @def FNIEMOPRM_DEF
4926	* Define an opcode decoder function with RM byte.
4927	*
4928	* We're using macors for this so that adding and removing parameters as well as
4929	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL_1
4930	*
4931	* @param a_Name The function name.
4932	*/
4933
4934	#if defined(__GNUC__) && defined(RT_ARCH_X86)
4935	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOP)(PVMCPUCC pVCpu);
4936	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4937	# define FNIEMOP_DEF(a_Name) \
4938	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu)
4939	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4940	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
4941	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4942	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
4943
4944	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
4945	typedef VBOXSTRICTRC (__fastcall * PFNIEMOP)(PVMCPUCC pVCpu);
4946	typedef VBOXSTRICTRC (__fastcall * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4947	# define FNIEMOP_DEF(a_Name) \
4948	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
4949	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4950	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
4951	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4952	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
4953
4954	#elif defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
4955	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
4956	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4957	# define FNIEMOP_DEF(a_Name) \
4958	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu)
4959	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4960	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
4961	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4962	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
4963
4964	#else
4965	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
4966	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
4967	# define FNIEMOP_DEF(a_Name) \
4968	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
4969	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
4970	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
4971	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
4972	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
4973
4974	#endif
4975	#define FNIEMOPRM_DEF(a_Name) FNIEMOP_DEF_1(a_Name, uint8_t, bRm)
4976
4977	/**
4978	* Call an opcode decoder function.
4979	*
4980	* We're using macors for this so that adding and removing parameters can be
4981	* done as we please. See FNIEMOP_DEF.
4982	*/
4983	#define FNIEMOP_CALL(a_pfn) (a_pfn)(pVCpu)
4984
4985	/**
4986	* Call a common opcode decoder function taking one extra argument.
4987	*
4988	* We're using macors for this so that adding and removing parameters can be
4989	* done as we please. See FNIEMOP_DEF_1.
4990	*/
4991	#define FNIEMOP_CALL_1(a_pfn, a0) (a_pfn)(pVCpu, a0)
4992
4993	/**
4994	* Call a common opcode decoder function taking one extra argument.
4995	*
4996	* We're using macors for this so that adding and removing parameters can be
4997	* done as we please. See FNIEMOP_DEF_1.
4998	*/
4999	#define FNIEMOP_CALL_2(a_pfn, a0, a1) (a_pfn)(pVCpu, a0, a1)
5000	/** @} */
5001
5002
5003	/** @name Misc Helpers
5004	* @{ */
5005
5006	/** Used to shut up GCC warnings about variables that 'may be used uninitialized'
5007	* due to GCC lacking knowledge about the value range of a switch. */
5008	#if RT_CPLUSPLUS_PREREQ(202000)
5009	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: [[unlikely]] AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
5010	#else
5011	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
5012	#endif
5013
5014	/** Variant of IEM_NOT_REACHED_DEFAULT_CASE_RET that returns a custom value. */
5015	#if RT_CPLUSPLUS_PREREQ(202000)
5016	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: [[unlikely]] AssertFailedReturn(a_RetValue)
5017	#else
5018	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: AssertFailedReturn(a_RetValue)
5019	#endif
5020
5021	/**
5022	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
5023	* occation.
5024	*/
5025	#ifdef LOG_ENABLED
5026	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
5027	do { \
5028	/Log/ LogAlways(("%s: returning IEM_RETURN_ASPECT_NOT_IMPLEMENTED (line %d)\n", __FUNCTION__, __LINE__)); \
5029	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
5030	} while (0)
5031	#else
5032	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
5033	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
5034	#endif
5035
5036	/**
5037	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
5038	* occation using the supplied logger statement.
5039	*
5040	* @param a_LoggerArgs What to log on failure.
5041	*/
5042	#ifdef LOG_ENABLED
5043	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
5044	do { \
5045	LogAlways((LOG_FN_FMT ": ", __PRETTY_FUNCTION__)); LogAlways(a_LoggerArgs); \
5046	/LogFunc(a_LoggerArgs);/ \
5047	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
5048	} while (0)
5049	#else
5050	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
5051	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
5052	#endif
5053
5054	/**
5055	* Gets the CPU mode (from fExec) as a IEMMODE value.
5056	*
5057	* @returns IEMMODE
5058	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5059	*/
5060	#define IEM_GET_CPU_MODE(a_pVCpu) ((a_pVCpu)->iem.s.fExec & IEM_F_MODE_CPUMODE_MASK)
5061
5062	/**
5063	* Check if we're currently executing in real or virtual 8086 mode.
5064	*
5065	* @returns @c true if it is, @c false if not.
5066	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5067	*/
5068	#define IEM_IS_REAL_OR_V86_MODE(a_pVCpu) (( ((a_pVCpu)->iem.s.fExec ^ IEM_F_MODE_X86_PROT_MASK) \
5069	& (IEM_F_MODE_X86_V86_MASK \| IEM_F_MODE_X86_PROT_MASK)) != 0)
5070
5071	/**
5072	* Check if we're currently executing in virtual 8086 mode.
5073	*
5074	* @returns @c true if it is, @c false if not.
5075	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5076	*/
5077	#define IEM_IS_V86_MODE(a_pVCpu) (((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_V86_MASK) != 0)
5078
5079	/**
5080	* Check if we're currently executing in long mode.
5081	*
5082	* @returns @c true if it is, @c false if not.
5083	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5084	*/
5085	#define IEM_IS_LONG_MODE(a_pVCpu) (CPUMIsGuestInLongModeEx(IEM_GET_CTX(a_pVCpu)))
5086
5087	/**
5088	* Check if we're currently executing in a 16-bit code segment.
5089	*
5090	* @returns @c true if it is, @c false if not.
5091	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5092	*/
5093	#define IEM_IS_16BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_16BIT)
5094
5095	/**
5096	* Check if we're currently executing in a 32-bit code segment.
5097	*
5098	* @returns @c true if it is, @c false if not.
5099	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5100	*/
5101	#define IEM_IS_32BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_32BIT)
5102
5103	/**
5104	* Check if we're currently executing in a 64-bit code segment.
5105	*
5106	* @returns @c true if it is, @c false if not.
5107	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5108	*/
5109	#define IEM_IS_64BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_64BIT)
5110
5111	/**
5112	* Check if we're currently executing in real mode.
5113	*
5114	* @returns @c true if it is, @c false if not.
5115	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5116	*/
5117	#define IEM_IS_REAL_MODE(a_pVCpu) (!((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_PROT_MASK))
5118
5119	/**
5120	* Gets the current protection level (CPL).
5121	*
5122	* @returns 0..3
5123	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5124	*/
5125	#define IEM_GET_CPL(a_pVCpu) (((a_pVCpu)->iem.s.fExec >> IEM_F_X86_CPL_SHIFT) & IEM_F_X86_CPL_SMASK)
5126
5127	/**
5128	* Sets the current protection level (CPL).
5129	*
5130	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5131	*/
5132	#define IEM_SET_CPL(a_pVCpu, a_uCpl) \
5133	do { (a_pVCpu)->iem.s.fExec = ((a_pVCpu)->iem.s.fExec & ~IEM_F_X86_CPL_MASK) \| ((a_uCpl) << IEM_F_X86_CPL_SHIFT); } while (0)
5134
5135	/**
5136	* Returns a (const) pointer to the CPUMFEATURES for the guest CPU.
5137	* @returns PCCPUMFEATURES
5138	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5139	*/
5140	#define IEM_GET_GUEST_CPU_FEATURES(a_pVCpu) (&((a_pVCpu)->CTX_SUFF(pVM)->cpum.ro.GuestFeatures))
5141
5142	/**
5143	* Returns a (const) pointer to the CPUMFEATURES for the host CPU.
5144	* @returns PCCPUMFEATURES
5145	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5146	*/
5147	#define IEM_GET_HOST_CPU_FEATURES(a_pVCpu) (&g_CpumHostFeatures.s)
5148
5149	/**
5150	* Evaluates to true if we're presenting an Intel CPU to the guest.
5151	*/
5152	#define IEM_IS_GUEST_CPU_INTEL(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL )
5153
5154	/**
5155	* Evaluates to true if we're presenting an AMD CPU to the guest.
5156	*/
5157	#define IEM_IS_GUEST_CPU_AMD(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_AMD \|\| (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_HYGON )
5158
5159	/**
5160	* Check if the address is canonical.
5161	*/
5162	#define IEM_IS_CANONICAL(a_u64Addr) X86_IS_CANONICAL(a_u64Addr)
5163
5164	/** Checks if the ModR/M byte is in register mode or not. */
5165	#define IEM_IS_MODRM_REG_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT) )
5166	/** Checks if the ModR/M byte is in memory mode or not. */
5167	#define IEM_IS_MODRM_MEM_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT) )
5168
5169	/**
5170	* Gets the register (reg) part of a ModR/M encoding, with REX.R added in.
5171	*
5172	* For use during decoding.
5173	*/
5174	#define IEM_GET_MODRM_REG(a_pVCpu, a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| (a_pVCpu)->iem.s.uRexReg )
5175	/**
5176	* Gets the r/m part of a ModR/M encoding as a register index, with REX.B added in.
5177	*
5178	* For use during decoding.
5179	*/
5180	#define IEM_GET_MODRM_RM(a_pVCpu, a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) \| (a_pVCpu)->iem.s.uRexB )
5181
5182	/**
5183	* Gets the register (reg) part of a ModR/M encoding, without REX.R.
5184	*
5185	* For use during decoding.
5186	*/
5187	#define IEM_GET_MODRM_REG_8(a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) )
5188	/**
5189	* Gets the r/m part of a ModR/M encoding as a register index, without REX.B.
5190	*
5191	* For use during decoding.
5192	*/
5193	#define IEM_GET_MODRM_RM_8(a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) )
5194
5195	/**
5196	* Gets the register (reg) part of a ModR/M encoding as an extended 8-bit
5197	* register index, with REX.R added in.
5198	*
5199	* For use during decoding.
5200	*
5201	* @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
5202	*/
5203	#define IEM_GET_MODRM_REG_EX8(a_pVCpu, a_bRm) \
5204	( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
5205	\|\| !((a_bRm) & (4 << X86_MODRM_REG_SHIFT)) /* IEM_GET_MODRM_REG(pVCpu, a_bRm) < 4 */ \
5206	? IEM_GET_MODRM_REG(pVCpu, a_bRm) : (((a_bRm) >> X86_MODRM_REG_SHIFT) & 3) \| 16)
5207	/**
5208	* Gets the r/m part of a ModR/M encoding as an extended 8-bit register index,
5209	* with REX.B added in.
5210	*
5211	* For use during decoding.
5212	*
5213	* @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
5214	*/
5215	#define IEM_GET_MODRM_RM_EX8(a_pVCpu, a_bRm) \
5216	( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
5217	\|\| !((a_bRm) & 4) /* IEM_GET_MODRM_RM(pVCpu, a_bRm) < 4 */ \
5218	? IEM_GET_MODRM_RM(pVCpu, a_bRm) : ((a_bRm) & 3) \| 16)
5219
5220	/**
5221	* Combines the prefix REX and ModR/M byte for passing to
5222	* iemOpHlpCalcRmEffAddrThreadedAddr64().
5223	*
5224	* @returns The ModRM byte but with bit 3 set to REX.B and bit 4 to REX.X.
5225	* The two bits are part of the REG sub-field, which isn't needed in
5226	* iemOpHlpCalcRmEffAddrThreadedAddr64().
5227	*
5228	* For use during decoding/recompiling.
5229	*/
5230	#define IEM_GET_MODRM_EX(a_pVCpu, a_bRm) \
5231	( ((a_bRm) & ~X86_MODRM_REG_MASK) \
5232	\| (uint8_t)( (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X)) >> (25 - 3) ) )
5233	AssertCompile(IEM_OP_PRF_REX_B == RT_BIT_32(25));
5234	AssertCompile(IEM_OP_PRF_REX_X == RT_BIT_32(26));
5235
5236	/**
5237	* Gets the effective VEX.VVVV value.
5238	*
5239	* The 4th bit is ignored if not 64-bit code.
5240	* @returns effective V-register value.
5241	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5242	*/
5243	#define IEM_GET_EFFECTIVE_VVVV(a_pVCpu) \
5244	(IEM_IS_64BIT_CODE(a_pVCpu) ? (a_pVCpu)->iem.s.uVex3rdReg : (a_pVCpu)->iem.s.uVex3rdReg & 7)
5245
5246
5247	/**
5248	* Gets the register (reg) part of a the special 4th register byte used by
5249	* vblendvps and vblendvpd.
5250	*
5251	* For use during decoding.
5252	*/
5253	#define IEM_GET_IMM8_REG(a_pVCpu, a_bRegImm8) \
5254	(IEM_IS_64BIT_CODE(a_pVCpu) ? (a_bRegImm8) >> 4 : ((a_bRegImm8) >> 4) & 7)
5255
5256
5257	/**
5258	* Checks if we're executing inside an AMD-V or VT-x guest.
5259	*/
5260	#if defined(VBOX_WITH_NESTED_HWVIRT_VMX) \|\| defined(VBOX_WITH_NESTED_HWVIRT_SVM)
5261	# define IEM_IS_IN_GUEST(a_pVCpu) RT_BOOL((a_pVCpu)->iem.s.fExec & IEM_F_X86_CTX_IN_GUEST)
5262	#else
5263	# define IEM_IS_IN_GUEST(a_pVCpu) false
5264	#endif
5265
5266
5267	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5268
5269	/**
5270	* Check if the guest has entered VMX root operation.
5271	*/
5272	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxRootMode(IEM_GET_CTX(a_pVCpu)))
5273
5274	/**
5275	* Check if the guest has entered VMX non-root operation.
5276	*/
5277	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) ( ((a_pVCpu)->iem.s.fExec & (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST)) \
5278	== (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST) )
5279
5280	/**
5281	* Check if the nested-guest has the given Pin-based VM-execution control set.
5282	*/
5283	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_PinCtl) (CPUMIsGuestVmxPinCtlsSet(IEM_GET_CTX(a_pVCpu), (a_PinCtl)))
5284
5285	/**
5286	* Check if the nested-guest has the given Processor-based VM-execution control set.
5287	*/
5288	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_ProcCtl) (CPUMIsGuestVmxProcCtlsSet(IEM_GET_CTX(a_pVCpu), (a_ProcCtl)))
5289
5290	/**
5291	* Check if the nested-guest has the given Secondary Processor-based VM-execution
5292	* control set.
5293	*/
5294	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_ProcCtl2) (CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(a_pVCpu), (a_ProcCtl2)))
5295
5296	/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
5297	# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
5298
5299	/** Whether a shadow VMCS is present for the given VCPU. */
5300	# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
5301
5302	/** Gets the VMXON region pointer. */
5303	# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
5304
5305	/** Gets the guest-physical address of the current VMCS for the given VCPU. */
5306	# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
5307
5308	/** Whether a current VMCS is present for the given VCPU. */
5309	# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
5310
5311	/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
5312	# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
5313	do \
5314	{ \
5315	Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
5316	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
5317	} while (0)
5318
5319	/** Clears any current VMCS for the given VCPU. */
5320	# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
5321	do \
5322	{ \
5323	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
5324	} while (0)
5325
5326	/**
5327	* Invokes the VMX VM-exit handler for an instruction intercept.
5328	*/
5329	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) \
5330	do { return iemVmxVmexitInstr((a_pVCpu), (a_uExitReason), (a_cbInstr)); } while (0)
5331
5332	/**
5333	* Invokes the VMX VM-exit handler for an instruction intercept where the
5334	* instruction provides additional VM-exit information.
5335	*/
5336	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) \
5337	do { return iemVmxVmexitInstrNeedsInfo((a_pVCpu), (a_uExitReason), (a_uInstrId), (a_cbInstr)); } while (0)
5338
5339	/**
5340	* Invokes the VMX VM-exit handler for a task switch.
5341	*/
5342	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) \
5343	do { return iemVmxVmexitTaskSwitch((a_pVCpu), (a_enmTaskSwitch), (a_SelNewTss), (a_cbInstr)); } while (0)
5344
5345	/**
5346	* Invokes the VMX VM-exit handler for MWAIT.
5347	*/
5348	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) \
5349	do { return iemVmxVmexitInstrMwait((a_pVCpu), (a_fMonitorArmed), (a_cbInstr)); } while (0)
5350
5351	/**
5352	* Invokes the VMX VM-exit handler for EPT faults.
5353	*/
5354	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) \
5355	do { return iemVmxVmexitEpt(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr); } while (0)
5356
5357	/**
5358	* Invokes the VMX VM-exit handler.
5359	*/
5360	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) \
5361	do { return iemVmxVmexit((a_pVCpu), (a_uExitReason), (a_uExitQual)); } while (0)
5362
5363	#else
5364	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (false)
5365	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (false)
5366	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_cbInstr) (false)
5367	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_cbInstr) (false)
5368	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_cbInstr) (false)
5369	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5370	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5371	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5372	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5373	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5374	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) do { return VERR_VMX_IPE_1; } while (0)
5375
5376	#endif
5377
5378	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5379	/**
5380	* Checks if we're executing a guest using AMD-V.
5381	*/
5382	# define IEM_SVM_IS_IN_GUEST(a_pVCpu) ( (a_pVCpu->iem.s.fExec & (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST)) \
5383	== (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST))
5384	/**
5385	* Check if an SVM control/instruction intercept is set.
5386	*/
5387	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) \
5388	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmCtrlInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_Intercept)))
5389
5390	/**
5391	* Check if an SVM read CRx intercept is set.
5392	*/
5393	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
5394	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
5395
5396	/**
5397	* Check if an SVM write CRx intercept is set.
5398	*/
5399	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
5400	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
5401
5402	/**
5403	* Check if an SVM read DRx intercept is set.
5404	*/
5405	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
5406	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
5407
5408	/**
5409	* Check if an SVM write DRx intercept is set.
5410	*/
5411	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
5412	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
5413
5414	/**
5415	* Check if an SVM exception intercept is set.
5416	*/
5417	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) \
5418	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmXcptInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uVector)))
5419
5420	/**
5421	* Invokes the SVM \#VMEXIT handler for the nested-guest.
5422	*/
5423	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
5424	do { return iemSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2)); } while (0)
5425
5426	/**
5427	* Invokes the 'MOV CRx' SVM \#VMEXIT handler after constructing the
5428	* corresponding decode assist information.
5429	*/
5430	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) \
5431	do \
5432	{ \
5433	uint64_t uExitInfo1; \
5434	if ( IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmDecodeAssists \
5435	&& (a_enmAccessCrX) == IEMACCESSCRX_MOV_CRX) \
5436	uExitInfo1 = SVM_EXIT1_MOV_CRX_MASK \| ((a_iGReg) & 7); \
5437	else \
5438	uExitInfo1 = 0; \
5439	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, uExitInfo1, 0); \
5440	} while (0)
5441
5442	/** Check and handles SVM nested-guest instruction intercept and updates
5443	* NRIP if needed.
5444	*/
5445	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
5446	do \
5447	{ \
5448	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept)) \
5449	{ \
5450	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
5451	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2); \
5452	} \
5453	} while (0)
5454
5455	/** Checks and handles SVM nested-guest CR0 read intercept. */
5456	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
5457	do \
5458	{ \
5459	if (!IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, 0)) \
5460	{ /* probably likely */ } \
5461	else \
5462	{ \
5463	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
5464	IEM_SVM_VMEXIT_RET(a_pVCpu, SVM_EXIT_READ_CR0, a_uExitInfo1, a_uExitInfo2); \
5465	} \
5466	} while (0)
5467
5468	/**
5469	* Updates the NextRIP (NRI) field in the nested-guest VMCB.
5470	*/
5471	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) \
5472	do { \
5473	if (IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmNextRipSave) \
5474	CPUMGuestSvmUpdateNRip(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_cbInstr)); \
5475	} while (0)
5476
5477	#else
5478	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) (false)
5479	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
5480	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
5481	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
5482	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
5483	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) (false)
5484	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { return VERR_SVM_IPE_1; } while (0)
5485	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) do { return VERR_SVM_IPE_1; } while (0)
5486	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, \
5487	a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
5488	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
5489	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) do { } while (0)
5490
5491	#endif
5492
5493	/** @} */
5494
5495	uint32_t iemCalcExecDbgFlagsSlow(PVMCPUCC pVCpu);
5496	VBOXSTRICTRC iemExecInjectPendingTrap(PVMCPUCC pVCpu);
5497
5498
5499	/**
5500	* Selector descriptor table entry as fetched by iemMemFetchSelDesc.
5501	*/
5502	typedef union IEMSELDESC
5503	{
5504	/** The legacy view. */
5505	X86DESC Legacy;
5506	/** The long mode view. */
5507	X86DESC64 Long;
5508	} IEMSELDESC;
5509	/** Pointer to a selector descriptor table entry. */
5510	typedef IEMSELDESC *PIEMSELDESC;
5511
5512	/** @name Raising Exceptions.
5513	* @{ */
5514	VBOXSTRICTRC iemTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, uint32_t uNextEip, uint32_t fFlags,
5515	uint16_t uErr, uint64_t uCr2, RTSEL SelTSS, PIEMSELDESC pNewDescTSS) RT_NOEXCEPT;
5516
5517	VBOXSTRICTRC iemRaiseXcptOrInt(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags,
5518	uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
5519	#ifdef IEM_WITH_SETJMP
5520	DECL_NO_RETURN(void) iemRaiseXcptOrIntJmp(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector,
5521	uint32_t fFlags, uint16_t uErr, uint64_t uCr2) IEM_NOEXCEPT_MAY_LONGJMP;
5522	#endif
5523	VBOXSTRICTRC iemRaiseDivideError(PVMCPUCC pVCpu) RT_NOEXCEPT;
5524	#ifdef IEM_WITH_SETJMP
5525	DECL_NO_RETURN(void) iemRaiseDivideErrorJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5526	#endif
5527	VBOXSTRICTRC iemRaiseDebugException(PVMCPUCC pVCpu) RT_NOEXCEPT;
5528	VBOXSTRICTRC iemRaiseBoundRangeExceeded(PVMCPUCC pVCpu) RT_NOEXCEPT;
5529	VBOXSTRICTRC iemRaiseUndefinedOpcode(PVMCPUCC pVCpu) RT_NOEXCEPT;
5530	#ifdef IEM_WITH_SETJMP
5531	DECL_NO_RETURN(void) iemRaiseUndefinedOpcodeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5532	#endif
5533	VBOXSTRICTRC iemRaiseDeviceNotAvailable(PVMCPUCC pVCpu) RT_NOEXCEPT;
5534	#ifdef IEM_WITH_SETJMP
5535	DECL_NO_RETURN(void) iemRaiseDeviceNotAvailableJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5536	#endif
5537	VBOXSTRICTRC iemRaiseTaskSwitchFaultWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5538	VBOXSTRICTRC iemRaiseTaskSwitchFaultCurrentTSS(PVMCPUCC pVCpu) RT_NOEXCEPT;
5539	VBOXSTRICTRC iemRaiseTaskSwitchFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
5540	VBOXSTRICTRC iemRaiseTaskSwitchFaultBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5541	/VBOXSTRICTRC iemRaiseSelectorNotPresent(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;/
5542	VBOXSTRICTRC iemRaiseSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5543	VBOXSTRICTRC iemRaiseSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5544	VBOXSTRICTRC iemRaiseStackSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5545	VBOXSTRICTRC iemRaiseStackSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5546	VBOXSTRICTRC iemRaiseGeneralProtectionFault(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5547	VBOXSTRICTRC iemRaiseGeneralProtectionFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
5548	#ifdef IEM_WITH_SETJMP
5549	DECL_NO_RETURN(void) iemRaiseGeneralProtectionFault0Jmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5550	#endif
5551	VBOXSTRICTRC iemRaiseGeneralProtectionFaultBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
5552	VBOXSTRICTRC iemRaiseNotCanonical(PVMCPUCC pVCpu) RT_NOEXCEPT;
5553	VBOXSTRICTRC iemRaiseSelectorBounds(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
5554	#ifdef IEM_WITH_SETJMP
5555	DECL_NO_RETURN(void) iemRaiseSelectorBoundsJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
5556	#endif
5557	VBOXSTRICTRC iemRaiseSelectorBoundsBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
5558	#ifdef IEM_WITH_SETJMP
5559	DECL_NO_RETURN(void) iemRaiseSelectorBoundsBySelectorJmp(PVMCPUCC pVCpu, RTSEL Sel) IEM_NOEXCEPT_MAY_LONGJMP;
5560	#endif
5561	VBOXSTRICTRC iemRaiseSelectorInvalidAccess(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
5562	#ifdef IEM_WITH_SETJMP
5563	DECL_NO_RETURN(void) iemRaiseSelectorInvalidAccessJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
5564	#endif
5565	VBOXSTRICTRC iemRaisePageFault(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) RT_NOEXCEPT;
5566	#ifdef IEM_WITH_SETJMP
5567	DECL_NO_RETURN(void) iemRaisePageFaultJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) IEM_NOEXCEPT_MAY_LONGJMP;
5568	#endif
5569	VBOXSTRICTRC iemRaiseMathFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
5570	#ifdef IEM_WITH_SETJMP
5571	DECL_NO_RETURN(void) iemRaiseMathFaultJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5572	#endif
5573	VBOXSTRICTRC iemRaiseAlignmentCheckException(PVMCPUCC pVCpu) RT_NOEXCEPT;
5574	#ifdef IEM_WITH_SETJMP
5575	DECL_NO_RETURN(void) iemRaiseAlignmentCheckExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5576	#endif
5577	VBOXSTRICTRC iemRaiseSimdFpException(PVMCPUCC pVCpu) RT_NOEXCEPT;
5578	#ifdef IEM_WITH_SETJMP
5579	DECL_NO_RETURN(void) iemRaiseSimdFpExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5580	#endif
5581
5582	void iemLogSyscallRealModeInt(PVMCPUCC pVCpu, uint8_t u8Vector, uint8_t cbInstr);
5583	void iemLogSyscallProtModeInt(PVMCPUCC pVCpu, uint8_t u8Vector, uint8_t cbInstr);
5584
5585	IEM_CIMPL_DEF_0(iemCImplRaiseDivideError);
5586	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidLockPrefix);
5587	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidOpcode);
5588
5589	/**
5590	* Macro for calling iemCImplRaiseDivideError().
5591	*
5592	* This is for things that will _always_ decode to an \#DE, taking the
5593	* recompiler into consideration and everything.
5594	*
5595	* @return Strict VBox status code.
5596	*/
5597	#define IEMOP_RAISE_DIVIDE_ERROR_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseDivideError)
5598
5599	/**
5600	* Macro for calling iemCImplRaiseInvalidLockPrefix().
5601	*
5602	* This is for things that will _always_ decode to an \#UD, taking the
5603	* recompiler into consideration and everything.
5604	*
5605	* @return Strict VBox status code.
5606	*/
5607	#define IEMOP_RAISE_INVALID_LOCK_PREFIX_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidLockPrefix)
5608
5609	/**
5610	* Macro for calling iemCImplRaiseInvalidOpcode() for decode/static \#UDs.
5611	*
5612	* This is for things that will _always_ decode to an \#UD, taking the
5613	* recompiler into consideration and everything.
5614	*
5615	* @return Strict VBox status code.
5616	*/
5617	#define IEMOP_RAISE_INVALID_OPCODE_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidOpcode)
5618
5619	/**
5620	* Macro for calling iemCImplRaiseInvalidOpcode() for runtime-style \#UDs.
5621	*
5622	* Using this macro means you've got _buggy_ _code_ and are doing things that
5623	* belongs exclusively in IEMAllCImpl.cpp during decoding.
5624	*
5625	* @return Strict VBox status code.
5626	* @see IEMOP_RAISE_INVALID_OPCODE_RET
5627	*/
5628	#define IEMOP_RAISE_INVALID_OPCODE_RUNTIME_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidOpcode)
5629
5630	/** @} */
5631
5632	/** @name Register Access.
5633	* @{ */
5634	VBOXSTRICTRC iemRegRipRelativeJumpS8AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int8_t offNextInstr,
5635	IEMMODE enmEffOpSize) RT_NOEXCEPT;
5636	VBOXSTRICTRC iemRegRipRelativeJumpS16AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int16_t offNextInstr) RT_NOEXCEPT;
5637	VBOXSTRICTRC iemRegRipRelativeJumpS32AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int32_t offNextInstr,
5638	IEMMODE enmEffOpSize) RT_NOEXCEPT;
5639	/** @} */
5640
5641	/** @name FPU access and helpers.
5642	* @{ */
5643	void iemFpuPushResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
5644	void iemFpuPushResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5645	void iemFpuPushResultTwo(PVMCPUCC pVCpu, PIEMFPURESULTTWO pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
5646	void iemFpuStoreResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
5647	void iemFpuStoreResultThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
5648	void iemFpuStoreResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
5649	uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5650	void iemFpuStoreResultWithMemOpThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
5651	uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5652	void iemFpuUpdateOpcodeAndIp(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5653	void iemFpuUpdateFSW(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
5654	void iemFpuUpdateFSWThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
5655	void iemFpuUpdateFSWWithMemOp(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5656	void iemFpuUpdateFSWThenPopPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
5657	void iemFpuUpdateFSWWithMemOpThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5658	void iemFpuStackUnderflow(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
5659	void iemFpuStackUnderflowWithMemOp(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5660	void iemFpuStackUnderflowThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
5661	void iemFpuStackUnderflowWithMemOpThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5662	void iemFpuStackUnderflowThenPopPop(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5663	void iemFpuStackPushUnderflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5664	void iemFpuStackPushUnderflowTwo(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5665	void iemFpuStackPushOverflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5666	void iemFpuStackPushOverflowWithMemOp(PVMCPUCC pVCpu, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5667	/** @} */
5668
5669	/** @name SSE+AVX SIMD access and helpers.
5670	* @{ */
5671	void iemSseUpdateMxcsr(PVMCPUCC pVCpu, uint32_t fMxcsr) RT_NOEXCEPT;
5672	/** @} */
5673
5674	/** @name Memory access.
5675	* @{ */
5676
5677	/** Report a \#GP instead of \#AC and do not restrict to ring-3 */
5678	#define IEM_MEMMAP_F_ALIGN_GP RT_BIT_32(16)
5679	/** SSE access that should report a \#GP instead of \#AC, unless MXCSR.MM=1
5680	* when it works like normal \#AC. Always used with IEM_MEMMAP_F_ALIGN_GP. */
5681	#define IEM_MEMMAP_F_ALIGN_SSE RT_BIT_32(17)
5682	/** If \#AC is applicable, raise it. Always used with IEM_MEMMAP_F_ALIGN_GP.
5683	* Users include FXSAVE & FXRSTOR. */
5684	#define IEM_MEMMAP_F_ALIGN_GP_OR_AC RT_BIT_32(18)
5685
5686	VBOXSTRICTRC iemMemMap(PVMCPUCC pVCpu, void *ppvMem, uint8_t pbUnmapInfo, size_t cbMem, uint8_t iSegReg, RTGCPTR GCPtrMem,
5687	uint32_t fAccess, uint32_t uAlignCtl) RT_NOEXCEPT;
5688	VBOXSTRICTRC iemMemCommitAndUnmap(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5689	#ifndef IN_RING3
5690	VBOXSTRICTRC iemMemCommitAndUnmapPostponeTroubleToR3(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5691	#endif
5692	void iemMemRollbackAndUnmap(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5693	void iemMemRollback(PVMCPUCC pVCpu) RT_NOEXCEPT;
5694	VBOXSTRICTRC iemMemApplySegment(PVMCPUCC pVCpu, uint32_t fAccess, uint8_t iSegReg, size_t cbMem, PRTGCPTR pGCPtrMem) RT_NOEXCEPT;
5695	VBOXSTRICTRC iemMemMarkSelDescAccessed(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5696	VBOXSTRICTRC iemMemPageTranslateAndCheckAccess(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t cbAccess, uint32_t fAccess, PRTGCPHYS pGCPhysMem) RT_NOEXCEPT;
5697
5698	void iemOpcodeFlushLight(PVMCPUCC pVCpu, uint8_t cbInstr);
5699	void iemOpcodeFlushHeavy(PVMCPUCC pVCpu, uint8_t cbInstr);
5700	#ifdef IEM_WITH_CODE_TLB
5701	void iemOpcodeFetchBytesJmp(PVMCPUCC pVCpu, size_t cbDst, void *pvDst) IEM_NOEXCEPT_MAY_LONGJMP;
5702	#else
5703	VBOXSTRICTRC iemOpcodeFetchMoreBytes(PVMCPUCC pVCpu, size_t cbMin) RT_NOEXCEPT;
5704	#endif
5705	#ifdef IEM_WITH_SETJMP
5706	uint8_t iemOpcodeGetNextU8SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5707	uint16_t iemOpcodeGetNextU16SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5708	uint32_t iemOpcodeGetNextU32SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5709	uint64_t iemOpcodeGetNextU64SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5710	#else
5711	VBOXSTRICTRC iemOpcodeGetNextU8Slow(PVMCPUCC pVCpu, uint8_t *pb) RT_NOEXCEPT;
5712	VBOXSTRICTRC iemOpcodeGetNextS8SxU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
5713	VBOXSTRICTRC iemOpcodeGetNextS8SxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
5714	VBOXSTRICTRC iemOpcodeGetNextS8SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5715	VBOXSTRICTRC iemOpcodeGetNextU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
5716	VBOXSTRICTRC iemOpcodeGetNextU16ZxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
5717	VBOXSTRICTRC iemOpcodeGetNextU16ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5718	VBOXSTRICTRC iemOpcodeGetNextU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
5719	VBOXSTRICTRC iemOpcodeGetNextU32ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5720	VBOXSTRICTRC iemOpcodeGetNextS32SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5721	VBOXSTRICTRC iemOpcodeGetNextU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5722	#endif
5723
5724	VBOXSTRICTRC iemMemFetchDataU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5725	VBOXSTRICTRC iemMemFetchDataU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5726	VBOXSTRICTRC iemMemFetchDataU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5727	VBOXSTRICTRC iemMemFetchDataU32_ZX_U64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5728	VBOXSTRICTRC iemMemFetchDataU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5729	VBOXSTRICTRC iemMemFetchDataU64AlignedU128(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5730	VBOXSTRICTRC iemMemFetchDataR80(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5731	VBOXSTRICTRC iemMemFetchDataD80(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5732	VBOXSTRICTRC iemMemFetchDataU128(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5733	VBOXSTRICTRC iemMemFetchDataU128NoAc(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5734	VBOXSTRICTRC iemMemFetchDataU128AlignedSse(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5735	VBOXSTRICTRC iemMemFetchDataU256(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5736	VBOXSTRICTRC iemMemFetchDataU256NoAc(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5737	VBOXSTRICTRC iemMemFetchDataU256AlignedAvx(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5738	VBOXSTRICTRC iemMemFetchDataXdtr(PVMCPUCC pVCpu, uint16_t *pcbLimit, PRTGCPTR pGCPtrBase, uint8_t iSegReg,
5739	RTGCPTR GCPtrMem, IEMMODE enmOpSize) RT_NOEXCEPT;
5740	#ifdef IEM_WITH_SETJMP
5741	uint8_t iemMemFetchDataU8SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5742	uint16_t iemMemFetchDataU16SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5743	uint32_t iemMemFetchDataU32SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5744	uint32_t iemMemFlatFetchDataU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5745	uint64_t iemMemFetchDataU64SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5746	uint64_t iemMemFetchDataU64AlignedU128SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5747	void iemMemFetchDataR80SafeJmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5748	void iemMemFetchDataD80SafeJmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5749	void iemMemFetchDataU128SafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5750	void iemMemFetchDataU128NoAcSafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5751	void iemMemFetchDataU128AlignedSseSafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5752	void iemMemFetchDataU256SafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5753	void iemMemFetchDataU256NoAcSafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5754	void iemMemFetchDataU256AlignedAvxSafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5755	# if 0 /* these are inlined now */
5756	uint8_t iemMemFetchDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5757	uint16_t iemMemFetchDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5758	uint32_t iemMemFetchDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5759	uint32_t iemMemFlatFetchDataU32Jmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5760	uint64_t iemMemFetchDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5761	uint64_t iemMemFetchDataU64AlignedU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5762	void iemMemFetchDataR80Jmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5763	void iemMemFetchDataD80Jmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5764	void iemMemFetchDataU128Jmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5765	void iemMemFetchDataU128NoAcJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5766	void iemMemFetchDataU128AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5767	void iemMemFetchDataU256NoAcJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5768	void iemMemFetchDataU256AlignedAvxJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5769	# endif
5770	void iemMemFetchDataU256Jmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5771	#endif
5772
5773	VBOXSTRICTRC iemMemFetchSysU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5774	VBOXSTRICTRC iemMemFetchSysU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5775	VBOXSTRICTRC iemMemFetchSysU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5776	VBOXSTRICTRC iemMemFetchSysU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5777	VBOXSTRICTRC iemMemFetchSelDesc(PVMCPUCC pVCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt) RT_NOEXCEPT;
5778
5779	VBOXSTRICTRC iemMemStoreDataU8(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) RT_NOEXCEPT;
5780	VBOXSTRICTRC iemMemStoreDataU16(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) RT_NOEXCEPT;
5781	VBOXSTRICTRC iemMemStoreDataU32(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) RT_NOEXCEPT;
5782	VBOXSTRICTRC iemMemStoreDataU64(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) RT_NOEXCEPT;
5783	VBOXSTRICTRC iemMemStoreDataU128(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
5784	VBOXSTRICTRC iemMemStoreDataU128NoAc(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
5785	VBOXSTRICTRC iemMemStoreDataU128AlignedSse(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
5786	VBOXSTRICTRC iemMemStoreDataU256(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
5787	VBOXSTRICTRC iemMemStoreDataU256NoAc(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
5788	VBOXSTRICTRC iemMemStoreDataU256AlignedAvx(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
5789	VBOXSTRICTRC iemMemStoreDataXdtr(PVMCPUCC pVCpu, uint16_t cbLimit, RTGCPTR GCPtrBase, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5790	#ifdef IEM_WITH_SETJMP
5791	void iemMemStoreDataU8SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
5792	void iemMemStoreDataU16SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
5793	void iemMemStoreDataU32SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
5794	void iemMemStoreDataU64SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
5795	void iemMemStoreDataU128SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5796	void iemMemStoreDataU128NoAcSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT128U pu128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5797	void iemMemStoreDataU128AlignedSseSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT128U pu128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5798	void iemMemStoreDataU256SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5799	void iemMemStoreDataU256NoAcSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5800	void iemMemStoreDataU256AlignedAvxSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5801	void iemMemStoreDataR80SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTFLOAT80U pr80Value) IEM_NOEXCEPT_MAY_LONGJMP;
5802	void iemMemStoreDataD80SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTPBCD80U pd80Value) IEM_NOEXCEPT_MAY_LONGJMP;
5803	#if 0
5804	void iemMemStoreDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
5805	void iemMemStoreDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
5806	void iemMemStoreDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
5807	void iemMemStoreDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
5808	void iemMemStoreDataU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5809	void iemMemStoreDataNoAcU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5810	void iemMemStoreDataU256NoAcJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5811	void iemMemStoreDataU256AlignedAvxJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5812	#endif
5813	void iemMemStoreDataU128AlignedSseJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5814	void iemMemStoreDataU256Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5815	#endif
5816
5817	#ifdef IEM_WITH_SETJMP
5818	uint8_t iemMemMapDataU8RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5819	uint8_t iemMemMapDataU8AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5820	uint8_t iemMemMapDataU8WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5821	uint8_t const iemMemMapDataU8RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5822	uint16_t iemMemMapDataU16RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5823	uint16_t iemMemMapDataU16AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5824	uint16_t iemMemMapDataU16WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5825	uint16_t const iemMemMapDataU16RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5826	uint32_t iemMemMapDataU32RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5827	uint32_t iemMemMapDataU32AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5828	uint32_t iemMemMapDataU32WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5829	uint32_t const iemMemMapDataU32RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5830	uint64_t iemMemMapDataU64RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5831	uint64_t iemMemMapDataU64AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5832	uint64_t iemMemMapDataU64WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5833	uint64_t const iemMemMapDataU64RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5834	PRTFLOAT80U iemMemMapDataR80RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5835	PRTFLOAT80U iemMemMapDataR80WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5836	PCRTFLOAT80U iemMemMapDataR80RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5837	PRTPBCD80U iemMemMapDataD80RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5838	PRTPBCD80U iemMemMapDataD80WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5839	PCRTPBCD80U iemMemMapDataD80RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5840	PRTUINT128U iemMemMapDataU128RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5841	PRTUINT128U iemMemMapDataU128AtSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5842	PRTUINT128U iemMemMapDataU128WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5843	PCRTUINT128U iemMemMapDataU128RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5844
5845	void iemMemCommitAndUnmapJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5846	void iemMemCommitAndUnmapRwSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5847	void iemMemCommitAndUnmapAtSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5848	void iemMemCommitAndUnmapWoSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5849	void iemMemCommitAndUnmapRoSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5850	void iemMemRollbackAndUnmapWoSafe(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5851	#endif
5852
5853	VBOXSTRICTRC iemMemStackPushBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
5854	void *ppvMem, uint8_t pbUnmapInfo, uint64_t *puNewRsp) RT_NOEXCEPT;
5855	VBOXSTRICTRC iemMemStackPushCommitSpecial(PVMCPUCC pVCpu, uint8_t bUnmapInfo, uint64_t uNewRsp) RT_NOEXCEPT;
5856	VBOXSTRICTRC iemMemStackPushU16(PVMCPUCC pVCpu, uint16_t u16Value) RT_NOEXCEPT;
5857	VBOXSTRICTRC iemMemStackPushU32(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
5858	VBOXSTRICTRC iemMemStackPushU64(PVMCPUCC pVCpu, uint64_t u64Value) RT_NOEXCEPT;
5859	VBOXSTRICTRC iemMemStackPushU16Ex(PVMCPUCC pVCpu, uint16_t u16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5860	VBOXSTRICTRC iemMemStackPushU32Ex(PVMCPUCC pVCpu, uint32_t u32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5861	VBOXSTRICTRC iemMemStackPushU64Ex(PVMCPUCC pVCpu, uint64_t u64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5862	VBOXSTRICTRC iemMemStackPushU32SReg(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
5863	VBOXSTRICTRC iemMemStackPopBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
5864	void const *ppvMem, uint8_t pbUnmapInfo, uint64_t *puNewRsp) RT_NOEXCEPT;
5865	VBOXSTRICTRC iemMemStackPopContinueSpecial(PVMCPUCC pVCpu, size_t off, size_t cbMem,
5866	void const *ppvMem, uint8_t pbUnmapInfo, uint64_t uCurNewRsp) RT_NOEXCEPT;
5867	VBOXSTRICTRC iemMemStackPopDoneSpecial(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5868	VBOXSTRICTRC iemMemStackPopU16(PVMCPUCC pVCpu, uint16_t *pu16Value) RT_NOEXCEPT;
5869	VBOXSTRICTRC iemMemStackPopU32(PVMCPUCC pVCpu, uint32_t *pu32Value) RT_NOEXCEPT;
5870	VBOXSTRICTRC iemMemStackPopU64(PVMCPUCC pVCpu, uint64_t *pu64Value) RT_NOEXCEPT;
5871	VBOXSTRICTRC iemMemStackPopU16Ex(PVMCPUCC pVCpu, uint16_t *pu16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5872	VBOXSTRICTRC iemMemStackPopU32Ex(PVMCPUCC pVCpu, uint32_t *pu32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5873	VBOXSTRICTRC iemMemStackPopU64Ex(PVMCPUCC pVCpu, uint64_t *pu64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
5874
5875	#ifdef IEM_WITH_SETJMP
5876	void iemMemStackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5877	void iemMemStackPushU32SafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5878	void iemMemStackPushU32SRegSafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5879	void iemMemStackPushU64SafeJmp(PVMCPUCC pVCpu, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5880	void iemMemStackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5881	void iemMemStackPopGRegU32SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5882	void iemMemStackPopGRegU64SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5883
5884	void iemMemFlat32StackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5885	void iemMemFlat32StackPushU32SafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5886	void iemMemFlat32StackPushU32SRegSafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5887	void iemMemFlat32StackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5888	void iemMemFlat32StackPopGRegU32SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5889
5890	void iemMemFlat64StackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5891	void iemMemFlat64StackPushU64SafeJmp(PVMCPUCC pVCpu, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5892	void iemMemFlat64StackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5893	void iemMemFlat64StackPopGRegU64SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
5894
5895	void iemMemStoreStackU16SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5896	void iemMemStoreStackU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5897	void iemMemStoreStackU32SRegSafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5898	void iemMemStoreStackU64SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
5899
5900	uint16_t iemMemFetchStackU16SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5901	uint32_t iemMemFetchStackU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5902	uint64_t iemMemFetchStackU64SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5903
5904	#endif
5905
5906	/** @} */
5907
5908	/** @name IEMAllCImpl.cpp
5909	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/'
5910	* @{ */
5911	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem16, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5912	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem32, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5913	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem64, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5914	IEM_CIMPL_PROTO_0(iemCImpl_popa_16);
5915	IEM_CIMPL_PROTO_0(iemCImpl_popa_32);
5916	IEM_CIMPL_PROTO_0(iemCImpl_pusha_16);
5917	IEM_CIMPL_PROTO_0(iemCImpl_pusha_32);
5918	IEM_CIMPL_PROTO_1(iemCImpl_pushf, IEMMODE, enmEffOpSize);
5919	IEM_CIMPL_PROTO_1(iemCImpl_popf, IEMMODE, enmEffOpSize);
5920	IEM_CIMPL_PROTO_3(iemCImpl_FarJmp, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
5921	IEM_CIMPL_PROTO_3(iemCImpl_callf, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
5922	typedef IEM_CIMPL_DECL_TYPE_3(FNIEMCIMPLFARBRANCH, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
5923	typedef FNIEMCIMPLFARBRANCH *PFNIEMCIMPLFARBRANCH;
5924	IEM_CIMPL_PROTO_2(iemCImpl_retf, IEMMODE, enmEffOpSize, uint16_t, cbPop);
5925	IEM_CIMPL_PROTO_3(iemCImpl_enter, IEMMODE, enmEffOpSize, uint16_t, cbFrame, uint8_t, cParameters);
5926	IEM_CIMPL_PROTO_1(iemCImpl_leave, IEMMODE, enmEffOpSize);
5927	IEM_CIMPL_PROTO_2(iemCImpl_int, uint8_t, u8Int, IEMINT, enmInt);
5928	IEM_CIMPL_PROTO_1(iemCImpl_iret_real_v8086, IEMMODE, enmEffOpSize);
5929	IEM_CIMPL_PROTO_4(iemCImpl_iret_prot_v8086, uint32_t, uNewEip, uint16_t, uNewCs, uint32_t, uNewFlags, uint64_t, uNewRsp);
5930	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot_NestedTask, IEMMODE, enmEffOpSize);
5931	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot, IEMMODE, enmEffOpSize);
5932	IEM_CIMPL_PROTO_1(iemCImpl_iret_64bit, IEMMODE, enmEffOpSize);
5933	IEM_CIMPL_PROTO_1(iemCImpl_iret, IEMMODE, enmEffOpSize);
5934	IEM_CIMPL_PROTO_0(iemCImpl_loadall286);
5935	IEM_CIMPL_PROTO_0(iemCImpl_syscall);
5936	IEM_CIMPL_PROTO_1(iemCImpl_sysret, IEMMODE, enmEffOpSize);
5937	IEM_CIMPL_PROTO_0(iemCImpl_sysenter);
5938	IEM_CIMPL_PROTO_1(iemCImpl_sysexit, IEMMODE, enmEffOpSize);
5939	IEM_CIMPL_PROTO_2(iemCImpl_LoadSReg, uint8_t, iSegReg, uint16_t, uSel);
5940	IEM_CIMPL_PROTO_2(iemCImpl_load_SReg, uint8_t, iSegReg, uint16_t, uSel);
5941	IEM_CIMPL_PROTO_2(iemCImpl_pop_Sreg, uint8_t, iSegReg, IEMMODE, enmEffOpSize);
5942	IEM_CIMPL_PROTO_5(iemCImpl_load_SReg_Greg, uint16_t, uSel, uint64_t, offSeg, uint8_t, iSegReg, uint8_t, iGReg, IEMMODE, enmEffOpSize);
5943	IEM_CIMPL_PROTO_2(iemCImpl_VerX, uint16_t, uSel, bool, fWrite);
5944	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u64, uint64_t *, pu64Dst, uint16_t, uSel, bool, fIsLar);
5945	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u16, uint16_t *, pu16Dst, uint16_t, uSel, bool, fIsLar);
5946	IEM_CIMPL_PROTO_3(iemCImpl_lgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
5947	IEM_CIMPL_PROTO_2(iemCImpl_sgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5948	IEM_CIMPL_PROTO_3(iemCImpl_lidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
5949	IEM_CIMPL_PROTO_2(iemCImpl_sidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5950	IEM_CIMPL_PROTO_1(iemCImpl_lldt, uint16_t, uNewLdt);
5951	IEM_CIMPL_PROTO_2(iemCImpl_sldt_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
5952	IEM_CIMPL_PROTO_2(iemCImpl_sldt_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5953	IEM_CIMPL_PROTO_1(iemCImpl_ltr, uint16_t, uNewTr);
5954	IEM_CIMPL_PROTO_2(iemCImpl_str_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
5955	IEM_CIMPL_PROTO_2(iemCImpl_str_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5956	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Cd, uint8_t, iGReg, uint8_t, iCrReg);
5957	IEM_CIMPL_PROTO_2(iemCImpl_smsw_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
5958	IEM_CIMPL_PROTO_2(iemCImpl_smsw_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
5959	IEM_CIMPL_PROTO_4(iemCImpl_load_CrX, uint8_t, iCrReg, uint64_t, uNewCrX, IEMACCESSCRX, enmAccessCrX, uint8_t, iGReg);
5960	IEM_CIMPL_PROTO_2(iemCImpl_mov_Cd_Rd, uint8_t, iCrReg, uint8_t, iGReg);
5961	IEM_CIMPL_PROTO_2(iemCImpl_lmsw, uint16_t, u16NewMsw, RTGCPTR, GCPtrEffDst);
5962	IEM_CIMPL_PROTO_0(iemCImpl_clts);
5963	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Dd, uint8_t, iGReg, uint8_t, iDrReg);
5964	IEM_CIMPL_PROTO_2(iemCImpl_mov_Dd_Rd, uint8_t, iDrReg, uint8_t, iGReg);
5965	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Td, uint8_t, iGReg, uint8_t, iTrReg);
5966	IEM_CIMPL_PROTO_2(iemCImpl_mov_Td_Rd, uint8_t, iTrReg, uint8_t, iGReg);
5967	IEM_CIMPL_PROTO_1(iemCImpl_invlpg, RTGCPTR, GCPtrPage);
5968	IEM_CIMPL_PROTO_3(iemCImpl_invpcid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvpcidDesc, uint64_t, uInvpcidType);
5969	IEM_CIMPL_PROTO_0(iemCImpl_invd);
5970	IEM_CIMPL_PROTO_0(iemCImpl_wbinvd);
5971	IEM_CIMPL_PROTO_0(iemCImpl_rsm);
5972	IEM_CIMPL_PROTO_0(iemCImpl_rdtsc);
5973	IEM_CIMPL_PROTO_0(iemCImpl_rdtscp);
5974	IEM_CIMPL_PROTO_0(iemCImpl_rdpmc);
5975	IEM_CIMPL_PROTO_0(iemCImpl_rdmsr);
5976	IEM_CIMPL_PROTO_0(iemCImpl_wrmsr);
5977	IEM_CIMPL_PROTO_3(iemCImpl_in, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
5978	IEM_CIMPL_PROTO_2(iemCImpl_in_eAX_DX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
5979	IEM_CIMPL_PROTO_3(iemCImpl_out, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
5980	IEM_CIMPL_PROTO_2(iemCImpl_out_DX_eAX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
5981	IEM_CIMPL_PROTO_0(iemCImpl_cli);
5982	IEM_CIMPL_PROTO_0(iemCImpl_sti);
5983	IEM_CIMPL_PROTO_0(iemCImpl_hlt);
5984	IEM_CIMPL_PROTO_1(iemCImpl_monitor, uint8_t, iEffSeg);
5985	IEM_CIMPL_PROTO_0(iemCImpl_mwait);
5986	IEM_CIMPL_PROTO_0(iemCImpl_swapgs);
5987	IEM_CIMPL_PROTO_0(iemCImpl_cpuid);
5988	IEM_CIMPL_PROTO_1(iemCImpl_aad, uint8_t, bImm);
5989	IEM_CIMPL_PROTO_1(iemCImpl_aam, uint8_t, bImm);
5990	IEM_CIMPL_PROTO_0(iemCImpl_daa);
5991	IEM_CIMPL_PROTO_0(iemCImpl_das);
5992	IEM_CIMPL_PROTO_0(iemCImpl_aaa);
5993	IEM_CIMPL_PROTO_0(iemCImpl_aas);
5994	IEM_CIMPL_PROTO_3(iemCImpl_bound_16, int16_t, idxArray, int16_t, idxLowerBound, int16_t, idxUpperBound);
5995	IEM_CIMPL_PROTO_3(iemCImpl_bound_32, int32_t, idxArray, int32_t, idxLowerBound, int32_t, idxUpperBound);
5996	IEM_CIMPL_PROTO_0(iemCImpl_xgetbv);
5997	IEM_CIMPL_PROTO_0(iemCImpl_xsetbv);
5998	IEM_CIMPL_PROTO_5(iemCImpl_cmpxchg16b_fallback_rendezvous, PRTUINT128U, pu128Dst, PRTUINT128U, pu128RaxRdx,
5999	PRTUINT128U, pu128RbxRcx, uint32_t *, pEFlags, uint8_t, bUnmapInfo);
6000	IEM_CIMPL_PROTO_2(iemCImpl_clflush_clflushopt, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
6001	IEM_CIMPL_PROTO_1(iemCImpl_finit, bool, fCheckXcpts);
6002	IEM_CIMPL_PROTO_3(iemCImpl_fxsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
6003	IEM_CIMPL_PROTO_3(iemCImpl_fxrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
6004	IEM_CIMPL_PROTO_3(iemCImpl_xsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
6005	IEM_CIMPL_PROTO_3(iemCImpl_xrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
6006	IEM_CIMPL_PROTO_2(iemCImpl_stmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
6007	IEM_CIMPL_PROTO_2(iemCImpl_vstmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
6008	IEM_CIMPL_PROTO_2(iemCImpl_ldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
6009	IEM_CIMPL_PROTO_3(iemCImpl_fnstenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6010	IEM_CIMPL_PROTO_3(iemCImpl_fnsave, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6011	IEM_CIMPL_PROTO_3(iemCImpl_fldenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6012	IEM_CIMPL_PROTO_3(iemCImpl_frstor, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6013	IEM_CIMPL_PROTO_1(iemCImpl_fldcw, uint16_t, u16Fcw);
6014	IEM_CIMPL_PROTO_2(iemCImpl_fxch_underflow, uint8_t, iStReg, uint16_t, uFpuOpcode);
6015	IEM_CIMPL_PROTO_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, bool, fUCmp, uint32_t, uPopAndFpuOpcode);
6016	IEM_CIMPL_PROTO_2(iemCImpl_rdseed, uint8_t, iReg, IEMMODE, enmEffOpSize);
6017	IEM_CIMPL_PROTO_2(iemCImpl_rdrand, uint8_t, iReg, IEMMODE, enmEffOpSize);
6018	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovps_load_u128, uint8_t, iXRegDst, uint8_t, iXRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6019	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovps_load_u256, uint8_t, iYRegDst, uint8_t, iYRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6020	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovps_store_u128, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iXRegMsk, uint8_t, iXRegSrc);
6021	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovps_store_u256, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iYRegMsk, uint8_t, iYRegSrc);
6022	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovd_load_u128, uint8_t, iXRegDst, uint8_t, iXRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6023	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovd_load_u256, uint8_t, iYRegDst, uint8_t, iYRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6024	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovd_store_u128, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iXRegMsk, uint8_t, iXRegSrc);
6025	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovd_store_u256, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iYRegMsk, uint8_t, iYRegSrc);
6026	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovpd_load_u128, uint8_t, iXRegDst, uint8_t, iXRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6027	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovpd_load_u256, uint8_t, iYRegDst, uint8_t, iYRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6028	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovpd_store_u128, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iXRegMsk, uint8_t, iXRegSrc);
6029	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovpd_store_u256, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iYRegMsk, uint8_t, iYRegSrc);
6030	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovq_load_u128, uint8_t, iXRegDst, uint8_t, iXRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6031	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovq_load_u256, uint8_t, iYRegDst, uint8_t, iYRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6032	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovq_store_u128, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iXRegMsk, uint8_t, iXRegSrc);
6033	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovq_store_u256, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iYRegMsk, uint8_t, iYRegSrc);
6034
6035	/** @} */
6036
6037	/** @name IEMAllCImplStrInstr.cpp.h
6038	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/' -e 's/RT_CONCAT4(//' \
6039	* -e 's/,ADDR_SIZE)/64/g' -e 's/,OP_SIZE,/64/g' -e 's/,OP_rAX,/rax/g' IEMAllCImplStrInstr.cpp.h
6040	* @{ */
6041	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr16, uint8_t, iEffSeg);
6042	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr16, uint8_t, iEffSeg);
6043	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m16);
6044	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m16);
6045	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr16, uint8_t, iEffSeg);
6046	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m16);
6047	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m16, int8_t, iEffSeg);
6048	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr16, bool, fIoChecked);
6049	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr16, bool, fIoChecked);
6050	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6051	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6052
6053	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr16, uint8_t, iEffSeg);
6054	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr16, uint8_t, iEffSeg);
6055	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m16);
6056	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m16);
6057	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr16, uint8_t, iEffSeg);
6058	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m16);
6059	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m16, int8_t, iEffSeg);
6060	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr16, bool, fIoChecked);
6061	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr16, bool, fIoChecked);
6062	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6063	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6064
6065	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr16, uint8_t, iEffSeg);
6066	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr16, uint8_t, iEffSeg);
6067	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m16);
6068	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m16);
6069	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr16, uint8_t, iEffSeg);
6070	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m16);
6071	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m16, int8_t, iEffSeg);
6072	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr16, bool, fIoChecked);
6073	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr16, bool, fIoChecked);
6074	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6075	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6076
6077
6078	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr32, uint8_t, iEffSeg);
6079	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr32, uint8_t, iEffSeg);
6080	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m32);
6081	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m32);
6082	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr32, uint8_t, iEffSeg);
6083	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m32);
6084	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m32, int8_t, iEffSeg);
6085	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr32, bool, fIoChecked);
6086	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr32, bool, fIoChecked);
6087	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6088	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6089
6090	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr32, uint8_t, iEffSeg);
6091	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr32, uint8_t, iEffSeg);
6092	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m32);
6093	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m32);
6094	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr32, uint8_t, iEffSeg);
6095	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m32);
6096	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m32, int8_t, iEffSeg);
6097	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr32, bool, fIoChecked);
6098	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr32, bool, fIoChecked);
6099	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6100	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6101
6102	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr32, uint8_t, iEffSeg);
6103	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr32, uint8_t, iEffSeg);
6104	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m32);
6105	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m32);
6106	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr32, uint8_t, iEffSeg);
6107	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m32);
6108	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m32, int8_t, iEffSeg);
6109	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr32, bool, fIoChecked);
6110	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr32, bool, fIoChecked);
6111	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6112	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6113
6114	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr32, uint8_t, iEffSeg);
6115	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr32, uint8_t, iEffSeg);
6116	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m32);
6117	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m32);
6118	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr32, uint8_t, iEffSeg);
6119	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m32);
6120	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m32, int8_t, iEffSeg);
6121	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr32, bool, fIoChecked);
6122	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr32, bool, fIoChecked);
6123	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6124	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6125
6126
6127	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr64, uint8_t, iEffSeg);
6128	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr64, uint8_t, iEffSeg);
6129	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m64);
6130	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m64);
6131	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr64, uint8_t, iEffSeg);
6132	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m64);
6133	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m64, int8_t, iEffSeg);
6134	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr64, bool, fIoChecked);
6135	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr64, bool, fIoChecked);
6136	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6137	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6138
6139	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr64, uint8_t, iEffSeg);
6140	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr64, uint8_t, iEffSeg);
6141	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m64);
6142	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m64);
6143	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr64, uint8_t, iEffSeg);
6144	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m64);
6145	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m64, int8_t, iEffSeg);
6146	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr64, bool, fIoChecked);
6147	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr64, bool, fIoChecked);
6148	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6149	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6150
6151	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr64, uint8_t, iEffSeg);
6152	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr64, uint8_t, iEffSeg);
6153	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m64);
6154	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m64);
6155	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr64, uint8_t, iEffSeg);
6156	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m64);
6157	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m64, int8_t, iEffSeg);
6158	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr64, bool, fIoChecked);
6159	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr64, bool, fIoChecked);
6160	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6161	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6162
6163	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr64, uint8_t, iEffSeg);
6164	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr64, uint8_t, iEffSeg);
6165	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m64);
6166	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m64);
6167	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr64, uint8_t, iEffSeg);
6168	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m64);
6169	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m64, int8_t, iEffSeg);
6170	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr64, bool, fIoChecked);
6171	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr64, bool, fIoChecked);
6172	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6173	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6174	/** @} */
6175
6176	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
6177	VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT;
6178	VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT;
6179	VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT;
6180	VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT;
6181	VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT;
6182	VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
6183	VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALKFAST pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT;
6184	VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT;
6185	VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT;
6186	VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
6187	bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT;
6188	VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
6189	bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT;
6190	VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6191	VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6192	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6193	VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6194	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6195	VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6196	VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT;
6197	VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
6198	RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT;
6199	VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT;
6200	VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT;
6201	VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT;
6202	uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT;
6203	void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT;
6204	VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
6205	uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT;
6206	bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT;
6207	IEM_CIMPL_PROTO_0(iemCImpl_vmxoff);
6208	IEM_CIMPL_PROTO_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon);
6209	IEM_CIMPL_PROTO_0(iemCImpl_vmlaunch);
6210	IEM_CIMPL_PROTO_0(iemCImpl_vmresume);
6211	IEM_CIMPL_PROTO_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
6212	IEM_CIMPL_PROTO_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
6213	IEM_CIMPL_PROTO_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
6214	IEM_CIMPL_PROTO_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField);
6215	IEM_CIMPL_PROTO_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField);
6216	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField);
6217	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg32, uint64_t *, pu32Dst, uint32_t, u32VmcsField);
6218	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField);
6219	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField);
6220	IEM_CIMPL_PROTO_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType);
6221	IEM_CIMPL_PROTO_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType);
6222	IEM_CIMPL_PROTO_0(iemCImpl_vmx_pause);
6223	#endif
6224
6225	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
6226	VBOXSTRICTRC iemSvmVmexit(PVMCPUCC pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2) RT_NOEXCEPT;
6227	VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr, uint64_t uCr2) RT_NOEXCEPT;
6228	VBOXSTRICTRC iemSvmHandleIOIntercept(PVMCPUCC pVCpu, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
6229	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, uint8_t cbInstr) RT_NOEXCEPT;
6230	VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPUCC pVCpu, uint32_t idMsr, bool fWrite, uint8_t cbInstr) RT_NOEXCEPT;
6231	IEM_CIMPL_PROTO_0(iemCImpl_vmrun);
6232	IEM_CIMPL_PROTO_0(iemCImpl_vmload);
6233	IEM_CIMPL_PROTO_0(iemCImpl_vmsave);
6234	IEM_CIMPL_PROTO_0(iemCImpl_clgi);
6235	IEM_CIMPL_PROTO_0(iemCImpl_stgi);
6236	IEM_CIMPL_PROTO_0(iemCImpl_invlpga);
6237	IEM_CIMPL_PROTO_0(iemCImpl_skinit);
6238	IEM_CIMPL_PROTO_0(iemCImpl_svm_pause);
6239	#endif
6240
6241	IEM_CIMPL_PROTO_0(iemCImpl_vmcall); /* vmx */
6242	IEM_CIMPL_PROTO_0(iemCImpl_vmmcall); /* svm */
6243	IEM_CIMPL_PROTO_1(iemCImpl_Hypercall, uint16_t, uDisOpcode); /* both */
6244
6245	extern const PFNIEMOP g_apfnIemInterpretOnlyOneByteMap[256];
6246	extern const PFNIEMOP g_apfnIemInterpretOnlyTwoByteMap[1024];
6247	extern const PFNIEMOP g_apfnIemInterpretOnlyThreeByte0f3a[1024];
6248	extern const PFNIEMOP g_apfnIemInterpretOnlyThreeByte0f38[1024];
6249	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap1[1024];
6250	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap2[1024];
6251	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap3[1024];
6252
6253	/*
6254	* Recompiler related stuff.
6255	*/
6256	extern const PFNIEMOP g_apfnIemThreadedRecompilerOneByteMap[256];
6257	extern const PFNIEMOP g_apfnIemThreadedRecompilerTwoByteMap[1024];
6258	extern const PFNIEMOP g_apfnIemThreadedRecompilerThreeByte0f3a[1024];
6259	extern const PFNIEMOP g_apfnIemThreadedRecompilerThreeByte0f38[1024];
6260	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap1[1024];
6261	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap2[1024];
6262	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap3[1024];
6263
6264	DECLCALLBACK(int) iemTbInit(PVMCC pVM, uint32_t cInitialTbs, uint32_t cMaxTbs,
6265	uint64_t cbInitialExec, uint64_t cbMaxExec, uint32_t cbChunkExec);
6266	void iemThreadedTbObsolete(PVMCPUCC pVCpu, PIEMTB pTb, bool fSafeToFree);
6267	DECLHIDDEN(void) iemTbAllocatorFree(PVMCPUCC pVCpu, PIEMTB pTb);
6268	void iemTbAllocatorProcessDelayedFrees(PVMCPUCC pVCpu, PIEMTBALLOCATOR pTbAllocator);
6269	void iemTbAllocatorFreeupNativeSpace(PVMCPUCC pVCpu, uint32_t cNeededInstrs);
6270	DECLHIDDEN(const char ) iemTbFlagsToString(uint32_t fFlags, char pszBuf, size_t cbBuf) RT_NOEXCEPT;
6271	DECLHIDDEN(void) iemThreadedDisassembleTb(PCIEMTB pTb, PCDBGFINFOHLP pHlp) RT_NOEXCEPT;
6272
6273
6274	/** @todo FNIEMTHREADEDFUNC and friends may need more work... */
6275	#if defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
6276	typedef VBOXSTRICTRC /__attribute__((__nothrow__))/ FNIEMTHREADEDFUNC(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
6277	typedef FNIEMTHREADEDFUNC *PFNIEMTHREADEDFUNC;
6278	# define IEM_DECL_IEMTHREADEDFUNC_DEF(a_Name) \
6279	VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2)
6280	# define IEM_DECL_IEMTHREADEDFUNC_PROTO(a_Name) \
6281	VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2)
6282
6283	#else
6284	typedef VBOXSTRICTRC (FNIEMTHREADEDFUNC)(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
6285	typedef FNIEMTHREADEDFUNC *PFNIEMTHREADEDFUNC;
6286	# define IEM_DECL_IEMTHREADEDFUNC_DEF(a_Name) \
6287	VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2) IEM_NOEXCEPT_MAY_LONGJMP
6288	# define IEM_DECL_IEMTHREADEDFUNC_PROTO(a_Name) \
6289	VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2) IEM_NOEXCEPT_MAY_LONGJMP
6290	#endif
6291
6292
6293	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_Nop);
6294	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_LogCpuState);
6295
6296	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_DeferToCImpl0);
6297
6298	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckIrq);
6299	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckMode);
6300	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckHwInstrBps);
6301	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLim);
6302
6303	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodes);
6304	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodes);
6305	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesConsiderCsLim);
6306
6307	/* Branching: */
6308	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndPcAndOpcodes);
6309	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckPcAndOpcodes);
6310	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckPcAndOpcodesConsiderCsLim);
6311
6312	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesLoadingTlb);
6313	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesLoadingTlb);
6314	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesLoadingTlbConsiderCsLim);
6315
6316	/* Natural page crossing: */
6317	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesAcrossPageLoadingTlb);
6318	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesAcrossPageLoadingTlb);
6319	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesAcrossPageLoadingTlbConsiderCsLim);
6320
6321	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesOnNextPageLoadingTlb);
6322	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNextPageLoadingTlb);
6323	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNextPageLoadingTlbConsiderCsLim);
6324
6325	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesOnNewPageLoadingTlb);
6326	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNewPageLoadingTlb);
6327	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNewPageLoadingTlbConsiderCsLim);
6328
6329	bool iemThreadedCompileEmitIrqCheckBefore(PVMCPUCC pVCpu, PIEMTB pTb);
6330	bool iemThreadedCompileBeginEmitCallsComplications(PVMCPUCC pVCpu, PIEMTB pTb);
6331
6332	/* Native recompiler public bits: */
6333	DECLHIDDEN(PIEMTB) iemNativeRecompile(PVMCPUCC pVCpu, PIEMTB pTb) RT_NOEXCEPT;
6334	DECLHIDDEN(void) iemNativeDisassembleTb(PCIEMTB pTb, PCDBGFINFOHLP pHlp) RT_NOEXCEPT;
6335	int iemExecMemAllocatorInit(PVMCPU pVCpu, uint64_t cbMax, uint64_t cbInitial, uint32_t cbChunk) RT_NOEXCEPT;
6336	DECLHIDDEN(void ) iemExecMemAllocatorAlloc(PVMCPU pVCpu, uint32_t cbReq, PIEMTB pTb, void *ppvExec) RT_NOEXCEPT;
6337	DECLHIDDEN(void) iemExecMemAllocatorReadyForUse(PVMCPUCC pVCpu, void *pv, size_t cb) RT_NOEXCEPT;
6338	void iemExecMemAllocatorFree(PVMCPU pVCpu, void *pv, size_t cb) RT_NOEXCEPT;
6339	DECLASM(DECL_NO_RETURN(void)) iemNativeTbLongJmp(void *pvFramePointer, int rc) RT_NOEXCEPT;
6340
6341	#endif /* !RT_IN_ASSEMBLER - ASM-NOINC-END */
6342
6343
6344	/** @} */
6345
6346	RT_C_DECLS_END
6347
6348	/* ASM-INC: %include "IEMInternalStruct.mac" */
6349
6350	#endif /* !VMM_INCLUDED_SRC_include_IEMInternal_h */
6351

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source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h@ 105231

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