IEMInternal.h@ 105284

Last change on this file since 105284 was 105284, checked in by vboxsync, 5 months ago
VMM/IEM: Large page TLB optimizations for INVLPG. bugref:10687
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 336.2 KB

Line
1	/* $Id: IEMInternal.h 105284 2024-07-12 00:14:36Z vboxsync $ */
2	/** @file
3	* IEM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2011-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_IEMInternal_h
29	#define VMM_INCLUDED_SRC_include_IEMInternal_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#ifndef RT_IN_ASSEMBLER
35	# include <VBox/vmm/cpum.h>
36	# include <VBox/vmm/iem.h>
37	# include <VBox/vmm/pgm.h>
38	# include <VBox/vmm/stam.h>
39	# include <VBox/param.h>
40
41	# include <iprt/setjmp-without-sigmask.h>
42	# include <iprt/list.h>
43	#endif /* !RT_IN_ASSEMBLER */
44
45
46	RT_C_DECLS_BEGIN
47
48
49	/** @defgroup grp_iem_int Internals
50	* @ingroup grp_iem
51	* @internal
52	* @{
53	*/
54
55	/* Make doxygen happy w/o overcomplicating the #if checks. */
56	#ifdef DOXYGEN_RUNNING
57	# define IEM_WITH_THROW_CATCH
58	# define VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
59	#endif
60
61	/** For expanding symbol in slickedit and other products tagging and
62	* crossreferencing IEM symbols. */
63	#ifndef IEM_STATIC
64	# define IEM_STATIC static
65	#endif
66
67	/** @def IEM_WITH_SETJMP
68	* Enables alternative status code handling using setjmps.
69	*
70	* This adds a bit of expense via the setjmp() call since it saves all the
71	* non-volatile registers. However, it eliminates return code checks and allows
72	* for more optimal return value passing (return regs instead of stack buffer).
73	*/
74	#if defined(DOXYGEN_RUNNING) \|\| defined(RT_OS_WINDOWS) \|\| 1
75	# define IEM_WITH_SETJMP
76	#endif
77
78	/** @def IEM_WITH_THROW_CATCH
79	* Enables using C++ throw/catch as an alternative to setjmp/longjmp in user
80	* mode code when IEM_WITH_SETJMP is in effect.
81	*
82	* With GCC 11.3.1 and code TLB on linux, using throw/catch instead of
83	* setjmp/long resulted in bs2-test-1 running 3.00% faster and all but on test
84	* result value improving by more than 1%. (Best out of three.)
85	*
86	* With Visual C++ 2019 and code TLB on windows, using throw/catch instead of
87	* setjmp/long resulted in bs2-test-1 running 3.68% faster and all but some of
88	* the MMIO and CPUID tests ran noticeably faster. Variation is greater than on
89	* Linux, but it should be quite a bit faster for normal code.
90	*/
91	#if defined(__cplusplus) && defined(IEM_WITH_SETJMP) && defined(IN_RING3) && (defined(__GNUC__) \|\| defined(_MSC_VER)) /* ASM-NOINC-START */
92	# define IEM_WITH_THROW_CATCH
93	#endif /ASM-NOINC-END/
94
95	/** @def IEMNATIVE_WITH_DELAYED_PC_UPDATING
96	* Enables the delayed PC updating optimization (see @bugref{10373}).
97	*/
98	#if defined(DOXYGEN_RUNNING) \|\| 1
99	# define IEMNATIVE_WITH_DELAYED_PC_UPDATING
100	#endif
101
102	/** Enables the SIMD register allocator @bugref{10614}. */
103	#if defined(DOXYGEN_RUNNING) \|\| 1
104	# define IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
105	#endif
106	/** Enables access to even callee saved registers. */
107	//# define IEMNATIVE_WITH_SIMD_REG_ACCESS_ALL_REGISTERS
108
109	#if defined(DOXYGEN_RUNNING) \|\| 1
110	/** @def IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
111	* Delay the writeback or dirty registers as long as possible. */
112	# define IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
113	#endif
114
115	/** @def IEM_WITH_TLB_STATISTICS
116	* Enables all TLB statistics. */
117	#if defined(VBOX_WITH_STATISTICS) \|\| defined(DOXYGEN_RUNNING)
118	# define IEM_WITH_TLB_STATISTICS
119	#endif
120
121	/** @def VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
122	* Enables a quicker alternative to throw/longjmp for IEM_DO_LONGJMP when
123	* executing native translation blocks.
124	*
125	* This exploits the fact that we save all non-volatile registers in the TB
126	* prologue and thus just need to do the same as the TB epilogue to get the
127	* effect of a longjmp/throw. Since MSC marks XMM6 thru XMM15 as
128	* non-volatile (and does something even more crazy for ARM), this probably
129	* won't work reliably on Windows. */
130	#ifdef RT_ARCH_ARM64
131	# ifndef RT_OS_WINDOWS
132	# define VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
133	# endif
134	#endif
135	/* ASM-NOINC-START */
136	#ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
137	# if !defined(IN_RING3) \
138	\|\| !defined(VBOX_WITH_IEM_RECOMPILER) \
139	\|\| !defined(VBOX_WITH_IEM_NATIVE_RECOMPILER)
140	# undef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
141	# elif defined(RT_OS_WINDOWS)
142	# pragma message("VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP is not safe to use on windows")
143	# endif
144	#endif
145
146
147	/** @def IEM_DO_LONGJMP
148	*
149	* Wrapper around longjmp / throw.
150	*
151	* @param a_pVCpu The CPU handle.
152	* @param a_rc The status code jump back with / throw.
153	*/
154	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
155	# ifdef IEM_WITH_THROW_CATCH
156	# ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
157	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) do { \
158	if ((a_pVCpu)->iem.s.pvTbFramePointerR3) \
159	iemNativeTbLongJmp((a_pVCpu)->iem.s.pvTbFramePointerR3, (a_rc)); \
160	throw int(a_rc); \
161	} while (0)
162	# else
163	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) throw int(a_rc)
164	# endif
165	# else
166	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) longjmp(*(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf), (a_rc))
167	# endif
168	#endif
169
170	/** For use with IEM function that may do a longjmp (when enabled).
171	*
172	* Visual C++ has trouble longjmp'ing from/over functions with the noexcept
173	* attribute. So, we indicate that function that may be part of a longjmp may
174	* throw "exceptions" and that the compiler should definitely not generate and
175	* std::terminate calling unwind code.
176	*
177	* Here is one example of this ending in std::terminate:
178	* @code{.txt}
179	00 00000041`cadfda10 00007ffc`5d5a1f9f ucrtbase!abort+0x4e
180	01 00000041`cadfda40 00007ffc`57af229a ucrtbase!terminate+0x1f
181	02 00000041`cadfda70 00007ffb`eec91030 VCRUNTIME140!__std_terminate+0xa [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\ehhelpers.cpp @ 192]
182	03 00000041`cadfdaa0 00007ffb`eec92c6d VCRUNTIME140_1!_CallSettingFrame+0x20 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\handlers.asm @ 50]
183	04 00000041`cadfdad0 00007ffb`eec93ae5 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToState+0x241 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 1085]
184	05 00000041`cadfdc00 00007ffb`eec92258 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToEmptyState+0x2d [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 218]
185	06 00000041`cadfdc30 00007ffb`eec940e9 VCRUNTIME140_1!__InternalCxxFrameHandler<__FrameHandler4>+0x194 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 304]
186	07 00000041`cadfdcd0 00007ffc`5f9f249f VCRUNTIME140_1!__CxxFrameHandler4+0xa9 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 290]
187	08 00000041`cadfdd40 00007ffc`5f980939 ntdll!RtlpExecuteHandlerForUnwind+0xf
188	09 00000041`cadfdd70 00007ffc`5f9a0edd ntdll!RtlUnwindEx+0x339
189	0a 00000041`cadfe490 00007ffc`57aff976 ntdll!RtlUnwind+0xcd
190	0b 00000041`cadfea00 00007ffb`e1b5de01 VCRUNTIME140!__longjmp_internal+0xe6 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\longjmp.asm @ 140]
191	0c (Inline Function) --------`-------- VBoxVMM!iemOpcodeGetNextU8SlowJmp+0x95 [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 1155]
192	0d 00000041`cadfea50 00007ffb`e1b60f6b VBoxVMM!iemOpcodeGetNextU8Jmp+0xc1 [L:\vbox-intern\src\VBox\VMM\include\IEMInline.h @ 402]
193	0e 00000041`cadfea90 00007ffb`e1cc6201 VBoxVMM!IEMExecForExits+0xdb [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 10185]
194	0f 00000041`cadfec70 00007ffb`e1d0df8d VBoxVMM!EMHistoryExec+0x4f1 [L:\vbox-intern\src\VBox\VMM\VMMAll\EMAll.cpp @ 452]
195	10 00000041`cadfed60 00007ffb`e1d0d4c0 VBoxVMM!nemR3WinHandleExitCpuId+0x79d [L:\vbox-intern\src\VBox\VMM\VMMAll\NEMAllNativeTemplate-win.cpp.h @ 1829] @encode
196	@endcode
197	*
198	* @see https://developercommunity.visualstudio.com/t/fragile-behavior-of-longjmp-called-from-noexcept-f/1532859
199	*/
200	#if defined(IEM_WITH_SETJMP) && (defined(_MSC_VER) \|\| defined(IEM_WITH_THROW_CATCH))
201	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT_EX(false)
202	#else
203	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT
204	#endif
205	/* ASM-NOINC-END */
206
207	#define IEM_IMPLEMENTS_TASKSWITCH
208
209	/** @def IEM_WITH_3DNOW
210	* Includes the 3DNow decoding. */
211	#if !defined(IEM_WITH_3DNOW) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
212	# ifndef IEM_WITHOUT_3DNOW
213	# define IEM_WITH_3DNOW
214	# endif
215	#endif
216
217	/** @def IEM_WITH_THREE_0F_38
218	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
219	#if !defined(IEM_WITH_THREE_0F_38) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
220	# ifndef IEM_WITHOUT_THREE_0F_38
221	# define IEM_WITH_THREE_0F_38
222	# endif
223	#endif
224
225	/** @def IEM_WITH_THREE_0F_3A
226	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
227	#if !defined(IEM_WITH_THREE_0F_3A) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
228	# ifndef IEM_WITHOUT_THREE_0F_3A
229	# define IEM_WITH_THREE_0F_3A
230	# endif
231	#endif
232
233	/** @def IEM_WITH_VEX
234	* Includes the VEX decoding. */
235	#if !defined(IEM_WITH_VEX) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
236	# ifndef IEM_WITHOUT_VEX
237	# define IEM_WITH_VEX
238	# endif
239	#endif
240
241	/** @def IEM_CFG_TARGET_CPU
242	* The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
243	*
244	* By default we allow this to be configured by the user via the
245	* CPUM/GuestCpuName config string, but this comes at a slight cost during
246	* decoding. So, for applications of this code where there is no need to
247	* be dynamic wrt target CPU, just modify this define.
248	*/
249	#if !defined(IEM_CFG_TARGET_CPU) \|\| defined(DOXYGEN_RUNNING)
250	# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
251	#endif
252
253	//#define IEM_WITH_CODE_TLB // - work in progress
254	//#define IEM_WITH_DATA_TLB // - work in progress
255
256
257	/** @def IEM_USE_UNALIGNED_DATA_ACCESS
258	* Use unaligned accesses instead of elaborate byte assembly. */
259	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86) \|\| defined(DOXYGEN_RUNNING) /ASM-NOINC/
260	# define IEM_USE_UNALIGNED_DATA_ACCESS
261	#endif /ASM-NOINC/
262
263	//#define IEM_LOG_MEMORY_WRITES
264
265
266
267	#ifndef RT_IN_ASSEMBLER /* ASM-NOINC-START - the rest of the file */
268
269	# if !defined(IEM_WITHOUT_INSTRUCTION_STATS) && !defined(DOXYGEN_RUNNING)
270	/** Instruction statistics. */
271	typedef struct IEMINSTRSTATS
272	{
273	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
274	# include "IEMInstructionStatisticsTmpl.h"
275	# undef IEM_DO_INSTR_STAT
276	} IEMINSTRSTATS;
277	#else
278	struct IEMINSTRSTATS;
279	typedef struct IEMINSTRSTATS IEMINSTRSTATS;
280	#endif
281	/** Pointer to IEM instruction statistics. */
282	typedef IEMINSTRSTATS *PIEMINSTRSTATS;
283
284
285	/** @name IEMTARGETCPU_EFL_BEHAVIOR_XXX - IEMCPU::aidxTargetCpuEflFlavour
286	* @{ */
287	#define IEMTARGETCPU_EFL_BEHAVIOR_NATIVE 0 /*< Native x86 EFLAGS result; Intel EFLAGS when on non-x86 hosts. /
288	#define IEMTARGETCPU_EFL_BEHAVIOR_INTEL 1 /*< Intel EFLAGS result. /
289	#define IEMTARGETCPU_EFL_BEHAVIOR_AMD 2 /*< AMD EFLAGS result /
290	#define IEMTARGETCPU_EFL_BEHAVIOR_RESERVED 3 /*< Reserved/dummy entry slot that's the same as 0. /
291	#define IEMTARGETCPU_EFL_BEHAVIOR_MASK 3 /*< For masking the index before use. /
292	/** Selects the right variant from a_aArray.
293	* pVCpu is implicit in the caller context. */
294	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT(a_aArray) \
295	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[1] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
296	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for when no native worker can
297	* be used because the host CPU does not support the operation. */
298	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_NON_NATIVE(a_aArray) \
299	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
300	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for a two dimentional
301	* array paralleling IEMCPU::aidxTargetCpuEflFlavour and a single bit index
302	* into the two.
303	* @sa IEM_SELECT_NATIVE_OR_FALLBACK */
304	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
305	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
306	(a_aaArray[a_fNative][pVCpu->iem.s.aidxTargetCpuEflFlavour[a_fNative] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
307	#else
308	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
309	(a_aaArray[0][pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
310	#endif
311	/** @} */
312
313	/**
314	* Picks @a a_pfnNative or @a a_pfnFallback according to the host CPU feature
315	* indicator given by @a a_fCpumFeatureMember (CPUMFEATURES member).
316	*
317	* On non-x86 hosts, this will shortcut to the fallback w/o checking the
318	* indicator.
319	*
320	* @sa IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX
321	*/
322	#if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
323	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) \
324	(g_CpumHostFeatures.s.a_fCpumFeatureMember ? a_pfnNative : a_pfnFallback)
325	#else
326	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) (a_pfnFallback)
327	#endif
328
329
330	/**
331	* Branch types.
332	*/
333	typedef enum IEMBRANCH
334	{
335	IEMBRANCH_JUMP = 1,
336	IEMBRANCH_CALL,
337	IEMBRANCH_TRAP,
338	IEMBRANCH_SOFTWARE_INT,
339	IEMBRANCH_HARDWARE_INT
340	} IEMBRANCH;
341	AssertCompileSize(IEMBRANCH, 4);
342
343
344	/**
345	* INT instruction types.
346	*/
347	typedef enum IEMINT
348	{
349	/** INT n instruction (opcode 0xcd imm). */
350	IEMINT_INTN = 0,
351	/** Single byte INT3 instruction (opcode 0xcc). */
352	IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
353	/** Single byte INTO instruction (opcode 0xce). */
354	IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
355	/** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
356	IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
357	} IEMINT;
358	AssertCompileSize(IEMINT, 4);
359
360
361	/**
362	* A FPU result.
363	*/
364	typedef struct IEMFPURESULT
365	{
366	/** The output value. */
367	RTFLOAT80U r80Result;
368	/** The output status. */
369	uint16_t FSW;
370	} IEMFPURESULT;
371	AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
372	/** Pointer to a FPU result. */
373	typedef IEMFPURESULT *PIEMFPURESULT;
374	/** Pointer to a const FPU result. */
375	typedef IEMFPURESULT const *PCIEMFPURESULT;
376
377
378	/**
379	* A FPU result consisting of two output values and FSW.
380	*/
381	typedef struct IEMFPURESULTTWO
382	{
383	/** The first output value. */
384	RTFLOAT80U r80Result1;
385	/** The output status. */
386	uint16_t FSW;
387	/** The second output value. */
388	RTFLOAT80U r80Result2;
389	} IEMFPURESULTTWO;
390	AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
391	AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
392	/** Pointer to a FPU result consisting of two output values and FSW. */
393	typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
394	/** Pointer to a const FPU result consisting of two output values and FSW. */
395	typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
396
397
398	/**
399	* IEM TLB entry.
400	*
401	* Lookup assembly:
402	* @code{.asm}
403	; Calculate tag.
404	mov rax, [VA]
405	shl rax, 16
406	shr rax, 16 + X86_PAGE_SHIFT
407	or rax, [uTlbRevision]
408
409	; Do indexing.
410	movzx ecx, al
411	lea rcx, [pTlbEntries + rcx]
412
413	; Check tag.
414	cmp [rcx + IEMTLBENTRY.uTag], rax
415	jne .TlbMiss
416
417	; Check access.
418	mov rax, ACCESS_FLAGS \| MAPPING_R3_NOT_VALID \| 0xffffff00
419	and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
420	cmp rax, [uTlbPhysRev]
421	jne .TlbMiss
422
423	; Calc address and we're done.
424	mov eax, X86_PAGE_OFFSET_MASK
425	and eax, [VA]
426	or rax, [rcx + IEMTLBENTRY.pMappingR3]
427	%ifdef VBOX_WITH_STATISTICS
428	inc qword [cTlbHits]
429	%endif
430	jmp .Done
431
432	.TlbMiss:
433	mov r8d, ACCESS_FLAGS
434	mov rdx, [VA]
435	mov rcx, [pVCpu]
436	call iemTlbTypeMiss
437	.Done:
438
439	@endcode
440	*
441	*/
442	typedef struct IEMTLBENTRY
443	{
444	/** The TLB entry tag.
445	* Bits 35 thru 0 are made up of the virtual address shifted right 12 bits, this
446	* is ASSUMING a virtual address width of 48 bits.
447	*
448	* Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
449	*
450	* The TLB lookup code uses the current TLB revision, which won't ever be zero,
451	* enabling an extremely cheap TLB invalidation most of the time. When the TLB
452	* revision wraps around though, the tags needs to be zeroed.
453	*
454	* @note Try use SHRD instruction? After seeing
455	* https://gmplib.org/~tege/x86-timing.pdf, maybe not.
456	*
457	* @todo This will need to be reorganized for 57-bit wide virtual address and
458	* PCID (currently 12 bits) and ASID (currently 6 bits) support. We'll
459	* have to move the TLB entry versioning entirely to the
460	* fFlagsAndPhysRev member then, 57 bit wide VAs means we'll only have
461	* 19 bits left (64 - 57 + 12 = 19) and they'll almost entire be
462	* consumed by PCID and ASID (12 + 6 = 18).
463	*/
464	uint64_t uTag;
465	/** Access flags and physical TLB revision.
466	*
467	* - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
468	* - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
469	* - Bit 2 - page tables - not user (complemented X86_PTE_US).
470	* - Bit 3 - pgm phys/virt - not directly writable.
471	* - Bit 4 - pgm phys page - not directly readable.
472	* - Bit 5 - page tables - not accessed (complemented X86_PTE_A).
473	* - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
474	* - Bit 7 - tlb entry - pMappingR3 member not valid.
475	* - Bits 63 thru 8 are used for the physical TLB revision number.
476	*
477	* We're using complemented bit meanings here because it makes it easy to check
478	* whether special action is required. For instance a user mode write access
479	* would do a "TEST fFlags, (X86_PTE_RW \| X86_PTE_US \| X86_PTE_D)" and a
480	* non-zero result would mean special handling needed because either it wasn't
481	* writable, or it wasn't user, or the page wasn't dirty. A user mode read
482	* access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
483	* need to check any PTE flag.
484	*/
485	uint64_t fFlagsAndPhysRev;
486	/** The guest physical page address. */
487	uint64_t GCPhys;
488	/** Pointer to the ring-3 mapping. */
489	R3PTRTYPE(uint8_t *) pbMappingR3;
490	#if HC_ARCH_BITS == 32
491	uint32_t u32Padding1;
492	#endif
493	} IEMTLBENTRY;
494	AssertCompileSize(IEMTLBENTRY, 32);
495	/** Pointer to an IEM TLB entry. */
496	typedef IEMTLBENTRY *PIEMTLBENTRY;
497	/** Pointer to a const IEM TLB entry. */
498	typedef IEMTLBENTRY const *PCIEMTLBENTRY;
499
500	/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
501	* @{ */
502	#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /*< Page tables: Not executable. /
503	#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /*< Page tables: Not writable. /
504	#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /*< Page tables: Not user accessible (supervisor only). /
505	#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /*< Phys page: Not writable (access handler, ROM, whatever). /
506	#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /*< Phys page: Not readable (MMIO / access handler, ROM) /
507	#define IEMTLBE_F_PT_NO_ACCESSED RT_BIT_64(5) /*< Phys tables: Not accessed (need to be marked accessed). /
508	#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /*< Page tables: Not dirty (needs to be made dirty on write). /
509	#define IEMTLBE_F_PT_LARGE_PAGE RT_BIT_64(7) /*< Page tables: Large 2 or 4 MiB page (for flushing). /
510	#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(8) /*< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. /
511	#define IEMTLBE_F_PG_UNASSIGNED RT_BIT_64(9) /*< Phys page: Unassigned memory (not RAM, ROM, MMIO2 or MMIO). /
512	#define IEMTLBE_F_PG_CODE_PAGE RT_BIT_64(10) /*< Phys page: Code page. /
513	#define IEMTLBE_F_PHYS_REV UINT64_C(0xfffffffffffff800) /*< Physical revision mask. @sa IEMTLB_PHYS_REV_INCR /
514	/** @} */
515	AssertCompile(PGMIEMGCPHYS2PTR_F_NO_WRITE == IEMTLBE_F_PG_NO_WRITE);
516	AssertCompile(PGMIEMGCPHYS2PTR_F_NO_READ == IEMTLBE_F_PG_NO_READ);
517	AssertCompile(PGMIEMGCPHYS2PTR_F_NO_MAPPINGR3 == IEMTLBE_F_NO_MAPPINGR3);
518	AssertCompile(PGMIEMGCPHYS2PTR_F_UNASSIGNED == IEMTLBE_F_PG_UNASSIGNED);
519	AssertCompile(PGMIEMGCPHYS2PTR_F_CODE_PAGE == IEMTLBE_F_PG_CODE_PAGE);
520	AssertCompile(PGM_WALKINFO_BIG_PAGE == IEMTLBE_F_PT_LARGE_PAGE);
521	/** The bits set by PGMPhysIemGCPhys2PtrNoLock. */
522	#define IEMTLBE_GCPHYS2PTR_MASK ( PGMIEMGCPHYS2PTR_F_NO_WRITE \
523	\| PGMIEMGCPHYS2PTR_F_NO_READ \
524	\| PGMIEMGCPHYS2PTR_F_NO_MAPPINGR3 \
525	\| PGMIEMGCPHYS2PTR_F_UNASSIGNED \
526	\| PGMIEMGCPHYS2PTR_F_CODE_PAGE \
527	\| IEMTLBE_F_PHYS_REV )
528
529	/** The TLB size (power of two).
530	* We initially chose 256 because that way we can obtain the result directly
531	* from a 8-bit register without an additional AND instruction.
532	* See also @bugref{10687}. */
533	#if defined(RT_ARCH_AMD64)
534	# define IEMTLB_ENTRY_COUNT 256
535	# define IEMTLB_ENTRY_COUNT_AS_POWER_OF_TWO 8
536	#else
537	# define IEMTLB_ENTRY_COUNT 8192
538	# define IEMTLB_ENTRY_COUNT_AS_POWER_OF_TWO 13
539	#endif
540	AssertCompile(RT_BIT_32(IEMTLB_ENTRY_COUNT_AS_POWER_OF_TWO) == IEMTLB_ENTRY_COUNT);
541
542	/**
543	* An IEM TLB.
544	*
545	* We've got two of these, one for data and one for instructions.
546	*/
547	typedef struct IEMTLB
548	{
549	/** The non-global TLB revision.
550	* This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
551	* by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
552	* the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
553	* (The revision zero indicates an invalid TLB entry.)
554	*
555	* The initial value is choosen to cause an early wraparound. */
556	uint64_t uTlbRevision;
557	/** The TLB physical address revision - shadow of PGM variable.
558	*
559	* This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
560	* incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
561	* a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
562	* as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
563	*
564	* The initial value is choosen to cause an early wraparound.
565	*
566	* @note This is placed between the two TLB revisions because we
567	* load it in pair with one or the other on arm64. */
568	uint64_t volatile uTlbPhysRev;
569	/** The global TLB revision.
570	* Same as uTlbRevision, but only increased for global flushes. */
571	uint64_t uTlbRevisionGlobal;
572
573	/** Large page tag range.
574	*
575	* This is used to avoid scanning a large page's worth of TLB entries for each
576	* INVLPG instruction, and only to do so iff we've loaded any and when the
577	* address is in this range. This is kept up to date when we loading new TLB
578	* entries.
579	*/
580	struct LARGEPAGERANGE
581	{
582	/** The lowest large page address tag, UINT64_MAX if none. */
583	uint64_t uFirstTag;
584	/** The highest large page address tag (with offset mask part set), 0 if none. */
585	uint64_t uLastTag;
586	}
587	/** Large page range for non-global pages. */
588	NonGlobalLargePageRange,
589	/** Large page range for global pages. */
590	GlobalLargePageRange;
591	/** Number of non-global entries for large pages loaded since last TLB flush. */
592	uint32_t cTlbNonGlobalLargePageCurLoads;
593	/** Number of global entries for large pages loaded since last TLB flush. */
594	uint32_t cTlbGlobalLargePageCurLoads;
595
596	/* Statistics: */
597
598	/** TLB hits in IEMAll.cpp code (IEM_WITH_TLB_STATISTICS only; both).
599	* @note For the data TLB this is only used in iemMemMap and and for direct (i.e.
600	* not via safe read/write path) calls to iemMemMapJmp. */
601	uint64_t cTlbCoreHits;
602	/** Safe read/write TLB hits in iemMemMapJmp (IEM_WITH_TLB_STATISTICS
603	* only; data tlb only). */
604	uint64_t cTlbSafeHits;
605	/** TLB hits in IEMAllMemRWTmplInline.cpp.h (data + IEM_WITH_TLB_STATISTICS only). */
606	uint64_t cTlbInlineCodeHits;
607
608	/** TLB misses in IEMAll.cpp code (both).
609	* @note For the data TLB this is only used in iemMemMap and for direct (i.e.
610	* not via safe read/write path) calls to iemMemMapJmp. So,
611	* for the data TLB this more like 'other misses', while for the code
612	* TLB is all misses. */
613	uint64_t cTlbCoreMisses;
614	/** Subset of cTlbCoreMisses that results in PTE.G=1 loads (odd entries). */
615	uint64_t cTlbCoreGlobalLoads;
616	/** Safe read/write TLB misses in iemMemMapJmp (so data only). */
617	uint64_t cTlbSafeMisses;
618	/** Subset of cTlbSafeMisses that results in PTE.G=1 loads (odd entries). */
619	uint64_t cTlbSafeGlobalLoads;
620	/** Safe read path taken (data only). */
621	uint64_t cTlbSafeReadPath;
622	/** Safe write path taken (data only). */
623	uint64_t cTlbSafeWritePath;
624
625	/** @name Details for native code TLB misses.
626	* @note These counts are included in the above counters (cTlbSafeReadPath,
627	* cTlbSafeWritePath, cTlbInlineCodeHits).
628	* @{ */
629	/** TLB misses in native code due to tag mismatch. */
630	STAMCOUNTER cTlbNativeMissTag;
631	/** TLB misses in native code due to flags or physical revision mismatch. */
632	STAMCOUNTER cTlbNativeMissFlagsAndPhysRev;
633	/** TLB misses in native code due to misaligned access. */
634	STAMCOUNTER cTlbNativeMissAlignment;
635	/** TLB misses in native code due to cross page access. */
636	uint32_t cTlbNativeMissCrossPage;
637	/** TLB misses in native code due to non-canonical address. */
638	uint32_t cTlbNativeMissNonCanonical;
639	/** @} */
640
641	/** Slow read path (code only). */
642	uint32_t cTlbSlowCodeReadPath;
643
644	/** Regular TLB flush count. */
645	uint32_t cTlsFlushes;
646	/** Global TLB flush count. */
647	uint32_t cTlsGlobalFlushes;
648	/** Revision rollovers. */
649	uint32_t cTlbRevisionRollovers;
650	/** Physical revision flushes. */
651	uint32_t cTlbPhysRevFlushes;
652	/** Physical revision rollovers. */
653	uint32_t cTlbPhysRevRollovers;
654
655	/uint32_t au32Padding[2];/
656
657	/** The TLB entries.
658	* Even entries are for PTE.G=0 and uses uTlbRevision.
659	* Odd entries are for PTE.G=1 and uses uTlbRevisionGlobal. */
660	IEMTLBENTRY aEntries[IEMTLB_ENTRY_COUNT * 2];
661	} IEMTLB;
662	AssertCompileSizeAlignment(IEMTLB, 64);
663	/** IEMTLB::uTlbRevision increment. */
664	#define IEMTLB_REVISION_INCR RT_BIT_64(36)
665	/** IEMTLB::uTlbRevision mask. */
666	#define IEMTLB_REVISION_MASK (~(RT_BIT_64(36) - 1))
667	/** IEMTLB::uTlbPhysRev increment.
668	* @sa IEMTLBE_F_PHYS_REV */
669	#define IEMTLB_PHYS_REV_INCR RT_BIT_64(11)
670	AssertCompile(IEMTLBE_F_PHYS_REV == ~(IEMTLB_PHYS_REV_INCR - 1U));
671
672	/**
673	* Calculates the TLB tag for a virtual address but without TLB revision.
674	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
675	* @param a_GCPtr The virtual address. Must be RTGCPTR or same size or
676	* the clearing of the top 16 bits won't work (if 32-bit
677	* we'll end up with mostly zeros).
678	*/
679	#define IEMTLB_CALC_TAG_NO_REV(a_GCPtr) ( (((a_GCPtr) << 16) >> (GUEST_PAGE_SHIFT + 16)) )
680	/**
681	* Converts a TLB tag value into a even TLB index.
682	* @returns Index into IEMTLB::aEntries.
683	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
684	*/
685	#if IEMTLB_ENTRY_COUNT == 256
686	# define IEMTLB_TAG_TO_EVEN_INDEX(a_uTag) ( (uint8_t)(a_uTag) * 2U )
687	#else
688	# define IEMTLB_TAG_TO_EVEN_INDEX(a_uTag) ( ((a_uTag) & (IEMTLB_ENTRY_COUNT - 1U)) * 2U )
689	AssertCompile(RT_IS_POWER_OF_TWO(IEMTLB_ENTRY_COUNT));
690	#endif
691	/**
692	* Converts a TLB tag value into an even TLB index.
693	* @returns Pointer into IEMTLB::aEntries corresponding to .
694	* @param a_pTlb The TLB.
695	* @param a_uTag Value returned by IEMTLB_CALC_TAG or
696	* IEMTLB_CALC_TAG_NO_REV.
697	*/
698	#define IEMTLB_TAG_TO_EVEN_ENTRY(a_pTlb, a_uTag) ( &(a_pTlb)->aEntries[IEMTLB_TAG_TO_EVEN_INDEX(a_uTag)] )
699
700
701	/** @name IEM_MC_F_XXX - MC block flags/clues.
702	* @todo Merge with IEM_CIMPL_F_XXX
703	* @{ */
704	#define IEM_MC_F_ONLY_8086 RT_BIT_32(0)
705	#define IEM_MC_F_MIN_186 RT_BIT_32(1)
706	#define IEM_MC_F_MIN_286 RT_BIT_32(2)
707	#define IEM_MC_F_NOT_286_OR_OLDER IEM_MC_F_MIN_386
708	#define IEM_MC_F_MIN_386 RT_BIT_32(3)
709	#define IEM_MC_F_MIN_486 RT_BIT_32(4)
710	#define IEM_MC_F_MIN_PENTIUM RT_BIT_32(5)
711	#define IEM_MC_F_MIN_PENTIUM_II IEM_MC_F_MIN_PENTIUM
712	#define IEM_MC_F_MIN_CORE IEM_MC_F_MIN_PENTIUM
713	#define IEM_MC_F_64BIT RT_BIT_32(6)
714	#define IEM_MC_F_NOT_64BIT RT_BIT_32(7)
715	/** This is set by IEMAllN8vePython.py to indicate a variation without the
716	* flags-clearing-and-checking, when there is also a variation with that.
717	* @note Do not use this manully, it's only for python and for testing in
718	* the native recompiler! */
719	#define IEM_MC_F_WITHOUT_FLAGS RT_BIT_32(8)
720	/** @} */
721
722	/** @name IEM_CIMPL_F_XXX - State change clues for CIMPL calls.
723	*
724	* These clues are mainly for the recompiler, so that it can emit correct code.
725	*
726	* They are processed by the python script and which also automatically
727	* calculates flags for MC blocks based on the statements, extending the use of
728	* these flags to describe MC block behavior to the recompiler core. The python
729	* script pass the flags to the IEM_MC2_END_EMIT_CALLS macro, but mainly for
730	* error checking purposes. The script emits the necessary fEndTb = true and
731	* similar statements as this reduces compile time a tiny bit.
732	*
733	* @{ */
734	/** Flag set if direct branch, clear if absolute or indirect. */
735	#define IEM_CIMPL_F_BRANCH_DIRECT RT_BIT_32(0)
736	/** Flag set if indirect branch, clear if direct or relative.
737	* This is also used for all system control transfers (SYSCALL, SYSRET, INT, ++)
738	* as well as for return instructions (RET, IRET, RETF). */
739	#define IEM_CIMPL_F_BRANCH_INDIRECT RT_BIT_32(1)
740	/** Flag set if relative branch, clear if absolute or indirect. */
741	#define IEM_CIMPL_F_BRANCH_RELATIVE RT_BIT_32(2)
742	/** Flag set if conditional branch, clear if unconditional. */
743	#define IEM_CIMPL_F_BRANCH_CONDITIONAL RT_BIT_32(3)
744	/** Flag set if it's a far branch (changes CS). */
745	#define IEM_CIMPL_F_BRANCH_FAR RT_BIT_32(4)
746	/** Convenience: Testing any kind of branch. */
747	#define IEM_CIMPL_F_BRANCH_ANY (IEM_CIMPL_F_BRANCH_DIRECT \| IEM_CIMPL_F_BRANCH_INDIRECT \| IEM_CIMPL_F_BRANCH_RELATIVE)
748
749	/** Execution flags may change (IEMCPU::fExec). */
750	#define IEM_CIMPL_F_MODE RT_BIT_32(5)
751	/** May change significant portions of RFLAGS. */
752	#define IEM_CIMPL_F_RFLAGS RT_BIT_32(6)
753	/** May change the status bits (X86_EFL_STATUS_BITS) in RFLAGS. */
754	#define IEM_CIMPL_F_STATUS_FLAGS RT_BIT_32(7)
755	/** May trigger interrupt shadowing. */
756	#define IEM_CIMPL_F_INHIBIT_SHADOW RT_BIT_32(8)
757	/** May enable interrupts, so recheck IRQ immediately afterwards executing
758	* the instruction. */
759	#define IEM_CIMPL_F_CHECK_IRQ_AFTER RT_BIT_32(9)
760	/** May disable interrupts, so recheck IRQ immediately before executing the
761	* instruction. */
762	#define IEM_CIMPL_F_CHECK_IRQ_BEFORE RT_BIT_32(10)
763	/** Convenience: Check for IRQ both before and after an instruction. */
764	#define IEM_CIMPL_F_CHECK_IRQ_BEFORE_AND_AFTER (IEM_CIMPL_F_CHECK_IRQ_BEFORE \| IEM_CIMPL_F_CHECK_IRQ_AFTER)
765	/** May trigger a VM exit (treated like IEM_CIMPL_F_MODE atm). */
766	#define IEM_CIMPL_F_VMEXIT RT_BIT_32(11)
767	/** May modify FPU state.
768	* @todo Not sure if this is useful yet. */
769	#define IEM_CIMPL_F_FPU RT_BIT_32(12)
770	/** REP prefixed instruction which may yield before updating PC.
771	* @todo Not sure if this is useful, REP functions now return non-zero
772	* status if they don't update the PC. */
773	#define IEM_CIMPL_F_REP RT_BIT_32(13)
774	/** I/O instruction.
775	* @todo Not sure if this is useful yet. */
776	#define IEM_CIMPL_F_IO RT_BIT_32(14)
777	/** Force end of TB after the instruction. */
778	#define IEM_CIMPL_F_END_TB RT_BIT_32(15)
779	/** Flag set if a branch may also modify the stack (push/pop return address). */
780	#define IEM_CIMPL_F_BRANCH_STACK RT_BIT_32(16)
781	/** Flag set if a branch may also modify the stack (push/pop return address)
782	* and switch it (load/restore SS:RSP). */
783	#define IEM_CIMPL_F_BRANCH_STACK_FAR RT_BIT_32(17)
784	/** Convenience: Raise exception (technically unnecessary, since it shouldn't return VINF_SUCCESS). */
785	#define IEM_CIMPL_F_XCPT \
786	(IEM_CIMPL_F_BRANCH_INDIRECT \| IEM_CIMPL_F_BRANCH_FAR \| IEM_CIMPL_F_BRANCH_STACK_FAR \
787	\| IEM_CIMPL_F_MODE \| IEM_CIMPL_F_RFLAGS \| IEM_CIMPL_F_VMEXIT)
788
789	/** The block calls a C-implementation instruction function with two implicit arguments.
790	* Mutually exclusive with IEM_CIMPL_F_CALLS_AIMPL and
791	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
792	* @note The python scripts will add this if missing. */
793	#define IEM_CIMPL_F_CALLS_CIMPL RT_BIT_32(18)
794	/** The block calls an ASM-implementation instruction function.
795	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL and
796	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
797	* @note The python scripts will add this if missing. */
798	#define IEM_CIMPL_F_CALLS_AIMPL RT_BIT_32(19)
799	/** The block calls an ASM-implementation instruction function with an implicit
800	* X86FXSTATE pointer argument.
801	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL, IEM_CIMPL_F_CALLS_AIMPL and
802	* IEM_CIMPL_F_CALLS_AIMPL_WITH_XSTATE.
803	* @note The python scripts will add this if missing. */
804	#define IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE RT_BIT_32(20)
805	/** The block calls an ASM-implementation instruction function with an implicit
806	* X86XSAVEAREA pointer argument.
807	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL, IEM_CIMPL_F_CALLS_AIMPL and
808	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
809	* @note No different from IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE, so same value.
810	* @note The python scripts will add this if missing. */
811	#define IEM_CIMPL_F_CALLS_AIMPL_WITH_XSTATE IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE
812	/** @} */
813
814
815	/** @name IEM_F_XXX - Execution mode flags (IEMCPU::fExec, IEMTB::fFlags).
816	*
817	* These flags are set when entering IEM and adjusted as code is executed, such
818	* that they will always contain the current values as instructions are
819	* finished.
820	*
821	* In recompiled execution mode, (most of) these flags are included in the
822	* translation block selection key and stored in IEMTB::fFlags alongside the
823	* IEMTB_F_XXX flags. The latter flags uses bits 31 thru 24, which are all zero
824	* in IEMCPU::fExec.
825	*
826	* @{ */
827	/** Mode: The block target mode mask. */
828	#define IEM_F_MODE_MASK UINT32_C(0x0000001f)
829	/** Mode: The IEMMODE part of the IEMTB_F_MODE_MASK value. */
830	#define IEM_F_MODE_CPUMODE_MASK UINT32_C(0x00000003)
831	/** X86 Mode: Bit used to indicating pre-386 CPU in 16-bit mode (for eliminating
832	* conditional in EIP/IP updating), and flat wide open CS, SS, DS, and ES in
833	* 32-bit mode (for simplifying most memory accesses). */
834	#define IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK UINT32_C(0x00000004)
835	/** X86 Mode: Bit indicating protected mode, real mode (or SMM) when not set. */
836	#define IEM_F_MODE_X86_PROT_MASK UINT32_C(0x00000008)
837	/** X86 Mode: Bit used to indicate virtual 8086 mode (only 16-bit). */
838	#define IEM_F_MODE_X86_V86_MASK UINT32_C(0x00000010)
839
840	/** X86 Mode: 16-bit on 386 or later. */
841	#define IEM_F_MODE_X86_16BIT UINT32_C(0x00000000)
842	/** X86 Mode: 80286, 80186 and 8086/88 targetting blocks (EIP update opt). */
843	#define IEM_F_MODE_X86_16BIT_PRE_386 UINT32_C(0x00000004)
844	/** X86 Mode: 16-bit protected mode on 386 or later. */
845	#define IEM_F_MODE_X86_16BIT_PROT UINT32_C(0x00000008)
846	/** X86 Mode: 16-bit protected mode on 386 or later. */
847	#define IEM_F_MODE_X86_16BIT_PROT_PRE_386 UINT32_C(0x0000000c)
848	/** X86 Mode: 16-bit virtual 8086 protected mode (on 386 or later). */
849	#define IEM_F_MODE_X86_16BIT_PROT_V86 UINT32_C(0x00000018)
850
851	/** X86 Mode: 32-bit on 386 or later. */
852	#define IEM_F_MODE_X86_32BIT UINT32_C(0x00000001)
853	/** X86 Mode: 32-bit mode with wide open flat CS, SS, DS and ES. */
854	#define IEM_F_MODE_X86_32BIT_FLAT UINT32_C(0x00000005)
855	/** X86 Mode: 32-bit protected mode. */
856	#define IEM_F_MODE_X86_32BIT_PROT UINT32_C(0x00000009)
857	/** X86 Mode: 32-bit protected mode with wide open flat CS, SS, DS and ES. */
858	#define IEM_F_MODE_X86_32BIT_PROT_FLAT UINT32_C(0x0000000d)
859
860	/** X86 Mode: 64-bit (includes protected, but not the flat bit). */
861	#define IEM_F_MODE_X86_64BIT UINT32_C(0x0000000a)
862
863	/** X86 Mode: Checks if @a a_fExec represent a FLAT mode. */
864	#define IEM_F_MODE_X86_IS_FLAT(a_fExec) ( ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_64BIT \
865	\|\| ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_32BIT_PROT_FLAT \
866	\|\| ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_32BIT_FLAT)
867
868	/** Bypass access handlers when set. */
869	#define IEM_F_BYPASS_HANDLERS UINT32_C(0x00010000)
870	/** Have pending hardware instruction breakpoints. */
871	#define IEM_F_PENDING_BRK_INSTR UINT32_C(0x00020000)
872	/** Have pending hardware data breakpoints. */
873	#define IEM_F_PENDING_BRK_DATA UINT32_C(0x00040000)
874
875	/** X86: Have pending hardware I/O breakpoints. */
876	#define IEM_F_PENDING_BRK_X86_IO UINT32_C(0x00000400)
877	/** X86: Disregard the lock prefix (implied or not) when set. */
878	#define IEM_F_X86_DISREGARD_LOCK UINT32_C(0x00000800)
879
880	/** Pending breakpoint mask (what iemCalcExecDbgFlags works out). */
881	#define IEM_F_PENDING_BRK_MASK (IEM_F_PENDING_BRK_INSTR \| IEM_F_PENDING_BRK_DATA \| IEM_F_PENDING_BRK_X86_IO)
882
883	/** Caller configurable options. */
884	#define IEM_F_USER_OPTS (IEM_F_BYPASS_HANDLERS \| IEM_F_X86_DISREGARD_LOCK)
885
886	/** X86: The current protection level (CPL) shift factor. */
887	#define IEM_F_X86_CPL_SHIFT 8
888	/** X86: The current protection level (CPL) mask. */
889	#define IEM_F_X86_CPL_MASK UINT32_C(0x00000300)
890	/** X86: The current protection level (CPL) shifted mask. */
891	#define IEM_F_X86_CPL_SMASK UINT32_C(0x00000003)
892
893	/** X86: Alignment checks enabled (CR0.AM=1 & EFLAGS.AC=1). */
894	#define IEM_F_X86_AC UINT32_C(0x00080000)
895
896	/** X86 execution context.
897	* The IEM_F_X86_CTX_XXX values are individual flags that can be combined (with
898	* the exception of IEM_F_X86_CTX_NORMAL). This allows running VMs from SMM
899	* mode. */
900	#define IEM_F_X86_CTX_MASK UINT32_C(0x0000f000)
901	/** X86 context: Plain regular execution context. */
902	#define IEM_F_X86_CTX_NORMAL UINT32_C(0x00000000)
903	/** X86 context: VT-x enabled. */
904	#define IEM_F_X86_CTX_VMX UINT32_C(0x00001000)
905	/** X86 context: AMD-V enabled. */
906	#define IEM_F_X86_CTX_SVM UINT32_C(0x00002000)
907	/** X86 context: In AMD-V or VT-x guest mode. */
908	#define IEM_F_X86_CTX_IN_GUEST UINT32_C(0x00004000)
909	/** X86 context: System management mode (SMM). */
910	#define IEM_F_X86_CTX_SMM UINT32_C(0x00008000)
911
912	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
913	* iemRegFinishClearingRF() most for most situations (CPUMCTX_DBG_HIT_DRX_MASK
914	* and CPUMCTX_DBG_DBGF_MASK are covered by the IEM_F_PENDING_BRK_XXX bits
915	* alread). */
916
917	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
918	* iemRegFinishClearingRF() most for most situations
919	* (CPUMCTX_DBG_HIT_DRX_MASK and CPUMCTX_DBG_DBGF_MASK are covered by
920	* the IEM_F_PENDING_BRK_XXX bits alread). */
921
922	/** @} */
923
924
925	/** @name IEMTB_F_XXX - Translation block flags (IEMTB::fFlags).
926	*
927	* Extends the IEM_F_XXX flags (subject to IEMTB_F_IEM_F_MASK) to make up the
928	* translation block flags. The combined flag mask (subject to
929	* IEMTB_F_KEY_MASK) is used as part of the lookup key for translation blocks.
930	*
931	* @{ */
932	/** Mask of IEM_F_XXX flags included in IEMTB_F_XXX. */
933	#define IEMTB_F_IEM_F_MASK UINT32_C(0x00ffffff)
934
935	/** Type: The block type mask. */
936	#define IEMTB_F_TYPE_MASK UINT32_C(0x03000000)
937	/** Type: Purly threaded recompiler (via tables). */
938	#define IEMTB_F_TYPE_THREADED UINT32_C(0x01000000)
939	/** Type: Native recompilation. */
940	#define IEMTB_F_TYPE_NATIVE UINT32_C(0x02000000)
941
942	/** Set when we're starting the block in an "interrupt shadow".
943	* We don't need to distingish between the two types of this mask, thus the one.
944	* @see CPUMCTX_INHIBIT_SHADOW, CPUMIsInInterruptShadow() */
945	#define IEMTB_F_INHIBIT_SHADOW UINT32_C(0x04000000)
946	/** Set when we're currently inhibiting NMIs
947	* @see CPUMCTX_INHIBIT_NMI, CPUMAreInterruptsInhibitedByNmi() */
948	#define IEMTB_F_INHIBIT_NMI UINT32_C(0x08000000)
949
950	/** Checks that EIP/IP is wihin CS.LIM before each instruction. Used when
951	* we're close the limit before starting a TB, as determined by
952	* iemGetTbFlagsForCurrentPc(). */
953	#define IEMTB_F_CS_LIM_CHECKS UINT32_C(0x10000000)
954
955	/** Mask of the IEMTB_F_XXX flags that are part of the TB lookup key.
956	*
957	* @note We skip all of IEM_F_X86_CTX_MASK, with the exception of SMM (which we
958	* don't implement), because we don't currently generate any context
959	* specific code - that's all handled in CIMPL functions.
960	*
961	* For the threaded recompiler we don't generate any CPL specific code
962	* either, but the native recompiler does for memory access (saves getting
963	* the CPL from fExec and turning it into IEMTLBE_F_PT_NO_USER).
964	* Since most OSes will not share code between rings, this shouldn't
965	* have any real effect on TB/memory/recompiling load.
966	*/
967	#define IEMTB_F_KEY_MASK ((UINT32_MAX & ~(IEM_F_X86_CTX_MASK \| IEMTB_F_TYPE_MASK)) \| IEM_F_X86_CTX_SMM)
968	/** @} */
969
970	AssertCompile( (IEM_F_MODE_X86_16BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
971	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
972	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_PROT_MASK));
973	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_V86_MASK));
974	AssertCompile( (IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
975	AssertCompile( IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
976	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_PROT_MASK));
977	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
978	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
979	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
980	AssertCompile( IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
981	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_V86_MASK));
982	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
983	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
984	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_PROT_MASK);
985	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
986	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_PROT_MASK);
987	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
988	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_V86_MASK);
989
990	AssertCompile( (IEM_F_MODE_X86_32BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
991	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
992	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_PROT_MASK));
993	AssertCompile( (IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
994	AssertCompile( IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
995	AssertCompile(!(IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_PROT_MASK));
996	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
997	AssertCompile(!(IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
998	AssertCompile( IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
999	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
1000	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
1001	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_PROT_MASK);
1002
1003	AssertCompile( (IEM_F_MODE_X86_64BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_64BIT);
1004	AssertCompile( IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_PROT_MASK);
1005	AssertCompile(!(IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
1006
1007	/** Native instruction type for use with the native code generator.
1008	* This is a byte (uint8_t) for x86 and amd64 and uint32_t for the other(s). */
1009	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
1010	typedef uint8_t IEMNATIVEINSTR;
1011	#else
1012	typedef uint32_t IEMNATIVEINSTR;
1013	#endif
1014	/** Pointer to a native instruction unit. */
1015	typedef IEMNATIVEINSTR *PIEMNATIVEINSTR;
1016	/** Pointer to a const native instruction unit. */
1017	typedef IEMNATIVEINSTR const *PCIEMNATIVEINSTR;
1018
1019	/**
1020	* A call for the threaded call table.
1021	*/
1022	typedef struct IEMTHRDEDCALLENTRY
1023	{
1024	/** The function to call (IEMTHREADEDFUNCS). */
1025	uint16_t enmFunction;
1026
1027	/** Instruction number in the TB (for statistics). */
1028	uint8_t idxInstr;
1029	/** The opcode length. */
1030	uint8_t cbOpcode;
1031	/** Offset into IEMTB::pabOpcodes. */
1032	uint16_t offOpcode;
1033
1034	/** TB lookup table index (7 bits) and large size (1 bits).
1035	*
1036	* The default size is 1 entry, but for indirect calls and returns we set the
1037	* top bit and allocate 4 (IEM_TB_LOOKUP_TAB_LARGE_SIZE) entries. The large
1038	* tables uses RIP for selecting the entry to use, as it is assumed a hash table
1039	* lookup isn't that slow compared to sequentially trying out 4 TBs.
1040	*
1041	* By default lookup table entry 0 for a TB is reserved as a fallback for
1042	* calltable entries w/o explicit entreis, so this member will be non-zero if
1043	* there is a lookup entry associated with this call.
1044	*
1045	* @sa IEM_TB_LOOKUP_TAB_GET_SIZE, IEM_TB_LOOKUP_TAB_GET_IDX
1046	*/
1047	uint8_t uTbLookup;
1048
1049	/** Unused atm. */
1050	uint8_t uUnused0;
1051
1052	/** Generic parameters. */
1053	uint64_t auParams[3];
1054	} IEMTHRDEDCALLENTRY;
1055	AssertCompileSize(IEMTHRDEDCALLENTRY, sizeof(uint64_t) * 4);
1056	/** Pointer to a threaded call entry. */
1057	typedef struct IEMTHRDEDCALLENTRY *PIEMTHRDEDCALLENTRY;
1058	/** Pointer to a const threaded call entry. */
1059	typedef IEMTHRDEDCALLENTRY const *PCIEMTHRDEDCALLENTRY;
1060
1061	/** The number of TB lookup table entries for a large allocation
1062	* (IEMTHRDEDCALLENTRY::uTbLookup bit 7 set). */
1063	#define IEM_TB_LOOKUP_TAB_LARGE_SIZE 4
1064	/** Get the lookup table size from IEMTHRDEDCALLENTRY::uTbLookup. */
1065	#define IEM_TB_LOOKUP_TAB_GET_SIZE(a_uTbLookup) (!((a_uTbLookup) & 0x80) ? 1 : IEM_TB_LOOKUP_TAB_LARGE_SIZE)
1066	/** Get the first lookup table index from IEMTHRDEDCALLENTRY::uTbLookup. */
1067	#define IEM_TB_LOOKUP_TAB_GET_IDX(a_uTbLookup) ((a_uTbLookup) & 0x7f)
1068	/** Get the lookup table index from IEMTHRDEDCALLENTRY::uTbLookup and RIP. */
1069	#define IEM_TB_LOOKUP_TAB_GET_IDX_WITH_RIP(a_uTbLookup, a_Rip) \
1070	(!((a_uTbLookup) & 0x80) ? (a_uTbLookup) & 0x7f : ((a_uTbLookup) & 0x7f) + ((a_Rip) & (IEM_TB_LOOKUP_TAB_LARGE_SIZE - 1)) )
1071
1072	/** Make a IEMTHRDEDCALLENTRY::uTbLookup value. */
1073	#define IEM_TB_LOOKUP_TAB_MAKE(a_idxTable, a_fLarge) ((a_idxTable) \| ((a_fLarge) ? 0x80 : 0))
1074
1075	/**
1076	* Native IEM TB 'function' typedef.
1077	*
1078	* This will throw/longjmp on occation.
1079	*
1080	* @note AMD64 doesn't have that many non-volatile registers and does sport
1081	* 32-bit address displacments, so we don't need pCtx.
1082	*
1083	* On ARM64 pCtx allows us to directly address the whole register
1084	* context without requiring a separate indexing register holding the
1085	* offset. This saves an instruction loading the offset for each guest
1086	* CPU context access, at the cost of a non-volatile register.
1087	* Fortunately, ARM64 has quite a lot more registers.
1088	*/
1089	typedef
1090	#ifdef RT_ARCH_AMD64
1091	int FNIEMTBNATIVE(PVMCPUCC pVCpu)
1092	#else
1093	int FNIEMTBNATIVE(PVMCPUCC pVCpu, PCPUMCTX pCtx)
1094	#endif
1095	#if RT_CPLUSPLUS_PREREQ(201700)
1096	IEM_NOEXCEPT_MAY_LONGJMP
1097	#endif
1098	;
1099	/** Pointer to a native IEM TB entry point function.
1100	* This will throw/longjmp on occation. */
1101	typedef FNIEMTBNATIVE *PFNIEMTBNATIVE;
1102
1103
1104	/**
1105	* Translation block debug info entry type.
1106	*/
1107	typedef enum IEMTBDBGENTRYTYPE
1108	{
1109	kIemTbDbgEntryType_Invalid = 0,
1110	/** The entry is for marking a native code position.
1111	* Entries following this all apply to this position. */
1112	kIemTbDbgEntryType_NativeOffset,
1113	/** The entry is for a new guest instruction. */
1114	kIemTbDbgEntryType_GuestInstruction,
1115	/** Marks the start of a threaded call. */
1116	kIemTbDbgEntryType_ThreadedCall,
1117	/** Marks the location of a label. */
1118	kIemTbDbgEntryType_Label,
1119	/** Info about a host register shadowing a guest register. */
1120	kIemTbDbgEntryType_GuestRegShadowing,
1121	#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
1122	/** Info about a host SIMD register shadowing a guest SIMD register. */
1123	kIemTbDbgEntryType_GuestSimdRegShadowing,
1124	#endif
1125	#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING
1126	/** Info about a delayed RIP update. */
1127	kIemTbDbgEntryType_DelayedPcUpdate,
1128	#endif
1129	#if defined(IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK) \|\| defined(IEMNATIVE_WITH_SIMD_REG_ALLOCATOR)
1130	/** Info about a shadowed guest register becoming dirty. */
1131	kIemTbDbgEntryType_GuestRegDirty,
1132	/** Info about register writeback/flush oepration. */
1133	kIemTbDbgEntryType_GuestRegWriteback,
1134	#endif
1135	kIemTbDbgEntryType_End
1136	} IEMTBDBGENTRYTYPE;
1137
1138	/**
1139	* Translation block debug info entry.
1140	*/
1141	typedef union IEMTBDBGENTRY
1142	{
1143	/** Plain 32-bit view. */
1144	uint32_t u;
1145
1146	/** Generic view for getting at the type field. */
1147	struct
1148	{
1149	/** IEMTBDBGENTRYTYPE */
1150	uint32_t uType : 4;
1151	uint32_t uTypeSpecific : 28;
1152	} Gen;
1153
1154	struct
1155	{
1156	/** kIemTbDbgEntryType_ThreadedCall1. */
1157	uint32_t uType : 4;
1158	/** Native code offset. */
1159	uint32_t offNative : 28;
1160	} NativeOffset;
1161
1162	struct
1163	{
1164	/** kIemTbDbgEntryType_GuestInstruction. */
1165	uint32_t uType : 4;
1166	uint32_t uUnused : 4;
1167	/** The IEM_F_XXX flags. */
1168	uint32_t fExec : 24;
1169	} GuestInstruction;
1170
1171	struct
1172	{
1173	/* kIemTbDbgEntryType_ThreadedCall. */
1174	uint32_t uType : 4;
1175	/** Set if the call was recompiled to native code, clear if just calling
1176	* threaded function. */
1177	uint32_t fRecompiled : 1;
1178	uint32_t uUnused : 11;
1179	/** The threaded call number (IEMTHREADEDFUNCS). */
1180	uint32_t enmCall : 16;
1181	} ThreadedCall;
1182
1183	struct
1184	{
1185	/* kIemTbDbgEntryType_Label. */
1186	uint32_t uType : 4;
1187	uint32_t uUnused : 4;
1188	/** The label type (IEMNATIVELABELTYPE). */
1189	uint32_t enmLabel : 8;
1190	/** The label data. */
1191	uint32_t uData : 16;
1192	} Label;
1193
1194	struct
1195	{
1196	/* kIemTbDbgEntryType_GuestRegShadowing. */
1197	uint32_t uType : 4;
1198	uint32_t uUnused : 4;
1199	/** The guest register being shadowed (IEMNATIVEGSTREG). */
1200	uint32_t idxGstReg : 8;
1201	/** The host new register number, UINT8_MAX if dropped. */
1202	uint32_t idxHstReg : 8;
1203	/** The previous host register number, UINT8_MAX if new. */
1204	uint32_t idxHstRegPrev : 8;
1205	} GuestRegShadowing;
1206
1207	#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
1208	struct
1209	{
1210	/* kIemTbDbgEntryType_GuestSimdRegShadowing. */
1211	uint32_t uType : 4;
1212	uint32_t uUnused : 4;
1213	/** The guest register being shadowed (IEMNATIVEGSTSIMDREG). */
1214	uint32_t idxGstSimdReg : 8;
1215	/** The host new register number, UINT8_MAX if dropped. */
1216	uint32_t idxHstSimdReg : 8;
1217	/** The previous host register number, UINT8_MAX if new. */
1218	uint32_t idxHstSimdRegPrev : 8;
1219	} GuestSimdRegShadowing;
1220	#endif
1221
1222	#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING
1223	struct
1224	{
1225	/* kIemTbDbgEntryType_DelayedPcUpdate. */
1226	uint32_t uType : 4;
1227	/* The instruction offset added to the program counter. */
1228	uint32_t offPc : 14;
1229	/** Number of instructions skipped. */
1230	uint32_t cInstrSkipped : 14;
1231	} DelayedPcUpdate;
1232	#endif
1233
1234	#if defined(IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK) \|\| defined(IEMNATIVE_WITH_SIMD_REG_ALLOCATOR)
1235	struct
1236	{
1237	/* kIemTbDbgEntryType_GuestRegDirty. */
1238	uint32_t uType : 4;
1239	uint32_t uUnused : 11;
1240	/** Flag whether this is about a SIMD (true) or general (false) register. */
1241	uint32_t fSimdReg : 1;
1242	/** The guest register index being marked as dirty. */
1243	uint32_t idxGstReg : 8;
1244	/** The host register number this register is shadowed in .*/
1245	uint32_t idxHstReg : 8;
1246	} GuestRegDirty;
1247
1248	struct
1249	{
1250	/* kIemTbDbgEntryType_GuestRegWriteback. */
1251	uint32_t uType : 4;
1252	/** Flag whether this is about a SIMD (true) or general (false) register flush. */
1253	uint32_t fSimdReg : 1;
1254	/** The mask shift. */
1255	uint32_t cShift : 2;
1256	/** The guest register mask being written back. */
1257	uint32_t fGstReg : 25;
1258	} GuestRegWriteback;
1259	#endif
1260
1261	} IEMTBDBGENTRY;
1262	AssertCompileSize(IEMTBDBGENTRY, sizeof(uint32_t));
1263	/** Pointer to a debug info entry. */
1264	typedef IEMTBDBGENTRY *PIEMTBDBGENTRY;
1265	/** Pointer to a const debug info entry. */
1266	typedef IEMTBDBGENTRY const *PCIEMTBDBGENTRY;
1267
1268	/**
1269	* Translation block debug info.
1270	*/
1271	typedef struct IEMTBDBG
1272	{
1273	/** Number of entries in aEntries. */
1274	uint32_t cEntries;
1275	/** The offset of the last kIemTbDbgEntryType_NativeOffset record. */
1276	uint32_t offNativeLast;
1277	/** Debug info entries. */
1278	RT_FLEXIBLE_ARRAY_EXTENSION
1279	IEMTBDBGENTRY aEntries[RT_FLEXIBLE_ARRAY];
1280	} IEMTBDBG;
1281	/** Pointer to TB debug info. */
1282	typedef IEMTBDBG *PIEMTBDBG;
1283	/** Pointer to const TB debug info. */
1284	typedef IEMTBDBG const *PCIEMTBDBG;
1285
1286
1287	/**
1288	* Translation block.
1289	*
1290	* The current plan is to just keep TBs and associated lookup hash table private
1291	* to each VCpu as that simplifies TB removal greatly (no races) and generally
1292	* avoids using expensive atomic primitives for updating lists and stuff.
1293	*/
1294	#pragma pack(2) /* to prevent the Thrd structure from being padded unnecessarily */
1295	typedef struct IEMTB
1296	{
1297	/** Next block with the same hash table entry. */
1298	struct IEMTB *pNext;
1299	/** Usage counter. */
1300	uint32_t cUsed;
1301	/** The IEMCPU::msRecompilerPollNow last time it was used. */
1302	uint32_t msLastUsed;
1303
1304	/** @name What uniquely identifies the block.
1305	* @{ */
1306	RTGCPHYS GCPhysPc;
1307	/** IEMTB_F_XXX (i.e. IEM_F_XXX ++). */
1308	uint32_t fFlags;
1309	union
1310	{
1311	struct
1312	{
1313	/*< Relevant CS X86DESCATTR_XXX bits. /
1314	uint16_t fAttr;
1315	} x86;
1316	};
1317	/** @} */
1318
1319	/** Number of opcode ranges. */
1320	uint8_t cRanges;
1321	/** Statistics: Number of instructions in the block. */
1322	uint8_t cInstructions;
1323
1324	/** Type specific info. */
1325	union
1326	{
1327	struct
1328	{
1329	/** The call sequence table. */
1330	PIEMTHRDEDCALLENTRY paCalls;
1331	/** Number of calls in paCalls. */
1332	uint16_t cCalls;
1333	/** Number of calls allocated. */
1334	uint16_t cAllocated;
1335	} Thrd;
1336	struct
1337	{
1338	/** The native instructions (PFNIEMTBNATIVE). */
1339	PIEMNATIVEINSTR paInstructions;
1340	/** Number of instructions pointed to by paInstructions. */
1341	uint32_t cInstructions;
1342	} Native;
1343	/** Generic view for zeroing when freeing. */
1344	struct
1345	{
1346	uintptr_t uPtr;
1347	uint32_t uData;
1348	} Gen;
1349	};
1350
1351	/** The allocation chunk this TB belongs to. */
1352	uint8_t idxAllocChunk;
1353	/** The number of entries in the lookup table.
1354	* Because we're out of space, the TB lookup table is located before the
1355	* opcodes pointed to by pabOpcodes. */
1356	uint8_t cTbLookupEntries;
1357
1358	/** Number of bytes of opcodes stored in pabOpcodes.
1359	* @todo this field isn't really needed, aRanges keeps the actual info. */
1360	uint16_t cbOpcodes;
1361	/** Pointer to the opcode bytes this block was recompiled from.
1362	* This also points to the TB lookup table, which starts cTbLookupEntries
1363	* entries before the opcodes (we don't have room atm for another point). */
1364	uint8_t *pabOpcodes;
1365
1366	/** Debug info if enabled.
1367	* This is only generated by the native recompiler. */
1368	PIEMTBDBG pDbgInfo;
1369
1370	/* --- 64 byte cache line end --- */
1371
1372	/** Opcode ranges.
1373	*
1374	* The opcode checkers and maybe TLB loading functions will use this to figure
1375	* out what to do. The parameter will specify an entry and the opcode offset to
1376	* start at and the minimum number of bytes to verify (instruction length).
1377	*
1378	* When VT-x and AMD-V looks up the opcode bytes for an exitting instruction,
1379	* they'll first translate RIP (+ cbInstr - 1) to a physical address using the
1380	* code TLB (must have a valid entry for that address) and scan the ranges to
1381	* locate the corresponding opcodes. Probably.
1382	*/
1383	struct IEMTBOPCODERANGE
1384	{
1385	/** Offset within pabOpcodes. */
1386	uint16_t offOpcodes;
1387	/** Number of bytes. */
1388	uint16_t cbOpcodes;
1389	/** The page offset. */
1390	RT_GCC_EXTENSION
1391	uint16_t offPhysPage : 12;
1392	/** Unused bits. */
1393	RT_GCC_EXTENSION
1394	uint16_t u2Unused : 2;
1395	/** Index into GCPhysPc + aGCPhysPages for the physical page address. */
1396	RT_GCC_EXTENSION
1397	uint16_t idxPhysPage : 2;
1398	} aRanges[8];
1399
1400	/** Physical pages that this TB covers.
1401	* The GCPhysPc w/o page offset is element zero, so starting here with 1. */
1402	RTGCPHYS aGCPhysPages[2];
1403	} IEMTB;
1404	#pragma pack()
1405	AssertCompileMemberAlignment(IEMTB, GCPhysPc, sizeof(RTGCPHYS));
1406	AssertCompileMemberAlignment(IEMTB, Thrd, sizeof(void *));
1407	AssertCompileMemberAlignment(IEMTB, pabOpcodes, sizeof(void *));
1408	AssertCompileMemberAlignment(IEMTB, pDbgInfo, sizeof(void *));
1409	AssertCompileMemberAlignment(IEMTB, aGCPhysPages, sizeof(RTGCPHYS));
1410	AssertCompileMemberOffset(IEMTB, aRanges, 64);
1411	AssertCompileMemberSize(IEMTB, aRanges[0], 6);
1412	#if 1
1413	AssertCompileSize(IEMTB, 128);
1414	# define IEMTB_SIZE_IS_POWER_OF_TWO /*< The IEMTB size is a power of two. /
1415	#else
1416	AssertCompileSize(IEMTB, 168);
1417	# undef IEMTB_SIZE_IS_POWER_OF_TWO
1418	#endif
1419
1420	/** Pointer to a translation block. */
1421	typedef IEMTB *PIEMTB;
1422	/** Pointer to a const translation block. */
1423	typedef IEMTB const *PCIEMTB;
1424
1425	/** Gets address of the given TB lookup table entry. */
1426	#define IEMTB_GET_TB_LOOKUP_TAB_ENTRY(a_pTb, a_idx) \
1427	((PIEMTB )&(a_pTb)->pabOpcodes[-(int)((a_pTb)->cTbLookupEntries - (a_idx)) sizeof(PIEMTB)])
1428
1429	/**
1430	* Gets the physical address for a TB opcode range.
1431	*/
1432	DECL_FORCE_INLINE(RTGCPHYS) iemTbGetRangePhysPageAddr(PCIEMTB pTb, uint8_t idxRange)
1433	{
1434	Assert(idxRange < RT_MIN(pTb->cRanges, RT_ELEMENTS(pTb->aRanges)));
1435	uint8_t const idxPage = pTb->aRanges[idxRange].idxPhysPage;
1436	Assert(idxPage <= RT_ELEMENTS(pTb->aGCPhysPages));
1437	if (idxPage == 0)
1438	return pTb->GCPhysPc & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
1439	Assert(!(pTb->aGCPhysPages[idxPage - 1] & GUEST_PAGE_OFFSET_MASK));
1440	return pTb->aGCPhysPages[idxPage - 1];
1441	}
1442
1443
1444	/**
1445	* A chunk of memory in the TB allocator.
1446	*/
1447	typedef struct IEMTBCHUNK
1448	{
1449	/** Pointer to the translation blocks in this chunk. */
1450	PIEMTB paTbs;
1451	#ifdef IN_RING0
1452	/** Allocation handle. */
1453	RTR0MEMOBJ hMemObj;
1454	#endif
1455	} IEMTBCHUNK;
1456
1457	/**
1458	* A per-CPU translation block allocator.
1459	*
1460	* Because of how the IEMTBCACHE uses the lower 6 bits of the TB address to keep
1461	* the length of the collision list, and of course also for cache line alignment
1462	* reasons, the TBs must be allocated with at least 64-byte alignment.
1463	* Memory is there therefore allocated using one of the page aligned allocators.
1464	*
1465	*
1466	* To avoid wasting too much memory, it is allocated piecemeal as needed,
1467	* in chunks (IEMTBCHUNK) of 2 MiB or more. The TB has an 8-bit chunk index
1468	* that enables us to quickly calculate the allocation bitmap position when
1469	* freeing the translation block.
1470	*/
1471	typedef struct IEMTBALLOCATOR
1472	{
1473	/** Magic value (IEMTBALLOCATOR_MAGIC). */
1474	uint32_t uMagic;
1475
1476	#ifdef IEMTB_SIZE_IS_POWER_OF_TWO
1477	/** Mask corresponding to cTbsPerChunk - 1. */
1478	uint32_t fChunkMask;
1479	/** Shift count corresponding to cTbsPerChunk. */
1480	uint8_t cChunkShift;
1481	#else
1482	uint32_t uUnused;
1483	uint8_t bUnused;
1484	#endif
1485	/** Number of chunks we're allowed to allocate. */
1486	uint8_t cMaxChunks;
1487	/** Number of chunks currently populated. */
1488	uint16_t cAllocatedChunks;
1489	/** Number of translation blocks per chunk. */
1490	uint32_t cTbsPerChunk;
1491	/** Chunk size. */
1492	uint32_t cbPerChunk;
1493
1494	/** The maximum number of TBs. */
1495	uint32_t cMaxTbs;
1496	/** Total number of TBs in the populated chunks.
1497	* (cAllocatedChunks * cTbsPerChunk) */
1498	uint32_t cTotalTbs;
1499	/** The current number of TBs in use.
1500	* The number of free TBs: cAllocatedTbs - cInUseTbs; */
1501	uint32_t cInUseTbs;
1502	/** Statistics: Number of the cInUseTbs that are native ones. */
1503	uint32_t cNativeTbs;
1504	/** Statistics: Number of the cInUseTbs that are threaded ones. */
1505	uint32_t cThreadedTbs;
1506
1507	/** Where to start pruning TBs from when we're out.
1508	* See iemTbAllocatorAllocSlow for details. */
1509	uint32_t iPruneFrom;
1510	/** Where to start pruning native TBs from when we're out of executable memory.
1511	* See iemTbAllocatorFreeupNativeSpace for details. */
1512	uint32_t iPruneNativeFrom;
1513	uint64_t u64Padding;
1514
1515	/** Statistics: Number of TB allocation calls. */
1516	STAMCOUNTER StatAllocs;
1517	/** Statistics: Number of TB free calls. */
1518	STAMCOUNTER StatFrees;
1519	/** Statistics: Time spend pruning. */
1520	STAMPROFILE StatPrune;
1521	/** Statistics: Time spend pruning native TBs. */
1522	STAMPROFILE StatPruneNative;
1523
1524	/** The delayed free list (see iemTbAlloctorScheduleForFree). */
1525	PIEMTB pDelayedFreeHead;
1526	/* Head of the list of free TBs. */
1527	PIEMTB pTbsFreeHead;
1528
1529	/** Allocation chunks. */
1530	IEMTBCHUNK aChunks[256];
1531	} IEMTBALLOCATOR;
1532	/** Pointer to a TB allocator. */
1533	typedef struct IEMTBALLOCATOR *PIEMTBALLOCATOR;
1534
1535	/** Magic value for the TB allocator (Emmet Harley Cohen). */
1536	#define IEMTBALLOCATOR_MAGIC UINT32_C(0x19900525)
1537
1538
1539	/**
1540	* A per-CPU translation block cache (hash table).
1541	*
1542	* The hash table is allocated once during IEM initialization and size double
1543	* the max TB count, rounded up to the nearest power of two (so we can use and
1544	* AND mask rather than a rest division when hashing).
1545	*/
1546	typedef struct IEMTBCACHE
1547	{
1548	/** Magic value (IEMTBCACHE_MAGIC). */
1549	uint32_t uMagic;
1550	/** Size of the hash table. This is a power of two. */
1551	uint32_t cHash;
1552	/** The mask corresponding to cHash. */
1553	uint32_t uHashMask;
1554	uint32_t uPadding;
1555
1556	/** @name Statistics
1557	* @{ */
1558	/** Number of collisions ever. */
1559	STAMCOUNTER cCollisions;
1560
1561	/** Statistics: Number of TB lookup misses. */
1562	STAMCOUNTER cLookupMisses;
1563	/** Statistics: Number of TB lookup hits via hash table (debug only). */
1564	STAMCOUNTER cLookupHits;
1565	/** Statistics: Number of TB lookup hits via TB associated lookup table (debug only). */
1566	STAMCOUNTER cLookupHitsViaTbLookupTable;
1567	STAMCOUNTER auPadding2[2];
1568	/** Statistics: Collision list length pruning. */
1569	STAMPROFILE StatPrune;
1570	/** @} */
1571
1572	/** The hash table itself.
1573	* @note The lower 6 bits of the pointer is used for keeping the collision
1574	* list length, so we can take action when it grows too long.
1575	* This works because TBs are allocated using a 64 byte (or
1576	* higher) alignment from page aligned chunks of memory, so the lower
1577	* 6 bits of the address will always be zero.
1578	* See IEMTBCACHE_PTR_COUNT_MASK, IEMTBCACHE_PTR_MAKE and friends.
1579	*/
1580	RT_FLEXIBLE_ARRAY_EXTENSION
1581	PIEMTB apHash[RT_FLEXIBLE_ARRAY];
1582	} IEMTBCACHE;
1583	/** Pointer to a per-CPU translation block cahce. */
1584	typedef IEMTBCACHE *PIEMTBCACHE;
1585
1586	/** Magic value for IEMTBCACHE (Johnny O'Neal). */
1587	#define IEMTBCACHE_MAGIC UINT32_C(0x19561010)
1588
1589	/** The collision count mask for IEMTBCACHE::apHash entries. */
1590	#define IEMTBCACHE_PTR_COUNT_MASK ((uintptr_t)0x3f)
1591	/** The max collision count for IEMTBCACHE::apHash entries before pruning. */
1592	#define IEMTBCACHE_PTR_MAX_COUNT ((uintptr_t)0x30)
1593	/** Combine a TB pointer and a collision list length into a value for an
1594	* IEMTBCACHE::apHash entry. */
1595	#define IEMTBCACHE_PTR_MAKE(a_pTb, a_cCount) (PIEMTB)((uintptr_t)(a_pTb) \| (a_cCount))
1596	/** Combine a TB pointer and a collision list length into a value for an
1597	* IEMTBCACHE::apHash entry. */
1598	#define IEMTBCACHE_PTR_GET_TB(a_pHashEntry) (PIEMTB)((uintptr_t)(a_pHashEntry) & ~IEMTBCACHE_PTR_COUNT_MASK)
1599	/** Combine a TB pointer and a collision list length into a value for an
1600	* IEMTBCACHE::apHash entry. */
1601	#define IEMTBCACHE_PTR_GET_COUNT(a_pHashEntry) ((uintptr_t)(a_pHashEntry) & IEMTBCACHE_PTR_COUNT_MASK)
1602
1603	/**
1604	* Calculates the hash table slot for a TB from physical PC address and TB flags.
1605	*/
1606	#define IEMTBCACHE_HASH(a_paCache, a_fTbFlags, a_GCPhysPc) \
1607	IEMTBCACHE_HASH_NO_KEY_MASK(a_paCache, (a_fTbFlags) & IEMTB_F_KEY_MASK, a_GCPhysPc)
1608
1609	/**
1610	* Calculates the hash table slot for a TB from physical PC address and TB
1611	* flags, ASSUMING the caller has applied IEMTB_F_KEY_MASK to @a a_fTbFlags.
1612	*/
1613	#define IEMTBCACHE_HASH_NO_KEY_MASK(a_paCache, a_fTbFlags, a_GCPhysPc) \
1614	(((uint32_t)(a_GCPhysPc) ^ (a_fTbFlags)) & (a_paCache)->uHashMask)
1615
1616
1617	/** @name IEMBRANCHED_F_XXX - Branched indicator (IEMCPU::fTbBranched).
1618	*
1619	* These flags parallels the main IEM_CIMPL_F_BRANCH_XXX flags.
1620	*
1621	* @{ */
1622	/** Value if no branching happened recently. */
1623	#define IEMBRANCHED_F_NO UINT8_C(0x00)
1624	/** Flag set if direct branch, clear if absolute or indirect. */
1625	#define IEMBRANCHED_F_DIRECT UINT8_C(0x01)
1626	/** Flag set if indirect branch, clear if direct or relative. */
1627	#define IEMBRANCHED_F_INDIRECT UINT8_C(0x02)
1628	/** Flag set if relative branch, clear if absolute or indirect. */
1629	#define IEMBRANCHED_F_RELATIVE UINT8_C(0x04)
1630	/** Flag set if conditional branch, clear if unconditional. */
1631	#define IEMBRANCHED_F_CONDITIONAL UINT8_C(0x08)
1632	/** Flag set if it's a far branch. */
1633	#define IEMBRANCHED_F_FAR UINT8_C(0x10)
1634	/** Flag set if the stack pointer is modified. */
1635	#define IEMBRANCHED_F_STACK UINT8_C(0x20)
1636	/** Flag set if the stack pointer and (maybe) the stack segment are modified. */
1637	#define IEMBRANCHED_F_STACK_FAR UINT8_C(0x40)
1638	/** Flag set (by IEM_MC_REL_JMP_XXX) if it's a zero bytes relative jump. */
1639	#define IEMBRANCHED_F_ZERO UINT8_C(0x80)
1640	/** @} */
1641
1642
1643	/**
1644	* The per-CPU IEM state.
1645	*/
1646	typedef struct IEMCPU
1647	{
1648	/** Info status code that needs to be propagated to the IEM caller.
1649	* This cannot be passed internally, as it would complicate all success
1650	* checks within the interpreter making the code larger and almost impossible
1651	* to get right. Instead, we'll store status codes to pass on here. Each
1652	* source of these codes will perform appropriate sanity checks. */
1653	int32_t rcPassUp; /* 0x00 */
1654	/** Execution flag, IEM_F_XXX. */
1655	uint32_t fExec; /* 0x04 */
1656
1657	/** @name Decoder state.
1658	* @{ */
1659	#ifdef IEM_WITH_CODE_TLB
1660	/** The offset of the next instruction byte. */
1661	uint32_t offInstrNextByte; /* 0x08 */
1662	/** The number of bytes available at pbInstrBuf for the current instruction.
1663	* This takes the max opcode length into account so that doesn't need to be
1664	* checked separately. */
1665	uint32_t cbInstrBuf; /* 0x0c */
1666	/** Pointer to the page containing RIP, user specified buffer or abOpcode.
1667	* This can be NULL if the page isn't mappable for some reason, in which
1668	* case we'll do fallback stuff.
1669	*
1670	* If we're executing an instruction from a user specified buffer,
1671	* IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
1672	* aligned pointer but pointer to the user data.
1673	*
1674	* For instructions crossing pages, this will start on the first page and be
1675	* advanced to the next page by the time we've decoded the instruction. This
1676	* therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
1677	*/
1678	uint8_t const pbInstrBuf; / 0x10 */
1679	# if ARCH_BITS == 32
1680	uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
1681	# endif
1682	/** The program counter corresponding to pbInstrBuf.
1683	* This is set to a non-canonical address when we need to invalidate it. */
1684	uint64_t uInstrBufPc; /* 0x18 */
1685	/** The guest physical address corresponding to pbInstrBuf. */
1686	RTGCPHYS GCPhysInstrBuf; /* 0x20 */
1687	/** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
1688	* This takes the CS segment limit into account.
1689	* @note Set to zero when the code TLB is flushed to trigger TLB reload. */
1690	uint16_t cbInstrBufTotal; /* 0x28 */
1691	/** Offset into pbInstrBuf of the first byte of the current instruction.
1692	* Can be negative to efficiently handle cross page instructions. */
1693	int16_t offCurInstrStart; /* 0x2a */
1694
1695	# ifndef IEM_WITH_OPAQUE_DECODER_STATE
1696	/** The prefix mask (IEM_OP_PRF_XXX). */
1697	uint32_t fPrefixes; /* 0x2c */
1698	/** The extra REX ModR/M register field bit (REX.R << 3). */
1699	uint8_t uRexReg; /* 0x30 */
1700	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
1701	* (REX.B << 3). */
1702	uint8_t uRexB; /* 0x31 */
1703	/** The extra REX SIB index field bit (REX.X << 3). */
1704	uint8_t uRexIndex; /* 0x32 */
1705
1706	/** The effective segment register (X86_SREG_XXX). */
1707	uint8_t iEffSeg; /* 0x33 */
1708
1709	/** The offset of the ModR/M byte relative to the start of the instruction. */
1710	uint8_t offModRm; /* 0x34 */
1711
1712	# ifdef IEM_WITH_CODE_TLB_AND_OPCODE_BUF
1713	/** The current offset into abOpcode. */
1714	uint8_t offOpcode; /* 0x35 */
1715	# else
1716	uint8_t bUnused; /* 0x35 */
1717	# endif
1718	# else /* IEM_WITH_OPAQUE_DECODER_STATE */
1719	uint8_t abOpaqueDecoderPart1[0x36 - 0x2c];
1720	# endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1721
1722	#else /* !IEM_WITH_CODE_TLB */
1723	# ifndef IEM_WITH_OPAQUE_DECODER_STATE
1724	/** The size of what has currently been fetched into abOpcode. */
1725	uint8_t cbOpcode; /* 0x08 */
1726	/** The current offset into abOpcode. */
1727	uint8_t offOpcode; /* 0x09 */
1728	/** The offset of the ModR/M byte relative to the start of the instruction. */
1729	uint8_t offModRm; /* 0x0a */
1730
1731	/** The effective segment register (X86_SREG_XXX). */
1732	uint8_t iEffSeg; /* 0x0b */
1733
1734	/** The prefix mask (IEM_OP_PRF_XXX). */
1735	uint32_t fPrefixes; /* 0x0c */
1736	/** The extra REX ModR/M register field bit (REX.R << 3). */
1737	uint8_t uRexReg; /* 0x10 */
1738	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
1739	* (REX.B << 3). */
1740	uint8_t uRexB; /* 0x11 */
1741	/** The extra REX SIB index field bit (REX.X << 3). */
1742	uint8_t uRexIndex; /* 0x12 */
1743
1744	# else /* IEM_WITH_OPAQUE_DECODER_STATE */
1745	uint8_t abOpaqueDecoderPart1[0x13 - 0x08];
1746	# endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1747	#endif /* !IEM_WITH_CODE_TLB */
1748
1749	#ifndef IEM_WITH_OPAQUE_DECODER_STATE
1750	/** The effective operand mode. */
1751	IEMMODE enmEffOpSize; /* 0x36, 0x13 */
1752	/** The default addressing mode. */
1753	IEMMODE enmDefAddrMode; /* 0x37, 0x14 */
1754	/** The effective addressing mode. */
1755	IEMMODE enmEffAddrMode; /* 0x38, 0x15 */
1756	/** The default operand mode. */
1757	IEMMODE enmDefOpSize; /* 0x39, 0x16 */
1758
1759	/** Prefix index (VEX.pp) for two byte and three byte tables. */
1760	uint8_t idxPrefix; /* 0x3a, 0x17 */
1761	/** 3rd VEX/EVEX/XOP register.
1762	* Please use IEM_GET_EFFECTIVE_VVVV to access. */
1763	uint8_t uVex3rdReg; /* 0x3b, 0x18 */
1764	/** The VEX/EVEX/XOP length field. */
1765	uint8_t uVexLength; /* 0x3c, 0x19 */
1766	/** Additional EVEX stuff. */
1767	uint8_t fEvexStuff; /* 0x3d, 0x1a */
1768
1769	# ifndef IEM_WITH_CODE_TLB
1770	/** Explicit alignment padding. */
1771	uint8_t abAlignment2a[1]; /* 0x1b */
1772	# endif
1773	/** The FPU opcode (FOP). */
1774	uint16_t uFpuOpcode; /* 0x3e, 0x1c */
1775	# ifndef IEM_WITH_CODE_TLB
1776	/** Explicit alignment padding. */
1777	uint8_t abAlignment2b[2]; /* 0x1e */
1778	# endif
1779
1780	/** The opcode bytes. */
1781	uint8_t abOpcode[15]; /* 0x40, 0x20 */
1782	/** Explicit alignment padding. */
1783	# ifdef IEM_WITH_CODE_TLB
1784	//uint8_t abAlignment2c[0x4f - 0x4f]; /* 0x4f */
1785	# else
1786	uint8_t abAlignment2c[0x4f - 0x2f]; /* 0x2f */
1787	# endif
1788
1789	#else /* IEM_WITH_OPAQUE_DECODER_STATE */
1790	# ifdef IEM_WITH_CODE_TLB
1791	uint8_t abOpaqueDecoderPart2[0x4f - 0x36];
1792	# else
1793	uint8_t abOpaqueDecoderPart2[0x4f - 0x13];
1794	# endif
1795	#endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1796	/** @} */
1797
1798
1799	/** The number of active guest memory mappings. */
1800	uint8_t cActiveMappings; /* 0x4f, 0x4f */
1801
1802	/** Records for tracking guest memory mappings. */
1803	struct
1804	{
1805	/** The address of the mapped bytes. */
1806	R3R0PTRTYPE(void *) pv;
1807	/** The access flags (IEM_ACCESS_XXX).
1808	* IEM_ACCESS_INVALID if the entry is unused. */
1809	uint32_t fAccess;
1810	#if HC_ARCH_BITS == 64
1811	uint32_t u32Alignment4; /*< Alignment padding. /
1812	#endif
1813	} aMemMappings[3]; /* 0x50 LB 0x30 */
1814
1815	/** Locking records for the mapped memory. */
1816	union
1817	{
1818	PGMPAGEMAPLOCK Lock;
1819	uint64_t au64Padding[2];
1820	} aMemMappingLocks[3]; /* 0x80 LB 0x30 */
1821
1822	/** Bounce buffer info.
1823	* This runs in parallel to aMemMappings. */
1824	struct
1825	{
1826	/** The physical address of the first byte. */
1827	RTGCPHYS GCPhysFirst;
1828	/** The physical address of the second page. */
1829	RTGCPHYS GCPhysSecond;
1830	/** The number of bytes in the first page. */
1831	uint16_t cbFirst;
1832	/** The number of bytes in the second page. */
1833	uint16_t cbSecond;
1834	/** Whether it's unassigned memory. */
1835	bool fUnassigned;
1836	/** Explicit alignment padding. */
1837	bool afAlignment5[3];
1838	} aMemBbMappings[3]; /* 0xb0 LB 0x48 */
1839
1840	/** The flags of the current exception / interrupt. */
1841	uint32_t fCurXcpt; /* 0xf8 */
1842	/** The current exception / interrupt. */
1843	uint8_t uCurXcpt; /* 0xfc */
1844	/** Exception / interrupt recursion depth. */
1845	int8_t cXcptRecursions; /* 0xfb */
1846
1847	/** The next unused mapping index.
1848	* @todo try find room for this up with cActiveMappings. */
1849	uint8_t iNextMapping; /* 0xfd */
1850	uint8_t abAlignment7[1];
1851
1852	/** Bounce buffer storage.
1853	* This runs in parallel to aMemMappings and aMemBbMappings. */
1854	struct
1855	{
1856	uint8_t ab[512];
1857	} aBounceBuffers[3]; /* 0x100 LB 0x600 */
1858
1859
1860	/** Pointer set jump buffer - ring-3 context. */
1861	R3PTRTYPE(jmp_buf *) pJmpBufR3;
1862	/** Pointer set jump buffer - ring-0 context. */
1863	R0PTRTYPE(jmp_buf *) pJmpBufR0;
1864
1865	/** @todo Should move this near @a fCurXcpt later. */
1866	/** The CR2 for the current exception / interrupt. */
1867	uint64_t uCurXcptCr2;
1868	/** The error code for the current exception / interrupt. */
1869	uint32_t uCurXcptErr;
1870
1871	/** @name Statistics
1872	* @{ */
1873	/** The number of instructions we've executed. */
1874	uint32_t cInstructions;
1875	/** The number of potential exits. */
1876	uint32_t cPotentialExits;
1877	/** The number of bytes data or stack written (mostly for IEMExecOneEx).
1878	* This may contain uncommitted writes. */
1879	uint32_t cbWritten;
1880	/** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
1881	uint32_t cRetInstrNotImplemented;
1882	/** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
1883	uint32_t cRetAspectNotImplemented;
1884	/** Counts informational statuses returned (other than VINF_SUCCESS). */
1885	uint32_t cRetInfStatuses;
1886	/** Counts other error statuses returned. */
1887	uint32_t cRetErrStatuses;
1888	/** Number of times rcPassUp has been used. */
1889	uint32_t cRetPassUpStatus;
1890	/** Number of times RZ left with instruction commit pending for ring-3. */
1891	uint32_t cPendingCommit;
1892	/** Number of misaligned (host sense) atomic instruction accesses. */
1893	uint32_t cMisalignedAtomics;
1894	/** Number of long jumps. */
1895	uint32_t cLongJumps;
1896	/** @} */
1897
1898	/** @name Target CPU information.
1899	* @{ */
1900	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
1901	/** The target CPU. */
1902	uint8_t uTargetCpu;
1903	#else
1904	uint8_t bTargetCpuPadding;
1905	#endif
1906	/** For selecting assembly works matching the target CPU EFLAGS behaviour, see
1907	* IEMTARGETCPU_EFL_BEHAVIOR_XXX for values, with the 1st entry for when no
1908	* native host support and the 2nd for when there is.
1909	*
1910	* The two values are typically indexed by a g_CpumHostFeatures bit.
1911	*
1912	* This is for instance used for the BSF & BSR instructions where AMD and
1913	* Intel CPUs produce different EFLAGS. */
1914	uint8_t aidxTargetCpuEflFlavour[2];
1915
1916	/** The CPU vendor. */
1917	CPUMCPUVENDOR enmCpuVendor;
1918	/** @} */
1919
1920	/** @name Host CPU information.
1921	* @{ */
1922	/** The CPU vendor. */
1923	CPUMCPUVENDOR enmHostCpuVendor;
1924	/** @} */
1925
1926	/** Counts RDMSR \#GP(0) LogRel(). */
1927	uint8_t cLogRelRdMsr;
1928	/** Counts WRMSR \#GP(0) LogRel(). */
1929	uint8_t cLogRelWrMsr;
1930	/** Alignment padding. */
1931	uint8_t abAlignment9[42];
1932
1933	/** @name Recompilation
1934	* @{ */
1935	/** Pointer to the current translation block.
1936	* This can either be one being executed or one being compiled. */
1937	R3PTRTYPE(PIEMTB) pCurTbR3;
1938	#ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
1939	/** Frame pointer for the last native TB to execute. */
1940	R3PTRTYPE(void *) pvTbFramePointerR3;
1941	#else
1942	R3PTRTYPE(void *) pvUnusedR3;
1943	#endif
1944	/** Fixed TB used for threaded recompilation.
1945	* This is allocated once with maxed-out sizes and re-used afterwards. */
1946	R3PTRTYPE(PIEMTB) pThrdCompileTbR3;
1947	/** Pointer to the ring-3 TB cache for this EMT. */
1948	R3PTRTYPE(PIEMTBCACHE) pTbCacheR3;
1949	/** Pointer to the ring-3 TB lookup entry.
1950	* This either points to pTbLookupEntryDummyR3 or an actually lookuptable
1951	* entry, thus it can always safely be used w/o NULL checking. */
1952	R3PTRTYPE(PIEMTB *) ppTbLookupEntryR3;
1953	/** The PC (RIP) at the start of pCurTbR3/pCurTbR0.
1954	* The TBs are based on physical addresses, so this is needed to correleated
1955	* RIP to opcode bytes stored in the TB (AMD-V / VT-x). */
1956	uint64_t uCurTbStartPc;
1957	/** Number of threaded TBs executed. */
1958	uint64_t cTbExecThreaded;
1959	/** Number of native TBs executed. */
1960	uint64_t cTbExecNative;
1961	/** Whether we need to check the opcode bytes for the current instruction.
1962	* This is set by a previous instruction if it modified memory or similar. */
1963	bool fTbCheckOpcodes;
1964	/** Indicates whether and how we just branched - IEMBRANCHED_F_XXX. */
1965	uint8_t fTbBranched;
1966	/** Set when GCPhysInstrBuf is updated because of a page crossing. */
1967	bool fTbCrossedPage;
1968	/** Whether to end the current TB. */
1969	bool fEndTb;
1970	/** Number of instructions before we need emit an IRQ check call again.
1971	* This helps making sure we don't execute too long w/o checking for
1972	* interrupts and immediately following instructions that may enable
1973	* interrupts (e.g. POPF, IRET, STI). With STI an additional hack is
1974	* required to make sure we check following the next instruction as well, see
1975	* fTbCurInstrIsSti. */
1976	uint8_t cInstrTillIrqCheck;
1977	/** Indicates that the current instruction is an STI. This is set by the
1978	* iemCImpl_sti code and subsequently cleared by the recompiler. */
1979	bool fTbCurInstrIsSti;
1980	/** The size of the IEMTB::pabOpcodes allocation in pThrdCompileTbR3. */
1981	uint16_t cbOpcodesAllocated;
1982	/** The current instruction number in a native TB.
1983	* This is set by code that may trigger an unexpected TB exit (throw/longjmp)
1984	* and will be picked up by the TB execution loop. Only used when
1985	* IEMNATIVE_WITH_INSTRUCTION_COUNTING is defined. */
1986	uint8_t idxTbCurInstr;
1987	/** Spaced reserved for recompiler data / alignment. */
1988	bool afRecompilerStuff1[3];
1989	/** The virtual sync time at the last timer poll call. */
1990	uint32_t msRecompilerPollNow;
1991	/** The IEMTB::cUsed value when to attempt native recompilation of a TB. */
1992	uint32_t uTbNativeRecompileAtUsedCount;
1993	/** The IEM_CIMPL_F_XXX mask for the current instruction. */
1994	uint32_t fTbCurInstr;
1995	/** The IEM_CIMPL_F_XXX mask for the previous instruction. */
1996	uint32_t fTbPrevInstr;
1997	/** Strict: Tracking skipped EFLAGS calculations. Any bits set here are
1998	* currently not up to date in EFLAGS. */
1999	uint32_t fSkippingEFlags;
2000	/** Previous GCPhysInstrBuf value - only valid if fTbCrossedPage is set. */
2001	RTGCPHYS GCPhysInstrBufPrev;
2002	/** Pointer to the ring-3 TB allocator for this EMT. */
2003	R3PTRTYPE(PIEMTBALLOCATOR) pTbAllocatorR3;
2004	/** Pointer to the ring-3 executable memory allocator for this EMT. */
2005	R3PTRTYPE(struct IEMEXECMEMALLOCATOR *) pExecMemAllocatorR3;
2006	/** Pointer to the native recompiler state for ring-3. */
2007	R3PTRTYPE(struct IEMRECOMPILERSTATE *) pNativeRecompilerStateR3;
2008	/** Dummy entry for ppTbLookupEntryR3. */
2009	R3PTRTYPE(PIEMTB) pTbLookupEntryDummyR3;
2010
2011	/** Dummy TLB entry used for accesses to pages with databreakpoints. */
2012	IEMTLBENTRY DataBreakpointTlbe;
2013
2014	/** Threaded TB statistics: Times TB execution was broken off before reaching the end. */
2015	STAMCOUNTER StatTbThreadedExecBreaks;
2016	/** Statistics: Times BltIn_CheckIrq breaks out of the TB. */
2017	STAMCOUNTER StatCheckIrqBreaks;
2018	/** Statistics: Times BltIn_CheckMode breaks out of the TB. */
2019	STAMCOUNTER StatCheckModeBreaks;
2020	/** Threaded TB statistics: Times execution break on call with lookup entries. */
2021	STAMCOUNTER StatTbThreadedExecBreaksWithLookup;
2022	/** Threaded TB statistics: Times execution break on call without lookup entries. */
2023	STAMCOUNTER StatTbThreadedExecBreaksWithoutLookup;
2024	/** Statistics: Times a post jump target check missed and had to find new TB. */
2025	STAMCOUNTER StatCheckBranchMisses;
2026	/** Statistics: Times a jump or page crossing required a TB with CS.LIM checking. */
2027	STAMCOUNTER StatCheckNeedCsLimChecking;
2028	/** Statistics: Times a loop was detected within a TB.. */
2029	STAMCOUNTER StatTbLoopInTbDetected;
2030	/** Exec memory allocator statistics: Number of times allocaintg executable memory failed. */
2031	STAMCOUNTER StatNativeExecMemInstrBufAllocFailed;
2032	/** Native TB statistics: Number of fully recompiled TBs. */
2033	STAMCOUNTER StatNativeFullyRecompiledTbs;
2034	/** TB statistics: Number of instructions per TB. */
2035	STAMPROFILE StatTbInstr;
2036	/** TB statistics: Number of TB lookup table entries per TB. */
2037	STAMPROFILE StatTbLookupEntries;
2038	/** Threaded TB statistics: Number of calls per TB. */
2039	STAMPROFILE StatTbThreadedCalls;
2040	/** Native TB statistics: Native code size per TB. */
2041	STAMPROFILE StatTbNativeCode;
2042	/** Native TB statistics: Profiling native recompilation. */
2043	STAMPROFILE StatNativeRecompilation;
2044	/** Native TB statistics: Number of calls per TB that were recompiled properly. */
2045	STAMPROFILE StatNativeCallsRecompiled;
2046	/** Native TB statistics: Number of threaded calls per TB that weren't recompiled. */
2047	STAMPROFILE StatNativeCallsThreaded;
2048	/** Native recompiled execution: TLB hits for data fetches. */
2049	STAMCOUNTER StatNativeTlbHitsForFetch;
2050	/** Native recompiled execution: TLB hits for data stores. */
2051	STAMCOUNTER StatNativeTlbHitsForStore;
2052	/** Native recompiled execution: TLB hits for stack accesses. */
2053	STAMCOUNTER StatNativeTlbHitsForStack;
2054	/** Native recompiled execution: TLB hits for mapped accesses. */
2055	STAMCOUNTER StatNativeTlbHitsForMapped;
2056	/** Native recompiled execution: Code TLB misses for new page. */
2057	STAMCOUNTER StatNativeCodeTlbMissesNewPage;
2058	/** Native recompiled execution: Code TLB hits for new page. */
2059	STAMCOUNTER StatNativeCodeTlbHitsForNewPage;
2060	/** Native recompiled execution: Code TLB misses for new page with offset. */
2061	STAMCOUNTER StatNativeCodeTlbMissesNewPageWithOffset;
2062	/** Native recompiled execution: Code TLB hits for new page with offset. */
2063	STAMCOUNTER StatNativeCodeTlbHitsForNewPageWithOffset;
2064
2065	/** Native recompiler: Number of calls to iemNativeRegAllocFindFree. */
2066	STAMCOUNTER StatNativeRegFindFree;
2067	/** Native recompiler: Number of times iemNativeRegAllocFindFree needed
2068	* to free a variable. */
2069	STAMCOUNTER StatNativeRegFindFreeVar;
2070	/** Native recompiler: Number of times iemNativeRegAllocFindFree did
2071	* not need to free any variables. */
2072	STAMCOUNTER StatNativeRegFindFreeNoVar;
2073	/** Native recompiler: Liveness info freed shadowed guest registers in
2074	* iemNativeRegAllocFindFree. */
2075	STAMCOUNTER StatNativeRegFindFreeLivenessUnshadowed;
2076	/** Native recompiler: Liveness info helped with the allocation in
2077	* iemNativeRegAllocFindFree. */
2078	STAMCOUNTER StatNativeRegFindFreeLivenessHelped;
2079
2080	/** Native recompiler: Number of times status flags calc has been skipped. */
2081	STAMCOUNTER StatNativeEflSkippedArithmetic;
2082	/** Native recompiler: Number of times status flags calc has been skipped. */
2083	STAMCOUNTER StatNativeEflSkippedLogical;
2084
2085	/** Native recompiler: Number of opportunities to skip EFLAGS.CF updating. */
2086	STAMCOUNTER StatNativeLivenessEflCfSkippable;
2087	/** Native recompiler: Number of opportunities to skip EFLAGS.PF updating. */
2088	STAMCOUNTER StatNativeLivenessEflPfSkippable;
2089	/** Native recompiler: Number of opportunities to skip EFLAGS.AF updating. */
2090	STAMCOUNTER StatNativeLivenessEflAfSkippable;
2091	/** Native recompiler: Number of opportunities to skip EFLAGS.ZF updating. */
2092	STAMCOUNTER StatNativeLivenessEflZfSkippable;
2093	/** Native recompiler: Number of opportunities to skip EFLAGS.SF updating. */
2094	STAMCOUNTER StatNativeLivenessEflSfSkippable;
2095	/** Native recompiler: Number of opportunities to skip EFLAGS.OF updating. */
2096	STAMCOUNTER StatNativeLivenessEflOfSkippable;
2097	/** Native recompiler: Number of required EFLAGS.CF updates. */
2098	STAMCOUNTER StatNativeLivenessEflCfRequired;
2099	/** Native recompiler: Number of required EFLAGS.PF updates. */
2100	STAMCOUNTER StatNativeLivenessEflPfRequired;
2101	/** Native recompiler: Number of required EFLAGS.AF updates. */
2102	STAMCOUNTER StatNativeLivenessEflAfRequired;
2103	/** Native recompiler: Number of required EFLAGS.ZF updates. */
2104	STAMCOUNTER StatNativeLivenessEflZfRequired;
2105	/** Native recompiler: Number of required EFLAGS.SF updates. */
2106	STAMCOUNTER StatNativeLivenessEflSfRequired;
2107	/** Native recompiler: Number of required EFLAGS.OF updates. */
2108	STAMCOUNTER StatNativeLivenessEflOfRequired;
2109	/** Native recompiler: Number of potentially delayable EFLAGS.CF updates. */
2110	STAMCOUNTER StatNativeLivenessEflCfDelayable;
2111	/** Native recompiler: Number of potentially delayable EFLAGS.PF updates. */
2112	STAMCOUNTER StatNativeLivenessEflPfDelayable;
2113	/** Native recompiler: Number of potentially delayable EFLAGS.AF updates. */
2114	STAMCOUNTER StatNativeLivenessEflAfDelayable;
2115	/** Native recompiler: Number of potentially delayable EFLAGS.ZF updates. */
2116	STAMCOUNTER StatNativeLivenessEflZfDelayable;
2117	/** Native recompiler: Number of potentially delayable EFLAGS.SF updates. */
2118	STAMCOUNTER StatNativeLivenessEflSfDelayable;
2119	/** Native recompiler: Number of potentially delayable EFLAGS.OF updates. */
2120	STAMCOUNTER StatNativeLivenessEflOfDelayable;
2121
2122	/** Native recompiler: Number of potential PC updates in total. */
2123	STAMCOUNTER StatNativePcUpdateTotal;
2124	/** Native recompiler: Number of PC updates which could be delayed. */
2125	STAMCOUNTER StatNativePcUpdateDelayed;
2126
2127	//#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
2128	/** Native recompiler: Number of calls to iemNativeSimdRegAllocFindFree. */
2129	STAMCOUNTER StatNativeSimdRegFindFree;
2130	/** Native recompiler: Number of times iemNativeSimdRegAllocFindFree needed
2131	* to free a variable. */
2132	STAMCOUNTER StatNativeSimdRegFindFreeVar;
2133	/** Native recompiler: Number of times iemNativeSimdRegAllocFindFree did
2134	* not need to free any variables. */
2135	STAMCOUNTER StatNativeSimdRegFindFreeNoVar;
2136	/** Native recompiler: Liveness info freed shadowed guest registers in
2137	* iemNativeSimdRegAllocFindFree. */
2138	STAMCOUNTER StatNativeSimdRegFindFreeLivenessUnshadowed;
2139	/** Native recompiler: Liveness info helped with the allocation in
2140	* iemNativeSimdRegAllocFindFree. */
2141	STAMCOUNTER StatNativeSimdRegFindFreeLivenessHelped;
2142
2143	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() checks. */
2144	STAMCOUNTER StatNativeMaybeDeviceNotAvailXcptCheckPotential;
2145	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() checks. */
2146	STAMCOUNTER StatNativeMaybeWaitDeviceNotAvailXcptCheckPotential;
2147	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() checks. */
2148	STAMCOUNTER StatNativeMaybeSseXcptCheckPotential;
2149	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() checks. */
2150	STAMCOUNTER StatNativeMaybeAvxXcptCheckPotential;
2151
2152	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() checks omitted. */
2153	STAMCOUNTER StatNativeMaybeDeviceNotAvailXcptCheckOmitted;
2154	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() checks omitted. */
2155	STAMCOUNTER StatNativeMaybeWaitDeviceNotAvailXcptCheckOmitted;
2156	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() checks omitted. */
2157	STAMCOUNTER StatNativeMaybeSseXcptCheckOmitted;
2158	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() checks omitted. */
2159	STAMCOUNTER StatNativeMaybeAvxXcptCheckOmitted;
2160	//#endif
2161
2162	/** Native recompiler: The TB finished executing completely without jumping to a an exit label.
2163	* Not availabe in release builds. */
2164	STAMCOUNTER StatNativeTbFinished;
2165	/** Native recompiler: The TB finished executing jumping to the ReturnBreak label. */
2166	STAMCOUNTER StatNativeTbExitReturnBreak;
2167	/** Native recompiler: The TB finished executing jumping to the ReturnBreakFF label. */
2168	STAMCOUNTER StatNativeTbExitReturnBreakFF;
2169	/** Native recompiler: The TB finished executing jumping to the ReturnWithFlags label. */
2170	STAMCOUNTER StatNativeTbExitReturnWithFlags;
2171	/** Native recompiler: The TB finished executing with other non-zero status. */
2172	STAMCOUNTER StatNativeTbExitReturnOtherStatus;
2173	/** Native recompiler: The TB finished executing via throw / long jump. */
2174	STAMCOUNTER StatNativeTbExitLongJump;
2175	/** Native recompiler: The TB finished executing jumping to the ReturnBreak
2176	* label, but directly jumped to the next TB, scenario \#1 w/o IRQ checks. */
2177	STAMCOUNTER StatNativeTbExitDirectLinking1NoIrq;
2178	/** Native recompiler: The TB finished executing jumping to the ReturnBreak
2179	* label, but directly jumped to the next TB, scenario \#1 with IRQ checks. */
2180	STAMCOUNTER StatNativeTbExitDirectLinking1Irq;
2181	/** Native recompiler: The TB finished executing jumping to the ReturnBreak
2182	* label, but directly jumped to the next TB, scenario \#1 w/o IRQ checks. */
2183	STAMCOUNTER StatNativeTbExitDirectLinking2NoIrq;
2184	/** Native recompiler: The TB finished executing jumping to the ReturnBreak
2185	* label, but directly jumped to the next TB, scenario \#2 with IRQ checks. */
2186	STAMCOUNTER StatNativeTbExitDirectLinking2Irq;
2187
2188	/** Native recompiler: The TB finished executing jumping to the RaiseDe label. */
2189	STAMCOUNTER StatNativeTbExitRaiseDe;
2190	/** Native recompiler: The TB finished executing jumping to the RaiseUd label. */
2191	STAMCOUNTER StatNativeTbExitRaiseUd;
2192	/** Native recompiler: The TB finished executing jumping to the RaiseSseRelated label. */
2193	STAMCOUNTER StatNativeTbExitRaiseSseRelated;
2194	/** Native recompiler: The TB finished executing jumping to the RaiseAvxRelated label. */
2195	STAMCOUNTER StatNativeTbExitRaiseAvxRelated;
2196	/** Native recompiler: The TB finished executing jumping to the RaiseSseAvxFpRelated label. */
2197	STAMCOUNTER StatNativeTbExitRaiseSseAvxFpRelated;
2198	/** Native recompiler: The TB finished executing jumping to the RaiseNm label. */
2199	STAMCOUNTER StatNativeTbExitRaiseNm;
2200	/** Native recompiler: The TB finished executing jumping to the RaiseGp0 label. */
2201	STAMCOUNTER StatNativeTbExitRaiseGp0;
2202	/** Native recompiler: The TB finished executing jumping to the RaiseMf label. */
2203	STAMCOUNTER StatNativeTbExitRaiseMf;
2204	/** Native recompiler: The TB finished executing jumping to the RaiseXf label. */
2205	STAMCOUNTER StatNativeTbExitRaiseXf;
2206	/** Native recompiler: The TB finished executing jumping to the ObsoleteTb label. */
2207	STAMCOUNTER StatNativeTbExitObsoleteTb;
2208
2209	/** Native recompiler: Failure situations with direct linking scenario \#1.
2210	* Counter with StatNativeTbExitReturnBreak. Not in release builds.
2211	* @{ */
2212	STAMCOUNTER StatNativeTbExitDirectLinking1NoTb;
2213	STAMCOUNTER StatNativeTbExitDirectLinking1MismatchGCPhysPc;
2214	STAMCOUNTER StatNativeTbExitDirectLinking1MismatchFlags;
2215	STAMCOUNTER StatNativeTbExitDirectLinking1PendingIrq;
2216	/** @} */
2217
2218	/** Native recompiler: Failure situations with direct linking scenario \#2.
2219	* Counter with StatNativeTbExitReturnBreak. Not in release builds.
2220	* @{ */
2221	STAMCOUNTER StatNativeTbExitDirectLinking2NoTb;
2222	STAMCOUNTER StatNativeTbExitDirectLinking2MismatchGCPhysPc;
2223	STAMCOUNTER StatNativeTbExitDirectLinking2MismatchFlags;
2224	STAMCOUNTER StatNativeTbExitDirectLinking2PendingIrq;
2225	/** @} */
2226
2227	/** iemMemMap and iemMemMapJmp statistics.
2228	* @{ */
2229	STAMCOUNTER StatMemMapJmp;
2230	STAMCOUNTER StatMemMapNoJmp;
2231	STAMCOUNTER StatMemBounceBufferCrossPage;
2232	STAMCOUNTER StatMemBounceBufferMapPhys;
2233	/** @} */
2234
2235	uint64_t au64Padding[5];
2236	/** @} */
2237
2238	/** Data TLB.
2239	* @remarks Must be 64-byte aligned. */
2240	IEMTLB DataTlb;
2241	/** Instruction TLB.
2242	* @remarks Must be 64-byte aligned. */
2243	IEMTLB CodeTlb;
2244
2245	/** Exception statistics. */
2246	STAMCOUNTER aStatXcpts[32];
2247	/** Interrupt statistics. */
2248	uint32_t aStatInts[256];
2249
2250	#if defined(VBOX_WITH_STATISTICS) && !defined(DOXYGEN_RUNNING) && !defined(IEM_WITHOUT_INSTRUCTION_STATS)
2251	/** Instruction statistics for ring-0/raw-mode. */
2252	IEMINSTRSTATS StatsRZ;
2253	/** Instruction statistics for ring-3. */
2254	IEMINSTRSTATS StatsR3;
2255	# ifdef VBOX_WITH_IEM_RECOMPILER
2256	/** Statistics per threaded function call.
2257	* Updated by both the threaded and native recompilers. */
2258	uint32_t acThreadedFuncStats[0x6000 /24576/];
2259	# endif
2260	#endif
2261	} IEMCPU;
2262	AssertCompileMemberOffset(IEMCPU, cActiveMappings, 0x4f);
2263	AssertCompileMemberAlignment(IEMCPU, aMemMappings, 16);
2264	AssertCompileMemberAlignment(IEMCPU, aMemMappingLocks, 16);
2265	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 64);
2266	AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
2267	AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
2268
2269	/** Pointer to the per-CPU IEM state. */
2270	typedef IEMCPU *PIEMCPU;
2271	/** Pointer to the const per-CPU IEM state. */
2272	typedef IEMCPU const *PCIEMCPU;
2273
2274
2275	/** @def IEM_GET_CTX
2276	* Gets the guest CPU context for the calling EMT.
2277	* @returns PCPUMCTX
2278	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2279	*/
2280	#define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
2281
2282	/** @def IEM_CTX_ASSERT
2283	* Asserts that the @a a_fExtrnMbz is present in the CPU context.
2284	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2285	* @param a_fExtrnMbz The mask of CPUMCTX_EXTRN_XXX flags that must be zero.
2286	*/
2287	#define IEM_CTX_ASSERT(a_pVCpu, a_fExtrnMbz) \
2288	AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
2289	("fExtrn=%#RX64 & fExtrnMbz=%#RX64 -> %#RX64\n", \
2290	(a_pVCpu)->cpum.GstCtx.fExtrn, (a_fExtrnMbz), (a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz) ))
2291
2292	/** @def IEM_CTX_IMPORT_RET
2293	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
2294	*
2295	* Will call the keep to import the bits as needed.
2296	*
2297	* Returns on import failure.
2298	*
2299	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2300	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
2301	*/
2302	#define IEM_CTX_IMPORT_RET(a_pVCpu, a_fExtrnImport) \
2303	do { \
2304	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
2305	{ /* likely */ } \
2306	else \
2307	{ \
2308	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
2309	AssertRCReturn(rcCtxImport, rcCtxImport); \
2310	} \
2311	} while (0)
2312
2313	/** @def IEM_CTX_IMPORT_NORET
2314	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
2315	*
2316	* Will call the keep to import the bits as needed.
2317	*
2318	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2319	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
2320	*/
2321	#define IEM_CTX_IMPORT_NORET(a_pVCpu, a_fExtrnImport) \
2322	do { \
2323	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
2324	{ /* likely */ } \
2325	else \
2326	{ \
2327	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
2328	AssertLogRelRC(rcCtxImport); \
2329	} \
2330	} while (0)
2331
2332	/** @def IEM_CTX_IMPORT_JMP
2333	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
2334	*
2335	* Will call the keep to import the bits as needed.
2336	*
2337	* Jumps on import failure.
2338	*
2339	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2340	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
2341	*/
2342	#define IEM_CTX_IMPORT_JMP(a_pVCpu, a_fExtrnImport) \
2343	do { \
2344	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
2345	{ /* likely */ } \
2346	else \
2347	{ \
2348	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
2349	AssertRCStmt(rcCtxImport, IEM_DO_LONGJMP(pVCpu, rcCtxImport)); \
2350	} \
2351	} while (0)
2352
2353
2354
2355	/** @def IEM_GET_TARGET_CPU
2356	* Gets the current IEMTARGETCPU value.
2357	* @returns IEMTARGETCPU value.
2358	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2359	*/
2360	#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
2361	# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
2362	#else
2363	# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
2364	#endif
2365
2366	/** @def IEM_GET_INSTR_LEN
2367	* Gets the instruction length. */
2368	#ifdef IEM_WITH_CODE_TLB
2369	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
2370	#else
2371	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
2372	#endif
2373
2374	/** @def IEM_TRY_SETJMP
2375	* Wrapper around setjmp / try, hiding all the ugly differences.
2376	*
2377	* @note Use with extreme care as this is a fragile macro.
2378	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2379	* @param a_rcTarget The variable that should receive the status code in case
2380	* of a longjmp/throw.
2381	*/
2382	/** @def IEM_TRY_SETJMP_AGAIN
2383	* For when setjmp / try is used again in the same variable scope as a previous
2384	* IEM_TRY_SETJMP invocation.
2385	*/
2386	/** @def IEM_CATCH_LONGJMP_BEGIN
2387	* Start wrapper for catch / setjmp-else.
2388	*
2389	* This will set up a scope.
2390	*
2391	* @note Use with extreme care as this is a fragile macro.
2392	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2393	* @param a_rcTarget The variable that should receive the status code in case
2394	* of a longjmp/throw.
2395	*/
2396	/** @def IEM_CATCH_LONGJMP_END
2397	* End wrapper for catch / setjmp-else.
2398	*
2399	* This will close the scope set up by IEM_CATCH_LONGJMP_BEGIN and clean up the
2400	* state.
2401	*
2402	* @note Use with extreme care as this is a fragile macro.
2403	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2404	*/
2405	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
2406	# ifdef IEM_WITH_THROW_CATCH
2407	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
2408	a_rcTarget = VINF_SUCCESS; \
2409	try
2410	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
2411	IEM_TRY_SETJMP(a_pVCpu, a_rcTarget)
2412	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
2413	catch (int rcThrown) \
2414	{ \
2415	a_rcTarget = rcThrown
2416	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
2417	} \
2418	((void)0)
2419	# else /* !IEM_WITH_THROW_CATCH */
2420	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
2421	jmp_buf JmpBuf; \
2422	jmp_buf * volatile pSavedJmpBuf = (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf); \
2423	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
2424	if ((rcStrict = setjmp(JmpBuf)) == 0)
2425	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
2426	pSavedJmpBuf = (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf); \
2427	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
2428	if ((rcStrict = setjmp(JmpBuf)) == 0)
2429	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
2430	else \
2431	{ \
2432	((void)0)
2433	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
2434	} \
2435	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = pSavedJmpBuf
2436	# endif /* !IEM_WITH_THROW_CATCH */
2437	#endif /* IEM_WITH_SETJMP */
2438
2439
2440	/**
2441	* Shared per-VM IEM data.
2442	*/
2443	typedef struct IEM
2444	{
2445	/** The VMX APIC-access page handler type. */
2446	PGMPHYSHANDLERTYPE hVmxApicAccessPage;
2447	#ifndef VBOX_WITHOUT_CPUID_HOST_CALL
2448	/** Set if the CPUID host call functionality is enabled. */
2449	bool fCpuIdHostCall;
2450	#endif
2451	} IEM;
2452
2453
2454
2455	/** @name IEM_ACCESS_XXX - Access details.
2456	* @{ */
2457	#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
2458	#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
2459	#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
2460	#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
2461	#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
2462	#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
2463	#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
2464	#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
2465	#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
2466	#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
2467	/** The writes are partial, so if initialize the bounce buffer with the
2468	* orignal RAM content. */
2469	#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
2470	/** Used in aMemMappings to indicate that the entry is bounce buffered. */
2471	#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
2472	/** Bounce buffer with ring-3 write pending, first page. */
2473	#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
2474	/** Bounce buffer with ring-3 write pending, second page. */
2475	#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
2476	/** Not locked, accessed via the TLB. */
2477	#define IEM_ACCESS_NOT_LOCKED UINT32_C(0x00001000)
2478	/** Atomic access.
2479	* This enables special alignment checks and the VINF_EM_EMULATE_SPLIT_LOCK
2480	* fallback for misaligned stuff. See @bugref{10547}. */
2481	#define IEM_ACCESS_ATOMIC UINT32_C(0x00002000)
2482	/** Valid bit mask. */
2483	#define IEM_ACCESS_VALID_MASK UINT32_C(0x00003fff)
2484	/** Shift count for the TLB flags (upper word). */
2485	#define IEM_ACCESS_SHIFT_TLB_FLAGS 16
2486
2487	/** Atomic read+write data alias. */
2488	#define IEM_ACCESS_DATA_ATOMIC (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA \| IEM_ACCESS_ATOMIC)
2489	/** Read+write data alias. */
2490	#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
2491	/** Write data alias. */
2492	#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
2493	/** Read data alias. */
2494	#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_DATA)
2495	/** Instruction fetch alias. */
2496	#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_WHAT_CODE)
2497	/** Stack write alias. */
2498	#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
2499	/** Stack read alias. */
2500	#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_STACK)
2501	/** Stack read+write alias. */
2502	#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
2503	/** Read system table alias. */
2504	#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_SYS)
2505	/** Read+write system table alias. */
2506	#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_SYS)
2507	/** @} */
2508
2509	/** @name Prefix constants (IEMCPU::fPrefixes)
2510	* @{ */
2511	#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /*< CS segment prefix (0x2e). /
2512	#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /*< SS segment prefix (0x36). /
2513	#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /*< DS segment prefix (0x3e). /
2514	#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /*< ES segment prefix (0x26). /
2515	#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /*< FS segment prefix (0x64). /
2516	#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /*< GS segment prefix (0x65). /
2517	#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
2518
2519	#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /*< Operand size prefix (0x66). /
2520	#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /*< REX.W prefix (0x48-0x4f). /
2521	#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /*< Address size prefix (0x67). /
2522
2523	#define IEM_OP_PRF_LOCK RT_BIT_32(16) /*< Lock prefix (0xf0). /
2524	#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /*< Repeat-not-zero prefix (0xf2). /
2525	#define IEM_OP_PRF_REPZ RT_BIT_32(18) /*< Repeat-if-zero prefix (0xf3). /
2526
2527	#define IEM_OP_PRF_REX RT_BIT_32(24) /*< Any REX prefix (0x40-0x4f). /
2528	#define IEM_OP_PRF_REX_B RT_BIT_32(25) /*< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). /
2529	#define IEM_OP_PRF_REX_X RT_BIT_32(26) /*< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). /
2530	#define IEM_OP_PRF_REX_R RT_BIT_32(27) /*< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). /
2531	/** Mask with all the REX prefix flags.
2532	* This is generally for use when needing to undo the REX prefixes when they
2533	* are followed legacy prefixes and therefore does not immediately preceed
2534	* the first opcode byte.
2535	* For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
2536	#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX \| IEM_OP_PRF_REX_R \| IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X \| IEM_OP_PRF_SIZE_REX_W )
2537
2538	#define IEM_OP_PRF_VEX RT_BIT_32(28) /*< Indiciates VEX prefix. /
2539	#define IEM_OP_PRF_EVEX RT_BIT_32(29) /*< Indiciates EVEX prefix. /
2540	#define IEM_OP_PRF_XOP RT_BIT_32(30) /*< Indiciates XOP prefix. /
2541	/** @} */
2542
2543	/** @name IEMOPFORM_XXX - Opcode forms
2544	* @note These are ORed together with IEMOPHINT_XXX.
2545	* @{ */
2546	/** ModR/M: reg, r/m */
2547	#define IEMOPFORM_RM 0
2548	/** ModR/M: reg, r/m (register) */
2549	#define IEMOPFORM_RM_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
2550	/** ModR/M: reg, r/m (memory) */
2551	#define IEMOPFORM_RM_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
2552	/** ModR/M: reg, r/m, imm */
2553	#define IEMOPFORM_RMI 1
2554	/** ModR/M: reg, r/m (register), imm */
2555	#define IEMOPFORM_RMI_REG (IEMOPFORM_RMI \| IEMOPFORM_MOD3)
2556	/** ModR/M: reg, r/m (memory), imm */
2557	#define IEMOPFORM_RMI_MEM (IEMOPFORM_RMI \| IEMOPFORM_NOT_MOD3)
2558	/** ModR/M: reg, r/m, xmm0 */
2559	#define IEMOPFORM_RM0 2
2560	/** ModR/M: reg, r/m (register), xmm0 */
2561	#define IEMOPFORM_RM0_REG (IEMOPFORM_RM0 \| IEMOPFORM_MOD3)
2562	/** ModR/M: reg, r/m (memory), xmm0 */
2563	#define IEMOPFORM_RM0_MEM (IEMOPFORM_RM0 \| IEMOPFORM_NOT_MOD3)
2564	/** ModR/M: r/m, reg */
2565	#define IEMOPFORM_MR 3
2566	/** ModR/M: r/m (register), reg */
2567	#define IEMOPFORM_MR_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
2568	/** ModR/M: r/m (memory), reg */
2569	#define IEMOPFORM_MR_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
2570	/** ModR/M: r/m, reg, imm */
2571	#define IEMOPFORM_MRI 4
2572	/** ModR/M: r/m (register), reg, imm */
2573	#define IEMOPFORM_MRI_REG (IEMOPFORM_MRI \| IEMOPFORM_MOD3)
2574	/** ModR/M: r/m (memory), reg, imm */
2575	#define IEMOPFORM_MRI_MEM (IEMOPFORM_MRI \| IEMOPFORM_NOT_MOD3)
2576	/** ModR/M: r/m only */
2577	#define IEMOPFORM_M 5
2578	/** ModR/M: r/m only (register). */
2579	#define IEMOPFORM_M_REG (IEMOPFORM_M \| IEMOPFORM_MOD3)
2580	/** ModR/M: r/m only (memory). */
2581	#define IEMOPFORM_M_MEM (IEMOPFORM_M \| IEMOPFORM_NOT_MOD3)
2582	/** ModR/M: r/m, imm */
2583	#define IEMOPFORM_MI 6
2584	/** ModR/M: r/m (register), imm */
2585	#define IEMOPFORM_MI_REG (IEMOPFORM_MI \| IEMOPFORM_MOD3)
2586	/** ModR/M: r/m (memory), imm */
2587	#define IEMOPFORM_MI_MEM (IEMOPFORM_MI \| IEMOPFORM_NOT_MOD3)
2588	/** ModR/M: r/m, 1 (shift and rotate instructions) */
2589	#define IEMOPFORM_M1 7
2590	/** ModR/M: r/m (register), 1. */
2591	#define IEMOPFORM_M1_REG (IEMOPFORM_M1 \| IEMOPFORM_MOD3)
2592	/** ModR/M: r/m (memory), 1. */
2593	#define IEMOPFORM_M1_MEM (IEMOPFORM_M1 \| IEMOPFORM_NOT_MOD3)
2594	/** ModR/M: r/m, CL (shift and rotate instructions)
2595	* @todo This should just've been a generic fixed register. But the python
2596	* code doesn't needs more convincing. */
2597	#define IEMOPFORM_M_CL 8
2598	/** ModR/M: r/m (register), CL. */
2599	#define IEMOPFORM_M_CL_REG (IEMOPFORM_M_CL \| IEMOPFORM_MOD3)
2600	/** ModR/M: r/m (memory), CL. */
2601	#define IEMOPFORM_M_CL_MEM (IEMOPFORM_M_CL \| IEMOPFORM_NOT_MOD3)
2602	/** ModR/M: reg only */
2603	#define IEMOPFORM_R 9
2604
2605	/** VEX+ModR/M: reg, r/m */
2606	#define IEMOPFORM_VEX_RM 16
2607	/** VEX+ModR/M: reg, r/m (register) */
2608	#define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM \| IEMOPFORM_MOD3)
2609	/** VEX+ModR/M: reg, r/m (memory) */
2610	#define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM \| IEMOPFORM_NOT_MOD3)
2611	/** VEX+ModR/M: r/m, reg */
2612	#define IEMOPFORM_VEX_MR 17
2613	/** VEX+ModR/M: r/m (register), reg */
2614	#define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR \| IEMOPFORM_MOD3)
2615	/** VEX+ModR/M: r/m (memory), reg */
2616	#define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR \| IEMOPFORM_NOT_MOD3)
2617	/** VEX+ModR/M: r/m, reg, imm8 */
2618	#define IEMOPFORM_VEX_MRI 18
2619	/** VEX+ModR/M: r/m (register), reg, imm8 */
2620	#define IEMOPFORM_VEX_MRI_REG (IEMOPFORM_VEX_MRI \| IEMOPFORM_MOD3)
2621	/** VEX+ModR/M: r/m (memory), reg, imm8 */
2622	#define IEMOPFORM_VEX_MRI_MEM (IEMOPFORM_VEX_MRI \| IEMOPFORM_NOT_MOD3)
2623	/** VEX+ModR/M: r/m only */
2624	#define IEMOPFORM_VEX_M 19
2625	/** VEX+ModR/M: r/m only (register). */
2626	#define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M \| IEMOPFORM_MOD3)
2627	/** VEX+ModR/M: r/m only (memory). */
2628	#define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M \| IEMOPFORM_NOT_MOD3)
2629	/** VEX+ModR/M: reg only */
2630	#define IEMOPFORM_VEX_R 20
2631	/** VEX+ModR/M: reg, vvvv, r/m */
2632	#define IEMOPFORM_VEX_RVM 21
2633	/** VEX+ModR/M: reg, vvvv, r/m (register). */
2634	#define IEMOPFORM_VEX_RVM_REG (IEMOPFORM_VEX_RVM \| IEMOPFORM_MOD3)
2635	/** VEX+ModR/M: reg, vvvv, r/m (memory). */
2636	#define IEMOPFORM_VEX_RVM_MEM (IEMOPFORM_VEX_RVM \| IEMOPFORM_NOT_MOD3)
2637	/** VEX+ModR/M: reg, vvvv, r/m, imm */
2638	#define IEMOPFORM_VEX_RVMI 22
2639	/** VEX+ModR/M: reg, vvvv, r/m (register), imm. */
2640	#define IEMOPFORM_VEX_RVMI_REG (IEMOPFORM_VEX_RVMI \| IEMOPFORM_MOD3)
2641	/** VEX+ModR/M: reg, vvvv, r/m (memory), imm. */
2642	#define IEMOPFORM_VEX_RVMI_MEM (IEMOPFORM_VEX_RVMI \| IEMOPFORM_NOT_MOD3)
2643	/** VEX+ModR/M: reg, vvvv, r/m, imm(reg) */
2644	#define IEMOPFORM_VEX_RVMR 23
2645	/** VEX+ModR/M: reg, vvvv, r/m (register), imm(reg). */
2646	#define IEMOPFORM_VEX_RVMR_REG (IEMOPFORM_VEX_RVMI \| IEMOPFORM_MOD3)
2647	/** VEX+ModR/M: reg, vvvv, r/m (memory), imm(reg). */
2648	#define IEMOPFORM_VEX_RVMR_MEM (IEMOPFORM_VEX_RVMI \| IEMOPFORM_NOT_MOD3)
2649	/** VEX+ModR/M: reg, r/m, vvvv */
2650	#define IEMOPFORM_VEX_RMV 24
2651	/** VEX+ModR/M: reg, r/m, vvvv (register). */
2652	#define IEMOPFORM_VEX_RMV_REG (IEMOPFORM_VEX_RMV \| IEMOPFORM_MOD3)
2653	/** VEX+ModR/M: reg, r/m, vvvv (memory). */
2654	#define IEMOPFORM_VEX_RMV_MEM (IEMOPFORM_VEX_RMV \| IEMOPFORM_NOT_MOD3)
2655	/** VEX+ModR/M: reg, r/m, imm8 */
2656	#define IEMOPFORM_VEX_RMI 25
2657	/** VEX+ModR/M: reg, r/m, imm8 (register). */
2658	#define IEMOPFORM_VEX_RMI_REG (IEMOPFORM_VEX_RMI \| IEMOPFORM_MOD3)
2659	/** VEX+ModR/M: reg, r/m, imm8 (memory). */
2660	#define IEMOPFORM_VEX_RMI_MEM (IEMOPFORM_VEX_RMI \| IEMOPFORM_NOT_MOD3)
2661	/** VEX+ModR/M: r/m, vvvv, reg */
2662	#define IEMOPFORM_VEX_MVR 26
2663	/** VEX+ModR/M: r/m, vvvv, reg (register) */
2664	#define IEMOPFORM_VEX_MVR_REG (IEMOPFORM_VEX_MVR \| IEMOPFORM_MOD3)
2665	/** VEX+ModR/M: r/m, vvvv, reg (memory) */
2666	#define IEMOPFORM_VEX_MVR_MEM (IEMOPFORM_VEX_MVR \| IEMOPFORM_NOT_MOD3)
2667	/** VEX+ModR/M+/n: vvvv, r/m */
2668	#define IEMOPFORM_VEX_VM 27
2669	/** VEX+ModR/M+/n: vvvv, r/m (register) */
2670	#define IEMOPFORM_VEX_VM_REG (IEMOPFORM_VEX_VM \| IEMOPFORM_MOD3)
2671	/** VEX+ModR/M+/n: vvvv, r/m (memory) */
2672	#define IEMOPFORM_VEX_VM_MEM (IEMOPFORM_VEX_VM \| IEMOPFORM_NOT_MOD3)
2673	/** VEX+ModR/M+/n: vvvv, r/m, imm8 */
2674	#define IEMOPFORM_VEX_VMI 28
2675	/** VEX+ModR/M+/n: vvvv, r/m, imm8 (register) */
2676	#define IEMOPFORM_VEX_VMI_REG (IEMOPFORM_VEX_VMI \| IEMOPFORM_MOD3)
2677	/** VEX+ModR/M+/n: vvvv, r/m, imm8 (memory) */
2678	#define IEMOPFORM_VEX_VMI_MEM (IEMOPFORM_VEX_VMI \| IEMOPFORM_NOT_MOD3)
2679
2680	/** Fixed register instruction, no R/M. */
2681	#define IEMOPFORM_FIXED 32
2682
2683	/** The r/m is a register. */
2684	#define IEMOPFORM_MOD3 RT_BIT_32(8)
2685	/** The r/m is a memory access. */
2686	#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
2687	/** @} */
2688
2689	/** @name IEMOPHINT_XXX - Additional Opcode Hints
2690	* @note These are ORed together with IEMOPFORM_XXX.
2691	* @{ */
2692	/** Ignores the operand size prefix (66h). */
2693	#define IEMOPHINT_IGNORES_OZ_PFX RT_BIT_32(10)
2694	/** Ignores REX.W (aka WIG). */
2695	#define IEMOPHINT_IGNORES_REXW RT_BIT_32(11)
2696	/** Both the operand size prefixes (66h + REX.W) are ignored. */
2697	#define IEMOPHINT_IGNORES_OP_SIZES (IEMOPHINT_IGNORES_OZ_PFX \| IEMOPHINT_IGNORES_REXW)
2698	/** Allowed with the lock prefix. */
2699	#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
2700	/** The VEX.L value is ignored (aka LIG). */
2701	#define IEMOPHINT_VEX_L_IGNORED RT_BIT_32(12)
2702	/** The VEX.L value must be zero (i.e. 128-bit width only). */
2703	#define IEMOPHINT_VEX_L_ZERO RT_BIT_32(13)
2704	/** The VEX.L value must be one (i.e. 256-bit width only). */
2705	#define IEMOPHINT_VEX_L_ONE RT_BIT_32(14)
2706	/** The VEX.V value must be zero. */
2707	#define IEMOPHINT_VEX_V_ZERO RT_BIT_32(15)
2708	/** The REX.W/VEX.V value must be zero. */
2709	#define IEMOPHINT_REX_W_ZERO RT_BIT_32(16)
2710	#define IEMOPHINT_VEX_W_ZERO IEMOPHINT_REX_W_ZERO
2711	/** The REX.W/VEX.V value must be one. */
2712	#define IEMOPHINT_REX_W_ONE RT_BIT_32(17)
2713	#define IEMOPHINT_VEX_W_ONE IEMOPHINT_REX_W_ONE
2714
2715	/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
2716	#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
2717	/** @} */
2718
2719	/**
2720	* Possible hardware task switch sources.
2721	*/
2722	typedef enum IEMTASKSWITCH
2723	{
2724	/** Task switch caused by an interrupt/exception. */
2725	IEMTASKSWITCH_INT_XCPT = 1,
2726	/** Task switch caused by a far CALL. */
2727	IEMTASKSWITCH_CALL,
2728	/** Task switch caused by a far JMP. */
2729	IEMTASKSWITCH_JUMP,
2730	/** Task switch caused by an IRET. */
2731	IEMTASKSWITCH_IRET
2732	} IEMTASKSWITCH;
2733	AssertCompileSize(IEMTASKSWITCH, 4);
2734
2735	/**
2736	* Possible CrX load (write) sources.
2737	*/
2738	typedef enum IEMACCESSCRX
2739	{
2740	/** CrX access caused by 'mov crX' instruction. */
2741	IEMACCESSCRX_MOV_CRX,
2742	/** CrX (CR0) write caused by 'lmsw' instruction. */
2743	IEMACCESSCRX_LMSW,
2744	/** CrX (CR0) write caused by 'clts' instruction. */
2745	IEMACCESSCRX_CLTS,
2746	/** CrX (CR0) read caused by 'smsw' instruction. */
2747	IEMACCESSCRX_SMSW
2748	} IEMACCESSCRX;
2749
2750	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2751	/** @name IEM_SLAT_FAIL_XXX - Second-level address translation failure information.
2752	*
2753	* These flags provide further context to SLAT page-walk failures that could not be
2754	* determined by PGM (e.g, PGM is not privy to memory access permissions).
2755	*
2756	* @{
2757	*/
2758	/** Translating a nested-guest linear address failed accessing a nested-guest
2759	* physical address. */
2760	# define IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR RT_BIT_32(0)
2761	/** Translating a nested-guest linear address failed accessing a
2762	* paging-structure entry or updating accessed/dirty bits. */
2763	# define IEM_SLAT_FAIL_LINEAR_TO_PAGE_TABLE RT_BIT_32(1)
2764	/** @} */
2765
2766	DECLCALLBACK(FNPGMPHYSHANDLER) iemVmxApicAccessPageHandler;
2767	# ifndef IN_RING3
2768	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) iemVmxApicAccessPagePfHandler;
2769	# endif
2770	#endif
2771
2772	/**
2773	* Indicates to the verifier that the given flag set is undefined.
2774	*
2775	* Can be invoked again to add more flags.
2776	*
2777	* This is a NOOP if the verifier isn't compiled in.
2778	*
2779	* @note We're temporarily keeping this until code is converted to new
2780	* disassembler style opcode handling.
2781	*/
2782	#define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
2783
2784
2785	/** @def IEM_DECL_IMPL_TYPE
2786	* For typedef'ing an instruction implementation function.
2787	*
2788	* @param a_RetType The return type.
2789	* @param a_Name The name of the type.
2790	* @param a_ArgList The argument list enclosed in parentheses.
2791	*/
2792
2793	/** @def IEM_DECL_IMPL_DEF
2794	* For defining an instruction implementation function.
2795	*
2796	* @param a_RetType The return type.
2797	* @param a_Name The name of the type.
2798	* @param a_ArgList The argument list enclosed in parentheses.
2799	*/
2800
2801	#if defined(__GNUC__) && defined(RT_ARCH_X86)
2802	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2803	__attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
2804	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2805	__attribute__((__fastcall__, __nothrow__)) DECL_HIDDEN_ONLY(a_RetType) a_Name a_ArgList
2806	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2807	__attribute__((__fastcall__, __nothrow__)) DECL_HIDDEN_ONLY(a_RetType) a_Name a_ArgList
2808
2809	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
2810	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2811	a_RetType (__fastcall a_Name) a_ArgList
2812	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2813	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
2814	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2815	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
2816
2817	#elif __cplusplus >= 201700 /* P0012R1 support */
2818	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2819	a_RetType (VBOXCALL a_Name) a_ArgList RT_NOEXCEPT
2820	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2821	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList RT_NOEXCEPT
2822	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2823	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList RT_NOEXCEPT
2824
2825	#else
2826	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
2827	a_RetType (VBOXCALL a_Name) a_ArgList
2828	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
2829	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList
2830	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
2831	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList
2832
2833	#endif
2834
2835	/** Defined in IEMAllAImplC.cpp but also used by IEMAllAImplA.asm. */
2836	RT_C_DECLS_BEGIN
2837	extern uint8_t const g_afParity[256];
2838	RT_C_DECLS_END
2839
2840
2841	/** @name Arithmetic assignment operations on bytes (binary).
2842	* @{ */
2843	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU8, (uint32_t fEFlagsIn, uint8_t *pu8Dst, uint8_t u8Src));
2844	typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
2845	FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
2846	FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
2847	FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
2848	FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
2849	FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
2850	FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
2851	FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
2852	/** @} */
2853
2854	/** @name Arithmetic assignment operations on words (binary).
2855	* @{ */
2856	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU16, (uint32_t fEFlagsIn, uint16_t *pu16Dst, uint16_t u16Src));
2857	typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
2858	FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
2859	FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
2860	FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
2861	FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
2862	FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
2863	FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
2864	FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
2865	/** @} */
2866
2867
2868	/** @name Arithmetic assignment operations on double words (binary).
2869	* @{ */
2870	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU32, (uint32_t fEFlagsIn, uint32_t *pu32Dst, uint32_t u32Src));
2871	typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
2872	FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
2873	FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
2874	FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
2875	FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
2876	FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
2877	FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
2878	FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
2879	FNIEMAIMPLBINU32 iemAImpl_blsi_u32, iemAImpl_blsi_u32_fallback;
2880	FNIEMAIMPLBINU32 iemAImpl_blsr_u32, iemAImpl_blsr_u32_fallback;
2881	FNIEMAIMPLBINU32 iemAImpl_blsmsk_u32, iemAImpl_blsmsk_u32_fallback;
2882	/** @} */
2883
2884	/** @name Arithmetic assignment operations on quad words (binary).
2885	* @{ */
2886	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU64, (uint32_t fEFlagsIn, uint64_t *pu64Dst, uint64_t u64Src));
2887	typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
2888	FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
2889	FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
2890	FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
2891	FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
2892	FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
2893	FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
2894	FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
2895	FNIEMAIMPLBINU64 iemAImpl_blsi_u64, iemAImpl_blsi_u64_fallback;
2896	FNIEMAIMPLBINU64 iemAImpl_blsr_u64, iemAImpl_blsr_u64_fallback;
2897	FNIEMAIMPLBINU64 iemAImpl_blsmsk_u64, iemAImpl_blsmsk_u64_fallback;
2898	/** @} */
2899
2900	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU8, (uint32_t fEFlagsIn, uint8_t const *pu8Dst, uint8_t u8Src));
2901	typedef FNIEMAIMPLBINROU8 *PFNIEMAIMPLBINROU8;
2902	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU16,(uint32_t fEFlagsIn, uint16_t const *pu16Dst, uint16_t u16Src));
2903	typedef FNIEMAIMPLBINROU16 *PFNIEMAIMPLBINROU16;
2904	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU32,(uint32_t fEFlagsIn, uint32_t const *pu32Dst, uint32_t u32Src));
2905	typedef FNIEMAIMPLBINROU32 *PFNIEMAIMPLBINROU32;
2906	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU64,(uint32_t fEFlagsIn, uint64_t const *pu64Dst, uint64_t u64Src));
2907	typedef FNIEMAIMPLBINROU64 *PFNIEMAIMPLBINROU64;
2908
2909	/** @name Compare operations (thrown in with the binary ops).
2910	* @{ */
2911	FNIEMAIMPLBINROU8 iemAImpl_cmp_u8;
2912	FNIEMAIMPLBINROU16 iemAImpl_cmp_u16;
2913	FNIEMAIMPLBINROU32 iemAImpl_cmp_u32;
2914	FNIEMAIMPLBINROU64 iemAImpl_cmp_u64;
2915	/** @} */
2916
2917	/** @name Test operations (thrown in with the binary ops).
2918	* @{ */
2919	FNIEMAIMPLBINROU8 iemAImpl_test_u8;
2920	FNIEMAIMPLBINROU16 iemAImpl_test_u16;
2921	FNIEMAIMPLBINROU32 iemAImpl_test_u32;
2922	FNIEMAIMPLBINROU64 iemAImpl_test_u64;
2923	/** @} */
2924
2925	/** @name Bit operations operations (thrown in with the binary ops).
2926	* @{ */
2927	FNIEMAIMPLBINROU16 iemAImpl_bt_u16;
2928	FNIEMAIMPLBINROU32 iemAImpl_bt_u32;
2929	FNIEMAIMPLBINROU64 iemAImpl_bt_u64;
2930	FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
2931	FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
2932	FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
2933	FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
2934	FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
2935	FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
2936	FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
2937	FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
2938	FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
2939	/** @} */
2940
2941	/** @name Arithmetic three operand operations on double words (binary).
2942	* @{ */
2943	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32, (uint32_t pu32Dst, uint32_t u32Src1, uint32_t u32Src2, uint32_t pEFlags));
2944	typedef FNIEMAIMPLBINVEXU32 *PFNIEMAIMPLBINVEXU32;
2945	FNIEMAIMPLBINVEXU32 iemAImpl_andn_u32, iemAImpl_andn_u32_fallback;
2946	FNIEMAIMPLBINVEXU32 iemAImpl_bextr_u32, iemAImpl_bextr_u32_fallback;
2947	FNIEMAIMPLBINVEXU32 iemAImpl_bzhi_u32, iemAImpl_bzhi_u32_fallback;
2948	/** @} */
2949
2950	/** @name Arithmetic three operand operations on quad words (binary).
2951	* @{ */
2952	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64, (uint64_t pu64Dst, uint64_t u64Src1, uint64_t u64Src2, uint32_t pEFlags));
2953	typedef FNIEMAIMPLBINVEXU64 *PFNIEMAIMPLBINVEXU64;
2954	FNIEMAIMPLBINVEXU64 iemAImpl_andn_u64, iemAImpl_andn_u64_fallback;
2955	FNIEMAIMPLBINVEXU64 iemAImpl_bextr_u64, iemAImpl_bextr_u64_fallback;
2956	FNIEMAIMPLBINVEXU64 iemAImpl_bzhi_u64, iemAImpl_bzhi_u64_fallback;
2957	/** @} */
2958
2959	/** @name Arithmetic three operand operations on double words w/o EFLAGS (binary).
2960	* @{ */
2961	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32NOEFL, (uint32_t *pu32Dst, uint32_t u32Src1, uint32_t u32Src2));
2962	typedef FNIEMAIMPLBINVEXU32NOEFL *PFNIEMAIMPLBINVEXU32NOEFL;
2963	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pdep_u32, iemAImpl_pdep_u32_fallback;
2964	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pext_u32, iemAImpl_pext_u32_fallback;
2965	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_sarx_u32, iemAImpl_sarx_u32_fallback;
2966	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shlx_u32, iemAImpl_shlx_u32_fallback;
2967	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shrx_u32, iemAImpl_shrx_u32_fallback;
2968	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_rorx_u32;
2969	/** @} */
2970
2971	/** @name Arithmetic three operand operations on quad words w/o EFLAGS (binary).
2972	* @{ */
2973	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64NOEFL, (uint64_t *pu64Dst, uint64_t u64Src1, uint64_t u64Src2));
2974	typedef FNIEMAIMPLBINVEXU64NOEFL *PFNIEMAIMPLBINVEXU64NOEFL;
2975	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pdep_u64, iemAImpl_pdep_u64_fallback;
2976	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pext_u64, iemAImpl_pext_u64_fallback;
2977	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_sarx_u64, iemAImpl_sarx_u64_fallback;
2978	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shlx_u64, iemAImpl_shlx_u64_fallback;
2979	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shrx_u64, iemAImpl_shrx_u64_fallback;
2980	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_rorx_u64;
2981	/** @} */
2982
2983	/** @name MULX 32-bit and 64-bit.
2984	* @{ */
2985	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU32, (uint32_t puDst1, uint32_t puDst2, uint32_t uSrc1, uint32_t uSrc2));
2986	typedef FNIEMAIMPLMULXVEXU32 *PFNIEMAIMPLMULXVEXU32;
2987	FNIEMAIMPLMULXVEXU32 iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback;
2988
2989	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU64, (uint64_t puDst1, uint64_t puDst2, uint64_t uSrc1, uint64_t uSrc2));
2990	typedef FNIEMAIMPLMULXVEXU64 *PFNIEMAIMPLMULXVEXU64;
2991	FNIEMAIMPLMULXVEXU64 iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback;
2992	/** @} */
2993
2994
2995	/** @name Exchange memory with register operations.
2996	* @{ */
2997	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_locked, (uint8_t pu8Mem, uint8_t pu8Reg));
2998	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_locked,(uint16_t pu16Mem, uint16_t pu16Reg));
2999	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_locked,(uint32_t pu32Mem, uint32_t pu32Reg));
3000	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_locked,(uint64_t pu64Mem, uint64_t pu64Reg));
3001	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_unlocked, (uint8_t pu8Mem, uint8_t pu8Reg));
3002	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_unlocked,(uint16_t pu16Mem, uint16_t pu16Reg));
3003	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_unlocked,(uint32_t pu32Mem, uint32_t pu32Reg));
3004	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_unlocked,(uint64_t pu64Mem, uint64_t pu64Reg));
3005	/** @} */
3006
3007	/** @name Exchange and add operations.
3008	* @{ */
3009	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
3010	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
3011	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
3012	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
3013	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
3014	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
3015	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
3016	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
3017	/** @} */
3018
3019	/** @name Compare and exchange.
3020	* @{ */
3021	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
3022	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
3023	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
3024	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
3025	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
3026	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
3027	#if ARCH_BITS == 32
3028	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
3029	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
3030	#else
3031	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
3032	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
3033	#endif
3034	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
3035	uint32_t *pEFlags));
3036	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
3037	uint32_t *pEFlags));
3038	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
3039	uint32_t *pEFlags));
3040	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
3041	uint32_t *pEFlags));
3042	#ifndef RT_ARCH_ARM64
3043	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
3044	PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
3045	#endif
3046	/** @} */
3047
3048	/** @name Memory ordering
3049	* @{ */
3050	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
3051	typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
3052	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
3053	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
3054	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
3055	#ifndef RT_ARCH_ARM64
3056	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
3057	#endif
3058	/** @} */
3059
3060	/** @name Double precision shifts
3061	* @{ */
3062	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t pEFlags));
3063	typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
3064	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t pEFlags));
3065	typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
3066	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t pEFlags));
3067	typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
3068	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16, iemAImpl_shld_u16_amd, iemAImpl_shld_u16_intel;
3069	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32, iemAImpl_shld_u32_amd, iemAImpl_shld_u32_intel;
3070	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64, iemAImpl_shld_u64_amd, iemAImpl_shld_u64_intel;
3071	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16, iemAImpl_shrd_u16_amd, iemAImpl_shrd_u16_intel;
3072	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32, iemAImpl_shrd_u32_amd, iemAImpl_shrd_u32_intel;
3073	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64, iemAImpl_shrd_u64_amd, iemAImpl_shrd_u64_intel;
3074	/** @} */
3075
3076
3077	/** @name Bit search operations (thrown in with the binary ops).
3078	* @{ */
3079	FNIEMAIMPLBINU16 iemAImpl_bsf_u16, iemAImpl_bsf_u16_amd, iemAImpl_bsf_u16_intel;
3080	FNIEMAIMPLBINU32 iemAImpl_bsf_u32, iemAImpl_bsf_u32_amd, iemAImpl_bsf_u32_intel;
3081	FNIEMAIMPLBINU64 iemAImpl_bsf_u64, iemAImpl_bsf_u64_amd, iemAImpl_bsf_u64_intel;
3082	FNIEMAIMPLBINU16 iemAImpl_bsr_u16, iemAImpl_bsr_u16_amd, iemAImpl_bsr_u16_intel;
3083	FNIEMAIMPLBINU32 iemAImpl_bsr_u32, iemAImpl_bsr_u32_amd, iemAImpl_bsr_u32_intel;
3084	FNIEMAIMPLBINU64 iemAImpl_bsr_u64, iemAImpl_bsr_u64_amd, iemAImpl_bsr_u64_intel;
3085	FNIEMAIMPLBINU16 iemAImpl_lzcnt_u16, iemAImpl_lzcnt_u16_amd, iemAImpl_lzcnt_u16_intel;
3086	FNIEMAIMPLBINU32 iemAImpl_lzcnt_u32, iemAImpl_lzcnt_u32_amd, iemAImpl_lzcnt_u32_intel;
3087	FNIEMAIMPLBINU64 iemAImpl_lzcnt_u64, iemAImpl_lzcnt_u64_amd, iemAImpl_lzcnt_u64_intel;
3088	FNIEMAIMPLBINU16 iemAImpl_tzcnt_u16, iemAImpl_tzcnt_u16_amd, iemAImpl_tzcnt_u16_intel;
3089	FNIEMAIMPLBINU32 iemAImpl_tzcnt_u32, iemAImpl_tzcnt_u32_amd, iemAImpl_tzcnt_u32_intel;
3090	FNIEMAIMPLBINU64 iemAImpl_tzcnt_u64, iemAImpl_tzcnt_u64_amd, iemAImpl_tzcnt_u64_intel;
3091	FNIEMAIMPLBINU16 iemAImpl_popcnt_u16, iemAImpl_popcnt_u16_fallback;
3092	FNIEMAIMPLBINU32 iemAImpl_popcnt_u32, iemAImpl_popcnt_u32_fallback;
3093	FNIEMAIMPLBINU64 iemAImpl_popcnt_u64, iemAImpl_popcnt_u64_fallback;
3094	/** @} */
3095
3096	/** @name Signed multiplication operations (thrown in with the binary ops).
3097	* @{ */
3098	FNIEMAIMPLBINU16 iemAImpl_imul_two_u16, iemAImpl_imul_two_u16_amd, iemAImpl_imul_two_u16_intel;
3099	FNIEMAIMPLBINU32 iemAImpl_imul_two_u32, iemAImpl_imul_two_u32_amd, iemAImpl_imul_two_u32_intel;
3100	FNIEMAIMPLBINU64 iemAImpl_imul_two_u64, iemAImpl_imul_two_u64_amd, iemAImpl_imul_two_u64_intel;
3101	/** @} */
3102
3103	/** @name Arithmetic assignment operations on bytes (unary).
3104	* @{ */
3105	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t pu8Dst, uint32_t pEFlags));
3106	typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
3107	FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
3108	FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
3109	FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
3110	FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
3111	/** @} */
3112
3113	/** @name Arithmetic assignment operations on words (unary).
3114	* @{ */
3115	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t pu16Dst, uint32_t pEFlags));
3116	typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
3117	FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
3118	FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
3119	FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
3120	FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
3121	/** @} */
3122
3123	/** @name Arithmetic assignment operations on double words (unary).
3124	* @{ */
3125	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t pu32Dst, uint32_t pEFlags));
3126	typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
3127	FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
3128	FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
3129	FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
3130	FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
3131	/** @} */
3132
3133	/** @name Arithmetic assignment operations on quad words (unary).
3134	* @{ */
3135	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t pu64Dst, uint32_t pEFlags));
3136	typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
3137	FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
3138	FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
3139	FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
3140	FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
3141	/** @} */
3142
3143
3144	/** @name Shift operations on bytes (Group 2).
3145	* @{ */
3146	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU8,(uint32_t fEFlagsIn, uint8_t *pu8Dst, uint8_t cShift));
3147	typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
3148	FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8, iemAImpl_rol_u8_amd, iemAImpl_rol_u8_intel;
3149	FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8, iemAImpl_ror_u8_amd, iemAImpl_ror_u8_intel;
3150	FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8, iemAImpl_rcl_u8_amd, iemAImpl_rcl_u8_intel;
3151	FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8, iemAImpl_rcr_u8_amd, iemAImpl_rcr_u8_intel;
3152	FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8, iemAImpl_shl_u8_amd, iemAImpl_shl_u8_intel;
3153	FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8, iemAImpl_shr_u8_amd, iemAImpl_shr_u8_intel;
3154	FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8, iemAImpl_sar_u8_amd, iemAImpl_sar_u8_intel;
3155	/** @} */
3156
3157	/** @name Shift operations on words (Group 2).
3158	* @{ */
3159	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU16,(uint32_t fEFlagsIn, uint16_t *pu16Dst, uint8_t cShift));
3160	typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
3161	FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16, iemAImpl_rol_u16_amd, iemAImpl_rol_u16_intel;
3162	FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16, iemAImpl_ror_u16_amd, iemAImpl_ror_u16_intel;
3163	FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16, iemAImpl_rcl_u16_amd, iemAImpl_rcl_u16_intel;
3164	FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16, iemAImpl_rcr_u16_amd, iemAImpl_rcr_u16_intel;
3165	FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16, iemAImpl_shl_u16_amd, iemAImpl_shl_u16_intel;
3166	FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16, iemAImpl_shr_u16_amd, iemAImpl_shr_u16_intel;
3167	FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16, iemAImpl_sar_u16_amd, iemAImpl_sar_u16_intel;
3168	/** @} */
3169
3170	/** @name Shift operations on double words (Group 2).
3171	* @{ */
3172	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU32,(uint32_t fEFlagsIn, uint32_t *pu32Dst, uint8_t cShift));
3173	typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
3174	FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32, iemAImpl_rol_u32_amd, iemAImpl_rol_u32_intel;
3175	FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32, iemAImpl_ror_u32_amd, iemAImpl_ror_u32_intel;
3176	FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32, iemAImpl_rcl_u32_amd, iemAImpl_rcl_u32_intel;
3177	FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32, iemAImpl_rcr_u32_amd, iemAImpl_rcr_u32_intel;
3178	FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32, iemAImpl_shl_u32_amd, iemAImpl_shl_u32_intel;
3179	FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32, iemAImpl_shr_u32_amd, iemAImpl_shr_u32_intel;
3180	FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32, iemAImpl_sar_u32_amd, iemAImpl_sar_u32_intel;
3181	/** @} */
3182
3183	/** @name Shift operations on words (Group 2).
3184	* @{ */
3185	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU64,(uint32_t fEFlagsIn, uint64_t *pu64Dst, uint8_t cShift));
3186	typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
3187	FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64, iemAImpl_rol_u64_amd, iemAImpl_rol_u64_intel;
3188	FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64, iemAImpl_ror_u64_amd, iemAImpl_ror_u64_intel;
3189	FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64, iemAImpl_rcl_u64_amd, iemAImpl_rcl_u64_intel;
3190	FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64, iemAImpl_rcr_u64_amd, iemAImpl_rcr_u64_intel;
3191	FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64, iemAImpl_shl_u64_amd, iemAImpl_shl_u64_intel;
3192	FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64, iemAImpl_shr_u64_amd, iemAImpl_shr_u64_intel;
3193	FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64, iemAImpl_sar_u64_amd, iemAImpl_sar_u64_intel;
3194	/** @} */
3195
3196	/** @name Multiplication and division operations.
3197	* @{ */
3198	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t pu16AX, uint8_t u8FactorDivisor, uint32_t pEFlags));
3199	typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
3200	FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_mul_u8_amd, iemAImpl_mul_u8_intel;
3201	FNIEMAIMPLMULDIVU8 iemAImpl_imul_u8, iemAImpl_imul_u8_amd, iemAImpl_imul_u8_intel;
3202	FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_div_u8_amd, iemAImpl_div_u8_intel;
3203	FNIEMAIMPLMULDIVU8 iemAImpl_idiv_u8, iemAImpl_idiv_u8_amd, iemAImpl_idiv_u8_intel;
3204
3205	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t pu16AX, uint16_t pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
3206	typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
3207	FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_mul_u16_amd, iemAImpl_mul_u16_intel;
3208	FNIEMAIMPLMULDIVU16 iemAImpl_imul_u16, iemAImpl_imul_u16_amd, iemAImpl_imul_u16_intel;
3209	FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_div_u16_amd, iemAImpl_div_u16_intel;
3210	FNIEMAIMPLMULDIVU16 iemAImpl_idiv_u16, iemAImpl_idiv_u16_amd, iemAImpl_idiv_u16_intel;
3211
3212	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t pu32EAX, uint32_t pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
3213	typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
3214	FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_mul_u32_amd, iemAImpl_mul_u32_intel;
3215	FNIEMAIMPLMULDIVU32 iemAImpl_imul_u32, iemAImpl_imul_u32_amd, iemAImpl_imul_u32_intel;
3216	FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_div_u32_amd, iemAImpl_div_u32_intel;
3217	FNIEMAIMPLMULDIVU32 iemAImpl_idiv_u32, iemAImpl_idiv_u32_amd, iemAImpl_idiv_u32_intel;
3218
3219	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t pu64RAX, uint64_t pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
3220	typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
3221	FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_mul_u64_amd, iemAImpl_mul_u64_intel;
3222	FNIEMAIMPLMULDIVU64 iemAImpl_imul_u64, iemAImpl_imul_u64_amd, iemAImpl_imul_u64_intel;
3223	FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_div_u64_amd, iemAImpl_div_u64_intel;
3224	FNIEMAIMPLMULDIVU64 iemAImpl_idiv_u64, iemAImpl_idiv_u64_amd, iemAImpl_idiv_u64_intel;
3225	/** @} */
3226
3227	/** @name Byte Swap.
3228	* @{ */
3229	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t pu32Dst)); / Yes, 32-bit register access. */
3230	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
3231	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
3232	/** @} */
3233
3234	/** @name Misc.
3235	* @{ */
3236	FNIEMAIMPLBINU16 iemAImpl_arpl;
3237	/** @} */
3238
3239	/** @name RDRAND and RDSEED
3240	* @{ */
3241	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU16,(uint16_t puDst, uint32_t pEFlags));
3242	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU32,(uint32_t puDst, uint32_t pEFlags));
3243	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU64,(uint64_t puDst, uint32_t pEFlags));
3244	typedef FNIEMAIMPLRDRANDSEEDU16 *PFNIEMAIMPLRDRANDSEEDU16;
3245	typedef FNIEMAIMPLRDRANDSEEDU32 *PFNIEMAIMPLRDRANDSEEDU32;
3246	typedef FNIEMAIMPLRDRANDSEEDU64 *PFNIEMAIMPLRDRANDSEEDU64;
3247
3248	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdrand_u16, iemAImpl_rdrand_u16_fallback;
3249	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdrand_u32, iemAImpl_rdrand_u32_fallback;
3250	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdrand_u64, iemAImpl_rdrand_u64_fallback;
3251	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdseed_u16, iemAImpl_rdseed_u16_fallback;
3252	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdseed_u32, iemAImpl_rdseed_u32_fallback;
3253	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdseed_u64, iemAImpl_rdseed_u64_fallback;
3254	/** @} */
3255
3256	/** @name ADOX and ADCX
3257	* @{ */
3258	FNIEMAIMPLBINU32 iemAImpl_adcx_u32, iemAImpl_adcx_u32_fallback;
3259	FNIEMAIMPLBINU64 iemAImpl_adcx_u64, iemAImpl_adcx_u64_fallback;
3260	FNIEMAIMPLBINU32 iemAImpl_adox_u32, iemAImpl_adox_u32_fallback;
3261	FNIEMAIMPLBINU64 iemAImpl_adox_u64, iemAImpl_adox_u64_fallback;
3262	/** @} */
3263
3264	/** @name FPU operations taking a 32-bit float argument
3265	* @{ */
3266	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3267	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
3268	typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
3269
3270	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3271	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
3272	typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
3273
3274	FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
3275	FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
3276	FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
3277	FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
3278	FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
3279	FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
3280	FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
3281
3282	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
3283	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3284	PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
3285	/** @} */
3286
3287	/** @name FPU operations taking a 64-bit float argument
3288	* @{ */
3289	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3290	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
3291	typedef FNIEMAIMPLFPUR64FSW *PFNIEMAIMPLFPUR64FSW;
3292
3293	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3294	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
3295	typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
3296
3297	FNIEMAIMPLFPUR64FSW iemAImpl_fcom_r80_by_r64;
3298	FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
3299	FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
3300	FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
3301	FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
3302	FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
3303	FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
3304
3305	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
3306	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3307	PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
3308	/** @} */
3309
3310	/** @name FPU operations taking a 80-bit float argument
3311	* @{ */
3312	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3313	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
3314	typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
3315	FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
3316	FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
3317	FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
3318	FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
3319	FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
3320	FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
3321	FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
3322	FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
3323	FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
3324
3325	FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80, iemAImpl_fpatan_r80_by_r80_amd, iemAImpl_fpatan_r80_by_r80_intel;
3326	FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80, iemAImpl_fyl2x_r80_by_r80_amd, iemAImpl_fyl2x_r80_by_r80_intel;
3327	FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80, iemAImpl_fyl2xp1_r80_by_r80_amd, iemAImpl_fyl2xp1_r80_by_r80_intel;
3328
3329	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3330	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
3331	typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
3332	FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
3333	FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
3334
3335	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
3336	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
3337	typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
3338	FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
3339	FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
3340
3341	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
3342	typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
3343	FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
3344	FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
3345	FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80, iemAImpl_f2xm1_r80_amd, iemAImpl_f2xm1_r80_intel;
3346	FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
3347	FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
3348	FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80, iemAImpl_fsin_r80_amd, iemAImpl_fsin_r80_intel;
3349	FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80, iemAImpl_fcos_r80_amd, iemAImpl_fcos_r80_intel;
3350
3351	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
3352	typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
3353	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
3354	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
3355
3356	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
3357	typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
3358	FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
3359	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
3360	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
3361	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
3362	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
3363	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
3364	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
3365
3366	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
3367	PCRTFLOAT80U pr80Val));
3368	typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
3369	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80, iemAImpl_fptan_r80_r80_amd, iemAImpl_fptan_r80_r80_intel;
3370	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
3371	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80, iemAImpl_fsincos_r80_r80_amd, iemAImpl_fsincos_r80_r80_intel;
3372
3373	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
3374	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3375	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
3376
3377	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_d80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTPBCD80U pd80Val));
3378	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_d80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3379	PRTPBCD80U pd80Dst, PCRTFLOAT80U pr80Src));
3380
3381	/** @} */
3382
3383	/** @name FPU operations taking a 16-bit signed integer argument
3384	* @{ */
3385	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3386	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
3387	typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
3388	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI16,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3389	int16_t *pi16Dst, PCRTFLOAT80U pr80Src));
3390	typedef FNIEMAIMPLFPUSTR80TOI16 *PFNIEMAIMPLFPUSTR80TOI16;
3391
3392	FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
3393	FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
3394	FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
3395	FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
3396	FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
3397	FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
3398
3399	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3400	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
3401	typedef FNIEMAIMPLFPUI16FSW *PFNIEMAIMPLFPUI16FSW;
3402	FNIEMAIMPLFPUI16FSW iemAImpl_ficom_r80_by_i16;
3403
3404	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
3405	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fist_r80_to_i16;
3406	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fistt_r80_to_i16, iemAImpl_fistt_r80_to_i16_amd, iemAImpl_fistt_r80_to_i16_intel;
3407	/** @} */
3408
3409	/** @name FPU operations taking a 32-bit signed integer argument
3410	* @{ */
3411	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3412	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
3413	typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
3414	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI32,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3415	int32_t *pi32Dst, PCRTFLOAT80U pr80Src));
3416	typedef FNIEMAIMPLFPUSTR80TOI32 *PFNIEMAIMPLFPUSTR80TOI32;
3417
3418	FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
3419	FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
3420	FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
3421	FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
3422	FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
3423	FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
3424
3425	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3426	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
3427	typedef FNIEMAIMPLFPUI32FSW *PFNIEMAIMPLFPUI32FSW;
3428	FNIEMAIMPLFPUI32FSW iemAImpl_ficom_r80_by_i32;
3429
3430	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
3431	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fist_r80_to_i32;
3432	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fistt_r80_to_i32;
3433	/** @} */
3434
3435	/** @name FPU operations taking a 64-bit signed integer argument
3436	* @{ */
3437	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI64,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3438	int64_t *pi64Dst, PCRTFLOAT80U pr80Src));
3439	typedef FNIEMAIMPLFPUSTR80TOI64 *PFNIEMAIMPLFPUSTR80TOI64;
3440
3441	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
3442	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fist_r80_to_i64;
3443	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fistt_r80_to_i64;
3444	/** @} */
3445
3446
3447	/** Temporary type representing a 256-bit vector register. */
3448	typedef struct { uint64_t au64[4]; } IEMVMM256;
3449	/** Temporary type pointing to a 256-bit vector register. */
3450	typedef IEMVMM256 *PIEMVMM256;
3451	/** Temporary type pointing to a const 256-bit vector register. */
3452	typedef IEMVMM256 *PCIEMVMM256;
3453
3454
3455	/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
3456	* @{ */
3457	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t puDst, uint64_t const puSrc));
3458	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
3459	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF2U128,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
3460	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
3461	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF2U256,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86YMMREG puSrc));
3462	typedef FNIEMAIMPLMEDIAF2U256 *PFNIEMAIMPLMEDIAF2U256;
3463	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF3U128,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
3464	typedef FNIEMAIMPLMEDIAF3U128 *PFNIEMAIMPLMEDIAF3U128;
3465	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF3U256,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86YMMREG puSrc1, PCX86YMMREG puSrc2));
3466	typedef FNIEMAIMPLMEDIAF3U256 *PFNIEMAIMPLMEDIAF3U256;
3467	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U64,(uint64_t puDst, uint64_t const puSrc));
3468	typedef FNIEMAIMPLMEDIAOPTF2U64 *PFNIEMAIMPLMEDIAOPTF2U64;
3469	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128,(PRTUINT128U puDst, PCRTUINT128U puSrc));
3470	typedef FNIEMAIMPLMEDIAOPTF2U128 *PFNIEMAIMPLMEDIAOPTF2U128;
3471	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
3472	typedef FNIEMAIMPLMEDIAOPTF3U128 *PFNIEMAIMPLMEDIAOPTF3U128;
3473	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
3474	typedef FNIEMAIMPLMEDIAOPTF3U256 *PFNIEMAIMPLMEDIAOPTF3U256;
3475	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256,(PRTUINT256U puDst, PCRTUINT256U puSrc));
3476	typedef FNIEMAIMPLMEDIAOPTF2U256 *PFNIEMAIMPLMEDIAOPTF2U256;
3477	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pshufb_u64, iemAImpl_pshufb_u64_fallback;
3478	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pand_u64, iemAImpl_pandn_u64, iemAImpl_por_u64, iemAImpl_pxor_u64;
3479	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
3480	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pcmpgtb_u64, iemAImpl_pcmpgtw_u64, iemAImpl_pcmpgtd_u64;
3481	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddb_u64, iemAImpl_paddsb_u64, iemAImpl_paddusb_u64;
3482	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddw_u64, iemAImpl_paddsw_u64, iemAImpl_paddusw_u64;
3483	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddd_u64;
3484	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddq_u64;
3485	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubb_u64, iemAImpl_psubsb_u64, iemAImpl_psubusb_u64;
3486	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubw_u64, iemAImpl_psubsw_u64, iemAImpl_psubusw_u64;
3487	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubd_u64;
3488	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubq_u64;
3489	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmaddwd_u64, iemAImpl_pmaddwd_u64_fallback;
3490	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmullw_u64, iemAImpl_pmulhw_u64;
3491	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pminub_u64, iemAImpl_pmaxub_u64;
3492	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pminsw_u64, iemAImpl_pmaxsw_u64;
3493	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pabsb_u64, iemAImpl_pabsb_u64_fallback;
3494	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pabsw_u64, iemAImpl_pabsw_u64_fallback;
3495	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pabsd_u64, iemAImpl_pabsd_u64_fallback;
3496	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psignb_u64, iemAImpl_psignb_u64_fallback;
3497	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psignw_u64, iemAImpl_psignw_u64_fallback;
3498	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psignd_u64, iemAImpl_psignd_u64_fallback;
3499	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phaddw_u64, iemAImpl_phaddw_u64_fallback;
3500	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phaddd_u64, iemAImpl_phaddd_u64_fallback;
3501	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phsubw_u64, iemAImpl_phsubw_u64_fallback;
3502	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phsubd_u64, iemAImpl_phsubd_u64_fallback;
3503	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phaddsw_u64, iemAImpl_phaddsw_u64_fallback;
3504	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phsubsw_u64, iemAImpl_phsubsw_u64_fallback;
3505	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmaddubsw_u64, iemAImpl_pmaddubsw_u64_fallback;
3506	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhrsw_u64, iemAImpl_pmulhrsw_u64_fallback;
3507	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmuludq_u64;
3508	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllw_u64, iemAImpl_psrlw_u64, iemAImpl_psraw_u64;
3509	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pslld_u64, iemAImpl_psrld_u64, iemAImpl_psrad_u64;
3510	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllq_u64, iemAImpl_psrlq_u64;
3511	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packsswb_u64, iemAImpl_packuswb_u64;
3512	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packssdw_u64;
3513	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhuw_u64;
3514	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pavgb_u64, iemAImpl_pavgw_u64;
3515	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psadbw_u64;
3516
3517	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pshufb_u128, iemAImpl_pshufb_u128_fallback;
3518	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pand_u128, iemAImpl_pandn_u128, iemAImpl_por_u128, iemAImpl_pxor_u128;
3519	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
3520	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpeqq_u128, iemAImpl_pcmpeqq_u128_fallback;
3521	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpgtb_u128, iemAImpl_pcmpgtw_u128, iemAImpl_pcmpgtd_u128;
3522	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpgtq_u128, iemAImpl_pcmpgtq_u128_fallback;
3523	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddb_u128, iemAImpl_paddsb_u128, iemAImpl_paddusb_u128;
3524	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddw_u128, iemAImpl_paddsw_u128, iemAImpl_paddusw_u128;
3525	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddd_u128;
3526	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddq_u128;
3527	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubb_u128, iemAImpl_psubsb_u128, iemAImpl_psubusb_u128;
3528	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubw_u128, iemAImpl_psubsw_u128, iemAImpl_psubusw_u128;
3529	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubd_u128;
3530	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubq_u128;
3531	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmullw_u128, iemAImpl_pmullw_u128_fallback;
3532	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhw_u128;
3533	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulld_u128, iemAImpl_pmulld_u128_fallback;
3534	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaddwd_u128, iemAImpl_pmaddwd_u128_fallback;
3535	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminub_u128;
3536	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminud_u128, iemAImpl_pminud_u128_fallback;
3537	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminuw_u128, iemAImpl_pminuw_u128_fallback;
3538	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminsb_u128, iemAImpl_pminsb_u128_fallback;
3539	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminsd_u128, iemAImpl_pminsd_u128_fallback;
3540	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminsw_u128, iemAImpl_pminsw_u128_fallback;
3541	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxub_u128;
3542	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxud_u128, iemAImpl_pmaxud_u128_fallback;
3543	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxuw_u128, iemAImpl_pmaxuw_u128_fallback;
3544	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxsb_u128, iemAImpl_pmaxsb_u128_fallback;
3545	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxsw_u128;
3546	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxsd_u128, iemAImpl_pmaxsd_u128_fallback;
3547	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pabsb_u128, iemAImpl_pabsb_u128_fallback;
3548	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pabsw_u128, iemAImpl_pabsw_u128_fallback;
3549	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pabsd_u128, iemAImpl_pabsd_u128_fallback;
3550	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psignb_u128, iemAImpl_psignb_u128_fallback;
3551	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psignw_u128, iemAImpl_psignw_u128_fallback;
3552	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psignd_u128, iemAImpl_psignd_u128_fallback;
3553	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phaddw_u128, iemAImpl_phaddw_u128_fallback;
3554	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phaddd_u128, iemAImpl_phaddd_u128_fallback;
3555	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phsubw_u128, iemAImpl_phsubw_u128_fallback;
3556	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phsubd_u128, iemAImpl_phsubd_u128_fallback;
3557	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phaddsw_u128, iemAImpl_phaddsw_u128_fallback;
3558	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phsubsw_u128, iemAImpl_phsubsw_u128_fallback;
3559	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaddubsw_u128, iemAImpl_pmaddubsw_u128_fallback;
3560	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhrsw_u128, iemAImpl_pmulhrsw_u128_fallback;
3561	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuludq_u128;
3562	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaddwd_u128, iemAImpl_pmaddwd_u128_fallback;
3563	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packsswb_u128, iemAImpl_packuswb_u128;
3564	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packssdw_u128, iemAImpl_packusdw_u128;
3565	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllw_u128, iemAImpl_psrlw_u128, iemAImpl_psraw_u128;
3566	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pslld_u128, iemAImpl_psrld_u128, iemAImpl_psrad_u128;
3567	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllq_u128, iemAImpl_psrlq_u128;
3568	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhuw_u128;
3569	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pavgb_u128, iemAImpl_pavgw_u128;
3570	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psadbw_u128;
3571	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuldq_u128, iemAImpl_pmuldq_u128_fallback;
3572	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpcklps_u128, iemAImpl_unpcklpd_u128;
3573	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpckhps_u128, iemAImpl_unpckhpd_u128;
3574	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phminposuw_u128, iemAImpl_phminposuw_u128_fallback;
3575
3576	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpshufb_u128, iemAImpl_vpshufb_u128_fallback;
3577	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpand_u128, iemAImpl_vpand_u128_fallback;
3578	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpandn_u128, iemAImpl_vpandn_u128_fallback;
3579	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpor_u128, iemAImpl_vpor_u128_fallback;
3580	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpxor_u128, iemAImpl_vpxor_u128_fallback;
3581	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqb_u128, iemAImpl_vpcmpeqb_u128_fallback;
3582	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqw_u128, iemAImpl_vpcmpeqw_u128_fallback;
3583	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqd_u128, iemAImpl_vpcmpeqd_u128_fallback;
3584	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqq_u128, iemAImpl_vpcmpeqq_u128_fallback;
3585	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtb_u128, iemAImpl_vpcmpgtb_u128_fallback;
3586	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtw_u128, iemAImpl_vpcmpgtw_u128_fallback;
3587	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtd_u128, iemAImpl_vpcmpgtd_u128_fallback;
3588	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtq_u128, iemAImpl_vpcmpgtq_u128_fallback;
3589	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddb_u128, iemAImpl_vpaddb_u128_fallback;
3590	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddw_u128, iemAImpl_vpaddw_u128_fallback;
3591	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddd_u128, iemAImpl_vpaddd_u128_fallback;
3592	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddq_u128, iemAImpl_vpaddq_u128_fallback;
3593	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubb_u128, iemAImpl_vpsubb_u128_fallback;
3594	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubw_u128, iemAImpl_vpsubw_u128_fallback;
3595	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubd_u128, iemAImpl_vpsubd_u128_fallback;
3596	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubq_u128, iemAImpl_vpsubq_u128_fallback;
3597	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminub_u128, iemAImpl_vpminub_u128_fallback;
3598	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminuw_u128, iemAImpl_vpminuw_u128_fallback;
3599	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminud_u128, iemAImpl_vpminud_u128_fallback;
3600	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminsb_u128, iemAImpl_vpminsb_u128_fallback;
3601	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminsw_u128, iemAImpl_vpminsw_u128_fallback;
3602	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminsd_u128, iemAImpl_vpminsd_u128_fallback;
3603	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxub_u128, iemAImpl_vpmaxub_u128_fallback;
3604	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxuw_u128, iemAImpl_vpmaxuw_u128_fallback;
3605	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxud_u128, iemAImpl_vpmaxud_u128_fallback;
3606	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxsb_u128, iemAImpl_vpmaxsb_u128_fallback;
3607	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxsw_u128, iemAImpl_vpmaxsw_u128_fallback;
3608	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxsd_u128, iemAImpl_vpmaxsd_u128_fallback;
3609	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpacksswb_u128, iemAImpl_vpacksswb_u128_fallback;
3610	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackssdw_u128, iemAImpl_vpackssdw_u128_fallback;
3611	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackuswb_u128, iemAImpl_vpackuswb_u128_fallback;
3612	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackusdw_u128, iemAImpl_vpackusdw_u128_fallback;
3613	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmullw_u128, iemAImpl_vpmullw_u128_fallback;
3614	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulld_u128, iemAImpl_vpmulld_u128_fallback;
3615	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhw_u128, iemAImpl_vpmulhw_u128_fallback;
3616	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhuw_u128, iemAImpl_vpmulhuw_u128_fallback;
3617	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgb_u128, iemAImpl_vpavgb_u128_fallback;
3618	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgw_u128, iemAImpl_vpavgw_u128_fallback;
3619	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignb_u128, iemAImpl_vpsignb_u128_fallback;
3620	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignw_u128, iemAImpl_vpsignw_u128_fallback;
3621	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignd_u128, iemAImpl_vpsignd_u128_fallback;
3622	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddw_u128, iemAImpl_vphaddw_u128_fallback;
3623	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddd_u128, iemAImpl_vphaddd_u128_fallback;
3624	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubw_u128, iemAImpl_vphsubw_u128_fallback;
3625	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubd_u128, iemAImpl_vphsubd_u128_fallback;
3626	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddsw_u128, iemAImpl_vphaddsw_u128_fallback;
3627	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubsw_u128, iemAImpl_vphsubsw_u128_fallback;
3628	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddubsw_u128, iemAImpl_vpmaddubsw_u128_fallback;
3629	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhrsw_u128, iemAImpl_vpmulhrsw_u128_fallback;
3630	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsadbw_u128, iemAImpl_vpsadbw_u128_fallback;
3631	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuldq_u128, iemAImpl_vpmuldq_u128_fallback;
3632	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuludq_u128, iemAImpl_vpmuludq_u128_fallback;
3633	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsb_u128, iemAImpl_vpsubsb_u128_fallback;
3634	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsw_u128, iemAImpl_vpsubsw_u128_fallback;
3635	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusb_u128, iemAImpl_vpsubusb_u128_fallback;
3636	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusw_u128, iemAImpl_vpsubusw_u128_fallback;
3637	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusb_u128, iemAImpl_vpaddusb_u128_fallback;
3638	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusw_u128, iemAImpl_vpaddusw_u128_fallback;
3639	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsb_u128, iemAImpl_vpaddsb_u128_fallback;
3640	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsw_u128, iemAImpl_vpaddsw_u128_fallback;
3641	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllw_u128, iemAImpl_vpsllw_u128_fallback;
3642	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpslld_u128, iemAImpl_vpslld_u128_fallback;
3643	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllq_u128, iemAImpl_vpsllq_u128_fallback;
3644	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsraw_u128, iemAImpl_vpsraw_u128_fallback;
3645	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrad_u128, iemAImpl_vpsrad_u128_fallback;
3646	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlw_u128, iemAImpl_vpsrlw_u128_fallback;
3647	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrld_u128, iemAImpl_vpsrld_u128_fallback;
3648	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlq_u128, iemAImpl_vpsrlq_u128_fallback;
3649	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddwd_u128, iemAImpl_vpmaddwd_u128_fallback;
3650
3651	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsb_u128, iemAImpl_vpabsb_u128_fallback;
3652	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsw_u128, iemAImpl_vpabsd_u128_fallback;
3653	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsd_u128, iemAImpl_vpabsw_u128_fallback;
3654	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vphminposuw_u128, iemAImpl_vphminposuw_u128_fallback;
3655
3656	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpshufb_u256, iemAImpl_vpshufb_u256_fallback;
3657	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpand_u256, iemAImpl_vpand_u256_fallback;
3658	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpandn_u256, iemAImpl_vpandn_u256_fallback;
3659	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpor_u256, iemAImpl_vpor_u256_fallback;
3660	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpxor_u256, iemAImpl_vpxor_u256_fallback;
3661	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqb_u256, iemAImpl_vpcmpeqb_u256_fallback;
3662	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqw_u256, iemAImpl_vpcmpeqw_u256_fallback;
3663	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqd_u256, iemAImpl_vpcmpeqd_u256_fallback;
3664	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqq_u256, iemAImpl_vpcmpeqq_u256_fallback;
3665	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtb_u256, iemAImpl_vpcmpgtb_u256_fallback;
3666	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtw_u256, iemAImpl_vpcmpgtw_u256_fallback;
3667	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtd_u256, iemAImpl_vpcmpgtd_u256_fallback;
3668	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtq_u256, iemAImpl_vpcmpgtq_u256_fallback;
3669	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddb_u256, iemAImpl_vpaddb_u256_fallback;
3670	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddw_u256, iemAImpl_vpaddw_u256_fallback;
3671	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddd_u256, iemAImpl_vpaddd_u256_fallback;
3672	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddq_u256, iemAImpl_vpaddq_u256_fallback;
3673	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubb_u256, iemAImpl_vpsubb_u256_fallback;
3674	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubw_u256, iemAImpl_vpsubw_u256_fallback;
3675	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubd_u256, iemAImpl_vpsubd_u256_fallback;
3676	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubq_u256, iemAImpl_vpsubq_u256_fallback;
3677	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminub_u256, iemAImpl_vpminub_u256_fallback;
3678	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminuw_u256, iemAImpl_vpminuw_u256_fallback;
3679	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminud_u256, iemAImpl_vpminud_u256_fallback;
3680	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminsb_u256, iemAImpl_vpminsb_u256_fallback;
3681	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminsw_u256, iemAImpl_vpminsw_u256_fallback;
3682	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminsd_u256, iemAImpl_vpminsd_u256_fallback;
3683	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxub_u256, iemAImpl_vpmaxub_u256_fallback;
3684	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxuw_u256, iemAImpl_vpmaxuw_u256_fallback;
3685	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxud_u256, iemAImpl_vpmaxud_u256_fallback;
3686	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxsb_u256, iemAImpl_vpmaxsb_u256_fallback;
3687	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxsw_u256, iemAImpl_vpmaxsw_u256_fallback;
3688	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxsd_u256, iemAImpl_vpmaxsd_u256_fallback;
3689	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpacksswb_u256, iemAImpl_vpacksswb_u256_fallback;
3690	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackssdw_u256, iemAImpl_vpackssdw_u256_fallback;
3691	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackuswb_u256, iemAImpl_vpackuswb_u256_fallback;
3692	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackusdw_u256, iemAImpl_vpackusdw_u256_fallback;
3693	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmullw_u256, iemAImpl_vpmullw_u256_fallback;
3694	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulld_u256, iemAImpl_vpmulld_u256_fallback;
3695	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhw_u256, iemAImpl_vpmulhw_u256_fallback;
3696	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhuw_u256, iemAImpl_vpmulhuw_u256_fallback;
3697	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgb_u256, iemAImpl_vpavgb_u256_fallback;
3698	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgw_u256, iemAImpl_vpavgw_u256_fallback;
3699	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignb_u256, iemAImpl_vpsignb_u256_fallback;
3700	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignw_u256, iemAImpl_vpsignw_u256_fallback;
3701	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignd_u256, iemAImpl_vpsignd_u256_fallback;
3702	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddw_u256, iemAImpl_vphaddw_u256_fallback;
3703	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddd_u256, iemAImpl_vphaddd_u256_fallback;
3704	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubw_u256, iemAImpl_vphsubw_u256_fallback;
3705	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubd_u256, iemAImpl_vphsubd_u256_fallback;
3706	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddsw_u256, iemAImpl_vphaddsw_u256_fallback;
3707	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubsw_u256, iemAImpl_vphsubsw_u256_fallback;
3708	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddubsw_u256, iemAImpl_vpmaddubsw_u256_fallback;
3709	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhrsw_u256, iemAImpl_vpmulhrsw_u256_fallback;
3710	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsadbw_u256, iemAImpl_vpsadbw_u256_fallback;
3711	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuldq_u256, iemAImpl_vpmuldq_u256_fallback;
3712	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuludq_u256, iemAImpl_vpmuludq_u256_fallback;
3713	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsb_u256, iemAImpl_vpsubsb_u256_fallback;
3714	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsw_u256, iemAImpl_vpsubsw_u256_fallback;
3715	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusb_u256, iemAImpl_vpsubusb_u256_fallback;
3716	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusw_u256, iemAImpl_vpsubusw_u256_fallback;
3717	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusb_u256, iemAImpl_vpaddusb_u256_fallback;
3718	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusw_u256, iemAImpl_vpaddusw_u256_fallback;
3719	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsb_u256, iemAImpl_vpaddsb_u256_fallback;
3720	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsw_u256, iemAImpl_vpaddsw_u256_fallback;
3721	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllw_u256, iemAImpl_vpsllw_u256_fallback;
3722	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpslld_u256, iemAImpl_vpslld_u256_fallback;
3723	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllq_u256, iemAImpl_vpsllq_u256_fallback;
3724	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsraw_u256, iemAImpl_vpsraw_u256_fallback;
3725	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrad_u256, iemAImpl_vpsrad_u256_fallback;
3726	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlw_u256, iemAImpl_vpsrlw_u256_fallback;
3727	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrld_u256, iemAImpl_vpsrld_u256_fallback;
3728	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlq_u256, iemAImpl_vpsrlq_u256_fallback;
3729	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddwd_u256, iemAImpl_vpmaddwd_u256_fallback;
3730
3731	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsb_u256, iemAImpl_vpabsb_u256_fallback;
3732	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsw_u256, iemAImpl_vpabsw_u256_fallback;
3733	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsd_u256, iemAImpl_vpabsd_u256_fallback;
3734	/** @} */
3735
3736	/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
3737	* @{ */
3738	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
3739	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
3740	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpcklbw_u128, iemAImpl_vpunpcklbw_u128_fallback,
3741	iemAImpl_vpunpcklwd_u128, iemAImpl_vpunpcklwd_u128_fallback,
3742	iemAImpl_vpunpckldq_u128, iemAImpl_vpunpckldq_u128_fallback,
3743	iemAImpl_vpunpcklqdq_u128, iemAImpl_vpunpcklqdq_u128_fallback,
3744	iemAImpl_vunpcklps_u128, iemAImpl_vunpcklps_u128_fallback,
3745	iemAImpl_vunpcklpd_u128, iemAImpl_vunpcklpd_u128_fallback,
3746	iemAImpl_vunpckhps_u128, iemAImpl_vunpckhps_u128_fallback,
3747	iemAImpl_vunpckhpd_u128, iemAImpl_vunpckhpd_u128_fallback;
3748
3749	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpcklbw_u256, iemAImpl_vpunpcklbw_u256_fallback,
3750	iemAImpl_vpunpcklwd_u256, iemAImpl_vpunpcklwd_u256_fallback,
3751	iemAImpl_vpunpckldq_u256, iemAImpl_vpunpckldq_u256_fallback,
3752	iemAImpl_vpunpcklqdq_u256, iemAImpl_vpunpcklqdq_u256_fallback,
3753	iemAImpl_vunpcklps_u256, iemAImpl_vunpcklps_u256_fallback,
3754	iemAImpl_vunpcklpd_u256, iemAImpl_vunpcklpd_u256_fallback,
3755	iemAImpl_vunpckhps_u256, iemAImpl_vunpckhps_u256_fallback,
3756	iemAImpl_vunpckhpd_u256, iemAImpl_vunpckhpd_u256_fallback;
3757	/** @} */
3758
3759	/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
3760	* @{ */
3761	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
3762	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
3763	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpckhbw_u128, iemAImpl_vpunpckhbw_u128_fallback,
3764	iemAImpl_vpunpckhwd_u128, iemAImpl_vpunpckhwd_u128_fallback,
3765	iemAImpl_vpunpckhdq_u128, iemAImpl_vpunpckhdq_u128_fallback,
3766	iemAImpl_vpunpckhqdq_u128, iemAImpl_vpunpckhqdq_u128_fallback;
3767	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpckhbw_u256, iemAImpl_vpunpckhbw_u256_fallback,
3768	iemAImpl_vpunpckhwd_u256, iemAImpl_vpunpckhwd_u256_fallback,
3769	iemAImpl_vpunpckhdq_u256, iemAImpl_vpunpckhdq_u256_fallback,
3770	iemAImpl_vpunpckhqdq_u256, iemAImpl_vpunpckhqdq_u256_fallback;
3771	/** @} */
3772
3773	/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
3774	* @{ */
3775	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3776	typedef FNIEMAIMPLMEDIAPSHUFU128 *PFNIEMAIMPLMEDIAPSHUFU128;
3777	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
3778	typedef FNIEMAIMPLMEDIAPSHUFU256 *PFNIEMAIMPLMEDIAPSHUFU256;
3779	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw_u64,(uint64_t puDst, uint64_t const puSrc, uint8_t bEvil));
3780	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_pshufhw_u128, iemAImpl_pshuflw_u128, iemAImpl_pshufd_u128;
3781	#ifndef IEM_WITHOUT_ASSEMBLY
3782	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256, iemAImpl_vpshuflw_u256, iemAImpl_vpshufd_u256;
3783	#endif
3784	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256_fallback, iemAImpl_vpshuflw_u256_fallback, iemAImpl_vpshufd_u256_fallback;
3785	/** @} */
3786
3787	/** @name Media (SSE/MMX/AVX) operation: Shift Immediate Stuff (evil)
3788	* @{ */
3789	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU64,(uint64_t *puDst, uint8_t bShift));
3790	typedef FNIEMAIMPLMEDIAPSHIFTU64 *PFNIEMAIMPLMEDIAPSHIFTU64;
3791	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU128,(PRTUINT128U puDst, uint8_t bShift));
3792	typedef FNIEMAIMPLMEDIAPSHIFTU128 *PFNIEMAIMPLMEDIAPSHIFTU128;
3793	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU256,(PRTUINT256U puDst, uint8_t bShift));
3794	typedef FNIEMAIMPLMEDIAPSHIFTU256 *PFNIEMAIMPLMEDIAPSHIFTU256;
3795	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psllw_imm_u64, iemAImpl_pslld_imm_u64, iemAImpl_psllq_imm_u64;
3796	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psrlw_imm_u64, iemAImpl_psrld_imm_u64, iemAImpl_psrlq_imm_u64;
3797	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psraw_imm_u64, iemAImpl_psrad_imm_u64;
3798	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psllw_imm_u128, iemAImpl_pslld_imm_u128, iemAImpl_psllq_imm_u128;
3799	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psrlw_imm_u128, iemAImpl_psrld_imm_u128, iemAImpl_psrlq_imm_u128;
3800	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psraw_imm_u128, iemAImpl_psrad_imm_u128;
3801	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_pslldq_imm_u128, iemAImpl_psrldq_imm_u128;
3802	/** @} */
3803
3804	/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
3805	* @{ */
3806	IEM_DECL_IMPL_DEF(void, iemAImpl_maskmovq_u64,(uint64_t puMem, uint64_t const puSrc, uint64_t const *puMsk));
3807	IEM_DECL_IMPL_DEF(void, iemAImpl_maskmovdqu_u128,(PRTUINT128U puMem, PCRTUINT128U puSrc, PCRTUINT128U puMsk));
3808	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(uint64_t pu64Dst, uint64_t const puSrc));
3809	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(uint64_t *pu64Dst, PCRTUINT128U puSrc));
3810	#ifndef IEM_WITHOUT_ASSEMBLY
3811	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
3812	#endif
3813	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256_fallback,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
3814	/** @} */
3815
3816	/** @name Media (SSE/MMX/AVX) operations: Variable Blend Packed Bytes/R32/R64.
3817	* @{ */
3818	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puMask));
3819	typedef FNIEMAIMPLBLENDU128 *PFNIEMAIMPLBLENDU128;
3820	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, PCRTUINT128U puMask));
3821	typedef FNIEMAIMPLAVXBLENDU128 *PFNIEMAIMPLAVXBLENDU128;
3822	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, PCRTUINT256U puMask));
3823	typedef FNIEMAIMPLAVXBLENDU256 *PFNIEMAIMPLAVXBLENDU256;
3824
3825	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128;
3826	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128_fallback;
3827	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128;
3828	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128_fallback;
3829	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256;
3830	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256_fallback;
3831
3832	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128;
3833	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128_fallback;
3834	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128;
3835	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128_fallback;
3836	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256;
3837	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256_fallback;
3838
3839	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128;
3840	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128_fallback;
3841	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128;
3842	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128_fallback;
3843	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256;
3844	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256_fallback;
3845	/** @} */
3846
3847
3848	/** @name Media (SSE/MMX/AVX) operation: Sort this later
3849	* @{ */
3850	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3851	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3852	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3853	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3854	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3855
3856	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3857	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3858	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3859	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3860	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3861
3862	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3863	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3864	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
3865	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3866	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3867
3868	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3869	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3870	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3871	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3872	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3873
3874	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3875	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3876	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3877	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3878	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3879
3880	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3881	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3882	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3883	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3884	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3885
3886	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3887	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
3888	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3889	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3890	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3891
3892	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3893	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
3894	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3895	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3896	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3897
3898	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3899	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
3900	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
3901	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3902	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3903
3904	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3905	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
3906	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3907	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3908	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3909
3910	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3911	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
3912	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
3913	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3914	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3915
3916	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3917	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
3918	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
3919	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3920	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
3921
3922	IEM_DECL_IMPL_DEF(void, iemAImpl_shufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3923	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3924	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3925	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3926	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3927
3928	IEM_DECL_IMPL_DEF(void, iemAImpl_shufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3929	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3930	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3931	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3932	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3933
3934	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
3935	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64_fallback,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
3936
3937	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3938	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3939	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3940	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3941	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3942
3943	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3944	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3945	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
3946	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3947	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
3948
3949
3950	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
3951	typedef FNIEMAIMPLMEDIAOPTF2U128IMM8 *PFNIEMAIMPLMEDIAOPTF2U128IMM8;
3952	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
3953	typedef FNIEMAIMPLMEDIAOPTF2U256IMM8 *PFNIEMAIMPLMEDIAOPTF2U256IMM8;
3954	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
3955	typedef FNIEMAIMPLMEDIAOPTF3U128IMM8 *PFNIEMAIMPLMEDIAOPTF3U128IMM8;
3956	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
3957	typedef FNIEMAIMPLMEDIAOPTF3U256IMM8 *PFNIEMAIMPLMEDIAOPTF3U256IMM8;
3958
3959	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_palignr_u128, iemAImpl_palignr_u128_fallback;
3960	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pblendw_u128, iemAImpl_pblendw_u128_fallback;
3961	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendps_u128, iemAImpl_blendps_u128_fallback;
3962	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendpd_u128, iemAImpl_blendpd_u128_fallback;
3963
3964	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpalignr_u128, iemAImpl_vpalignr_u128_fallback;
3965	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendw_u128, iemAImpl_vpblendw_u128_fallback;
3966	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendd_u128, iemAImpl_vpblendd_u128_fallback;
3967	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendps_u128, iemAImpl_vblendps_u128_fallback;
3968	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendpd_u128, iemAImpl_vblendpd_u128_fallback;
3969
3970	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpalignr_u256, iemAImpl_vpalignr_u256_fallback;
3971	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendw_u256, iemAImpl_vpblendw_u256_fallback;
3972	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendd_u256, iemAImpl_vpblendd_u256_fallback;
3973	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendps_u256, iemAImpl_vblendps_u256_fallback;
3974	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendpd_u256, iemAImpl_vblendpd_u256_fallback;
3975	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2i128_u256, iemAImpl_vperm2i128_u256_fallback;
3976	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2f128_u256, iemAImpl_vperm2f128_u256_fallback;
3977
3978	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesimc_u128, iemAImpl_aesimc_u128_fallback;
3979	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenc_u128, iemAImpl_aesenc_u128_fallback;
3980	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenclast_u128, iemAImpl_aesenclast_u128_fallback;
3981	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdec_u128, iemAImpl_aesdec_u128_fallback;
3982	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdeclast_u128, iemAImpl_aesdeclast_u128_fallback;
3983
3984	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesimc_u128, iemAImpl_vaesimc_u128_fallback;
3985	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenc_u128, iemAImpl_vaesenc_u128_fallback;
3986	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenclast_u128, iemAImpl_vaesenclast_u128_fallback;
3987	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdec_u128, iemAImpl_vaesdec_u128_fallback;
3988	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdeclast_u128, iemAImpl_vaesdeclast_u128_fallback;
3989
3990	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_aeskeygenassist_u128, iemAImpl_aeskeygenassist_u128_fallback;
3991
3992	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vaeskeygenassist_u128, iemAImpl_vaeskeygenassist_u128_fallback;
3993
3994	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1nexte_u128, iemAImpl_sha1nexte_u128_fallback;
3995	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg1_u128, iemAImpl_sha1msg1_u128_fallback;
3996	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg2_u128, iemAImpl_sha1msg2_u128_fallback;
3997	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg1_u128, iemAImpl_sha256msg1_u128_fallback;
3998	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg2_u128, iemAImpl_sha256msg2_u128_fallback;
3999	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_sha1rnds4_u128, iemAImpl_sha1rnds4_u128_fallback;
4000	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
4001	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
4002
4003	typedef struct IEMPCMPISTRXSRC
4004	{
4005	RTUINT128U uSrc1;
4006	RTUINT128U uSrc2;
4007	} IEMPCMPISTRXSRC;
4008	typedef IEMPCMPISTRXSRC *PIEMPCMPISTRXSRC;
4009	typedef const IEMPCMPISTRXSRC *PCIEMPCMPISTRXSRC;
4010
4011	typedef struct IEMPCMPESTRXSRC
4012	{
4013	RTUINT128U uSrc1;
4014	RTUINT128U uSrc2;
4015	uint64_t u64Rax;
4016	uint64_t u64Rdx;
4017	} IEMPCMPESTRXSRC;
4018	typedef IEMPCMPESTRXSRC *PIEMPCMPESTRXSRC;
4019	typedef const IEMPCMPESTRXSRC *PCIEMPCMPESTRXSRC;
4020
4021	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLPCMPISTRIU128IMM8,(uint32_t *pEFlags, PCRTUINT128U pSrc1, PCRTUINT128U pSrc2, uint8_t bEvil));
4022	typedef FNIEMAIMPLPCMPISTRIU128IMM8 *PFNIEMAIMPLPCMPISTRIU128IMM8;
4023	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRIU128IMM8,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
4024	typedef FNIEMAIMPLPCMPESTRIU128IMM8 *PFNIEMAIMPLPCMPESTRIU128IMM8;
4025
4026	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPISTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
4027	typedef FNIEMAIMPLPCMPISTRMU128IMM8 *PFNIEMAIMPLPCMPISTRMU128IMM8;
4028	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
4029	typedef FNIEMAIMPLPCMPESTRMU128IMM8 *PFNIEMAIMPLPCMPESTRMU128IMM8;
4030
4031	FNIEMAIMPLPCMPISTRIU128IMM8 iemAImpl_pcmpistri_u128, iemAImpl_pcmpistri_u128_fallback;
4032	FNIEMAIMPLPCMPESTRIU128IMM8 iemAImpl_pcmpestri_u128, iemAImpl_pcmpestri_u128_fallback;
4033	FNIEMAIMPLPCMPISTRMU128IMM8 iemAImpl_pcmpistrm_u128, iemAImpl_pcmpistrm_u128_fallback;
4034	FNIEMAIMPLPCMPESTRMU128IMM8 iemAImpl_pcmpestrm_u128, iemAImpl_pcmpestrm_u128_fallback;
4035	FNIEMAIMPLPCMPISTRIU128IMM8 iemAImpl_vpcmpistri_u128, iemAImpl_vpcmpistri_u128_fallback;
4036	FNIEMAIMPLPCMPESTRIU128IMM8 iemAImpl_vpcmpestri_u128, iemAImpl_vpcmpestri_u128_fallback;
4037	FNIEMAIMPLPCMPISTRMU128IMM8 iemAImpl_vpcmpistrm_u128, iemAImpl_vpcmpistrm_u128_fallback;
4038	FNIEMAIMPLPCMPESTRMU128IMM8 iemAImpl_vpcmpestrm_u128, iemAImpl_vpcmpestrm_u128_fallback;
4039
4040
4041	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pclmulqdq_u128, iemAImpl_pclmulqdq_u128_fallback;
4042	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpclmulqdq_u128, iemAImpl_vpclmulqdq_u128_fallback;
4043
4044	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_mpsadbw_u128, iemAImpl_mpsadbw_u128_fallback;
4045	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vmpsadbw_u128, iemAImpl_vmpsadbw_u128_fallback;
4046	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vmpsadbw_u256, iemAImpl_vmpsadbw_u256_fallback;
4047
4048	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsllw_imm_u128, iemAImpl_vpsllw_imm_u128_fallback;
4049	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsllw_imm_u256, iemAImpl_vpsllw_imm_u256_fallback;
4050	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpslld_imm_u128, iemAImpl_vpslld_imm_u128_fallback;
4051	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpslld_imm_u256, iemAImpl_vpslld_imm_u256_fallback;
4052	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsllq_imm_u128, iemAImpl_vpsllq_imm_u128_fallback;
4053	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsllq_imm_u256, iemAImpl_vpsllq_imm_u256_fallback;
4054	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
4055	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
4056	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
4057	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
4058
4059	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsraw_imm_u128, iemAImpl_vpsraw_imm_u128_fallback;
4060	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsraw_imm_u256, iemAImpl_vpsraw_imm_u256_fallback;
4061	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrad_imm_u128, iemAImpl_vpsrad_imm_u128_fallback;
4062	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrad_imm_u256, iemAImpl_vpsrad_imm_u256_fallback;
4063
4064	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrlw_imm_u128, iemAImpl_vpsrlw_imm_u128_fallback;
4065	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrlw_imm_u256, iemAImpl_vpsrlw_imm_u256_fallback;
4066	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrld_imm_u128, iemAImpl_vpsrld_imm_u128_fallback;
4067	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrld_imm_u256, iemAImpl_vpsrld_imm_u256_fallback;
4068	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrlq_imm_u128, iemAImpl_vpsrlq_imm_u128_fallback;
4069	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrlq_imm_u256, iemAImpl_vpsrlq_imm_u256_fallback;
4070	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
4071	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
4072	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
4073	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
4074
4075	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpermilps_u128, iemAImpl_vpermilps_u128_fallback;
4076	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_vpermilps_imm_u128, iemAImpl_vpermilps_imm_u128_fallback;
4077	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpermilps_u256, iemAImpl_vpermilps_u256_fallback;
4078	FNIEMAIMPLMEDIAOPTF2U256IMM8 iemAImpl_vpermilps_imm_u256, iemAImpl_vpermilps_imm_u256_fallback;
4079
4080	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpermilpd_u128, iemAImpl_vpermilpd_u128_fallback;
4081	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_vpermilpd_imm_u128, iemAImpl_vpermilpd_imm_u128_fallback;
4082	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpermilpd_u256, iemAImpl_vpermilpd_u256_fallback;
4083	FNIEMAIMPLMEDIAOPTF2U256IMM8 iemAImpl_vpermilpd_imm_u256, iemAImpl_vpermilpd_imm_u256_fallback;
4084
4085	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllvd_u128, iemAImpl_vpsllvd_u128_fallback;
4086	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllvd_u256, iemAImpl_vpsllvd_u256_fallback;
4087	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllvq_u128, iemAImpl_vpsllvq_u128_fallback;
4088	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllvq_u256, iemAImpl_vpsllvq_u256_fallback;
4089	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsravd_u128, iemAImpl_vpsravd_u128_fallback;
4090	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsravd_u256, iemAImpl_vpsravd_u256_fallback;
4091	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlvd_u128, iemAImpl_vpsrlvd_u128_fallback;
4092	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlvd_u256, iemAImpl_vpsrlvd_u256_fallback;
4093	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlvq_u128, iemAImpl_vpsrlvq_u128_fallback;
4094	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlvq_u256, iemAImpl_vpsrlvq_u256_fallback;
4095	/** @} */
4096
4097	/** @name Media Odds and Ends
4098	* @{ */
4099	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U8,(uint32_t *puDst, uint8_t uSrc));
4100	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U16,(uint32_t *puDst, uint16_t uSrc));
4101	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U32,(uint32_t *puDst, uint32_t uSrc));
4102	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U64,(uint32_t *puDst, uint64_t uSrc));
4103	FNIEMAIMPLCR32U8 iemAImpl_crc32_u8, iemAImpl_crc32_u8_fallback;
4104	FNIEMAIMPLCR32U16 iemAImpl_crc32_u16, iemAImpl_crc32_u16_fallback;
4105	FNIEMAIMPLCR32U32 iemAImpl_crc32_u32, iemAImpl_crc32_u32_fallback;
4106	FNIEMAIMPLCR32U64 iemAImpl_crc32_u64, iemAImpl_crc32_u64_fallback;
4107
4108	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL128,(PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint32_t *pEFlags));
4109	typedef FNIEMAIMPLF2EFL128 *PFNIEMAIMPLF2EFL128;
4110	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL256,(PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint32_t *pEFlags));
4111	typedef FNIEMAIMPLF2EFL256 *PFNIEMAIMPLF2EFL256;
4112	FNIEMAIMPLF2EFL128 iemAImpl_ptest_u128;
4113	FNIEMAIMPLF2EFL256 iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback;
4114	FNIEMAIMPLF2EFL128 iemAImpl_vtestps_u128, iemAImpl_vtestps_u128_fallback;
4115	FNIEMAIMPLF2EFL256 iemAImpl_vtestps_u256, iemAImpl_vtestps_u256_fallback;
4116	FNIEMAIMPLF2EFL128 iemAImpl_vtestpd_u128, iemAImpl_vtestpd_u128_fallback;
4117	FNIEMAIMPLF2EFL256 iemAImpl_vtestpd_u256, iemAImpl_vtestpd_u256_fallback;
4118
4119	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I32U64,(uint32_t uMxCsrIn, int32_t pi32Dst, const uint64_t pu64Src)); /* pu64Src is a double precision floating point. */
4120	typedef FNIEMAIMPLSSEF2I32U64 *PFNIEMAIMPLSSEF2I32U64;
4121	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I64U64,(uint32_t uMxCsrIn, int64_t pi64Dst, const uint64_t pu64Src)); /* pu64Src is a double precision floating point. */
4122	typedef FNIEMAIMPLSSEF2I64U64 *PFNIEMAIMPLSSEF2I64U64;
4123	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I32U32,(uint32_t uMxCsrIn, int32_t pi32Dst, const uint32_t pu32Src)); /* pu32Src is a single precision floating point. */
4124	typedef FNIEMAIMPLSSEF2I32U32 *PFNIEMAIMPLSSEF2I32U32;
4125	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I64U32,(uint32_t uMxCsrIn, int64_t pi64Dst, const uint32_t pu32Src)); /* pu32Src is a single precision floating point. */
4126	typedef FNIEMAIMPLSSEF2I64U32 *PFNIEMAIMPLSSEF2I64U32;
4127
4128	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvttsd2si_i32_r64;
4129	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvtsd2si_i32_r64;
4130
4131	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvttsd2si_i64_r64;
4132	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvtsd2si_i64_r64;
4133
4134	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvttss2si_i32_r32;
4135	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvtss2si_i32_r32;
4136
4137	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvttss2si_i64_r32;
4138	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvtss2si_i64_r32;
4139
4140	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R32I32,(uint32_t uMxCsrIn, PRTFLOAT32U pr32Dst, const int32_t *pi32Src));
4141	typedef FNIEMAIMPLSSEF2R32I32 *PFNIEMAIMPLSSEF2R32I32;
4142	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R32I64,(uint32_t uMxCsrIn, PRTFLOAT32U pr32Dst, const int64_t *pi64Src));
4143	typedef FNIEMAIMPLSSEF2R32I64 *PFNIEMAIMPLSSEF2R32I64;
4144
4145	FNIEMAIMPLSSEF2R32I32 iemAImpl_cvtsi2ss_r32_i32;
4146	FNIEMAIMPLSSEF2R32I64 iemAImpl_cvtsi2ss_r32_i64;
4147
4148	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R64I32,(uint32_t uMxCsrIn, PRTFLOAT64U pr64Dst, const int32_t *pi32Src));
4149	typedef FNIEMAIMPLSSEF2R64I32 *PFNIEMAIMPLSSEF2R64I32;
4150	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R64I64,(uint32_t uMxCsrIn, PRTFLOAT64U pr64Dst, const int64_t *pi64Src));
4151	typedef FNIEMAIMPLSSEF2R64I64 *PFNIEMAIMPLSSEF2R64I64;
4152
4153	FNIEMAIMPLSSEF2R64I32 iemAImpl_cvtsi2sd_r64_i32;
4154	FNIEMAIMPLSSEF2R64I64 iemAImpl_cvtsi2sd_r64_i64;
4155
4156
4157	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLF2EFLMXCSRR32R32,(uint32_t uMxCsrIn, uint32_t *pfEFlags, RTFLOAT32U uSrc1, RTFLOAT32U uSrc2));
4158	typedef FNIEMAIMPLF2EFLMXCSRR32R32 *PFNIEMAIMPLF2EFLMXCSRR32R32;
4159
4160	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLF2EFLMXCSRR64R64,(uint32_t uMxCsrIn, uint32_t *pfEFlags, RTFLOAT64U uSrc1, RTFLOAT64U uSrc2));
4161	typedef FNIEMAIMPLF2EFLMXCSRR64R64 *PFNIEMAIMPLF2EFLMXCSRR64R64;
4162
4163	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_ucomiss_u128;
4164	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback;
4165
4166	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_ucomisd_u128;
4167	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback;
4168
4169	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_comiss_u128;
4170	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback;
4171
4172	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_comisd_u128;
4173	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback;
4174
4175
4176	typedef struct IEMMEDIAF2XMMSRC
4177	{
4178	X86XMMREG uSrc1;
4179	X86XMMREG uSrc2;
4180	} IEMMEDIAF2XMMSRC;
4181	typedef IEMMEDIAF2XMMSRC *PIEMMEDIAF2XMMSRC;
4182	typedef const IEMMEDIAF2XMMSRC *PCIEMMEDIAF2XMMSRC;
4183
4184
4185	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF3XMMIMM8,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCIEMMEDIAF2XMMSRC puSrc, uint8_t bEvil));
4186	typedef FNIEMAIMPLMEDIAF3XMMIMM8 *PFNIEMAIMPLMEDIAF3XMMIMM8;
4187
4188
4189	typedef struct IEMMEDIAF2YMMSRC
4190	{
4191	X86YMMREG uSrc1;
4192	X86YMMREG uSrc2;
4193	} IEMMEDIAF2YMMSRC;
4194	typedef IEMMEDIAF2YMMSRC *PIEMMEDIAF2YMMSRC;
4195	typedef const IEMMEDIAF2YMMSRC *PCIEMMEDIAF2YMMSRC;
4196
4197
4198	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF3YMMIMM8,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCIEMMEDIAF2YMMSRC puSrc, uint8_t bEvil));
4199	typedef FNIEMAIMPLMEDIAF3YMMIMM8 *PFNIEMAIMPLMEDIAF3YMMIMM8;
4200
4201
4202	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_cmpps_u128;
4203	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_cmppd_u128;
4204	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_cmpss_u128;
4205	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_cmpsd_u128;
4206
4207	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vcmpps_u128, iemAImpl_vcmpps_u128_fallback;
4208	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vcmppd_u128, iemAImpl_vcmppd_u128_fallback;
4209	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vcmpss_u128, iemAImpl_vcmpss_u128_fallback;
4210	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vcmpsd_u128, iemAImpl_vcmpsd_u128_fallback;
4211
4212	FNIEMAIMPLMEDIAF3YMMIMM8 iemAImpl_vcmpps_u256, iemAImpl_vcmpps_u256_fallback;
4213	FNIEMAIMPLMEDIAF3YMMIMM8 iemAImpl_vcmppd_u256, iemAImpl_vcmppd_u256_fallback;
4214
4215	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_roundss_u128;
4216	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_roundsd_u128;
4217
4218	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_dpps_u128, iemAImpl_dpps_u128_fallback;
4219	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_dppd_u128, iemAImpl_dppd_u128_fallback;
4220
4221
4222	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF2U128IMM8,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc, uint8_t bEvil));
4223	typedef FNIEMAIMPLMEDIAF2U128IMM8 *PFNIEMAIMPLMEDIAF2U128IMM8;
4224
4225
4226	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF2U256IMM8,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86YMMREG puSrc, uint8_t bEvil));
4227	typedef FNIEMAIMPLMEDIAF2U256IMM8 *PFNIEMAIMPLMEDIAF2U256IMM8;
4228
4229
4230	FNIEMAIMPLMEDIAF2U128IMM8 iemAImpl_roundps_u128, iemAImpl_roundps_u128_fallback;
4231	FNIEMAIMPLMEDIAF2U128IMM8 iemAImpl_roundpd_u128, iemAImpl_roundpd_u128_fallback;
4232
4233	FNIEMAIMPLMEDIAF2U128IMM8 iemAImpl_vroundps_u128, iemAImpl_vroundps_u128_fallback;
4234	FNIEMAIMPLMEDIAF2U128IMM8 iemAImpl_vroundpd_u128, iemAImpl_vroundpd_u128_fallback;
4235
4236	FNIEMAIMPLMEDIAF2U256IMM8 iemAImpl_vroundps_u256, iemAImpl_vroundps_u256_fallback;
4237	FNIEMAIMPLMEDIAF2U256IMM8 iemAImpl_vroundpd_u256, iemAImpl_vroundpd_u256_fallback;
4238
4239
4240	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRU64U128,(uint32_t fMxCsrIn, uint64_t *pu64Dst, PCX86XMMREG pSrc));
4241	typedef FNIEMAIMPLMXCSRU64U128 *PFNIEMAIMPLMXCSRU64U128;
4242
4243	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvtpd2pi_u128;
4244	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvttpd2pi_u128;
4245
4246	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRU128U64,(uint32_t fMxCsrIn, PX86XMMREG pDst, uint64_t u64Src));
4247	typedef FNIEMAIMPLMXCSRU128U64 *PFNIEMAIMPLMXCSRU128U64;
4248
4249	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2ps_u128;
4250	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2pd_u128;
4251
4252	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRU64U64,(uint32_t fMxCsrIn, uint64_t *pu64Dst, uint64_t u64Src));
4253	typedef FNIEMAIMPLMXCSRU64U64 *PFNIEMAIMPLMXCSRU64U64;
4254
4255	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvtps2pi_u128;
4256	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvttps2pi_u128;
4257
4258	/** @} */
4259
4260
4261	/** @name Function tables.
4262	* @{
4263	*/
4264
4265	/**
4266	* Function table for a binary operator providing implementation based on
4267	* operand size.
4268	*/
4269	typedef struct IEMOPBINSIZES
4270	{
4271	PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
4272	PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
4273	PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
4274	PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
4275	} IEMOPBINSIZES;
4276	/** Pointer to a binary operator function table. */
4277	typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
4278
4279
4280	/**
4281	* Function table for a unary operator providing implementation based on
4282	* operand size.
4283	*/
4284	typedef struct IEMOPUNARYSIZES
4285	{
4286	PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
4287	PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
4288	PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
4289	PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
4290	} IEMOPUNARYSIZES;
4291	/** Pointer to a unary operator function table. */
4292	typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
4293
4294
4295	/**
4296	* Function table for a shift operator providing implementation based on
4297	* operand size.
4298	*/
4299	typedef struct IEMOPSHIFTSIZES
4300	{
4301	PFNIEMAIMPLSHIFTU8 pfnNormalU8;
4302	PFNIEMAIMPLSHIFTU16 pfnNormalU16;
4303	PFNIEMAIMPLSHIFTU32 pfnNormalU32;
4304	PFNIEMAIMPLSHIFTU64 pfnNormalU64;
4305	} IEMOPSHIFTSIZES;
4306	/** Pointer to a shift operator function table. */
4307	typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
4308
4309
4310	/**
4311	* Function table for a multiplication or division operation.
4312	*/
4313	typedef struct IEMOPMULDIVSIZES
4314	{
4315	PFNIEMAIMPLMULDIVU8 pfnU8;
4316	PFNIEMAIMPLMULDIVU16 pfnU16;
4317	PFNIEMAIMPLMULDIVU32 pfnU32;
4318	PFNIEMAIMPLMULDIVU64 pfnU64;
4319	} IEMOPMULDIVSIZES;
4320	/** Pointer to a multiplication or division operation function table. */
4321	typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
4322
4323
4324	/**
4325	* Function table for a double precision shift operator providing implementation
4326	* based on operand size.
4327	*/
4328	typedef struct IEMOPSHIFTDBLSIZES
4329	{
4330	PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
4331	PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
4332	PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
4333	} IEMOPSHIFTDBLSIZES;
4334	/** Pointer to a double precision shift function table. */
4335	typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
4336
4337
4338	/**
4339	* Function table for media instruction taking two full sized media source
4340	* registers and one full sized destination register (AVX).
4341	*/
4342	typedef struct IEMOPMEDIAF3
4343	{
4344	PFNIEMAIMPLMEDIAF3U128 pfnU128;
4345	PFNIEMAIMPLMEDIAF3U256 pfnU256;
4346	} IEMOPMEDIAF3;
4347	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
4348	typedef IEMOPMEDIAF3 const *PCIEMOPMEDIAF3;
4349
4350	/** @def IEMOPMEDIAF3_INIT_VARS_EX
4351	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4352	* given functions as initializers. For use in AVX functions where a pair of
4353	* functions are only used once and the function table need not be public. */
4354	#ifndef TST_IEM_CHECK_MC
4355	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4356	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4357	static IEMOPMEDIAF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4358	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4359	# else
4360	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4361	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4362	# endif
4363	#else
4364	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4365	#endif
4366	/** @def IEMOPMEDIAF3_INIT_VARS
4367	* Generate AVX function tables for the @a a_InstrNm instruction.
4368	* @sa IEMOPMEDIAF3_INIT_VARS_EX */
4369	#define IEMOPMEDIAF3_INIT_VARS(a_InstrNm) \
4370	IEMOPMEDIAF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4371	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4372
4373
4374	/**
4375	* Function table for media instruction taking one full sized media source
4376	* registers and one full sized destination register (AVX).
4377	*/
4378	typedef struct IEMOPMEDIAF2
4379	{
4380	PFNIEMAIMPLMEDIAF2U128 pfnU128;
4381	PFNIEMAIMPLMEDIAF2U256 pfnU256;
4382	} IEMOPMEDIAF2;
4383	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
4384	typedef IEMOPMEDIAF2 const *PCIEMOPMEDIAF2;
4385
4386	/** @def IEMOPMEDIAF2_INIT_VARS_EX
4387	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4388	* given functions as initializers. For use in AVX functions where a pair of
4389	* functions are only used once and the function table need not be public. */
4390	#ifndef TST_IEM_CHECK_MC
4391	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4392	# define IEMOPMEDIAF2_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4393	static IEMOPMEDIAF2 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4394	static IEMOPMEDIAF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4395	# else
4396	# define IEMOPMEDIAF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4397	static IEMOPMEDIAF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4398	# endif
4399	#else
4400	# define IEMOPMEDIAF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4401	#endif
4402	/** @def IEMOPMEDIAF2_INIT_VARS
4403	* Generate AVX function tables for the @a a_InstrNm instruction.
4404	* @sa IEMOPMEDIAF2_INIT_VARS_EX */
4405	#define IEMOPMEDIAF2_INIT_VARS(a_InstrNm) \
4406	IEMOPMEDIAF2_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4407	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4408
4409
4410	/**
4411	* Function table for media instruction taking two full sized media source
4412	* registers and one full sized destination register, but no additional state
4413	* (AVX).
4414	*/
4415	typedef struct IEMOPMEDIAOPTF3
4416	{
4417	PFNIEMAIMPLMEDIAOPTF3U128 pfnU128;
4418	PFNIEMAIMPLMEDIAOPTF3U256 pfnU256;
4419	} IEMOPMEDIAOPTF3;
4420	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
4421	typedef IEMOPMEDIAOPTF3 const *PCIEMOPMEDIAOPTF3;
4422
4423	/** @def IEMOPMEDIAOPTF3_INIT_VARS_EX
4424	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4425	* given functions as initializers. For use in AVX functions where a pair of
4426	* functions are only used once and the function table need not be public. */
4427	#ifndef TST_IEM_CHECK_MC
4428	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4429	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4430	static IEMOPMEDIAOPTF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4431	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4432	# else
4433	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4434	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4435	# endif
4436	#else
4437	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4438	#endif
4439	/** @def IEMOPMEDIAOPTF3_INIT_VARS
4440	* Generate AVX function tables for the @a a_InstrNm instruction.
4441	* @sa IEMOPMEDIAOPTF3_INIT_VARS_EX */
4442	#define IEMOPMEDIAOPTF3_INIT_VARS(a_InstrNm) \
4443	IEMOPMEDIAOPTF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4444	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4445
4446	/**
4447	* Function table for media instruction taking one full sized media source
4448	* registers and one full sized destination register, but no additional state
4449	* (AVX).
4450	*/
4451	typedef struct IEMOPMEDIAOPTF2
4452	{
4453	PFNIEMAIMPLMEDIAOPTF2U128 pfnU128;
4454	PFNIEMAIMPLMEDIAOPTF2U256 pfnU256;
4455	} IEMOPMEDIAOPTF2;
4456	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
4457	typedef IEMOPMEDIAOPTF2 const *PCIEMOPMEDIAOPTF2;
4458
4459	/** @def IEMOPMEDIAOPTF2_INIT_VARS_EX
4460	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4461	* given functions as initializers. For use in AVX functions where a pair of
4462	* functions are only used once and the function table need not be public. */
4463	#ifndef TST_IEM_CHECK_MC
4464	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4465	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4466	static IEMOPMEDIAOPTF2 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4467	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4468	# else
4469	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4470	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4471	# endif
4472	#else
4473	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4474	#endif
4475	/** @def IEMOPMEDIAOPTF2_INIT_VARS
4476	* Generate AVX function tables for the @a a_InstrNm instruction.
4477	* @sa IEMOPMEDIAOPTF2_INIT_VARS_EX */
4478	#define IEMOPMEDIAOPTF2_INIT_VARS(a_InstrNm) \
4479	IEMOPMEDIAOPTF2_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4480	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4481
4482
4483	/**
4484	* Function table for media instruction taking one full sized media source
4485	* register and one full sized destination register and an 8-bit immediate (AVX).
4486	*/
4487	typedef struct IEMOPMEDIAF2IMM8
4488	{
4489	PFNIEMAIMPLMEDIAF2U128IMM8 pfnU128;
4490	PFNIEMAIMPLMEDIAF2U256IMM8 pfnU256;
4491	} IEMOPMEDIAF2IMM8;
4492	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
4493	typedef IEMOPMEDIAF2IMM8 const *PCIEMOPMEDIAF2IMM8;
4494
4495	/** @def IEMOPMEDIAF2IMM8_INIT_VARS_EX
4496	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4497	* given functions as initializers. For use in AVX functions where a pair of
4498	* functions are only used once and the function table need not be public. */
4499	#ifndef TST_IEM_CHECK_MC
4500	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4501	# define IEMOPMEDIAF2IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4502	static IEMOPMEDIAF2IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4503	static IEMOPMEDIAF2IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4504	# else
4505	# define IEMOPMEDIAF2IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4506	static IEMOPMEDIAF2IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4507	# endif
4508	#else
4509	# define IEMOPMEDIAF2IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4510	#endif
4511	/** @def IEMOPMEDIAF2IMM8_INIT_VARS
4512	* Generate AVX function tables for the @a a_InstrNm instruction.
4513	* @sa IEMOPMEDIAF2IMM8_INIT_VARS_EX */
4514	#define IEMOPMEDIAF2IMM8_INIT_VARS(a_InstrNm) \
4515	IEMOPMEDIAF2IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4516	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4517
4518
4519	/**
4520	* Function table for media instruction taking one full sized media source
4521	* register and one full sized destination register and an 8-bit immediate, but no additional state
4522	* (AVX).
4523	*/
4524	typedef struct IEMOPMEDIAOPTF2IMM8
4525	{
4526	PFNIEMAIMPLMEDIAOPTF2U128IMM8 pfnU128;
4527	PFNIEMAIMPLMEDIAOPTF2U256IMM8 pfnU256;
4528	} IEMOPMEDIAOPTF2IMM8;
4529	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
4530	typedef IEMOPMEDIAOPTF2IMM8 const *PCIEMOPMEDIAOPTF2IMM8;
4531
4532	/** @def IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX
4533	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4534	* given functions as initializers. For use in AVX functions where a pair of
4535	* functions are only used once and the function table need not be public. */
4536	#ifndef TST_IEM_CHECK_MC
4537	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4538	# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4539	static IEMOPMEDIAOPTF2IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4540	static IEMOPMEDIAOPTF2IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4541	# else
4542	# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4543	static IEMOPMEDIAOPTF2IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4544	# endif
4545	#else
4546	# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4547	#endif
4548	/** @def IEMOPMEDIAOPTF2IMM8_INIT_VARS
4549	* Generate AVX function tables for the @a a_InstrNm instruction.
4550	* @sa IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX */
4551	#define IEMOPMEDIAOPTF2IMM8_INIT_VARS(a_InstrNm) \
4552	IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u256),\
4553	RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u256_fallback))
4554
4555	/**
4556	* Function table for media instruction taking two full sized media source
4557	* registers and one full sized destination register and an 8-bit immediate, but no additional state
4558	* (AVX).
4559	*/
4560	typedef struct IEMOPMEDIAOPTF3IMM8
4561	{
4562	PFNIEMAIMPLMEDIAOPTF3U128IMM8 pfnU128;
4563	PFNIEMAIMPLMEDIAOPTF3U256IMM8 pfnU256;
4564	} IEMOPMEDIAOPTF3IMM8;
4565	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
4566	typedef IEMOPMEDIAOPTF3IMM8 const *PCIEMOPMEDIAOPTF3IMM8;
4567
4568	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX
4569	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4570	* given functions as initializers. For use in AVX functions where a pair of
4571	* functions are only used once and the function table need not be public. */
4572	#ifndef TST_IEM_CHECK_MC
4573	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4574	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4575	static IEMOPMEDIAOPTF3IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4576	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4577	# else
4578	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4579	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4580	# endif
4581	#else
4582	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4583	#endif
4584	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS
4585	* Generate AVX function tables for the @a a_InstrNm instruction.
4586	* @sa IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX */
4587	#define IEMOPMEDIAOPTF3IMM8_INIT_VARS(a_InstrNm) \
4588	IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4589	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4590	/** @} */
4591
4592
4593	/**
4594	* Function table for blend type instruction taking three full sized media source
4595	* registers and one full sized destination register, but no additional state
4596	* (AVX).
4597	*/
4598	typedef struct IEMOPBLENDOP
4599	{
4600	PFNIEMAIMPLAVXBLENDU128 pfnU128;
4601	PFNIEMAIMPLAVXBLENDU256 pfnU256;
4602	} IEMOPBLENDOP;
4603	/** Pointer to a media operation function table for 4 full sized ops (AVX). */
4604	typedef IEMOPBLENDOP const *PCIEMOPBLENDOP;
4605
4606	/** @def IEMOPBLENDOP_INIT_VARS_EX
4607	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4608	* given functions as initializers. For use in AVX functions where a pair of
4609	* functions are only used once and the function table need not be public. */
4610	#ifndef TST_IEM_CHECK_MC
4611	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4612	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4613	static IEMOPBLENDOP const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4614	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4615	# else
4616	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4617	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4618	# endif
4619	#else
4620	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4621	#endif
4622	/** @def IEMOPBLENDOP_INIT_VARS
4623	* Generate AVX function tables for the @a a_InstrNm instruction.
4624	* @sa IEMOPBLENDOP_INIT_VARS_EX */
4625	#define IEMOPBLENDOP_INIT_VARS(a_InstrNm) \
4626	IEMOPBLENDOP_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4627	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4628
4629
4630	/** @name SSE/AVX single/double precision floating point operations.
4631	* @{ */
4632	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
4633	typedef FNIEMAIMPLFPSSEF2U128 *PFNIEMAIMPLFPSSEF2U128;
4634	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128R32,(uint32_t uMxCsrIn, PX86XMMREG Result, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
4635	typedef FNIEMAIMPLFPSSEF2U128R32 *PFNIEMAIMPLFPSSEF2U128R32;
4636	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128R64,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
4637	typedef FNIEMAIMPLFPSSEF2U128R64 *PFNIEMAIMPLFPSSEF2U128R64;
4638
4639	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
4640	typedef FNIEMAIMPLFPAVXF3U128 *PFNIEMAIMPLFPAVXF3U128;
4641	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U128R32,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
4642	typedef FNIEMAIMPLFPAVXF3U128R32 *PFNIEMAIMPLFPAVXF3U128R32;
4643	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U128R64,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
4644	typedef FNIEMAIMPLFPAVXF3U128R64 *PFNIEMAIMPLFPAVXF3U128R64;
4645
4646	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U256,(uint32_t uMxCsrIn, PX86YMMREG pResult, PCX86YMMREG puSrc1, PCX86YMMREG puSrc2));
4647	typedef FNIEMAIMPLFPAVXF3U256 *PFNIEMAIMPLFPAVXF3U256;
4648
4649	FNIEMAIMPLFPSSEF2U128 iemAImpl_addps_u128;
4650	FNIEMAIMPLFPSSEF2U128 iemAImpl_addpd_u128;
4651	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulps_u128;
4652	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulpd_u128;
4653	FNIEMAIMPLFPSSEF2U128 iemAImpl_subps_u128;
4654	FNIEMAIMPLFPSSEF2U128 iemAImpl_subpd_u128;
4655	FNIEMAIMPLFPSSEF2U128 iemAImpl_minps_u128;
4656	FNIEMAIMPLFPSSEF2U128 iemAImpl_minpd_u128;
4657	FNIEMAIMPLFPSSEF2U128 iemAImpl_divps_u128;
4658	FNIEMAIMPLFPSSEF2U128 iemAImpl_divpd_u128;
4659	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxps_u128;
4660	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxpd_u128;
4661	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddps_u128;
4662	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddpd_u128;
4663	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubps_u128;
4664	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubpd_u128;
4665	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtps_u128;
4666	FNIEMAIMPLFPSSEF2U128 iemAImpl_rsqrtps_u128;
4667	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtpd_u128;
4668	FNIEMAIMPLFPSSEF2U128 iemAImpl_rcpps_u128;
4669	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubps_u128;
4670	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubpd_u128;
4671
4672	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2ps_u128;
4673	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_cvtps2pd_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, uint64_t const *pu64Src));
4674
4675	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2ps_u128;
4676	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2dq_u128;
4677	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttps2dq_u128;
4678	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttpd2dq_u128;
4679	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2pd_u128;
4680	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2dq_u128;
4681
4682	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_addss_u128_r32;
4683	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_addsd_u128_r64;
4684	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_mulss_u128_r32;
4685	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_mulsd_u128_r64;
4686	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_subss_u128_r32;
4687	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_subsd_u128_r64;
4688	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_minss_u128_r32;
4689	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_minsd_u128_r64;
4690	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_divss_u128_r32;
4691	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_divsd_u128_r64;
4692	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_maxss_u128_r32;
4693	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_maxsd_u128_r64;
4694	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_cvtss2sd_u128_r32;
4695	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_cvtsd2ss_u128_r64;
4696	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_sqrtss_u128_r32;
4697	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_sqrtsd_u128_r64;
4698	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_rsqrtss_u128_r32;
4699	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_rcpss_u128_r32;
4700
4701	FNIEMAIMPLMEDIAF3U128 iemAImpl_vaddps_u128, iemAImpl_vaddps_u128_fallback;
4702	FNIEMAIMPLMEDIAF3U128 iemAImpl_vaddpd_u128, iemAImpl_vaddpd_u128_fallback;
4703	FNIEMAIMPLMEDIAF3U128 iemAImpl_vmulps_u128, iemAImpl_vmulps_u128_fallback;
4704	FNIEMAIMPLMEDIAF3U128 iemAImpl_vmulpd_u128, iemAImpl_vmulpd_u128_fallback;
4705	FNIEMAIMPLMEDIAF3U128 iemAImpl_vsubps_u128, iemAImpl_vsubps_u128_fallback;
4706	FNIEMAIMPLMEDIAF3U128 iemAImpl_vsubpd_u128, iemAImpl_vsubpd_u128_fallback;
4707	FNIEMAIMPLMEDIAF3U128 iemAImpl_vminps_u128, iemAImpl_vminps_u128_fallback;
4708	FNIEMAIMPLMEDIAF3U128 iemAImpl_vminpd_u128, iemAImpl_vminpd_u128_fallback;
4709	FNIEMAIMPLMEDIAF3U128 iemAImpl_vdivps_u128, iemAImpl_vdivps_u128_fallback;
4710	FNIEMAIMPLMEDIAF3U128 iemAImpl_vdivpd_u128, iemAImpl_vdivpd_u128_fallback;
4711	FNIEMAIMPLMEDIAF3U128 iemAImpl_vmaxps_u128, iemAImpl_vmaxps_u128_fallback;
4712	FNIEMAIMPLMEDIAF3U128 iemAImpl_vmaxpd_u128, iemAImpl_vmaxpd_u128_fallback;
4713	FNIEMAIMPLMEDIAF3U128 iemAImpl_vhaddps_u128, iemAImpl_vhaddps_u128_fallback;
4714	FNIEMAIMPLMEDIAF3U128 iemAImpl_vhaddpd_u128, iemAImpl_vhaddpd_u128_fallback;
4715	FNIEMAIMPLMEDIAF3U128 iemAImpl_vhsubps_u128, iemAImpl_vhsubps_u128_fallback;
4716	FNIEMAIMPLMEDIAF3U128 iemAImpl_vhsubpd_u128, iemAImpl_vhsubpd_u128_fallback;
4717	FNIEMAIMPLMEDIAF2U128 iemAImpl_vsqrtps_u128, iemAImpl_vsqrtps_u128_fallback;
4718	FNIEMAIMPLMEDIAF2U128 iemAImpl_vsqrtpd_u128, iemAImpl_vsqrtpd_u128_fallback;
4719	FNIEMAIMPLMEDIAF2U128 iemAImpl_vrsqrtps_u128, iemAImpl_vrsqrtps_u128_fallback;
4720	FNIEMAIMPLMEDIAF2U128 iemAImpl_vrcpps_u128, iemAImpl_vrcpps_u128_fallback;
4721	FNIEMAIMPLMEDIAF3U128 iemAImpl_vaddsubps_u128, iemAImpl_vaddsubps_u128_fallback;
4722	FNIEMAIMPLMEDIAF3U128 iemAImpl_vaddsubpd_u128, iemAImpl_vaddsubpd_u128_fallback;
4723	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtpd2ps_u128, iemAImpl_vcvtpd2ps_u128_fallback;
4724	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtps2pd_u128, iemAImpl_vcvtps2pd_u128_fallback;
4725
4726	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vaddss_u128_r32, iemAImpl_vaddss_u128_r32_fallback;
4727	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vaddsd_u128_r64, iemAImpl_vaddsd_u128_r64_fallback;
4728	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmulss_u128_r32, iemAImpl_vmulss_u128_r32_fallback;
4729	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmulsd_u128_r64, iemAImpl_vmulsd_u128_r64_fallback;
4730	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsubss_u128_r32, iemAImpl_vsubss_u128_r32_fallback;
4731	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsubsd_u128_r64, iemAImpl_vsubsd_u128_r64_fallback;
4732	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vminss_u128_r32, iemAImpl_vminss_u128_r32_fallback;
4733	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vminsd_u128_r64, iemAImpl_vminsd_u128_r64_fallback;
4734	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vdivss_u128_r32, iemAImpl_vdivss_u128_r32_fallback;
4735	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vdivsd_u128_r64, iemAImpl_vdivsd_u128_r64_fallback;
4736	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmaxss_u128_r32, iemAImpl_vmaxss_u128_r32_fallback;
4737	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmaxsd_u128_r64, iemAImpl_vmaxsd_u128_r64_fallback;
4738	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsqrtss_u128_r32, iemAImpl_vsqrtss_u128_r32_fallback;
4739	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsqrtsd_u128_r64, iemAImpl_vsqrtsd_u128_r64_fallback;
4740	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vrsqrtss_u128_r32, iemAImpl_vrsqrtss_u128_r32_fallback;
4741	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vrcpss_u128_r32, iemAImpl_vrcpss_u128_r32_fallback;
4742
4743	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddps_u256, iemAImpl_vaddps_u256_fallback;
4744	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddpd_u256, iemAImpl_vaddpd_u256_fallback;
4745	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulps_u256, iemAImpl_vmulps_u256_fallback;
4746	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulpd_u256, iemAImpl_vmulpd_u256_fallback;
4747	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubps_u256, iemAImpl_vsubps_u256_fallback;
4748	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubpd_u256, iemAImpl_vsubpd_u256_fallback;
4749	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminps_u256, iemAImpl_vminps_u256_fallback;
4750	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminpd_u256, iemAImpl_vminpd_u256_fallback;
4751	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivps_u256, iemAImpl_vdivps_u256_fallback;
4752	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivpd_u256, iemAImpl_vdivpd_u256_fallback;
4753	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxps_u256, iemAImpl_vmaxps_u256_fallback;
4754	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxpd_u256, iemAImpl_vmaxpd_u256_fallback;
4755	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddps_u256, iemAImpl_vhaddps_u256_fallback;
4756	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddpd_u256, iemAImpl_vhaddpd_u256_fallback;
4757	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubps_u256, iemAImpl_vhsubps_u256_fallback;
4758	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubpd_u256, iemAImpl_vhsubpd_u256_fallback;
4759	FNIEMAIMPLMEDIAF3U256 iemAImpl_vaddsubps_u256, iemAImpl_vaddsubps_u256_fallback;
4760	FNIEMAIMPLMEDIAF3U256 iemAImpl_vaddsubpd_u256, iemAImpl_vaddsubpd_u256_fallback;
4761	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtpd2ps_u256, iemAImpl_vcvtpd2ps_u256_fallback;
4762	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtps2pd_u256, iemAImpl_vcvtps2pd_u256_fallback;
4763	FNIEMAIMPLMEDIAF2U256 iemAImpl_vsqrtps_u256, iemAImpl_vsqrtps_u256_fallback;
4764	FNIEMAIMPLMEDIAF2U256 iemAImpl_vsqrtpd_u256, iemAImpl_vsqrtpd_u256_fallback;
4765	FNIEMAIMPLMEDIAF2U256 iemAImpl_vrsqrtps_u256, iemAImpl_vrsqrtps_u256_fallback;
4766	FNIEMAIMPLMEDIAF2U256 iemAImpl_vrcpps_u256, iemAImpl_vrcpps_u256_fallback;
4767	/** @} */
4768
4769	/** @name C instruction implementations for anything slightly complicated.
4770	* @{ */
4771
4772	/**
4773	* For typedef'ing or declaring a C instruction implementation function taking
4774	* no extra arguments.
4775	*
4776	* @param a_Name The name of the type.
4777	*/
4778	# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
4779	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
4780	/**
4781	* For defining a C instruction implementation function taking no extra
4782	* arguments.
4783	*
4784	* @param a_Name The name of the function
4785	*/
4786	# define IEM_CIMPL_DEF_0(a_Name) \
4787	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
4788	/**
4789	* Prototype version of IEM_CIMPL_DEF_0.
4790	*/
4791	# define IEM_CIMPL_PROTO_0(a_Name) \
4792	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
4793	/**
4794	* For calling a C instruction implementation function taking no extra
4795	* arguments.
4796	*
4797	* This special call macro adds default arguments to the call and allow us to
4798	* change these later.
4799	*
4800	* @param a_fn The name of the function.
4801	*/
4802	# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
4803
4804	/** Type for a C instruction implementation function taking no extra
4805	* arguments. */
4806	typedef IEM_CIMPL_DECL_TYPE_0(FNIEMCIMPL0);
4807	/** Function pointer type for a C instruction implementation function taking
4808	* no extra arguments. */
4809	typedef FNIEMCIMPL0 *PFNIEMCIMPL0;
4810
4811	/**
4812	* For typedef'ing or declaring a C instruction implementation function taking
4813	* one extra argument.
4814	*
4815	* @param a_Name The name of the type.
4816	* @param a_Type0 The argument type.
4817	* @param a_Arg0 The argument name.
4818	*/
4819	# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
4820	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
4821	/**
4822	* For defining a C instruction implementation function taking one extra
4823	* argument.
4824	*
4825	* @param a_Name The name of the function
4826	* @param a_Type0 The argument type.
4827	* @param a_Arg0 The argument name.
4828	*/
4829	# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
4830	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
4831	/**
4832	* Prototype version of IEM_CIMPL_DEF_1.
4833	*/
4834	# define IEM_CIMPL_PROTO_1(a_Name, a_Type0, a_Arg0) \
4835	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
4836	/**
4837	* For calling a C instruction implementation function taking one extra
4838	* argument.
4839	*
4840	* This special call macro adds default arguments to the call and allow us to
4841	* change these later.
4842	*
4843	* @param a_fn The name of the function.
4844	* @param a0 The name of the 1st argument.
4845	*/
4846	# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
4847
4848	/**
4849	* For typedef'ing or declaring a C instruction implementation function taking
4850	* two extra arguments.
4851	*
4852	* @param a_Name The name of the type.
4853	* @param a_Type0 The type of the 1st argument
4854	* @param a_Arg0 The name of the 1st argument.
4855	* @param a_Type1 The type of the 2nd argument.
4856	* @param a_Arg1 The name of the 2nd argument.
4857	*/
4858	# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
4859	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
4860	/**
4861	* For defining a C instruction implementation function taking two extra
4862	* arguments.
4863	*
4864	* @param a_Name The name of the function.
4865	* @param a_Type0 The type of the 1st argument
4866	* @param a_Arg0 The name of the 1st argument.
4867	* @param a_Type1 The type of the 2nd argument.
4868	* @param a_Arg1 The name of the 2nd argument.
4869	*/
4870	# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
4871	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
4872	/**
4873	* Prototype version of IEM_CIMPL_DEF_2.
4874	*/
4875	# define IEM_CIMPL_PROTO_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
4876	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
4877	/**
4878	* For calling a C instruction implementation function taking two extra
4879	* arguments.
4880	*
4881	* This special call macro adds default arguments to the call and allow us to
4882	* change these later.
4883	*
4884	* @param a_fn The name of the function.
4885	* @param a0 The name of the 1st argument.
4886	* @param a1 The name of the 2nd argument.
4887	*/
4888	# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
4889
4890	/**
4891	* For typedef'ing or declaring a C instruction implementation function taking
4892	* three extra arguments.
4893	*
4894	* @param a_Name The name of the type.
4895	* @param a_Type0 The type of the 1st argument
4896	* @param a_Arg0 The name of the 1st argument.
4897	* @param a_Type1 The type of the 2nd argument.
4898	* @param a_Arg1 The name of the 2nd argument.
4899	* @param a_Type2 The type of the 3rd argument.
4900	* @param a_Arg2 The name of the 3rd argument.
4901	*/
4902	# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
4903	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
4904	/**
4905	* For defining a C instruction implementation function taking three extra
4906	* arguments.
4907	*
4908	* @param a_Name The name of the function.
4909	* @param a_Type0 The type of the 1st argument
4910	* @param a_Arg0 The name of the 1st argument.
4911	* @param a_Type1 The type of the 2nd argument.
4912	* @param a_Arg1 The name of the 2nd argument.
4913	* @param a_Type2 The type of the 3rd argument.
4914	* @param a_Arg2 The name of the 3rd argument.
4915	*/
4916	# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
4917	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
4918	/**
4919	* Prototype version of IEM_CIMPL_DEF_3.
4920	*/
4921	# define IEM_CIMPL_PROTO_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
4922	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
4923	/**
4924	* For calling a C instruction implementation function taking three extra
4925	* arguments.
4926	*
4927	* This special call macro adds default arguments to the call and allow us to
4928	* change these later.
4929	*
4930	* @param a_fn The name of the function.
4931	* @param a0 The name of the 1st argument.
4932	* @param a1 The name of the 2nd argument.
4933	* @param a2 The name of the 3rd argument.
4934	*/
4935	# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
4936
4937
4938	/**
4939	* For typedef'ing or declaring a C instruction implementation function taking
4940	* four extra arguments.
4941	*
4942	* @param a_Name The name of the type.
4943	* @param a_Type0 The type of the 1st argument
4944	* @param a_Arg0 The name of the 1st argument.
4945	* @param a_Type1 The type of the 2nd argument.
4946	* @param a_Arg1 The name of the 2nd argument.
4947	* @param a_Type2 The type of the 3rd argument.
4948	* @param a_Arg2 The name of the 3rd argument.
4949	* @param a_Type3 The type of the 4th argument.
4950	* @param a_Arg3 The name of the 4th argument.
4951	*/
4952	# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
4953	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
4954	/**
4955	* For defining a C instruction implementation function taking four extra
4956	* arguments.
4957	*
4958	* @param a_Name The name of the function.
4959	* @param a_Type0 The type of the 1st argument
4960	* @param a_Arg0 The name of the 1st argument.
4961	* @param a_Type1 The type of the 2nd argument.
4962	* @param a_Arg1 The name of the 2nd argument.
4963	* @param a_Type2 The type of the 3rd argument.
4964	* @param a_Arg2 The name of the 3rd argument.
4965	* @param a_Type3 The type of the 4th argument.
4966	* @param a_Arg3 The name of the 4th argument.
4967	*/
4968	# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
4969	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4970	a_Type2 a_Arg2, a_Type3 a_Arg3))
4971	/**
4972	* Prototype version of IEM_CIMPL_DEF_4.
4973	*/
4974	# define IEM_CIMPL_PROTO_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
4975	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
4976	a_Type2 a_Arg2, a_Type3 a_Arg3))
4977	/**
4978	* For calling a C instruction implementation function taking four extra
4979	* arguments.
4980	*
4981	* This special call macro adds default arguments to the call and allow us to
4982	* change these later.
4983	*
4984	* @param a_fn The name of the function.
4985	* @param a0 The name of the 1st argument.
4986	* @param a1 The name of the 2nd argument.
4987	* @param a2 The name of the 3rd argument.
4988	* @param a3 The name of the 4th argument.
4989	*/
4990	# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
4991
4992
4993	/**
4994	* For typedef'ing or declaring a C instruction implementation function taking
4995	* five extra arguments.
4996	*
4997	* @param a_Name The name of the type.
4998	* @param a_Type0 The type of the 1st argument
4999	* @param a_Arg0 The name of the 1st argument.
5000	* @param a_Type1 The type of the 2nd argument.
5001	* @param a_Arg1 The name of the 2nd argument.
5002	* @param a_Type2 The type of the 3rd argument.
5003	* @param a_Arg2 The name of the 3rd argument.
5004	* @param a_Type3 The type of the 4th argument.
5005	* @param a_Arg3 The name of the 4th argument.
5006	* @param a_Type4 The type of the 5th argument.
5007	* @param a_Arg4 The name of the 5th argument.
5008	*/
5009	# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
5010	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, \
5011	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
5012	a_Type3 a_Arg3, a_Type4 a_Arg4))
5013	/**
5014	* For defining a C instruction implementation function taking five extra
5015	* arguments.
5016	*
5017	* @param a_Name The name of the function.
5018	* @param a_Type0 The type of the 1st argument
5019	* @param a_Arg0 The name of the 1st argument.
5020	* @param a_Type1 The type of the 2nd argument.
5021	* @param a_Arg1 The name of the 2nd argument.
5022	* @param a_Type2 The type of the 3rd argument.
5023	* @param a_Arg2 The name of the 3rd argument.
5024	* @param a_Type3 The type of the 4th argument.
5025	* @param a_Arg3 The name of the 4th argument.
5026	* @param a_Type4 The type of the 5th argument.
5027	* @param a_Arg4 The name of the 5th argument.
5028	*/
5029	# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
5030	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
5031	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
5032	/**
5033	* Prototype version of IEM_CIMPL_DEF_5.
5034	*/
5035	# define IEM_CIMPL_PROTO_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
5036	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
5037	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
5038	/**
5039	* For calling a C instruction implementation function taking five extra
5040	* arguments.
5041	*
5042	* This special call macro adds default arguments to the call and allow us to
5043	* change these later.
5044	*
5045	* @param a_fn The name of the function.
5046	* @param a0 The name of the 1st argument.
5047	* @param a1 The name of the 2nd argument.
5048	* @param a2 The name of the 3rd argument.
5049	* @param a3 The name of the 4th argument.
5050	* @param a4 The name of the 5th argument.
5051	*/
5052	# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
5053
5054	/** @} */
5055
5056
5057	/** @name Opcode Decoder Function Types.
5058	* @{ */
5059
5060	/** @typedef PFNIEMOP
5061	* Pointer to an opcode decoder function.
5062	*/
5063
5064	/** @def FNIEMOP_DEF
5065	* Define an opcode decoder function.
5066	*
5067	* We're using macors for this so that adding and removing parameters as well as
5068	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL
5069	*
5070	* @param a_Name The function name.
5071	*/
5072
5073	/** @typedef PFNIEMOPRM
5074	* Pointer to an opcode decoder function with RM byte.
5075	*/
5076
5077	/** @def FNIEMOPRM_DEF
5078	* Define an opcode decoder function with RM byte.
5079	*
5080	* We're using macors for this so that adding and removing parameters as well as
5081	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL_1
5082	*
5083	* @param a_Name The function name.
5084	*/
5085
5086	#if defined(__GNUC__) && defined(RT_ARCH_X86)
5087	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOP)(PVMCPUCC pVCpu);
5088	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
5089	# define FNIEMOP_DEF(a_Name) \
5090	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu)
5091	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
5092	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
5093	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
5094	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
5095
5096	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
5097	typedef VBOXSTRICTRC (__fastcall * PFNIEMOP)(PVMCPUCC pVCpu);
5098	typedef VBOXSTRICTRC (__fastcall * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
5099	# define FNIEMOP_DEF(a_Name) \
5100	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
5101	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
5102	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
5103	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
5104	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
5105
5106	#elif defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
5107	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
5108	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
5109	# define FNIEMOP_DEF(a_Name) \
5110	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu)
5111	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
5112	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
5113	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
5114	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
5115
5116	#else
5117	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
5118	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
5119	# define FNIEMOP_DEF(a_Name) \
5120	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
5121	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
5122	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
5123	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
5124	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
5125
5126	#endif
5127	#define FNIEMOPRM_DEF(a_Name) FNIEMOP_DEF_1(a_Name, uint8_t, bRm)
5128
5129	/**
5130	* Call an opcode decoder function.
5131	*
5132	* We're using macors for this so that adding and removing parameters can be
5133	* done as we please. See FNIEMOP_DEF.
5134	*/
5135	#define FNIEMOP_CALL(a_pfn) (a_pfn)(pVCpu)
5136
5137	/**
5138	* Call a common opcode decoder function taking one extra argument.
5139	*
5140	* We're using macors for this so that adding and removing parameters can be
5141	* done as we please. See FNIEMOP_DEF_1.
5142	*/
5143	#define FNIEMOP_CALL_1(a_pfn, a0) (a_pfn)(pVCpu, a0)
5144
5145	/**
5146	* Call a common opcode decoder function taking one extra argument.
5147	*
5148	* We're using macors for this so that adding and removing parameters can be
5149	* done as we please. See FNIEMOP_DEF_1.
5150	*/
5151	#define FNIEMOP_CALL_2(a_pfn, a0, a1) (a_pfn)(pVCpu, a0, a1)
5152	/** @} */
5153
5154
5155	/** @name Misc Helpers
5156	* @{ */
5157
5158	/** Used to shut up GCC warnings about variables that 'may be used uninitialized'
5159	* due to GCC lacking knowledge about the value range of a switch. */
5160	#if RT_CPLUSPLUS_PREREQ(202000)
5161	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: [[unlikely]] AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
5162	#else
5163	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
5164	#endif
5165
5166	/** Variant of IEM_NOT_REACHED_DEFAULT_CASE_RET that returns a custom value. */
5167	#if RT_CPLUSPLUS_PREREQ(202000)
5168	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: [[unlikely]] AssertFailedReturn(a_RetValue)
5169	#else
5170	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: AssertFailedReturn(a_RetValue)
5171	#endif
5172
5173	/**
5174	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
5175	* occation.
5176	*/
5177	#ifdef LOG_ENABLED
5178	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
5179	do { \
5180	/Log/ LogAlways(("%s: returning IEM_RETURN_ASPECT_NOT_IMPLEMENTED (line %d)\n", __FUNCTION__, __LINE__)); \
5181	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
5182	} while (0)
5183	#else
5184	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
5185	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
5186	#endif
5187
5188	/**
5189	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
5190	* occation using the supplied logger statement.
5191	*
5192	* @param a_LoggerArgs What to log on failure.
5193	*/
5194	#ifdef LOG_ENABLED
5195	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
5196	do { \
5197	LogAlways((LOG_FN_FMT ": ", __PRETTY_FUNCTION__)); LogAlways(a_LoggerArgs); \
5198	/LogFunc(a_LoggerArgs);/ \
5199	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
5200	} while (0)
5201	#else
5202	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
5203	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
5204	#endif
5205
5206	/**
5207	* Gets the CPU mode (from fExec) as a IEMMODE value.
5208	*
5209	* @returns IEMMODE
5210	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5211	*/
5212	#define IEM_GET_CPU_MODE(a_pVCpu) ((a_pVCpu)->iem.s.fExec & IEM_F_MODE_CPUMODE_MASK)
5213
5214	/**
5215	* Check if we're currently executing in real or virtual 8086 mode.
5216	*
5217	* @returns @c true if it is, @c false if not.
5218	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5219	*/
5220	#define IEM_IS_REAL_OR_V86_MODE(a_pVCpu) (( ((a_pVCpu)->iem.s.fExec ^ IEM_F_MODE_X86_PROT_MASK) \
5221	& (IEM_F_MODE_X86_V86_MASK \| IEM_F_MODE_X86_PROT_MASK)) != 0)
5222
5223	/**
5224	* Check if we're currently executing in virtual 8086 mode.
5225	*
5226	* @returns @c true if it is, @c false if not.
5227	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5228	*/
5229	#define IEM_IS_V86_MODE(a_pVCpu) (((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_V86_MASK) != 0)
5230
5231	/**
5232	* Check if we're currently executing in long mode.
5233	*
5234	* @returns @c true if it is, @c false if not.
5235	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5236	*/
5237	#define IEM_IS_LONG_MODE(a_pVCpu) (CPUMIsGuestInLongModeEx(IEM_GET_CTX(a_pVCpu)))
5238
5239	/**
5240	* Check if we're currently executing in a 16-bit code segment.
5241	*
5242	* @returns @c true if it is, @c false if not.
5243	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5244	*/
5245	#define IEM_IS_16BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_16BIT)
5246
5247	/**
5248	* Check if we're currently executing in a 32-bit code segment.
5249	*
5250	* @returns @c true if it is, @c false if not.
5251	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5252	*/
5253	#define IEM_IS_32BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_32BIT)
5254
5255	/**
5256	* Check if we're currently executing in a 64-bit code segment.
5257	*
5258	* @returns @c true if it is, @c false if not.
5259	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5260	*/
5261	#define IEM_IS_64BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_64BIT)
5262
5263	/**
5264	* Check if we're currently executing in real mode.
5265	*
5266	* @returns @c true if it is, @c false if not.
5267	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5268	*/
5269	#define IEM_IS_REAL_MODE(a_pVCpu) (!((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_PROT_MASK))
5270
5271	/**
5272	* Gets the current protection level (CPL).
5273	*
5274	* @returns 0..3
5275	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5276	*/
5277	#define IEM_GET_CPL(a_pVCpu) (((a_pVCpu)->iem.s.fExec >> IEM_F_X86_CPL_SHIFT) & IEM_F_X86_CPL_SMASK)
5278
5279	/**
5280	* Sets the current protection level (CPL).
5281	*
5282	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5283	*/
5284	#define IEM_SET_CPL(a_pVCpu, a_uCpl) \
5285	do { (a_pVCpu)->iem.s.fExec = ((a_pVCpu)->iem.s.fExec & ~IEM_F_X86_CPL_MASK) \| ((a_uCpl) << IEM_F_X86_CPL_SHIFT); } while (0)
5286
5287	/**
5288	* Returns a (const) pointer to the CPUMFEATURES for the guest CPU.
5289	* @returns PCCPUMFEATURES
5290	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5291	*/
5292	#define IEM_GET_GUEST_CPU_FEATURES(a_pVCpu) (&((a_pVCpu)->CTX_SUFF(pVM)->cpum.ro.GuestFeatures))
5293
5294	/**
5295	* Returns a (const) pointer to the CPUMFEATURES for the host CPU.
5296	* @returns PCCPUMFEATURES
5297	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5298	*/
5299	#define IEM_GET_HOST_CPU_FEATURES(a_pVCpu) (&g_CpumHostFeatures.s)
5300
5301	/**
5302	* Evaluates to true if we're presenting an Intel CPU to the guest.
5303	*/
5304	#define IEM_IS_GUEST_CPU_INTEL(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL )
5305
5306	/**
5307	* Evaluates to true if we're presenting an AMD CPU to the guest.
5308	*/
5309	#define IEM_IS_GUEST_CPU_AMD(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_AMD \|\| (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_HYGON )
5310
5311	/**
5312	* Check if the address is canonical.
5313	*/
5314	#define IEM_IS_CANONICAL(a_u64Addr) X86_IS_CANONICAL(a_u64Addr)
5315
5316	/** Checks if the ModR/M byte is in register mode or not. */
5317	#define IEM_IS_MODRM_REG_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT) )
5318	/** Checks if the ModR/M byte is in memory mode or not. */
5319	#define IEM_IS_MODRM_MEM_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT) )
5320
5321	/**
5322	* Gets the register (reg) part of a ModR/M encoding, with REX.R added in.
5323	*
5324	* For use during decoding.
5325	*/
5326	#define IEM_GET_MODRM_REG(a_pVCpu, a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| (a_pVCpu)->iem.s.uRexReg )
5327	/**
5328	* Gets the r/m part of a ModR/M encoding as a register index, with REX.B added in.
5329	*
5330	* For use during decoding.
5331	*/
5332	#define IEM_GET_MODRM_RM(a_pVCpu, a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) \| (a_pVCpu)->iem.s.uRexB )
5333
5334	/**
5335	* Gets the register (reg) part of a ModR/M encoding, without REX.R.
5336	*
5337	* For use during decoding.
5338	*/
5339	#define IEM_GET_MODRM_REG_8(a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) )
5340	/**
5341	* Gets the r/m part of a ModR/M encoding as a register index, without REX.B.
5342	*
5343	* For use during decoding.
5344	*/
5345	#define IEM_GET_MODRM_RM_8(a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) )
5346
5347	/**
5348	* Gets the register (reg) part of a ModR/M encoding as an extended 8-bit
5349	* register index, with REX.R added in.
5350	*
5351	* For use during decoding.
5352	*
5353	* @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
5354	*/
5355	#define IEM_GET_MODRM_REG_EX8(a_pVCpu, a_bRm) \
5356	( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
5357	\|\| !((a_bRm) & (4 << X86_MODRM_REG_SHIFT)) /* IEM_GET_MODRM_REG(pVCpu, a_bRm) < 4 */ \
5358	? IEM_GET_MODRM_REG(pVCpu, a_bRm) : (((a_bRm) >> X86_MODRM_REG_SHIFT) & 3) \| 16)
5359	/**
5360	* Gets the r/m part of a ModR/M encoding as an extended 8-bit register index,
5361	* with REX.B added in.
5362	*
5363	* For use during decoding.
5364	*
5365	* @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
5366	*/
5367	#define IEM_GET_MODRM_RM_EX8(a_pVCpu, a_bRm) \
5368	( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
5369	\|\| !((a_bRm) & 4) /* IEM_GET_MODRM_RM(pVCpu, a_bRm) < 4 */ \
5370	? IEM_GET_MODRM_RM(pVCpu, a_bRm) : ((a_bRm) & 3) \| 16)
5371
5372	/**
5373	* Combines the prefix REX and ModR/M byte for passing to
5374	* iemOpHlpCalcRmEffAddrThreadedAddr64().
5375	*
5376	* @returns The ModRM byte but with bit 3 set to REX.B and bit 4 to REX.X.
5377	* The two bits are part of the REG sub-field, which isn't needed in
5378	* iemOpHlpCalcRmEffAddrThreadedAddr64().
5379	*
5380	* For use during decoding/recompiling.
5381	*/
5382	#define IEM_GET_MODRM_EX(a_pVCpu, a_bRm) \
5383	( ((a_bRm) & ~X86_MODRM_REG_MASK) \
5384	\| (uint8_t)( (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X)) >> (25 - 3) ) )
5385	AssertCompile(IEM_OP_PRF_REX_B == RT_BIT_32(25));
5386	AssertCompile(IEM_OP_PRF_REX_X == RT_BIT_32(26));
5387
5388	/**
5389	* Gets the effective VEX.VVVV value.
5390	*
5391	* The 4th bit is ignored if not 64-bit code.
5392	* @returns effective V-register value.
5393	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5394	*/
5395	#define IEM_GET_EFFECTIVE_VVVV(a_pVCpu) \
5396	(IEM_IS_64BIT_CODE(a_pVCpu) ? (a_pVCpu)->iem.s.uVex3rdReg : (a_pVCpu)->iem.s.uVex3rdReg & 7)
5397
5398
5399	/**
5400	* Gets the register (reg) part of a the special 4th register byte used by
5401	* vblendvps and vblendvpd.
5402	*
5403	* For use during decoding.
5404	*/
5405	#define IEM_GET_IMM8_REG(a_pVCpu, a_bRegImm8) \
5406	(IEM_IS_64BIT_CODE(a_pVCpu) ? (a_bRegImm8) >> 4 : ((a_bRegImm8) >> 4) & 7)
5407
5408
5409	/**
5410	* Checks if we're executing inside an AMD-V or VT-x guest.
5411	*/
5412	#if defined(VBOX_WITH_NESTED_HWVIRT_VMX) \|\| defined(VBOX_WITH_NESTED_HWVIRT_SVM)
5413	# define IEM_IS_IN_GUEST(a_pVCpu) RT_BOOL((a_pVCpu)->iem.s.fExec & IEM_F_X86_CTX_IN_GUEST)
5414	#else
5415	# define IEM_IS_IN_GUEST(a_pVCpu) false
5416	#endif
5417
5418
5419	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5420
5421	/**
5422	* Check if the guest has entered VMX root operation.
5423	*/
5424	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxRootMode(IEM_GET_CTX(a_pVCpu)))
5425
5426	/**
5427	* Check if the guest has entered VMX non-root operation.
5428	*/
5429	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) ( ((a_pVCpu)->iem.s.fExec & (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST)) \
5430	== (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST) )
5431
5432	/**
5433	* Check if the nested-guest has the given Pin-based VM-execution control set.
5434	*/
5435	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_PinCtl) (CPUMIsGuestVmxPinCtlsSet(IEM_GET_CTX(a_pVCpu), (a_PinCtl)))
5436
5437	/**
5438	* Check if the nested-guest has the given Processor-based VM-execution control set.
5439	*/
5440	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_ProcCtl) (CPUMIsGuestVmxProcCtlsSet(IEM_GET_CTX(a_pVCpu), (a_ProcCtl)))
5441
5442	/**
5443	* Check if the nested-guest has the given Secondary Processor-based VM-execution
5444	* control set.
5445	*/
5446	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_ProcCtl2) (CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(a_pVCpu), (a_ProcCtl2)))
5447
5448	/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
5449	# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
5450
5451	/** Whether a shadow VMCS is present for the given VCPU. */
5452	# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
5453
5454	/** Gets the VMXON region pointer. */
5455	# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
5456
5457	/** Gets the guest-physical address of the current VMCS for the given VCPU. */
5458	# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
5459
5460	/** Whether a current VMCS is present for the given VCPU. */
5461	# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
5462
5463	/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
5464	# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
5465	do \
5466	{ \
5467	Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
5468	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
5469	} while (0)
5470
5471	/** Clears any current VMCS for the given VCPU. */
5472	# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
5473	do \
5474	{ \
5475	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
5476	} while (0)
5477
5478	/**
5479	* Invokes the VMX VM-exit handler for an instruction intercept.
5480	*/
5481	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) \
5482	do { return iemVmxVmexitInstr((a_pVCpu), (a_uExitReason), (a_cbInstr)); } while (0)
5483
5484	/**
5485	* Invokes the VMX VM-exit handler for an instruction intercept where the
5486	* instruction provides additional VM-exit information.
5487	*/
5488	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) \
5489	do { return iemVmxVmexitInstrNeedsInfo((a_pVCpu), (a_uExitReason), (a_uInstrId), (a_cbInstr)); } while (0)
5490
5491	/**
5492	* Invokes the VMX VM-exit handler for a task switch.
5493	*/
5494	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) \
5495	do { return iemVmxVmexitTaskSwitch((a_pVCpu), (a_enmTaskSwitch), (a_SelNewTss), (a_cbInstr)); } while (0)
5496
5497	/**
5498	* Invokes the VMX VM-exit handler for MWAIT.
5499	*/
5500	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) \
5501	do { return iemVmxVmexitInstrMwait((a_pVCpu), (a_fMonitorArmed), (a_cbInstr)); } while (0)
5502
5503	/**
5504	* Invokes the VMX VM-exit handler for EPT faults.
5505	*/
5506	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) \
5507	do { return iemVmxVmexitEpt(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr); } while (0)
5508
5509	/**
5510	* Invokes the VMX VM-exit handler.
5511	*/
5512	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) \
5513	do { return iemVmxVmexit((a_pVCpu), (a_uExitReason), (a_uExitQual)); } while (0)
5514
5515	#else
5516	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (false)
5517	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (false)
5518	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_cbInstr) (false)
5519	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_cbInstr) (false)
5520	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_cbInstr) (false)
5521	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5522	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5523	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5524	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5525	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5526	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) do { return VERR_VMX_IPE_1; } while (0)
5527
5528	#endif
5529
5530	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5531	/**
5532	* Checks if we're executing a guest using AMD-V.
5533	*/
5534	# define IEM_SVM_IS_IN_GUEST(a_pVCpu) ( (a_pVCpu->iem.s.fExec & (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST)) \
5535	== (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST))
5536	/**
5537	* Check if an SVM control/instruction intercept is set.
5538	*/
5539	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) \
5540	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmCtrlInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_Intercept)))
5541
5542	/**
5543	* Check if an SVM read CRx intercept is set.
5544	*/
5545	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
5546	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
5547
5548	/**
5549	* Check if an SVM write CRx intercept is set.
5550	*/
5551	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
5552	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
5553
5554	/**
5555	* Check if an SVM read DRx intercept is set.
5556	*/
5557	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
5558	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
5559
5560	/**
5561	* Check if an SVM write DRx intercept is set.
5562	*/
5563	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
5564	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
5565
5566	/**
5567	* Check if an SVM exception intercept is set.
5568	*/
5569	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) \
5570	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmXcptInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uVector)))
5571
5572	/**
5573	* Invokes the SVM \#VMEXIT handler for the nested-guest.
5574	*/
5575	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
5576	do { return iemSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2)); } while (0)
5577
5578	/**
5579	* Invokes the 'MOV CRx' SVM \#VMEXIT handler after constructing the
5580	* corresponding decode assist information.
5581	*/
5582	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) \
5583	do \
5584	{ \
5585	uint64_t uExitInfo1; \
5586	if ( IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmDecodeAssists \
5587	&& (a_enmAccessCrX) == IEMACCESSCRX_MOV_CRX) \
5588	uExitInfo1 = SVM_EXIT1_MOV_CRX_MASK \| ((a_iGReg) & 7); \
5589	else \
5590	uExitInfo1 = 0; \
5591	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, uExitInfo1, 0); \
5592	} while (0)
5593
5594	/** Check and handles SVM nested-guest instruction intercept and updates
5595	* NRIP if needed.
5596	*/
5597	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
5598	do \
5599	{ \
5600	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept)) \
5601	{ \
5602	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
5603	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2); \
5604	} \
5605	} while (0)
5606
5607	/** Checks and handles SVM nested-guest CR0 read intercept. */
5608	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
5609	do \
5610	{ \
5611	if (!IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, 0)) \
5612	{ /* probably likely */ } \
5613	else \
5614	{ \
5615	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
5616	IEM_SVM_VMEXIT_RET(a_pVCpu, SVM_EXIT_READ_CR0, a_uExitInfo1, a_uExitInfo2); \
5617	} \
5618	} while (0)
5619
5620	/**
5621	* Updates the NextRIP (NRI) field in the nested-guest VMCB.
5622	*/
5623	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) \
5624	do { \
5625	if (IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmNextRipSave) \
5626	CPUMGuestSvmUpdateNRip(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_cbInstr)); \
5627	} while (0)
5628
5629	#else
5630	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) (false)
5631	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
5632	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
5633	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
5634	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
5635	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) (false)
5636	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { return VERR_SVM_IPE_1; } while (0)
5637	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) do { return VERR_SVM_IPE_1; } while (0)
5638	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, \
5639	a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
5640	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
5641	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) do { } while (0)
5642
5643	#endif
5644
5645	/** @} */
5646
5647	uint32_t iemCalcExecDbgFlagsSlow(PVMCPUCC pVCpu);
5648	VBOXSTRICTRC iemExecInjectPendingTrap(PVMCPUCC pVCpu);
5649
5650
5651	/**
5652	* Selector descriptor table entry as fetched by iemMemFetchSelDesc.
5653	*/
5654	typedef union IEMSELDESC
5655	{
5656	/** The legacy view. */
5657	X86DESC Legacy;
5658	/** The long mode view. */
5659	X86DESC64 Long;
5660	} IEMSELDESC;
5661	/** Pointer to a selector descriptor table entry. */
5662	typedef IEMSELDESC *PIEMSELDESC;
5663
5664	/** @name Raising Exceptions.
5665	* @{ */
5666	VBOXSTRICTRC iemTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, uint32_t uNextEip, uint32_t fFlags,
5667	uint16_t uErr, uint64_t uCr2, RTSEL SelTSS, PIEMSELDESC pNewDescTSS) RT_NOEXCEPT;
5668
5669	VBOXSTRICTRC iemRaiseXcptOrInt(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags,
5670	uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
5671	#ifdef IEM_WITH_SETJMP
5672	DECL_NO_RETURN(void) iemRaiseXcptOrIntJmp(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector,
5673	uint32_t fFlags, uint16_t uErr, uint64_t uCr2) IEM_NOEXCEPT_MAY_LONGJMP;
5674	#endif
5675	VBOXSTRICTRC iemRaiseDivideError(PVMCPUCC pVCpu) RT_NOEXCEPT;
5676	#ifdef IEM_WITH_SETJMP
5677	DECL_NO_RETURN(void) iemRaiseDivideErrorJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5678	#endif
5679	VBOXSTRICTRC iemRaiseDebugException(PVMCPUCC pVCpu) RT_NOEXCEPT;
5680	VBOXSTRICTRC iemRaiseBoundRangeExceeded(PVMCPUCC pVCpu) RT_NOEXCEPT;
5681	VBOXSTRICTRC iemRaiseUndefinedOpcode(PVMCPUCC pVCpu) RT_NOEXCEPT;
5682	#ifdef IEM_WITH_SETJMP
5683	DECL_NO_RETURN(void) iemRaiseUndefinedOpcodeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5684	#endif
5685	VBOXSTRICTRC iemRaiseDeviceNotAvailable(PVMCPUCC pVCpu) RT_NOEXCEPT;
5686	#ifdef IEM_WITH_SETJMP
5687	DECL_NO_RETURN(void) iemRaiseDeviceNotAvailableJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5688	#endif
5689	VBOXSTRICTRC iemRaiseTaskSwitchFaultWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5690	VBOXSTRICTRC iemRaiseTaskSwitchFaultCurrentTSS(PVMCPUCC pVCpu) RT_NOEXCEPT;
5691	VBOXSTRICTRC iemRaiseTaskSwitchFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
5692	VBOXSTRICTRC iemRaiseTaskSwitchFaultBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5693	/VBOXSTRICTRC iemRaiseSelectorNotPresent(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;/
5694	VBOXSTRICTRC iemRaiseSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5695	VBOXSTRICTRC iemRaiseSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5696	VBOXSTRICTRC iemRaiseStackSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5697	VBOXSTRICTRC iemRaiseStackSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5698	VBOXSTRICTRC iemRaiseGeneralProtectionFault(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
5699	VBOXSTRICTRC iemRaiseGeneralProtectionFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
5700	#ifdef IEM_WITH_SETJMP
5701	DECL_NO_RETURN(void) iemRaiseGeneralProtectionFault0Jmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5702	#endif
5703	VBOXSTRICTRC iemRaiseGeneralProtectionFaultBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
5704	VBOXSTRICTRC iemRaiseNotCanonical(PVMCPUCC pVCpu) RT_NOEXCEPT;
5705	VBOXSTRICTRC iemRaiseSelectorBounds(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
5706	#ifdef IEM_WITH_SETJMP
5707	DECL_NO_RETURN(void) iemRaiseSelectorBoundsJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
5708	#endif
5709	VBOXSTRICTRC iemRaiseSelectorBoundsBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
5710	#ifdef IEM_WITH_SETJMP
5711	DECL_NO_RETURN(void) iemRaiseSelectorBoundsBySelectorJmp(PVMCPUCC pVCpu, RTSEL Sel) IEM_NOEXCEPT_MAY_LONGJMP;
5712	#endif
5713	VBOXSTRICTRC iemRaiseSelectorInvalidAccess(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
5714	#ifdef IEM_WITH_SETJMP
5715	DECL_NO_RETURN(void) iemRaiseSelectorInvalidAccessJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
5716	#endif
5717	VBOXSTRICTRC iemRaisePageFault(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) RT_NOEXCEPT;
5718	#ifdef IEM_WITH_SETJMP
5719	DECL_NO_RETURN(void) iemRaisePageFaultJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) IEM_NOEXCEPT_MAY_LONGJMP;
5720	#endif
5721	VBOXSTRICTRC iemRaiseMathFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
5722	#ifdef IEM_WITH_SETJMP
5723	DECL_NO_RETURN(void) iemRaiseMathFaultJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5724	#endif
5725	VBOXSTRICTRC iemRaiseAlignmentCheckException(PVMCPUCC pVCpu) RT_NOEXCEPT;
5726	#ifdef IEM_WITH_SETJMP
5727	DECL_NO_RETURN(void) iemRaiseAlignmentCheckExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5728	#endif
5729	VBOXSTRICTRC iemRaiseSimdFpException(PVMCPUCC pVCpu) RT_NOEXCEPT;
5730	#ifdef IEM_WITH_SETJMP
5731	DECL_NO_RETURN(void) iemRaiseSimdFpExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5732	#endif
5733
5734	void iemLogSyscallRealModeInt(PVMCPUCC pVCpu, uint8_t u8Vector, uint8_t cbInstr);
5735	void iemLogSyscallProtModeInt(PVMCPUCC pVCpu, uint8_t u8Vector, uint8_t cbInstr);
5736
5737	IEM_CIMPL_DEF_0(iemCImplRaiseDivideError);
5738	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidLockPrefix);
5739	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidOpcode);
5740
5741	/**
5742	* Macro for calling iemCImplRaiseDivideError().
5743	*
5744	* This is for things that will _always_ decode to an \#DE, taking the
5745	* recompiler into consideration and everything.
5746	*
5747	* @return Strict VBox status code.
5748	*/
5749	#define IEMOP_RAISE_DIVIDE_ERROR_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseDivideError)
5750
5751	/**
5752	* Macro for calling iemCImplRaiseInvalidLockPrefix().
5753	*
5754	* This is for things that will _always_ decode to an \#UD, taking the
5755	* recompiler into consideration and everything.
5756	*
5757	* @return Strict VBox status code.
5758	*/
5759	#define IEMOP_RAISE_INVALID_LOCK_PREFIX_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidLockPrefix)
5760
5761	/**
5762	* Macro for calling iemCImplRaiseInvalidOpcode() for decode/static \#UDs.
5763	*
5764	* This is for things that will _always_ decode to an \#UD, taking the
5765	* recompiler into consideration and everything.
5766	*
5767	* @return Strict VBox status code.
5768	*/
5769	#define IEMOP_RAISE_INVALID_OPCODE_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidOpcode)
5770
5771	/**
5772	* Macro for calling iemCImplRaiseInvalidOpcode() for runtime-style \#UDs.
5773	*
5774	* Using this macro means you've got _buggy_ _code_ and are doing things that
5775	* belongs exclusively in IEMAllCImpl.cpp during decoding.
5776	*
5777	* @return Strict VBox status code.
5778	* @see IEMOP_RAISE_INVALID_OPCODE_RET
5779	*/
5780	#define IEMOP_RAISE_INVALID_OPCODE_RUNTIME_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidOpcode)
5781
5782	/** @} */
5783
5784	/** @name Register Access.
5785	* @{ */
5786	VBOXSTRICTRC iemRegRipRelativeJumpS8AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int8_t offNextInstr,
5787	IEMMODE enmEffOpSize) RT_NOEXCEPT;
5788	VBOXSTRICTRC iemRegRipRelativeJumpS16AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int16_t offNextInstr) RT_NOEXCEPT;
5789	VBOXSTRICTRC iemRegRipRelativeJumpS32AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int32_t offNextInstr,
5790	IEMMODE enmEffOpSize) RT_NOEXCEPT;
5791	/** @} */
5792
5793	/** @name FPU access and helpers.
5794	* @{ */
5795	void iemFpuPushResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
5796	void iemFpuPushResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5797	void iemFpuPushResultTwo(PVMCPUCC pVCpu, PIEMFPURESULTTWO pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
5798	void iemFpuStoreResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
5799	void iemFpuStoreResultThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
5800	void iemFpuStoreResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
5801	uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5802	void iemFpuStoreResultWithMemOpThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
5803	uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5804	void iemFpuUpdateOpcodeAndIp(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5805	void iemFpuUpdateFSW(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
5806	void iemFpuUpdateFSWThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
5807	void iemFpuUpdateFSWWithMemOp(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5808	void iemFpuUpdateFSWThenPopPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
5809	void iemFpuUpdateFSWWithMemOpThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5810	void iemFpuStackUnderflow(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
5811	void iemFpuStackUnderflowWithMemOp(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5812	void iemFpuStackUnderflowThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
5813	void iemFpuStackUnderflowWithMemOpThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5814	void iemFpuStackUnderflowThenPopPop(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5815	void iemFpuStackPushUnderflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5816	void iemFpuStackPushUnderflowTwo(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5817	void iemFpuStackPushOverflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
5818	void iemFpuStackPushOverflowWithMemOp(PVMCPUCC pVCpu, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
5819	/** @} */
5820
5821	/** @name SSE+AVX SIMD access and helpers.
5822	* @{ */
5823	void iemSseUpdateMxcsr(PVMCPUCC pVCpu, uint32_t fMxcsr) RT_NOEXCEPT;
5824	/** @} */
5825
5826	/** @name Memory access.
5827	* @{ */
5828
5829	/** Report a \#GP instead of \#AC and do not restrict to ring-3 */
5830	#define IEM_MEMMAP_F_ALIGN_GP RT_BIT_32(16)
5831	/** SSE access that should report a \#GP instead of \#AC, unless MXCSR.MM=1
5832	* when it works like normal \#AC. Always used with IEM_MEMMAP_F_ALIGN_GP. */
5833	#define IEM_MEMMAP_F_ALIGN_SSE RT_BIT_32(17)
5834	/** If \#AC is applicable, raise it. Always used with IEM_MEMMAP_F_ALIGN_GP.
5835	* Users include FXSAVE & FXRSTOR. */
5836	#define IEM_MEMMAP_F_ALIGN_GP_OR_AC RT_BIT_32(18)
5837
5838	VBOXSTRICTRC iemMemMap(PVMCPUCC pVCpu, void *ppvMem, uint8_t pbUnmapInfo, size_t cbMem, uint8_t iSegReg, RTGCPTR GCPtrMem,
5839	uint32_t fAccess, uint32_t uAlignCtl) RT_NOEXCEPT;
5840	VBOXSTRICTRC iemMemCommitAndUnmap(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5841	#ifndef IN_RING3
5842	VBOXSTRICTRC iemMemCommitAndUnmapPostponeTroubleToR3(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5843	#endif
5844	void iemMemRollbackAndUnmap(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
5845	void iemMemRollback(PVMCPUCC pVCpu) RT_NOEXCEPT;
5846	VBOXSTRICTRC iemMemApplySegment(PVMCPUCC pVCpu, uint32_t fAccess, uint8_t iSegReg, size_t cbMem, PRTGCPTR pGCPtrMem) RT_NOEXCEPT;
5847	VBOXSTRICTRC iemMemMarkSelDescAccessed(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
5848	VBOXSTRICTRC iemMemPageTranslateAndCheckAccess(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t cbAccess, uint32_t fAccess, PRTGCPHYS pGCPhysMem) RT_NOEXCEPT;
5849
5850	void iemOpcodeFlushLight(PVMCPUCC pVCpu, uint8_t cbInstr);
5851	void iemOpcodeFlushHeavy(PVMCPUCC pVCpu, uint8_t cbInstr);
5852	#ifdef IEM_WITH_CODE_TLB
5853	void iemOpcodeFetchBytesJmp(PVMCPUCC pVCpu, size_t cbDst, void *pvDst) IEM_NOEXCEPT_MAY_LONGJMP;
5854	#else
5855	VBOXSTRICTRC iemOpcodeFetchMoreBytes(PVMCPUCC pVCpu, size_t cbMin) RT_NOEXCEPT;
5856	#endif
5857	#ifdef IEM_WITH_SETJMP
5858	uint8_t iemOpcodeGetNextU8SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5859	uint16_t iemOpcodeGetNextU16SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5860	uint32_t iemOpcodeGetNextU32SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5861	uint64_t iemOpcodeGetNextU64SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
5862	#else
5863	VBOXSTRICTRC iemOpcodeGetNextU8Slow(PVMCPUCC pVCpu, uint8_t *pb) RT_NOEXCEPT;
5864	VBOXSTRICTRC iemOpcodeGetNextS8SxU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
5865	VBOXSTRICTRC iemOpcodeGetNextS8SxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
5866	VBOXSTRICTRC iemOpcodeGetNextS8SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5867	VBOXSTRICTRC iemOpcodeGetNextU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
5868	VBOXSTRICTRC iemOpcodeGetNextU16ZxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
5869	VBOXSTRICTRC iemOpcodeGetNextU16ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5870	VBOXSTRICTRC iemOpcodeGetNextU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
5871	VBOXSTRICTRC iemOpcodeGetNextU32ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5872	VBOXSTRICTRC iemOpcodeGetNextS32SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5873	VBOXSTRICTRC iemOpcodeGetNextU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
5874	#endif
5875
5876	VBOXSTRICTRC iemMemFetchDataU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5877	VBOXSTRICTRC iemMemFetchDataU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5878	VBOXSTRICTRC iemMemFetchDataU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5879	VBOXSTRICTRC iemMemFetchDataU32_ZX_U64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5880	VBOXSTRICTRC iemMemFetchDataU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5881	VBOXSTRICTRC iemMemFetchDataU64AlignedU128(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5882	VBOXSTRICTRC iemMemFetchDataR80(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5883	VBOXSTRICTRC iemMemFetchDataD80(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5884	VBOXSTRICTRC iemMemFetchDataU128(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5885	VBOXSTRICTRC iemMemFetchDataU128NoAc(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5886	VBOXSTRICTRC iemMemFetchDataU128AlignedSse(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5887	VBOXSTRICTRC iemMemFetchDataU256(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5888	VBOXSTRICTRC iemMemFetchDataU256NoAc(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5889	VBOXSTRICTRC iemMemFetchDataU256AlignedAvx(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5890	VBOXSTRICTRC iemMemFetchDataXdtr(PVMCPUCC pVCpu, uint16_t *pcbLimit, PRTGCPTR pGCPtrBase, uint8_t iSegReg,
5891	RTGCPTR GCPtrMem, IEMMODE enmOpSize) RT_NOEXCEPT;
5892	#ifdef IEM_WITH_SETJMP
5893	uint8_t iemMemFetchDataU8SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5894	uint16_t iemMemFetchDataU16SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5895	uint32_t iemMemFetchDataU32SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5896	uint32_t iemMemFlatFetchDataU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5897	uint64_t iemMemFetchDataU64SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5898	uint64_t iemMemFetchDataU64AlignedU128SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5899	void iemMemFetchDataR80SafeJmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5900	void iemMemFetchDataD80SafeJmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5901	void iemMemFetchDataU128SafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5902	void iemMemFetchDataU128NoAcSafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5903	void iemMemFetchDataU128AlignedSseSafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5904	void iemMemFetchDataU256SafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5905	void iemMemFetchDataU256NoAcSafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5906	void iemMemFetchDataU256AlignedAvxSafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5907	# if 0 /* these are inlined now */
5908	uint8_t iemMemFetchDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5909	uint16_t iemMemFetchDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5910	uint32_t iemMemFetchDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5911	uint32_t iemMemFlatFetchDataU32Jmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5912	uint64_t iemMemFetchDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5913	uint64_t iemMemFetchDataU64AlignedU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5914	void iemMemFetchDataR80Jmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5915	void iemMemFetchDataD80Jmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5916	void iemMemFetchDataU128Jmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5917	void iemMemFetchDataU128NoAcJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5918	void iemMemFetchDataU128AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5919	void iemMemFetchDataU256NoAcJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5920	void iemMemFetchDataU256AlignedAvxJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5921	# endif
5922	void iemMemFetchDataU256Jmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5923	#endif
5924
5925	VBOXSTRICTRC iemMemFetchSysU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5926	VBOXSTRICTRC iemMemFetchSysU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5927	VBOXSTRICTRC iemMemFetchSysU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5928	VBOXSTRICTRC iemMemFetchSysU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5929	VBOXSTRICTRC iemMemFetchSelDesc(PVMCPUCC pVCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt) RT_NOEXCEPT;
5930
5931	VBOXSTRICTRC iemMemStoreDataU8(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) RT_NOEXCEPT;
5932	VBOXSTRICTRC iemMemStoreDataU16(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) RT_NOEXCEPT;
5933	VBOXSTRICTRC iemMemStoreDataU32(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) RT_NOEXCEPT;
5934	VBOXSTRICTRC iemMemStoreDataU64(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) RT_NOEXCEPT;
5935	VBOXSTRICTRC iemMemStoreDataU128(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
5936	VBOXSTRICTRC iemMemStoreDataU128NoAc(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
5937	VBOXSTRICTRC iemMemStoreDataU128AlignedSse(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
5938	VBOXSTRICTRC iemMemStoreDataU256(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
5939	VBOXSTRICTRC iemMemStoreDataU256NoAc(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
5940	VBOXSTRICTRC iemMemStoreDataU256AlignedAvx(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
5941	VBOXSTRICTRC iemMemStoreDataXdtr(PVMCPUCC pVCpu, uint16_t cbLimit, RTGCPTR GCPtrBase, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
5942	#ifdef IEM_WITH_SETJMP
5943	void iemMemStoreDataU8SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
5944	void iemMemStoreDataU16SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
5945	void iemMemStoreDataU32SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
5946	void iemMemStoreDataU64SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
5947	void iemMemStoreDataU128SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5948	void iemMemStoreDataU128NoAcSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT128U pu128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5949	void iemMemStoreDataU128AlignedSseSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT128U pu128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5950	void iemMemStoreDataU256SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5951	void iemMemStoreDataU256NoAcSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5952	void iemMemStoreDataU256AlignedAvxSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5953	void iemMemStoreDataR80SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTFLOAT80U pr80Value) IEM_NOEXCEPT_MAY_LONGJMP;
5954	void iemMemStoreDataD80SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTPBCD80U pd80Value) IEM_NOEXCEPT_MAY_LONGJMP;
5955	#if 0
5956	void iemMemStoreDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
5957	void iemMemStoreDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
5958	void iemMemStoreDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
5959	void iemMemStoreDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
5960	void iemMemStoreDataU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5961	void iemMemStoreDataNoAcU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5962	void iemMemStoreDataU256NoAcJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5963	void iemMemStoreDataU256AlignedAvxJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5964	#endif
5965	void iemMemStoreDataU128AlignedSseJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
5966	void iemMemStoreDataU256Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
5967	#endif
5968
5969	#ifdef IEM_WITH_SETJMP
5970	uint8_t iemMemMapDataU8RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5971	uint8_t iemMemMapDataU8AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5972	uint8_t iemMemMapDataU8WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5973	uint8_t const iemMemMapDataU8RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5974	uint16_t iemMemMapDataU16RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5975	uint16_t iemMemMapDataU16AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5976	uint16_t iemMemMapDataU16WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5977	uint16_t const iemMemMapDataU16RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5978	uint32_t iemMemMapDataU32RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5979	uint32_t iemMemMapDataU32AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5980	uint32_t iemMemMapDataU32WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5981	uint32_t const iemMemMapDataU32RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5982	uint64_t iemMemMapDataU64RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5983	uint64_t iemMemMapDataU64AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5984	uint64_t iemMemMapDataU64WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5985	uint64_t const iemMemMapDataU64RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5986	PRTFLOAT80U iemMemMapDataR80RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5987	PRTFLOAT80U iemMemMapDataR80WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5988	PCRTFLOAT80U iemMemMapDataR80RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5989	PRTPBCD80U iemMemMapDataD80RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5990	PRTPBCD80U iemMemMapDataD80WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5991	PCRTPBCD80U iemMemMapDataD80RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5992	PRTUINT128U iemMemMapDataU128RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5993	PRTUINT128U iemMemMapDataU128AtSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5994	PRTUINT128U iemMemMapDataU128WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5995	PCRTUINT128U iemMemMapDataU128RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
5996
5997	void iemMemCommitAndUnmapJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5998	void iemMemCommitAndUnmapRwSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
5999	void iemMemCommitAndUnmapAtSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
6000	void iemMemCommitAndUnmapWoSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
6001	void iemMemCommitAndUnmapRoSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
6002	void iemMemRollbackAndUnmapWoSafe(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
6003	#endif
6004
6005	VBOXSTRICTRC iemMemStackPushBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
6006	void *ppvMem, uint8_t pbUnmapInfo, uint64_t *puNewRsp) RT_NOEXCEPT;
6007	VBOXSTRICTRC iemMemStackPushCommitSpecial(PVMCPUCC pVCpu, uint8_t bUnmapInfo, uint64_t uNewRsp) RT_NOEXCEPT;
6008	VBOXSTRICTRC iemMemStackPushU16(PVMCPUCC pVCpu, uint16_t u16Value) RT_NOEXCEPT;
6009	VBOXSTRICTRC iemMemStackPushU32(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
6010	VBOXSTRICTRC iemMemStackPushU64(PVMCPUCC pVCpu, uint64_t u64Value) RT_NOEXCEPT;
6011	VBOXSTRICTRC iemMemStackPushU16Ex(PVMCPUCC pVCpu, uint16_t u16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
6012	VBOXSTRICTRC iemMemStackPushU32Ex(PVMCPUCC pVCpu, uint32_t u32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
6013	VBOXSTRICTRC iemMemStackPushU64Ex(PVMCPUCC pVCpu, uint64_t u64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
6014	VBOXSTRICTRC iemMemStackPushU32SReg(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
6015	VBOXSTRICTRC iemMemStackPopBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
6016	void const *ppvMem, uint8_t pbUnmapInfo, uint64_t *puNewRsp) RT_NOEXCEPT;
6017	VBOXSTRICTRC iemMemStackPopContinueSpecial(PVMCPUCC pVCpu, size_t off, size_t cbMem,
6018	void const *ppvMem, uint8_t pbUnmapInfo, uint64_t uCurNewRsp) RT_NOEXCEPT;
6019	VBOXSTRICTRC iemMemStackPopDoneSpecial(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
6020	VBOXSTRICTRC iemMemStackPopU16(PVMCPUCC pVCpu, uint16_t *pu16Value) RT_NOEXCEPT;
6021	VBOXSTRICTRC iemMemStackPopU32(PVMCPUCC pVCpu, uint32_t *pu32Value) RT_NOEXCEPT;
6022	VBOXSTRICTRC iemMemStackPopU64(PVMCPUCC pVCpu, uint64_t *pu64Value) RT_NOEXCEPT;
6023	VBOXSTRICTRC iemMemStackPopU16Ex(PVMCPUCC pVCpu, uint16_t *pu16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
6024	VBOXSTRICTRC iemMemStackPopU32Ex(PVMCPUCC pVCpu, uint32_t *pu32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
6025	VBOXSTRICTRC iemMemStackPopU64Ex(PVMCPUCC pVCpu, uint64_t *pu64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
6026
6027	#ifdef IEM_WITH_SETJMP
6028	void iemMemStackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6029	void iemMemStackPushU32SafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6030	void iemMemStackPushU32SRegSafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6031	void iemMemStackPushU64SafeJmp(PVMCPUCC pVCpu, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6032	void iemMemStackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
6033	void iemMemStackPopGRegU32SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
6034	void iemMemStackPopGRegU64SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
6035
6036	void iemMemFlat32StackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6037	void iemMemFlat32StackPushU32SafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6038	void iemMemFlat32StackPushU32SRegSafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6039	void iemMemFlat32StackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
6040	void iemMemFlat32StackPopGRegU32SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
6041
6042	void iemMemFlat64StackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6043	void iemMemFlat64StackPushU64SafeJmp(PVMCPUCC pVCpu, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6044	void iemMemFlat64StackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
6045	void iemMemFlat64StackPopGRegU64SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
6046
6047	void iemMemStoreStackU16SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6048	void iemMemStoreStackU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6049	void iemMemStoreStackU32SRegSafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6050	void iemMemStoreStackU64SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6051
6052	uint16_t iemMemFetchStackU16SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6053	uint32_t iemMemFetchStackU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6054	uint64_t iemMemFetchStackU64SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6055
6056	#endif
6057
6058	/** @} */
6059
6060	/** @name IEMAllCImpl.cpp
6061	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/'
6062	* @{ */
6063	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem16, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6064	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem32, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6065	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem64, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6066	IEM_CIMPL_PROTO_0(iemCImpl_popa_16);
6067	IEM_CIMPL_PROTO_0(iemCImpl_popa_32);
6068	IEM_CIMPL_PROTO_0(iemCImpl_pusha_16);
6069	IEM_CIMPL_PROTO_0(iemCImpl_pusha_32);
6070	IEM_CIMPL_PROTO_1(iemCImpl_pushf, IEMMODE, enmEffOpSize);
6071	IEM_CIMPL_PROTO_1(iemCImpl_popf, IEMMODE, enmEffOpSize);
6072	IEM_CIMPL_PROTO_3(iemCImpl_FarJmp, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
6073	IEM_CIMPL_PROTO_3(iemCImpl_callf, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
6074	typedef IEM_CIMPL_DECL_TYPE_3(FNIEMCIMPLFARBRANCH, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
6075	typedef FNIEMCIMPLFARBRANCH *PFNIEMCIMPLFARBRANCH;
6076	IEM_CIMPL_PROTO_2(iemCImpl_retf, IEMMODE, enmEffOpSize, uint16_t, cbPop);
6077	IEM_CIMPL_PROTO_3(iemCImpl_enter, IEMMODE, enmEffOpSize, uint16_t, cbFrame, uint8_t, cParameters);
6078	IEM_CIMPL_PROTO_1(iemCImpl_leave, IEMMODE, enmEffOpSize);
6079	IEM_CIMPL_PROTO_2(iemCImpl_int, uint8_t, u8Int, IEMINT, enmInt);
6080	IEM_CIMPL_PROTO_1(iemCImpl_iret_real_v8086, IEMMODE, enmEffOpSize);
6081	IEM_CIMPL_PROTO_4(iemCImpl_iret_prot_v8086, uint32_t, uNewEip, uint16_t, uNewCs, uint32_t, uNewFlags, uint64_t, uNewRsp);
6082	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot_NestedTask, IEMMODE, enmEffOpSize);
6083	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot, IEMMODE, enmEffOpSize);
6084	IEM_CIMPL_PROTO_1(iemCImpl_iret_64bit, IEMMODE, enmEffOpSize);
6085	IEM_CIMPL_PROTO_1(iemCImpl_iret, IEMMODE, enmEffOpSize);
6086	IEM_CIMPL_PROTO_0(iemCImpl_loadall286);
6087	IEM_CIMPL_PROTO_0(iemCImpl_syscall);
6088	IEM_CIMPL_PROTO_1(iemCImpl_sysret, IEMMODE, enmEffOpSize);
6089	IEM_CIMPL_PROTO_0(iemCImpl_sysenter);
6090	IEM_CIMPL_PROTO_1(iemCImpl_sysexit, IEMMODE, enmEffOpSize);
6091	IEM_CIMPL_PROTO_2(iemCImpl_LoadSReg, uint8_t, iSegReg, uint16_t, uSel);
6092	IEM_CIMPL_PROTO_2(iemCImpl_load_SReg, uint8_t, iSegReg, uint16_t, uSel);
6093	IEM_CIMPL_PROTO_2(iemCImpl_pop_Sreg, uint8_t, iSegReg, IEMMODE, enmEffOpSize);
6094	IEM_CIMPL_PROTO_5(iemCImpl_load_SReg_Greg, uint16_t, uSel, uint64_t, offSeg, uint8_t, iSegReg, uint8_t, iGReg, IEMMODE, enmEffOpSize);
6095	IEM_CIMPL_PROTO_2(iemCImpl_VerX, uint16_t, uSel, bool, fWrite);
6096	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u64, uint64_t *, pu64Dst, uint16_t, uSel, bool, fIsLar);
6097	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u16, uint16_t *, pu16Dst, uint16_t, uSel, bool, fIsLar);
6098	IEM_CIMPL_PROTO_3(iemCImpl_lgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
6099	IEM_CIMPL_PROTO_2(iemCImpl_sgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6100	IEM_CIMPL_PROTO_3(iemCImpl_lidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
6101	IEM_CIMPL_PROTO_2(iemCImpl_sidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6102	IEM_CIMPL_PROTO_1(iemCImpl_lldt, uint16_t, uNewLdt);
6103	IEM_CIMPL_PROTO_2(iemCImpl_sldt_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
6104	IEM_CIMPL_PROTO_2(iemCImpl_sldt_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6105	IEM_CIMPL_PROTO_1(iemCImpl_ltr, uint16_t, uNewTr);
6106	IEM_CIMPL_PROTO_2(iemCImpl_str_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
6107	IEM_CIMPL_PROTO_2(iemCImpl_str_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6108	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Cd, uint8_t, iGReg, uint8_t, iCrReg);
6109	IEM_CIMPL_PROTO_2(iemCImpl_smsw_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
6110	IEM_CIMPL_PROTO_2(iemCImpl_smsw_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6111	IEM_CIMPL_PROTO_4(iemCImpl_load_CrX, uint8_t, iCrReg, uint64_t, uNewCrX, IEMACCESSCRX, enmAccessCrX, uint8_t, iGReg);
6112	IEM_CIMPL_PROTO_2(iemCImpl_mov_Cd_Rd, uint8_t, iCrReg, uint8_t, iGReg);
6113	IEM_CIMPL_PROTO_2(iemCImpl_lmsw, uint16_t, u16NewMsw, RTGCPTR, GCPtrEffDst);
6114	IEM_CIMPL_PROTO_0(iemCImpl_clts);
6115	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Dd, uint8_t, iGReg, uint8_t, iDrReg);
6116	IEM_CIMPL_PROTO_2(iemCImpl_mov_Dd_Rd, uint8_t, iDrReg, uint8_t, iGReg);
6117	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Td, uint8_t, iGReg, uint8_t, iTrReg);
6118	IEM_CIMPL_PROTO_2(iemCImpl_mov_Td_Rd, uint8_t, iTrReg, uint8_t, iGReg);
6119	IEM_CIMPL_PROTO_1(iemCImpl_invlpg, RTGCPTR, GCPtrPage);
6120	IEM_CIMPL_PROTO_3(iemCImpl_invpcid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvpcidDesc, uint64_t, uInvpcidType);
6121	IEM_CIMPL_PROTO_0(iemCImpl_invd);
6122	IEM_CIMPL_PROTO_0(iemCImpl_wbinvd);
6123	IEM_CIMPL_PROTO_0(iemCImpl_rsm);
6124	IEM_CIMPL_PROTO_0(iemCImpl_rdtsc);
6125	IEM_CIMPL_PROTO_0(iemCImpl_rdtscp);
6126	IEM_CIMPL_PROTO_0(iemCImpl_rdpmc);
6127	IEM_CIMPL_PROTO_0(iemCImpl_rdmsr);
6128	IEM_CIMPL_PROTO_0(iemCImpl_wrmsr);
6129	IEM_CIMPL_PROTO_3(iemCImpl_in, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
6130	IEM_CIMPL_PROTO_2(iemCImpl_in_eAX_DX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
6131	IEM_CIMPL_PROTO_3(iemCImpl_out, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
6132	IEM_CIMPL_PROTO_2(iemCImpl_out_DX_eAX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
6133	IEM_CIMPL_PROTO_0(iemCImpl_cli);
6134	IEM_CIMPL_PROTO_0(iemCImpl_sti);
6135	IEM_CIMPL_PROTO_0(iemCImpl_hlt);
6136	IEM_CIMPL_PROTO_1(iemCImpl_monitor, uint8_t, iEffSeg);
6137	IEM_CIMPL_PROTO_0(iemCImpl_mwait);
6138	IEM_CIMPL_PROTO_0(iemCImpl_swapgs);
6139	IEM_CIMPL_PROTO_0(iemCImpl_cpuid);
6140	IEM_CIMPL_PROTO_1(iemCImpl_aad, uint8_t, bImm);
6141	IEM_CIMPL_PROTO_1(iemCImpl_aam, uint8_t, bImm);
6142	IEM_CIMPL_PROTO_0(iemCImpl_daa);
6143	IEM_CIMPL_PROTO_0(iemCImpl_das);
6144	IEM_CIMPL_PROTO_0(iemCImpl_aaa);
6145	IEM_CIMPL_PROTO_0(iemCImpl_aas);
6146	IEM_CIMPL_PROTO_3(iemCImpl_bound_16, int16_t, idxArray, int16_t, idxLowerBound, int16_t, idxUpperBound);
6147	IEM_CIMPL_PROTO_3(iemCImpl_bound_32, int32_t, idxArray, int32_t, idxLowerBound, int32_t, idxUpperBound);
6148	IEM_CIMPL_PROTO_0(iemCImpl_xgetbv);
6149	IEM_CIMPL_PROTO_0(iemCImpl_xsetbv);
6150	IEM_CIMPL_PROTO_5(iemCImpl_cmpxchg16b_fallback_rendezvous, PRTUINT128U, pu128Dst, PRTUINT128U, pu128RaxRdx,
6151	PRTUINT128U, pu128RbxRcx, uint32_t *, pEFlags, uint8_t, bUnmapInfo);
6152	IEM_CIMPL_PROTO_2(iemCImpl_clflush_clflushopt, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
6153	IEM_CIMPL_PROTO_1(iemCImpl_finit, bool, fCheckXcpts);
6154	IEM_CIMPL_PROTO_3(iemCImpl_fxsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
6155	IEM_CIMPL_PROTO_3(iemCImpl_fxrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
6156	IEM_CIMPL_PROTO_3(iemCImpl_xsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
6157	IEM_CIMPL_PROTO_3(iemCImpl_xrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
6158	IEM_CIMPL_PROTO_2(iemCImpl_stmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
6159	IEM_CIMPL_PROTO_2(iemCImpl_vstmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
6160	IEM_CIMPL_PROTO_2(iemCImpl_ldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
6161	IEM_CIMPL_PROTO_3(iemCImpl_fnstenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6162	IEM_CIMPL_PROTO_3(iemCImpl_fnsave, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6163	IEM_CIMPL_PROTO_3(iemCImpl_fldenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6164	IEM_CIMPL_PROTO_3(iemCImpl_frstor, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6165	IEM_CIMPL_PROTO_1(iemCImpl_fldcw, uint16_t, u16Fcw);
6166	IEM_CIMPL_PROTO_2(iemCImpl_fxch_underflow, uint8_t, iStReg, uint16_t, uFpuOpcode);
6167	IEM_CIMPL_PROTO_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, bool, fUCmp, uint32_t, uPopAndFpuOpcode);
6168	IEM_CIMPL_PROTO_2(iemCImpl_rdseed, uint8_t, iReg, IEMMODE, enmEffOpSize);
6169	IEM_CIMPL_PROTO_2(iemCImpl_rdrand, uint8_t, iReg, IEMMODE, enmEffOpSize);
6170	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovps_load_u128, uint8_t, iXRegDst, uint8_t, iXRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6171	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovps_load_u256, uint8_t, iYRegDst, uint8_t, iYRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6172	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovps_store_u128, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iXRegMsk, uint8_t, iXRegSrc);
6173	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovps_store_u256, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iYRegMsk, uint8_t, iYRegSrc);
6174	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovd_load_u128, uint8_t, iXRegDst, uint8_t, iXRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6175	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovd_load_u256, uint8_t, iYRegDst, uint8_t, iYRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6176	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovd_store_u128, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iXRegMsk, uint8_t, iXRegSrc);
6177	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovd_store_u256, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iYRegMsk, uint8_t, iYRegSrc);
6178	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovpd_load_u128, uint8_t, iXRegDst, uint8_t, iXRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6179	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovpd_load_u256, uint8_t, iYRegDst, uint8_t, iYRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6180	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovpd_store_u128, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iXRegMsk, uint8_t, iXRegSrc);
6181	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovpd_store_u256, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iYRegMsk, uint8_t, iYRegSrc);
6182	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovq_load_u128, uint8_t, iXRegDst, uint8_t, iXRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6183	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovq_load_u256, uint8_t, iYRegDst, uint8_t, iYRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6184	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovq_store_u128, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iXRegMsk, uint8_t, iXRegSrc);
6185	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovq_store_u256, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iYRegMsk, uint8_t, iYRegSrc);
6186
6187	/** @} */
6188
6189	/** @name IEMAllCImplStrInstr.cpp.h
6190	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/' -e 's/RT_CONCAT4(//' \
6191	* -e 's/,ADDR_SIZE)/64/g' -e 's/,OP_SIZE,/64/g' -e 's/,OP_rAX,/rax/g' IEMAllCImplStrInstr.cpp.h
6192	* @{ */
6193	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr16, uint8_t, iEffSeg);
6194	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr16, uint8_t, iEffSeg);
6195	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m16);
6196	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m16);
6197	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr16, uint8_t, iEffSeg);
6198	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m16);
6199	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m16, int8_t, iEffSeg);
6200	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr16, bool, fIoChecked);
6201	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr16, bool, fIoChecked);
6202	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6203	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6204
6205	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr16, uint8_t, iEffSeg);
6206	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr16, uint8_t, iEffSeg);
6207	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m16);
6208	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m16);
6209	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr16, uint8_t, iEffSeg);
6210	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m16);
6211	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m16, int8_t, iEffSeg);
6212	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr16, bool, fIoChecked);
6213	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr16, bool, fIoChecked);
6214	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6215	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6216
6217	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr16, uint8_t, iEffSeg);
6218	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr16, uint8_t, iEffSeg);
6219	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m16);
6220	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m16);
6221	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr16, uint8_t, iEffSeg);
6222	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m16);
6223	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m16, int8_t, iEffSeg);
6224	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr16, bool, fIoChecked);
6225	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr16, bool, fIoChecked);
6226	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6227	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6228
6229
6230	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr32, uint8_t, iEffSeg);
6231	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr32, uint8_t, iEffSeg);
6232	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m32);
6233	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m32);
6234	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr32, uint8_t, iEffSeg);
6235	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m32);
6236	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m32, int8_t, iEffSeg);
6237	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr32, bool, fIoChecked);
6238	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr32, bool, fIoChecked);
6239	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6240	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6241
6242	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr32, uint8_t, iEffSeg);
6243	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr32, uint8_t, iEffSeg);
6244	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m32);
6245	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m32);
6246	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr32, uint8_t, iEffSeg);
6247	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m32);
6248	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m32, int8_t, iEffSeg);
6249	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr32, bool, fIoChecked);
6250	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr32, bool, fIoChecked);
6251	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6252	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6253
6254	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr32, uint8_t, iEffSeg);
6255	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr32, uint8_t, iEffSeg);
6256	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m32);
6257	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m32);
6258	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr32, uint8_t, iEffSeg);
6259	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m32);
6260	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m32, int8_t, iEffSeg);
6261	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr32, bool, fIoChecked);
6262	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr32, bool, fIoChecked);
6263	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6264	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6265
6266	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr32, uint8_t, iEffSeg);
6267	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr32, uint8_t, iEffSeg);
6268	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m32);
6269	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m32);
6270	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr32, uint8_t, iEffSeg);
6271	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m32);
6272	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m32, int8_t, iEffSeg);
6273	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr32, bool, fIoChecked);
6274	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr32, bool, fIoChecked);
6275	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6276	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6277
6278
6279	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr64, uint8_t, iEffSeg);
6280	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr64, uint8_t, iEffSeg);
6281	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m64);
6282	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m64);
6283	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr64, uint8_t, iEffSeg);
6284	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m64);
6285	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m64, int8_t, iEffSeg);
6286	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr64, bool, fIoChecked);
6287	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr64, bool, fIoChecked);
6288	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6289	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6290
6291	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr64, uint8_t, iEffSeg);
6292	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr64, uint8_t, iEffSeg);
6293	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m64);
6294	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m64);
6295	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr64, uint8_t, iEffSeg);
6296	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m64);
6297	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m64, int8_t, iEffSeg);
6298	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr64, bool, fIoChecked);
6299	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr64, bool, fIoChecked);
6300	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6301	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6302
6303	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr64, uint8_t, iEffSeg);
6304	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr64, uint8_t, iEffSeg);
6305	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m64);
6306	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m64);
6307	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr64, uint8_t, iEffSeg);
6308	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m64);
6309	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m64, int8_t, iEffSeg);
6310	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr64, bool, fIoChecked);
6311	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr64, bool, fIoChecked);
6312	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6313	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6314
6315	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr64, uint8_t, iEffSeg);
6316	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr64, uint8_t, iEffSeg);
6317	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m64);
6318	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m64);
6319	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr64, uint8_t, iEffSeg);
6320	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m64);
6321	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m64, int8_t, iEffSeg);
6322	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr64, bool, fIoChecked);
6323	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr64, bool, fIoChecked);
6324	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6325	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6326	/** @} */
6327
6328	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
6329	VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT;
6330	VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT;
6331	VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT;
6332	VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT;
6333	VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT;
6334	VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
6335	VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALKFAST pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT;
6336	VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT;
6337	VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT;
6338	VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
6339	bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT;
6340	VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
6341	bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT;
6342	VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6343	VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6344	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6345	VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6346	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6347	VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6348	VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT;
6349	VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
6350	RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT;
6351	VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT;
6352	VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT;
6353	VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT;
6354	uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT;
6355	void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT;
6356	VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
6357	uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT;
6358	bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT;
6359	IEM_CIMPL_PROTO_0(iemCImpl_vmxoff);
6360	IEM_CIMPL_PROTO_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon);
6361	IEM_CIMPL_PROTO_0(iemCImpl_vmlaunch);
6362	IEM_CIMPL_PROTO_0(iemCImpl_vmresume);
6363	IEM_CIMPL_PROTO_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
6364	IEM_CIMPL_PROTO_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
6365	IEM_CIMPL_PROTO_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
6366	IEM_CIMPL_PROTO_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField);
6367	IEM_CIMPL_PROTO_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField);
6368	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField);
6369	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg32, uint64_t *, pu32Dst, uint32_t, u32VmcsField);
6370	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField);
6371	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField);
6372	IEM_CIMPL_PROTO_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType);
6373	IEM_CIMPL_PROTO_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType);
6374	IEM_CIMPL_PROTO_0(iemCImpl_vmx_pause);
6375	#endif
6376
6377	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
6378	VBOXSTRICTRC iemSvmVmexit(PVMCPUCC pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2) RT_NOEXCEPT;
6379	VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr, uint64_t uCr2) RT_NOEXCEPT;
6380	VBOXSTRICTRC iemSvmHandleIOIntercept(PVMCPUCC pVCpu, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
6381	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, uint8_t cbInstr) RT_NOEXCEPT;
6382	VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPUCC pVCpu, uint32_t idMsr, bool fWrite, uint8_t cbInstr) RT_NOEXCEPT;
6383	IEM_CIMPL_PROTO_0(iemCImpl_vmrun);
6384	IEM_CIMPL_PROTO_0(iemCImpl_vmload);
6385	IEM_CIMPL_PROTO_0(iemCImpl_vmsave);
6386	IEM_CIMPL_PROTO_0(iemCImpl_clgi);
6387	IEM_CIMPL_PROTO_0(iemCImpl_stgi);
6388	IEM_CIMPL_PROTO_0(iemCImpl_invlpga);
6389	IEM_CIMPL_PROTO_0(iemCImpl_skinit);
6390	IEM_CIMPL_PROTO_0(iemCImpl_svm_pause);
6391	#endif
6392
6393	IEM_CIMPL_PROTO_0(iemCImpl_vmcall); /* vmx */
6394	IEM_CIMPL_PROTO_0(iemCImpl_vmmcall); /* svm */
6395	IEM_CIMPL_PROTO_1(iemCImpl_Hypercall, uint16_t, uDisOpcode); /* both */
6396
6397	extern const PFNIEMOP g_apfnIemInterpretOnlyOneByteMap[256];
6398	extern const PFNIEMOP g_apfnIemInterpretOnlyTwoByteMap[1024];
6399	extern const PFNIEMOP g_apfnIemInterpretOnlyThreeByte0f3a[1024];
6400	extern const PFNIEMOP g_apfnIemInterpretOnlyThreeByte0f38[1024];
6401	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap1[1024];
6402	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap2[1024];
6403	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap3[1024];
6404
6405	/*
6406	* Recompiler related stuff.
6407	*/
6408	extern const PFNIEMOP g_apfnIemThreadedRecompilerOneByteMap[256];
6409	extern const PFNIEMOP g_apfnIemThreadedRecompilerTwoByteMap[1024];
6410	extern const PFNIEMOP g_apfnIemThreadedRecompilerThreeByte0f3a[1024];
6411	extern const PFNIEMOP g_apfnIemThreadedRecompilerThreeByte0f38[1024];
6412	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap1[1024];
6413	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap2[1024];
6414	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap3[1024];
6415
6416	DECLCALLBACK(int) iemTbInit(PVMCC pVM, uint32_t cInitialTbs, uint32_t cMaxTbs,
6417	uint64_t cbInitialExec, uint64_t cbMaxExec, uint32_t cbChunkExec);
6418	void iemThreadedTbObsolete(PVMCPUCC pVCpu, PIEMTB pTb, bool fSafeToFree);
6419	DECLHIDDEN(void) iemTbAllocatorFree(PVMCPUCC pVCpu, PIEMTB pTb);
6420	void iemTbAllocatorProcessDelayedFrees(PVMCPUCC pVCpu, PIEMTBALLOCATOR pTbAllocator);
6421	void iemTbAllocatorFreeupNativeSpace(PVMCPUCC pVCpu, uint32_t cNeededInstrs);
6422	DECLHIDDEN(const char ) iemTbFlagsToString(uint32_t fFlags, char pszBuf, size_t cbBuf) RT_NOEXCEPT;
6423	DECLHIDDEN(void) iemThreadedDisassembleTb(PCIEMTB pTb, PCDBGFINFOHLP pHlp) RT_NOEXCEPT;
6424
6425
6426	/** @todo FNIEMTHREADEDFUNC and friends may need more work... */
6427	#if defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
6428	typedef VBOXSTRICTRC /__attribute__((__nothrow__))/ FNIEMTHREADEDFUNC(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
6429	typedef FNIEMTHREADEDFUNC *PFNIEMTHREADEDFUNC;
6430	# define IEM_DECL_IEMTHREADEDFUNC_DEF(a_Name) \
6431	VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2)
6432	# define IEM_DECL_IEMTHREADEDFUNC_PROTO(a_Name) \
6433	VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2)
6434
6435	#else
6436	typedef VBOXSTRICTRC (FNIEMTHREADEDFUNC)(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
6437	typedef FNIEMTHREADEDFUNC *PFNIEMTHREADEDFUNC;
6438	# define IEM_DECL_IEMTHREADEDFUNC_DEF(a_Name) \
6439	VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2) IEM_NOEXCEPT_MAY_LONGJMP
6440	# define IEM_DECL_IEMTHREADEDFUNC_PROTO(a_Name) \
6441	VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2) IEM_NOEXCEPT_MAY_LONGJMP
6442	#endif
6443
6444
6445	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_Nop);
6446	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_LogCpuState);
6447
6448	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_DeferToCImpl0);
6449
6450	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckIrq);
6451	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckMode);
6452	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckHwInstrBps);
6453	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLim);
6454
6455	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodes);
6456	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodes);
6457	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesConsiderCsLim);
6458
6459	/* Branching: */
6460	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndPcAndOpcodes);
6461	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckPcAndOpcodes);
6462	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckPcAndOpcodesConsiderCsLim);
6463
6464	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesLoadingTlb);
6465	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesLoadingTlb);
6466	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesLoadingTlbConsiderCsLim);
6467
6468	/* Natural page crossing: */
6469	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesAcrossPageLoadingTlb);
6470	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesAcrossPageLoadingTlb);
6471	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesAcrossPageLoadingTlbConsiderCsLim);
6472
6473	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesOnNextPageLoadingTlb);
6474	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNextPageLoadingTlb);
6475	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNextPageLoadingTlbConsiderCsLim);
6476
6477	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesOnNewPageLoadingTlb);
6478	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNewPageLoadingTlb);
6479	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNewPageLoadingTlbConsiderCsLim);
6480
6481	bool iemThreadedCompileEmitIrqCheckBefore(PVMCPUCC pVCpu, PIEMTB pTb);
6482	bool iemThreadedCompileBeginEmitCallsComplications(PVMCPUCC pVCpu, PIEMTB pTb);
6483
6484	/* Native recompiler public bits: */
6485
6486	DECLHIDDEN(PIEMTB) iemNativeRecompile(PVMCPUCC pVCpu, PIEMTB pTb) RT_NOEXCEPT;
6487	DECLHIDDEN(void) iemNativeDisassembleTb(PVMCPU pVCpu, PCIEMTB pTb, PCDBGFINFOHLP pHlp) RT_NOEXCEPT;
6488	int iemExecMemAllocatorInit(PVMCPU pVCpu, uint64_t cbMax, uint64_t cbInitial, uint32_t cbChunk) RT_NOEXCEPT;
6489	DECLHIDDEN(PIEMNATIVEINSTR) iemExecMemAllocatorAlloc(PVMCPU pVCpu, uint32_t cbReq, PIEMTB pTb, PIEMNATIVEINSTR *ppaExec,
6490	struct IEMNATIVEPERCHUNKCTX const **ppChunkCtx) RT_NOEXCEPT;
6491	DECLHIDDEN(PIEMNATIVEINSTR) iemExecMemAllocatorAllocFromChunk(PVMCPU pVCpu, uint32_t idxChunk, uint32_t cbReq,
6492	PIEMNATIVEINSTR *ppaExec);
6493	DECLHIDDEN(void) iemExecMemAllocatorReadyForUse(PVMCPUCC pVCpu, void *pv, size_t cb) RT_NOEXCEPT;
6494	void iemExecMemAllocatorFree(PVMCPU pVCpu, void *pv, size_t cb) RT_NOEXCEPT;
6495	DECLASM(DECL_NO_RETURN(void)) iemNativeTbLongJmp(void *pvFramePointer, int rc) RT_NOEXCEPT;
6496	DECLHIDDEN(struct IEMNATIVEPERCHUNKCTX const *) iemExecMemGetTbChunkCtx(PVMCPU pVCpu, PCIEMTB pTb);
6497	DECLHIDDEN(struct IEMNATIVEPERCHUNKCTX const *) iemNativeRecompileAttachExecMemChunkCtx(PVMCPU pVCpu, uint32_t idxChunk);
6498
6499	#endif /* !RT_IN_ASSEMBLER - ASM-NOINC-END */
6500
6501
6502	/** @} */
6503
6504	RT_C_DECLS_END
6505
6506	/* ASM-INC: %include "IEMInternalStruct.mac" */
6507
6508	#endif /* !VMM_INCLUDED_SRC_include_IEMInternal_h */
6509

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h@ 105284

Download in other formats: