IEMInternal.h@ 105700

Last change on this file since 105700 was 105698, checked in by vboxsync, 8 months ago
VMM/IEM,TM: Adaptive timer polling and running of the timer queues from the IEM recompiler execution loop. bugref:10656
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 358.2 KB

Line
1	/* $Id: IEMInternal.h 105698 2024-08-15 23:33:49Z vboxsync $ */
2	/** @file
3	* IEM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2011-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_IEMInternal_h
29	#define VMM_INCLUDED_SRC_include_IEMInternal_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#ifndef RT_IN_ASSEMBLER
35	# include <VBox/vmm/cpum.h>
36	# include <VBox/vmm/iem.h>
37	# include <VBox/vmm/pgm.h>
38	# include <VBox/vmm/stam.h>
39	# include <VBox/param.h>
40
41	# include <iprt/setjmp-without-sigmask.h>
42	# include <iprt/list.h>
43	#endif /* !RT_IN_ASSEMBLER */
44
45
46	RT_C_DECLS_BEGIN
47
48
49	/** @defgroup grp_iem_int Internals
50	* @ingroup grp_iem
51	* @internal
52	* @{
53	*/
54
55	/* Make doxygen happy w/o overcomplicating the #if checks. */
56	#ifdef DOXYGEN_RUNNING
57	# define IEM_WITH_THROW_CATCH
58	# define VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
59	#endif
60
61	/** For expanding symbol in slickedit and other products tagging and
62	* crossreferencing IEM symbols. */
63	#ifndef IEM_STATIC
64	# define IEM_STATIC static
65	#endif
66
67	/** @def IEM_WITH_SETJMP
68	* Enables alternative status code handling using setjmps.
69	*
70	* This adds a bit of expense via the setjmp() call since it saves all the
71	* non-volatile registers. However, it eliminates return code checks and allows
72	* for more optimal return value passing (return regs instead of stack buffer).
73	*/
74	#if defined(DOXYGEN_RUNNING) \|\| defined(RT_OS_WINDOWS) \|\| 1
75	# define IEM_WITH_SETJMP
76	#endif
77
78	/** @def IEM_WITH_THROW_CATCH
79	* Enables using C++ throw/catch as an alternative to setjmp/longjmp in user
80	* mode code when IEM_WITH_SETJMP is in effect.
81	*
82	* With GCC 11.3.1 and code TLB on linux, using throw/catch instead of
83	* setjmp/long resulted in bs2-test-1 running 3.00% faster and all but on test
84	* result value improving by more than 1%. (Best out of three.)
85	*
86	* With Visual C++ 2019 and code TLB on windows, using throw/catch instead of
87	* setjmp/long resulted in bs2-test-1 running 3.68% faster and all but some of
88	* the MMIO and CPUID tests ran noticeably faster. Variation is greater than on
89	* Linux, but it should be quite a bit faster for normal code.
90	*/
91	#if defined(__cplusplus) && defined(IEM_WITH_SETJMP) && defined(IN_RING3) && (defined(__GNUC__) \|\| defined(_MSC_VER)) /* ASM-NOINC-START */
92	# define IEM_WITH_THROW_CATCH
93	#endif /ASM-NOINC-END/
94
95	/** @def IEM_WITH_ADAPTIVE_TIMER_POLLING
96	* Enables the adaptive timer polling code.
97	*/
98	#if defined(DOXYGEN_RUNNING) \|\| 0
99	# define IEM_WITH_ADAPTIVE_TIMER_POLLING
100	#endif
101
102	/** @def IEM_WITH_INTRA_TB_JUMPS
103	* Enables loop-jumps within a TB (currently only to the first call).
104	*/
105	#if defined(DOXYGEN_RUNNING) \|\| 1
106	# define IEM_WITH_INTRA_TB_JUMPS
107	#endif
108
109	/** @def IEMNATIVE_WITH_DELAYED_PC_UPDATING
110	* Enables the delayed PC updating optimization (see @bugref{10373}).
111	*/
112	#if defined(DOXYGEN_RUNNING) \|\| 1
113	# define IEMNATIVE_WITH_DELAYED_PC_UPDATING
114	#endif
115
116	/** Enables the SIMD register allocator @bugref{10614}. */
117	#if defined(DOXYGEN_RUNNING) \|\| 1
118	# define IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
119	#endif
120	/** Enables access to even callee saved registers. */
121	//# define IEMNATIVE_WITH_SIMD_REG_ACCESS_ALL_REGISTERS
122
123	#if defined(DOXYGEN_RUNNING) \|\| 1
124	/** @def IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
125	* Delay the writeback or dirty registers as long as possible. */
126	# define IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
127	#endif
128
129	/** @def IEM_WITH_TLB_STATISTICS
130	* Enables all TLB statistics. */
131	#if defined(VBOX_WITH_STATISTICS) \|\| defined(DOXYGEN_RUNNING)
132	# define IEM_WITH_TLB_STATISTICS
133	#endif
134
135	/** @def IEMNATIVE_WITH_SIMD_FP_NATIVE_EMITTERS
136	* Enable this to use native emitters for certain SIMD FP operations. */
137	#if 1 \|\| defined(DOXYGEN_RUNNING)
138	# define IEMNATIVE_WITH_SIMD_FP_NATIVE_EMITTERS
139	#endif
140
141	/** @def VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
142	* Enables a quicker alternative to throw/longjmp for IEM_DO_LONGJMP when
143	* executing native translation blocks.
144	*
145	* This exploits the fact that we save all non-volatile registers in the TB
146	* prologue and thus just need to do the same as the TB epilogue to get the
147	* effect of a longjmp/throw. Since MSC marks XMM6 thru XMM15 as
148	* non-volatile (and does something even more crazy for ARM), this probably
149	* won't work reliably on Windows. */
150	#ifdef RT_ARCH_ARM64
151	# ifndef RT_OS_WINDOWS
152	# define VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
153	# endif
154	#endif
155	/* ASM-NOINC-START */
156	#ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
157	# if !defined(IN_RING3) \
158	\|\| !defined(VBOX_WITH_IEM_RECOMPILER) \
159	\|\| !defined(VBOX_WITH_IEM_NATIVE_RECOMPILER)
160	# undef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
161	# elif defined(RT_OS_WINDOWS)
162	# pragma message("VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP is not safe to use on windows")
163	# endif
164	#endif
165
166
167	/** @def IEM_DO_LONGJMP
168	*
169	* Wrapper around longjmp / throw.
170	*
171	* @param a_pVCpu The CPU handle.
172	* @param a_rc The status code jump back with / throw.
173	*/
174	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
175	# ifdef IEM_WITH_THROW_CATCH
176	# ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
177	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) do { \
178	if ((a_pVCpu)->iem.s.pvTbFramePointerR3) \
179	iemNativeTbLongJmp((a_pVCpu)->iem.s.pvTbFramePointerR3, (a_rc)); \
180	throw int(a_rc); \
181	} while (0)
182	# else
183	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) throw int(a_rc)
184	# endif
185	# else
186	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) longjmp(*(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf), (a_rc))
187	# endif
188	#endif
189
190	/** For use with IEM function that may do a longjmp (when enabled).
191	*
192	* Visual C++ has trouble longjmp'ing from/over functions with the noexcept
193	* attribute. So, we indicate that function that may be part of a longjmp may
194	* throw "exceptions" and that the compiler should definitely not generate and
195	* std::terminate calling unwind code.
196	*
197	* Here is one example of this ending in std::terminate:
198	* @code{.txt}
199	00 00000041`cadfda10 00007ffc`5d5a1f9f ucrtbase!abort+0x4e
200	01 00000041`cadfda40 00007ffc`57af229a ucrtbase!terminate+0x1f
201	02 00000041`cadfda70 00007ffb`eec91030 VCRUNTIME140!__std_terminate+0xa [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\ehhelpers.cpp @ 192]
202	03 00000041`cadfdaa0 00007ffb`eec92c6d VCRUNTIME140_1!_CallSettingFrame+0x20 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\handlers.asm @ 50]
203	04 00000041`cadfdad0 00007ffb`eec93ae5 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToState+0x241 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 1085]
204	05 00000041`cadfdc00 00007ffb`eec92258 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToEmptyState+0x2d [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 218]
205	06 00000041`cadfdc30 00007ffb`eec940e9 VCRUNTIME140_1!__InternalCxxFrameHandler<__FrameHandler4>+0x194 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 304]
206	07 00000041`cadfdcd0 00007ffc`5f9f249f VCRUNTIME140_1!__CxxFrameHandler4+0xa9 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 290]
207	08 00000041`cadfdd40 00007ffc`5f980939 ntdll!RtlpExecuteHandlerForUnwind+0xf
208	09 00000041`cadfdd70 00007ffc`5f9a0edd ntdll!RtlUnwindEx+0x339
209	0a 00000041`cadfe490 00007ffc`57aff976 ntdll!RtlUnwind+0xcd
210	0b 00000041`cadfea00 00007ffb`e1b5de01 VCRUNTIME140!__longjmp_internal+0xe6 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\longjmp.asm @ 140]
211	0c (Inline Function) --------`-------- VBoxVMM!iemOpcodeGetNextU8SlowJmp+0x95 [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 1155]
212	0d 00000041`cadfea50 00007ffb`e1b60f6b VBoxVMM!iemOpcodeGetNextU8Jmp+0xc1 [L:\vbox-intern\src\VBox\VMM\include\IEMInline.h @ 402]
213	0e 00000041`cadfea90 00007ffb`e1cc6201 VBoxVMM!IEMExecForExits+0xdb [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 10185]
214	0f 00000041`cadfec70 00007ffb`e1d0df8d VBoxVMM!EMHistoryExec+0x4f1 [L:\vbox-intern\src\VBox\VMM\VMMAll\EMAll.cpp @ 452]
215	10 00000041`cadfed60 00007ffb`e1d0d4c0 VBoxVMM!nemR3WinHandleExitCpuId+0x79d [L:\vbox-intern\src\VBox\VMM\VMMAll\NEMAllNativeTemplate-win.cpp.h @ 1829] @encode
216	@endcode
217	*
218	* @see https://developercommunity.visualstudio.com/t/fragile-behavior-of-longjmp-called-from-noexcept-f/1532859
219	*/
220	#if defined(IEM_WITH_SETJMP) && (defined(_MSC_VER) \|\| defined(IEM_WITH_THROW_CATCH))
221	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT_EX(false)
222	#else
223	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT
224	#endif
225	/* ASM-NOINC-END */
226
227	#define IEM_IMPLEMENTS_TASKSWITCH
228
229	/** @def IEM_WITH_3DNOW
230	* Includes the 3DNow decoding. */
231	#if !defined(IEM_WITH_3DNOW) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
232	# ifndef IEM_WITHOUT_3DNOW
233	# define IEM_WITH_3DNOW
234	# endif
235	#endif
236
237	/** @def IEM_WITH_THREE_0F_38
238	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
239	#if !defined(IEM_WITH_THREE_0F_38) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
240	# ifndef IEM_WITHOUT_THREE_0F_38
241	# define IEM_WITH_THREE_0F_38
242	# endif
243	#endif
244
245	/** @def IEM_WITH_THREE_0F_3A
246	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
247	#if !defined(IEM_WITH_THREE_0F_3A) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
248	# ifndef IEM_WITHOUT_THREE_0F_3A
249	# define IEM_WITH_THREE_0F_3A
250	# endif
251	#endif
252
253	/** @def IEM_WITH_VEX
254	* Includes the VEX decoding. */
255	#if !defined(IEM_WITH_VEX) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
256	# ifndef IEM_WITHOUT_VEX
257	# define IEM_WITH_VEX
258	# endif
259	#endif
260
261	/** @def IEM_CFG_TARGET_CPU
262	* The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
263	*
264	* By default we allow this to be configured by the user via the
265	* CPUM/GuestCpuName config string, but this comes at a slight cost during
266	* decoding. So, for applications of this code where there is no need to
267	* be dynamic wrt target CPU, just modify this define.
268	*/
269	#if !defined(IEM_CFG_TARGET_CPU) \|\| defined(DOXYGEN_RUNNING)
270	# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
271	#endif
272
273	//#define IEM_WITH_CODE_TLB // - work in progress
274	//#define IEM_WITH_DATA_TLB // - work in progress
275
276
277	/** @def IEM_USE_UNALIGNED_DATA_ACCESS
278	* Use unaligned accesses instead of elaborate byte assembly. */
279	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86) \|\| defined(DOXYGEN_RUNNING) /ASM-NOINC/
280	# define IEM_USE_UNALIGNED_DATA_ACCESS
281	#endif /ASM-NOINC/
282
283	//#define IEM_LOG_MEMORY_WRITES
284
285
286
287	#ifndef RT_IN_ASSEMBLER /* ASM-NOINC-START - the rest of the file */
288
289	# if !defined(IEM_WITHOUT_INSTRUCTION_STATS) && !defined(DOXYGEN_RUNNING)
290	/** Instruction statistics. */
291	typedef struct IEMINSTRSTATS
292	{
293	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
294	# include "IEMInstructionStatisticsTmpl.h"
295	# undef IEM_DO_INSTR_STAT
296	} IEMINSTRSTATS;
297	#else
298	struct IEMINSTRSTATS;
299	typedef struct IEMINSTRSTATS IEMINSTRSTATS;
300	#endif
301	/** Pointer to IEM instruction statistics. */
302	typedef IEMINSTRSTATS *PIEMINSTRSTATS;
303
304
305	/** @name IEMTARGETCPU_EFL_BEHAVIOR_XXX - IEMCPU::aidxTargetCpuEflFlavour
306	* @{ */
307	#define IEMTARGETCPU_EFL_BEHAVIOR_NATIVE 0 /*< Native x86 EFLAGS result; Intel EFLAGS when on non-x86 hosts. /
308	#define IEMTARGETCPU_EFL_BEHAVIOR_INTEL 1 /*< Intel EFLAGS result. /
309	#define IEMTARGETCPU_EFL_BEHAVIOR_AMD 2 /*< AMD EFLAGS result /
310	#define IEMTARGETCPU_EFL_BEHAVIOR_RESERVED 3 /*< Reserved/dummy entry slot that's the same as 0. /
311	#define IEMTARGETCPU_EFL_BEHAVIOR_MASK 3 /*< For masking the index before use. /
312	/** Selects the right variant from a_aArray.
313	* pVCpu is implicit in the caller context. */
314	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT(a_aArray) \
315	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[1] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
316	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for when no native worker can
317	* be used because the host CPU does not support the operation. */
318	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_NON_NATIVE(a_aArray) \
319	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
320	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for a two dimentional
321	* array paralleling IEMCPU::aidxTargetCpuEflFlavour and a single bit index
322	* into the two.
323	* @sa IEM_SELECT_NATIVE_OR_FALLBACK */
324	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
325	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
326	(a_aaArray[a_fNative][pVCpu->iem.s.aidxTargetCpuEflFlavour[a_fNative] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
327	#else
328	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
329	(a_aaArray[0][pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
330	#endif
331	/** @} */
332
333	/**
334	* Picks @a a_pfnNative or @a a_pfnFallback according to the host CPU feature
335	* indicator given by @a a_fCpumFeatureMember (CPUMFEATURES member).
336	*
337	* On non-x86 hosts, this will shortcut to the fallback w/o checking the
338	* indicator.
339	*
340	* @sa IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX
341	*/
342	#if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
343	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) \
344	(g_CpumHostFeatures.s.a_fCpumFeatureMember ? a_pfnNative : a_pfnFallback)
345	#else
346	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) (a_pfnFallback)
347	#endif
348
349
350	/**
351	* Branch types.
352	*/
353	typedef enum IEMBRANCH
354	{
355	IEMBRANCH_JUMP = 1,
356	IEMBRANCH_CALL,
357	IEMBRANCH_TRAP,
358	IEMBRANCH_SOFTWARE_INT,
359	IEMBRANCH_HARDWARE_INT
360	} IEMBRANCH;
361	AssertCompileSize(IEMBRANCH, 4);
362
363
364	/**
365	* INT instruction types.
366	*/
367	typedef enum IEMINT
368	{
369	/** INT n instruction (opcode 0xcd imm). */
370	IEMINT_INTN = 0,
371	/** Single byte INT3 instruction (opcode 0xcc). */
372	IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
373	/** Single byte INTO instruction (opcode 0xce). */
374	IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
375	/** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
376	IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
377	} IEMINT;
378	AssertCompileSize(IEMINT, 4);
379
380
381	/**
382	* A FPU result.
383	*/
384	typedef struct IEMFPURESULT
385	{
386	/** The output value. */
387	RTFLOAT80U r80Result;
388	/** The output status. */
389	uint16_t FSW;
390	} IEMFPURESULT;
391	AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
392	/** Pointer to a FPU result. */
393	typedef IEMFPURESULT *PIEMFPURESULT;
394	/** Pointer to a const FPU result. */
395	typedef IEMFPURESULT const *PCIEMFPURESULT;
396
397
398	/**
399	* A FPU result consisting of two output values and FSW.
400	*/
401	typedef struct IEMFPURESULTTWO
402	{
403	/** The first output value. */
404	RTFLOAT80U r80Result1;
405	/** The output status. */
406	uint16_t FSW;
407	/** The second output value. */
408	RTFLOAT80U r80Result2;
409	} IEMFPURESULTTWO;
410	AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
411	AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
412	/** Pointer to a FPU result consisting of two output values and FSW. */
413	typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
414	/** Pointer to a const FPU result consisting of two output values and FSW. */
415	typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
416
417
418	/**
419	* IEM TLB entry.
420	*
421	* Lookup assembly:
422	* @code{.asm}
423	; Calculate tag.
424	mov rax, [VA]
425	shl rax, 16
426	shr rax, 16 + X86_PAGE_SHIFT
427	or rax, [uTlbRevision]
428
429	; Do indexing.
430	movzx ecx, al
431	lea rcx, [pTlbEntries + rcx]
432
433	; Check tag.
434	cmp [rcx + IEMTLBENTRY.uTag], rax
435	jne .TlbMiss
436
437	; Check access.
438	mov rax, ACCESS_FLAGS \| MAPPING_R3_NOT_VALID \| 0xffffff00
439	and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
440	cmp rax, [uTlbPhysRev]
441	jne .TlbMiss
442
443	; Calc address and we're done.
444	mov eax, X86_PAGE_OFFSET_MASK
445	and eax, [VA]
446	or rax, [rcx + IEMTLBENTRY.pMappingR3]
447	%ifdef VBOX_WITH_STATISTICS
448	inc qword [cTlbHits]
449	%endif
450	jmp .Done
451
452	.TlbMiss:
453	mov r8d, ACCESS_FLAGS
454	mov rdx, [VA]
455	mov rcx, [pVCpu]
456	call iemTlbTypeMiss
457	.Done:
458
459	@endcode
460	*
461	*/
462	typedef struct IEMTLBENTRY
463	{
464	/** The TLB entry tag.
465	* Bits 35 thru 0 are made up of the virtual address shifted right 12 bits, this
466	* is ASSUMING a virtual address width of 48 bits.
467	*
468	* Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
469	*
470	* The TLB lookup code uses the current TLB revision, which won't ever be zero,
471	* enabling an extremely cheap TLB invalidation most of the time. When the TLB
472	* revision wraps around though, the tags needs to be zeroed.
473	*
474	* @note Try use SHRD instruction? After seeing
475	* https://gmplib.org/~tege/x86-timing.pdf, maybe not.
476	*
477	* @todo This will need to be reorganized for 57-bit wide virtual address and
478	* PCID (currently 12 bits) and ASID (currently 6 bits) support. We'll
479	* have to move the TLB entry versioning entirely to the
480	* fFlagsAndPhysRev member then, 57 bit wide VAs means we'll only have
481	* 19 bits left (64 - 57 + 12 = 19) and they'll almost entire be
482	* consumed by PCID and ASID (12 + 6 = 18).
483	*/
484	uint64_t uTag;
485	/** Access flags and physical TLB revision.
486	*
487	* - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
488	* - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
489	* - Bit 2 - page tables - not user (complemented X86_PTE_US).
490	* - Bit 3 - pgm phys/virt - not directly writable.
491	* - Bit 4 - pgm phys page - not directly readable.
492	* - Bit 5 - page tables - not accessed (complemented X86_PTE_A).
493	* - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
494	* - Bit 7 - tlb entry - pMappingR3 member not valid.
495	* - Bits 63 thru 8 are used for the physical TLB revision number.
496	*
497	* We're using complemented bit meanings here because it makes it easy to check
498	* whether special action is required. For instance a user mode write access
499	* would do a "TEST fFlags, (X86_PTE_RW \| X86_PTE_US \| X86_PTE_D)" and a
500	* non-zero result would mean special handling needed because either it wasn't
501	* writable, or it wasn't user, or the page wasn't dirty. A user mode read
502	* access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
503	* need to check any PTE flag.
504	*/
505	uint64_t fFlagsAndPhysRev;
506	/** The guest physical page address. */
507	uint64_t GCPhys;
508	/** Pointer to the ring-3 mapping. */
509	R3PTRTYPE(uint8_t *) pbMappingR3;
510	#if HC_ARCH_BITS == 32
511	uint32_t u32Padding1;
512	#endif
513	} IEMTLBENTRY;
514	AssertCompileSize(IEMTLBENTRY, 32);
515	/** Pointer to an IEM TLB entry. */
516	typedef IEMTLBENTRY *PIEMTLBENTRY;
517	/** Pointer to a const IEM TLB entry. */
518	typedef IEMTLBENTRY const *PCIEMTLBENTRY;
519
520	/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
521	* @{ */
522	#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /*< Page tables: Not executable. /
523	#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /*< Page tables: Not writable. /
524	#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /*< Page tables: Not user accessible (supervisor only). /
525	#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /*< Phys page: Not writable (access handler, ROM, whatever). /
526	#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /*< Phys page: Not readable (MMIO / access handler, ROM) /
527	#define IEMTLBE_F_PT_NO_ACCESSED RT_BIT_64(5) /*< Phys tables: Not accessed (need to be marked accessed). /
528	#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /*< Page tables: Not dirty (needs to be made dirty on write). /
529	#define IEMTLBE_F_PT_LARGE_PAGE RT_BIT_64(7) /*< Page tables: Large 2 or 4 MiB page (for flushing). /
530	#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(8) /*< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. /
531	#define IEMTLBE_F_PG_UNASSIGNED RT_BIT_64(9) /*< Phys page: Unassigned memory (not RAM, ROM, MMIO2 or MMIO). /
532	#define IEMTLBE_F_PG_CODE_PAGE RT_BIT_64(10) /*< Phys page: Code page. /
533	#define IEMTLBE_F_PHYS_REV UINT64_C(0xfffffffffffff800) /*< Physical revision mask. @sa IEMTLB_PHYS_REV_INCR /
534	/** @} */
535	AssertCompile(PGMIEMGCPHYS2PTR_F_NO_WRITE == IEMTLBE_F_PG_NO_WRITE);
536	AssertCompile(PGMIEMGCPHYS2PTR_F_NO_READ == IEMTLBE_F_PG_NO_READ);
537	AssertCompile(PGMIEMGCPHYS2PTR_F_NO_MAPPINGR3 == IEMTLBE_F_NO_MAPPINGR3);
538	AssertCompile(PGMIEMGCPHYS2PTR_F_UNASSIGNED == IEMTLBE_F_PG_UNASSIGNED);
539	AssertCompile(PGMIEMGCPHYS2PTR_F_CODE_PAGE == IEMTLBE_F_PG_CODE_PAGE);
540	AssertCompile(PGM_WALKINFO_BIG_PAGE == IEMTLBE_F_PT_LARGE_PAGE);
541	/** The bits set by PGMPhysIemGCPhys2PtrNoLock. */
542	#define IEMTLBE_GCPHYS2PTR_MASK ( PGMIEMGCPHYS2PTR_F_NO_WRITE \
543	\| PGMIEMGCPHYS2PTR_F_NO_READ \
544	\| PGMIEMGCPHYS2PTR_F_NO_MAPPINGR3 \
545	\| PGMIEMGCPHYS2PTR_F_UNASSIGNED \
546	\| PGMIEMGCPHYS2PTR_F_CODE_PAGE \
547	\| IEMTLBE_F_PHYS_REV )
548
549
550	/** The TLB size (power of two).
551	* We initially chose 256 because that way we can obtain the result directly
552	* from a 8-bit register without an additional AND instruction.
553	* See also @bugref{10687}. */
554	#if defined(RT_ARCH_AMD64)
555	# define IEMTLB_ENTRY_COUNT 256
556	# define IEMTLB_ENTRY_COUNT_AS_POWER_OF_TWO 8
557	#else
558	# define IEMTLB_ENTRY_COUNT 8192
559	# define IEMTLB_ENTRY_COUNT_AS_POWER_OF_TWO 13
560	#endif
561	AssertCompile(RT_BIT_32(IEMTLB_ENTRY_COUNT_AS_POWER_OF_TWO) == IEMTLB_ENTRY_COUNT);
562
563	/** TLB slot format spec (assumes uint32_t or unsigned value). */
564	#if IEMTLB_ENTRY_COUNT <= 0x100 / 2
565	# define IEMTLB_SLOT_FMT "%02x"
566	#elif IEMTLB_ENTRY_COUNT <= 0x1000 / 2
567	# define IEMTLB_SLOT_FMT "%03x"
568	#elif IEMTLB_ENTRY_COUNT <= 0x10000 / 2
569	# define IEMTLB_SLOT_FMT "%04x"
570	#else
571	# define IEMTLB_SLOT_FMT "%05x"
572	#endif
573
574	/** Enable the large page bitmap TLB optimization.
575	*
576	* The idea here is to avoid scanning the full 32 KB (2MB pages, 2*512 TLB
577	* entries) or 64 KB (4MB pages, 2*1024 TLB entries) worth of TLB entries during
578	* invlpg when large pages are used, and instead just scan 128 or 256 bytes of
579	* the bmLargePage bitmap to determin which TLB entires that might be containing
580	* large pages and actually require checking.
581	*
582	* There is a good posibility of false positives since we currently don't clear
583	* the bitmap when flushing the TLB, but it should help reduce the workload when
584	* the large pages aren't fully loaded into the TLB in their entirity...
585	*/
586	#define IEMTLB_WITH_LARGE_PAGE_BITMAP
587
588	/**
589	* An IEM TLB.
590	*
591	* We've got two of these, one for data and one for instructions.
592	*/
593	typedef struct IEMTLB
594	{
595	/** The non-global TLB revision.
596	* This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
597	* by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
598	* the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
599	* (The revision zero indicates an invalid TLB entry.)
600	*
601	* The initial value is choosen to cause an early wraparound. */
602	uint64_t uTlbRevision;
603	/** The TLB physical address revision - shadow of PGM variable.
604	*
605	* This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
606	* incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
607	* a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
608	* as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
609	*
610	* The initial value is choosen to cause an early wraparound.
611	*
612	* @note This is placed between the two TLB revisions because we
613	* load it in pair with one or the other on arm64. */
614	uint64_t volatile uTlbPhysRev;
615	/** The global TLB revision.
616	* Same as uTlbRevision, but only increased for global flushes. */
617	uint64_t uTlbRevisionGlobal;
618
619	/** Large page tag range.
620	*
621	* This is used to avoid scanning a large page's worth of TLB entries for each
622	* INVLPG instruction, and only to do so iff we've loaded any and when the
623	* address is in this range. This is kept up to date when we loading new TLB
624	* entries.
625	*/
626	struct LARGEPAGERANGE
627	{
628	/** The lowest large page address tag, UINT64_MAX if none. */
629	uint64_t uFirstTag;
630	/** The highest large page address tag (with offset mask part set), 0 if none. */
631	uint64_t uLastTag;
632	}
633	/** Large page range for non-global pages. */
634	NonGlobalLargePageRange,
635	/** Large page range for global pages. */
636	GlobalLargePageRange;
637	/** Number of non-global entries for large pages loaded since last TLB flush. */
638	uint32_t cTlbNonGlobalLargePageCurLoads;
639	/** Number of global entries for large pages loaded since last TLB flush. */
640	uint32_t cTlbGlobalLargePageCurLoads;
641
642	/* Statistics: */
643
644	/** TLB hits in IEMAll.cpp code (IEM_WITH_TLB_STATISTICS only; both).
645	* @note For the data TLB this is only used in iemMemMap and and for direct (i.e.
646	* not via safe read/write path) calls to iemMemMapJmp. */
647	uint64_t cTlbCoreHits;
648	/** Safe read/write TLB hits in iemMemMapJmp (IEM_WITH_TLB_STATISTICS
649	* only; data tlb only). */
650	uint64_t cTlbSafeHits;
651	/** TLB hits in IEMAllMemRWTmplInline.cpp.h (data + IEM_WITH_TLB_STATISTICS only). */
652	uint64_t cTlbInlineCodeHits;
653
654	/** TLB misses in IEMAll.cpp code (both).
655	* @note For the data TLB this is only used in iemMemMap and for direct (i.e.
656	* not via safe read/write path) calls to iemMemMapJmp. So,
657	* for the data TLB this more like 'other misses', while for the code
658	* TLB is all misses. */
659	uint64_t cTlbCoreMisses;
660	/** Subset of cTlbCoreMisses that results in PTE.G=1 loads (odd entries). */
661	uint64_t cTlbCoreGlobalLoads;
662	/** Safe read/write TLB misses in iemMemMapJmp (so data only). */
663	uint64_t cTlbSafeMisses;
664	/** Subset of cTlbSafeMisses that results in PTE.G=1 loads (odd entries). */
665	uint64_t cTlbSafeGlobalLoads;
666	/** Safe read path taken (data only). */
667	uint64_t cTlbSafeReadPath;
668	/** Safe write path taken (data only). */
669	uint64_t cTlbSafeWritePath;
670
671	/** @name Details for native code TLB misses.
672	* @note These counts are included in the above counters (cTlbSafeReadPath,
673	* cTlbSafeWritePath, cTlbInlineCodeHits).
674	* @{ */
675	/** TLB misses in native code due to tag mismatch. */
676	STAMCOUNTER cTlbNativeMissTag;
677	/** TLB misses in native code due to flags or physical revision mismatch. */
678	STAMCOUNTER cTlbNativeMissFlagsAndPhysRev;
679	/** TLB misses in native code due to misaligned access. */
680	STAMCOUNTER cTlbNativeMissAlignment;
681	/** TLB misses in native code due to cross page access. */
682	uint32_t cTlbNativeMissCrossPage;
683	/** TLB misses in native code due to non-canonical address. */
684	uint32_t cTlbNativeMissNonCanonical;
685	/** @} */
686
687	/** Slow read path (code only). */
688	uint32_t cTlbSlowCodeReadPath;
689
690	/** Regular TLB flush count. */
691	uint32_t cTlsFlushes;
692	/** Global TLB flush count. */
693	uint32_t cTlsGlobalFlushes;
694	/** Revision rollovers. */
695	uint32_t cTlbRevisionRollovers;
696	/** Physical revision flushes. */
697	uint32_t cTlbPhysRevFlushes;
698	/** Physical revision rollovers. */
699	uint32_t cTlbPhysRevRollovers;
700
701	/** Number of INVLPG (and similar) operations. */
702	uint32_t cTlbInvlPg;
703	/** Subset of cTlbInvlPg that involved non-global large pages. */
704	uint32_t cTlbInvlPgLargeNonGlobal;
705	/** Subset of cTlbInvlPg that involved global large pages. */
706	uint32_t cTlbInvlPgLargeGlobal;
707
708	uint32_t au32Padding[13];
709
710	/** The TLB entries.
711	* Even entries are for PTE.G=0 and uses uTlbRevision.
712	* Odd entries are for PTE.G=1 and uses uTlbRevisionGlobal. */
713	IEMTLBENTRY aEntries[IEMTLB_ENTRY_COUNT * 2];
714	#ifdef IEMTLB_WITH_LARGE_PAGE_BITMAP
715	/** Bitmap tracking TLB entries for large pages.
716	* This duplicates IEMTLBE_F_PT_LARGE_PAGE for each TLB entry. */
717	uint64_t bmLargePage[IEMTLB_ENTRY_COUNT * 2 / 64];
718	#endif
719	} IEMTLB;
720	AssertCompileSizeAlignment(IEMTLB, 64);
721	#ifdef IEMTLB_WITH_LARGE_PAGE_BITMAP
722	AssertCompile(IEMTLB_ENTRY_COUNT >= 32 /* bmLargePage ASSUMPTION */);
723	#endif
724	/** The width (in bits) of the address portion of the TLB tag. */
725	#define IEMTLB_TAG_ADDR_WIDTH 36
726	/** IEMTLB::uTlbRevision increment. */
727	#define IEMTLB_REVISION_INCR RT_BIT_64(IEMTLB_TAG_ADDR_WIDTH)
728	/** IEMTLB::uTlbRevision mask. */
729	#define IEMTLB_REVISION_MASK (~(RT_BIT_64(IEMTLB_TAG_ADDR_WIDTH) - 1))
730
731	/** IEMTLB::uTlbPhysRev increment.
732	* @sa IEMTLBE_F_PHYS_REV */
733	#define IEMTLB_PHYS_REV_INCR RT_BIT_64(11)
734	AssertCompile(IEMTLBE_F_PHYS_REV == ~(IEMTLB_PHYS_REV_INCR - 1U));
735
736	/**
737	* Calculates the TLB tag for a virtual address but without TLB revision.
738	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
739	* @param a_GCPtr The virtual address. Must be RTGCPTR or same size or
740	* the clearing of the top 16 bits won't work (if 32-bit
741	* we'll end up with mostly zeros).
742	*/
743	#define IEMTLB_CALC_TAG_NO_REV(a_GCPtr) ( (((a_GCPtr) << 16) >> (GUEST_PAGE_SHIFT + 16)) )
744	/**
745	* Converts a TLB tag value into a even TLB index.
746	* @returns Index into IEMTLB::aEntries.
747	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
748	*/
749	#if IEMTLB_ENTRY_COUNT == 256
750	# define IEMTLB_TAG_TO_EVEN_INDEX(a_uTag) ( (uint8_t)(a_uTag) * 2U )
751	#else
752	# define IEMTLB_TAG_TO_EVEN_INDEX(a_uTag) ( ((a_uTag) & (IEMTLB_ENTRY_COUNT - 1U)) * 2U )
753	AssertCompile(RT_IS_POWER_OF_TWO(IEMTLB_ENTRY_COUNT));
754	#endif
755	/**
756	* Converts a TLB tag value into an even TLB index.
757	* @returns Pointer into IEMTLB::aEntries corresponding to .
758	* @param a_pTlb The TLB.
759	* @param a_uTag Value returned by IEMTLB_CALC_TAG or
760	* IEMTLB_CALC_TAG_NO_REV.
761	*/
762	#define IEMTLB_TAG_TO_EVEN_ENTRY(a_pTlb, a_uTag) ( &(a_pTlb)->aEntries[IEMTLB_TAG_TO_EVEN_INDEX(a_uTag)] )
763
764	/** Converts a GC address to an even TLB index. */
765	#define IEMTLB_ADDR_TO_EVEN_INDEX(a_GCPtr) IEMTLB_TAG_TO_EVEN_INDEX(IEMTLB_CALC_TAG_NO_REV(a_GCPtr))
766
767
768	/** @def IEM_WITH_TLB_TRACE
769	* Enables the TLB tracing.
770	* Adjust buffer size in IEMR3Init. */
771	#if defined(DOXYGEN_RUNNING) \|\| 0
772	# define IEM_WITH_TLB_TRACE
773	#endif
774
775	#ifdef IEM_WITH_TLB_TRACE
776
777	/** TLB trace entry types. */
778	typedef enum : uint8_t
779	{
780	kIemTlbTraceType_Invalid,
781	kIemTlbTraceType_InvlPg,
782	kIemTlbTraceType_EvictSlot,
783	kIemTlbTraceType_LargeEvictSlot,
784	kIemTlbTraceType_LargeScan,
785	kIemTlbTraceType_Flush,
786	kIemTlbTraceType_FlushGlobal,
787	kIemTlbTraceType_Load,
788	kIemTlbTraceType_LoadGlobal,
789	kIemTlbTraceType_Load_Cr0,
790	kIemTlbTraceType_Load_Cr3,
791	kIemTlbTraceType_Load_Cr4,
792	kIemTlbTraceType_Load_Efer,
793	kIemTlbTraceType_Irq,
794	kIemTlbTraceType_Xcpt,
795	kIemTlbTraceType_IRet,
796	kIemTlbTraceType_Tb_Compile,
797	kIemTlbTraceType_Tb_Exec_Threaded,
798	kIemTlbTraceType_Tb_Exec_Native,
799	kIemTlbTraceType_User0,
800	kIemTlbTraceType_User1,
801	kIemTlbTraceType_User2,
802	kIemTlbTraceType_User3,
803	} IEMTLBTRACETYPE;
804
805	/** TLB trace entry. */
806	typedef struct IEMTLBTRACEENTRY
807	{
808	/** The flattened RIP for the event. */
809	uint64_t rip;
810	/** The event type. */
811	IEMTLBTRACETYPE enmType;
812	/** Byte parameter - typically used as 'bool fDataTlb'. */
813	uint8_t bParam;
814	/** 16-bit parameter value. */
815	uint16_t u16Param;
816	/** 32-bit parameter value. */
817	uint32_t u32Param;
818	/** 64-bit parameter value. */
819	uint64_t u64Param;
820	/** 64-bit parameter value. */
821	uint64_t u64Param2;
822	} IEMTLBTRACEENTRY;
823	AssertCompileSize(IEMTLBTRACEENTRY, 32);
824	/** Pointer to a TLB trace entry. */
825	typedef IEMTLBTRACEENTRY *PIEMTLBTRACEENTRY;
826	/** Pointer to a const TLB trace entry. */
827	typedef IEMTLBTRACEENTRY const *PCIEMTLBTRACEENTRY;
828	#endif /* !IEM_WITH_TLB_TRACE */
829
830	#if defined(IEM_WITH_TLB_TRACE) && defined(IN_RING3) && 1
831	# define IEMTLBTRACE_INVLPG(a_pVCpu, a_GCPtr) \
832	iemTlbTrace(a_pVCpu, kIemTlbTraceType_InvlPg, a_GCPtr)
833	# define IEMTLBTRACE_EVICT_SLOT(a_pVCpu, a_GCPtrTag, a_GCPhys, a_idxSlot, a_fDataTlb) \
834	iemTlbTrace(a_pVCpu, kIemTlbTraceType_EvictSlot, a_GCPtrTag, a_GCPhys, a_fDataTlb, a_idxSlot)
835	# define IEMTLBTRACE_LARGE_EVICT_SLOT(a_pVCpu, a_GCPtrTag, a_GCPhys, a_idxSlot, a_fDataTlb) \
836	iemTlbTrace(a_pVCpu, kIemTlbTraceType_LargeEvictSlot, a_GCPtrTag, a_GCPhys, a_fDataTlb, a_idxSlot)
837	# define IEMTLBTRACE_LARGE_SCAN(a_pVCpu, a_fGlobal, a_fNonGlobal, a_fDataTlb) \
838	iemTlbTrace(a_pVCpu, kIemTlbTraceType_LargeScan, 0, 0, a_fDataTlb, (uint8_t)a_fGlobal \| ((uint8_t)a_fNonGlobal << 1))
839	# define IEMTLBTRACE_FLUSH(a_pVCpu, a_uRev, a_fDataTlb) \
840	iemTlbTrace(a_pVCpu, kIemTlbTraceType_Flush, a_uRev, 0, a_fDataTlb)
841	# define IEMTLBTRACE_FLUSH_GLOBAL(a_pVCpu, a_uRev, a_uGRev, a_fDataTlb) \
842	iemTlbTrace(a_pVCpu, kIemTlbTraceType_FlushGlobal, a_uRev, a_uGRev, a_fDataTlb)
843	# define IEMTLBTRACE_LOAD(a_pVCpu, a_GCPtr, a_GCPhys, a_fTlb, a_fDataTlb) \
844	iemTlbTrace(a_pVCpu, kIemTlbTraceType_Load, a_GCPtr, a_GCPhys, a_fDataTlb, a_fTlb)
845	# define IEMTLBTRACE_LOAD_GLOBAL(a_pVCpu, a_GCPtr, a_GCPhys, a_fTlb, a_fDataTlb) \
846	iemTlbTrace(a_pVCpu, kIemTlbTraceType_LoadGlobal, a_GCPtr, a_GCPhys, a_fDataTlb, a_fTlb)
847	#else
848	# define IEMTLBTRACE_INVLPG(a_pVCpu, a_GCPtr) do { } while (0)
849	# define IEMTLBTRACE_EVICT_SLOT(a_pVCpu, a_GCPtrTag, a_GCPhys, a_idxSlot, a_fDataTlb) do { } while (0)
850	# define IEMTLBTRACE_LARGE_EVICT_SLOT(a_pVCpu, a_GCPtrTag, a_GCPhys, a_idxSlot, a_fDataTlb) do { } while (0)
851	# define IEMTLBTRACE_LARGE_SCAN(a_pVCpu, a_fGlobal, a_fNonGlobal, a_fDataTlb) do { } while (0)
852	# define IEMTLBTRACE_FLUSH(a_pVCpu, a_uRev, a_fDataTlb) do { } while (0)
853	# define IEMTLBTRACE_FLUSH_GLOBAL(a_pVCpu, a_uRev, a_uGRev, a_fDataTlb) do { } while (0)
854	# define IEMTLBTRACE_LOAD(a_pVCpu, a_GCPtr, a_GCPhys, a_fTlb, a_fDataTlb) do { } while (0)
855	# define IEMTLBTRACE_LOAD_GLOBAL(a_pVCpu, a_GCPtr, a_GCPhys, a_fTlb, a_fDataTlb) do { } while (0)
856	#endif
857
858	#if defined(IEM_WITH_TLB_TRACE) && defined(IN_RING3) && 1
859	# define IEMTLBTRACE_LOAD_CR0(a_pVCpu, a_uNew, a_uOld) iemTlbTrace(a_pVCpu, kIemTlbTraceType_Load_Cr0, a_uNew, a_uOld)
860	# define IEMTLBTRACE_LOAD_CR3(a_pVCpu, a_uNew, a_uOld) iemTlbTrace(a_pVCpu, kIemTlbTraceType_Load_Cr3, a_uNew, a_uOld)
861	# define IEMTLBTRACE_LOAD_CR4(a_pVCpu, a_uNew, a_uOld) iemTlbTrace(a_pVCpu, kIemTlbTraceType_Load_Cr4, a_uNew, a_uOld)
862	# define IEMTLBTRACE_LOAD_EFER(a_pVCpu, a_uNew, a_uOld) iemTlbTrace(a_pVCpu, kIemTlbTraceType_Load_Efer, a_uNew, a_uOld)
863	#else
864	# define IEMTLBTRACE_LOAD_CR0(a_pVCpu, a_uNew, a_uOld) do { } while (0)
865	# define IEMTLBTRACE_LOAD_CR3(a_pVCpu, a_uNew, a_uOld) do { } while (0)
866	# define IEMTLBTRACE_LOAD_CR4(a_pVCpu, a_uNew, a_uOld) do { } while (0)
867	# define IEMTLBTRACE_LOAD_EFER(a_pVCpu, a_uNew, a_uOld) do { } while (0)
868	#endif
869
870	#if defined(IEM_WITH_TLB_TRACE) && defined(IN_RING3) && 1
871	# define IEMTLBTRACE_IRQ(a_pVCpu, a_uVector, a_fFlags, a_fEFlags) \
872	iemTlbTrace(a_pVCpu, kIemTlbTraceType_Irq, a_fEFlags, 0, a_uVector, a_fFlags)
873	# define IEMTLBTRACE_XCPT(a_pVCpu, a_uVector, a_uErr, a_uCr2, a_fFlags) \
874	iemTlbTrace(a_pVCpu, kIemTlbTraceType_Xcpt, a_uErr, a_uCr2, a_uVector, a_fFlags)
875	# define IEMTLBTRACE_IRET(a_pVCpu, a_uRetCs, a_uRetRip, a_fEFlags) \
876	iemTlbTrace(a_pVCpu, kIemTlbTraceType_IRet, a_uRetRip, a_fEFlags, 0, a_uRetCs)
877	#else
878	# define IEMTLBTRACE_IRQ(a_pVCpu, a_uVector, a_fFlags, a_fEFlags) do { } while (0)
879	# define IEMTLBTRACE_XCPT(a_pVCpu, a_uVector, a_uErr, a_uCr2, a_fFlags) do { } while (0)
880	# define IEMTLBTRACE_IRET(a_pVCpu, a_uRetCs, a_uRetRip, a_fEFlags) do { } while (0)
881	#endif
882
883	#if defined(IEM_WITH_TLB_TRACE) && defined(IN_RING3) && 1
884	# define IEMTLBTRACE_TB_COMPILE(a_pVCpu, a_GCPhysPc) \
885	iemTlbTrace(a_pVCpu, kIemTlbTraceType_Tb_Compile, a_GCPhysPc)
886	# define IEMTLBTRACE_TB_EXEC_THRD(a_pVCpu, a_pTb) \
887	iemTlbTrace(a_pVCpu, kIemTlbTraceType_Tb_Exec_Threaded, (a_pTb)->GCPhysPc, (uintptr_t)a_pTb, 0, (a_pTb)->cUsed)
888	# define IEMTLBTRACE_TB_EXEC_N8VE(a_pVCpu, a_pTb) \
889	iemTlbTrace(a_pVCpu, kIemTlbTraceType_Tb_Exec_Native, (a_pTb)->GCPhysPc, (uintptr_t)a_pTb, 0, (a_pTb)->cUsed)
890	#else
891	# define IEMTLBTRACE_TB_COMPILE(a_pVCpu, a_GCPhysPc) do { } while (0)
892	# define IEMTLBTRACE_TB_EXEC_THRD(a_pVCpu, a_pTb) do { } while (0)
893	# define IEMTLBTRACE_TB_EXEC_N8VE(a_pVCpu, a_pTb) do { } while (0)
894	#endif
895
896	#if defined(IEM_WITH_TLB_TRACE) && defined(IN_RING3) && 1
897	# define IEMTLBTRACE_USER0(a_pVCpu, a_u64Param1, a_u64Param2, a_u32Param, a_bParam) \
898	iemTlbTrace(a_pVCpu, kIemTlbTraceType_User0, a_u64Param1, a_u64Param2, a_bParam, a_u32Param)
899	# define IEMTLBTRACE_USER1(a_pVCpu, a_u64Param1, a_u64Param2, a_u32Param, a_bParam) \
900	iemTlbTrace(a_pVCpu, kIemTlbTraceType_User1, a_u64Param1, a_u64Param2, a_bParam, a_u32Param)
901	# define IEMTLBTRACE_USER2(a_pVCpu, a_u64Param1, a_u64Param2, a_u32Param, a_bParam) \
902	iemTlbTrace(a_pVCpu, kIemTlbTraceType_User2, a_u64Param1, a_u64Param2, a_bParam, a_u32Param)
903	# define IEMTLBTRACE_USER3(a_pVCpu, a_u64Param1, a_u64Param2, a_u32Param, a_bParam) \
904	iemTlbTrace(a_pVCpu, kIemTlbTraceType_User3, a_u64Param1, a_u64Param2, a_bParam, a_u32Param)
905	#else
906	# define IEMTLBTRACE_USER0(a_pVCpu, a_u64Param1, a_u64Param2, a_u32Param, a_bParam) do { } while (0)
907	# define IEMTLBTRACE_USER1(a_pVCpu, a_u64Param1, a_u64Param2, a_u32Param, a_bParam) do { } while (0)
908	# define IEMTLBTRACE_USER2(a_pVCpu, a_u64Param1, a_u64Param2, a_u32Param, a_bParam) do { } while (0)
909	# define IEMTLBTRACE_USER3(a_pVCpu, a_u64Param1, a_u64Param2, a_u32Param, a_bParam) do { } while (0)
910	#endif
911
912
913	/** @name IEM_MC_F_XXX - MC block flags/clues.
914	* @todo Merge with IEM_CIMPL_F_XXX
915	* @{ */
916	#define IEM_MC_F_ONLY_8086 RT_BIT_32(0)
917	#define IEM_MC_F_MIN_186 RT_BIT_32(1)
918	#define IEM_MC_F_MIN_286 RT_BIT_32(2)
919	#define IEM_MC_F_NOT_286_OR_OLDER IEM_MC_F_MIN_386
920	#define IEM_MC_F_MIN_386 RT_BIT_32(3)
921	#define IEM_MC_F_MIN_486 RT_BIT_32(4)
922	#define IEM_MC_F_MIN_PENTIUM RT_BIT_32(5)
923	#define IEM_MC_F_MIN_PENTIUM_II IEM_MC_F_MIN_PENTIUM
924	#define IEM_MC_F_MIN_CORE IEM_MC_F_MIN_PENTIUM
925	#define IEM_MC_F_64BIT RT_BIT_32(6)
926	#define IEM_MC_F_NOT_64BIT RT_BIT_32(7)
927	/** This is set by IEMAllN8vePython.py to indicate a variation without the
928	* flags-clearing-and-checking, when there is also a variation with that.
929	* @note Do not use this manully, it's only for python and for testing in
930	* the native recompiler! */
931	#define IEM_MC_F_WITHOUT_FLAGS RT_BIT_32(8)
932	/** @} */
933
934	/** @name IEM_CIMPL_F_XXX - State change clues for CIMPL calls.
935	*
936	* These clues are mainly for the recompiler, so that it can emit correct code.
937	*
938	* They are processed by the python script and which also automatically
939	* calculates flags for MC blocks based on the statements, extending the use of
940	* these flags to describe MC block behavior to the recompiler core. The python
941	* script pass the flags to the IEM_MC2_END_EMIT_CALLS macro, but mainly for
942	* error checking purposes. The script emits the necessary fEndTb = true and
943	* similar statements as this reduces compile time a tiny bit.
944	*
945	* @{ */
946	/** Flag set if direct branch, clear if absolute or indirect. */
947	#define IEM_CIMPL_F_BRANCH_DIRECT RT_BIT_32(0)
948	/** Flag set if indirect branch, clear if direct or relative.
949	* This is also used for all system control transfers (SYSCALL, SYSRET, INT, ++)
950	* as well as for return instructions (RET, IRET, RETF). */
951	#define IEM_CIMPL_F_BRANCH_INDIRECT RT_BIT_32(1)
952	/** Flag set if relative branch, clear if absolute or indirect. */
953	#define IEM_CIMPL_F_BRANCH_RELATIVE RT_BIT_32(2)
954	/** Flag set if conditional branch, clear if unconditional. */
955	#define IEM_CIMPL_F_BRANCH_CONDITIONAL RT_BIT_32(3)
956	/** Flag set if it's a far branch (changes CS). */
957	#define IEM_CIMPL_F_BRANCH_FAR RT_BIT_32(4)
958	/** Convenience: Testing any kind of branch. */
959	#define IEM_CIMPL_F_BRANCH_ANY (IEM_CIMPL_F_BRANCH_DIRECT \| IEM_CIMPL_F_BRANCH_INDIRECT \| IEM_CIMPL_F_BRANCH_RELATIVE)
960
961	/** Execution flags may change (IEMCPU::fExec). */
962	#define IEM_CIMPL_F_MODE RT_BIT_32(5)
963	/** May change significant portions of RFLAGS. */
964	#define IEM_CIMPL_F_RFLAGS RT_BIT_32(6)
965	/** May change the status bits (X86_EFL_STATUS_BITS) in RFLAGS. */
966	#define IEM_CIMPL_F_STATUS_FLAGS RT_BIT_32(7)
967	/** May trigger interrupt shadowing. */
968	#define IEM_CIMPL_F_INHIBIT_SHADOW RT_BIT_32(8)
969	/** May enable interrupts, so recheck IRQ immediately afterwards executing
970	* the instruction. */
971	#define IEM_CIMPL_F_CHECK_IRQ_AFTER RT_BIT_32(9)
972	/** May disable interrupts, so recheck IRQ immediately before executing the
973	* instruction. */
974	#define IEM_CIMPL_F_CHECK_IRQ_BEFORE RT_BIT_32(10)
975	/** Convenience: Check for IRQ both before and after an instruction. */
976	#define IEM_CIMPL_F_CHECK_IRQ_BEFORE_AND_AFTER (IEM_CIMPL_F_CHECK_IRQ_BEFORE \| IEM_CIMPL_F_CHECK_IRQ_AFTER)
977	/** May trigger a VM exit (treated like IEM_CIMPL_F_MODE atm). */
978	#define IEM_CIMPL_F_VMEXIT RT_BIT_32(11)
979	/** May modify FPU state.
980	* @todo Not sure if this is useful yet. */
981	#define IEM_CIMPL_F_FPU RT_BIT_32(12)
982	/** REP prefixed instruction which may yield before updating PC.
983	* @todo Not sure if this is useful, REP functions now return non-zero
984	* status if they don't update the PC. */
985	#define IEM_CIMPL_F_REP RT_BIT_32(13)
986	/** I/O instruction.
987	* @todo Not sure if this is useful yet. */
988	#define IEM_CIMPL_F_IO RT_BIT_32(14)
989	/** Force end of TB after the instruction. */
990	#define IEM_CIMPL_F_END_TB RT_BIT_32(15)
991	/** Flag set if a branch may also modify the stack (push/pop return address). */
992	#define IEM_CIMPL_F_BRANCH_STACK RT_BIT_32(16)
993	/** Flag set if a branch may also modify the stack (push/pop return address)
994	* and switch it (load/restore SS:RSP). */
995	#define IEM_CIMPL_F_BRANCH_STACK_FAR RT_BIT_32(17)
996	/** Convenience: Raise exception (technically unnecessary, since it shouldn't return VINF_SUCCESS). */
997	#define IEM_CIMPL_F_XCPT \
998	(IEM_CIMPL_F_BRANCH_INDIRECT \| IEM_CIMPL_F_BRANCH_FAR \| IEM_CIMPL_F_BRANCH_STACK_FAR \
999	\| IEM_CIMPL_F_MODE \| IEM_CIMPL_F_RFLAGS \| IEM_CIMPL_F_VMEXIT)
1000
1001	/** The block calls a C-implementation instruction function with two implicit arguments.
1002	* Mutually exclusive with IEM_CIMPL_F_CALLS_AIMPL and
1003	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
1004	* @note The python scripts will add this if missing. */
1005	#define IEM_CIMPL_F_CALLS_CIMPL RT_BIT_32(18)
1006	/** The block calls an ASM-implementation instruction function.
1007	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL and
1008	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
1009	* @note The python scripts will add this if missing. */
1010	#define IEM_CIMPL_F_CALLS_AIMPL RT_BIT_32(19)
1011	/** The block calls an ASM-implementation instruction function with an implicit
1012	* X86FXSTATE pointer argument.
1013	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL, IEM_CIMPL_F_CALLS_AIMPL and
1014	* IEM_CIMPL_F_CALLS_AIMPL_WITH_XSTATE.
1015	* @note The python scripts will add this if missing. */
1016	#define IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE RT_BIT_32(20)
1017	/** The block calls an ASM-implementation instruction function with an implicit
1018	* X86XSAVEAREA pointer argument.
1019	* Mutually exclusive with IEM_CIMPL_F_CALLS_CIMPL, IEM_CIMPL_F_CALLS_AIMPL and
1020	* IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE.
1021	* @note No different from IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE, so same value.
1022	* @note The python scripts will add this if missing. */
1023	#define IEM_CIMPL_F_CALLS_AIMPL_WITH_XSTATE IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE
1024	/** @} */
1025
1026
1027	/** @name IEM_F_XXX - Execution mode flags (IEMCPU::fExec, IEMTB::fFlags).
1028	*
1029	* These flags are set when entering IEM and adjusted as code is executed, such
1030	* that they will always contain the current values as instructions are
1031	* finished.
1032	*
1033	* In recompiled execution mode, (most of) these flags are included in the
1034	* translation block selection key and stored in IEMTB::fFlags alongside the
1035	* IEMTB_F_XXX flags. The latter flags uses bits 31 thru 24, which are all zero
1036	* in IEMCPU::fExec.
1037	*
1038	* @{ */
1039	/** Mode: The block target mode mask. */
1040	#define IEM_F_MODE_MASK UINT32_C(0x0000001f)
1041	/** Mode: The IEMMODE part of the IEMTB_F_MODE_MASK value. */
1042	#define IEM_F_MODE_CPUMODE_MASK UINT32_C(0x00000003)
1043	/** X86 Mode: Bit used to indicating pre-386 CPU in 16-bit mode (for eliminating
1044	* conditional in EIP/IP updating), and flat wide open CS, SS, DS, and ES in
1045	* 32-bit mode (for simplifying most memory accesses). */
1046	#define IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK UINT32_C(0x00000004)
1047	/** X86 Mode: Bit indicating protected mode, real mode (or SMM) when not set. */
1048	#define IEM_F_MODE_X86_PROT_MASK UINT32_C(0x00000008)
1049	/** X86 Mode: Bit used to indicate virtual 8086 mode (only 16-bit). */
1050	#define IEM_F_MODE_X86_V86_MASK UINT32_C(0x00000010)
1051
1052	/** X86 Mode: 16-bit on 386 or later. */
1053	#define IEM_F_MODE_X86_16BIT UINT32_C(0x00000000)
1054	/** X86 Mode: 80286, 80186 and 8086/88 targetting blocks (EIP update opt). */
1055	#define IEM_F_MODE_X86_16BIT_PRE_386 UINT32_C(0x00000004)
1056	/** X86 Mode: 16-bit protected mode on 386 or later. */
1057	#define IEM_F_MODE_X86_16BIT_PROT UINT32_C(0x00000008)
1058	/** X86 Mode: 16-bit protected mode on 386 or later. */
1059	#define IEM_F_MODE_X86_16BIT_PROT_PRE_386 UINT32_C(0x0000000c)
1060	/** X86 Mode: 16-bit virtual 8086 protected mode (on 386 or later). */
1061	#define IEM_F_MODE_X86_16BIT_PROT_V86 UINT32_C(0x00000018)
1062
1063	/** X86 Mode: 32-bit on 386 or later. */
1064	#define IEM_F_MODE_X86_32BIT UINT32_C(0x00000001)
1065	/** X86 Mode: 32-bit mode with wide open flat CS, SS, DS and ES. */
1066	#define IEM_F_MODE_X86_32BIT_FLAT UINT32_C(0x00000005)
1067	/** X86 Mode: 32-bit protected mode. */
1068	#define IEM_F_MODE_X86_32BIT_PROT UINT32_C(0x00000009)
1069	/** X86 Mode: 32-bit protected mode with wide open flat CS, SS, DS and ES. */
1070	#define IEM_F_MODE_X86_32BIT_PROT_FLAT UINT32_C(0x0000000d)
1071
1072	/** X86 Mode: 64-bit (includes protected, but not the flat bit). */
1073	#define IEM_F_MODE_X86_64BIT UINT32_C(0x0000000a)
1074
1075	/** X86 Mode: Checks if @a a_fExec represent a FLAT mode. */
1076	#define IEM_F_MODE_X86_IS_FLAT(a_fExec) ( ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_64BIT \
1077	\|\| ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_32BIT_PROT_FLAT \
1078	\|\| ((a_fExec) & IEM_F_MODE_MASK) == IEM_F_MODE_X86_32BIT_FLAT)
1079
1080	/** Bypass access handlers when set. */
1081	#define IEM_F_BYPASS_HANDLERS UINT32_C(0x00010000)
1082	/** Have pending hardware instruction breakpoints. */
1083	#define IEM_F_PENDING_BRK_INSTR UINT32_C(0x00020000)
1084	/** Have pending hardware data breakpoints. */
1085	#define IEM_F_PENDING_BRK_DATA UINT32_C(0x00040000)
1086
1087	/** X86: Have pending hardware I/O breakpoints. */
1088	#define IEM_F_PENDING_BRK_X86_IO UINT32_C(0x00000400)
1089	/** X86: Disregard the lock prefix (implied or not) when set. */
1090	#define IEM_F_X86_DISREGARD_LOCK UINT32_C(0x00000800)
1091
1092	/** Pending breakpoint mask (what iemCalcExecDbgFlags works out). */
1093	#define IEM_F_PENDING_BRK_MASK (IEM_F_PENDING_BRK_INSTR \| IEM_F_PENDING_BRK_DATA \| IEM_F_PENDING_BRK_X86_IO)
1094
1095	/** Caller configurable options. */
1096	#define IEM_F_USER_OPTS (IEM_F_BYPASS_HANDLERS \| IEM_F_X86_DISREGARD_LOCK)
1097
1098	/** X86: The current protection level (CPL) shift factor. */
1099	#define IEM_F_X86_CPL_SHIFT 8
1100	/** X86: The current protection level (CPL) mask. */
1101	#define IEM_F_X86_CPL_MASK UINT32_C(0x00000300)
1102	/** X86: The current protection level (CPL) shifted mask. */
1103	#define IEM_F_X86_CPL_SMASK UINT32_C(0x00000003)
1104
1105	/** X86: Alignment checks enabled (CR0.AM=1 & EFLAGS.AC=1). */
1106	#define IEM_F_X86_AC UINT32_C(0x00080000)
1107
1108	/** X86 execution context.
1109	* The IEM_F_X86_CTX_XXX values are individual flags that can be combined (with
1110	* the exception of IEM_F_X86_CTX_NORMAL). This allows running VMs from SMM
1111	* mode. */
1112	#define IEM_F_X86_CTX_MASK UINT32_C(0x0000f000)
1113	/** X86 context: Plain regular execution context. */
1114	#define IEM_F_X86_CTX_NORMAL UINT32_C(0x00000000)
1115	/** X86 context: VT-x enabled. */
1116	#define IEM_F_X86_CTX_VMX UINT32_C(0x00001000)
1117	/** X86 context: AMD-V enabled. */
1118	#define IEM_F_X86_CTX_SVM UINT32_C(0x00002000)
1119	/** X86 context: In AMD-V or VT-x guest mode. */
1120	#define IEM_F_X86_CTX_IN_GUEST UINT32_C(0x00004000)
1121	/** X86 context: System management mode (SMM). */
1122	#define IEM_F_X86_CTX_SMM UINT32_C(0x00008000)
1123
1124	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
1125	* iemRegFinishClearingRF() most for most situations (CPUMCTX_DBG_HIT_DRX_MASK
1126	* and CPUMCTX_DBG_DBGF_MASK are covered by the IEM_F_PENDING_BRK_XXX bits
1127	* alread). */
1128
1129	/** @todo Add TF+RF+INHIBIT indicator(s), so we can eliminate the conditional in
1130	* iemRegFinishClearingRF() most for most situations
1131	* (CPUMCTX_DBG_HIT_DRX_MASK and CPUMCTX_DBG_DBGF_MASK are covered by
1132	* the IEM_F_PENDING_BRK_XXX bits alread). */
1133
1134	/** @} */
1135
1136
1137	/** @name IEMTB_F_XXX - Translation block flags (IEMTB::fFlags).
1138	*
1139	* Extends the IEM_F_XXX flags (subject to IEMTB_F_IEM_F_MASK) to make up the
1140	* translation block flags. The combined flag mask (subject to
1141	* IEMTB_F_KEY_MASK) is used as part of the lookup key for translation blocks.
1142	*
1143	* @{ */
1144	/** Mask of IEM_F_XXX flags included in IEMTB_F_XXX. */
1145	#define IEMTB_F_IEM_F_MASK UINT32_C(0x00ffffff)
1146
1147	/** Type: The block type mask. */
1148	#define IEMTB_F_TYPE_MASK UINT32_C(0x03000000)
1149	/** Type: Purly threaded recompiler (via tables). */
1150	#define IEMTB_F_TYPE_THREADED UINT32_C(0x01000000)
1151	/** Type: Native recompilation. */
1152	#define IEMTB_F_TYPE_NATIVE UINT32_C(0x02000000)
1153
1154	/** Set when we're starting the block in an "interrupt shadow".
1155	* We don't need to distingish between the two types of this mask, thus the one.
1156	* @see CPUMCTX_INHIBIT_SHADOW, CPUMIsInInterruptShadow() */
1157	#define IEMTB_F_INHIBIT_SHADOW UINT32_C(0x04000000)
1158	/** Set when we're currently inhibiting NMIs
1159	* @see CPUMCTX_INHIBIT_NMI, CPUMAreInterruptsInhibitedByNmi() */
1160	#define IEMTB_F_INHIBIT_NMI UINT32_C(0x08000000)
1161
1162	/** Checks that EIP/IP is wihin CS.LIM before each instruction. Used when
1163	* we're close the limit before starting a TB, as determined by
1164	* iemGetTbFlagsForCurrentPc(). */
1165	#define IEMTB_F_CS_LIM_CHECKS UINT32_C(0x10000000)
1166
1167	/** Mask of the IEMTB_F_XXX flags that are part of the TB lookup key.
1168	*
1169	* @note We skip all of IEM_F_X86_CTX_MASK, with the exception of SMM (which we
1170	* don't implement), because we don't currently generate any context
1171	* specific code - that's all handled in CIMPL functions.
1172	*
1173	* For the threaded recompiler we don't generate any CPL specific code
1174	* either, but the native recompiler does for memory access (saves getting
1175	* the CPL from fExec and turning it into IEMTLBE_F_PT_NO_USER).
1176	* Since most OSes will not share code between rings, this shouldn't
1177	* have any real effect on TB/memory/recompiling load.
1178	*/
1179	#define IEMTB_F_KEY_MASK ((UINT32_MAX & ~(IEM_F_X86_CTX_MASK \| IEMTB_F_TYPE_MASK)) \| IEM_F_X86_CTX_SMM)
1180	/** @} */
1181
1182	AssertCompile( (IEM_F_MODE_X86_16BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
1183	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
1184	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_PROT_MASK));
1185	AssertCompile(!(IEM_F_MODE_X86_16BIT & IEM_F_MODE_X86_V86_MASK));
1186	AssertCompile( (IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
1187	AssertCompile( IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
1188	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_PROT_MASK));
1189	AssertCompile(!(IEM_F_MODE_X86_16BIT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
1190	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
1191	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
1192	AssertCompile( IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
1193	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT & IEM_F_MODE_X86_V86_MASK));
1194	AssertCompile( (IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_16BIT);
1195	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
1196	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_PROT_MASK);
1197	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_PRE_386 & IEM_F_MODE_X86_V86_MASK));
1198	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_PROT_MASK);
1199	AssertCompile(!(IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
1200	AssertCompile( IEM_F_MODE_X86_16BIT_PROT_V86 & IEM_F_MODE_X86_V86_MASK);
1201
1202	AssertCompile( (IEM_F_MODE_X86_32BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
1203	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
1204	AssertCompile(!(IEM_F_MODE_X86_32BIT & IEM_F_MODE_X86_PROT_MASK));
1205	AssertCompile( (IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
1206	AssertCompile( IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
1207	AssertCompile(!(IEM_F_MODE_X86_32BIT_FLAT & IEM_F_MODE_X86_PROT_MASK));
1208	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
1209	AssertCompile(!(IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
1210	AssertCompile( IEM_F_MODE_X86_32BIT_PROT & IEM_F_MODE_X86_PROT_MASK);
1211	AssertCompile( (IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT);
1212	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK);
1213	AssertCompile( IEM_F_MODE_X86_32BIT_PROT_FLAT & IEM_F_MODE_X86_PROT_MASK);
1214
1215	AssertCompile( (IEM_F_MODE_X86_64BIT & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_64BIT);
1216	AssertCompile( IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_PROT_MASK);
1217	AssertCompile(!(IEM_F_MODE_X86_64BIT & IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK));
1218
1219	/** Native instruction type for use with the native code generator.
1220	* This is a byte (uint8_t) for x86 and amd64 and uint32_t for the other(s). */
1221	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
1222	typedef uint8_t IEMNATIVEINSTR;
1223	#else
1224	typedef uint32_t IEMNATIVEINSTR;
1225	#endif
1226	/** Pointer to a native instruction unit. */
1227	typedef IEMNATIVEINSTR *PIEMNATIVEINSTR;
1228	/** Pointer to a const native instruction unit. */
1229	typedef IEMNATIVEINSTR const *PCIEMNATIVEINSTR;
1230
1231	/**
1232	* A call for the threaded call table.
1233	*/
1234	typedef struct IEMTHRDEDCALLENTRY
1235	{
1236	/** The function to call (IEMTHREADEDFUNCS). */
1237	uint16_t enmFunction;
1238
1239	/** Instruction number in the TB (for statistics). */
1240	uint8_t idxInstr;
1241	/** The opcode length. */
1242	uint8_t cbOpcode;
1243	/** Offset into IEMTB::pabOpcodes. */
1244	uint16_t offOpcode;
1245
1246	/** TB lookup table index (7 bits) and large size (1 bits).
1247	*
1248	* The default size is 1 entry, but for indirect calls and returns we set the
1249	* top bit and allocate 4 (IEM_TB_LOOKUP_TAB_LARGE_SIZE) entries. The large
1250	* tables uses RIP for selecting the entry to use, as it is assumed a hash table
1251	* lookup isn't that slow compared to sequentially trying out 4 TBs.
1252	*
1253	* By default lookup table entry 0 for a TB is reserved as a fallback for
1254	* calltable entries w/o explicit entreis, so this member will be non-zero if
1255	* there is a lookup entry associated with this call.
1256	*
1257	* @sa IEM_TB_LOOKUP_TAB_GET_SIZE, IEM_TB_LOOKUP_TAB_GET_IDX
1258	*/
1259	uint8_t uTbLookup;
1260
1261	/** Flags - IEMTHREADEDCALLENTRY_F_XXX. */
1262	uint8_t fFlags;
1263
1264	/** Generic parameters. */
1265	uint64_t auParams[3];
1266	} IEMTHRDEDCALLENTRY;
1267	AssertCompileSize(IEMTHRDEDCALLENTRY, sizeof(uint64_t) * 4);
1268	/** Pointer to a threaded call entry. */
1269	typedef struct IEMTHRDEDCALLENTRY *PIEMTHRDEDCALLENTRY;
1270	/** Pointer to a const threaded call entry. */
1271	typedef IEMTHRDEDCALLENTRY const *PCIEMTHRDEDCALLENTRY;
1272
1273	/** The number of TB lookup table entries for a large allocation
1274	* (IEMTHRDEDCALLENTRY::uTbLookup bit 7 set). */
1275	#define IEM_TB_LOOKUP_TAB_LARGE_SIZE 4
1276	/** Get the lookup table size from IEMTHRDEDCALLENTRY::uTbLookup. */
1277	#define IEM_TB_LOOKUP_TAB_GET_SIZE(a_uTbLookup) (!((a_uTbLookup) & 0x80) ? 1 : IEM_TB_LOOKUP_TAB_LARGE_SIZE)
1278	/** Get the first lookup table index from IEMTHRDEDCALLENTRY::uTbLookup. */
1279	#define IEM_TB_LOOKUP_TAB_GET_IDX(a_uTbLookup) ((a_uTbLookup) & 0x7f)
1280	/** Get the lookup table index from IEMTHRDEDCALLENTRY::uTbLookup and RIP. */
1281	#define IEM_TB_LOOKUP_TAB_GET_IDX_WITH_RIP(a_uTbLookup, a_Rip) \
1282	(!((a_uTbLookup) & 0x80) ? (a_uTbLookup) & 0x7f : ((a_uTbLookup) & 0x7f) + ((a_Rip) & (IEM_TB_LOOKUP_TAB_LARGE_SIZE - 1)) )
1283
1284	/** Make a IEMTHRDEDCALLENTRY::uTbLookup value. */
1285	#define IEM_TB_LOOKUP_TAB_MAKE(a_idxTable, a_fLarge) ((a_idxTable) \| ((a_fLarge) ? 0x80 : 0))
1286
1287
1288	/** The call entry is a jump target. */
1289	#define IEMTHREADEDCALLENTRY_F_JUMP_TARGET UINT8_C(0x01)
1290
1291
1292	/**
1293	* Native IEM TB 'function' typedef.
1294	*
1295	* This will throw/longjmp on occation.
1296	*
1297	* @note AMD64 doesn't have that many non-volatile registers and does sport
1298	* 32-bit address displacments, so we don't need pCtx.
1299	*
1300	* On ARM64 pCtx allows us to directly address the whole register
1301	* context without requiring a separate indexing register holding the
1302	* offset. This saves an instruction loading the offset for each guest
1303	* CPU context access, at the cost of a non-volatile register.
1304	* Fortunately, ARM64 has quite a lot more registers.
1305	*/
1306	typedef
1307	#ifdef RT_ARCH_AMD64
1308	int FNIEMTBNATIVE(PVMCPUCC pVCpu)
1309	#else
1310	int FNIEMTBNATIVE(PVMCPUCC pVCpu, PCPUMCTX pCtx)
1311	#endif
1312	#if RT_CPLUSPLUS_PREREQ(201700)
1313	IEM_NOEXCEPT_MAY_LONGJMP
1314	#endif
1315	;
1316	/** Pointer to a native IEM TB entry point function.
1317	* This will throw/longjmp on occation. */
1318	typedef FNIEMTBNATIVE *PFNIEMTBNATIVE;
1319
1320
1321	/**
1322	* Translation block debug info entry type.
1323	*/
1324	typedef enum IEMTBDBGENTRYTYPE
1325	{
1326	kIemTbDbgEntryType_Invalid = 0,
1327	/** The entry is for marking a native code position.
1328	* Entries following this all apply to this position. */
1329	kIemTbDbgEntryType_NativeOffset,
1330	/** The entry is for a new guest instruction. */
1331	kIemTbDbgEntryType_GuestInstruction,
1332	/** Marks the start of a threaded call. */
1333	kIemTbDbgEntryType_ThreadedCall,
1334	/** Marks the location of a label. */
1335	kIemTbDbgEntryType_Label,
1336	/** Info about a host register shadowing a guest register. */
1337	kIemTbDbgEntryType_GuestRegShadowing,
1338	#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
1339	/** Info about a host SIMD register shadowing a guest SIMD register. */
1340	kIemTbDbgEntryType_GuestSimdRegShadowing,
1341	#endif
1342	#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING
1343	/** Info about a delayed RIP update. */
1344	kIemTbDbgEntryType_DelayedPcUpdate,
1345	#endif
1346	#if defined(IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK) \|\| defined(IEMNATIVE_WITH_SIMD_REG_ALLOCATOR)
1347	/** Info about a shadowed guest register becoming dirty. */
1348	kIemTbDbgEntryType_GuestRegDirty,
1349	/** Info about register writeback/flush oepration. */
1350	kIemTbDbgEntryType_GuestRegWriteback,
1351	#endif
1352	kIemTbDbgEntryType_End
1353	} IEMTBDBGENTRYTYPE;
1354
1355	/**
1356	* Translation block debug info entry.
1357	*/
1358	typedef union IEMTBDBGENTRY
1359	{
1360	/** Plain 32-bit view. */
1361	uint32_t u;
1362
1363	/** Generic view for getting at the type field. */
1364	struct
1365	{
1366	/** IEMTBDBGENTRYTYPE */
1367	uint32_t uType : 4;
1368	uint32_t uTypeSpecific : 28;
1369	} Gen;
1370
1371	struct
1372	{
1373	/** kIemTbDbgEntryType_ThreadedCall1. */
1374	uint32_t uType : 4;
1375	/** Native code offset. */
1376	uint32_t offNative : 28;
1377	} NativeOffset;
1378
1379	struct
1380	{
1381	/** kIemTbDbgEntryType_GuestInstruction. */
1382	uint32_t uType : 4;
1383	uint32_t uUnused : 4;
1384	/** The IEM_F_XXX flags. */
1385	uint32_t fExec : 24;
1386	} GuestInstruction;
1387
1388	struct
1389	{
1390	/* kIemTbDbgEntryType_ThreadedCall. */
1391	uint32_t uType : 4;
1392	/** Set if the call was recompiled to native code, clear if just calling
1393	* threaded function. */
1394	uint32_t fRecompiled : 1;
1395	uint32_t uUnused : 11;
1396	/** The threaded call number (IEMTHREADEDFUNCS). */
1397	uint32_t enmCall : 16;
1398	} ThreadedCall;
1399
1400	struct
1401	{
1402	/* kIemTbDbgEntryType_Label. */
1403	uint32_t uType : 4;
1404	uint32_t uUnused : 4;
1405	/** The label type (IEMNATIVELABELTYPE). */
1406	uint32_t enmLabel : 8;
1407	/** The label data. */
1408	uint32_t uData : 16;
1409	} Label;
1410
1411	struct
1412	{
1413	/* kIemTbDbgEntryType_GuestRegShadowing. */
1414	uint32_t uType : 4;
1415	uint32_t uUnused : 4;
1416	/** The guest register being shadowed (IEMNATIVEGSTREG). */
1417	uint32_t idxGstReg : 8;
1418	/** The host new register number, UINT8_MAX if dropped. */
1419	uint32_t idxHstReg : 8;
1420	/** The previous host register number, UINT8_MAX if new. */
1421	uint32_t idxHstRegPrev : 8;
1422	} GuestRegShadowing;
1423
1424	#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
1425	struct
1426	{
1427	/* kIemTbDbgEntryType_GuestSimdRegShadowing. */
1428	uint32_t uType : 4;
1429	uint32_t uUnused : 4;
1430	/** The guest register being shadowed (IEMNATIVEGSTSIMDREG). */
1431	uint32_t idxGstSimdReg : 8;
1432	/** The host new register number, UINT8_MAX if dropped. */
1433	uint32_t idxHstSimdReg : 8;
1434	/** The previous host register number, UINT8_MAX if new. */
1435	uint32_t idxHstSimdRegPrev : 8;
1436	} GuestSimdRegShadowing;
1437	#endif
1438
1439	#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING
1440	struct
1441	{
1442	/* kIemTbDbgEntryType_DelayedPcUpdate. */
1443	uint32_t uType : 4;
1444	/* The instruction offset added to the program counter. */
1445	uint32_t offPc : 14;
1446	/** Number of instructions skipped. */
1447	uint32_t cInstrSkipped : 14;
1448	} DelayedPcUpdate;
1449	#endif
1450
1451	#if defined(IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK) \|\| defined(IEMNATIVE_WITH_SIMD_REG_ALLOCATOR)
1452	struct
1453	{
1454	/* kIemTbDbgEntryType_GuestRegDirty. */
1455	uint32_t uType : 4;
1456	uint32_t uUnused : 11;
1457	/** Flag whether this is about a SIMD (true) or general (false) register. */
1458	uint32_t fSimdReg : 1;
1459	/** The guest register index being marked as dirty. */
1460	uint32_t idxGstReg : 8;
1461	/** The host register number this register is shadowed in .*/
1462	uint32_t idxHstReg : 8;
1463	} GuestRegDirty;
1464
1465	struct
1466	{
1467	/* kIemTbDbgEntryType_GuestRegWriteback. */
1468	uint32_t uType : 4;
1469	/** Flag whether this is about a SIMD (true) or general (false) register flush. */
1470	uint32_t fSimdReg : 1;
1471	/** The mask shift. */
1472	uint32_t cShift : 2;
1473	/** The guest register mask being written back. */
1474	uint32_t fGstReg : 25;
1475	} GuestRegWriteback;
1476	#endif
1477
1478	} IEMTBDBGENTRY;
1479	AssertCompileSize(IEMTBDBGENTRY, sizeof(uint32_t));
1480	/** Pointer to a debug info entry. */
1481	typedef IEMTBDBGENTRY *PIEMTBDBGENTRY;
1482	/** Pointer to a const debug info entry. */
1483	typedef IEMTBDBGENTRY const *PCIEMTBDBGENTRY;
1484
1485	/**
1486	* Translation block debug info.
1487	*/
1488	typedef struct IEMTBDBG
1489	{
1490	/** Number of entries in aEntries. */
1491	uint32_t cEntries;
1492	/** The offset of the last kIemTbDbgEntryType_NativeOffset record. */
1493	uint32_t offNativeLast;
1494	/** Debug info entries. */
1495	RT_FLEXIBLE_ARRAY_EXTENSION
1496	IEMTBDBGENTRY aEntries[RT_FLEXIBLE_ARRAY];
1497	} IEMTBDBG;
1498	/** Pointer to TB debug info. */
1499	typedef IEMTBDBG *PIEMTBDBG;
1500	/** Pointer to const TB debug info. */
1501	typedef IEMTBDBG const *PCIEMTBDBG;
1502
1503
1504	/**
1505	* Translation block.
1506	*
1507	* The current plan is to just keep TBs and associated lookup hash table private
1508	* to each VCpu as that simplifies TB removal greatly (no races) and generally
1509	* avoids using expensive atomic primitives for updating lists and stuff.
1510	*/
1511	#pragma pack(2) /* to prevent the Thrd structure from being padded unnecessarily */
1512	typedef struct IEMTB
1513	{
1514	/** Next block with the same hash table entry. */
1515	struct IEMTB *pNext;
1516	/** Usage counter. */
1517	uint32_t cUsed;
1518	/** The IEMCPU::msRecompilerPollNow last time it was used. */
1519	uint32_t msLastUsed;
1520
1521	/** @name What uniquely identifies the block.
1522	* @{ */
1523	RTGCPHYS GCPhysPc;
1524	/** IEMTB_F_XXX (i.e. IEM_F_XXX ++). */
1525	uint32_t fFlags;
1526	union
1527	{
1528	struct
1529	{
1530	/*< Relevant CS X86DESCATTR_XXX bits. /
1531	uint16_t fAttr;
1532	} x86;
1533	};
1534	/** @} */
1535
1536	/** Number of opcode ranges. */
1537	uint8_t cRanges;
1538	/** Statistics: Number of instructions in the block. */
1539	uint8_t cInstructions;
1540
1541	/** Type specific info. */
1542	union
1543	{
1544	struct
1545	{
1546	/** The call sequence table. */
1547	PIEMTHRDEDCALLENTRY paCalls;
1548	/** Number of calls in paCalls. */
1549	uint16_t cCalls;
1550	/** Number of calls allocated. */
1551	uint16_t cAllocated;
1552	} Thrd;
1553	struct
1554	{
1555	/** The native instructions (PFNIEMTBNATIVE). */
1556	PIEMNATIVEINSTR paInstructions;
1557	/** Number of instructions pointed to by paInstructions. */
1558	uint32_t cInstructions;
1559	} Native;
1560	/** Generic view for zeroing when freeing. */
1561	struct
1562	{
1563	uintptr_t uPtr;
1564	uint32_t uData;
1565	} Gen;
1566	};
1567
1568	/** The allocation chunk this TB belongs to. */
1569	uint8_t idxAllocChunk;
1570	/** The number of entries in the lookup table.
1571	* Because we're out of space, the TB lookup table is located before the
1572	* opcodes pointed to by pabOpcodes. */
1573	uint8_t cTbLookupEntries;
1574
1575	/** Number of bytes of opcodes stored in pabOpcodes.
1576	* @todo this field isn't really needed, aRanges keeps the actual info. */
1577	uint16_t cbOpcodes;
1578	/** Pointer to the opcode bytes this block was recompiled from.
1579	* This also points to the TB lookup table, which starts cTbLookupEntries
1580	* entries before the opcodes (we don't have room atm for another point). */
1581	uint8_t *pabOpcodes;
1582
1583	/** Debug info if enabled.
1584	* This is only generated by the native recompiler. */
1585	PIEMTBDBG pDbgInfo;
1586
1587	/* --- 64 byte cache line end --- */
1588
1589	/** Opcode ranges.
1590	*
1591	* The opcode checkers and maybe TLB loading functions will use this to figure
1592	* out what to do. The parameter will specify an entry and the opcode offset to
1593	* start at and the minimum number of bytes to verify (instruction length).
1594	*
1595	* When VT-x and AMD-V looks up the opcode bytes for an exitting instruction,
1596	* they'll first translate RIP (+ cbInstr - 1) to a physical address using the
1597	* code TLB (must have a valid entry for that address) and scan the ranges to
1598	* locate the corresponding opcodes. Probably.
1599	*/
1600	struct IEMTBOPCODERANGE
1601	{
1602	/** Offset within pabOpcodes. */
1603	uint16_t offOpcodes;
1604	/** Number of bytes. */
1605	uint16_t cbOpcodes;
1606	/** The page offset. */
1607	RT_GCC_EXTENSION
1608	uint16_t offPhysPage : 12;
1609	/** Unused bits. */
1610	RT_GCC_EXTENSION
1611	uint16_t u2Unused : 2;
1612	/** Index into GCPhysPc + aGCPhysPages for the physical page address. */
1613	RT_GCC_EXTENSION
1614	uint16_t idxPhysPage : 2;
1615	} aRanges[8];
1616
1617	/** Physical pages that this TB covers.
1618	* The GCPhysPc w/o page offset is element zero, so starting here with 1. */
1619	RTGCPHYS aGCPhysPages[2];
1620	} IEMTB;
1621	#pragma pack()
1622	AssertCompileMemberAlignment(IEMTB, GCPhysPc, sizeof(RTGCPHYS));
1623	AssertCompileMemberAlignment(IEMTB, Thrd, sizeof(void *));
1624	AssertCompileMemberAlignment(IEMTB, pabOpcodes, sizeof(void *));
1625	AssertCompileMemberAlignment(IEMTB, pDbgInfo, sizeof(void *));
1626	AssertCompileMemberAlignment(IEMTB, aGCPhysPages, sizeof(RTGCPHYS));
1627	AssertCompileMemberOffset(IEMTB, aRanges, 64);
1628	AssertCompileMemberSize(IEMTB, aRanges[0], 6);
1629	#if 1
1630	AssertCompileSize(IEMTB, 128);
1631	# define IEMTB_SIZE_IS_POWER_OF_TWO /*< The IEMTB size is a power of two. /
1632	#else
1633	AssertCompileSize(IEMTB, 168);
1634	# undef IEMTB_SIZE_IS_POWER_OF_TWO
1635	#endif
1636
1637	/** Pointer to a translation block. */
1638	typedef IEMTB *PIEMTB;
1639	/** Pointer to a const translation block. */
1640	typedef IEMTB const *PCIEMTB;
1641
1642	/** Gets address of the given TB lookup table entry. */
1643	#define IEMTB_GET_TB_LOOKUP_TAB_ENTRY(a_pTb, a_idx) \
1644	((PIEMTB )&(a_pTb)->pabOpcodes[-(int)((a_pTb)->cTbLookupEntries - (a_idx)) sizeof(PIEMTB)])
1645
1646	/**
1647	* Gets the physical address for a TB opcode range.
1648	*/
1649	DECL_FORCE_INLINE(RTGCPHYS) iemTbGetRangePhysPageAddr(PCIEMTB pTb, uint8_t idxRange)
1650	{
1651	Assert(idxRange < RT_MIN(pTb->cRanges, RT_ELEMENTS(pTb->aRanges)));
1652	uint8_t const idxPage = pTb->aRanges[idxRange].idxPhysPage;
1653	Assert(idxPage <= RT_ELEMENTS(pTb->aGCPhysPages));
1654	if (idxPage == 0)
1655	return pTb->GCPhysPc & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
1656	Assert(!(pTb->aGCPhysPages[idxPage - 1] & GUEST_PAGE_OFFSET_MASK));
1657	return pTb->aGCPhysPages[idxPage - 1];
1658	}
1659
1660
1661	/**
1662	* A chunk of memory in the TB allocator.
1663	*/
1664	typedef struct IEMTBCHUNK
1665	{
1666	/** Pointer to the translation blocks in this chunk. */
1667	PIEMTB paTbs;
1668	#ifdef IN_RING0
1669	/** Allocation handle. */
1670	RTR0MEMOBJ hMemObj;
1671	#endif
1672	} IEMTBCHUNK;
1673
1674	/**
1675	* A per-CPU translation block allocator.
1676	*
1677	* Because of how the IEMTBCACHE uses the lower 6 bits of the TB address to keep
1678	* the length of the collision list, and of course also for cache line alignment
1679	* reasons, the TBs must be allocated with at least 64-byte alignment.
1680	* Memory is there therefore allocated using one of the page aligned allocators.
1681	*
1682	*
1683	* To avoid wasting too much memory, it is allocated piecemeal as needed,
1684	* in chunks (IEMTBCHUNK) of 2 MiB or more. The TB has an 8-bit chunk index
1685	* that enables us to quickly calculate the allocation bitmap position when
1686	* freeing the translation block.
1687	*/
1688	typedef struct IEMTBALLOCATOR
1689	{
1690	/** Magic value (IEMTBALLOCATOR_MAGIC). */
1691	uint32_t uMagic;
1692
1693	#ifdef IEMTB_SIZE_IS_POWER_OF_TWO
1694	/** Mask corresponding to cTbsPerChunk - 1. */
1695	uint32_t fChunkMask;
1696	/** Shift count corresponding to cTbsPerChunk. */
1697	uint8_t cChunkShift;
1698	#else
1699	uint32_t uUnused;
1700	uint8_t bUnused;
1701	#endif
1702	/** Number of chunks we're allowed to allocate. */
1703	uint8_t cMaxChunks;
1704	/** Number of chunks currently populated. */
1705	uint16_t cAllocatedChunks;
1706	/** Number of translation blocks per chunk. */
1707	uint32_t cTbsPerChunk;
1708	/** Chunk size. */
1709	uint32_t cbPerChunk;
1710
1711	/** The maximum number of TBs. */
1712	uint32_t cMaxTbs;
1713	/** Total number of TBs in the populated chunks.
1714	* (cAllocatedChunks * cTbsPerChunk) */
1715	uint32_t cTotalTbs;
1716	/** The current number of TBs in use.
1717	* The number of free TBs: cAllocatedTbs - cInUseTbs; */
1718	uint32_t cInUseTbs;
1719	/** Statistics: Number of the cInUseTbs that are native ones. */
1720	uint32_t cNativeTbs;
1721	/** Statistics: Number of the cInUseTbs that are threaded ones. */
1722	uint32_t cThreadedTbs;
1723
1724	/** Where to start pruning TBs from when we're out.
1725	* See iemTbAllocatorAllocSlow for details. */
1726	uint32_t iPruneFrom;
1727	/** Where to start pruning native TBs from when we're out of executable memory.
1728	* See iemTbAllocatorFreeupNativeSpace for details. */
1729	uint32_t iPruneNativeFrom;
1730	uint64_t u64Padding;
1731
1732	/** Statistics: Number of TB allocation calls. */
1733	STAMCOUNTER StatAllocs;
1734	/** Statistics: Number of TB free calls. */
1735	STAMCOUNTER StatFrees;
1736	/** Statistics: Time spend pruning. */
1737	STAMPROFILE StatPrune;
1738	/** Statistics: Time spend pruning native TBs. */
1739	STAMPROFILE StatPruneNative;
1740
1741	/** The delayed free list (see iemTbAlloctorScheduleForFree). */
1742	PIEMTB pDelayedFreeHead;
1743	/* Head of the list of free TBs. */
1744	PIEMTB pTbsFreeHead;
1745
1746	/** Allocation chunks. */
1747	IEMTBCHUNK aChunks[256];
1748	} IEMTBALLOCATOR;
1749	/** Pointer to a TB allocator. */
1750	typedef struct IEMTBALLOCATOR *PIEMTBALLOCATOR;
1751
1752	/** Magic value for the TB allocator (Emmet Harley Cohen). */
1753	#define IEMTBALLOCATOR_MAGIC UINT32_C(0x19900525)
1754
1755
1756	/**
1757	* A per-CPU translation block cache (hash table).
1758	*
1759	* The hash table is allocated once during IEM initialization and size double
1760	* the max TB count, rounded up to the nearest power of two (so we can use and
1761	* AND mask rather than a rest division when hashing).
1762	*/
1763	typedef struct IEMTBCACHE
1764	{
1765	/** Magic value (IEMTBCACHE_MAGIC). */
1766	uint32_t uMagic;
1767	/** Size of the hash table. This is a power of two. */
1768	uint32_t cHash;
1769	/** The mask corresponding to cHash. */
1770	uint32_t uHashMask;
1771	uint32_t uPadding;
1772
1773	/** @name Statistics
1774	* @{ */
1775	/** Number of collisions ever. */
1776	STAMCOUNTER cCollisions;
1777
1778	/** Statistics: Number of TB lookup misses. */
1779	STAMCOUNTER cLookupMisses;
1780	/** Statistics: Number of TB lookup hits via hash table (debug only). */
1781	STAMCOUNTER cLookupHits;
1782	/** Statistics: Number of TB lookup hits via TB associated lookup table (debug only). */
1783	STAMCOUNTER cLookupHitsViaTbLookupTable;
1784	STAMCOUNTER auPadding2[2];
1785	/** Statistics: Collision list length pruning. */
1786	STAMPROFILE StatPrune;
1787	/** @} */
1788
1789	/** The hash table itself.
1790	* @note The lower 6 bits of the pointer is used for keeping the collision
1791	* list length, so we can take action when it grows too long.
1792	* This works because TBs are allocated using a 64 byte (or
1793	* higher) alignment from page aligned chunks of memory, so the lower
1794	* 6 bits of the address will always be zero.
1795	* See IEMTBCACHE_PTR_COUNT_MASK, IEMTBCACHE_PTR_MAKE and friends.
1796	*/
1797	RT_FLEXIBLE_ARRAY_EXTENSION
1798	PIEMTB apHash[RT_FLEXIBLE_ARRAY];
1799	} IEMTBCACHE;
1800	/** Pointer to a per-CPU translation block cahce. */
1801	typedef IEMTBCACHE *PIEMTBCACHE;
1802
1803	/** Magic value for IEMTBCACHE (Johnny O'Neal). */
1804	#define IEMTBCACHE_MAGIC UINT32_C(0x19561010)
1805
1806	/** The collision count mask for IEMTBCACHE::apHash entries. */
1807	#define IEMTBCACHE_PTR_COUNT_MASK ((uintptr_t)0x3f)
1808	/** The max collision count for IEMTBCACHE::apHash entries before pruning. */
1809	#define IEMTBCACHE_PTR_MAX_COUNT ((uintptr_t)0x30)
1810	/** Combine a TB pointer and a collision list length into a value for an
1811	* IEMTBCACHE::apHash entry. */
1812	#define IEMTBCACHE_PTR_MAKE(a_pTb, a_cCount) (PIEMTB)((uintptr_t)(a_pTb) \| (a_cCount))
1813	/** Combine a TB pointer and a collision list length into a value for an
1814	* IEMTBCACHE::apHash entry. */
1815	#define IEMTBCACHE_PTR_GET_TB(a_pHashEntry) (PIEMTB)((uintptr_t)(a_pHashEntry) & ~IEMTBCACHE_PTR_COUNT_MASK)
1816	/** Combine a TB pointer and a collision list length into a value for an
1817	* IEMTBCACHE::apHash entry. */
1818	#define IEMTBCACHE_PTR_GET_COUNT(a_pHashEntry) ((uintptr_t)(a_pHashEntry) & IEMTBCACHE_PTR_COUNT_MASK)
1819
1820	/**
1821	* Calculates the hash table slot for a TB from physical PC address and TB flags.
1822	*/
1823	#define IEMTBCACHE_HASH(a_paCache, a_fTbFlags, a_GCPhysPc) \
1824	IEMTBCACHE_HASH_NO_KEY_MASK(a_paCache, (a_fTbFlags) & IEMTB_F_KEY_MASK, a_GCPhysPc)
1825
1826	/**
1827	* Calculates the hash table slot for a TB from physical PC address and TB
1828	* flags, ASSUMING the caller has applied IEMTB_F_KEY_MASK to @a a_fTbFlags.
1829	*/
1830	#define IEMTBCACHE_HASH_NO_KEY_MASK(a_paCache, a_fTbFlags, a_GCPhysPc) \
1831	(((uint32_t)(a_GCPhysPc) ^ (a_fTbFlags)) & (a_paCache)->uHashMask)
1832
1833
1834	/** @name IEMBRANCHED_F_XXX - Branched indicator (IEMCPU::fTbBranched).
1835	*
1836	* These flags parallels the main IEM_CIMPL_F_BRANCH_XXX flags.
1837	*
1838	* @{ */
1839	/** Value if no branching happened recently. */
1840	#define IEMBRANCHED_F_NO UINT8_C(0x00)
1841	/** Flag set if direct branch, clear if absolute or indirect. */
1842	#define IEMBRANCHED_F_DIRECT UINT8_C(0x01)
1843	/** Flag set if indirect branch, clear if direct or relative. */
1844	#define IEMBRANCHED_F_INDIRECT UINT8_C(0x02)
1845	/** Flag set if relative branch, clear if absolute or indirect. */
1846	#define IEMBRANCHED_F_RELATIVE UINT8_C(0x04)
1847	/** Flag set if conditional branch, clear if unconditional. */
1848	#define IEMBRANCHED_F_CONDITIONAL UINT8_C(0x08)
1849	/** Flag set if it's a far branch. */
1850	#define IEMBRANCHED_F_FAR UINT8_C(0x10)
1851	/** Flag set if the stack pointer is modified. */
1852	#define IEMBRANCHED_F_STACK UINT8_C(0x20)
1853	/** Flag set if the stack pointer and (maybe) the stack segment are modified. */
1854	#define IEMBRANCHED_F_STACK_FAR UINT8_C(0x40)
1855	/** Flag set (by IEM_MC_REL_JMP_XXX) if it's a zero bytes relative jump. */
1856	#define IEMBRANCHED_F_ZERO UINT8_C(0x80)
1857	/** @} */
1858
1859
1860	/**
1861	* The per-CPU IEM state.
1862	*/
1863	typedef struct IEMCPU
1864	{
1865	/** Info status code that needs to be propagated to the IEM caller.
1866	* This cannot be passed internally, as it would complicate all success
1867	* checks within the interpreter making the code larger and almost impossible
1868	* to get right. Instead, we'll store status codes to pass on here. Each
1869	* source of these codes will perform appropriate sanity checks. */
1870	int32_t rcPassUp; /* 0x00 */
1871	/** Execution flag, IEM_F_XXX. */
1872	uint32_t fExec; /* 0x04 */
1873
1874	/** @name Decoder state.
1875	* @{ */
1876	#ifdef IEM_WITH_CODE_TLB
1877	/** The offset of the next instruction byte. */
1878	uint32_t offInstrNextByte; /* 0x08 */
1879	/** The number of bytes available at pbInstrBuf for the current instruction.
1880	* This takes the max opcode length into account so that doesn't need to be
1881	* checked separately. */
1882	uint32_t cbInstrBuf; /* 0x0c */
1883	/** Pointer to the page containing RIP, user specified buffer or abOpcode.
1884	* This can be NULL if the page isn't mappable for some reason, in which
1885	* case we'll do fallback stuff.
1886	*
1887	* If we're executing an instruction from a user specified buffer,
1888	* IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
1889	* aligned pointer but pointer to the user data.
1890	*
1891	* For instructions crossing pages, this will start on the first page and be
1892	* advanced to the next page by the time we've decoded the instruction. This
1893	* therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
1894	*/
1895	uint8_t const pbInstrBuf; / 0x10 */
1896	# if ARCH_BITS == 32
1897	uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
1898	# endif
1899	/** The program counter corresponding to pbInstrBuf.
1900	* This is set to a non-canonical address when we need to invalidate it. */
1901	uint64_t uInstrBufPc; /* 0x18 */
1902	/** The guest physical address corresponding to pbInstrBuf. */
1903	RTGCPHYS GCPhysInstrBuf; /* 0x20 */
1904	/** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
1905	* This takes the CS segment limit into account.
1906	* @note Set to zero when the code TLB is flushed to trigger TLB reload. */
1907	uint16_t cbInstrBufTotal; /* 0x28 */
1908	/** Offset into pbInstrBuf of the first byte of the current instruction.
1909	* Can be negative to efficiently handle cross page instructions. */
1910	int16_t offCurInstrStart; /* 0x2a */
1911
1912	# ifndef IEM_WITH_OPAQUE_DECODER_STATE
1913	/** The prefix mask (IEM_OP_PRF_XXX). */
1914	uint32_t fPrefixes; /* 0x2c */
1915	/** The extra REX ModR/M register field bit (REX.R << 3). */
1916	uint8_t uRexReg; /* 0x30 */
1917	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
1918	* (REX.B << 3). */
1919	uint8_t uRexB; /* 0x31 */
1920	/** The extra REX SIB index field bit (REX.X << 3). */
1921	uint8_t uRexIndex; /* 0x32 */
1922
1923	/** The effective segment register (X86_SREG_XXX). */
1924	uint8_t iEffSeg; /* 0x33 */
1925
1926	/** The offset of the ModR/M byte relative to the start of the instruction. */
1927	uint8_t offModRm; /* 0x34 */
1928
1929	# ifdef IEM_WITH_CODE_TLB_AND_OPCODE_BUF
1930	/** The current offset into abOpcode. */
1931	uint8_t offOpcode; /* 0x35 */
1932	# else
1933	uint8_t bUnused; /* 0x35 */
1934	# endif
1935	# else /* IEM_WITH_OPAQUE_DECODER_STATE */
1936	uint8_t abOpaqueDecoderPart1[0x36 - 0x2c];
1937	# endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1938
1939	#else /* !IEM_WITH_CODE_TLB */
1940	# ifndef IEM_WITH_OPAQUE_DECODER_STATE
1941	/** The size of what has currently been fetched into abOpcode. */
1942	uint8_t cbOpcode; /* 0x08 */
1943	/** The current offset into abOpcode. */
1944	uint8_t offOpcode; /* 0x09 */
1945	/** The offset of the ModR/M byte relative to the start of the instruction. */
1946	uint8_t offModRm; /* 0x0a */
1947
1948	/** The effective segment register (X86_SREG_XXX). */
1949	uint8_t iEffSeg; /* 0x0b */
1950
1951	/** The prefix mask (IEM_OP_PRF_XXX). */
1952	uint32_t fPrefixes; /* 0x0c */
1953	/** The extra REX ModR/M register field bit (REX.R << 3). */
1954	uint8_t uRexReg; /* 0x10 */
1955	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
1956	* (REX.B << 3). */
1957	uint8_t uRexB; /* 0x11 */
1958	/** The extra REX SIB index field bit (REX.X << 3). */
1959	uint8_t uRexIndex; /* 0x12 */
1960
1961	# else /* IEM_WITH_OPAQUE_DECODER_STATE */
1962	uint8_t abOpaqueDecoderPart1[0x13 - 0x08];
1963	# endif /* IEM_WITH_OPAQUE_DECODER_STATE */
1964	#endif /* !IEM_WITH_CODE_TLB */
1965
1966	#ifndef IEM_WITH_OPAQUE_DECODER_STATE
1967	/** The effective operand mode. */
1968	IEMMODE enmEffOpSize; /* 0x36, 0x13 */
1969	/** The default addressing mode. */
1970	IEMMODE enmDefAddrMode; /* 0x37, 0x14 */
1971	/** The effective addressing mode. */
1972	IEMMODE enmEffAddrMode; /* 0x38, 0x15 */
1973	/** The default operand mode. */
1974	IEMMODE enmDefOpSize; /* 0x39, 0x16 */
1975
1976	/** Prefix index (VEX.pp) for two byte and three byte tables. */
1977	uint8_t idxPrefix; /* 0x3a, 0x17 */
1978	/** 3rd VEX/EVEX/XOP register.
1979	* Please use IEM_GET_EFFECTIVE_VVVV to access. */
1980	uint8_t uVex3rdReg; /* 0x3b, 0x18 */
1981	/** The VEX/EVEX/XOP length field. */
1982	uint8_t uVexLength; /* 0x3c, 0x19 */
1983	/** Additional EVEX stuff. */
1984	uint8_t fEvexStuff; /* 0x3d, 0x1a */
1985
1986	# ifndef IEM_WITH_CODE_TLB
1987	/** Explicit alignment padding. */
1988	uint8_t abAlignment2a[1]; /* 0x1b */
1989	# endif
1990	/** The FPU opcode (FOP). */
1991	uint16_t uFpuOpcode; /* 0x3e, 0x1c */
1992	# ifndef IEM_WITH_CODE_TLB
1993	/** Explicit alignment padding. */
1994	uint8_t abAlignment2b[2]; /* 0x1e */
1995	# endif
1996
1997	/** The opcode bytes. */
1998	uint8_t abOpcode[15]; /* 0x40, 0x20 */
1999	/** Explicit alignment padding. */
2000	# ifdef IEM_WITH_CODE_TLB
2001	//uint8_t abAlignment2c[0x4f - 0x4f]; /* 0x4f */
2002	# else
2003	uint8_t abAlignment2c[0x4f - 0x2f]; /* 0x2f */
2004	# endif
2005
2006	#else /* IEM_WITH_OPAQUE_DECODER_STATE */
2007	# ifdef IEM_WITH_CODE_TLB
2008	uint8_t abOpaqueDecoderPart2[0x4f - 0x36];
2009	# else
2010	uint8_t abOpaqueDecoderPart2[0x4f - 0x13];
2011	# endif
2012	#endif /* IEM_WITH_OPAQUE_DECODER_STATE */
2013	/** @} */
2014
2015
2016	/** The number of active guest memory mappings. */
2017	uint8_t cActiveMappings; /* 0x4f, 0x4f */
2018
2019	/** Records for tracking guest memory mappings. */
2020	struct
2021	{
2022	/** The address of the mapped bytes. */
2023	R3R0PTRTYPE(void *) pv;
2024	/** The access flags (IEM_ACCESS_XXX).
2025	* IEM_ACCESS_INVALID if the entry is unused. */
2026	uint32_t fAccess;
2027	#if HC_ARCH_BITS == 64
2028	uint32_t u32Alignment4; /*< Alignment padding. /
2029	#endif
2030	} aMemMappings[3]; /* 0x50 LB 0x30 */
2031
2032	/** Locking records for the mapped memory. */
2033	union
2034	{
2035	PGMPAGEMAPLOCK Lock;
2036	uint64_t au64Padding[2];
2037	} aMemMappingLocks[3]; /* 0x80 LB 0x30 */
2038
2039	/** Bounce buffer info.
2040	* This runs in parallel to aMemMappings. */
2041	struct
2042	{
2043	/** The physical address of the first byte. */
2044	RTGCPHYS GCPhysFirst;
2045	/** The physical address of the second page. */
2046	RTGCPHYS GCPhysSecond;
2047	/** The number of bytes in the first page. */
2048	uint16_t cbFirst;
2049	/** The number of bytes in the second page. */
2050	uint16_t cbSecond;
2051	/** Whether it's unassigned memory. */
2052	bool fUnassigned;
2053	/** Explicit alignment padding. */
2054	bool afAlignment5[3];
2055	} aMemBbMappings[3]; /* 0xb0 LB 0x48 */
2056
2057	/** The flags of the current exception / interrupt. */
2058	uint32_t fCurXcpt; /* 0xf8 */
2059	/** The current exception / interrupt. */
2060	uint8_t uCurXcpt; /* 0xfc */
2061	/** Exception / interrupt recursion depth. */
2062	int8_t cXcptRecursions; /* 0xfb */
2063
2064	/** The next unused mapping index.
2065	* @todo try find room for this up with cActiveMappings. */
2066	uint8_t iNextMapping; /* 0xfd */
2067	uint8_t abAlignment7[1];
2068
2069	/** Bounce buffer storage.
2070	* This runs in parallel to aMemMappings and aMemBbMappings. */
2071	struct
2072	{
2073	uint8_t ab[512];
2074	} aBounceBuffers[3]; /* 0x100 LB 0x600 */
2075
2076
2077	/** Pointer set jump buffer - ring-3 context. */
2078	R3PTRTYPE(jmp_buf *) pJmpBufR3;
2079	/** Pointer set jump buffer - ring-0 context. */
2080	R0PTRTYPE(jmp_buf *) pJmpBufR0;
2081
2082	/** @todo Should move this near @a fCurXcpt later. */
2083	/** The CR2 for the current exception / interrupt. */
2084	uint64_t uCurXcptCr2;
2085	/** The error code for the current exception / interrupt. */
2086	uint32_t uCurXcptErr;
2087
2088	/** @name Statistics
2089	* @{ */
2090	/** The number of instructions we've executed. */
2091	uint32_t cInstructions;
2092	/** The number of potential exits. */
2093	uint32_t cPotentialExits;
2094	/** The number of bytes data or stack written (mostly for IEMExecOneEx).
2095	* This may contain uncommitted writes. */
2096	uint32_t cbWritten;
2097	/** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
2098	uint32_t cRetInstrNotImplemented;
2099	/** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
2100	uint32_t cRetAspectNotImplemented;
2101	/** Counts informational statuses returned (other than VINF_SUCCESS). */
2102	uint32_t cRetInfStatuses;
2103	/** Counts other error statuses returned. */
2104	uint32_t cRetErrStatuses;
2105	/** Number of times rcPassUp has been used. */
2106	uint32_t cRetPassUpStatus;
2107	/** Number of times RZ left with instruction commit pending for ring-3. */
2108	uint32_t cPendingCommit;
2109	/** Number of misaligned (host sense) atomic instruction accesses. */
2110	uint32_t cMisalignedAtomics;
2111	/** Number of long jumps. */
2112	uint32_t cLongJumps;
2113	/** @} */
2114
2115	/** @name Target CPU information.
2116	* @{ */
2117	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
2118	/** The target CPU. */
2119	uint8_t uTargetCpu;
2120	#else
2121	uint8_t bTargetCpuPadding;
2122	#endif
2123	/** For selecting assembly works matching the target CPU EFLAGS behaviour, see
2124	* IEMTARGETCPU_EFL_BEHAVIOR_XXX for values, with the 1st entry for when no
2125	* native host support and the 2nd for when there is.
2126	*
2127	* The two values are typically indexed by a g_CpumHostFeatures bit.
2128	*
2129	* This is for instance used for the BSF & BSR instructions where AMD and
2130	* Intel CPUs produce different EFLAGS. */
2131	uint8_t aidxTargetCpuEflFlavour[2];
2132
2133	/** The CPU vendor. */
2134	CPUMCPUVENDOR enmCpuVendor;
2135	/** @} */
2136
2137	/** @name Host CPU information.
2138	* @{ */
2139	/** The CPU vendor. */
2140	CPUMCPUVENDOR enmHostCpuVendor;
2141	/** @} */
2142
2143	/** Counts RDMSR \#GP(0) LogRel(). */
2144	uint8_t cLogRelRdMsr;
2145	/** Counts WRMSR \#GP(0) LogRel(). */
2146	uint8_t cLogRelWrMsr;
2147	/** Alignment padding. */
2148	uint8_t abAlignment9[42];
2149
2150
2151	/** @name Recompiled Exection
2152	* @{ */
2153	/** Pointer to the current translation block.
2154	* This can either be one being executed or one being compiled. */
2155	R3PTRTYPE(PIEMTB) pCurTbR3;
2156	#ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
2157	/** Frame pointer for the last native TB to execute. */
2158	R3PTRTYPE(void *) pvTbFramePointerR3;
2159	#else
2160	R3PTRTYPE(void *) pvUnusedR3;
2161	#endif
2162	#ifdef IEMNATIVE_WITH_SIMD_FP_NATIVE_EMITTERS
2163	/** The saved host floating point control register (MXCSR on x86, FPCR on arm64)
2164	* needing restore when the TB finished, IEMNATIVE_SIMD_FP_CTRL_REG_NOT_MODIFIED indicates the TB
2165	* didn't modify it so we don't need to restore it. */
2166	# ifdef RT_ARCH_AMD64
2167	uint32_t uRegFpCtrl;
2168	/** Temporary copy of MXCSR for stmxcsr/ldmxcsr (so we don't have to fiddle with stack pointers). */
2169	uint32_t uRegMxcsrTmp;
2170	# elif defined(RT_ARCH_ARM64)
2171	uint64_t uRegFpCtrl;
2172	# else
2173	# error "Port me"
2174	# endif
2175	#else
2176	uint64_t u64Unused;
2177	#endif
2178	/** Pointer to the ring-3 TB cache for this EMT. */
2179	R3PTRTYPE(PIEMTBCACHE) pTbCacheR3;
2180	/** Pointer to the ring-3 TB lookup entry.
2181	* This either points to pTbLookupEntryDummyR3 or an actually lookuptable
2182	* entry, thus it can always safely be used w/o NULL checking. */
2183	R3PTRTYPE(PIEMTB *) ppTbLookupEntryR3;
2184	#if 0 /* unused */
2185	/** The PC (RIP) at the start of pCurTbR3/pCurTbR0.
2186	* The TBs are based on physical addresses, so this is needed to correleated
2187	* RIP to opcode bytes stored in the TB (AMD-V / VT-x). */
2188	uint64_t uCurTbStartPc;
2189	#endif
2190
2191	/** Number of threaded TBs executed. */
2192	uint64_t cTbExecThreaded;
2193	/** Number of native TBs executed. */
2194	uint64_t cTbExecNative;
2195
2196	/** The number of IRQ/FF checks till the next timer poll call. */
2197	uint32_t cTbsTillNextTimerPoll;
2198	/** The virtual sync time at the last timer poll call in milliseconds. */
2199	uint32_t msRecompilerPollNow;
2200	/** The virtual sync time at the last timer poll call in nanoseconds. */
2201	uint64_t nsRecompilerPollNow;
2202	/** The previous cTbsTillNextTimerPoll value. */
2203	uint32_t cTbsTillNextTimerPollPrev;
2204
2205	/** The current instruction number in a native TB.
2206	* This is set by code that may trigger an unexpected TB exit (throw/longjmp)
2207	* and will be picked up by the TB execution loop. Only used when
2208	* IEMNATIVE_WITH_INSTRUCTION_COUNTING is defined. */
2209	uint8_t idxTbCurInstr;
2210	/** @} */
2211
2212	/** @name Recompilation
2213	* @{ */
2214	/** Whether we need to check the opcode bytes for the current instruction.
2215	* This is set by a previous instruction if it modified memory or similar. */
2216	bool fTbCheckOpcodes;
2217	/** Indicates whether and how we just branched - IEMBRANCHED_F_XXX. */
2218	uint8_t fTbBranched;
2219	/** Set when GCPhysInstrBuf is updated because of a page crossing. */
2220	bool fTbCrossedPage;
2221	/** Whether to end the current TB. */
2222	bool fEndTb;
2223	/** Indicates that the current instruction is an STI. This is set by the
2224	* iemCImpl_sti code and subsequently cleared by the recompiler. */
2225	bool fTbCurInstrIsSti;
2226	/** Spaced reserved for recompiler data / alignment. */
2227	bool afRecompilerStuff1[1];
2228	/** Number of instructions before we need emit an IRQ check call again.
2229	* This helps making sure we don't execute too long w/o checking for
2230	* interrupts and immediately following instructions that may enable
2231	* interrupts (e.g. POPF, IRET, STI). With STI an additional hack is
2232	* required to make sure we check following the next instruction as well, see
2233	* fTbCurInstrIsSti. */
2234	uint8_t cInstrTillIrqCheck;
2235	/** The index of the last CheckIrq call during threaded recompilation. */
2236	uint16_t idxLastCheckIrqCallNo;
2237	/** The size of the IEMTB::pabOpcodes allocation in pThrdCompileTbR3. */
2238	uint16_t cbOpcodesAllocated;
2239	/** The IEMTB::cUsed value when to attempt native recompilation of a TB. */
2240	uint32_t uTbNativeRecompileAtUsedCount;
2241	/** The IEM_CIMPL_F_XXX mask for the current instruction. */
2242	uint32_t fTbCurInstr;
2243	/** The IEM_CIMPL_F_XXX mask for the previous instruction. */
2244	uint32_t fTbPrevInstr;
2245	/** Strict: Tracking skipped EFLAGS calculations. Any bits set here are
2246	* currently not up to date in EFLAGS. */
2247	uint32_t fSkippingEFlags;
2248	#if 0 /* unused */
2249	/** Previous GCPhysInstrBuf value - only valid if fTbCrossedPage is set. */
2250	RTGCPHYS GCPhysInstrBufPrev;
2251	#endif
2252
2253	/** Fixed TB used for threaded recompilation.
2254	* This is allocated once with maxed-out sizes and re-used afterwards. */
2255	R3PTRTYPE(PIEMTB) pThrdCompileTbR3;
2256	/** Pointer to the ring-3 TB allocator for this EMT. */
2257	R3PTRTYPE(PIEMTBALLOCATOR) pTbAllocatorR3;
2258	/** Pointer to the ring-3 executable memory allocator for this EMT. */
2259	R3PTRTYPE(struct IEMEXECMEMALLOCATOR *) pExecMemAllocatorR3;
2260	/** Pointer to the native recompiler state for ring-3. */
2261	R3PTRTYPE(struct IEMRECOMPILERSTATE *) pNativeRecompilerStateR3;
2262	/** Dummy entry for ppTbLookupEntryR3. */
2263	R3PTRTYPE(PIEMTB) pTbLookupEntryDummyR3;
2264	/** @} */
2265
2266	/** Dummy TLB entry used for accesses to pages with databreakpoints. */
2267	IEMTLBENTRY DataBreakpointTlbe;
2268
2269	/** Threaded TB statistics: Times TB execution was broken off before reaching the end. */
2270	STAMCOUNTER StatTbThreadedExecBreaks;
2271	/** Statistics: Times BltIn_CheckIrq breaks out of the TB. */
2272	STAMCOUNTER StatCheckIrqBreaks;
2273	/** Statistics: Times BltIn_CheckTimers breaks direct linking TBs. */
2274	STAMCOUNTER StatCheckTimersBreaks;
2275	/** Statistics: Times BltIn_CheckMode breaks out of the TB. */
2276	STAMCOUNTER StatCheckModeBreaks;
2277	/** Threaded TB statistics: Times execution break on call with lookup entries. */
2278	STAMCOUNTER StatTbThreadedExecBreaksWithLookup;
2279	/** Threaded TB statistics: Times execution break on call without lookup entries. */
2280	STAMCOUNTER StatTbThreadedExecBreaksWithoutLookup;
2281	/** Statistics: Times a post jump target check missed and had to find new TB. */
2282	STAMCOUNTER StatCheckBranchMisses;
2283	/** Statistics: Times a jump or page crossing required a TB with CS.LIM checking. */
2284	STAMCOUNTER StatCheckNeedCsLimChecking;
2285	/** Statistics: Times a loop was detected within a TB. */
2286	STAMCOUNTER StatTbLoopInTbDetected;
2287	/** Statistics: Times a loop back to the start of the TB was detected. */
2288	STAMCOUNTER StatTbLoopFullTbDetected;
2289	/** Exec memory allocator statistics: Number of times allocaintg executable memory failed. */
2290	STAMCOUNTER StatNativeExecMemInstrBufAllocFailed;
2291	/** Native TB statistics: Number of fully recompiled TBs. */
2292	STAMCOUNTER StatNativeFullyRecompiledTbs;
2293	/** TB statistics: Number of instructions per TB. */
2294	STAMPROFILE StatTbInstr;
2295	/** TB statistics: Number of TB lookup table entries per TB. */
2296	STAMPROFILE StatTbLookupEntries;
2297	/** Threaded TB statistics: Number of calls per TB. */
2298	STAMPROFILE StatTbThreadedCalls;
2299	/** Native TB statistics: Native code size per TB. */
2300	STAMPROFILE StatTbNativeCode;
2301	/** Native TB statistics: Profiling native recompilation. */
2302	STAMPROFILE StatNativeRecompilation;
2303	/** Native TB statistics: Number of calls per TB that were recompiled properly. */
2304	STAMPROFILE StatNativeCallsRecompiled;
2305	/** Native TB statistics: Number of threaded calls per TB that weren't recompiled. */
2306	STAMPROFILE StatNativeCallsThreaded;
2307	/** Native recompiled execution: TLB hits for data fetches. */
2308	STAMCOUNTER StatNativeTlbHitsForFetch;
2309	/** Native recompiled execution: TLB hits for data stores. */
2310	STAMCOUNTER StatNativeTlbHitsForStore;
2311	/** Native recompiled execution: TLB hits for stack accesses. */
2312	STAMCOUNTER StatNativeTlbHitsForStack;
2313	/** Native recompiled execution: TLB hits for mapped accesses. */
2314	STAMCOUNTER StatNativeTlbHitsForMapped;
2315	/** Native recompiled execution: Code TLB misses for new page. */
2316	STAMCOUNTER StatNativeCodeTlbMissesNewPage;
2317	/** Native recompiled execution: Code TLB hits for new page. */
2318	STAMCOUNTER StatNativeCodeTlbHitsForNewPage;
2319	/** Native recompiled execution: Code TLB misses for new page with offset. */
2320	STAMCOUNTER StatNativeCodeTlbMissesNewPageWithOffset;
2321	/** Native recompiled execution: Code TLB hits for new page with offset. */
2322	STAMCOUNTER StatNativeCodeTlbHitsForNewPageWithOffset;
2323
2324	/** Native recompiler: Number of calls to iemNativeRegAllocFindFree. */
2325	STAMCOUNTER StatNativeRegFindFree;
2326	/** Native recompiler: Number of times iemNativeRegAllocFindFree needed
2327	* to free a variable. */
2328	STAMCOUNTER StatNativeRegFindFreeVar;
2329	/** Native recompiler: Number of times iemNativeRegAllocFindFree did
2330	* not need to free any variables. */
2331	STAMCOUNTER StatNativeRegFindFreeNoVar;
2332	/** Native recompiler: Liveness info freed shadowed guest registers in
2333	* iemNativeRegAllocFindFree. */
2334	STAMCOUNTER StatNativeRegFindFreeLivenessUnshadowed;
2335	/** Native recompiler: Liveness info helped with the allocation in
2336	* iemNativeRegAllocFindFree. */
2337	STAMCOUNTER StatNativeRegFindFreeLivenessHelped;
2338
2339	/** Native recompiler: Number of times status flags calc has been skipped. */
2340	STAMCOUNTER StatNativeEflSkippedArithmetic;
2341	/** Native recompiler: Number of times status flags calc has been skipped. */
2342	STAMCOUNTER StatNativeEflSkippedLogical;
2343
2344	/** Native recompiler: Number of opportunities to skip EFLAGS.CF updating. */
2345	STAMCOUNTER StatNativeLivenessEflCfSkippable;
2346	/** Native recompiler: Number of opportunities to skip EFLAGS.PF updating. */
2347	STAMCOUNTER StatNativeLivenessEflPfSkippable;
2348	/** Native recompiler: Number of opportunities to skip EFLAGS.AF updating. */
2349	STAMCOUNTER StatNativeLivenessEflAfSkippable;
2350	/** Native recompiler: Number of opportunities to skip EFLAGS.ZF updating. */
2351	STAMCOUNTER StatNativeLivenessEflZfSkippable;
2352	/** Native recompiler: Number of opportunities to skip EFLAGS.SF updating. */
2353	STAMCOUNTER StatNativeLivenessEflSfSkippable;
2354	/** Native recompiler: Number of opportunities to skip EFLAGS.OF updating. */
2355	STAMCOUNTER StatNativeLivenessEflOfSkippable;
2356	/** Native recompiler: Number of required EFLAGS.CF updates. */
2357	STAMCOUNTER StatNativeLivenessEflCfRequired;
2358	/** Native recompiler: Number of required EFLAGS.PF updates. */
2359	STAMCOUNTER StatNativeLivenessEflPfRequired;
2360	/** Native recompiler: Number of required EFLAGS.AF updates. */
2361	STAMCOUNTER StatNativeLivenessEflAfRequired;
2362	/** Native recompiler: Number of required EFLAGS.ZF updates. */
2363	STAMCOUNTER StatNativeLivenessEflZfRequired;
2364	/** Native recompiler: Number of required EFLAGS.SF updates. */
2365	STAMCOUNTER StatNativeLivenessEflSfRequired;
2366	/** Native recompiler: Number of required EFLAGS.OF updates. */
2367	STAMCOUNTER StatNativeLivenessEflOfRequired;
2368	/** Native recompiler: Number of potentially delayable EFLAGS.CF updates. */
2369	STAMCOUNTER StatNativeLivenessEflCfDelayable;
2370	/** Native recompiler: Number of potentially delayable EFLAGS.PF updates. */
2371	STAMCOUNTER StatNativeLivenessEflPfDelayable;
2372	/** Native recompiler: Number of potentially delayable EFLAGS.AF updates. */
2373	STAMCOUNTER StatNativeLivenessEflAfDelayable;
2374	/** Native recompiler: Number of potentially delayable EFLAGS.ZF updates. */
2375	STAMCOUNTER StatNativeLivenessEflZfDelayable;
2376	/** Native recompiler: Number of potentially delayable EFLAGS.SF updates. */
2377	STAMCOUNTER StatNativeLivenessEflSfDelayable;
2378	/** Native recompiler: Number of potentially delayable EFLAGS.OF updates. */
2379	STAMCOUNTER StatNativeLivenessEflOfDelayable;
2380
2381	/** Native recompiler: Number of potential PC updates in total. */
2382	STAMCOUNTER StatNativePcUpdateTotal;
2383	/** Native recompiler: Number of PC updates which could be delayed. */
2384	STAMCOUNTER StatNativePcUpdateDelayed;
2385
2386	//#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
2387	/** Native recompiler: Number of calls to iemNativeSimdRegAllocFindFree. */
2388	STAMCOUNTER StatNativeSimdRegFindFree;
2389	/** Native recompiler: Number of times iemNativeSimdRegAllocFindFree needed
2390	* to free a variable. */
2391	STAMCOUNTER StatNativeSimdRegFindFreeVar;
2392	/** Native recompiler: Number of times iemNativeSimdRegAllocFindFree did
2393	* not need to free any variables. */
2394	STAMCOUNTER StatNativeSimdRegFindFreeNoVar;
2395	/** Native recompiler: Liveness info freed shadowed guest registers in
2396	* iemNativeSimdRegAllocFindFree. */
2397	STAMCOUNTER StatNativeSimdRegFindFreeLivenessUnshadowed;
2398	/** Native recompiler: Liveness info helped with the allocation in
2399	* iemNativeSimdRegAllocFindFree. */
2400	STAMCOUNTER StatNativeSimdRegFindFreeLivenessHelped;
2401
2402	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() checks. */
2403	STAMCOUNTER StatNativeMaybeDeviceNotAvailXcptCheckPotential;
2404	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() checks. */
2405	STAMCOUNTER StatNativeMaybeWaitDeviceNotAvailXcptCheckPotential;
2406	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() checks. */
2407	STAMCOUNTER StatNativeMaybeSseXcptCheckPotential;
2408	/** Native recompiler: Number of potential IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() checks. */
2409	STAMCOUNTER StatNativeMaybeAvxXcptCheckPotential;
2410
2411	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() checks omitted. */
2412	STAMCOUNTER StatNativeMaybeDeviceNotAvailXcptCheckOmitted;
2413	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() checks omitted. */
2414	STAMCOUNTER StatNativeMaybeWaitDeviceNotAvailXcptCheckOmitted;
2415	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() checks omitted. */
2416	STAMCOUNTER StatNativeMaybeSseXcptCheckOmitted;
2417	/** Native recompiler: Number of IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() checks omitted. */
2418	STAMCOUNTER StatNativeMaybeAvxXcptCheckOmitted;
2419	//#endif
2420
2421	/** Native recompiler: The TB finished executing completely without jumping to a an exit label.
2422	* Not availabe in release builds. */
2423	STAMCOUNTER StatNativeTbFinished;
2424	/** Native recompiler: The TB finished executing jumping to the ReturnBreak label. */
2425	STAMCOUNTER StatNativeTbExitReturnBreak;
2426	/** Native recompiler: The TB finished executing jumping to the ReturnBreakFF label. */
2427	STAMCOUNTER StatNativeTbExitReturnBreakFF;
2428	/** Native recompiler: The TB finished executing jumping to the ReturnWithFlags label. */
2429	STAMCOUNTER StatNativeTbExitReturnWithFlags;
2430	/** Native recompiler: The TB finished executing with other non-zero status. */
2431	STAMCOUNTER StatNativeTbExitReturnOtherStatus;
2432	/** Native recompiler: The TB finished executing via throw / long jump. */
2433	STAMCOUNTER StatNativeTbExitLongJump;
2434	/** Native recompiler: The TB finished executing jumping to the ReturnBreak
2435	* label, but directly jumped to the next TB, scenario \#1 w/o IRQ checks. */
2436	STAMCOUNTER StatNativeTbExitDirectLinking1NoIrq;
2437	/** Native recompiler: The TB finished executing jumping to the ReturnBreak
2438	* label, but directly jumped to the next TB, scenario \#1 with IRQ checks. */
2439	STAMCOUNTER StatNativeTbExitDirectLinking1Irq;
2440	/** Native recompiler: The TB finished executing jumping to the ReturnBreak
2441	* label, but directly jumped to the next TB, scenario \#1 w/o IRQ checks. */
2442	STAMCOUNTER StatNativeTbExitDirectLinking2NoIrq;
2443	/** Native recompiler: The TB finished executing jumping to the ReturnBreak
2444	* label, but directly jumped to the next TB, scenario \#2 with IRQ checks. */
2445	STAMCOUNTER StatNativeTbExitDirectLinking2Irq;
2446
2447	/** Native recompiler: The TB finished executing jumping to the RaiseDe label. */
2448	STAMCOUNTER StatNativeTbExitRaiseDe;
2449	/** Native recompiler: The TB finished executing jumping to the RaiseUd label. */
2450	STAMCOUNTER StatNativeTbExitRaiseUd;
2451	/** Native recompiler: The TB finished executing jumping to the RaiseSseRelated label. */
2452	STAMCOUNTER StatNativeTbExitRaiseSseRelated;
2453	/** Native recompiler: The TB finished executing jumping to the RaiseAvxRelated label. */
2454	STAMCOUNTER StatNativeTbExitRaiseAvxRelated;
2455	/** Native recompiler: The TB finished executing jumping to the RaiseSseAvxFpRelated label. */
2456	STAMCOUNTER StatNativeTbExitRaiseSseAvxFpRelated;
2457	/** Native recompiler: The TB finished executing jumping to the RaiseNm label. */
2458	STAMCOUNTER StatNativeTbExitRaiseNm;
2459	/** Native recompiler: The TB finished executing jumping to the RaiseGp0 label. */
2460	STAMCOUNTER StatNativeTbExitRaiseGp0;
2461	/** Native recompiler: The TB finished executing jumping to the RaiseMf label. */
2462	STAMCOUNTER StatNativeTbExitRaiseMf;
2463	/** Native recompiler: The TB finished executing jumping to the RaiseXf label. */
2464	STAMCOUNTER StatNativeTbExitRaiseXf;
2465	/** Native recompiler: The TB finished executing jumping to the ObsoleteTb label. */
2466	STAMCOUNTER StatNativeTbExitObsoleteTb;
2467
2468	/** Native recompiler: Number of full TB loops (jumps from end to start). */
2469	STAMCOUNTER StatNativeTbExitLoopFullTb;
2470
2471	/** Native recompiler: Failure situations with direct linking scenario \#1.
2472	* Counter with StatNativeTbExitReturnBreak. Not in release builds.
2473	* @{ */
2474	STAMCOUNTER StatNativeTbExitDirectLinking1NoTb;
2475	STAMCOUNTER StatNativeTbExitDirectLinking1MismatchGCPhysPc;
2476	STAMCOUNTER StatNativeTbExitDirectLinking1MismatchFlags;
2477	STAMCOUNTER StatNativeTbExitDirectLinking1PendingIrq;
2478	/** @} */
2479
2480	/** Native recompiler: Failure situations with direct linking scenario \#2.
2481	* Counter with StatNativeTbExitReturnBreak. Not in release builds.
2482	* @{ */
2483	STAMCOUNTER StatNativeTbExitDirectLinking2NoTb;
2484	STAMCOUNTER StatNativeTbExitDirectLinking2MismatchGCPhysPc;
2485	STAMCOUNTER StatNativeTbExitDirectLinking2MismatchFlags;
2486	STAMCOUNTER StatNativeTbExitDirectLinking2PendingIrq;
2487	/** @} */
2488
2489	/** iemMemMap and iemMemMapJmp statistics.
2490	* @{ */
2491	STAMCOUNTER StatMemMapJmp;
2492	STAMCOUNTER StatMemMapNoJmp;
2493	STAMCOUNTER StatMemBounceBufferCrossPage;
2494	STAMCOUNTER StatMemBounceBufferMapPhys;
2495	/** @} */
2496
2497	/** Timer polling statistics (debug only).
2498	* @{ */
2499	STAMPROFILE StatTimerPoll;
2500	STAMPROFILE StatTimerPollPoll;
2501	STAMPROFILE StatTimerPollRun;
2502	STAMCOUNTER StatTimerPollUnchanged;
2503	STAMCOUNTER StatTimerPollTiny;
2504	STAMCOUNTER StatTimerPollDefaultCalc;
2505	STAMCOUNTER StatTimerPollMax;
2506	STAMPROFILE StatTimerPollFactorDivision;
2507	STAMPROFILE StatTimerPollFactorMultiplication;
2508	/** @} */
2509
2510	#ifdef IEM_WITH_TLB_TRACE
2511	uint64_t au64Padding[7];
2512	#else
2513	uint64_t au64Padding[1];
2514	#endif
2515
2516	#ifdef IEM_WITH_TLB_TRACE
2517	/** The end (next) trace entry. */
2518	uint32_t idxTlbTraceEntry;
2519	/** Number of trace entries allocated expressed as a power of two. */
2520	uint32_t cTlbTraceEntriesShift;
2521	/** The trace entries. */
2522	PIEMTLBTRACEENTRY paTlbTraceEntries;
2523	#endif
2524
2525	/** Data TLB.
2526	* @remarks Must be 64-byte aligned. */
2527	IEMTLB DataTlb;
2528	/** Instruction TLB.
2529	* @remarks Must be 64-byte aligned. */
2530	IEMTLB CodeTlb;
2531
2532	/** Exception statistics. */
2533	STAMCOUNTER aStatXcpts[32];
2534	/** Interrupt statistics. */
2535	uint32_t aStatInts[256];
2536
2537	#if defined(VBOX_WITH_STATISTICS) && !defined(DOXYGEN_RUNNING) && !defined(IEM_WITHOUT_INSTRUCTION_STATS)
2538	/** Instruction statistics for ring-0/raw-mode. */
2539	IEMINSTRSTATS StatsRZ;
2540	/** Instruction statistics for ring-3. */
2541	IEMINSTRSTATS StatsR3;
2542	# ifdef VBOX_WITH_IEM_RECOMPILER
2543	/** Statistics per threaded function call.
2544	* Updated by both the threaded and native recompilers. */
2545	uint32_t acThreadedFuncStats[0x6000 /24576/];
2546	# endif
2547	#endif
2548	} IEMCPU;
2549	AssertCompileMemberOffset(IEMCPU, cActiveMappings, 0x4f);
2550	AssertCompileMemberAlignment(IEMCPU, aMemMappings, 16);
2551	AssertCompileMemberAlignment(IEMCPU, aMemMappingLocks, 16);
2552	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 64);
2553	AssertCompileMemberAlignment(IEMCPU, pCurTbR3, 64);
2554	AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
2555	AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
2556
2557	/** Pointer to the per-CPU IEM state. */
2558	typedef IEMCPU *PIEMCPU;
2559	/** Pointer to the const per-CPU IEM state. */
2560	typedef IEMCPU const *PCIEMCPU;
2561
2562	/** @def IEMNATIVE_SIMD_FP_CTRL_REG_NOT_MODIFIED
2563	* Value indicating the TB didn't modified the floating point control register.
2564	* @note Neither FPCR nor MXCSR accept this as a valid value (MXCSR is not fully populated,
2565	* FPCR has the upper 32-bit reserved), so this is safe. */
2566	#if defined(IEMNATIVE_WITH_SIMD_FP_NATIVE_EMITTERS) \|\| defined(DOXYGEN_RUNNING)
2567	# ifdef RT_ARCH_AMD64
2568	# define IEMNATIVE_SIMD_FP_CTRL_REG_NOT_MODIFIED UINT32_MAX
2569	# elif defined(RT_ARCH_ARM64)
2570	# define IEMNATIVE_SIMD_FP_CTRL_REG_NOT_MODIFIED UINT64_MAX
2571	# else
2572	# error "Port me"
2573	# endif
2574	#endif
2575
2576	/** @def IEM_GET_CTX
2577	* Gets the guest CPU context for the calling EMT.
2578	* @returns PCPUMCTX
2579	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2580	*/
2581	#define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
2582
2583	/** @def IEM_CTX_ASSERT
2584	* Asserts that the @a a_fExtrnMbz is present in the CPU context.
2585	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2586	* @param a_fExtrnMbz The mask of CPUMCTX_EXTRN_XXX flags that must be zero.
2587	*/
2588	#define IEM_CTX_ASSERT(a_pVCpu, a_fExtrnMbz) \
2589	AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
2590	("fExtrn=%#RX64 & fExtrnMbz=%#RX64 -> %#RX64\n", \
2591	(a_pVCpu)->cpum.GstCtx.fExtrn, (a_fExtrnMbz), (a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz) ))
2592
2593	/** @def IEM_CTX_IMPORT_RET
2594	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
2595	*
2596	* Will call the keep to import the bits as needed.
2597	*
2598	* Returns on import failure.
2599	*
2600	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2601	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
2602	*/
2603	#define IEM_CTX_IMPORT_RET(a_pVCpu, a_fExtrnImport) \
2604	do { \
2605	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
2606	{ /* likely */ } \
2607	else \
2608	{ \
2609	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
2610	AssertRCReturn(rcCtxImport, rcCtxImport); \
2611	} \
2612	} while (0)
2613
2614	/** @def IEM_CTX_IMPORT_NORET
2615	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
2616	*
2617	* Will call the keep to import the bits as needed.
2618	*
2619	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2620	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
2621	*/
2622	#define IEM_CTX_IMPORT_NORET(a_pVCpu, a_fExtrnImport) \
2623	do { \
2624	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
2625	{ /* likely */ } \
2626	else \
2627	{ \
2628	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
2629	AssertLogRelRC(rcCtxImport); \
2630	} \
2631	} while (0)
2632
2633	/** @def IEM_CTX_IMPORT_JMP
2634	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
2635	*
2636	* Will call the keep to import the bits as needed.
2637	*
2638	* Jumps on import failure.
2639	*
2640	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2641	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
2642	*/
2643	#define IEM_CTX_IMPORT_JMP(a_pVCpu, a_fExtrnImport) \
2644	do { \
2645	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
2646	{ /* likely */ } \
2647	else \
2648	{ \
2649	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
2650	AssertRCStmt(rcCtxImport, IEM_DO_LONGJMP(pVCpu, rcCtxImport)); \
2651	} \
2652	} while (0)
2653
2654
2655
2656	/** @def IEM_GET_TARGET_CPU
2657	* Gets the current IEMTARGETCPU value.
2658	* @returns IEMTARGETCPU value.
2659	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2660	*/
2661	#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
2662	# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
2663	#else
2664	# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
2665	#endif
2666
2667	/** @def IEM_GET_INSTR_LEN
2668	* Gets the instruction length. */
2669	#ifdef IEM_WITH_CODE_TLB
2670	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
2671	#else
2672	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
2673	#endif
2674
2675	/** @def IEM_TRY_SETJMP
2676	* Wrapper around setjmp / try, hiding all the ugly differences.
2677	*
2678	* @note Use with extreme care as this is a fragile macro.
2679	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2680	* @param a_rcTarget The variable that should receive the status code in case
2681	* of a longjmp/throw.
2682	*/
2683	/** @def IEM_TRY_SETJMP_AGAIN
2684	* For when setjmp / try is used again in the same variable scope as a previous
2685	* IEM_TRY_SETJMP invocation.
2686	*/
2687	/** @def IEM_CATCH_LONGJMP_BEGIN
2688	* Start wrapper for catch / setjmp-else.
2689	*
2690	* This will set up a scope.
2691	*
2692	* @note Use with extreme care as this is a fragile macro.
2693	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2694	* @param a_rcTarget The variable that should receive the status code in case
2695	* of a longjmp/throw.
2696	*/
2697	/** @def IEM_CATCH_LONGJMP_END
2698	* End wrapper for catch / setjmp-else.
2699	*
2700	* This will close the scope set up by IEM_CATCH_LONGJMP_BEGIN and clean up the
2701	* state.
2702	*
2703	* @note Use with extreme care as this is a fragile macro.
2704	* @param a_pVCpu The cross context virtual CPU structure of the calling EMT.
2705	*/
2706	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
2707	# ifdef IEM_WITH_THROW_CATCH
2708	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
2709	a_rcTarget = VINF_SUCCESS; \
2710	try
2711	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
2712	IEM_TRY_SETJMP(a_pVCpu, a_rcTarget)
2713	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
2714	catch (int rcThrown) \
2715	{ \
2716	a_rcTarget = rcThrown
2717	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
2718	} \
2719	((void)0)
2720	# else /* !IEM_WITH_THROW_CATCH */
2721	# define IEM_TRY_SETJMP(a_pVCpu, a_rcTarget) \
2722	jmp_buf JmpBuf; \
2723	jmp_buf * volatile pSavedJmpBuf = (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf); \
2724	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
2725	if ((rcStrict = setjmp(JmpBuf)) == 0)
2726	# define IEM_TRY_SETJMP_AGAIN(a_pVCpu, a_rcTarget) \
2727	pSavedJmpBuf = (a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf); \
2728	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = &JmpBuf; \
2729	if ((rcStrict = setjmp(JmpBuf)) == 0)
2730	# define IEM_CATCH_LONGJMP_BEGIN(a_pVCpu, a_rcTarget) \
2731	else \
2732	{ \
2733	((void)0)
2734	# define IEM_CATCH_LONGJMP_END(a_pVCpu) \
2735	} \
2736	(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf) = pSavedJmpBuf
2737	# endif /* !IEM_WITH_THROW_CATCH */
2738	#endif /* IEM_WITH_SETJMP */
2739
2740
2741	/**
2742	* Shared per-VM IEM data.
2743	*/
2744	typedef struct IEM
2745	{
2746	/** The VMX APIC-access page handler type. */
2747	PGMPHYSHANDLERTYPE hVmxApicAccessPage;
2748	#ifndef VBOX_WITHOUT_CPUID_HOST_CALL
2749	/** Set if the CPUID host call functionality is enabled. */
2750	bool fCpuIdHostCall;
2751	#endif
2752	} IEM;
2753
2754
2755
2756	/** @name IEM_ACCESS_XXX - Access details.
2757	* @{ */
2758	#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
2759	#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
2760	#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
2761	#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
2762	#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
2763	#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
2764	#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
2765	#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
2766	#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
2767	#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
2768	/** The writes are partial, so if initialize the bounce buffer with the
2769	* orignal RAM content. */
2770	#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
2771	/** Used in aMemMappings to indicate that the entry is bounce buffered. */
2772	#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
2773	/** Bounce buffer with ring-3 write pending, first page. */
2774	#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
2775	/** Bounce buffer with ring-3 write pending, second page. */
2776	#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
2777	/** Not locked, accessed via the TLB. */
2778	#define IEM_ACCESS_NOT_LOCKED UINT32_C(0x00001000)
2779	/** Atomic access.
2780	* This enables special alignment checks and the VINF_EM_EMULATE_SPLIT_LOCK
2781	* fallback for misaligned stuff. See @bugref{10547}. */
2782	#define IEM_ACCESS_ATOMIC UINT32_C(0x00002000)
2783	/** Valid bit mask. */
2784	#define IEM_ACCESS_VALID_MASK UINT32_C(0x00003fff)
2785	/** Shift count for the TLB flags (upper word). */
2786	#define IEM_ACCESS_SHIFT_TLB_FLAGS 16
2787
2788	/** Atomic read+write data alias. */
2789	#define IEM_ACCESS_DATA_ATOMIC (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA \| IEM_ACCESS_ATOMIC)
2790	/** Read+write data alias. */
2791	#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
2792	/** Write data alias. */
2793	#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
2794	/** Read data alias. */
2795	#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_DATA)
2796	/** Instruction fetch alias. */
2797	#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_WHAT_CODE)
2798	/** Stack write alias. */
2799	#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
2800	/** Stack read alias. */
2801	#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_STACK)
2802	/** Stack read+write alias. */
2803	#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
2804	/** Read system table alias. */
2805	#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_SYS)
2806	/** Read+write system table alias. */
2807	#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_SYS)
2808	/** @} */
2809
2810	/** @name Prefix constants (IEMCPU::fPrefixes)
2811	* @{ */
2812	#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /*< CS segment prefix (0x2e). /
2813	#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /*< SS segment prefix (0x36). /
2814	#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /*< DS segment prefix (0x3e). /
2815	#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /*< ES segment prefix (0x26). /
2816	#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /*< FS segment prefix (0x64). /
2817	#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /*< GS segment prefix (0x65). /
2818	#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
2819
2820	#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /*< Operand size prefix (0x66). /
2821	#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /*< REX.W prefix (0x48-0x4f). /
2822	#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /*< Address size prefix (0x67). /
2823
2824	#define IEM_OP_PRF_LOCK RT_BIT_32(16) /*< Lock prefix (0xf0). /
2825	#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /*< Repeat-not-zero prefix (0xf2). /
2826	#define IEM_OP_PRF_REPZ RT_BIT_32(18) /*< Repeat-if-zero prefix (0xf3). /
2827
2828	#define IEM_OP_PRF_REX RT_BIT_32(24) /*< Any REX prefix (0x40-0x4f). /
2829	#define IEM_OP_PRF_REX_B RT_BIT_32(25) /*< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). /
2830	#define IEM_OP_PRF_REX_X RT_BIT_32(26) /*< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). /
2831	#define IEM_OP_PRF_REX_R RT_BIT_32(27) /*< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). /
2832	/** Mask with all the REX prefix flags.
2833	* This is generally for use when needing to undo the REX prefixes when they
2834	* are followed legacy prefixes and therefore does not immediately preceed
2835	* the first opcode byte.
2836	* For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
2837	#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX \| IEM_OP_PRF_REX_R \| IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X \| IEM_OP_PRF_SIZE_REX_W )
2838
2839	#define IEM_OP_PRF_VEX RT_BIT_32(28) /*< Indiciates VEX prefix. /
2840	#define IEM_OP_PRF_EVEX RT_BIT_32(29) /*< Indiciates EVEX prefix. /
2841	#define IEM_OP_PRF_XOP RT_BIT_32(30) /*< Indiciates XOP prefix. /
2842	/** @} */
2843
2844	/** @name IEMOPFORM_XXX - Opcode forms
2845	* @note These are ORed together with IEMOPHINT_XXX.
2846	* @{ */
2847	/** ModR/M: reg, r/m */
2848	#define IEMOPFORM_RM 0
2849	/** ModR/M: reg, r/m (register) */
2850	#define IEMOPFORM_RM_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
2851	/** ModR/M: reg, r/m (memory) */
2852	#define IEMOPFORM_RM_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
2853	/** ModR/M: reg, r/m, imm */
2854	#define IEMOPFORM_RMI 1
2855	/** ModR/M: reg, r/m (register), imm */
2856	#define IEMOPFORM_RMI_REG (IEMOPFORM_RMI \| IEMOPFORM_MOD3)
2857	/** ModR/M: reg, r/m (memory), imm */
2858	#define IEMOPFORM_RMI_MEM (IEMOPFORM_RMI \| IEMOPFORM_NOT_MOD3)
2859	/** ModR/M: reg, r/m, xmm0 */
2860	#define IEMOPFORM_RM0 2
2861	/** ModR/M: reg, r/m (register), xmm0 */
2862	#define IEMOPFORM_RM0_REG (IEMOPFORM_RM0 \| IEMOPFORM_MOD3)
2863	/** ModR/M: reg, r/m (memory), xmm0 */
2864	#define IEMOPFORM_RM0_MEM (IEMOPFORM_RM0 \| IEMOPFORM_NOT_MOD3)
2865	/** ModR/M: r/m, reg */
2866	#define IEMOPFORM_MR 3
2867	/** ModR/M: r/m (register), reg */
2868	#define IEMOPFORM_MR_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
2869	/** ModR/M: r/m (memory), reg */
2870	#define IEMOPFORM_MR_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
2871	/** ModR/M: r/m, reg, imm */
2872	#define IEMOPFORM_MRI 4
2873	/** ModR/M: r/m (register), reg, imm */
2874	#define IEMOPFORM_MRI_REG (IEMOPFORM_MRI \| IEMOPFORM_MOD3)
2875	/** ModR/M: r/m (memory), reg, imm */
2876	#define IEMOPFORM_MRI_MEM (IEMOPFORM_MRI \| IEMOPFORM_NOT_MOD3)
2877	/** ModR/M: r/m only */
2878	#define IEMOPFORM_M 5
2879	/** ModR/M: r/m only (register). */
2880	#define IEMOPFORM_M_REG (IEMOPFORM_M \| IEMOPFORM_MOD3)
2881	/** ModR/M: r/m only (memory). */
2882	#define IEMOPFORM_M_MEM (IEMOPFORM_M \| IEMOPFORM_NOT_MOD3)
2883	/** ModR/M: r/m, imm */
2884	#define IEMOPFORM_MI 6
2885	/** ModR/M: r/m (register), imm */
2886	#define IEMOPFORM_MI_REG (IEMOPFORM_MI \| IEMOPFORM_MOD3)
2887	/** ModR/M: r/m (memory), imm */
2888	#define IEMOPFORM_MI_MEM (IEMOPFORM_MI \| IEMOPFORM_NOT_MOD3)
2889	/** ModR/M: r/m, 1 (shift and rotate instructions) */
2890	#define IEMOPFORM_M1 7
2891	/** ModR/M: r/m (register), 1. */
2892	#define IEMOPFORM_M1_REG (IEMOPFORM_M1 \| IEMOPFORM_MOD3)
2893	/** ModR/M: r/m (memory), 1. */
2894	#define IEMOPFORM_M1_MEM (IEMOPFORM_M1 \| IEMOPFORM_NOT_MOD3)
2895	/** ModR/M: r/m, CL (shift and rotate instructions)
2896	* @todo This should just've been a generic fixed register. But the python
2897	* code doesn't needs more convincing. */
2898	#define IEMOPFORM_M_CL 8
2899	/** ModR/M: r/m (register), CL. */
2900	#define IEMOPFORM_M_CL_REG (IEMOPFORM_M_CL \| IEMOPFORM_MOD3)
2901	/** ModR/M: r/m (memory), CL. */
2902	#define IEMOPFORM_M_CL_MEM (IEMOPFORM_M_CL \| IEMOPFORM_NOT_MOD3)
2903	/** ModR/M: reg only */
2904	#define IEMOPFORM_R 9
2905
2906	/** VEX+ModR/M: reg, r/m */
2907	#define IEMOPFORM_VEX_RM 16
2908	/** VEX+ModR/M: reg, r/m (register) */
2909	#define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM \| IEMOPFORM_MOD3)
2910	/** VEX+ModR/M: reg, r/m (memory) */
2911	#define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM \| IEMOPFORM_NOT_MOD3)
2912	/** VEX+ModR/M: r/m, reg */
2913	#define IEMOPFORM_VEX_MR 17
2914	/** VEX+ModR/M: r/m (register), reg */
2915	#define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR \| IEMOPFORM_MOD3)
2916	/** VEX+ModR/M: r/m (memory), reg */
2917	#define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR \| IEMOPFORM_NOT_MOD3)
2918	/** VEX+ModR/M: r/m, reg, imm8 */
2919	#define IEMOPFORM_VEX_MRI 18
2920	/** VEX+ModR/M: r/m (register), reg, imm8 */
2921	#define IEMOPFORM_VEX_MRI_REG (IEMOPFORM_VEX_MRI \| IEMOPFORM_MOD3)
2922	/** VEX+ModR/M: r/m (memory), reg, imm8 */
2923	#define IEMOPFORM_VEX_MRI_MEM (IEMOPFORM_VEX_MRI \| IEMOPFORM_NOT_MOD3)
2924	/** VEX+ModR/M: r/m only */
2925	#define IEMOPFORM_VEX_M 19
2926	/** VEX+ModR/M: r/m only (register). */
2927	#define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M \| IEMOPFORM_MOD3)
2928	/** VEX+ModR/M: r/m only (memory). */
2929	#define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M \| IEMOPFORM_NOT_MOD3)
2930	/** VEX+ModR/M: reg only */
2931	#define IEMOPFORM_VEX_R 20
2932	/** VEX+ModR/M: reg, vvvv, r/m */
2933	#define IEMOPFORM_VEX_RVM 21
2934	/** VEX+ModR/M: reg, vvvv, r/m (register). */
2935	#define IEMOPFORM_VEX_RVM_REG (IEMOPFORM_VEX_RVM \| IEMOPFORM_MOD3)
2936	/** VEX+ModR/M: reg, vvvv, r/m (memory). */
2937	#define IEMOPFORM_VEX_RVM_MEM (IEMOPFORM_VEX_RVM \| IEMOPFORM_NOT_MOD3)
2938	/** VEX+ModR/M: reg, vvvv, r/m, imm */
2939	#define IEMOPFORM_VEX_RVMI 22
2940	/** VEX+ModR/M: reg, vvvv, r/m (register), imm. */
2941	#define IEMOPFORM_VEX_RVMI_REG (IEMOPFORM_VEX_RVMI \| IEMOPFORM_MOD3)
2942	/** VEX+ModR/M: reg, vvvv, r/m (memory), imm. */
2943	#define IEMOPFORM_VEX_RVMI_MEM (IEMOPFORM_VEX_RVMI \| IEMOPFORM_NOT_MOD3)
2944	/** VEX+ModR/M: reg, vvvv, r/m, imm(reg) */
2945	#define IEMOPFORM_VEX_RVMR 23
2946	/** VEX+ModR/M: reg, vvvv, r/m (register), imm(reg). */
2947	#define IEMOPFORM_VEX_RVMR_REG (IEMOPFORM_VEX_RVMI \| IEMOPFORM_MOD3)
2948	/** VEX+ModR/M: reg, vvvv, r/m (memory), imm(reg). */
2949	#define IEMOPFORM_VEX_RVMR_MEM (IEMOPFORM_VEX_RVMI \| IEMOPFORM_NOT_MOD3)
2950	/** VEX+ModR/M: reg, r/m, vvvv */
2951	#define IEMOPFORM_VEX_RMV 24
2952	/** VEX+ModR/M: reg, r/m, vvvv (register). */
2953	#define IEMOPFORM_VEX_RMV_REG (IEMOPFORM_VEX_RMV \| IEMOPFORM_MOD3)
2954	/** VEX+ModR/M: reg, r/m, vvvv (memory). */
2955	#define IEMOPFORM_VEX_RMV_MEM (IEMOPFORM_VEX_RMV \| IEMOPFORM_NOT_MOD3)
2956	/** VEX+ModR/M: reg, r/m, imm8 */
2957	#define IEMOPFORM_VEX_RMI 25
2958	/** VEX+ModR/M: reg, r/m, imm8 (register). */
2959	#define IEMOPFORM_VEX_RMI_REG (IEMOPFORM_VEX_RMI \| IEMOPFORM_MOD3)
2960	/** VEX+ModR/M: reg, r/m, imm8 (memory). */
2961	#define IEMOPFORM_VEX_RMI_MEM (IEMOPFORM_VEX_RMI \| IEMOPFORM_NOT_MOD3)
2962	/** VEX+ModR/M: r/m, vvvv, reg */
2963	#define IEMOPFORM_VEX_MVR 26
2964	/** VEX+ModR/M: r/m, vvvv, reg (register) */
2965	#define IEMOPFORM_VEX_MVR_REG (IEMOPFORM_VEX_MVR \| IEMOPFORM_MOD3)
2966	/** VEX+ModR/M: r/m, vvvv, reg (memory) */
2967	#define IEMOPFORM_VEX_MVR_MEM (IEMOPFORM_VEX_MVR \| IEMOPFORM_NOT_MOD3)
2968	/** VEX+ModR/M+/n: vvvv, r/m */
2969	#define IEMOPFORM_VEX_VM 27
2970	/** VEX+ModR/M+/n: vvvv, r/m (register) */
2971	#define IEMOPFORM_VEX_VM_REG (IEMOPFORM_VEX_VM \| IEMOPFORM_MOD3)
2972	/** VEX+ModR/M+/n: vvvv, r/m (memory) */
2973	#define IEMOPFORM_VEX_VM_MEM (IEMOPFORM_VEX_VM \| IEMOPFORM_NOT_MOD3)
2974	/** VEX+ModR/M+/n: vvvv, r/m, imm8 */
2975	#define IEMOPFORM_VEX_VMI 28
2976	/** VEX+ModR/M+/n: vvvv, r/m, imm8 (register) */
2977	#define IEMOPFORM_VEX_VMI_REG (IEMOPFORM_VEX_VMI \| IEMOPFORM_MOD3)
2978	/** VEX+ModR/M+/n: vvvv, r/m, imm8 (memory) */
2979	#define IEMOPFORM_VEX_VMI_MEM (IEMOPFORM_VEX_VMI \| IEMOPFORM_NOT_MOD3)
2980
2981	/** Fixed register instruction, no R/M. */
2982	#define IEMOPFORM_FIXED 32
2983
2984	/** The r/m is a register. */
2985	#define IEMOPFORM_MOD3 RT_BIT_32(8)
2986	/** The r/m is a memory access. */
2987	#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
2988	/** @} */
2989
2990	/** @name IEMOPHINT_XXX - Additional Opcode Hints
2991	* @note These are ORed together with IEMOPFORM_XXX.
2992	* @{ */
2993	/** Ignores the operand size prefix (66h). */
2994	#define IEMOPHINT_IGNORES_OZ_PFX RT_BIT_32(10)
2995	/** Ignores REX.W (aka WIG). */
2996	#define IEMOPHINT_IGNORES_REXW RT_BIT_32(11)
2997	/** Both the operand size prefixes (66h + REX.W) are ignored. */
2998	#define IEMOPHINT_IGNORES_OP_SIZES (IEMOPHINT_IGNORES_OZ_PFX \| IEMOPHINT_IGNORES_REXW)
2999	/** Allowed with the lock prefix. */
3000	#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
3001	/** The VEX.L value is ignored (aka LIG). */
3002	#define IEMOPHINT_VEX_L_IGNORED RT_BIT_32(12)
3003	/** The VEX.L value must be zero (i.e. 128-bit width only). */
3004	#define IEMOPHINT_VEX_L_ZERO RT_BIT_32(13)
3005	/** The VEX.L value must be one (i.e. 256-bit width only). */
3006	#define IEMOPHINT_VEX_L_ONE RT_BIT_32(14)
3007	/** The VEX.V value must be zero. */
3008	#define IEMOPHINT_VEX_V_ZERO RT_BIT_32(15)
3009	/** The REX.W/VEX.V value must be zero. */
3010	#define IEMOPHINT_REX_W_ZERO RT_BIT_32(16)
3011	#define IEMOPHINT_VEX_W_ZERO IEMOPHINT_REX_W_ZERO
3012	/** The REX.W/VEX.V value must be one. */
3013	#define IEMOPHINT_REX_W_ONE RT_BIT_32(17)
3014	#define IEMOPHINT_VEX_W_ONE IEMOPHINT_REX_W_ONE
3015
3016	/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
3017	#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
3018	/** @} */
3019
3020	/**
3021	* Possible hardware task switch sources.
3022	*/
3023	typedef enum IEMTASKSWITCH
3024	{
3025	/** Task switch caused by an interrupt/exception. */
3026	IEMTASKSWITCH_INT_XCPT = 1,
3027	/** Task switch caused by a far CALL. */
3028	IEMTASKSWITCH_CALL,
3029	/** Task switch caused by a far JMP. */
3030	IEMTASKSWITCH_JUMP,
3031	/** Task switch caused by an IRET. */
3032	IEMTASKSWITCH_IRET
3033	} IEMTASKSWITCH;
3034	AssertCompileSize(IEMTASKSWITCH, 4);
3035
3036	/**
3037	* Possible CrX load (write) sources.
3038	*/
3039	typedef enum IEMACCESSCRX
3040	{
3041	/** CrX access caused by 'mov crX' instruction. */
3042	IEMACCESSCRX_MOV_CRX,
3043	/** CrX (CR0) write caused by 'lmsw' instruction. */
3044	IEMACCESSCRX_LMSW,
3045	/** CrX (CR0) write caused by 'clts' instruction. */
3046	IEMACCESSCRX_CLTS,
3047	/** CrX (CR0) read caused by 'smsw' instruction. */
3048	IEMACCESSCRX_SMSW
3049	} IEMACCESSCRX;
3050
3051	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
3052	/** @name IEM_SLAT_FAIL_XXX - Second-level address translation failure information.
3053	*
3054	* These flags provide further context to SLAT page-walk failures that could not be
3055	* determined by PGM (e.g, PGM is not privy to memory access permissions).
3056	*
3057	* @{
3058	*/
3059	/** Translating a nested-guest linear address failed accessing a nested-guest
3060	* physical address. */
3061	# define IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR RT_BIT_32(0)
3062	/** Translating a nested-guest linear address failed accessing a
3063	* paging-structure entry or updating accessed/dirty bits. */
3064	# define IEM_SLAT_FAIL_LINEAR_TO_PAGE_TABLE RT_BIT_32(1)
3065	/** @} */
3066
3067	DECLCALLBACK(FNPGMPHYSHANDLER) iemVmxApicAccessPageHandler;
3068	# ifndef IN_RING3
3069	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) iemVmxApicAccessPagePfHandler;
3070	# endif
3071	#endif
3072
3073	/**
3074	* Indicates to the verifier that the given flag set is undefined.
3075	*
3076	* Can be invoked again to add more flags.
3077	*
3078	* This is a NOOP if the verifier isn't compiled in.
3079	*
3080	* @note We're temporarily keeping this until code is converted to new
3081	* disassembler style opcode handling.
3082	*/
3083	#define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
3084
3085
3086	/** @def IEM_DECL_IMPL_TYPE
3087	* For typedef'ing an instruction implementation function.
3088	*
3089	* @param a_RetType The return type.
3090	* @param a_Name The name of the type.
3091	* @param a_ArgList The argument list enclosed in parentheses.
3092	*/
3093
3094	/** @def IEM_DECL_IMPL_DEF
3095	* For defining an instruction implementation function.
3096	*
3097	* @param a_RetType The return type.
3098	* @param a_Name The name of the type.
3099	* @param a_ArgList The argument list enclosed in parentheses.
3100	*/
3101
3102	#if defined(__GNUC__) && defined(RT_ARCH_X86)
3103	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
3104	__attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
3105	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
3106	__attribute__((__fastcall__, __nothrow__)) DECL_HIDDEN_ONLY(a_RetType) a_Name a_ArgList
3107	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
3108	__attribute__((__fastcall__, __nothrow__)) DECL_HIDDEN_ONLY(a_RetType) a_Name a_ArgList
3109
3110	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
3111	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
3112	a_RetType (__fastcall a_Name) a_ArgList
3113	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
3114	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
3115	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
3116	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
3117
3118	#elif __cplusplus >= 201700 /* P0012R1 support */
3119	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
3120	a_RetType (VBOXCALL a_Name) a_ArgList RT_NOEXCEPT
3121	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
3122	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList RT_NOEXCEPT
3123	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
3124	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList RT_NOEXCEPT
3125
3126	#else
3127	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
3128	a_RetType (VBOXCALL a_Name) a_ArgList
3129	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
3130	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList
3131	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
3132	DECL_HIDDEN_ONLY(a_RetType) VBOXCALL a_Name a_ArgList
3133
3134	#endif
3135
3136	/** Defined in IEMAllAImplC.cpp but also used by IEMAllAImplA.asm. */
3137	RT_C_DECLS_BEGIN
3138	extern uint8_t const g_afParity[256];
3139	RT_C_DECLS_END
3140
3141
3142	/** @name Arithmetic assignment operations on bytes (binary).
3143	* @{ */
3144	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU8, (uint32_t fEFlagsIn, uint8_t *pu8Dst, uint8_t u8Src));
3145	typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
3146	FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
3147	FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
3148	FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
3149	FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
3150	FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
3151	FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
3152	FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
3153	/** @} */
3154
3155	/** @name Arithmetic assignment operations on words (binary).
3156	* @{ */
3157	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU16, (uint32_t fEFlagsIn, uint16_t *pu16Dst, uint16_t u16Src));
3158	typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
3159	FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
3160	FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
3161	FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
3162	FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
3163	FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
3164	FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
3165	FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
3166	/** @} */
3167
3168
3169	/** @name Arithmetic assignment operations on double words (binary).
3170	* @{ */
3171	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU32, (uint32_t fEFlagsIn, uint32_t *pu32Dst, uint32_t u32Src));
3172	typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
3173	FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
3174	FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
3175	FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
3176	FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
3177	FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
3178	FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
3179	FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
3180	FNIEMAIMPLBINU32 iemAImpl_blsi_u32, iemAImpl_blsi_u32_fallback;
3181	FNIEMAIMPLBINU32 iemAImpl_blsr_u32, iemAImpl_blsr_u32_fallback;
3182	FNIEMAIMPLBINU32 iemAImpl_blsmsk_u32, iemAImpl_blsmsk_u32_fallback;
3183	/** @} */
3184
3185	/** @name Arithmetic assignment operations on quad words (binary).
3186	* @{ */
3187	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU64, (uint32_t fEFlagsIn, uint64_t *pu64Dst, uint64_t u64Src));
3188	typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
3189	FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
3190	FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
3191	FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
3192	FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
3193	FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
3194	FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
3195	FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
3196	FNIEMAIMPLBINU64 iemAImpl_blsi_u64, iemAImpl_blsi_u64_fallback;
3197	FNIEMAIMPLBINU64 iemAImpl_blsr_u64, iemAImpl_blsr_u64_fallback;
3198	FNIEMAIMPLBINU64 iemAImpl_blsmsk_u64, iemAImpl_blsmsk_u64_fallback;
3199	/** @} */
3200
3201	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU8, (uint32_t fEFlagsIn, uint8_t const *pu8Dst, uint8_t u8Src));
3202	typedef FNIEMAIMPLBINROU8 *PFNIEMAIMPLBINROU8;
3203	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU16,(uint32_t fEFlagsIn, uint16_t const *pu16Dst, uint16_t u16Src));
3204	typedef FNIEMAIMPLBINROU16 *PFNIEMAIMPLBINROU16;
3205	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU32,(uint32_t fEFlagsIn, uint32_t const *pu32Dst, uint32_t u32Src));
3206	typedef FNIEMAIMPLBINROU32 *PFNIEMAIMPLBINROU32;
3207	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU64,(uint32_t fEFlagsIn, uint64_t const *pu64Dst, uint64_t u64Src));
3208	typedef FNIEMAIMPLBINROU64 *PFNIEMAIMPLBINROU64;
3209
3210	/** @name Compare operations (thrown in with the binary ops).
3211	* @{ */
3212	FNIEMAIMPLBINROU8 iemAImpl_cmp_u8;
3213	FNIEMAIMPLBINROU16 iemAImpl_cmp_u16;
3214	FNIEMAIMPLBINROU32 iemAImpl_cmp_u32;
3215	FNIEMAIMPLBINROU64 iemAImpl_cmp_u64;
3216	/** @} */
3217
3218	/** @name Test operations (thrown in with the binary ops).
3219	* @{ */
3220	FNIEMAIMPLBINROU8 iemAImpl_test_u8;
3221	FNIEMAIMPLBINROU16 iemAImpl_test_u16;
3222	FNIEMAIMPLBINROU32 iemAImpl_test_u32;
3223	FNIEMAIMPLBINROU64 iemAImpl_test_u64;
3224	/** @} */
3225
3226	/** @name Bit operations operations (thrown in with the binary ops).
3227	* @{ */
3228	FNIEMAIMPLBINROU16 iemAImpl_bt_u16;
3229	FNIEMAIMPLBINROU32 iemAImpl_bt_u32;
3230	FNIEMAIMPLBINROU64 iemAImpl_bt_u64;
3231	FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
3232	FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
3233	FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
3234	FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
3235	FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
3236	FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
3237	FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
3238	FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
3239	FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
3240	/** @} */
3241
3242	/** @name Arithmetic three operand operations on double words (binary).
3243	* @{ */
3244	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32, (uint32_t pu32Dst, uint32_t u32Src1, uint32_t u32Src2, uint32_t pEFlags));
3245	typedef FNIEMAIMPLBINVEXU32 *PFNIEMAIMPLBINVEXU32;
3246	FNIEMAIMPLBINVEXU32 iemAImpl_andn_u32, iemAImpl_andn_u32_fallback;
3247	FNIEMAIMPLBINVEXU32 iemAImpl_bextr_u32, iemAImpl_bextr_u32_fallback;
3248	FNIEMAIMPLBINVEXU32 iemAImpl_bzhi_u32, iemAImpl_bzhi_u32_fallback;
3249	/** @} */
3250
3251	/** @name Arithmetic three operand operations on quad words (binary).
3252	* @{ */
3253	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64, (uint64_t pu64Dst, uint64_t u64Src1, uint64_t u64Src2, uint32_t pEFlags));
3254	typedef FNIEMAIMPLBINVEXU64 *PFNIEMAIMPLBINVEXU64;
3255	FNIEMAIMPLBINVEXU64 iemAImpl_andn_u64, iemAImpl_andn_u64_fallback;
3256	FNIEMAIMPLBINVEXU64 iemAImpl_bextr_u64, iemAImpl_bextr_u64_fallback;
3257	FNIEMAIMPLBINVEXU64 iemAImpl_bzhi_u64, iemAImpl_bzhi_u64_fallback;
3258	/** @} */
3259
3260	/** @name Arithmetic three operand operations on double words w/o EFLAGS (binary).
3261	* @{ */
3262	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32NOEFL, (uint32_t *pu32Dst, uint32_t u32Src1, uint32_t u32Src2));
3263	typedef FNIEMAIMPLBINVEXU32NOEFL *PFNIEMAIMPLBINVEXU32NOEFL;
3264	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pdep_u32, iemAImpl_pdep_u32_fallback;
3265	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pext_u32, iemAImpl_pext_u32_fallback;
3266	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_sarx_u32, iemAImpl_sarx_u32_fallback;
3267	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shlx_u32, iemAImpl_shlx_u32_fallback;
3268	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shrx_u32, iemAImpl_shrx_u32_fallback;
3269	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_rorx_u32;
3270	/** @} */
3271
3272	/** @name Arithmetic three operand operations on quad words w/o EFLAGS (binary).
3273	* @{ */
3274	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64NOEFL, (uint64_t *pu64Dst, uint64_t u64Src1, uint64_t u64Src2));
3275	typedef FNIEMAIMPLBINVEXU64NOEFL *PFNIEMAIMPLBINVEXU64NOEFL;
3276	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pdep_u64, iemAImpl_pdep_u64_fallback;
3277	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pext_u64, iemAImpl_pext_u64_fallback;
3278	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_sarx_u64, iemAImpl_sarx_u64_fallback;
3279	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shlx_u64, iemAImpl_shlx_u64_fallback;
3280	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shrx_u64, iemAImpl_shrx_u64_fallback;
3281	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_rorx_u64;
3282	/** @} */
3283
3284	/** @name MULX 32-bit and 64-bit.
3285	* @{ */
3286	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU32, (uint32_t puDst1, uint32_t puDst2, uint32_t uSrc1, uint32_t uSrc2));
3287	typedef FNIEMAIMPLMULXVEXU32 *PFNIEMAIMPLMULXVEXU32;
3288	FNIEMAIMPLMULXVEXU32 iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback;
3289
3290	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU64, (uint64_t puDst1, uint64_t puDst2, uint64_t uSrc1, uint64_t uSrc2));
3291	typedef FNIEMAIMPLMULXVEXU64 *PFNIEMAIMPLMULXVEXU64;
3292	FNIEMAIMPLMULXVEXU64 iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback;
3293	/** @} */
3294
3295
3296	/** @name Exchange memory with register operations.
3297	* @{ */
3298	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_locked, (uint8_t pu8Mem, uint8_t pu8Reg));
3299	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_locked,(uint16_t pu16Mem, uint16_t pu16Reg));
3300	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_locked,(uint32_t pu32Mem, uint32_t pu32Reg));
3301	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_locked,(uint64_t pu64Mem, uint64_t pu64Reg));
3302	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_unlocked, (uint8_t pu8Mem, uint8_t pu8Reg));
3303	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_unlocked,(uint16_t pu16Mem, uint16_t pu16Reg));
3304	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_unlocked,(uint32_t pu32Mem, uint32_t pu32Reg));
3305	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_unlocked,(uint64_t pu64Mem, uint64_t pu64Reg));
3306	/** @} */
3307
3308	/** @name Exchange and add operations.
3309	* @{ */
3310	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
3311	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
3312	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
3313	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
3314	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
3315	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
3316	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
3317	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
3318	/** @} */
3319
3320	/** @name Compare and exchange.
3321	* @{ */
3322	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
3323	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
3324	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
3325	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
3326	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
3327	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
3328	#if ARCH_BITS == 32
3329	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
3330	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
3331	#else
3332	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
3333	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
3334	#endif
3335	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
3336	uint32_t *pEFlags));
3337	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
3338	uint32_t *pEFlags));
3339	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
3340	uint32_t *pEFlags));
3341	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
3342	uint32_t *pEFlags));
3343	#ifndef RT_ARCH_ARM64
3344	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
3345	PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
3346	#endif
3347	/** @} */
3348
3349	/** @name Memory ordering
3350	* @{ */
3351	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
3352	typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
3353	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
3354	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
3355	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
3356	#ifndef RT_ARCH_ARM64
3357	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
3358	#endif
3359	/** @} */
3360
3361	/** @name Double precision shifts
3362	* @{ */
3363	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t pEFlags));
3364	typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
3365	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t pEFlags));
3366	typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
3367	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t pEFlags));
3368	typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
3369	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16, iemAImpl_shld_u16_amd, iemAImpl_shld_u16_intel;
3370	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32, iemAImpl_shld_u32_amd, iemAImpl_shld_u32_intel;
3371	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64, iemAImpl_shld_u64_amd, iemAImpl_shld_u64_intel;
3372	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16, iemAImpl_shrd_u16_amd, iemAImpl_shrd_u16_intel;
3373	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32, iemAImpl_shrd_u32_amd, iemAImpl_shrd_u32_intel;
3374	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64, iemAImpl_shrd_u64_amd, iemAImpl_shrd_u64_intel;
3375	/** @} */
3376
3377
3378	/** @name Bit search operations (thrown in with the binary ops).
3379	* @{ */
3380	FNIEMAIMPLBINU16 iemAImpl_bsf_u16, iemAImpl_bsf_u16_amd, iemAImpl_bsf_u16_intel;
3381	FNIEMAIMPLBINU32 iemAImpl_bsf_u32, iemAImpl_bsf_u32_amd, iemAImpl_bsf_u32_intel;
3382	FNIEMAIMPLBINU64 iemAImpl_bsf_u64, iemAImpl_bsf_u64_amd, iemAImpl_bsf_u64_intel;
3383	FNIEMAIMPLBINU16 iemAImpl_bsr_u16, iemAImpl_bsr_u16_amd, iemAImpl_bsr_u16_intel;
3384	FNIEMAIMPLBINU32 iemAImpl_bsr_u32, iemAImpl_bsr_u32_amd, iemAImpl_bsr_u32_intel;
3385	FNIEMAIMPLBINU64 iemAImpl_bsr_u64, iemAImpl_bsr_u64_amd, iemAImpl_bsr_u64_intel;
3386	FNIEMAIMPLBINU16 iemAImpl_lzcnt_u16, iemAImpl_lzcnt_u16_amd, iemAImpl_lzcnt_u16_intel;
3387	FNIEMAIMPLBINU32 iemAImpl_lzcnt_u32, iemAImpl_lzcnt_u32_amd, iemAImpl_lzcnt_u32_intel;
3388	FNIEMAIMPLBINU64 iemAImpl_lzcnt_u64, iemAImpl_lzcnt_u64_amd, iemAImpl_lzcnt_u64_intel;
3389	FNIEMAIMPLBINU16 iemAImpl_tzcnt_u16, iemAImpl_tzcnt_u16_amd, iemAImpl_tzcnt_u16_intel;
3390	FNIEMAIMPLBINU32 iemAImpl_tzcnt_u32, iemAImpl_tzcnt_u32_amd, iemAImpl_tzcnt_u32_intel;
3391	FNIEMAIMPLBINU64 iemAImpl_tzcnt_u64, iemAImpl_tzcnt_u64_amd, iemAImpl_tzcnt_u64_intel;
3392	FNIEMAIMPLBINU16 iemAImpl_popcnt_u16, iemAImpl_popcnt_u16_fallback;
3393	FNIEMAIMPLBINU32 iemAImpl_popcnt_u32, iemAImpl_popcnt_u32_fallback;
3394	FNIEMAIMPLBINU64 iemAImpl_popcnt_u64, iemAImpl_popcnt_u64_fallback;
3395	/** @} */
3396
3397	/** @name Signed multiplication operations (thrown in with the binary ops).
3398	* @{ */
3399	FNIEMAIMPLBINU16 iemAImpl_imul_two_u16, iemAImpl_imul_two_u16_amd, iemAImpl_imul_two_u16_intel;
3400	FNIEMAIMPLBINU32 iemAImpl_imul_two_u32, iemAImpl_imul_two_u32_amd, iemAImpl_imul_two_u32_intel;
3401	FNIEMAIMPLBINU64 iemAImpl_imul_two_u64, iemAImpl_imul_two_u64_amd, iemAImpl_imul_two_u64_intel;
3402	/** @} */
3403
3404	/** @name Arithmetic assignment operations on bytes (unary).
3405	* @{ */
3406	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t pu8Dst, uint32_t pEFlags));
3407	typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
3408	FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
3409	FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
3410	FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
3411	FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
3412	/** @} */
3413
3414	/** @name Arithmetic assignment operations on words (unary).
3415	* @{ */
3416	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t pu16Dst, uint32_t pEFlags));
3417	typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
3418	FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
3419	FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
3420	FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
3421	FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
3422	/** @} */
3423
3424	/** @name Arithmetic assignment operations on double words (unary).
3425	* @{ */
3426	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t pu32Dst, uint32_t pEFlags));
3427	typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
3428	FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
3429	FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
3430	FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
3431	FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
3432	/** @} */
3433
3434	/** @name Arithmetic assignment operations on quad words (unary).
3435	* @{ */
3436	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t pu64Dst, uint32_t pEFlags));
3437	typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
3438	FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
3439	FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
3440	FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
3441	FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
3442	/** @} */
3443
3444
3445	/** @name Shift operations on bytes (Group 2).
3446	* @{ */
3447	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU8,(uint32_t fEFlagsIn, uint8_t *pu8Dst, uint8_t cShift));
3448	typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
3449	FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8, iemAImpl_rol_u8_amd, iemAImpl_rol_u8_intel;
3450	FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8, iemAImpl_ror_u8_amd, iemAImpl_ror_u8_intel;
3451	FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8, iemAImpl_rcl_u8_amd, iemAImpl_rcl_u8_intel;
3452	FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8, iemAImpl_rcr_u8_amd, iemAImpl_rcr_u8_intel;
3453	FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8, iemAImpl_shl_u8_amd, iemAImpl_shl_u8_intel;
3454	FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8, iemAImpl_shr_u8_amd, iemAImpl_shr_u8_intel;
3455	FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8, iemAImpl_sar_u8_amd, iemAImpl_sar_u8_intel;
3456	/** @} */
3457
3458	/** @name Shift operations on words (Group 2).
3459	* @{ */
3460	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU16,(uint32_t fEFlagsIn, uint16_t *pu16Dst, uint8_t cShift));
3461	typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
3462	FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16, iemAImpl_rol_u16_amd, iemAImpl_rol_u16_intel;
3463	FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16, iemAImpl_ror_u16_amd, iemAImpl_ror_u16_intel;
3464	FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16, iemAImpl_rcl_u16_amd, iemAImpl_rcl_u16_intel;
3465	FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16, iemAImpl_rcr_u16_amd, iemAImpl_rcr_u16_intel;
3466	FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16, iemAImpl_shl_u16_amd, iemAImpl_shl_u16_intel;
3467	FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16, iemAImpl_shr_u16_amd, iemAImpl_shr_u16_intel;
3468	FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16, iemAImpl_sar_u16_amd, iemAImpl_sar_u16_intel;
3469	/** @} */
3470
3471	/** @name Shift operations on double words (Group 2).
3472	* @{ */
3473	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU32,(uint32_t fEFlagsIn, uint32_t *pu32Dst, uint8_t cShift));
3474	typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
3475	FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32, iemAImpl_rol_u32_amd, iemAImpl_rol_u32_intel;
3476	FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32, iemAImpl_ror_u32_amd, iemAImpl_ror_u32_intel;
3477	FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32, iemAImpl_rcl_u32_amd, iemAImpl_rcl_u32_intel;
3478	FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32, iemAImpl_rcr_u32_amd, iemAImpl_rcr_u32_intel;
3479	FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32, iemAImpl_shl_u32_amd, iemAImpl_shl_u32_intel;
3480	FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32, iemAImpl_shr_u32_amd, iemAImpl_shr_u32_intel;
3481	FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32, iemAImpl_sar_u32_amd, iemAImpl_sar_u32_intel;
3482	/** @} */
3483
3484	/** @name Shift operations on words (Group 2).
3485	* @{ */
3486	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSHIFTU64,(uint32_t fEFlagsIn, uint64_t *pu64Dst, uint8_t cShift));
3487	typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
3488	FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64, iemAImpl_rol_u64_amd, iemAImpl_rol_u64_intel;
3489	FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64, iemAImpl_ror_u64_amd, iemAImpl_ror_u64_intel;
3490	FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64, iemAImpl_rcl_u64_amd, iemAImpl_rcl_u64_intel;
3491	FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64, iemAImpl_rcr_u64_amd, iemAImpl_rcr_u64_intel;
3492	FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64, iemAImpl_shl_u64_amd, iemAImpl_shl_u64_intel;
3493	FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64, iemAImpl_shr_u64_amd, iemAImpl_shr_u64_intel;
3494	FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64, iemAImpl_sar_u64_amd, iemAImpl_sar_u64_intel;
3495	/** @} */
3496
3497	/** @name Multiplication and division operations.
3498	* @{ */
3499	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t pu16AX, uint8_t u8FactorDivisor, uint32_t pEFlags));
3500	typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
3501	FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_mul_u8_amd, iemAImpl_mul_u8_intel;
3502	FNIEMAIMPLMULDIVU8 iemAImpl_imul_u8, iemAImpl_imul_u8_amd, iemAImpl_imul_u8_intel;
3503	FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_div_u8_amd, iemAImpl_div_u8_intel;
3504	FNIEMAIMPLMULDIVU8 iemAImpl_idiv_u8, iemAImpl_idiv_u8_amd, iemAImpl_idiv_u8_intel;
3505
3506	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t pu16AX, uint16_t pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
3507	typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
3508	FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_mul_u16_amd, iemAImpl_mul_u16_intel;
3509	FNIEMAIMPLMULDIVU16 iemAImpl_imul_u16, iemAImpl_imul_u16_amd, iemAImpl_imul_u16_intel;
3510	FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_div_u16_amd, iemAImpl_div_u16_intel;
3511	FNIEMAIMPLMULDIVU16 iemAImpl_idiv_u16, iemAImpl_idiv_u16_amd, iemAImpl_idiv_u16_intel;
3512
3513	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t pu32EAX, uint32_t pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
3514	typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
3515	FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_mul_u32_amd, iemAImpl_mul_u32_intel;
3516	FNIEMAIMPLMULDIVU32 iemAImpl_imul_u32, iemAImpl_imul_u32_amd, iemAImpl_imul_u32_intel;
3517	FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_div_u32_amd, iemAImpl_div_u32_intel;
3518	FNIEMAIMPLMULDIVU32 iemAImpl_idiv_u32, iemAImpl_idiv_u32_amd, iemAImpl_idiv_u32_intel;
3519
3520	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t pu64RAX, uint64_t pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
3521	typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
3522	FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_mul_u64_amd, iemAImpl_mul_u64_intel;
3523	FNIEMAIMPLMULDIVU64 iemAImpl_imul_u64, iemAImpl_imul_u64_amd, iemAImpl_imul_u64_intel;
3524	FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_div_u64_amd, iemAImpl_div_u64_intel;
3525	FNIEMAIMPLMULDIVU64 iemAImpl_idiv_u64, iemAImpl_idiv_u64_amd, iemAImpl_idiv_u64_intel;
3526	/** @} */
3527
3528	/** @name Byte Swap.
3529	* @{ */
3530	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t pu32Dst)); / Yes, 32-bit register access. */
3531	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
3532	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
3533	/** @} */
3534
3535	/** @name Misc.
3536	* @{ */
3537	FNIEMAIMPLBINU16 iemAImpl_arpl;
3538	/** @} */
3539
3540	/** @name RDRAND and RDSEED
3541	* @{ */
3542	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU16,(uint16_t puDst, uint32_t pEFlags));
3543	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU32,(uint32_t puDst, uint32_t pEFlags));
3544	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU64,(uint64_t puDst, uint32_t pEFlags));
3545	typedef FNIEMAIMPLRDRANDSEEDU16 *PFNIEMAIMPLRDRANDSEEDU16;
3546	typedef FNIEMAIMPLRDRANDSEEDU32 *PFNIEMAIMPLRDRANDSEEDU32;
3547	typedef FNIEMAIMPLRDRANDSEEDU64 *PFNIEMAIMPLRDRANDSEEDU64;
3548
3549	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdrand_u16, iemAImpl_rdrand_u16_fallback;
3550	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdrand_u32, iemAImpl_rdrand_u32_fallback;
3551	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdrand_u64, iemAImpl_rdrand_u64_fallback;
3552	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdseed_u16, iemAImpl_rdseed_u16_fallback;
3553	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdseed_u32, iemAImpl_rdseed_u32_fallback;
3554	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdseed_u64, iemAImpl_rdseed_u64_fallback;
3555	/** @} */
3556
3557	/** @name ADOX and ADCX
3558	* @{ */
3559	FNIEMAIMPLBINU32 iemAImpl_adcx_u32, iemAImpl_adcx_u32_fallback;
3560	FNIEMAIMPLBINU64 iemAImpl_adcx_u64, iemAImpl_adcx_u64_fallback;
3561	FNIEMAIMPLBINU32 iemAImpl_adox_u32, iemAImpl_adox_u32_fallback;
3562	FNIEMAIMPLBINU64 iemAImpl_adox_u64, iemAImpl_adox_u64_fallback;
3563	/** @} */
3564
3565	/** @name FPU operations taking a 32-bit float argument
3566	* @{ */
3567	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3568	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
3569	typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
3570
3571	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3572	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
3573	typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
3574
3575	FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
3576	FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
3577	FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
3578	FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
3579	FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
3580	FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
3581	FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
3582
3583	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
3584	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3585	PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
3586	/** @} */
3587
3588	/** @name FPU operations taking a 64-bit float argument
3589	* @{ */
3590	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3591	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
3592	typedef FNIEMAIMPLFPUR64FSW *PFNIEMAIMPLFPUR64FSW;
3593
3594	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3595	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
3596	typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
3597
3598	FNIEMAIMPLFPUR64FSW iemAImpl_fcom_r80_by_r64;
3599	FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
3600	FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
3601	FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
3602	FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
3603	FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
3604	FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
3605
3606	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
3607	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3608	PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
3609	/** @} */
3610
3611	/** @name FPU operations taking a 80-bit float argument
3612	* @{ */
3613	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3614	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
3615	typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
3616	FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
3617	FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
3618	FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
3619	FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
3620	FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
3621	FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
3622	FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
3623	FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
3624	FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
3625
3626	FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80, iemAImpl_fpatan_r80_by_r80_amd, iemAImpl_fpatan_r80_by_r80_intel;
3627	FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80, iemAImpl_fyl2x_r80_by_r80_amd, iemAImpl_fyl2x_r80_by_r80_intel;
3628	FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80, iemAImpl_fyl2xp1_r80_by_r80_amd, iemAImpl_fyl2xp1_r80_by_r80_intel;
3629
3630	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3631	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
3632	typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
3633	FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
3634	FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
3635
3636	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
3637	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
3638	typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
3639	FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
3640	FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
3641
3642	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
3643	typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
3644	FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
3645	FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
3646	FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80, iemAImpl_f2xm1_r80_amd, iemAImpl_f2xm1_r80_intel;
3647	FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
3648	FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
3649	FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80, iemAImpl_fsin_r80_amd, iemAImpl_fsin_r80_intel;
3650	FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80, iemAImpl_fcos_r80_amd, iemAImpl_fcos_r80_intel;
3651
3652	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
3653	typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
3654	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
3655	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
3656
3657	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
3658	typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
3659	FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
3660	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
3661	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
3662	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
3663	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
3664	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
3665	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
3666
3667	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
3668	PCRTFLOAT80U pr80Val));
3669	typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
3670	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80, iemAImpl_fptan_r80_r80_amd, iemAImpl_fptan_r80_r80_intel;
3671	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
3672	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80, iemAImpl_fsincos_r80_r80_amd, iemAImpl_fsincos_r80_r80_intel;
3673
3674	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
3675	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3676	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
3677
3678	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_d80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTPBCD80U pd80Val));
3679	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_d80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
3680	PRTPBCD80U pd80Dst, PCRTFLOAT80U pr80Src));
3681
3682	/** @} */
3683
3684	/** @name FPU operations taking a 16-bit signed integer argument
3685	* @{ */
3686	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3687	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
3688	typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
3689	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI16,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3690	int16_t *pi16Dst, PCRTFLOAT80U pr80Src));
3691	typedef FNIEMAIMPLFPUSTR80TOI16 *PFNIEMAIMPLFPUSTR80TOI16;
3692
3693	FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
3694	FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
3695	FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
3696	FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
3697	FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
3698	FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
3699
3700	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3701	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
3702	typedef FNIEMAIMPLFPUI16FSW *PFNIEMAIMPLFPUI16FSW;
3703	FNIEMAIMPLFPUI16FSW iemAImpl_ficom_r80_by_i16;
3704
3705	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
3706	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fist_r80_to_i16;
3707	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fistt_r80_to_i16, iemAImpl_fistt_r80_to_i16_amd, iemAImpl_fistt_r80_to_i16_intel;
3708	/** @} */
3709
3710	/** @name FPU operations taking a 32-bit signed integer argument
3711	* @{ */
3712	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
3713	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
3714	typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
3715	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI32,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3716	int32_t *pi32Dst, PCRTFLOAT80U pr80Src));
3717	typedef FNIEMAIMPLFPUSTR80TOI32 *PFNIEMAIMPLFPUSTR80TOI32;
3718
3719	FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
3720	FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
3721	FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
3722	FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
3723	FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
3724	FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
3725
3726	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
3727	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
3728	typedef FNIEMAIMPLFPUI32FSW *PFNIEMAIMPLFPUI32FSW;
3729	FNIEMAIMPLFPUI32FSW iemAImpl_ficom_r80_by_i32;
3730
3731	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
3732	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fist_r80_to_i32;
3733	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fistt_r80_to_i32;
3734	/** @} */
3735
3736	/** @name FPU operations taking a 64-bit signed integer argument
3737	* @{ */
3738	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI64,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
3739	int64_t *pi64Dst, PCRTFLOAT80U pr80Src));
3740	typedef FNIEMAIMPLFPUSTR80TOI64 *PFNIEMAIMPLFPUSTR80TOI64;
3741
3742	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
3743	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fist_r80_to_i64;
3744	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fistt_r80_to_i64;
3745	/** @} */
3746
3747
3748	/** Temporary type representing a 256-bit vector register. */
3749	typedef struct { uint64_t au64[4]; } IEMVMM256;
3750	/** Temporary type pointing to a 256-bit vector register. */
3751	typedef IEMVMM256 *PIEMVMM256;
3752	/** Temporary type pointing to a const 256-bit vector register. */
3753	typedef IEMVMM256 *PCIEMVMM256;
3754
3755
3756	/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
3757	* @{ */
3758	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t puDst, uint64_t const puSrc));
3759	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
3760	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF2U128,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
3761	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
3762	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF2U256,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86YMMREG puSrc));
3763	typedef FNIEMAIMPLMEDIAF2U256 *PFNIEMAIMPLMEDIAF2U256;
3764	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF3U128,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
3765	typedef FNIEMAIMPLMEDIAF3U128 *PFNIEMAIMPLMEDIAF3U128;
3766	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF3U256,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86YMMREG puSrc1, PCX86YMMREG puSrc2));
3767	typedef FNIEMAIMPLMEDIAF3U256 *PFNIEMAIMPLMEDIAF3U256;
3768	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U64,(uint64_t puDst, uint64_t const puSrc));
3769	typedef FNIEMAIMPLMEDIAOPTF2U64 *PFNIEMAIMPLMEDIAOPTF2U64;
3770	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128,(PRTUINT128U puDst, PCRTUINT128U puSrc));
3771	typedef FNIEMAIMPLMEDIAOPTF2U128 *PFNIEMAIMPLMEDIAOPTF2U128;
3772	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
3773	typedef FNIEMAIMPLMEDIAOPTF3U128 *PFNIEMAIMPLMEDIAOPTF3U128;
3774	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
3775	typedef FNIEMAIMPLMEDIAOPTF3U256 *PFNIEMAIMPLMEDIAOPTF3U256;
3776	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256,(PRTUINT256U puDst, PCRTUINT256U puSrc));
3777	typedef FNIEMAIMPLMEDIAOPTF2U256 *PFNIEMAIMPLMEDIAOPTF2U256;
3778	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pshufb_u64, iemAImpl_pshufb_u64_fallback;
3779	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pand_u64, iemAImpl_pandn_u64, iemAImpl_por_u64, iemAImpl_pxor_u64;
3780	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
3781	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pcmpgtb_u64, iemAImpl_pcmpgtw_u64, iemAImpl_pcmpgtd_u64;
3782	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddb_u64, iemAImpl_paddsb_u64, iemAImpl_paddusb_u64;
3783	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddw_u64, iemAImpl_paddsw_u64, iemAImpl_paddusw_u64;
3784	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddd_u64;
3785	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_paddq_u64;
3786	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubb_u64, iemAImpl_psubsb_u64, iemAImpl_psubusb_u64;
3787	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubw_u64, iemAImpl_psubsw_u64, iemAImpl_psubusw_u64;
3788	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubd_u64;
3789	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psubq_u64;
3790	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmaddwd_u64, iemAImpl_pmaddwd_u64_fallback;
3791	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmullw_u64, iemAImpl_pmulhw_u64;
3792	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pminub_u64, iemAImpl_pmaxub_u64;
3793	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pminsw_u64, iemAImpl_pmaxsw_u64;
3794	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pabsb_u64, iemAImpl_pabsb_u64_fallback;
3795	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pabsw_u64, iemAImpl_pabsw_u64_fallback;
3796	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pabsd_u64, iemAImpl_pabsd_u64_fallback;
3797	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psignb_u64, iemAImpl_psignb_u64_fallback;
3798	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psignw_u64, iemAImpl_psignw_u64_fallback;
3799	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psignd_u64, iemAImpl_psignd_u64_fallback;
3800	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phaddw_u64, iemAImpl_phaddw_u64_fallback;
3801	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phaddd_u64, iemAImpl_phaddd_u64_fallback;
3802	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phsubw_u64, iemAImpl_phsubw_u64_fallback;
3803	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phsubd_u64, iemAImpl_phsubd_u64_fallback;
3804	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phaddsw_u64, iemAImpl_phaddsw_u64_fallback;
3805	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_phsubsw_u64, iemAImpl_phsubsw_u64_fallback;
3806	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmaddubsw_u64, iemAImpl_pmaddubsw_u64_fallback;
3807	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhrsw_u64, iemAImpl_pmulhrsw_u64_fallback;
3808	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmuludq_u64;
3809	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllw_u64, iemAImpl_psrlw_u64, iemAImpl_psraw_u64;
3810	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pslld_u64, iemAImpl_psrld_u64, iemAImpl_psrad_u64;
3811	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllq_u64, iemAImpl_psrlq_u64;
3812	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packsswb_u64, iemAImpl_packuswb_u64;
3813	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packssdw_u64;
3814	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhuw_u64;
3815	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pavgb_u64, iemAImpl_pavgw_u64;
3816	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psadbw_u64;
3817
3818	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pshufb_u128, iemAImpl_pshufb_u128_fallback;
3819	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pand_u128, iemAImpl_pandn_u128, iemAImpl_por_u128, iemAImpl_pxor_u128;
3820	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
3821	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpeqq_u128, iemAImpl_pcmpeqq_u128_fallback;
3822	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpgtb_u128, iemAImpl_pcmpgtw_u128, iemAImpl_pcmpgtd_u128;
3823	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pcmpgtq_u128, iemAImpl_pcmpgtq_u128_fallback;
3824	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddb_u128, iemAImpl_paddsb_u128, iemAImpl_paddusb_u128;
3825	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddw_u128, iemAImpl_paddsw_u128, iemAImpl_paddusw_u128;
3826	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddd_u128;
3827	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_paddq_u128;
3828	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubb_u128, iemAImpl_psubsb_u128, iemAImpl_psubusb_u128;
3829	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubw_u128, iemAImpl_psubsw_u128, iemAImpl_psubusw_u128;
3830	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubd_u128;
3831	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psubq_u128;
3832	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmullw_u128, iemAImpl_pmullw_u128_fallback;
3833	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhw_u128;
3834	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulld_u128, iemAImpl_pmulld_u128_fallback;
3835	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaddwd_u128, iemAImpl_pmaddwd_u128_fallback;
3836	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminub_u128;
3837	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminud_u128, iemAImpl_pminud_u128_fallback;
3838	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminuw_u128, iemAImpl_pminuw_u128_fallback;
3839	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminsb_u128, iemAImpl_pminsb_u128_fallback;
3840	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminsd_u128, iemAImpl_pminsd_u128_fallback;
3841	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pminsw_u128, iemAImpl_pminsw_u128_fallback;
3842	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxub_u128;
3843	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxud_u128, iemAImpl_pmaxud_u128_fallback;
3844	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxuw_u128, iemAImpl_pmaxuw_u128_fallback;
3845	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxsb_u128, iemAImpl_pmaxsb_u128_fallback;
3846	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxsw_u128;
3847	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaxsd_u128, iemAImpl_pmaxsd_u128_fallback;
3848	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pabsb_u128, iemAImpl_pabsb_u128_fallback;
3849	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pabsw_u128, iemAImpl_pabsw_u128_fallback;
3850	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pabsd_u128, iemAImpl_pabsd_u128_fallback;
3851	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psignb_u128, iemAImpl_psignb_u128_fallback;
3852	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psignw_u128, iemAImpl_psignw_u128_fallback;
3853	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psignd_u128, iemAImpl_psignd_u128_fallback;
3854	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phaddw_u128, iemAImpl_phaddw_u128_fallback;
3855	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phaddd_u128, iemAImpl_phaddd_u128_fallback;
3856	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phsubw_u128, iemAImpl_phsubw_u128_fallback;
3857	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phsubd_u128, iemAImpl_phsubd_u128_fallback;
3858	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phaddsw_u128, iemAImpl_phaddsw_u128_fallback;
3859	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phsubsw_u128, iemAImpl_phsubsw_u128_fallback;
3860	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaddubsw_u128, iemAImpl_pmaddubsw_u128_fallback;
3861	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhrsw_u128, iemAImpl_pmulhrsw_u128_fallback;
3862	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuludq_u128;
3863	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmaddwd_u128, iemAImpl_pmaddwd_u128_fallback;
3864	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packsswb_u128, iemAImpl_packuswb_u128;
3865	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packssdw_u128, iemAImpl_packusdw_u128;
3866	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllw_u128, iemAImpl_psrlw_u128, iemAImpl_psraw_u128;
3867	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pslld_u128, iemAImpl_psrld_u128, iemAImpl_psrad_u128;
3868	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllq_u128, iemAImpl_psrlq_u128;
3869	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhuw_u128;
3870	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pavgb_u128, iemAImpl_pavgw_u128;
3871	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psadbw_u128;
3872	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuldq_u128, iemAImpl_pmuldq_u128_fallback;
3873	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpcklps_u128, iemAImpl_unpcklpd_u128;
3874	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpckhps_u128, iemAImpl_unpckhpd_u128;
3875	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phminposuw_u128, iemAImpl_phminposuw_u128_fallback;
3876
3877	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpshufb_u128, iemAImpl_vpshufb_u128_fallback;
3878	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpand_u128, iemAImpl_vpand_u128_fallback;
3879	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpandn_u128, iemAImpl_vpandn_u128_fallback;
3880	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpor_u128, iemAImpl_vpor_u128_fallback;
3881	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpxor_u128, iemAImpl_vpxor_u128_fallback;
3882	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqb_u128, iemAImpl_vpcmpeqb_u128_fallback;
3883	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqw_u128, iemAImpl_vpcmpeqw_u128_fallback;
3884	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqd_u128, iemAImpl_vpcmpeqd_u128_fallback;
3885	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpeqq_u128, iemAImpl_vpcmpeqq_u128_fallback;
3886	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtb_u128, iemAImpl_vpcmpgtb_u128_fallback;
3887	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtw_u128, iemAImpl_vpcmpgtw_u128_fallback;
3888	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtd_u128, iemAImpl_vpcmpgtd_u128_fallback;
3889	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpcmpgtq_u128, iemAImpl_vpcmpgtq_u128_fallback;
3890	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddb_u128, iemAImpl_vpaddb_u128_fallback;
3891	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddw_u128, iemAImpl_vpaddw_u128_fallback;
3892	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddd_u128, iemAImpl_vpaddd_u128_fallback;
3893	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddq_u128, iemAImpl_vpaddq_u128_fallback;
3894	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubb_u128, iemAImpl_vpsubb_u128_fallback;
3895	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubw_u128, iemAImpl_vpsubw_u128_fallback;
3896	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubd_u128, iemAImpl_vpsubd_u128_fallback;
3897	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubq_u128, iemAImpl_vpsubq_u128_fallback;
3898	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminub_u128, iemAImpl_vpminub_u128_fallback;
3899	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminuw_u128, iemAImpl_vpminuw_u128_fallback;
3900	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminud_u128, iemAImpl_vpminud_u128_fallback;
3901	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminsb_u128, iemAImpl_vpminsb_u128_fallback;
3902	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminsw_u128, iemAImpl_vpminsw_u128_fallback;
3903	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpminsd_u128, iemAImpl_vpminsd_u128_fallback;
3904	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxub_u128, iemAImpl_vpmaxub_u128_fallback;
3905	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxuw_u128, iemAImpl_vpmaxuw_u128_fallback;
3906	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxud_u128, iemAImpl_vpmaxud_u128_fallback;
3907	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxsb_u128, iemAImpl_vpmaxsb_u128_fallback;
3908	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxsw_u128, iemAImpl_vpmaxsw_u128_fallback;
3909	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaxsd_u128, iemAImpl_vpmaxsd_u128_fallback;
3910	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpacksswb_u128, iemAImpl_vpacksswb_u128_fallback;
3911	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackssdw_u128, iemAImpl_vpackssdw_u128_fallback;
3912	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackuswb_u128, iemAImpl_vpackuswb_u128_fallback;
3913	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackusdw_u128, iemAImpl_vpackusdw_u128_fallback;
3914	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmullw_u128, iemAImpl_vpmullw_u128_fallback;
3915	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulld_u128, iemAImpl_vpmulld_u128_fallback;
3916	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhw_u128, iemAImpl_vpmulhw_u128_fallback;
3917	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhuw_u128, iemAImpl_vpmulhuw_u128_fallback;
3918	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgb_u128, iemAImpl_vpavgb_u128_fallback;
3919	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgw_u128, iemAImpl_vpavgw_u128_fallback;
3920	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignb_u128, iemAImpl_vpsignb_u128_fallback;
3921	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignw_u128, iemAImpl_vpsignw_u128_fallback;
3922	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignd_u128, iemAImpl_vpsignd_u128_fallback;
3923	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddw_u128, iemAImpl_vphaddw_u128_fallback;
3924	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddd_u128, iemAImpl_vphaddd_u128_fallback;
3925	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubw_u128, iemAImpl_vphsubw_u128_fallback;
3926	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubd_u128, iemAImpl_vphsubd_u128_fallback;
3927	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddsw_u128, iemAImpl_vphaddsw_u128_fallback;
3928	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubsw_u128, iemAImpl_vphsubsw_u128_fallback;
3929	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddubsw_u128, iemAImpl_vpmaddubsw_u128_fallback;
3930	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhrsw_u128, iemAImpl_vpmulhrsw_u128_fallback;
3931	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsadbw_u128, iemAImpl_vpsadbw_u128_fallback;
3932	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuldq_u128, iemAImpl_vpmuldq_u128_fallback;
3933	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuludq_u128, iemAImpl_vpmuludq_u128_fallback;
3934	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsb_u128, iemAImpl_vpsubsb_u128_fallback;
3935	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubsw_u128, iemAImpl_vpsubsw_u128_fallback;
3936	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusb_u128, iemAImpl_vpsubusb_u128_fallback;
3937	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsubusw_u128, iemAImpl_vpsubusw_u128_fallback;
3938	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusb_u128, iemAImpl_vpaddusb_u128_fallback;
3939	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddusw_u128, iemAImpl_vpaddusw_u128_fallback;
3940	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsb_u128, iemAImpl_vpaddsb_u128_fallback;
3941	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpaddsw_u128, iemAImpl_vpaddsw_u128_fallback;
3942	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllw_u128, iemAImpl_vpsllw_u128_fallback;
3943	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpslld_u128, iemAImpl_vpslld_u128_fallback;
3944	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllq_u128, iemAImpl_vpsllq_u128_fallback;
3945	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsraw_u128, iemAImpl_vpsraw_u128_fallback;
3946	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrad_u128, iemAImpl_vpsrad_u128_fallback;
3947	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlw_u128, iemAImpl_vpsrlw_u128_fallback;
3948	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrld_u128, iemAImpl_vpsrld_u128_fallback;
3949	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlq_u128, iemAImpl_vpsrlq_u128_fallback;
3950	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddwd_u128, iemAImpl_vpmaddwd_u128_fallback;
3951
3952	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsb_u128, iemAImpl_vpabsb_u128_fallback;
3953	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsw_u128, iemAImpl_vpabsd_u128_fallback;
3954	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsd_u128, iemAImpl_vpabsw_u128_fallback;
3955	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vphminposuw_u128, iemAImpl_vphminposuw_u128_fallback;
3956
3957	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpshufb_u256, iemAImpl_vpshufb_u256_fallback;
3958	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpand_u256, iemAImpl_vpand_u256_fallback;
3959	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpandn_u256, iemAImpl_vpandn_u256_fallback;
3960	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpor_u256, iemAImpl_vpor_u256_fallback;
3961	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpxor_u256, iemAImpl_vpxor_u256_fallback;
3962	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqb_u256, iemAImpl_vpcmpeqb_u256_fallback;
3963	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqw_u256, iemAImpl_vpcmpeqw_u256_fallback;
3964	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqd_u256, iemAImpl_vpcmpeqd_u256_fallback;
3965	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpeqq_u256, iemAImpl_vpcmpeqq_u256_fallback;
3966	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtb_u256, iemAImpl_vpcmpgtb_u256_fallback;
3967	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtw_u256, iemAImpl_vpcmpgtw_u256_fallback;
3968	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtd_u256, iemAImpl_vpcmpgtd_u256_fallback;
3969	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpcmpgtq_u256, iemAImpl_vpcmpgtq_u256_fallback;
3970	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddb_u256, iemAImpl_vpaddb_u256_fallback;
3971	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddw_u256, iemAImpl_vpaddw_u256_fallback;
3972	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddd_u256, iemAImpl_vpaddd_u256_fallback;
3973	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddq_u256, iemAImpl_vpaddq_u256_fallback;
3974	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubb_u256, iemAImpl_vpsubb_u256_fallback;
3975	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubw_u256, iemAImpl_vpsubw_u256_fallback;
3976	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubd_u256, iemAImpl_vpsubd_u256_fallback;
3977	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubq_u256, iemAImpl_vpsubq_u256_fallback;
3978	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminub_u256, iemAImpl_vpminub_u256_fallback;
3979	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminuw_u256, iemAImpl_vpminuw_u256_fallback;
3980	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminud_u256, iemAImpl_vpminud_u256_fallback;
3981	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminsb_u256, iemAImpl_vpminsb_u256_fallback;
3982	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminsw_u256, iemAImpl_vpminsw_u256_fallback;
3983	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpminsd_u256, iemAImpl_vpminsd_u256_fallback;
3984	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxub_u256, iemAImpl_vpmaxub_u256_fallback;
3985	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxuw_u256, iemAImpl_vpmaxuw_u256_fallback;
3986	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxud_u256, iemAImpl_vpmaxud_u256_fallback;
3987	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxsb_u256, iemAImpl_vpmaxsb_u256_fallback;
3988	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxsw_u256, iemAImpl_vpmaxsw_u256_fallback;
3989	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaxsd_u256, iemAImpl_vpmaxsd_u256_fallback;
3990	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpacksswb_u256, iemAImpl_vpacksswb_u256_fallback;
3991	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackssdw_u256, iemAImpl_vpackssdw_u256_fallback;
3992	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackuswb_u256, iemAImpl_vpackuswb_u256_fallback;
3993	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackusdw_u256, iemAImpl_vpackusdw_u256_fallback;
3994	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmullw_u256, iemAImpl_vpmullw_u256_fallback;
3995	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulld_u256, iemAImpl_vpmulld_u256_fallback;
3996	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhw_u256, iemAImpl_vpmulhw_u256_fallback;
3997	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhuw_u256, iemAImpl_vpmulhuw_u256_fallback;
3998	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgb_u256, iemAImpl_vpavgb_u256_fallback;
3999	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgw_u256, iemAImpl_vpavgw_u256_fallback;
4000	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignb_u256, iemAImpl_vpsignb_u256_fallback;
4001	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignw_u256, iemAImpl_vpsignw_u256_fallback;
4002	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignd_u256, iemAImpl_vpsignd_u256_fallback;
4003	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddw_u256, iemAImpl_vphaddw_u256_fallback;
4004	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddd_u256, iemAImpl_vphaddd_u256_fallback;
4005	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubw_u256, iemAImpl_vphsubw_u256_fallback;
4006	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubd_u256, iemAImpl_vphsubd_u256_fallback;
4007	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddsw_u256, iemAImpl_vphaddsw_u256_fallback;
4008	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubsw_u256, iemAImpl_vphsubsw_u256_fallback;
4009	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddubsw_u256, iemAImpl_vpmaddubsw_u256_fallback;
4010	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhrsw_u256, iemAImpl_vpmulhrsw_u256_fallback;
4011	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsadbw_u256, iemAImpl_vpsadbw_u256_fallback;
4012	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuldq_u256, iemAImpl_vpmuldq_u256_fallback;
4013	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuludq_u256, iemAImpl_vpmuludq_u256_fallback;
4014	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsb_u256, iemAImpl_vpsubsb_u256_fallback;
4015	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubsw_u256, iemAImpl_vpsubsw_u256_fallback;
4016	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusb_u256, iemAImpl_vpsubusb_u256_fallback;
4017	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsubusw_u256, iemAImpl_vpsubusw_u256_fallback;
4018	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusb_u256, iemAImpl_vpaddusb_u256_fallback;
4019	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddusw_u256, iemAImpl_vpaddusw_u256_fallback;
4020	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsb_u256, iemAImpl_vpaddsb_u256_fallback;
4021	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpaddsw_u256, iemAImpl_vpaddsw_u256_fallback;
4022	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllw_u256, iemAImpl_vpsllw_u256_fallback;
4023	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpslld_u256, iemAImpl_vpslld_u256_fallback;
4024	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllq_u256, iemAImpl_vpsllq_u256_fallback;
4025	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsraw_u256, iemAImpl_vpsraw_u256_fallback;
4026	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrad_u256, iemAImpl_vpsrad_u256_fallback;
4027	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlw_u256, iemAImpl_vpsrlw_u256_fallback;
4028	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrld_u256, iemAImpl_vpsrld_u256_fallback;
4029	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlq_u256, iemAImpl_vpsrlq_u256_fallback;
4030	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddwd_u256, iemAImpl_vpmaddwd_u256_fallback;
4031	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpermps_u256, iemAImpl_vpermps_u256_fallback;
4032	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpermd_u256, iemAImpl_vpermd_u256_fallback;
4033
4034	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsb_u256, iemAImpl_vpabsb_u256_fallback;
4035	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsw_u256, iemAImpl_vpabsw_u256_fallback;
4036	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsd_u256, iemAImpl_vpabsd_u256_fallback;
4037	/** @} */
4038
4039	/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
4040	* @{ */
4041	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
4042	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
4043	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpcklbw_u128, iemAImpl_vpunpcklbw_u128_fallback,
4044	iemAImpl_vpunpcklwd_u128, iemAImpl_vpunpcklwd_u128_fallback,
4045	iemAImpl_vpunpckldq_u128, iemAImpl_vpunpckldq_u128_fallback,
4046	iemAImpl_vpunpcklqdq_u128, iemAImpl_vpunpcklqdq_u128_fallback,
4047	iemAImpl_vunpcklps_u128, iemAImpl_vunpcklps_u128_fallback,
4048	iemAImpl_vunpcklpd_u128, iemAImpl_vunpcklpd_u128_fallback,
4049	iemAImpl_vunpckhps_u128, iemAImpl_vunpckhps_u128_fallback,
4050	iemAImpl_vunpckhpd_u128, iemAImpl_vunpckhpd_u128_fallback;
4051
4052	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpcklbw_u256, iemAImpl_vpunpcklbw_u256_fallback,
4053	iemAImpl_vpunpcklwd_u256, iemAImpl_vpunpcklwd_u256_fallback,
4054	iemAImpl_vpunpckldq_u256, iemAImpl_vpunpckldq_u256_fallback,
4055	iemAImpl_vpunpcklqdq_u256, iemAImpl_vpunpcklqdq_u256_fallback,
4056	iemAImpl_vunpcklps_u256, iemAImpl_vunpcklps_u256_fallback,
4057	iemAImpl_vunpcklpd_u256, iemAImpl_vunpcklpd_u256_fallback,
4058	iemAImpl_vunpckhps_u256, iemAImpl_vunpckhps_u256_fallback,
4059	iemAImpl_vunpckhpd_u256, iemAImpl_vunpckhpd_u256_fallback;
4060	/** @} */
4061
4062	/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
4063	* @{ */
4064	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
4065	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
4066	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpckhbw_u128, iemAImpl_vpunpckhbw_u128_fallback,
4067	iemAImpl_vpunpckhwd_u128, iemAImpl_vpunpckhwd_u128_fallback,
4068	iemAImpl_vpunpckhdq_u128, iemAImpl_vpunpckhdq_u128_fallback,
4069	iemAImpl_vpunpckhqdq_u128, iemAImpl_vpunpckhqdq_u128_fallback;
4070	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpckhbw_u256, iemAImpl_vpunpckhbw_u256_fallback,
4071	iemAImpl_vpunpckhwd_u256, iemAImpl_vpunpckhwd_u256_fallback,
4072	iemAImpl_vpunpckhdq_u256, iemAImpl_vpunpckhdq_u256_fallback,
4073	iemAImpl_vpunpckhqdq_u256, iemAImpl_vpunpckhqdq_u256_fallback;
4074	/** @} */
4075
4076	/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
4077	* @{ */
4078	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
4079	typedef FNIEMAIMPLMEDIAPSHUFU128 *PFNIEMAIMPLMEDIAPSHUFU128;
4080	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
4081	typedef FNIEMAIMPLMEDIAPSHUFU256 *PFNIEMAIMPLMEDIAPSHUFU256;
4082	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw_u64,(uint64_t puDst, uint64_t const puSrc, uint8_t bEvil));
4083	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_pshufhw_u128, iemAImpl_pshuflw_u128, iemAImpl_pshufd_u128;
4084	#ifndef IEM_WITHOUT_ASSEMBLY
4085	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256, iemAImpl_vpshuflw_u256, iemAImpl_vpshufd_u256;
4086	#endif
4087	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256_fallback, iemAImpl_vpshuflw_u256_fallback, iemAImpl_vpshufd_u256_fallback;
4088	/** @} */
4089
4090	/** @name Media (SSE/MMX/AVX) operation: Shift Immediate Stuff (evil)
4091	* @{ */
4092	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU64,(uint64_t *puDst, uint8_t bShift));
4093	typedef FNIEMAIMPLMEDIAPSHIFTU64 *PFNIEMAIMPLMEDIAPSHIFTU64;
4094	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU128,(PRTUINT128U puDst, uint8_t bShift));
4095	typedef FNIEMAIMPLMEDIAPSHIFTU128 *PFNIEMAIMPLMEDIAPSHIFTU128;
4096	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU256,(PRTUINT256U puDst, uint8_t bShift));
4097	typedef FNIEMAIMPLMEDIAPSHIFTU256 *PFNIEMAIMPLMEDIAPSHIFTU256;
4098	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psllw_imm_u64, iemAImpl_pslld_imm_u64, iemAImpl_psllq_imm_u64;
4099	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psrlw_imm_u64, iemAImpl_psrld_imm_u64, iemAImpl_psrlq_imm_u64;
4100	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psraw_imm_u64, iemAImpl_psrad_imm_u64;
4101	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psllw_imm_u128, iemAImpl_pslld_imm_u128, iemAImpl_psllq_imm_u128;
4102	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psrlw_imm_u128, iemAImpl_psrld_imm_u128, iemAImpl_psrlq_imm_u128;
4103	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psraw_imm_u128, iemAImpl_psrad_imm_u128;
4104	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_pslldq_imm_u128, iemAImpl_psrldq_imm_u128;
4105	/** @} */
4106
4107	/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
4108	* @{ */
4109	IEM_DECL_IMPL_DEF(void, iemAImpl_maskmovq_u64,(uint64_t puMem, uint64_t const puSrc, uint64_t const *puMsk));
4110	IEM_DECL_IMPL_DEF(void, iemAImpl_maskmovdqu_u128,(PRTUINT128U puMem, PCRTUINT128U puSrc, PCRTUINT128U puMsk));
4111	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(uint64_t pu64Dst, uint64_t const puSrc));
4112	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(uint64_t *pu64Dst, PCRTUINT128U puSrc));
4113	#ifndef IEM_WITHOUT_ASSEMBLY
4114	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
4115	#endif
4116	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256_fallback,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
4117	/** @} */
4118
4119	/** @name Media (SSE/MMX/AVX) operations: Variable Blend Packed Bytes/R32/R64.
4120	* @{ */
4121	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puMask));
4122	typedef FNIEMAIMPLBLENDU128 *PFNIEMAIMPLBLENDU128;
4123	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, PCRTUINT128U puMask));
4124	typedef FNIEMAIMPLAVXBLENDU128 *PFNIEMAIMPLAVXBLENDU128;
4125	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, PCRTUINT256U puMask));
4126	typedef FNIEMAIMPLAVXBLENDU256 *PFNIEMAIMPLAVXBLENDU256;
4127
4128	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128;
4129	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128_fallback;
4130	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128;
4131	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128_fallback;
4132	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256;
4133	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256_fallback;
4134
4135	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128;
4136	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128_fallback;
4137	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128;
4138	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128_fallback;
4139	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256;
4140	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256_fallback;
4141
4142	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128;
4143	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128_fallback;
4144	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128;
4145	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128_fallback;
4146	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256;
4147	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256_fallback;
4148	/** @} */
4149
4150
4151	/** @name Media (SSE/MMX/AVX) operation: Sort this later
4152	* @{ */
4153	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
4154	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
4155	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
4156	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4157	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4158
4159	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
4160	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
4161	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
4162	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4163	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4164
4165	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
4166	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
4167	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
4168	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4169	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4170
4171	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
4172	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
4173	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
4174	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4175	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4176
4177	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
4178	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
4179	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
4180	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4181	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4182
4183	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
4184	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
4185	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
4186	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4187	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4188
4189	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
4190	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
4191	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
4192	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4193	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4194
4195	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
4196	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
4197	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
4198	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4199	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4200
4201	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
4202	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
4203	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
4204	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4205	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4206
4207	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
4208	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
4209	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
4210	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4211	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4212
4213	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
4214	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
4215	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
4216	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4217	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4218
4219	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
4220	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
4221	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
4222	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4223	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
4224
4225	IEM_DECL_IMPL_DEF(void, iemAImpl_shufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
4226	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
4227	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
4228	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
4229	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
4230
4231	IEM_DECL_IMPL_DEF(void, iemAImpl_shufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
4232	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
4233	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
4234	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
4235	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
4236
4237	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
4238	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64_fallback,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
4239
4240	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
4241	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
4242	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
4243	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
4244	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
4245
4246	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
4247	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
4248	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
4249	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
4250	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
4251
4252
4253	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
4254	typedef FNIEMAIMPLMEDIAOPTF2U128IMM8 *PFNIEMAIMPLMEDIAOPTF2U128IMM8;
4255	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
4256	typedef FNIEMAIMPLMEDIAOPTF2U256IMM8 *PFNIEMAIMPLMEDIAOPTF2U256IMM8;
4257	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
4258	typedef FNIEMAIMPLMEDIAOPTF3U128IMM8 *PFNIEMAIMPLMEDIAOPTF3U128IMM8;
4259	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
4260	typedef FNIEMAIMPLMEDIAOPTF3U256IMM8 *PFNIEMAIMPLMEDIAOPTF3U256IMM8;
4261
4262	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_palignr_u128, iemAImpl_palignr_u128_fallback;
4263	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pblendw_u128, iemAImpl_pblendw_u128_fallback;
4264	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendps_u128, iemAImpl_blendps_u128_fallback;
4265	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendpd_u128, iemAImpl_blendpd_u128_fallback;
4266
4267	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpalignr_u128, iemAImpl_vpalignr_u128_fallback;
4268	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendw_u128, iemAImpl_vpblendw_u128_fallback;
4269	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendd_u128, iemAImpl_vpblendd_u128_fallback;
4270	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendps_u128, iemAImpl_vblendps_u128_fallback;
4271	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendpd_u128, iemAImpl_vblendpd_u128_fallback;
4272
4273	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpalignr_u256, iemAImpl_vpalignr_u256_fallback;
4274	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendw_u256, iemAImpl_vpblendw_u256_fallback;
4275	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendd_u256, iemAImpl_vpblendd_u256_fallback;
4276	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendps_u256, iemAImpl_vblendps_u256_fallback;
4277	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendpd_u256, iemAImpl_vblendpd_u256_fallback;
4278	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2i128_u256, iemAImpl_vperm2i128_u256_fallback;
4279	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vperm2f128_u256, iemAImpl_vperm2f128_u256_fallback;
4280
4281	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesimc_u128, iemAImpl_aesimc_u128_fallback;
4282	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenc_u128, iemAImpl_aesenc_u128_fallback;
4283	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenclast_u128, iemAImpl_aesenclast_u128_fallback;
4284	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdec_u128, iemAImpl_aesdec_u128_fallback;
4285	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdeclast_u128, iemAImpl_aesdeclast_u128_fallback;
4286
4287	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesimc_u128, iemAImpl_vaesimc_u128_fallback;
4288	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vaesenc_u128, iemAImpl_vaesenc_u128_fallback;
4289	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vaesenclast_u128, iemAImpl_vaesenclast_u128_fallback;
4290	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vaesdec_u128, iemAImpl_vaesdec_u128_fallback;
4291	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vaesdeclast_u128, iemAImpl_vaesdeclast_u128_fallback;
4292
4293	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_aeskeygenassist_u128, iemAImpl_aeskeygenassist_u128_fallback;
4294
4295	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_vaeskeygenassist_u128, iemAImpl_vaeskeygenassist_u128_fallback;
4296
4297	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1nexte_u128, iemAImpl_sha1nexte_u128_fallback;
4298	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg1_u128, iemAImpl_sha1msg1_u128_fallback;
4299	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg2_u128, iemAImpl_sha1msg2_u128_fallback;
4300	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg1_u128, iemAImpl_sha256msg1_u128_fallback;
4301	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg2_u128, iemAImpl_sha256msg2_u128_fallback;
4302	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_sha1rnds4_u128, iemAImpl_sha1rnds4_u128_fallback;
4303	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
4304	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
4305
4306	FNIEMAIMPLMEDIAOPTF2U256IMM8 iemAImpl_vpermq_u256, iemAImpl_vpermq_u256_fallback;
4307	FNIEMAIMPLMEDIAOPTF2U256IMM8 iemAImpl_vpermpd_u256, iemAImpl_vpermpd_u256_fallback;
4308
4309	typedef struct IEMPCMPISTRXSRC
4310	{
4311	RTUINT128U uSrc1;
4312	RTUINT128U uSrc2;
4313	} IEMPCMPISTRXSRC;
4314	typedef IEMPCMPISTRXSRC *PIEMPCMPISTRXSRC;
4315	typedef const IEMPCMPISTRXSRC *PCIEMPCMPISTRXSRC;
4316
4317	typedef struct IEMPCMPESTRXSRC
4318	{
4319	RTUINT128U uSrc1;
4320	RTUINT128U uSrc2;
4321	uint64_t u64Rax;
4322	uint64_t u64Rdx;
4323	} IEMPCMPESTRXSRC;
4324	typedef IEMPCMPESTRXSRC *PIEMPCMPESTRXSRC;
4325	typedef const IEMPCMPESTRXSRC *PCIEMPCMPESTRXSRC;
4326
4327	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLPCMPISTRIU128IMM8,(uint32_t *pEFlags, PCRTUINT128U pSrc1, PCRTUINT128U pSrc2, uint8_t bEvil));
4328	typedef FNIEMAIMPLPCMPISTRIU128IMM8 *PFNIEMAIMPLPCMPISTRIU128IMM8;
4329	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRIU128IMM8,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
4330	typedef FNIEMAIMPLPCMPESTRIU128IMM8 *PFNIEMAIMPLPCMPESTRIU128IMM8;
4331
4332	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPISTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
4333	typedef FNIEMAIMPLPCMPISTRMU128IMM8 *PFNIEMAIMPLPCMPISTRMU128IMM8;
4334	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
4335	typedef FNIEMAIMPLPCMPESTRMU128IMM8 *PFNIEMAIMPLPCMPESTRMU128IMM8;
4336
4337	FNIEMAIMPLPCMPISTRIU128IMM8 iemAImpl_pcmpistri_u128, iemAImpl_pcmpistri_u128_fallback;
4338	FNIEMAIMPLPCMPESTRIU128IMM8 iemAImpl_pcmpestri_u128, iemAImpl_pcmpestri_u128_fallback;
4339	FNIEMAIMPLPCMPISTRMU128IMM8 iemAImpl_pcmpistrm_u128, iemAImpl_pcmpistrm_u128_fallback;
4340	FNIEMAIMPLPCMPESTRMU128IMM8 iemAImpl_pcmpestrm_u128, iemAImpl_pcmpestrm_u128_fallback;
4341	FNIEMAIMPLPCMPISTRIU128IMM8 iemAImpl_vpcmpistri_u128, iemAImpl_vpcmpistri_u128_fallback;
4342	FNIEMAIMPLPCMPESTRIU128IMM8 iemAImpl_vpcmpestri_u128, iemAImpl_vpcmpestri_u128_fallback;
4343	FNIEMAIMPLPCMPISTRMU128IMM8 iemAImpl_vpcmpistrm_u128, iemAImpl_vpcmpistrm_u128_fallback;
4344	FNIEMAIMPLPCMPESTRMU128IMM8 iemAImpl_vpcmpestrm_u128, iemAImpl_vpcmpestrm_u128_fallback;
4345
4346
4347	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pclmulqdq_u128, iemAImpl_pclmulqdq_u128_fallback;
4348	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpclmulqdq_u128, iemAImpl_vpclmulqdq_u128_fallback;
4349
4350	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_mpsadbw_u128, iemAImpl_mpsadbw_u128_fallback;
4351	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vmpsadbw_u128, iemAImpl_vmpsadbw_u128_fallback;
4352	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vmpsadbw_u256, iemAImpl_vmpsadbw_u256_fallback;
4353
4354	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsllw_imm_u128, iemAImpl_vpsllw_imm_u128_fallback;
4355	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsllw_imm_u256, iemAImpl_vpsllw_imm_u256_fallback;
4356	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpslld_imm_u128, iemAImpl_vpslld_imm_u128_fallback;
4357	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpslld_imm_u256, iemAImpl_vpslld_imm_u256_fallback;
4358	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsllq_imm_u128, iemAImpl_vpsllq_imm_u128_fallback;
4359	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsllq_imm_u256, iemAImpl_vpsllq_imm_u256_fallback;
4360	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
4361	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
4362	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
4363	IEM_DECL_IMPL_DEF(void, iemAImpl_vpslldq_imm_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
4364
4365	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsraw_imm_u128, iemAImpl_vpsraw_imm_u128_fallback;
4366	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsraw_imm_u256, iemAImpl_vpsraw_imm_u256_fallback;
4367	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrad_imm_u128, iemAImpl_vpsrad_imm_u128_fallback;
4368	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrad_imm_u256, iemAImpl_vpsrad_imm_u256_fallback;
4369
4370	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrlw_imm_u128, iemAImpl_vpsrlw_imm_u128_fallback;
4371	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrlw_imm_u256, iemAImpl_vpsrlw_imm_u256_fallback;
4372	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrld_imm_u128, iemAImpl_vpsrld_imm_u128_fallback;
4373	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrld_imm_u256, iemAImpl_vpsrld_imm_u256_fallback;
4374	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrlq_imm_u128, iemAImpl_vpsrlq_imm_u128_fallback;
4375	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrlq_imm_u256, iemAImpl_vpsrlq_imm_u256_fallback;
4376	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
4377	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t uShift));
4378	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
4379	IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrldq_imm_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t uShift));
4380
4381	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpermilps_u128, iemAImpl_vpermilps_u128_fallback;
4382	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_vpermilps_imm_u128, iemAImpl_vpermilps_imm_u128_fallback;
4383	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpermilps_u256, iemAImpl_vpermilps_u256_fallback;
4384	FNIEMAIMPLMEDIAOPTF2U256IMM8 iemAImpl_vpermilps_imm_u256, iemAImpl_vpermilps_imm_u256_fallback;
4385
4386	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpermilpd_u128, iemAImpl_vpermilpd_u128_fallback;
4387	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_vpermilpd_imm_u128, iemAImpl_vpermilpd_imm_u128_fallback;
4388	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpermilpd_u256, iemAImpl_vpermilpd_u256_fallback;
4389	FNIEMAIMPLMEDIAOPTF2U256IMM8 iemAImpl_vpermilpd_imm_u256, iemAImpl_vpermilpd_imm_u256_fallback;
4390
4391	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllvd_u128, iemAImpl_vpsllvd_u128_fallback;
4392	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllvd_u256, iemAImpl_vpsllvd_u256_fallback;
4393	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllvq_u128, iemAImpl_vpsllvq_u128_fallback;
4394	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllvq_u256, iemAImpl_vpsllvq_u256_fallback;
4395	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsravd_u128, iemAImpl_vpsravd_u128_fallback;
4396	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsravd_u256, iemAImpl_vpsravd_u256_fallback;
4397	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlvd_u128, iemAImpl_vpsrlvd_u128_fallback;
4398	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlvd_u256, iemAImpl_vpsrlvd_u256_fallback;
4399	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlvq_u128, iemAImpl_vpsrlvq_u128_fallback;
4400	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlvq_u256, iemAImpl_vpsrlvq_u256_fallback;
4401	/** @} */
4402
4403	/** @name Media Odds and Ends
4404	* @{ */
4405	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U8,(uint32_t *puDst, uint8_t uSrc));
4406	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U16,(uint32_t *puDst, uint16_t uSrc));
4407	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U32,(uint32_t *puDst, uint32_t uSrc));
4408	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U64,(uint32_t *puDst, uint64_t uSrc));
4409	FNIEMAIMPLCR32U8 iemAImpl_crc32_u8, iemAImpl_crc32_u8_fallback;
4410	FNIEMAIMPLCR32U16 iemAImpl_crc32_u16, iemAImpl_crc32_u16_fallback;
4411	FNIEMAIMPLCR32U32 iemAImpl_crc32_u32, iemAImpl_crc32_u32_fallback;
4412	FNIEMAIMPLCR32U64 iemAImpl_crc32_u64, iemAImpl_crc32_u64_fallback;
4413
4414	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL128,(PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint32_t *pEFlags));
4415	typedef FNIEMAIMPLF2EFL128 *PFNIEMAIMPLF2EFL128;
4416	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL256,(PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint32_t *pEFlags));
4417	typedef FNIEMAIMPLF2EFL256 *PFNIEMAIMPLF2EFL256;
4418	FNIEMAIMPLF2EFL128 iemAImpl_ptest_u128;
4419	FNIEMAIMPLF2EFL256 iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback;
4420	FNIEMAIMPLF2EFL128 iemAImpl_vtestps_u128, iemAImpl_vtestps_u128_fallback;
4421	FNIEMAIMPLF2EFL256 iemAImpl_vtestps_u256, iemAImpl_vtestps_u256_fallback;
4422	FNIEMAIMPLF2EFL128 iemAImpl_vtestpd_u128, iemAImpl_vtestpd_u128_fallback;
4423	FNIEMAIMPLF2EFL256 iemAImpl_vtestpd_u256, iemAImpl_vtestpd_u256_fallback;
4424
4425	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I32U64,(uint32_t uMxCsrIn, int32_t pi32Dst, const uint64_t pu64Src)); /* pu64Src is a double precision floating point. */
4426	typedef FNIEMAIMPLSSEF2I32U64 *PFNIEMAIMPLSSEF2I32U64;
4427	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I64U64,(uint32_t uMxCsrIn, int64_t pi64Dst, const uint64_t pu64Src)); /* pu64Src is a double precision floating point. */
4428	typedef FNIEMAIMPLSSEF2I64U64 *PFNIEMAIMPLSSEF2I64U64;
4429	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I32U32,(uint32_t uMxCsrIn, int32_t pi32Dst, const uint32_t pu32Src)); /* pu32Src is a single precision floating point. */
4430	typedef FNIEMAIMPLSSEF2I32U32 *PFNIEMAIMPLSSEF2I32U32;
4431	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I64U32,(uint32_t uMxCsrIn, int64_t pi64Dst, const uint32_t pu32Src)); /* pu32Src is a single precision floating point. */
4432	typedef FNIEMAIMPLSSEF2I64U32 *PFNIEMAIMPLSSEF2I64U32;
4433	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I32R32,(uint32_t uMxCsrIn, int32_t *pi32Dst, PCRTFLOAT32U pr32Src));
4434	typedef FNIEMAIMPLSSEF2I32R32 *PFNIEMAIMPLSSEF2I32R32;
4435	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I64R32,(uint32_t uMxCsrIn, int64_t *pi64Dst, PCRTFLOAT32U pr32Src));
4436	typedef FNIEMAIMPLSSEF2I64R32 *PFNIEMAIMPLSSEF2I64R32;
4437	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I32R64,(uint32_t uMxCsrIn, int32_t *pi32Dst, PCRTFLOAT64U pr64Src));
4438	typedef FNIEMAIMPLSSEF2I32R64 *PFNIEMAIMPLSSEF2I32R64;
4439	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I64R64,(uint32_t uMxCsrIn, int64_t *pi64Dst, PCRTFLOAT64U pr64Src));
4440	typedef FNIEMAIMPLSSEF2I64R64 *PFNIEMAIMPLSSEF2I64R64;
4441
4442	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvttsd2si_i32_r64;
4443	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvtsd2si_i32_r64;
4444
4445	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvttsd2si_i64_r64;
4446	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvtsd2si_i64_r64;
4447
4448	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvttss2si_i32_r32;
4449	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvtss2si_i32_r32;
4450
4451	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvttss2si_i64_r32;
4452	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvtss2si_i64_r32;
4453
4454	FNIEMAIMPLSSEF2I32R32 iemAImpl_vcvttss2si_i32_r32, iemAImpl_vcvttss2si_i32_r32_fallback;
4455	FNIEMAIMPLSSEF2I64R32 iemAImpl_vcvttss2si_i64_r32, iemAImpl_vcvttss2si_i64_r32_fallback;
4456	FNIEMAIMPLSSEF2I32R32 iemAImpl_vcvtss2si_i32_r32, iemAImpl_vcvtss2si_i32_r32_fallback;
4457	FNIEMAIMPLSSEF2I64R32 iemAImpl_vcvtss2si_i64_r32, iemAImpl_vcvtss2si_i64_r32_fallback;
4458
4459	FNIEMAIMPLSSEF2I32R64 iemAImpl_vcvttss2si_i32_r64, iemAImpl_vcvttss2si_i32_r64_fallback;
4460	FNIEMAIMPLSSEF2I64R64 iemAImpl_vcvttss2si_i64_r64, iemAImpl_vcvttss2si_i64_r64_fallback;
4461	FNIEMAIMPLSSEF2I32R64 iemAImpl_vcvtss2si_i32_r64, iemAImpl_vcvtss2si_i32_r64_fallback;
4462	FNIEMAIMPLSSEF2I64R64 iemAImpl_vcvtss2si_i64_r64, iemAImpl_vcvtss2si_i64_r64_fallback;
4463
4464	FNIEMAIMPLSSEF2I32R32 iemAImpl_vcvttsd2si_i32_r32, iemAImpl_vcvttsd2si_i32_r32_fallback;
4465	FNIEMAIMPLSSEF2I64R32 iemAImpl_vcvttsd2si_i64_r32, iemAImpl_vcvttsd2si_i64_r32_fallback;
4466	FNIEMAIMPLSSEF2I32R32 iemAImpl_vcvtsd2si_i32_r32, iemAImpl_vcvtsd2si_i32_r32_fallback;
4467	FNIEMAIMPLSSEF2I64R32 iemAImpl_vcvtsd2si_i64_r32, iemAImpl_vcvtsd2si_i64_r32_fallback;
4468
4469	FNIEMAIMPLSSEF2I32R64 iemAImpl_vcvttsd2si_i32_r64, iemAImpl_vcvttsd2si_i32_r64_fallback;
4470	FNIEMAIMPLSSEF2I64R64 iemAImpl_vcvttsd2si_i64_r64, iemAImpl_vcvttsd2si_i64_r64_fallback;
4471	FNIEMAIMPLSSEF2I32R64 iemAImpl_vcvtsd2si_i32_r64, iemAImpl_vcvtsd2si_i32_r64_fallback;
4472	FNIEMAIMPLSSEF2I64R64 iemAImpl_vcvtsd2si_i64_r64, iemAImpl_vcvtsd2si_i64_r64_fallback;
4473
4474	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R32I32,(uint32_t uMxCsrIn, PRTFLOAT32U pr32Dst, const int32_t *pi32Src));
4475	typedef FNIEMAIMPLSSEF2R32I32 *PFNIEMAIMPLSSEF2R32I32;
4476	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R32I64,(uint32_t uMxCsrIn, PRTFLOAT32U pr32Dst, const int64_t *pi64Src));
4477	typedef FNIEMAIMPLSSEF2R32I64 *PFNIEMAIMPLSSEF2R32I64;
4478
4479	FNIEMAIMPLSSEF2R32I32 iemAImpl_cvtsi2ss_r32_i32;
4480	FNIEMAIMPLSSEF2R32I64 iemAImpl_cvtsi2ss_r32_i64;
4481
4482	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLAVXF3XMMI32,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc, const int32_t *pi32Src));
4483	typedef FNIEMAIMPLAVXF3XMMI32 *PFNIEMAIMPLAVXF3XMMI32;
4484	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLAVXF3XMMI64,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc, const int64_t *pi64Src));
4485	typedef FNIEMAIMPLAVXF3XMMI64 *PFNIEMAIMPLAVXF3XMMI64;
4486
4487	FNIEMAIMPLAVXF3XMMI32 iemAImpl_vcvtsi2ss_u128_i32, iemAImpl_vcvtsi2ss_u128_i32_fallback;
4488	FNIEMAIMPLAVXF3XMMI64 iemAImpl_vcvtsi2ss_u128_i64, iemAImpl_vcvtsi2ss_u128_i64_fallback;
4489
4490
4491	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R64I32,(uint32_t uMxCsrIn, PRTFLOAT64U pr64Dst, const int32_t *pi32Src));
4492	typedef FNIEMAIMPLSSEF2R64I32 *PFNIEMAIMPLSSEF2R64I32;
4493	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R64I64,(uint32_t uMxCsrIn, PRTFLOAT64U pr64Dst, const int64_t *pi64Src));
4494	typedef FNIEMAIMPLSSEF2R64I64 *PFNIEMAIMPLSSEF2R64I64;
4495
4496	FNIEMAIMPLSSEF2R64I32 iemAImpl_cvtsi2sd_r64_i32;
4497	FNIEMAIMPLSSEF2R64I64 iemAImpl_cvtsi2sd_r64_i64;
4498
4499	FNIEMAIMPLAVXF3XMMI32 iemAImpl_vcvtsi2sd_u128_i32, iemAImpl_vcvtsi2sd_u128_i32_fallback;
4500	FNIEMAIMPLAVXF3XMMI64 iemAImpl_vcvtsi2sd_u128_i64, iemAImpl_vcvtsi2sd_u128_i64_fallback;
4501
4502	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtps2pd_u128_u64,(uint32_t uMxCsrIn, PX86XMMREG puDst, const uint64_t pu64Src)); / Actually two single precision floating point values. */
4503	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtps2pd_u128_u64_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, const uint64_t pu64Src)); / Actually two single precision floating point values. */
4504	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtps2pd_u256_u128,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86XMMREG puSrc));
4505	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtps2pd_u256_u128_fallback,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86XMMREG puSrc));
4506
4507
4508	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtdq2pd_u128_u64,(uint32_t uMxCsrIn, PX86XMMREG puDst, const uint64_t pu64Src)); / Actually two single precision floating point values. */
4509	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtdq2pd_u128_u64_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, const uint64_t pu64Src)); / Actually two single precision floating point values. */
4510	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtdq2pd_u256_u128,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86XMMREG puSrc));
4511	IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcvtdq2pd_u256_u128_fallback,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86XMMREG puSrc));
4512
4513
4514	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLF2EFLMXCSRR32R32,(uint32_t uMxCsrIn, uint32_t *pfEFlags, RTFLOAT32U uSrc1, RTFLOAT32U uSrc2));
4515	typedef FNIEMAIMPLF2EFLMXCSRR32R32 *PFNIEMAIMPLF2EFLMXCSRR32R32;
4516
4517	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLF2EFLMXCSRR64R64,(uint32_t uMxCsrIn, uint32_t *pfEFlags, RTFLOAT64U uSrc1, RTFLOAT64U uSrc2));
4518	typedef FNIEMAIMPLF2EFLMXCSRR64R64 *PFNIEMAIMPLF2EFLMXCSRR64R64;
4519
4520	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_ucomiss_u128;
4521	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback;
4522
4523	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_ucomisd_u128;
4524	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback;
4525
4526	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_comiss_u128;
4527	FNIEMAIMPLF2EFLMXCSRR32R32 iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback;
4528
4529	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_comisd_u128;
4530	FNIEMAIMPLF2EFLMXCSRR64R64 iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback;
4531
4532
4533	typedef struct IEMMEDIAF2XMMSRC
4534	{
4535	X86XMMREG uSrc1;
4536	X86XMMREG uSrc2;
4537	} IEMMEDIAF2XMMSRC;
4538	typedef IEMMEDIAF2XMMSRC *PIEMMEDIAF2XMMSRC;
4539	typedef const IEMMEDIAF2XMMSRC *PCIEMMEDIAF2XMMSRC;
4540
4541
4542	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF3XMMIMM8,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCIEMMEDIAF2XMMSRC puSrc, uint8_t bEvil));
4543	typedef FNIEMAIMPLMEDIAF3XMMIMM8 *PFNIEMAIMPLMEDIAF3XMMIMM8;
4544
4545
4546	typedef struct IEMMEDIAF2YMMSRC
4547	{
4548	X86YMMREG uSrc1;
4549	X86YMMREG uSrc2;
4550	} IEMMEDIAF2YMMSRC;
4551	typedef IEMMEDIAF2YMMSRC *PIEMMEDIAF2YMMSRC;
4552	typedef const IEMMEDIAF2YMMSRC *PCIEMMEDIAF2YMMSRC;
4553
4554
4555	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF3YMMIMM8,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCIEMMEDIAF2YMMSRC puSrc, uint8_t bEvil));
4556	typedef FNIEMAIMPLMEDIAF3YMMIMM8 *PFNIEMAIMPLMEDIAF3YMMIMM8;
4557
4558
4559	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_cmpps_u128;
4560	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_cmppd_u128;
4561	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_cmpss_u128;
4562	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_cmpsd_u128;
4563
4564	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vcmpps_u128, iemAImpl_vcmpps_u128_fallback;
4565	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vcmppd_u128, iemAImpl_vcmppd_u128_fallback;
4566	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vcmpss_u128, iemAImpl_vcmpss_u128_fallback;
4567	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vcmpsd_u128, iemAImpl_vcmpsd_u128_fallback;
4568
4569	FNIEMAIMPLMEDIAF3YMMIMM8 iemAImpl_vcmpps_u256, iemAImpl_vcmpps_u256_fallback;
4570	FNIEMAIMPLMEDIAF3YMMIMM8 iemAImpl_vcmppd_u256, iemAImpl_vcmppd_u256_fallback;
4571
4572	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_roundss_u128;
4573	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_roundsd_u128;
4574
4575	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_dpps_u128, iemAImpl_dpps_u128_fallback;
4576	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_dppd_u128, iemAImpl_dppd_u128_fallback;
4577
4578
4579	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF2U128IMM8,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc, uint8_t bEvil));
4580	typedef FNIEMAIMPLMEDIAF2U128IMM8 *PFNIEMAIMPLMEDIAF2U128IMM8;
4581
4582
4583	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMEDIAF2U256IMM8,(uint32_t uMxCsrIn, PX86YMMREG puDst, PCX86YMMREG puSrc, uint8_t bEvil));
4584	typedef FNIEMAIMPLMEDIAF2U256IMM8 *PFNIEMAIMPLMEDIAF2U256IMM8;
4585
4586
4587	FNIEMAIMPLMEDIAF2U128IMM8 iemAImpl_roundps_u128, iemAImpl_roundps_u128_fallback;
4588	FNIEMAIMPLMEDIAF2U128IMM8 iemAImpl_roundpd_u128, iemAImpl_roundpd_u128_fallback;
4589
4590	FNIEMAIMPLMEDIAF2U128IMM8 iemAImpl_vroundps_u128, iemAImpl_vroundps_u128_fallback;
4591	FNIEMAIMPLMEDIAF2U128IMM8 iemAImpl_vroundpd_u128, iemAImpl_vroundpd_u128_fallback;
4592
4593	FNIEMAIMPLMEDIAF2U256IMM8 iemAImpl_vroundps_u256, iemAImpl_vroundps_u256_fallback;
4594	FNIEMAIMPLMEDIAF2U256IMM8 iemAImpl_vroundpd_u256, iemAImpl_vroundpd_u256_fallback;
4595
4596	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vroundss_u128, iemAImpl_vroundss_u128_fallback;
4597	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vroundsd_u128, iemAImpl_vroundsd_u128_fallback;
4598
4599	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vdpps_u128, iemAImpl_vdpps_u128_fallback;
4600	FNIEMAIMPLMEDIAF3XMMIMM8 iemAImpl_vdppd_u128, iemAImpl_vdppd_u128_fallback;
4601
4602	FNIEMAIMPLMEDIAF3YMMIMM8 iemAImpl_vdpps_u256, iemAImpl_vdpps_u256_fallback;
4603
4604
4605	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRU64U128,(uint32_t fMxCsrIn, uint64_t *pu64Dst, PCX86XMMREG pSrc));
4606	typedef FNIEMAIMPLMXCSRU64U128 *PFNIEMAIMPLMXCSRU64U128;
4607
4608	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvtpd2pi_u128;
4609	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvttpd2pi_u128;
4610
4611	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRU128U64,(uint32_t fMxCsrIn, PX86XMMREG pDst, uint64_t u64Src));
4612	typedef FNIEMAIMPLMXCSRU128U64 *PFNIEMAIMPLMXCSRU128U64;
4613
4614	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2ps_u128;
4615	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2pd_u128;
4616
4617	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLMXCSRU64U64,(uint32_t fMxCsrIn, uint64_t *pu64Dst, uint64_t u64Src));
4618	typedef FNIEMAIMPLMXCSRU64U64 *PFNIEMAIMPLMXCSRU64U64;
4619
4620	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvtps2pi_u128;
4621	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvttps2pi_u128;
4622
4623	/** @} */
4624
4625
4626	/** @name Function tables.
4627	* @{
4628	*/
4629
4630	/**
4631	* Function table for a binary operator providing implementation based on
4632	* operand size.
4633	*/
4634	typedef struct IEMOPBINSIZES
4635	{
4636	PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
4637	PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
4638	PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
4639	PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
4640	} IEMOPBINSIZES;
4641	/** Pointer to a binary operator function table. */
4642	typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
4643
4644
4645	/**
4646	* Function table for a unary operator providing implementation based on
4647	* operand size.
4648	*/
4649	typedef struct IEMOPUNARYSIZES
4650	{
4651	PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
4652	PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
4653	PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
4654	PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
4655	} IEMOPUNARYSIZES;
4656	/** Pointer to a unary operator function table. */
4657	typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
4658
4659
4660	/**
4661	* Function table for a shift operator providing implementation based on
4662	* operand size.
4663	*/
4664	typedef struct IEMOPSHIFTSIZES
4665	{
4666	PFNIEMAIMPLSHIFTU8 pfnNormalU8;
4667	PFNIEMAIMPLSHIFTU16 pfnNormalU16;
4668	PFNIEMAIMPLSHIFTU32 pfnNormalU32;
4669	PFNIEMAIMPLSHIFTU64 pfnNormalU64;
4670	} IEMOPSHIFTSIZES;
4671	/** Pointer to a shift operator function table. */
4672	typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
4673
4674
4675	/**
4676	* Function table for a multiplication or division operation.
4677	*/
4678	typedef struct IEMOPMULDIVSIZES
4679	{
4680	PFNIEMAIMPLMULDIVU8 pfnU8;
4681	PFNIEMAIMPLMULDIVU16 pfnU16;
4682	PFNIEMAIMPLMULDIVU32 pfnU32;
4683	PFNIEMAIMPLMULDIVU64 pfnU64;
4684	} IEMOPMULDIVSIZES;
4685	/** Pointer to a multiplication or division operation function table. */
4686	typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
4687
4688
4689	/**
4690	* Function table for a double precision shift operator providing implementation
4691	* based on operand size.
4692	*/
4693	typedef struct IEMOPSHIFTDBLSIZES
4694	{
4695	PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
4696	PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
4697	PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
4698	} IEMOPSHIFTDBLSIZES;
4699	/** Pointer to a double precision shift function table. */
4700	typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
4701
4702
4703	/**
4704	* Function table for media instruction taking two full sized media source
4705	* registers and one full sized destination register (AVX).
4706	*/
4707	typedef struct IEMOPMEDIAF3
4708	{
4709	PFNIEMAIMPLMEDIAF3U128 pfnU128;
4710	PFNIEMAIMPLMEDIAF3U256 pfnU256;
4711	} IEMOPMEDIAF3;
4712	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
4713	typedef IEMOPMEDIAF3 const *PCIEMOPMEDIAF3;
4714
4715	/** @def IEMOPMEDIAF3_INIT_VARS_EX
4716	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4717	* given functions as initializers. For use in AVX functions where a pair of
4718	* functions are only used once and the function table need not be public. */
4719	#ifndef TST_IEM_CHECK_MC
4720	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4721	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4722	static IEMOPMEDIAF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4723	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4724	# else
4725	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4726	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4727	# endif
4728	#else
4729	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4730	#endif
4731	/** @def IEMOPMEDIAF3_INIT_VARS
4732	* Generate AVX function tables for the @a a_InstrNm instruction.
4733	* @sa IEMOPMEDIAF3_INIT_VARS_EX */
4734	#define IEMOPMEDIAF3_INIT_VARS(a_InstrNm) \
4735	IEMOPMEDIAF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4736	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4737
4738
4739	/**
4740	* Function table for media instruction taking one full sized media source
4741	* registers and one full sized destination register (AVX).
4742	*/
4743	typedef struct IEMOPMEDIAF2
4744	{
4745	PFNIEMAIMPLMEDIAF2U128 pfnU128;
4746	PFNIEMAIMPLMEDIAF2U256 pfnU256;
4747	} IEMOPMEDIAF2;
4748	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
4749	typedef IEMOPMEDIAF2 const *PCIEMOPMEDIAF2;
4750
4751	/** @def IEMOPMEDIAF2_INIT_VARS_EX
4752	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4753	* given functions as initializers. For use in AVX functions where a pair of
4754	* functions are only used once and the function table need not be public. */
4755	#ifndef TST_IEM_CHECK_MC
4756	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4757	# define IEMOPMEDIAF2_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4758	static IEMOPMEDIAF2 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4759	static IEMOPMEDIAF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4760	# else
4761	# define IEMOPMEDIAF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4762	static IEMOPMEDIAF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4763	# endif
4764	#else
4765	# define IEMOPMEDIAF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4766	#endif
4767	/** @def IEMOPMEDIAF2_INIT_VARS
4768	* Generate AVX function tables for the @a a_InstrNm instruction.
4769	* @sa IEMOPMEDIAF2_INIT_VARS_EX */
4770	#define IEMOPMEDIAF2_INIT_VARS(a_InstrNm) \
4771	IEMOPMEDIAF2_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4772	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4773
4774
4775	/**
4776	* Function table for media instruction taking two full sized media source
4777	* registers and one full sized destination register, but no additional state
4778	* (AVX).
4779	*/
4780	typedef struct IEMOPMEDIAOPTF3
4781	{
4782	PFNIEMAIMPLMEDIAOPTF3U128 pfnU128;
4783	PFNIEMAIMPLMEDIAOPTF3U256 pfnU256;
4784	} IEMOPMEDIAOPTF3;
4785	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
4786	typedef IEMOPMEDIAOPTF3 const *PCIEMOPMEDIAOPTF3;
4787
4788	/** @def IEMOPMEDIAOPTF3_INIT_VARS_EX
4789	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4790	* given functions as initializers. For use in AVX functions where a pair of
4791	* functions are only used once and the function table need not be public. */
4792	#ifndef TST_IEM_CHECK_MC
4793	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4794	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4795	static IEMOPMEDIAOPTF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4796	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4797	# else
4798	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4799	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4800	# endif
4801	#else
4802	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4803	#endif
4804	/** @def IEMOPMEDIAOPTF3_INIT_VARS
4805	* Generate AVX function tables for the @a a_InstrNm instruction.
4806	* @sa IEMOPMEDIAOPTF3_INIT_VARS_EX */
4807	#define IEMOPMEDIAOPTF3_INIT_VARS(a_InstrNm) \
4808	IEMOPMEDIAOPTF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4809	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4810
4811	/**
4812	* Function table for media instruction taking one full sized media source
4813	* registers and one full sized destination register, but no additional state
4814	* (AVX).
4815	*/
4816	typedef struct IEMOPMEDIAOPTF2
4817	{
4818	PFNIEMAIMPLMEDIAOPTF2U128 pfnU128;
4819	PFNIEMAIMPLMEDIAOPTF2U256 pfnU256;
4820	} IEMOPMEDIAOPTF2;
4821	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
4822	typedef IEMOPMEDIAOPTF2 const *PCIEMOPMEDIAOPTF2;
4823
4824	/** @def IEMOPMEDIAOPTF2_INIT_VARS_EX
4825	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4826	* given functions as initializers. For use in AVX functions where a pair of
4827	* functions are only used once and the function table need not be public. */
4828	#ifndef TST_IEM_CHECK_MC
4829	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4830	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4831	static IEMOPMEDIAOPTF2 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4832	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4833	# else
4834	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4835	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4836	# endif
4837	#else
4838	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4839	#endif
4840	/** @def IEMOPMEDIAOPTF2_INIT_VARS
4841	* Generate AVX function tables for the @a a_InstrNm instruction.
4842	* @sa IEMOPMEDIAOPTF2_INIT_VARS_EX */
4843	#define IEMOPMEDIAOPTF2_INIT_VARS(a_InstrNm) \
4844	IEMOPMEDIAOPTF2_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4845	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4846
4847
4848	/**
4849	* Function table for media instruction taking one full sized media source
4850	* register and one full sized destination register and an 8-bit immediate (AVX).
4851	*/
4852	typedef struct IEMOPMEDIAF2IMM8
4853	{
4854	PFNIEMAIMPLMEDIAF2U128IMM8 pfnU128;
4855	PFNIEMAIMPLMEDIAF2U256IMM8 pfnU256;
4856	} IEMOPMEDIAF2IMM8;
4857	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
4858	typedef IEMOPMEDIAF2IMM8 const *PCIEMOPMEDIAF2IMM8;
4859
4860	/** @def IEMOPMEDIAF2IMM8_INIT_VARS_EX
4861	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4862	* given functions as initializers. For use in AVX functions where a pair of
4863	* functions are only used once and the function table need not be public. */
4864	#ifndef TST_IEM_CHECK_MC
4865	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4866	# define IEMOPMEDIAF2IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4867	static IEMOPMEDIAF2IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4868	static IEMOPMEDIAF2IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4869	# else
4870	# define IEMOPMEDIAF2IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4871	static IEMOPMEDIAF2IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4872	# endif
4873	#else
4874	# define IEMOPMEDIAF2IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4875	#endif
4876	/** @def IEMOPMEDIAF2IMM8_INIT_VARS
4877	* Generate AVX function tables for the @a a_InstrNm instruction.
4878	* @sa IEMOPMEDIAF2IMM8_INIT_VARS_EX */
4879	#define IEMOPMEDIAF2IMM8_INIT_VARS(a_InstrNm) \
4880	IEMOPMEDIAF2IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4881	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4882
4883
4884	/**
4885	* Function table for media instruction taking one full sized media source
4886	* register and one full sized destination register and an 8-bit immediate, but no additional state
4887	* (AVX).
4888	*/
4889	typedef struct IEMOPMEDIAOPTF2IMM8
4890	{
4891	PFNIEMAIMPLMEDIAOPTF2U128IMM8 pfnU128;
4892	PFNIEMAIMPLMEDIAOPTF2U256IMM8 pfnU256;
4893	} IEMOPMEDIAOPTF2IMM8;
4894	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
4895	typedef IEMOPMEDIAOPTF2IMM8 const *PCIEMOPMEDIAOPTF2IMM8;
4896
4897	/** @def IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX
4898	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4899	* given functions as initializers. For use in AVX functions where a pair of
4900	* functions are only used once and the function table need not be public. */
4901	#ifndef TST_IEM_CHECK_MC
4902	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4903	# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4904	static IEMOPMEDIAOPTF2IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4905	static IEMOPMEDIAOPTF2IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4906	# else
4907	# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4908	static IEMOPMEDIAOPTF2IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4909	# endif
4910	#else
4911	# define IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4912	#endif
4913	/** @def IEMOPMEDIAOPTF2IMM8_INIT_VARS
4914	* Generate AVX function tables for the @a a_InstrNm instruction.
4915	* @sa IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX */
4916	#define IEMOPMEDIAOPTF2IMM8_INIT_VARS(a_InstrNm) \
4917	IEMOPMEDIAOPTF2IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u256),\
4918	RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_imm_u256_fallback))
4919
4920	/**
4921	* Function table for media instruction taking two full sized media source
4922	* registers and one full sized destination register and an 8-bit immediate, but no additional state
4923	* (AVX).
4924	*/
4925	typedef struct IEMOPMEDIAOPTF3IMM8
4926	{
4927	PFNIEMAIMPLMEDIAOPTF3U128IMM8 pfnU128;
4928	PFNIEMAIMPLMEDIAOPTF3U256IMM8 pfnU256;
4929	} IEMOPMEDIAOPTF3IMM8;
4930	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
4931	typedef IEMOPMEDIAOPTF3IMM8 const *PCIEMOPMEDIAOPTF3IMM8;
4932
4933	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX
4934	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4935	* given functions as initializers. For use in AVX functions where a pair of
4936	* functions are only used once and the function table need not be public. */
4937	#ifndef TST_IEM_CHECK_MC
4938	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4939	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4940	static IEMOPMEDIAOPTF3IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4941	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4942	# else
4943	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4944	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4945	# endif
4946	#else
4947	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4948	#endif
4949	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS
4950	* Generate AVX function tables for the @a a_InstrNm instruction.
4951	* @sa IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX */
4952	#define IEMOPMEDIAOPTF3IMM8_INIT_VARS(a_InstrNm) \
4953	IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4954	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4955	/** @} */
4956
4957
4958	/**
4959	* Function table for blend type instruction taking three full sized media source
4960	* registers and one full sized destination register, but no additional state
4961	* (AVX).
4962	*/
4963	typedef struct IEMOPBLENDOP
4964	{
4965	PFNIEMAIMPLAVXBLENDU128 pfnU128;
4966	PFNIEMAIMPLAVXBLENDU256 pfnU256;
4967	} IEMOPBLENDOP;
4968	/** Pointer to a media operation function table for 4 full sized ops (AVX). */
4969	typedef IEMOPBLENDOP const *PCIEMOPBLENDOP;
4970
4971	/** @def IEMOPBLENDOP_INIT_VARS_EX
4972	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
4973	* given functions as initializers. For use in AVX functions where a pair of
4974	* functions are only used once and the function table need not be public. */
4975	#ifndef TST_IEM_CHECK_MC
4976	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
4977	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4978	static IEMOPBLENDOP const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
4979	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4980	# else
4981	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
4982	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
4983	# endif
4984	#else
4985	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
4986	#endif
4987	/** @def IEMOPBLENDOP_INIT_VARS
4988	* Generate AVX function tables for the @a a_InstrNm instruction.
4989	* @sa IEMOPBLENDOP_INIT_VARS_EX */
4990	#define IEMOPBLENDOP_INIT_VARS(a_InstrNm) \
4991	IEMOPBLENDOP_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
4992	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
4993
4994
4995	/** @name SSE/AVX single/double precision floating point operations.
4996	* @{ */
4997	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
4998	typedef FNIEMAIMPLFPSSEF2U128 *PFNIEMAIMPLFPSSEF2U128;
4999	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128R32,(uint32_t uMxCsrIn, PX86XMMREG Result, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
5000	typedef FNIEMAIMPLFPSSEF2U128R32 *PFNIEMAIMPLFPSSEF2U128R32;
5001	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128R64,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
5002	typedef FNIEMAIMPLFPSSEF2U128R64 *PFNIEMAIMPLFPSSEF2U128R64;
5003
5004	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
5005	typedef FNIEMAIMPLFPAVXF3U128 *PFNIEMAIMPLFPAVXF3U128;
5006	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U128R32,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
5007	typedef FNIEMAIMPLFPAVXF3U128R32 *PFNIEMAIMPLFPAVXF3U128R32;
5008	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U128R64,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
5009	typedef FNIEMAIMPLFPAVXF3U128R64 *PFNIEMAIMPLFPAVXF3U128R64;
5010
5011	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPAVXF3U256,(uint32_t uMxCsrIn, PX86YMMREG pResult, PCX86YMMREG puSrc1, PCX86YMMREG puSrc2));
5012	typedef FNIEMAIMPLFPAVXF3U256 *PFNIEMAIMPLFPAVXF3U256;
5013
5014	FNIEMAIMPLFPSSEF2U128 iemAImpl_addps_u128;
5015	FNIEMAIMPLFPSSEF2U128 iemAImpl_addpd_u128;
5016	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulps_u128;
5017	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulpd_u128;
5018	FNIEMAIMPLFPSSEF2U128 iemAImpl_subps_u128;
5019	FNIEMAIMPLFPSSEF2U128 iemAImpl_subpd_u128;
5020	FNIEMAIMPLFPSSEF2U128 iemAImpl_minps_u128;
5021	FNIEMAIMPLFPSSEF2U128 iemAImpl_minpd_u128;
5022	FNIEMAIMPLFPSSEF2U128 iemAImpl_divps_u128;
5023	FNIEMAIMPLFPSSEF2U128 iemAImpl_divpd_u128;
5024	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxps_u128;
5025	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxpd_u128;
5026	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddps_u128;
5027	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddpd_u128;
5028	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubps_u128;
5029	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubpd_u128;
5030	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtps_u128;
5031	FNIEMAIMPLFPSSEF2U128 iemAImpl_rsqrtps_u128;
5032	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtpd_u128;
5033	FNIEMAIMPLFPSSEF2U128 iemAImpl_rcpps_u128;
5034	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubps_u128;
5035	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubpd_u128;
5036
5037	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2ps_u128;
5038	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_cvtps2pd_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, uint64_t const *pu64Src));
5039
5040	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2ps_u128;
5041	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2dq_u128;
5042	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttps2dq_u128;
5043	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttpd2dq_u128;
5044	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2pd_u128;
5045	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2dq_u128;
5046
5047	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_addss_u128_r32;
5048	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_addsd_u128_r64;
5049	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_mulss_u128_r32;
5050	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_mulsd_u128_r64;
5051	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_subss_u128_r32;
5052	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_subsd_u128_r64;
5053	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_minss_u128_r32;
5054	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_minsd_u128_r64;
5055	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_divss_u128_r32;
5056	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_divsd_u128_r64;
5057	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_maxss_u128_r32;
5058	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_maxsd_u128_r64;
5059	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_cvtss2sd_u128_r32;
5060	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_cvtsd2ss_u128_r64;
5061	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_sqrtss_u128_r32;
5062	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_sqrtsd_u128_r64;
5063	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_rsqrtss_u128_r32;
5064	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_rcpss_u128_r32;
5065
5066	FNIEMAIMPLMEDIAF3U128 iemAImpl_vaddps_u128, iemAImpl_vaddps_u128_fallback;
5067	FNIEMAIMPLMEDIAF3U128 iemAImpl_vaddpd_u128, iemAImpl_vaddpd_u128_fallback;
5068	FNIEMAIMPLMEDIAF3U128 iemAImpl_vmulps_u128, iemAImpl_vmulps_u128_fallback;
5069	FNIEMAIMPLMEDIAF3U128 iemAImpl_vmulpd_u128, iemAImpl_vmulpd_u128_fallback;
5070	FNIEMAIMPLMEDIAF3U128 iemAImpl_vsubps_u128, iemAImpl_vsubps_u128_fallback;
5071	FNIEMAIMPLMEDIAF3U128 iemAImpl_vsubpd_u128, iemAImpl_vsubpd_u128_fallback;
5072	FNIEMAIMPLMEDIAF3U128 iemAImpl_vminps_u128, iemAImpl_vminps_u128_fallback;
5073	FNIEMAIMPLMEDIAF3U128 iemAImpl_vminpd_u128, iemAImpl_vminpd_u128_fallback;
5074	FNIEMAIMPLMEDIAF3U128 iemAImpl_vdivps_u128, iemAImpl_vdivps_u128_fallback;
5075	FNIEMAIMPLMEDIAF3U128 iemAImpl_vdivpd_u128, iemAImpl_vdivpd_u128_fallback;
5076	FNIEMAIMPLMEDIAF3U128 iemAImpl_vmaxps_u128, iemAImpl_vmaxps_u128_fallback;
5077	FNIEMAIMPLMEDIAF3U128 iemAImpl_vmaxpd_u128, iemAImpl_vmaxpd_u128_fallback;
5078	FNIEMAIMPLMEDIAF3U128 iemAImpl_vhaddps_u128, iemAImpl_vhaddps_u128_fallback;
5079	FNIEMAIMPLMEDIAF3U128 iemAImpl_vhaddpd_u128, iemAImpl_vhaddpd_u128_fallback;
5080	FNIEMAIMPLMEDIAF3U128 iemAImpl_vhsubps_u128, iemAImpl_vhsubps_u128_fallback;
5081	FNIEMAIMPLMEDIAF3U128 iemAImpl_vhsubpd_u128, iemAImpl_vhsubpd_u128_fallback;
5082	FNIEMAIMPLMEDIAF2U128 iemAImpl_vsqrtps_u128, iemAImpl_vsqrtps_u128_fallback;
5083	FNIEMAIMPLMEDIAF2U128 iemAImpl_vsqrtpd_u128, iemAImpl_vsqrtpd_u128_fallback;
5084	FNIEMAIMPLMEDIAF2U128 iemAImpl_vrsqrtps_u128, iemAImpl_vrsqrtps_u128_fallback;
5085	FNIEMAIMPLMEDIAF2U128 iemAImpl_vrcpps_u128, iemAImpl_vrcpps_u128_fallback;
5086	FNIEMAIMPLMEDIAF3U128 iemAImpl_vaddsubps_u128, iemAImpl_vaddsubps_u128_fallback;
5087	FNIEMAIMPLMEDIAF3U128 iemAImpl_vaddsubpd_u128, iemAImpl_vaddsubpd_u128_fallback;
5088	FNIEMAIMPLMEDIAF2U128 iemAImpl_vcvtdq2ps_u128, iemAImpl_vcvtdq2ps_u128_fallback;
5089	FNIEMAIMPLMEDIAF2U128 iemAImpl_vcvtps2dq_u128, iemAImpl_vcvtps2dq_u128_fallback;
5090	FNIEMAIMPLMEDIAF2U128 iemAImpl_vcvttps2dq_u128, iemAImpl_vcvttps2dq_u128_fallback;
5091	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2ps_u128_u128,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
5092	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2ps_u128_u128_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
5093	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvttpd2dq_u128_u128,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
5094	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvttpd2dq_u128_u128_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
5095	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2dq_u128_u128,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
5096	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2dq_u128_u128_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86XMMREG puSrc));
5097
5098
5099	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vaddss_u128_r32, iemAImpl_vaddss_u128_r32_fallback;
5100	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vaddsd_u128_r64, iemAImpl_vaddsd_u128_r64_fallback;
5101	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmulss_u128_r32, iemAImpl_vmulss_u128_r32_fallback;
5102	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmulsd_u128_r64, iemAImpl_vmulsd_u128_r64_fallback;
5103	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsubss_u128_r32, iemAImpl_vsubss_u128_r32_fallback;
5104	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsubsd_u128_r64, iemAImpl_vsubsd_u128_r64_fallback;
5105	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vminss_u128_r32, iemAImpl_vminss_u128_r32_fallback;
5106	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vminsd_u128_r64, iemAImpl_vminsd_u128_r64_fallback;
5107	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vdivss_u128_r32, iemAImpl_vdivss_u128_r32_fallback;
5108	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vdivsd_u128_r64, iemAImpl_vdivsd_u128_r64_fallback;
5109	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmaxss_u128_r32, iemAImpl_vmaxss_u128_r32_fallback;
5110	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmaxsd_u128_r64, iemAImpl_vmaxsd_u128_r64_fallback;
5111	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsqrtss_u128_r32, iemAImpl_vsqrtss_u128_r32_fallback;
5112	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsqrtsd_u128_r64, iemAImpl_vsqrtsd_u128_r64_fallback;
5113	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vrsqrtss_u128_r32, iemAImpl_vrsqrtss_u128_r32_fallback;
5114	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vrcpss_u128_r32, iemAImpl_vrcpss_u128_r32_fallback;
5115	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vcvtss2sd_u128_r32, iemAImpl_vcvtss2sd_u128_r32_fallback;
5116	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vcvtsd2ss_u128_r64, iemAImpl_vcvtsd2ss_u128_r64_fallback;
5117
5118
5119	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddps_u256, iemAImpl_vaddps_u256_fallback;
5120	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddpd_u256, iemAImpl_vaddpd_u256_fallback;
5121	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulps_u256, iemAImpl_vmulps_u256_fallback;
5122	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulpd_u256, iemAImpl_vmulpd_u256_fallback;
5123	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubps_u256, iemAImpl_vsubps_u256_fallback;
5124	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubpd_u256, iemAImpl_vsubpd_u256_fallback;
5125	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminps_u256, iemAImpl_vminps_u256_fallback;
5126	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminpd_u256, iemAImpl_vminpd_u256_fallback;
5127	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivps_u256, iemAImpl_vdivps_u256_fallback;
5128	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivpd_u256, iemAImpl_vdivpd_u256_fallback;
5129	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxps_u256, iemAImpl_vmaxps_u256_fallback;
5130	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxpd_u256, iemAImpl_vmaxpd_u256_fallback;
5131	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddps_u256, iemAImpl_vhaddps_u256_fallback;
5132	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddpd_u256, iemAImpl_vhaddpd_u256_fallback;
5133	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubps_u256, iemAImpl_vhsubps_u256_fallback;
5134	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubpd_u256, iemAImpl_vhsubpd_u256_fallback;
5135	FNIEMAIMPLMEDIAF3U256 iemAImpl_vaddsubps_u256, iemAImpl_vaddsubps_u256_fallback;
5136	FNIEMAIMPLMEDIAF3U256 iemAImpl_vaddsubpd_u256, iemAImpl_vaddsubpd_u256_fallback;
5137	FNIEMAIMPLMEDIAF2U256 iemAImpl_vsqrtps_u256, iemAImpl_vsqrtps_u256_fallback;
5138	FNIEMAIMPLMEDIAF2U256 iemAImpl_vsqrtpd_u256, iemAImpl_vsqrtpd_u256_fallback;
5139	FNIEMAIMPLMEDIAF2U256 iemAImpl_vrsqrtps_u256, iemAImpl_vrsqrtps_u256_fallback;
5140	FNIEMAIMPLMEDIAF2U256 iemAImpl_vrcpps_u256, iemAImpl_vrcpps_u256_fallback;
5141	FNIEMAIMPLMEDIAF2U256 iemAImpl_vcvtdq2ps_u256, iemAImpl_vcvtdq2ps_u256_fallback;
5142	FNIEMAIMPLMEDIAF2U256 iemAImpl_vcvtps2dq_u256, iemAImpl_vcvtps2dq_u256_fallback;
5143	FNIEMAIMPLMEDIAF2U256 iemAImpl_vcvttps2dq_u256, iemAImpl_vcvttps2dq_u256_fallback;
5144	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2ps_u128_u256,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86YMMREG puSrc));
5145	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2ps_u128_u256_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86YMMREG puSrc));
5146	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvttpd2dq_u128_u256,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86YMMREG puSrc));
5147	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvttpd2dq_u128_u256_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86YMMREG puSrc));
5148	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2dq_u128_u256,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86YMMREG puSrc));
5149	IEM_DECL_IMPL_PROTO(uint32_t, iemAImpl_vcvtpd2dq_u128_u256_fallback,(uint32_t uMxCsrIn, PX86XMMREG puDst, PCX86YMMREG puSrc));
5150	/** @} */
5151
5152	/** @name C instruction implementations for anything slightly complicated.
5153	* @{ */
5154
5155	/**
5156	* For typedef'ing or declaring a C instruction implementation function taking
5157	* no extra arguments.
5158	*
5159	* @param a_Name The name of the type.
5160	*/
5161	# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
5162	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
5163	/**
5164	* For defining a C instruction implementation function taking no extra
5165	* arguments.
5166	*
5167	* @param a_Name The name of the function
5168	*/
5169	# define IEM_CIMPL_DEF_0(a_Name) \
5170	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
5171	/**
5172	* Prototype version of IEM_CIMPL_DEF_0.
5173	*/
5174	# define IEM_CIMPL_PROTO_0(a_Name) \
5175	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
5176	/**
5177	* For calling a C instruction implementation function taking no extra
5178	* arguments.
5179	*
5180	* This special call macro adds default arguments to the call and allow us to
5181	* change these later.
5182	*
5183	* @param a_fn The name of the function.
5184	*/
5185	# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
5186
5187	/** Type for a C instruction implementation function taking no extra
5188	* arguments. */
5189	typedef IEM_CIMPL_DECL_TYPE_0(FNIEMCIMPL0);
5190	/** Function pointer type for a C instruction implementation function taking
5191	* no extra arguments. */
5192	typedef FNIEMCIMPL0 *PFNIEMCIMPL0;
5193
5194	/**
5195	* For typedef'ing or declaring a C instruction implementation function taking
5196	* one extra argument.
5197	*
5198	* @param a_Name The name of the type.
5199	* @param a_Type0 The argument type.
5200	* @param a_Arg0 The argument name.
5201	*/
5202	# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
5203	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
5204	/**
5205	* For defining a C instruction implementation function taking one extra
5206	* argument.
5207	*
5208	* @param a_Name The name of the function
5209	* @param a_Type0 The argument type.
5210	* @param a_Arg0 The argument name.
5211	*/
5212	# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
5213	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
5214	/**
5215	* Prototype version of IEM_CIMPL_DEF_1.
5216	*/
5217	# define IEM_CIMPL_PROTO_1(a_Name, a_Type0, a_Arg0) \
5218	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
5219	/**
5220	* For calling a C instruction implementation function taking one extra
5221	* argument.
5222	*
5223	* This special call macro adds default arguments to the call and allow us to
5224	* change these later.
5225	*
5226	* @param a_fn The name of the function.
5227	* @param a0 The name of the 1st argument.
5228	*/
5229	# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
5230
5231	/**
5232	* For typedef'ing or declaring a C instruction implementation function taking
5233	* two extra arguments.
5234	*
5235	* @param a_Name The name of the type.
5236	* @param a_Type0 The type of the 1st argument
5237	* @param a_Arg0 The name of the 1st argument.
5238	* @param a_Type1 The type of the 2nd argument.
5239	* @param a_Arg1 The name of the 2nd argument.
5240	*/
5241	# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
5242	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
5243	/**
5244	* For defining a C instruction implementation function taking two extra
5245	* arguments.
5246	*
5247	* @param a_Name The name of the function.
5248	* @param a_Type0 The type of the 1st argument
5249	* @param a_Arg0 The name of the 1st argument.
5250	* @param a_Type1 The type of the 2nd argument.
5251	* @param a_Arg1 The name of the 2nd argument.
5252	*/
5253	# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
5254	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
5255	/**
5256	* Prototype version of IEM_CIMPL_DEF_2.
5257	*/
5258	# define IEM_CIMPL_PROTO_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
5259	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
5260	/**
5261	* For calling a C instruction implementation function taking two extra
5262	* arguments.
5263	*
5264	* This special call macro adds default arguments to the call and allow us to
5265	* change these later.
5266	*
5267	* @param a_fn The name of the function.
5268	* @param a0 The name of the 1st argument.
5269	* @param a1 The name of the 2nd argument.
5270	*/
5271	# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
5272
5273	/**
5274	* For typedef'ing or declaring a C instruction implementation function taking
5275	* three extra arguments.
5276	*
5277	* @param a_Name The name of the type.
5278	* @param a_Type0 The type of the 1st argument
5279	* @param a_Arg0 The name of the 1st argument.
5280	* @param a_Type1 The type of the 2nd argument.
5281	* @param a_Arg1 The name of the 2nd argument.
5282	* @param a_Type2 The type of the 3rd argument.
5283	* @param a_Arg2 The name of the 3rd argument.
5284	*/
5285	# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
5286	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
5287	/**
5288	* For defining a C instruction implementation function taking three extra
5289	* arguments.
5290	*
5291	* @param a_Name The name of the function.
5292	* @param a_Type0 The type of the 1st argument
5293	* @param a_Arg0 The name of the 1st argument.
5294	* @param a_Type1 The type of the 2nd argument.
5295	* @param a_Arg1 The name of the 2nd argument.
5296	* @param a_Type2 The type of the 3rd argument.
5297	* @param a_Arg2 The name of the 3rd argument.
5298	*/
5299	# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
5300	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
5301	/**
5302	* Prototype version of IEM_CIMPL_DEF_3.
5303	*/
5304	# define IEM_CIMPL_PROTO_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
5305	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
5306	/**
5307	* For calling a C instruction implementation function taking three extra
5308	* arguments.
5309	*
5310	* This special call macro adds default arguments to the call and allow us to
5311	* change these later.
5312	*
5313	* @param a_fn The name of the function.
5314	* @param a0 The name of the 1st argument.
5315	* @param a1 The name of the 2nd argument.
5316	* @param a2 The name of the 3rd argument.
5317	*/
5318	# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
5319
5320
5321	/**
5322	* For typedef'ing or declaring a C instruction implementation function taking
5323	* four extra arguments.
5324	*
5325	* @param a_Name The name of the type.
5326	* @param a_Type0 The type of the 1st argument
5327	* @param a_Arg0 The name of the 1st argument.
5328	* @param a_Type1 The type of the 2nd argument.
5329	* @param a_Arg1 The name of the 2nd argument.
5330	* @param a_Type2 The type of the 3rd argument.
5331	* @param a_Arg2 The name of the 3rd argument.
5332	* @param a_Type3 The type of the 4th argument.
5333	* @param a_Arg3 The name of the 4th argument.
5334	*/
5335	# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
5336	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
5337	/**
5338	* For defining a C instruction implementation function taking four extra
5339	* arguments.
5340	*
5341	* @param a_Name The name of the function.
5342	* @param a_Type0 The type of the 1st argument
5343	* @param a_Arg0 The name of the 1st argument.
5344	* @param a_Type1 The type of the 2nd argument.
5345	* @param a_Arg1 The name of the 2nd argument.
5346	* @param a_Type2 The type of the 3rd argument.
5347	* @param a_Arg2 The name of the 3rd argument.
5348	* @param a_Type3 The type of the 4th argument.
5349	* @param a_Arg3 The name of the 4th argument.
5350	*/
5351	# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
5352	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
5353	a_Type2 a_Arg2, a_Type3 a_Arg3))
5354	/**
5355	* Prototype version of IEM_CIMPL_DEF_4.
5356	*/
5357	# define IEM_CIMPL_PROTO_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
5358	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
5359	a_Type2 a_Arg2, a_Type3 a_Arg3))
5360	/**
5361	* For calling a C instruction implementation function taking four extra
5362	* arguments.
5363	*
5364	* This special call macro adds default arguments to the call and allow us to
5365	* change these later.
5366	*
5367	* @param a_fn The name of the function.
5368	* @param a0 The name of the 1st argument.
5369	* @param a1 The name of the 2nd argument.
5370	* @param a2 The name of the 3rd argument.
5371	* @param a3 The name of the 4th argument.
5372	*/
5373	# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
5374
5375
5376	/**
5377	* For typedef'ing or declaring a C instruction implementation function taking
5378	* five extra arguments.
5379	*
5380	* @param a_Name The name of the type.
5381	* @param a_Type0 The type of the 1st argument
5382	* @param a_Arg0 The name of the 1st argument.
5383	* @param a_Type1 The type of the 2nd argument.
5384	* @param a_Arg1 The name of the 2nd argument.
5385	* @param a_Type2 The type of the 3rd argument.
5386	* @param a_Arg2 The name of the 3rd argument.
5387	* @param a_Type3 The type of the 4th argument.
5388	* @param a_Arg3 The name of the 4th argument.
5389	* @param a_Type4 The type of the 5th argument.
5390	* @param a_Arg4 The name of the 5th argument.
5391	*/
5392	# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
5393	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, \
5394	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
5395	a_Type3 a_Arg3, a_Type4 a_Arg4))
5396	/**
5397	* For defining a C instruction implementation function taking five extra
5398	* arguments.
5399	*
5400	* @param a_Name The name of the function.
5401	* @param a_Type0 The type of the 1st argument
5402	* @param a_Arg0 The name of the 1st argument.
5403	* @param a_Type1 The type of the 2nd argument.
5404	* @param a_Arg1 The name of the 2nd argument.
5405	* @param a_Type2 The type of the 3rd argument.
5406	* @param a_Arg2 The name of the 3rd argument.
5407	* @param a_Type3 The type of the 4th argument.
5408	* @param a_Arg3 The name of the 4th argument.
5409	* @param a_Type4 The type of the 5th argument.
5410	* @param a_Arg4 The name of the 5th argument.
5411	*/
5412	# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
5413	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
5414	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
5415	/**
5416	* Prototype version of IEM_CIMPL_DEF_5.
5417	*/
5418	# define IEM_CIMPL_PROTO_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
5419	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
5420	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
5421	/**
5422	* For calling a C instruction implementation function taking five extra
5423	* arguments.
5424	*
5425	* This special call macro adds default arguments to the call and allow us to
5426	* change these later.
5427	*
5428	* @param a_fn The name of the function.
5429	* @param a0 The name of the 1st argument.
5430	* @param a1 The name of the 2nd argument.
5431	* @param a2 The name of the 3rd argument.
5432	* @param a3 The name of the 4th argument.
5433	* @param a4 The name of the 5th argument.
5434	*/
5435	# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
5436
5437	/** @} */
5438
5439
5440	/** @name Opcode Decoder Function Types.
5441	* @{ */
5442
5443	/** @typedef PFNIEMOP
5444	* Pointer to an opcode decoder function.
5445	*/
5446
5447	/** @def FNIEMOP_DEF
5448	* Define an opcode decoder function.
5449	*
5450	* We're using macors for this so that adding and removing parameters as well as
5451	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL
5452	*
5453	* @param a_Name The function name.
5454	*/
5455
5456	/** @typedef PFNIEMOPRM
5457	* Pointer to an opcode decoder function with RM byte.
5458	*/
5459
5460	/** @def FNIEMOPRM_DEF
5461	* Define an opcode decoder function with RM byte.
5462	*
5463	* We're using macors for this so that adding and removing parameters as well as
5464	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL_1
5465	*
5466	* @param a_Name The function name.
5467	*/
5468
5469	#if defined(__GNUC__) && defined(RT_ARCH_X86)
5470	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOP)(PVMCPUCC pVCpu);
5471	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
5472	# define FNIEMOP_DEF(a_Name) \
5473	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu)
5474	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
5475	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
5476	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
5477	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
5478
5479	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
5480	typedef VBOXSTRICTRC (__fastcall * PFNIEMOP)(PVMCPUCC pVCpu);
5481	typedef VBOXSTRICTRC (__fastcall * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
5482	# define FNIEMOP_DEF(a_Name) \
5483	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
5484	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
5485	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
5486	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
5487	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
5488
5489	#elif defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
5490	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
5491	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
5492	# define FNIEMOP_DEF(a_Name) \
5493	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu)
5494	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
5495	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
5496	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
5497	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
5498
5499	#else
5500	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
5501	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
5502	# define FNIEMOP_DEF(a_Name) \
5503	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
5504	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
5505	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
5506	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
5507	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
5508
5509	#endif
5510	#define FNIEMOPRM_DEF(a_Name) FNIEMOP_DEF_1(a_Name, uint8_t, bRm)
5511
5512	/**
5513	* Call an opcode decoder function.
5514	*
5515	* We're using macors for this so that adding and removing parameters can be
5516	* done as we please. See FNIEMOP_DEF.
5517	*/
5518	#define FNIEMOP_CALL(a_pfn) (a_pfn)(pVCpu)
5519
5520	/**
5521	* Call a common opcode decoder function taking one extra argument.
5522	*
5523	* We're using macors for this so that adding and removing parameters can be
5524	* done as we please. See FNIEMOP_DEF_1.
5525	*/
5526	#define FNIEMOP_CALL_1(a_pfn, a0) (a_pfn)(pVCpu, a0)
5527
5528	/**
5529	* Call a common opcode decoder function taking one extra argument.
5530	*
5531	* We're using macors for this so that adding and removing parameters can be
5532	* done as we please. See FNIEMOP_DEF_1.
5533	*/
5534	#define FNIEMOP_CALL_2(a_pfn, a0, a1) (a_pfn)(pVCpu, a0, a1)
5535	/** @} */
5536
5537
5538	/** @name Misc Helpers
5539	* @{ */
5540
5541	/** Used to shut up GCC warnings about variables that 'may be used uninitialized'
5542	* due to GCC lacking knowledge about the value range of a switch. */
5543	#if RT_CPLUSPLUS_PREREQ(202000)
5544	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: [[unlikely]] AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
5545	#else
5546	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
5547	#endif
5548
5549	/** Variant of IEM_NOT_REACHED_DEFAULT_CASE_RET that returns a custom value. */
5550	#if RT_CPLUSPLUS_PREREQ(202000)
5551	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: [[unlikely]] AssertFailedReturn(a_RetValue)
5552	#else
5553	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: AssertFailedReturn(a_RetValue)
5554	#endif
5555
5556	/**
5557	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
5558	* occation.
5559	*/
5560	#ifdef LOG_ENABLED
5561	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
5562	do { \
5563	/Log/ LogAlways(("%s: returning IEM_RETURN_ASPECT_NOT_IMPLEMENTED (line %d)\n", __FUNCTION__, __LINE__)); \
5564	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
5565	} while (0)
5566	#else
5567	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
5568	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
5569	#endif
5570
5571	/**
5572	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
5573	* occation using the supplied logger statement.
5574	*
5575	* @param a_LoggerArgs What to log on failure.
5576	*/
5577	#ifdef LOG_ENABLED
5578	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
5579	do { \
5580	LogAlways((LOG_FN_FMT ": ", __PRETTY_FUNCTION__)); LogAlways(a_LoggerArgs); \
5581	/LogFunc(a_LoggerArgs);/ \
5582	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
5583	} while (0)
5584	#else
5585	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
5586	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
5587	#endif
5588
5589	/**
5590	* Gets the CPU mode (from fExec) as a IEMMODE value.
5591	*
5592	* @returns IEMMODE
5593	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5594	*/
5595	#define IEM_GET_CPU_MODE(a_pVCpu) ((a_pVCpu)->iem.s.fExec & IEM_F_MODE_CPUMODE_MASK)
5596
5597	/**
5598	* Check if we're currently executing in real or virtual 8086 mode.
5599	*
5600	* @returns @c true if it is, @c false if not.
5601	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5602	*/
5603	#define IEM_IS_REAL_OR_V86_MODE(a_pVCpu) (( ((a_pVCpu)->iem.s.fExec ^ IEM_F_MODE_X86_PROT_MASK) \
5604	& (IEM_F_MODE_X86_V86_MASK \| IEM_F_MODE_X86_PROT_MASK)) != 0)
5605
5606	/**
5607	* Check if we're currently executing in virtual 8086 mode.
5608	*
5609	* @returns @c true if it is, @c false if not.
5610	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5611	*/
5612	#define IEM_IS_V86_MODE(a_pVCpu) (((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_V86_MASK) != 0)
5613
5614	/**
5615	* Check if we're currently executing in long mode.
5616	*
5617	* @returns @c true if it is, @c false if not.
5618	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5619	*/
5620	#define IEM_IS_LONG_MODE(a_pVCpu) (CPUMIsGuestInLongModeEx(IEM_GET_CTX(a_pVCpu)))
5621
5622	/**
5623	* Check if we're currently executing in a 16-bit code segment.
5624	*
5625	* @returns @c true if it is, @c false if not.
5626	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5627	*/
5628	#define IEM_IS_16BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_16BIT)
5629
5630	/**
5631	* Check if we're currently executing in a 32-bit code segment.
5632	*
5633	* @returns @c true if it is, @c false if not.
5634	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5635	*/
5636	#define IEM_IS_32BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_32BIT)
5637
5638	/**
5639	* Check if we're currently executing in a 64-bit code segment.
5640	*
5641	* @returns @c true if it is, @c false if not.
5642	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5643	*/
5644	#define IEM_IS_64BIT_CODE(a_pVCpu) (IEM_GET_CPU_MODE(a_pVCpu) == IEMMODE_64BIT)
5645
5646	/**
5647	* Check if we're currently executing in real mode.
5648	*
5649	* @returns @c true if it is, @c false if not.
5650	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5651	*/
5652	#define IEM_IS_REAL_MODE(a_pVCpu) (!((a_pVCpu)->iem.s.fExec & IEM_F_MODE_X86_PROT_MASK))
5653
5654	/**
5655	* Gets the current protection level (CPL).
5656	*
5657	* @returns 0..3
5658	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5659	*/
5660	#define IEM_GET_CPL(a_pVCpu) (((a_pVCpu)->iem.s.fExec >> IEM_F_X86_CPL_SHIFT) & IEM_F_X86_CPL_SMASK)
5661
5662	/**
5663	* Sets the current protection level (CPL).
5664	*
5665	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5666	*/
5667	#define IEM_SET_CPL(a_pVCpu, a_uCpl) \
5668	do { (a_pVCpu)->iem.s.fExec = ((a_pVCpu)->iem.s.fExec & ~IEM_F_X86_CPL_MASK) \| ((a_uCpl) << IEM_F_X86_CPL_SHIFT); } while (0)
5669
5670	/**
5671	* Returns a (const) pointer to the CPUMFEATURES for the guest CPU.
5672	* @returns PCCPUMFEATURES
5673	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5674	*/
5675	#define IEM_GET_GUEST_CPU_FEATURES(a_pVCpu) (&((a_pVCpu)->CTX_SUFF(pVM)->cpum.ro.GuestFeatures))
5676
5677	/**
5678	* Returns a (const) pointer to the CPUMFEATURES for the host CPU.
5679	* @returns PCCPUMFEATURES
5680	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5681	*/
5682	#define IEM_GET_HOST_CPU_FEATURES(a_pVCpu) (&g_CpumHostFeatures.s)
5683
5684	/**
5685	* Evaluates to true if we're presenting an Intel CPU to the guest.
5686	*/
5687	#define IEM_IS_GUEST_CPU_INTEL(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL )
5688
5689	/**
5690	* Evaluates to true if we're presenting an AMD CPU to the guest.
5691	*/
5692	#define IEM_IS_GUEST_CPU_AMD(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_AMD \|\| (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_HYGON )
5693
5694	/**
5695	* Check if the address is canonical.
5696	*/
5697	#define IEM_IS_CANONICAL(a_u64Addr) X86_IS_CANONICAL(a_u64Addr)
5698
5699	/** Checks if the ModR/M byte is in register mode or not. */
5700	#define IEM_IS_MODRM_REG_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT) )
5701	/** Checks if the ModR/M byte is in memory mode or not. */
5702	#define IEM_IS_MODRM_MEM_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT) )
5703
5704	/**
5705	* Gets the register (reg) part of a ModR/M encoding, with REX.R added in.
5706	*
5707	* For use during decoding.
5708	*/
5709	#define IEM_GET_MODRM_REG(a_pVCpu, a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| (a_pVCpu)->iem.s.uRexReg )
5710	/**
5711	* Gets the r/m part of a ModR/M encoding as a register index, with REX.B added in.
5712	*
5713	* For use during decoding.
5714	*/
5715	#define IEM_GET_MODRM_RM(a_pVCpu, a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) \| (a_pVCpu)->iem.s.uRexB )
5716
5717	/**
5718	* Gets the register (reg) part of a ModR/M encoding, without REX.R.
5719	*
5720	* For use during decoding.
5721	*/
5722	#define IEM_GET_MODRM_REG_8(a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) )
5723	/**
5724	* Gets the r/m part of a ModR/M encoding as a register index, without REX.B.
5725	*
5726	* For use during decoding.
5727	*/
5728	#define IEM_GET_MODRM_RM_8(a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) )
5729
5730	/**
5731	* Gets the register (reg) part of a ModR/M encoding as an extended 8-bit
5732	* register index, with REX.R added in.
5733	*
5734	* For use during decoding.
5735	*
5736	* @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
5737	*/
5738	#define IEM_GET_MODRM_REG_EX8(a_pVCpu, a_bRm) \
5739	( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
5740	\|\| !((a_bRm) & (4 << X86_MODRM_REG_SHIFT)) /* IEM_GET_MODRM_REG(pVCpu, a_bRm) < 4 */ \
5741	? IEM_GET_MODRM_REG(pVCpu, a_bRm) : (((a_bRm) >> X86_MODRM_REG_SHIFT) & 3) \| 16)
5742	/**
5743	* Gets the r/m part of a ModR/M encoding as an extended 8-bit register index,
5744	* with REX.B added in.
5745	*
5746	* For use during decoding.
5747	*
5748	* @see iemGRegRefU8Ex, iemGRegFetchU8Ex, iemGRegStoreU8Ex
5749	*/
5750	#define IEM_GET_MODRM_RM_EX8(a_pVCpu, a_bRm) \
5751	( (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_REX) \
5752	\|\| !((a_bRm) & 4) /* IEM_GET_MODRM_RM(pVCpu, a_bRm) < 4 */ \
5753	? IEM_GET_MODRM_RM(pVCpu, a_bRm) : ((a_bRm) & 3) \| 16)
5754
5755	/**
5756	* Combines the prefix REX and ModR/M byte for passing to
5757	* iemOpHlpCalcRmEffAddrThreadedAddr64().
5758	*
5759	* @returns The ModRM byte but with bit 3 set to REX.B and bit 4 to REX.X.
5760	* The two bits are part of the REG sub-field, which isn't needed in
5761	* iemOpHlpCalcRmEffAddrThreadedAddr64().
5762	*
5763	* For use during decoding/recompiling.
5764	*/
5765	#define IEM_GET_MODRM_EX(a_pVCpu, a_bRm) \
5766	( ((a_bRm) & ~X86_MODRM_REG_MASK) \
5767	\| (uint8_t)( (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X)) >> (25 - 3) ) )
5768	AssertCompile(IEM_OP_PRF_REX_B == RT_BIT_32(25));
5769	AssertCompile(IEM_OP_PRF_REX_X == RT_BIT_32(26));
5770
5771	/**
5772	* Gets the effective VEX.VVVV value.
5773	*
5774	* The 4th bit is ignored if not 64-bit code.
5775	* @returns effective V-register value.
5776	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
5777	*/
5778	#define IEM_GET_EFFECTIVE_VVVV(a_pVCpu) \
5779	(IEM_IS_64BIT_CODE(a_pVCpu) ? (a_pVCpu)->iem.s.uVex3rdReg : (a_pVCpu)->iem.s.uVex3rdReg & 7)
5780
5781
5782	/**
5783	* Gets the register (reg) part of a the special 4th register byte used by
5784	* vblendvps and vblendvpd.
5785	*
5786	* For use during decoding.
5787	*/
5788	#define IEM_GET_IMM8_REG(a_pVCpu, a_bRegImm8) \
5789	(IEM_IS_64BIT_CODE(a_pVCpu) ? (a_bRegImm8) >> 4 : ((a_bRegImm8) >> 4) & 7)
5790
5791
5792	/**
5793	* Checks if we're executing inside an AMD-V or VT-x guest.
5794	*/
5795	#if defined(VBOX_WITH_NESTED_HWVIRT_VMX) \|\| defined(VBOX_WITH_NESTED_HWVIRT_SVM)
5796	# define IEM_IS_IN_GUEST(a_pVCpu) RT_BOOL((a_pVCpu)->iem.s.fExec & IEM_F_X86_CTX_IN_GUEST)
5797	#else
5798	# define IEM_IS_IN_GUEST(a_pVCpu) false
5799	#endif
5800
5801
5802	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5803
5804	/**
5805	* Check if the guest has entered VMX root operation.
5806	*/
5807	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxRootMode(IEM_GET_CTX(a_pVCpu)))
5808
5809	/**
5810	* Check if the guest has entered VMX non-root operation.
5811	*/
5812	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) ( ((a_pVCpu)->iem.s.fExec & (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST)) \
5813	== (IEM_F_X86_CTX_VMX \| IEM_F_X86_CTX_IN_GUEST) )
5814
5815	/**
5816	* Check if the nested-guest has the given Pin-based VM-execution control set.
5817	*/
5818	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_PinCtl) (CPUMIsGuestVmxPinCtlsSet(IEM_GET_CTX(a_pVCpu), (a_PinCtl)))
5819
5820	/**
5821	* Check if the nested-guest has the given Processor-based VM-execution control set.
5822	*/
5823	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_ProcCtl) (CPUMIsGuestVmxProcCtlsSet(IEM_GET_CTX(a_pVCpu), (a_ProcCtl)))
5824
5825	/**
5826	* Check if the nested-guest has the given Secondary Processor-based VM-execution
5827	* control set.
5828	*/
5829	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_ProcCtl2) (CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(a_pVCpu), (a_ProcCtl2)))
5830
5831	/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
5832	# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
5833
5834	/** Whether a shadow VMCS is present for the given VCPU. */
5835	# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
5836
5837	/** Gets the VMXON region pointer. */
5838	# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
5839
5840	/** Gets the guest-physical address of the current VMCS for the given VCPU. */
5841	# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
5842
5843	/** Whether a current VMCS is present for the given VCPU. */
5844	# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
5845
5846	/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
5847	# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
5848	do \
5849	{ \
5850	Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
5851	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
5852	} while (0)
5853
5854	/** Clears any current VMCS for the given VCPU. */
5855	# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
5856	do \
5857	{ \
5858	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
5859	} while (0)
5860
5861	/**
5862	* Invokes the VMX VM-exit handler for an instruction intercept.
5863	*/
5864	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) \
5865	do { return iemVmxVmexitInstr((a_pVCpu), (a_uExitReason), (a_cbInstr)); } while (0)
5866
5867	/**
5868	* Invokes the VMX VM-exit handler for an instruction intercept where the
5869	* instruction provides additional VM-exit information.
5870	*/
5871	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) \
5872	do { return iemVmxVmexitInstrNeedsInfo((a_pVCpu), (a_uExitReason), (a_uInstrId), (a_cbInstr)); } while (0)
5873
5874	/**
5875	* Invokes the VMX VM-exit handler for a task switch.
5876	*/
5877	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) \
5878	do { return iemVmxVmexitTaskSwitch((a_pVCpu), (a_enmTaskSwitch), (a_SelNewTss), (a_cbInstr)); } while (0)
5879
5880	/**
5881	* Invokes the VMX VM-exit handler for MWAIT.
5882	*/
5883	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) \
5884	do { return iemVmxVmexitInstrMwait((a_pVCpu), (a_fMonitorArmed), (a_cbInstr)); } while (0)
5885
5886	/**
5887	* Invokes the VMX VM-exit handler for EPT faults.
5888	*/
5889	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) \
5890	do { return iemVmxVmexitEpt(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr); } while (0)
5891
5892	/**
5893	* Invokes the VMX VM-exit handler.
5894	*/
5895	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) \
5896	do { return iemVmxVmexit((a_pVCpu), (a_uExitReason), (a_uExitQual)); } while (0)
5897
5898	#else
5899	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (false)
5900	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (false)
5901	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_cbInstr) (false)
5902	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_cbInstr) (false)
5903	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_cbInstr) (false)
5904	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5905	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5906	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5907	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5908	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
5909	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) do { return VERR_VMX_IPE_1; } while (0)
5910
5911	#endif
5912
5913	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5914	/**
5915	* Checks if we're executing a guest using AMD-V.
5916	*/
5917	# define IEM_SVM_IS_IN_GUEST(a_pVCpu) ( (a_pVCpu->iem.s.fExec & (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST)) \
5918	== (IEM_F_X86_CTX_SVM \| IEM_F_X86_CTX_IN_GUEST))
5919	/**
5920	* Check if an SVM control/instruction intercept is set.
5921	*/
5922	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) \
5923	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmCtrlInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_Intercept)))
5924
5925	/**
5926	* Check if an SVM read CRx intercept is set.
5927	*/
5928	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
5929	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
5930
5931	/**
5932	* Check if an SVM write CRx intercept is set.
5933	*/
5934	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
5935	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
5936
5937	/**
5938	* Check if an SVM read DRx intercept is set.
5939	*/
5940	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
5941	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmReadDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
5942
5943	/**
5944	* Check if an SVM write DRx intercept is set.
5945	*/
5946	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
5947	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmWriteDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
5948
5949	/**
5950	* Check if an SVM exception intercept is set.
5951	*/
5952	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) \
5953	(IEM_SVM_IS_IN_GUEST(a_pVCpu) && CPUMIsGuestSvmXcptInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uVector)))
5954
5955	/**
5956	* Invokes the SVM \#VMEXIT handler for the nested-guest.
5957	*/
5958	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
5959	do { return iemSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2)); } while (0)
5960
5961	/**
5962	* Invokes the 'MOV CRx' SVM \#VMEXIT handler after constructing the
5963	* corresponding decode assist information.
5964	*/
5965	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) \
5966	do \
5967	{ \
5968	uint64_t uExitInfo1; \
5969	if ( IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmDecodeAssists \
5970	&& (a_enmAccessCrX) == IEMACCESSCRX_MOV_CRX) \
5971	uExitInfo1 = SVM_EXIT1_MOV_CRX_MASK \| ((a_iGReg) & 7); \
5972	else \
5973	uExitInfo1 = 0; \
5974	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, uExitInfo1, 0); \
5975	} while (0)
5976
5977	/** Check and handles SVM nested-guest instruction intercept and updates
5978	* NRIP if needed.
5979	*/
5980	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
5981	do \
5982	{ \
5983	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept)) \
5984	{ \
5985	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
5986	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2); \
5987	} \
5988	} while (0)
5989
5990	/** Checks and handles SVM nested-guest CR0 read intercept. */
5991	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) \
5992	do \
5993	{ \
5994	if (!IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, 0)) \
5995	{ /* probably likely */ } \
5996	else \
5997	{ \
5998	IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr); \
5999	IEM_SVM_VMEXIT_RET(a_pVCpu, SVM_EXIT_READ_CR0, a_uExitInfo1, a_uExitInfo2); \
6000	} \
6001	} while (0)
6002
6003	/**
6004	* Updates the NextRIP (NRI) field in the nested-guest VMCB.
6005	*/
6006	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) \
6007	do { \
6008	if (IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmNextRipSave) \
6009	CPUMGuestSvmUpdateNRip(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_cbInstr)); \
6010	} while (0)
6011
6012	#else
6013	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) (false)
6014	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
6015	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
6016	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
6017	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
6018	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) (false)
6019	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { return VERR_SVM_IPE_1; } while (0)
6020	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) do { return VERR_SVM_IPE_1; } while (0)
6021	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, \
6022	a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
6023	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2, a_cbInstr) do { } while (0)
6024	# define IEM_SVM_UPDATE_NRIP(a_pVCpu, a_cbInstr) do { } while (0)
6025
6026	#endif
6027
6028	/** @} */
6029
6030	uint32_t iemCalcExecDbgFlagsSlow(PVMCPUCC pVCpu);
6031	VBOXSTRICTRC iemExecInjectPendingTrap(PVMCPUCC pVCpu);
6032
6033
6034	/**
6035	* Selector descriptor table entry as fetched by iemMemFetchSelDesc.
6036	*/
6037	typedef union IEMSELDESC
6038	{
6039	/** The legacy view. */
6040	X86DESC Legacy;
6041	/** The long mode view. */
6042	X86DESC64 Long;
6043	} IEMSELDESC;
6044	/** Pointer to a selector descriptor table entry. */
6045	typedef IEMSELDESC *PIEMSELDESC;
6046
6047	/** @name Raising Exceptions.
6048	* @{ */
6049	VBOXSTRICTRC iemTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, uint32_t uNextEip, uint32_t fFlags,
6050	uint16_t uErr, uint64_t uCr2, RTSEL SelTSS, PIEMSELDESC pNewDescTSS) RT_NOEXCEPT;
6051
6052	VBOXSTRICTRC iemRaiseXcptOrInt(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags,
6053	uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
6054	#ifdef IEM_WITH_SETJMP
6055	DECL_NO_RETURN(void) iemRaiseXcptOrIntJmp(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector,
6056	uint32_t fFlags, uint16_t uErr, uint64_t uCr2) IEM_NOEXCEPT_MAY_LONGJMP;
6057	#endif
6058	VBOXSTRICTRC iemRaiseDivideError(PVMCPUCC pVCpu) RT_NOEXCEPT;
6059	#ifdef IEM_WITH_SETJMP
6060	DECL_NO_RETURN(void) iemRaiseDivideErrorJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6061	#endif
6062	VBOXSTRICTRC iemRaiseDebugException(PVMCPUCC pVCpu) RT_NOEXCEPT;
6063	VBOXSTRICTRC iemRaiseBoundRangeExceeded(PVMCPUCC pVCpu) RT_NOEXCEPT;
6064	VBOXSTRICTRC iemRaiseUndefinedOpcode(PVMCPUCC pVCpu) RT_NOEXCEPT;
6065	#ifdef IEM_WITH_SETJMP
6066	DECL_NO_RETURN(void) iemRaiseUndefinedOpcodeJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6067	#endif
6068	VBOXSTRICTRC iemRaiseDeviceNotAvailable(PVMCPUCC pVCpu) RT_NOEXCEPT;
6069	#ifdef IEM_WITH_SETJMP
6070	DECL_NO_RETURN(void) iemRaiseDeviceNotAvailableJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6071	#endif
6072	VBOXSTRICTRC iemRaiseTaskSwitchFaultWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
6073	VBOXSTRICTRC iemRaiseTaskSwitchFaultCurrentTSS(PVMCPUCC pVCpu) RT_NOEXCEPT;
6074	VBOXSTRICTRC iemRaiseTaskSwitchFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
6075	VBOXSTRICTRC iemRaiseTaskSwitchFaultBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
6076	/VBOXSTRICTRC iemRaiseSelectorNotPresent(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;/
6077	VBOXSTRICTRC iemRaiseSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
6078	VBOXSTRICTRC iemRaiseSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
6079	VBOXSTRICTRC iemRaiseStackSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
6080	VBOXSTRICTRC iemRaiseStackSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
6081	VBOXSTRICTRC iemRaiseGeneralProtectionFault(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
6082	VBOXSTRICTRC iemRaiseGeneralProtectionFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
6083	#ifdef IEM_WITH_SETJMP
6084	DECL_NO_RETURN(void) iemRaiseGeneralProtectionFault0Jmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6085	#endif
6086	VBOXSTRICTRC iemRaiseGeneralProtectionFaultBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
6087	VBOXSTRICTRC iemRaiseNotCanonical(PVMCPUCC pVCpu) RT_NOEXCEPT;
6088	VBOXSTRICTRC iemRaiseSelectorBounds(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
6089	#ifdef IEM_WITH_SETJMP
6090	DECL_NO_RETURN(void) iemRaiseSelectorBoundsJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
6091	#endif
6092	VBOXSTRICTRC iemRaiseSelectorBoundsBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
6093	#ifdef IEM_WITH_SETJMP
6094	DECL_NO_RETURN(void) iemRaiseSelectorBoundsBySelectorJmp(PVMCPUCC pVCpu, RTSEL Sel) IEM_NOEXCEPT_MAY_LONGJMP;
6095	#endif
6096	VBOXSTRICTRC iemRaiseSelectorInvalidAccess(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
6097	#ifdef IEM_WITH_SETJMP
6098	DECL_NO_RETURN(void) iemRaiseSelectorInvalidAccessJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
6099	#endif
6100	VBOXSTRICTRC iemRaisePageFault(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) RT_NOEXCEPT;
6101	#ifdef IEM_WITH_SETJMP
6102	DECL_NO_RETURN(void) iemRaisePageFaultJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) IEM_NOEXCEPT_MAY_LONGJMP;
6103	#endif
6104	VBOXSTRICTRC iemRaiseMathFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
6105	#ifdef IEM_WITH_SETJMP
6106	DECL_NO_RETURN(void) iemRaiseMathFaultJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6107	#endif
6108	VBOXSTRICTRC iemRaiseAlignmentCheckException(PVMCPUCC pVCpu) RT_NOEXCEPT;
6109	#ifdef IEM_WITH_SETJMP
6110	DECL_NO_RETURN(void) iemRaiseAlignmentCheckExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6111	#endif
6112	VBOXSTRICTRC iemRaiseSimdFpException(PVMCPUCC pVCpu) RT_NOEXCEPT;
6113	#ifdef IEM_WITH_SETJMP
6114	DECL_NO_RETURN(void) iemRaiseSimdFpExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6115	#endif
6116
6117	void iemLogSyscallRealModeInt(PVMCPUCC pVCpu, uint8_t u8Vector, uint8_t cbInstr);
6118	void iemLogSyscallProtModeInt(PVMCPUCC pVCpu, uint8_t u8Vector, uint8_t cbInstr);
6119
6120	IEM_CIMPL_DEF_0(iemCImplRaiseDivideError);
6121	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidLockPrefix);
6122	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidOpcode);
6123
6124	/**
6125	* Macro for calling iemCImplRaiseDivideError().
6126	*
6127	* This is for things that will _always_ decode to an \#DE, taking the
6128	* recompiler into consideration and everything.
6129	*
6130	* @return Strict VBox status code.
6131	*/
6132	#define IEMOP_RAISE_DIVIDE_ERROR_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseDivideError)
6133
6134	/**
6135	* Macro for calling iemCImplRaiseInvalidLockPrefix().
6136	*
6137	* This is for things that will _always_ decode to an \#UD, taking the
6138	* recompiler into consideration and everything.
6139	*
6140	* @return Strict VBox status code.
6141	*/
6142	#define IEMOP_RAISE_INVALID_LOCK_PREFIX_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidLockPrefix)
6143
6144	/**
6145	* Macro for calling iemCImplRaiseInvalidOpcode() for decode/static \#UDs.
6146	*
6147	* This is for things that will _always_ decode to an \#UD, taking the
6148	* recompiler into consideration and everything.
6149	*
6150	* @return Strict VBox status code.
6151	*/
6152	#define IEMOP_RAISE_INVALID_OPCODE_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidOpcode)
6153
6154	/**
6155	* Macro for calling iemCImplRaiseInvalidOpcode() for runtime-style \#UDs.
6156	*
6157	* Using this macro means you've got _buggy_ _code_ and are doing things that
6158	* belongs exclusively in IEMAllCImpl.cpp during decoding.
6159	*
6160	* @return Strict VBox status code.
6161	* @see IEMOP_RAISE_INVALID_OPCODE_RET
6162	*/
6163	#define IEMOP_RAISE_INVALID_OPCODE_RUNTIME_RET() IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_XCPT, 0, iemCImplRaiseInvalidOpcode)
6164
6165	/** @} */
6166
6167	/** @name Register Access.
6168	* @{ */
6169	VBOXSTRICTRC iemRegRipRelativeJumpS8AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int8_t offNextInstr,
6170	IEMMODE enmEffOpSize) RT_NOEXCEPT;
6171	VBOXSTRICTRC iemRegRipRelativeJumpS16AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int16_t offNextInstr) RT_NOEXCEPT;
6172	VBOXSTRICTRC iemRegRipRelativeJumpS32AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int32_t offNextInstr,
6173	IEMMODE enmEffOpSize) RT_NOEXCEPT;
6174	/** @} */
6175
6176	/** @name FPU access and helpers.
6177	* @{ */
6178	void iemFpuPushResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
6179	void iemFpuPushResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
6180	void iemFpuPushResultTwo(PVMCPUCC pVCpu, PIEMFPURESULTTWO pResult, uint16_t uFpuOpcode) RT_NOEXCEPT;
6181	void iemFpuStoreResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
6182	void iemFpuStoreResultThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
6183	void iemFpuStoreResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
6184	uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
6185	void iemFpuStoreResultWithMemOpThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
6186	uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
6187	void iemFpuUpdateOpcodeAndIp(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
6188	void iemFpuUpdateFSW(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
6189	void iemFpuUpdateFSWThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
6190	void iemFpuUpdateFSWWithMemOp(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
6191	void iemFpuUpdateFSWThenPopPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint16_t uFpuOpcode) RT_NOEXCEPT;
6192	void iemFpuUpdateFSWWithMemOpThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
6193	void iemFpuStackUnderflow(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
6194	void iemFpuStackUnderflowWithMemOp(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
6195	void iemFpuStackUnderflowThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint16_t uFpuOpcode) RT_NOEXCEPT;
6196	void iemFpuStackUnderflowWithMemOpThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
6197	void iemFpuStackUnderflowThenPopPop(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
6198	void iemFpuStackPushUnderflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
6199	void iemFpuStackPushUnderflowTwo(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
6200	void iemFpuStackPushOverflow(PVMCPUCC pVCpu, uint16_t uFpuOpcode) RT_NOEXCEPT;
6201	void iemFpuStackPushOverflowWithMemOp(PVMCPUCC pVCpu, uint8_t iEffSeg, RTGCPTR GCPtrEff, uint16_t uFpuOpcode) RT_NOEXCEPT;
6202	/** @} */
6203
6204	/** @name SSE+AVX SIMD access and helpers.
6205	* @{ */
6206	void iemSseUpdateMxcsr(PVMCPUCC pVCpu, uint32_t fMxcsr) RT_NOEXCEPT;
6207	/** @} */
6208
6209	/** @name Memory access.
6210	* @{ */
6211
6212	/** Report a \#GP instead of \#AC and do not restrict to ring-3 */
6213	#define IEM_MEMMAP_F_ALIGN_GP RT_BIT_32(16)
6214	/** SSE access that should report a \#GP instead of \#AC, unless MXCSR.MM=1
6215	* when it works like normal \#AC. Always used with IEM_MEMMAP_F_ALIGN_GP. */
6216	#define IEM_MEMMAP_F_ALIGN_SSE RT_BIT_32(17)
6217	/** If \#AC is applicable, raise it. Always used with IEM_MEMMAP_F_ALIGN_GP.
6218	* Users include FXSAVE & FXRSTOR. */
6219	#define IEM_MEMMAP_F_ALIGN_GP_OR_AC RT_BIT_32(18)
6220
6221	VBOXSTRICTRC iemMemMap(PVMCPUCC pVCpu, void *ppvMem, uint8_t pbUnmapInfo, size_t cbMem, uint8_t iSegReg, RTGCPTR GCPtrMem,
6222	uint32_t fAccess, uint32_t uAlignCtl) RT_NOEXCEPT;
6223	VBOXSTRICTRC iemMemCommitAndUnmap(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
6224	#ifndef IN_RING3
6225	VBOXSTRICTRC iemMemCommitAndUnmapPostponeTroubleToR3(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
6226	#endif
6227	void iemMemRollbackAndUnmap(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
6228	void iemMemRollback(PVMCPUCC pVCpu) RT_NOEXCEPT;
6229	VBOXSTRICTRC iemMemApplySegment(PVMCPUCC pVCpu, uint32_t fAccess, uint8_t iSegReg, size_t cbMem, PRTGCPTR pGCPtrMem) RT_NOEXCEPT;
6230	VBOXSTRICTRC iemMemMarkSelDescAccessed(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
6231	VBOXSTRICTRC iemMemPageTranslateAndCheckAccess(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t cbAccess, uint32_t fAccess, PRTGCPHYS pGCPhysMem) RT_NOEXCEPT;
6232
6233	void iemOpcodeFlushLight(PVMCPUCC pVCpu, uint8_t cbInstr);
6234	void iemOpcodeFlushHeavy(PVMCPUCC pVCpu, uint8_t cbInstr);
6235	#ifdef IEM_WITH_CODE_TLB
6236	void iemOpcodeFetchBytesJmp(PVMCPUCC pVCpu, size_t cbDst, void *pvDst) IEM_NOEXCEPT_MAY_LONGJMP;
6237	#else
6238	VBOXSTRICTRC iemOpcodeFetchMoreBytes(PVMCPUCC pVCpu, size_t cbMin) RT_NOEXCEPT;
6239	#endif
6240	#ifdef IEM_WITH_SETJMP
6241	uint8_t iemOpcodeGetNextU8SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6242	uint16_t iemOpcodeGetNextU16SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6243	uint32_t iemOpcodeGetNextU32SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6244	uint64_t iemOpcodeGetNextU64SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
6245	#else
6246	VBOXSTRICTRC iemOpcodeGetNextU8Slow(PVMCPUCC pVCpu, uint8_t *pb) RT_NOEXCEPT;
6247	VBOXSTRICTRC iemOpcodeGetNextS8SxU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
6248	VBOXSTRICTRC iemOpcodeGetNextS8SxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
6249	VBOXSTRICTRC iemOpcodeGetNextS8SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
6250	VBOXSTRICTRC iemOpcodeGetNextU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
6251	VBOXSTRICTRC iemOpcodeGetNextU16ZxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
6252	VBOXSTRICTRC iemOpcodeGetNextU16ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
6253	VBOXSTRICTRC iemOpcodeGetNextU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
6254	VBOXSTRICTRC iemOpcodeGetNextU32ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
6255	VBOXSTRICTRC iemOpcodeGetNextS32SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
6256	VBOXSTRICTRC iemOpcodeGetNextU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
6257	#endif
6258
6259	VBOXSTRICTRC iemMemFetchDataU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6260	VBOXSTRICTRC iemMemFetchDataU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6261	VBOXSTRICTRC iemMemFetchDataU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6262	VBOXSTRICTRC iemMemFetchDataU32NoAc(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6263	VBOXSTRICTRC iemMemFetchDataU32_ZX_U64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6264	VBOXSTRICTRC iemMemFetchDataU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6265	VBOXSTRICTRC iemMemFetchDataU64NoAc(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6266	VBOXSTRICTRC iemMemFetchDataU64AlignedU128(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6267	VBOXSTRICTRC iemMemFetchDataR80(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6268	VBOXSTRICTRC iemMemFetchDataD80(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6269	VBOXSTRICTRC iemMemFetchDataU128(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6270	VBOXSTRICTRC iemMemFetchDataU128NoAc(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6271	VBOXSTRICTRC iemMemFetchDataU128AlignedSse(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6272	VBOXSTRICTRC iemMemFetchDataU256(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6273	VBOXSTRICTRC iemMemFetchDataU256NoAc(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6274	VBOXSTRICTRC iemMemFetchDataU256AlignedAvx(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6275	VBOXSTRICTRC iemMemFetchDataXdtr(PVMCPUCC pVCpu, uint16_t *pcbLimit, PRTGCPTR pGCPtrBase, uint8_t iSegReg,
6276	RTGCPTR GCPtrMem, IEMMODE enmOpSize) RT_NOEXCEPT;
6277	#ifdef IEM_WITH_SETJMP
6278	uint8_t iemMemFetchDataU8SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6279	uint16_t iemMemFetchDataU16SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6280	uint32_t iemMemFetchDataU32SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6281	uint32_t iemMemFetchDataU32NoAcSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6282	uint32_t iemMemFlatFetchDataU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6283	uint64_t iemMemFetchDataU64SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6284	uint64_t iemMemFetchDataU64NoAcSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6285	uint64_t iemMemFetchDataU64AlignedU128SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6286	void iemMemFetchDataR80SafeJmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6287	void iemMemFetchDataD80SafeJmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6288	void iemMemFetchDataU128SafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6289	void iemMemFetchDataU128NoAcSafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6290	void iemMemFetchDataU128AlignedSseSafeJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6291	void iemMemFetchDataU256SafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6292	void iemMemFetchDataU256NoAcSafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6293	void iemMemFetchDataU256AlignedAvxSafeJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6294	# if 0 /* these are inlined now */
6295	uint8_t iemMemFetchDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6296	uint16_t iemMemFetchDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6297	uint32_t iemMemFetchDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6298	uint32_t iemMemFlatFetchDataU32Jmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6299	uint64_t iemMemFetchDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6300	uint64_t iemMemFetchDataU64AlignedU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6301	void iemMemFetchDataR80Jmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6302	void iemMemFetchDataD80Jmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6303	void iemMemFetchDataU128Jmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6304	void iemMemFetchDataU128NoAcJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6305	void iemMemFetchDataU128AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6306	void iemMemFetchDataU256NoAcJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6307	void iemMemFetchDataU256AlignedAvxJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6308	# endif
6309	void iemMemFetchDataU256Jmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6310	#endif
6311
6312	VBOXSTRICTRC iemMemFetchSysU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6313	VBOXSTRICTRC iemMemFetchSysU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6314	VBOXSTRICTRC iemMemFetchSysU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6315	VBOXSTRICTRC iemMemFetchSysU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6316	VBOXSTRICTRC iemMemFetchSelDesc(PVMCPUCC pVCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt) RT_NOEXCEPT;
6317
6318	VBOXSTRICTRC iemMemStoreDataU8(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) RT_NOEXCEPT;
6319	VBOXSTRICTRC iemMemStoreDataU16(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) RT_NOEXCEPT;
6320	VBOXSTRICTRC iemMemStoreDataU32(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) RT_NOEXCEPT;
6321	VBOXSTRICTRC iemMemStoreDataU64(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) RT_NOEXCEPT;
6322	VBOXSTRICTRC iemMemStoreDataU128(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
6323	VBOXSTRICTRC iemMemStoreDataU128NoAc(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
6324	VBOXSTRICTRC iemMemStoreDataU128AlignedSse(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
6325	VBOXSTRICTRC iemMemStoreDataU256(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
6326	VBOXSTRICTRC iemMemStoreDataU256NoAc(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
6327	VBOXSTRICTRC iemMemStoreDataU256AlignedAvx(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
6328	VBOXSTRICTRC iemMemStoreDataXdtr(PVMCPUCC pVCpu, uint16_t cbLimit, RTGCPTR GCPtrBase, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
6329	#ifdef IEM_WITH_SETJMP
6330	void iemMemStoreDataU8SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
6331	void iemMemStoreDataU16SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
6332	void iemMemStoreDataU32SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
6333	void iemMemStoreDataU64SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
6334	void iemMemStoreDataU128SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
6335	void iemMemStoreDataU128NoAcSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT128U pu128Value) IEM_NOEXCEPT_MAY_LONGJMP;
6336	void iemMemStoreDataU128AlignedSseSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT128U pu128Value) IEM_NOEXCEPT_MAY_LONGJMP;
6337	void iemMemStoreDataU256SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
6338	void iemMemStoreDataU256NoAcSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
6339	void iemMemStoreDataU256AlignedAvxSafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
6340	void iemMemStoreDataR80SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTFLOAT80U pr80Value) IEM_NOEXCEPT_MAY_LONGJMP;
6341	void iemMemStoreDataD80SafeJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTPBCD80U pd80Value) IEM_NOEXCEPT_MAY_LONGJMP;
6342	#if 0
6343	void iemMemStoreDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
6344	void iemMemStoreDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
6345	void iemMemStoreDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
6346	void iemMemStoreDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
6347	void iemMemStoreDataU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
6348	void iemMemStoreDataNoAcU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
6349	void iemMemStoreDataU256NoAcJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
6350	void iemMemStoreDataU256AlignedAvxJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
6351	#endif
6352	void iemMemStoreDataU128AlignedSseJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
6353	void iemMemStoreDataU256Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
6354	#endif
6355
6356	#ifdef IEM_WITH_SETJMP
6357	uint8_t iemMemMapDataU8RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6358	uint8_t iemMemMapDataU8AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6359	uint8_t iemMemMapDataU8WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6360	uint8_t const iemMemMapDataU8RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6361	uint16_t iemMemMapDataU16RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6362	uint16_t iemMemMapDataU16AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6363	uint16_t iemMemMapDataU16WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6364	uint16_t const iemMemMapDataU16RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6365	uint32_t iemMemMapDataU32RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6366	uint32_t iemMemMapDataU32AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6367	uint32_t iemMemMapDataU32WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6368	uint32_t const iemMemMapDataU32RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6369	uint64_t iemMemMapDataU64RwSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6370	uint64_t iemMemMapDataU64AtSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6371	uint64_t iemMemMapDataU64WoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6372	uint64_t const iemMemMapDataU64RoSafeJmp(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6373	PRTFLOAT80U iemMemMapDataR80RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6374	PRTFLOAT80U iemMemMapDataR80WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6375	PCRTFLOAT80U iemMemMapDataR80RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6376	PRTPBCD80U iemMemMapDataD80RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6377	PRTPBCD80U iemMemMapDataD80WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6378	PCRTPBCD80U iemMemMapDataD80RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6379	PRTUINT128U iemMemMapDataU128RwSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6380	PRTUINT128U iemMemMapDataU128AtSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6381	PRTUINT128U iemMemMapDataU128WoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6382	PCRTUINT128U iemMemMapDataU128RoSafeJmp(PVMCPUCC pVCpu, uint8_t *pbUnmapInfo, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6383
6384	void iemMemCommitAndUnmapJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
6385	void iemMemCommitAndUnmapRwSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
6386	void iemMemCommitAndUnmapAtSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
6387	void iemMemCommitAndUnmapWoSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
6388	void iemMemCommitAndUnmapRoSafeJmp(PVMCPUCC pVCpu, uint8_t bUnmapInfo) IEM_NOEXCEPT_MAY_LONGJMP;
6389	void iemMemRollbackAndUnmapWoSafe(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
6390	#endif
6391
6392	VBOXSTRICTRC iemMemStackPushBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
6393	void *ppvMem, uint8_t pbUnmapInfo, uint64_t *puNewRsp) RT_NOEXCEPT;
6394	VBOXSTRICTRC iemMemStackPushCommitSpecial(PVMCPUCC pVCpu, uint8_t bUnmapInfo, uint64_t uNewRsp) RT_NOEXCEPT;
6395	VBOXSTRICTRC iemMemStackPushU16(PVMCPUCC pVCpu, uint16_t u16Value) RT_NOEXCEPT;
6396	VBOXSTRICTRC iemMemStackPushU32(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
6397	VBOXSTRICTRC iemMemStackPushU64(PVMCPUCC pVCpu, uint64_t u64Value) RT_NOEXCEPT;
6398	VBOXSTRICTRC iemMemStackPushU16Ex(PVMCPUCC pVCpu, uint16_t u16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
6399	VBOXSTRICTRC iemMemStackPushU32Ex(PVMCPUCC pVCpu, uint32_t u32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
6400	VBOXSTRICTRC iemMemStackPushU64Ex(PVMCPUCC pVCpu, uint64_t u64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
6401	VBOXSTRICTRC iemMemStackPushU32SReg(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
6402	VBOXSTRICTRC iemMemStackPopBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
6403	void const *ppvMem, uint8_t pbUnmapInfo, uint64_t *puNewRsp) RT_NOEXCEPT;
6404	VBOXSTRICTRC iemMemStackPopContinueSpecial(PVMCPUCC pVCpu, size_t off, size_t cbMem,
6405	void const *ppvMem, uint8_t pbUnmapInfo, uint64_t uCurNewRsp) RT_NOEXCEPT;
6406	VBOXSTRICTRC iemMemStackPopDoneSpecial(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
6407	VBOXSTRICTRC iemMemStackPopU16(PVMCPUCC pVCpu, uint16_t *pu16Value) RT_NOEXCEPT;
6408	VBOXSTRICTRC iemMemStackPopU32(PVMCPUCC pVCpu, uint32_t *pu32Value) RT_NOEXCEPT;
6409	VBOXSTRICTRC iemMemStackPopU64(PVMCPUCC pVCpu, uint64_t *pu64Value) RT_NOEXCEPT;
6410	VBOXSTRICTRC iemMemStackPopU16Ex(PVMCPUCC pVCpu, uint16_t *pu16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
6411	VBOXSTRICTRC iemMemStackPopU32Ex(PVMCPUCC pVCpu, uint32_t *pu32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
6412	VBOXSTRICTRC iemMemStackPopU64Ex(PVMCPUCC pVCpu, uint64_t *pu64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
6413
6414	#ifdef IEM_WITH_SETJMP
6415	void iemMemStackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6416	void iemMemStackPushU32SafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6417	void iemMemStackPushU32SRegSafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6418	void iemMemStackPushU64SafeJmp(PVMCPUCC pVCpu, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6419	void iemMemStackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
6420	void iemMemStackPopGRegU32SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
6421	void iemMemStackPopGRegU64SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
6422
6423	void iemMemFlat32StackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6424	void iemMemFlat32StackPushU32SafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6425	void iemMemFlat32StackPushU32SRegSafeJmp(PVMCPUCC pVCpu, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6426	void iemMemFlat32StackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
6427	void iemMemFlat32StackPopGRegU32SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
6428
6429	void iemMemFlat64StackPushU16SafeJmp(PVMCPUCC pVCpu, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6430	void iemMemFlat64StackPushU64SafeJmp(PVMCPUCC pVCpu, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6431	void iemMemFlat64StackPopGRegU16SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
6432	void iemMemFlat64StackPopGRegU64SafeJmp(PVMCPUCC pVCpu, uint8_t iGReg) IEM_NOEXCEPT_MAY_LONGJMP;
6433
6434	void iemMemStoreStackU16SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint16_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6435	void iemMemStoreStackU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6436	void iemMemStoreStackU32SRegSafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6437	void iemMemStoreStackU64SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint64_t uValue) IEM_NOEXCEPT_MAY_LONGJMP;
6438
6439	uint16_t iemMemFetchStackU16SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6440	uint32_t iemMemFetchStackU32SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6441	uint64_t iemMemFetchStackU64SafeJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
6442
6443	#endif
6444
6445	/** @} */
6446
6447	/** @name IEMAllCImpl.cpp
6448	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/'
6449	* @{ */
6450	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem16, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6451	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem32, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6452	IEM_CIMPL_PROTO_2(iemCImpl_pop_mem64, uint16_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6453	IEM_CIMPL_PROTO_0(iemCImpl_popa_16);
6454	IEM_CIMPL_PROTO_0(iemCImpl_popa_32);
6455	IEM_CIMPL_PROTO_0(iemCImpl_pusha_16);
6456	IEM_CIMPL_PROTO_0(iemCImpl_pusha_32);
6457	IEM_CIMPL_PROTO_1(iemCImpl_pushf, IEMMODE, enmEffOpSize);
6458	IEM_CIMPL_PROTO_1(iemCImpl_popf, IEMMODE, enmEffOpSize);
6459	IEM_CIMPL_PROTO_3(iemCImpl_FarJmp, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
6460	IEM_CIMPL_PROTO_3(iemCImpl_callf, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
6461	typedef IEM_CIMPL_DECL_TYPE_3(FNIEMCIMPLFARBRANCH, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
6462	typedef FNIEMCIMPLFARBRANCH *PFNIEMCIMPLFARBRANCH;
6463	IEM_CIMPL_PROTO_2(iemCImpl_retf, IEMMODE, enmEffOpSize, uint16_t, cbPop);
6464	IEM_CIMPL_PROTO_3(iemCImpl_enter, IEMMODE, enmEffOpSize, uint16_t, cbFrame, uint8_t, cParameters);
6465	IEM_CIMPL_PROTO_1(iemCImpl_leave, IEMMODE, enmEffOpSize);
6466	IEM_CIMPL_PROTO_2(iemCImpl_int, uint8_t, u8Int, IEMINT, enmInt);
6467	IEM_CIMPL_PROTO_1(iemCImpl_iret_real_v8086, IEMMODE, enmEffOpSize);
6468	IEM_CIMPL_PROTO_4(iemCImpl_iret_prot_v8086, uint32_t, uNewEip, uint16_t, uNewCs, uint32_t, uNewFlags, uint64_t, uNewRsp);
6469	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot_NestedTask, IEMMODE, enmEffOpSize);
6470	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot, IEMMODE, enmEffOpSize);
6471	IEM_CIMPL_PROTO_1(iemCImpl_iret_64bit, IEMMODE, enmEffOpSize);
6472	IEM_CIMPL_PROTO_1(iemCImpl_iret, IEMMODE, enmEffOpSize);
6473	IEM_CIMPL_PROTO_0(iemCImpl_loadall286);
6474	IEM_CIMPL_PROTO_0(iemCImpl_syscall);
6475	IEM_CIMPL_PROTO_1(iemCImpl_sysret, IEMMODE, enmEffOpSize);
6476	IEM_CIMPL_PROTO_0(iemCImpl_sysenter);
6477	IEM_CIMPL_PROTO_1(iemCImpl_sysexit, IEMMODE, enmEffOpSize);
6478	IEM_CIMPL_PROTO_2(iemCImpl_LoadSReg, uint8_t, iSegReg, uint16_t, uSel);
6479	IEM_CIMPL_PROTO_2(iemCImpl_load_SReg, uint8_t, iSegReg, uint16_t, uSel);
6480	IEM_CIMPL_PROTO_2(iemCImpl_pop_Sreg, uint8_t, iSegReg, IEMMODE, enmEffOpSize);
6481	IEM_CIMPL_PROTO_5(iemCImpl_load_SReg_Greg, uint16_t, uSel, uint64_t, offSeg, uint8_t, iSegReg, uint8_t, iGReg, IEMMODE, enmEffOpSize);
6482	IEM_CIMPL_PROTO_2(iemCImpl_VerX, uint16_t, uSel, bool, fWrite);
6483	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u64, uint64_t *, pu64Dst, uint16_t, uSel, bool, fIsLar);
6484	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u16, uint16_t *, pu16Dst, uint16_t, uSel, bool, fIsLar);
6485	IEM_CIMPL_PROTO_3(iemCImpl_lgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
6486	IEM_CIMPL_PROTO_2(iemCImpl_sgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6487	IEM_CIMPL_PROTO_3(iemCImpl_lidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
6488	IEM_CIMPL_PROTO_2(iemCImpl_sidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6489	IEM_CIMPL_PROTO_1(iemCImpl_lldt, uint16_t, uNewLdt);
6490	IEM_CIMPL_PROTO_2(iemCImpl_sldt_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
6491	IEM_CIMPL_PROTO_2(iemCImpl_sldt_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6492	IEM_CIMPL_PROTO_1(iemCImpl_ltr, uint16_t, uNewTr);
6493	IEM_CIMPL_PROTO_2(iemCImpl_str_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
6494	IEM_CIMPL_PROTO_2(iemCImpl_str_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6495	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Cd, uint8_t, iGReg, uint8_t, iCrReg);
6496	IEM_CIMPL_PROTO_2(iemCImpl_smsw_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
6497	IEM_CIMPL_PROTO_2(iemCImpl_smsw_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6498	IEM_CIMPL_PROTO_4(iemCImpl_load_CrX, uint8_t, iCrReg, uint64_t, uNewCrX, IEMACCESSCRX, enmAccessCrX, uint8_t, iGReg);
6499	IEM_CIMPL_PROTO_2(iemCImpl_mov_Cd_Rd, uint8_t, iCrReg, uint8_t, iGReg);
6500	IEM_CIMPL_PROTO_2(iemCImpl_lmsw, uint16_t, u16NewMsw, RTGCPTR, GCPtrEffDst);
6501	IEM_CIMPL_PROTO_0(iemCImpl_clts);
6502	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Dd, uint8_t, iGReg, uint8_t, iDrReg);
6503	IEM_CIMPL_PROTO_2(iemCImpl_mov_Dd_Rd, uint8_t, iDrReg, uint8_t, iGReg);
6504	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Td, uint8_t, iGReg, uint8_t, iTrReg);
6505	IEM_CIMPL_PROTO_2(iemCImpl_mov_Td_Rd, uint8_t, iTrReg, uint8_t, iGReg);
6506	IEM_CIMPL_PROTO_1(iemCImpl_invlpg, RTGCPTR, GCPtrPage);
6507	IEM_CIMPL_PROTO_3(iemCImpl_invpcid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvpcidDesc, uint64_t, uInvpcidType);
6508	IEM_CIMPL_PROTO_0(iemCImpl_invd);
6509	IEM_CIMPL_PROTO_0(iemCImpl_wbinvd);
6510	IEM_CIMPL_PROTO_0(iemCImpl_rsm);
6511	IEM_CIMPL_PROTO_0(iemCImpl_rdtsc);
6512	IEM_CIMPL_PROTO_0(iemCImpl_rdtscp);
6513	IEM_CIMPL_PROTO_0(iemCImpl_rdpmc);
6514	IEM_CIMPL_PROTO_0(iemCImpl_rdmsr);
6515	IEM_CIMPL_PROTO_0(iemCImpl_wrmsr);
6516	IEM_CIMPL_PROTO_3(iemCImpl_in, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
6517	IEM_CIMPL_PROTO_2(iemCImpl_in_eAX_DX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
6518	IEM_CIMPL_PROTO_3(iemCImpl_out, uint16_t, u16Port, uint8_t, cbReg, uint8_t, bImmAndEffAddrMode);
6519	IEM_CIMPL_PROTO_2(iemCImpl_out_DX_eAX, uint8_t, cbReg, IEMMODE, enmEffAddrMode);
6520	IEM_CIMPL_PROTO_0(iemCImpl_cli);
6521	IEM_CIMPL_PROTO_0(iemCImpl_sti);
6522	IEM_CIMPL_PROTO_0(iemCImpl_hlt);
6523	IEM_CIMPL_PROTO_1(iemCImpl_monitor, uint8_t, iEffSeg);
6524	IEM_CIMPL_PROTO_0(iemCImpl_mwait);
6525	IEM_CIMPL_PROTO_0(iemCImpl_swapgs);
6526	IEM_CIMPL_PROTO_0(iemCImpl_cpuid);
6527	IEM_CIMPL_PROTO_1(iemCImpl_aad, uint8_t, bImm);
6528	IEM_CIMPL_PROTO_1(iemCImpl_aam, uint8_t, bImm);
6529	IEM_CIMPL_PROTO_0(iemCImpl_daa);
6530	IEM_CIMPL_PROTO_0(iemCImpl_das);
6531	IEM_CIMPL_PROTO_0(iemCImpl_aaa);
6532	IEM_CIMPL_PROTO_0(iemCImpl_aas);
6533	IEM_CIMPL_PROTO_3(iemCImpl_bound_16, int16_t, idxArray, int16_t, idxLowerBound, int16_t, idxUpperBound);
6534	IEM_CIMPL_PROTO_3(iemCImpl_bound_32, int32_t, idxArray, int32_t, idxLowerBound, int32_t, idxUpperBound);
6535	IEM_CIMPL_PROTO_0(iemCImpl_xgetbv);
6536	IEM_CIMPL_PROTO_0(iemCImpl_xsetbv);
6537	IEM_CIMPL_PROTO_5(iemCImpl_cmpxchg16b_fallback_rendezvous, PRTUINT128U, pu128Dst, PRTUINT128U, pu128RaxRdx,
6538	PRTUINT128U, pu128RbxRcx, uint32_t *, pEFlags, uint8_t, bUnmapInfo);
6539	IEM_CIMPL_PROTO_2(iemCImpl_clflush_clflushopt, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
6540	IEM_CIMPL_PROTO_1(iemCImpl_finit, bool, fCheckXcpts);
6541	IEM_CIMPL_PROTO_3(iemCImpl_fxsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
6542	IEM_CIMPL_PROTO_3(iemCImpl_fxrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
6543	IEM_CIMPL_PROTO_3(iemCImpl_xsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
6544	IEM_CIMPL_PROTO_3(iemCImpl_xrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
6545	IEM_CIMPL_PROTO_2(iemCImpl_stmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
6546	IEM_CIMPL_PROTO_2(iemCImpl_vstmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
6547	IEM_CIMPL_PROTO_2(iemCImpl_ldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
6548	IEM_CIMPL_PROTO_2(iemCImpl_vldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
6549	IEM_CIMPL_PROTO_3(iemCImpl_fnstenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6550	IEM_CIMPL_PROTO_3(iemCImpl_fnsave, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
6551	IEM_CIMPL_PROTO_3(iemCImpl_fldenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6552	IEM_CIMPL_PROTO_3(iemCImpl_frstor, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6553	IEM_CIMPL_PROTO_1(iemCImpl_fldcw, uint16_t, u16Fcw);
6554	IEM_CIMPL_PROTO_2(iemCImpl_fxch_underflow, uint8_t, iStReg, uint16_t, uFpuOpcode);
6555	IEM_CIMPL_PROTO_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, bool, fUCmp, uint32_t, uPopAndFpuOpcode);
6556	IEM_CIMPL_PROTO_2(iemCImpl_rdseed, uint8_t, iReg, IEMMODE, enmEffOpSize);
6557	IEM_CIMPL_PROTO_2(iemCImpl_rdrand, uint8_t, iReg, IEMMODE, enmEffOpSize);
6558	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovps_load_u128, uint8_t, iXRegDst, uint8_t, iXRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6559	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovps_load_u256, uint8_t, iYRegDst, uint8_t, iYRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6560	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovps_store_u128, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iXRegMsk, uint8_t, iXRegSrc);
6561	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovps_store_u256, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iYRegMsk, uint8_t, iYRegSrc);
6562	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovd_load_u128, uint8_t, iXRegDst, uint8_t, iXRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6563	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovd_load_u256, uint8_t, iYRegDst, uint8_t, iYRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6564	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovd_store_u128, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iXRegMsk, uint8_t, iXRegSrc);
6565	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovd_store_u256, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iYRegMsk, uint8_t, iYRegSrc);
6566	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovpd_load_u128, uint8_t, iXRegDst, uint8_t, iXRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6567	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovpd_load_u256, uint8_t, iYRegDst, uint8_t, iYRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6568	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovpd_store_u128, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iXRegMsk, uint8_t, iXRegSrc);
6569	IEM_CIMPL_PROTO_4(iemCImpl_vmaskmovpd_store_u256, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iYRegMsk, uint8_t, iYRegSrc);
6570	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovq_load_u128, uint8_t, iXRegDst, uint8_t, iXRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6571	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovq_load_u256, uint8_t, iYRegDst, uint8_t, iYRegMsk, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
6572	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovq_store_u128, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iXRegMsk, uint8_t, iXRegSrc);
6573	IEM_CIMPL_PROTO_4(iemCImpl_vpmaskmovq_store_u256, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst, uint8_t, iYRegMsk, uint8_t, iYRegSrc);
6574	IEM_CIMPL_PROTO_2(iemCImpl_vpgather_worker_xx, uint32_t, u32PackedArgs, uint32_t, u32Disp);
6575
6576	/** @} */
6577
6578	/** @name IEMAllCImplStrInstr.cpp.h
6579	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/' -e 's/RT_CONCAT4(//' \
6580	* -e 's/,ADDR_SIZE)/64/g' -e 's/,OP_SIZE,/64/g' -e 's/,OP_rAX,/rax/g' IEMAllCImplStrInstr.cpp.h
6581	* @{ */
6582	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr16, uint8_t, iEffSeg);
6583	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr16, uint8_t, iEffSeg);
6584	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m16);
6585	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m16);
6586	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr16, uint8_t, iEffSeg);
6587	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m16);
6588	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m16, int8_t, iEffSeg);
6589	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr16, bool, fIoChecked);
6590	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr16, bool, fIoChecked);
6591	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6592	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6593
6594	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr16, uint8_t, iEffSeg);
6595	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr16, uint8_t, iEffSeg);
6596	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m16);
6597	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m16);
6598	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr16, uint8_t, iEffSeg);
6599	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m16);
6600	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m16, int8_t, iEffSeg);
6601	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr16, bool, fIoChecked);
6602	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr16, bool, fIoChecked);
6603	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6604	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6605
6606	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr16, uint8_t, iEffSeg);
6607	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr16, uint8_t, iEffSeg);
6608	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m16);
6609	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m16);
6610	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr16, uint8_t, iEffSeg);
6611	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m16);
6612	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m16, int8_t, iEffSeg);
6613	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr16, bool, fIoChecked);
6614	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr16, bool, fIoChecked);
6615	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6616	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
6617
6618
6619	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr32, uint8_t, iEffSeg);
6620	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr32, uint8_t, iEffSeg);
6621	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m32);
6622	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m32);
6623	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr32, uint8_t, iEffSeg);
6624	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m32);
6625	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m32, int8_t, iEffSeg);
6626	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr32, bool, fIoChecked);
6627	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr32, bool, fIoChecked);
6628	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6629	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6630
6631	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr32, uint8_t, iEffSeg);
6632	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr32, uint8_t, iEffSeg);
6633	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m32);
6634	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m32);
6635	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr32, uint8_t, iEffSeg);
6636	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m32);
6637	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m32, int8_t, iEffSeg);
6638	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr32, bool, fIoChecked);
6639	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr32, bool, fIoChecked);
6640	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6641	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6642
6643	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr32, uint8_t, iEffSeg);
6644	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr32, uint8_t, iEffSeg);
6645	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m32);
6646	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m32);
6647	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr32, uint8_t, iEffSeg);
6648	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m32);
6649	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m32, int8_t, iEffSeg);
6650	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr32, bool, fIoChecked);
6651	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr32, bool, fIoChecked);
6652	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6653	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6654
6655	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr32, uint8_t, iEffSeg);
6656	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr32, uint8_t, iEffSeg);
6657	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m32);
6658	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m32);
6659	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr32, uint8_t, iEffSeg);
6660	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m32);
6661	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m32, int8_t, iEffSeg);
6662	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr32, bool, fIoChecked);
6663	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr32, bool, fIoChecked);
6664	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6665	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
6666
6667
6668	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr64, uint8_t, iEffSeg);
6669	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr64, uint8_t, iEffSeg);
6670	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m64);
6671	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m64);
6672	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr64, uint8_t, iEffSeg);
6673	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m64);
6674	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m64, int8_t, iEffSeg);
6675	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr64, bool, fIoChecked);
6676	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr64, bool, fIoChecked);
6677	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6678	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6679
6680	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr64, uint8_t, iEffSeg);
6681	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr64, uint8_t, iEffSeg);
6682	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m64);
6683	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m64);
6684	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr64, uint8_t, iEffSeg);
6685	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m64);
6686	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m64, int8_t, iEffSeg);
6687	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr64, bool, fIoChecked);
6688	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr64, bool, fIoChecked);
6689	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6690	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6691
6692	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr64, uint8_t, iEffSeg);
6693	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr64, uint8_t, iEffSeg);
6694	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m64);
6695	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m64);
6696	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr64, uint8_t, iEffSeg);
6697	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m64);
6698	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m64, int8_t, iEffSeg);
6699	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr64, bool, fIoChecked);
6700	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr64, bool, fIoChecked);
6701	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6702	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6703
6704	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr64, uint8_t, iEffSeg);
6705	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr64, uint8_t, iEffSeg);
6706	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m64);
6707	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m64);
6708	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr64, uint8_t, iEffSeg);
6709	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m64);
6710	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m64, int8_t, iEffSeg);
6711	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr64, bool, fIoChecked);
6712	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr64, bool, fIoChecked);
6713	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6714	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
6715	/** @} */
6716
6717	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
6718	VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT;
6719	VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT;
6720	VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT;
6721	VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT;
6722	VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT;
6723	VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
6724	VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALKFAST pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT;
6725	VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT;
6726	VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT;
6727	VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
6728	bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT;
6729	VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
6730	bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT;
6731	VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6732	VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6733	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6734	VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6735	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6736	VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
6737	VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT;
6738	VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
6739	RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT;
6740	VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT;
6741	VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT;
6742	VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT;
6743	uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT;
6744	void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT;
6745	VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
6746	uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT;
6747	bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT;
6748	IEM_CIMPL_PROTO_0(iemCImpl_vmxoff);
6749	IEM_CIMPL_PROTO_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon);
6750	IEM_CIMPL_PROTO_0(iemCImpl_vmlaunch);
6751	IEM_CIMPL_PROTO_0(iemCImpl_vmresume);
6752	IEM_CIMPL_PROTO_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
6753	IEM_CIMPL_PROTO_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
6754	IEM_CIMPL_PROTO_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
6755	IEM_CIMPL_PROTO_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField);
6756	IEM_CIMPL_PROTO_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField);
6757	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField);
6758	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg32, uint64_t *, pu32Dst, uint32_t, u32VmcsField);
6759	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField);
6760	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField);
6761	IEM_CIMPL_PROTO_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType);
6762	IEM_CIMPL_PROTO_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType);
6763	IEM_CIMPL_PROTO_0(iemCImpl_vmx_pause);
6764	#endif
6765
6766	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
6767	VBOXSTRICTRC iemSvmVmexit(PVMCPUCC pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2) RT_NOEXCEPT;
6768	VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr, uint64_t uCr2) RT_NOEXCEPT;
6769	VBOXSTRICTRC iemSvmHandleIOIntercept(PVMCPUCC pVCpu, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
6770	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, uint8_t cbInstr) RT_NOEXCEPT;
6771	VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPUCC pVCpu, uint32_t idMsr, bool fWrite, uint8_t cbInstr) RT_NOEXCEPT;
6772	IEM_CIMPL_PROTO_0(iemCImpl_vmrun);
6773	IEM_CIMPL_PROTO_0(iemCImpl_vmload);
6774	IEM_CIMPL_PROTO_0(iemCImpl_vmsave);
6775	IEM_CIMPL_PROTO_0(iemCImpl_clgi);
6776	IEM_CIMPL_PROTO_0(iemCImpl_stgi);
6777	IEM_CIMPL_PROTO_0(iemCImpl_invlpga);
6778	IEM_CIMPL_PROTO_0(iemCImpl_skinit);
6779	IEM_CIMPL_PROTO_0(iemCImpl_svm_pause);
6780	#endif
6781
6782	IEM_CIMPL_PROTO_0(iemCImpl_vmcall); /* vmx */
6783	IEM_CIMPL_PROTO_0(iemCImpl_vmmcall); /* svm */
6784	IEM_CIMPL_PROTO_1(iemCImpl_Hypercall, uint16_t, uDisOpcode); /* both */
6785
6786	extern const PFNIEMOP g_apfnIemInterpretOnlyOneByteMap[256];
6787	extern const PFNIEMOP g_apfnIemInterpretOnlyTwoByteMap[1024];
6788	extern const PFNIEMOP g_apfnIemInterpretOnlyThreeByte0f3a[1024];
6789	extern const PFNIEMOP g_apfnIemInterpretOnlyThreeByte0f38[1024];
6790	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap1[1024];
6791	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap2[1024];
6792	extern const PFNIEMOP g_apfnIemInterpretOnlyVecMap3[1024];
6793
6794	/*
6795	* Recompiler related stuff.
6796	*/
6797	extern const PFNIEMOP g_apfnIemThreadedRecompilerOneByteMap[256];
6798	extern const PFNIEMOP g_apfnIemThreadedRecompilerTwoByteMap[1024];
6799	extern const PFNIEMOP g_apfnIemThreadedRecompilerThreeByte0f3a[1024];
6800	extern const PFNIEMOP g_apfnIemThreadedRecompilerThreeByte0f38[1024];
6801	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap1[1024];
6802	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap2[1024];
6803	extern const PFNIEMOP g_apfnIemThreadedRecompilerVecMap3[1024];
6804
6805	DECLHIDDEN(int) iemPollTimers(PVMCC pVM, PVMCPUCC pVCpu) RT_NOEXCEPT;
6806
6807	DECLCALLBACK(int) iemTbInit(PVMCC pVM, uint32_t cInitialTbs, uint32_t cMaxTbs,
6808	uint64_t cbInitialExec, uint64_t cbMaxExec, uint32_t cbChunkExec);
6809	void iemThreadedTbObsolete(PVMCPUCC pVCpu, PIEMTB pTb, bool fSafeToFree);
6810	DECLHIDDEN(void) iemTbAllocatorFree(PVMCPUCC pVCpu, PIEMTB pTb);
6811	void iemTbAllocatorProcessDelayedFrees(PVMCPUCC pVCpu, PIEMTBALLOCATOR pTbAllocator);
6812	void iemTbAllocatorFreeupNativeSpace(PVMCPUCC pVCpu, uint32_t cNeededInstrs);
6813	DECLHIDDEN(const char ) iemTbFlagsToString(uint32_t fFlags, char pszBuf, size_t cbBuf) RT_NOEXCEPT;
6814	DECLHIDDEN(void) iemThreadedDisassembleTb(PCIEMTB pTb, PCDBGFINFOHLP pHlp) RT_NOEXCEPT;
6815
6816
6817	/** @todo FNIEMTHREADEDFUNC and friends may need more work... */
6818	#if defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
6819	typedef VBOXSTRICTRC /__attribute__((__nothrow__))/ FNIEMTHREADEDFUNC(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
6820	typedef FNIEMTHREADEDFUNC *PFNIEMTHREADEDFUNC;
6821	# define IEM_DECL_IEMTHREADEDFUNC_DEF(a_Name) \
6822	VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2)
6823	# define IEM_DECL_IEMTHREADEDFUNC_PROTO(a_Name) \
6824	VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2)
6825
6826	#else
6827	typedef VBOXSTRICTRC (FNIEMTHREADEDFUNC)(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
6828	typedef FNIEMTHREADEDFUNC *PFNIEMTHREADEDFUNC;
6829	# define IEM_DECL_IEMTHREADEDFUNC_DEF(a_Name) \
6830	VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2) IEM_NOEXCEPT_MAY_LONGJMP
6831	# define IEM_DECL_IEMTHREADEDFUNC_PROTO(a_Name) \
6832	VBOXSTRICTRC a_Name(PVMCPU pVCpu, uint64_t uParam0, uint64_t uParam1, uint64_t uParam2) IEM_NOEXCEPT_MAY_LONGJMP
6833	#endif
6834
6835
6836	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_Nop);
6837	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_LogCpuState);
6838
6839	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_DeferToCImpl0);
6840
6841	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckIrq);
6842	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckTimers);
6843	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckTimersAndIrq);
6844	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckMode);
6845	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckHwInstrBps);
6846	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLim);
6847
6848	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodes);
6849	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodes);
6850	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesConsiderCsLim);
6851
6852	/* Branching: */
6853	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndPcAndOpcodes);
6854	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckPcAndOpcodes);
6855	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckPcAndOpcodesConsiderCsLim);
6856
6857	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesLoadingTlb);
6858	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesLoadingTlb);
6859	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesLoadingTlbConsiderCsLim);
6860
6861	/* Natural page crossing: */
6862	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesAcrossPageLoadingTlb);
6863	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesAcrossPageLoadingTlb);
6864	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesAcrossPageLoadingTlbConsiderCsLim);
6865
6866	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesOnNextPageLoadingTlb);
6867	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNextPageLoadingTlb);
6868	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNextPageLoadingTlbConsiderCsLim);
6869
6870	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckCsLimAndOpcodesOnNewPageLoadingTlb);
6871	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNewPageLoadingTlb);
6872	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_CheckOpcodesOnNewPageLoadingTlbConsiderCsLim);
6873
6874	IEM_DECL_IEMTHREADEDFUNC_PROTO(iemThreadedFunc_BltIn_Jump);
6875
6876	bool iemThreadedCompileEmitIrqCheckBefore(PVMCPUCC pVCpu, PIEMTB pTb);
6877	bool iemThreadedCompileBeginEmitCallsComplications(PVMCPUCC pVCpu, PIEMTB pTb);
6878
6879	/* Native recompiler public bits: */
6880
6881	DECLHIDDEN(PIEMTB) iemNativeRecompile(PVMCPUCC pVCpu, PIEMTB pTb) RT_NOEXCEPT;
6882	DECLHIDDEN(void) iemNativeDisassembleTb(PVMCPU pVCpu, PCIEMTB pTb, PCDBGFINFOHLP pHlp) RT_NOEXCEPT;
6883	int iemExecMemAllocatorInit(PVMCPU pVCpu, uint64_t cbMax, uint64_t cbInitial, uint32_t cbChunk) RT_NOEXCEPT;
6884	DECLHIDDEN(PIEMNATIVEINSTR) iemExecMemAllocatorAlloc(PVMCPU pVCpu, uint32_t cbReq, PIEMTB pTb, PIEMNATIVEINSTR *ppaExec,
6885	struct IEMNATIVEPERCHUNKCTX const **ppChunkCtx) RT_NOEXCEPT;
6886	DECLHIDDEN(PIEMNATIVEINSTR) iemExecMemAllocatorAllocFromChunk(PVMCPU pVCpu, uint32_t idxChunk, uint32_t cbReq,
6887	PIEMNATIVEINSTR *ppaExec);
6888	DECLHIDDEN(void) iemExecMemAllocatorReadyForUse(PVMCPUCC pVCpu, void *pv, size_t cb) RT_NOEXCEPT;
6889	void iemExecMemAllocatorFree(PVMCPU pVCpu, void *pv, size_t cb) RT_NOEXCEPT;
6890	DECLASM(DECL_NO_RETURN(void)) iemNativeTbLongJmp(void *pvFramePointer, int rc) RT_NOEXCEPT;
6891	DECLHIDDEN(struct IEMNATIVEPERCHUNKCTX const *) iemExecMemGetTbChunkCtx(PVMCPU pVCpu, PCIEMTB pTb);
6892	DECLHIDDEN(struct IEMNATIVEPERCHUNKCTX const *) iemNativeRecompileAttachExecMemChunkCtx(PVMCPU pVCpu, uint32_t idxChunk);
6893
6894	/** Packed 32-bit argument for iemCImpl_vpgather_worker_xx. */
6895	typedef union IEMGATHERARGS
6896	{
6897	/** Integer view. */
6898	uint32_t u;
6899	/** Bitfield view. */
6900	struct
6901	{
6902	uint32_t iYRegDst : 4; /*< 0 - XMM or YMM register number (destination) /
6903	uint32_t iYRegIdc : 4; /*< 4 - XMM or YMM register number (indices) /
6904	uint32_t iYRegMsk : 4; /*< 8 - XMM or YMM register number (mask) /
6905	uint32_t iGRegBase : 4; /*< 12 - general register number (base ptr) /
6906	uint32_t iScale : 2; /*< 16 - scale factor (1/2/4/8) /
6907	uint32_t enmEffOpSize : 2; /*< 18 - operand size (16/32/64/--) /
6908	uint32_t enmEffAddrMode : 2; /*< 20 - addressing mode (16/32/64/--) /
6909	uint32_t iEffSeg : 3; /*< 22 - effective segment (ES/CS/SS/DS/FS/GS) /
6910	uint32_t fVex256 : 1; /*< 25 - overall instruction width (128/256 bits) /
6911	uint32_t fIdxQword : 1; /*< 26 - individual index width (4/8 bytes) /
6912	uint32_t fValQword : 1; /*< 27 - individual value width (4/8 bytes) /
6913	} s;
6914	} IEMGATHERARGS;
6915	AssertCompileSize(IEMGATHERARGS, sizeof(uint32_t));
6916
6917	#endif /* !RT_IN_ASSEMBLER - ASM-NOINC-END */
6918
6919
6920	/** @} */
6921
6922	RT_C_DECLS_END
6923
6924	/* ASM-INC: %include "IEMInternalStruct.mac" */
6925
6926	#endif /* !VMM_INCLUDED_SRC_include_IEMInternal_h */
6927

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h@ 105700

Download in other formats: